1 ;; Machine description for IBM RISC System
6000 (POWER) for GNU C compiler
2 ;; Copyright (C)
1990-
2024 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version
3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 (STACK_POINTER_REGNUM
1)
31 (STATIC_CHAIN_REGNUM
11)
32 (HARD_FRAME_POINTER_REGNUM
31)
36 (FIRST_ALTIVEC_REGNO
64)
37 (LAST_ALTIVEC_REGNO
95)
41 (ARG_POINTER_REGNUM
99)
53 (FRAME_POINTER_REGNUM
110)
60 (define_c_enum "unspec"
61 [UNSPEC_PROBE_STACK ; probe stack memory reference
62 UNSPEC_TOCPTR ; address of a word pointing to the TOC
63 UNSPEC_TOC ; address of the TOC (more-or-less)
64 UNSPEC_TOCSLOT ; offset from r1 of toc pointer save slot
72 UNSPEC_LD_MPIC ; load_macho_picbase
73 UNSPEC_RELD_MPIC ; re-load_macho_picbase
74 UNSPEC_MPIC_CORRECT ; macho_correct_pic
91 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
109 UNSPEC_MACHOPIC_OFFSET
122 UNSPEC_P8V_RELOAD_FROM_GPR
125 UNSPEC_P8V_RELOAD_FROM_VSX
139 UNSPEC_ADD_ROUND_TO_ODD
140 UNSPEC_SUB_ROUND_TO_ODD
141 UNSPEC_MUL_ROUND_TO_ODD
142 UNSPEC_DIV_ROUND_TO_ODD
143 UNSPEC_FMA_ROUND_TO_ODD
144 UNSPEC_SQRT_ROUND_TO_ODD
145 UNSPEC_TRUNC_ROUND_TO_ODD
158 UNSPEC_XXSPLTIDP_CONST
159 UNSPEC_XXSPLTIW_CONST
165 ;; UNSPEC_VOLATILE usage
168 (define_c_enum "unspecv"
170 UNSPECV_LL ; load-locked
171 UNSPECV_SC ; store-conditional
172 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
173 UNSPECV_EH_RR ; eh_reg_restore
174 UNSPECV_ISYNC ; isync instruction
175 UNSPECV_MFTB ; move from time base
176 UNSPECV_DARN ; darn (deliver a random number)
177 UNSPECV_NLGR ; non-local goto receiver
178 UNSPECV_MFFS ; Move from FPSCR
179 UNSPECV_MFFSL ; Move from FPSCR light instruction version
180 UNSPECV_MFFSCRN ; Move from FPSCR float rounding mode
181 UNSPECV_MFFSCDRN ; Move from FPSCR decimal float rounding mode
182 UNSPECV_MTFSF ; Move to FPSCR Fields
8 to
15
183 UNSPECV_MTFSF_HI ; Move to FPSCR Fields
0 to
7
184 UNSPECV_MTFSB0 ; Set FPSCR Field bit to
0
185 UNSPECV_MTFSB1 ; Set FPSCR Field bit to
1
186 UNSPECV_SPLIT_STACK_RETURN ; A camouflaged return
187 UNSPECV_SPEC_BARRIER ; Speculation barrier
192 ; The three different kinds of epilogue.
193 (define_enum "epilogue_type" [normal sibcall eh_return])
195 ;; Define an insn type attribute. This is used in function unit delay
199 add,logical,shift,insert,
201 exts,cntlz,popcnt,isel,
202 load,store,fpload,fpstore,vecload,vecstore,
204 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
205 cr_logical,mfcr,mfcrf,mtcr,
206 fpcompare,fp,fpsimple,dmul,qmul,sdiv,ddiv,ssqrt,dsqrt,
207 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
208 vecfloat,vecfdiv,vecdouble,mtvsr,mfvsr,crypto,
209 veclogical,veccmpfx,vecexts,vecmove,
210 htm,htmsimple,dfp,mma,
215 fused_load_load,fused_store_store,
219 (const_string "integer"))
220 ;; Attr type definitions for fused pairs:
221 ;; fused_arith_logical is used for scalar logical+add/subf and
222 ;; add/subf+logical pairs of instructions.
223 ;; fused_load_cmpi is used for a D-form load fused with
224 ;; a compare immediate.
225 ;; fused_load_load is for a fused pair of loads to adjacent addresses.
226 ;; fused_store_store is for a fused pair of stores to adjacent addresses.
227 ;; fused_addis_load is for addis fused to D-form load for a larger immediate.
228 ;; fused_mtbc is for fused mtlr and bclr[l] pairs.
229 ;; fused_vector is for a fused pair of vector logical instructions.
231 ;; What data size does this instruction work on?
232 ;; This is used for insert, mul and others as necessary.
233 (define_attr "size" "
8,
16,
32,
64,
128,
256" (const_string "
32"))
235 ;; What is the insn_cost for this insn? The target hook can still override
236 ;; this. For optimizing for size the "length" attribute is used instead.
237 (define_attr "cost" "" (const_int
0))
239 ;; Is this instruction record form ("dot", signed compare to
0, writing CR0)?
240 ;; This is used for add, logical, shift, exts, mul.
241 (define_attr "dot" "no,yes" (const_string "no"))
243 ;; Does this instruction sign-extend its result?
244 ;; This is used for load insns.
245 (define_attr "sign_extend" "no,yes" (const_string "no"))
247 ;; Does this cr_logical instruction have three operands? That is, BT != BB.
248 (define_attr "cr_logical_3op" "no,yes" (const_string "no"))
250 ;; Does this instruction use indexed (that is, reg+reg) addressing?
251 ;; This is used for load and store insns. If operand
0 or
1 is a MEM
252 ;; it is automatically set based on that. If a load or store instruction
253 ;; has fewer than two operands it needs to set this attribute manually
254 ;; or the compiler will crash.
255 (define_attr "indexed" "no,yes"
256 (if_then_else (ior (match_operand
0 "indexed_address_mem")
257 (match_operand
1 "indexed_address_mem"))
259 (const_string "no")))
261 ;; Does this instruction use update addressing?
262 ;; This is used for load and store insns. See the comments for "indexed".
263 (define_attr "update" "no,yes"
264 (if_then_else (ior (match_operand
0 "update_address_mem")
265 (match_operand
1 "update_address_mem"))
267 (const_string "no")))
269 ;; Is this instruction using operands[
2] as shift amount, and can that be a
271 ;; This is used for shift insns.
272 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
274 ;; Is this instruction using a shift amount from a register?
275 ;; This is used for shift insns.
276 (define_attr "var_shift" "no,yes"
277 (if_then_else (and (eq_attr "type" "shift")
278 (eq_attr "maybe_var_shift" "yes"))
279 (if_then_else (match_operand
2 "gpc_reg_operand")
282 (const_string "no")))
284 ;; Is copying of this instruction disallowed?
285 (define_attr "cannot_copy" "no,yes" (const_string "no"))
288 ;; Whether this insn has a prefixed form and a non-prefixed form.
289 (define_attr "maybe_prefixed" "no,yes"
290 (if_then_else (eq_attr "type" "load,fpload,vecload,store,fpstore,vecstore,
291 integer,add,fused_load_cmpi")
293 (const_string "no")))
295 ;; Whether an insn is a prefixed insn. A prefixed instruction has a prefix
296 ;; instruction word that conveys additional information such as a larger
297 ;; immediate, additional operands, etc., in addition to the normal instruction
298 ;; word. The default "length" attribute will also be adjusted by default to
300 (define_attr "prefixed" "no,yes"
301 (cond [(ior (match_test "!TARGET_PREFIXED")
302 (match_test "!NONJUMP_INSN_P (insn)")
303 (eq_attr "maybe_prefixed" "no"))
306 (eq_attr "type" "load,fpload,vecload,fused_load_cmpi")
307 (if_then_else (match_test "prefixed_load_p (insn)")
311 (eq_attr "type" "store,fpstore,vecstore")
312 (if_then_else (match_test "prefixed_store_p (insn)")
316 (eq_attr "type" "integer,add")
317 (if_then_else (match_test "prefixed_paddi_p (insn)")
319 (const_string "no"))]
321 (const_string "no")))
323 ;; Whether an insn loads an external address for the PCREL_OPT optimizaton.
324 (define_attr "loads_external_address" "no,yes"
327 ;; Return the number of real hardware instructions in a combined insn. If it
328 ;; is
0, just use the length /
4.
329 (define_attr "num_insns" "" (const_int
0))
331 ;; If an insn is prefixed, return the maximum number of prefixed instructions
332 ;; in the insn. The macro ADJUST_INSN_LENGTH uses this number to adjust the
334 (define_attr "max_prefixed_insns" "" (const_int
1))
336 ;; Length of the instruction (in bytes). This length does not consider the
337 ;; length for prefixed instructions. The macro ADJUST_INSN_LENGTH will adjust
338 ;; the length if there are prefixed instructions.
340 ;; While it might be tempting to use num_insns to calculate the length, it can
341 ;; be problematical unless all insn lengths are adjusted to use num_insns
342 ;; (i.e. if num_insns is
0, it will get the length, which in turn will get
343 ;; num_insns and recurse).
344 (define_attr "length" "" (const_int
4))
346 ;; Processor type -- this attribute must exactly match the processor_type
347 ;; enumeration in rs6000-opts.h.
349 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
350 ppc750,ppc7400,ppc7450,
351 ppc403,ppc405,ppc440,ppc476,
352 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
353 power4,power5,power6,power7,power8,power9,power10,
354 rs64a,mpccore,cell,ppca2,titan,power11"
355 (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
357 ;; The ISA we implement.
358 (define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
359 (const_string "any"))
361 ;; Is this alternative enabled for the current CPU/ISA/etc.?
362 (define_attr "enabled" ""
364 [(eq_attr "isa" "any")
367 (and (eq_attr "isa" "p5")
368 (match_test "TARGET_POPCNTB"))
371 (and (eq_attr "isa" "p6")
372 (match_test "TARGET_CMPB"))
375 (and (eq_attr "isa" "p7")
376 (match_test "TARGET_POPCNTD"))
379 (and (eq_attr "isa" "p7v")
380 (match_test "TARGET_VSX"))
383 (and (eq_attr "isa" "p8v")
384 (match_test "TARGET_P8_VECTOR"))
387 (and (eq_attr "isa" "p9")
388 (match_test "TARGET_MODULO"))
391 (and (eq_attr "isa" "p9v")
392 (match_test "TARGET_P9_VECTOR"))
395 (and (eq_attr "isa" "p9kf")
396 (match_test "TARGET_FLOAT128_TYPE"))
399 (and (eq_attr "isa" "p9tf")
400 (match_test "FLOAT128_VECTOR_P (TFmode)"))
403 (and (eq_attr "isa" "p10")
404 (match_test "TARGET_POWER10"))
408 ;; If this instruction is microcoded on the CELL processor
409 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
410 (define_attr "cell_micro" "not,conditional,always"
411 (if_then_else (ior (and (eq_attr "type" "shift,exts,mul")
412 (eq_attr "dot" "yes"))
413 (and (eq_attr "type" "load")
414 (eq_attr "sign_extend" "yes"))
415 (and (eq_attr "type" "shift")
416 (eq_attr "var_shift" "yes")))
417 (const_string "always")
418 (const_string "not")))
420 (automata_option "ndfa")
433 (include "e300c2c3.md")
434 (include "e500mc.md")
435 (include "e500mc64.md")
438 (include "power4.md")
439 (include "power5.md")
440 (include "power6.md")
441 (include "power7.md")
442 (include "power8.md")
443 (include "power9.md")
444 (include "power10.md")
449 (include "predicates.md")
450 (include "constraints.md")
455 ; This mode iterator allows :GPR to be used to indicate the allowable size
456 ; of whole values in GPRs.
457 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
459 ; And again, for patterns that need two (potentially) different integer modes.
460 (define_mode_iterator GPR2 [SI (DI "TARGET_POWERPC64")])
462 ; Any supported integer mode.
463 (define_mode_iterator INT [QI HI SI DI TI PTI])
465 ; Any supported integer mode that fits in one register.
466 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
468 ; Integer modes supported in VSX registers with ISA
3.0 instructions
469 (define_mode_iterator INT_ISA3 [QI HI SI DI])
471 ; Everything we can extend QImode to.
472 (define_mode_iterator EXTQI [SI (DI "TARGET_POWERPC64")])
474 ; Everything we can extend HImode to.
475 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
477 ; Everything we can extend SImode to.
478 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
480 ; QImode or HImode for small integer moves and small atomic ops
481 (define_mode_iterator QHI [QI HI])
483 ; QImode, HImode, SImode for fused ops only for GPR loads
484 (define_mode_iterator QHSI [QI HI SI])
486 ; HImode or SImode for sign extended fusion ops
487 (define_mode_iterator HSI [HI SI])
489 ; SImode or DImode, even if DImode doesn't fit in GPRs.
490 (define_mode_iterator SDI [SI DI])
492 ; The size of a pointer. Also, the size of the value that a record-condition
493 ; (one with a '.') will compare; and the size used for arithmetic carries.
494 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
495 (define_mode_iterator WORD [(SI "!TARGET_POWERPC64") (DI "TARGET_POWERPC64")])
497 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
498 ; PTImode is GPR only)
499 (define_mode_iterator TI2 [TI PTI])
501 ; Any hardware-supported floating-point mode
502 (define_mode_iterator FP [
503 (SF "TARGET_HARD_FLOAT")
504 (DF "TARGET_HARD_FLOAT")
505 (TF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
506 (IF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
507 (KF "TARGET_FLOAT128_TYPE")
511 ; Any fma capable floating-point mode.
512 (define_mode_iterator FMA_F [
513 (SF "TARGET_HARD_FLOAT")
514 (DF "TARGET_HARD_FLOAT || VECTOR_UNIT_VSX_P (DFmode)")
515 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
516 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
517 (KF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (KFmode)")
518 (TF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (TFmode)")
521 ; Floating point move iterators to combine binary and decimal moves
522 (define_mode_iterator FMOVE32 [SF SD])
523 (define_mode_iterator FMOVE64 [DF DD])
524 (define_mode_iterator FMOVE64X [DI DF DD])
525 (define_mode_iterator FMOVE128 [(TF "TARGET_LONG_DOUBLE_128")
526 (IF "FLOAT128_IBM_P (IFmode)")
527 (TD "TARGET_HARD_FLOAT")])
529 (define_mode_iterator FMOVE128_FPR [(TF "FLOAT128_2REG_P (TFmode)")
530 (IF "FLOAT128_2REG_P (IFmode)")
531 (TD "TARGET_HARD_FLOAT")])
533 ; Iterators for
128 bit types for direct move
534 (define_mode_iterator FMOVE128_GPR [TI
542 (KF "FLOAT128_VECTOR_P (KFmode)")
543 (TF "FLOAT128_VECTOR_P (TFmode)")])
545 ; Iterator for
128-bit VSX types for pack/unpack
546 (define_mode_iterator FMOVE128_VSX [V1TI KF])
548 ; Iterators for converting to/from TFmode
549 (define_mode_iterator IFKF [IF KF])
551 ; Constraints for moving IF/KFmode.
552 (define_mode_attr IFKF_reg [(IF "d") (KF "wa")])
554 ; Whether a floating point move is ok, don't allow SD without hardware FP
555 (define_mode_attr fmove_ok [(SF "")
557 (SD "TARGET_HARD_FLOAT")
560 ; Convert REAL_VALUE to the appropriate bits
561 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
562 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
563 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
564 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
566 ; Whether
0.0 has an all-zero bit pattern
567 (define_mode_attr zero_fp [(SF "j")
576 ; Definitions for
64-bit VSX
577 (define_mode_attr f64_vsx [(DF "wa") (DD "wn")])
579 ; Definitions for
64-bit direct move
580 (define_mode_attr f64_dm [(DF "wa") (DD "d")])
582 ; Definitions for
64-bit use of altivec registers
583 (define_mode_attr f64_av [(DF "v") (DD "wn")])
585 ; Definitions for
64-bit access to ISA
3.0 (power9) vector
586 (define_mode_attr f64_p9 [(DF "v") (DD "wn")])
588 ; These modes do not fit in integer registers in
32-bit mode.
589 (define_mode_iterator DIFD [DI DF DD])
591 ; Iterator for reciprocal estimate instructions
592 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
595 (define_mode_iterator SFDF [SF DF])
597 ; And again, for when we need two FP modes in a pattern.
598 (define_mode_iterator SFDF2 [SF DF])
600 ; A generic s/d attribute, for sp/dp for example.
601 (define_mode_attr sd [(SF "s") (DF "d")
602 (V4SF "s") (V2DF "d")])
604 ; "s" or nothing, for fmuls/fmul for example.
605 (define_mode_attr s [(SF "s") (DF "")])
607 ; Iterator for
128-bit floating point that uses the IBM double-double format
608 (define_mode_iterator IBM128 [(IF "FLOAT128_IBM_P (IFmode)")
609 (TF "FLOAT128_IBM_P (TFmode)")])
611 ; Iterator for
128-bit floating point that uses IEEE
128-bit float
612 (define_mode_iterator IEEE128 [(KF "FLOAT128_IEEE_P (KFmode)")
613 (TF "FLOAT128_IEEE_P (TFmode)")])
615 ; Iterator for
128-bit floating point
616 (define_mode_iterator FLOAT128 [(KF "TARGET_FLOAT128_TYPE")
617 (IF "TARGET_FLOAT128_TYPE")
618 (TF "TARGET_LONG_DOUBLE_128")])
620 ; Iterator for signbit on
64-bit machines with direct move
621 (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
622 (TF "FLOAT128_VECTOR_P (TFmode)")])
624 ; Which isa is needed for those float instructions?
625 (define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
628 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
630 ; Conditional returns.
631 (define_code_iterator any_return [return simple_return])
632 (define_code_attr return_pred [(return "direct_return ()")
633 (simple_return "
1")])
634 (define_code_attr return_str [(return "") (simple_return "simple_")])
637 (define_code_iterator iorxor [ior xor])
638 (define_code_iterator and_ior_xor [and ior xor])
640 ; Signed/unsigned variants of ops.
641 (define_code_iterator any_extend [sign_extend zero_extend])
642 (define_code_iterator any_fix [fix unsigned_fix])
643 (define_code_iterator any_float [float unsigned_float])
646 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
648 (define_code_attr u [(sign_extend "")
653 (define_code_attr su [(sign_extend "s")
658 (unsigned_float "u")])
660 (define_code_attr az [(sign_extend "a")
665 (unsigned_float "z")])
667 (define_code_attr uns [(fix "")
670 (unsigned_float "uns")])
672 ; Various instructions that come in SI and DI forms.
673 ; A generic w/d attribute, for things like cmpw/cmpd.
674 (define_mode_attr wd [(QI "b")
685 ; For double extract from different origin types
686 (define_mode_attr du_or_d [(QI "du")
695 ;; How many bits (per element) in this mode?
696 (define_mode_attr bits [(QI "
8") (HI "
16") (SI "
32") (DI "
64")
699 (V4SI "
32") (V2DI "
64")])
702 (define_mode_attr dbits [(QI "
56") (HI "
48") (SI "
32")])
704 ;; Bitmask for shift instructions
705 (define_mode_attr hH [(SI "h") (DI "H")])
707 ;; A mode twice the size of the given mode
708 (define_mode_attr dmode [(SI "di") (DI "ti")])
709 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
711 ;; Suffix for reload patterns
712 (define_mode_attr ptrsize [(SI "
32bit")
715 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
716 (DI "TARGET_64BIT")])
718 (define_mode_attr mptrsize [(SI "si")
721 (define_mode_attr ptrload [(SI "lwz")
724 (define_mode_attr ptrm [(SI "m")
727 (define_mode_attr rreg [(SF "f")
734 (define_mode_attr rreg2 [(SF "f")
737 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
738 (DF "TARGET_FCFID")])
740 ;; Mode iterator for logical operations on
128-bit types
741 (define_mode_iterator BOOL_128 [TI
743 (V16QI "TARGET_ALTIVEC")
744 (V8HI "TARGET_ALTIVEC")
745 (V4SI "TARGET_ALTIVEC")
746 (V4SF "TARGET_ALTIVEC")
747 (V2DI "TARGET_ALTIVEC")
748 (V2DF "TARGET_ALTIVEC")
749 (V1TI "TARGET_ALTIVEC")])
751 ;; For the GPRs we use
3 constraints for register outputs, two that are the
752 ;; same as the output register, and a third where the output register is an
753 ;; early clobber, so we don't have to deal with register overlaps. For the
754 ;; vector types, we prefer to use the vector registers. For TI mode, allow
757 ;; Mode attribute for boolean operation register constraints for output
758 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
760 (V16QI "wa,v,&?r,?r,?r")
761 (V8HI "wa,v,&?r,?r,?r")
762 (V4SI "wa,v,&?r,?r,?r")
763 (V4SF "wa,v,&?r,?r,?r")
764 (V2DI "wa,v,&?r,?r,?r")
765 (V2DF "wa,v,&?r,?r,?r")
766 (V1TI "wa,v,&?r,?r,?r")])
768 ;; Mode attribute for boolean operation register constraints for operand1
769 (define_mode_attr BOOL_REGS_OP1 [(TI "r,
0,r,wa,v")
777 (V1TI "wa,v,r,
0,r")])
779 ;; Mode attribute for boolean operation register constraints for operand2
780 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,
0,wa,v")
788 (V1TI "wa,v,r,r,
0")])
790 ;; Mode attribute for boolean operation register constraints for operand1
791 ;; for one_cmpl. To simplify things, we repeat the constraint where
0
792 ;; is used for operand1 or operand2
793 (define_mode_attr BOOL_REGS_UNARY [(TI "r,
0,
0,wa,v")
801 (V1TI "wa,v,r,
0,
0")])
803 ;; Reload iterator for creating the function to allocate a base register to
804 ;; supplement addressing modes.
805 (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
806 SF SD SI DF DD DI TI PTI KF IF TF
809 ;; Iterate over smin, smax
810 (define_code_iterator fp_minmax [smin smax])
812 (define_code_attr minmax [(smin "min")
815 (define_code_attr SMINMAX [(smin "SMIN")
818 ;; Iterator to optimize the following cases:
819 ;; D-form load to FPR register & move to Altivec register
820 ;; Move Altivec register to FPR register and store
821 (define_mode_iterator ALTIVEC_DFORM [DF
822 (SF "TARGET_P8_VECTOR")
823 (DI "TARGET_POWERPC64")])
825 (include "darwin.md")
827 ;; Start with fixed-point load and store insns. Here we put only the more
828 ;; complex forms. Basic data transfer is done later.
830 (define_insn "zero_extendqi<mode>
2"
831 [(set (match_operand:EXTQI
0 "gpc_reg_operand" "=r,r,wa,^v")
832 (zero_extend:EXTQI (match_operand:QI
1 "reg_or_mem_operand" "m,r,?Z,v")))]
839 [(set_attr "type" "load,shift,fpload,vecperm")
840 (set_attr "isa" "*,*,p9v,p9v")])
842 (define_insn_and_split "*zero_extendqi<mode>
2_dot"
843 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
844 (compare:CC (zero_extend:EXTQI (match_operand:QI
1 "gpc_reg_operand" "r,r"))
846 (clobber (match_scratch:EXTQI
0 "=r,r"))]
851 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
853 (zero_extend:EXTQI (match_dup
1)))
855 (compare:CC (match_dup
0)
858 [(set_attr "type" "logical")
859 (set_attr "dot" "yes")
860 (set_attr "length" "
4,
8")])
862 (define_insn_and_split "*zero_extendqi<mode>
2_dot2"
863 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
864 (compare:CC (zero_extend:EXTQI (match_operand:QI
1 "gpc_reg_operand" "r,r"))
866 (set (match_operand:EXTQI
0 "gpc_reg_operand" "=r,r")
867 (zero_extend:EXTQI (match_dup
1)))]
872 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
874 (zero_extend:EXTQI (match_dup
1)))
876 (compare:CC (match_dup
0)
879 [(set_attr "type" "logical")
880 (set_attr "dot" "yes")
881 (set_attr "length" "
4,
8")])
884 (define_insn "zero_extendhi<mode>
2"
885 [(set (match_operand:EXTHI
0 "gpc_reg_operand" "=r,r,wa,^v")
886 (zero_extend:EXTHI (match_operand:HI
1 "reg_or_mem_operand" "m,r,?Z,v")))]
890 rlwinm %
0,%
1,
0,
0xffff
893 [(set_attr "type" "load,shift,fpload,vecperm")
894 (set_attr "isa" "*,*,p9v,p9v")])
896 (define_insn_and_split "*zero_extendhi<mode>
2_dot"
897 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
898 (compare:CC (zero_extend:EXTHI (match_operand:HI
1 "gpc_reg_operand" "r,r"))
900 (clobber (match_scratch:EXTHI
0 "=r,r"))]
905 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
907 (zero_extend:EXTHI (match_dup
1)))
909 (compare:CC (match_dup
0)
912 [(set_attr "type" "logical")
913 (set_attr "dot" "yes")
914 (set_attr "length" "
4,
8")])
916 (define_insn_and_split "*zero_extendhi<mode>
2_dot2"
917 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
918 (compare:CC (zero_extend:EXTHI (match_operand:HI
1 "gpc_reg_operand" "r,r"))
920 (set (match_operand:EXTHI
0 "gpc_reg_operand" "=r,r")
921 (zero_extend:EXTHI (match_dup
1)))]
926 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
928 (zero_extend:EXTHI (match_dup
1)))
930 (compare:CC (match_dup
0)
933 [(set_attr "type" "logical")
934 (set_attr "dot" "yes")
935 (set_attr "length" "
4,
8")])
938 (define_insn "zero_extendsi<mode>
2"
939 [(set (match_operand:EXTSI
0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
940 (zero_extend:EXTSI (match_operand:SI
1 "reg_or_mem_operand" "m,r,?Z,?Z,r,wa,wa")))]
949 xxextractuw %x0,%x1,
4"
950 [(set_attr "type" "load,shift,fpload,fpload,mtvsr,mfvsr,vecexts")
951 (set_attr "isa" "*,*,p7,p8v,p8v,p8v,p9v")])
953 (define_insn_and_split "*zero_extendsi<mode>
2_dot"
954 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
955 (compare:CC (zero_extend:EXTSI (match_operand:SI
1 "gpc_reg_operand" "r,r"))
957 (clobber (match_scratch:EXTSI
0 "=r,r"))]
962 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
964 (zero_extend:DI (match_dup
1)))
966 (compare:CC (match_dup
0)
969 [(set_attr "type" "shift")
970 (set_attr "dot" "yes")
971 (set_attr "length" "
4,
8")])
973 (define_insn_and_split "*zero_extendsi<mode>
2_dot2"
974 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
975 (compare:CC (zero_extend:EXTSI (match_operand:SI
1 "gpc_reg_operand" "r,r"))
977 (set (match_operand:EXTSI
0 "gpc_reg_operand" "=r,r")
978 (zero_extend:EXTSI (match_dup
1)))]
983 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
985 (zero_extend:EXTSI (match_dup
1)))
987 (compare:CC (match_dup
0)
990 [(set_attr "type" "shift")
991 (set_attr "dot" "yes")
992 (set_attr "length" "
4,
8")])
995 (define_insn "extendqi<mode>
2"
996 [(set (match_operand:EXTQI
0 "gpc_reg_operand" "=r,?*v")
997 (sign_extend:EXTQI (match_operand:QI
1 "gpc_reg_operand" "r,?*v")))]
1002 [(set_attr "type" "exts,vecperm")
1003 (set_attr "isa" "*,p9v")])
1005 (define_insn_and_split "*extendqi<mode>
2_dot"
1006 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
1007 (compare:CC (sign_extend:EXTQI (match_operand:QI
1 "gpc_reg_operand" "r,r"))
1009 (clobber (match_scratch:EXTQI
0 "=r,r"))]
1014 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
1016 (sign_extend:EXTQI (match_dup
1)))
1018 (compare:CC (match_dup
0)
1021 [(set_attr "type" "exts")
1022 (set_attr "dot" "yes")
1023 (set_attr "length" "
4,
8")])
1025 (define_insn_and_split "*extendqi<mode>
2_dot2"
1026 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
1027 (compare:CC (sign_extend:EXTQI (match_operand:QI
1 "gpc_reg_operand" "r,r"))
1029 (set (match_operand:EXTQI
0 "gpc_reg_operand" "=r,r")
1030 (sign_extend:EXTQI (match_dup
1)))]
1035 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
1037 (sign_extend:EXTQI (match_dup
1)))
1039 (compare:CC (match_dup
0)
1042 [(set_attr "type" "exts")
1043 (set_attr "dot" "yes")
1044 (set_attr "length" "
4,
8")])
1047 (define_expand "extendhi<mode>
2"
1048 [(set (match_operand:EXTHI
0 "gpc_reg_operand")
1049 (sign_extend:EXTHI (match_operand:HI
1 "gpc_reg_operand")))]
1053 (define_insn "*extendhi<mode>
2"
1054 [(set (match_operand:EXTHI
0 "gpc_reg_operand" "=r,r,?*v,?*v")
1055 (sign_extend:EXTHI (match_operand:HI
1 "reg_or_mem_operand" "m,r,Z,v")))]
1062 [(set_attr "type" "load,exts,fpload,vecperm")
1063 (set_attr "sign_extend" "yes")
1064 (set_attr "length" "*,*,
8,*")
1065 (set_attr "isa" "*,*,p9v,p9v")])
1068 [(set (match_operand:EXTHI
0 "altivec_register_operand")
1070 (match_operand:HI
1 "indexed_or_indirect_operand")))]
1071 "TARGET_P9_VECTOR && reload_completed"
1075 (sign_extend:EXTHI (match_dup
2)))]
1077 operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
0]));
1080 (define_insn_and_split "*extendhi<mode>
2_dot"
1081 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
1082 (compare:CC (sign_extend:EXTHI (match_operand:HI
1 "gpc_reg_operand" "r,r"))
1084 (clobber (match_scratch:EXTHI
0 "=r,r"))]
1089 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
1091 (sign_extend:EXTHI (match_dup
1)))
1093 (compare:CC (match_dup
0)
1096 [(set_attr "type" "exts")
1097 (set_attr "dot" "yes")
1098 (set_attr "length" "
4,
8")])
1100 (define_insn_and_split "*extendhi<mode>
2_dot2"
1101 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
1102 (compare:CC (sign_extend:EXTHI (match_operand:HI
1 "gpc_reg_operand" "r,r"))
1104 (set (match_operand:EXTHI
0 "gpc_reg_operand" "=r,r")
1105 (sign_extend:EXTHI (match_dup
1)))]
1110 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
1112 (sign_extend:EXTHI (match_dup
1)))
1114 (compare:CC (match_dup
0)
1117 [(set_attr "type" "exts")
1118 (set_attr "dot" "yes")
1119 (set_attr "length" "
4,
8")])
1122 (define_insn "extendsi<mode>
2"
1123 [(set (match_operand:EXTSI
0 "gpc_reg_operand"
1124 "=r, r, d, wa, wa, v, v, wr")
1125 (sign_extend:EXTSI (match_operand:SI
1 "lwa_operand"
1126 "YZ, r, Z, Z, r, v, v, ?wa")))]
1137 [(set_attr "type" "load,exts,fpload,fpload,mtvsr,vecexts,vecperm,mfvsr")
1138 (set_attr "sign_extend" "yes")
1139 (set_attr "length" "*,*,*,*,*,*,
8,
8")
1140 (set_attr "isa" "*,*,p6,p8v,p8v,p9v,p8v,p8v")])
1143 [(set (match_operand:EXTSI
0 "int_reg_operand")
1144 (sign_extend:EXTSI (match_operand:SI
1 "vsx_register_operand")))]
1145 "TARGET_DIRECT_MOVE_64BIT && reload_completed"
1149 (sign_extend:DI (match_dup
2)))]
1151 operands[
2] = gen_rtx_REG (SImode, reg_or_subregno (operands[
0]));
1155 [(set (match_operand:DI
0 "altivec_register_operand")
1156 (sign_extend:DI (match_operand:SI
1 "altivec_register_operand")))]
1157 "TARGET_P8_VECTOR && !TARGET_P9_VECTOR && reload_completed"
1160 rtx dest = operands[
0];
1161 rtx src = operands[
1];
1162 int dest_regno = REGNO (dest);
1163 int src_regno = REGNO (src);
1164 rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
1165 rtx src_v4si = gen_rtx_REG (V4SImode, src_regno);
1167 if (BYTES_BIG_ENDIAN)
1169 emit_insn (gen_altivec_vupkhsw (dest_v2di, src_v4si));
1170 emit_insn (gen_vsx_xxspltd_v2di (dest_v2di, dest_v2di, const1_rtx));
1174 emit_insn (gen_altivec_vupklsw (dest_v2di, src_v4si));
1175 emit_insn (gen_vsx_xxspltd_v2di (dest_v2di, dest_v2di, const0_rtx));
1180 (define_insn_and_split "*extendsi<mode>
2_dot"
1181 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
1182 (compare:CC (sign_extend:EXTSI (match_operand:SI
1 "gpc_reg_operand" "r,r"))
1184 (clobber (match_scratch:EXTSI
0 "=r,r"))]
1189 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
1191 (sign_extend:EXTSI (match_dup
1)))
1193 (compare:CC (match_dup
0)
1196 [(set_attr "type" "exts")
1197 (set_attr "dot" "yes")
1198 (set_attr "length" "
4,
8")])
1200 (define_insn_and_split "*extendsi<mode>
2_dot2"
1201 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
1202 (compare:CC (sign_extend:EXTSI (match_operand:SI
1 "gpc_reg_operand" "r,r"))
1204 (set (match_operand:EXTSI
0 "gpc_reg_operand" "=r,r")
1205 (sign_extend:EXTSI (match_dup
1)))]
1210 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
1212 (sign_extend:EXTSI (match_dup
1)))
1214 (compare:CC (match_dup
0)
1217 [(set_attr "type" "exts")
1218 (set_attr "dot" "yes")
1219 (set_attr "length" "
4,
8")])
1221 ;; IBM
405,
440,
464 and
476 half-word multiplication operations.
1223 (define_insn "*macchwc"
1224 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1225 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1226 (match_operand:SI
2 "gpc_reg_operand" "r")
1229 (match_operand:HI
1 "gpc_reg_operand" "r")))
1230 (match_operand:SI
4 "gpc_reg_operand" "
0"))
1232 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1233 (plus:SI (mult:SI (ashiftrt:SI
1241 [(set_attr "type" "halfmul")])
1243 (define_insn "*macchw"
1244 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1245 (plus:SI (mult:SI (ashiftrt:SI
1246 (match_operand:SI
2 "gpc_reg_operand" "r")
1249 (match_operand:HI
1 "gpc_reg_operand" "r")))
1250 (match_operand:SI
3 "gpc_reg_operand" "
0")))]
1253 [(set_attr "type" "halfmul")])
1255 (define_insn "*macchwuc"
1256 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1257 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1258 (match_operand:SI
2 "gpc_reg_operand" "r")
1261 (match_operand:HI
1 "gpc_reg_operand" "r")))
1262 (match_operand:SI
4 "gpc_reg_operand" "
0"))
1264 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1265 (plus:SI (mult:SI (lshiftrt:SI
1273 [(set_attr "type" "halfmul")])
1275 (define_insn "*macchwu"
1276 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1277 (plus:SI (mult:SI (lshiftrt:SI
1278 (match_operand:SI
2 "gpc_reg_operand" "r")
1281 (match_operand:HI
1 "gpc_reg_operand" "r")))
1282 (match_operand:SI
3 "gpc_reg_operand" "
0")))]
1285 [(set_attr "type" "halfmul")])
1287 (define_insn "*machhwc"
1288 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1289 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1290 (match_operand:SI
1 "gpc_reg_operand" "%r")
1293 (match_operand:SI
2 "gpc_reg_operand" "r")
1295 (match_operand:SI
4 "gpc_reg_operand" "
0"))
1297 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1298 (plus:SI (mult:SI (ashiftrt:SI
1307 [(set_attr "type" "halfmul")])
1309 (define_insn "*machhw"
1310 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1311 (plus:SI (mult:SI (ashiftrt:SI
1312 (match_operand:SI
1 "gpc_reg_operand" "%r")
1315 (match_operand:SI
2 "gpc_reg_operand" "r")
1317 (match_operand:SI
3 "gpc_reg_operand" "
0")))]
1320 [(set_attr "type" "halfmul")])
1322 (define_insn "*machhwuc"
1323 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1324 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1325 (match_operand:SI
1 "gpc_reg_operand" "%r")
1328 (match_operand:SI
2 "gpc_reg_operand" "r")
1330 (match_operand:SI
4 "gpc_reg_operand" "
0"))
1332 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1333 (plus:SI (mult:SI (lshiftrt:SI
1342 [(set_attr "type" "halfmul")])
1344 (define_insn "*machhwu"
1345 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1346 (plus:SI (mult:SI (lshiftrt:SI
1347 (match_operand:SI
1 "gpc_reg_operand" "%r")
1350 (match_operand:SI
2 "gpc_reg_operand" "r")
1352 (match_operand:SI
3 "gpc_reg_operand" "
0")))]
1355 [(set_attr "type" "halfmul")])
1357 (define_insn "*maclhwc"
1358 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1359 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1360 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1362 (match_operand:HI
2 "gpc_reg_operand" "r")))
1363 (match_operand:SI
4 "gpc_reg_operand" "
0"))
1365 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1366 (plus:SI (mult:SI (sign_extend:SI
1373 [(set_attr "type" "halfmul")])
1375 (define_insn "*maclhw"
1376 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1377 (plus:SI (mult:SI (sign_extend:SI
1378 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1380 (match_operand:HI
2 "gpc_reg_operand" "r")))
1381 (match_operand:SI
3 "gpc_reg_operand" "
0")))]
1384 [(set_attr "type" "halfmul")])
1386 (define_insn "*maclhwuc"
1387 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1388 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1389 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1391 (match_operand:HI
2 "gpc_reg_operand" "r")))
1392 (match_operand:SI
4 "gpc_reg_operand" "
0"))
1394 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1395 (plus:SI (mult:SI (zero_extend:SI
1402 [(set_attr "type" "halfmul")])
1404 (define_insn "*maclhwu"
1405 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1406 (plus:SI (mult:SI (zero_extend:SI
1407 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1409 (match_operand:HI
2 "gpc_reg_operand" "r")))
1410 (match_operand:SI
3 "gpc_reg_operand" "
0")))]
1413 [(set_attr "type" "halfmul")])
1415 (define_insn "*nmacchwc"
1416 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1417 (compare:CC (minus:SI (match_operand:SI
4 "gpc_reg_operand" "
0")
1418 (mult:SI (ashiftrt:SI
1419 (match_operand:SI
2 "gpc_reg_operand" "r")
1422 (match_operand:HI
1 "gpc_reg_operand" "r"))))
1424 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1425 (minus:SI (match_dup
4)
1426 (mult:SI (ashiftrt:SI
1433 [(set_attr "type" "halfmul")])
1435 (define_insn "*nmacchw"
1436 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1437 (minus:SI (match_operand:SI
3 "gpc_reg_operand" "
0")
1438 (mult:SI (ashiftrt:SI
1439 (match_operand:SI
2 "gpc_reg_operand" "r")
1442 (match_operand:HI
1 "gpc_reg_operand" "r")))))]
1445 [(set_attr "type" "halfmul")])
1447 (define_insn "*nmachhwc"
1448 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1449 (compare:CC (minus:SI (match_operand:SI
4 "gpc_reg_operand" "
0")
1450 (mult:SI (ashiftrt:SI
1451 (match_operand:SI
1 "gpc_reg_operand" "%r")
1454 (match_operand:SI
2 "gpc_reg_operand" "r")
1457 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1458 (minus:SI (match_dup
4)
1459 (mult:SI (ashiftrt:SI
1467 [(set_attr "type" "halfmul")])
1469 (define_insn "*nmachhw"
1470 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1471 (minus:SI (match_operand:SI
3 "gpc_reg_operand" "
0")
1472 (mult:SI (ashiftrt:SI
1473 (match_operand:SI
1 "gpc_reg_operand" "%r")
1476 (match_operand:SI
2 "gpc_reg_operand" "r")
1480 [(set_attr "type" "halfmul")])
1482 (define_insn "*nmaclhwc"
1483 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1484 (compare:CC (minus:SI (match_operand:SI
4 "gpc_reg_operand" "
0")
1485 (mult:SI (sign_extend:SI
1486 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1488 (match_operand:HI
2 "gpc_reg_operand" "r"))))
1490 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1491 (minus:SI (match_dup
4)
1492 (mult:SI (sign_extend:SI
1498 [(set_attr "type" "halfmul")])
1500 (define_insn "*nmaclhw"
1501 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1502 (minus:SI (match_operand:SI
3 "gpc_reg_operand" "
0")
1503 (mult:SI (sign_extend:SI
1504 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1506 (match_operand:HI
2 "gpc_reg_operand" "r")))))]
1509 [(set_attr "type" "halfmul")])
1511 (define_insn "*mulchwc"
1512 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1513 (compare:CC (mult:SI (ashiftrt:SI
1514 (match_operand:SI
2 "gpc_reg_operand" "r")
1517 (match_operand:HI
1 "gpc_reg_operand" "r")))
1519 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1520 (mult:SI (ashiftrt:SI
1527 [(set_attr "type" "halfmul")])
1529 (define_insn "*mulchw"
1530 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1531 (mult:SI (ashiftrt:SI
1532 (match_operand:SI
2 "gpc_reg_operand" "r")
1535 (match_operand:HI
1 "gpc_reg_operand" "r"))))]
1538 [(set_attr "type" "halfmul")])
1540 (define_insn "*mulchwuc"
1541 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1542 (compare:CC (mult:SI (lshiftrt:SI
1543 (match_operand:SI
2 "gpc_reg_operand" "r")
1546 (match_operand:HI
1 "gpc_reg_operand" "r")))
1548 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1549 (mult:SI (lshiftrt:SI
1556 [(set_attr "type" "halfmul")])
1558 (define_insn "*mulchwu"
1559 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1560 (mult:SI (lshiftrt:SI
1561 (match_operand:SI
2 "gpc_reg_operand" "r")
1564 (match_operand:HI
1 "gpc_reg_operand" "r"))))]
1567 [(set_attr "type" "halfmul")])
1569 (define_insn "*mulhhwc"
1570 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1571 (compare:CC (mult:SI (ashiftrt:SI
1572 (match_operand:SI
1 "gpc_reg_operand" "%r")
1575 (match_operand:SI
2 "gpc_reg_operand" "r")
1578 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1579 (mult:SI (ashiftrt:SI
1587 [(set_attr "type" "halfmul")])
1589 (define_insn "*mulhhw"
1590 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1591 (mult:SI (ashiftrt:SI
1592 (match_operand:SI
1 "gpc_reg_operand" "%r")
1595 (match_operand:SI
2 "gpc_reg_operand" "r")
1599 [(set_attr "type" "halfmul")])
1601 (define_insn "*mulhhwuc"
1602 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1603 (compare:CC (mult:SI (lshiftrt:SI
1604 (match_operand:SI
1 "gpc_reg_operand" "%r")
1607 (match_operand:SI
2 "gpc_reg_operand" "r")
1610 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1611 (mult:SI (lshiftrt:SI
1619 [(set_attr "type" "halfmul")])
1621 (define_insn "*mulhhwu"
1622 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1623 (mult:SI (lshiftrt:SI
1624 (match_operand:SI
1 "gpc_reg_operand" "%r")
1627 (match_operand:SI
2 "gpc_reg_operand" "r")
1631 [(set_attr "type" "halfmul")])
1633 (define_insn "*mullhwc"
1634 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1635 (compare:CC (mult:SI (sign_extend:SI
1636 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1638 (match_operand:HI
2 "gpc_reg_operand" "r")))
1640 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1641 (mult:SI (sign_extend:SI
1647 [(set_attr "type" "halfmul")])
1649 (define_insn "*mullhw"
1650 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1651 (mult:SI (sign_extend:SI
1652 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1654 (match_operand:HI
2 "gpc_reg_operand" "r"))))]
1657 [(set_attr "type" "halfmul")])
1659 (define_insn "*mullhwuc"
1660 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1661 (compare:CC (mult:SI (zero_extend:SI
1662 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1664 (match_operand:HI
2 "gpc_reg_operand" "r")))
1666 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1667 (mult:SI (zero_extend:SI
1673 [(set_attr "type" "halfmul")])
1675 (define_insn "*mullhwu"
1676 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1677 (mult:SI (zero_extend:SI
1678 (match_operand:HI
1 "gpc_reg_operand" "%r"))
1680 (match_operand:HI
2 "gpc_reg_operand" "r"))))]
1683 [(set_attr "type" "halfmul")])
1685 ;; IBM
405,
440,
464 and
476 string-search dlmzb instruction support.
1686 (define_insn "dlmzb"
1687 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1688 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
1689 (match_operand:SI
2 "gpc_reg_operand" "r")]
1691 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1692 (unspec:SI [(match_dup
1)
1698 (define_expand "strlensi"
1699 [(set (match_operand:SI
0 "gpc_reg_operand")
1700 (unspec:SI [(match_operand:BLK
1 "general_operand")
1701 (match_operand:QI
2 "const_int_operand")
1702 (match_operand
3 "const_int_operand")]
1703 UNSPEC_DLMZB_STRLEN))
1704 (clobber (match_scratch:CC
4))]
1705 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1707 rtx result = operands[
0];
1708 rtx src = operands[
1];
1709 rtx search_char = operands[
2];
1710 rtx align = operands[
3];
1711 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1712 rtx loop_label, end_label, mem, cr0, cond;
1713 if (search_char != const0_rtx
1714 || !CONST_INT_P (align)
1715 || INTVAL (align) <
8)
1717 word1 = gen_reg_rtx (SImode);
1718 word2 = gen_reg_rtx (SImode);
1719 scratch_dlmzb = gen_reg_rtx (SImode);
1720 scratch_string = gen_reg_rtx (Pmode);
1721 loop_label = gen_label_rtx ();
1722 end_label = gen_label_rtx ();
1723 addr = force_reg (Pmode, XEXP (src,
0));
1724 emit_move_insn (scratch_string, addr);
1725 emit_label (loop_label);
1726 mem = change_address (src, SImode, scratch_string);
1727 emit_move_insn (word1, mem);
1728 emit_move_insn (word2, adjust_address (mem, SImode,
4));
1729 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1730 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1731 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1732 emit_jump_insn (gen_rtx_SET (pc_rtx,
1733 gen_rtx_IF_THEN_ELSE (VOIDmode,
1739 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (
8)));
1740 emit_jump_insn (gen_rtx_SET (pc_rtx,
1741 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1743 emit_label (end_label);
1744 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1745 emit_insn (gen_subsi3 (result, scratch_string, addr));
1746 emit_insn (gen_addsi3 (result, result, constm1_rtx));
1750 ;; Fixed-point arithmetic insns.
1752 (define_expand "add<mode>
3"
1753 [(set (match_operand:SDI
0 "gpc_reg_operand")
1754 (plus:SDI (match_operand:SDI
1 "gpc_reg_operand")
1755 (match_operand:SDI
2 "reg_or_add_cint_operand")))]
1758 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1760 rtx lo0 = gen_lowpart (SImode, operands[
0]);
1761 rtx lo1 = gen_lowpart (SImode, operands[
1]);
1762 rtx lo2 = gen_lowpart (SImode, operands[
2]);
1763 rtx hi0 = gen_highpart (SImode, operands[
0]);
1764 rtx hi1 = gen_highpart (SImode, operands[
1]);
1765 rtx hi2 = gen_highpart_mode (SImode, DImode, operands[
2]);
1767 if (!reg_or_short_operand (lo2, SImode))
1768 lo2 = force_reg (SImode, lo2);
1769 if (!adde_operand (hi2, SImode))
1770 hi2 = force_reg (SImode, hi2);
1772 emit_insn (gen_addsi3_carry (lo0, lo1, lo2));
1773 emit_insn (gen_addsi3_carry_in (hi0, hi1, hi2));
1777 if (CONST_INT_P (operands[
2]) && !add_operand (operands[
2], <MODE>mode))
1779 rtx tmp = ((!can_create_pseudo_p ()
1780 || rtx_equal_p (operands[
0], operands[
1]))
1781 ? operands[
0] : gen_reg_rtx (<MODE>mode));
1783 /* Adding a constant to r0 is not a valid insn, so use a different
1784 strategy in that case. */
1785 if (reg_or_subregno (operands[
1]) ==
0 || reg_or_subregno (tmp) ==
0)
1787 if (operands[
0] == operands[
1])
1789 rs6000_emit_move (operands[
0], operands[
2], <MODE>mode);
1790 emit_insn (gen_add<mode>
3 (operands[
0], operands[
1], operands[
0]));
1794 HOST_WIDE_INT val = INTVAL (operands[
2]);
1795 HOST_WIDE_INT low = sext_hwi (val,
16);
1796 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1798 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1801 /* The ordering here is important for the prolog expander.
1802 When space is allocated from the stack, adding 'low' first may
1803 produce a temporary deallocation (which would be bad). */
1804 emit_insn (gen_add<mode>
3 (tmp, operands[
1], GEN_INT (rest)));
1805 emit_insn (gen_add<mode>
3 (operands[
0], tmp, GEN_INT (low)));
1810 (define_insn "*add<mode>
3"
1811 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r,r,r,r")
1812 (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,b,b,b")
1813 (match_operand:GPR
2 "add_operand" "r,I,L,eI")))]
1820 [(set_attr "type" "add")
1821 (set_attr "isa" "*,*,*,p10")])
1823 (define_insn "*addsi3_high"
1824 [(set (match_operand:SI
0 "gpc_reg_operand" "=b")
1825 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "b")
1826 (high:SI (match_operand
2 "" ""))))]
1827 "TARGET_MACHO && !TARGET_64BIT"
1828 "addis %
0,%
1,ha16(%
2)"
1829 [(set_attr "type" "add")])
1831 (define_insn_and_split "*add<mode>
3_dot"
1832 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
1833 (compare:CC (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
1834 (match_operand:GPR
2 "gpc_reg_operand" "r,r"))
1836 (clobber (match_scratch:GPR
0 "=r,r"))]
1837 "<MODE>mode == Pmode"
1841 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
1843 (plus:GPR (match_dup
1)
1846 (compare:CC (match_dup
0)
1849 [(set_attr "type" "add")
1850 (set_attr "dot" "yes")
1851 (set_attr "length" "
4,
8")])
1853 (define_insn_and_split "*add<mode>
3_dot2"
1854 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
1855 (compare:CC (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
1856 (match_operand:GPR
2 "gpc_reg_operand" "r,r"))
1858 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
1859 (plus:GPR (match_dup
1)
1861 "<MODE>mode == Pmode"
1865 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
1867 (plus:GPR (match_dup
1)
1870 (compare:CC (match_dup
0)
1873 [(set_attr "type" "add")
1874 (set_attr "dot" "yes")
1875 (set_attr "length" "
4,
8")])
1877 (define_insn_and_split "*add<mode>
3_imm_dot"
1878 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
1879 (compare:CC (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,b")
1880 (match_operand:GPR
2 "short_cint_operand" "I,I"))
1882 (clobber (match_scratch:GPR
0 "=r,r"))
1883 (clobber (reg:GPR CA_REGNO))]
1884 "<MODE>mode == Pmode"
1888 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
1890 (plus:GPR (match_dup
1)
1893 (compare:CC (match_dup
0)
1896 [(set_attr "type" "add")
1897 (set_attr "dot" "yes")
1898 (set_attr "length" "
4,
8")])
1900 (define_insn_and_split "*add<mode>
3_imm_dot2"
1901 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
1902 (compare:CC (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,b")
1903 (match_operand:GPR
2 "short_cint_operand" "I,I"))
1905 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
1906 (plus:GPR (match_dup
1)
1908 (clobber (reg:GPR CA_REGNO))]
1909 "<MODE>mode == Pmode"
1913 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
1915 (plus:GPR (match_dup
1)
1918 (compare:CC (match_dup
0)
1921 [(set_attr "type" "add")
1922 (set_attr "dot" "yes")
1923 (set_attr "length" "
4,
8")])
1925 ;; Split an add that we can't do in one insn into two insns, each of which
1926 ;; does one
16-bit part. This is used by combine. Note that the low-order
1927 ;; add should be last in case the result gets used in an address.
1930 [(set (match_operand:GPR
0 "gpc_reg_operand")
1931 (plus:GPR (match_operand:GPR
1 "gpc_reg_operand")
1932 (match_operand:GPR
2 "non_add_cint_operand")))]
1934 [(set (match_dup
0) (plus:GPR (match_dup
1) (match_dup
3)))
1935 (set (match_dup
0) (plus:GPR (match_dup
0) (match_dup
4)))]
1937 HOST_WIDE_INT val = INTVAL (operands[
2]);
1938 HOST_WIDE_INT low = sext_hwi (val,
16);
1939 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1941 operands[
4] = GEN_INT (low);
1942 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1943 operands[
3] = GEN_INT (rest);
1944 else if (can_create_pseudo_p ())
1946 operands[
3] = gen_reg_rtx (DImode);
1947 emit_move_insn (operands[
3], operands[
2]);
1948 emit_insn (gen_adddi3 (operands[
0], operands[
1], operands[
3]));
1956 (define_insn "add<mode>
3_carry"
1957 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
1958 (plus:P (match_operand:P
1 "gpc_reg_operand" "r")
1959 (match_operand:P
2 "reg_or_short_operand" "rI")))
1960 (set (reg:P CA_REGNO)
1961 (ltu:P (plus:P (match_dup
1)
1966 [(set_attr "type" "add")])
1968 (define_insn "*add<mode>
3_imm_carry_pos"
1969 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
1970 (plus:P (match_operand:P
1 "gpc_reg_operand" "r")
1971 (match_operand:P
2 "short_cint_operand" "n")))
1972 (set (reg:P CA_REGNO)
1973 (geu:P (match_dup
1)
1974 (match_operand:P
3 "const_int_operand" "n")))]
1975 "INTVAL (operands[
2]) >
0
1976 && INTVAL (operands[
2]) + INTVAL (operands[
3]) ==
0"
1978 [(set_attr "type" "add")])
1980 (define_insn "*add<mode>
3_imm_carry_0"
1981 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
1982 (match_operand:P
1 "gpc_reg_operand" "r"))
1983 (set (reg:P CA_REGNO)
1987 [(set_attr "type" "add")])
1989 (define_insn "*add<mode>
3_imm_carry_m1"
1990 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
1991 (plus:P (match_operand:P
1 "gpc_reg_operand" "r")
1993 (set (reg:P CA_REGNO)
1998 [(set_attr "type" "add")])
2000 (define_insn "*add<mode>
3_imm_carry_neg"
2001 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
2002 (plus:P (match_operand:P
1 "gpc_reg_operand" "r")
2003 (match_operand:P
2 "short_cint_operand" "n")))
2004 (set (reg:P CA_REGNO)
2005 (gtu:P (match_dup
1)
2006 (match_operand:P
3 "const_int_operand" "n")))]
2007 "INTVAL (operands[
2]) <
0
2008 && INTVAL (operands[
2]) + INTVAL (operands[
3]) == -
1"
2010 [(set_attr "type" "add")])
2013 (define_expand "add<mode>
3_carry_in"
2015 (set (match_operand:GPR
0 "gpc_reg_operand")
2016 (plus:GPR (plus:GPR (match_operand:GPR
1 "gpc_reg_operand")
2017 (match_operand:GPR
2 "adde_operand"))
2018 (reg:GPR CA_REGNO)))
2019 (clobber (reg:GPR CA_REGNO))])]
2022 if (operands[
2] == const0_rtx)
2024 emit_insn (gen_add<mode>
3_carry_in_0 (operands[
0], operands[
1]));
2027 if (operands[
2] == constm1_rtx)
2029 emit_insn (gen_add<mode>
3_carry_in_m1 (operands[
0], operands[
1]));
2034 (define_insn "*add<mode>
3_carry_in_internal"
2035 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2036 (plus:GPR (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
2037 (match_operand:GPR
2 "gpc_reg_operand" "r"))
2038 (reg:GPR CA_REGNO)))
2039 (clobber (reg:GPR CA_REGNO))]
2042 [(set_attr "type" "add")])
2044 (define_insn "*add<mode>
3_carry_in_internal2"
2045 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2046 (plus:GPR (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
2048 (match_operand:GPR
2 "gpc_reg_operand" "r")))
2049 (clobber (reg:GPR CA_REGNO))]
2052 [(set_attr "type" "add")])
2054 (define_insn "add<mode>
3_carry_in_0"
2055 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2056 (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
2057 (reg:GPR CA_REGNO)))
2058 (clobber (reg:GPR CA_REGNO))]
2061 [(set_attr "type" "add")])
2063 (define_insn "add<mode>
3_carry_in_m1"
2064 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2065 (plus:GPR (plus:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
2068 (clobber (reg:GPR CA_REGNO))]
2071 [(set_attr "type" "add")])
2074 (define_expand "one_cmpl<mode>
2"
2075 [(set (match_operand:SDI
0 "gpc_reg_operand")
2076 (not:SDI (match_operand:SDI
1 "gpc_reg_operand")))]
2079 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2081 rs6000_split_logical (operands, NOT, false, false, false);
2086 (define_insn "*one_cmpl<mode>
2"
2087 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2088 (not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")))]
2092 (define_insn_and_split "*one_cmpl<mode>
2_dot"
2093 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
2094 (compare:CC (not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
2096 (clobber (match_scratch:GPR
0 "=r,r"))]
2097 "<MODE>mode == Pmode"
2101 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
2103 (not:GPR (match_dup
1)))
2105 (compare:CC (match_dup
0)
2108 [(set_attr "type" "logical")
2109 (set_attr "dot" "yes")
2110 (set_attr "length" "
4,
8")])
2112 (define_insn_and_split "*one_cmpl<mode>
2_dot2"
2113 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
2114 (compare:CC (not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
2116 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
2117 (not:GPR (match_dup
1)))]
2118 "<MODE>mode == Pmode"
2122 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
2124 (not:GPR (match_dup
1)))
2126 (compare:CC (match_dup
0)
2129 [(set_attr "type" "logical")
2130 (set_attr "dot" "yes")
2131 (set_attr "length" "
4,
8")])
2134 (define_expand "sub<mode>
3"
2135 [(set (match_operand:SDI
0 "gpc_reg_operand")
2136 (minus:SDI (match_operand:SDI
1 "reg_or_short_operand")
2137 (match_operand:SDI
2 "gpc_reg_operand")))]
2140 if (<MODE>mode == DImode && !TARGET_POWERPC64)
2142 rtx lo0 = gen_lowpart (SImode, operands[
0]);
2143 rtx lo1 = gen_lowpart (SImode, operands[
1]);
2144 rtx lo2 = gen_lowpart (SImode, operands[
2]);
2145 rtx hi0 = gen_highpart (SImode, operands[
0]);
2146 rtx hi1 = gen_highpart_mode (SImode, DImode, operands[
1]);
2147 rtx hi2 = gen_highpart (SImode, operands[
2]);
2149 if (!reg_or_short_operand (lo1, SImode))
2150 lo1 = force_reg (SImode, lo1);
2151 if (!adde_operand (hi1, SImode))
2152 hi1 = force_reg (SImode, hi1);
2154 emit_insn (gen_subfsi3_carry (lo0, lo2, lo1));
2155 emit_insn (gen_subfsi3_carry_in (hi0, hi2, hi1));
2159 if (short_cint_operand (operands[
1], <MODE>mode))
2161 emit_insn (gen_subf<mode>
3_imm (operands[
0], operands[
2], operands[
1]));
2166 (define_insn "*subf<mode>
3"
2167 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2168 (minus:GPR (match_operand:GPR
2 "gpc_reg_operand" "r")
2169 (match_operand:GPR
1 "gpc_reg_operand" "r")))]
2172 [(set_attr "type" "add")])
2174 (define_insn_and_split "*subf<mode>
3_dot"
2175 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
2176 (compare:CC (minus:GPR (match_operand:GPR
2 "gpc_reg_operand" "r,r")
2177 (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
2179 (clobber (match_scratch:GPR
0 "=r,r"))]
2180 "<MODE>mode == Pmode"
2184 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
2186 (minus:GPR (match_dup
2)
2189 (compare:CC (match_dup
0)
2192 [(set_attr "type" "add")
2193 (set_attr "dot" "yes")
2194 (set_attr "length" "
4,
8")])
2196 (define_insn_and_split "*subf<mode>
3_dot2"
2197 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
2198 (compare:CC (minus:GPR (match_operand:GPR
2 "gpc_reg_operand" "r,r")
2199 (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
2201 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
2202 (minus:GPR (match_dup
2)
2204 "<MODE>mode == Pmode"
2208 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
2210 (minus:GPR (match_dup
2)
2213 (compare:CC (match_dup
0)
2216 [(set_attr "type" "add")
2217 (set_attr "dot" "yes")
2218 (set_attr "length" "
4,
8")])
2220 (define_insn "subf<mode>
3_imm"
2221 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2222 (minus:GPR (match_operand:GPR
2 "short_cint_operand" "I")
2223 (match_operand:GPR
1 "gpc_reg_operand" "r")))
2224 (clobber (reg:GPR CA_REGNO))]
2227 [(set_attr "type" "add")])
2229 (define_insn_and_split "subf<mode>
3_carry_dot2"
2230 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
2231 (compare:CC (minus:P (match_operand:P
2 "gpc_reg_operand" "r,r")
2232 (match_operand:P
1 "gpc_reg_operand" "r,r"))
2234 (set (match_operand:P
0 "gpc_reg_operand" "=r,r")
2235 (minus:P (match_dup
2)
2237 (set (reg:P CA_REGNO)
2238 (leu:P (match_dup
1)
2240 "<MODE>mode == Pmode"
2244 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
2245 [(parallel [(set (match_dup
0)
2246 (minus:P (match_dup
2)
2248 (set (reg:P CA_REGNO)
2249 (leu:P (match_dup
1)
2252 (compare:CC (match_dup
0)
2255 [(set_attr "type" "add")
2256 (set_attr "dot" "yes")
2257 (set_attr "length" "
4,
8")])
2259 (define_insn "subf<mode>
3_carry"
2260 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
2261 (minus:P (match_operand:P
2 "reg_or_short_operand" "rI")
2262 (match_operand:P
1 "gpc_reg_operand" "r")))
2263 (set (reg:P CA_REGNO)
2264 (leu:P (match_dup
1)
2268 [(set_attr "type" "add")])
2270 (define_insn "*subf<mode>
3_imm_carry_0"
2271 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
2272 (neg:P (match_operand:P
1 "gpc_reg_operand" "r")))
2273 (set (reg:P CA_REGNO)
2278 [(set_attr "type" "add")])
2280 (define_insn "*subf<mode>
3_imm_carry_m1"
2281 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
2282 (not:P (match_operand:P
1 "gpc_reg_operand" "r")))
2283 (set (reg:P CA_REGNO)
2287 [(set_attr "type" "add")])
2290 (define_expand "subf<mode>
3_carry_in"
2292 (set (match_operand:GPR
0 "gpc_reg_operand")
2293 (plus:GPR (plus:GPR (not:GPR (match_operand:GPR
1 "gpc_reg_operand"))
2295 (match_operand:GPR
2 "adde_operand")))
2296 (clobber (reg:GPR CA_REGNO))])]
2299 if (operands[
2] == const0_rtx)
2301 emit_insn (gen_subf<mode>
3_carry_in_0 (operands[
0], operands[
1]));
2304 if (operands[
2] == constm1_rtx)
2306 emit_insn (gen_subf<mode>
3_carry_in_m1 (operands[
0], operands[
1]));
2311 (define_insn "*subf<mode>
3_carry_in_internal"
2312 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2313 (plus:GPR (plus:GPR (not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r"))
2315 (match_operand:GPR
2 "gpc_reg_operand" "r")))
2316 (clobber (reg:GPR CA_REGNO))]
2319 [(set_attr "type" "add")])
2321 (define_insn "subf<mode>
3_carry_in_0"
2322 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2323 (plus:GPR (not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r"))
2324 (reg:GPR CA_REGNO)))
2325 (clobber (reg:GPR CA_REGNO))]
2328 [(set_attr "type" "add")])
2330 (define_insn "subf<mode>
3_carry_in_m1"
2331 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2332 (plus:GPR (minus:GPR (reg:GPR CA_REGNO)
2333 (match_operand:GPR
1 "gpc_reg_operand" "r"))
2335 (clobber (reg:GPR CA_REGNO))]
2338 [(set_attr "type" "add")])
2340 (define_insn "subf<mode>
3_carry_in_xx"
2341 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2342 (plus:GPR (reg:GPR CA_REGNO)
2344 (clobber (reg:GPR CA_REGNO))]
2347 [(set_attr "type" "add")])
2349 (define_insn_and_split "*subfsi3_carry_in_xx_64"
2350 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2351 (sign_extend:DI (plus:SI (reg:SI CA_REGNO)
2356 [(parallel [(set (match_dup
0)
2357 (plus:DI (reg:DI CA_REGNO)
2359 (clobber (reg:DI CA_REGNO))])]
2363 (define_insn "@neg<mode>
2"
2364 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2365 (neg:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")))]
2368 [(set_attr "type" "add")])
2370 (define_insn_and_split "*neg<mode>
2_dot"
2371 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
2372 (compare:CC (neg:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
2374 (clobber (match_scratch:GPR
0 "=r,r"))]
2375 "<MODE>mode == Pmode"
2379 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
2381 (neg:GPR (match_dup
1)))
2383 (compare:CC (match_dup
0)
2386 [(set_attr "type" "add")
2387 (set_attr "dot" "yes")
2388 (set_attr "length" "
4,
8")])
2390 (define_insn_and_split "*neg<mode>
2_dot2"
2391 [(set (match_operand:CC
2 "cc_reg_operand" "=x,?y")
2392 (compare:CC (neg:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
2394 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
2395 (neg:GPR (match_dup
1)))]
2396 "<MODE>mode == Pmode"
2400 "&& reload_completed && cc_reg_not_cr0_operand (operands[
2], CCmode)"
2402 (neg:GPR (match_dup
1)))
2404 (compare:CC (match_dup
0)
2407 [(set_attr "type" "add")
2408 (set_attr "dot" "yes")
2409 (set_attr "length" "
4,
8")])
2412 (define_insn "clz<mode>
2"
2413 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2414 (clz:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")))]
2417 [(set_attr "type" "cntlz")])
2419 (define_expand "ctz<mode>
2"
2420 [(set (match_operand:GPR
0 "gpc_reg_operand")
2421 (ctz:GPR (match_operand:GPR
1 "gpc_reg_operand")))]
2426 emit_insn (gen_ctz<mode>
2_hw (operands[
0], operands[
1]));
2430 rtx tmp1 = gen_reg_rtx (<MODE>mode);
2431 rtx tmp2 = gen_reg_rtx (<MODE>mode);
2432 rtx tmp3 = gen_reg_rtx (<MODE>mode);
2436 emit_insn (gen_add<mode>
3 (tmp1, operands[
1], constm1_rtx));
2437 emit_insn (gen_one_cmpl<mode>
2 (tmp2, operands[
1]));
2438 emit_insn (gen_and<mode>
3 (tmp3, tmp1, tmp2));
2439 emit_insn (gen_popcntd<mode>
2 (operands[
0], tmp3));
2443 emit_insn (gen_neg<mode>
2 (tmp1, operands[
1]));
2444 emit_insn (gen_and<mode>
3 (tmp2, operands[
1], tmp1));
2445 emit_insn (gen_clz<mode>
2 (tmp3, tmp2));
2446 emit_insn (gen_sub<mode>
3 (operands[
0], GEN_INT (<bits> -
1), tmp3));
2452 (define_insn "ctz<mode>
2_hw"
2453 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2454 (ctz:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")))]
2457 [(set_attr "type" "cntlz")])
2459 (define_expand "ffs<mode>
2"
2460 [(set (match_operand:GPR
0 "gpc_reg_operand")
2461 (ffs:GPR (match_operand:GPR
1 "gpc_reg_operand")))]
2464 rtx tmp1 = gen_reg_rtx (<MODE>mode);
2465 rtx tmp2 = gen_reg_rtx (<MODE>mode);
2466 rtx tmp3 = gen_reg_rtx (<MODE>mode);
2467 emit_insn (gen_neg<mode>
2 (tmp1, operands[
1]));
2468 emit_insn (gen_and<mode>
3 (tmp2, operands[
1], tmp1));
2469 emit_insn (gen_clz<mode>
2 (tmp3, tmp2));
2470 emit_insn (gen_sub<mode>
3 (operands[
0], GEN_INT (<bits>), tmp3));
2475 (define_expand "popcount<mode>
2"
2476 [(set (match_operand:GPR
0 "gpc_reg_operand")
2477 (popcount:GPR (match_operand:GPR
1 "gpc_reg_operand")))]
2478 "TARGET_POPCNTB || TARGET_POPCNTD"
2480 rs6000_emit_popcount (operands[
0], operands[
1]);
2484 (define_insn "popcntb<mode>
2"
2485 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2486 (unspec:GPR [(match_operand:GPR
1 "gpc_reg_operand" "r")]
2490 [(set_attr "type" "popcnt")])
2492 (define_insn "popcntd<mode>
2"
2493 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2494 (popcount:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")))]
2497 [(set_attr "type" "popcnt")])
2500 (define_expand "parity<mode>
2"
2501 [(set (match_operand:GPR
0 "gpc_reg_operand")
2502 (parity:GPR (match_operand:GPR
1 "gpc_reg_operand")))]
2505 rs6000_emit_parity (operands[
0], operands[
1]);
2509 (define_insn "parity<mode>
2_cmpb"
2510 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2511 (unspec:GPR [(match_operand:GPR
1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2512 "TARGET_CMPB && TARGET_POPCNTB"
2514 [(set_attr "type" "popcnt")])
2516 (define_insn "cfuged"
2517 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2518 (unspec:DI [(match_operand:DI
1 "gpc_reg_operand" "r")
2519 (match_operand:DI
2 "gpc_reg_operand" "r")]
2521 "TARGET_POWER10 && TARGET_64BIT"
2523 [(set_attr "type" "integer")])
2525 (define_insn "cntlzdm"
2526 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2527 (unspec:DI [(match_operand:DI
1 "gpc_reg_operand" "r")
2528 (match_operand:DI
2 "gpc_reg_operand" "r")]
2530 "TARGET_POWER10 && TARGET_POWERPC64"
2532 [(set_attr "type" "integer")])
2534 (define_insn "cnttzdm"
2535 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2536 (unspec:DI [(match_operand:DI
1 "gpc_reg_operand" "r")
2537 (match_operand:DI
2 "gpc_reg_operand" "r")]
2539 "TARGET_POWER10 && TARGET_POWERPC64"
2541 [(set_attr "type" "integer")])
2543 (define_insn "pdepd"
2544 [(set (match_operand:DI
0 "register_operand" "=r")
2545 (unspec:DI [(match_operand:DI
1 "gpc_reg_operand" "r")
2546 (match_operand:DI
2 "gpc_reg_operand" "r")]
2548 "TARGET_POWER10 && TARGET_POWERPC64"
2550 [(set_attr "type" "integer")])
2552 (define_insn "pextd"
2553 [(set (match_operand:DI
0 "register_operand" "=r")
2554 (unspec:DI [(match_operand:DI
1 "gpc_reg_operand" "r")
2555 (match_operand:DI
2 "gpc_reg_operand" "r")]
2557 "TARGET_POWER10 && TARGET_POWERPC64"
2559 [(set_attr "type" "integer")])
2561 (define_insn "cmpb<mode>
3"
2562 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
2563 (unspec:GPR [(match_operand:GPR
1 "gpc_reg_operand" "r")
2564 (match_operand:GPR
2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
2567 [(set_attr "type" "cmp")])
2569 ;; Since the hardware zeros the upper part of the register, save generating the
2570 ;; AND immediate if we are converting to unsigned
2571 (define_insn "*bswap<mode>
2_extenddi"
2572 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2574 (bswap:HSI (match_operand:HSI
1 "memory_operand" "Z"))))]
2577 [(set_attr "type" "load")])
2579 (define_insn "*bswaphi2_extendsi"
2580 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2582 (bswap:HI (match_operand:HI
1 "memory_operand" "Z"))))]
2585 [(set_attr "type" "load")])
2587 ;; Separate the bswap patterns into load, store, and gpr<-gpr. This prevents
2588 ;; the register allocator from converting a gpr<-gpr swap into a store and then
2589 ;; load with byte swap, which can be slower than doing it in the registers. It
2590 ;; also prevents certain failures with the RELOAD register allocator.
2592 (define_expand "bswap<mode>
2"
2593 [(use (match_operand:HSI
0 "reg_or_mem_operand"))
2594 (use (match_operand:HSI
1 "reg_or_mem_operand"))]
2597 rtx dest = operands[
0];
2598 rtx src = operands[
1];
2600 if (!REG_P (dest) && !REG_P (src))
2601 src = force_reg (<MODE>mode, src);
2605 src = rs6000_force_indexed_or_indirect_mem (src);
2606 emit_insn (gen_bswap<mode>
2_load (dest, src));
2608 else if (MEM_P (dest))
2610 dest = rs6000_force_indexed_or_indirect_mem (dest);
2611 emit_insn (gen_bswap<mode>
2_store (dest, src));
2614 emit_insn (gen_bswap<mode>
2_reg (dest, src));
2618 (define_insn "bswap<mode>
2_load"
2619 [(set (match_operand:HSI
0 "gpc_reg_operand" "=r")
2620 (bswap:HSI (match_operand:HSI
1 "memory_operand" "Z")))]
2623 [(set_attr "type" "load")])
2625 (define_insn "bswap<mode>
2_store"
2626 [(set (match_operand:HSI
0 "memory_operand" "=Z")
2627 (bswap:HSI (match_operand:HSI
1 "gpc_reg_operand" "r")))]
2630 [(set_attr "type" "store")])
2632 (define_insn_and_split "bswaphi2_reg"
2633 [(set (match_operand:HI
0 "gpc_reg_operand" "=r,&r,wa")
2635 (match_operand:HI
1 "gpc_reg_operand" "r,r,wa")))
2636 (clobber (match_scratch:SI
2 "=X,&r,X"))]
2642 "reload_completed && !TARGET_POWER10 && int_reg_operand (operands[
0], HImode)"
2644 (and:SI (lshiftrt:SI (match_dup
4)
2648 (and:SI (ashift:SI (match_dup
4)
2650 (const_int
65280))) ;;
0xff00
2652 (ior:SI (match_dup
3)
2655 operands[
3] = simplify_gen_subreg (SImode, operands[
0], HImode,
0);
2656 operands[
4] = simplify_gen_subreg (SImode, operands[
1], HImode,
0);
2658 [(set_attr "length" "*,
12,*")
2659 (set_attr "type" "shift,*,vecperm")
2660 (set_attr "isa" "p10,*,p9v")])
2662 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2663 ;; zero_extract insns do not change for -mlittle.
2664 (define_insn_and_split "bswapsi2_reg"
2665 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,&r,wa")
2667 (match_operand:SI
1 "gpc_reg_operand" "r,r,wa")))]
2673 "reload_completed && !TARGET_POWER10 && int_reg_operand (operands[
0], SImode)"
2674 [(set (match_dup
0) ; DABC
2675 (rotate:SI (match_dup
1)
2677 (set (match_dup
0) ; DCBC
2678 (ior:SI (and:SI (ashift:SI (match_dup
1)
2680 (const_int
16711680))
2681 (and:SI (match_dup
0)
2682 (const_int -
16711681))))
2683 (set (match_dup
0) ; DCBA
2684 (ior:SI (and:SI (lshiftrt:SI (match_dup
1)
2687 (and:SI (match_dup
0)
2688 (const_int -
256))))]
2690 [(set_attr "length" "
4,
12,
4")
2691 (set_attr "type" "shift,*,vecperm")
2692 (set_attr "isa" "p10,*,p9v")])
2694 ;; On systems with LDBRX/STDBRX generate the loads/stores directly, just like
2695 ;; we do for L{H,W}BRX and ST{H,W}BRX above. If not, we have to generate more
2698 (define_expand "bswapdi2"
2699 [(parallel [(set (match_operand:DI
0 "reg_or_mem_operand")
2701 (match_operand:DI
1 "reg_or_mem_operand")))
2702 (clobber (match_scratch:DI
2))
2703 (clobber (match_scratch:DI
3))])]
2706 rtx dest = operands[
0];
2707 rtx src = operands[
1];
2709 if (!REG_P (dest) && !REG_P (src))
2710 operands[
1] = src = force_reg (DImode, src);
2712 if (TARGET_POWERPC64 && TARGET_LDBRX)
2716 src = rs6000_force_indexed_or_indirect_mem (src);
2717 emit_insn (gen_bswapdi2_load (dest, src));
2719 else if (MEM_P (dest))
2721 dest = rs6000_force_indexed_or_indirect_mem (dest);
2722 emit_insn (gen_bswapdi2_store (dest, src));
2724 else if (TARGET_P9_VECTOR)
2725 emit_insn (gen_bswapdi2_brd (dest, src));
2727 emit_insn (gen_bswapdi2_reg (dest, src));
2731 if (!TARGET_POWERPC64)
2733 /*
32-bit mode needs fewer scratch registers, but
32-bit addressing mode
2734 that uses
64-bit registers needs the same scratch registers as
64-bit
2736 emit_insn (gen_bswapdi2_32bit (dest, src));
2741 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2742 (define_insn "bswapdi2_load"
2743 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2744 (bswap:DI (match_operand:DI
1 "memory_operand" "Z")))]
2745 "TARGET_POWERPC64 && TARGET_LDBRX"
2747 [(set_attr "type" "load")])
2749 (define_insn "bswapdi2_store"
2750 [(set (match_operand:DI
0 "memory_operand" "=Z")
2751 (bswap:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
2752 "TARGET_POWERPC64 && TARGET_LDBRX"
2754 [(set_attr "type" "store")])
2756 (define_insn "bswapdi2_brd"
2757 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,wa")
2758 (bswap:DI (match_operand:DI
1 "gpc_reg_operand" "r,wa")))]
2763 [(set_attr "type" "shift,vecperm")
2764 (set_attr "isa" "p10,p9v")])
2766 (define_insn "bswapdi2_reg"
2767 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
2768 (bswap:DI (match_operand:DI
1 "gpc_reg_operand" "r")))
2769 (clobber (match_scratch:DI
2 "=&r"))
2770 (clobber (match_scratch:DI
3 "=&r"))]
2771 "TARGET_POWERPC64 && TARGET_LDBRX && !TARGET_P9_VECTOR"
2773 [(set_attr "length" "
36")])
2775 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2776 (define_insn "*bswapdi2_64bit"
2777 [(set (match_operand:DI
0 "reg_or_mem_operand" "=r,Z,&r")
2778 (bswap:DI (match_operand:DI
1 "reg_or_mem_operand" "Z,r,r")))
2779 (clobber (match_scratch:DI
2 "=&b,&b,&r"))
2780 (clobber (match_scratch:DI
3 "=&r,&r,&r"))]
2781 "TARGET_POWERPC64 && !TARGET_LDBRX
2782 && (REG_P (operands[
0]) || REG_P (operands[
1]))
2783 && !(MEM_P (operands[
0]) && MEM_VOLATILE_P (operands[
0]))
2784 && !(MEM_P (operands[
1]) && MEM_VOLATILE_P (operands[
1]))"
2786 [(set_attr "length" "
16,
12,
36")])
2789 [(set (match_operand:DI
0 "gpc_reg_operand")
2790 (bswap:DI (match_operand:DI
1 "indexed_or_indirect_operand")))
2791 (clobber (match_operand:DI
2 "gpc_reg_operand"))
2792 (clobber (match_operand:DI
3 "gpc_reg_operand"))]
2793 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2796 rtx dest = operands[
0];
2797 rtx src = operands[
1];
2798 rtx op2 = operands[
2];
2799 rtx op3 = operands[
3];
2800 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2801 BYTES_BIG_ENDIAN ?
4 :
0);
2802 rtx dest_32 = simplify_gen_subreg (SImode, dest, DImode,
2803 BYTES_BIG_ENDIAN ?
4 :
0);
2809 addr1 = XEXP (src,
0);
2810 if (GET_CODE (addr1) == PLUS)
2812 emit_insn (gen_add3_insn (op2, XEXP (addr1,
0), GEN_INT (
4)));
2813 if (TARGET_AVOID_XFORM)
2815 emit_insn (gen_add3_insn (op2, XEXP (addr1,
1), op2));
2819 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1,
1));
2821 else if (TARGET_AVOID_XFORM)
2823 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (
4)));
2828 emit_move_insn (op2, GEN_INT (
4));
2829 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2832 word1 = change_address (src, SImode, addr1);
2833 word2 = change_address (src, SImode, addr2);
2835 if (BYTES_BIG_ENDIAN)
2837 emit_insn (gen_bswapsi2 (op3_32, word2));
2838 emit_insn (gen_bswapsi2 (dest_32, word1));
2842 emit_insn (gen_bswapsi2 (op3_32, word1));
2843 emit_insn (gen_bswapsi2 (dest_32, word2));
2846 emit_insn (gen_rotldi3_insert_3 (dest, op3, GEN_INT (
32), dest,
2847 GEN_INT (
0xffffffff)));
2852 [(set (match_operand:DI
0 "indexed_or_indirect_operand")
2853 (bswap:DI (match_operand:DI
1 "gpc_reg_operand")))
2854 (clobber (match_operand:DI
2 "gpc_reg_operand"))
2855 (clobber (match_operand:DI
3 "gpc_reg_operand"))]
2856 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2859 rtx dest = operands[
0];
2860 rtx src = operands[
1];
2861 rtx op2 = operands[
2];
2862 rtx op3 = operands[
3];
2863 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2864 BYTES_BIG_ENDIAN ?
4 :
0);
2865 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2866 BYTES_BIG_ENDIAN ?
4 :
0);
2872 addr1 = XEXP (dest,
0);
2873 if (GET_CODE (addr1) == PLUS)
2875 emit_insn (gen_add3_insn (op2, XEXP (addr1,
0), GEN_INT (
4)));
2876 if (TARGET_AVOID_XFORM)
2878 emit_insn (gen_add3_insn (op2, XEXP (addr1,
1), op2));
2882 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1,
1));
2884 else if (TARGET_AVOID_XFORM)
2886 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (
4)));
2891 emit_move_insn (op2, GEN_INT (
4));
2892 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2895 word1 = change_address (dest, SImode, addr1);
2896 word2 = change_address (dest, SImode, addr2);
2898 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (
32)));
2900 if (BYTES_BIG_ENDIAN)
2902 emit_insn (gen_bswapsi2 (word1, src_si));
2903 emit_insn (gen_bswapsi2 (word2, op3_si));
2907 emit_insn (gen_bswapsi2 (word2, src_si));
2908 emit_insn (gen_bswapsi2 (word1, op3_si));
2914 [(set (match_operand:DI
0 "gpc_reg_operand")
2915 (bswap:DI (match_operand:DI
1 "gpc_reg_operand")))
2916 (clobber (match_operand:DI
2 "gpc_reg_operand"))
2917 (clobber (match_operand:DI
3 "gpc_reg_operand"))]
2918 "TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed"
2921 rtx dest = operands[
0];
2922 rtx src = operands[
1];
2923 rtx op2 = operands[
2];
2924 rtx op3 = operands[
3];
2925 int lo_off = BYTES_BIG_ENDIAN ?
4 :
0;
2926 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2927 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2928 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2929 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2931 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (
32)));
2932 emit_insn (gen_bswapsi2 (op3_si, src_si));
2933 emit_insn (gen_bswapsi2 (dest_si, op2_si));
2934 emit_insn (gen_rotldi3_insert_3 (dest, op3, GEN_INT (
32), dest,
2935 GEN_INT (
0xffffffff)));
2939 (define_insn "bswapdi2_32bit"
2940 [(set (match_operand:DI
0 "reg_or_mem_operand" "=r,Z,?&r")
2941 (bswap:DI (match_operand:DI
1 "reg_or_mem_operand" "Z,r,r")))
2942 (clobber (match_scratch:SI
2 "=&b,&b,X"))]
2943 "!TARGET_POWERPC64 && (REG_P (operands[
0]) || REG_P (operands[
1]))"
2945 [(set_attr "length" "
16,
12,
36")])
2948 [(set (match_operand:DI
0 "gpc_reg_operand")
2949 (bswap:DI (match_operand:DI
1 "indexed_or_indirect_operand")))
2950 (clobber (match_operand:SI
2 "gpc_reg_operand"))]
2951 "!TARGET_POWERPC64 && reload_completed"
2954 rtx dest = operands[
0];
2955 rtx src = operands[
1];
2956 rtx op2 = operands[
2];
2957 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode,
0);
2958 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode,
4);
2964 addr1 = XEXP (src,
0);
2965 if (GET_CODE (addr1) == PLUS)
2967 emit_insn (gen_add3_insn (op2, XEXP (addr1,
0), GEN_INT (
4)));
2968 if (TARGET_AVOID_XFORM
2969 || REGNO (XEXP (addr1,
1)) == REGNO (dest2))
2971 emit_insn (gen_add3_insn (op2, XEXP (addr1,
1), op2));
2975 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1,
1));
2977 else if (TARGET_AVOID_XFORM
2978 || REGNO (addr1) == REGNO (dest2))
2980 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (
4)));
2985 emit_move_insn (op2, GEN_INT (
4));
2986 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2989 word1 = change_address (src, SImode, addr1);
2990 word2 = change_address (src, SImode, addr2);
2992 emit_insn (gen_bswapsi2 (dest2, word1));
2993 /* The REGNO (dest2) tests above ensure that addr2 has not been trashed,
2994 thus allowing us to omit an early clobber on the output. */
2995 emit_insn (gen_bswapsi2 (dest1, word2));
3000 [(set (match_operand:DI
0 "indexed_or_indirect_operand")
3001 (bswap:DI (match_operand:DI
1 "gpc_reg_operand")))
3002 (clobber (match_operand:SI
2 "gpc_reg_operand"))]
3003 "!TARGET_POWERPC64 && reload_completed"
3006 rtx dest = operands[
0];
3007 rtx src = operands[
1];
3008 rtx op2 = operands[
2];
3009 rtx src1 = simplify_gen_subreg (SImode, src, DImode,
0);
3010 rtx src2 = simplify_gen_subreg (SImode, src, DImode,
4);
3016 addr1 = XEXP (dest,
0);
3017 if (GET_CODE (addr1) == PLUS)
3019 emit_insn (gen_add3_insn (op2, XEXP (addr1,
0), GEN_INT (
4)));
3020 if (TARGET_AVOID_XFORM)
3022 emit_insn (gen_add3_insn (op2, XEXP (addr1,
1), op2));
3026 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1,
1));
3028 else if (TARGET_AVOID_XFORM)
3030 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (
4)));
3035 emit_move_insn (op2, GEN_INT (
4));
3036 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
3039 word1 = change_address (dest, SImode, addr1);
3040 word2 = change_address (dest, SImode, addr2);
3042 emit_insn (gen_bswapsi2 (word2, src1));
3043 emit_insn (gen_bswapsi2 (word1, src2));
3048 [(set (match_operand:DI
0 "gpc_reg_operand")
3049 (bswap:DI (match_operand:DI
1 "gpc_reg_operand")))
3050 (clobber (match_operand:SI
2 ""))]
3051 "!TARGET_POWERPC64 && reload_completed"
3054 rtx dest = operands[
0];
3055 rtx src = operands[
1];
3056 rtx src1 = simplify_gen_subreg (SImode, src, DImode,
0);
3057 rtx src2 = simplify_gen_subreg (SImode, src, DImode,
4);
3058 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode,
0);
3059 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode,
4);
3061 emit_insn (gen_bswapsi2 (dest1, src2));
3062 emit_insn (gen_bswapsi2 (dest2, src1));
3067 (define_insn "mul<mode>
3"
3068 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
3069 (mult:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3070 (match_operand:GPR
2 "reg_or_short_operand" "r,I")))]
3075 [(set_attr "type" "mul")
3077 (cond [(match_operand:GPR
2 "s8bit_cint_operand")
3079 (match_operand:GPR
2 "short_cint_operand")
3080 (const_string "
16")]
3081 (const_string "<bits>")))])
3083 (define_insn_and_split "*mul<mode>
3_dot"
3084 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3085 (compare:CC (mult:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
3086 (match_operand:GPR
2 "gpc_reg_operand" "r,r"))
3088 (clobber (match_scratch:GPR
0 "=r,r"))]
3089 "<MODE>mode == Pmode"
3093 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3095 (mult:GPR (match_dup
1)
3098 (compare:CC (match_dup
0)
3101 [(set_attr "type" "mul")
3102 (set_attr "size" "<bits>")
3103 (set_attr "dot" "yes")
3104 (set_attr "length" "
4,
8")])
3106 (define_insn_and_split "*mul<mode>
3_dot2"
3107 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3108 (compare:CC (mult:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
3109 (match_operand:GPR
2 "gpc_reg_operand" "r,r"))
3111 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
3112 (mult:GPR (match_dup
1)
3114 "<MODE>mode == Pmode"
3118 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3120 (mult:GPR (match_dup
1)
3123 (compare:CC (match_dup
0)
3126 [(set_attr "type" "mul")
3127 (set_attr "size" "<bits>")
3128 (set_attr "dot" "yes")
3129 (set_attr "length" "
4,
8")])
3132 (define_expand "<su>mul<mode>
3_highpart"
3133 [(set (match_operand:GPR
0 "gpc_reg_operand")
3135 (mult:<DMODE> (any_extend:<DMODE>
3136 (match_operand:GPR
1 "gpc_reg_operand"))
3138 (match_operand:GPR
2 "gpc_reg_operand")))
3142 if (<MODE>mode == SImode && TARGET_POWERPC64)
3144 emit_insn (gen_<su>mulsi3_highpart_64 (operands[
0], operands[
1],
3149 if (!WORDS_BIG_ENDIAN)
3151 emit_insn (gen_<su>mul<mode>
3_highpart_le (operands[
0], operands[
1],
3157 (define_insn "*<su>mul<mode>
3_highpart"
3158 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3160 (mult:<DMODE> (any_extend:<DMODE>
3161 (match_operand:GPR
1 "gpc_reg_operand" "r"))
3163 (match_operand:GPR
2 "gpc_reg_operand" "r")))
3165 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
3166 "mulh<wd><u> %
0,%
1,%
2"
3167 [(set_attr "type" "mul")
3168 (set_attr "size" "<bits>")])
3170 (define_insn "<su>mulsi3_highpart_le"
3171 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3173 (mult:DI (any_extend:DI
3174 (match_operand:SI
1 "gpc_reg_operand" "r"))
3176 (match_operand:SI
2 "gpc_reg_operand" "r")))
3178 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
3180 [(set_attr "type" "mul")])
3182 (define_insn "<su>muldi3_highpart_le"
3183 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
3185 (mult:TI (any_extend:TI
3186 (match_operand:DI
1 "gpc_reg_operand" "r"))
3188 (match_operand:DI
2 "gpc_reg_operand" "r")))
3190 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
3192 [(set_attr "type" "mul")
3193 (set_attr "size" "
64")])
3195 (define_insn "<su>mulsi3_highpart_64"
3196 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3199 (mult:DI (any_extend:DI
3200 (match_operand:SI
1 "gpc_reg_operand" "r"))
3202 (match_operand:SI
2 "gpc_reg_operand" "r")))
3206 [(set_attr "type" "mul")])
3208 (define_expand "<u>mul<mode><dmode>
3"
3209 [(set (match_operand:<DMODE>
0 "gpc_reg_operand")
3210 (mult:<DMODE> (any_extend:<DMODE>
3211 (match_operand:GPR
1 "gpc_reg_operand"))
3213 (match_operand:GPR
2 "gpc_reg_operand"))))]
3214 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
3216 rtx l = gen_reg_rtx (<MODE>mode);
3217 rtx h = gen_reg_rtx (<MODE>mode);
3218 emit_insn (gen_mul<mode>
3 (l, operands[
1], operands[
2]));
3219 emit_insn (gen_<su>mul<mode>
3_highpart (h, operands[
1], operands[
2]));
3220 emit_move_insn (gen_lowpart (<MODE>mode, operands[
0]), l);
3221 emit_move_insn (gen_highpart (<MODE>mode, operands[
0]), h);
3225 (define_insn "maddld<mode>
4"
3226 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3227 (plus:GPR (mult:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
3228 (match_operand:GPR
2 "gpc_reg_operand" "r"))
3229 (match_operand:GPR
3 "gpc_reg_operand" "r")))]
3231 "maddld %
0,%
1,%
2,%
3"
3232 [(set_attr "type" "mul")])
3234 ;; umaddditi4 generally needs maddhdu + maddld + add instructions,
3235 ;; unless last operand is zero extended from DImode, then needs
3236 ;; maddhdu + maddld, which is both faster than mulld + mulhdu + addc + adde
3237 ;; resp. mulld + mulhdu + addc + addze.
3238 ;; We don't define maddditi4, as that one needs
3239 ;; maddhd + sradi + maddld + add + sub and for last operand sign extended
3240 ;; from DImode nothing is able to optimize it into maddhd + maddld, while
3241 ;; without maddditi4 mulld + mulhd + addc + adde or
3242 ;; mulld + mulhd + sradi + addc + adde is needed. See PR108787.
3243 (define_expand "umaddditi4"
3244 [(set (match_operand:TI
0 "gpc_reg_operand")
3246 (mult:TI (zero_extend:TI (match_operand:DI
1 "gpc_reg_operand"))
3247 (zero_extend:TI (match_operand:DI
2 "gpc_reg_operand")))
3248 (match_operand:TI
3 "gpc_reg_operand")))]
3249 "TARGET_MADDLD && TARGET_POWERPC64"
3251 rtx op0_lo = gen_rtx_SUBREG (DImode, operands[
0], BYTES_BIG_ENDIAN ?
8 :
0);
3252 rtx op0_hi = gen_rtx_SUBREG (DImode, operands[
0], BYTES_BIG_ENDIAN ?
0 :
8);
3253 rtx op3_lo = gen_rtx_SUBREG (DImode, operands[
3], BYTES_BIG_ENDIAN ?
8 :
0);
3254 rtx op3_hi = gen_rtx_SUBREG (DImode, operands[
3], BYTES_BIG_ENDIAN ?
0 :
8);
3255 rtx hi_temp = gen_reg_rtx (DImode);
3257 if (BYTES_BIG_ENDIAN)
3258 emit_insn (gen_umadddi4_highpart (hi_temp, operands[
1], operands[
2],
3261 emit_insn (gen_umadddi4_highpart_le (hi_temp, operands[
1], operands[
2],
3264 emit_insn (gen_maddlddi4 (op0_lo, operands[
1], operands[
2], op3_lo));
3266 emit_insn (gen_adddi3 (op0_hi, hi_temp, op3_hi));
3271 (define_insn "<u>madddi4_highpart"
3272 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
3275 (mult:TI (any_extend:TI (match_operand:DI
1 "gpc_reg_operand" "r"))
3276 (any_extend:TI (match_operand:DI
2 "gpc_reg_operand" "r")))
3277 (any_extend:TI (match_operand:DI
3 "gpc_reg_operand" "r")))
3279 "TARGET_MADDLD && BYTES_BIG_ENDIAN && TARGET_POWERPC64"
3280 "maddhd<u> %
0,%
1,%
2,%
3"
3281 [(set_attr "type" "mul")])
3283 (define_insn "<u>madddi4_highpart_le"
3284 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
3287 (mult:TI (any_extend:TI (match_operand:DI
1 "gpc_reg_operand" "r"))
3288 (any_extend:TI (match_operand:DI
2 "gpc_reg_operand" "r")))
3289 (any_extend:TI (match_operand:DI
3 "gpc_reg_operand" "r")))
3291 "TARGET_MADDLD && !BYTES_BIG_ENDIAN && TARGET_POWERPC64"
3292 "maddhd<u> %
0,%
1,%
2,%
3"
3293 [(set_attr "type" "mul")])
3295 (define_insn "udiv<mode>
3"
3296 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3297 (udiv:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
3298 (match_operand:GPR
2 "gpc_reg_operand" "r")))]
3301 [(set_attr "type" "div")
3302 (set_attr "size" "<bits>")])
3304 (define_insn "udivti3"
3305 [(set (match_operand:TI
0 "altivec_register_operand" "=v")
3306 (udiv:TI (match_operand:TI
1 "altivec_register_operand" "v")
3307 (match_operand:TI
2 "altivec_register_operand" "v")))]
3308 "TARGET_POWER10 && TARGET_POWERPC64"
3310 [(set_attr "type" "vecdiv")
3311 (set_attr "size" "
128")])
3313 ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
3314 ;; modulus. If it isn't a power of two, force operands into register and do
3316 (define_expand "div<mode>
3"
3317 [(set (match_operand:GPR
0 "gpc_reg_operand")
3318 (div:GPR (match_operand:GPR
1 "gpc_reg_operand")
3319 (match_operand:GPR
2 "reg_or_cint_operand")))]
3322 if (CONST_INT_P (operands[
2])
3323 && INTVAL (operands[
2]) >
0
3324 && exact_log2 (INTVAL (operands[
2])) >=
0)
3326 emit_insn (gen_div<mode>
3_sra (operands[
0], operands[
1], operands[
2]));
3330 operands[
2] = force_reg (<MODE>mode, operands[
2]);
3333 (define_insn "*div<mode>
3"
3334 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3335 (div:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
3336 (match_operand:GPR
2 "gpc_reg_operand" "r")))]
3339 [(set_attr "type" "div")
3340 (set_attr "size" "<bits>")])
3342 (define_insn "div<mode>
3_sra"
3343 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3344 (div:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
3345 (match_operand:GPR
2 "exact_log2_cint_operand" "N")))
3346 (clobber (reg:GPR CA_REGNO))]
3348 "sra<wd>i %
0,%
1,%p2\;addze %
0,%
0"
3349 [(set_attr "type" "two")
3350 (set_attr "length" "
8")])
3352 (define_insn_and_split "*div<mode>
3_sra_dot"
3353 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3354 (compare:CC (div:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
3355 (match_operand:GPR
2 "exact_log2_cint_operand" "N,N"))
3357 (clobber (match_scratch:GPR
0 "=r,r"))
3358 (clobber (reg:GPR CA_REGNO))]
3359 "<MODE>mode == Pmode"
3361 sra<wd>i %
0,%
1,%p2\;addze. %
0,%
0
3363 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3364 [(parallel [(set (match_dup
0)
3365 (div:GPR (match_dup
1)
3367 (clobber (reg:GPR CA_REGNO))])
3369 (compare:CC (match_dup
0)
3372 [(set_attr "type" "two")
3373 (set_attr "length" "
8,
12")
3374 (set_attr "cell_micro" "not")])
3376 (define_insn_and_split "*div<mode>
3_sra_dot2"
3377 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3378 (compare:CC (div:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
3379 (match_operand:GPR
2 "exact_log2_cint_operand" "N,N"))
3381 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
3382 (div:GPR (match_dup
1)
3384 (clobber (reg:GPR CA_REGNO))]
3385 "<MODE>mode == Pmode"
3387 sra<wd>i %
0,%
1,%p2\;addze. %
0,%
0
3389 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3390 [(parallel [(set (match_dup
0)
3391 (div:GPR (match_dup
1)
3393 (clobber (reg:GPR CA_REGNO))])
3395 (compare:CC (match_dup
0)
3398 [(set_attr "type" "two")
3399 (set_attr "length" "
8,
12")
3400 (set_attr "cell_micro" "not")])
3402 (define_insn "divti3"
3403 [(set (match_operand:TI
0 "altivec_register_operand" "=v")
3404 (div:TI (match_operand:TI
1 "altivec_register_operand" "v")
3405 (match_operand:TI
2 "altivec_register_operand" "v")))]
3406 "TARGET_POWER10 && TARGET_POWERPC64"
3408 [(set_attr "type" "vecdiv")
3409 (set_attr "size" "
128")])
3411 (define_expand "mod<mode>
3"
3412 [(set (match_operand:GPR
0 "gpc_reg_operand")
3413 (mod:GPR (match_operand:GPR
1 "gpc_reg_operand")
3414 (match_operand:GPR
2 "reg_or_cint_operand")))]
3421 if (!CONST_INT_P (operands[
2])
3422 || INTVAL (operands[
2]) <=
0
3423 || (i = exact_log2 (INTVAL (operands[
2]))) <
0)
3428 operands[
2] = force_reg (<MODE>mode, operands[
2]);
3430 if (RS6000_DISABLE_SCALAR_MODULO)
3432 temp1 = gen_reg_rtx (<MODE>mode);
3433 temp2 = gen_reg_rtx (<MODE>mode);
3435 emit_insn (gen_div<mode>
3 (temp1, operands[
1], operands[
2]));
3436 emit_insn (gen_mul<mode>
3 (temp2, temp1, operands[
2]));
3437 emit_insn (gen_sub<mode>
3 (operands[
0], operands[
1], temp2));
3443 temp1 = gen_reg_rtx (<MODE>mode);
3444 temp2 = gen_reg_rtx (<MODE>mode);
3446 emit_insn (gen_div<mode>
3 (temp1, operands[
1], operands[
2]));
3447 emit_insn (gen_ashl<mode>
3 (temp2, temp1, GEN_INT (i)));
3448 emit_insn (gen_sub<mode>
3 (operands[
0], operands[
1], temp2));
3453 ;; In order to enable using a peephole2 for combining div/mod to eliminate the
3454 ;; mod, prefer putting the result of mod into a different register
3455 (define_insn "*mod<mode>
3"
3456 [(set (match_operand:GPR
0 "gpc_reg_operand" "=&r,r")
3457 (mod:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
3458 (match_operand:GPR
2 "gpc_reg_operand" "r,r")))]
3459 "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
3461 [(set_attr "type" "div")
3462 (set_attr "size" "<bits>")])
3464 ;; This define_expand can be removed when RS6000_DISABLE_SCALAR_MODULO is
3466 (define_expand "umod<mode>
3"
3467 [(set (match_operand:GPR
0 "gpc_reg_operand")
3468 (umod:GPR (match_operand:GPR
1 "gpc_reg_operand")
3469 (match_operand:GPR
2 "gpc_reg_operand")))]
3472 if (RS6000_DISABLE_SCALAR_MODULO)
3474 rtx temp1 = gen_reg_rtx (<MODE>mode);
3475 rtx temp2 = gen_reg_rtx (<MODE>mode);
3477 emit_insn (gen_udiv<mode>
3 (temp1, operands[
1], operands[
2]));
3478 emit_insn (gen_mul<mode>
3 (temp2, temp1, operands[
2]));
3479 emit_insn (gen_sub<mode>
3 (operands[
0], operands[
1], temp2));
3484 (define_insn "*umod<mode>
3"
3485 [(set (match_operand:GPR
0 "gpc_reg_operand" "=&r,r")
3486 (umod:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
3487 (match_operand:GPR
2 "gpc_reg_operand" "r,r")))]
3488 "TARGET_MODULO && !RS6000_DISABLE_SCALAR_MODULO"
3490 [(set_attr "type" "div")
3491 (set_attr "size" "<bits>")])
3493 ;; On machines with modulo support, do a combined div/mod the old fashioned
3494 ;; method, since the multiply/subtract is faster than doing the mod instruction
3498 [(set (match_operand:GPR
0 "gpc_reg_operand")
3499 (div:GPR (match_operand:GPR
1 "gpc_reg_operand")
3500 (match_operand:GPR
2 "gpc_reg_operand")))
3501 (set (match_operand:GPR
3 "gpc_reg_operand")
3502 (mod:GPR (match_dup
1)
3505 && ! reg_mentioned_p (operands[
0], operands[
1])
3506 && ! reg_mentioned_p (operands[
0], operands[
2])
3507 && ! reg_mentioned_p (operands[
3], operands[
1])
3508 && ! reg_mentioned_p (operands[
3], operands[
2])"
3510 (div:GPR (match_dup
1)
3513 (mult:GPR (match_dup
0)
3516 (minus:GPR (match_dup
1)
3520 [(set (match_operand:GPR
0 "gpc_reg_operand")
3521 (udiv:GPR (match_operand:GPR
1 "gpc_reg_operand")
3522 (match_operand:GPR
2 "gpc_reg_operand")))
3523 (set (match_operand:GPR
3 "gpc_reg_operand")
3524 (umod:GPR (match_dup
1)
3527 && ! reg_mentioned_p (operands[
0], operands[
1])
3528 && ! reg_mentioned_p (operands[
0], operands[
2])
3529 && ! reg_mentioned_p (operands[
3], operands[
1])
3530 && ! reg_mentioned_p (operands[
3], operands[
2])"
3532 (udiv:GPR (match_dup
1)
3535 (mult:GPR (match_dup
0)
3538 (minus:GPR (match_dup
1)
3541 (define_insn "umodti3"
3542 [(set (match_operand:TI
0 "altivec_register_operand" "=v")
3543 (umod:TI (match_operand:TI
1 "altivec_register_operand" "v")
3544 (match_operand:TI
2 "altivec_register_operand" "v")))]
3545 "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO"
3547 [(set_attr "type" "vecdiv")
3548 (set_attr "size" "
128")])
3550 (define_insn "modti3"
3551 [(set (match_operand:TI
0 "altivec_register_operand" "=v")
3552 (mod:TI (match_operand:TI
1 "altivec_register_operand" "v")
3553 (match_operand:TI
2 "altivec_register_operand" "v")))]
3554 "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO"
3556 [(set_attr "type" "vecdiv")
3557 (set_attr "size" "
128")])
3559 ;; Logical instructions
3560 ;; The logical instructions are mostly combined by using match_operator,
3561 ;; but the plain AND insns are somewhat different because there is no
3562 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3563 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3565 (define_expand "and<mode>
3"
3566 [(set (match_operand:SDI
0 "gpc_reg_operand")
3567 (and:SDI (match_operand:SDI
1 "gpc_reg_operand")
3568 (match_operand:SDI
2 "reg_or_cint_operand")))]
3571 if (<MODE>mode == DImode && !TARGET_POWERPC64)
3573 rs6000_split_logical (operands, AND, false, false, false);
3577 if (CONST_INT_P (operands[
2]))
3579 if (rs6000_is_valid_and_mask (operands[
2], <MODE>mode))
3581 emit_insn (gen_and<mode>
3_mask (operands[
0], operands[
1], operands[
2]));
3585 if (logical_const_operand (operands[
2], <MODE>mode))
3587 emit_insn (gen_and<mode>
3_imm (operands[
0], operands[
1], operands[
2]));
3591 if (rs6000_is_valid_2insn_and (operands[
2], <MODE>mode))
3593 rs6000_emit_2insn_and (<MODE>mode, operands, true,
0);
3597 operands[
2] = force_reg (<MODE>mode, operands[
2]);
3602 (define_insn "and<mode>
3_imm"
3603 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3604 (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r")
3605 (match_operand:GPR
2 "logical_const_operand" "n")))
3606 (clobber (match_scratch:CC
3 "=x"))]
3607 "!rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3608 "andi%e2. %
0,%
1,%u2"
3609 [(set_attr "type" "logical")
3610 (set_attr "dot" "yes")])
3612 (define_insn_and_split "*and<mode>
3_imm_dot"
3613 [(set (match_operand:CC
3 "cc_reg_operand" "=x,??y")
3614 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3615 (match_operand:GPR
2 "logical_const_operand" "n,n"))
3617 (clobber (match_scratch:GPR
0 "=r,r"))
3618 (clobber (match_scratch:CC
4 "=X,x"))]
3619 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3620 && !rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3624 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3625 [(parallel [(set (match_dup
0)
3626 (and:GPR (match_dup
1)
3628 (clobber (match_dup
4))])
3630 (compare:CC (match_dup
0)
3633 [(set_attr "type" "logical")
3634 (set_attr "dot" "yes")
3635 (set_attr "length" "
4,
8")])
3637 (define_insn_and_split "*and<mode>
3_imm_dot2"
3638 [(set (match_operand:CC
3 "cc_reg_operand" "=x,??y")
3639 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3640 (match_operand:GPR
2 "logical_const_operand" "n,n"))
3642 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
3643 (and:GPR (match_dup
1)
3645 (clobber (match_scratch:CC
4 "=X,x"))]
3646 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3647 && !rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3651 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3652 [(parallel [(set (match_dup
0)
3653 (and:GPR (match_dup
1)
3655 (clobber (match_dup
4))])
3657 (compare:CC (match_dup
0)
3660 [(set_attr "type" "logical")
3661 (set_attr "dot" "yes")
3662 (set_attr "length" "
4,
8")])
3664 (define_insn_and_split "*and<mode>
3_imm_mask_dot"
3665 [(set (match_operand:CC
3 "cc_reg_operand" "=x,??y")
3666 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3667 (match_operand:GPR
2 "logical_const_operand" "n,n"))
3669 (clobber (match_scratch:GPR
0 "=r,r"))]
3670 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3671 && rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3675 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3677 (and:GPR (match_dup
1)
3680 (compare:CC (match_dup
0)
3683 [(set_attr "type" "logical")
3684 (set_attr "dot" "yes")
3685 (set_attr "length" "
4,
8")])
3687 (define_insn_and_split "*and<mode>
3_imm_mask_dot2"
3688 [(set (match_operand:CC
3 "cc_reg_operand" "=x,??y")
3689 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3690 (match_operand:GPR
2 "logical_const_operand" "n,n"))
3692 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
3693 (and:GPR (match_dup
1)
3695 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3696 && rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3700 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3702 (and:GPR (match_dup
1)
3705 (compare:CC (match_dup
0)
3708 [(set_attr "type" "logical")
3709 (set_attr "dot" "yes")
3710 (set_attr "length" "
4,
8")])
3712 (define_insn "*and<mode>
3_imm_dot_shifted"
3713 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
3716 (lshiftrt:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r")
3717 (match_operand:SI
4 "const_int_operand" "n"))
3718 (match_operand:GPR
2 "const_int_operand" "n"))
3720 (clobber (match_scratch:GPR
0 "=r"))]
3721 "logical_const_operand (GEN_INT (UINTVAL (operands[
2])
3722 << INTVAL (operands[
4])),
3724 && (<MODE>mode == Pmode
3725 || (UINTVAL (operands[
2]) << INTVAL (operands[
4])) <=
0x7fffffff)"
3727 operands[
2] = GEN_INT (UINTVAL (operands[
2]) << INTVAL (operands[
4]));
3728 return "andi%e2. %
0,%
1,%u2";
3730 [(set_attr "type" "logical")
3731 (set_attr "dot" "yes")])
3734 (define_insn "and<mode>
3_mask"
3735 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3736 (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r")
3737 (match_operand:GPR
2 "const_int_operand" "n")))]
3738 "rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3740 return rs6000_insn_for_and_mask (<MODE>mode, operands, false);
3742 [(set_attr "type" "shift")])
3744 (define_insn_and_split "*and<mode>
3_mask_dot"
3745 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3746 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3747 (match_operand:GPR
2 "const_int_operand" "n,n"))
3749 (clobber (match_scratch:GPR
0 "=r,r"))]
3750 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3751 && !logical_const_operand (operands[
2], <MODE>mode)
3752 && rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3754 if (which_alternative ==
0)
3755 return rs6000_insn_for_and_mask (<MODE>mode, operands, true);
3759 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3761 (and:GPR (match_dup
1)
3764 (compare:CC (match_dup
0)
3767 [(set_attr "type" "shift")
3768 (set_attr "dot" "yes")
3769 (set_attr "length" "
4,
8")])
3771 (define_insn_and_split "*and<mode>
3_mask_dot2"
3772 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3773 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3774 (match_operand:GPR
2 "const_int_operand" "n,n"))
3776 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
3777 (and:GPR (match_dup
1)
3779 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3780 && !logical_const_operand (operands[
2], <MODE>mode)
3781 && rs6000_is_valid_and_mask (operands[
2], <MODE>mode)"
3783 if (which_alternative ==
0)
3784 return rs6000_insn_for_and_mask (<MODE>mode, operands, true);
3788 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
3790 (and:GPR (match_dup
1)
3793 (compare:CC (match_dup
0)
3796 [(set_attr "type" "shift")
3797 (set_attr "dot" "yes")
3798 (set_attr "length" "
4,
8")])
3801 (define_insn_and_split "*and<mode>
3_2insn"
3802 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3803 (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r")
3804 (match_operand:GPR
2 "const_int_operand" "n")))]
3805 "rs6000_is_valid_2insn_and (operands[
2], <MODE>mode)
3806 && !(rs6000_is_valid_and_mask (operands[
2], <MODE>mode)
3807 || logical_const_operand (operands[
2], <MODE>mode))"
3812 rs6000_emit_2insn_and (<MODE>mode, operands, false,
0);
3815 [(set_attr "type" "shift")
3816 (set_attr "length" "
8")])
3818 (define_insn_and_split "*and<mode>
3_2insn_dot"
3819 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3820 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3821 (match_operand:GPR
2 "const_int_operand" "n,n"))
3823 (clobber (match_scratch:GPR
0 "=r,r"))]
3824 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3825 && rs6000_is_valid_2insn_and (operands[
2], <MODE>mode)
3826 && !(rs6000_is_valid_and_mask (operands[
2], <MODE>mode)
3827 || logical_const_operand (operands[
2], <MODE>mode))"
3829 "&& reload_completed"
3832 rs6000_emit_2insn_and (<MODE>mode, operands, false,
1);
3835 [(set_attr "type" "shift")
3836 (set_attr "dot" "yes")
3837 (set_attr "length" "
8,
12")])
3839 (define_insn_and_split "*and<mode>
3_2insn_dot2"
3840 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
3841 (compare:CC (and:GPR (match_operand:GPR
1 "gpc_reg_operand" "%r,r")
3842 (match_operand:GPR
2 "const_int_operand" "n,n"))
3844 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
3845 (and:GPR (match_dup
1)
3847 "(<MODE>mode == Pmode || UINTVAL (operands[
2]) <=
0x7fffffff)
3848 && rs6000_is_valid_2insn_and (operands[
2], <MODE>mode)
3849 && !(rs6000_is_valid_and_mask (operands[
2], <MODE>mode)
3850 || logical_const_operand (operands[
2], <MODE>mode))"
3852 "&& reload_completed"
3855 rs6000_emit_2insn_and (<MODE>mode, operands, false,
2);
3858 [(set_attr "type" "shift")
3859 (set_attr "dot" "yes")
3860 (set_attr "length" "
8,
12")])
3862 (define_insn_and_split "*branch_anddi3_dot"
3864 (if_then_else (eq (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
3865 (match_operand:DI
2 "const_int_operand" "n,n"))
3867 (label_ref (match_operand
3 ""))
3869 (clobber (match_scratch:DI
0 "=r,r"))
3870 (clobber (reg:CC CR0_REGNO))]
3871 "rs6000_is_valid_rotate_dot_mask (operands[
2], DImode)
3872 && TARGET_POWERPC64"
3874 "&& reload_completed"
3878 if (rs6000_is_valid_mask (operands[
2], &nb, &ne, DImode)
3882 unsigned HOST_WIDE_INT val = INTVAL (operands[
2]);
3883 int shift =
63 - nb;
3884 rtx tmp = gen_rtx_ASHIFT (DImode, operands[
1], GEN_INT (shift));
3885 tmp = gen_rtx_AND (DImode, tmp, GEN_INT (val << shift));
3886 rtx cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
3887 rs6000_emit_dot_insn (operands[
0], tmp,
1, cr0);
3888 rtx loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[
3]);
3889 rtx cond = gen_rtx_EQ (CCEQmode, cr0, const0_rtx);
3890 rtx ite = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, loc_ref, pc_rtx);
3891 emit_jump_insn (gen_rtx_SET (pc_rtx, ite));
3897 [(set_attr "type" "shift")
3898 (set_attr "dot" "yes")
3899 (set_attr "length" "
8,
12")])
3901 (define_expand "<code><mode>
3"
3902 [(set (match_operand:SDI
0 "gpc_reg_operand")
3903 (iorxor:SDI (match_operand:SDI
1 "gpc_reg_operand")
3904 (match_operand:SDI
2 "reg_or_cint_operand")))]
3907 if (<MODE>mode == DImode && !TARGET_POWERPC64)
3909 rs6000_split_logical (operands, <CODE>, false, false, false);
3913 if (non_logical_cint_operand (operands[
2], <MODE>mode))
3915 rtx tmp = ((!can_create_pseudo_p ()
3916 || rtx_equal_p (operands[
0], operands[
1]))
3917 ? operands[
0] : gen_reg_rtx (<MODE>mode));
3919 HOST_WIDE_INT value = INTVAL (operands[
2]);
3920 HOST_WIDE_INT lo = value &
0xffff;
3921 HOST_WIDE_INT hi = value - lo;
3923 emit_insn (gen_<code><mode>
3 (tmp, operands[
1], GEN_INT (hi)));
3924 emit_insn (gen_<code><mode>
3 (operands[
0], tmp, GEN_INT (lo)));
3928 if (!reg_or_logical_cint_operand (operands[
2], <MODE>mode))
3929 operands[
2] = force_reg (<MODE>mode, operands[
2]);
3933 [(set (match_operand:GPR
0 "gpc_reg_operand")
3934 (iorxor:GPR (match_operand:GPR
1 "gpc_reg_operand")
3935 (match_operand:GPR
2 "non_logical_cint_operand")))]
3938 (iorxor:GPR (match_dup
1)
3941 (iorxor:GPR (match_dup
3)
3944 operands[
3] = ((!can_create_pseudo_p ()
3945 || rtx_equal_p (operands[
0], operands[
1]))
3946 ? operands[
0] : gen_reg_rtx (<MODE>mode));
3948 HOST_WIDE_INT value = INTVAL (operands[
2]);
3949 HOST_WIDE_INT lo = value &
0xffff;
3950 HOST_WIDE_INT hi = value - lo;
3952 operands[
4] = GEN_INT (hi);
3953 operands[
5] = GEN_INT (lo);
3956 (define_insn "*bool<mode>
3_imm"
3957 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3958 (match_operator:GPR
3 "boolean_or_operator"
3959 [(match_operand:GPR
1 "gpc_reg_operand" "%r")
3960 (match_operand:GPR
2 "logical_const_operand" "n")]))]
3963 [(set_attr "type" "logical")])
3965 (define_insn "*bool<mode>
3"
3966 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
3967 (match_operator:GPR
3 "boolean_operator"
3968 [(match_operand:GPR
1 "gpc_reg_operand" "r")
3969 (match_operand:GPR
2 "gpc_reg_operand" "r")]))]
3972 [(set_attr "type" "logical")])
3974 (define_insn_and_split "*bool<mode>
3_dot"
3975 [(set (match_operand:CC
4 "cc_reg_operand" "=x,?y")
3976 (compare:CC (match_operator:GPR
3 "boolean_operator"
3977 [(match_operand:GPR
1 "gpc_reg_operand" "r,r")
3978 (match_operand:GPR
2 "gpc_reg_operand" "r,r")])
3980 (clobber (match_scratch:GPR
0 "=r,r"))]
3981 "<MODE>mode == Pmode"
3985 "&& reload_completed && cc_reg_not_cr0_operand (operands[
4], CCmode)"
3989 (compare:CC (match_dup
0)
3992 [(set_attr "type" "logical")
3993 (set_attr "dot" "yes")
3994 (set_attr "length" "
4,
8")])
3996 (define_insn_and_split "*bool<mode>
3_dot2"
3997 [(set (match_operand:CC
4 "cc_reg_operand" "=x,?y")
3998 (compare:CC (match_operator:GPR
3 "boolean_operator"
3999 [(match_operand:GPR
1 "gpc_reg_operand" "r,r")
4000 (match_operand:GPR
2 "gpc_reg_operand" "r,r")])
4002 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4004 "<MODE>mode == Pmode"
4008 "&& reload_completed && cc_reg_not_cr0_operand (operands[
4], CCmode)"
4012 (compare:CC (match_dup
0)
4015 [(set_attr "type" "logical")
4016 (set_attr "dot" "yes")
4017 (set_attr "length" "
4,
8")])
4020 (define_insn "*boolc<mode>
3"
4021 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4022 (match_operator:GPR
3 "boolean_operator"
4023 [(not:GPR (match_operand:GPR
2 "gpc_reg_operand" "r"))
4024 (match_operand:GPR
1 "gpc_reg_operand" "r")]))]
4027 [(set_attr "type" "logical")])
4029 (define_insn_and_split "*boolc<mode>
3_dot"
4030 [(set (match_operand:CC
4 "cc_reg_operand" "=x,?y")
4031 (compare:CC (match_operator:GPR
3 "boolean_operator"
4032 [(not:GPR (match_operand:GPR
2 "gpc_reg_operand" "r,r"))
4033 (match_operand:GPR
1 "gpc_reg_operand" "r,r")])
4035 (clobber (match_scratch:GPR
0 "=r,r"))]
4036 "<MODE>mode == Pmode"
4040 "&& reload_completed && cc_reg_not_cr0_operand (operands[
4], CCmode)"
4044 (compare:CC (match_dup
0)
4047 [(set_attr "type" "logical")
4048 (set_attr "dot" "yes")
4049 (set_attr "length" "
4,
8")])
4051 (define_insn_and_split "*boolc<mode>
3_dot2"
4052 [(set (match_operand:CC
4 "cc_reg_operand" "=x,?y")
4053 (compare:CC (match_operator:GPR
3 "boolean_operator"
4054 [(not:GPR (match_operand:GPR
2 "gpc_reg_operand" "r,r"))
4055 (match_operand:GPR
1 "gpc_reg_operand" "r,r")])
4057 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4059 "<MODE>mode == Pmode"
4063 "&& reload_completed && cc_reg_not_cr0_operand (operands[
4], CCmode)"
4067 (compare:CC (match_dup
0)
4070 [(set_attr "type" "logical")
4071 (set_attr "dot" "yes")
4072 (set_attr "length" "
4,
8")])
4075 (define_insn "*boolcc<mode>
3"
4076 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4077 (match_operator:GPR
3 "boolean_operator"
4078 [(not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r"))
4079 (not:GPR (match_operand:GPR
2 "gpc_reg_operand" "r"))]))]
4082 [(set_attr "type" "logical")])
4084 (define_insn_and_split "*boolcc<mode>
3_dot"
4085 [(set (match_operand:CC
4 "cc_reg_operand" "=x,?y")
4086 (compare:CC (match_operator:GPR
3 "boolean_operator"
4087 [(not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
4088 (not:GPR (match_operand:GPR
2 "gpc_reg_operand" "r,r"))])
4090 (clobber (match_scratch:GPR
0 "=r,r"))]
4091 "<MODE>mode == Pmode"
4095 "&& reload_completed && cc_reg_not_cr0_operand (operands[
4], CCmode)"
4099 (compare:CC (match_dup
0)
4102 [(set_attr "type" "logical")
4103 (set_attr "dot" "yes")
4104 (set_attr "length" "
4,
8")])
4106 (define_insn_and_split "*boolcc<mode>
3_dot2"
4107 [(set (match_operand:CC
4 "cc_reg_operand" "=x,?y")
4108 (compare:CC (match_operator:GPR
3 "boolean_operator"
4109 [(not:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r"))
4110 (not:GPR (match_operand:GPR
2 "gpc_reg_operand" "r,r"))])
4112 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4114 "<MODE>mode == Pmode"
4118 "&& reload_completed && cc_reg_not_cr0_operand (operands[
4], CCmode)"
4122 (compare:CC (match_dup
0)
4125 [(set_attr "type" "logical")
4126 (set_attr "dot" "yes")
4127 (set_attr "length" "
4,
8")])
4130 ;; TODO: Should have dots of this as well.
4131 (define_insn "*eqv<mode>
3"
4132 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4133 (not:GPR (xor:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
4134 (match_operand:GPR
2 "gpc_reg_operand" "r"))))]
4137 [(set_attr "type" "logical")])
4139 ;; Rotate-and-mask and insert.
4141 (define_insn "*rotl<mode>
3_mask"
4142 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4143 (and:GPR (match_operator:GPR
4 "rotate_mask_operator"
4144 [(match_operand:GPR
1 "gpc_reg_operand" "r")
4145 (match_operand:SI
2 "reg_or_cint_operand" "rn")])
4146 (match_operand:GPR
3 "const_int_operand" "n")))]
4147 "rs6000_is_valid_shift_mask (operands[
3], operands[
4], <MODE>mode)"
4149 return rs6000_insn_for_shift_mask (<MODE>mode, operands, false);
4151 [(set_attr "type" "shift")
4152 (set_attr "maybe_var_shift" "yes")])
4154 (define_insn_and_split "*rotl<mode>
3_mask_dot"
4155 [(set (match_operand:CC
5 "cc_reg_operand" "=x,?y")
4157 (and:GPR (match_operator:GPR
4 "rotate_mask_operator"
4158 [(match_operand:GPR
1 "gpc_reg_operand" "r,r")
4159 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn")])
4160 (match_operand:GPR
3 "const_int_operand" "n,n"))
4162 (clobber (match_scratch:GPR
0 "=r,r"))]
4163 "(<MODE>mode == Pmode || UINTVAL (operands[
3]) <=
0x7fffffff)
4164 && rs6000_is_valid_shift_mask (operands[
3], operands[
4], <MODE>mode)"
4166 if (which_alternative ==
0)
4167 return rs6000_insn_for_shift_mask (<MODE>mode, operands, true);
4171 "&& reload_completed && cc_reg_not_cr0_operand (operands[
5], CCmode)"
4173 (and:GPR (match_dup
4)
4176 (compare:CC (match_dup
0)
4179 [(set_attr "type" "shift")
4180 (set_attr "maybe_var_shift" "yes")
4181 (set_attr "dot" "yes")
4182 (set_attr "length" "
4,
8")])
4184 (define_insn_and_split "*rotl<mode>
3_mask_dot2"
4185 [(set (match_operand:CC
5 "cc_reg_operand" "=x,?y")
4187 (and:GPR (match_operator:GPR
4 "rotate_mask_operator"
4188 [(match_operand:GPR
1 "gpc_reg_operand" "r,r")
4189 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn")])
4190 (match_operand:GPR
3 "const_int_operand" "n,n"))
4192 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4193 (and:GPR (match_dup
4)
4195 "(<MODE>mode == Pmode || UINTVAL (operands[
3]) <=
0x7fffffff)
4196 && rs6000_is_valid_shift_mask (operands[
3], operands[
4], <MODE>mode)"
4198 if (which_alternative ==
0)
4199 return rs6000_insn_for_shift_mask (<MODE>mode, operands, true);
4203 "&& reload_completed && cc_reg_not_cr0_operand (operands[
5], CCmode)"
4205 (and:GPR (match_dup
4)
4208 (compare:CC (match_dup
0)
4211 [(set_attr "type" "shift")
4212 (set_attr "maybe_var_shift" "yes")
4213 (set_attr "dot" "yes")
4214 (set_attr "length" "
4,
8")])
4216 ; Special case for less-than-
0. We can do it with just one machine
4217 ; instruction, but the generic optimizers do not realise it is cheap.
4218 (define_insn "*lt0_<mode>di"
4219 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4220 (lt:GPR (match_operand:DI
1 "gpc_reg_operand" "r")
4224 [(set_attr "type" "shift")])
4226 (define_insn "*lt0_<mode>si"
4227 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4228 (lt:GPR (match_operand:SI
1 "gpc_reg_operand" "r")
4231 "rlwinm %
0,%
1,
1,
31,
31"
4232 [(set_attr "type" "shift")])
4236 ; Two forms for insert (the two arms of the IOR are not canonicalized,
4237 ; both are an AND so are the same precedence).
4238 (define_insn "*rotl<mode>
3_insert"
4239 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4240 (ior:GPR (and:GPR (match_operator:GPR
4 "rotate_mask_operator"
4241 [(match_operand:GPR
1 "gpc_reg_operand" "r")
4242 (match_operand:SI
2 "const_int_operand" "n")])
4243 (match_operand:GPR
3 "const_int_operand" "n"))
4244 (and:GPR (match_operand:GPR
5 "gpc_reg_operand" "
0")
4245 (match_operand:GPR
6 "const_int_operand" "n"))))]
4246 "rs6000_is_valid_insert_mask (operands[
3], operands[
4], <MODE>mode)
4247 && UINTVAL (operands[
3]) + UINTVAL (operands[
6]) +
1 ==
0"
4249 return rs6000_insn_for_insert_mask (<MODE>mode, operands, false);
4251 [(set_attr "type" "insert")])
4252 ; FIXME: this needs an attr "size", so that the scheduler can see the
4253 ; difference between rlwimi and rldimi. We also might want dot forms,
4254 ; but not for rlwimi on POWER4 and similar processors.
4256 (define_insn "*rotl<mode>
3_insert_2"
4257 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4258 (ior:GPR (and:GPR (match_operand:GPR
5 "gpc_reg_operand" "
0")
4259 (match_operand:GPR
6 "const_int_operand" "n"))
4260 (and:GPR (match_operator:GPR
4 "rotate_mask_operator"
4261 [(match_operand:GPR
1 "gpc_reg_operand" "r")
4262 (match_operand:SI
2 "const_int_operand" "n")])
4263 (match_operand:GPR
3 "const_int_operand" "n"))))]
4264 "rs6000_is_valid_insert_mask (operands[
3], operands[
4], <MODE>mode)
4265 && UINTVAL (operands[
3]) + UINTVAL (operands[
6]) +
1 ==
0"
4267 return rs6000_insn_for_insert_mask (<MODE>mode, operands, false);
4269 [(set_attr "type" "insert")])
4271 ; There are also some forms without one of the ANDs.
4272 (define_insn "rotl<mode>
3_insert_3"
4273 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4274 (ior:GPR (and:GPR (match_operand:GPR
3 "gpc_reg_operand" "
0")
4275 (match_operand:GPR
4 "const_int_operand" "n"))
4276 (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
4277 (match_operand:SI
2 "const_int_operand" "n"))))]
4278 "INTVAL (operands[
2]) >
0
4279 && INTVAL (operands[
2]) == exact_log2 (UINTVAL (operands[
4]) +
1)"
4281 if (<MODE>mode == SImode)
4282 return "rlwimi %
0,%
1,%h2,
0,
31-%h2";
4284 return "rldimi %
0,%
1,%H2,
0";
4286 [(set_attr "type" "insert")])
4288 ; Canonicalize the PLUS and XOR forms to IOR for rotl<mode>
3_insert_3
4289 (define_code_iterator plus_xor [plus xor])
4291 (define_insn_and_split "*rotl<mode>
3_insert_3_<code>"
4292 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4294 (and:GPR (match_operand:GPR
3 "gpc_reg_operand" "
0")
4295 (match_operand:GPR
4 "const_int_operand" "n"))
4296 (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
4297 (match_operand:SI
2 "const_int_operand" "n"))))]
4298 "INTVAL (operands[
2]) >
0
4299 && INTVAL (operands[
2]) == exact_log2 (UINTVAL (operands[
4]) +
1)"
4303 (ior:GPR (and:GPR (match_dup
3) (match_dup
4))
4304 (ashift:GPR (match_dup
1) (match_dup
2))))])
4306 (define_code_iterator plus_ior_xor [plus ior xor])
4309 [(set (match_operand:GPR
0 "gpc_reg_operand")
4310 (plus_ior_xor:GPR (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand")
4311 (match_operand:SI
2 "const_int_operand"))
4312 (match_operand:GPR
3 "gpc_reg_operand")))]
4313 "nonzero_bits (operands[
3], <MODE>mode)
4314 < HOST_WIDE_INT_1U << INTVAL (operands[
2])"
4316 (ior:GPR (and:GPR (match_dup
3)
4318 (ashift:GPR (match_dup
1)
4321 operands[
4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[
2])) -
1);
4324 (define_insn "*rotlsi3_insert_4"
4325 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4326 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "
0")
4327 (match_operand:SI
4 "const_int_operand" "n"))
4328 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4329 (match_operand:SI
2 "const_int_operand" "n"))))]
4330 "INTVAL (operands[
2]) + exact_log2 (-UINTVAL (operands[
4])) ==
32"
4331 "rlwimi %
0,%
1,
32-%h2,%h2,
31"
4332 [(set_attr "type" "insert")])
4334 (define_insn "*rotlsi3_insert_5"
4335 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4336 (ior:SI (and:SI (match_operand:SI
1 "gpc_reg_operand" "
0,r")
4337 (match_operand:SI
2 "const_int_operand" "n,n"))
4338 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r,
0")
4339 (match_operand:SI
4 "const_int_operand" "n,n"))))]
4340 "rs6000_is_valid_mask (operands[
2], NULL, NULL, SImode)
4341 && UINTVAL (operands[
2]) !=
0 && UINTVAL (operands[
4]) !=
0
4342 && UINTVAL (operands[
2]) + UINTVAL (operands[
4]) +
1 ==
0"
4346 [(set_attr "type" "insert")])
4348 (define_insn "*rotldi3_insert_6"
4349 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4350 (ior:DI (and:DI (match_operand:DI
1 "gpc_reg_operand" "
0")
4351 (match_operand:DI
2 "const_int_operand" "n"))
4352 (and:DI (match_operand:DI
3 "gpc_reg_operand" "r")
4353 (match_operand:DI
4 "const_int_operand" "n"))))]
4354 "exact_log2 (-UINTVAL (operands[
2])) >
0
4355 && UINTVAL (operands[
2]) + UINTVAL (operands[
4]) +
1 ==
0"
4357 operands[
5] = GEN_INT (
64 - exact_log2 (-UINTVAL (operands[
2])));
4358 return "rldimi %
0,%
3,
0,%
5";
4360 [(set_attr "type" "insert")
4361 (set_attr "size" "
64")])
4363 (define_insn "*rotldi3_insert_7"
4364 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4365 (ior:DI (and:DI (match_operand:DI
3 "gpc_reg_operand" "r")
4366 (match_operand:DI
4 "const_int_operand" "n"))
4367 (and:DI (match_operand:DI
1 "gpc_reg_operand" "
0")
4368 (match_operand:DI
2 "const_int_operand" "n"))))]
4369 "exact_log2 (-UINTVAL (operands[
2])) >
0
4370 && UINTVAL (operands[
2]) + UINTVAL (operands[
4]) +
1 ==
0"
4372 operands[
5] = GEN_INT (
64 - exact_log2 (-UINTVAL (operands[
2])));
4373 return "rldimi %
0,%
3,
0,%
5";
4375 [(set_attr "type" "insert")
4376 (set_attr "size" "
64")])
4379 ; This handles the important case of multiple-precision shifts. There is
4380 ; no canonicalization rule for ASHIFT vs. LSHIFTRT, so two patterns.
4382 [(set (match_operand:GPR
0 "gpc_reg_operand")
4383 (ior:GPR (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand")
4384 (match_operand:SI
3 "const_int_operand"))
4385 (lshiftrt:GPR (match_operand:GPR
2 "gpc_reg_operand")
4386 (match_operand:SI
4 "const_int_operand"))))]
4387 "can_create_pseudo_p ()
4388 && INTVAL (operands[
3]) + INTVAL (operands[
4])
4389 >= GET_MODE_PRECISION (<MODE>mode)"
4391 (lshiftrt:GPR (match_dup
2)
4394 (ior:GPR (and:GPR (match_dup
5)
4396 (ashift:GPR (match_dup
1)
4399 unsigned HOST_WIDE_INT mask =
1;
4400 mask = (mask << INTVAL (operands[
3])) -
1;
4401 operands[
5] = gen_reg_rtx (<MODE>mode);
4402 operands[
6] = GEN_INT (mask);
4406 [(set (match_operand:GPR
0 "gpc_reg_operand")
4407 (ior:GPR (lshiftrt:GPR (match_operand:GPR
2 "gpc_reg_operand")
4408 (match_operand:SI
4 "const_int_operand"))
4409 (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand")
4410 (match_operand:SI
3 "const_int_operand"))))]
4411 "can_create_pseudo_p ()
4412 && INTVAL (operands[
3]) + INTVAL (operands[
4])
4413 >= GET_MODE_PRECISION (<MODE>mode)"
4415 (lshiftrt:GPR (match_dup
2)
4418 (ior:GPR (and:GPR (match_dup
5)
4420 (ashift:GPR (match_dup
1)
4423 unsigned HOST_WIDE_INT mask =
1;
4424 mask = (mask << INTVAL (operands[
3])) -
1;
4425 operands[
5] = gen_reg_rtx (<MODE>mode);
4426 operands[
6] = GEN_INT (mask);
4430 ; Another important case is setting some bits to
1; we can do that with
4431 ; an insert instruction, in many cases.
4432 (define_insn_and_split "*ior<mode>_mask"
4433 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4434 (ior:GPR (match_operand:GPR
1 "gpc_reg_operand" "
0")
4435 (match_operand:GPR
2 "const_int_operand" "n")))
4436 (clobber (match_scratch:GPR
3 "=r"))]
4437 "!logical_const_operand (operands[
2], <MODE>mode)
4438 && rs6000_is_valid_mask (operands[
2], NULL, NULL, <MODE>mode)"
4444 (ior:GPR (and:GPR (rotate:GPR (match_dup
3)
4447 (and:GPR (match_dup
1)
4451 rs6000_is_valid_mask (operands[
2], &nb, &ne, <MODE>mode);
4452 if (GET_CODE (operands[
3]) == SCRATCH)
4453 operands[
3] = gen_reg_rtx (<MODE>mode);
4454 operands[
4] = GEN_INT (ne);
4455 operands[
5] = GEN_INT (~UINTVAL (operands[
2]));
4457 [(set_attr "type" "two")
4458 (set_attr "length" "
8")])
4461 ; Yet another case is an rldimi with the second value coming from memory.
4462 ; The zero_extend that should become part of the rldimi is merged into the
4463 ; load from memory instead. Split things properly again.
4465 [(set (match_operand:DI
0 "gpc_reg_operand")
4466 (ior:DI (ashift:DI (match_operand:DI
1 "gpc_reg_operand")
4467 (match_operand:SI
2 "const_int_operand"))
4468 (zero_extend:DI (match_operand:QHSI
3 "memory_operand"))))]
4469 "INTVAL (operands[
2]) == <bits>"
4471 (zero_extend:DI (match_dup
3)))
4473 (ior:DI (and:DI (match_dup
4)
4475 (ashift:DI (match_dup
1)
4478 operands[
4] = gen_reg_rtx (DImode);
4479 operands[
5] = GEN_INT ((HOST_WIDE_INT_1U << <bits>) -
1);
4482 ; rldimi with UNSPEC_SI_FROM_SF.
4483 (define_insn_and_split "*rotldi3_insert_sf"
4484 [(set (match_operand:DI
0 "gpc_reg_operand")
4486 (ashift:DI (match_operand:DI
1 "gpc_reg_operand")
4487 (match_operand:SI
2 "const_int_operand"))
4490 [(match_operand:SF
3 "memory_operand")]
4491 UNSPEC_SI_FROM_SF))))
4492 (clobber (match_scratch:V4SF
4))]
4493 "TARGET_POWERPC64 && INTVAL (operands[
2]) == <bits>"
4496 [(parallel [(set (match_dup
5)
4497 (zero_extend:DI (unspec:QHSI [(match_dup
3)] UNSPEC_SI_FROM_SF)))
4498 (clobber (match_dup
4))])
4501 (and:DI (match_dup
5) (match_dup
6))
4502 (ashift:DI (match_dup
1) (match_dup
2))))]
4504 operands[
5] = gen_reg_rtx (DImode);
4505 operands[
6] = GEN_INT ((HOST_WIDE_INT_1U << <bits>) -
1);
4510 [(set (match_operand:SI
0 "gpc_reg_operand")
4511 (ior:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand")
4512 (match_operand:SI
2 "const_int_operand"))
4513 (zero_extend:SI (match_operand:QHI
3 "memory_operand"))))]
4514 "INTVAL (operands[
2]) == <bits>"
4516 (zero_extend:SI (match_dup
3)))
4518 (ior:SI (and:SI (match_dup
4)
4520 (ashift:SI (match_dup
1)
4523 operands[
4] = gen_reg_rtx (SImode);
4524 operands[
5] = GEN_INT ((HOST_WIDE_INT_1U << <bits>) -
1);
4528 ;; Now the simple shifts.
4530 (define_insn "rotl<mode>
3"
4531 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4532 (rotate:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
4533 (match_operand:SI
2 "reg_or_cint_operand" "rn")))]
4535 "rotl<wd>%I2 %
0,%
1,%<hH>
2"
4536 [(set_attr "type" "shift")
4537 (set_attr "maybe_var_shift" "yes")])
4539 (define_insn "*rotlsi3_64"
4540 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4542 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4543 (match_operand:SI
2 "reg_or_cint_operand" "rn"))))]
4545 "rotlw%I2 %
0,%
1,%h2"
4546 [(set_attr "type" "shift")
4547 (set_attr "maybe_var_shift" "yes")])
4549 (define_insn_and_split "*rotl<mode>
3_dot"
4550 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4551 (compare:CC (rotate:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4552 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4554 (clobber (match_scratch:GPR
0 "=r,r"))]
4555 "<MODE>mode == Pmode"
4557 rotl<wd>%I2. %
0,%
1,%<hH>
2
4559 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4561 (rotate:GPR (match_dup
1)
4564 (compare:CC (match_dup
0)
4567 [(set_attr "type" "shift")
4568 (set_attr "maybe_var_shift" "yes")
4569 (set_attr "dot" "yes")
4570 (set_attr "length" "
4,
8")])
4572 (define_insn_and_split "*rotl<mode>
3_dot2"
4573 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4574 (compare:CC (rotate:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4575 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4577 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4578 (rotate:GPR (match_dup
1)
4580 "<MODE>mode == Pmode"
4582 rotl<wd>%I2. %
0,%
1,%<hH>
2
4584 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4586 (rotate:GPR (match_dup
1)
4589 (compare:CC (match_dup
0)
4592 [(set_attr "type" "shift")
4593 (set_attr "maybe_var_shift" "yes")
4594 (set_attr "dot" "yes")
4595 (set_attr "length" "
4,
8")])
4598 (define_insn "ashl<mode>
3"
4599 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4600 (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
4601 (match_operand:SI
2 "reg_or_cint_operand" "rn")))]
4603 "sl<wd>%I2 %
0,%
1,%<hH>
2"
4604 [(set_attr "type" "shift")
4605 (set_attr "maybe_var_shift" "yes")])
4607 (define_insn "*ashlsi3_64"
4608 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4610 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4611 (match_operand:SI
2 "reg_or_cint_operand" "rn"))))]
4614 [(set_attr "type" "shift")
4615 (set_attr "maybe_var_shift" "yes")])
4617 (define_insn_and_split "*ashl<mode>
3_dot"
4618 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4619 (compare:CC (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4620 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4622 (clobber (match_scratch:GPR
0 "=r,r"))]
4623 "<MODE>mode == Pmode"
4625 sl<wd>%I2. %
0,%
1,%<hH>
2
4627 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4629 (ashift:GPR (match_dup
1)
4632 (compare:CC (match_dup
0)
4635 [(set_attr "type" "shift")
4636 (set_attr "maybe_var_shift" "yes")
4637 (set_attr "dot" "yes")
4638 (set_attr "length" "
4,
8")])
4640 (define_insn_and_split "*ashl<mode>
3_dot2"
4641 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4642 (compare:CC (ashift:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4643 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4645 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4646 (ashift:GPR (match_dup
1)
4648 "<MODE>mode == Pmode"
4650 sl<wd>%I2. %
0,%
1,%<hH>
2
4652 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4654 (ashift:GPR (match_dup
1)
4657 (compare:CC (match_dup
0)
4660 [(set_attr "type" "shift")
4661 (set_attr "maybe_var_shift" "yes")
4662 (set_attr "dot" "yes")
4663 (set_attr "length" "
4,
8")])
4665 ;; Pretend we have a memory form of extswsli until register allocation is done
4666 ;; so that we use LWZ to load the value from memory, instead of LWA.
4667 (define_insn_and_split "ashdi3_extswsli"
4668 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4670 (sign_extend:DI (match_operand:SI
1 "reg_or_mem_operand" "r,m"))
4671 (match_operand:DI
2 "u6bit_cint_operand" "n,n")))]
4676 "&& reload_completed && MEM_P (operands[
1])"
4680 (ashift:DI (sign_extend:DI (match_dup
3))
4683 operands[
3] = gen_lowpart (SImode, operands[
0]);
4685 [(set_attr "type" "shift")
4686 (set_attr "maybe_var_shift" "no")])
4689 (define_insn_and_split "ashdi3_extswsli_dot"
4690 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y,?x,??y")
4693 (sign_extend:DI (match_operand:SI
1 "reg_or_mem_operand" "r,r,m,m"))
4694 (match_operand:DI
2 "u6bit_cint_operand" "n,n,n,n"))
4696 (clobber (match_scratch:DI
0 "=r,r,r,r"))]
4703 "&& reload_completed
4704 && (cc_reg_not_cr0_operand (operands[
3], CCmode)
4705 || memory_operand (operands[
1], SImode))"
4708 rtx dest = operands[
0];
4709 rtx src = operands[
1];
4710 rtx shift = operands[
2];
4711 rtx cr = operands[
3];
4718 src2 = gen_lowpart (SImode, dest);
4719 emit_move_insn (src2, src);
4722 if (REGNO (cr) == CR0_REGNO)
4724 emit_insn (gen_ashdi3_extswsli_dot2 (dest, src2, shift, cr));
4728 emit_insn (gen_ashdi3_extswsli (dest, src2, shift));
4729 emit_insn (gen_rtx_SET (cr, gen_rtx_COMPARE (CCmode, dest, const0_rtx)));
4732 [(set_attr "type" "shift")
4733 (set_attr "maybe_var_shift" "no")
4734 (set_attr "dot" "yes")
4735 (set_attr "length" "
4,
8,
8,
12")])
4737 (define_insn_and_split "ashdi3_extswsli_dot2"
4738 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y,?x,??y")
4741 (sign_extend:DI (match_operand:SI
1 "reg_or_mem_operand" "r,r,m,m"))
4742 (match_operand:DI
2 "u6bit_cint_operand" "n,n,n,n"))
4744 (set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r,r")
4745 (ashift:DI (sign_extend:DI (match_dup
1))
4753 "&& reload_completed
4754 && (cc_reg_not_cr0_operand (operands[
3], CCmode)
4755 || memory_operand (operands[
1], SImode))"
4758 rtx dest = operands[
0];
4759 rtx src = operands[
1];
4760 rtx shift = operands[
2];
4761 rtx cr = operands[
3];
4768 src2 = gen_lowpart (SImode, dest);
4769 emit_move_insn (src2, src);
4772 if (REGNO (cr) == CR0_REGNO)
4774 emit_insn (gen_ashdi3_extswsli_dot2 (dest, src2, shift, cr));
4778 emit_insn (gen_ashdi3_extswsli (dest, src2, shift));
4779 emit_insn (gen_rtx_SET (cr, gen_rtx_COMPARE (CCmode, dest, const0_rtx)));
4782 [(set_attr "type" "shift")
4783 (set_attr "maybe_var_shift" "no")
4784 (set_attr "dot" "yes")
4785 (set_attr "length" "
4,
8,
8,
12")])
4787 (define_insn "lshr<mode>
3"
4788 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4789 (lshiftrt:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
4790 (match_operand:SI
2 "reg_or_cint_operand" "rn")))]
4792 "sr<wd>%I2 %
0,%
1,%<hH>
2"
4793 [(set_attr "type" "shift")
4794 (set_attr "maybe_var_shift" "yes")])
4796 (define_insn "*lshrsi3_64"
4797 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4799 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4800 (match_operand:SI
2 "reg_or_cint_operand" "rn"))))]
4803 [(set_attr "type" "shift")
4804 (set_attr "maybe_var_shift" "yes")])
4806 (define_insn_and_split "*lshr<mode>
3_dot"
4807 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4808 (compare:CC (lshiftrt:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4809 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4811 (clobber (match_scratch:GPR
0 "=r,r"))]
4812 "<MODE>mode == Pmode"
4814 sr<wd>%I2. %
0,%
1,%<hH>
2
4816 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4818 (lshiftrt:GPR (match_dup
1)
4821 (compare:CC (match_dup
0)
4824 [(set_attr "type" "shift")
4825 (set_attr "maybe_var_shift" "yes")
4826 (set_attr "dot" "yes")
4827 (set_attr "length" "
4,
8")])
4829 (define_insn_and_split "*lshr<mode>
3_dot2"
4830 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4831 (compare:CC (lshiftrt:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4832 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4834 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4835 (lshiftrt:GPR (match_dup
1)
4837 "<MODE>mode == Pmode"
4839 sr<wd>%I2. %
0,%
1,%<hH>
2
4841 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4843 (lshiftrt:GPR (match_dup
1)
4846 (compare:CC (match_dup
0)
4849 [(set_attr "type" "shift")
4850 (set_attr "maybe_var_shift" "yes")
4851 (set_attr "dot" "yes")
4852 (set_attr "length" "
4,
8")])
4855 (define_insn "ashr<mode>
3"
4856 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
4857 (ashiftrt:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
4858 (match_operand:SI
2 "reg_or_cint_operand" "rn")))
4859 (clobber (reg:GPR CA_REGNO))]
4861 "sra<wd>%I2 %
0,%
1,%<hH>
2"
4862 [(set_attr "type" "shift")
4863 (set_attr "maybe_var_shift" "yes")])
4865 (define_insn "*ashrsi3_64"
4866 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4868 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4869 (match_operand:SI
2 "reg_or_cint_operand" "rn"))))
4870 (clobber (reg:SI CA_REGNO))]
4873 [(set_attr "type" "shift")
4874 (set_attr "maybe_var_shift" "yes")])
4876 (define_insn_and_split "*ashr<mode>
3_dot"
4877 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4878 (compare:CC (ashiftrt:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4879 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4881 (clobber (match_scratch:GPR
0 "=r,r"))
4882 (clobber (reg:GPR CA_REGNO))]
4883 "<MODE>mode == Pmode"
4885 sra<wd>%I2. %
0,%
1,%<hH>
2
4887 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4888 [(parallel [(set (match_dup
0)
4889 (ashiftrt:GPR (match_dup
1)
4891 (clobber (reg:GPR CA_REGNO))])
4893 (compare:CC (match_dup
0)
4896 [(set_attr "type" "shift")
4897 (set_attr "maybe_var_shift" "yes")
4898 (set_attr "dot" "yes")
4899 (set_attr "length" "
4,
8")])
4901 (define_insn_and_split "*ashr<mode>
3_dot2"
4902 [(set (match_operand:CC
3 "cc_reg_operand" "=x,?y")
4903 (compare:CC (ashiftrt:GPR (match_operand:GPR
1 "gpc_reg_operand" "r,r")
4904 (match_operand:SI
2 "reg_or_cint_operand" "rn,rn"))
4906 (set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
4907 (ashiftrt:GPR (match_dup
1)
4909 (clobber (reg:GPR CA_REGNO))]
4910 "<MODE>mode == Pmode"
4912 sra<wd>%I2. %
0,%
1,%<hH>
2
4914 "&& reload_completed && cc_reg_not_cr0_operand (operands[
3], CCmode)"
4915 [(parallel [(set (match_dup
0)
4916 (ashiftrt:GPR (match_dup
1)
4918 (clobber (reg:GPR CA_REGNO))])
4920 (compare:CC (match_dup
0)
4923 [(set_attr "type" "shift")
4924 (set_attr "maybe_var_shift" "yes")
4925 (set_attr "dot" "yes")
4926 (set_attr "length" "
4,
8")])
4928 ;; Builtins to replace a division to generate FRE reciprocal estimate
4929 ;; instructions and the necessary fixup instructions
4930 (define_expand "recip<mode>
3"
4931 [(match_operand:RECIPF
0 "gpc_reg_operand")
4932 (match_operand:RECIPF
1 "gpc_reg_operand")
4933 (match_operand:RECIPF
2 "gpc_reg_operand")]
4934 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4936 rs6000_emit_swdiv (operands[
0], operands[
1], operands[
2], false);
4940 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4941 ;; hardware division. This is only done before register allocation and with
4942 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4943 ;; We used to also check optimize_insn_for_speed_p () but problems with guessed
4944 ;; frequencies (pr68212/pr77536) yields that unreliable so it was removed.
4946 [(set (match_operand:RECIPF
0 "gpc_reg_operand")
4947 (div:RECIPF (match_operand
1 "gpc_reg_operand")
4948 (match_operand
2 "gpc_reg_operand")))]
4949 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4950 && can_create_pseudo_p () && flag_finite_math_only
4951 && !flag_trapping_math && flag_reciprocal_math"
4954 rs6000_emit_swdiv (operands[
0], operands[
1], operands[
2], true);
4958 ;; Builtins to replace
1/sqrt(x) with instructions using RSQRTE and the
4959 ;; appropriate fixup.
4960 (define_expand "rsqrt<mode>
2"
4961 [(match_operand:RECIPF
0 "gpc_reg_operand")
4962 (match_operand:RECIPF
1 "gpc_reg_operand")]
4963 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4965 rs6000_emit_swsqrt (operands[
0], operands[
1],
1);
4969 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4970 ;; modes here, and also add in conditional vsx/power8-vector support to access
4971 ;; values in the traditional Altivec registers if the appropriate
4972 ;; -mupper-regs-{df,sf} option is enabled.
4974 (define_expand "abs<mode>
2"
4975 [(set (match_operand:SFDF
0 "gpc_reg_operand")
4976 (abs:SFDF (match_operand:SFDF
1 "gpc_reg_operand")))]
4980 (define_insn "*abs<mode>
2_fpr"
4981 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
4982 (abs:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")))]
4987 [(set_attr "type" "fpsimple")])
4989 (define_insn "*nabs<mode>
2_fpr"
4990 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
4993 (match_operand:SFDF
1 "gpc_reg_operand" "d,wa"))))]
4998 [(set_attr "type" "fpsimple")])
5000 (define_expand "neg<mode>
2"
5001 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5002 (neg:SFDF (match_operand:SFDF
1 "gpc_reg_operand")))]
5006 (define_insn "*neg<mode>
2_fpr"
5007 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5008 (neg:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")))]
5013 [(set_attr "type" "fpsimple")])
5015 (define_expand "add<mode>
3"
5016 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5017 (plus:SFDF (match_operand:SFDF
1 "gpc_reg_operand")
5018 (match_operand:SFDF
2 "gpc_reg_operand")))]
5022 (define_insn "*add<mode>
3_fpr"
5023 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5024 (plus:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "%d,wa")
5025 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa")))]
5029 xsadd<sd>p %x0,%x1,%x2"
5030 [(set_attr "type" "fp")
5031 (set_attr "isa" "*,<Fisa>")])
5033 (define_expand "sub<mode>
3"
5034 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5035 (minus:SFDF (match_operand:SFDF
1 "gpc_reg_operand")
5036 (match_operand:SFDF
2 "gpc_reg_operand")))]
5040 (define_insn "*sub<mode>
3_fpr"
5041 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5042 (minus:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")
5043 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa")))]
5047 xssub<sd>p %x0,%x1,%x2"
5048 [(set_attr "type" "fp")
5049 (set_attr "isa" "*,<Fisa>")])
5051 (define_expand "mul<mode>
3"
5052 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5053 (mult:SFDF (match_operand:SFDF
1 "gpc_reg_operand")
5054 (match_operand:SFDF
2 "gpc_reg_operand")))]
5058 (define_insn "*mul<mode>
3_fpr"
5059 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5060 (mult:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "%d,wa")
5061 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa")))]
5065 xsmul<sd>p %x0,%x1,%x2"
5066 [(set_attr "type" "dmul")
5067 (set_attr "isa" "*,<Fisa>")])
5069 (define_expand "div<mode>
3"
5070 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5071 (div:SFDF (match_operand:SFDF
1 "gpc_reg_operand")
5072 (match_operand:SFDF
2 "gpc_reg_operand")))]
5075 if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5076 && can_create_pseudo_p () && flag_finite_math_only
5077 && !flag_trapping_math && flag_reciprocal_math)
5079 rs6000_emit_swdiv (operands[
0], operands[
1], operands[
2], true);
5084 (define_insn "*div<mode>
3_fpr"
5085 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5086 (div:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")
5087 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa")))]
5091 xsdiv<sd>p %x0,%x1,%x2"
5092 [(set_attr "type" "<sd>div")
5093 (set_attr "isa" "*,<Fisa>")])
5095 (define_insn "*sqrt<mode>
2_internal"
5096 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5097 (sqrt:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")))]
5098 "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
5101 xssqrt<sd>p %x0,%x1"
5102 [(set_attr "type" "<sd>sqrt")
5103 (set_attr "isa" "*,<Fisa>")])
5105 (define_expand "sqrt<mode>
2"
5106 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5107 (sqrt:SFDF (match_operand:SFDF
1 "gpc_reg_operand")))]
5108 "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
5110 if (<MODE>mode == SFmode
5111 && TARGET_RECIP_PRECISION
5112 && RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)
5113 && !optimize_function_for_size_p (cfun)
5114 && flag_finite_math_only && !flag_trapping_math
5115 && flag_unsafe_math_optimizations)
5117 rs6000_emit_swsqrt (operands[
0], operands[
1],
0);
5122 ;; Floating point reciprocal approximation
5123 (define_insn "fre<sd>"
5124 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5125 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand" "d,wa")]
5131 [(set_attr "type" "fp")
5132 (set_attr "isa" "*,<Fisa>")])
5134 (define_expand "fmod<mode>
3"
5135 [(use (match_operand:SFDF
0 "gpc_reg_operand"))
5136 (use (match_operand:SFDF
1 "gpc_reg_operand"))
5137 (use (match_operand:SFDF
2 "gpc_reg_operand"))]
5140 && flag_unsafe_math_optimizations"
5142 rtx div = gen_reg_rtx (<MODE>mode);
5143 emit_insn (gen_div<mode>
3 (div, operands[
1], operands[
2]));
5145 rtx friz = gen_reg_rtx (<MODE>mode);
5146 emit_insn (gen_btrunc<mode>
2 (friz, div));
5148 emit_insn (gen_nfms<mode>
4 (operands[
0], operands[
2], friz, operands[
1]));
5152 (define_expand "remainder<mode>
3"
5153 [(use (match_operand:SFDF
0 "gpc_reg_operand"))
5154 (use (match_operand:SFDF
1 "gpc_reg_operand"))
5155 (use (match_operand:SFDF
2 "gpc_reg_operand"))]
5158 && flag_unsafe_math_optimizations"
5160 rtx div = gen_reg_rtx (<MODE>mode);
5161 emit_insn (gen_div<mode>
3 (div, operands[
1], operands[
2]));
5163 rtx frin = gen_reg_rtx (<MODE>mode);
5164 emit_insn (gen_round<mode>
2 (frin, div));
5166 emit_insn (gen_nfms<mode>
4 (operands[
0], operands[
2], frin, operands[
1]));
5170 (define_insn "*rsqrt<mode>
2"
5171 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5172 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand" "d,wa")]
5174 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5177 xsrsqrte<sd>p %x0,%x1"
5178 [(set_attr "type" "fp")
5179 (set_attr "isa" "*,<Fisa>")])
5181 ;; Floating point comparisons
5182 (define_insn "*cmp<mode>_fpr"
5183 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y,y")
5184 (compare:CCFP (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")
5185 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa")))]
5189 xscmpudp %
0,%x1,%x2"
5190 [(set_attr "type" "fpcompare")
5191 (set_attr "isa" "*,<Fisa>")])
5193 ;; Floating point conversions
5194 (define_expand "extendsfdf2"
5195 [(set (match_operand:DF
0 "gpc_reg_operand")
5196 (float_extend:DF (match_operand:SF
1 "reg_or_mem_operand")))]
5199 if (HONOR_SNANS (SFmode))
5200 operands[
1] = force_reg (SFmode, operands[
1]);
5203 (define_insn_and_split "*extendsfdf2_fpr"
5204 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,?d,d,wa,?wa,wa,v")
5205 (float_extend:DF (match_operand:SF
1 "reg_or_mem_operand" "
0,f,m,
0,wa,Z,wY")))]
5206 "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
5212 xscpsgndp %x0,%x1,%x1
5215 "&& reload_completed && REG_P (operands[
1]) && REGNO (operands[
0]) == REGNO (operands[
1])"
5218 emit_note (NOTE_INSN_DELETED);
5221 [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")
5222 (set_attr "isa" "*,*,*,*,p8v,p8v,p9v")])
5224 (define_insn "*extendsfdf2_snan"
5225 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,wa")
5226 (float_extend:DF (match_operand:SF
1 "gpc_reg_operand" "f,wa")))]
5227 "TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
5231 [(set_attr "type" "fp")
5232 (set_attr "isa" "*,p8v")])
5234 (define_expand "truncdfsf2"
5235 [(set (match_operand:SF
0 "gpc_reg_operand")
5236 (float_truncate:SF (match_operand:DF
1 "gpc_reg_operand")))]
5240 (define_insn "*truncdfsf2_fpr"
5241 [(set (match_operand:SF
0 "gpc_reg_operand" "=f,wa")
5242 (float_truncate:SF (match_operand:DF
1 "gpc_reg_operand" "d,wa")))]
5247 [(set_attr "type" "fp")
5248 (set_attr "isa" "*,p8v")])
5250 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5251 ;; builtins.cc and optabs.cc that are not correct for IBM long double
5252 ;; when little-endian.
5253 (define_expand "signbit<mode>
2"
5255 (float_truncate:DF (match_operand:FLOAT128
1 "gpc_reg_operand")))
5257 (subreg:DI (match_dup
2)
0))
5260 (set (match_operand:SI
0 "gpc_reg_operand")
5263 && (!FLOAT128_IEEE_P (<MODE>mode)
5264 || (TARGET_POWERPC64 && TARGET_DIRECT_MOVE))"
5266 if (FLOAT128_IEEE_P (<MODE>mode))
5268 rtx dest = operands[
0];
5269 rtx src = operands[
1];
5270 rtx tmp = gen_reg_rtx (DImode);
5271 rtx dest_di = gen_lowpart (DImode, dest);
5273 emit_insn (gen_signbit2_dm (<MODE>mode, tmp, src));
5274 emit_insn (gen_lshrdi3 (dest_di, tmp, GEN_INT (
63)));
5277 operands[
2] = gen_reg_rtx (DFmode);
5278 operands[
3] = gen_reg_rtx (DImode);
5279 if (TARGET_POWERPC64)
5281 operands[
4] = gen_reg_rtx (DImode);
5282 operands[
5] = gen_rtx_LSHIFTRT (DImode, operands[
3], GEN_INT (
63));
5283 operands[
6] = gen_rtx_SUBREG (SImode, operands[
4],
5284 WORDS_BIG_ENDIAN ?
4 :
0);
5288 operands[
4] = gen_reg_rtx (SImode);
5289 operands[
5] = gen_rtx_SUBREG (SImode, operands[
3],
5290 WORDS_BIG_ENDIAN ?
0 :
4);
5291 operands[
6] = gen_rtx_LSHIFTRT (SImode, operands[
4], GEN_INT (
31));
5295 ;; Optimize IEEE
128-bit signbit on
64-bit systems with direct move to avoid
5296 ;; multiple direct moves. If we used a SUBREG:DI of the Floa128 type, the
5297 ;; register allocator would typically move the entire _Float128 item to GPRs (
2
5298 ;; instructions on ISA
3.0,
3-
4 instructions on ISA
2.07).
5300 ;; After register allocation, if the _Float128 had originally been in GPRs, the
5301 ;; split allows the post reload phases to eliminate the move, and do the shift
5302 ;; directly with the register that contains the signbit.
5303 (define_insn_and_split "@signbit<mode>
2_dm"
5304 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
5305 (unspec:DI [(match_operand:SIGNBIT
1 "gpc_reg_operand" "wa,r")]
5307 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
5311 "&& reload_completed && int_reg_operand (operands[
1], <MODE>mode)"
5315 operands[
2] = gen_highpart (DImode, operands[
1]);
5317 [(set_attr "type" "mfvsr,*")])
5319 ;; Optimize IEEE
128-bit signbit on to avoid loading the value into a vector
5320 ;; register and then doing a direct move if the value comes from memory. On
5321 ;; little endian, we have to load the
2nd double-word to get the sign bit.
5322 (define_insn_and_split "*signbit<mode>
2_dm_mem"
5323 [(set (match_operand:DI
0 "gpc_reg_operand" "=b")
5324 (unspec:DI [(match_operand:SIGNBIT
1 "memory_operand" "m")]
5326 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
5332 rtx dest = operands[
0];
5333 rtx src = operands[
1];
5334 rtx addr = XEXP (src,
0);
5336 if (WORDS_BIG_ENDIAN)
5337 operands[
2] = adjust_address (src, DImode,
0);
5339 else if (REG_P (addr) || SUBREG_P (addr))
5340 operands[
2] = adjust_address (src, DImode,
8);
5342 else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr,
0))
5343 && CONST_INT_P (XEXP (addr,
1)) && mem_operand_gpr (src, DImode))
5344 operands[
2] = adjust_address (src, DImode,
8);
5348 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (DImode) : dest;
5349 emit_insn (gen_rtx_SET (tmp, addr));
5350 operands[
2] = change_address (src, DImode,
5351 gen_rtx_PLUS (DImode, tmp, GEN_INT (
8)));
5355 (define_expand "copysign<mode>
3"
5357 (abs:SFDF (match_operand:SFDF
1 "gpc_reg_operand")))
5359 (neg:SFDF (abs:SFDF (match_dup
1))))
5360 (set (match_operand:SFDF
0 "gpc_reg_operand")
5361 (if_then_else:SFDF (ge (match_operand:SFDF
2 "any_operand")
5366 && ((TARGET_PPC_GFXOPT
5367 && !HONOR_NANS (<MODE>mode)
5368 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5370 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5372 /* Middle-end canonicalizes -fabs (x) to copysign (x, -
1),
5373 but PowerPC prefers -fabs (x). */
5374 if (CONST_DOUBLE_AS_FLOAT_P (operands[
2]))
5376 if (real_isneg (CONST_DOUBLE_REAL_VALUE (operands[
2])))
5378 operands[
3] = gen_reg_rtx (<MODE>mode);
5379 emit_insn (gen_abs<mode>
2 (operands[
3], operands[
1]));
5380 emit_insn (gen_neg<mode>
2 (operands[
0], operands[
3]));
5383 emit_insn (gen_abs<mode>
2 (operands[
0], operands[
1]));
5387 if (!gpc_reg_operand (operands[
2], <MODE>mode))
5388 operands[
2] = copy_to_mode_reg (<MODE>mode, operands[
2]);
5390 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5392 emit_insn (gen_copysign<mode>
3_fcpsgn (operands[
0], operands[
1],
5397 operands[
3] = gen_reg_rtx (<MODE>mode);
5398 operands[
4] = gen_reg_rtx (<MODE>mode);
5399 operands[
5] = CONST0_RTX (<MODE>mode);
5402 (define_insn "copysign<mode>
3_fcpsgn"
5403 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5404 (copysign:SFDF (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")
5405 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa")))]
5406 "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
5409 xscpsgndp %x0,%x2,%x1"
5410 [(set_attr "type" "fpsimple")])
5412 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5413 ;; fsel instruction and some auxiliary computations. Then we just have a
5414 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5416 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5417 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5418 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5419 ;; define_splits to make them if made by combine. On VSX machines we have the
5420 ;; min/max instructions.
5422 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5423 ;; to allow either DF/SF to use only traditional registers.
5425 (define_expand "s<minmax><mode>
3"
5426 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5427 (fp_minmax:SFDF (match_operand:SFDF
1 "gpc_reg_operand")
5428 (match_operand:SFDF
2 "gpc_reg_operand")))]
5431 rs6000_emit_minmax (operands[
0], <SMINMAX>, operands[
1], operands[
2]);
5435 (define_insn "*s<minmax><mode>
3_vsx"
5436 [(set (match_operand:SFDF
0 "vsx_register_operand" "=wa")
5437 (fp_minmax:SFDF (match_operand:SFDF
1 "vsx_register_operand" "wa")
5438 (match_operand:SFDF
2 "vsx_register_operand" "wa")))]
5439 "TARGET_VSX && TARGET_HARD_FLOAT"
5441 return (TARGET_P9_MINMAX
5442 ? "xs<minmax>cdp %x0,%x1,%x2"
5443 : "xs<minmax>dp %x0,%x1,%x2");
5445 [(set_attr "type" "fp")])
5447 ;; Min/max for ISA
3.1 IEEE
128-bit floating point
5448 (define_insn "s<minmax><mode>
3"
5449 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
5451 (match_operand:IEEE128
1 "altivec_register_operand" "v")
5452 (match_operand:IEEE128
2 "altivec_register_operand" "v")))]
5453 "TARGET_POWER10 && TARGET_FLOAT128_HW"
5454 "xs<minmax>cqp %
0,%
1,%
2"
5455 [(set_attr "type" "vecfloat")
5456 (set_attr "size" "
128")])
5458 ;; The conditional move instructions allow us to perform max and min operations
5459 ;; even when we don't have the appropriate max/min instruction using the FSEL
5462 (define_insn_and_split "*s<minmax><mode>
3_fpr"
5463 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5464 (fp_minmax:SFDF (match_operand:SFDF
1 "gpc_reg_operand")
5465 (match_operand:SFDF
2 "gpc_reg_operand")))]
5466 "!TARGET_VSX && TARGET_MINMAX"
5471 rs6000_emit_minmax (operands[
0], <SMINMAX>, operands[
1], operands[
2]);
5476 (define_int_iterator FMINMAX [UNSPEC_FMAX UNSPEC_FMIN])
5478 (define_int_attr minmax_op [(UNSPEC_FMAX "max")
5479 (UNSPEC_FMIN "min")])
5481 (define_insn "f<minmax_op><mode>
3"
5482 [(set (match_operand:SFDF
0 "vsx_register_operand" "=wa")
5483 (unspec:SFDF [(match_operand:SFDF
1 "vsx_register_operand" "wa")
5484 (match_operand:SFDF
2 "vsx_register_operand" "wa")]
5486 "TARGET_VSX && !flag_finite_math_only"
5487 "xs<minmax_op>dp %x0,%x1,%x2"
5488 [(set_attr "type" "fp")]
5491 (define_expand "mov<mode>cc"
5492 [(set (match_operand:GPR
0 "gpc_reg_operand")
5493 (if_then_else:GPR (match_operand
1 "comparison_operator")
5494 (match_operand:GPR
2 "gpc_reg_operand")
5495 (match_operand:GPR
3 "gpc_reg_operand")))]
5498 if (rs6000_emit_cmove (operands[
0], operands[
1], operands[
2], operands[
3]))
5504 ;; We use the BASE_REGS for the isel input operands because, if rA is
5505 ;;
0, the value of
0 is placed in rD upon truth. Similarly for rB
5506 ;; because we may switch the operands and rB may end up being rA.
5508 ;; We need
2 patterns: an unsigned and a signed pattern. We could
5509 ;; leave out the mode in operand
4 and use one pattern, but reload can
5510 ;; change the mode underneath our feet and then gets confused trying
5511 ;; to reload the value.
5512 (define_mode_iterator CCANY [CC CCUNS])
5513 (define_insn "isel_<CCANY:mode>_<GPR:mode>"
5514 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
5516 (match_operator
1 "scc_comparison_operator"
5517 [(match_operand:CCANY
4 "cc_reg_operand" "y,y")
5519 (match_operand:GPR
2 "reg_or_zero_operand" "O,b")
5520 (match_operand:GPR
3 "gpc_reg_operand" "r,r")))]
5523 [(set_attr "type" "isel")])
5525 ;; These patterns can be useful for combine; they let combine know that
5526 ;; isel can handle reversed comparisons so long as the operands are
5529 (define_insn "*isel_reversed_<CCANY:mode>_<GPR:mode>"
5530 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r,r")
5532 (match_operator
1 "scc_rev_comparison_operator"
5533 [(match_operand:CCANY
4 "cc_reg_operand" "y,y")
5535 (match_operand:GPR
2 "gpc_reg_operand" "r,r")
5536 (match_operand:GPR
3 "reg_or_zero_operand" "O,b")))]
5539 PUT_CODE (operands[
1], reverse_condition (GET_CODE (operands[
1])));
5540 return "isel %
0,%
3,%
2,%j1";
5542 [(set_attr "type" "isel")])
5544 ; Set Boolean Condition (Reverse)
5545 (define_insn "setbc_<CCANY:mode>_<GPR:mode>"
5546 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
5547 (match_operator:GPR
1 "scc_comparison_operator"
5548 [(match_operand:CCANY
2 "cc_reg_operand" "y")
5552 [(set_attr "type" "isel")])
5554 (define_insn "*setbcr_<CCANY:mode>_<GPR:mode>"
5555 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
5556 (match_operator:GPR
1 "scc_rev_comparison_operator"
5557 [(match_operand:CCANY
2 "cc_reg_operand" "y")
5561 [(set_attr "type" "isel")])
5563 ; Set Negative Boolean Condition (Reverse)
5564 (define_insn "*setnbc_<CCANY:mode>_<GPR:mode>"
5565 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
5566 (neg:GPR (match_operator:GPR
1 "scc_comparison_operator"
5567 [(match_operand:CCANY
2 "cc_reg_operand" "y")
5571 [(set_attr "type" "isel")])
5573 (define_insn "*setnbcr_<CCANY:mode>_<GPR:mode>"
5574 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
5575 (neg:GPR (match_operator:GPR
1 "scc_rev_comparison_operator"
5576 [(match_operand:CCANY
2 "cc_reg_operand" "y")
5580 [(set_attr "type" "isel")])
5582 ;; Floating point conditional move
5583 (define_expand "mov<mode>cc"
5584 [(set (match_operand:SFDF
0 "gpc_reg_operand")
5585 (if_then_else:SFDF (match_operand
1 "comparison_operator")
5586 (match_operand:SFDF
2 "gpc_reg_operand")
5587 (match_operand:SFDF
3 "gpc_reg_operand")))]
5588 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5590 if (rs6000_emit_cmove (operands[
0], operands[
1], operands[
2], operands[
3]))
5596 (define_insn "*fsel<SFDF:mode><SFDF2:mode>
4"
5597 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=&<SFDF:rreg2>")
5599 (ge (match_operand:SFDF2
1 "gpc_reg_operand" "<SFDF2:rreg2>")
5600 (match_operand:SFDF2
4 "zero_fp_constant" "F"))
5601 (match_operand:SFDF
2 "gpc_reg_operand" "<SFDF:rreg2>")
5602 (match_operand:SFDF
3 "gpc_reg_operand" "<SFDF:rreg2>")))]
5603 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5605 [(set_attr "type" "fp")])
5607 (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
5608 [(set (match_operand:SFDF
0 "vsx_register_operand" "=&wa,wa")
5610 (match_operator:CCFP
1 "fpmask_comparison_operator"
5611 [(match_operand:SFDF2
2 "vsx_register_operand" "wa,wa")
5612 (match_operand:SFDF2
3 "vsx_register_operand" "wa,wa")])
5613 (match_operand:SFDF
4 "vsx_register_operand" "wa,wa")
5614 (match_operand:SFDF
5 "vsx_register_operand" "wa,wa")))
5615 (clobber (match_scratch:V2DI
6 "=
0,&wa"))]
5620 (if_then_else:V2DI (match_dup
1)
5624 (if_then_else:SFDF (ne (match_dup
6)
5629 if (GET_CODE (operands[
6]) == SCRATCH)
5630 operands[
6] = gen_reg_rtx (V2DImode);
5632 operands[
7] = CONSTM1_RTX (V2DImode);
5633 operands[
8] = CONST0_RTX (V2DImode);
5635 [(set_attr "length" "
8")
5636 (set_attr "type" "vecperm")])
5638 ;; Handle inverting the fpmask comparisons.
5639 (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_invert_p9"
5640 [(set (match_operand:SFDF
0 "vsx_register_operand" "=&wa,wa")
5642 (match_operator:CCFP
1 "invert_fpmask_comparison_operator"
5643 [(match_operand:SFDF2
2 "vsx_register_operand" "wa,wa")
5644 (match_operand:SFDF2
3 "vsx_register_operand" "wa,wa")])
5645 (match_operand:SFDF
4 "vsx_register_operand" "wa,wa")
5646 (match_operand:SFDF
5 "vsx_register_operand" "wa,wa")))
5647 (clobber (match_scratch:V2DI
6 "=
0,&wa"))]
5652 (if_then_else:V2DI (match_dup
9)
5656 (if_then_else:SFDF (ne (match_dup
6)
5661 rtx op1 = operands[
1];
5662 enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
5664 if (GET_CODE (operands[
6]) == SCRATCH)
5665 operands[
6] = gen_reg_rtx (V2DImode);
5667 operands[
7] = CONSTM1_RTX (V2DImode);
5668 operands[
8] = CONST0_RTX (V2DImode);
5670 operands[
9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[
2], operands[
3]);
5672 [(set_attr "length" "
8")
5673 (set_attr "type" "vecperm")])
5675 (define_insn "*fpmask<mode>"
5676 [(set (match_operand:V2DI
0 "vsx_register_operand" "=wa")
5678 (match_operator:CCFP
1 "fpmask_comparison_operator"
5679 [(match_operand:SFDF
2 "vsx_register_operand" "wa")
5680 (match_operand:SFDF
3 "vsx_register_operand" "wa")])
5681 (match_operand:V2DI
4 "all_ones_constant" "")
5682 (match_operand:V2DI
5 "zero_constant" "")))]
5684 "xscmp%V1dp %x0,%x2,%x3"
5685 [(set_attr "type" "fpcompare")])
5687 (define_insn "*xxsel<mode>"
5688 [(set (match_operand:SFDF
0 "vsx_register_operand" "=wa")
5689 (if_then_else:SFDF (ne (match_operand:V2DI
1 "vsx_register_operand" "wa")
5690 (match_operand:V2DI
2 "zero_constant" ""))
5691 (match_operand:SFDF
3 "vsx_register_operand" "wa")
5692 (match_operand:SFDF
4 "vsx_register_operand" "wa")))]
5694 "xxsel %x0,%x4,%x3,%x1"
5695 [(set_attr "type" "vecmove")])
5697 ;; Support for ISA
3.1 IEEE
128-bit conditional move. The mode used in the
5698 ;; comparison must be the same as used in the move.
5699 (define_expand "mov<mode>cc"
5700 [(set (match_operand:IEEE128
0 "gpc_reg_operand")
5701 (if_then_else:IEEE128 (match_operand
1 "comparison_operator")
5702 (match_operand:IEEE128
2 "gpc_reg_operand")
5703 (match_operand:IEEE128
3 "gpc_reg_operand")))]
5704 "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
5706 if (rs6000_emit_cmove (operands[
0], operands[
1], operands[
2], operands[
3]))
5712 (define_insn_and_split "*mov<mode>cc_p10"
5713 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=&v,v")
5714 (if_then_else:IEEE128
5715 (match_operator:CCFP
1 "fpmask_comparison_operator"
5716 [(match_operand:IEEE128
2 "altivec_register_operand" "v,v")
5717 (match_operand:IEEE128
3 "altivec_register_operand" "v,v")])
5718 (match_operand:IEEE128
4 "altivec_register_operand" "v,v")
5719 (match_operand:IEEE128
5 "altivec_register_operand" "v,v")))
5720 (clobber (match_scratch:V2DI
6 "=
0,&v"))]
5721 "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
5725 (if_then_else:V2DI (match_dup
1)
5729 (if_then_else:IEEE128 (ne (match_dup
6)
5734 if (GET_CODE (operands[
6]) == SCRATCH)
5735 operands[
6] = gen_reg_rtx (V2DImode);
5737 operands[
7] = CONSTM1_RTX (V2DImode);
5738 operands[
8] = CONST0_RTX (V2DImode);
5740 [(set_attr "length" "
8")
5741 (set_attr "type" "vecperm")])
5743 ;; Handle inverting the fpmask comparisons.
5744 (define_insn_and_split "*mov<mode>cc_invert_p10"
5745 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=&v,v")
5746 (if_then_else:IEEE128
5747 (match_operator:CCFP
1 "invert_fpmask_comparison_operator"
5748 [(match_operand:IEEE128
2 "altivec_register_operand" "v,v")
5749 (match_operand:IEEE128
3 "altivec_register_operand" "v,v")])
5750 (match_operand:IEEE128
4 "altivec_register_operand" "v,v")
5751 (match_operand:IEEE128
5 "altivec_register_operand" "v,v")))
5752 (clobber (match_scratch:V2DI
6 "=
0,&v"))]
5753 "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
5757 (if_then_else:V2DI (match_dup
9)
5761 (if_then_else:IEEE128 (ne (match_dup
6)
5766 rtx op1 = operands[
1];
5767 enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
5769 if (GET_CODE (operands[
6]) == SCRATCH)
5770 operands[
6] = gen_reg_rtx (V2DImode);
5772 operands[
7] = CONSTM1_RTX (V2DImode);
5773 operands[
8] = CONST0_RTX (V2DImode);
5775 operands[
9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[
2], operands[
3]);
5777 [(set_attr "length" "
8")
5778 (set_attr "type" "vecperm")])
5780 (define_insn "*fpmask<mode>"
5781 [(set (match_operand:V2DI
0 "altivec_register_operand" "=v")
5783 (match_operator:CCFP
1 "fpmask_comparison_operator"
5784 [(match_operand:IEEE128
2 "altivec_register_operand" "v")
5785 (match_operand:IEEE128
3 "altivec_register_operand" "v")])
5786 (match_operand:V2DI
4 "all_ones_constant" "")
5787 (match_operand:V2DI
5 "zero_constant" "")))]
5788 "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
5789 "xscmp%V1qp %
0,%
2,%
3"
5790 [(set_attr "type" "fpcompare")])
5792 (define_insn "*xxsel<mode>"
5793 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
5794 (if_then_else:IEEE128
5795 (ne (match_operand:V2DI
1 "altivec_register_operand" "v")
5796 (match_operand:V2DI
2 "zero_constant" ""))
5797 (match_operand:IEEE128
3 "altivec_register_operand" "v")
5798 (match_operand:IEEE128
4 "altivec_register_operand" "v")))]
5799 "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
5800 "xxsel %x0,%x4,%x3,%x1"
5801 [(set_attr "type" "vecmove")])
5804 ;; Conversions to and from floating-point.
5806 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5807 ; don't want to support putting SImode in FPR registers.
5808 (define_insn "lfiwax"
5809 [(set (match_operand:DI
0 "gpc_reg_operand" "=d,wa,wa,v")
5810 (unspec:DI [(match_operand:SI
1 "reg_or_indexed_operand" "Z,Z,r,v")]
5812 "TARGET_HARD_FLOAT && TARGET_LFIWAX"
5818 [(set_attr "type" "fpload,fpload,mtvsr,vecexts")
5819 (set_attr "isa" "*,p8v,p8v,p9v")])
5821 ; This split must be run before register allocation because it allocates the
5822 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5823 ; it earlier to allow for the combiner to merge insns together where it might
5824 ; not be needed and also in case the insns are deleted as dead code.
5826 (define_insn_and_split "floatsi<mode>
2_lfiwax"
5827 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5828 (float:SFDF (match_operand:SI
1 "nonimmediate_operand" "r,r")))
5829 (clobber (match_scratch:DI
2 "=d,wa"))]
5830 "TARGET_HARD_FLOAT && TARGET_LFIWAX
5831 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5836 rtx dest = operands[
0];
5837 rtx src = operands[
1];
5840 if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
5841 tmp = convert_to_mode (DImode, src, false);
5845 if (GET_CODE (tmp) == SCRATCH)
5846 tmp = gen_reg_rtx (DImode);
5849 src = rs6000_force_indexed_or_indirect_mem (src);
5850 emit_insn (gen_lfiwax (tmp, src));
5854 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5855 emit_move_insn (stack, src);
5856 emit_insn (gen_lfiwax (tmp, stack));
5859 emit_insn (gen_floatdi<mode>
2 (dest, tmp));
5862 [(set_attr "length" "
12")
5863 (set_attr "type" "fpload")])
5865 (define_insn_and_split "floatsi<mode>
2_lfiwax_mem"
5866 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5869 (match_operand:SI
1 "indexed_or_indirect_operand" "Z,Z"))))
5870 (clobber (match_scratch:DI
2 "=d,wa"))]
5871 "TARGET_HARD_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
5876 operands[
1] = rs6000_force_indexed_or_indirect_mem (operands[
1]);
5877 if (GET_CODE (operands[
2]) == SCRATCH)
5878 operands[
2] = gen_reg_rtx (DImode);
5879 if (TARGET_P8_VECTOR)
5880 emit_insn (gen_extendsidi2 (operands[
2], operands[
1]));
5882 emit_insn (gen_lfiwax (operands[
2], operands[
1]));
5883 emit_insn (gen_floatdi<mode>
2 (operands[
0], operands[
2]));
5886 [(set_attr "length" "
8")
5887 (set_attr "type" "fpload")])
5889 (define_insn_and_split "floatsi<SFDF:mode>
2_lfiwax_<QHI:mode>_mem_zext"
5890 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5893 (match_operand:QHI
1 "indexed_or_indirect_operand" "Z,Z"))))
5894 (clobber (match_scratch:DI
2 "=d,wa"))]
5895 "TARGET_HARD_FLOAT && <SI_CONVERT_FP> && TARGET_P9_VECTOR
5896 && TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
5901 if (GET_CODE (operands[
2]) == SCRATCH)
5902 operands[
2] = gen_reg_rtx (DImode);
5903 emit_insn (gen_zero_extendhidi2 (operands[
2], operands[
1]));
5904 emit_insn (gen_floatdi<SFDF:mode>
2 (operands[
0], operands[
2]));
5907 [(set_attr "length" "
8")
5908 (set_attr "type" "fpload")])
5910 (define_insn "lfiwzx"
5911 [(set (match_operand:DI
0 "gpc_reg_operand" "=d,wa,wa,wa")
5912 (unspec:DI [(match_operand:SI
1 "reg_or_indexed_operand" "Z,Z,r,wa")]
5914 "TARGET_HARD_FLOAT && TARGET_LFIWZX"
5919 xxextractuw %x0,%x1,
4"
5920 [(set_attr "type" "fpload,fpload,mtvsr,vecexts")
5921 (set_attr "isa" "*,p8v,p8v,p9v")])
5923 (define_insn_and_split "floatunssi<mode>
2_lfiwzx"
5924 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5925 (unsigned_float:SFDF (match_operand:SI
1 "nonimmediate_operand" "r,r")))
5926 (clobber (match_scratch:DI
2 "=d,wa"))]
5927 "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
5932 rtx dest = operands[
0];
5933 rtx src = operands[
1];
5936 if (!MEM_P (src) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
5937 tmp = convert_to_mode (DImode, src, true);
5941 if (GET_CODE (tmp) == SCRATCH)
5942 tmp = gen_reg_rtx (DImode);
5945 src = rs6000_force_indexed_or_indirect_mem (src);
5946 emit_insn (gen_lfiwzx (tmp, src));
5950 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5951 emit_move_insn (stack, src);
5952 emit_insn (gen_lfiwzx (tmp, stack));
5955 emit_insn (gen_floatdi<mode>
2 (dest, tmp));
5958 [(set_attr "length" "
12")
5959 (set_attr "type" "fpload")])
5961 (define_insn_and_split "floatunssi<mode>
2_lfiwzx_mem"
5962 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
5963 (unsigned_float:SFDF
5965 (match_operand:SI
1 "indexed_or_indirect_operand" "Z,Z"))))
5966 (clobber (match_scratch:DI
2 "=d,wa"))]
5967 "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
5972 operands[
1] = rs6000_force_indexed_or_indirect_mem (operands[
1]);
5973 if (GET_CODE (operands[
2]) == SCRATCH)
5974 operands[
2] = gen_reg_rtx (DImode);
5975 if (TARGET_P8_VECTOR)
5976 emit_insn (gen_zero_extendsidi2 (operands[
2], operands[
1]));
5978 emit_insn (gen_lfiwzx (operands[
2], operands[
1]));
5979 emit_insn (gen_floatdi<mode>
2 (operands[
0], operands[
2]));
5982 [(set_attr "length" "
8")
5983 (set_attr "type" "fpload")])
5985 ; For each of these conversions, there is a define_expand, a define_insn
5986 ; with a '#' template, and a define_split (with C code). The idea is
5987 ; to allow constant folding with the template of the define_insn,
5988 ; then to have the insns split later (between sched1 and final).
5990 (define_expand "floatsidf2"
5991 [(parallel [(set (match_operand:DF
0 "gpc_reg_operand")
5992 (float:DF (match_operand:SI
1 "nonimmediate_operand")))
5995 (clobber (match_dup
4))
5996 (clobber (match_dup
5))
5997 (clobber (match_dup
6))])]
6000 if (TARGET_LFIWAX && TARGET_FCFID)
6002 emit_insn (gen_floatsidf2_lfiwax (operands[
0], operands[
1]));
6005 else if (TARGET_FCFID)
6007 rtx dreg = operands[
1];
6009 dreg = force_reg (SImode, dreg);
6010 dreg = convert_to_mode (DImode, dreg, false);
6011 emit_insn (gen_floatdidf2 (operands[
0], dreg));
6015 if (!REG_P (operands[
1]))
6016 operands[
1] = force_reg (SImode, operands[
1]);
6017 operands[
2] = force_reg (SImode, GEN_INT (
0x43300000));
6018 operands[
3] = force_reg (DFmode, CONST_DOUBLE_ATOF (
\"4503601774854144\", DFmode));
6019 operands[
4] = rs6000_allocate_stack_temp (DFmode, true, false);
6020 operands[
5] = gen_reg_rtx (DFmode);
6021 operands[
6] = gen_reg_rtx (SImode);
6024 (define_insn_and_split "*floatsidf2_internal"
6025 [(set (match_operand:DF
0 "gpc_reg_operand" "=&d")
6026 (float:DF (match_operand:SI
1 "gpc_reg_operand" "r")))
6027 (use (match_operand:SI
2 "gpc_reg_operand" "r"))
6028 (use (match_operand:DF
3 "gpc_reg_operand" "d"))
6029 (clobber (match_operand:DF
4 "offsettable_mem_operand" "=o"))
6030 (clobber (match_operand:DF
5 "gpc_reg_operand" "=&d"))
6031 (clobber (match_operand:SI
6 "gpc_reg_operand" "=&r"))]
6032 "!TARGET_FCFID && TARGET_HARD_FLOAT"
6037 rtx lowword, highword;
6038 gcc_assert (MEM_P (operands[
4]));
6039 highword = adjust_address (operands[
4], SImode,
0);
6040 lowword = adjust_address (operands[
4], SImode,
4);
6041 if (! WORDS_BIG_ENDIAN)
6042 std::swap (lowword, highword);
6044 emit_insn (gen_xorsi3 (operands[
6], operands[
1],
6045 GEN_INT (~ (HOST_WIDE_INT)
0x7fffffff)));
6046 emit_move_insn (lowword, operands[
6]);
6047 emit_move_insn (highword, operands[
2]);
6048 emit_move_insn (operands[
5], operands[
4]);
6049 emit_insn (gen_subdf3 (operands[
0], operands[
5], operands[
3]));
6052 [(set_attr "length" "
24")
6053 (set_attr "type" "fp")])
6055 ;; If we don't have a direct conversion to single precision, don't enable this
6056 ;; conversion for
32-bit without fast math, because we don't have the insn to
6057 ;; generate the fixup swizzle to avoid double rounding problems.
6058 (define_expand "floatunssisf2"
6059 [(set (match_operand:SF
0 "gpc_reg_operand")
6060 (unsigned_float:SF (match_operand:SI
1 "nonimmediate_operand")))]
6062 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
6064 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
6066 if (TARGET_LFIWZX && TARGET_FCFIDUS)
6068 emit_insn (gen_floatunssisf2_lfiwzx (operands[
0], operands[
1]));
6073 rtx dreg = operands[
1];
6075 dreg = force_reg (SImode, dreg);
6076 dreg = convert_to_mode (DImode, dreg, true);
6077 emit_insn (gen_floatdisf2 (operands[
0], dreg));
6082 (define_expand "floatunssidf2"
6083 [(parallel [(set (match_operand:DF
0 "gpc_reg_operand")
6084 (unsigned_float:DF (match_operand:SI
1 "nonimmediate_operand")))
6087 (clobber (match_dup
4))
6088 (clobber (match_dup
5))])]
6091 if (TARGET_LFIWZX && TARGET_FCFID)
6093 emit_insn (gen_floatunssidf2_lfiwzx (operands[
0], operands[
1]));
6096 else if (TARGET_FCFID)
6098 rtx dreg = operands[
1];
6100 dreg = force_reg (SImode, dreg);
6101 dreg = convert_to_mode (DImode, dreg, true);
6102 emit_insn (gen_floatdidf2 (operands[
0], dreg));
6106 if (!REG_P (operands[
1]))
6107 operands[
1] = force_reg (SImode, operands[
1]);
6108 operands[
2] = force_reg (SImode, GEN_INT (
0x43300000));
6109 operands[
3] = force_reg (DFmode, CONST_DOUBLE_ATOF (
\"4503599627370496\", DFmode));
6110 operands[
4] = rs6000_allocate_stack_temp (DFmode, true, false);
6111 operands[
5] = gen_reg_rtx (DFmode);
6114 (define_insn_and_split "*floatunssidf2_internal"
6115 [(set (match_operand:DF
0 "gpc_reg_operand" "=&d")
6116 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "r")))
6117 (use (match_operand:SI
2 "gpc_reg_operand" "r"))
6118 (use (match_operand:DF
3 "gpc_reg_operand" "d"))
6119 (clobber (match_operand:DF
4 "offsettable_mem_operand" "=o"))
6120 (clobber (match_operand:DF
5 "gpc_reg_operand" "=&d"))]
6121 "!TARGET_FCFIDU && TARGET_HARD_FLOAT
6122 && !(TARGET_FCFID && TARGET_POWERPC64)"
6127 rtx lowword, highword;
6128 gcc_assert (MEM_P (operands[
4]));
6129 highword = adjust_address (operands[
4], SImode,
0);
6130 lowword = adjust_address (operands[
4], SImode,
4);
6131 if (! WORDS_BIG_ENDIAN)
6132 std::swap (lowword, highword);
6134 emit_move_insn (lowword, operands[
1]);
6135 emit_move_insn (highword, operands[
2]);
6136 emit_move_insn (operands[
5], operands[
4]);
6137 emit_insn (gen_subdf3 (operands[
0], operands[
5], operands[
3]));
6140 [(set_attr "length" "
20")
6141 (set_attr "type" "fp")])
6143 ;; ISA
3.0 adds instructions lxsi[bh]zx to directly load QImode and HImode to
6144 ;; vector registers. These insns favor doing the sign/zero extension in
6145 ;; the vector registers, rather then loading up a GPR, doing a sign/zero
6146 ;; extension and then a direct move.
6148 (define_expand "float<QHI:mode><SFDF:mode>
2"
6149 [(parallel [(set (match_operand:SFDF
0 "vsx_register_operand")
6151 (match_operand:QHI
1 "input_operand")))
6152 (clobber (match_scratch:DI
2))
6153 (clobber (match_scratch:DI
3))
6154 (clobber (match_scratch:<QHI:MODE>
4))])]
6155 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
6157 if (MEM_P (operands[
1]))
6158 operands[
1] = rs6000_force_indexed_or_indirect_mem (operands[
1]);
6161 (define_insn_and_split "*float<QHI:mode><SFDF:mode>
2_internal"
6162 [(set (match_operand:SFDF
0 "vsx_register_operand" "=wa,wa,wa")
6164 (match_operand:QHI
1 "reg_or_indexed_operand" "v,r,Z")))
6165 (clobber (match_scratch:DI
2 "=v,wa,v"))
6166 (clobber (match_scratch:DI
3 "=X,r,X"))
6167 (clobber (match_scratch:<QHI:MODE>
4 "=X,X,v"))]
6168 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
6170 "&& reload_completed"
6173 rtx result = operands[
0];
6174 rtx input = operands[
1];
6175 rtx di = operands[
2];
6179 rtx tmp = operands[
3];
6180 if (altivec_register_operand (input, <QHI:MODE>mode))
6181 emit_insn (gen_extend<QHI:mode>di2 (di, input));
6182 else if (GET_CODE (tmp) == SCRATCH)
6183 emit_insn (gen_extend<QHI:mode>di2 (di, input));
6186 emit_insn (gen_extend<QHI:mode>di2 (tmp, input));
6187 emit_move_insn (di, tmp);
6192 rtx tmp = operands[
4];
6193 emit_move_insn (tmp, input);
6194 emit_insn (gen_extend<QHI:mode>di2 (di, tmp));
6197 emit_insn (gen_floatdi<SFDF:mode>
2 (result, di));
6200 [(set_attr "isa" "p9v,*,p9v")])
6202 (define_expand "floatuns<QHI:mode><SFDF:mode>
2"
6203 [(parallel [(set (match_operand:SFDF
0 "vsx_register_operand")
6204 (unsigned_float:SFDF
6205 (match_operand:QHI
1 "input_operand")))
6206 (clobber (match_scratch:DI
2))
6207 (clobber (match_scratch:DI
3))])]
6208 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
6210 if (MEM_P (operands[
1]))
6211 operands[
1] = rs6000_force_indexed_or_indirect_mem (operands[
1]);
6214 (define_insn_and_split "*floatuns<QHI:mode><SFDF:mode>
2_internal"
6215 [(set (match_operand:SFDF
0 "vsx_register_operand" "=wa,wa,wa")
6216 (unsigned_float:SFDF
6217 (match_operand:QHI
1 "reg_or_indexed_operand" "v,r,Z")))
6218 (clobber (match_scratch:DI
2 "=v,wa,wa"))
6219 (clobber (match_scratch:DI
3 "=X,r,X"))]
6220 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
6222 "&& reload_completed"
6225 rtx result = operands[
0];
6226 rtx input = operands[
1];
6227 rtx di = operands[
2];
6229 if (MEM_P (input) || altivec_register_operand (input, <QHI:MODE>mode))
6230 emit_insn (gen_zero_extend<QHI:mode>di2 (di, input));
6233 rtx tmp = operands[
3];
6234 if (GET_CODE (tmp) == SCRATCH)
6235 emit_insn (gen_extend<QHI:mode>di2 (di, input));
6238 emit_insn (gen_zero_extend<QHI:mode>di2 (tmp, input));
6239 emit_move_insn (di, tmp);
6243 emit_insn (gen_floatdi<SFDF:mode>
2 (result, di));
6246 [(set_attr "isa" "p9v,*,p9v")])
6248 (define_expand "fix_trunc<mode>si2"
6249 [(set (match_operand:SI
0 "gpc_reg_operand")
6250 (fix:SI (match_operand:SFDF
1 "gpc_reg_operand")))]
6253 if (!(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE))
6255 rtx src = force_reg (<MODE>mode, operands[
1]);
6258 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[
0], src));
6261 rtx tmp = gen_reg_rtx (DImode);
6262 rtx stack = rs6000_allocate_stack_temp (DImode, true, false);
6263 emit_insn (gen_fix_trunc<mode>si2_internal (operands[
0], src,
6270 ; Like the convert to float patterns, this insn must be split before
6271 ; register allocation so that it can allocate the memory slot if it
6273 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
6274 [(set (match_operand:SI
0 "nonimmediate_operand" "=rm")
6275 (fix:SI (match_operand:SFDF
1 "gpc_reg_operand" "d")))
6276 (clobber (match_scratch:DI
2 "=d"))]
6277 "TARGET_HARD_FLOAT && TARGET_STFIWX && can_create_pseudo_p ()
6278 && !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
6283 rtx dest = operands[
0];
6284 rtx src = operands[
1];
6285 rtx tmp = operands[
2];
6287 if (GET_CODE (tmp) == SCRATCH)
6288 tmp = gen_reg_rtx (DImode);
6290 emit_insn (gen_fctiwz_<mode> (tmp, src));
6291 if (MEM_P (dest) && (TARGET_MFCRF || MEM_ALIGN (dest) >=
32))
6293 dest = rs6000_force_indexed_or_indirect_mem (dest);
6294 emit_insn (gen_stfiwx (dest, tmp));
6297 else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE && !MEM_P (dest))
6299 dest = gen_lowpart (DImode, dest);
6300 emit_move_insn (dest, tmp);
6305 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6306 emit_insn (gen_stfiwx (stack, tmp));
6307 emit_move_insn (dest, stack);
6311 [(set_attr "length" "
12")
6312 (set_attr "type" "fp")])
6314 (define_insn_and_split "fix_trunc<mode>si2_internal"
6315 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,?r")
6316 (fix:SI (match_operand:SFDF
1 "gpc_reg_operand" "d,<rreg>")))
6317 (clobber (match_operand:DI
2 "gpc_reg_operand" "=
1,d"))
6318 (clobber (match_operand:DI
3 "offsettable_mem_operand" "=o,o"))]
6320 && !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
6326 gcc_assert (MEM_P (operands[
3]));
6327 lowword = adjust_address (operands[
3], SImode, WORDS_BIG_ENDIAN ?
4 :
0);
6329 emit_insn (gen_fctiwz_<mode> (operands[
2], operands[
1]));
6330 emit_move_insn (operands[
3], operands[
2]);
6331 emit_move_insn (operands[
0], lowword);
6334 [(set_attr "length" "
16")
6335 (set_attr "type" "fp")])
6337 (define_expand "fix_trunc<mode>di2"
6338 [(set (match_operand:DI
0 "gpc_reg_operand")
6339 (fix:DI (match_operand:SFDF
1 "gpc_reg_operand")))]
6340 "TARGET_HARD_FLOAT && TARGET_FCFID"
6343 (define_insn "*fix_trunc<mode>di2_fctidz"
6344 [(set (match_operand:DI
0 "gpc_reg_operand" "=d,wa")
6345 (fix:DI (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")))]
6346 "TARGET_HARD_FLOAT && TARGET_FCFID"
6350 [(set_attr "type" "fp")])
6352 ;; If we have ISA
3.0, QI/HImode values can go in both VSX registers and GPR
6353 ;; registers. If we have ISA
2.07, we don't allow QI/HImode values in the
6354 ;; vector registers, so we need to do direct moves to the GPRs, but SImode
6355 ;; values can go in VSX registers. Keeping the direct move part through
6356 ;; register allocation prevents the register allocator from doing a direct move
6357 ;; of the SImode value to a GPR, and then a store/load.
6358 (define_insn_and_split "fix<uns>_trunc<SFDF:mode><QHI:mode>
2"
6359 [(set (match_operand:<QHI:MODE>
0 "gpc_reg_operand" "=d,wa,r")
6360 (any_fix:QHI (match_operand:SFDF
1 "gpc_reg_operand" "d,wa,wa")))
6361 (clobber (match_scratch:SI
2 "=X,X,wa"))]
6362 "TARGET_DIRECT_MOVE"
6365 xscvdp<su>xws %x0,%x1
6367 "&& reload_completed && int_reg_operand (operands[
0], <QHI:MODE>mode)"
6369 (any_fix:SI (match_dup
1)))
6373 operands[
3] = gen_rtx_REG (SImode, REGNO (operands[
0]));
6375 [(set_attr "type" "fp")
6376 (set_attr "length" "
4,
4,
8")
6377 (set_attr "isa" "p9v,p9v,*")])
6379 (define_insn "*fix<uns>_trunc<SFDF:mode>si2_p8"
6380 [(set (match_operand:SI
0 "gpc_reg_operand" "=d,wa")
6381 (any_fix:SI (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")))]
6382 "TARGET_DIRECT_MOVE"
6385 xscvdp<su>xws %x0,%x1"
6386 [(set_attr "type" "fp")])
6388 ;; Keep the convert and store together through register allocation to prevent
6389 ;; the register allocator from getting clever and doing a direct move to a GPR
6390 ;; and then store for reg+offset stores.
6391 (define_insn_and_split "*fix<uns>_trunc<SFDF:mode><QHSI:mode>
2_mem"
6392 [(set (match_operand:QHSI
0 "memory_operand" "=Z")
6393 (any_fix:QHSI (match_operand:SFDF
1 "gpc_reg_operand" "wa")))
6394 (clobber (match_scratch:SI
2 "=wa"))]
6395 "(<QHSI:MODE>mode == SImode && TARGET_P8_VECTOR) || TARGET_P9_VECTOR"
6397 "&& reload_completed"
6399 (any_fix:SI (match_dup
1)))
6403 operands[
3] = (<QHSI:MODE>mode == SImode
6405 : gen_rtx_REG (<QHSI:MODE>mode, REGNO (operands[
2])));
6408 (define_expand "fixuns_trunc<mode>si2"
6409 [(set (match_operand:SI
0 "gpc_reg_operand")
6410 (unsigned_fix:SI (match_operand:SFDF
1 "gpc_reg_operand")))]
6411 "TARGET_HARD_FLOAT && TARGET_FCTIWUZ && TARGET_STFIWX"
6413 if (!TARGET_P8_VECTOR)
6415 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[
0], operands[
1]));
6420 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6421 [(set (match_operand:SI
0 "nonimmediate_operand" "=rm")
6422 (unsigned_fix:SI (match_operand:SFDF
1 "gpc_reg_operand" "d")))
6423 (clobber (match_scratch:DI
2 "=d"))]
6424 "TARGET_HARD_FLOAT && TARGET_FCTIWUZ
6425 && TARGET_STFIWX && can_create_pseudo_p ()
6426 && !TARGET_P8_VECTOR"
6431 rtx dest = operands[
0];
6432 rtx src = operands[
1];
6433 rtx tmp = operands[
2];
6435 if (GET_CODE (tmp) == SCRATCH)
6436 tmp = gen_reg_rtx (DImode);
6438 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6441 dest = rs6000_force_indexed_or_indirect_mem (dest);
6442 emit_insn (gen_stfiwx (dest, tmp));
6445 else if (TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
6447 dest = gen_lowpart (DImode, dest);
6448 emit_move_insn (dest, tmp);
6453 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6454 emit_insn (gen_stfiwx (stack, tmp));
6455 emit_move_insn (dest, stack);
6459 [(set_attr "length" "
12")
6460 (set_attr "type" "fp")])
6462 (define_insn "fixuns_trunc<mode>di2"
6463 [(set (match_operand:DI
0 "gpc_reg_operand" "=d,wa")
6464 (unsigned_fix:DI (match_operand:SFDF
1 "gpc_reg_operand" "d,wa")))]
6465 "TARGET_HARD_FLOAT && TARGET_FCTIDUZ"
6469 [(set_attr "type" "fp")])
6471 (define_insn "rs6000_mtfsb0"
6472 [(unspec_volatile [(match_operand:SI
0 "u5bit_cint_operand" "n")]
6476 [(set_attr "type" "fp")])
6478 (define_insn "rs6000_mtfsb1"
6479 [(unspec_volatile [(match_operand:SI
0 "u5bit_cint_operand" "n")]
6483 [(set_attr "type" "fp")])
6485 (define_insn "rs6000_mffscrn"
6486 [(set (match_operand:DF
0 "gpc_reg_operand" "=d")
6487 (unspec_volatile:DF [(match_operand:DF
1 "gpc_reg_operand" "d")]
6491 [(set_attr "type" "fp")])
6493 (define_insn "rs6000_mffscrni"
6494 [(set (match_operand:DF
0 "gpc_reg_operand" "=d")
6495 (unspec_volatile:DF [(match_operand:SI
1 "const_0_to_3_operand" "n")]
6499 [(set_attr "type" "fp")])
6501 (define_insn "rs6000_mffscdrn"
6502 [(set (match_operand:DF
0 "gpc_reg_operand" "=d")
6503 (unspec_volatile:DF [(const_int
0)] UNSPECV_MFFSCDRN))
6504 (use (match_operand:DF
1 "gpc_reg_operand" "d"))]
6507 [(set_attr "type" "fp")])
6509 (define_expand "rs6000_set_fpscr_rn"
6510 [(use (match_operand:DF
0 "gpc_reg_operand"))
6511 (use (match_operand:SI
1 "reg_or_cint_operand"))]
6514 rtx tmp_df = gen_reg_rtx (DFmode);
6516 /* The floating point rounding control bits are FPSCR[
62:
63]. Put the
6517 new rounding mode bits from operands[
0][
62:
63] into FPSCR[
62:
63]. */
6520 if (const_0_to_3_operand (operands[
1], VOIDmode))
6521 emit_insn (gen_rs6000_mffscrni (tmp_df, operands[
1]));
6524 rtx op1 = convert_to_mode (DImode, operands[
1], false);
6525 rtx src_df = simplify_gen_subreg (DFmode, op1, DImode,
0);
6526 emit_insn (gen_rs6000_mffscrn (tmp_df, src_df));
6528 emit_move_insn (operands[
0], tmp_df);
6532 /* Emulate the behavior of the mffscrni, mffscrn instructions for earlier
6533 ISAs. Return bits
29:
31 (DRN) and bits
56:
63 (VE, OE, UE, ZE, XE, NI,
6534 RN) from the FPSCR. Set the RN field based on the value in operands[
1].
6537 /* Get the current FPSCR fields, bits
29:
31 (DRN) and bits
56:
63 (VE, OE, UE,
6538 ZE, XE, NI, RN) from the FPSCR and return them. */
6540 emit_insn (gen_rs6000_mffs (tmp_df));
6541 rtx orig_df_in_di = simplify_gen_subreg (DImode, tmp_df, DFmode,
0);
6542 rtx tmp_di1 = gen_reg_rtx (DImode);
6543 emit_insn (gen_anddi3 (tmp_di1, orig_df_in_di,
6544 GEN_INT (
0x00000007000000FFULL)));
6545 rtx tmp_rtn = simplify_gen_subreg (DFmode, tmp_di1, DImode,
0);
6546 emit_move_insn (operands[
0], tmp_rtn);
6548 if (CONST_INT_P (operands[
1]))
6550 if ((INTVAL (operands[
1]) &
0x1) ==
0x1)
6551 emit_insn (gen_rs6000_mtfsb1 (GEN_INT (
31)));
6553 emit_insn (gen_rs6000_mtfsb0 (GEN_INT (
31)));
6555 if ((INTVAL (operands[
1]) &
0x2) ==
0x2)
6556 emit_insn (gen_rs6000_mtfsb1 (GEN_INT (
30)));
6558 emit_insn (gen_rs6000_mtfsb0 (GEN_INT (
30)));
6562 /* Extract new RN mode from operand. */
6563 rtx op1 = convert_to_mode (DImode, operands[
1], false);
6564 rtx tmp_rn = gen_reg_rtx (DImode);
6565 emit_insn (gen_anddi3 (tmp_rn, op1, GEN_INT (
3)));
6567 /* Insert the new RN value from tmp_rn into FPSCR bit [
62:
63]. */
6568 rtx tmp_di1 = gen_reg_rtx (DImode);
6569 emit_insn (gen_anddi3 (tmp_di1, orig_df_in_di, GEN_INT (-
4)));
6570 rtx tmp_di2 = gen_reg_rtx (DImode);
6571 emit_insn (gen_iordi3 (tmp_di2, tmp_di1, tmp_rn));
6573 /* Need to write to field k=
15. The fields are [
0:
15]. Hence with
6574 L=
0, W=
0, FLM_i must be equal to
8,
16 = i +
8*(
1-W). FLM is an
6575 8-bit field[
0:
7]. Need to set the bit that corresponds to the
6576 value of i that you want [
0:
7]. */
6577 tmp_df = simplify_gen_subreg (DFmode, tmp_di2, DImode,
0);
6578 emit_insn (gen_rs6000_mtfsf (GEN_INT (
0x01), tmp_df));
6583 (define_expand "rs6000_set_fpscr_drn"
6584 [(match_operand:DI
0 "gpc_reg_operand")]
6587 rtx tmp_df = gen_reg_rtx (DFmode);
6589 /* The decimal floating point rounding control bits are FPSCR[
29:
31]. Put the
6590 new rounding mode bits from operands[
0][
61:
63] into FPSCR[
29:
31]. */
6593 rtx src_df = gen_reg_rtx (DFmode);
6595 emit_insn (gen_ashldi3 (operands[
0], operands[
0], GEN_INT (
32)));
6596 src_df = simplify_gen_subreg (DFmode, operands[
0], DImode,
0);
6597 emit_insn (gen_rs6000_mffscdrn (tmp_df, src_df));
6601 rtx tmp_rn = gen_reg_rtx (DImode);
6602 rtx tmp_di = gen_reg_rtx (DImode);
6604 /* Extract new DRN mode from operand. */
6605 emit_insn (gen_anddi3 (tmp_rn, operands[
0], GEN_INT (
0x7)));
6606 emit_insn (gen_ashldi3 (tmp_rn, tmp_rn, GEN_INT (
32)));
6608 /* Insert new RN mode into FSCPR. */
6609 emit_insn (gen_rs6000_mffs (tmp_df));
6610 tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode,
0);
6611 emit_insn (gen_anddi3 (tmp_di, tmp_di, GEN_INT (
0xFFFFFFF8FFFFFFFFULL)));
6612 emit_insn (gen_iordi3 (tmp_di, tmp_di, tmp_rn));
6614 /* Need to write to field
7. The fields are [
0:
15]. The equation to
6615 select the field is i +
8*(
1-W). Hence with L=
0 and W=
1, need to set
6616 i to
0x1 to get field
7 where i selects the field. */
6617 tmp_df = simplify_gen_subreg (DFmode, tmp_di, DImode,
0);
6618 emit_insn (gen_rs6000_mtfsf_hi (GEN_INT (
0x01), tmp_df));
6623 ;; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6624 ;; rather than (set (subreg:SI (reg)) (fix:SI ...))
6625 ;; because the first makes it clear that operand
0 is not live
6626 ;; before the instruction.
6627 (define_insn "fctiwz_<mode>"
6628 [(set (match_operand:DI
0 "gpc_reg_operand" "=d,wa")
6630 (match_operand:SFDF
1 "gpc_reg_operand" "d,wa"))]
6636 [(set_attr "type" "fp")])
6638 (define_insn "fctiwuz_<mode>"
6639 [(set (match_operand:DI
0 "gpc_reg_operand" "=d,wa")
6640 (unspec:DI [(unsigned_fix:SI
6641 (match_operand:SFDF
1 "gpc_reg_operand" "d,wa"))]
6643 "TARGET_HARD_FLOAT && TARGET_FCTIWUZ"
6647 [(set_attr "type" "fp")])
6649 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6650 ;; since the friz instruction does not truncate the value if the floating
6651 ;; point value is < LONG_MIN or > LONG_MAX.
6652 (define_insn "*friz"
6653 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,wa")
6654 (float:DF (fix:DI (match_operand:DF
1 "gpc_reg_operand" "d,wa"))))]
6655 "TARGET_HARD_FLOAT && TARGET_FPRND
6656 && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
6660 [(set_attr "type" "fp")])
6662 ;; Opitmize converting SF/DFmode to signed SImode and back to SF/DFmode. This
6663 ;; optimization prevents on ISA
2.06 systems and earlier having to store the
6664 ;; value from the FPR/vector unit to the stack, load the value into a GPR, sign
6665 ;; extend it, store it back on the stack from the GPR, load it back into the
6666 ;; FP/vector unit to do the rounding. If we have direct move (ISA
2.07),
6667 ;; disable using store and load to sign/zero extend the value.
6668 (define_insn_and_split "*round32<mode>
2_fprs"
6669 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d")
6671 (fix:SI (match_operand:SFDF
1 "gpc_reg_operand" "d"))))
6672 (clobber (match_scratch:DI
2 "=d"))
6673 (clobber (match_scratch:DI
3 "=d"))]
6675 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6676 && !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
6681 rtx dest = operands[
0];
6682 rtx src = operands[
1];
6683 rtx tmp1 = operands[
2];
6684 rtx tmp2 = operands[
3];
6685 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6687 if (GET_CODE (tmp1) == SCRATCH)
6688 tmp1 = gen_reg_rtx (DImode);
6689 if (GET_CODE (tmp2) == SCRATCH)
6690 tmp2 = gen_reg_rtx (DImode);
6692 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6693 emit_insn (gen_stfiwx (stack, tmp1));
6694 emit_insn (gen_lfiwax (tmp2, stack));
6695 emit_insn (gen_floatdi<mode>
2 (dest, tmp2));
6698 [(set_attr "type" "fpload")
6699 (set_attr "length" "
16")])
6701 (define_insn_and_split "*roundu32<mode>
2_fprs"
6702 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d")
6703 (unsigned_float:SFDF
6704 (unsigned_fix:SI (match_operand:SFDF
1 "gpc_reg_operand" "d"))))
6705 (clobber (match_scratch:DI
2 "=d"))
6706 (clobber (match_scratch:DI
3 "=d"))]
6708 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
6709 && can_create_pseudo_p ()"
6714 rtx dest = operands[
0];
6715 rtx src = operands[
1];
6716 rtx tmp1 = operands[
2];
6717 rtx tmp2 = operands[
3];
6718 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6720 if (GET_CODE (tmp1) == SCRATCH)
6721 tmp1 = gen_reg_rtx (DImode);
6722 if (GET_CODE (tmp2) == SCRATCH)
6723 tmp2 = gen_reg_rtx (DImode);
6725 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6726 emit_insn (gen_stfiwx (stack, tmp1));
6727 emit_insn (gen_lfiwzx (tmp2, stack));
6728 emit_insn (gen_floatdi<mode>
2 (dest, tmp2));
6731 [(set_attr "type" "fpload")
6732 (set_attr "length" "
16")])
6734 ;; No VSX equivalent to fctid
6735 (define_insn "lrint<mode>di2"
6736 [(set (match_operand:DI
0 "gpc_reg_operand" "=d")
6737 (unspec:DI [(match_operand:SFDF
1 "gpc_reg_operand" "<rreg2>")]
6739 "TARGET_HARD_FLOAT && TARGET_FCTID"
6741 [(set_attr "type" "fp")])
6743 (define_expand "lrint<mode>si2"
6744 [(set (match_operand:SI
0 "gpc_reg_operand" "=d")
6745 (unspec:SI [(match_operand:SFDF
1 "gpc_reg_operand" "<rreg2>")]
6747 "TARGET_HARD_FLOAT && TARGET_STFIWX"
6749 /* For those old archs in which SImode can't be hold in float registers,
6750 call lrint<mode>si_di to put the result in DImode then convert it via
6752 if (!TARGET_POPCNTD)
6754 rtx tmp = gen_reg_rtx (DImode);
6755 emit_insn (gen_lrint<mode>si_di (tmp, operands[
1]));
6756 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6757 emit_insn (gen_stfiwx (stack, tmp));
6758 emit_move_insn (operands[
0], stack);
6763 (define_insn "*lrint<mode>si"
6764 [(set (match_operand:SI
0 "gpc_reg_operand" "=d")
6765 (unspec:SI [(match_operand:SFDF
1 "gpc_reg_operand" "<rreg2>")]
6767 "TARGET_HARD_FLOAT && TARGET_POPCNTD"
6769 [(set_attr "type" "fp")])
6771 (define_insn "lrint<mode>si_di"
6772 [(set (match_operand:DI
0 "gpc_reg_operand" "=d")
6773 (unspec:DI [(match_operand:SFDF
1 "gpc_reg_operand" "<rreg2>")]
6775 "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
6777 [(set_attr "type" "fp")])
6779 (define_insn "btrunc<mode>
2"
6780 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
6781 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand" "d,wa")]
6783 "TARGET_HARD_FLOAT && TARGET_FPRND"
6787 [(set_attr "type" "fp")])
6789 (define_insn "ceil<mode>
2"
6790 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
6791 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand" "d,wa")]
6793 "TARGET_HARD_FLOAT && TARGET_FPRND"
6797 [(set_attr "type" "fp")])
6799 (define_insn "floor<mode>
2"
6800 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa")
6801 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand" "d,wa")]
6803 "TARGET_HARD_FLOAT && TARGET_FPRND"
6807 [(set_attr "type" "fp")])
6809 ;; No VSX equivalent to frin
6810 (define_insn "round<mode>
2"
6811 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=<rreg2>")
6812 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand" "<rreg2>")]
6814 "TARGET_HARD_FLOAT && TARGET_FPRND"
6816 [(set_attr "type" "fp")])
6818 (define_insn "*xsrdpi<mode>
2"
6819 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=wa")
6820 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand" "wa")]
6822 "TARGET_HARD_FLOAT && TARGET_VSX"
6824 [(set_attr "type" "fp")])
6826 (define_expand "lround<mode>di2"
6828 (unspec:SFDF [(match_operand:SFDF
1 "gpc_reg_operand")]
6830 (set (match_operand:DI
0 "gpc_reg_operand")
6831 (unspec:DI [(match_dup
2)]
6833 "TARGET_HARD_FLOAT && TARGET_VSX && TARGET_FCTID"
6835 operands[
2] = gen_reg_rtx (<MODE>mode);
6838 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6839 (define_insn "stfiwx"
6840 [(set (match_operand:SI
0 "memory_operand" "=Z,Z")
6841 (unspec:SI [(match_operand:DI
1 "gpc_reg_operand" "d,wa")]
6847 [(set_attr "type" "fpstore")
6848 (set_attr "isa" "*,p8v")])
6850 ;; If we don't have a direct conversion to single precision, don't enable this
6851 ;; conversion for
32-bit without fast math, because we don't have the insn to
6852 ;; generate the fixup swizzle to avoid double rounding problems.
6853 (define_expand "floatsisf2"
6854 [(set (match_operand:SF
0 "gpc_reg_operand")
6855 (float:SF (match_operand:SI
1 "nonimmediate_operand")))]
6857 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6859 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
6861 if (TARGET_FCFIDS && TARGET_LFIWAX)
6863 emit_insn (gen_floatsisf2_lfiwax (operands[
0], operands[
1]));
6866 else if (TARGET_FCFID && TARGET_LFIWAX)
6868 rtx dfreg = gen_reg_rtx (DFmode);
6869 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[
1]));
6870 emit_insn (gen_truncdfsf2 (operands[
0], dfreg));
6875 rtx dreg = operands[
1];
6877 dreg = force_reg (SImode, dreg);
6878 dreg = convert_to_mode (DImode, dreg, false);
6879 emit_insn (gen_floatdisf2 (operands[
0], dreg));
6884 (define_insn "floatdidf2"
6885 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,wa")
6886 (float:DF (match_operand:DI
1 "gpc_reg_operand" "d,wa")))]
6887 "TARGET_FCFID && TARGET_HARD_FLOAT"
6891 [(set_attr "type" "fp")])
6893 (define_insn "floatti<mode>
2"
6894 [(set (match_operand:IEEE128
0 "vsx_register_operand" "=v")
6895 (float:IEEE128 (match_operand:TI
1 "vsx_register_operand" "v")))]
6898 return "xscvsqqp %
0,%
1";
6900 [(set_attr "type" "fp")])
6902 (define_insn "floatunsti<mode>
2"
6903 [(set (match_operand:IEEE128
0 "vsx_register_operand" "=v")
6904 (unsigned_float:IEEE128 (match_operand:TI
1 "vsx_register_operand" "v")))]
6907 return "xscvuqqp %
0,%
1";
6909 [(set_attr "type" "fp")])
6911 (define_insn "fix_trunc<mode>ti2"
6912 [(set (match_operand:TI
0 "vsx_register_operand" "=v")
6913 (fix:TI (match_operand:IEEE128
1 "vsx_register_operand" "v")))]
6916 return "xscvqpsqz %
0,%
1";
6918 [(set_attr "type" "fp")])
6920 (define_insn "fixuns_trunc<mode>ti2"
6921 [(set (match_operand:TI
0 "vsx_register_operand" "=v")
6922 (unsigned_fix:TI (match_operand:IEEE128
1 "vsx_register_operand" "v")))]
6925 return "xscvqpuqz %
0,%
1";
6927 [(set_attr "type" "fp")])
6929 ; Allow the combiner to merge source memory operands to the conversion so that
6930 ; the optimizer/register allocator doesn't try to load the value too early in a
6931 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6932 ; hit. We will split after reload to avoid the trip through the GPRs
6934 (define_insn_and_split "*floatdidf2_mem"
6935 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,wa")
6936 (float:DF (match_operand:DI
1 "memory_operand" "m,Z")))
6937 (clobber (match_scratch:DI
2 "=d,wa"))]
6938 "TARGET_HARD_FLOAT && TARGET_FCFID"
6940 "&& reload_completed"
6941 [(set (match_dup
2) (match_dup
1))
6942 (set (match_dup
0) (float:DF (match_dup
2)))]
6944 [(set_attr "length" "
8")
6945 (set_attr "type" "fpload")])
6947 (define_expand "floatunsdidf2"
6948 [(set (match_operand:DF
0 "gpc_reg_operand")
6950 (match_operand:DI
1 "gpc_reg_operand")))]
6951 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6954 (define_insn "*floatunsdidf2_fcfidu"
6955 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,wa")
6956 (unsigned_float:DF (match_operand:DI
1 "gpc_reg_operand" "d,wa")))]
6957 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
6961 [(set_attr "type" "fp")])
6963 (define_insn_and_split "*floatunsdidf2_mem"
6964 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,wa")
6965 (unsigned_float:DF (match_operand:DI
1 "memory_operand" "m,Z")))
6966 (clobber (match_scratch:DI
2 "=d,wa"))]
6967 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6969 "&& reload_completed"
6970 [(set (match_dup
2) (match_dup
1))
6971 (set (match_dup
0) (unsigned_float:DF (match_dup
2)))]
6973 [(set_attr "length" "
8")
6974 (set_attr "type" "fpload")])
6976 (define_expand "floatdisf2"
6977 [(set (match_operand:SF
0 "gpc_reg_operand")
6978 (float:SF (match_operand:DI
1 "gpc_reg_operand")))]
6979 "TARGET_FCFID && TARGET_HARD_FLOAT
6980 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6984 rtx val = operands[
1];
6985 if (!flag_unsafe_math_optimizations)
6987 rtx label = gen_label_rtx ();
6988 val = gen_reg_rtx (DImode);
6989 emit_insn (gen_floatdisf2_internal2 (val, operands[
1], label));
6992 emit_insn (gen_floatdisf2_internal1 (operands[
0], val));
6997 (define_insn "floatdisf2_fcfids"
6998 [(set (match_operand:SF
0 "gpc_reg_operand" "=f,wa")
6999 (float:SF (match_operand:DI
1 "gpc_reg_operand" "d,wa")))]
7000 "TARGET_HARD_FLOAT && TARGET_FCFIDS"
7004 [(set_attr "type" "fp")
7005 (set_attr "isa" "*,p8v")])
7007 (define_insn_and_split "*floatdisf2_mem"
7008 [(set (match_operand:SF
0 "gpc_reg_operand" "=f,wa,wa")
7009 (float:SF (match_operand:DI
1 "memory_operand" "m,m,Z")))
7010 (clobber (match_scratch:DI
2 "=d,d,wa"))]
7011 "TARGET_HARD_FLOAT && TARGET_FCFIDS"
7013 "&& reload_completed"
7016 emit_move_insn (operands[
2], operands[
1]);
7017 emit_insn (gen_floatdisf2_fcfids (operands[
0], operands[
2]));
7020 [(set_attr "length" "
8")
7021 (set_attr "isa" "*,p8v,p8v")])
7023 ;; This is not IEEE compliant if rounding mode is "round to nearest".
7024 ;; If the DI->DF conversion is inexact, then it's possible to suffer
7025 ;; from double rounding.
7026 ;; Instead of creating a new cpu type for two FP operations, just use fp
7027 (define_insn_and_split "floatdisf2_internal1"
7028 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
7029 (float:SF (match_operand:DI
1 "gpc_reg_operand" "d")))
7030 (clobber (match_scratch:DF
2 "=d"))]
7031 "TARGET_FCFID && TARGET_HARD_FLOAT && !TARGET_FCFIDS"
7033 "&& reload_completed"
7035 (float:DF (match_dup
1)))
7037 (float_truncate:SF (match_dup
2)))]
7039 [(set_attr "length" "
8")
7040 (set_attr "type" "fp")])
7042 ;; Twiddles bits to avoid double rounding.
7043 ;; Bits that might be truncated when converting to DFmode are replaced
7044 ;; by a bit that won't be lost at that stage, but is below the SFmode
7045 ;; rounding position.
7046 (define_expand "floatdisf2_internal2"
7047 [(parallel [(set (match_dup
3) (ashiftrt:DI (match_operand:DI
1 "")
7049 (clobber (reg:DI CA_REGNO))])
7050 (set (match_operand:DI
0 "") (and:DI (match_dup
1)
7052 (set (match_dup
3) (plus:DI (match_dup
3)
7054 (set (match_dup
0) (plus:DI (match_dup
0)
7056 (set (match_dup
4) (compare:CCUNS (match_dup
3)
7058 (set (match_dup
0) (ior:DI (match_dup
0)
7060 (set (match_dup
0) (and:DI (match_dup
0)
7062 (set (pc) (if_then_else (geu (match_dup
4) (const_int
0))
7063 (label_ref (match_operand:DI
2 ""))
7065 (set (match_dup
0) (match_dup
1))]
7066 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && !TARGET_FCFIDS"
7068 operands[
3] = gen_reg_rtx (DImode);
7069 operands[
4] = gen_reg_rtx (CCUNSmode);
7072 (define_expand "floatunsdisf2"
7073 [(set (match_operand:SF
0 "gpc_reg_operand")
7074 (unsigned_float:SF (match_operand:DI
1 "gpc_reg_operand")))]
7075 "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
7078 (define_insn "floatunsdisf2_fcfidus"
7079 [(set (match_operand:SF
0 "gpc_reg_operand" "=f,wa")
7080 (unsigned_float:SF (match_operand:DI
1 "gpc_reg_operand" "d,wa")))]
7081 "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
7085 [(set_attr "type" "fp")
7086 (set_attr "isa" "*,p8v")])
7088 (define_insn_and_split "*floatunsdisf2_mem"
7089 [(set (match_operand:SF
0 "gpc_reg_operand" "=f,wa,wa")
7090 (unsigned_float:SF (match_operand:DI
1 "memory_operand" "m,m,Z")))
7091 (clobber (match_scratch:DI
2 "=d,d,wa"))]
7092 "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
7094 "&& reload_completed"
7097 emit_move_insn (operands[
2], operands[
1]);
7098 emit_insn (gen_floatunsdisf2_fcfidus (operands[
0], operands[
2]));
7101 [(set_attr "type" "fpload")
7102 (set_attr "length" "
8")
7103 (set_attr "isa" "*,p8v,p8v")])
7105 ;; int fegetround(void)
7107 ;; This expansion for the C99 function only expands for compatible
7108 ;; target libcs, because it needs to return one of FE_DOWNWARD,
7109 ;; FE_TONEAREST, FE_TOWARDZERO or FE_UPWARD with the values as defined
7110 ;; by the target libc, and since the libc is free to choose the values
7111 ;; (and they may differ from the hardware) and the expander needs to
7112 ;; know then beforehand, this expanded only expands for target libcs
7113 ;; that it can handle the values is knows.
7114 ;; Because of these restriction, this only expands on the desired
7115 ;; case and fallback to a call to libc otherwise.
7116 (define_expand "fegetroundsi"
7117 [(set (match_operand:SI
0 "gpc_reg_operand")
7118 (unspec_volatile:SI [(const_int
0)] UNSPECV_MFFSL))]
7124 rtx tmp_df = gen_reg_rtx (DFmode);
7125 emit_insn (gen_rs6000_mffsl (tmp_df));
7127 rtx tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode,
0);
7128 rtx tmp_di_2 = gen_reg_rtx (DImode);
7129 emit_insn (gen_anddi3 (tmp_di_2, tmp_di, GEN_INT (
3)));
7130 rtx tmp_si = gen_reg_rtx (SImode);
7131 tmp_si = gen_lowpart (SImode, tmp_di_2);
7132 emit_move_insn (operands[
0], tmp_si);
7136 ;; int feclearexcept(int excepts)
7138 ;; This expansion for the C99 function only works when EXCEPTS is a
7139 ;; constant known at compile time and specifies any one of
7140 ;; FE_INEXACT, FE_DIVBYZERO, FE_UNDERFLOW and FE_OVERFLOW flags.
7141 ;; It doesn't handle values out of range, and always returns
0.
7142 ;; Note that FE_INVALID is unsupported because it maps to more than
7143 ;; one bit of the FPSCR register.
7144 ;; The FE_* are defined in the target libc, and since they are free to
7145 ;; choose the values and the expand needs to know them beforehand,
7146 ;; this expander only expands for target libcs that it can handle the
7148 ;; Because of these restrictions, this only expands on the desired
7149 ;; cases and fallback to a call to libc on any other case.
7150 (define_expand "feclearexceptsi"
7151 [(use (match_operand:SI
1 "const_int_operand" "n"))
7152 (set (match_operand:SI
0 "gpc_reg_operand")
7159 unsigned int fe = INTVAL (operands[
1]);
7160 if (fe != (fe &
0x1e000000))
7163 if (fe &
0x02000000) /* FE_INEXACT */
7164 emit_insn (gen_rs6000_mtfsb0 (gen_rtx_CONST_INT (SImode,
6)));
7165 if (fe &
0x04000000) /* FE_DIVBYZERO */
7166 emit_insn (gen_rs6000_mtfsb0 (gen_rtx_CONST_INT (SImode,
5)));
7167 if (fe &
0x08000000) /* FE_UNDERFLOW */
7168 emit_insn (gen_rs6000_mtfsb0 (gen_rtx_CONST_INT (SImode,
4)));
7169 if (fe &
0x10000000) /* FE_OVERFLOW */
7170 emit_insn (gen_rs6000_mtfsb0 (gen_rtx_CONST_INT (SImode,
3)));
7172 emit_move_insn (operands[
0], const0_rtx);
7176 ;; int feraiseexcept(int excepts)
7178 ;; This expansion for the C99 function only works when excepts is a
7179 ;; constant known at compile time and specifies any one of
7180 ;; FE_INEXACT, FE_DIVBYZERO, FE_UNDERFLOW and FE_OVERFLOW flags.
7181 ;; It doesn't handle values out of range, and always returns
0.
7182 ;; Note that FE_INVALID is unsupported because it maps to more than
7183 ;; one bit of the FPSCR register.
7184 ;; The FE_* are defined in the target libc, and since they are free to
7185 ;; choose the values and the expand needs to know them beforehand,
7186 ;; this expander only expands for target libcs that it can handle the
7188 ;; Because of these restrictions, this only expands on the desired
7189 ;; cases and fallback to a call to libc on any other case.
7190 (define_expand "feraiseexceptsi"
7191 [(use (match_operand:SI
1 "const_int_operand" "n"))
7192 (set (match_operand:SI
0 "gpc_reg_operand")
7199 unsigned int fe = INTVAL (operands[
1]);
7200 if (fe != (fe &
0x1e000000))
7203 if (fe &
0x02000000) /* FE_INEXACT */
7204 emit_insn (gen_rs6000_mtfsb1 (gen_rtx_CONST_INT (SImode,
6)));
7205 if (fe &
0x04000000) /* FE_DIVBYZERO */
7206 emit_insn (gen_rs6000_mtfsb1 (gen_rtx_CONST_INT (SImode,
5)));
7207 if (fe &
0x08000000) /* FE_UNDERFLOW */
7208 emit_insn (gen_rs6000_mtfsb1 (gen_rtx_CONST_INT (SImode,
4)));
7209 if (fe &
0x10000000) /* FE_OVERFLOW */
7210 emit_insn (gen_rs6000_mtfsb1 (gen_rtx_CONST_INT (SImode,
3)));
7212 emit_move_insn (operands[
0], const0_rtx);
7216 ;; Define the TImode operations that can be done in a small number
7217 ;; of instructions. The & constraints are to prevent the register
7218 ;; allocator from allocating registers that overlap with the inputs
7219 ;; (for example, having an input in
7,
8 and an output in
6,
7). We
7220 ;; also allow for the output being the same as one of the inputs.
7222 (define_expand "addti3"
7223 [(set (match_operand:TI
0 "gpc_reg_operand")
7224 (plus:TI (match_operand:TI
1 "gpc_reg_operand")
7225 (match_operand:TI
2 "reg_or_short_operand")))]
7228 rtx lo0 = gen_lowpart (DImode, operands[
0]);
7229 rtx lo1 = gen_lowpart (DImode, operands[
1]);
7230 rtx lo2 = gen_lowpart (DImode, operands[
2]);
7231 rtx hi0 = gen_highpart (DImode, operands[
0]);
7232 rtx hi1 = gen_highpart (DImode, operands[
1]);
7233 rtx hi2 = gen_highpart_mode (DImode, TImode, operands[
2]);
7235 if (!reg_or_short_operand (lo2, DImode))
7236 lo2 = force_reg (DImode, lo2);
7237 if (!adde_operand (hi2, DImode))
7238 hi2 = force_reg (DImode, hi2);
7240 emit_insn (gen_adddi3_carry (lo0, lo1, lo2));
7241 emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2));
7245 (define_expand "subti3"
7246 [(set (match_operand:TI
0 "gpc_reg_operand")
7247 (minus:TI (match_operand:TI
1 "reg_or_short_operand")
7248 (match_operand:TI
2 "gpc_reg_operand")))]
7251 rtx lo0 = gen_lowpart (DImode, operands[
0]);
7252 rtx lo1 = gen_lowpart (DImode, operands[
1]);
7253 rtx lo2 = gen_lowpart (DImode, operands[
2]);
7254 rtx hi0 = gen_highpart (DImode, operands[
0]);
7255 rtx hi1 = gen_highpart_mode (DImode, TImode, operands[
1]);
7256 rtx hi2 = gen_highpart (DImode, operands[
2]);
7258 if (!reg_or_short_operand (lo1, DImode))
7259 lo1 = force_reg (DImode, lo1);
7260 if (!adde_operand (hi1, DImode))
7261 hi1 = force_reg (DImode, hi1);
7263 emit_insn (gen_subfdi3_carry (lo0, lo2, lo1));
7264 emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1));
7268 ;;
128-bit logical operations expanders
7270 (define_expand "and<mode>
3"
7271 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7272 (and:BOOL_128 (match_operand:BOOL_128
1 "vlogical_operand")
7273 (match_operand:BOOL_128
2 "vlogical_operand")))]
7277 (define_expand "ior<mode>
3"
7278 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7279 (ior:BOOL_128 (match_operand:BOOL_128
1 "vlogical_operand")
7280 (match_operand:BOOL_128
2 "vlogical_operand")))]
7284 (define_expand "xor<mode>
3"
7285 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7286 (xor:BOOL_128 (match_operand:BOOL_128
1 "vlogical_operand")
7287 (match_operand:BOOL_128
2 "vlogical_operand")))]
7291 (define_expand "nor<mode>
3"
7292 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7294 (not:BOOL_128 (match_operand:BOOL_128
1 "vlogical_operand"))
7295 (not:BOOL_128 (match_operand:BOOL_128
2 "vlogical_operand"))))]
7299 (define_expand "andc<mode>
3"
7300 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7302 (not:BOOL_128 (match_operand:BOOL_128
2 "vlogical_operand"))
7303 (match_operand:BOOL_128
1 "vlogical_operand")))]
7307 ;; Power8 vector logical instructions.
7308 (define_expand "eqv<mode>
3"
7309 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7311 (xor:BOOL_128 (match_operand:BOOL_128
1 "vlogical_operand")
7312 (match_operand:BOOL_128
2 "vlogical_operand"))))]
7313 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7316 ;; Rewrite nand into canonical form
7317 (define_expand "nand<mode>
3"
7318 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7320 (not:BOOL_128 (match_operand:BOOL_128
1 "vlogical_operand"))
7321 (not:BOOL_128 (match_operand:BOOL_128
2 "vlogical_operand"))))]
7322 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7325 ;; The canonical form is to have the negated element first, so we need to
7326 ;; reverse arguments.
7327 (define_expand "orc<mode>
3"
7328 [(set (match_operand:BOOL_128
0 "vlogical_operand")
7330 (not:BOOL_128 (match_operand:BOOL_128
2 "vlogical_operand"))
7331 (match_operand:BOOL_128
1 "vlogical_operand")))]
7332 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
7335 ;;
128-bit logical operations insns and split operations
7336 (define_insn_and_split "*and<mode>
3_internal"
7337 [(set (match_operand:BOOL_128
0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7339 (match_operand:BOOL_128
1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7340 (match_operand:BOOL_128
2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
7343 if (TARGET_VSX && vsx_register_operand (operands[
0], <MODE>mode))
7344 return "xxland %x0,%x1,%x2";
7346 if (TARGET_ALTIVEC && altivec_register_operand (operands[
0], <MODE>mode))
7347 return "vand %
0,%
1,%
2";
7351 "reload_completed && int_reg_operand (operands[
0], <MODE>mode)"
7354 rs6000_split_logical (operands, AND, false, false, false);
7359 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7360 (const_string "veclogical")
7361 (const_string "integer")))
7362 (set (attr "length")
7364 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7367 (match_test "TARGET_POWERPC64")
7369 (const_string "
16"))))])
7372 (define_insn_and_split "*bool<mode>
3_internal"
7373 [(set (match_operand:BOOL_128
0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7374 (match_operator:BOOL_128
3 "boolean_or_operator"
7375 [(match_operand:BOOL_128
1 "vlogical_operand" "%<BOOL_REGS_OP1>")
7376 (match_operand:BOOL_128
2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
7379 if (TARGET_VSX && vsx_register_operand (operands[
0], <MODE>mode))
7380 return "xxl%q3 %x0,%x1,%x2";
7382 if (TARGET_ALTIVEC && altivec_register_operand (operands[
0], <MODE>mode))
7383 return "v%q3 %
0,%
1,%
2";
7387 "reload_completed && int_reg_operand (operands[
0], <MODE>mode)"
7390 rs6000_split_logical (operands, GET_CODE (operands[
3]), false, false, false);
7395 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7396 (const_string "veclogical")
7397 (const_string "integer")))
7398 (set (attr "length")
7400 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7403 (match_test "TARGET_POWERPC64")
7405 (const_string "
16"))))])
7408 (define_insn_and_split "*boolc<mode>
3_internal1"
7409 [(set (match_operand:BOOL_128
0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7410 (match_operator:BOOL_128
3 "boolean_operator"
7412 (match_operand:BOOL_128
2 "vlogical_operand" "<BOOL_REGS_OP2>"))
7413 (match_operand:BOOL_128
1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
7414 "TARGET_P8_VECTOR || (GET_CODE (operands[
3]) == AND)"
7416 if (TARGET_VSX && vsx_register_operand (operands[
0], <MODE>mode))
7417 return "xxl%q3 %x0,%x1,%x2";
7419 if (TARGET_ALTIVEC && altivec_register_operand (operands[
0], <MODE>mode))
7420 return "v%q3 %
0,%
1,%
2";
7424 "(TARGET_P8_VECTOR || (GET_CODE (operands[
3]) == AND))
7425 && reload_completed && int_reg_operand (operands[
0], <MODE>mode)"
7428 rs6000_split_logical (operands, GET_CODE (operands[
3]), false, false, true);
7433 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7434 (const_string "veclogical")
7435 (const_string "integer")))
7436 (set (attr "length")
7438 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7441 (match_test "TARGET_POWERPC64")
7443 (const_string "
16"))))])
7445 (define_insn_and_split "*boolc<mode>
3_internal2"
7446 [(set (match_operand:TI2
0 "int_reg_operand" "=&r,r,r")
7447 (match_operator:TI2
3 "boolean_operator"
7449 (match_operand:TI2
2 "int_reg_operand" "r,
0,r"))
7450 (match_operand:TI2
1 "int_reg_operand" "r,r,
0")]))]
7451 "!TARGET_P8_VECTOR && (GET_CODE (operands[
3]) != AND)"
7453 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[
3]) != AND)"
7456 rs6000_split_logical (operands, GET_CODE (operands[
3]), false, false, true);
7459 [(set_attr "type" "integer")
7460 (set (attr "length")
7462 (match_test "TARGET_POWERPC64")
7464 (const_string "
16")))])
7467 (define_insn_and_split "*boolcc<mode>
3_internal1"
7468 [(set (match_operand:BOOL_128
0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7469 (match_operator:BOOL_128
3 "boolean_operator"
7471 (match_operand:BOOL_128
1 "vlogical_operand" "<BOOL_REGS_OP1>"))
7473 (match_operand:BOOL_128
2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
7474 "TARGET_P8_VECTOR || (GET_CODE (operands[
3]) == AND)"
7476 if (TARGET_VSX && vsx_register_operand (operands[
0], <MODE>mode))
7477 return "xxl%q3 %x0,%x1,%x2";
7479 if (TARGET_ALTIVEC && altivec_register_operand (operands[
0], <MODE>mode))
7480 return "v%q3 %
0,%
1,%
2";
7484 "(TARGET_P8_VECTOR || (GET_CODE (operands[
3]) == AND))
7485 && reload_completed && int_reg_operand (operands[
0], <MODE>mode)"
7488 rs6000_split_logical (operands, GET_CODE (operands[
3]), false, true, true);
7493 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7494 (const_string "veclogical")
7495 (const_string "integer")))
7496 (set (attr "length")
7498 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7501 (match_test "TARGET_POWERPC64")
7503 (const_string "
16"))))])
7505 (define_insn_and_split "*boolcc<mode>
3_internal2"
7506 [(set (match_operand:TI2
0 "int_reg_operand" "=&r,r,r")
7507 (match_operator:TI2
3 "boolean_operator"
7509 (match_operand:TI2
1 "int_reg_operand" "r,
0,r"))
7511 (match_operand:TI2
2 "int_reg_operand" "r,r,
0"))]))]
7512 "!TARGET_P8_VECTOR && (GET_CODE (operands[
3]) != AND)"
7514 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[
3]) != AND)"
7517 rs6000_split_logical (operands, GET_CODE (operands[
3]), false, true, true);
7520 [(set_attr "type" "integer")
7521 (set (attr "length")
7523 (match_test "TARGET_POWERPC64")
7525 (const_string "
16")))])
7529 (define_insn_and_split "*eqv<mode>
3_internal1"
7530 [(set (match_operand:BOOL_128
0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7533 (match_operand:BOOL_128
1 "vlogical_operand" "<BOOL_REGS_OP1>")
7534 (match_operand:BOOL_128
2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
7537 if (vsx_register_operand (operands[
0], <MODE>mode))
7538 return "xxleqv %x0,%x1,%x2";
7542 "TARGET_P8_VECTOR && reload_completed
7543 && int_reg_operand (operands[
0], <MODE>mode)"
7546 rs6000_split_logical (operands, XOR, true, false, false);
7551 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7552 (const_string "veclogical")
7553 (const_string "integer")))
7554 (set (attr "length")
7556 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7559 (match_test "TARGET_POWERPC64")
7561 (const_string "
16"))))])
7563 (define_insn_and_split "*eqv<mode>
3_internal2"
7564 [(set (match_operand:TI2
0 "int_reg_operand" "=&r,r,r")
7567 (match_operand:TI2
1 "int_reg_operand" "r,
0,r")
7568 (match_operand:TI2
2 "int_reg_operand" "r,r,
0"))))]
7571 "reload_completed && !TARGET_P8_VECTOR"
7574 rs6000_split_logical (operands, XOR, true, false, false);
7577 [(set_attr "type" "integer")
7578 (set (attr "length")
7580 (match_test "TARGET_POWERPC64")
7582 (const_string "
16")))])
7584 ;;
128-bit one's complement
7585 (define_insn_and_split "one_cmpl<mode>
2"
7586 [(set (match_operand:BOOL_128
0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
7588 (match_operand:BOOL_128
1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
7591 if (TARGET_VSX && vsx_register_operand (operands[
0], <MODE>mode))
7592 return "xxlnor %x0,%x1,%x1";
7594 if (TARGET_ALTIVEC && altivec_register_operand (operands[
0], <MODE>mode))
7595 return "vnor %
0,%
1,%
1";
7599 "reload_completed && int_reg_operand (operands[
0], <MODE>mode)"
7602 rs6000_split_logical (operands, NOT, false, false, false);
7607 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7608 (const_string "veclogical")
7609 (const_string "integer")))
7610 (set (attr "length")
7612 (match_test "vsx_register_operand (operands[
0], <MODE>mode)")
7615 (match_test "TARGET_POWERPC64")
7617 (const_string "
16"))))])
7620 ;; Now define ways of moving data around.
7622 ;; Set up a register with a value from the GOT table
7624 (define_expand "movsi_got"
7625 [(set (match_operand:SI
0 "gpc_reg_operand")
7626 (unspec:SI [(match_operand:SI
1 "got_operand")
7627 (match_dup
2)] UNSPEC_MOVSI_GOT))]
7628 "DEFAULT_ABI == ABI_V4 && flag_pic ==
1"
7630 if (GET_CODE (operands[
1]) == CONST)
7632 rtx offset = const0_rtx;
7633 HOST_WIDE_INT value;
7635 operands[
1] = eliminate_constant_term (XEXP (operands[
1],
0), &offset);
7636 value = INTVAL (offset);
7639 rtx tmp = (!can_create_pseudo_p ()
7641 : gen_reg_rtx (Pmode));
7642 emit_insn (gen_movsi_got (tmp, operands[
1]));
7643 emit_insn (gen_addsi3 (operands[
0], tmp, offset));
7648 operands[
2] = rs6000_got_register (operands[
1]);
7651 (define_insn "*movsi_got_internal"
7652 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7653 (unspec:SI [(match_operand:SI
1 "got_no_const_operand" "")
7654 (match_operand:SI
2 "gpc_reg_operand" "b")]
7656 "DEFAULT_ABI == ABI_V4 && flag_pic ==
1"
7657 "lwz %
0,%a1@got(%
2)"
7658 [(set_attr "type" "load")])
7660 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7661 ;; didn't get allocated to a hard register.
7663 [(set (match_operand:SI
0 "gpc_reg_operand")
7664 (unspec:SI [(match_operand:SI
1 "got_no_const_operand")
7665 (match_operand:SI
2 "memory_operand")]
7667 "DEFAULT_ABI == ABI_V4
7669 && reload_completed"
7670 [(set (match_dup
0) (match_dup
2))
7671 (set (match_dup
0) (unspec:SI [(match_dup
1)(match_dup
0)]
7676 ;; LWZ LFIWZX LXSIWZX
7677 ;; STW STFIWX STXSIWX
7679 ;; XXLOR XXSPLTIB
0 XXSPLTIB -
1 VSPLTISW
7680 ;; XXLXOR
0 XXLORC -
1 P9 const
7684 (define_insn "*movsi_internal1"
7685 [(set (match_operand:SI
0 "nonimmediate_operand"
7694 (match_operand:SI
1 "input_operand"
7703 "gpc_reg_operand (operands[
0], SImode)
7704 || gpc_reg_operand (operands[
1], SImode)"
7733 load, fpload, fpload,
7734 store, fpstore, fpstore,
7736 veclogical, vecsimple, vecsimple, vecsimple,
7737 veclogical, veclogical, vecsimple,
7759 ;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
7760 ;; (set (reg:SI ...) (subreg:SI (reg:SF ...)
0))
7762 ;; Because SF values are actually stored as DF values within the vector
7763 ;; registers, we need to convert the value to the vector SF format when
7764 ;; we need to use the bits in a union or similar cases. We only need
7765 ;; to do this transformation when the value is a vector register. Loads,
7766 ;; stores, and transfers within GPRs are assumed to be safe.
7768 ;; This is a more general case of reload_gpr_from_vsxsf. That insn must have
7769 ;; no alternatives, because the call is created as part of secondary_reload,
7770 ;; and operand #
2's register class is used to allocate the temporary register.
7771 ;; This function is called before reload, and it creates the temporary as
7774 ;; MR LWZ LFIWZX LXSIWZX STW
7775 ;; STFS STXSSP STXSSPX VSX->GPR VSX->VSX
7778 (define_insn_and_split "movsi_from_sf"
7779 [(set (match_operand:SI
0 "nonimmediate_operand"
7780 "=r, r, ?*d, ?*v, m,
7783 (unspec:SI [(match_operand:SF
1 "input_operand"
7788 (clobber (match_scratch:V4SF
2
7792 "TARGET_NO_SF_SUBREG
7793 && (register_operand (operands[
0], SImode)
7794 || register_operand (operands[
1], SFmode))"
7807 "&& reload_completed
7808 && int_reg_operand (operands[
0], SImode)
7809 && vsx_reg_sfsubreg_ok (operands[
1], SFmode)"
7812 rtx op0 = operands[
0];
7813 rtx op1 = operands[
1];
7814 rtx op2 = operands[
2];
7815 rtx op0_di = gen_rtx_REG (DImode, reg_or_subregno (op0));
7816 rtx op2_si = gen_rtx_REG (SImode, reg_or_subregno (op2));
7818 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
7819 emit_insn (gen_zero_extendsidi2 (op0_di, op2_si));
7823 "*, load, fpload, fpload, store,
7824 fpstore, fpstore, fpstore, mfvsr, fp,
7832 *, p9v, p8v, p8v, p8v,
7835 ;; movsi_from_sf with zero extension
7837 ;; RLDICL LWZ LFIWZX LXSIWZX VSX->GPR
7840 (define_insn_and_split "*movdi_from_sf_zero_ext"
7841 [(set (match_operand:DI
0 "gpc_reg_operand"
7842 "=r, r, ?*d, ?*v, r,
7845 (unspec:SI [(match_operand:SF
1 "input_operand"
7848 UNSPEC_SI_FROM_SF)))
7849 (clobber (match_scratch:V4SF
2
7852 "TARGET_DIRECT_MOVE_64BIT
7853 && (register_operand (operands[
0], DImode)
7854 || register_operand (operands[
1], SImode))"
7863 "&& reload_completed
7864 && register_operand (operands[
0], DImode)
7865 && vsx_reg_sfsubreg_ok (operands[
1], SFmode)"
7868 rtx op0 = operands[
0];
7869 rtx op1 = operands[
1];
7870 rtx op2 = operands[
2];
7871 rtx op2_si = gen_rtx_REG (SImode, reg_or_subregno (op2));
7873 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
7874 emit_insn (gen_zero_extendsidi2 (op0, op2_si));
7878 "*, load, fpload, fpload, two,
7884 "*, *, p8v, p8v, p8v,
7887 ;; Like movsi_from_sf, but combine a convert from DFmode to SFmode before
7888 ;; moving it to SImode. We cannot do a SFmode store without having to do the
7889 ;; conversion explicitly since that doesn't work in most cases if the input
7890 ;; isn't representable as SF. Use XSCVDPSP instead of XSCVDPSPN, since the
7891 ;; former handles cases where the input will not fit in a SFmode, and the
7892 ;; latter assumes the value has already been rounded.
7893 (define_insn "*movsi_from_df"
7894 [(set (match_operand:SI
0 "gpc_reg_operand" "=wa")
7895 (unspec:SI [(float_truncate:SF
7896 (match_operand:DF
1 "gpc_reg_operand" "wa"))]
7897 UNSPEC_SI_FROM_SF))]
7898 "TARGET_NO_SF_SUBREG"
7900 [(set_attr "type" "fp")])
7903 (define_code_iterator eqne [eq ne])
7905 ;; "i == C" ==> "rotl(i,N) == rotl(C,N)"
7906 (define_insn_and_split "*rotate_on_cmpdi"
7908 (if_then_else (eqne (match_operand:DI
1 "gpc_reg_operand" "r")
7909 (match_operand:DI
2 "const_int_operand" "n"))
7910 (label_ref (match_operand
0 ""))
7912 (clobber (match_scratch:DI
3 "=r"))
7913 (clobber (match_scratch:CCUNS
4 "=y"))]
7914 "TARGET_POWERPC64 && num_insns_constant (operands[
2], DImode) >
1
7915 && (can_be_rotated_to_positive_16bits (INTVAL (operands[
2]))
7916 || can_be_rotated_to_negative_15bits (INTVAL (operands[
2])))"
7922 unsigned HOST_WIDE_INT C = INTVAL (operands[
2]);
7926 if (!can_be_rotated_to_lowbits (C,
16, &rot))
7930 bool res = can_be_rotated_to_lowbits (~C,
15, &rot);
7934 rtx n = GEN_INT (rot);
7936 /* i' = rotl (i, n) */
7937 rtx op0 = can_create_pseudo_p () ? gen_reg_rtx (DImode) : operands[
3];
7938 emit_insn (gen_rtx_SET (op0, gen_rtx_ROTATE (DImode, operands[
1], n)));
7940 /* C' = rotl (C, n) */
7941 rtx op1 = GEN_INT ((C << rot) | (C >> (HOST_BITS_PER_WIDE_INT - rot)));
7944 machine_mode comp_mode = sgn ? CCmode : CCUNSmode;
7945 rtx cc = can_create_pseudo_p () ? gen_reg_rtx (comp_mode) : operands[
4];
7946 PUT_MODE (cc, comp_mode);
7947 emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (comp_mode, op0, op1)));
7948 rtx cmp = gen_rtx_<eqne:CODE> (CCmode, cc, const0_rtx);
7949 rtx loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[
0]);
7950 emit_jump_insn (gen_rtx_SET (pc_rtx,
7951 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
7954 /* Keep the probability info for the prediction of the branch insn. */
7955 rtx note = find_reg_note (curr_insn, REG_BR_PROB,
0);
7958 profile_probability prob
7959 = profile_probability::from_reg_br_prob_note (XINT (note,
0));
7961 add_reg_br_prob_note (get_last_insn (), prob);
7967 ;; Split a load of a large constant into the appropriate two-insn
7971 [(set (match_operand:SI
0 "gpc_reg_operand")
7972 (match_operand:SI
1 "const_int_operand"))]
7973 "num_insns_constant (operands[
1], SImode) >
1"
7976 if (rs6000_emit_set_const (operands[
0], operands[
1]))
7982 ;; Split loading -
128.
.127 to use XXSPLITB and VEXTSW2D
7984 [(set (match_operand:DI
0 "altivec_register_operand")
7985 (match_operand:DI
1 "xxspltib_constant_split"))]
7986 "TARGET_P9_VECTOR && reload_completed"
7989 rtx op0 = operands[
0];
7990 rtx op1 = operands[
1];
7991 int r = REGNO (op0);
7992 rtx op0_v16qi = gen_rtx_REG (V16QImode, r);
7994 emit_insn (gen_xxspltib_v16qi (op0_v16qi, op1));
7995 emit_insn (gen_vsx_sign_extend_v16qi_si (operands[
0], op0_v16qi));
7999 (define_insn "*mov<mode>_internal2"
8000 [(set (match_operand:CC
2 "cc_reg_operand" "=y,x,?y")
8001 (compare:CC (match_operand:WORD
1 "gpc_reg_operand" "
0,r,r")
8003 (set (match_operand:WORD
0 "gpc_reg_operand" "=r,r,r") (match_dup
1))]
8009 [(set_attr "type" "cmp,logical,cmp")
8010 (set_attr "dot" "yes")
8011 (set_attr "length" "
4,
4,
8")])
8014 [(set (match_operand:CC
2 "cc_reg_operand")
8015 (compare:CC (match_operand:WORD
1 "int_reg_operand")
8017 (set (match_operand:WORD
0 "int_reg_operand")
8019 "!cc_reg_not_cr0_operand (operands[
2], CCmode)"
8020 [(parallel [(set (match_operand:CC
2 "cc_reg_operand" "=x")
8021 (compare:CC (match_operand:WORD
1 "int_reg_operand" "r")
8023 (set (match_operand:WORD
0 "int_reg_operand" "=r")
8029 [(set (match_operand:WORD
0 "int_reg_operand")
8030 (match_operand:WORD
1 "int_reg_operand"))
8031 (set (match_operand:CC
2 "cc_reg_operand")
8032 (compare:CC (match_dup
1)
8034 "!cc_reg_not_cr0_operand (operands[
2], CCmode)"
8035 [(parallel [(set (match_operand:CC
2 "cc_reg_operand" "=x")
8036 (compare:CC (match_operand:GPR
1 "int_reg_operand" "r")
8038 (set (match_operand:WORD
0 "int_reg_operand" "=r")
8044 [(set (match_operand:CC
2 "cc_reg_not_cr0_operand")
8045 (compare:CC (match_operand:WORD
1 "gpc_reg_operand")
8047 (set (match_operand:WORD
0 "gpc_reg_operand") (match_dup
1))]
8049 [(set (match_dup
0) (match_dup
1))
8051 (compare:CC (match_dup
0)
8055 (define_expand "mov<mode>"
8056 [(set (match_operand:INT
0 "general_operand")
8057 (match_operand:INT
1 "any_operand"))]
8060 rs6000_emit_move (operands[
0], operands[
1], <MODE>mode);
8064 ;; MR LHZ/LBZ LXSI*ZX STH/STB STXSI*X LI
8065 ;; XXLOR load
0 load -
1 VSPLTI* # MFVSRWZ
8066 ;; MTVSRWZ MF%
1 MT%
1 NOP
8067 (define_insn "*mov<mode>_internal"
8068 [(set (match_operand:QHI
0 "nonimmediate_operand"
8069 "=r, r, wa, m, ?Z, r,
8070 wa, wa, wa, v, ?v, r,
8072 (match_operand:QHI
1 "input_operand"
8073 "r, m, ?Z, r, wa, i,
8074 wa, O, wM, wB, wS, wa,
8076 "gpc_reg_operand (operands[
0], <MODE>mode)
8077 || gpc_reg_operand (operands[
1], <MODE>mode)"
8096 "*, load, fpload, store, fpstore, *,
8097 vecsimple, vecperm, vecperm, vecperm, vecperm, mfvsr,
8098 mtvsr, mfjmpr, mtjmpr, *")
8104 "*, *, p9v, *, p9v, *,
8105 p9v, p9v, p9v, p9v, p9v, p9v,
8109 ;; Here is how to move condition codes around. When we store CC data in
8110 ;; an integer register or memory, we store just the high-order
4 bits.
8111 ;; This lets us not shift in the most common case of CR0.
8112 (define_expand "movcc"
8113 [(set (match_operand:CC
0 "nonimmediate_operand")
8114 (match_operand:CC
1 "nonimmediate_operand"))]
8118 (define_mode_iterator CC_any [CC CCUNS CCEQ CCFP])
8120 (define_insn "*movcc_<mode>"
8121 [(set (match_operand:CC_any
0 "nonimmediate_operand"
8122 "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
8123 (match_operand:CC_any
1 "general_operand"
8124 " y,r, r,O,x,y,r,I,*h, r,m,r"))]
8125 "register_operand (operands[
0], <MODE>mode)
8126 || register_operand (operands[
1], <MODE>mode)"
8130 rlwinm %
1,%
1,%F0,
0xffffffff\;mtcrf %R0,%
1\;rlwinm %
1,%
1,%f0,
0xffffffff
8133 mfcr %
0%Q1\;rlwinm %
0,%
0,%f1,
0xf0000000
8140 [(set_attr_alternative "type"
8141 [(const_string "cr_logical")
8142 (const_string "mtcr")
8143 (const_string "mtcr")
8144 (const_string "cr_logical")
8145 (if_then_else (match_test "TARGET_MFCRF")
8146 (const_string "mfcrf") (const_string "mfcr"))
8147 (if_then_else (match_test "TARGET_MFCRF")
8148 (const_string "mfcrf") (const_string "mfcr"))
8149 (const_string "integer")
8150 (const_string "integer")
8151 (const_string "mfjmpr")
8152 (const_string "mtjmpr")
8153 (const_string "load")
8154 (const_string "store")])
8155 (set_attr "length" "*,*,
12,*,*,
8,*,*,*,*,*,*")])
8157 ;; For floating-point, we normally deal with the floating-point registers
8158 ;; unless -msoft-float is used. The sole exception is that parameter passing
8159 ;; can produce floating-point values in fixed-point registers. Unless the
8160 ;; value is a simple constant or already in memory, we deal with this by
8161 ;; allocating memory and copying the value explicitly via that memory location.
8163 ;; Move
32-bit binary/decimal floating point
8164 (define_expand "mov<mode>"
8165 [(set (match_operand:FMOVE32
0 "nonimmediate_operand")
8166 (match_operand:FMOVE32
1 "any_operand"))]
8169 rs6000_emit_move (operands[
0], operands[
1], <MODE>mode);
8174 [(set (match_operand:FMOVE32
0 "gpc_reg_operand")
8175 (match_operand:FMOVE32
1 "const_double_operand"))]
8177 && ((REG_P (operands[
0]) && REGNO (operands[
0]) <=
31)
8178 || (SUBREG_P (operands[
0])
8179 && REG_P (SUBREG_REG (operands[
0]))
8180 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
8181 [(set (match_dup
2) (match_dup
3))]
8185 <real_value_to_target> (*CONST_DOUBLE_REAL_VALUE (operands[
1]), l);
8187 if (! TARGET_POWERPC64)
8188 operands[
2] = operand_subword (operands[
0],
0,
0, <MODE>mode);
8190 operands[
2] = gen_lowpart (SImode, operands[
0]);
8192 operands[
3] = gen_int_mode (l, SImode);
8195 ;; Originally, we tried to keep movsf and movsd common, but the differences
8196 ;; addressing was making it rather difficult to hide with mode attributes. In
8197 ;; particular for SFmode, on ISA
2.07 (power8) systems, having the GPR store
8198 ;; before the VSX stores meant that the register allocator would tend to do a
8199 ;; direct move to the GPR (which involves conversion from scalar to
8200 ;; vector/memory formats) to save values in the traditional Altivec registers,
8201 ;; while SDmode had problems on power6 if the GPR store was not first due to
8202 ;; the power6 not having an integer store operation.
8204 ;; LWZ LFS LXSSP LXSSPX STFS STXSSP
8205 ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
8206 ;; MR MT<x> MF<x> NOP XXSPLTIDP
8208 (define_insn "movsf_hardfloat"
8209 [(set (match_operand:SF
0 "nonimmediate_operand"
8210 "=!r, f, v, wa, m, wY,
8211 Z, m, wa, !r, f, wa,
8212 !r, *c*l, !r, *h, wa")
8213 (match_operand:SF
1 "input_operand"
8217 "(register_operand (operands[
0], SFmode)
8218 || register_operand (operands[
1], SFmode))
8219 && TARGET_HARD_FLOAT
8220 && (TARGET_ALLOW_SF_SUBREG
8221 || valid_sf_si_move (operands[
0], operands[
1], SFmode))"
8234 xscpsgndp %x0,%x1,%x1
8241 "load, fpload, fpload, fpload, fpstore, fpstore,
8242 fpstore, store, veclogical, integer, fpsimple, fpsimple,
8243 *, mtjmpr, mfjmpr, *, vecperm")
8245 "*, *, p9v, p8v, *, p9v,
8248 (set_attr "prefixed"
8253 ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
8254 ;; FMR MR MT%
0 MF%
1 NOP
8255 (define_insn "movsd_hardfloat"
8256 [(set (match_operand:SD
0 "nonimmediate_operand"
8257 "=!r, d, m, ?Z, ?d, ?r,
8258 f, !r, *c*l, !r, *h")
8259 (match_operand:SD
1 "input_operand"
8260 "m, ?Z, r, wx, r, d,
8262 "(register_operand (operands[
0], SDmode)
8263 || register_operand (operands[
1], SDmode))
8264 && TARGET_HARD_FLOAT"
8278 "load, fpload, store, fpstore, mtvsr, mfvsr,
8279 fpsimple, *, mtjmpr, mfjmpr, *")
8281 "*, p7, *, *, p8v, p8v,
8284 ;; MR MT%
0 MF%
0 LWZ STW LI
8285 ;; LIS G-const. F/n-const NOP
8286 (define_insn "*mov<mode>_softfloat"
8287 [(set (match_operand:FMOVE32
0 "nonimmediate_operand"
8288 "=r, *c*l, r, r, m, r,
8291 (match_operand:FMOVE32
1 "input_operand"
8295 "(gpc_reg_operand (operands[
0], <MODE>mode)
8296 || gpc_reg_operand (operands[
1], <MODE>mode))
8297 && TARGET_SOFT_FLOAT"
8310 "*, mtjmpr, mfjmpr, load, store, *,
8317 ;; Like movsf, but adjust a SI value to be used in a SF context, i.e.
8318 ;; (set (reg:SF ...) (subreg:SF (reg:SI ...)
0))
8320 ;; Because SF values are actually stored as DF values within the vector
8321 ;; registers, we need to convert the value to the vector SF format when
8322 ;; we need to use the bits in a union or similar cases. We only need
8323 ;; to do this transformation when the value is a vector register. Loads,
8324 ;; stores, and transfers within GPRs are assumed to be safe.
8326 ;; This is a more general case of reload_vsx_from_gprsf. That insn must have
8327 ;; no alternatives, because the call is created as part of secondary_reload,
8328 ;; and operand #
2's register class is used to allocate the temporary register.
8329 ;; This function is called before reload, and it creates the temporary as
8332 ;; LWZ LFS LXSSP LXSSPX STW STFIWX
8333 ;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
8334 (define_insn_and_split "movsf_from_si"
8335 [(set (match_operand:SF
0 "nonimmediate_operand"
8336 "=!r, f, v, wa, m, Z,
8338 (unspec:SF [(match_operand:SI
1 "input_operand"
8342 (clobber (match_scratch:DI
2
8345 "TARGET_NO_SF_SUBREG
8346 && (register_operand (operands[
0], SFmode)
8347 || register_operand (operands[
1], SImode))"
8360 "&& reload_completed
8361 && vsx_reg_sfsubreg_ok (operands[
0], SFmode)
8362 && int_reg_operand_not_pseudo (operands[
1], SImode)"
8365 rtx op0 = operands[
0];
8366 rtx op1 = operands[
1];
8368 /* Move lowpart
32-bits from register for SFmode. */
8369 if (TARGET_P9_VECTOR)
8371 /* Using mtvsrws;xscvspdpn. */
8372 rtx op0_v = gen_rtx_REG (V4SImode, REGNO (op0));
8373 emit_insn (gen_vsx_splat_v4si (op0_v, op1));
8374 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
8378 rtx op2 = operands[
2];
8379 rtx op1_di = gen_rtx_REG (DImode, REGNO (op1));
8381 /* Using sldi;mtvsrd;xscvspdpn. */
8382 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (
32)));
8383 emit_insn (gen_p8_mtvsrd_sf (op0, op2));
8384 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
8393 "load, fpload, fpload, fpload, store, fpstore,
8394 fpstore, vecfloat, mfvsr, *")
8396 "*, *, p9v, p8v, *, *,
8397 p8v, p8v, p8v, *")])
8399 ;; For extracting high part element from DImode register like:
8400 ;; {%
1:SF=unspec[r122:DI>>
0x20#
0]
86;clobber scratch;}
8401 ;; split it before reload with "and mask" to avoid generating shift right
8402 ;;
32 bit then shift left
32 bit.
8403 (define_insn_and_split "movsf_from_si2_<code>"
8404 [(set (match_operand:SF
0 "gpc_reg_operand" "=wa")
8406 [(match_operator:SI
3 "lowpart_subreg_operator"
8408 (match_operand:DI
1 "input_operand" "r")
8411 (clobber (match_scratch:DI
2 "=r"))]
8412 "TARGET_NO_SF_SUBREG"
8417 if (GET_CODE (operands[
2]) == SCRATCH)
8418 operands[
2] = gen_reg_rtx (DImode);
8420 rtx mask = GEN_INT (HOST_WIDE_INT_M1U <<
32);
8421 emit_insn (gen_anddi3 (operands[
2], operands[
1], mask));
8422 emit_insn (gen_p8_mtvsrd_sf (operands[
0], operands[
2]));
8423 emit_insn (gen_vsx_xscvspdpn_directmove (operands[
0], operands[
0]));
8426 [(set_attr "length" "
12")
8427 (set_attr "type" "vecfloat")
8428 (set_attr "isa" "p8v")])
8430 ;; Move
64-bit binary/decimal floating point
8431 (define_expand "mov<mode>"
8432 [(set (match_operand:FMOVE64
0 "nonimmediate_operand")
8433 (match_operand:FMOVE64
1 "any_operand"))]
8436 rs6000_emit_move (operands[
0], operands[
1], <MODE>mode);
8441 [(set (match_operand:FMOVE64
0 "gpc_reg_operand")
8442 (match_operand:FMOVE64
1 "const_int_operand"))]
8443 "! TARGET_POWERPC64 && reload_completed
8444 && ((REG_P (operands[
0]) && REGNO (operands[
0]) <=
31)
8445 || (SUBREG_P (operands[
0])
8446 && REG_P (SUBREG_REG (operands[
0]))
8447 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
8448 [(set (match_dup
2) (match_dup
4))
8449 (set (match_dup
3) (match_dup
1))]
8451 int endian = (WORDS_BIG_ENDIAN ==
0);
8452 HOST_WIDE_INT value = INTVAL (operands[
1]);
8454 operands[
2] = operand_subword (operands[
0], endian,
0, <MODE>mode);
8455 operands[
3] = operand_subword (operands[
0],
1 - endian,
0, <MODE>mode);
8456 operands[
4] = GEN_INT (value >>
32);
8457 operands[
1] = GEN_INT (sext_hwi (value,
32));
8461 [(set (match_operand:FMOVE64
0 "gpc_reg_operand")
8462 (match_operand:FMOVE64
1 "const_double_operand"))]
8463 "! TARGET_POWERPC64 && reload_completed
8464 && ((REG_P (operands[
0]) && REGNO (operands[
0]) <=
31)
8465 || (SUBREG_P (operands[
0])
8466 && REG_P (SUBREG_REG (operands[
0]))
8467 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
8468 [(set (match_dup
2) (match_dup
4))
8469 (set (match_dup
3) (match_dup
5))]
8471 int endian = (WORDS_BIG_ENDIAN ==
0);
8474 <real_value_to_target> (*CONST_DOUBLE_REAL_VALUE (operands[
1]), l);
8476 operands[
2] = operand_subword (operands[
0], endian,
0, <MODE>mode);
8477 operands[
3] = operand_subword (operands[
0],
1 - endian,
0, <MODE>mode);
8478 operands[
4] = gen_int_mode (l[endian], SImode);
8479 operands[
5] = gen_int_mode (l[
1 - endian], SImode);
8483 [(set (match_operand:FMOVE64
0 "gpc_reg_operand")
8484 (match_operand:FMOVE64
1 "const_double_operand"))]
8485 "TARGET_POWERPC64 && reload_completed
8486 && ((REG_P (operands[
0]) && REGNO (operands[
0]) <=
31)
8487 || (SUBREG_P (operands[
0])
8488 && REG_P (SUBREG_REG (operands[
0]))
8489 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
8490 [(set (match_dup
2) (match_dup
3))]
8492 int endian = (WORDS_BIG_ENDIAN ==
0);
8496 <real_value_to_target> (*CONST_DOUBLE_REAL_VALUE (operands[
1]), l);
8498 operands[
2] = gen_lowpart (DImode, operands[
0]);
8499 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8500 val = ((HOST_WIDE_INT)(unsigned long)l[endian] <<
32
8501 | ((HOST_WIDE_INT)(unsigned long)l[
1 - endian]));
8503 operands[
3] = gen_int_mode (val, DImode);
8506 ;; Don't have reload use general registers to load a constant. It is
8507 ;; less efficient than loading the constant into an FP register, since
8508 ;; it will probably be used there.
8510 ;; The move constraints are ordered to prefer floating point registers before
8511 ;; general purpose registers to avoid doing a store and a load to get the value
8512 ;; into a floating point register when it is needed for a floating point
8513 ;; operation. Prefer traditional floating point registers over VSX registers,
8514 ;; since the D-form version of the memory instructions does not need a GPR for
8515 ;; reloading. ISA
3.0 (power9) adds D-form addressing for scalars to Altivec
8518 ;; If we have FPR registers, rs6000_emit_move has moved all constants to memory,
8519 ;; except for
0.0 which can be created on VSX with an xor instruction.
8521 ;; STFD LFD FMR LXSD STXSD
8522 ;; LXSD STXSD XXLOR XXLXOR GPR<-
0
8523 ;; LWZ STW MR XXSPLTIDP
8526 (define_insn "*mov<mode>_hardfloat32"
8527 [(set (match_operand:FMOVE64
0 "nonimmediate_operand"
8528 "=m, d, d, <f64_p9>, wY,
8529 <f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
8531 (match_operand:FMOVE64
1 "input_operand"
8532 "d, m, d, wY, <f64_p9>,
8533 Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
8535 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
8536 && (gpc_reg_operand (operands[
0], <MODE>mode)
8537 || gpc_reg_operand (operands[
1], <MODE>mode))"
8554 "fpstore, fpload, fpsimple, fpload, fpstore,
8555 fpload, fpstore, veclogical, veclogical, two,
8556 store, load, two, vecperm")
8557 (set_attr "size" "
64")
8566 (set_attr "prefixed"
8571 ;; STW LWZ MR G-const H-const F-const
8573 (define_insn "*mov<mode>_softfloat32"
8574 [(set (match_operand:FMOVE64
0 "nonimmediate_operand"
8575 "=Y, r, r, r, r, r")
8577 (match_operand:FMOVE64
1 "input_operand"
8578 "r, Y, r, G, H, F"))]
8581 && (gpc_reg_operand (operands[
0], <MODE>mode)
8582 || gpc_reg_operand (operands[
1], <MODE>mode))"
8585 "store, load, two, *, *, *")
8588 "
8,
8,
8,
8,
12,
16")])
8590 ; ld/std require word-aligned displacements -> 'Y' constraint.
8591 ; List Y->r and r->Y before r->r for reload.
8593 ;; STFD LFD FMR LXSD STXSD
8594 ;; LXSDX STXSDX XXLOR XXLXOR LI
0
8595 ;; STD LD MR MT{CTR,LR} MF{CTR,LR}
8596 ;; NOP MFVSRD MTVSRD XXSPLTIDP
8598 (define_insn "*mov<mode>_hardfloat64"
8599 [(set (match_operand:FMOVE64
0 "nonimmediate_operand"
8600 "=m, d, d, <f64_p9>, wY,
8601 <f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
8602 YZ, r, !r, *c*l, !r,
8603 *h, r, <f64_dm>, wa")
8604 (match_operand:FMOVE64
1 "input_operand"
8605 "d, m, d, wY, <f64_p9>,
8606 Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
8608 0, <f64_dm>, r, eP"))]
8609 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
8610 && (gpc_reg_operand (operands[
0], <MODE>mode)
8611 || gpc_reg_operand (operands[
1], <MODE>mode))"
8633 "fpstore, fpload, fpsimple, fpload, fpstore,
8634 fpload, fpstore, veclogical, veclogical, integer,
8635 store, load, *, mtjmpr, mfjmpr,
8636 *, mfvsr, mtvsr, vecperm")
8637 (set_attr "size" "
64")
8643 (set_attr "prefixed"
8649 ;; STD LD MR MT<SPR> MF<SPR> G-const
8650 ;; H-const F-const Special
8652 (define_insn "*mov<mode>_softfloat64"
8653 [(set (match_operand:FMOVE64
0 "nonimmediate_operand"
8654 "=Y, r, r, *c*l, r, r,
8657 (match_operand:FMOVE64
1 "input_operand"
8661 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
8662 && (gpc_reg_operand (operands[
0], <MODE>mode)
8663 || gpc_reg_operand (operands[
1], <MODE>mode))"
8675 "store, load, *, mtjmpr, mfjmpr, *,
8682 ;; Split the VSX prefixed instruction to support SFmode and DFmode scalar
8683 ;; constants that look like DFmode floating point values where both elements
8684 ;; are the same. The constant has to be expressible as a SFmode constant that
8685 ;; is not a SFmode denormal value.
8687 ;; We don't need splitters for the
128-bit types, since the function
8688 ;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
8689 (define_insn "xxspltidp_<mode>_internal"
8690 [(set (match_operand:SFDF
0 "register_operand" "=wa")
8691 (unspec:SFDF [(match_operand:SI
1 "c32bit_cint_operand" "n")]
8692 UNSPEC_XXSPLTIDP_CONST))]
8695 [(set_attr "type" "vecperm")
8696 (set_attr "prefixed" "yes")])
8698 (define_insn "xxspltiw_<mode>_internal"
8699 [(set (match_operand:SFDF
0 "register_operand" "=wa")
8700 (unspec:SFDF [(match_operand:SI
1 "c32bit_cint_operand" "n")]
8701 UNSPEC_XXSPLTIW_CONST))]
8704 [(set_attr "type" "vecperm")
8705 (set_attr "prefixed" "yes")])
8708 [(set (match_operand:SFDF
0 "vsx_register_operand")
8709 (match_operand:SFDF
1 "vsx_prefixed_constant"))]
8713 rtx dest = operands[
0];
8714 rtx src = operands[
1];
8715 vec_const_128bit_type vsx_const;
8717 if (!vec_const_128bit_to_bytes (src, <MODE>mode, &vsx_const))
8720 unsigned imm = constant_generates_xxspltidp (&vsx_const);
8723 emit_insn (gen_xxspltidp_<mode>_internal (dest, GEN_INT (imm)));
8727 imm = constant_generates_xxspltiw (&vsx_const);
8730 emit_insn (gen_xxspltiw_<mode>_internal (dest, GEN_INT (imm)));
8738 (define_expand "mov<mode>"
8739 [(set (match_operand:FMOVE128
0 "general_operand")
8740 (match_operand:FMOVE128
1 "any_operand"))]
8743 rs6000_emit_move (operands[
0], operands[
1], <MODE>mode);
8747 ;; It's important to list Y->r and r->Y before r->r because otherwise
8748 ;; reload, given m->r, will try to pick r->r and reload it, which
8749 ;; doesn't make progress.
8751 ;; We can't split little endian direct moves of TDmode, because the words are
8752 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
8753 ;; problematical. Don't allow direct move for this case.
8755 ;; FPR load FPR store FPR move FPR zero GPR load
8756 ;; GPR zero GPR store GPR move MFVSRD MTVSRD
8758 (define_insn_and_split "*mov<mode>_64bit_dm"
8759 [(set (match_operand:FMOVE128_FPR
0 "nonimmediate_operand"
8763 (match_operand:FMOVE128_FPR
1 "input_operand"
8764 "d, m, d, <zero_fp>, r,
8765 <zero_fp>, Y, r, d, r"))]
8767 "TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
8768 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
8769 && (gpc_reg_operand (operands[
0], <MODE>mode)
8770 || gpc_reg_operand (operands[
1], <MODE>mode))"
8772 "&& reload_completed"
8775 rs6000_split_multireg_move (operands[
0], operands[
1]);
8778 [(set_attr "length" "
8")
8779 (set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v")
8780 (set_attr "max_prefixed_insns" "
2")
8781 (set_attr "num_insns" "
2")])
8783 (define_insn_and_split "*movtd_64bit_nodm"
8784 [(set (match_operand:TD
0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8785 (match_operand:TD
1 "input_operand" "d,m,d,r,Y,r"))]
8786 "TARGET_HARD_FLOAT && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
8787 && (gpc_reg_operand (operands[
0], TDmode)
8788 || gpc_reg_operand (operands[
1], TDmode))"
8790 "&& reload_completed"
8793 rs6000_split_multireg_move (operands[
0], operands[
1]);
8796 [(set_attr "length" "
8,
8,
8,
12,
12,
8")
8797 (set_attr "max_prefixed_insns" "
2")
8798 (set_attr "num_insns" "
2,
2,
2,
3,
3,
2")])
8800 (define_insn_and_split "*mov<mode>_32bit"
8801 [(set (match_operand:FMOVE128_FPR
0 "nonimmediate_operand" "=m,d,d,d,Y,r,r")
8802 (match_operand:FMOVE128_FPR
1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))]
8803 "TARGET_HARD_FLOAT && !TARGET_POWERPC64
8804 && (FLOAT128_2REG_P (<MODE>mode)
8805 || int_reg_operand_not_pseudo (operands[
0], <MODE>mode)
8806 || int_reg_operand_not_pseudo (operands[
1], <MODE>mode))
8807 && (gpc_reg_operand (operands[
0], <MODE>mode)
8808 || gpc_reg_operand (operands[
1], <MODE>mode))"
8810 "&& reload_completed"
8813 rs6000_split_multireg_move (operands[
0], operands[
1]);
8816 [(set_attr "length" "
8,
8,
8,
8,
20,
20,
16")])
8818 (define_insn_and_split "*mov<mode>_softfloat"
8819 [(set (match_operand:FMOVE128
0 "nonimmediate_operand" "=Y,r,r,r")
8820 (match_operand:FMOVE128
1 "input_operand" "r,Y,F,r"))]
8822 && (gpc_reg_operand (operands[
0], <MODE>mode)
8823 || gpc_reg_operand (operands[
1], <MODE>mode))"
8825 "&& reload_completed"
8828 rs6000_split_multireg_move (operands[
0], operands[
1]);
8831 [(set_attr_alternative "length"
8832 [(if_then_else (match_test "TARGET_POWERPC64")
8834 (const_string "
16"))
8835 (if_then_else (match_test "TARGET_POWERPC64")
8837 (const_string "
16"))
8838 (if_then_else (match_test "TARGET_POWERPC64")
8840 (const_string "
32"))
8841 (if_then_else (match_test "TARGET_POWERPC64")
8843 (const_string "
16"))])])
8845 (define_expand "@extenddf<mode>
2"
8846 [(set (match_operand:FLOAT128
0 "gpc_reg_operand")
8847 (float_extend:FLOAT128 (match_operand:DF
1 "gpc_reg_operand")))]
8848 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8850 if (FLOAT128_IEEE_P (<MODE>mode))
8851 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
8852 else if (TARGET_VSX)
8853 emit_insn (gen_extenddf2_vsx (<MODE>mode, operands[
0], operands[
1]));
8856 rtx zero = gen_reg_rtx (DFmode);
8857 rs6000_emit_move (zero, CONST0_RTX (DFmode), DFmode);
8859 emit_insn (gen_extenddf2_fprs (<MODE>mode,
8860 operands[
0], operands[
1], zero));
8865 ;; Allow memory operands for the source to be created by the combiner.
8866 (define_insn_and_split "@extenddf<mode>
2_fprs"
8867 [(set (match_operand:IBM128
0 "gpc_reg_operand" "=d,d,&d")
8868 (float_extend:IBM128
8869 (match_operand:DF
1 "nonimmediate_operand" "d,m,d")))
8870 (use (match_operand:DF
2 "nonimmediate_operand" "m,m,d"))]
8871 "!TARGET_VSX && TARGET_HARD_FLOAT
8872 && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
8874 "&& reload_completed"
8875 [(set (match_dup
3) (match_dup
1))
8876 (set (match_dup
4) (match_dup
2))]
8878 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) :
0;
8879 const int hi_word = LONG_DOUBLE_LARGE_FIRST ?
0 : GET_MODE_SIZE (DFmode);
8881 operands[
3] = simplify_gen_subreg (DFmode, operands[
0], <MODE>mode, hi_word);
8882 operands[
4] = simplify_gen_subreg (DFmode, operands[
0], <MODE>mode, lo_word);
8885 (define_insn_and_split "@extenddf<mode>
2_vsx"
8886 [(set (match_operand:IBM128
0 "gpc_reg_operand" "=d,d")
8887 (float_extend:IBM128
8888 (match_operand:DF
1 "nonimmediate_operand" "wa,m")))]
8889 "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
8891 "&& reload_completed"
8892 [(set (match_dup
2) (match_dup
1))
8893 (set (match_dup
3) (match_dup
4))]
8895 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) :
0;
8896 const int hi_word = LONG_DOUBLE_LARGE_FIRST ?
0 : GET_MODE_SIZE (DFmode);
8898 operands[
2] = simplify_gen_subreg (DFmode, operands[
0], <MODE>mode, hi_word);
8899 operands[
3] = simplify_gen_subreg (DFmode, operands[
0], <MODE>mode, lo_word);
8900 operands[
4] = CONST0_RTX (DFmode);
8903 (define_expand "extendsf<mode>
2"
8904 [(set (match_operand:FLOAT128
0 "gpc_reg_operand")
8905 (float_extend:FLOAT128 (match_operand:SF
1 "gpc_reg_operand")))]
8906 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8908 if (FLOAT128_IEEE_P (<MODE>mode))
8909 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
8912 rtx tmp = gen_reg_rtx (DFmode);
8913 emit_insn (gen_extendsfdf2 (tmp, operands[
1]));
8914 emit_insn (gen_extenddf<mode>
2 (operands[
0], tmp));
8919 (define_expand "trunc<mode>df2"
8920 [(set (match_operand:DF
0 "gpc_reg_operand")
8921 (float_truncate:DF (match_operand:FLOAT128
1 "gpc_reg_operand")))]
8922 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8924 if (FLOAT128_IEEE_P (<MODE>mode))
8926 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
8931 (define_insn_and_split "trunc<mode>df2_internal1"
8932 [(set (match_operand:DF
0 "gpc_reg_operand" "=d,?d")
8934 (match_operand:IBM128
1 "gpc_reg_operand" "
0,d")))]
8935 "FLOAT128_IBM_P (<MODE>mode) && !TARGET_XL_COMPAT
8936 && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8940 "&& reload_completed && REGNO (operands[
0]) == REGNO (operands[
1])"
8943 emit_note (NOTE_INSN_DELETED);
8946 [(set_attr "type" "fpsimple")])
8948 (define_insn "trunc<mode>df2_internal2"
8949 [(set (match_operand:DF
0 "gpc_reg_operand" "=d")
8950 (float_truncate:DF (match_operand:IBM128
1 "gpc_reg_operand" "d")))]
8951 "FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT
8952 && TARGET_LONG_DOUBLE_128"
8954 [(set_attr "type" "fp")])
8956 (define_expand "trunc<mode>sf2"
8957 [(set (match_operand:SF
0 "gpc_reg_operand")
8958 (float_truncate:SF (match_operand:FLOAT128
1 "gpc_reg_operand")))]
8959 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8961 if (FLOAT128_IEEE_P (<MODE>mode))
8962 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
8965 rtx tmp = gen_reg_rtx (DFmode);
8966 emit_insn (gen_trunc<mode>df2 (tmp, operands[
1]));
8967 emit_insn (gen_truncdfsf2 (operands[
0], tmp));
8972 (define_expand "floatsi<mode>
2"
8973 [(parallel [(set (match_operand:FLOAT128
0 "gpc_reg_operand")
8974 (float:FLOAT128 (match_operand:SI
1 "gpc_reg_operand")))
8975 (clobber (match_scratch:DI
2))])]
8976 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
8978 rtx op0 = operands[
0];
8979 rtx op1 = operands[
1];
8981 if (TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode))
8983 else if (FLOAT128_IEEE_P (<MODE>mode))
8985 rs6000_expand_float128_convert (op0, op1, false);
8990 rtx tmp = gen_reg_rtx (DFmode);
8991 expand_float (tmp, op1, false);
8992 emit_insn (gen_extenddf2 (<MODE>mode, op0, tmp));
8997 ; fadd, but rounding towards zero.
8998 ; This is probably not the optimal code sequence.
8999 (define_insn "fix_trunc_helper<mode>"
9000 [(set (match_operand:DF
0 "gpc_reg_operand" "=d")
9001 (unspec:DF [(match_operand:IBM128
1 "gpc_reg_operand" "d")]
9002 UNSPEC_FIX_TRUNC_TF))
9003 (clobber (match_operand:DF
2 "gpc_reg_operand" "=&d"))]
9004 "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
9005 "mffs %
2\n\tmtfsb
1 31\n\tmtfsb
0 30\n\tfadd %
0,%
1,%L1
\n\tmtfsf
1,%
2"
9006 [(set_attr "type" "fp")
9007 (set_attr "length" "
20")])
9009 (define_expand "fix_trunc<mode>si2"
9010 [(set (match_operand:SI
0 "gpc_reg_operand")
9011 (fix:SI (match_operand:FLOAT128
1 "gpc_reg_operand")))]
9012 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
9014 rtx op0 = operands[
0];
9015 rtx op1 = operands[
1];
9017 if (TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode))
9021 if (FLOAT128_IEEE_P (<MODE>mode))
9022 rs6000_expand_float128_convert (op0, op1, false);
9024 emit_insn (gen_fix_truncsi2_fprs (<MODE>mode, op0, op1));
9029 (define_expand "@fix_trunc<mode>si2_fprs"
9030 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand")
9031 (fix:SI (match_operand:IBM128
1 "gpc_reg_operand")))
9032 (clobber (match_dup
2))
9033 (clobber (match_dup
3))
9034 (clobber (match_dup
4))
9035 (clobber (match_dup
5))])]
9036 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
9038 operands[
2] = gen_reg_rtx (DFmode);
9039 operands[
3] = gen_reg_rtx (DFmode);
9040 operands[
4] = gen_reg_rtx (DImode);
9041 operands[
5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9044 (define_insn_and_split "*fix_trunc<mode>si2_internal"
9045 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
9046 (fix:SI (match_operand:IBM128
1 "gpc_reg_operand" "d")))
9047 (clobber (match_operand:DF
2 "gpc_reg_operand" "=d"))
9048 (clobber (match_operand:DF
3 "gpc_reg_operand" "=&d"))
9049 (clobber (match_operand:DI
4 "gpc_reg_operand" "=d"))
9050 (clobber (match_operand:DI
5 "offsettable_mem_operand" "=o"))]
9051 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
9057 emit_insn (gen_fix_trunc_helper<mode> (operands[
2], operands[
1],
9060 gcc_assert (MEM_P (operands[
5]));
9061 lowword = adjust_address (operands[
5], SImode, WORDS_BIG_ENDIAN ?
4 :
0);
9063 emit_insn (gen_fctiwz_df (operands[
4], operands[
2]));
9064 emit_move_insn (operands[
5], operands[
4]);
9065 emit_move_insn (operands[
0], lowword);
9069 (define_expand "fix_trunc<mode>di2"
9070 [(set (match_operand:DI
0 "gpc_reg_operand")
9071 (fix:DI (match_operand:IEEE128
1 "gpc_reg_operand")))]
9072 "TARGET_FLOAT128_TYPE"
9074 if (!TARGET_FLOAT128_HW)
9076 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9081 (define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>
2"
9082 [(set (match_operand:SDI
0 "gpc_reg_operand")
9083 (unsigned_fix:SDI (match_operand:IEEE128
1 "gpc_reg_operand")))]
9084 "TARGET_FLOAT128_TYPE"
9086 rs6000_expand_float128_convert (operands[
0], operands[
1], true);
9090 (define_expand "floatdi<mode>
2"
9091 [(set (match_operand:IEEE128
0 "gpc_reg_operand")
9092 (float:IEEE128 (match_operand:DI
1 "gpc_reg_operand")))]
9093 "TARGET_FLOAT128_TYPE"
9095 if (!TARGET_FLOAT128_HW)
9097 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9102 (define_expand "floatunsdi<IEEE128:mode>
2"
9103 [(set (match_operand:IEEE128
0 "gpc_reg_operand")
9104 (unsigned_float:IEEE128 (match_operand:DI
1 "gpc_reg_operand")))]
9105 "TARGET_FLOAT128_TYPE"
9107 if (!TARGET_FLOAT128_HW)
9109 rs6000_expand_float128_convert (operands[
0], operands[
1], true);
9114 (define_expand "floatuns<IEEE128:mode>
2"
9115 [(set (match_operand:IEEE128
0 "gpc_reg_operand")
9116 (unsigned_float:IEEE128 (match_operand:SI
1 "gpc_reg_operand")))]
9117 "TARGET_FLOAT128_TYPE"
9119 rtx op0 = operands[
0];
9120 rtx op1 = operands[
1];
9122 if (TARGET_FLOAT128_HW)
9123 emit_insn (gen_floatuns_<IEEE128:mode>si2_hw (op0, op1));
9125 rs6000_expand_float128_convert (op0, op1, true);
9129 (define_expand "neg<mode>
2"
9130 [(set (match_operand:FLOAT128
0 "gpc_reg_operand")
9131 (neg:FLOAT128 (match_operand:FLOAT128
1 "gpc_reg_operand")))]
9132 "FLOAT128_IEEE_P (<MODE>mode)
9133 || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
9135 if (FLOAT128_IEEE_P (<MODE>mode))
9137 if (TARGET_FLOAT128_HW)
9138 emit_insn (gen_neg2_hw (<MODE>mode, operands[
0], operands[
1]));
9139 else if (TARGET_FLOAT128_TYPE)
9140 emit_insn (gen_ieee_128bit_vsx_neg2 (<MODE>mode,
9141 operands[
0], operands[
1]));
9144 rtx libfunc = optab_libfunc (neg_optab, <MODE>mode);
9145 rtx target = emit_library_call_value (libfunc, operands[
0], LCT_CONST,
9147 operands[
1], <MODE>mode);
9149 if (target && !rtx_equal_p (target, operands[
0]))
9150 emit_move_insn (operands[
0], target);
9156 (define_insn "neg<mode>
2_internal"
9157 [(set (match_operand:IBM128
0 "gpc_reg_operand" "=d")
9158 (neg:IBM128 (match_operand:IBM128
1 "gpc_reg_operand" "d")))]
9159 "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
9161 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
9162 return "fneg %L0,%L1\;fneg %
0,%
1";
9164 return "fneg %
0,%
1\;fneg %L0,%L1";
9166 [(set_attr "type" "fpsimple")
9167 (set_attr "length" "
8")])
9169 (define_expand "abs<mode>
2"
9170 [(set (match_operand:FLOAT128
0 "gpc_reg_operand")
9171 (abs:FLOAT128 (match_operand:FLOAT128
1 "gpc_reg_operand")))]
9172 "FLOAT128_IEEE_P (<MODE>mode)
9173 || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)"
9177 if (FLOAT128_IEEE_P (<MODE>mode))
9179 if (TARGET_FLOAT128_HW)
9181 emit_insn (gen_abs2_hw (<MODE>mode, operands[
0], operands[
1]));
9184 else if (TARGET_FLOAT128_TYPE)
9186 emit_insn (gen_ieee_128bit_vsx_abs2 (<MODE>mode,
9187 operands[
0], operands[
1]));
9194 label = gen_label_rtx ();
9195 emit_insn (gen_abs2_internal (<MODE>mode, operands[
0], operands[
1], label));
9200 (define_expand "@abs<mode>
2_internal"
9201 [(set (match_operand:IBM128
0 "gpc_reg_operand")
9202 (match_operand:IBM128
1 "gpc_reg_operand"))
9203 (set (match_dup
3) (match_dup
5))
9204 (set (match_dup
5) (abs:DF (match_dup
5)))
9205 (set (match_dup
4) (compare:CCFP (match_dup
3) (match_dup
5)))
9206 (set (pc) (if_then_else (eq (match_dup
4) (const_int
0))
9207 (label_ref (match_operand
2 ""))
9209 (set (match_dup
6) (neg:DF (match_dup
6)))]
9210 "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
9212 const int hi_word = LONG_DOUBLE_LARGE_FIRST ?
0 : GET_MODE_SIZE (DFmode);
9213 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) :
0;
9214 operands[
3] = gen_reg_rtx (DFmode);
9215 operands[
4] = gen_reg_rtx (CCFPmode);
9216 operands[
5] = simplify_gen_subreg (DFmode, operands[
0], <MODE>mode, hi_word);
9217 operands[
6] = simplify_gen_subreg (DFmode, operands[
0], <MODE>mode, lo_word);
9221 ;; Generate IEEE
128-bit -
0.0 (
0x80000000000000000000000000000000) in a vector
9224 (define_expand "ieee_128bit_negative_zero"
9225 [(set (match_operand:V16QI
0 "register_operand") (match_dup
1))]
9226 "TARGET_FLOAT128_TYPE"
9228 rtvec v = rtvec_alloc (
16);
9231 for (i =
0; i <
16; i++)
9232 RTVEC_ELT (v, i) = const0_rtx;
9234 high = (BYTES_BIG_ENDIAN) ?
0 :
15;
9235 RTVEC_ELT (v, high) = gen_int_mode (
0x80, QImode);
9237 rs6000_expand_vector_init (operands[
0], gen_rtx_PARALLEL (V16QImode, v));
9241 ;; IEEE
128-bit negate
9243 ;; We have
2 insns here for negate and absolute value. The first uses
9244 ;; match_scratch so that phases like combine can recognize neg/abs as generic
9245 ;; insns, and second insn after the first split pass loads up the bit to
9246 ;; twiddle the sign bit. Later GCSE passes can then combine multiple uses of
9247 ;; neg/abs to create the constant just once.
9249 (define_insn_and_split "@ieee_128bit_vsx_neg<mode>
2"
9250 [(set (match_operand:IEEE128
0 "register_operand" "=wa")
9251 (neg:IEEE128 (match_operand:IEEE128
1 "register_operand" "wa")))
9252 (clobber (match_scratch:V16QI
2 "=v"))]
9253 "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW"
9256 [(parallel [(set (match_dup
0)
9257 (neg:IEEE128 (match_dup
1)))
9258 (use (match_dup
2))])]
9260 if (GET_CODE (operands[
2]) == SCRATCH)
9261 operands[
2] = gen_reg_rtx (V16QImode);
9263 operands[
3] = gen_reg_rtx (V16QImode);
9264 emit_insn (gen_ieee_128bit_negative_zero (operands[
2]));
9266 [(set_attr "length" "
8")
9267 (set_attr "type" "vecsimple")])
9269 (define_insn "*ieee_128bit_vsx_neg<mode>
2_internal"
9270 [(set (match_operand:IEEE128
0 "register_operand" "=wa")
9271 (neg:IEEE128 (match_operand:IEEE128
1 "register_operand" "wa")))
9272 (use (match_operand:V16QI
2 "register_operand" "v"))]
9273 "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW"
9274 "xxlxor %x0,%x1,%x2"
9275 [(set_attr "type" "veclogical")])
9277 ;; IEEE
128-bit absolute value
9278 (define_insn_and_split "@ieee_128bit_vsx_abs<mode>
2"
9279 [(set (match_operand:IEEE128
0 "register_operand" "=wa")
9280 (abs:IEEE128 (match_operand:IEEE128
1 "register_operand" "wa")))
9281 (clobber (match_scratch:V16QI
2 "=v"))]
9282 "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
9285 [(parallel [(set (match_dup
0)
9286 (abs:IEEE128 (match_dup
1)))
9287 (use (match_dup
2))])]
9289 if (GET_CODE (operands[
2]) == SCRATCH)
9290 operands[
2] = gen_reg_rtx (V16QImode);
9292 operands[
3] = gen_reg_rtx (V16QImode);
9293 emit_insn (gen_ieee_128bit_negative_zero (operands[
2]));
9295 [(set_attr "length" "
8")
9296 (set_attr "type" "vecsimple")])
9298 (define_insn "*ieee_128bit_vsx_abs<mode>
2_internal"
9299 [(set (match_operand:IEEE128
0 "register_operand" "=wa")
9300 (abs:IEEE128 (match_operand:IEEE128
1 "register_operand" "wa")))
9301 (use (match_operand:V16QI
2 "register_operand" "v"))]
9302 "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW"
9303 "xxlandc %x0,%x1,%x2"
9304 [(set_attr "type" "veclogical")])
9306 ;; IEEE
128-bit negative absolute value
9307 (define_insn_and_split "*ieee_128bit_vsx_nabs<mode>
2"
9308 [(set (match_operand:IEEE128
0 "register_operand" "=wa")
9311 (match_operand:IEEE128
1 "register_operand" "wa"))))
9312 (clobber (match_scratch:V16QI
2 "=v"))]
9313 "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW
9314 && FLOAT128_IEEE_P (<MODE>mode)"
9317 [(parallel [(set (match_dup
0)
9318 (neg:IEEE128 (abs:IEEE128 (match_dup
1))))
9319 (use (match_dup
2))])]
9321 if (GET_CODE (operands[
2]) == SCRATCH)
9322 operands[
2] = gen_reg_rtx (V16QImode);
9324 operands[
3] = gen_reg_rtx (V16QImode);
9325 emit_insn (gen_ieee_128bit_negative_zero (operands[
2]));
9327 [(set_attr "length" "
8")
9328 (set_attr "type" "vecsimple")])
9330 (define_insn "*ieee_128bit_vsx_nabs<mode>
2_internal"
9331 [(set (match_operand:IEEE128
0 "register_operand" "=wa")
9334 (match_operand:IEEE128
1 "register_operand" "wa"))))
9335 (use (match_operand:V16QI
2 "register_operand" "v"))]
9336 "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW"
9338 [(set_attr "type" "veclogical")])
9340 ;; Float128 conversion functions. These expand to library function calls.
9341 ;; We use expand to convert from IBM double double to IEEE
128-bit
9342 ;; and trunc for the opposite.
9343 (define_expand "extendiftf2"
9344 [(set (match_operand:TF
0 "gpc_reg_operand")
9345 (float_extend:TF (match_operand:IF
1 "gpc_reg_operand")))]
9346 "TARGET_FLOAT128_TYPE"
9348 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9352 (define_expand "extendifkf2"
9353 [(set (match_operand:KF
0 "gpc_reg_operand")
9354 (float_extend:KF (match_operand:IF
1 "gpc_reg_operand")))]
9355 "TARGET_FLOAT128_TYPE"
9357 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9361 (define_expand "extendtfkf2"
9362 [(set (match_operand:KF
0 "gpc_reg_operand")
9363 (float_extend:KF (match_operand:TF
1 "gpc_reg_operand")))]
9364 "TARGET_FLOAT128_TYPE"
9366 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9370 (define_expand "extendtfif2"
9371 [(set (match_operand:IF
0 "gpc_reg_operand")
9372 (float_extend:IF (match_operand:TF
1 "gpc_reg_operand")))]
9373 "TARGET_FLOAT128_TYPE"
9375 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9379 (define_expand "trunciftf2"
9380 [(set (match_operand:TF
0 "gpc_reg_operand")
9381 (float_truncate:TF (match_operand:IF
1 "gpc_reg_operand")))]
9382 "TARGET_FLOAT128_TYPE"
9384 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9388 (define_expand "truncifkf2"
9389 [(set (match_operand:KF
0 "gpc_reg_operand")
9390 (float_truncate:KF (match_operand:IF
1 "gpc_reg_operand")))]
9391 "TARGET_FLOAT128_TYPE"
9393 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9397 (define_expand "trunckftf2"
9398 [(set (match_operand:TF
0 "gpc_reg_operand")
9399 (float_truncate:TF (match_operand:KF
1 "gpc_reg_operand")))]
9400 "TARGET_FLOAT128_TYPE"
9402 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9406 (define_expand "trunctfif2"
9407 [(set (match_operand:IF
0 "gpc_reg_operand")
9408 (float_truncate:IF (match_operand:TF
1 "gpc_reg_operand")))]
9409 "TARGET_FLOAT128_TYPE"
9411 rs6000_expand_float128_convert (operands[
0], operands[
1], false);
9415 (define_insn_and_split "*extend<mode>tf2_internal"
9416 [(set (match_operand:TF
0 "gpc_reg_operand" "=<IFKF_reg>")
9418 (match_operand:IFKF
1 "gpc_reg_operand" "<IFKF_reg>")))]
9419 "TARGET_FLOAT128_TYPE
9420 && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
9422 "&& reload_completed"
9423 [(set (match_dup
0) (match_dup
2))]
9425 operands[
2] = gen_rtx_REG (TFmode, REGNO (operands[
1]));
9428 (define_insn_and_split "*extendtf<mode>
2_internal"
9429 [(set (match_operand:IFKF
0 "gpc_reg_operand" "=<IFKF_reg>")
9431 (match_operand:TF
1 "gpc_reg_operand" "<IFKF_reg>")))]
9432 "TARGET_FLOAT128_TYPE
9433 && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
9435 "&& reload_completed"
9436 [(set (match_dup
0) (match_dup
2))]
9438 operands[
2] = gen_rtx_REG (<MODE>mode, REGNO (operands[
1]));
9442 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9443 ;; must have
3 arguments, and scratch register constraint must be a single
9446 ;; Reload patterns to support gpr load/store with misaligned mem.
9447 ;; and multiple gpr load/store at offset >=
0xfffc
9448 (define_expand "reload_<mode>_store"
9449 [(parallel [(match_operand
0 "memory_operand" "=m")
9450 (match_operand
1 "gpc_reg_operand" "r")
9451 (match_operand:GPR
2 "register_operand" "=&b")])]
9454 rs6000_secondary_reload_gpr (operands[
1], operands[
0], operands[
2], true);
9458 (define_expand "reload_<mode>_load"
9459 [(parallel [(match_operand
0 "gpc_reg_operand" "=r")
9460 (match_operand
1 "memory_operand" "m")
9461 (match_operand:GPR
2 "register_operand" "=b")])]
9464 rs6000_secondary_reload_gpr (operands[
0], operands[
1], operands[
2], false);
9469 ;; Reload patterns for various types using the vector registers. We may need
9470 ;; an additional base register to convert the reg+offset addressing to reg+reg
9471 ;; for vector registers and reg+reg or (reg+reg)&(-
16) addressing to just an
9472 ;; index register for gpr registers.
9473 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
9474 [(parallel [(match_operand:RELOAD
0 "memory_operand" "m")
9475 (match_operand:RELOAD
1 "gpc_reg_operand" "wa")
9476 (match_operand:P
2 "register_operand" "=b")])]
9479 rs6000_secondary_reload_inner (operands[
1], operands[
0], operands[
2], true);
9483 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
9484 [(parallel [(match_operand:RELOAD
0 "gpc_reg_operand" "wa")
9485 (match_operand:RELOAD
1 "memory_operand" "m")
9486 (match_operand:P
2 "register_operand" "=b")])]
9489 rs6000_secondary_reload_inner (operands[
0], operands[
1], operands[
2], false);
9494 ;; Reload sometimes tries to move the address to a GPR, and can generate
9495 ;; invalid RTL for addresses involving AND -
16. Allow addresses involving
9496 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -
16.
9498 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
9499 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
9500 (and:P (plus:P (match_operand:P
1 "gpc_reg_operand" "r")
9501 (match_operand:P
2 "reg_or_cint_operand" "rI"))
9503 "TARGET_ALTIVEC && reload_completed"
9505 "&& reload_completed"
9507 (plus:P (match_dup
1)
9510 (and:P (match_dup
0)
9513 ;; Power8 merge instructions to allow direct move to/from floating point
9514 ;; registers in
32-bit mode. We use TF mode to get two registers to move the
9515 ;; individual
32-bit parts across. Subreg doesn't work too well on the TF
9516 ;; value, since it is allocated in reload and not all of the flow information
9517 ;; is setup for it. We have two patterns to do the two moves between gprs and
9518 ;; fprs. There isn't a dependancy between the two, but we could potentially
9519 ;; schedule other instructions between the two instructions.
9521 (define_insn "p8_fmrgow_<mode>"
9522 [(set (match_operand:FMOVE64X
0 "register_operand" "=d")
9524 (match_operand:DF
1 "register_operand" "d")
9525 (match_operand:DF
2 "register_operand" "d")]
9526 UNSPEC_P8V_FMRGOW))]
9527 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9529 [(set_attr "type" "fpsimple")])
9531 (define_insn "p8_mtvsrwz"
9532 [(set (match_operand:DF
0 "register_operand" "=d")
9533 (unspec:DF [(match_operand:SI
1 "register_operand" "r")]
9534 UNSPEC_P8V_MTVSRWZ))]
9535 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9537 [(set_attr "type" "mtvsr")])
9539 (define_insn "p8_mtvsrwz_v16qisi2"
9540 [(set (match_operand:V16QI
0 "register_operand" "=wa")
9541 (unspec:V16QI [(match_operand:SI
1 "register_operand" "r")]
9542 UNSPEC_P8V_MTVSRWZ))]
9543 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9545 [(set_attr "type" "mtvsr")])
9547 (define_insn "p8_mtvsrd_v16qidi2"
9548 [(set (match_operand:V16QI
0 "register_operand" "=wa")
9549 (unspec:V16QI [(match_operand:DI
1 "register_operand" "r")]
9550 UNSPEC_P8V_MTVSRD))]
9551 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9553 [(set_attr "type" "mtvsr")])
9555 (define_insn_and_split "reload_fpr_from_gpr<mode>"
9556 [(set (match_operand:FMOVE64X
0 "register_operand" "=d")
9557 (unspec:FMOVE64X [(match_operand:FMOVE64X
1 "register_operand" "r")]
9558 UNSPEC_P8V_RELOAD_FROM_GPR))
9559 (clobber (match_operand:IF
2 "register_operand" "=d"))]
9560 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9562 "&& reload_completed"
9565 rtx dest = operands[
0];
9566 rtx src = operands[
1];
9567 rtx tmp_hi = simplify_gen_subreg (DFmode, operands[
2], IFmode,
0);
9568 rtx tmp_lo = simplify_gen_subreg (DFmode, operands[
2], IFmode,
8);
9569 rtx gpr_hi_reg = gen_highpart (SImode, src);
9570 rtx gpr_lo_reg = gen_lowpart (SImode, src);
9572 emit_insn (gen_p8_mtvsrwz (tmp_hi, gpr_hi_reg));
9573 emit_insn (gen_p8_mtvsrwz (tmp_lo, gpr_lo_reg));
9574 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp_hi, tmp_lo));
9577 [(set_attr "length" "
12")
9578 (set_attr "type" "three")])
9580 ;; Move
128 bit values from GPRs to VSX registers in
64-bit mode
9581 (define_insn "p8_mtvsrd_df"
9582 [(set (match_operand:DF
0 "register_operand" "=wa")
9583 (unspec:DF [(match_operand:DI
1 "register_operand" "r")]
9584 UNSPEC_P8V_MTVSRD))]
9585 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9587 [(set_attr "type" "mtvsr")])
9589 (define_insn "p8_xxpermdi_<mode>"
9590 [(set (match_operand:FMOVE128_GPR
0 "register_operand" "=wa")
9591 (unspec:FMOVE128_GPR [
9592 (match_operand:DF
1 "register_operand" "wa")
9593 (match_operand:DF
2 "register_operand" "wa")]
9594 UNSPEC_P8V_XXPERMDI))]
9595 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9596 "xxpermdi %x0,%x1,%x2,
0"
9597 [(set_attr "type" "vecperm")])
9599 (define_insn_and_split "reload_vsx_from_gpr<mode>"
9600 [(set (match_operand:FMOVE128_GPR
0 "register_operand" "=wa")
9601 (unspec:FMOVE128_GPR
9602 [(match_operand:FMOVE128_GPR
1 "register_operand" "r")]
9603 UNSPEC_P8V_RELOAD_FROM_GPR))
9604 (clobber (match_operand:IF
2 "register_operand" "=wa"))]
9605 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9607 "&& reload_completed"
9610 rtx dest = operands[
0];
9611 rtx src = operands[
1];
9612 /* You might think that we could use op0 as one temp and a DF clobber
9613 as op2, but you'd be wrong. Secondary reload move patterns don't
9614 check for overlap of the clobber and the destination. */
9615 rtx tmp_hi = simplify_gen_subreg (DFmode, operands[
2], IFmode,
0);
9616 rtx tmp_lo = simplify_gen_subreg (DFmode, operands[
2], IFmode,
8);
9617 rtx gpr_hi_reg = gen_highpart (DImode, src);
9618 rtx gpr_lo_reg = gen_lowpart (DImode, src);
9620 emit_insn (gen_p8_mtvsrd_df (tmp_hi, gpr_hi_reg));
9621 emit_insn (gen_p8_mtvsrd_df (tmp_lo, gpr_lo_reg));
9622 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp_hi, tmp_lo));
9625 [(set_attr "length" "
12")
9626 (set_attr "type" "three")])
9629 [(set (match_operand:FMOVE128_GPR
0 "nonimmediate_operand")
9630 (match_operand:FMOVE128_GPR
1 "input_operand"))]
9632 && (int_reg_operand (operands[
0], <MODE>mode)
9633 || int_reg_operand (operands[
1], <MODE>mode))
9634 && (!TARGET_DIRECT_MOVE_128
9635 || (!vsx_register_operand (operands[
0], <MODE>mode)
9636 && !vsx_register_operand (operands[
1], <MODE>mode)))"
9639 rs6000_split_multireg_move (operands[
0], operands[
1]);
9643 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
9644 ;; type is stored internally as double precision in the VSX registers, we have
9645 ;; to convert it from the vector format.
9646 (define_insn "p8_mtvsrd_sf"
9647 [(set (match_operand:SF
0 "register_operand" "=wa")
9648 (unspec:SF [(match_operand:DI
1 "register_operand" "r")]
9649 UNSPEC_P8V_MTVSRD))]
9650 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9652 [(set_attr "type" "mtvsr")])
9654 (define_insn_and_split "reload_vsx_from_gprsf"
9655 [(set (match_operand:SF
0 "register_operand" "=wa")
9656 (unspec:SF [(match_operand:SF
1 "register_operand" "r")]
9657 UNSPEC_P8V_RELOAD_FROM_GPR))
9658 (clobber (match_operand:DI
2 "register_operand" "=r"))]
9659 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9661 "&& reload_completed"
9664 rtx op0 = operands[
0];
9665 rtx op1 = operands[
1];
9666 rtx op2 = operands[
2];
9667 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode,
0);
9669 /* Move SF value to upper
32-bits for xscvspdpn. */
9670 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (
32)));
9671 emit_insn (gen_p8_mtvsrd_sf (op0, op2));
9672 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
9675 [(set_attr "length" "
8")
9676 (set_attr "type" "two")])
9678 ;; Move
128 bit values from VSX registers to GPRs in
64-bit mode by doing a
9679 ;; normal
64-bit move, followed by an xxpermdi to get the bottom
64-bit value,
9680 ;; and then doing a move of that.
9681 (define_insn "p8_mfvsrd_3_<mode>"
9682 [(set (match_operand:DF
0 "register_operand" "=r")
9683 (unspec:DF [(match_operand:FMOVE128_GPR
1 "register_operand" "wa")]
9684 UNSPEC_P8V_RELOAD_FROM_VSX))]
9685 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9687 [(set_attr "type" "mfvsr")])
9689 (define_insn_and_split "reload_gpr_from_vsx<mode>"
9690 [(set (match_operand:FMOVE128_GPR
0 "register_operand" "=r")
9691 (unspec:FMOVE128_GPR
9692 [(match_operand:FMOVE128_GPR
1 "register_operand" "wa")]
9693 UNSPEC_P8V_RELOAD_FROM_VSX))
9694 (clobber (match_operand:FMOVE128_GPR
2 "register_operand" "=wa"))]
9695 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9697 "&& reload_completed"
9700 rtx dest = operands[
0];
9701 rtx src = operands[
1];
9702 rtx tmp = operands[
2];
9703 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
9704 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
9706 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
9707 emit_insn (gen_vsx_xxpermdi_<mode>_be (tmp, src, src, GEN_INT (
3)));
9708 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
9711 [(set_attr "length" "
12")
9712 (set_attr "type" "three")])
9714 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
9715 ;; type is stored internally as double precision, we have to convert it to the
9718 (define_insn_and_split "reload_gpr_from_vsxsf"
9719 [(set (match_operand:SF
0 "register_operand" "=r")
9720 (unspec:SF [(match_operand:SF
1 "register_operand" "wa")]
9721 UNSPEC_P8V_RELOAD_FROM_VSX))
9722 (clobber (match_operand:V4SF
2 "register_operand" "=wa"))]
9723 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9725 "&& reload_completed"
9728 rtx op0 = operands[
0];
9729 rtx op1 = operands[
1];
9730 rtx op2 = operands[
2];
9731 rtx op0_di = gen_rtx_REG (DImode, reg_or_subregno (op0));
9732 rtx op2_si = gen_rtx_REG (SImode, reg_or_subregno (op2));
9734 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
9735 emit_insn (gen_zero_extendsidi2 (op0_di, op2_si));
9738 [(set_attr "length" "
8")
9739 (set_attr "type" "two")
9740 (set_attr "isa" "p8v")])
9742 ;; Next come the multi-word integer load and store and the load and store
9745 ;; List r->r after r->Y, otherwise reload will try to reload a
9746 ;; non-offsettable address by using r->r which won't make progress.
9747 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9748 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9750 ;; GPR store GPR load GPR move FPR store FPR load FPR move
9751 ;; GPR const AVX store AVX store AVX load AVX load VSX move
9752 ;; P9
0 P9 -
1 AVX
0/-
1 VSX
0 VSX -
1 P9 const
9755 (define_insn "*movdi_internal32"
9756 [(set (match_operand:DI
0 "nonimmediate_operand"
9757 "=Y, r, r, m, ^d, ^d,
9758 r, wY, Z, ^v, $v, ^wa,
9759 wa, wa, v, wa, *i, v,
9761 (match_operand:DI
1 "input_operand"
9762 "r, Y, r, ^d, m, ^d,
9763 IJKnF, ^v, $v, wY, Z, ^wa,
9764 Oj, wM, OjwM, Oj, wM, wS,
9767 && (gpc_reg_operand (operands[
0], DImode)
9768 || gpc_reg_operand (operands[
1], DImode))"
9790 "store, load, *, fpstore, fpload, fpsimple,
9791 *, fpstore, fpstore, fpload, fpload, veclogical,
9792 vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
9794 (set_attr "size" "
64")
9802 *, p9v, p7v, p9v, p7v, *,
9803 p9v, p9v, p7v, *, *, p7v,
9807 [(set (match_operand:DI
0 "gpc_reg_operand")
9808 (match_operand:DI
1 "const_int_operand"))]
9809 "! TARGET_POWERPC64 && reload_completed
9810 && gpr_or_gpr_p (operands[
0], operands[
1])
9811 && !direct_move_p (operands[
0], operands[
1])"
9812 [(set (match_dup
2) (match_dup
4))
9813 (set (match_dup
3) (match_dup
1))]
9815 HOST_WIDE_INT value = INTVAL (operands[
1]);
9816 operands[
2] = operand_subword_force (operands[
0], WORDS_BIG_ENDIAN ==
0,
9818 operands[
3] = operand_subword_force (operands[
0], WORDS_BIG_ENDIAN !=
0,
9820 operands[
4] = GEN_INT (value >>
32);
9821 operands[
1] = GEN_INT (sext_hwi (value,
32));
9825 [(set (match_operand:DIFD
0 "nonimmediate_operand")
9826 (match_operand:DIFD
1 "input_operand"))]
9827 "reload_completed && !TARGET_POWERPC64
9828 && gpr_or_gpr_p (operands[
0], operands[
1])
9829 && !direct_move_p (operands[
0], operands[
1])"
9832 rs6000_split_multireg_move (operands[
0], operands[
1]);
9836 ;; GPR store GPR load GPR move
9837 ;; GPR li GPR lis GPR pli GPR #
9838 ;; FPR store FPR load FPR move
9839 ;; AVX store AVX store AVX load AVX load VSX move
9840 ;; P9
0 P9 -
1 AVX
0/-
1 VSX
0 VSX -
1
9841 ;; P9 const AVX const
9842 ;; From SPR To SPR SPR<->SPR
9843 ;; VSX->GPR GPR->VSX
9844 (define_insn "*movdi_internal64"
9845 [(set (match_operand:DI
0 "nonimmediate_operand"
9854 (match_operand:DI
1 "input_operand"
9859 Oj, wM, OjwM, Oj, wM,
9864 && (gpc_reg_operand (operands[
0], DImode)
9865 || gpc_reg_operand (operands[
1], DImode))"
9897 fpstore, fpload, fpsimple,
9898 fpstore, fpstore, fpload, fpload, veclogical,
9899 vecsimple, vecsimple, vecsimple, veclogical, veclogical,
9900 vecsimple, vecsimple,
9903 (set_attr "size" "
64")
9917 p9v, p7v, p9v, p7v, *,
9918 p9v, p9v, p7v, *, *,
9923 ; Some DImode loads are best done as a load of -
1 followed by a mask
9926 [(set (match_operand:DI
0 "int_reg_operand")
9927 (match_operand:DI
1 "const_int_operand"))]
9929 && num_insns_constant (operands[
1], DImode) >
1
9930 && !IN_RANGE (INTVAL (operands[
1]), -
0x80000000,
0xffffffff)
9931 && rs6000_is_valid_and_mask (operands[
1], DImode)"
9935 (and:DI (match_dup
0)
9939 ;; Split a load of a large constant into the appropriate five-instruction
9940 ;; sequence. Handle anything in a constant number of insns.
9941 ;; When non-easy constants can go in the TOC, this should use
9942 ;; easy_fp_constant predicate.
9944 [(set (match_operand:DI
0 "int_reg_operand")
9945 (match_operand:DI
1 "const_int_operand"))]
9946 "TARGET_POWERPC64 && num_insns_constant (operands[
1], DImode) >
1"
9949 if (rs6000_emit_set_const (operands[
0], operands[
1]))
9956 [(set (match_operand:DI
0 "altivec_register_operand")
9957 (match_operand:DI
1 "s5bit_cint_operand"))]
9958 "TARGET_VSX && reload_completed"
9961 rtx op0 = operands[
0];
9962 rtx op1 = operands[
1];
9963 int r = REGNO (op0);
9964 rtx op0_v4si = gen_rtx_REG (V4SImode, r);
9966 emit_insn (gen_altivec_vspltisw (op0_v4si, op1));
9967 if (op1 != const0_rtx && op1 != constm1_rtx)
9969 rtx op0_v2di = gen_rtx_REG (V2DImode, r);
9970 emit_insn (gen_altivec_vupkhsw (op0_v2di, op0_v4si));
9975 ;; Split integer constants that can be loaded with XXSPLTIB and a
9976 ;; sign extend operation.
9978 [(set (match_operand:INT_ISA3
0 "altivec_register_operand")
9979 (match_operand:INT_ISA3
1 "xxspltib_constant_split"))]
9980 "TARGET_P9_VECTOR && reload_completed"
9983 rtx op0 = operands[
0];
9984 rtx op1 = operands[
1];
9985 int r = REGNO (op0);
9986 rtx op0_v16qi = gen_rtx_REG (V16QImode, r);
9988 emit_insn (gen_xxspltib_v16qi (op0_v16qi, op1));
9989 if (<MODE>mode == DImode)
9990 emit_insn (gen_vsx_sign_extend_v16qi_di (operands[
0], op0_v16qi));
9991 else if (<MODE>mode == SImode)
9992 emit_insn (gen_vsx_sign_extend_v16qi_si (operands[
0], op0_v16qi));
9993 else if (<MODE>mode == HImode)
9995 rtx op0_v8hi = gen_rtx_REG (V8HImode, r);
9996 emit_insn (gen_altivec_vupkhsb (op0_v8hi, op0_v16qi));
10002 ;; TImode/PTImode is similar, except that we usually want to compute the
10003 ;; address into a register and use lsi/stsi (the exception is during reload).
10005 (define_insn "*mov<mode>_string"
10006 [(set (match_operand:TI2
0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
10007 (match_operand:TI2
1 "input_operand" "r,r,Q,Y,r,n"))]
10008 "! TARGET_POWERPC64
10009 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
10010 && (gpc_reg_operand (operands[
0], <MODE>mode)
10011 || gpc_reg_operand (operands[
1], <MODE>mode))"
10013 [(set_attr "type" "store,store,load,load,*,*")
10014 (set_attr "update" "yes")
10015 (set_attr "indexed" "yes")
10016 (set_attr "cell_micro" "conditional")])
10018 (define_insn "*mov<mode>_ppc64"
10019 [(set (match_operand:TI2
0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
10020 (match_operand:TI2
1 "input_operand" "r,r,wQ,Y,r,n"))]
10021 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
10022 && (gpc_reg_operand (operands[
0], <MODE>mode)
10023 || gpc_reg_operand (operands[
1], <MODE>mode)))"
10025 return rs6000_output_move_128bit (operands);
10027 [(set_attr "type" "store,store,load,load,*,*")
10028 (set_attr "length" "
8")
10029 (set_attr "max_prefixed_insns" "
2")])
10032 [(set (match_operand:TI2
0 "int_reg_operand")
10033 (match_operand:TI2
1 "const_scalar_int_operand"))]
10035 && (VECTOR_MEM_NONE_P (<MODE>mode)
10036 || (reload_completed && INT_REGNO_P (REGNO (operands[
0]))))"
10037 [(set (match_dup
2) (match_dup
4))
10038 (set (match_dup
3) (match_dup
5))]
10040 operands[
2] = operand_subword_force (operands[
0], WORDS_BIG_ENDIAN ==
0,
10042 operands[
3] = operand_subword_force (operands[
0], WORDS_BIG_ENDIAN !=
0,
10044 if (CONST_WIDE_INT_P (operands[
1]))
10046 operands[
4] = GEN_INT (CONST_WIDE_INT_ELT (operands[
1],
1));
10047 operands[
5] = GEN_INT (CONST_WIDE_INT_ELT (operands[
1],
0));
10049 else if (CONST_INT_P (operands[
1]))
10051 operands[
4] = GEN_INT (- (INTVAL (operands[
1]) <
0));
10052 operands[
5] = operands[
1];
10059 [(set (match_operand:TI2
0 "nonimmediate_operand")
10060 (match_operand:TI2
1 "input_operand"))]
10062 && gpr_or_gpr_p (operands[
0], operands[
1])
10063 && !direct_move_p (operands[
0], operands[
1])
10064 && !quad_load_store_p (operands[
0], operands[
1])"
10067 rs6000_split_multireg_move (operands[
0], operands[
1]);
10071 (define_expand "setmemsi"
10072 [(parallel [(set (match_operand:BLK
0 "")
10073 (match_operand
2 "const_int_operand"))
10074 (use (match_operand:SI
1 ""))
10075 (use (match_operand:SI
3 ""))])]
10078 /* If value to set is not zero, use the library routine. */
10079 if (operands[
2] != const0_rtx)
10082 if (expand_block_clear (operands))
10088 ;; String compare N insn.
10089 ;; Argument
0 is the target (result)
10090 ;; Argument
1 is the destination
10091 ;; Argument
2 is the source
10092 ;; Argument
3 is the length
10093 ;; Argument
4 is the alignment
10095 (define_expand "cmpstrnsi"
10096 [(parallel [(set (match_operand:SI
0)
10097 (compare:SI (match_operand:BLK
1)
10098 (match_operand:BLK
2)))
10099 (use (match_operand:SI
3))
10100 (use (match_operand:SI
4))])]
10101 "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
10103 if (optimize_insn_for_size_p ())
10106 if (expand_strn_compare (operands,
0))
10112 ;; String compare insn.
10113 ;; Argument
0 is the target (result)
10114 ;; Argument
1 is the destination
10115 ;; Argument
2 is the source
10116 ;; Argument
3 is the alignment
10118 (define_expand "cmpstrsi"
10119 [(parallel [(set (match_operand:SI
0)
10120 (compare:SI (match_operand:BLK
1)
10121 (match_operand:BLK
2)))
10122 (use (match_operand:SI
3))])]
10123 "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
10125 if (optimize_insn_for_size_p ())
10128 if (expand_strn_compare (operands,
1))
10134 ;; Block compare insn.
10135 ;; Argument
0 is the target (result)
10136 ;; Argument
1 is the destination
10137 ;; Argument
2 is the source
10138 ;; Argument
3 is the length
10139 ;; Argument
4 is the alignment
10141 (define_expand "cmpmemsi"
10142 [(parallel [(set (match_operand:SI
0)
10143 (compare:SI (match_operand:BLK
1)
10144 (match_operand:BLK
2)))
10145 (use (match_operand:SI
3))
10146 (use (match_operand:SI
4))])]
10149 if (optimize_insn_for_size_p ())
10152 if (expand_block_compare (operands))
10158 ;; String/block copy insn (source and destination must not overlap).
10159 ;; Argument
0 is the destination
10160 ;; Argument
1 is the source
10161 ;; Argument
2 is the length
10162 ;; Argument
3 is the alignment
10164 (define_expand "cpymemsi"
10165 [(parallel [(set (match_operand:BLK
0 "")
10166 (match_operand:BLK
1 ""))
10167 (use (match_operand:SI
2 ""))
10168 (use (match_operand:SI
3 ""))])]
10171 if (expand_block_move (operands, false))
10177 ;; String/block move insn (source and destination may overlap).
10178 ;; Argument
0 is the destination
10179 ;; Argument
1 is the source
10180 ;; Argument
2 is the length
10181 ;; Argument
3 is the alignment
10183 (define_expand "movmemsi"
10184 [(parallel [(set (match_operand:BLK
0 "")
10185 (match_operand:BLK
1 ""))
10186 (use (match_operand:SI
2 ""))
10187 (use (match_operand:SI
3 ""))])]
10190 if (expand_block_move (operands, true))
10197 ;; Define insns that do load or store with update. Some of these we can
10198 ;; get by using pre-decrement or pre-increment, but the hardware can also
10199 ;; do cases where the increment is not the size of the object.
10201 ;; In all these cases, we use operands
0 and
1 for the register being
10202 ;; incremented because those are the operands that local-alloc will
10203 ;; tie and these are the pair most likely to be tieable (and the ones
10204 ;; that will benefit the most).
10206 (define_insn "*movdi_update1"
10207 [(set (match_operand:DI
3 "gpc_reg_operand" "=r,r")
10208 (mem:DI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10209 (match_operand:P
2 "reg_or_aligned_short_operand" "r,I"))))
10210 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10211 (plus:P (match_dup
1) (match_dup
2)))]
10212 "TARGET_POWERPC64 && TARGET_UPDATE
10213 && (!avoiding_indexed_address_p (DImode)
10214 || !gpc_reg_operand (operands[
2], Pmode))"
10218 [(set_attr "type" "load")
10219 (set_attr "update" "yes")
10220 (set_attr "indexed" "yes,no")])
10222 (define_insn "movdi_<mode>_update"
10223 [(set (mem:DI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10224 (match_operand:P
2 "reg_or_aligned_short_operand" "r,I")))
10225 (match_operand:DI
3 "gpc_reg_operand" "r,r"))
10226 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10227 (plus:P (match_dup
1) (match_dup
2)))]
10228 "TARGET_POWERPC64 && TARGET_UPDATE
10229 && (!avoiding_indexed_address_p (DImode)
10230 || !gpc_reg_operand (operands[
2], Pmode)
10231 || (REG_P (operands[
0])
10232 && REGNO (operands[
0]) == STACK_POINTER_REGNUM))"
10236 [(set_attr "type" "store")
10237 (set_attr "update" "yes")
10238 (set_attr "indexed" "yes,no")])
10240 ;; This pattern is only conditional on TARGET_64BIT, as it is
10241 ;; needed for stack allocation, even if the user passes -mno-update.
10242 (define_insn "movdi_update_stack"
10243 [(set (mem:DI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0,
0")
10244 (match_operand:DI
2 "reg_or_aligned_short_operand" "r,I")))
10245 (match_operand:DI
3 "gpc_reg_operand" "r,r"))
10246 (set (match_operand:DI
0 "gpc_reg_operand" "=b,b")
10247 (plus:DI (match_dup
1) (match_dup
2)))]
10252 [(set_attr "type" "store")
10253 (set_attr "update" "yes")
10254 (set_attr "indexed" "yes,no")])
10256 (define_insn "*movsi_update1"
10257 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
10258 (mem:SI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10259 (match_operand:P
2 "reg_or_short_operand" "r,I"))))
10260 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10261 (plus:P (match_dup
1) (match_dup
2)))]
10263 && (!avoiding_indexed_address_p (SImode)
10264 || !gpc_reg_operand (operands[
2], Pmode))"
10268 [(set_attr "type" "load")
10269 (set_attr "update" "yes")
10270 (set_attr "indexed" "yes,no")])
10272 (define_insn "*movsi_update2"
10273 [(set (match_operand:EXTSI
3 "gpc_reg_operand" "=r")
10275 (mem:SI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0")
10276 (match_operand:P
2 "gpc_reg_operand" "r")))))
10277 (set (match_operand:P
0 "gpc_reg_operand" "=b")
10278 (plus:P (match_dup
1) (match_dup
2)))]
10279 "TARGET_POWERPC64 && !avoiding_indexed_address_p (DImode)"
10281 [(set_attr "type" "load")
10282 (set_attr "sign_extend" "yes")
10283 (set_attr "update" "yes")
10284 (set_attr "indexed" "yes")])
10286 (define_insn "movsi_<mode>_update"
10287 [(set (mem:SI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10288 (match_operand:P
2 "reg_or_short_operand" "r,I")))
10289 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
10290 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10291 (plus:P (match_dup
1) (match_dup
2)))]
10293 && (!avoiding_indexed_address_p (SImode)
10294 || !gpc_reg_operand (operands[
2], Pmode)
10295 || (REG_P (operands[
0])
10296 && REGNO (operands[
0]) == STACK_POINTER_REGNUM))"
10300 [(set_attr "type" "store")
10301 (set_attr "update" "yes")
10302 (set_attr "indexed" "yes,no")])
10304 ;; This is an unconditional pattern; needed for stack allocation, even
10305 ;; if the user passes -mno-update.
10306 (define_insn "movsi_update_stack"
10307 [(set (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
10308 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
10309 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
10310 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
10311 (plus:SI (match_dup
1) (match_dup
2)))]
10316 [(set_attr "type" "store")
10317 (set_attr "update" "yes")
10318 (set_attr "indexed" "yes,no")])
10320 (define_insn "*movhi_update1"
10321 [(set (match_operand:HI
3 "gpc_reg_operand" "=r,r")
10322 (mem:HI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10323 (match_operand:P
2 "reg_or_short_operand" "r,I"))))
10324 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10325 (plus:P (match_dup
1) (match_dup
2)))]
10327 && (!avoiding_indexed_address_p (HImode)
10328 || !gpc_reg_operand (operands[
2], SImode))"
10332 [(set_attr "type" "load")
10333 (set_attr "update" "yes")
10334 (set_attr "indexed" "yes,no")])
10336 (define_insn "*movhi_update2"
10337 [(set (match_operand:EXTHI
3 "gpc_reg_operand" "=r,r")
10339 (mem:HI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10340 (match_operand:P
2 "reg_or_short_operand" "r,I")))))
10341 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10342 (plus:P (match_dup
1) (match_dup
2)))]
10344 && (!avoiding_indexed_address_p (HImode)
10345 || !gpc_reg_operand (operands[
2], Pmode))"
10349 [(set_attr "type" "load")
10350 (set_attr "update" "yes")
10351 (set_attr "indexed" "yes,no")])
10353 (define_insn "*movhi_update3"
10354 [(set (match_operand:EXTHI
3 "gpc_reg_operand" "=r,r")
10356 (mem:HI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10357 (match_operand:P
2 "reg_or_short_operand" "r,I")))))
10358 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10359 (plus:P (match_dup
1) (match_dup
2)))]
10361 && !(avoiding_indexed_address_p (HImode)
10362 && gpc_reg_operand (operands[
2], Pmode))"
10366 [(set_attr "type" "load")
10367 (set_attr "sign_extend" "yes")
10368 (set_attr "update" "yes")
10369 (set_attr "indexed" "yes,no")])
10371 (define_insn "*movhi_update4"
10372 [(set (mem:HI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10373 (match_operand:P
2 "reg_or_short_operand" "r,I")))
10374 (match_operand:HI
3 "gpc_reg_operand" "r,r"))
10375 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10376 (plus:P (match_dup
1) (match_dup
2)))]
10378 && (!avoiding_indexed_address_p (HImode)
10379 || !gpc_reg_operand (operands[
2], Pmode))"
10383 [(set_attr "type" "store")
10384 (set_attr "update" "yes")
10385 (set_attr "indexed" "yes,no")])
10387 (define_insn "*movqi_update1"
10388 [(set (match_operand:QI
3 "gpc_reg_operand" "=r,r")
10389 (mem:QI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10390 (match_operand:P
2 "reg_or_short_operand" "r,I"))))
10391 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10392 (plus:P (match_dup
1) (match_dup
2)))]
10394 && (!avoiding_indexed_address_p (QImode)
10395 || !gpc_reg_operand (operands[
2], Pmode))"
10399 [(set_attr "type" "load")
10400 (set_attr "update" "yes")
10401 (set_attr "indexed" "yes,no")])
10403 (define_insn "*movqi_update2"
10404 [(set (match_operand:EXTQI
3 "gpc_reg_operand" "=r,r")
10406 (mem:QI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10407 (match_operand:P
2 "reg_or_short_operand" "r,I")))))
10408 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10409 (plus:P (match_dup
1) (match_dup
2)))]
10411 && (!avoiding_indexed_address_p (QImode)
10412 || !gpc_reg_operand (operands[
2], Pmode))"
10416 [(set_attr "type" "load")
10417 (set_attr "update" "yes")
10418 (set_attr "indexed" "yes,no")])
10420 (define_insn "*movqi_update3"
10421 [(set (mem:QI (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10422 (match_operand:P
2 "reg_or_short_operand" "r,I")))
10423 (match_operand:QI
3 "gpc_reg_operand" "r,r"))
10424 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10425 (plus:P (match_dup
1) (match_dup
2)))]
10427 && (!avoiding_indexed_address_p (QImode)
10428 || !gpc_reg_operand (operands[
2], Pmode))"
10432 [(set_attr "type" "store")
10433 (set_attr "update" "yes")
10434 (set_attr "indexed" "yes,no")])
10436 (define_insn "*mov<SFDF:mode>_update1"
10437 [(set (match_operand:SFDF
3 "gpc_reg_operand" "=d,d")
10438 (mem:SFDF (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10439 (match_operand:P
2 "reg_or_short_operand" "r,I"))))
10440 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10441 (plus:P (match_dup
1) (match_dup
2)))]
10442 "TARGET_HARD_FLOAT && TARGET_UPDATE
10443 && (!avoiding_indexed_address_p (<SFDF:MODE>mode)
10444 || !gpc_reg_operand (operands[
2], Pmode))"
10448 [(set_attr "type" "fpload")
10449 (set_attr "update" "yes")
10450 (set_attr "indexed" "yes,no")
10451 (set_attr "size" "<SFDF:bits>")])
10453 (define_insn "*mov<SFDF:mode>_update2"
10454 [(set (mem:SFDF (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10455 (match_operand:P
2 "reg_or_short_operand" "r,I")))
10456 (match_operand:SFDF
3 "gpc_reg_operand" "d,d"))
10457 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10458 (plus:P (match_dup
1) (match_dup
2)))]
10459 "TARGET_HARD_FLOAT && TARGET_UPDATE
10460 && (!avoiding_indexed_address_p (<SFDF:MODE>mode)
10461 || !gpc_reg_operand (operands[
2], Pmode))"
10464 stf<sd>u %
3,%
2(%
0)"
10465 [(set_attr "type" "fpstore")
10466 (set_attr "update" "yes")
10467 (set_attr "indexed" "yes,no")
10468 (set_attr "size" "<SFDF:bits>")])
10470 (define_insn "*movsf_update3"
10471 [(set (match_operand:SF
3 "gpc_reg_operand" "=r,r")
10472 (mem:SF (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10473 (match_operand:P
2 "reg_or_short_operand" "r,I"))))
10474 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10475 (plus:P (match_dup
1) (match_dup
2)))]
10476 "TARGET_SOFT_FLOAT && TARGET_UPDATE
10477 && (!avoiding_indexed_address_p (SFmode)
10478 || !gpc_reg_operand (operands[
2], Pmode))"
10482 [(set_attr "type" "load")
10483 (set_attr "update" "yes")
10484 (set_attr "indexed" "yes,no")])
10486 (define_insn "*movsf_update4"
10487 [(set (mem:SF (plus:P (match_operand:P
1 "gpc_reg_operand" "
0,
0")
10488 (match_operand:P
2 "reg_or_short_operand" "r,I")))
10489 (match_operand:SF
3 "gpc_reg_operand" "r,r"))
10490 (set (match_operand:P
0 "gpc_reg_operand" "=b,b")
10491 (plus:P (match_dup
1) (match_dup
2)))]
10492 "TARGET_SOFT_FLOAT && TARGET_UPDATE
10493 && (!avoiding_indexed_address_p (SFmode)
10494 || !gpc_reg_operand (operands[
2], Pmode))"
10498 [(set_attr "type" "store")
10499 (set_attr "update" "yes")
10500 (set_attr "indexed" "yes,no")])
10503 ;; After inserting conditional returns we can sometimes have
10504 ;; unnecessary register moves. Unfortunately we cannot have a
10505 ;; modeless peephole here, because some single SImode sets have early
10506 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10507 ;; sequences, using get_attr_length here will smash the operands
10508 ;; array. Neither is there an early_cobbler_p predicate.
10509 ;; Also this optimization interferes with scalars going into
10510 ;; altivec registers (the code does reloading through the FPRs).
10512 [(set (match_operand:DF
0 "gpc_reg_operand")
10513 (match_operand:DF
1 "any_operand"))
10514 (set (match_operand:DF
2 "gpc_reg_operand")
10517 && peep2_reg_dead_p (
2, operands[
0])"
10518 [(set (match_dup
2) (match_dup
1))])
10521 [(set (match_operand:SF
0 "gpc_reg_operand")
10522 (match_operand:SF
1 "any_operand"))
10523 (set (match_operand:SF
2 "gpc_reg_operand")
10526 && peep2_reg_dead_p (
2, operands[
0])"
10527 [(set (match_dup
2) (match_dup
1))])
10532 (define_insn "*tls_gd_pcrel<bits>"
10533 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10534 (unspec:P [(match_operand:P
1 "rs6000_tls_symbol_ref" "")
10537 "HAVE_AS_TLS && TARGET_ELF"
10538 "la %
0,%
1@got@tlsgd@pcrel"
10539 [(set_attr "prefixed" "yes")])
10541 (define_insn_and_split "*tls_gd<bits>"
10542 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10543 (unspec:P [(match_operand:P
1 "rs6000_tls_symbol_ref" "")
10544 (match_operand:P
2 "gpc_reg_operand" "b")]
10546 "HAVE_AS_TLS && TARGET_ELF"
10547 "addi %
0,%
2,%
1@got@tlsgd"
10548 "&& TARGET_CMODEL != CMODEL_SMALL"
10549 [(set (match_dup
3)
10551 (unspec:P [(match_dup
1) (match_dup
2)] UNSPEC_TLSGD)))
10553 (lo_sum:P (match_dup
3)
10554 (unspec:P [(match_dup
1) (match_dup
2)] UNSPEC_TLSGD)))]
10556 operands[
3] = gen_reg_rtx (<MODE>mode);
10558 [(set (attr "length")
10559 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10563 (define_insn "*tls_gd_high<bits>"
10564 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10566 (unspec:P [(match_operand:P
1 "rs6000_tls_symbol_ref" "")
10567 (match_operand:P
2 "gpc_reg_operand" "b")]
10569 "HAVE_AS_TLS && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10570 "addis %
0,%
2,%
1@got@tlsgd@ha")
10572 (define_insn "*tls_gd_low<bits>"
10573 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10574 (lo_sum:P (match_operand:P
1 "gpc_reg_operand" "b")
10575 (unspec:P [(match_operand:P
2 "rs6000_tls_symbol_ref" "")
10576 (match_operand:P
3 "gpc_reg_operand" "b")]
10578 "HAVE_AS_TLS && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10579 "addi %
0,%
1,%
2@got@tlsgd@l")
10581 (define_insn "*tls_ld_pcrel<bits>"
10582 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10583 (unspec:P [(const_int
0)]
10585 "HAVE_AS_TLS && TARGET_ELF"
10586 "la %
0,%&@got@tlsld@pcrel"
10587 [(set_attr "prefixed" "yes")])
10589 (define_insn_and_split "*tls_ld<bits>"
10590 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10591 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")]
10593 "HAVE_AS_TLS && TARGET_ELF"
10594 "addi %
0,%
1,%&@got@tlsld"
10595 "&& TARGET_CMODEL != CMODEL_SMALL"
10596 [(set (match_dup
2)
10598 (unspec:P [(match_dup
1)] UNSPEC_TLSLD)))
10600 (lo_sum:P (match_dup
2)
10601 (unspec:P [(match_dup
1)] UNSPEC_TLSLD)))]
10603 operands[
2] = gen_reg_rtx (<MODE>mode);
10605 [(set (attr "length")
10606 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10610 (define_insn "*tls_ld_high<bits>"
10611 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10613 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")]
10615 "HAVE_AS_TLS && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10616 "addis %
0,%
1,%&@got@tlsld@ha")
10618 (define_insn "*tls_ld_low<bits>"
10619 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10620 (lo_sum:P (match_operand:P
1 "gpc_reg_operand" "b")
10621 (unspec:P [(match_operand:P
2 "gpc_reg_operand" "b")]
10623 "HAVE_AS_TLS && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10624 "addi %
0,%
1,%&@got@tlsld@l")
10626 (define_insn "tls_dtprel_<bits>"
10627 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10628 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10629 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10630 UNSPEC_TLSDTPREL))]
10632 "addi %
0,%
1,%
2@dtprel"
10633 [(set (attr "prefixed")
10634 (if_then_else (match_test "rs6000_tls_size ==
16")
10635 (const_string "no")
10636 (const_string "yes")))])
10638 (define_insn "tls_dtprel_ha_<bits>"
10639 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10640 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10641 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10642 UNSPEC_TLSDTPRELHA))]
10644 "addis %
0,%
1,%
2@dtprel@ha")
10646 (define_insn "tls_dtprel_lo_<bits>"
10647 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10648 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10649 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10650 UNSPEC_TLSDTPRELLO))]
10652 "addi %
0,%
1,%
2@dtprel@l")
10654 (define_insn_and_split "tls_got_dtprel_<bits>"
10655 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10656 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10657 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10658 UNSPEC_TLSGOTDTPREL))]
10660 "<ptrload> %
0,%
2@got@dtprel(%
1)"
10661 "&& TARGET_CMODEL != CMODEL_SMALL"
10662 [(set (match_dup
3)
10664 (unspec:P [(match_dup
1) (match_dup
2)] UNSPEC_TLSGOTDTPREL)))
10666 (lo_sum:P (match_dup
3)
10667 (unspec:P [(match_dup
1) (match_dup
2)] UNSPEC_TLSGOTDTPREL)))]
10669 operands[
3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10671 [(set (attr "length")
10672 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10676 (define_insn "*tls_got_dtprel_high<bits>"
10677 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10679 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10680 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10681 UNSPEC_TLSGOTDTPREL)))]
10682 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10683 "addis %
0,%
1,%
2@got@dtprel@ha")
10685 (define_insn "*tls_got_dtprel_low<bits>"
10686 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10687 (lo_sum:P (match_operand:P
1 "gpc_reg_operand" "b")
10688 (unspec:P [(match_operand:P
3 "gpc_reg_operand" "b")
10689 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10690 UNSPEC_TLSGOTDTPREL)))]
10691 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10692 "<ptrload> %
0,%
2@got@dtprel@l(%
1)")
10694 (define_insn "tls_tprel_<bits>"
10695 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10696 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10697 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10700 "addi %
0,%
1,%
2@tprel"
10701 [(set (attr "prefixed")
10702 (if_then_else (match_test "rs6000_tls_size ==
16")
10703 (const_string "no")
10704 (const_string "yes")))])
10706 (define_insn "tls_tprel_ha_<bits>"
10707 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10708 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10709 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10710 UNSPEC_TLSTPRELHA))]
10712 "addis %
0,%
1,%
2@tprel@ha")
10714 (define_insn "tls_tprel_lo_<bits>"
10715 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10716 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10717 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10718 UNSPEC_TLSTPRELLO))]
10720 "addi %
0,%
1,%
2@tprel@l")
10722 (define_insn "*tls_got_tprel_pcrel_<bits>"
10723 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10724 (unspec:P [(const_int
0)
10725 (match_operand:P
1 "rs6000_tls_symbol_ref" "")]
10726 UNSPEC_TLSGOTTPREL))]
10728 "<ptrload> %
0,%
1@got@tprel@pcrel"
10729 [(set_attr "prefixed" "yes")])
10731 ;; "b" output constraint here and on tls_tls input to support linker tls
10732 ;; optimization. The linker may edit the instructions emitted by a
10733 ;; tls_got_tprel/tls_tls pair to addis,addi.
10734 (define_insn_and_split "tls_got_tprel_<bits>"
10735 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10736 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10737 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10738 UNSPEC_TLSGOTTPREL))]
10740 "<ptrload> %
0,%
2@got@tprel(%
1)"
10741 "&& TARGET_CMODEL != CMODEL_SMALL"
10742 [(set (match_dup
3)
10744 (unspec:P [(match_dup
1) (match_dup
2)] UNSPEC_TLSGOTTPREL)))
10746 (lo_sum:P (match_dup
3)
10747 (unspec:P [(match_dup
1) (match_dup
2)] UNSPEC_TLSGOTTPREL)))]
10749 operands[
3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10751 [(set (attr "length")
10752 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10756 (define_insn "*tls_got_tprel_high<bits>"
10757 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
10759 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10760 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10761 UNSPEC_TLSGOTTPREL)))]
10762 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10763 "addis %
0,%
1,%
2@got@tprel@ha")
10765 (define_insn "*tls_got_tprel_low<bits>"
10766 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10767 (lo_sum:P (match_operand:P
1 "gpc_reg_operand" "b")
10768 (unspec:P [(match_operand:P
3 "gpc_reg_operand" "b")
10769 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10770 UNSPEC_TLSGOTTPREL)))]
10771 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10772 "<ptrload> %
0,%
2@got@tprel@l(%
1)")
10774 (define_insn "tls_tls_pcrel_<bits>"
10775 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10776 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10777 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10778 UNSPEC_TLSTLS_PCREL))]
10779 "TARGET_ELF && HAVE_AS_TLS"
10780 "add %
0,%
1,%
2@tls@pcrel")
10782 (define_insn "tls_tls_<bits>"
10783 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
10784 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
10785 (match_operand:P
2 "rs6000_tls_symbol_ref" "")]
10787 "TARGET_ELF && HAVE_AS_TLS"
10788 "add %
0,%
1,%
2@tls")
10790 (define_expand "tls_get_tpointer"
10791 [(set (match_operand:SI
0 "gpc_reg_operand")
10792 (unspec:SI [(const_int
0)] UNSPEC_TLSTLS))]
10793 "TARGET_XCOFF && HAVE_AS_TLS"
10795 emit_insn (gen_tls_get_tpointer_internal ());
10796 emit_move_insn (operands[
0], gen_rtx_REG (SImode,
3));
10800 (define_insn "tls_get_tpointer_internal"
10802 (unspec:SI [(const_int
0)] UNSPEC_TLSTLS))
10803 (clobber (reg:SI LR_REGNO))]
10804 "TARGET_XCOFF && HAVE_AS_TLS"
10805 "bla .__get_tpointer")
10807 (define_expand "tls_get_addr<mode>"
10808 [(set (match_operand:P
0 "gpc_reg_operand")
10809 (unspec:P [(match_operand:P
1 "gpc_reg_operand")
10810 (match_operand:P
2 "gpc_reg_operand")] UNSPEC_TLSTLS))]
10811 "TARGET_XCOFF && HAVE_AS_TLS"
10813 emit_move_insn (gen_rtx_REG (Pmode,
3), operands[
1]);
10814 emit_move_insn (gen_rtx_REG (Pmode,
4), operands[
2]);
10815 emit_insn (gen_tls_get_addr_internal<mode> ());
10816 emit_move_insn (operands[
0], gen_rtx_REG (Pmode,
3));
10820 (define_insn "tls_get_addr_internal<mode>"
10822 (unspec:P [(reg:P
3) (reg:P
4)] UNSPEC_TLSTLS))
10823 (clobber (reg:P
0))
10824 (clobber (reg:P
4))
10825 (clobber (reg:P
5))
10826 (clobber (reg:P
11))
10827 (clobber (reg:CC CR0_REGNO))
10828 (clobber (reg:P LR_REGNO))]
10829 "TARGET_XCOFF && HAVE_AS_TLS"
10830 "bla .__tls_get_addr")
10832 ;; Next come insns related to the calling sequence.
10834 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10835 ;; We move the back-chain and decrement the stack pointer.
10837 ;; Operand1 is more naturally reg_or_short_operand. However, for a large
10838 ;; constant alloca, using that predicate will force the generic code to put
10839 ;; the constant size into a register before calling the expander.
10841 ;; As a result the expander would not have the constant size information
10842 ;; in those cases and would have to generate less efficient code.
10844 ;; Thus we allow reg_or_cint_operand instead so that the expander can see
10845 ;; the constant size. The value is forced into a register if necessary.
10847 (define_expand "allocate_stack"
10848 [(set (match_operand
0 "gpc_reg_operand")
10849 (minus (reg
1) (match_operand
1 "reg_or_cint_operand")))
10851 (minus (reg
1) (match_dup
1)))]
10854 rtx chain = gen_reg_rtx (Pmode);
10855 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10857 rtx insn, par, set, mem;
10859 /* By allowing reg_or_cint_operand as the predicate we can get
10860 better code for stack-clash-protection because we do not lose
10861 size information. But the rest of the code expects the operand
10862 to be reg_or_short_operand. If it isn't, then force it into
10864 rtx orig_op1 = operands[
1];
10865 if (!reg_or_short_operand (operands[
1], Pmode))
10866 operands[
1] = force_reg (Pmode, operands[
1]);
10868 emit_move_insn (chain, stack_bot);
10870 /* Check stack bounds if necessary. */
10871 if (crtl->limit_stack)
10874 available = expand_binop (Pmode, sub_optab,
10875 stack_pointer_rtx, stack_limit_rtx,
10876 NULL_RTX,
1, OPTAB_WIDEN);
10877 emit_insn (gen_cond_trap (LTU, available, operands[
1], const0_rtx));
10880 /* Allocate and probe if requested.
10881 This may look similar to the loop we use for prologue allocations,
10882 but it is critically different. For the former we know the loop
10883 will iterate, but do not know that generally here. The former
10884 uses that knowledge to rotate the loop. Combining them would be
10885 possible with some performance cost. */
10886 if (flag_stack_clash_protection)
10888 rtx rounded_size, last_addr, residual;
10889 HOST_WIDE_INT probe_interval;
10890 compute_stack_clash_protection_loop_data (&rounded_size, &last_addr,
10891 &residual, &probe_interval,
10894 /* We do occasionally get in here with constant sizes, we might
10895 as well do a reasonable job when we obviously can. */
10896 if (rounded_size != const0_rtx)
10898 rtx loop_lab, end_loop;
10899 bool rotated = CONST_INT_P (rounded_size);
10900 rtx update = GEN_INT (-probe_interval);
10901 if (probe_interval >
32768)
10902 update = force_reg (Pmode, update);
10904 emit_stack_clash_protection_probe_loop_start (&loop_lab, &end_loop,
10905 last_addr, rotated);
10908 emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
10912 emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
10915 emit_stack_clash_protection_probe_loop_end (loop_lab, end_loop,
10916 last_addr, rotated);
10919 /* Now handle residuals. We just have to set operands[
1] correctly
10920 and let the rest of the expander run. */
10921 operands[
1] = residual;
10924 if (!(CONST_INT_P (operands[
1])
10925 && IN_RANGE (INTVAL (operands[
1]), -
32767,
32768)))
10927 operands[
1] = force_reg (Pmode, operands[
1]);
10928 neg_op0 = gen_reg_rtx (Pmode);
10929 emit_insn (gen_neg2 (Pmode, neg_op0, operands[
1]));
10932 neg_op0 = GEN_INT (-INTVAL (operands[
1]));
10934 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10935 : gen_movdi_update_stack))
10936 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10938 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10939 it now and set the alias set/attributes. The above gen_*_update
10940 calls will generate a PARALLEL with the MEM set being the first
10942 par = PATTERN (insn);
10943 gcc_assert (GET_CODE (par) == PARALLEL);
10944 set = XVECEXP (par,
0,
0);
10945 gcc_assert (GET_CODE (set) == SET);
10946 mem = SET_DEST (set);
10947 gcc_assert (MEM_P (mem));
10948 MEM_NOTRAP_P (mem) =
1;
10949 set_mem_alias_set (mem, get_frame_alias_set ());
10951 emit_move_insn (operands[
0], virtual_stack_dynamic_rtx);
10955 ;; These patterns say how to save and restore the stack pointer. We need not
10956 ;; save the stack pointer at function level since we are careful to
10957 ;; preserve the backchain. At block level, we have to restore the backchain
10958 ;; when we restore the stack pointer.
10960 ;; For nonlocal gotos, we must save both the stack pointer and its
10961 ;; backchain and restore both. Note that in the nonlocal case, the
10962 ;; save area is a memory location.
10964 (define_expand "save_stack_function"
10965 [(match_operand
0 "any_operand")
10966 (match_operand
1 "any_operand")]
10970 (define_expand "restore_stack_function"
10971 [(match_operand
0 "any_operand")
10972 (match_operand
1 "any_operand")]
10976 ;; Adjust stack pointer (op0) to a new value (op1).
10977 ;; First copy old stack backchain to new location, and ensure that the
10978 ;; scheduler won't reorder the sp assignment before the backchain write.
10979 (define_expand "restore_stack_block"
10980 [(set (match_dup
2) (match_dup
3))
10981 (set (match_dup
4) (match_dup
2))
10983 (set (match_operand
0 "register_operand")
10984 (match_operand
1 "register_operand"))]
10989 operands[
1] = force_reg (Pmode, operands[
1]);
10990 operands[
2] = gen_reg_rtx (Pmode);
10991 operands[
3] = gen_frame_mem (Pmode, operands[
0]);
10992 operands[
4] = gen_frame_mem (Pmode, operands[
1]);
10993 p = rtvec_alloc (
1);
10994 RTVEC_ELT (p,
0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[
0]),
10996 operands[
5] = gen_rtx_PARALLEL (VOIDmode, p);
10999 (define_expand "save_stack_nonlocal"
11000 [(set (match_dup
3) (match_dup
4))
11001 (set (match_operand
0 "memory_operand") (match_dup
3))
11002 (set (match_dup
2) (match_operand
1 "register_operand"))]
11005 int units_per_word = (TARGET_32BIT) ?
4 :
8;
11007 /* Copy the backchain to the first word, sp to the second. */
11008 operands[
0] = adjust_address_nv (operands[
0], Pmode,
0);
11009 operands[
2] = adjust_address_nv (operands[
0], Pmode, units_per_word);
11010 operands[
3] = gen_reg_rtx (Pmode);
11011 operands[
4] = gen_frame_mem (Pmode, operands[
1]);
11014 (define_expand "restore_stack_nonlocal"
11015 [(set (match_dup
2) (match_operand
1 "memory_operand"))
11016 (set (match_dup
3) (match_dup
4))
11017 (set (match_dup
5) (match_dup
2))
11019 (set (match_operand
0 "register_operand") (match_dup
3))]
11022 int units_per_word = (TARGET_32BIT) ?
4 :
8;
11025 /* Restore the backchain from the first word, sp from the second. */
11026 operands[
2] = gen_reg_rtx (Pmode);
11027 operands[
3] = gen_reg_rtx (Pmode);
11028 operands[
1] = adjust_address_nv (operands[
1], Pmode,
0);
11029 operands[
4] = adjust_address_nv (operands[
1], Pmode, units_per_word);
11030 operands[
5] = gen_frame_mem (Pmode, operands[
3]);
11031 p = rtvec_alloc (
1);
11032 RTVEC_ELT (p,
0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[
0]),
11034 operands[
6] = gen_rtx_PARALLEL (VOIDmode, p);
11037 ;; Load up a PC-relative address. Print_operand_address will append a @pcrel
11038 ;; to the symbol or label.
11039 (define_insn "*pcrel_local_addr"
11040 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
11041 (match_operand:DI
1 "pcrel_local_address"))]
11044 [(set_attr "prefixed" "yes")])
11046 ;; Load up a PC-relative address to an external symbol. If the symbol and the
11047 ;; program are both defined in the main program, the linker will optimize this
11048 ;; to a PADDI. Otherwise, it will create a GOT address that is relocated by
11049 ;; the dynamic linker and loaded up. Print_operand_address will append a
11050 ;; @got@pcrel to the symbol.
11051 (define_insn "*pcrel_extern_addr"
11052 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
11053 (match_operand:DI
1 "pcrel_external_address"))]
11056 [(set_attr "prefixed" "yes")
11057 (set_attr "type" "load")
11058 (set_attr "loads_external_address" "yes")])
11060 ;; TOC register handling.
11062 ;; Code to initialize the TOC register...
11064 (define_insn "load_toc_aix_si"
11065 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
11066 (unspec:SI [(const_int
0)] UNSPEC_TOC))
11067 (use (reg:SI
2))])]
11068 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
11071 extern int need_toc_init;
11073 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC",
1);
11074 operands[
1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11075 operands[
2] = gen_rtx_REG (Pmode,
2);
11076 return "lwz %
0,%
1(%
2)";
11078 [(set_attr "type" "load")
11079 (set_attr "update" "no")
11080 (set_attr "indexed" "no")])
11082 (define_insn "load_toc_aix_di"
11083 [(parallel [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
11084 (unspec:DI [(const_int
0)] UNSPEC_TOC))
11085 (use (reg:DI
2))])]
11086 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
11089 extern int need_toc_init;
11091 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC",
11092 !TARGET_ELF || !TARGET_MINIMAL_TOC);
11094 strcat (buf, "@toc");
11095 operands[
1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11096 operands[
2] = gen_rtx_REG (Pmode,
2);
11097 return "ld %
0,%
1(%
2)";
11099 [(set_attr "type" "load")
11100 (set_attr "update" "no")
11101 (set_attr "indexed" "no")])
11103 (define_insn "load_toc_v4_pic_si"
11104 [(set (reg:SI LR_REGNO)
11105 (unspec:SI [(const_int
0)] UNSPEC_TOC))]
11106 "DEFAULT_ABI == ABI_V4 && flag_pic ==
1 && TARGET_32BIT"
11107 "bl _GLOBAL_OFFSET_TABLE_@local-
4"
11108 [(set_attr "type" "branch")])
11110 (define_expand "load_toc_v4_PIC_1"
11111 [(parallel [(set (reg:SI LR_REGNO)
11112 (match_operand:SI
0 "immediate_operand" "s"))
11113 (use (unspec [(match_dup
0)] UNSPEC_TOC))])]
11114 "TARGET_ELF && DEFAULT_ABI == ABI_V4
11115 && (flag_pic ==
2 || (flag_pic && TARGET_SECURE_PLT))"
11118 (define_insn "load_toc_v4_PIC_1_normal"
11119 [(set (reg:SI LR_REGNO)
11120 (match_operand:SI
0 "immediate_operand" "s"))
11121 (use (unspec [(match_dup
0)] UNSPEC_TOC))]
11122 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11123 && (flag_pic ==
2 || (flag_pic && TARGET_SECURE_PLT))"
11124 "bcl
20,
31,%
0\n%
0:"
11125 [(set_attr "type" "branch")
11126 (set_attr "cannot_copy" "yes")])
11128 (define_insn "load_toc_v4_PIC_1_476"
11129 [(set (reg:SI LR_REGNO)
11130 (match_operand:SI
0 "immediate_operand" "s"))
11131 (use (unspec [(match_dup
0)] UNSPEC_TOC))]
11132 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11133 && (flag_pic ==
2 || (flag_pic && TARGET_SECURE_PLT))"
11136 static char templ[
32];
11138 get_ppc476_thunk_name (name);
11139 sprintf (templ, "bl %s
\n%%
0:", name);
11142 [(set_attr "type" "branch")
11143 (set_attr "cannot_copy" "yes")])
11145 (define_expand "load_toc_v4_PIC_1b"
11146 [(parallel [(set (reg:SI LR_REGNO)
11147 (unspec:SI [(match_operand:SI
0 "immediate_operand" "s")
11148 (label_ref (match_operand
1 ""))]
11151 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic ==
2"
11154 (define_insn "load_toc_v4_PIC_1b_normal"
11155 [(set (reg:SI LR_REGNO)
11156 (unspec:SI [(match_operand:SI
0 "immediate_operand" "s")
11157 (label_ref (match_operand
1 "" ""))]
11160 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic ==
2"
11161 "bcl
20,
31,$+
8\;.long %
0-$"
11162 [(set_attr "type" "branch")
11163 (set_attr "length" "
8")])
11165 (define_insn "load_toc_v4_PIC_1b_476"
11166 [(set (reg:SI LR_REGNO)
11167 (unspec:SI [(match_operand:SI
0 "immediate_operand" "s")
11168 (label_ref (match_operand
1 "" ""))]
11171 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic ==
2"
11174 static char templ[
32];
11176 get_ppc476_thunk_name (name);
11177 sprintf (templ, "bl %s\;b $+
8\;.long %%
0-$", name);
11180 [(set_attr "type" "branch")
11181 (set_attr "length" "
16")])
11183 (define_insn "load_toc_v4_PIC_2"
11184 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
11186 (match_operand:SI
1 "gpc_reg_operand" "b")
11188 (minus:SI (match_operand:SI
2 "immediate_operand" "s")
11189 (match_operand:SI
3 "immediate_operand" "s"))))))]
11190 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic ==
2"
11192 [(set_attr "type" "load")])
11194 (define_insn "load_toc_v4_PIC_3b"
11195 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
11197 (match_operand:SI
1 "gpc_reg_operand" "b")
11200 (minus:SI (match_operand:SI
2 "symbol_ref_operand" "s")
11201 (match_operand:SI
3 "symbol_ref_operand" "s"))))))]
11202 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11203 "addis %
0,%
1,%
2-%
3@ha")
11205 (define_insn "load_toc_v4_PIC_3c"
11206 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
11208 (match_operand:SI
1 "gpc_reg_operand" "b")
11210 (minus:SI (match_operand:SI
2 "symbol_ref_operand" "s")
11211 (match_operand:SI
3 "symbol_ref_operand" "s")))))]
11212 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11213 "addi %
0,%
1,%
2-%
3@l")
11215 ;; If the TOC is shared over a translation unit, as happens with all
11216 ;; the kinds of PIC that we support, we need to restore the TOC
11217 ;; pointer only when jumping over units of translation.
11218 ;; On Darwin, we need to reload the picbase.
11220 (define_expand "builtin_setjmp_receiver"
11221 [(use (label_ref (match_operand
0 "")))]
11222 "(DEFAULT_ABI == ABI_V4 && flag_pic ==
1)
11223 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11224 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11227 if (DEFAULT_ABI == ABI_DARWIN)
11229 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11230 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11234 crtl->uses_pic_offset_table =
1;
11235 ASM_GENERATE_INTERNAL_LABEL(tmplab, "LSJR",
11236 CODE_LABEL_NUMBER (operands[
0]));
11237 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11239 emit_insn (gen_load_macho_picbase (Pmode, tmplabrtx));
11240 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11241 emit_insn (gen_macho_correct_pic (Pmode, picreg, picreg,
11242 picrtx, tmplabrtx));
11246 rs6000_emit_load_toc_table (FALSE);
11250 ;; Largetoc support
11251 (define_insn "*largetoc_high"
11252 [(set (match_operand:DI
0 "gpc_reg_operand" "=b*r")
11254 (unspec [(match_operand:DI
1 "" "")
11255 (match_operand:DI
2 "gpc_reg_operand" "b")]
11257 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11258 "addis %
0,%
2,%
1@toc@ha")
11260 (define_insn "*largetoc_high_aix<mode>"
11261 [(set (match_operand:P
0 "gpc_reg_operand" "=b*r")
11263 (unspec [(match_operand:P
1 "" "")
11264 (match_operand:P
2 "gpc_reg_operand" "b")]
11266 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11267 "addis %
0,%
1@u(%
2)")
11269 (define_insn "*largetoc_high_plus"
11270 [(set (match_operand:DI
0 "gpc_reg_operand" "=b*r")
11273 (unspec [(match_operand:DI
1 "" "")
11274 (match_operand:DI
2 "gpc_reg_operand" "b")]
11276 (match_operand:DI
3 "add_cint_operand" "n"))))]
11277 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11278 "addis %
0,%
2,%
1+%
3@toc@ha")
11280 (define_insn "*largetoc_high_plus_aix<mode>"
11281 [(set (match_operand:P
0 "gpc_reg_operand" "=b*r")
11284 (unspec [(match_operand:P
1 "" "")
11285 (match_operand:P
2 "gpc_reg_operand" "b")]
11287 (match_operand:P
3 "add_cint_operand" "n"))))]
11288 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11289 "addis %
0,%
1+%
3@u(%
2)")
11291 (define_insn "*largetoc_low"
11292 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
11293 (lo_sum:DI (match_operand:DI
1 "gpc_reg_operand" "b")
11294 (match_operand:DI
2 "" "")))]
11295 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
11298 (define_insn "*largetoc_low_aix<mode>"
11299 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
11300 (lo_sum:P (match_operand:P
1 "gpc_reg_operand" "b")
11301 (match_operand:P
2 "" "")))]
11302 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
11305 (define_insn_and_split "*tocref<mode>"
11306 [(set (match_operand:P
0 "gpc_reg_operand" "=b")
11307 (match_operand:P
1 "small_toc_ref" "R"))]
11309 && legitimate_constant_pool_address_p (operands[
1], QImode, false)"
11311 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
11312 [(set (match_dup
0) (high:P (match_dup
1)))
11313 (set (match_dup
0) (lo_sum:P (match_dup
0) (match_dup
1)))])
11315 ;; Elf specific ways of loading addresses for non-PIC code.
11316 ;; The output of this could be r0, but we make a very strong
11317 ;; preference for a base register because it will usually
11318 ;; be needed there.
11319 (define_insn "elf_high"
11320 [(set (match_operand:SI
0 "gpc_reg_operand" "=b*r")
11321 (high:SI (match_operand
1 "" "")))]
11322 "TARGET_ELF && !TARGET_64BIT && !flag_pic"
11325 (define_insn "elf_low"
11326 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
11327 (lo_sum:SI (match_operand:SI
1 "gpc_reg_operand" "b")
11328 (match_operand
2 "" "")))]
11329 "TARGET_ELF && !TARGET_64BIT && !flag_pic"
11332 (define_insn "*pltseq_tocsave_<mode>"
11333 [(set (match_operand:P
0 "memory_operand" "=m")
11334 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "b")
11335 (match_operand:P
2 "symbol_ref_operand" "s")
11336 (match_operand:P
3 "" "")]
11339 && DEFAULT_ABI == ABI_ELFv2"
11341 return rs6000_pltseq_template (operands, RS6000_PLTSEQ_TOCSAVE);
11344 (define_insn "*pltseq_plt16_ha_<mode>"
11345 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
11346 (unspec:P [(match_operand:P
1 "" "")
11347 (match_operand:P
2 "symbol_ref_operand" "s")
11348 (match_operand:P
3 "" "")]
11352 return rs6000_pltseq_template (operands, RS6000_PLTSEQ_PLT16_HA);
11355 (define_insn "*pltseq_plt16_lo_<mode>"
11356 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
11357 (unspec_volatile:P [(match_operand:P
1 "gpc_reg_operand" "b")
11358 (match_operand:P
2 "symbol_ref_operand" "s")
11359 (match_operand:P
3 "" "")]
11360 UNSPECV_PLT16_LO))]
11363 return rs6000_pltseq_template (operands, RS6000_PLTSEQ_PLT16_LO);
11365 [(set_attr "type" "load")])
11367 (define_insn "*pltseq_mtctr_<mode>"
11368 [(set (match_operand:P
0 "register_operand" "=c")
11369 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "r")
11370 (match_operand:P
2 "symbol_ref_operand" "s")
11371 (match_operand:P
3 "" "")]
11375 return rs6000_pltseq_template (operands, RS6000_PLTSEQ_MTCTR);
11378 (define_insn "*pltseq_plt_pcrel<mode>"
11379 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
11380 (unspec_volatile:P [(match_operand:P
1 "" "")
11381 (match_operand:P
2 "symbol_ref_operand" "s")
11382 (match_operand:P
3 "" "")]
11383 UNSPECV_PLT_PCREL))]
11384 "HAVE_AS_PLTSEQ && TARGET_ELF
11385 && rs6000_pcrel_p ()"
11387 return rs6000_pltseq_template (operands, RS6000_PLTSEQ_PLT_PCREL34);
11389 [(set_attr "type" "load")
11390 (set_attr "length" "
12")])
11392 ;; Call and call_value insns
11393 ;; For the purposes of expanding calls, Darwin is very similar to SYSV.
11394 (define_expand "call"
11395 [(parallel [(call (mem:SI (match_operand
0 "address_operand"))
11396 (match_operand
1 ""))
11397 (use (match_operand
2 ""))
11398 (clobber (reg:SI LR_REGNO))])]
11402 if (MACHOPIC_INDIRECT)
11403 operands[
0] = machopic_indirect_call_target (operands[
0]);
11406 gcc_assert (MEM_P (operands[
0]));
11408 operands[
0] = XEXP (operands[
0],
0);
11410 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11411 rs6000_call_aix (NULL_RTX, operands[
0], operands[
1], operands[
2]);
11412 else if (DEFAULT_ABI == ABI_V4)
11413 rs6000_call_sysv (NULL_RTX, operands[
0], operands[
1], operands[
2]);
11414 else if (DEFAULT_ABI == ABI_DARWIN)
11415 rs6000_call_darwin (NULL_RTX, operands[
0], operands[
1], operands[
2]);
11417 gcc_unreachable ();
11422 (define_expand "call_value"
11423 [(parallel [(set (match_operand
0 "")
11424 (call (mem:SI (match_operand
1 "address_operand"))
11425 (match_operand
2 "")))
11426 (use (match_operand
3 ""))
11427 (clobber (reg:SI LR_REGNO))])]
11431 if (MACHOPIC_INDIRECT)
11432 operands[
1] = machopic_indirect_call_target (operands[
1]);
11435 gcc_assert (MEM_P (operands[
1]));
11437 operands[
1] = XEXP (operands[
1],
0);
11439 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11440 rs6000_call_aix (operands[
0], operands[
1], operands[
2], operands[
3]);
11441 else if (DEFAULT_ABI == ABI_V4)
11442 rs6000_call_sysv (operands[
0], operands[
1], operands[
2], operands[
3]);
11443 else if (DEFAULT_ABI == ABI_DARWIN)
11444 rs6000_call_darwin (operands[
0], operands[
1], operands[
2], operands[
3]);
11446 gcc_unreachable ();
11451 ;; Call to function in current module. No TOC pointer reload needed.
11452 ;; Operand2 is nonzero if we are using the V
.4 calling sequence and
11453 ;; either the function was not prototyped, or it was prototyped as a
11454 ;; variable argument function. It is >
0 if FP registers were passed
11455 ;; and <
0 if they were not.
11457 (define_insn "*call_local<mode>"
11458 [(call (mem:SI (match_operand:P
0 "current_file_function_operand" "s,s"))
11460 (use (match_operand:SI
2 "immediate_operand" "O,n"))
11461 (clobber (reg:P LR_REGNO))]
11462 "(INTVAL (operands[
2]) & CALL_LONG) ==
0"
11464 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
11465 output_asm_insn ("crxor
6,
6,
6", operands);
11467 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
11468 output_asm_insn ("creqv
6,
6,
6", operands);
11470 if (rs6000_pcrel_p ())
11471 return "bl %z0@notoc";
11472 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0";
11474 [(set_attr "type" "branch")
11475 (set_attr "length" "
4,
8")])
11477 (define_insn "*call_value_local<mode>"
11478 [(set (match_operand
0 "" "")
11479 (call (mem:SI (match_operand:P
1 "current_file_function_operand" "s,s"))
11480 (match_operand
2)))
11481 (use (match_operand:SI
3 "immediate_operand" "O,n"))
11482 (clobber (reg:P LR_REGNO))]
11483 "(INTVAL (operands[
3]) & CALL_LONG) ==
0"
11485 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
11486 output_asm_insn ("crxor
6,
6,
6", operands);
11488 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
11489 output_asm_insn ("creqv
6,
6,
6", operands);
11491 if (rs6000_pcrel_p ())
11492 return "bl %z1@notoc";
11493 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1";
11495 [(set_attr "type" "branch")
11496 (set_attr "length" "
4,
8")])
11499 ;; A function pointer under System V is just a normal pointer
11500 ;; operands[
0] is the function pointer
11501 ;; operands[
1] is the tls call arg
11502 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument
11503 ;; which indicates how to set cr1
11505 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11506 [(call (mem:SI (match_operand:P
0 "indirect_call_operand" "c,*l,X"))
11508 (use (match_operand:SI
2 "immediate_operand" "n,n,n"))
11509 (clobber (reg:P LR_REGNO))]
11510 "DEFAULT_ABI == ABI_V4
11511 || DEFAULT_ABI == ABI_DARWIN"
11513 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
11514 output_asm_insn ("crxor
6,
6,
6", operands);
11516 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
11517 output_asm_insn ("creqv
6,
6,
6", operands);
11519 return rs6000_indirect_call_template (operands,
0);
11521 [(set_attr "type" "jmpreg")
11522 (set (attr "length")
11523 (cond [(and (and (match_test "!rs6000_speculate_indirect_jumps")
11524 (match_test "which_alternative !=
1"))
11525 (match_test "(INTVAL (operands[
2]) & (CALL_V4_SET_FP_ARGS | CALL_V4_CLEAR_FP_ARGS))"))
11526 (const_string "
12")
11527 (ior (and (match_test "!rs6000_speculate_indirect_jumps")
11528 (match_test "which_alternative !=
1"))
11529 (match_test "(INTVAL (operands[
2]) & (CALL_V4_SET_FP_ARGS | CALL_V4_CLEAR_FP_ARGS))"))
11530 (const_string "
8")]
11531 (const_string "
4")))])
11533 (define_insn "*call_nonlocal_sysv<mode>"
11534 [(call (mem:SI (match_operand:P
0 "symbol_ref_operand" "s,s"))
11536 (use (match_operand:SI
2 "immediate_operand" "O,n"))
11537 (clobber (reg:P LR_REGNO))]
11538 "(DEFAULT_ABI == ABI_DARWIN
11539 || (DEFAULT_ABI == ABI_V4
11540 && (INTVAL (operands[
2]) & CALL_LONG) ==
0))"
11542 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
11543 output_asm_insn ("crxor
6,
6,
6", operands);
11545 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
11546 output_asm_insn ("creqv
6,
6,
6", operands);
11548 return rs6000_call_template (operands,
0);
11550 [(set_attr "type" "branch,branch")
11551 (set_attr "length" "
4,
8")])
11553 (define_insn "*call_nonlocal_sysv_secure<mode>"
11554 [(call (mem:SI (match_operand:P
0 "symbol_ref_operand" "s,s"))
11556 (use (match_operand:SI
2 "immediate_operand" "O,n"))
11557 (use (match_operand:SI
3 "register_operand" "r,r"))
11558 (clobber (reg:P LR_REGNO))]
11559 "(DEFAULT_ABI == ABI_V4
11560 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[
0])
11561 && (INTVAL (operands[
2]) & CALL_LONG) ==
0)"
11563 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
11564 output_asm_insn ("crxor
6,
6,
6", operands);
11566 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
11567 output_asm_insn ("creqv
6,
6,
6", operands);
11569 return rs6000_call_template (operands,
0);
11571 [(set_attr "type" "branch,branch")
11572 (set_attr "length" "
4,
8")])
11574 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11575 [(set (match_operand
0 "" "")
11576 (call (mem:SI (match_operand:P
1 "indirect_call_operand" "c,*l,X"))
11577 (match_operand:P
2 "unspec_tls" "")))
11578 (use (match_operand:SI
3 "immediate_operand" "n,n,n"))
11579 (clobber (reg:P LR_REGNO))]
11580 "DEFAULT_ABI == ABI_V4
11581 || DEFAULT_ABI == ABI_DARWIN"
11583 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
11584 output_asm_insn ("crxor
6,
6,
6", operands);
11586 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
11587 output_asm_insn ("creqv
6,
6,
6", operands);
11589 return rs6000_indirect_call_template (operands,
1);
11591 [(set_attr "type" "jmpreg")
11592 (set (attr "length")
11594 (if_then_else (match_test "IS_V4_FP_ARGS (operands[
3])")
11597 (if_then_else (and (match_test "!rs6000_speculate_indirect_jumps")
11598 (match_test "which_alternative !=
1"))
11602 (define_insn "*call_value_nonlocal_sysv<mode>"
11603 [(set (match_operand
0 "" "")
11604 (call (mem:SI (match_operand:P
1 "symbol_ref_operand" "s"))
11605 (match_operand:P
2 "unspec_tls" "")))
11606 (use (match_operand:SI
3 "immediate_operand" "n"))
11607 (clobber (reg:P LR_REGNO))]
11608 "(DEFAULT_ABI == ABI_DARWIN
11609 || (DEFAULT_ABI == ABI_V4
11610 && (INTVAL (operands[
3]) & CALL_LONG) ==
0))"
11612 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
11613 output_asm_insn ("crxor
6,
6,
6", operands);
11615 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
11616 output_asm_insn ("creqv
6,
6,
6", operands);
11618 return rs6000_call_template (operands,
1);
11620 [(set_attr "type" "branch")
11621 (set (attr "length")
11622 (if_then_else (match_test "IS_V4_FP_ARGS (operands[
3])")
11626 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11627 [(set (match_operand
0 "" "")
11628 (call (mem:SI (match_operand:P
1 "symbol_ref_operand" "s"))
11629 (match_operand:P
2 "unspec_tls" "")))
11630 (use (match_operand:SI
3 "immediate_operand" "n"))
11631 (use (match_operand:SI
4 "register_operand" "r"))
11632 (clobber (reg:P LR_REGNO))]
11633 "(DEFAULT_ABI == ABI_V4
11634 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[
1])
11635 && (INTVAL (operands[
3]) & CALL_LONG) ==
0)"
11637 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
11638 output_asm_insn ("crxor
6,
6,
6", operands);
11640 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
11641 output_asm_insn ("creqv
6,
6,
6", operands);
11643 return rs6000_call_template (operands,
1);
11645 [(set_attr "type" "branch")
11646 (set (attr "length")
11647 (if_then_else (match_test "IS_V4_FP_ARGS (operands[
3])")
11651 ;; Call to AIX abi function which may be in another module.
11652 ;; Restore the TOC pointer (r2) after the call.
11654 (define_insn "*call_nonlocal_aix<mode>"
11655 [(call (mem:SI (match_operand:P
0 "symbol_ref_operand" "s"))
11657 (use (match_operand:SI
2 "immediate_operand" "n"))
11658 (clobber (reg:P LR_REGNO))]
11659 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11660 && (INTVAL (operands[
2]) & CALL_LONG) ==
0"
11662 return rs6000_call_template (operands,
0);
11664 [(set_attr "type" "branch")
11665 (set (attr "length")
11666 (if_then_else (match_test "rs6000_pcrel_p ()")
11670 (define_insn "*call_value_nonlocal_aix<mode>"
11671 [(set (match_operand
0 "" "")
11672 (call (mem:SI (match_operand:P
1 "symbol_ref_operand" "s"))
11673 (match_operand:P
2 "unspec_tls" "")))
11674 (use (match_operand:SI
3 "immediate_operand" "n"))
11675 (clobber (reg:P LR_REGNO))]
11676 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11677 && (INTVAL (operands[
3]) & CALL_LONG) ==
0"
11679 return rs6000_call_template (operands,
1);
11681 [(set_attr "type" "branch")
11682 (set (attr "length")
11683 (if_then_else (match_test "rs6000_pcrel_p ()")
11687 ;; Call to indirect functions with the AIX abi using a
3 word descriptor.
11688 ;; Operand0 is the addresss of the function to call
11689 ;; Operand3 is the location in the function descriptor to load r2 from
11690 ;; Operand4 is the offset of the stack location holding the current TOC pointer
11692 (define_insn "*call_indirect_aix<mode>"
11693 [(call (mem:SI (match_operand:P
0 "indirect_call_operand" "c,*l,X"))
11695 (use (match_operand:SI
2 "immediate_operand" "n,n,n"))
11696 (use (match_operand:P
3 "memory_operand" "<ptrm>,<ptrm>,<ptrm>"))
11697 (set (reg:P TOC_REGNUM) (unspec:P [(match_operand:P
4 "const_int_operand" "n,n,n")] UNSPEC_TOCSLOT))
11698 (clobber (reg:P LR_REGNO))]
11699 "DEFAULT_ABI == ABI_AIX"
11701 return rs6000_indirect_call_template (operands,
0);
11703 [(set_attr "type" "jmpreg")
11704 (set (attr "length")
11705 (if_then_else (and (match_test "!rs6000_speculate_indirect_jumps")
11706 (match_test "which_alternative !=
1"))
11707 (const_string "
16")
11708 (const_string "
12")))])
11710 (define_insn "*call_value_indirect_aix<mode>"
11711 [(set (match_operand
0 "" "")
11712 (call (mem:SI (match_operand:P
1 "indirect_call_operand" "c,*l,X"))
11713 (match_operand:P
2 "unspec_tls" "")))
11714 (use (match_operand:SI
3 "immediate_operand" "n,n,n"))
11715 (use (match_operand:P
4 "memory_operand" "<ptrm>,<ptrm>,<ptrm>"))
11716 (set (reg:P TOC_REGNUM)
11717 (unspec:P [(match_operand:P
5 "const_int_operand" "n,n,n")]
11719 (clobber (reg:P LR_REGNO))]
11720 "DEFAULT_ABI == ABI_AIX"
11722 return rs6000_indirect_call_template (operands,
1);
11724 [(set_attr "type" "jmpreg")
11725 (set (attr "length")
11726 (if_then_else (and (match_test "!rs6000_speculate_indirect_jumps")
11727 (match_test "which_alternative !=
1"))
11728 (const_string "
16")
11729 (const_string "
12")))])
11731 ;; Call to indirect functions with the ELFv2 ABI.
11732 ;; Operand0 is the addresss of the function to call
11733 ;; Operand3 is the offset of the stack location holding the current TOC pointer
11735 (define_insn "*call_indirect_elfv2<mode>"
11736 [(call (mem:SI (match_operand:P
0 "indirect_call_operand" "c,*l,X"))
11738 (use (match_operand:SI
2 "immediate_operand" "n,n,n"))
11739 (set (reg:P TOC_REGNUM) (unspec:P [(match_operand:P
3 "const_int_operand" "n,n,n")] UNSPEC_TOCSLOT))
11740 (clobber (reg:P LR_REGNO))]
11741 "DEFAULT_ABI == ABI_ELFv2"
11743 return rs6000_indirect_call_template (operands,
0);
11745 [(set_attr "type" "jmpreg")
11746 (set (attr "length")
11747 (if_then_else (and (match_test "!rs6000_speculate_indirect_jumps")
11748 (match_test "which_alternative !=
1"))
11749 (const_string "
12")
11750 (const_string "
8")))])
11752 (define_insn "*call_indirect_pcrel<mode>"
11753 [(call (mem:SI (match_operand:P
0 "indirect_call_operand" "c,*l,X"))
11755 (use (match_operand:SI
2 "immediate_operand" "n,n,n"))
11756 (clobber (reg:P LR_REGNO))]
11757 "rs6000_pcrel_p ()"
11759 return rs6000_indirect_call_template (operands,
0);
11761 [(set_attr "type" "jmpreg")
11762 (set (attr "length")
11763 (if_then_else (and (match_test "!rs6000_speculate_indirect_jumps")
11764 (match_test "which_alternative !=
1"))
11766 (const_string "
4")))])
11768 (define_insn "*call_value_indirect_elfv2<mode>"
11769 [(set (match_operand
0 "" "")
11770 (call (mem:SI (match_operand:P
1 "indirect_call_operand" "c,*l,X"))
11771 (match_operand:P
2 "unspec_tls" "")))
11772 (use (match_operand:SI
3 "immediate_operand" "n,n,n"))
11773 (set (reg:P TOC_REGNUM)
11774 (unspec:P [(match_operand:P
4 "const_int_operand" "n,n,n")]
11776 (clobber (reg:P LR_REGNO))]
11777 "DEFAULT_ABI == ABI_ELFv2"
11779 return rs6000_indirect_call_template (operands,
1);
11781 [(set_attr "type" "jmpreg")
11782 (set (attr "length")
11783 (if_then_else (and (match_test "!rs6000_speculate_indirect_jumps")
11784 (match_test "which_alternative !=
1"))
11785 (const_string "
12")
11786 (const_string "
8")))])
11788 (define_insn "*call_value_indirect_pcrel<mode>"
11789 [(set (match_operand
0 "" "")
11790 (call (mem:SI (match_operand:P
1 "indirect_call_operand" "c,*l,X"))
11791 (match_operand:P
2 "unspec_tls" "")))
11792 (use (match_operand:SI
3 "immediate_operand" "n,n,n"))
11793 (clobber (reg:P LR_REGNO))]
11794 "rs6000_pcrel_p ()"
11796 return rs6000_indirect_call_template (operands,
1);
11798 [(set_attr "type" "jmpreg")
11799 (set (attr "length")
11800 (if_then_else (and (match_test "!rs6000_speculate_indirect_jumps")
11801 (match_test "which_alternative !=
1"))
11803 (const_string "
4")))])
11805 ;; Call subroutine returning any type.
11806 (define_expand "untyped_call"
11807 [(parallel [(call (match_operand
0 "")
11809 (match_operand
1 "")
11810 (match_operand
2 "")])]
11815 emit_call_insn (gen_call (operands[
0], const0_rtx, const0_rtx));
11817 for (int i =
0; i < XVECLEN (operands[
2],
0); i++)
11818 emit_clobber (SET_SRC (XVECEXP (operands[
2],
0, i)));
11819 emit_insn (gen_blockage ());
11821 for (i =
0; i < XVECLEN (operands[
2],
0); i++)
11823 rtx set = XVECEXP (operands[
2],
0, i);
11824 emit_move_insn (SET_DEST (set), SET_SRC (set));
11827 /* The optimizer does not know that the call sets the function value
11828 registers we stored in the result block. We avoid problems by
11829 claiming that all hard registers are used and clobbered at this
11831 emit_insn (gen_blockage ());
11836 ;; sibling call patterns
11837 (define_expand "sibcall"
11838 [(parallel [(call (mem:SI (match_operand
0 "address_operand"))
11839 (match_operand
1 ""))
11840 (use (match_operand
2 ""))
11845 if (MACHOPIC_INDIRECT)
11846 operands[
0] = machopic_indirect_call_target (operands[
0]);
11849 gcc_assert (MEM_P (operands[
0]));
11850 gcc_assert (CONST_INT_P (operands[
1]));
11852 operands[
0] = XEXP (operands[
0],
0);
11854 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11855 rs6000_sibcall_aix (NULL_RTX, operands[
0], operands[
1], operands[
2]);
11856 else if (DEFAULT_ABI == ABI_V4)
11857 rs6000_sibcall_sysv (NULL_RTX, operands[
0], operands[
1], operands[
2]);
11858 else if (DEFAULT_ABI == ABI_DARWIN)
11859 rs6000_sibcall_darwin (NULL_RTX, operands[
0], operands[
1], operands[
2]);
11861 gcc_unreachable ();
11866 (define_expand "sibcall_value"
11867 [(parallel [(set (match_operand
0 "register_operand")
11868 (call (mem:SI (match_operand
1 "address_operand"))
11869 (match_operand
2 "")))
11870 (use (match_operand
3 ""))
11875 if (MACHOPIC_INDIRECT)
11876 operands[
1] = machopic_indirect_call_target (operands[
1]);
11879 gcc_assert (MEM_P (operands[
1]));
11880 gcc_assert (CONST_INT_P (operands[
2]));
11882 operands[
1] = XEXP (operands[
1],
0);
11884 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11885 rs6000_sibcall_aix (operands[
0], operands[
1], operands[
2], operands[
3]);
11886 else if (DEFAULT_ABI == ABI_V4)
11887 rs6000_sibcall_sysv (operands[
0], operands[
1], operands[
2], operands[
3]);
11888 else if (DEFAULT_ABI == ABI_DARWIN)
11889 rs6000_sibcall_darwin (operands[
0], operands[
1], operands[
2], operands[
3]);
11891 gcc_unreachable ();
11896 (define_insn "*sibcall_local<mode>"
11897 [(call (mem:SI (match_operand:P
0 "current_file_function_operand" "s,s"))
11899 (use (match_operand:SI
2 "immediate_operand" "O,n"))
11901 "(INTVAL (operands[
2]) & CALL_LONG) ==
0"
11903 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
11904 output_asm_insn ("crxor
6,
6,
6", operands);
11906 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
11907 output_asm_insn ("creqv
6,
6,
6", operands);
11909 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0";
11911 [(set_attr "type" "branch")
11912 (set_attr "length" "
4,
8")])
11914 (define_insn "*sibcall_value_local<mode>"
11915 [(set (match_operand
0 "" "")
11916 (call (mem:SI (match_operand:P
1 "current_file_function_operand" "s,s"))
11917 (match_operand
2)))
11918 (use (match_operand:SI
3 "immediate_operand" "O,n"))
11920 "(INTVAL (operands[
3]) & CALL_LONG) ==
0"
11922 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
11923 output_asm_insn ("crxor
6,
6,
6", operands);
11925 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
11926 output_asm_insn ("creqv
6,
6,
6", operands);
11928 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1";
11930 [(set_attr "type" "branch")
11931 (set_attr "length" "
4,
8")])
11933 (define_insn "*sibcall_indirect_nonlocal_sysv<mode>"
11934 [(call (mem:SI (match_operand:P
0 "indirect_call_operand" "c,*l,X"))
11936 (use (match_operand:SI
2 "immediate_operand" "n,n,n"))
11938 "DEFAULT_ABI == ABI_V4
11939 || DEFAULT_ABI == ABI_DARWIN"
11941 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
11942 output_asm_insn ("crxor
6,
6,
6", operands);
11944 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
11945 output_asm_insn ("creqv
6,
6,
6", operands);
11947 return rs6000_indirect_sibcall_template (operands,
0);
11949 [(set_attr "type" "jmpreg")
11950 (set (attr "length")
11951 (cond [(and (and (match_test "!rs6000_speculate_indirect_jumps")
11952 (match_test "which_alternative !=
1"))
11953 (match_test "(INTVAL (operands[
2]) & (CALL_V4_SET_FP_ARGS | CALL_V4_CLEAR_FP_ARGS))"))
11954 (const_string "
12")
11955 (ior (and (match_test "!rs6000_speculate_indirect_jumps")
11956 (match_test "which_alternative !=
1"))
11957 (match_test "(INTVAL (operands[
2]) & (CALL_V4_SET_FP_ARGS | CALL_V4_CLEAR_FP_ARGS))"))
11958 (const_string "
8")]
11959 (const_string "
4")))])
11961 (define_insn "*sibcall_nonlocal_sysv<mode>"
11962 [(call (mem:SI (match_operand:P
0 "symbol_ref_operand" "s,s"))
11964 (use (match_operand
2 "immediate_operand" "O,n"))
11966 "(DEFAULT_ABI == ABI_DARWIN
11967 || DEFAULT_ABI == ABI_V4)
11968 && (INTVAL (operands[
2]) & CALL_LONG) ==
0"
11970 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
11971 output_asm_insn ("crxor
6,
6,
6", operands);
11973 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
11974 output_asm_insn ("creqv
6,
6,
6", operands);
11976 return rs6000_sibcall_template (operands,
0);
11978 [(set_attr "type" "branch")
11979 (set_attr "length" "
4,
8")])
11981 (define_insn "*sibcall_value_indirect_nonlocal_sysv<mode>"
11982 [(set (match_operand
0 "" "")
11983 (call (mem:SI (match_operand:P
1 "indirect_call_operand" "c,*l,X"))
11984 (match_operand
2)))
11985 (use (match_operand:SI
3 "immediate_operand" "n,n,n"))
11987 "DEFAULT_ABI == ABI_V4
11988 || DEFAULT_ABI == ABI_DARWIN"
11990 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
11991 output_asm_insn ("crxor
6,
6,
6", operands);
11993 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
11994 output_asm_insn ("creqv
6,
6,
6", operands);
11996 return rs6000_indirect_sibcall_template (operands,
1);
11998 [(set_attr "type" "jmpreg")
11999 (set (attr "length")
12000 (cond [(and (and (match_test "!rs6000_speculate_indirect_jumps")
12001 (match_test "which_alternative !=
1"))
12002 (match_test "(INTVAL (operands[
3]) & (CALL_V4_SET_FP_ARGS | CALL_V4_CLEAR_FP_ARGS))"))
12003 (const_string "
12")
12004 (ior (and (match_test "!rs6000_speculate_indirect_jumps")
12005 (match_test "which_alternative !=
1"))
12006 (match_test "(INTVAL (operands[
3]) & (CALL_V4_SET_FP_ARGS | CALL_V4_CLEAR_FP_ARGS))"))
12007 (const_string "
8")]
12008 (const_string "
4")))])
12010 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12011 [(set (match_operand
0 "" "")
12012 (call (mem:SI (match_operand:P
1 "symbol_ref_operand" "s,s"))
12013 (match_operand
2)))
12014 (use (match_operand:SI
3 "immediate_operand" "O,n"))
12016 "(DEFAULT_ABI == ABI_DARWIN
12017 || DEFAULT_ABI == ABI_V4)
12018 && (INTVAL (operands[
3]) & CALL_LONG) ==
0"
12020 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
12021 output_asm_insn ("crxor
6,
6,
6", operands);
12023 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
12024 output_asm_insn ("creqv
6,
6,
6", operands);
12026 return rs6000_sibcall_template (operands,
1);
12028 [(set_attr "type" "branch")
12029 (set_attr "length" "
4,
8")])
12031 ;; AIX ABI sibling call patterns.
12033 (define_insn "*sibcall_aix<mode>"
12034 [(call (mem:SI (match_operand:P
0 "call_operand" "s,c"))
12037 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12039 if (which_alternative ==
0)
12040 return rs6000_sibcall_template (operands,
0);
12044 [(set_attr "type" "branch")])
12046 (define_insn "*sibcall_value_aix<mode>"
12047 [(set (match_operand
0 "" "")
12048 (call (mem:SI (match_operand:P
1 "call_operand" "s,c"))
12049 (match_operand
2)))
12051 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12053 if (which_alternative ==
0)
12054 return rs6000_sibcall_template (operands,
1);
12058 [(set_attr "type" "branch")])
12060 (define_expand "sibcall_epilogue"
12061 [(use (const_int
0))]
12064 if (!TARGET_SCHED_PROLOG)
12065 emit_insn (gen_blockage ());
12066 rs6000_emit_epilogue (EPILOGUE_TYPE_SIBCALL);
12070 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12071 ;; all of memory. This blocks insns from being moved across this point.
12073 (define_insn "blockage"
12074 [(unspec_volatile [(const_int
0)] UNSPECV_BLOCK)]
12077 [(set_attr "length" "
0")])
12079 (define_expand "probe_stack_address"
12080 [(use (match_operand
0 "address_operand"))]
12083 operands[
0] = gen_rtx_MEM (Pmode, operands[
0]);
12084 MEM_VOLATILE_P (operands[
0]) =
1;
12087 emit_insn (gen_probe_stack_di (operands[
0]));
12089 emit_insn (gen_probe_stack_si (operands[
0]));
12093 (define_insn "probe_stack_<mode>"
12094 [(set (match_operand:P
0 "memory_operand" "=m")
12095 (unspec:P [(const_int
0)] UNSPEC_PROBE_STACK))]
12098 operands[
1] = gen_rtx_REG (Pmode,
0);
12099 return "st<wd>%U0%X0 %
1,%
0";
12101 [(set_attr "type" "store")
12102 (set (attr "update")
12103 (if_then_else (match_operand
0 "update_address_mem")
12104 (const_string "yes")
12105 (const_string "no")))
12106 (set (attr "indexed")
12107 (if_then_else (match_operand
0 "indexed_address_mem")
12108 (const_string "yes")
12109 (const_string "no")))])
12111 (define_insn "probe_stack_range<P:mode>"
12112 [(set (match_operand:P
0 "register_operand" "=&r")
12113 (unspec_volatile:P [(match_operand:P
1 "register_operand" "
0")
12114 (match_operand:P
2 "register_operand" "r")
12115 (match_operand:P
3 "register_operand" "r")]
12116 UNSPECV_PROBE_STACK_RANGE))]
12118 "* return output_probe_stack_range (operands[
0], operands[
2], operands[
3]);"
12119 [(set_attr "type" "three")])
12121 ;; Compare insns are next. Note that the RS/
6000 has two types of compares,
12122 ;; signed & unsigned, and one type of branch.
12124 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12125 ;; insns, and branches.
12127 (define_expand "cbranch<mode>
4"
12128 [(use (match_operator
0 "comparison_operator"
12129 [(match_operand:GPR
1 "gpc_reg_operand")
12130 (match_operand:GPR
2 "reg_or_short_operand")]))
12131 (use (match_operand
3))]
12134 /* Take care of the possibility that operands[
2] might be negative but
12135 this might be a logical operation. That insn doesn't exist. */
12136 if (CONST_INT_P (operands[
2])
12137 && INTVAL (operands[
2]) <
0)
12139 operands[
2] = force_reg (<MODE>mode, operands[
2]);
12140 operands[
0] = gen_rtx_fmt_ee (GET_CODE (operands[
0]),
12141 GET_MODE (operands[
0]),
12142 operands[
1], operands[
2]);
12145 rs6000_emit_cbranch (<MODE>mode, operands);
12149 (define_expand "cbranch<mode>
4"
12150 [(use (match_operator
0 "comparison_operator"
12151 [(match_operand:FP
1 "gpc_reg_operand")
12152 (match_operand:FP
2 "gpc_reg_operand")]))
12153 (use (match_operand
3))]
12156 rs6000_emit_cbranch (<MODE>mode, operands);
12160 (define_expand "cbranchcc4"
12162 (if_then_else (match_operator
0 "branch_comparison_operator"
12163 [(match_operand
1 "cc_reg_operand")
12164 (match_operand
2 "zero_constant")])
12165 (label_ref (match_operand
3))
12170 (define_expand "cstore<mode>
4_signed"
12171 [(use (match_operator
1 "signed_comparison_operator"
12172 [(match_operand:P
2 "gpc_reg_operand")
12173 (match_operand:P
3 "gpc_reg_operand")]))
12174 (clobber (match_operand:P
0 "gpc_reg_operand"))]
12177 enum rtx_code cond_code = GET_CODE (operands[
1]);
12179 rtx op0 = operands[
0];
12180 rtx op1 = operands[
2];
12181 rtx op2 = operands[
3];
12183 if (cond_code == GE || cond_code == LT)
12185 cond_code = swap_condition (cond_code);
12186 std::swap (op1, op2);
12189 rtx tmp1 = gen_reg_rtx (<MODE>mode);
12190 rtx tmp2 = gen_reg_rtx (<MODE>mode);
12191 rtx tmp3 = gen_reg_rtx (<MODE>mode);
12193 int sh = GET_MODE_BITSIZE (<MODE>mode) -
1;
12194 emit_insn (gen_lshr<mode>
3 (tmp1, op1, GEN_INT (sh)));
12195 emit_insn (gen_ashr<mode>
3 (tmp2, op2, GEN_INT (sh)));
12197 emit_insn (gen_subf<mode>
3_carry (tmp3, op1, op2));
12199 if (cond_code == LE)
12200 emit_insn (gen_add<mode>
3_carry_in (op0, tmp1, tmp2));
12203 rtx tmp4 = gen_reg_rtx (<MODE>mode);
12204 emit_insn (gen_add<mode>
3_carry_in (tmp4, tmp1, tmp2));
12205 emit_insn (gen_xor<mode>
3 (op0, tmp4, const1_rtx));
12211 (define_expand "cstore<mode>
4_unsigned"
12212 [(use (match_operator
1 "unsigned_comparison_operator"
12213 [(match_operand:P
2 "gpc_reg_operand")
12214 (match_operand:P
3 "reg_or_short_operand")]))
12215 (clobber (match_operand:P
0 "gpc_reg_operand"))]
12218 enum rtx_code cond_code = GET_CODE (operands[
1]);
12220 rtx op0 = operands[
0];
12221 rtx op1 = operands[
2];
12222 rtx op2 = operands[
3];
12224 if (cond_code == GEU || cond_code == LTU)
12226 cond_code = swap_condition (cond_code);
12227 std::swap (op1, op2);
12230 if (!gpc_reg_operand (op1, <MODE>mode))
12231 op1 = force_reg (<MODE>mode, op1);
12232 if (!reg_or_short_operand (op2, <MODE>mode))
12233 op2 = force_reg (<MODE>mode, op2);
12235 rtx tmp = gen_reg_rtx (<MODE>mode);
12236 rtx tmp2 = gen_reg_rtx (<MODE>mode);
12238 emit_insn (gen_subf<mode>
3_carry (tmp, op1, op2));
12239 emit_insn (gen_subf<mode>
3_carry_in_xx (tmp2));
12241 if (cond_code == LEU)
12242 emit_insn (gen_add<mode>
3 (op0, tmp2, const1_rtx));
12244 emit_insn (gen_neg<mode>
2 (op0, tmp2));
12249 (define_expand "cstore_si_as_di"
12250 [(use (match_operator
1 "unsigned_comparison_operator"
12251 [(match_operand:SI
2 "gpc_reg_operand")
12252 (match_operand:SI
3 "reg_or_short_operand")]))
12253 (clobber (match_operand:SI
0 "gpc_reg_operand"))]
12256 int uns_flag = unsigned_comparison_operator (operands[
1], VOIDmode) ?
1 :
0;
12257 enum rtx_code cond_code = signed_condition (GET_CODE (operands[
1]));
12259 operands[
2] = force_reg (SImode, operands[
2]);
12260 operands[
3] = force_reg (SImode, operands[
3]);
12261 rtx op1 = gen_reg_rtx (DImode);
12262 rtx op2 = gen_reg_rtx (DImode);
12263 convert_move (op1, operands[
2], uns_flag);
12264 convert_move (op2, operands[
3], uns_flag);
12266 if (cond_code == GT || cond_code == LE)
12268 cond_code = swap_condition (cond_code);
12269 std::swap (op1, op2);
12272 rtx tmp = gen_reg_rtx (DImode);
12273 rtx tmp2 = gen_reg_rtx (DImode);
12274 emit_insn (gen_subdi3 (tmp, op1, op2));
12275 emit_insn (gen_lshrdi3 (tmp2, tmp, GEN_INT (
63)));
12281 gcc_unreachable ();
12286 tmp3 = gen_reg_rtx (DImode);
12287 emit_insn (gen_xordi3 (tmp3, tmp2, const1_rtx));
12291 convert_move (operands[
0], tmp3,
1);
12296 (define_expand "cstore<mode>
4_signed_imm"
12297 [(use (match_operator
1 "signed_comparison_operator"
12298 [(match_operand:GPR
2 "gpc_reg_operand")
12299 (match_operand:GPR
3 "immediate_operand")]))
12300 (clobber (match_operand:GPR
0 "gpc_reg_operand"))]
12303 bool invert = false;
12305 enum rtx_code cond_code = GET_CODE (operands[
1]);
12307 rtx op0 = operands[
0];
12308 rtx op1 = operands[
2];
12309 HOST_WIDE_INT val = INTVAL (operands[
3]);
12311 if (cond_code == GE || cond_code == GT)
12313 cond_code = reverse_condition (cond_code);
12317 if (cond_code == LE)
12320 rtx tmp = gen_reg_rtx (<MODE>mode);
12321 emit_insn (gen_add<mode>
3 (tmp, op1, GEN_INT (-val)));
12322 rtx x = gen_reg_rtx (<MODE>mode);
12324 emit_insn (gen_and<mode>
3 (x, op1, tmp));
12326 emit_insn (gen_ior<mode>
3 (x, op1, tmp));
12330 rtx tmp = gen_reg_rtx (<MODE>mode);
12331 emit_insn (gen_one_cmpl<mode>
2 (tmp, x));
12335 int sh = GET_MODE_BITSIZE (<MODE>mode) -
1;
12336 emit_insn (gen_lshr<mode>
3 (op0, x, GEN_INT (sh)));
12341 (define_expand "cstore<mode>
4_unsigned_imm"
12342 [(use (match_operator
1 "unsigned_comparison_operator"
12343 [(match_operand:GPR
2 "gpc_reg_operand")
12344 (match_operand:GPR
3 "immediate_operand")]))
12345 (clobber (match_operand:GPR
0 "gpc_reg_operand"))]
12348 bool invert = false;
12350 enum rtx_code cond_code = GET_CODE (operands[
1]);
12352 rtx op0 = operands[
0];
12353 rtx op1 = operands[
2];
12354 HOST_WIDE_INT val = INTVAL (operands[
3]);
12356 if (cond_code == GEU || cond_code == GTU)
12358 cond_code = reverse_condition (cond_code);
12362 if (cond_code == LEU)
12365 rtx tmp = gen_reg_rtx (<MODE>mode);
12366 rtx tmp2 = gen_reg_rtx (<MODE>mode);
12367 emit_insn (gen_add<mode>
3 (tmp, op1, GEN_INT (-val)));
12368 emit_insn (gen_one_cmpl<mode>
2 (tmp2, op1));
12369 rtx x = gen_reg_rtx (<MODE>mode);
12371 emit_insn (gen_ior<mode>
3 (x, tmp, tmp2));
12373 emit_insn (gen_and<mode>
3 (x, tmp, tmp2));
12377 rtx tmp = gen_reg_rtx (<MODE>mode);
12378 emit_insn (gen_one_cmpl<mode>
2 (tmp, x));
12382 int sh = GET_MODE_BITSIZE (<MODE>mode) -
1;
12383 emit_insn (gen_lshr<mode>
3 (op0, x, GEN_INT (sh)));
12388 (define_expand "cstore<mode>
4"
12389 [(use (match_operator
1 "comparison_operator"
12390 [(match_operand:GPR
2 "gpc_reg_operand")
12391 (match_operand:GPR
3 "reg_or_short_operand")]))
12392 (clobber (match_operand:GPR
0 "gpc_reg_operand"))]
12395 /* Everything is best done with setbc[r] if available. */
12396 if (TARGET_POWER10 && TARGET_ISEL)
12398 rs6000_emit_int_cmove (operands[
0], operands[
1], const1_rtx, const0_rtx);
12402 /* Expanding EQ and NE directly to some machine instructions does not help
12403 but does hurt combine. So don't. */
12404 if (GET_CODE (operands[
1]) == EQ)
12405 emit_insn (gen_eq<mode>
3 (operands[
0], operands[
2], operands[
3]));
12406 else if (<MODE>mode == Pmode
12407 && GET_CODE (operands[
1]) == NE)
12408 emit_insn (gen_ne<mode>
3 (operands[
0], operands[
2], operands[
3]));
12409 else if (GET_CODE (operands[
1]) == NE)
12411 rtx tmp = gen_reg_rtx (<MODE>mode);
12412 emit_insn (gen_eq<mode>
3 (tmp, operands[
2], operands[
3]));
12413 emit_insn (gen_xor<mode>
3 (operands[
0], tmp, const1_rtx));
12416 /* If ISEL is fast, expand to it. */
12417 else if (TARGET_ISEL)
12418 rs6000_emit_int_cmove (operands[
0], operands[
1], const1_rtx, const0_rtx);
12420 /* Expanding the unsigned comparisons helps a lot: all the neg_ltu
12421 etc. combinations magically work out just right. */
12422 else if (<MODE>mode == Pmode
12423 && unsigned_comparison_operator (operands[
1], VOIDmode))
12424 emit_insn (gen_cstore<mode>
4_unsigned (operands[
0], operands[
1],
12425 operands[
2], operands[
3]));
12427 /* For comparisons smaller than Pmode we can cheaply do things in Pmode. */
12428 else if (<MODE>mode == SImode && Pmode == DImode)
12429 emit_insn (gen_cstore_si_as_di (operands[
0], operands[
1],
12430 operands[
2], operands[
3]));
12432 /* For signed comparisons against a constant, we can do some simple
12434 else if (signed_comparison_operator (operands[
1], VOIDmode)
12435 && CONST_INT_P (operands[
3]))
12436 emit_insn (gen_cstore<mode>
4_signed_imm (operands[
0], operands[
1],
12437 operands[
2], operands[
3]));
12439 /* And similarly for unsigned comparisons. */
12440 else if (unsigned_comparison_operator (operands[
1], VOIDmode)
12441 && CONST_INT_P (operands[
3]))
12442 emit_insn (gen_cstore<mode>
4_unsigned_imm (operands[
0], operands[
1],
12443 operands[
2], operands[
3]));
12445 /* We also do not want to use mfcr for signed comparisons. */
12446 else if (<MODE>mode == Pmode
12447 && signed_comparison_operator (operands[
1], VOIDmode))
12448 emit_insn (gen_cstore<mode>
4_signed (operands[
0], operands[
1],
12449 operands[
2], operands[
3]));
12451 /* Everything else, use the mfcr brute force. */
12453 rs6000_emit_sCOND (<MODE>mode, operands);
12458 (define_expand "cstore<mode>
4"
12459 [(use (match_operator
1 "comparison_operator"
12460 [(match_operand:FP
2 "gpc_reg_operand")
12461 (match_operand:FP
3 "gpc_reg_operand")]))
12462 (clobber (match_operand:SI
0 "gpc_reg_operand"))]
12465 rs6000_emit_sCOND (<MODE>mode, operands);
12470 (define_expand "stack_protect_set"
12471 [(match_operand
0 "memory_operand")
12472 (match_operand
1 "memory_operand")]
12475 if (rs6000_stack_protector_guard == SSP_TLS)
12477 rtx reg = gen_rtx_REG (Pmode, rs6000_stack_protector_guard_reg);
12478 rtx offset = GEN_INT (rs6000_stack_protector_guard_offset);
12479 rtx addr = gen_rtx_PLUS (Pmode, reg, offset);
12480 operands[
1] = gen_rtx_MEM (Pmode, addr);
12484 emit_insn (gen_stack_protect_setdi (operands[
0], operands[
1]));
12486 emit_insn (gen_stack_protect_setsi (operands[
0], operands[
1]));
12491 ;; We can't use the prefixed attribute here because there are two memory
12492 ;; instructions. We can't split the insn due to the fact that this operation
12493 ;; needs to be done in one piece.
12494 (define_insn "stack_protect_set<mode>"
12495 [(set (match_operand:P
0 "memory_operand" "=YZ")
12496 (unspec:P [(match_operand:P
1 "memory_operand" "YZ")] UNSPEC_SP_SET))
12497 (set (match_scratch:P
2 "=&r") (const_int
0))]
12500 if (prefixed_memory (operands[
1], <MODE>mode))
12501 /* Prefixed load only supports D-form but no update and X-form. */
12502 output_asm_insn ("p<ptrload> %
2,%
1", operands);
12504 output_asm_insn ("<ptrload>%U1%X1 %
2,%
1", operands);
12506 if (prefixed_memory (operands[
0], <MODE>mode))
12507 /* Prefixed store only supports D-form but no update and X-form. */
12508 output_asm_insn ("pst<wd> %
2,%
0", operands);
12510 output_asm_insn ("st<wd>%U0%X0 %
2,%
0", operands);
12514 [(set_attr "type" "three")
12516 ;; Back to back prefixed memory instructions take
20 bytes (
8 bytes for each
12517 ;; prefixed instruction +
4 bytes for the possible NOP). Add in
4 bytes for
12518 ;; the LI
0 at the end.
12519 (set_attr "prefixed" "no")
12520 (set_attr "num_insns" "
3")
12521 (set (attr "length")
12522 (cond [(and (match_operand
0 "prefixed_memory")
12523 (match_operand
1 "prefixed_memory"))
12526 (ior (match_operand
0 "prefixed_memory")
12527 (match_operand
1 "prefixed_memory"))
12532 (define_expand "stack_protect_test"
12533 [(match_operand
0 "memory_operand")
12534 (match_operand
1 "memory_operand")
12535 (match_operand
2 "")]
12538 rtx guard = operands[
1];
12540 if (rs6000_stack_protector_guard == SSP_TLS)
12542 rtx reg = gen_rtx_REG (Pmode, rs6000_stack_protector_guard_reg);
12543 rtx offset = GEN_INT (rs6000_stack_protector_guard_offset);
12544 rtx addr = gen_rtx_PLUS (Pmode, reg, offset);
12545 guard = gen_rtx_MEM (Pmode, addr);
12548 operands[
1] = gen_rtx_UNSPEC (Pmode, gen_rtvec (
1, guard), UNSPEC_SP_TEST);
12549 rtx test = gen_rtx_EQ (VOIDmode, operands[
0], operands[
1]);
12550 rtx jump = gen_cbranchsi4 (test, operands[
0], operands[
1], operands[
2]);
12551 emit_jump_insn (jump);
12556 ;; We can't use the prefixed attribute here because there are two memory
12557 ;; instructions. We can't split the insn due to the fact that this operation
12558 ;; needs to be done in one piece.
12559 (define_insn "stack_protect_test<mode>"
12560 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=x,?y")
12561 (unspec:CCEQ [(match_operand:P
1 "memory_operand" "YZ,YZ")
12562 (match_operand:P
2 "memory_operand" "YZ,YZ")]
12564 (set (match_scratch:P
4 "=r,r") (const_int
0))
12565 (clobber (match_scratch:P
3 "=&r,&r"))]
12568 if (prefixed_memory (operands[
1], <MODE>mode))
12569 /* Prefixed load only supports D-form but no update and X-form. */
12570 output_asm_insn ("p<ptrload> %
3,%
1", operands);
12572 output_asm_insn ("<ptrload>%U1%X1 %
3,%
1", operands);
12574 if (prefixed_memory (operands[
2], <MODE>mode))
12575 output_asm_insn ("p<ptrload> %
4,%
2", operands);
12577 output_asm_insn ("<ptrload>%U2%X2 %
4,%
2", operands);
12579 if (which_alternative ==
0)
12580 output_asm_insn ("xor. %
3,%
3,%
4", operands);
12582 output_asm_insn ("cmpl<wd> %
0,%
3,%
4\;li %
3,
0", operands);
12586 ;; Back to back prefixed memory instructions take
20 bytes (
8 bytes for each
12587 ;; prefixed instruction +
4 bytes for the possible NOP). Add in either
4 or
12588 ;;
8 bytes to do the test.
12589 [(set_attr "prefixed" "no")
12590 (set_attr "num_insns" "
4,
5")
12591 (set (attr "length")
12592 (cond [(and (match_operand
1 "prefixed_memory")
12593 (match_operand
2 "prefixed_memory"))
12594 (if_then_else (eq_attr "alternative" "
0")
12598 (ior (match_operand
1 "prefixed_memory")
12599 (match_operand
2 "prefixed_memory"))
12600 (if_then_else (eq_attr "alternative" "
0")
12604 (if_then_else (eq_attr "alternative" "
0")
12606 (const_int
20))))])
12609 ;; Here are the actual compare insns.
12610 (define_insn "*cmp<mode>_signed"
12611 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
12612 (compare:CC (match_operand:GPR
1 "gpc_reg_operand" "r")
12613 (match_operand:GPR
2 "reg_or_short_operand" "rI")))]
12615 "cmp<wd>%I2 %
0,%
1,%
2"
12616 [(set_attr "type" "cmp")])
12618 (define_insn "*cmp<mode>_unsigned"
12619 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
12620 (compare:CCUNS (match_operand:GPR
1 "gpc_reg_operand" "r")
12621 (match_operand:GPR
2 "reg_or_u_short_operand" "rK")))]
12623 "cmpl<wd>%I2 %
0,%
1,%
2"
12624 [(set_attr "type" "cmp")])
12626 ;; If we are comparing a register for equality with a large constant,
12627 ;; we can do this with an XOR followed by a compare. But this is profitable
12628 ;; only if the large constant is only used for the comparison (and in this
12629 ;; case we already have a register to reuse as scratch).
12631 ;; For
64-bit registers, we could only do so if the constant's bit
15 is clear:
12632 ;; otherwise we'd need to XOR with FFFFFFFF????
0000 which is not available.
12635 [(set (match_operand:SI
0 "register_operand")
12636 (match_operand:SI
1 "logical_const_operand"))
12637 (set (match_dup
0) (match_operator:SI
3 "boolean_or_operator"
12639 (match_operand:SI
2 "logical_const_operand")]))
12640 (set (match_operand:CC
4 "cc_reg_operand")
12641 (compare:CC (match_operand:SI
5 "gpc_reg_operand")
12644 (if_then_else (match_operator
6 "equality_operator"
12645 [(match_dup
4) (const_int
0)])
12646 (match_operand
7 "")
12647 (match_operand
8 "")))]
12648 "peep2_reg_dead_p (
3, operands[
0])
12649 && peep2_reg_dead_p (
4, operands[
4])
12650 && REGNO (operands[
0]) != REGNO (operands[
5])"
12651 [(set (match_dup
0) (xor:SI (match_dup
5) (match_dup
9)))
12652 (set (match_dup
4) (compare:CC (match_dup
0) (match_dup
10)))
12653 (set (pc) (if_then_else (match_dup
6) (match_dup
7) (match_dup
8)))]
12656 /* Get the constant we are comparing against, and see what it looks like
12657 when sign-extended from
16 to
32 bits. Then see what constant we could
12658 XOR with SEXTC to get the sign-extended value. */
12659 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[
3]),
12661 operands[
1], operands[
2]);
12662 HOST_WIDE_INT c = INTVAL (cnst);
12663 HOST_WIDE_INT sextc = sext_hwi (c,
16);
12664 HOST_WIDE_INT xorv = c ^ sextc;
12666 operands[
9] = GEN_INT (xorv);
12667 operands[
10] = GEN_INT (sextc);
12670 ;; Only need to compare second words if first words equal
12671 (define_insn "*cmp<mode>_internal1"
12672 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
12673 (compare:CCFP (match_operand:IBM128
1 "gpc_reg_operand" "d")
12674 (match_operand:IBM128
2 "gpc_reg_operand" "d")))]
12675 "!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
12676 && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
12677 "fcmpu %
0,%
1,%
2\;bne %
0,$+
8\;fcmpu %
0,%L1,%L2"
12678 [(set_attr "type" "fpcompare")
12679 (set_attr "length" "
12")])
12681 (define_insn_and_split "*cmp<IBM128:mode>_internal2"
12682 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
12683 (compare:CCFP (match_operand:IBM128
1 "gpc_reg_operand" "d")
12684 (match_operand:IBM128
2 "gpc_reg_operand" "d")))
12685 (clobber (match_scratch:DF
3 "=d"))
12686 (clobber (match_scratch:DF
4 "=d"))
12687 (clobber (match_scratch:DF
5 "=d"))
12688 (clobber (match_scratch:DF
6 "=d"))
12689 (clobber (match_scratch:DF
7 "=d"))
12690 (clobber (match_scratch:DF
8 "=d"))
12691 (clobber (match_scratch:DF
9 "=d"))
12692 (clobber (match_scratch:DF
10 "=d"))
12693 (clobber (match_scratch:GPR
11 "=b"))]
12694 "TARGET_XL_COMPAT && FLOAT128_IBM_P (<IBM128:MODE>mode)
12695 && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
12697 "&& reload_completed"
12698 [(set (match_dup
3) (match_dup
14))
12699 (set (match_dup
4) (match_dup
15))
12700 (set (match_dup
9) (abs:DF (match_dup
5)))
12701 (set (match_dup
0) (compare:CCFP (match_dup
9) (match_dup
3)))
12702 (set (pc) (if_then_else (ne (match_dup
0) (const_int
0))
12703 (label_ref (match_dup
12))
12705 (set (match_dup
0) (compare:CCFP (match_dup
5) (match_dup
7)))
12706 (set (pc) (label_ref (match_dup
13)))
12708 (set (match_dup
10) (minus:DF (match_dup
5) (match_dup
7)))
12709 (set (match_dup
9) (minus:DF (match_dup
6) (match_dup
8)))
12710 (set (match_dup
9) (plus:DF (match_dup
10) (match_dup
9)))
12711 (set (match_dup
0) (compare:CCFP (match_dup
9) (match_dup
4)))
12714 REAL_VALUE_TYPE rv;
12715 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) :
0;
12716 const int hi_word = LONG_DOUBLE_LARGE_FIRST ?
0 : GET_MODE_SIZE (DFmode);
12718 operands[
5] = simplify_gen_subreg (DFmode, operands[
1],
12719 <IBM128:MODE>mode, hi_word);
12720 operands[
6] = simplify_gen_subreg (DFmode, operands[
1],
12721 <IBM128:MODE>mode, lo_word);
12722 operands[
7] = simplify_gen_subreg (DFmode, operands[
2],
12723 <IBM128:MODE>mode, hi_word);
12724 operands[
8] = simplify_gen_subreg (DFmode, operands[
2],
12725 <IBM128:MODE>mode, lo_word);
12726 operands[
12] = gen_label_rtx ();
12727 operands[
13] = gen_label_rtx ();
12729 operands[
14] = force_const_mem (DFmode,
12730 const_double_from_real_value (rv, DFmode));
12731 operands[
15] = force_const_mem (DFmode,
12732 const_double_from_real_value (dconst0,
12737 tocref = create_TOC_reference (XEXP (operands[
14],
0), operands[
11]);
12738 operands[
14] = gen_const_mem (DFmode, tocref);
12739 tocref = create_TOC_reference (XEXP (operands[
15],
0), operands[
11]);
12740 operands[
15] = gen_const_mem (DFmode, tocref);
12741 set_mem_alias_set (operands[
14], get_TOC_alias_set ());
12742 set_mem_alias_set (operands[
15], get_TOC_alias_set ());
12746 ;; Now we have the scc insns. We can do some combinations because of the
12747 ;; way the machine works.
12749 ;; Note that this is probably faster if we can put an insn between the
12750 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12751 ;; cases the insns below which don't use an intermediate CR field will
12752 ;; be used instead.
12753 (define_insn "set<mode>_cc"
12754 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
12755 (match_operator:GPR
1 "scc_comparison_operator"
12756 [(match_operand
2 "cc_reg_operand" "y")
12759 "mfcr %
0%Q2\;rlwinm %
0,%
0,%J1,
1"
12760 [(set (attr "type")
12761 (cond [(match_test "TARGET_MFCRF")
12762 (const_string "mfcrf")
12764 (const_string "mfcr")))
12765 (set_attr "length" "
8")])
12768 (define_code_iterator cmp [eq ne lt ltu gt gtu le leu ge geu])
12769 (define_code_attr UNS [(eq "CC")
12771 (lt "CC") (ltu "CCUNS")
12772 (gt "CC") (gtu "CCUNS")
12773 (le "CC") (leu "CCUNS")
12774 (ge "CC") (geu "CCUNS")])
12775 (define_code_attr UNSu_ [(eq "")
12780 (ge "") (geu "u_")])
12781 (define_code_attr UNSIK [(eq "I")
12786 (ge "I") (geu "K")])
12788 (define_insn_and_split "<code><GPR:mode><GPR2:mode>
2_isel"
12789 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
12790 (cmp:GPR (match_operand:GPR2
1 "gpc_reg_operand" "r")
12791 (match_operand:GPR2
2 "reg_or_<cmp:UNSu_>short_operand" "r<cmp:UNSIK>")))
12792 (clobber (match_scratch:GPR
3 "=r"))
12793 (clobber (match_scratch:GPR
4 "=r"))
12794 (clobber (match_scratch:<UNS>
5 "=y"))]
12795 "!TARGET_POWER10 && TARGET_ISEL
12796 && !(<CODE> == EQ && operands[
2] == const0_rtx)
12797 && !(<CODE> == NE && operands[
2] == const0_rtx
12798 && <GPR:MODE>mode == Pmode && <GPR2:MODE>mode == Pmode)"
12803 rtx_code code = <CODE>;
12804 if (CONST_INT_P (operands[
2]) && code != EQ && code != NE)
12806 HOST_WIDE_INT val = INTVAL (operands[
2]);
12807 if (code == LT && val != -
0x8000)
12812 if (code == GT && val !=
0x7fff)
12817 if (code == LTU && val !=
0)
12822 if (code == GTU && val !=
0xffff)
12827 operands[
2] = GEN_INT (val);
12830 if (code == NE || code == LE || code == GE || code == LEU || code == GEU)
12831 operands[
3] = const0_rtx;
12834 if (GET_CODE (operands[
3]) == SCRATCH)
12835 operands[
3] = gen_reg_rtx (<GPR:MODE>mode);
12836 emit_move_insn (operands[
3], const0_rtx);
12839 if (GET_CODE (operands[
4]) == SCRATCH)
12840 operands[
4] = gen_reg_rtx (<GPR:MODE>mode);
12841 emit_move_insn (operands[
4], const1_rtx);
12843 if (GET_CODE (operands[
5]) == SCRATCH)
12844 operands[
5] = gen_reg_rtx (<UNS>mode);
12846 rtx c1 = gen_rtx_COMPARE (<UNS>mode, operands[
1], operands[
2]);
12847 emit_insn (gen_rtx_SET (operands[
5], c1));
12849 rtx c2 = gen_rtx_fmt_ee (code, <GPR:MODE>mode, operands[
5], const0_rtx);
12850 rtx x = gen_rtx_IF_THEN_ELSE (<GPR:MODE>mode, c2, operands[
4], operands[
3]);
12851 emit_move_insn (operands[
0], x);
12855 [(set (attr "cost")
12856 (if_then_else (match_test "(CONST_INT_P (operands[
2]) && <CODE> != EQ)
12858 || <CODE> == LE || <CODE> == GE
12859 || <CODE> == LEU || <CODE> == GEU")
12861 (const_string "
10")))])
12863 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12866 (define_expand "eq<mode>
3"
12868 (set (match_operand:GPR
0 "gpc_reg_operand" "=r")
12869 (eq:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
12870 (match_operand:GPR
2 "scc_eq_operand" "<scc_eq_op2>")))
12871 (clobber (match_scratch:GPR
3 "=r"))
12872 (clobber (match_scratch:GPR
4 "=r"))])]
12875 if (TARGET_POWER10)
12877 rtx cc = gen_reg_rtx (CCmode);
12878 rtx compare = gen_rtx_COMPARE (CCmode, operands[
1], operands[
2]);
12879 emit_insn (gen_rtx_SET (cc, compare));
12880 rtx eq = gen_rtx_fmt_ee (EQ, <MODE>mode, cc, const0_rtx);
12881 emit_insn (gen_setbc_cc_<mode> (operands[
0], eq, cc));
12885 if (TARGET_ISEL && operands[
2] != const0_rtx)
12887 emit_insn (gen_eq<mode><mode>
2_isel (operands[
0], operands[
1],
12893 (define_insn_and_split "*eq<mode>
3"
12894 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
12895 (eq:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
12896 (match_operand:GPR
2 "scc_eq_operand" "<scc_eq_op2>")))
12897 (clobber (match_scratch:GPR
3 "=r"))
12898 (clobber (match_scratch:GPR
4 "=r"))]
12899 "!TARGET_POWER10 && !(TARGET_ISEL && operands[
2] != const0_rtx)"
12902 [(set (match_dup
4)
12903 (clz:GPR (match_dup
3)))
12905 (lshiftrt:GPR (match_dup
4)
12908 operands[
3] = rs6000_emit_eqne (<MODE>mode,
12909 operands[
1], operands[
2], operands[
3]);
12911 if (GET_CODE (operands[
4]) == SCRATCH)
12912 operands[
4] = gen_reg_rtx (<MODE>mode);
12914 operands[
5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12916 [(set (attr "length")
12917 (if_then_else (match_test "operands[
2] == const0_rtx")
12919 (const_string "
12")))])
12921 (define_expand "ne<mode>
3"
12923 (set (match_operand:GPR
0 "gpc_reg_operand" "=r")
12924 (ne:GPR (match_operand:GPR
1 "gpc_reg_operand" "r")
12925 (match_operand:GPR
2 "scc_eq_operand" "<scc_eq_op2>")))
12926 (clobber (match_scratch:GPR
3 "=r"))
12927 (clobber (match_scratch:GPR
4 "=r"))
12928 (clobber (reg:GPR CA_REGNO))])]
12931 if (TARGET_POWER10)
12933 rtx cc = gen_reg_rtx (CCmode);
12934 rtx compare = gen_rtx_COMPARE (CCmode, operands[
1], operands[
2]);
12935 emit_insn (gen_rtx_SET (cc, compare));
12936 rtx ne = gen_rtx_fmt_ee (NE, <MODE>mode, cc, const0_rtx);
12937 emit_insn (gen_setbc_cc_<mode> (operands[
0], ne, cc));
12941 if (<MODE>mode != Pmode)
12943 rtx x = gen_reg_rtx (<MODE>mode);
12944 emit_insn (gen_eq<mode>
3 (x, operands[
1], operands[
2]));
12945 emit_insn (gen_xor<mode>
3 (operands[
0], x, const1_rtx));
12949 if (TARGET_ISEL && operands[
2] != const0_rtx)
12951 emit_insn (gen_ne<mode><mode>
2_isel (operands[
0], operands[
1],
12957 (define_insn_and_split "*ne<mode>
3"
12958 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
12959 (ne:P (match_operand:P
1 "gpc_reg_operand" "r")
12960 (match_operand:P
2 "scc_eq_operand" "<scc_eq_op2>")))
12961 (clobber (match_scratch:P
3 "=r"))
12962 (clobber (match_scratch:P
4 "=r"))
12963 (clobber (reg:P CA_REGNO))]
12964 "!TARGET_POWER10 && !(TARGET_ISEL && operands[
2] != const0_rtx)"
12967 [(parallel [(set (match_dup
4)
12968 (plus:P (match_dup
3)
12970 (set (reg:P CA_REGNO)
12971 (ne:P (match_dup
3)
12973 (parallel [(set (match_dup
0)
12974 (plus:P (plus:P (not:P (match_dup
4))
12977 (clobber (reg:P CA_REGNO))])]
12979 operands[
3] = rs6000_emit_eqne (<MODE>mode,
12980 operands[
1], operands[
2], operands[
3]);
12982 if (GET_CODE (operands[
4]) == SCRATCH)
12983 operands[
4] = gen_reg_rtx (<MODE>mode);
12985 [(set (attr "length")
12986 (if_then_else (match_test "operands[
2] == const0_rtx")
12988 (const_string "
12")))])
12990 (define_insn_and_split "*neg_eq_<mode>"
12991 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
12992 (neg:P (eq:P (match_operand:P
1 "gpc_reg_operand" "r")
12993 (match_operand:P
2 "scc_eq_operand" "<scc_eq_op2>"))))
12994 (clobber (match_scratch:P
3 "=r"))
12995 (clobber (match_scratch:P
4 "=r"))
12996 (clobber (reg:P CA_REGNO))]
13000 [(parallel [(set (match_dup
4)
13001 (plus:P (match_dup
3)
13003 (set (reg:P CA_REGNO)
13004 (ne:P (match_dup
3)
13006 (parallel [(set (match_dup
0)
13007 (plus:P (reg:P CA_REGNO)
13009 (clobber (reg:P CA_REGNO))])]
13011 operands[
3] = rs6000_emit_eqne (<MODE>mode,
13012 operands[
1], operands[
2], operands[
3]);
13014 if (GET_CODE (operands[
4]) == SCRATCH)
13015 operands[
4] = gen_reg_rtx (<MODE>mode);
13017 [(set (attr "length")
13018 (if_then_else (match_test "operands[
2] == const0_rtx")
13020 (const_string "
12")))])
13022 (define_insn_and_split "*neg_ne_<mode>"
13023 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
13024 (neg:P (ne:P (match_operand:P
1 "gpc_reg_operand" "r")
13025 (match_operand:P
2 "scc_eq_operand" "<scc_eq_op2>"))))
13026 (clobber (match_scratch:P
3 "=r"))
13027 (clobber (match_scratch:P
4 "=r"))
13028 (clobber (reg:P CA_REGNO))]
13032 [(parallel [(set (match_dup
4)
13033 (neg:P (match_dup
3)))
13034 (set (reg:P CA_REGNO)
13035 (eq:P (match_dup
3)
13037 (parallel [(set (match_dup
0)
13038 (plus:P (reg:P CA_REGNO)
13040 (clobber (reg:P CA_REGNO))])]
13042 operands[
3] = rs6000_emit_eqne (<MODE>mode,
13043 operands[
1], operands[
2], operands[
3]);
13045 if (GET_CODE (operands[
4]) == SCRATCH)
13046 operands[
4] = gen_reg_rtx (<MODE>mode);
13048 [(set (attr "length")
13049 (if_then_else (match_test "operands[
2] == const0_rtx")
13051 (const_string "
12")))])
13053 (define_insn_and_split "*plus_eq_<mode>"
13054 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
13055 (plus:P (eq:P (match_operand:P
1 "gpc_reg_operand" "r")
13056 (match_operand:P
2 "scc_eq_operand" "<scc_eq_op2>"))
13057 (match_operand:P
3 "gpc_reg_operand" "r")))
13058 (clobber (match_scratch:P
4 "=r"))
13059 (clobber (match_scratch:P
5 "=r"))
13060 (clobber (reg:P CA_REGNO))]
13064 [(parallel [(set (match_dup
5)
13065 (neg:P (match_dup
4)))
13066 (set (reg:P CA_REGNO)
13067 (eq:P (match_dup
4)
13069 (parallel [(set (match_dup
0)
13070 (plus:P (match_dup
3)
13072 (clobber (reg:P CA_REGNO))])]
13074 operands[
4] = rs6000_emit_eqne (<MODE>mode,
13075 operands[
1], operands[
2], operands[
4]);
13077 if (GET_CODE (operands[
5]) == SCRATCH)
13078 operands[
5] = gen_reg_rtx (<MODE>mode);
13080 [(set (attr "length")
13081 (if_then_else (match_test "operands[
2] == const0_rtx")
13083 (const_string "
12")))])
13085 (define_insn_and_split "*plus_ne_<mode>"
13086 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
13087 (plus:P (ne:P (match_operand:P
1 "gpc_reg_operand" "r")
13088 (match_operand:P
2 "scc_eq_operand" "<scc_eq_op2>"))
13089 (match_operand:P
3 "gpc_reg_operand" "r")))
13090 (clobber (match_scratch:P
4 "=r"))
13091 (clobber (match_scratch:P
5 "=r"))
13092 (clobber (reg:P CA_REGNO))]
13096 [(parallel [(set (match_dup
5)
13097 (plus:P (match_dup
4)
13099 (set (reg:P CA_REGNO)
13100 (ne:P (match_dup
4)
13102 (parallel [(set (match_dup
0)
13103 (plus:P (match_dup
3)
13105 (clobber (reg:P CA_REGNO))])]
13107 operands[
4] = rs6000_emit_eqne (<MODE>mode,
13108 operands[
1], operands[
2], operands[
4]);
13110 if (GET_CODE (operands[
5]) == SCRATCH)
13111 operands[
5] = gen_reg_rtx (<MODE>mode);
13113 [(set (attr "length")
13114 (if_then_else (match_test "operands[
2] == const0_rtx")
13116 (const_string "
12")))])
13118 (define_insn_and_split "*minus_eq_<mode>"
13119 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
13120 (minus:P (match_operand:P
3 "gpc_reg_operand" "r")
13121 (eq:P (match_operand:P
1 "gpc_reg_operand" "r")
13122 (match_operand:P
2 "scc_eq_operand" "<scc_eq_op2>"))))
13123 (clobber (match_scratch:P
4 "=r"))
13124 (clobber (match_scratch:P
5 "=r"))
13125 (clobber (reg:P CA_REGNO))]
13129 [(parallel [(set (match_dup
5)
13130 (plus:P (match_dup
4)
13132 (set (reg:P CA_REGNO)
13133 (ne:P (match_dup
4)
13135 (parallel [(set (match_dup
0)
13136 (plus:P (plus:P (match_dup
3)
13139 (clobber (reg:P CA_REGNO))])]
13141 operands[
4] = rs6000_emit_eqne (<MODE>mode,
13142 operands[
1], operands[
2], operands[
4]);
13144 if (GET_CODE (operands[
5]) == SCRATCH)
13145 operands[
5] = gen_reg_rtx (<MODE>mode);
13147 [(set (attr "length")
13148 (if_then_else (match_test "operands[
2] == const0_rtx")
13150 (const_string "
12")))])
13152 (define_insn_and_split "*minus_ne_<mode>"
13153 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
13154 (minus:P (match_operand:P
3 "gpc_reg_operand" "r")
13155 (ne:P (match_operand:P
1 "gpc_reg_operand" "r")
13156 (match_operand:P
2 "scc_eq_operand" "<scc_eq_op2>"))))
13157 (clobber (match_scratch:P
4 "=r"))
13158 (clobber (match_scratch:P
5 "=r"))
13159 (clobber (reg:P CA_REGNO))]
13163 [(parallel [(set (match_dup
5)
13164 (neg:P (match_dup
4)))
13165 (set (reg:P CA_REGNO)
13166 (eq:P (match_dup
4)
13168 (parallel [(set (match_dup
0)
13169 (plus:P (plus:P (match_dup
3)
13172 (clobber (reg:P CA_REGNO))])]
13174 operands[
4] = rs6000_emit_eqne (<MODE>mode,
13175 operands[
1], operands[
2], operands[
4]);
13177 if (GET_CODE (operands[
5]) == SCRATCH)
13178 operands[
5] = gen_reg_rtx (<MODE>mode);
13180 [(set (attr "length")
13181 (if_then_else (match_test "operands[
2] == const0_rtx")
13183 (const_string "
12")))])
13185 (define_insn_and_split "*eqsi3_ext<mode>"
13186 [(set (match_operand:EXTSI
0 "gpc_reg_operand" "=r")
13187 (eq:EXTSI (match_operand:SI
1 "gpc_reg_operand" "r")
13188 (match_operand:SI
2 "scc_eq_operand" "rKLI")))
13189 (clobber (match_scratch:SI
3 "=r"))
13190 (clobber (match_scratch:SI
4 "=r"))]
13194 [(set (match_dup
4)
13195 (clz:SI (match_dup
3)))
13198 (lshiftrt:SI (match_dup
4)
13201 operands[
3] = rs6000_emit_eqne (SImode,
13202 operands[
1], operands[
2], operands[
3]);
13204 if (GET_CODE (operands[
4]) == SCRATCH)
13205 operands[
4] = gen_reg_rtx (SImode);
13207 [(set (attr "length")
13208 (if_then_else (match_test "operands[
2] == const0_rtx")
13210 (const_string "
12")))])
13212 (define_insn_and_split "*nesi3_ext<mode>"
13213 [(set (match_operand:EXTSI
0 "gpc_reg_operand" "=r")
13214 (ne:EXTSI (match_operand:SI
1 "gpc_reg_operand" "r")
13215 (match_operand:SI
2 "scc_eq_operand" "rKLI")))
13216 (clobber (match_scratch:SI
3 "=r"))
13217 (clobber (match_scratch:SI
4 "=r"))
13218 (clobber (match_scratch:EXTSI
5 "=r"))]
13222 [(set (match_dup
4)
13223 (clz:SI (match_dup
3)))
13226 (lshiftrt:SI (match_dup
4)
13229 (xor:EXTSI (match_dup
5)
13232 operands[
3] = rs6000_emit_eqne (SImode,
13233 operands[
1], operands[
2], operands[
3]);
13235 if (GET_CODE (operands[
4]) == SCRATCH)
13236 operands[
4] = gen_reg_rtx (SImode);
13237 if (GET_CODE (operands[
5]) == SCRATCH)
13238 operands[
5] = gen_reg_rtx (<MODE>mode);
13240 [(set (attr "length")
13241 (if_then_else (match_test "operands[
2] == const0_rtx")
13242 (const_string "
12")
13243 (const_string "
16")))])
13246 (define_code_iterator fp_rev [ordered ne unle unge])
13247 (define_code_iterator fp_two [ltgt le ge unlt ungt uneq])
13249 (define_insn_and_split "*<code><mode>_cc"
13250 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
13251 (fp_rev:GPR (match_operand:CCFP
1 "cc_reg_operand" "y")
13253 "!flag_finite_math_only"
13258 rtx_code revcode = reverse_condition_maybe_unordered (<CODE>);
13259 rtx eq = gen_rtx_fmt_ee (revcode, <MODE>mode, operands[
1], const0_rtx);
13260 rtx tmp = gen_reg_rtx (<MODE>mode);
13261 emit_move_insn (tmp, eq);
13262 emit_insn (gen_xor<mode>
3 (operands[
0], tmp, const1_rtx));
13265 [(set_attr "length" "
12")])
13267 (define_insn_and_split "*<code><mode>_cc"
13268 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
13269 (fp_two:GPR (match_operand:CCFP
1 "cc_reg_operand" "y")
13271 "!flag_finite_math_only"
13276 rtx cc = rs6000_emit_fp_cror (<CODE>, <MODE>mode, operands[
1]);
13278 emit_move_insn (operands[
0], gen_rtx_EQ (<MODE>mode, cc, const0_rtx));
13281 [(set_attr "length" "
12")])
13283 ;; Conditional branches.
13284 ;; These either are a single bc insn, or a bc around a b.
13286 (define_insn "*cbranch"
13288 (if_then_else (match_operator
1 "branch_comparison_operator"
13289 [(match_operand
2 "cc_reg_operand" "y")
13291 (label_ref (match_operand
0))
13295 return output_cbranch (operands[
1], "%l0",
0, insn);
13297 [(set_attr "type" "branch")
13298 (set (attr "length")
13299 (if_then_else (and (ge (minus (match_dup
0) (pc))
13300 (const_int -
32768))
13301 (lt (minus (match_dup
0) (pc))
13302 (const_int
32764)))
13306 (define_insn_and_split "*cbranch_2insn"
13308 (if_then_else (match_operator
1 "extra_insn_branch_comparison_operator"
13309 [(match_operand
2 "cc_reg_operand" "y")
13311 (label_ref (match_operand
0))
13313 "!flag_finite_math_only"
13318 rtx cc = rs6000_emit_fp_cror (GET_CODE (operands[
1]), SImode, operands[
2]);
13320 rtx note = find_reg_note (curr_insn, REG_BR_PROB,
0);
13322 rtx loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[
0]);
13323 rtx cond = gen_rtx_EQ (CCEQmode, cc, const0_rtx);
13324 rtx ite = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, loc_ref, pc_rtx);
13325 emit_jump_insn (gen_rtx_SET (pc_rtx, ite));
13329 profile_probability prob
13330 = profile_probability::from_reg_br_prob_note (XINT (note,
0));
13332 add_reg_br_prob_note (get_last_insn (), prob);
13337 [(set_attr "type" "branch")
13338 (set (attr "length")
13339 (if_then_else (and (ge (minus (match_dup
0) (pc))
13340 (const_int -
32764))
13341 (lt (minus (match_dup
0) (pc))
13342 (const_int
32760)))
13346 ;; Conditional return.
13347 (define_insn "*creturn"
13349 (if_then_else (match_operator
0 "branch_comparison_operator"
13350 [(match_operand
1 "cc_reg_operand" "y")
13356 return output_cbranch (operands[
0], NULL,
0, insn);
13358 [(set_attr "type" "jmpreg")])
13360 ;; Logic on condition register values.
13362 ; This pattern matches things like
13363 ; (set (reg:CCEQ
68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP
68) (const_int
0))
13364 ; (eq:SI (reg:CCFP
68) (const_int
0)))
13366 ; which are generated by the branch logic.
13367 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13369 (define_insn "@cceq_ior_compare_<mode>"
13370 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y,?y")
13371 (compare:CCEQ (match_operator:GPR
1 "boolean_operator"
13372 [(match_operator:GPR
2
13373 "branch_positive_comparison_operator"
13375 "cc_reg_operand" "y,y")
13377 (match_operator:GPR
4
13378 "branch_positive_comparison_operator"
13380 "cc_reg_operand" "
0,y")
13384 "cr%q1 %E0,%j2,%j4"
13385 [(set_attr "type" "cr_logical")
13386 (set_attr "cr_logical_3op" "no,yes")])
13388 ; Why is the constant -
1 here, but
1 in the previous pattern?
13389 ; Because ~
1 has all but the low bit set.
13390 (define_insn "cceq_ior_compare_complement"
13391 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y,?y")
13392 (compare:CCEQ (match_operator:SI
1 "boolean_operator"
13393 [(not:SI (match_operator:SI
2
13394 "branch_positive_comparison_operator"
13396 "cc_reg_operand" "y,y")
13398 (match_operator:SI
4
13399 "branch_positive_comparison_operator"
13401 "cc_reg_operand" "
0,y")
13405 "cr%q1 %E0,%j2,%j4"
13406 [(set_attr "type" "cr_logical")
13407 (set_attr "cr_logical_3op" "no,yes")])
13409 (define_insn "@cceq_rev_compare_<mode>"
13410 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y,?y")
13411 (compare:CCEQ (match_operator:GPR
1
13412 "branch_positive_comparison_operator"
13414 "cc_reg_operand" "
0,y")
13419 [(set_attr "type" "cr_logical")
13420 (set_attr "cr_logical_3op" "no,yes")])
13422 ;; If we are comparing the result of two comparisons, this can be done
13423 ;; using creqv or crxor.
13425 (define_insn_and_split ""
13426 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y")
13427 (compare:CCEQ (match_operator
1 "branch_comparison_operator"
13428 [(match_operand
2 "cc_reg_operand" "y")
13430 (match_operator
3 "branch_comparison_operator"
13431 [(match_operand
4 "cc_reg_operand" "y")
13436 [(set (match_dup
0) (compare:CCEQ (xor:SI (match_dup
1) (match_dup
3))
13439 int positive_1, positive_2;
13441 positive_1 = branch_positive_comparison_operator (operands[
1],
13442 GET_MODE (operands[
1]));
13443 positive_2 = branch_positive_comparison_operator (operands[
3],
13444 GET_MODE (operands[
3]));
13447 operands[
1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[
2]),
13448 GET_CODE (operands[
1])),
13450 operands[
2], const0_rtx);
13451 else if (GET_MODE (operands[
1]) != SImode)
13452 operands[
1] = gen_rtx_fmt_ee (GET_CODE (operands[
1]), SImode,
13453 operands[
2], const0_rtx);
13456 operands[
3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[
4]),
13457 GET_CODE (operands[
3])),
13459 operands[
4], const0_rtx);
13460 else if (GET_MODE (operands[
3]) != SImode)
13461 operands[
3] = gen_rtx_fmt_ee (GET_CODE (operands[
3]), SImode,
13462 operands[
4], const0_rtx);
13464 if (positive_1 == positive_2)
13466 operands[
1] = gen_rtx_NOT (SImode, operands[
1]);
13467 operands[
5] = constm1_rtx;
13471 operands[
5] = const1_rtx;
13475 ;; Unconditional branch and return.
13477 (define_insn "jump"
13479 (label_ref (match_operand
0)))]
13482 [(set_attr "type" "branch")])
13484 (define_insn "<return_str>return"
13488 [(set_attr "type" "jmpreg")])
13490 (define_expand "indirect_jump"
13491 [(set (pc) (match_operand
0 "register_operand"))]
13494 if (!rs6000_speculate_indirect_jumps) {
13495 rtx ccreg = gen_reg_rtx (CCmode);
13496 emit_jump_insn (gen_indirect_jump_nospec (Pmode, operands[
0], ccreg));
13501 (define_insn "*indirect_jump<mode>"
13503 (match_operand:P
0 "register_operand" "c,*l"))]
13504 "rs6000_speculate_indirect_jumps"
13506 [(set_attr "type" "jmpreg")])
13508 (define_insn "@indirect_jump<mode>_nospec"
13509 [(set (pc) (match_operand:P
0 "register_operand" "c,*l"))
13510 (clobber (match_operand:CC
1 "cc_reg_operand" "=y,y"))]
13511 "!rs6000_speculate_indirect_jumps"
13512 "crset %E1\;beq%T0- %
1\;b $"
13513 [(set_attr "type" "jmpreg")
13514 (set_attr "length" "
12")])
13516 ;; Table jump for switch statements:
13517 (define_expand "tablejump"
13518 [(use (match_operand
0))
13519 (use (label_ref (match_operand
1)))]
13522 if (rs6000_speculate_indirect_jumps)
13524 if (rs6000_relative_jumptables)
13525 emit_jump_insn (gen_tablejump_normal (Pmode, operands[
0], operands[
1]));
13527 emit_jump_insn (gen_tablejump_absolute (Pmode, operands[
0],
13532 rtx ccreg = gen_reg_rtx (CCmode);
13534 if (rs6000_relative_jumptables)
13535 jump = gen_tablejump_nospec (Pmode, operands[
0], operands[
1], ccreg);
13537 jump = gen_tablejump_absolute_nospec (Pmode, operands[
0], operands[
1],
13539 emit_jump_insn (jump);
13544 (define_expand "@tablejump<mode>_normal"
13545 [(use (match_operand:SI
0))
13546 (use (match_operand:P
1))]
13547 "rs6000_speculate_indirect_jumps && rs6000_relative_jumptables"
13549 rtx off = force_reg (SImode, operands[
0]);
13550 if (<MODE>mode != SImode)
13552 rtx src = gen_rtx_fmt_e (SIGN_EXTEND, Pmode, off);
13553 off = gen_reg_rtx (Pmode);
13554 emit_move_insn (off, src);
13557 rtx lab = force_reg (Pmode, gen_rtx_LABEL_REF (Pmode, operands[
1]));
13558 rtx addr = gen_reg_rtx (Pmode);
13560 emit_insn (gen_add<mode>
3 (addr, off, lab));
13561 emit_jump_insn (gen_tablejump_insn_normal (Pmode, addr, operands[
1]));
13565 (define_expand "@tablejump<mode>_absolute"
13566 [(use (match_operand:P
0))
13567 (use (match_operand:P
1))]
13568 "rs6000_speculate_indirect_jumps && !rs6000_relative_jumptables"
13570 rtx addr = gen_reg_rtx (Pmode);
13571 emit_move_insn (addr, operands[
0]);
13573 emit_jump_insn (gen_tablejump_insn_normal (Pmode, addr, operands[
1]));
13577 (define_expand "@tablejump<mode>_nospec"
13578 [(use (match_operand:SI
0))
13579 (use (match_operand:P
1))
13580 (use (match_operand:CC
2))]
13581 "!rs6000_speculate_indirect_jumps && rs6000_relative_jumptables"
13583 rtx off = force_reg (SImode, operands[
0]);
13584 if (<MODE>mode != SImode)
13586 rtx src = gen_rtx_fmt_e (SIGN_EXTEND, Pmode, off);
13587 off = gen_reg_rtx (Pmode);
13588 emit_move_insn (off, src);
13591 rtx lab = force_reg (Pmode, gen_rtx_LABEL_REF (Pmode, operands[
1]));
13592 rtx addr = gen_reg_rtx (Pmode);
13594 emit_insn (gen_add<mode>
3 (addr, off, lab));
13595 emit_jump_insn (gen_tablejump_insn_nospec (Pmode, addr, operands[
1],
13600 (define_expand "@tablejump<mode>_absolute_nospec"
13601 [(use (match_operand:P
0))
13602 (use (match_operand:P
1))
13603 (use (match_operand:CC
2))]
13604 "!rs6000_speculate_indirect_jumps && !rs6000_relative_jumptables"
13606 rtx addr = gen_reg_rtx (Pmode);
13607 emit_move_insn (addr, operands[
0]);
13609 emit_jump_insn (gen_tablejump_insn_nospec (Pmode, addr, operands[
1],
13614 (define_insn "@tablejump<mode>_insn_normal"
13616 (match_operand:P
0 "register_operand" "c,*l"))
13617 (use (label_ref (match_operand
1)))]
13618 "rs6000_speculate_indirect_jumps"
13620 [(set_attr "type" "jmpreg")])
13622 (define_insn "@tablejump<mode>_insn_nospec"
13624 (match_operand:P
0 "register_operand" "c,*l"))
13625 (use (label_ref (match_operand
1)))
13626 (clobber (match_operand:CC
2 "cc_reg_operand" "=y,y"))]
13627 "!rs6000_speculate_indirect_jumps"
13628 "crset %E2\;beq%T0- %
2\;b $"
13629 [(set_attr "type" "jmpreg")
13630 (set_attr "length" "
12")])
13633 [(unspec [(const_int
0)] UNSPEC_NOP)]
13637 (define_insn "group_ending_nop"
13638 [(unspec [(const_int
0)] UNSPEC_GRP_END_NOP)]
13641 operands[
0] = gen_rtx_REG (Pmode,
13642 rs6000_tune == PROCESSOR_POWER6 ?
1 :
2);
13643 return "ori %
0,%
0,
0";
13646 (define_insn "speculation_barrier"
13647 [(unspec_volatile:BLK [(const_int
0)] UNSPECV_SPEC_BARRIER)]
13650 operands[
0] = gen_rtx_REG (Pmode,
31);
13651 return "ori %
0,%
0,
0";
13654 ;; Define the subtract-one-and-jump insns, starting with the template
13655 ;; so loop.c knows what to generate.
13657 (define_expand "doloop_end"
13658 [(use (match_operand
0)) ; loop pseudo
13659 (use (match_operand
1))] ; label
13662 if (GET_MODE (operands[
0]) != Pmode)
13665 emit_jump_insn (gen_ctr (Pmode, operands[
0], operands[
1]));
13669 (define_expand "@ctr<mode>"
13670 [(parallel [(set (pc)
13671 (if_then_else (ne (match_operand:P
0 "register_operand")
13673 (label_ref (match_operand
1))
13676 (plus:P (match_dup
0)
13678 (clobber (match_scratch:CC
2))
13679 (clobber (match_scratch:P
3))])]
13683 ;; We need to be able to do this for any operand, including MEM, or we
13684 ;; will cause reload to blow up since we don't allow output reloads on
13686 ;; For the length attribute to be calculated correctly, the
13687 ;; label MUST be operand
0.
13688 ;; rs6000_legitimate_combined_insn prevents combine creating any of
13689 ;; the ctr<mode> insns.
13691 (define_code_attr bd [(eq "bdz") (ne "bdnz")])
13692 (define_code_attr bd_neg [(eq "bdnz") (ne "bdz")])
13694 (define_insn "<bd>_<mode>"
13696 (if_then_else (eqne (match_operand:P
1 "register_operand" "c,*b,*b,*b")
13698 (label_ref (match_operand
0))
13700 (set (match_operand:P
2 "nonimmediate_operand" "=
1,*r,m,*d*wa*c*l")
13701 (plus:P (match_dup
1)
13703 (clobber (match_scratch:CC
3 "=X,&x,&x,&x"))
13704 (clobber (match_scratch:P
4 "=X,X,&r,r"))]
13707 if (which_alternative !=
0)
13709 else if (get_attr_length (insn) ==
4)
13712 return "<bd_neg> $+
8\;b %l0";
13714 [(set_attr "type" "branch")
13715 (set_attr_alternative "length"
13716 [(if_then_else (and (ge (minus (match_dup
0) (pc))
13717 (const_int -
32768))
13718 (lt (minus (match_dup
0) (pc))
13719 (const_int
32764)))
13722 (const_string "
16")
13723 (const_string "
20")
13724 (const_string "
20")])])
13726 ;; Now the splitter if we could not allocate the CTR register
13729 (if_then_else (match_operator
2 "comparison_operator"
13730 [(match_operand:P
1 "gpc_reg_operand")
13733 (match_operand
6)))
13734 (set (match_operand:P
0 "nonimmediate_operand")
13735 (plus:P (match_dup
1)
13737 (clobber (match_scratch:CC
3))
13738 (clobber (match_scratch:P
4))]
13741 (if_then_else (match_dup
7)
13745 operands[
7] = gen_rtx_fmt_ee (GET_CODE (operands[
2]), VOIDmode, operands[
3],
13747 emit_insn (gen_rtx_SET (operands[
3],
13748 gen_rtx_COMPARE (CCmode, operands[
1], const1_rtx)));
13749 if (int_reg_operand (operands[
0], <MODE>mode))
13750 emit_insn (gen_add<mode>
3 (operands[
0], operands[
1], constm1_rtx));
13753 emit_insn (gen_add<mode>
3 (operands[
4], operands[
1], constm1_rtx));
13754 emit_move_insn (operands[
0], operands[
4]);
13756 /* No DONE so branch comes from the pattern. */
13759 ;; patterns for bdnzt/bdnzf/bdzt/bdzf
13760 ;; Note that in the case of long branches we have to decompose this into
13761 ;; bdnz+bc. This is because bdnzt has an implied AND between the ctr condition
13762 ;; and the CR bit, which means there is no way to conveniently invert the
13763 ;; comparison as is done with plain bdnz/bdz.
13765 (define_insn "<bd>tf_<mode>"
13769 (eqne (match_operand:P
1 "register_operand" "c,*b,*b,*b")
13771 (match_operator
3 "branch_comparison_operator"
13772 [(match_operand
4 "cc_reg_operand" "y,y,y,y")
13774 (label_ref (match_operand
0))
13776 (set (match_operand:P
2 "nonimmediate_operand" "=
1,*r,m,*d*wa*c*l")
13777 (plus:P (match_dup
1)
13779 (clobber (match_scratch:P
5 "=X,X,&r,r"))
13780 (clobber (match_scratch:CC
6 "=X,&y,&y,&y"))
13781 (clobber (match_scratch:CCEQ
7 "=X,&y,&y,&y"))]
13784 if (which_alternative !=
0)
13786 else if (get_attr_length (insn) ==
4)
13788 if (branch_positive_comparison_operator (operands[
3],
13789 GET_MODE (operands[
3])))
13790 return "<bd>t %j3,%l0";
13792 return "<bd>f %j3,%l0";
13796 static char seq[
96];
13797 char *bcs = output_cbranch (operands[
3], ".Lshort%=",
1, insn);
13798 sprintf(seq, "<bd_neg> .Lshort%%=\;%s\;b %%l0\;.Lshort%%=:", bcs);
13802 [(set_attr "type" "branch")
13803 (set_attr_alternative "length"
13804 [(if_then_else (and (ge (minus (match_dup
0) (pc))
13805 (const_int -
32768))
13806 (lt (minus (match_dup
0) (pc))
13807 (const_int
32764)))
13810 (const_string "
16")
13811 (const_string "
20")
13812 (const_string "
20")])])
13814 ;; Now the splitter if we could not allocate the CTR register
13819 (match_operator
1 "comparison_operator"
13820 [(match_operand:P
0 "gpc_reg_operand")
13822 (match_operator
3 "branch_comparison_operator"
13823 [(match_operand
2 "cc_reg_operand")
13826 (match_operand
5)))
13827 (set (match_operand:P
6 "nonimmediate_operand")
13828 (plus:P (match_dup
0)
13830 (clobber (match_scratch:P
7))
13831 (clobber (match_scratch:CC
8))
13832 (clobber (match_scratch:CCEQ
9))]
13836 rtx ctr = operands[
0];
13837 rtx ctrcmp = operands[
1];
13838 rtx ccin = operands[
2];
13839 rtx cccmp = operands[
3];
13840 rtx dst1 = operands[
4];
13841 rtx dst2 = operands[
5];
13842 rtx ctrout = operands[
6];
13843 rtx ctrtmp = operands[
7];
13844 enum rtx_code cmpcode = GET_CODE (ctrcmp);
13845 bool ispos = branch_positive_comparison_operator (ctrcmp, GET_MODE (ctrcmp));
13847 cmpcode = reverse_condition (cmpcode);
13848 /* Generate crand/crandc here. */
13849 emit_insn (gen_rtx_SET (operands[
8],
13850 gen_rtx_COMPARE (CCmode, ctr, const1_rtx)));
13851 rtx ctrcmpcc = gen_rtx_fmt_ee (cmpcode, SImode, operands[
8], const0_rtx);
13853 rtx andexpr = gen_rtx_AND (SImode, ctrcmpcc, cccmp);
13855 emit_insn (gen_cceq_ior_compare (SImode, operands[
9], andexpr, ctrcmpcc,
13856 operands[
8], cccmp, ccin));
13858 emit_insn (gen_cceq_ior_compare_complement (operands[
9], andexpr, ctrcmpcc,
13859 operands[
8], cccmp, ccin));
13860 if (int_reg_operand (ctrout, <MODE>mode))
13861 emit_insn (gen_add<mode>
3 (ctrout, ctr, constm1_rtx));
13864 emit_insn (gen_add<mode>
3 (ctrtmp, ctr, constm1_rtx));
13865 emit_move_insn (ctrout, ctrtmp);
13867 rtx cmp = gen_rtx_EQ (CCEQmode, operands[
9], const0_rtx);
13868 emit_jump_insn (gen_rtx_SET (pc_rtx,
13869 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp,
13875 (define_insn "trap"
13876 [(trap_if (const_int
1) (const_int
0))]
13879 [(set_attr "type" "trap")])
13881 (define_expand "ctrap<mode>
4"
13882 [(trap_if (match_operator
0 "ordered_comparison_operator"
13883 [(match_operand:GPR
1 "register_operand")
13884 (match_operand:GPR
2 "reg_or_short_operand")])
13885 (match_operand
3 "zero_constant" ""))]
13890 [(trap_if (match_operator
0 "ordered_comparison_operator"
13891 [(match_operand:GPR
1 "register_operand" "r")
13892 (match_operand:GPR
2 "reg_or_short_operand" "rI")])
13895 "t<wd>%V0%I2 %
1,%
2"
13896 [(set_attr "type" "trap")])
13898 ;; Insns related to generating the function prologue and epilogue.
13900 (define_expand "prologue"
13901 [(use (const_int
0))]
13904 rs6000_emit_prologue ();
13905 if (!TARGET_SCHED_PROLOG)
13906 emit_insn (gen_blockage ());
13910 (define_insn "*movesi_from_cr_one"
13911 [(match_parallel
0 "mfcr_operation"
13912 [(set (match_operand:SI
1 "gpc_reg_operand" "=r")
13913 (unspec:SI [(match_operand:CC
2 "cc_reg_operand" "y")
13914 (match_operand
3 "immediate_operand" "n")]
13915 UNSPEC_MOVESI_FROM_CR))])]
13920 for (i =
0; i < XVECLEN (operands[
0],
0); i++)
13922 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[
0],
0, i)),
0,
1));
13923 operands[
4] = GEN_INT (mask);
13924 output_asm_insn ("mfcr %
1,%
4", operands);
13928 [(set_attr "type" "mfcrf")])
13930 ;; Don't include the volatile CRs since their values are not used wrt CR save
13931 ;; in the prologue and doing so prevents shrink-wrapping because we can't move the
13932 ;; prologue past an insn (early exit test) that defines a register used in the
13934 (define_insn "prologue_movesi_from_cr"
13935 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
13936 (unspec:SI [(reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13937 (reg:CC CR4_REGNO)]
13938 UNSPEC_MOVESI_FROM_CR))]
13941 [(set_attr "type" "mfcr")])
13943 (define_insn "*crsave"
13944 [(match_parallel
0 "crsave_operation"
13945 [(set (match_operand:SI
1 "memory_operand" "=m")
13946 (match_operand:SI
2 "gpc_reg_operand" "r"))])]
13949 [(set_attr "type" "store")])
13951 (define_insn "*stmw"
13952 [(match_parallel
0 "stmw_operation"
13953 [(set (match_operand:SI
1 "memory_operand" "=m")
13954 (match_operand:SI
2 "gpc_reg_operand" "r"))])]
13957 [(set_attr "type" "store")
13958 (set_attr "update" "yes")
13959 (set_attr "indexed" "yes")])
13961 ; The following comment applies to:
13965 ; return_and_restore_gpregs*
13966 ; return_and_restore_fpregs*
13967 ; return_and_restore_fpregs_aix*
13969 ; The out-of-line save / restore functions expects one input argument.
13970 ; Since those are not standard call_insn's, we must avoid using
13971 ; MATCH_OPERAND for that argument. That way the register rename
13972 ; optimization will not try to rename this register.
13973 ; Each pattern is repeated for each possible register number used in
13974 ; various ABIs (r11, r1, and for some functions r12)
13976 (define_insn "*save_gpregs_<mode>_r11"
13977 [(match_parallel
0 "any_parallel_operand"
13978 [(clobber (reg:P LR_REGNO))
13979 (use (match_operand:P
1 "symbol_ref_operand" "s"))
13981 (set (match_operand:P
2 "memory_operand" "=m")
13982 (match_operand:P
3 "gpc_reg_operand" "r"))])]
13985 [(set_attr "type" "branch")])
13987 (define_insn "*save_gpregs_<mode>_r12"
13988 [(match_parallel
0 "any_parallel_operand"
13989 [(clobber (reg:P LR_REGNO))
13990 (use (match_operand:P
1 "symbol_ref_operand" "s"))
13992 (set (match_operand:P
2 "memory_operand" "=m")
13993 (match_operand:P
3 "gpc_reg_operand" "r"))])]
13996 [(set_attr "type" "branch")])
13998 (define_insn "*save_gpregs_<mode>_r1"
13999 [(match_parallel
0 "any_parallel_operand"
14000 [(clobber (reg:P LR_REGNO))
14001 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14003 (set (match_operand:P
2 "memory_operand" "=m")
14004 (match_operand:P
3 "gpc_reg_operand" "r"))])]
14007 [(set_attr "type" "branch")])
14009 (define_insn "*save_fpregs_<mode>_r11"
14010 [(match_parallel
0 "any_parallel_operand"
14011 [(clobber (reg:P LR_REGNO))
14012 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14014 (set (match_operand:DF
2 "memory_operand" "=m")
14015 (match_operand:DF
3 "gpc_reg_operand" "d"))])]
14018 [(set_attr "type" "branch")])
14020 (define_insn "*save_fpregs_<mode>_r12"
14021 [(match_parallel
0 "any_parallel_operand"
14022 [(clobber (reg:P LR_REGNO))
14023 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14025 (set (match_operand:DF
2 "memory_operand" "=m")
14026 (match_operand:DF
3 "gpc_reg_operand" "d"))])]
14029 [(set_attr "type" "branch")])
14031 (define_insn "*save_fpregs_<mode>_r1"
14032 [(match_parallel
0 "any_parallel_operand"
14033 [(clobber (reg:P LR_REGNO))
14034 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14036 (set (match_operand:DF
2 "memory_operand" "=m")
14037 (match_operand:DF
3 "gpc_reg_operand" "d"))])]
14040 [(set_attr "type" "branch")])
14042 ; This is to explain that changes to the stack pointer should
14043 ; not be moved over loads from or stores to stack memory.
14044 (define_insn "stack_tie"
14045 [(match_parallel
0 "tie_operand"
14046 [(set (mem:BLK (reg
1)) (const_int
0))])]
14049 [(set_attr "length" "
0")])
14051 ; Some
32-bit ABIs do not have a red zone, so the stack deallocation has to
14052 ; stay behind all restores from the stack, it cannot be reordered to before
14053 ; one. See PR77687. This insn is an add or mr, and a memory clobber.
14054 (define_insn "stack_restore_tie"
14055 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
14056 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
14057 (match_operand:SI
2 "reg_or_cint_operand" "O,rI")))
14058 (set (mem:BLK (scratch)) (const_int
0))]
14063 [(set_attr "type" "*,add")])
14065 (define_expand "epilogue"
14066 [(use (const_int
0))]
14069 if (!TARGET_SCHED_PROLOG)
14070 emit_insn (gen_blockage ());
14071 rs6000_emit_epilogue (EPILOGUE_TYPE_NORMAL);
14075 ; On some processors, doing the mtcrf one CC register at a time is
14076 ; faster (like on the
604e). On others, doing them all at once is
14077 ; faster; for instance, on the
601 and
750.
14079 (define_expand "movsi_to_cr_one"
14080 [(set (match_operand:CC
0 "cc_reg_operand")
14081 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand")
14082 (match_dup
2)] UNSPEC_MOVESI_TO_CR))]
14084 "operands[
2] = GEN_INT (
1 << (
7 - (REGNO (operands[
0]) - CR0_REGNO)));")
14086 (define_insn "*movsi_to_cr"
14087 [(match_parallel
0 "mtcrf_operation"
14088 [(set (match_operand:CC
1 "cc_reg_operand" "=y")
14089 (unspec:CC [(match_operand:SI
2 "gpc_reg_operand" "r")
14090 (match_operand
3 "immediate_operand" "n")]
14091 UNSPEC_MOVESI_TO_CR))])]
14096 for (i =
0; i < XVECLEN (operands[
0],
0); i++)
14097 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[
0],
0, i)),
0,
1));
14098 operands[
4] = GEN_INT (mask);
14099 return "mtcrf %
4,%
2";
14101 [(set_attr "type" "mtcr")])
14103 (define_insn "*mtcrfsi"
14104 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
14105 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
14106 (match_operand
2 "immediate_operand" "n")]
14107 UNSPEC_MOVESI_TO_CR))]
14108 "REG_P (operands[
0])
14109 && CR_REGNO_P (REGNO (operands[
0]))
14110 && CONST_INT_P (operands[
2])
14111 && INTVAL (operands[
2]) ==
1 << (
7 - (REGNO (operands[
0]) - CR0_REGNO))"
14113 [(set_attr "type" "mtcr")])
14115 ; The load-multiple instructions have similar properties.
14116 ; Note that "load_multiple" is a name known to the machine-independent
14117 ; code that actually corresponds to the PowerPC load-string.
14119 (define_insn "*lmw"
14120 [(match_parallel
0 "lmw_operation"
14121 [(set (match_operand:SI
1 "gpc_reg_operand" "=r")
14122 (match_operand:SI
2 "memory_operand" "m"))])]
14125 [(set_attr "type" "load")
14126 (set_attr "update" "yes")
14127 (set_attr "indexed" "yes")
14128 (set_attr "cell_micro" "always")])
14130 ; FIXME: "any_parallel_operand" is a bit flexible...
14132 ; The following comment applies to:
14136 ; return_and_restore_gpregs*
14137 ; return_and_restore_fpregs*
14138 ; return_and_restore_fpregs_aix*
14140 ; The out-of-line save / restore functions expects one input argument.
14141 ; Since those are not standard call_insn's, we must avoid using
14142 ; MATCH_OPERAND for that argument. That way the register rename
14143 ; optimization will not try to rename this register.
14144 ; Each pattern is repeated for each possible register number used in
14145 ; various ABIs (r11, r1, and for some functions r12)
14147 (define_insn "*restore_gpregs_<mode>_r11"
14148 [(match_parallel
0 "any_parallel_operand"
14149 [(clobber (reg:P LR_REGNO))
14150 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14152 (set (match_operand:P
2 "gpc_reg_operand" "=r")
14153 (match_operand:P
3 "memory_operand" "m"))])]
14156 [(set_attr "type" "branch")])
14158 (define_insn "*restore_gpregs_<mode>_r12"
14159 [(match_parallel
0 "any_parallel_operand"
14160 [(clobber (reg:P LR_REGNO))
14161 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14163 (set (match_operand:P
2 "gpc_reg_operand" "=r")
14164 (match_operand:P
3 "memory_operand" "m"))])]
14167 [(set_attr "type" "branch")])
14169 (define_insn "*restore_gpregs_<mode>_r1"
14170 [(match_parallel
0 "any_parallel_operand"
14171 [(clobber (reg:P LR_REGNO))
14172 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14174 (set (match_operand:P
2 "gpc_reg_operand" "=r")
14175 (match_operand:P
3 "memory_operand" "m"))])]
14178 [(set_attr "type" "branch")])
14180 (define_insn "*return_and_restore_gpregs_<mode>_r11"
14181 [(match_parallel
0 "any_parallel_operand"
14183 (clobber (reg:P LR_REGNO))
14184 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14186 (set (match_operand:P
2 "gpc_reg_operand" "=r")
14187 (match_operand:P
3 "memory_operand" "m"))])]
14190 [(set_attr "type" "branch")])
14192 (define_insn "*return_and_restore_gpregs_<mode>_r12"
14193 [(match_parallel
0 "any_parallel_operand"
14195 (clobber (reg:P LR_REGNO))
14196 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14198 (set (match_operand:P
2 "gpc_reg_operand" "=r")
14199 (match_operand:P
3 "memory_operand" "m"))])]
14202 [(set_attr "type" "branch")])
14204 (define_insn "*return_and_restore_gpregs_<mode>_r1"
14205 [(match_parallel
0 "any_parallel_operand"
14207 (clobber (reg:P LR_REGNO))
14208 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14210 (set (match_operand:P
2 "gpc_reg_operand" "=r")
14211 (match_operand:P
3 "memory_operand" "m"))])]
14214 [(set_attr "type" "branch")])
14216 (define_insn "*return_and_restore_fpregs_<mode>_r11"
14217 [(match_parallel
0 "any_parallel_operand"
14219 (clobber (reg:P LR_REGNO))
14220 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14222 (set (match_operand:DF
2 "gpc_reg_operand" "=d")
14223 (match_operand:DF
3 "memory_operand" "m"))])]
14226 [(set_attr "type" "branch")])
14228 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14229 [(match_parallel
0 "any_parallel_operand"
14231 (clobber (reg:P LR_REGNO))
14232 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14234 (set (match_operand:DF
2 "gpc_reg_operand" "=d")
14235 (match_operand:DF
3 "memory_operand" "m"))])]
14238 [(set_attr "type" "branch")])
14240 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14241 [(match_parallel
0 "any_parallel_operand"
14243 (clobber (reg:P LR_REGNO))
14244 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14246 (set (match_operand:DF
2 "gpc_reg_operand" "=d")
14247 (match_operand:DF
3 "memory_operand" "m"))])]
14250 [(set_attr "type" "branch")])
14252 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14253 [(match_parallel
0 "any_parallel_operand"
14255 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14257 (set (match_operand:DF
2 "gpc_reg_operand" "=d")
14258 (match_operand:DF
3 "memory_operand" "m"))])]
14261 [(set_attr "type" "branch")])
14263 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14264 [(match_parallel
0 "any_parallel_operand"
14266 (use (match_operand:P
1 "symbol_ref_operand" "s"))
14268 (set (match_operand:DF
2 "gpc_reg_operand" "=d")
14269 (match_operand:DF
3 "memory_operand" "m"))])]
14272 [(set_attr "type" "branch")])
14274 ; This is used in compiling the unwind routines.
14275 (define_expand "eh_return"
14276 [(use (match_operand
0 "general_operand"))]
14279 emit_insn (gen_eh_set_lr (Pmode, operands[
0]));
14283 ; We can't expand this before we know where the link register is stored.
14284 (define_insn_and_split "@eh_set_lr_<mode>"
14285 [(unspec_volatile [(match_operand:P
0 "register_operand" "r")] UNSPECV_EH_RR)
14286 (clobber (match_scratch:P
1 "=&b"))]
14292 rs6000_emit_eh_reg_restore (operands[
0], operands[
1]);
14296 (define_insn "prefetch"
14297 [(prefetch (match_operand
0 "indexed_or_indirect_address" "a")
14298 (match_operand:SI
1 "const_int_operand" "n")
14299 (match_operand:SI
2 "const_int_operand" "n"))]
14304 /* dcbtstt, dcbtt and TH=
0b10000 support starts with ISA
2.06 (Power7).
14305 AIX does not support the dcbtstt and dcbtt extended mnemonics.
14306 The AIX assembler does not support the three operand form of dcbt
14307 and dcbtst on Power
7 (-mpwr7). */
14308 int inst_select = INTVAL (operands[
2]) || !TARGET_DIRECT_MOVE;
14310 if (REG_P (operands[
0]))
14312 if (INTVAL (operands[
1]) ==
0)
14313 return inst_select ? "dcbt
0,%
0" : "dcbt
0,%
0,
16";
14315 return inst_select ? "dcbtst
0,%
0" : "dcbtst
0,%
0,
16";
14319 if (INTVAL (operands[
1]) ==
0)
14320 return inst_select ? "dcbt %a0" : "dcbt %a0,
16";
14322 return inst_select ? "dcbtst %a0" : "dcbtst %a0,
16";
14325 [(set_attr "type" "load")])
14327 ;; Handle -fsplit-stack.
14329 (define_expand "split_stack_prologue"
14333 rs6000_expand_split_stack_prologue ();
14337 (define_expand "load_split_stack_limit"
14338 [(set (match_operand
0)
14339 (unspec [(const_int
0)] UNSPEC_STACK_CHECK))]
14342 emit_insn (gen_rtx_SET (operands[
0],
14343 gen_rtx_UNSPEC (Pmode,
14344 gen_rtvec (
1, const0_rtx),
14345 UNSPEC_STACK_CHECK)));
14349 (define_insn "load_split_stack_limit_di"
14350 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
14351 (unspec:DI [(const_int
0)] UNSPEC_STACK_CHECK))]
14353 "ld %
0,-
0x7040(
13)"
14354 [(set_attr "type" "load")
14355 (set_attr "update" "no")
14356 (set_attr "indexed" "no")])
14358 (define_insn "load_split_stack_limit_si"
14359 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
14360 (unspec:SI [(const_int
0)] UNSPEC_STACK_CHECK))]
14362 "lwz %
0,-
0x7020(
2)"
14363 [(set_attr "type" "load")
14364 (set_attr "update" "no")
14365 (set_attr "indexed" "no")])
14367 ;; A return instruction which the middle-end doesn't see.
14368 ;; Use r0 to stop regrename twiddling with lr restore insns emitted
14369 ;; after the call to __morestack.
14370 (define_insn "split_stack_return"
14371 [(unspec_volatile [(reg:SI
0) (reg:SI LR_REGNO)] UNSPECV_SPLIT_STACK_RETURN)]
14374 [(set_attr "type" "jmpreg")])
14376 ;; If there are operand
0 bytes available on the stack, jump to
14378 (define_expand "split_stack_space_check"
14379 [(set (match_dup
2)
14380 (unspec [(const_int
0)] UNSPEC_STACK_CHECK))
14382 (minus (reg STACK_POINTER_REGNUM)
14383 (match_operand
0)))
14384 (set (match_dup
4) (compare:CCUNS (match_dup
3) (match_dup
2)))
14385 (set (pc) (if_then_else
14386 (geu (match_dup
4) (const_int
0))
14387 (label_ref (match_operand
1))
14391 rs6000_split_stack_space_check (operands[
0], operands[
1]);
14395 (define_insn "bpermd_<mode>"
14396 [(set (match_operand:P
0 "gpc_reg_operand" "=r")
14397 (unspec:P [(match_operand:P
1 "gpc_reg_operand" "r")
14398 (match_operand:P
2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14401 [(set_attr "type" "popcnt")])
14404 ;; Builtin fma support. Handle
14405 ;; Note that the conditions for expansion are in the FMA_F iterator.
14407 (define_expand "fma<mode>
4"
14408 [(set (match_operand:FMA_F
0 "gpc_reg_operand")
14410 (match_operand:FMA_F
1 "gpc_reg_operand")
14411 (match_operand:FMA_F
2 "gpc_reg_operand")
14412 (match_operand:FMA_F
3 "gpc_reg_operand")))]
14416 (define_insn "*fma<mode>
4_fpr"
14417 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa,wa")
14419 (match_operand:SFDF
1 "gpc_reg_operand" "%d,wa,wa")
14420 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa,
0")
14421 (match_operand:SFDF
3 "gpc_reg_operand" "d,
0,wa")))]
14422 "TARGET_HARD_FLOAT"
14424 fmadd<s> %
0,%
1,%
2,%
3
14425 xsmadda<sd>p %x0,%x1,%x2
14426 xsmaddm<sd>p %x0,%x1,%x3"
14427 [(set_attr "type" "fp")
14428 (set_attr "isa" "*,<Fisa>,<Fisa>")])
14430 ; Altivec only has fma and nfms.
14431 (define_expand "fms<mode>
4"
14432 [(set (match_operand:FMA_F
0 "gpc_reg_operand")
14434 (match_operand:FMA_F
1 "gpc_reg_operand")
14435 (match_operand:FMA_F
2 "gpc_reg_operand")
14436 (neg:FMA_F (match_operand:FMA_F
3 "gpc_reg_operand"))))]
14437 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14440 (define_insn "*fms<mode>
4_fpr"
14441 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa,wa")
14443 (match_operand:SFDF
1 "gpc_reg_operand" "d,wa,wa")
14444 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa,
0")
14445 (neg:SFDF (match_operand:SFDF
3 "gpc_reg_operand" "d,
0,wa"))))]
14446 "TARGET_HARD_FLOAT"
14448 fmsub<s> %
0,%
1,%
2,%
3
14449 xsmsuba<sd>p %x0,%x1,%x2
14450 xsmsubm<sd>p %x0,%x1,%x3"
14451 [(set_attr "type" "fp")
14452 (set_attr "isa" "*,<Fisa>,<Fisa>")])
14454 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14455 (define_expand "fnma<mode>
4"
14456 [(set (match_operand:FMA_F
0 "gpc_reg_operand")
14459 (match_operand:FMA_F
1 "gpc_reg_operand")
14460 (match_operand:FMA_F
2 "gpc_reg_operand")
14461 (neg:FMA_F (match_operand:FMA_F
3 "gpc_reg_operand")))))]
14462 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14465 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14466 (define_expand "fnms<mode>
4"
14467 [(set (match_operand:FMA_F
0 "gpc_reg_operand")
14470 (match_operand:FMA_F
1 "gpc_reg_operand")
14471 (match_operand:FMA_F
2 "gpc_reg_operand")
14472 (match_operand:FMA_F
3 "gpc_reg_operand"))))]
14473 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14476 ; Not an official optab name, but used from builtins.
14477 (define_expand "nfma<mode>
4"
14478 [(set (match_operand:FMA_F
0 "gpc_reg_operand")
14481 (match_operand:FMA_F
1 "gpc_reg_operand")
14482 (match_operand:FMA_F
2 "gpc_reg_operand")
14483 (match_operand:FMA_F
3 "gpc_reg_operand"))))]
14484 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14487 (define_insn "*nfma<mode>
4_fpr"
14488 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa,wa")
14491 (match_operand:SFDF
1 "gpc_reg_operand" "d,wa,wa")
14492 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa,
0")
14493 (match_operand:SFDF
3 "gpc_reg_operand" "d,
0,wa"))))]
14494 "TARGET_HARD_FLOAT"
14496 fnmadd<s> %
0,%
1,%
2,%
3
14497 xsnmadda<sd>p %x0,%x1,%x2
14498 xsnmaddm<sd>p %x0,%x1,%x3"
14499 [(set_attr "type" "fp")
14500 (set_attr "isa" "*,<Fisa>,<Fisa>")])
14502 ; Not an official optab name, but used from builtins.
14503 (define_expand "nfms<mode>
4"
14504 [(set (match_operand:FMA_F
0 "gpc_reg_operand")
14507 (match_operand:FMA_F
1 "gpc_reg_operand")
14508 (match_operand:FMA_F
2 "gpc_reg_operand")
14509 (neg:FMA_F (match_operand:FMA_F
3 "gpc_reg_operand")))))]
14513 (define_insn "*nfmssf4_fpr"
14514 [(set (match_operand:SFDF
0 "gpc_reg_operand" "=d,wa,wa")
14517 (match_operand:SFDF
1 "gpc_reg_operand" "d,wa,wa")
14518 (match_operand:SFDF
2 "gpc_reg_operand" "d,wa,
0")
14520 (match_operand:SFDF
3 "gpc_reg_operand" "d,
0,wa")))))]
14521 "TARGET_HARD_FLOAT"
14523 fnmsub<s> %
0,%
1,%
2,%
3
14524 xsnmsuba<sd>p %x0,%x1,%x2
14525 xsnmsubm<sd>p %x0,%x1,%x3"
14526 [(set_attr "type" "fp")
14527 (set_attr "isa" "*,<Fisa>,<Fisa>")])
14529 (define_expand "rs6000_get_timebase"
14530 [(use (match_operand:DI
0 "gpc_reg_operand"))]
14533 if (TARGET_POWERPC64)
14534 emit_insn (gen_rs6000_mftb_di (operands[
0]));
14536 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[
0]));
14540 (define_insn "rs6000_get_timebase_ppc32"
14541 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
14542 (unspec_volatile:DI [(const_int
0)] UNSPECV_MFTB))
14543 (clobber (match_scratch:SI
1 "=r"))
14544 (clobber (match_scratch:CC
2 "=y"))]
14545 "!TARGET_POWERPC64"
14547 if (WORDS_BIG_ENDIAN)
14550 return "mfspr %
0,
269\;"
14558 return "mftbu %
0\;"
14567 return "mfspr %L0,
269\;"
14575 return "mftbu %L0\;"
14582 [(set_attr "length" "
20")])
14584 (define_insn "rs6000_mftb_<mode>"
14585 [(set (match_operand:GPR
0 "gpc_reg_operand" "=r")
14586 (unspec_volatile:GPR [(const_int
0)] UNSPECV_MFTB))]
14590 return "mfspr %
0,
268";
14596 ;; The ISA
3.0 mffsl instruction is a lower latency instruction
14597 ;; for reading bits [
29:
31], [
45:
51] and [
56:
63] of the FPSCR.
14598 (define_insn "rs6000_mffsl_hw"
14599 [(set (match_operand:DF
0 "gpc_reg_operand" "=d")
14600 (unspec_volatile:DF [(const_int
0)] UNSPECV_MFFSL))]
14601 "TARGET_HARD_FLOAT"
14604 (define_expand "rs6000_mffsl"
14605 [(set (match_operand:DF
0 "gpc_reg_operand")
14606 (unspec_volatile:DF [(const_int
0)] UNSPECV_MFFSL))]
14607 "TARGET_HARD_FLOAT"
14609 /* If the low latency mffsl instruction (ISA
3.0) is available use it,
14610 otherwise fall back to the older mffs instruction to emulate the mffsl
14613 if (!TARGET_P9_MISC)
14615 rtx tmp1 = gen_reg_rtx (DFmode);
14617 /* The mffs instruction reads the entire FPSCR. Emulate the mffsl
14618 instruction using the mffs instruction and masking the result. */
14619 emit_insn (gen_rs6000_mffs (tmp1));
14621 rtx tmp1di = simplify_gen_subreg (DImode, tmp1, DFmode,
0);
14622 rtx tmp2 = gen_reg_rtx (DImode);
14623 emit_insn (gen_anddi3 (tmp2, tmp1di, GEN_INT (
0x70007f0ffLL)));
14625 rtx tmp2df = simplify_gen_subreg (DFmode, tmp2, DImode,
0);
14626 emit_move_insn (operands[
0], tmp2df);
14630 emit_insn (gen_rs6000_mffsl_hw (operands[
0]));
14634 (define_insn "rs6000_mffs"
14635 [(set (match_operand:DF
0 "gpc_reg_operand" "=d")
14636 (unspec_volatile:DF [(const_int
0)] UNSPECV_MFFS))]
14637 "TARGET_HARD_FLOAT"
14640 (define_insn "rs6000_mtfsf"
14641 [(unspec_volatile [(match_operand:SI
0 "const_int_operand" "i")
14642 (match_operand:DF
1 "gpc_reg_operand" "d")]
14644 "TARGET_HARD_FLOAT"
14647 (define_insn "rs6000_mtfsf_hi"
14648 [(unspec_volatile [(match_operand:SI
0 "const_int_operand" "n")
14649 (match_operand:DF
1 "gpc_reg_operand" "d")]
14651 "TARGET_HARD_FLOAT"
14655 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
14656 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
14657 ;; register that is being loaded. The fused ops must be physically adjacent.
14659 ;; On Power8 GPR loads, we try to use the register that is being load. The
14660 ;; peephole2 then gathers any other fused possibilities that it can find after
14661 ;; register allocation. If power9 fusion is selected, we also fuse floating
14662 ;; point loads/stores.
14664 ;; Find cases where the addis that feeds into a load instruction is either used
14665 ;; once or is the same as the target register, and replace it with the fusion
14669 [(set (match_operand:P
0 "base_reg_operand")
14670 (match_operand:P
1 "fusion_gpr_addis"))
14671 (set (match_operand:INT1
2 "base_reg_operand")
14672 (match_operand:INT1
3 "fusion_gpr_mem_load"))]
14674 && fusion_gpr_load_p (operands[
0], operands[
1], operands[
2],
14678 expand_fusion_gpr_load (operands);
14682 ;; Fusion insn, created by the define_peephole2 above (and eventually by
14685 (define_insn "*fusion_gpr_load_<mode>"
14686 [(set (match_operand:INT1
0 "base_reg_operand" "=b")
14687 (unspec:INT1 [(match_operand:INT1
1 "fusion_addis_mem_combo_load" "wF")]
14688 UNSPEC_FUSION_GPR))]
14691 return emit_fusion_gpr_load (operands[
0], operands[
1]);
14693 [(set_attr "type" "load")
14694 (set_attr "length" "
8")])
14697 ;; Optimize cases where we want to do a D-form load (register+offset) on
14698 ;; ISA
2.06/
2.07 to an Altivec register, and the register allocator
14703 ;; and we change this to:
14708 [(match_scratch:P
0 "b")
14709 (set (match_operand:ALTIVEC_DFORM
1 "fpr_reg_operand")
14710 (match_operand:ALTIVEC_DFORM
2 "simple_offsettable_mem_operand"))
14711 (set (match_operand:ALTIVEC_DFORM
3 "altivec_register_operand")
14713 "TARGET_VSX && !TARGET_P9_VECTOR && peep2_reg_dead_p (
2, operands[
1])"
14714 [(set (match_dup
0)
14719 rtx tmp_reg = operands[
0];
14720 rtx mem = operands[
2];
14721 rtx addr = XEXP (mem,
0);
14722 rtx add_op0, add_op1, new_addr;
14724 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
14725 add_op0 = XEXP (addr,
0);
14726 add_op1 = XEXP (addr,
1);
14727 gcc_assert (REG_P (add_op0));
14728 new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
14730 operands[
4] = add_op1;
14731 operands[
5] = change_address (mem, <ALTIVEC_DFORM:MODE>mode, new_addr);
14734 ;; Optimize cases were want to do a D-form store on ISA
2.06/
2.07 from an
14735 ;; Altivec register, and the register allocator has generated:
14739 ;; and we change this to:
14744 [(match_scratch:P
0 "b")
14745 (set (match_operand:ALTIVEC_DFORM
1 "fpr_reg_operand")
14746 (match_operand:ALTIVEC_DFORM
2 "altivec_register_operand"))
14747 (set (match_operand:ALTIVEC_DFORM
3 "simple_offsettable_mem_operand")
14749 "TARGET_VSX && !TARGET_P9_VECTOR && peep2_reg_dead_p (
2, operands[
1])"
14750 [(set (match_dup
0)
14755 rtx tmp_reg = operands[
0];
14756 rtx mem = operands[
3];
14757 rtx addr = XEXP (mem,
0);
14758 rtx add_op0, add_op1, new_addr;
14760 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
14761 add_op0 = XEXP (addr,
0);
14762 add_op1 = XEXP (addr,
1);
14763 gcc_assert (REG_P (add_op0));
14764 new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
14766 operands[
4] = add_op1;
14767 operands[
5] = change_address (mem, <ALTIVEC_DFORM:MODE>mode, new_addr);
14771 ;; Miscellaneous ISA
2.06 (power7) instructions
14772 (define_insn "addg6s"
14773 [(set (match_operand:SI
0 "register_operand" "=r")
14774 (unspec:SI [(match_operand:SI
1 "register_operand" "r")
14775 (match_operand:SI
2 "register_operand" "r")]
14779 [(set_attr "type" "integer")])
14781 (define_insn "cdtbcd"
14782 [(set (match_operand:SI
0 "register_operand" "=r")
14783 (unspec:SI [(match_operand:SI
1 "register_operand" "r")]
14787 [(set_attr "type" "integer")])
14789 (define_insn "cbcdtd"
14790 [(set (match_operand:SI
0 "register_operand" "=r")
14791 (unspec:SI [(match_operand:SI
1 "register_operand" "r")]
14795 [(set_attr "type" "integer")])
14797 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
14800 (define_int_attr div_extend [(UNSPEC_DIVE "e")
14801 (UNSPEC_DIVEU "eu")])
14803 (define_insn "div<div_extend>_<mode>"
14804 [(set (match_operand:GPR
0 "register_operand" "=r")
14805 (unspec:GPR [(match_operand:GPR
1 "register_operand" "r")
14806 (match_operand:GPR
2 "register_operand" "r")]
14807 UNSPEC_DIV_EXTEND))]
14809 "div<wd><div_extend> %
0,%
1,%
2"
14810 [(set_attr "type" "div")
14811 (set_attr "size" "<bits>")])
14814 ;; Pack/unpack
128-bit floating point types that take
2 scalar registers
14816 ; Type of the
64-bit part when packing/unpacking
128-bit floating point types
14817 (define_mode_attr FP128_64 [(TF "DF")
14822 (define_expand "unpack<mode>"
14823 [(set (match_operand:<FP128_64>
0 "nonimmediate_operand")
14825 [(match_operand:FMOVE128
1 "register_operand")
14826 (match_operand:QI
2 "const_0_to_1_operand")]
14827 UNSPEC_UNPACK_128BIT))]
14828 "FLOAT128_2REG_P (<MODE>mode)"
14831 (define_insn_and_split "unpack<mode>_dm"
14832 [(set (match_operand:<FP128_64>
0 "nonimmediate_operand" "=d,m,d,r,m")
14834 [(match_operand:FMOVE128
1 "register_operand" "d,d,r,d,r")
14835 (match_operand:QI
2 "const_0_to_1_operand" "i,i,i,i,i")]
14836 UNSPEC_UNPACK_128BIT))]
14837 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (<MODE>mode)"
14839 "&& reload_completed"
14840 [(set (match_dup
0) (match_dup
3))]
14842 unsigned fp_regno = REGNO (operands[
1]) + UINTVAL (operands[
2]);
14844 if (REG_P (operands[
0]) && REGNO (operands[
0]) == fp_regno)
14846 emit_note (NOTE_INSN_DELETED);
14850 operands[
3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14852 [(set_attr "type" "fp,fpstore,mtvsr,mfvsr,store")])
14854 (define_insn_and_split "unpack<mode>_nodm"
14855 [(set (match_operand:<FP128_64>
0 "nonimmediate_operand" "=d,m,m")
14857 [(match_operand:FMOVE128
1 "register_operand" "d,d,r")
14858 (match_operand:QI
2 "const_0_to_1_operand" "i,i,i")]
14859 UNSPEC_UNPACK_128BIT))]
14860 "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (<MODE>mode)"
14862 "&& reload_completed"
14863 [(set (match_dup
0) (match_dup
3))]
14865 unsigned fp_regno = REGNO (operands[
1]) + UINTVAL (operands[
2]);
14867 if (REG_P (operands[
0]) && REGNO (operands[
0]) == fp_regno)
14869 emit_note (NOTE_INSN_DELETED);
14873 operands[
3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
14875 [(set_attr "type" "fp,fpstore,store")])
14877 (define_expand "pack<mode>"
14878 [(use (match_operand:FMOVE128
0 "register_operand"))
14879 (use (match_operand:<FP128_64>
1 "register_operand"))
14880 (use (match_operand:<FP128_64>
2 "register_operand"))]
14881 "FLOAT128_2REG_P (<MODE>mode)"
14883 if (TARGET_HARD_FLOAT)
14884 emit_insn (gen_pack<mode>_hard (operands[
0], operands[
1], operands[
2]));
14886 emit_insn (gen_pack<mode>_soft (operands[
0], operands[
1], operands[
2]));
14890 (define_insn_and_split "pack<mode>_hard"
14891 [(set (match_operand:FMOVE128
0 "register_operand" "=&d")
14893 [(match_operand:<FP128_64>
1 "register_operand" "d")
14894 (match_operand:<FP128_64>
2 "register_operand" "d")]
14895 UNSPEC_PACK_128BIT))]
14896 "FLOAT128_2REG_P (<MODE>mode) && TARGET_HARD_FLOAT"
14898 "&& reload_completed"
14899 [(set (match_dup
3) (match_dup
1))
14900 (set (match_dup
4) (match_dup
2))]
14902 unsigned dest_hi = REGNO (operands[
0]);
14903 unsigned dest_lo = dest_hi +
1;
14905 gcc_assert (!IN_RANGE (REGNO (operands[
1]), dest_hi, dest_lo));
14906 gcc_assert (!IN_RANGE (REGNO (operands[
2]), dest_hi, dest_lo));
14908 operands[
3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14909 operands[
4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14911 [(set_attr "type" "fp")
14912 (set_attr "length" "
8")])
14914 (define_insn_and_split "pack<mode>_soft"
14915 [(set (match_operand:FMOVE128
0 "register_operand" "=&r")
14917 [(match_operand:<FP128_64>
1 "register_operand" "r")
14918 (match_operand:<FP128_64>
2 "register_operand" "r")]
14919 UNSPEC_PACK_128BIT))]
14920 "FLOAT128_2REG_P (<MODE>mode) && TARGET_SOFT_FLOAT"
14922 "&& reload_completed"
14923 [(set (match_dup
3) (match_dup
1))
14924 (set (match_dup
4) (match_dup
2))]
14926 unsigned dest_hi = REGNO (operands[
0]);
14927 unsigned dest_lo = dest_hi + (TARGET_POWERPC64 ?
1 :
2);
14929 gcc_assert (!IN_RANGE (REGNO (operands[
1]), dest_hi, dest_lo));
14930 gcc_assert (!IN_RANGE (REGNO (operands[
2]), dest_hi, dest_lo));
14932 operands[
3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
14933 operands[
4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
14935 [(set_attr "type" "integer")
14936 (set (attr "length")
14938 (match_test "TARGET_POWERPC64")
14940 (const_string "
16")))])
14942 (define_insn "unpack<mode>"
14943 [(set (match_operand:DI
0 "register_operand" "=wa,wa")
14944 (unspec:DI [(match_operand:FMOVE128_VSX
1 "register_operand" "
0,wa")
14945 (match_operand:QI
2 "const_0_to_1_operand" "O,i")]
14946 UNSPEC_UNPACK_128BIT))]
14947 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
14949 if (REGNO (operands[
0]) == REGNO (operands[
1]) && INTVAL (operands[
2]) ==
0)
14950 return ASM_COMMENT_START " xxpermdi to same register";
14952 operands[
3] = GEN_INT (INTVAL (operands[
2]) ==
0 ?
0 :
3);
14953 return "xxpermdi %x0,%x1,%x1,%
3";
14955 [(set_attr "type" "vecperm")])
14957 (define_insn "pack<mode>"
14958 [(set (match_operand:FMOVE128_VSX
0 "register_operand" "=wa")
14959 (unspec:FMOVE128_VSX
14960 [(match_operand:DI
1 "register_operand" "wa")
14961 (match_operand:DI
2 "register_operand" "wa")]
14962 UNSPEC_PACK_128BIT))]
14964 "xxpermdi %x0,%x1,%x2,
0"
14965 [(set_attr "type" "vecperm")])
14969 ;; ISA
2.08 IEEE
128-bit floating point support.
14971 (define_insn "add<mode>
3"
14972 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
14974 (match_operand:IEEE128
1 "altivec_register_operand" "v")
14975 (match_operand:IEEE128
2 "altivec_register_operand" "v")))]
14976 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
14978 [(set_attr "type" "vecfloat")
14979 (set_attr "size" "
128")])
14981 (define_insn "sub<mode>
3"
14982 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
14984 (match_operand:IEEE128
1 "altivec_register_operand" "v")
14985 (match_operand:IEEE128
2 "altivec_register_operand" "v")))]
14986 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
14988 [(set_attr "type" "vecfloat")
14989 (set_attr "size" "
128")])
14991 (define_insn "mul<mode>
3"
14992 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
14994 (match_operand:IEEE128
1 "altivec_register_operand" "v")
14995 (match_operand:IEEE128
2 "altivec_register_operand" "v")))]
14996 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
14998 [(set_attr "type" "qmul")
14999 (set_attr "size" "
128")])
15001 (define_insn "div<mode>
3"
15002 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15004 (match_operand:IEEE128
1 "altivec_register_operand" "v")
15005 (match_operand:IEEE128
2 "altivec_register_operand" "v")))]
15006 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15008 [(set_attr "type" "vecdiv")
15009 (set_attr "size" "
128")])
15011 (define_insn "sqrt<mode>
2"
15012 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15014 (match_operand:IEEE128
1 "altivec_register_operand" "v")))]
15015 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15017 [(set_attr "type" "vecdiv")
15018 (set_attr "size" "
128")])
15020 (define_expand "copysign<mode>
3"
15021 [(use (match_operand:IEEE128
0 "altivec_register_operand"))
15022 (use (match_operand:IEEE128
1 "altivec_register_operand"))
15023 (use (match_operand:IEEE128
2 "any_operand"))]
15024 "FLOAT128_IEEE_P (<MODE>mode)"
15026 /* Middle-end canonicalizes -fabs (x) to copysign (x, -
1),
15027 but PowerPC prefers -fabs (x). */
15028 if (CONST_DOUBLE_AS_FLOAT_P (operands[
2]))
15030 if (real_isneg (CONST_DOUBLE_REAL_VALUE (operands[
2])))
15032 rtx abs_res = gen_reg_rtx (<MODE>mode);
15033 emit_insn (gen_abs<mode>
2 (abs_res, operands[
1]));
15034 emit_insn (gen_neg<mode>
2 (operands[
0], abs_res));
15037 emit_insn (gen_abs<mode>
2 (operands[
0], operands[
1]));
15041 if (!altivec_register_operand (operands[
2], <MODE>mode))
15042 operands[
2] = copy_to_mode_reg (<MODE>mode, operands[
2]);
15044 if (TARGET_FLOAT128_HW)
15045 emit_insn (gen_copysign<mode>
3_hard (operands[
0], operands[
1],
15048 emit_insn (gen_copysign<mode>
3_soft (operands[
0], operands[
1],
15053 (define_insn "copysign<mode>
3_hard"
15054 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15056 (match_operand:IEEE128
1 "altivec_register_operand" "v")
15057 (match_operand:IEEE128
2 "altivec_register_operand" "v")))]
15058 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15059 "xscpsgnqp %
0,%
2,%
1"
15060 [(set_attr "type" "vecmove")
15061 (set_attr "size" "
128")])
15063 (define_insn "copysign<mode>
3_soft"
15064 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15066 (match_operand:IEEE128
1 "altivec_register_operand" "v")
15067 (match_operand:IEEE128
2 "altivec_register_operand" "v")))
15068 (clobber (match_scratch:IEEE128
3 "=&v"))]
15069 "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15070 "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,
1"
15071 [(set_attr "type" "veccomplex")
15072 (set_attr "length" "
8")])
15074 (define_insn "@neg<mode>
2_hw"
15075 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15077 (match_operand:IEEE128
1 "altivec_register_operand" "v")))]
15078 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15080 [(set_attr "type" "vecmove")
15081 (set_attr "size" "
128")])
15084 (define_insn "@abs<mode>
2_hw"
15085 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15087 (match_operand:IEEE128
1 "altivec_register_operand" "v")))]
15088 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15090 [(set_attr "type" "vecmove")
15091 (set_attr "size" "
128")])
15094 (define_insn "*nabs<mode>
2_hw"
15095 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15098 (match_operand:IEEE128
1 "altivec_register_operand" "v"))))]
15099 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15101 [(set_attr "type" "vecmove")
15102 (set_attr "size" "
128")])
15104 ;; Initially don't worry about doing fusion
15105 (define_insn "fma<mode>
4_hw"
15106 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15108 (match_operand:IEEE128
1 "altivec_register_operand" "%v")
15109 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15110 (match_operand:IEEE128
3 "altivec_register_operand" "
0")))]
15111 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15112 "xsmaddqp %
0,%
1,%
2"
15113 [(set_attr "type" "qmul")
15114 (set_attr "size" "
128")])
15116 (define_insn "*fms<mode>
4_hw"
15117 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15119 (match_operand:IEEE128
1 "altivec_register_operand" "%v")
15120 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15122 (match_operand:IEEE128
3 "altivec_register_operand" "
0"))))]
15123 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15124 "xsmsubqp %
0,%
1,%
2"
15125 [(set_attr "type" "qmul")
15126 (set_attr "size" "
128")])
15128 (define_insn "*nfma<mode>
4_hw"
15129 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15132 (match_operand:IEEE128
1 "altivec_register_operand" "%v")
15133 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15134 (match_operand:IEEE128
3 "altivec_register_operand" "
0"))))]
15135 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15136 "xsnmaddqp %
0,%
1,%
2"
15137 [(set_attr "type" "qmul")
15138 (set_attr "size" "
128")])
15140 (define_insn "*nfms<mode>
4_hw"
15141 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15144 (match_operand:IEEE128
1 "altivec_register_operand" "%v")
15145 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15147 (match_operand:IEEE128
3 "altivec_register_operand" "
0")))))]
15148 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15149 "xsnmsubqp %
0,%
1,%
2"
15150 [(set_attr "type" "qmul")
15151 (set_attr "size" "
128")])
15153 (define_insn "extend<SFDF:mode><IEEE128:mode>
2_hw"
15154 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15155 (float_extend:IEEE128
15156 (match_operand:SFDF
1 "altivec_register_operand" "v")))]
15157 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
15159 [(set_attr "type" "vecfloat")
15160 (set_attr "size" "
128")])
15162 ;; Conversion between KFmode and TFmode if TFmode is ieee
128-bit floating
15163 ;; point is a simple copy.
15164 (define_insn_and_split "extendkftf2"
15165 [(set (match_operand:TF
0 "vsx_register_operand" "=wa,?wa")
15166 (float_extend:TF (match_operand:KF
1 "vsx_register_operand" "
0,wa")))]
15167 "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
15171 "&& reload_completed && REGNO (operands[
0]) == REGNO (operands[
1])"
15174 emit_note (NOTE_INSN_DELETED);
15177 [(set_attr "type" "*,veclogical")
15178 (set_attr "length" "
0,
4")])
15180 (define_insn_and_split "trunctfkf2"
15181 [(set (match_operand:KF
0 "vsx_register_operand" "=wa,?wa")
15182 (float_extend:KF (match_operand:TF
1 "vsx_register_operand" "
0,wa")))]
15183 "TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD"
15187 "&& reload_completed && REGNO (operands[
0]) == REGNO (operands[
1])"
15190 emit_note (NOTE_INSN_DELETED);
15193 [(set_attr "type" "*,veclogical")
15194 (set_attr "length" "
0,
4")])
15196 (define_insn "trunc<mode>df2_hw"
15197 [(set (match_operand:DF
0 "altivec_register_operand" "=v")
15199 (match_operand:IEEE128
1 "altivec_register_operand" "v")))]
15200 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15202 [(set_attr "type" "vecfloat")
15203 (set_attr "size" "
128")])
15205 ;; There is no KFmode -> SFmode instruction. Preserve the accuracy by doing
15206 ;; the KFmode -> DFmode conversion using round to odd rather than the normal
15208 (define_insn_and_split "trunc<mode>sf2_hw"
15209 [(set (match_operand:SF
0 "vsx_register_operand" "=wa")
15211 (match_operand:IEEE128
1 "altivec_register_operand" "v")))
15212 (clobber (match_scratch:DF
2 "=v"))]
15213 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15216 [(set (match_dup
2)
15217 (unspec:DF [(match_dup
1)]
15218 UNSPEC_TRUNC_ROUND_TO_ODD))
15220 (float_truncate:SF (match_dup
2)))]
15222 if (GET_CODE (operands[
2]) == SCRATCH)
15223 operands[
2] = gen_reg_rtx (DFmode);
15225 [(set_attr "type" "vecfloat")
15226 (set_attr "length" "
8")
15227 (set_attr "isa" "p8v")])
15229 ;; Conversion between IEEE
128-bit and integer types
15231 ;; The fix function for DImode and SImode was declared earlier as a
15232 ;; define_expand. It calls into rs6000_expand_float128_convert if we don't
15233 ;; have IEEE
128-bit hardware support. QImode and HImode are not provided
15234 ;; unless we have the IEEE
128-bit hardware.
15236 ;; Unlike the code for converting SFmode/DFmode to QImode/HImode, we don't have
15237 ;; to provide a GPR target that used direct move and a conversion in the GPR
15238 ;; which works around QImode/HImode not being allowed in vector registers in
15239 ;; ISA
2.07 (power8).
15240 (define_insn "fix<uns>_<IEEE128:mode><SDI:mode>
2_hw"
15241 [(set (match_operand:SDI
0 "altivec_register_operand" "=v")
15242 (any_fix:SDI (match_operand:IEEE128
1 "altivec_register_operand" "v")))]
15243 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
15244 "xscvqp<su><wd>z %
0,%
1"
15245 [(set_attr "type" "vecfloat")
15246 (set_attr "size" "
128")])
15248 (define_insn "fix<uns>_trunc<IEEE128:mode><QHI:mode>
2"
15249 [(set (match_operand:QHI
0 "altivec_register_operand" "=v")
15251 (match_operand:IEEE128
1 "altivec_register_operand" "v")))]
15252 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
15253 "xscvqp<su>wz %
0,%
1"
15254 [(set_attr "type" "vecfloat")
15255 (set_attr "size" "
128")])
15257 ;; Combiner patterns to prevent moving the result of converting an IEEE
128-bit
15258 ;; floating point value to
8/
16/
32-bit integer to GPR in order to save it.
15259 (define_insn_and_split "*fix<uns>_trunc<IEEE128:mode><QHSI:mode>
2_mem"
15260 [(set (match_operand:QHSI
0 "memory_operand" "=Z")
15262 (match_operand:IEEE128
1 "altivec_register_operand" "v")))
15263 (clobber (match_scratch:QHSI
2 "=v"))]
15264 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
15266 "&& reload_completed"
15267 [(set (match_dup
2)
15268 (any_fix:QHSI (match_dup
1)))
15272 (define_insn "float_<mode>di2_hw"
15273 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15274 (float:IEEE128 (match_operand:DI
1 "altivec_register_operand" "v")))]
15275 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15277 [(set_attr "type" "vecfloat")
15278 (set_attr "size" "
128")])
15280 (define_insn_and_split "float_<mode>si2_hw"
15281 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15282 (float:IEEE128 (match_operand:SI
1 "nonimmediate_operand" "vrZ")))
15283 (clobber (match_scratch:DI
2 "=v"))]
15284 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15287 [(set (match_dup
2)
15288 (sign_extend:DI (match_dup
1)))
15290 (float:IEEE128 (match_dup
2)))]
15292 if (GET_CODE (operands[
2]) == SCRATCH)
15293 operands[
2] = gen_reg_rtx (DImode);
15295 if (MEM_P (operands[
1]))
15296 operands[
1] = rs6000_force_indexed_or_indirect_mem (operands[
1]);
15299 (define_insn_and_split "float<QHI:mode><IEEE128:mode>
2"
15300 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v,v,v")
15301 (float:IEEE128 (match_operand:QHI
1 "nonimmediate_operand" "v,r,Z")))
15302 (clobber (match_scratch:DI
2 "=X,r,X"))]
15303 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
15305 "&& reload_completed"
15308 rtx dest = operands[
0];
15309 rtx src = operands[
1];
15310 rtx dest_di = gen_rtx_REG (DImode, REGNO (dest));
15312 if (altivec_register_operand (src, <QHI:MODE>mode))
15313 emit_insn (gen_extend<QHI:mode>di2 (dest_di, src));
15314 else if (int_reg_operand (src, <QHI:MODE>mode))
15316 rtx ext_di = operands[
2];
15317 emit_insn (gen_extend<QHI:mode>di2 (ext_di, src));
15318 emit_move_insn (dest_di, ext_di);
15320 else if (MEM_P (src))
15322 rtx dest_qhi = gen_rtx_REG (<QHI:MODE>mode, REGNO (dest));
15323 emit_move_insn (dest_qhi, src);
15324 emit_insn (gen_extend<QHI:mode>di2 (dest_di, dest_qhi));
15327 gcc_unreachable ();
15329 emit_insn (gen_float_<IEEE128:mode>di2_hw (dest, dest_di));
15332 [(set_attr "length" "
8,
12,
12")
15333 (set_attr "type" "vecfloat")
15334 (set_attr "size" "
128")])
15336 (define_insn "floatuns_<mode>di2_hw"
15337 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15338 (unsigned_float:IEEE128
15339 (match_operand:DI
1 "altivec_register_operand" "v")))]
15340 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15342 [(set_attr "type" "vecfloat")
15343 (set_attr "size" "
128")])
15345 (define_insn_and_split "floatuns_<mode>si2_hw"
15346 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15347 (unsigned_float:IEEE128
15348 (match_operand:SI
1 "nonimmediate_operand" "vrZ")))
15349 (clobber (match_scratch:DI
2 "=v"))]
15350 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15353 [(set (match_dup
2)
15354 (zero_extend:DI (match_dup
1)))
15356 (float:IEEE128 (match_dup
2)))]
15358 if (GET_CODE (operands[
2]) == SCRATCH)
15359 operands[
2] = gen_reg_rtx (DImode);
15361 if (MEM_P (operands[
1]))
15362 operands[
1] = rs6000_force_indexed_or_indirect_mem (operands[
1]);
15365 (define_insn_and_split "floatuns<QHI:mode><IEEE128:mode>
2"
15366 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v,v,v")
15367 (unsigned_float:IEEE128
15368 (match_operand:QHI
1 "nonimmediate_operand" "v,r,Z")))
15369 (clobber (match_scratch:DI
2 "=X,r,X"))]
15370 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
15372 "&& reload_completed"
15375 rtx dest = operands[
0];
15376 rtx src = operands[
1];
15377 rtx dest_di = gen_rtx_REG (DImode, REGNO (dest));
15379 if (altivec_register_operand (src, <QHI:MODE>mode) || MEM_P (src))
15380 emit_insn (gen_zero_extend<QHI:mode>di2 (dest_di, src));
15381 else if (int_reg_operand (src, <QHI:MODE>mode))
15383 rtx ext_di = operands[
2];
15384 emit_insn (gen_zero_extend<QHI:mode>di2 (ext_di, src));
15385 emit_move_insn (dest_di, ext_di);
15388 gcc_unreachable ();
15390 emit_insn (gen_floatuns_<IEEE128:mode>di2_hw (dest, dest_di));
15393 [(set_attr "length" "
8,
12,
8")
15394 (set_attr "type" "vecfloat")
15395 (set_attr "size" "
128")])
15397 ;; IEEE
128-bit round to integer built-in functions
15398 (define_insn "floor<mode>
2"
15399 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15401 [(match_operand:IEEE128
1 "altivec_register_operand" "v")]
15403 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15405 [(set_attr "type" "vecfloat")
15406 (set_attr "size" "
128")])
15408 (define_insn "ceil<mode>
2"
15409 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15411 [(match_operand:IEEE128
1 "altivec_register_operand" "v")]
15413 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15415 [(set_attr "type" "vecfloat")
15416 (set_attr "size" "
128")])
15418 (define_insn "btrunc<mode>
2"
15419 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15421 [(match_operand:IEEE128
1 "altivec_register_operand" "v")]
15423 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15425 [(set_attr "type" "vecfloat")
15426 (set_attr "size" "
128")])
15428 (define_insn "round<mode>
2"
15429 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15431 [(match_operand:IEEE128
1 "altivec_register_operand" "v")]
15433 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15435 [(set_attr "type" "vecfloat")
15436 (set_attr "size" "
128")])
15438 ;; IEEE
128-bit instructions with round to odd semantics
15439 (define_insn "add<mode>
3_odd"
15440 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15442 [(match_operand:IEEE128
1 "altivec_register_operand" "v")
15443 (match_operand:IEEE128
2 "altivec_register_operand" "v")]
15444 UNSPEC_ADD_ROUND_TO_ODD))]
15445 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15446 "xsaddqpo %
0,%
1,%
2"
15447 [(set_attr "type" "vecfloat")
15448 (set_attr "size" "
128")])
15450 (define_insn "sub<mode>
3_odd"
15451 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15453 [(match_operand:IEEE128
1 "altivec_register_operand" "v")
15454 (match_operand:IEEE128
2 "altivec_register_operand" "v")]
15455 UNSPEC_SUB_ROUND_TO_ODD))]
15456 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15457 "xssubqpo %
0,%
1,%
2"
15458 [(set_attr "type" "vecfloat")
15459 (set_attr "size" "
128")])
15461 (define_insn "mul<mode>
3_odd"
15462 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15464 [(match_operand:IEEE128
1 "altivec_register_operand" "v")
15465 (match_operand:IEEE128
2 "altivec_register_operand" "v")]
15466 UNSPEC_MUL_ROUND_TO_ODD))]
15467 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15468 "xsmulqpo %
0,%
1,%
2"
15469 [(set_attr "type" "qmul")
15470 (set_attr "size" "
128")])
15472 (define_insn "div<mode>
3_odd"
15473 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15475 [(match_operand:IEEE128
1 "altivec_register_operand" "v")
15476 (match_operand:IEEE128
2 "altivec_register_operand" "v")]
15477 UNSPEC_DIV_ROUND_TO_ODD))]
15478 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15479 "xsdivqpo %
0,%
1,%
2"
15480 [(set_attr "type" "vecdiv")
15481 (set_attr "size" "
128")])
15483 (define_insn "sqrt<mode>
2_odd"
15484 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15486 [(match_operand:IEEE128
1 "altivec_register_operand" "v")]
15487 UNSPEC_SQRT_ROUND_TO_ODD))]
15488 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15490 [(set_attr "type" "vecdiv")
15491 (set_attr "size" "
128")])
15493 (define_insn "fma<mode>
4_odd"
15494 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15496 [(match_operand:IEEE128
1 "altivec_register_operand" "v")
15497 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15498 (match_operand:IEEE128
3 "altivec_register_operand" "
0")]
15499 UNSPEC_FMA_ROUND_TO_ODD))]
15500 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15501 "xsmaddqpo %
0,%
1,%
2"
15502 [(set_attr "type" "qmul")
15503 (set_attr "size" "
128")])
15505 (define_insn "*fms<mode>
4_odd"
15506 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15508 [(match_operand:IEEE128
1 "altivec_register_operand" "%v")
15509 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15511 (match_operand:IEEE128
3 "altivec_register_operand" "
0"))]
15512 UNSPEC_FMA_ROUND_TO_ODD))]
15513 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15514 "xsmsubqpo %
0,%
1,%
2"
15515 [(set_attr "type" "qmul")
15516 (set_attr "size" "
128")])
15518 (define_insn "*nfma<mode>
4_odd"
15519 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15522 [(match_operand:IEEE128
1 "altivec_register_operand" "%v")
15523 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15524 (match_operand:IEEE128
3 "altivec_register_operand" "
0")]
15525 UNSPEC_FMA_ROUND_TO_ODD)))]
15526 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15527 "xsnmaddqpo %
0,%
1,%
2"
15528 [(set_attr "type" "qmul")
15529 (set_attr "size" "
128")])
15531 (define_insn "*nfms<mode>
4_odd"
15532 [(set (match_operand:IEEE128
0 "altivec_register_operand" "=v")
15535 [(match_operand:IEEE128
1 "altivec_register_operand" "%v")
15536 (match_operand:IEEE128
2 "altivec_register_operand" "v")
15538 (match_operand:IEEE128
3 "altivec_register_operand" "
0"))]
15539 UNSPEC_FMA_ROUND_TO_ODD)))]
15540 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15541 "xsnmsubqpo %
0,%
1,%
2"
15542 [(set_attr "type" "qmul")
15543 (set_attr "size" "
128")])
15545 (define_insn "trunc<mode>df2_odd"
15546 [(set (match_operand:DF
0 "vsx_register_operand" "=v")
15547 (unspec:DF [(match_operand:IEEE128
1 "altivec_register_operand" "v")]
15548 UNSPEC_TRUNC_ROUND_TO_ODD))]
15549 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15551 [(set_attr "type" "vecfloat")
15552 (set_attr "size" "
128")])
15554 ;; IEEE
128-bit comparisons
15555 (define_insn "*cmp<mode>_hw"
15556 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
15557 (compare:CCFP (match_operand:IEEE128
1 "altivec_register_operand" "v")
15558 (match_operand:IEEE128
2 "altivec_register_operand" "v")))]
15559 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
15560 "xscmpuqp %
0,%
1,%
2"
15561 [(set_attr "type" "veccmp")
15562 (set_attr "size" "
128")])
15564 ;; Miscellaneous ISA
3.0 (power9) instructions
15566 (define_expand "darn_32_<mode>"
15567 [(use (match_operand:GPR
0 "register_operand"))]
15570 emit_insn (gen_darn (<MODE>mode, operands[
0], const0_rtx));
15574 (define_expand "darn_64_<mode>"
15575 [(use (match_operand:GPR
0 "register_operand"))]
15578 emit_insn (gen_darn (<MODE>mode, operands[
0], const1_rtx));
15582 (define_expand "darn_raw_<mode>"
15583 [(use (match_operand:GPR
0 "register_operand"))]
15586 emit_insn (gen_darn (<MODE>mode, operands[
0], const2_rtx));
15590 (define_insn "@darn<mode>"
15591 [(set (match_operand:GPR
0 "register_operand" "=r")
15592 (unspec_volatile:GPR [(match_operand
1 "const_int_operand" "n")]
15596 [(set_attr "type" "integer")])
15598 ;; Test byte within range.
15600 ;; The bytes of operand
1 are organized as xx:xx:xx:vv, where xx
15601 ;; represents a byte whose value is ignored in this context and
15602 ;; vv, the least significant byte, holds the byte value that is to
15603 ;; be tested for membership within the range specified by operand
2.
15604 ;; The bytes of operand
2 are organized as xx:xx:hi:lo.
15606 ;; Return in target register operand
0 a value of
1 if lo <= vv and
15607 ;; vv <= hi. Otherwise, set register operand
0 to
0.
15609 ;; Though the instructions to which this expansion maps operate on
15610 ;;
64-bit registers, the current implementation only operates on
15611 ;; SI-mode operands as the high-order bits provide no information
15612 ;; that is not already available in the low-order bits. To avoid the
15613 ;; costs of data widening operations, future enhancements might allow
15614 ;; DI mode for operand
0 and/or might allow operand
1 to be QI mode.
15615 (define_expand "cmprb"
15616 [(set (match_dup
3)
15617 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
15618 (match_operand:SI
2 "gpc_reg_operand" "r")]
15620 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
15621 (if_then_else:SI (lt (match_dup
3)
15624 (if_then_else (gt (match_dup
3)
15630 operands[
3] = gen_reg_rtx (CCmode);
15633 ;; The bytes of operand
1 are organized as xx:xx:xx:vv, where xx
15634 ;; represents a byte whose value is ignored in this context and
15635 ;; vv, the least significant byte, holds the byte value that is to
15636 ;; be tested for membership within the range specified by operand
2.
15637 ;; The bytes of operand
2 are organized as xx:xx:hi:lo.
15639 ;; Set bit
1 (the GT bit,
0x4) of CR register operand
0 to
1 if
15640 ;; lo <= vv and vv <= hi. Otherwise, set the GT bit to
0. The other
15641 ;;
3 bits of the target CR register are all set to
0.
15642 (define_insn "*cmprb_internal"
15643 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
15644 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
15645 (match_operand:SI
2 "gpc_reg_operand" "r")]
15649 [(set_attr "type" "logical")])
15651 ;; Set operand
0 register to -
1 if the LT bit (
0x8) of condition
15652 ;; register operand
1 is on. Otherwise, set operand
0 register to
1
15653 ;; if the GT bit (
0x4) of condition register operand
1 is on.
15654 ;; Otherwise, set operand
0 to
0. Note that the result stored into
15655 ;; register operand
0 is non-zero iff either the LT or GT bits are on
15656 ;; within condition register operand
1.
15657 (define_insn "setb_signed"
15658 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
15659 (if_then_else:SI (lt (match_operand:CC
1 "cc_reg_operand" "y")
15662 (if_then_else (gt (match_dup
1)
15668 [(set_attr "type" "logical")])
15670 (define_insn "setb_unsigned"
15671 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
15672 (if_then_else:SI (ltu (match_operand:CCUNS
1 "cc_reg_operand" "y")
15675 (if_then_else (gtu (match_dup
1)
15681 [(set_attr "type" "logical")])
15683 ;; Test byte within two ranges.
15685 ;; The bytes of operand
1 are organized as xx:xx:xx:vv, where xx
15686 ;; represents a byte whose value is ignored in this context and
15687 ;; vv, the least significant byte, holds the byte value that is to
15688 ;; be tested for membership within the range specified by operand
2.
15689 ;; The bytes of operand
2 are organized as hi_1:lo_1:hi_2:lo_2.
15691 ;; Return in target register operand
0 a value of
1 if (lo_1 <= vv and
15692 ;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register
15695 ;; Though the instructions to which this expansion maps operate on
15696 ;;
64-bit registers, the current implementation only operates on
15697 ;; SI-mode operands as the high-order bits provide no information
15698 ;; that is not already available in the low-order bits. To avoid the
15699 ;; costs of data widening operations, future enhancements might allow
15700 ;; DI mode for operand
0 and/or might allow operand
1 to be QI mode.
15701 (define_expand "cmprb2"
15702 [(set (match_dup
3)
15703 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
15704 (match_operand:SI
2 "gpc_reg_operand" "r")]
15706 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
15707 (if_then_else:SI (lt (match_dup
3)
15710 (if_then_else (gt (match_dup
3)
15716 operands[
3] = gen_reg_rtx (CCmode);
15719 ;; The bytes of operand
1 are organized as xx:xx:xx:vv, where xx
15720 ;; represents a byte whose value is ignored in this context and
15721 ;; vv, the least significant byte, holds the byte value that is to
15722 ;; be tested for membership within the ranges specified by operand
2.
15723 ;; The bytes of operand
2 are organized as hi_1:lo_1:hi_2:lo_2.
15725 ;; Set bit
1 (the GT bit,
0x4) of CR register operand
0 to
1 if
15726 ;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2).
15727 ;; Otherwise, set the GT bit to
0. The other
3 bits of the target
15728 ;; CR register are all set to
0.
15729 (define_insn "*cmprb2_internal"
15730 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
15731 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
15732 (match_operand:SI
2 "gpc_reg_operand" "r")]
15736 [(set_attr "type" "logical")])
15738 ;; Test byte membership within set of
8 bytes.
15740 ;; The bytes of operand
1 are organized as xx:xx:xx:vv, where xx
15741 ;; represents a byte whose value is ignored in this context and
15742 ;; vv, the least significant byte, holds the byte value that is to
15743 ;; be tested for membership within the set specified by operand
2.
15744 ;; The bytes of operand
2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
15746 ;; Return in target register operand
0 a value of
1 if vv equals one
15747 ;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set
15748 ;; register operand
0 to
0. Note that the
8 byte values held within
15749 ;; operand
2 need not be unique.
15751 ;; Though the instructions to which this expansion maps operate on
15752 ;;
64-bit registers, the current implementation requires that operands
15753 ;;
0 and
1 have mode SI as the high-order bits provide no information
15754 ;; that is not already available in the low-order bits. To avoid the
15755 ;; costs of data widening operations, future enhancements might allow
15756 ;; DI mode for operand
0 and/or might allow operand
1 to be QI mode.
15757 (define_expand "cmpeqb"
15758 [(set (match_dup
3)
15759 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
15760 (match_operand:DI
2 "gpc_reg_operand" "r")]
15762 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
15763 (if_then_else:SI (lt (match_dup
3)
15766 (if_then_else (gt (match_dup
3)
15770 "TARGET_P9_MISC && TARGET_64BIT"
15772 operands[
3] = gen_reg_rtx (CCmode);
15775 ;; The bytes of operand
1 are organized as xx:xx:xx:vv, where xx
15776 ;; represents a byte whose value is ignored in this context and
15777 ;; vv, the least significant byte, holds the byte value that is to
15778 ;; be tested for membership within the set specified by operand
2.
15779 ;; The bytes of operand
2 are organized as e0:e1:e2:e3:e4:e5:e6:e7.
15781 ;; Set bit
1 (the GT bit,
0x4) of CR register operand
0 to
1 if vv
15782 ;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise,
15783 ;; set the GT bit to zero. The other
3 bits of the target CR register
15784 ;; are all set to
0.
15785 (define_insn "*cmpeqb_internal"
15786 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
15787 (unspec:CC [(match_operand:SI
1 "gpc_reg_operand" "r")
15788 (match_operand:DI
2 "gpc_reg_operand" "r")]
15790 "TARGET_P9_MISC && TARGET_64BIT"
15792 [(set_attr "type" "logical")])
15795 ;; ROP mitigation instructions.
15797 (define_insn "hashst"
15798 [(set (match_operand:DI
0 "simple_offsettable_mem_operand" "=m")
15799 (unspec_volatile:DI [(match_operand:DI
1 "int_reg_operand" "r")]
15801 "TARGET_POWER10 && rs6000_rop_protect"
15803 static char templ[
32];
15804 const char *p = rs6000_privileged ? "p" : "";
15805 sprintf (templ, "hashst%s %%
1,%%
0", p);
15808 [(set_attr "type" "store")])
15810 (define_insn "hashchk"
15811 [(unspec_volatile [(match_operand:DI
0 "int_reg_operand" "r")
15812 (match_operand:DI
1 "simple_offsettable_mem_operand" "m")]
15814 "TARGET_POWER10 && rs6000_rop_protect"
15816 static char templ[
32];
15817 const char *p = rs6000_privileged ? "p" : "";
15818 sprintf (templ, "hashchk%s %%
0,%%
1", p);
15821 [(set_attr "type" "load")])
15824 (include "sync.md")
15825 (include "vector.md")
15827 (include "altivec.md")
15830 (include "crypto.md")
15832 (include "fusion.md")
15833 (include "pcrel-opt.md")