1 ;; Machine description for IBM RISC System
6000 (POWER) for GNU C compiler
2 ;; Copyright (C)
1990,
91,
92,
93,
94,
95,
1996 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
20 ;; Boston, MA
02111-
1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Define an insn type attribute. This is used in function unit delay
26 (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup
0))
34 (lt (minus (pc) (match_dup
0))
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"
44 (const (symbol_ref "rs6000_cpu_attr")))
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
49 ; Load/Store Unit -- pure PowerPC only
50 ; (POWER and
601 use Integer Unit)
51 (define_function_unit "lsu"
1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
56 (define_function_unit "lsu"
1 0
57 (and (eq_attr "type" "store,fpstore")
58 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
61 (define_function_unit "lsu"
1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc603"))
66 (define_function_unit "lsu"
1 0
67 (and (eq_attr "type" "fpload")
68 (eq_attr "cpu" "ppc604,ppc620"))
71 (define_function_unit "iu"
1 0
72 (and (eq_attr "type" "load")
73 (eq_attr "cpu" "rios1,ppc403,ppc601"))
76 (define_function_unit "iu"
1 0
77 (and (eq_attr "type" "store,fpstore")
78 (eq_attr "cpu" "rios1,ppc403,ppc601"))
81 (define_function_unit "fpu"
1 0
82 (and (eq_attr "type" "fpstore")
83 (eq_attr "cpu" "rios1,ppc601"))
86 (define_function_unit "iu"
1 0
87 (and (eq_attr "type" "fpload")
88 (eq_attr "cpu" "rios1"))
91 (define_function_unit "iu"
1 0
92 (and (eq_attr "type" "fpload")
93 (eq_attr "cpu" "ppc601"))
96 (define_function_unit "iu2"
2 0
97 (and (eq_attr "type" "load,fpload")
98 (eq_attr "cpu" "rios2"))
101 (define_function_unit "iu2"
2 0
102 (and (eq_attr "type" "store,fpstore")
103 (eq_attr "cpu" "rios2"))
106 ; Integer Unit (RIOS1, PPC601, PPC603)
107 (define_function_unit "iu"
1 0
108 (and (eq_attr "type" "integer")
109 (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
112 (define_function_unit "iu"
1 0
113 (and (eq_attr "type" "imul")
114 (eq_attr "cpu" "ppc403"))
117 (define_function_unit "iu"
1 0
118 (and (eq_attr "type" "imul")
119 (eq_attr "cpu" "rios1,ppc601,ppc603"))
122 (define_function_unit "iu"
1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios1"))
127 (define_function_unit "iu"
1 0
128 (and (eq_attr "type" "idiv")
129 (eq_attr "cpu" "ppc403"))
132 (define_function_unit "iu"
1 0
133 (and (eq_attr "type" "idiv")
134 (eq_attr "cpu" "ppc601"))
137 (define_function_unit "iu"
1 0
138 (and (eq_attr "type" "idiv")
139 (eq_attr "cpu" "ppc603"))
142 ; RIOS2 has two integer units: a primary one which can perform all
143 ; operations and a secondary one which is fed in lock step with the first
144 ; and can perform "simple" integer operations.
145 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
146 ; for the complex insns.
147 (define_function_unit "iu2"
2 0
148 (and (eq_attr "type" "integer")
149 (eq_attr "cpu" "rios2"))
152 (define_function_unit "iu2"
2 0
153 (and (eq_attr "type" "imul")
154 (eq_attr "cpu" "rios2"))
157 (define_function_unit "iu2"
2 0
158 (and (eq_attr "type" "idiv")
159 (eq_attr "cpu" "rios2"))
162 (define_function_unit "imuldiv"
1 0
163 (and (eq_attr "type" "imul")
164 (eq_attr "cpu" "rios2"))
167 (define_function_unit "imuldiv"
1 0
168 (and (eq_attr "type" "idiv")
169 (eq_attr "cpu" "rios2"))
172 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
173 ; Divide latency varies greatly from
2-
11, use
6 as average
174 (define_function_unit "imuldiv"
1 0
175 (and (eq_attr "type" "imul")
176 (eq_attr "cpu" "mpccore"))
179 (define_function_unit "imuldiv"
1 0
180 (and (eq_attr "type" "idiv")
181 (eq_attr "cpu" "mpccore"))
184 ; PPC604 has two units that perform integer operations
185 ; and one unit for divide/multiply operations (and move
187 (define_function_unit "iu2"
2 0
188 (and (eq_attr "type" "integer")
189 (eq_attr "cpu" "ppc604,ppc620"))
192 (define_function_unit "imuldiv"
1 0
193 (and (eq_attr "type" "imul")
194 (eq_attr "cpu" "ppc604,ppc620"))
197 (define_function_unit "imuldiv"
1 0
198 (and (eq_attr "type" "idiv")
199 (eq_attr "cpu" "ppc604,ppc620"))
202 ; compare is done on integer unit, but feeds insns which
203 ; execute on the branch unit.
204 (define_function_unit "iu"
1 0
205 (and (eq_attr "type" "compare")
206 (eq_attr "cpu" "rios1"))
209 (define_function_unit "iu"
1 0
210 (and (eq_attr "type" "delayed_compare")
211 (eq_attr "cpu" "rios1"))
214 (define_function_unit "iu"
1 0
215 (and (eq_attr "type" "compare,delayed_compare")
216 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
219 (define_function_unit "iu2"
2 0
220 (and (eq_attr "type" "compare,delayed_compare")
221 (eq_attr "cpu" "rios2"))
224 (define_function_unit "iu2"
2 0
225 (and (eq_attr "type" "compare,delayed_compare")
226 (eq_attr "cpu" "ppc604,ppc620"))
229 ; fp compare uses fp unit
230 (define_function_unit "fpu"
1 0
231 (and (eq_attr "type" "fpcompare")
232 (eq_attr "cpu" "rios1"))
235 ; rios1 and rios2 have different fpcompare delays
236 (define_function_unit "fpu2"
2 0
237 (and (eq_attr "type" "fpcompare")
238 (eq_attr "cpu" "rios2"))
241 ; on ppc601 and ppc603, fpcompare takes also
2 cycles from
243 ; here we do not define delays, just occupy the unit. The dependencies
244 ; will be assigned by the fpcompare definition in the fpu.
245 (define_function_unit "iu"
1 0
246 (and (eq_attr "type" "fpcompare")
247 (eq_attr "cpu" "ppc601,ppc603"))
250 ; fp compare uses fp unit
251 (define_function_unit "fpu"
1 0
252 (and (eq_attr "type" "fpcompare")
253 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
256 (define_function_unit "fpu"
1 0
257 (and (eq_attr "type" "fpcompare")
258 (eq_attr "cpu" "mpccore"))
261 (define_function_unit "bpu"
1 0
262 (and (eq_attr "type" "mtjmpr")
263 (eq_attr "cpu" "rios1,rios2"))
266 (define_function_unit "bpu"
1 0
267 (and (eq_attr "type" "mtjmpr")
268 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
271 ; all jumps/branches are executing on the bpu, in
1 cycle, for all machines.
272 (define_function_unit "bpu"
1 0
273 (eq_attr "type" "jmpreg")
276 (define_function_unit "bpu"
1 0
277 (eq_attr "type" "branch")
280 ; Floating Point Unit
281 (define_function_unit "fpu"
1 0
282 (and (eq_attr "type" "fp,dmul")
283 (eq_attr "cpu" "rios1"))
286 (define_function_unit "fpu"
1 0
287 (and (eq_attr "type" "fp")
288 (eq_attr "cpu" "mpccore"))
291 (define_function_unit "fpu"
1 0
292 (and (eq_attr "type" "fp")
293 (eq_attr "cpu" "ppc601"))
296 (define_function_unit "fpu"
1 0
297 (and (eq_attr "type" "fp")
298 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
301 (define_function_unit "fpu"
1 0
302 (and (eq_attr "type" "dmul")
303 (eq_attr "cpu" "mpccore"))
306 (define_function_unit "fpu"
1 0
307 (and (eq_attr "type" "dmul")
308 (eq_attr "cpu" "ppc601"))
312 (define_function_unit "fpu"
1 0
313 (and (eq_attr "type" "dmul")
314 (eq_attr "cpu" "ppc603"))
317 (define_function_unit "fpu"
1 0
318 (and (eq_attr "type" "dmul")
319 (eq_attr "cpu" "ppc604,ppc620"))
322 (define_function_unit "fpu"
1 0
323 (and (eq_attr "type" "sdiv,ddiv")
324 (eq_attr "cpu" "rios1"))
327 (define_function_unit "fpu"
1 0
328 (and (eq_attr "type" "sdiv")
329 (eq_attr "cpu" "ppc601"))
332 (define_function_unit "fpu"
1 0
333 (and (eq_attr "type" "sdiv")
334 (eq_attr "cpu" "mpccore"))
337 (define_function_unit "fpu"
1 0
338 (and (eq_attr "type" "sdiv")
339 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
342 (define_function_unit "fpu"
1 0
343 (and (eq_attr "type" "ddiv")
344 (eq_attr "cpu" "mpccore"))
347 (define_function_unit "fpu"
1 0
348 (and (eq_attr "type" "ddiv")
349 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
352 (define_function_unit "fpu"
1 0
353 (and (eq_attr "type" "ddiv")
354 (eq_attr "cpu" "ppc603"))
357 (define_function_unit "fpu"
1 0
358 (and (eq_attr "type" "ssqrt")
359 (eq_attr "cpu" "ppc620"))
362 (define_function_unit "fpu"
1 0
363 (and (eq_attr "type" "dsqrt")
364 (eq_attr "cpu" "ppc620"))
367 ; RIOS2 has two symmetric FPUs.
368 (define_function_unit "fpu2"
2 0
369 (and (eq_attr "type" "fp")
370 (eq_attr "cpu" "rios2"))
373 (define_function_unit "fpu2"
2 0
374 (and (eq_attr "type" "dmul")
375 (eq_attr "cpu" "rios2"))
378 (define_function_unit "fpu2"
2 0
379 (and (eq_attr "type" "sdiv,ddiv")
380 (eq_attr "cpu" "rios2"))
383 (define_function_unit "fpu2"
2 0
384 (and (eq_attr "type" "ssqrt,dsqrt")
385 (eq_attr "cpu" "rios2"))
389 ;; Start with fixed-point load and store insns. Here we put only the more
390 ;; complex forms. Basic data transfer is done later.
392 (define_expand "zero_extendqidi2"
393 [(set (match_operand:DI
0 "gpc_reg_operand" "")
394 (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "")))]
399 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
400 (zero_extend:DI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
405 [(set_attr "type" "load,*")])
408 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
409 (compare:CC (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
411 (clobber (match_scratch:DI
2 "=r"))]
414 [(set_attr "type" "compare")])
417 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
418 (compare:CC (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
420 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
421 (zero_extend:DI (match_dup
1)))]
424 [(set_attr "type" "compare")])
426 (define_insn "extendqidi2"
427 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
428 (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r")))]
433 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
434 (compare:CC (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
436 (clobber (match_scratch:DI
2 "=r"))]
439 [(set_attr "type" "compare")])
442 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
443 (compare:CC (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
445 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
446 (sign_extend:DI (match_dup
1)))]
449 [(set_attr "type" "compare")])
451 (define_expand "zero_extendhidi2"
452 [(set (match_operand:DI
0 "gpc_reg_operand" "")
453 (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "")))]
458 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
459 (zero_extend:DI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
464 [(set_attr "type" "load,*")])
467 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
468 (compare:CC (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
470 (clobber (match_scratch:DI
2 "=r"))]
473 [(set_attr "type" "compare")])
476 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
477 (compare:CC (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
479 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
480 (zero_extend:DI (match_dup
1)))]
483 [(set_attr "type" "compare")])
485 (define_expand "extendhidi2"
486 [(set (match_operand:DI
0 "gpc_reg_operand" "")
487 (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "")))]
492 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
498 [(set_attr "type" "load,*")])
501 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
502 (compare:CC (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
504 (clobber (match_scratch:DI
2 "=r"))]
507 [(set_attr "type" "compare")])
510 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
511 (compare:CC (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
513 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
514 (sign_extend:DI (match_dup
1)))]
517 [(set_attr "type" "compare")])
519 (define_expand "zero_extendsidi2"
520 [(set (match_operand:DI
0 "gpc_reg_operand" "")
521 (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "")))]
526 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
527 (zero_extend:DI (match_operand:SI
1 "reg_or_mem_operand" "m,r")))]
532 [(set_attr "type" "load,*")])
535 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
536 (compare:CC (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
538 (clobber (match_scratch:DI
2 "=r"))]
541 [(set_attr "type" "compare")])
544 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
545 (compare:CC (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
547 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
548 (zero_extend:DI (match_dup
1)))]
551 [(set_attr "type" "compare")])
553 (define_expand "extendsidi2"
554 [(set (match_operand:DI
0 "gpc_reg_operand" "")
555 (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "")))]
560 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
561 (sign_extend:DI (match_operand:SI
1 "lwa_operand" "m,r")))]
566 [(set_attr "type" "load,*")])
569 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
570 (compare:CC (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
572 (clobber (match_scratch:DI
2 "=r"))]
575 [(set_attr "type" "compare")])
578 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
579 (compare:CC (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
581 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
582 (sign_extend:DI (match_dup
1)))]
585 [(set_attr "type" "compare")])
587 (define_expand "zero_extendqisi2"
588 [(set (match_operand:SI
0 "gpc_reg_operand" "")
589 (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "")))]
594 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
595 (zero_extend:SI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
599 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
600 [(set_attr "type" "load,*")])
603 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
604 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
606 (clobber (match_scratch:SI
2 "=r"))]
608 "{andil.|andi.} %
2,%
1,
0xff"
609 [(set_attr "type" "compare")])
612 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
613 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
615 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
616 (zero_extend:SI (match_dup
1)))]
618 "{andil.|andi.} %
0,%
1,
0xff"
619 [(set_attr "type" "compare")])
621 (define_expand "extendqisi2"
622 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
623 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
628 emit_insn (gen_extendqisi2_ppc (operands[
0], operands[
1]));
629 else if (TARGET_POWER)
630 emit_insn (gen_extendqisi2_power (operands[
0], operands[
1]));
632 emit_insn (gen_extendqisi2_no_power (operands[
0], operands[
1]));
636 (define_insn "extendqisi2_ppc"
637 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
638 (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r")))]
643 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
644 (compare:CC (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
646 (clobber (match_scratch:SI
2 "=r"))]
649 [(set_attr "type" "compare")])
652 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
653 (compare:CC (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
655 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
656 (sign_extend:SI (match_dup
1)))]
659 [(set_attr "type" "compare")])
661 (define_expand "extendqisi2_power"
662 [(parallel [(set (match_dup
2)
663 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
665 (clobber (scratch:SI))])
666 (parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
667 (ashiftrt:SI (match_dup
2)
669 (clobber (scratch:SI))])]
672 { operands[
1] = gen_lowpart (SImode, operands[
1]);
673 operands[
2] = gen_reg_rtx (SImode); }")
675 (define_expand "extendqisi2_no_power"
677 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
679 (set (match_operand:SI
0 "gpc_reg_operand" "")
680 (ashiftrt:SI (match_dup
2)
682 "! TARGET_POWER && ! TARGET_POWERPC"
684 { operands[
1] = gen_lowpart (SImode, operands[
1]);
685 operands[
2] = gen_reg_rtx (SImode); }")
687 (define_expand "zero_extendqihi2"
688 [(set (match_operand:HI
0 "gpc_reg_operand" "")
689 (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "")))]
694 [(set (match_operand:HI
0 "gpc_reg_operand" "=r,r")
695 (zero_extend:HI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
699 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
700 [(set_attr "type" "load,*")])
703 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
704 (compare:CC (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
706 (clobber (match_scratch:HI
2 "=r"))]
708 "{andil.|andi.} %
2,%
1,
0xff"
709 [(set_attr "type" "compare")])
712 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
713 (compare:CC (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
715 (set (match_operand:HI
0 "gpc_reg_operand" "=r")
716 (zero_extend:HI (match_dup
1)))]
718 "{andil.|andi.} %
0,%
1,
0xff"
719 [(set_attr "type" "compare")])
721 (define_expand "extendqihi2"
722 [(use (match_operand:HI
0 "gpc_reg_operand" ""))
723 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
728 emit_insn (gen_extendqihi2_ppc (operands[
0], operands[
1]));
729 else if (TARGET_POWER)
730 emit_insn (gen_extendqihi2_power (operands[
0], operands[
1]));
732 emit_insn (gen_extendqihi2_no_power (operands[
0], operands[
1]));
736 (define_insn "extendqihi2_ppc"
737 [(set (match_operand:HI
0 "gpc_reg_operand" "=r")
738 (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r")))]
743 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
744 (compare:CC (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
746 (clobber (match_scratch:HI
2 "=r"))]
749 [(set_attr "type" "compare")])
752 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
753 (compare:CC (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
755 (set (match_operand:HI
0 "gpc_reg_operand" "=r")
756 (sign_extend:HI (match_dup
1)))]
759 [(set_attr "type" "compare")])
761 (define_expand "extendqihi2_power"
762 [(parallel [(set (match_dup
2)
763 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
765 (clobber (scratch:SI))])
766 (parallel [(set (match_operand:HI
0 "gpc_reg_operand" "")
767 (ashiftrt:SI (match_dup
2)
769 (clobber (scratch:SI))])]
772 { operands[
0] = gen_lowpart (SImode, operands[
0]);
773 operands[
1] = gen_lowpart (SImode, operands[
1]);
774 operands[
2] = gen_reg_rtx (SImode); }")
776 (define_expand "extendqihi2_no_power"
778 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
780 (set (match_operand:HI
0 "gpc_reg_operand" "")
781 (ashiftrt:SI (match_dup
2)
783 "! TARGET_POWER && ! TARGET_POWERPC"
785 { operands[
0] = gen_lowpart (SImode, operands[
0]);
786 operands[
1] = gen_lowpart (SImode, operands[
1]);
787 operands[
2] = gen_reg_rtx (SImode); }")
789 (define_expand "zero_extendhisi2"
790 [(set (match_operand:SI
0 "gpc_reg_operand" "")
791 (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
796 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
797 (zero_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
801 {rlinm|rlwinm} %
0,%
1,
0,
0xffff"
802 [(set_attr "type" "load,*")])
805 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
806 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
808 (clobber (match_scratch:SI
2 "=r"))]
810 "{andil.|andi.} %
2,%
1,
0xffff"
811 [(set_attr "type" "compare")])
814 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
815 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
817 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
818 (zero_extend:SI (match_dup
1)))]
820 "{andil.|andi.} %
0,%
1,
0xffff"
821 [(set_attr "type" "compare")])
823 (define_expand "extendhisi2"
824 [(set (match_operand:SI
0 "gpc_reg_operand" "")
825 (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
830 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
831 (sign_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
836 [(set_attr "type" "load,*")])
839 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
840 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
842 (clobber (match_scratch:SI
2 "=r"))]
844 "{exts.|extsh.} %
2,%
1"
845 [(set_attr "type" "compare")])
848 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
849 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
851 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
852 (sign_extend:SI (match_dup
1)))]
854 "{exts.|extsh.} %
0,%
1"
855 [(set_attr "type" "compare")])
857 ;; Fixed-point arithmetic insns.
859 ;; Discourage ai/addic because of carry but provide it in an alternative
860 ;; allowing register zero as source.
861 (define_insn "addsi3"
862 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,?r,r")
863 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,b,r,b")
864 (match_operand:SI
2 "add_operand" "r,I,I,J")))]
868 {cal %
0,%
2(%
1)|addi %
0,%
1,%
2}
870 {cau|addis} %
0,%
1,%v2")
873 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
874 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
875 (match_operand:SI
2 "reg_or_short_operand" "r,I"))
877 (clobber (match_scratch:SI
3 "=r,r"))]
881 {ai.|addic.} %
3,%
1,%
2"
882 [(set_attr "type" "compare")])
885 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
886 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
887 (match_operand:SI
2 "reg_or_short_operand" "r,I"))
889 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
890 (plus:SI (match_dup
1) (match_dup
2)))]
894 {ai.|addic.} %
0,%
1,%
2"
895 [(set_attr "type" "compare")])
897 ;; Split an add that we can't do in one insn into two insns, each of which
898 ;; does one
16-bit part. This is used by combine. Note that the low-order
899 ;; add should be last in case the result gets used in an address.
902 [(set (match_operand:SI
0 "gpc_reg_operand" "")
903 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "")
904 (match_operand:SI
2 "non_add_cint_operand" "")))]
906 [(set (match_dup
0) (plus:SI (match_dup
1) (match_dup
3)))
907 (set (match_dup
0) (plus:SI (match_dup
0) (match_dup
4)))]
910 HOST_WIDE_INT low = INTVAL (operands[
2]) &
0xffff;
911 HOST_WIDE_INT high = INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff);
914 high +=
0x10000, low |= ((HOST_WIDE_INT) -
1) <<
16;
916 operands[
3] = GEN_INT (high);
917 operands[
4] = GEN_INT (low);
920 (define_insn "one_cmplsi2"
921 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
922 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
927 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
928 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
930 (clobber (match_scratch:SI
2 "=r"))]
933 [(set_attr "type" "compare")])
936 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
937 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
939 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
940 (not:SI (match_dup
1)))]
943 [(set_attr "type" "compare")])
946 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
947 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "rI")
948 (match_operand:SI
2 "gpc_reg_operand" "r")))]
950 "{sf%I1|subf%I1c} %
0,%
2,%
1")
953 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
954 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "r,I")
955 (match_operand:SI
2 "gpc_reg_operand" "r,r")))]
962 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
963 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
964 (match_operand:SI
2 "gpc_reg_operand" "r"))
966 (clobber (match_scratch:SI
3 "=r"))]
968 "{sf.|subfc.} %
3,%
2,%
1"
969 [(set_attr "type" "compare")])
972 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
973 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
974 (match_operand:SI
2 "gpc_reg_operand" "r"))
976 (clobber (match_scratch:SI
3 "=r"))]
979 [(set_attr "type" "compare")])
982 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
983 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
984 (match_operand:SI
2 "gpc_reg_operand" "r"))
986 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
987 (minus:SI (match_dup
1) (match_dup
2)))]
989 "{sf.|subfc.} %
0,%
2,%
1"
990 [(set_attr "type" "compare")])
993 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
994 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
995 (match_operand:SI
2 "gpc_reg_operand" "r"))
997 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
998 (minus:SI (match_dup
1) (match_dup
2)))]
1001 [(set_attr "type" "compare")])
1003 (define_expand "subsi3"
1004 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1005 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "")
1006 (match_operand:SI
2 "reg_or_cint_operand" "")))]
1010 if (GET_CODE (operands[
2]) == CONST_INT)
1012 emit_insn (gen_addsi3 (operands[
0], operands[
1],
1013 negate_rtx (SImode, operands[
2])));
1018 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1019 ;; instruction and some auxiliary computations. Then we just have a single
1020 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1023 (define_expand "sminsi3"
1025 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
1026 (match_operand:SI
2 "reg_or_short_operand" ""))
1028 (minus:SI (match_dup
2) (match_dup
1))))
1029 (set (match_operand:SI
0 "gpc_reg_operand" "")
1030 (minus:SI (match_dup
2) (match_dup
3)))]
1033 { operands[
3] = gen_reg_rtx (SImode); }")
1036 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1037 (smin:SI (match_operand:SI
1 "gpc_reg_operand" "")
1038 (match_operand:SI
2 "reg_or_short_operand" "")))
1039 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
1042 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
1044 (minus:SI (match_dup
2) (match_dup
1))))
1045 (set (match_dup
0) (minus:SI (match_dup
2) (match_dup
3)))]
1048 (define_expand "smaxsi3"
1050 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
1051 (match_operand:SI
2 "reg_or_short_operand" ""))
1053 (minus:SI (match_dup
2) (match_dup
1))))
1054 (set (match_operand:SI
0 "gpc_reg_operand" "")
1055 (plus:SI (match_dup
3) (match_dup
1)))]
1058 { operands[
3] = gen_reg_rtx (SImode); }")
1061 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1062 (smax:SI (match_operand:SI
1 "gpc_reg_operand" "")
1063 (match_operand:SI
2 "reg_or_short_operand" "")))
1064 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
1067 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
1069 (minus:SI (match_dup
2) (match_dup
1))))
1070 (set (match_dup
0) (plus:SI (match_dup
3) (match_dup
1)))]
1073 (define_expand "uminsi3"
1074 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1076 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
1078 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
1080 (minus:SI (match_dup
4) (match_dup
3))))
1081 (set (match_operand:SI
0 "gpc_reg_operand" "")
1082 (minus:SI (match_dup
2) (match_dup
3)))]
1086 operands[
3] = gen_reg_rtx (SImode);
1087 operands[
4] = gen_reg_rtx (SImode);
1088 operands[
5] = GEN_INT (-
2147483647 -
1);
1091 (define_expand "umaxsi3"
1092 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1094 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
1096 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
1098 (minus:SI (match_dup
4) (match_dup
3))))
1099 (set (match_operand:SI
0 "gpc_reg_operand" "")
1100 (plus:SI (match_dup
3) (match_dup
1)))]
1104 operands[
3] = gen_reg_rtx (SImode);
1105 operands[
4] = gen_reg_rtx (SImode);
1106 operands[
5] = GEN_INT (-
2147483647 -
1);
1110 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1111 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1112 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1114 (minus:SI (match_dup
2) (match_dup
1))))]
1119 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1121 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1122 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1124 (minus:SI (match_dup
2) (match_dup
1)))
1126 (clobber (match_scratch:SI
3 "=r"))]
1129 [(set_attr "type" "delayed_compare")])
1132 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1134 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1135 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1137 (minus:SI (match_dup
2) (match_dup
1)))
1139 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1140 (if_then_else:SI (gt (match_dup
1) (match_dup
2))
1142 (minus:SI (match_dup
2) (match_dup
1))))]
1145 [(set_attr "type" "delayed_compare")])
1147 ;; We don't need abs with condition code because such comparisons should
1149 (define_expand "abssi2"
1150 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1151 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "")))]
1157 emit_insn (gen_abssi2_nopower (operands[
0], operands[
1]));
1162 (define_insn "abssi2_power"
1163 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1164 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1168 (define_insn "abssi2_nopower"
1169 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1170 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0")))
1171 (clobber (match_scratch:SI
2 "=&r,&r"))]
1175 return (TARGET_POWERPC)
1176 ?
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
2,%
0\"
1177 :
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;{sf|subfc} %
0,%
2,%
0\";
1179 [(set_attr "length" "
12")])
1182 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1183 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0")))
1184 (clobber (match_scratch:SI
2 "=&r,&r"))]
1185 "!TARGET_POWER && reload_completed"
1186 [(set (match_dup
2) (ashiftrt:SI (match_dup
1) (const_int
31)))
1187 (set (match_dup
0) (xor:SI (match_dup
2) (match_dup
1)))
1188 (set (match_dup
0) (minus:SI (match_dup
0) (match_dup
2)))]
1192 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1193 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r"))))]
1198 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1199 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0"))))
1200 (clobber (match_scratch:SI
2 "=&r,&r"))]
1204 return (TARGET_POWERPC)
1205 ?
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
0,%
2\"
1206 :
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;{sf|subfc} %
0,%
0,%
2\";
1208 [(set_attr "length" "
12")])
1211 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1212 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0"))))
1213 (clobber (match_scratch:SI
2 "=&r,&r"))]
1214 "!TARGET_POWER && reload_completed"
1215 [(set (match_dup
2) (ashiftrt:SI (match_dup
1) (const_int
31)))
1216 (set (match_dup
0) (xor:SI (match_dup
2) (match_dup
1)))
1217 (set (match_dup
0) (minus:SI (match_dup
2) (match_dup
0)))]
1220 (define_insn "negsi2"
1221 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1222 (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1227 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1228 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1230 (clobber (match_scratch:SI
2 "=r"))]
1233 [(set_attr "type" "compare")])
1236 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
1237 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1239 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1240 (neg:SI (match_dup
1)))]
1243 [(set_attr "type" "compare")])
1245 (define_insn "ffssi2"
1246 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r")
1247 (ffs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1249 "neg %
0,%
1\;and %
0,%
0,%
1\;{cntlz|cntlzw} %
0,%
0\;{sfi|subfic} %
0,%
0,
32"
1250 [(set_attr "length" "
16")])
1252 (define_expand "mulsi3"
1253 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1254 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1255 (use (match_operand:SI
2 "reg_or_short_operand" ""))]
1260 emit_insn (gen_mulsi3_mq (operands[
0], operands[
1], operands[
2]));
1262 emit_insn (gen_mulsi3_no_mq (operands[
0], operands[
1], operands[
2]));
1266 (define_insn "mulsi3_mq"
1267 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1268 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
1269 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
1270 (clobber (match_scratch:SI
3 "=q,q"))]
1273 {muls|mullw} %
0,%
1,%
2
1274 {muli|mulli} %
0,%
1,%
2"
1275 [(set_attr "type" "imul")])
1277 (define_insn "mulsi3_no_mq"
1278 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1279 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
1280 (match_operand:SI
2 "reg_or_short_operand" "r,I")))]
1283 {muls|mullw} %
0,%
1,%
2
1284 {muli|mulli} %
0,%
1,%
2"
1285 [(set_attr "type" "imul")])
1288 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1289 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1290 (match_operand:SI
2 "gpc_reg_operand" "r"))
1292 (clobber (match_scratch:SI
3 "=r"))
1293 (clobber (match_scratch:SI
4 "=q"))]
1295 "{muls.|mullw.} %
3,%
1,%
2"
1296 [(set_attr "type" "delayed_compare")])
1299 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1300 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1301 (match_operand:SI
2 "gpc_reg_operand" "r"))
1303 (clobber (match_scratch:SI
3 "=r"))]
1305 "{muls.|mullw.} %
3,%
1,%
2"
1306 [(set_attr "type" "delayed_compare")])
1309 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1310 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1311 (match_operand:SI
2 "gpc_reg_operand" "r"))
1313 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1314 (mult:SI (match_dup
1) (match_dup
2)))
1315 (clobber (match_scratch:SI
4 "=q"))]
1317 "{muls.|mullw.} %
0,%
1,%
2"
1318 [(set_attr "type" "delayed_compare")])
1321 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1322 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1323 (match_operand:SI
2 "gpc_reg_operand" "r"))
1325 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1326 (mult:SI (match_dup
1) (match_dup
2)))]
1328 "{muls.|mullw.} %
0,%
1,%
2"
1329 [(set_attr "type" "delayed_compare")])
1331 ;; Operand
1 is divided by operand
2; quotient goes to operand
1332 ;;
0 and remainder to operand
3.
1333 ;; ??? At some point, see what, if anything, we can do about if (x % y ==
0).
1335 (define_expand "divmodsi4"
1336 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
1337 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
1338 (match_operand:SI
2 "gpc_reg_operand" "")))
1339 (set (match_operand:SI
3 "gpc_reg_operand" "")
1340 (mod:SI (match_dup
1) (match_dup
2)))])]
1341 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1344 if (! TARGET_POWER && ! TARGET_POWERPC)
1346 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1347 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1348 emit_insn (gen_divss_call ());
1349 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1350 emit_move_insn (operands[
3], gen_rtx (REG, SImode,
4));
1356 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1357 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1358 (match_operand:SI
2 "gpc_reg_operand" "r")))
1359 (set (match_operand:SI
3 "gpc_reg_operand" "=q")
1360 (mod:SI (match_dup
1) (match_dup
2)))]
1363 [(set_attr "type" "idiv")])
1366 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1367 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1368 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1371 [(set_attr "type" "idiv")])
1373 (define_expand "udivsi3"
1374 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1375 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "")
1376 (match_operand:SI
2 "gpc_reg_operand" "")))]
1377 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1380 if (! TARGET_POWER && ! TARGET_POWERPC)
1382 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1383 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1384 emit_insn (gen_quous_call ());
1385 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1391 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1392 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1393 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1396 [(set_attr "type" "idiv")])
1398 ;; For powers of two we can do srai/aze for divide and then adjust for
1399 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1400 ;; used; for PowerPC, force operands into register and do a normal divide;
1401 ;; for AIX common-mode, use quoss call on register operands.
1402 (define_expand "divsi3"
1403 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1404 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
1405 (match_operand:SI
2 "reg_or_cint_operand" "")))]
1409 if (GET_CODE (operands[
2]) == CONST_INT
1410 && exact_log2 (INTVAL (operands[
2])) >=
0)
1412 else if (TARGET_POWERPC)
1413 operands[
2] = force_reg (SImode, operands[
2]);
1414 else if (TARGET_POWER)
1418 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1419 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1420 emit_insn (gen_quoss_call ());
1421 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1426 (define_expand "modsi3"
1427 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1428 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1429 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
1433 int i = exact_log2 (INTVAL (operands[
2]));
1437 if (GET_CODE (operands[
2]) != CONST_INT || i <
0)
1440 temp1 = gen_reg_rtx (SImode);
1441 temp2 = gen_reg_rtx (SImode);
1443 emit_insn (gen_divsi3 (temp1, operands[
1], operands[
2]));
1444 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1445 emit_insn (gen_subsi3 (operands[
0], operands[
1], temp2));
1450 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1451 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1452 (match_operand:SI
2 "const_int_operand" "N")))]
1453 "exact_log2 (INTVAL (operands[
2])) >=
0"
1454 "{srai|srawi} %
0,%
1,%p2\;{aze|addze} %
0,%
0"
1455 [(set_attr "length" "
8")])
1458 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1459 (compare:CC (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1460 (match_operand:SI
2 "const_int_operand" "N"))
1462 (clobber (match_scratch:SI
3 "=r"))]
1463 "exact_log2 (INTVAL (operands[
2])) >=
0"
1464 "{srai|srawi} %
3,%
1,%p2\;{aze.|addze.} %
3,%
3"
1465 [(set_attr "type" "compare")
1466 (set_attr "length" "
8")])
1469 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1470 (compare:CC (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1471 (match_operand:SI
2 "const_int_operand" "N"))
1473 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1474 (div:SI (match_dup
1) (match_dup
2)))]
1475 "exact_log2 (INTVAL (operands[
2])) >=
0"
1476 "{srai|srawi} %
0,%
1,%p2\;{aze.|addze.} %
0,%
0"
1477 [(set_attr "type" "compare")
1478 (set_attr "length" "
8")])
1481 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1484 (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
1486 (zero_extend:DI (match_operand:SI
4 "register_operand" "
2")))
1487 (match_operand:SI
3 "gpc_reg_operand" "r")))
1488 (set (match_operand:SI
2 "register_operand" "=*q")
1491 (zero_extend:DI (match_dup
1)) (const_int
32))
1492 (zero_extend:DI (match_dup
4)))
1496 [(set_attr "type" "idiv")])
1498 ;; To do unsigned divide we handle the cases of the divisor looking like a
1499 ;; negative number. If it is a constant that is less than
2**
31, we don't
1500 ;; have to worry about the branches. So make a few subroutines here.
1502 ;; First comes the normal case.
1503 (define_expand "udivmodsi4_normal"
1504 [(set (match_dup
4) (const_int
0))
1505 (parallel [(set (match_operand:SI
0 "" "")
1506 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup
4))
1508 (zero_extend:DI (match_operand:SI
1 "" "")))
1509 (match_operand:SI
2 "" "")))
1510 (set (match_operand:SI
3 "" "")
1511 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup
4))
1513 (zero_extend:DI (match_dup
1)))
1517 { operands[
4] = gen_reg_rtx (SImode); }")
1519 ;; This handles the branches.
1520 (define_expand "udivmodsi4_tests"
1521 [(set (match_operand:SI
0 "" "") (const_int
0))
1522 (set (match_operand:SI
3 "" "") (match_operand:SI
1 "" ""))
1523 (set (match_dup
5) (compare:CCUNS (match_dup
1) (match_operand:SI
2 "" "")))
1524 (set (pc) (if_then_else (ltu (match_dup
5) (const_int
0))
1525 (label_ref (match_operand:SI
4 "" "")) (pc)))
1526 (set (match_dup
0) (const_int
1))
1527 (set (match_dup
3) (minus:SI (match_dup
1) (match_dup
2)))
1528 (set (match_dup
6) (compare:CC (match_dup
2) (const_int
0)))
1529 (set (pc) (if_then_else (lt (match_dup
6) (const_int
0))
1530 (label_ref (match_dup
4)) (pc)))]
1533 { operands[
5] = gen_reg_rtx (CCUNSmode);
1534 operands[
6] = gen_reg_rtx (CCmode);
1537 (define_expand "udivmodsi4"
1538 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
1539 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "")
1540 (match_operand:SI
2 "reg_or_cint_operand" "")))
1541 (set (match_operand:SI
3 "gpc_reg_operand" "")
1542 (umod:SI (match_dup
1) (match_dup
2)))])]
1549 if (! TARGET_POWERPC)
1551 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1552 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1553 emit_insn (gen_divus_call ());
1554 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1555 emit_move_insn (operands[
3], gen_rtx (REG, SImode,
4));
1561 if (GET_CODE (operands[
2]) != CONST_INT || INTVAL (operands[
2]) <
0)
1563 operands[
2] = force_reg (SImode, operands[
2]);
1564 label = gen_label_rtx ();
1565 emit (gen_udivmodsi4_tests (operands[
0], operands[
1], operands[
2],
1566 operands[
3], label));
1569 operands[
2] = force_reg (SImode, operands[
2]);
1571 emit (gen_udivmodsi4_normal (operands[
0], operands[
1], operands[
2],
1579 ;; AIX architecture-independent common-mode multiply (DImode),
1580 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1581 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1582 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1583 ;; assumed unused if generating common-mode, so ignore.
1584 (define_insn "mulh_call"
1587 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI
3))
1588 (sign_extend:DI (reg:SI
4)))
1590 (clobber (match_scratch:SI
0 "=l"))]
1591 "! TARGET_POWER && ! TARGET_POWERPC"
1593 [(set_attr "type" "imul")])
1595 (define_insn "mull_call"
1597 (mult:DI (sign_extend:DI (reg:SI
3))
1598 (sign_extend:DI (reg:SI
4))))
1599 (clobber (match_scratch:SI
0 "=l"))
1600 (clobber (reg:SI
0))]
1601 "! TARGET_POWER && ! TARGET_POWERPC"
1603 [(set_attr "type" "imul")])
1605 (define_insn "divss_call"
1607 (div:SI (reg:SI
3) (reg:SI
4)))
1609 (mod:SI (reg:SI
3) (reg:SI
4)))
1610 (clobber (match_scratch:SI
0 "=l"))
1611 (clobber (reg:SI
0))]
1612 "! TARGET_POWER && ! TARGET_POWERPC"
1614 [(set_attr "type" "idiv")])
1616 (define_insn "divus_call"
1618 (udiv:SI (reg:SI
3) (reg:SI
4)))
1620 (umod:SI (reg:SI
3) (reg:SI
4)))
1621 (clobber (match_scratch:SI
0 "=l"))
1622 (clobber (reg:SI
0))
1623 (clobber (match_scratch:CC
1 "=x"))
1624 (clobber (reg:CC
69))]
1625 "! TARGET_POWER && ! TARGET_POWERPC"
1627 [(set_attr "type" "idiv")])
1629 (define_insn "quoss_call"
1631 (div:SI (reg:SI
3) (reg:SI
4)))
1632 (clobber (match_scratch:SI
0 "=l"))]
1633 "! TARGET_POWER && ! TARGET_POWERPC"
1635 [(set_attr "type" "idiv")])
1637 (define_insn "quous_call"
1639 (udiv:SI (reg:SI
3) (reg:SI
4)))
1640 (clobber (match_scratch:SI
0 "=l"))
1641 (clobber (reg:SI
0))
1642 (clobber (match_scratch:CC
1 "=x"))
1643 (clobber (reg:CC
69))]
1644 "! TARGET_POWER && ! TARGET_POWERPC"
1646 [(set_attr "type" "idiv")])
1648 (define_insn "andsi3"
1649 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
1650 (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1651 (match_operand:SI
2 "and_operand" "?r,L,K,J")))
1652 (clobber (match_scratch:CC
3 "=X,X,x,x"))]
1656 {rlinm|rlwinm} %
0,%
1,
0,%m2,%M2
1657 {andil.|andi.} %
0,%
1,%b2
1658 {andiu.|andis.} %
0,%
1,%u2")
1661 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x")
1662 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1663 (match_operand:SI
2 "and_operand" "r,K,J,L"))
1665 (clobber (match_scratch:SI
3 "=r,r,r,r"))]
1669 {andil.|andi.} %
3,%
1,%b2
1670 {andiu.|andis.} %
3,%
1,%u2
1671 {rlinm.|rlwinm.} %
3,%
1,
0,%m2,%M2"
1672 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1675 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x,x")
1676 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1677 (match_operand:SI
2 "and_operand" "r,K,J,L"))
1679 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
1680 (and:SI (match_dup
1) (match_dup
2)))]
1684 {andil.|andi.} %
0,%
1,%b2
1685 {andiu.|andis.} %
0,%
1,%u2
1686 {rlinm.|rlwinm.} %
0,%
1,
0,%m2,%M2"
1687 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1689 ;; Take a AND with a constant that cannot be done in a single insn and try to
1690 ;; split it into two insns. This does not verify that the insns are valid
1691 ;; since this need not be done as combine will do it.
1694 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1695 (and:SI (match_operand:SI
1 "gpc_reg_operand" "")
1696 (match_operand:SI
2 "non_and_cint_operand" "")))]
1698 [(set (match_dup
0) (and:SI (match_dup
1) (match_dup
3)))
1699 (set (match_dup
0) (and:SI (match_dup
0) (match_dup
4)))]
1702 int maskval = INTVAL (operands[
2]);
1703 int i, transitions, last_bit_value;
1704 int orig = maskval, first_c = maskval, second_c;
1706 /* We know that MASKVAL must have more than
2 bit-transitions. Start at
1707 the low-order bit and count for the third transition. When we get there,
1708 make a first mask that has everything to the left of that position
1709 a one. Then make the second mask to turn off whatever else is needed. */
1711 for (i =
1, transitions =
0, last_bit_value = maskval &
1; i <
32; i++)
1713 if (((maskval >>=
1) &
1) != last_bit_value)
1714 last_bit_value ^=
1, transitions++;
1716 if (transitions >
2)
1718 first_c |= (~
0) << i;
1723 second_c = orig | ~ first_c;
1725 operands[
3] = gen_rtx (CONST_INT, VOIDmode, first_c);
1726 operands[
4] = gen_rtx (CONST_INT, VOIDmode, second_c);
1729 (define_insn "iorsi3"
1730 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
1731 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
1732 (match_operand:SI
2 "logical_operand" "r,K,J")))]
1736 {oril|ori} %
0,%
1,%b2
1737 {oriu|oris} %
0,%
1,%u2")
1740 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1741 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1742 (match_operand:SI
2 "gpc_reg_operand" "r"))
1744 (clobber (match_scratch:SI
3 "=r"))]
1747 [(set_attr "type" "compare")])
1750 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1751 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1752 (match_operand:SI
2 "gpc_reg_operand" "r"))
1754 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1755 (ior:SI (match_dup
1) (match_dup
2)))]
1758 [(set_attr "type" "compare")])
1760 ;; Split an IOR that we can't do in one insn into two insns, each of which
1761 ;; does one
16-bit part. This is used by combine.
1764 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1765 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "")
1766 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1768 [(set (match_dup
0) (ior:SI (match_dup
1) (match_dup
3)))
1769 (set (match_dup
0) (ior:SI (match_dup
0) (match_dup
4)))]
1772 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1773 INTVAL (operands[
2]) &
0xffff0000);
1774 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1777 (define_insn "xorsi3"
1778 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
1779 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
1780 (match_operand:SI
2 "logical_operand" "r,K,J")))]
1784 {xoril|xori} %
0,%
1,%b2
1785 {xoriu|xoris} %
0,%
1,%u2")
1788 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1789 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1790 (match_operand:SI
2 "gpc_reg_operand" "r"))
1792 (clobber (match_scratch:SI
3 "=r"))]
1795 [(set_attr "type" "compare")])
1798 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1799 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1800 (match_operand:SI
2 "gpc_reg_operand" "r"))
1802 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1803 (xor:SI (match_dup
1) (match_dup
2)))]
1806 [(set_attr "type" "compare")])
1808 ;; Split an XOR that we can't do in one insn into two insns, each of which
1809 ;; does one
16-bit part. This is used by combine.
1812 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1813 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1814 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1816 [(set (match_dup
0) (xor:SI (match_dup
1) (match_dup
3)))
1817 (set (match_dup
0) (xor:SI (match_dup
0) (match_dup
4)))]
1820 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1821 INTVAL (operands[
2]) &
0xffff0000);
1822 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1826 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1827 (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1828 (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1833 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1834 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1835 (match_operand:SI
2 "gpc_reg_operand" "r")))
1837 (clobber (match_scratch:SI
3 "=r"))]
1840 [(set_attr "type" "compare")])
1843 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1844 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1845 (match_operand:SI
2 "gpc_reg_operand" "r")))
1847 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1848 (not:SI (xor:SI (match_dup
1) (match_dup
2))))]
1851 [(set_attr "type" "compare")])
1854 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1855 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1856 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1861 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1862 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1863 (match_operand:SI
2 "gpc_reg_operand" "r"))
1865 (clobber (match_scratch:SI
3 "=r"))]
1868 [(set_attr "type" "compare")])
1871 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1872 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1873 (match_operand:SI
2 "gpc_reg_operand" "r"))
1875 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1876 (and:SI (not:SI (match_dup
1)) (match_dup
2)))]
1879 [(set_attr "type" "compare")])
1882 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1883 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1884 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1889 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1890 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1891 (match_operand:SI
2 "gpc_reg_operand" "r"))
1893 (clobber (match_scratch:SI
3 "=r"))]
1896 [(set_attr "type" "compare")])
1899 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1900 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1901 (match_operand:SI
2 "gpc_reg_operand" "r"))
1903 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1904 (ior:SI (not:SI (match_dup
1)) (match_dup
2)))]
1907 [(set_attr "type" "compare")])
1910 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1911 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1912 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1917 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1918 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1919 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1921 (clobber (match_scratch:SI
3 "=r"))]
1924 [(set_attr "type" "compare")])
1927 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1928 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1929 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1931 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1932 (ior:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1935 [(set_attr "type" "compare")])
1938 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1939 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1940 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1945 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1946 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1947 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1949 (clobber (match_scratch:SI
3 "=r"))]
1952 [(set_attr "type" "compare")])
1955 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1956 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1957 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1959 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1960 (and:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1963 [(set_attr "type" "compare")])
1965 ;; maskir insn. We need four forms because things might be in arbitrary
1966 ;; orders. Don't define forms that only set CR fields because these
1967 ;; would modify an input register.
1970 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1971 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1972 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1973 (and:SI (match_dup
2)
1974 (match_operand:SI
3 "gpc_reg_operand" "r"))))]
1979 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1980 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1981 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1982 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1988 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1989 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1990 (match_operand:SI
3 "gpc_reg_operand" "r"))
1991 (and:SI (not:SI (match_dup
2))
1992 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
1997 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1998 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1999 (match_operand:SI
2 "gpc_reg_operand" "r"))
2000 (and:SI (not:SI (match_dup
2))
2001 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
2006 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2008 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
2009 (match_operand:SI
1 "gpc_reg_operand" "
0"))
2010 (and:SI (match_dup
2)
2011 (match_operand:SI
3 "gpc_reg_operand" "r")))
2013 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2014 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
2015 (and:SI (match_dup
2) (match_dup
3))))]
2018 [(set_attr "type" "compare")])
2021 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2023 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
2024 (match_operand:SI
1 "gpc_reg_operand" "
0"))
2025 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2028 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2029 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
2030 (and:SI (match_dup
3) (match_dup
2))))]
2033 [(set_attr "type" "compare")])
2036 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2038 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2039 (match_operand:SI
3 "gpc_reg_operand" "r"))
2040 (and:SI (not:SI (match_dup
2))
2041 (match_operand:SI
1 "gpc_reg_operand" "
0")))
2043 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2044 (ior:SI (and:SI (match_dup
2) (match_dup
3))
2045 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
2048 [(set_attr "type" "compare")])
2051 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2053 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2054 (match_operand:SI
2 "gpc_reg_operand" "r"))
2055 (and:SI (not:SI (match_dup
2))
2056 (match_operand:SI
1 "gpc_reg_operand" "
0")))
2058 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2059 (ior:SI (and:SI (match_dup
3) (match_dup
2))
2060 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
2063 [(set_attr "type" "compare")])
2065 ;; Rotate and shift insns, in all their variants. These support shifts,
2066 ;; field inserts and extracts, and various combinations thereof.
2067 (define_expand "insv"
2068 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2069 (match_operand:SI
1 "const_int_operand" "i")
2070 (match_operand:SI
2 "const_int_operand" "i"))
2071 (match_operand:SI
3 "gpc_reg_operand" "r"))]
2075 /* Do not handle
16/
8 bit structures that fit in HI/QI modes directly, since
2076 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2077 compiler if the address of the structure is taken later. */
2078 if (GET_CODE (operands[
0]) == SUBREG
2079 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[
0]))) < UNITS_PER_WORD))
2084 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2085 (match_operand:SI
1 "const_int_operand" "i")
2086 (match_operand:SI
2 "const_int_operand" "i"))
2087 (match_operand:SI
3 "gpc_reg_operand" "r"))]
2091 int start = INTVAL (operands[
2]) &
31;
2092 int size = INTVAL (operands[
1]) &
31;
2094 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - start - size);
2095 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2096 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2100 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2101 (match_operand:SI
1 "const_int_operand" "i")
2102 (match_operand:SI
2 "const_int_operand" "i"))
2103 (ashift:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2104 (match_operand:SI
4 "const_int_operand" "i")))]
2108 int shift = INTVAL (operands[
4]) &
31;
2109 int start = INTVAL (operands[
2]) &
31;
2110 int size = INTVAL (operands[
1]) &
31;
2112 operands[
4] = gen_rtx (CONST_INT, VOIDmode, shift - start - size);
2113 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2114 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2118 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2119 (match_operand:SI
1 "const_int_operand" "i")
2120 (match_operand:SI
2 "const_int_operand" "i"))
2121 (ashiftrt:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2122 (match_operand:SI
4 "const_int_operand" "i")))]
2126 int shift = INTVAL (operands[
4]) &
31;
2127 int start = INTVAL (operands[
2]) &
31;
2128 int size = INTVAL (operands[
1]) &
31;
2130 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - shift - start - size);
2131 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2132 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2136 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2137 (match_operand:SI
1 "const_int_operand" "i")
2138 (match_operand:SI
2 "const_int_operand" "i"))
2139 (lshiftrt:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2140 (match_operand:SI
4 "const_int_operand" "i")))]
2144 int shift = INTVAL (operands[
4]) &
31;
2145 int start = INTVAL (operands[
2]) &
31;
2146 int size = INTVAL (operands[
1]) &
31;
2148 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - shift - start - size);
2149 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2150 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2154 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2155 (match_operand:SI
1 "const_int_operand" "i")
2156 (match_operand:SI
2 "const_int_operand" "i"))
2157 (zero_extract:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2158 (match_operand:SI
4 "const_int_operand" "i")
2159 (match_operand:SI
5 "const_int_operand" "i")))]
2160 "INTVAL (operands[
4]) >= INTVAL (operands[
1])"
2163 int extract_start = INTVAL (operands[
5]) &
31;
2164 int extract_size = INTVAL (operands[
4]) &
31;
2165 int insert_start = INTVAL (operands[
2]) &
31;
2166 int insert_size = INTVAL (operands[
1]) &
31;
2168 /* Align extract field with insert field */
2169 operands[
5] = gen_rtx (CONST_INT, VOIDmode,
2170 extract_start + extract_size - insert_start - insert_size);
2171 operands[
1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size -
1);
2172 return
\"{rlimi|rlwimi} %
0,%
3,%h5,%h2,%h1
\";
2176 [(set (zero_extract:DI (match_operand:DI
0 "gpc_reg_operand" "+r")
2177 (match_operand:DI
1 "const_int_operand" "i")
2178 (match_operand:DI
2 "const_int_operand" "i"))
2179 (match_operand:DI
3 "gpc_reg_operand" "r"))]
2183 int start = INTVAL (operands[
2]) &
63;
2184 int size = INTVAL (operands[
1]) &
63;
2186 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - start - size);
2187 return
\"rldimi %
0,%
3,%H2,%H1
\";
2190 (define_expand "extzv"
2191 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2192 (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2193 (match_operand:SI
2 "const_int_operand" "i")
2194 (match_operand:SI
3 "const_int_operand" "i")))]
2198 /* Do not handle
16/
8 bit structures that fit in HI/QI modes directly, since
2199 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2200 compiler if the address of the structure is taken later. */
2201 if (GET_CODE (operands[
0]) == SUBREG
2202 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[
0]))) < UNITS_PER_WORD))
2207 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2208 (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2209 (match_operand:SI
2 "const_int_operand" "i")
2210 (match_operand:SI
3 "const_int_operand" "i")))]
2214 int start = INTVAL (operands[
3]) &
31;
2215 int size = INTVAL (operands[
2]) &
31;
2217 if (start + size >=
32)
2218 operands[
3] = const0_rtx;
2220 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2221 return
\"{rlinm|rlwinm} %
0,%
1,%
3,%s2,
31\";
2225 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2226 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2227 (match_operand:SI
2 "const_int_operand" "i")
2228 (match_operand:SI
3 "const_int_operand" "i"))
2230 (clobber (match_scratch:SI
4 "=r"))]
2234 int start = INTVAL (operands[
3]) &
31;
2235 int size = INTVAL (operands[
2]) &
31;
2237 /* If the bitfield being tested fits in the upper or lower half of a
2238 word, it is possible to use andiu. or andil. to test it. This is
2239 useful because the condition register set-use delay is smaller for
2240 andi[ul]. than for rlinm. This doesn't work when the starting bit
2241 position is
0 because the LT and GT bits may be set wrong. */
2243 if ((start >
0 && start + size <=
16) || start >=
16)
2245 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
2246 ((
1 << (
16 - (start &
15)))
2247 - (
1 << (
16 - (start &
15) - size))));
2249 return
\"{andiu.|andis.} %
4,%
1,%
3\";
2251 return
\"{andil.|andi.} %
4,%
1,%
3\";
2254 if (start + size >=
32)
2255 operands[
3] = const0_rtx;
2257 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2258 return
\"{rlinm.|rlwinm.} %
4,%
1,%
3,%s2,
31\";
2260 [(set_attr "type" "compare")])
2263 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2264 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2265 (match_operand:SI
2 "const_int_operand" "i")
2266 (match_operand:SI
3 "const_int_operand" "i"))
2268 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2269 (zero_extract:SI (match_dup
1) (match_dup
2) (match_dup
3)))]
2273 int start = INTVAL (operands[
3]) &
31;
2274 int size = INTVAL (operands[
2]) &
31;
2276 if (start >=
16 && start + size ==
32)
2278 operands[
3] = gen_rtx (CONST_INT, VOIDmode, (
1 << (
32 - start)) -
1);
2279 return
\"{andil.|andi.} %
0,%
1,%
3\";
2282 if (start + size >=
32)
2283 operands[
3] = const0_rtx;
2285 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2286 return
\"{rlinm.|rlwinm.} %
0,%
1,%
3,%s2,
31\";
2288 [(set_attr "type" "delayed_compare")])
2291 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2292 (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2293 (match_operand:DI
2 "const_int_operand" "i")
2294 (match_operand:DI
3 "const_int_operand" "i")))]
2298 int start = INTVAL (operands[
3]) &
63;
2299 int size = INTVAL (operands[
2]) &
63;
2301 if (start + size >=
64)
2302 operands[
3] = const0_rtx;
2304 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2305 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2306 return
\"rldicl %
0,%
1,%
3,%
2\";
2310 [(set (match_operand:CC
0 "gpc_reg_operand" "=x")
2311 (compare:CC (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2312 (match_operand:DI
2 "const_int_operand" "i")
2313 (match_operand:DI
3 "const_int_operand" "i"))
2315 (clobber (match_scratch:DI
4 "=r"))]
2319 int start = INTVAL (operands[
3]) &
63;
2320 int size = INTVAL (operands[
2]) &
63;
2322 if (start + size >=
64)
2323 operands[
3] = const0_rtx;
2325 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2326 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2327 return
\"rldicl. %
4,%
1,%
3,%
2\";
2331 [(set (match_operand:CC
4 "gpc_reg_operand" "=x")
2332 (compare:CC (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2333 (match_operand:DI
2 "const_int_operand" "i")
2334 (match_operand:DI
3 "const_int_operand" "i"))
2336 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
2337 (zero_extract:DI (match_dup
1) (match_dup
2) (match_dup
3)))]
2341 int start = INTVAL (operands[
3]) &
63;
2342 int size = INTVAL (operands[
2]) &
63;
2344 if (start + size >=
64)
2345 operands[
3] = const0_rtx;
2347 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2348 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2349 return
\"rldicl. %
0,%
1,%
3,%
2\";
2352 (define_insn "rotlsi3"
2353 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2354 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2355 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2357 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffffffff")
2360 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2361 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2362 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2364 (clobber (match_scratch:SI
3 "=r"))]
2366 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffffffff"
2367 [(set_attr "type" "delayed_compare")])
2370 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2371 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2372 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2374 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2375 (rotate:SI (match_dup
1) (match_dup
2)))]
2377 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffffffff"
2378 [(set_attr "type" "delayed_compare")])
2381 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2382 (and:SI (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2383 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2384 (match_operand:SI
3 "mask_operand" "L")))]
2386 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,%m3,%M3")
2389 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2391 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2392 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2393 (match_operand:SI
3 "mask_operand" "L"))
2395 (clobber (match_scratch:SI
4 "=r"))]
2397 "{rl%I2nm.|rlw%I2nm.} %
4,%
1,%h2,%m3,%M3"
2398 [(set_attr "type" "delayed_compare")])
2401 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2403 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2404 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2405 (match_operand:SI
3 "mask_operand" "L"))
2407 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2408 (and:SI (rotate:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2410 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,%m3,%M3"
2411 [(set_attr "type" "delayed_compare")])
2414 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2417 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2418 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
2420 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xff")
2423 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2424 (compare:CC (zero_extend:SI
2426 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2427 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2429 (clobber (match_scratch:SI
3 "=r"))]
2431 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xff"
2432 [(set_attr "type" "delayed_compare")])
2435 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2436 (compare:CC (zero_extend:SI
2438 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2439 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2441 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2442 (zero_extend:SI (subreg:QI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
2444 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xff"
2445 [(set_attr "type" "delayed_compare")])
2448 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2451 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2452 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
2454 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffff")
2457 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2458 (compare:CC (zero_extend:SI
2460 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2461 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2463 (clobber (match_scratch:SI
3 "=r"))]
2465 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffff"
2466 [(set_attr "type" "delayed_compare")])
2469 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2470 (compare:CC (zero_extend:SI
2472 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2473 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2475 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2476 (zero_extend:SI (subreg:HI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
2478 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffff"
2479 [(set_attr "type" "delayed_compare")])
2481 ;; Note that we use "sle." instead of "sl." so that we can set
2482 ;; SHIFT_COUNT_TRUNCATED.
2484 (define_expand "ashlsi3"
2485 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
2486 (use (match_operand:SI
1 "gpc_reg_operand" ""))
2487 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
2492 emit_insn (gen_ashlsi3_power (operands[
0], operands[
1], operands[
2]));
2494 emit_insn (gen_ashlsi3_no_power (operands[
0], operands[
1], operands[
2]));
2498 (define_insn "ashlsi3_power"
2499 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2500 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2501 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
2502 (clobber (match_scratch:SI
3 "=q,X"))]
2506 {sli|slwi} %
0,%
1,%h2"
2507 [(set_attr "length" "
8")])
2509 (define_insn "ashlsi3_no_power"
2510 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2511 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2512 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2514 "{sl|slw}%I2 %
0,%
1,%h2"
2515 [(set_attr "length" "
8")])
2518 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2519 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2520 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2522 (clobber (match_scratch:SI
3 "=r,r"))
2523 (clobber (match_scratch:SI
4 "=q,X"))]
2527 {sli.|slwi.} %
3,%
1,%h2"
2528 [(set_attr "type" "delayed_compare")])
2531 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2532 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2533 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2535 (clobber (match_scratch:SI
3 "=r"))]
2537 "{sl|slw}%I2. %
3,%
1,%h2"
2538 [(set_attr "type" "delayed_compare")])
2541 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2542 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2543 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2545 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2546 (ashift:SI (match_dup
1) (match_dup
2)))
2547 (clobber (match_scratch:SI
4 "=q,X"))]
2551 {sli.|slwi.} %
0,%
1,%h2"
2552 [(set_attr "type" "delayed_compare")])
2555 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2556 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2557 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2559 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2560 (ashift:SI (match_dup
1) (match_dup
2)))]
2562 "{sl|slw}%I2. %
0,%
1,%h2"
2563 [(set_attr "type" "delayed_compare")])
2566 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2567 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2568 (match_operand:SI
2 "const_int_operand" "i"))
2569 (match_operand:SI
3 "mask_operand" "L")))]
2570 "includes_lshift_p (operands[
2], operands[
3])"
2571 "{rlinm|rlwinm} %
0,%
1,%h2,%m3,%M3")
2574 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2576 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2577 (match_operand:SI
2 "const_int_operand" "i"))
2578 (match_operand:SI
3 "mask_operand" "L"))
2580 (clobber (match_scratch:SI
4 "=r"))]
2581 "includes_lshift_p (operands[
2], operands[
3])"
2582 "{rlinm.|rlwinm.} %
4,%
1,%h2,%m3,%M3"
2583 [(set_attr "type" "delayed_compare")])
2586 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2588 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2589 (match_operand:SI
2 "const_int_operand" "i"))
2590 (match_operand:SI
3 "mask_operand" "L"))
2592 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2593 (and:SI (ashift:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2594 "includes_lshift_p (operands[
2], operands[
3])"
2595 "{rlinm.|rlwinm.} %
0,%
1,%h2,%m3,%M3"
2596 [(set_attr "type" "delayed_compare")])
2598 ;; The AIX assembler mis-handles "sri x,x,
0", so write that case as
2600 (define_expand "lshrsi3"
2601 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
2602 (use (match_operand:SI
1 "gpc_reg_operand" ""))
2603 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
2608 emit_insn (gen_lshrsi3_power (operands[
0], operands[
1], operands[
2]));
2610 emit_insn (gen_lshrsi3_no_power (operands[
0], operands[
1], operands[
2]));
2614 (define_insn "lshrsi3_power"
2615 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
2616 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
2617 (match_operand:SI
2 "reg_or_cint_operand" "r,O,i")))
2618 (clobber (match_scratch:SI
3 "=q,X,X"))]
2623 {s%A2i|s%A2wi} %
0,%
1,%h2")
2625 (define_insn "lshrsi3_no_power"
2626 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2627 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2628 (match_operand:SI
2 "reg_or_cint_operand" "O,ri")))]
2632 {sr|srw}%I2 %
0,%
1,%h2")
2635 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x")
2636 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
2637 (match_operand:SI
2 "reg_or_cint_operand" "r,O,i"))
2639 (clobber (match_scratch:SI
3 "=r,X,r"))
2640 (clobber (match_scratch:SI
4 "=q,X,X"))]
2645 {s%A2i.|s%A2wi.} %
3,%
1,%h2"
2646 [(set_attr "type" "delayed_compare")])
2649 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2650 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2651 (match_operand:SI
2 "reg_or_cint_operand" "O,ri"))
2653 (clobber (match_scratch:SI
3 "=X,r"))]
2657 {sr|srw}%I2. %
3,%
1,%h2"
2658 [(set_attr "type" "delayed_compare")])
2661 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x")
2662 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
2663 (match_operand:SI
2 "reg_or_cint_operand" "r,O,i"))
2665 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
2666 (lshiftrt:SI (match_dup
1) (match_dup
2)))
2667 (clobber (match_scratch:SI
4 "=q,X,X"))]
2672 {s%A2i.|s%A2wi.} %
0,%
1,%h2"
2673 [(set_attr "type" "delayed_compare")])
2676 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2677 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2678 (match_operand:SI
2 "reg_or_cint_operand" "O,ri"))
2680 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2681 (lshiftrt:SI (match_dup
1) (match_dup
2)))]
2685 {sr|srw}%I2. %
0,%
1,%h2"
2686 [(set_attr "type" "delayed_compare")])
2689 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2690 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2691 (match_operand:SI
2 "const_int_operand" "i"))
2692 (match_operand:SI
3 "mask_operand" "L")))]
2693 "includes_rshift_p (operands[
2], operands[
3])"
2694 "{rlinm|rlwinm} %
0,%
1,%s2,%m3,%M3")
2697 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2699 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2700 (match_operand:SI
2 "const_int_operand" "i"))
2701 (match_operand:SI
3 "mask_operand" "L"))
2703 (clobber (match_scratch:SI
4 "=r"))]
2704 "includes_rshift_p (operands[
2], operands[
3])"
2705 "{rlinm.|rlwinm.} %
4,%
1,%s2,%m3,%M3"
2706 [(set_attr "type" "delayed_compare")])
2709 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2711 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2712 (match_operand:SI
2 "const_int_operand" "i"))
2713 (match_operand:SI
3 "mask_operand" "L"))
2715 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2716 (and:SI (lshiftrt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2717 "includes_rshift_p (operands[
2], operands[
3])"
2718 "{rlinm.|rlwinm.} %
0,%
1,%s2,%m3,%M3"
2719 [(set_attr "type" "delayed_compare")])
2722 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2725 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2726 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
2727 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2728 "{rlinm|rlwinm} %
0,%
1,%s2,
0xff")
2731 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2735 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2736 (match_operand:SI
2 "const_int_operand" "i"))
0))
2738 (clobber (match_scratch:SI
3 "=r"))]
2739 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2740 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xff"
2741 [(set_attr "type" "delayed_compare")])
2744 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2748 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2749 (match_operand:SI
2 "const_int_operand" "i"))
0))
2751 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2752 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
2753 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2754 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xff"
2755 [(set_attr "type" "delayed_compare")])
2758 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2761 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2762 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
2763 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2764 "{rlinm|rlwinm} %
0,%
1,%s2,
0xffff")
2767 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2771 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2772 (match_operand:SI
2 "const_int_operand" "i"))
0))
2774 (clobber (match_scratch:SI
3 "=r"))]
2775 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2776 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xffff"
2777 [(set_attr "type" "delayed_compare")])
2780 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2784 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2785 (match_operand:SI
2 "const_int_operand" "i"))
0))
2787 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2788 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
2789 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2790 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xffff"
2791 [(set_attr "type" "delayed_compare")])
2794 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2796 (match_operand:SI
1 "gpc_reg_operand" "r"))
2797 (ashiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2803 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2805 (match_operand:SI
1 "gpc_reg_operand" "r"))
2806 (lshiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2812 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2814 (match_operand:SI
1 "gpc_reg_operand" "r"))
2815 (zero_extract:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2821 (define_expand "ashrsi3"
2822 [(set (match_operand:SI
0 "gpc_reg_operand" "")
2823 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "")
2824 (match_operand:SI
2 "reg_or_cint_operand" "")))]
2829 emit_insn (gen_ashrsi3_power (operands[
0], operands[
1], operands[
2]));
2831 emit_insn (gen_ashrsi3_no_power (operands[
0], operands[
1], operands[
2]));
2835 (define_insn "ashrsi3_power"
2836 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2837 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2838 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
2839 (clobber (match_scratch:SI
3 "=q,X"))]
2843 {srai|srawi} %
0,%
1,%h2")
2845 (define_insn "ashrsi3_no_power"
2846 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2847 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2848 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2850 "{sra|sraw}%I2 %
0,%
1,%h2")
2853 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2854 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2855 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2857 (clobber (match_scratch:SI
3 "=r,r"))
2858 (clobber (match_scratch:SI
4 "=q,X"))]
2862 {srai.|srawi.} %
3,%
1,%h2"
2863 [(set_attr "type" "delayed_compare")])
2866 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2867 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2868 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2870 (clobber (match_scratch:SI
3 "=r"))]
2872 "{sra|sraw}%I2. %
3,%
1,%h2"
2873 [(set_attr "type" "delayed_compare")])
2876 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2877 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2878 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2880 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2881 (ashiftrt:SI (match_dup
1) (match_dup
2)))
2882 (clobber (match_scratch:SI
4 "=q,X"))]
2886 {srai.|srawi.} %
0,%
1,%h2"
2887 [(set_attr "type" "delayed_compare")])
2890 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2891 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2892 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2894 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2895 (ashiftrt:SI (match_dup
1) (match_dup
2)))]
2897 "{sra|sraw}%I2. %
0,%
1,%h2"
2898 [(set_attr "type" "delayed_compare")])
2900 ;; Floating-point insns, excluding normal data motion.
2902 ;; PowerPC has a full set of single-precision floating point instructions.
2904 ;; For the POWER architecture, we pretend that we have both SFmode and
2905 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2906 ;; The only conversions we will do will be when storing to memory. In that
2907 ;; case, we will use the "frsp" instruction before storing.
2909 ;; Note that when we store into a single-precision memory location, we need to
2910 ;; use the frsp insn first. If the register being stored isn't dead, we
2911 ;; need a scratch register for the frsp. But this is difficult when the store
2912 ;; is done by reload. It is not incorrect to do the frsp on the register in
2913 ;; this case, we just lose precision that we would have otherwise gotten but
2914 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2916 (define_insn "extendsfdf2"
2917 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2918 (float_extend:DF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2922 if (REGNO (operands[
0]) == REGNO (operands[
1]))
2925 return
\"fmr %
0,%
1\";
2927 [(set_attr "type" "fp")])
2929 (define_insn "truncdfsf2"
2930 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2931 (float_truncate:SF (match_operand:DF
1 "gpc_reg_operand" "f")))]
2934 [(set_attr "type" "fp")])
2936 (define_insn "aux_truncdfsf2"
2937 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2938 (unspec:SF [(match_operand:SF
1 "gpc_reg_operand" "f")]
0))]
2939 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2941 [(set_attr "type" "fp")])
2943 (define_insn "negsf2"
2944 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2945 (neg:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2948 [(set_attr "type" "fp")])
2950 (define_insn "abssf2"
2951 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2952 (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2955 [(set_attr "type" "fp")])
2958 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2959 (neg:SF (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f"))))]
2962 [(set_attr "type" "fp")])
2964 (define_expand "addsf3"
2965 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2966 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2967 (match_operand:SF
2 "gpc_reg_operand" "")))]
2972 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2973 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2974 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2975 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2977 [(set_attr "type" "fp")])
2980 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2981 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2982 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2983 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2984 "{fa|fadd} %
0,%
1,%
2"
2985 [(set_attr "type" "fp")])
2987 (define_expand "subsf3"
2988 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2989 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2990 (match_operand:SF
2 "gpc_reg_operand" "")))]
2995 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2996 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2997 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2998 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3000 [(set_attr "type" "fp")])
3003 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3004 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3005 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3006 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3007 "{fs|fsub} %
0,%
1,%
2"
3008 [(set_attr "type" "fp")])
3010 (define_expand "mulsf3"
3011 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3012 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "")
3013 (match_operand:SF
2 "gpc_reg_operand" "")))]
3018 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3019 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3020 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3021 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3023 [(set_attr "type" "fp")])
3026 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3027 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3028 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3029 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3030 "{fm|fmul} %
0,%
1,%
2"
3031 [(set_attr "type" "dmul")])
3033 (define_expand "divsf3"
3034 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3035 (div:SF (match_operand:SF
1 "gpc_reg_operand" "")
3036 (match_operand:SF
2 "gpc_reg_operand" "")))]
3041 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3042 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3043 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3044 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3046 [(set_attr "type" "sdiv")])
3049 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3050 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3051 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3052 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3053 "{fd|fdiv} %
0,%
1,%
2"
3054 [(set_attr "type" "ddiv")])
3057 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3058 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3059 (match_operand:SF
2 "gpc_reg_operand" "f"))
3060 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3061 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3062 "fmadds %
0,%
1,%
2,%
3"
3063 [(set_attr "type" "fp")])
3066 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3067 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3068 (match_operand:SF
2 "gpc_reg_operand" "f"))
3069 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3070 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3071 "{fma|fmadd} %
0,%
1,%
2,%
3"
3072 [(set_attr "type" "dmul")])
3075 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3076 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3077 (match_operand:SF
2 "gpc_reg_operand" "f"))
3078 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3079 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3080 "fmsubs %
0,%
1,%
2,%
3"
3081 [(set_attr "type" "fp")])
3084 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3085 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3086 (match_operand:SF
2 "gpc_reg_operand" "f"))
3087 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3088 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3089 "{fms|fmsub} %
0,%
1,%
2,%
3"
3090 [(set_attr "type" "dmul")])
3093 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3094 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3095 (match_operand:SF
2 "gpc_reg_operand" "f"))
3096 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3097 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3098 "fnmadds %
0,%
1,%
2,%
3"
3099 [(set_attr "type" "fp")])
3102 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3103 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3104 (match_operand:SF
2 "gpc_reg_operand" "f"))
3105 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3106 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3107 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
3108 [(set_attr "type" "dmul")])
3111 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3112 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3113 (match_operand:SF
2 "gpc_reg_operand" "f"))
3114 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3115 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3116 "fnmsubs %
0,%
1,%
2,%
3"
3117 [(set_attr "type" "fp")])
3120 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3121 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3122 (match_operand:SF
2 "gpc_reg_operand" "f"))
3123 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3124 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3125 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
3126 [(set_attr "type" "dmul")])
3128 (define_expand "sqrtsf2"
3129 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3130 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "")))]
3131 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3135 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3136 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
3137 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3139 [(set_attr "type" "ssqrt")])
3142 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3143 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
3144 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3146 [(set_attr "type" "dsqrt")])
3148 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3149 ;; fsel instruction and some auxiliary computations. Then we just have a
3150 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3152 (define_expand "maxsf3"
3154 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "")
3155 (match_operand:SF
2 "gpc_reg_operand" "")))
3156 (set (match_operand:SF
0 "gpc_reg_operand" "")
3157 (if_then_else:SF (ge (match_dup
3)
3161 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3163 { operands[
3] = gen_reg_rtx (SFmode); }")
3166 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3167 (smax:SF (match_operand:SF
1 "gpc_reg_operand" "")
3168 (match_operand:SF
2 "gpc_reg_operand" "")))
3169 (clobber (match_operand:SF
3 "gpc_reg_operand" ""))]
3170 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3172 (minus:SF (match_dup
1) (match_dup
2)))
3174 (if_then_else:SF (ge (match_dup
3)
3180 (define_expand "minsf3"
3182 (minus:SF (match_operand:SF
2 "gpc_reg_operand" "")
3183 (match_operand:SF
1 "gpc_reg_operand" "")))
3184 (set (match_operand:SF
0 "gpc_reg_operand" "")
3185 (if_then_else:SF (ge (match_dup
3)
3189 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3191 { operands[
3] = gen_reg_rtx (SFmode); }")
3194 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3195 (smin:SF (match_operand:SF
1 "gpc_reg_operand" "")
3196 (match_operand:SF
2 "gpc_reg_operand" "")))
3197 (clobber (match_operand:SF
3 "gpc_reg_operand" ""))]
3198 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3200 (minus:SF (match_dup
2) (match_dup
1)))
3202 (if_then_else:SF (ge (match_dup
3)
3208 (define_expand "movsfcc"
3209 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3210 (if_then_else:SF (match_operand
1 "comparison_operator" "")
3211 (match_operand:SF
2 "gpc_reg_operand" "f")
3212 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3213 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3217 enum rtx_code code = GET_CODE (operands[
1]);
3218 if (! rs6000_compare_fp_p)
3222 case GE: case EQ: case NE:
3223 op0 = rs6000_compare_op0;
3224 op1 = rs6000_compare_op1;
3227 op0 = rs6000_compare_op1;
3228 op1 = rs6000_compare_op0;
3229 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3232 op0 = rs6000_compare_op1;
3233 op1 = rs6000_compare_op0;
3236 op0 = rs6000_compare_op0;
3237 op1 = rs6000_compare_op1;
3238 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3243 if (GET_MODE (rs6000_compare_op0) == DFmode)
3245 temp = gen_reg_rtx (DFmode);
3246 emit_insn (gen_subdf3 (temp, op0, op1));
3247 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
2], operands[
3]));
3250 emit_insn (gen_negdf2 (temp, temp));
3251 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
0], operands[
3]));
3255 emit_insn (gen_negdf2 (temp, temp));
3256 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
3], operands[
0]));
3261 temp = gen_reg_rtx (SFmode);
3262 emit_insn (gen_subsf3 (temp, op0, op1));
3263 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
2], operands[
3]));
3266 emit_insn (gen_negsf2 (temp, temp));
3267 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
0], operands[
3]));
3271 emit_insn (gen_negsf2 (temp, temp));
3272 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
3], operands[
0]));
3278 (define_insn "fselsfsf4"
3279 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3280 (if_then_else:SF (ge (match_operand:SF
1 "gpc_reg_operand" "f")
3282 (match_operand:SF
2 "gpc_reg_operand" "f")
3283 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3284 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3286 [(set_attr "type" "fp")])
3288 (define_insn "fseldfsf4"
3289 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3290 (if_then_else:SF (ge (match_operand:DF
1 "gpc_reg_operand" "f")
3292 (match_operand:SF
2 "gpc_reg_operand" "f")
3293 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3294 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3296 [(set_attr "type" "fp")])
3298 (define_insn "negdf2"
3299 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3300 (neg:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3303 [(set_attr "type" "fp")])
3305 (define_insn "absdf2"
3306 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3307 (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3310 [(set_attr "type" "fp")])
3313 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3314 (neg:DF (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f"))))]
3317 [(set_attr "type" "fp")])
3319 (define_insn "adddf3"
3320 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3321 (plus:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3322 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3324 "{fa|fadd} %
0,%
1,%
2"
3325 [(set_attr "type" "fp")])
3327 (define_insn "subdf3"
3328 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3329 (minus:DF (match_operand:DF
1 "gpc_reg_operand" "f")
3330 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3332 "{fs|fsub} %
0,%
1,%
2"
3333 [(set_attr "type" "fp")])
3335 (define_insn "muldf3"
3336 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3337 (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3338 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3340 "{fm|fmul} %
0,%
1,%
2"
3341 [(set_attr "type" "dmul")])
3343 (define_insn "divdf3"
3344 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3345 (div:DF (match_operand:DF
1 "gpc_reg_operand" "f")
3346 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3348 "{fd|fdiv} %
0,%
1,%
2"
3349 [(set_attr "type" "ddiv")])
3352 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3353 (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3354 (match_operand:DF
2 "gpc_reg_operand" "f"))
3355 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3357 "{fma|fmadd} %
0,%
1,%
2,%
3"
3358 [(set_attr "type" "dmul")])
3361 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3362 (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3363 (match_operand:DF
2 "gpc_reg_operand" "f"))
3364 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3366 "{fms|fmsub} %
0,%
1,%
2,%
3"
3367 [(set_attr "type" "dmul")])
3370 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3371 (neg:DF (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3372 (match_operand:DF
2 "gpc_reg_operand" "f"))
3373 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
3375 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
3376 [(set_attr "type" "dmul")])
3379 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3380 (neg:DF (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3381 (match_operand:DF
2 "gpc_reg_operand" "f"))
3382 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
3384 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
3385 [(set_attr "type" "dmul")])
3387 (define_insn "sqrtdf2"
3388 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3389 (sqrt:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3390 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3392 [(set_attr "type" "dsqrt")])
3394 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3395 ;; fsel instruction and some auxiliary computations. Then we just have a
3396 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3399 (define_expand "maxdf3"
3401 (minus:DF (match_operand:DF
1 "gpc_reg_operand" "")
3402 (match_operand:DF
2 "gpc_reg_operand" "")))
3403 (set (match_operand:DF
0 "gpc_reg_operand" "")
3404 (if_then_else:DF (ge (match_dup
3)
3408 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3410 { operands[
3] = gen_reg_rtx (DFmode); }")
3413 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3414 (smax:DF (match_operand:DF
1 "gpc_reg_operand" "")
3415 (match_operand:DF
2 "gpc_reg_operand" "")))
3416 (clobber (match_operand:DF
3 "gpc_reg_operand" ""))]
3417 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3419 (minus:DF (match_dup
1) (match_dup
2)))
3421 (if_then_else:DF (ge (match_dup
3)
3427 (define_expand "mindf3"
3429 (minus:DF (match_operand:DF
2 "gpc_reg_operand" "")
3430 (match_operand:DF
1 "gpc_reg_operand" "")))
3431 (set (match_operand:DF
0 "gpc_reg_operand" "")
3432 (if_then_else:DF (ge (match_dup
3)
3436 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3438 { operands[
3] = gen_reg_rtx (DFmode); }")
3441 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3442 (smin:DF (match_operand:DF
1 "gpc_reg_operand" "")
3443 (match_operand:DF
2 "gpc_reg_operand" "")))
3444 (clobber (match_operand:DF
3 "gpc_reg_operand" ""))]
3445 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3447 (minus:DF (match_dup
2) (match_dup
1)))
3449 (if_then_else:DF (ge (match_dup
3)
3455 (define_expand "movdfcc"
3456 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3457 (if_then_else:DF (match_operand
1 "comparison_operator" "")
3458 (match_operand:DF
2 "gpc_reg_operand" "f")
3459 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3460 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3464 enum rtx_code code = GET_CODE (operands[
1]);
3465 if (! rs6000_compare_fp_p)
3469 case GE: case EQ: case NE:
3470 op0 = rs6000_compare_op0;
3471 op1 = rs6000_compare_op1;
3474 op0 = rs6000_compare_op1;
3475 op1 = rs6000_compare_op0;
3476 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3479 op0 = rs6000_compare_op1;
3480 op1 = rs6000_compare_op0;
3483 op0 = rs6000_compare_op0;
3484 op1 = rs6000_compare_op1;
3485 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3490 if (GET_MODE (rs6000_compare_op0) == DFmode)
3492 temp = gen_reg_rtx (DFmode);
3493 emit_insn (gen_subdf3 (temp, op0, op1));
3494 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
2], operands[
3]));
3497 emit_insn (gen_negdf2 (temp, temp));
3498 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
0], operands[
3]));
3502 emit_insn (gen_negdf2 (temp, temp));
3503 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
3], operands[
0]));
3508 temp = gen_reg_rtx (SFmode);
3509 emit_insn (gen_subsf3 (temp, op0, op1));
3510 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
2], operands[
3]));
3513 emit_insn (gen_negsf2 (temp, temp));
3514 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
0], operands[
3]));
3518 emit_insn (gen_negsf2 (temp, temp));
3519 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
3], operands[
0]));
3525 (define_insn "fseldfdf4"
3526 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3527 (if_then_else:DF (ge (match_operand:DF
1 "gpc_reg_operand" "f")
3529 (match_operand:DF
2 "gpc_reg_operand" "f")
3530 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3531 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3533 [(set_attr "type" "fp")])
3535 (define_insn "fselsfdf4"
3536 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3537 (if_then_else:DF (ge (match_operand:SF
1 "gpc_reg_operand" "f")
3539 (match_operand:DF
2 "gpc_reg_operand" "f")
3540 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3543 [(set_attr "type" "fp")])
3545 ;; Conversions to and from floating-point.
3547 (define_expand "floatsidf2"
3548 [(parallel [(set (match_operand:DF
0 "gpc_reg_operand" "")
3549 (float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3552 (clobber (match_dup
4))
3553 (clobber (match_dup
5))
3554 (clobber (reg:DF
76))])]
3555 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3558 operands[
2] = force_reg (SImode, GEN_INT (
0x43300000));
3559 operands[
3] = force_reg (DFmode, rs6000_float_const (
\"4503601774854144\", DFmode));
3560 operands[
4] = gen_reg_rtx (SImode);
3561 operands[
5] = gen_reg_rtx (Pmode);
3564 (define_insn "*floatsidf2_internal"
3565 [(set (match_operand:DF
0 "gpc_reg_operand" "=&f")
3566 (float:DF (match_operand:SI
1 "gpc_reg_operand" "r")))
3567 (use (match_operand:SI
2 "gpc_reg_operand" "r"))
3568 (use (match_operand:DF
3 "gpc_reg_operand" "f"))
3569 (clobber (match_operand:SI
4 "gpc_reg_operand" "=r"))
3570 (clobber (match_operand:SI
5 "gpc_reg_operand" "=b"))
3571 (clobber (reg:DF
76))]
3572 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3574 [(set_attr "length" "
24")])
3577 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3578 (float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3579 (use (match_operand:SI
2 "gpc_reg_operand" ""))
3580 (use (match_operand:DF
3 "gpc_reg_operand" ""))
3581 (clobber (match_operand:SI
4 "gpc_reg_operand" ""))
3582 (clobber (match_operand:SI
5 "gpc_reg_operand" ""))
3583 (clobber (reg:DF
76))]
3584 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3586 (xor:SI (match_dup
1)
3589 (unspec [(const_int
0)]
11))
3591 (unspec [(match_dup
4)
3592 (match_dup
5)]
12)) ;; low word
3594 (unspec [(match_dup
2)
3596 (match_dup
7)]
13)) ;; high word
3598 (unspec [(match_dup
7)
3601 (minus:DF (match_dup
0)
3605 operands[
6] = GEN_INT (
0x80000000);
3606 operands[
7] = gen_rtx (REG, DFmode, FPMEM_REGNUM);
3609 (define_expand "floatunssidf2"
3610 [(parallel [(set (match_operand:DF
0 "gpc_reg_operand" "")
3611 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3614 (clobber (match_dup
4))
3615 (clobber (reg:DF
76))])]
3616 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3619 operands[
2] = force_reg (SImode, GEN_INT (
0x43300000));
3620 operands[
3] = force_reg (DFmode, rs6000_float_const (
\"4503599627370496\", DFmode));
3621 operands[
4] = gen_reg_rtx (Pmode);
3624 (define_insn "*floatunssidf2_internal"
3625 [(set (match_operand:DF
0 "gpc_reg_operand" "=&f")
3626 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "r")))
3627 (use (match_operand:SI
2 "gpc_reg_operand" "r"))
3628 (use (match_operand:DF
3 "gpc_reg_operand" "f"))
3629 (clobber (match_operand:SI
4 "gpc_reg_operand" "=b"))
3630 (clobber (reg:DF
76))]
3631 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3633 [(set_attr "length" "
20")])
3636 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3637 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3638 (use (match_operand:SI
2 "gpc_reg_operand" ""))
3639 (use (match_operand:DF
3 "gpc_reg_operand" ""))
3640 (clobber (match_operand:SI
4 "gpc_reg_operand" "=b"))
3641 (clobber (reg:DF
76))]
3642 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3644 (unspec [(const_int
0)]
11))
3646 (unspec [(match_dup
1)
3647 (match_dup
4)]
12)) ;; low word
3649 (unspec [(match_dup
2)
3651 (match_dup
5)]
13)) ;; high word
3653 (unspec [(match_dup
5)
3656 (minus:DF (match_dup
0)
3658 "operands[
5] = gen_rtx (REG, DFmode, FPMEM_REGNUM);")
3660 ;; Load up scratch register with base address + offset if needed
3661 (define_insn "*floatsidf2_loadaddr"
3662 [(set (match_operand:SI
0 "gpc_reg_operand" "=b")
3663 (unspec [(const_int
0)]
11))]
3667 if (rs6000_fpmem_offset >
32760)
3671 xop[
0] = operands[
0];
3672 xop[
1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
3673 xop[
2] = GEN_INT ((rs6000_fpmem_offset >>
16) + ((rs6000_fpmem_offset &
0x8000) >>
15));
3674 output_asm_insn (
\"{cau|addis} %
0,%
1,%
2\", xop);
3676 else if (rs6000_fpmem_offset <
0)
3681 [(set_attr "length" "
4")])
3683 (define_insn "*floatsidf2_store1"
3685 (unspec [(match_operand:SI
0 "gpc_reg_operand" "r")
3686 (match_operand:SI
1 "gpc_reg_operand" "r")]
12))]
3687 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3692 if (rs6000_fpmem_offset >
32760)
3694 else if (frame_pointer_needed)
3695 indx = frame_pointer_rtx;
3697 indx = stack_pointer_rtx;
3699 operands[
2] = gen_rtx (MEM, SImode,
3700 gen_rtx (PLUS, Pmode,
3702 GEN_INT ((((rs6000_fpmem_offset &
0xffff) ^
0x8000) -
0x8000)
3703 + ((WORDS_BIG_ENDIAN !=
0) *
4))));
3705 return
\"{st|stw} %
0,%
2\";
3707 [(set_attr "type" "store")])
3709 (define_insn "*floatsidf2_store2"
3711 (unspec [(match_operand:SI
0 "gpc_reg_operand" "r")
3712 (match_operand:SI
1 "gpc_reg_operand" "r")
3714 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3719 if (rs6000_fpmem_offset >
32760)
3721 else if (frame_pointer_needed)
3722 indx = frame_pointer_rtx;
3724 indx = stack_pointer_rtx;
3726 operands[
2] = gen_rtx (MEM, SImode,
3727 gen_rtx (PLUS, Pmode,
3729 GEN_INT ((((rs6000_fpmem_offset &
0xffff) ^
0x8000) -
0x8000)
3730 + ((WORDS_BIG_ENDIAN ==
0) *
4))));
3732 return
\"{st|stw} %
0,%
2\";
3734 [(set_attr "type" "store")])
3736 (define_insn "*floatsidf2_load"
3737 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3738 (unspec [(reg:DF
76)
3739 (match_operand:SI
1 "gpc_reg_operand" "b")]
14))]
3740 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3744 HOST_WIDE_INT offset = rs6000_fpmem_offset;
3746 if (rs6000_fpmem_offset >
32760)
3749 offset = (((offset &
0xffff) ^
0x8000) -
0x8000);
3751 else if (frame_pointer_needed)
3752 indx = frame_pointer_rtx;
3754 indx = stack_pointer_rtx;
3756 operands[
2] = gen_rtx (MEM, SImode,
3757 gen_rtx (PLUS, Pmode, indx, GEN_INT (offset)));
3759 return
\"lfd %
0,%
2\";
3761 [(set_attr "type" "fpload")])
3763 (define_expand "fix_truncdfsi2"
3764 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
3765 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))
3766 (clobber (match_dup
2))
3767 (clobber (match_dup
3))
3768 (clobber (match_dup
4))])]
3772 if (!TARGET_POWER2 && !TARGET_POWERPC)
3774 emit_insn (gen_trunc_call (operands[
0], operands[
1],
3775 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3779 operands[
2] = gen_reg_rtx (DImode);
3780 operands[
3] = gen_reg_rtx (Pmode);
3781 operands[
4] = gen_rtx (REG, DImode, FPMEM_REGNUM);
3784 (define_insn "*fix_truncdfsi2_internal"
3785 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3786 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "f")))
3787 (clobber (match_operand:DI
2 "gpc_reg_operand" "=f"))
3788 (clobber (match_operand:SI
3 "gpc_reg_operand" "=b"))
3789 (clobber (reg:DI
76))]
3792 [(set_attr "length" "
12")])
3795 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3796 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "f")))
3797 (clobber (match_operand:DI
2 "gpc_reg_operand" ""))
3798 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))
3799 (clobber (reg:DI
76))]
3802 (sign_extend:DI (fix:SI (match_operand:DF
1 "gpc_reg_operand" ""))))
3804 (unspec [(const_int
0)]
11))
3806 (unspec [(match_dup
2)
3808 (set (match_operand:SI
0 "gpc_reg_operand" "")
3809 (unspec [(match_dup
4)
3810 (match_dup
3)]
16))]
3811 "operands[
4] = gen_rtx (REG, DImode, FPMEM_REGNUM);")
3813 (define_insn "*fctiwz"
3814 [(set (match_operand:DI
0 "gpc_reg_operand" "=f")
3815 (sign_extend:DI (fix:SI (match_operand:DF
1 "gpc_reg_operand" "f"))))]
3816 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3817 "{fcirz|fctiwz} %
0,%
1"
3818 [(set_attr "type" "fp")])
3820 (define_insn "*fix_truncdfsi2_store"
3822 (unspec [(match_operand:DI
0 "gpc_reg_operand" "f")
3823 (match_operand:SI
1 "gpc_reg_operand" "b")]
15))]
3824 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3829 if (rs6000_fpmem_offset >
32760)
3831 else if (frame_pointer_needed)
3832 indx = frame_pointer_rtx;
3834 indx = stack_pointer_rtx;
3836 operands[
2] = gen_rtx (MEM, DFmode,
3837 gen_rtx (PLUS, Pmode,
3839 GEN_INT ((((rs6000_fpmem_offset &
0xffff)
3840 ^
0x8000) -
0x8000))));
3842 return
\"stfd %
0,%w2
\";
3844 [(set_attr "type" "fpstore")])
3846 (define_insn "*fix_truncdfsi2_load"
3847 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3848 (unspec [(reg:DI
76)
3849 (match_operand:SI
1 "gpc_reg_operand" "b")]
16))]
3850 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3855 if (rs6000_fpmem_offset >
32760)
3857 else if (frame_pointer_needed)
3858 indx = frame_pointer_rtx;
3860 indx = stack_pointer_rtx;
3862 operands[
2] = gen_rtx (MEM, DFmode,
3863 gen_rtx (PLUS, Pmode,
3865 GEN_INT ((((rs6000_fpmem_offset &
0xffff) ^
0x8000) -
0x8000)
3866 + ((WORDS_BIG_ENDIAN) ?
4 :
0))));
3868 return
\"{l|lwz} %
0,%
2\";
3870 [(set_attr "type" "load")])
3872 (define_expand "fixuns_truncdfsi2"
3873 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3874 (unsigned_fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))]
3875 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3878 emit_insn (gen_trunc_call (operands[
0], operands[
1],
3879 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3883 (define_expand "trunc_call"
3884 [(parallel [(set (match_operand:SI
0 "" "")
3885 (fix:SI (match_operand:DF
1 "" "")))
3886 (use (match_operand:SI
2 "" ""))])]
3890 rtx insns = gen_trunc_call_rtl (operands[
0], operands[
1], operands[
2]);
3891 rtx first = XVECEXP (insns,
0,
0);
3892 rtx last = XVECEXP (insns,
0, XVECLEN (insns,
0) -
1);
3894 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3896 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3902 (define_expand "trunc_call_rtl"
3903 [(set (reg:DF
33) (match_operand:DF
1 "gpc_reg_operand" ""))
3905 (parallel [(set (reg:SI
3)
3906 (call (mem:SI (match_operand
2 "" "")) (const_int
0)))
3908 (clobber (scratch:SI))])
3909 (set (match_operand:SI
0 "gpc_reg_operand" "")
3914 rs6000_trunc_used =
1;
3917 (define_insn "floatdidf2"
3918 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3919 (float:DF (match_operand:DI
1 "gpc_reg_operand" "f")))]
3920 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3922 [(set_attr "type" "fp")])
3924 (define_insn "fix_truncdfdi2"
3925 [(set (match_operand:DI
0 "gpc_reg_operand" "=f")
3926 (fix:DI (match_operand:DF
1 "gpc_reg_operand" "f")))]
3927 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3929 [(set_attr "type" "fp")])
3931 ;; Define the DImode operations that can be done in a small number
3932 ;; of instructions. The & constraints are to prevent the register
3933 ;; allocator from allocating registers that overlap with the inputs
3934 ;; (for example, having an input in
7,
8 and an output in
6,
7). We
3935 ;; also allow for the the output being the same as one of the inputs.
3937 (define_insn "*adddi3_noppc64"
3938 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,&r,r,r")
3939 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,
0,
0")
3940 (match_operand:DI
2 "reg_or_short_operand" "r,I,r,I")))]
3941 "! TARGET_POWERPC64"
3944 if (WORDS_BIG_ENDIAN)
3945 return (GET_CODE (operands[
2])) != CONST_INT
3946 ?
\"{a|addc} %L0,%L1,%L2\;{ae|adde} %
0,%
1,%
2\"
3947 :
\"{ai|addic} %L0,%L1,%
2\;{a%G2e|add%G2e} %
0,%
1\";
3949 return (GET_CODE (operands[
2])) != CONST_INT
3950 ?
\"{a|addc} %
0,%
1,%
2\;{ae|adde} %L0,%L1,%L2
\"
3951 :
\"{ai|addic} %
0,%
1,%
2\;{a%G2e|add%G2e} %L0,%L1
\";
3953 [(set_attr "length" "
8")])
3955 (define_insn "*subdi3_noppc64"
3956 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,&r,r,r,r")
3957 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I,
0,r,I")
3958 (match_operand:DI
2 "gpc_reg_operand" "r,r,r,
0,
0")))]
3959 "! TARGET_POWERPC64"
3962 if (WORDS_BIG_ENDIAN)
3963 return (GET_CODE (operands[
1]) != CONST_INT)
3964 ?
\"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %
0,%
2,%
1\"
3965 :
\"{sfi|subfic} %L0,%L2,%
1\;{sf%G1e|subf%G1e} %
0,%
2\";
3967 return (GET_CODE (operands[
1]) != CONST_INT)
3968 ?
\"{sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %L0,%L2,%L1
\"
3969 :
\"{sfi|subfic} %
0,%
2,%
1\;{sf%G1e|subf%G1e} %L0,%L2
\";
3971 [(set_attr "length" "
8")])
3973 (define_insn "*negdi2_noppc64"
3974 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
3975 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))]
3976 "! TARGET_POWERPC64"
3979 return (WORDS_BIG_ENDIAN)
3980 ?
\"{sfi|subfic} %L0,%L1,
0\;{sfze|subfze} %
0,%
1\"
3981 :
\"{sfi|subfic} %
0,%
1,
0\;{sfze|subfze} %L0,%L1
\";
3983 [(set_attr "length" "
8")])
3985 (define_expand "mulsidi3"
3986 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3987 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
3988 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
3992 if (! TARGET_POWER && ! TARGET_POWERPC)
3994 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
3995 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
3996 emit_insn (gen_mull_call ());
3997 if (WORDS_BIG_ENDIAN)
3998 emit_move_insn (operands[
0], gen_rtx (REG, DImode,
3));
4001 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode),
4002 gen_rtx (REG, SImode,
3));
4003 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode),
4004 gen_rtx (REG, SImode,
4));
4008 else if (TARGET_POWER)
4010 emit_insn (gen_mulsidi3_mq (operands[
0], operands[
1], operands[
2]));
4015 (define_insn "mulsidi3_mq"
4016 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4017 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
4018 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))
4019 (clobber (match_scratch:SI
3 "=q"))]
4021 "mul %
0,%
1,%
2\;mfmq %L0"
4022 [(set_attr "type" "imul")
4023 (set_attr "length" "
8")])
4025 (define_insn "*mulsidi3_powerpc"
4026 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
4027 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
4028 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
4029 "TARGET_POWERPC && ! TARGET_POWERPC64"
4032 return (WORDS_BIG_ENDIAN)
4033 ?
\"mulhw %
0,%
1,%
2\;mullw %L0,%
1,%
2\"
4034 :
\"mulhw %L0,%
1,%
2\;mullw %
0,%
1,%
2\";
4036 [(set_attr "type" "imul")
4037 (set_attr "length" "
8")])
4040 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4041 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
4042 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
4043 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4046 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup
1))
4047 (sign_extend:DI (match_dup
2)))
4050 (mult:SI (match_dup
1)
4054 int endian = (WORDS_BIG_ENDIAN ==
0);
4055 operands[
3] = operand_subword (operands[
0], endian,
0, DImode);
4056 operands[
4] = operand_subword (operands[
0],
1 - endian,
0, DImode);
4059 (define_insn "umulsidi3"
4060 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
4061 (mult:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
4062 (zero_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
4063 "TARGET_POWERPC && ! TARGET_POWERPC64"
4066 return (WORDS_BIG_ENDIAN)
4067 ?
\"mulhwu %
0,%
1,%
2\;mullw %L0,%
1,%
2\"
4068 :
\"mulhwu %L0,%
1,%
2\;mullw %
0,%
1,%
2\";
4070 [(set_attr "type" "imul")
4071 (set_attr "length" "
8")])
4074 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4075 (mult:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
4076 (zero_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
4077 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
4080 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup
1))
4081 (zero_extend:DI (match_dup
2)))
4084 (mult:SI (match_dup
1)
4088 int endian = (WORDS_BIG_ENDIAN ==
0);
4089 operands[
3] = operand_subword (operands[
0], endian,
0, DImode);
4090 operands[
4] = operand_subword (operands[
0],
1 - endian,
0, DImode);
4093 (define_expand "smulsi3_highpart"
4094 [(set (match_operand:SI
0 "gpc_reg_operand" "")
4096 (lshiftrt:DI (mult:DI (sign_extend:DI
4097 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4099 (match_operand:SI
2 "gpc_reg_operand" "r")))
4104 if (! TARGET_POWER && ! TARGET_POWERPC)
4106 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
4107 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
4108 emit_insn (gen_mulh_call ());
4109 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
4112 else if (TARGET_POWER)
4114 emit_insn (gen_smulsi3_highpart_mq (operands[
0], operands[
1], operands[
2]));
4119 (define_insn "smulsi3_highpart_mq"
4120 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4122 (lshiftrt:DI (mult:DI (sign_extend:DI
4123 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4125 (match_operand:SI
2 "gpc_reg_operand" "r")))
4127 (clobber (match_scratch:SI
3 "=q"))]
4130 [(set_attr "type" "imul")])
4133 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4135 (lshiftrt:DI (mult:DI (sign_extend:DI
4136 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4138 (match_operand:SI
2 "gpc_reg_operand" "r")))
4142 [(set_attr "type" "imul")])
4144 (define_insn "umulsi3_highpart"
4145 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4147 (lshiftrt:DI (mult:DI (zero_extend:DI
4148 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4150 (match_operand:SI
2 "gpc_reg_operand" "r")))
4154 [(set_attr "type" "imul")])
4156 ;; If operands
0 and
2 are in the same register, we have a problem. But
4157 ;; operands
0 and
1 (the usual case) can be in the same register. That's
4158 ;; why we have the strange constraints below.
4159 (define_insn "ashldi3_power"
4160 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r,&r")
4161 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
4162 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
4163 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
4166 {sli|slwi} %
0,%L1,%h2\;{cal %L0,
0(
0)|li %L0,
0}
4167 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
4168 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
4169 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2"
4170 [(set_attr "length" "
8")])
4172 (define_insn "lshrdi3_power"
4173 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r,r,&r")
4174 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
4175 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
4176 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
4179 {cal %
0,
0(
0)|li %
0,
0}\;{s%A2i|s%A2wi} %L0,%
1,%h2
4180 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
4181 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
4182 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2"
4183 [(set_attr "length" "
8")])
4185 ;; Shift by a variable amount is too complex to be worth open-coding. We
4186 ;; just handle shifts by constants.
4187 (define_insn "ashrdi3_power"
4188 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4189 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r")
4190 (match_operand:SI
2 "const_int_operand" "M,i")))
4191 (clobber (match_scratch:SI
3 "=X,q"))]
4194 {srai|srawi} %
0,%
1,
31\;{srai|srawi} %L0,%
1,%h2
4195 sraiq %
0,%
1,%h2\;srliq %L0,%L1,%h2"
4196 [(set_attr "length" "
8")])
4198 ;; PowerPC64 DImode operations.
4200 (define_expand "adddi3"
4201 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4202 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "")
4203 (match_operand:DI
2 "add_operand" "")))]
4207 if (! TARGET_POWERPC64 && non_short_cint_operand (operands[
2], DImode))
4211 ;; Discourage ai/addic because of carry but provide it in an alternative
4212 ;; allowing register zero as source.
4215 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,?r,r")
4216 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,b,r,b")
4217 (match_operand:DI
2 "add_operand" "r,I,I,J")))]
4226 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
4227 (compare:CC (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
4228 (match_operand:DI
2 "reg_or_short_operand" "r,I"))
4230 (clobber (match_scratch:DI
3 "=r,r"))]
4235 [(set_attr "type" "compare")])
4238 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
4239 (compare:CC (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
4240 (match_operand:DI
2 "reg_or_short_operand" "r,I"))
4242 (set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4243 (plus:DI (match_dup
1) (match_dup
2)))]
4248 [(set_attr "type" "compare")])
4250 ;; Split an add that we can't do in one insn into two insns, each of which
4251 ;; does one
16-bit part. This is used by combine. Note that the low-order
4252 ;; add should be last in case the result gets used in an address.
4255 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4256 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "")
4257 (match_operand:DI
2 "non_add_cint_operand" "")))]
4259 [(set (match_dup
0) (plus:DI (match_dup
1) (match_dup
3)))
4260 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
4)))]
4263 HOST_WIDE_INT low = INTVAL (operands[
2]) &
0xffff;
4264 HOST_WIDE_INT high = INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff);
4267 high+=
0x10000, low |= ((HOST_WIDE_INT) -
1) <<
16;
4269 operands[
3] = GEN_INT (high);
4270 operands[
4] = GEN_INT (low);
4273 (define_insn "one_cmpldi2"
4274 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4275 (not:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4280 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4281 (compare:CC (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4283 (clobber (match_scratch:DI
2 "=r"))]
4286 [(set_attr "type" "compare")])
4289 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
4290 (compare:CC (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4292 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4293 (not:DI (match_dup
1)))]
4296 [(set_attr "type" "compare")])
4299 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4300 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I")
4301 (match_operand:DI
2 "gpc_reg_operand" "r,r")))]
4308 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4309 (compare:CC (minus:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4310 (match_operand:DI
2 "gpc_reg_operand" "r"))
4312 (clobber (match_scratch:DI
3 "=r"))]
4315 [(set_attr "type" "compare")])
4318 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4319 (compare:CC (minus:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4320 (match_operand:DI
2 "gpc_reg_operand" "r"))
4322 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4323 (minus:DI (match_dup
1) (match_dup
2)))]
4326 [(set_attr "type" "compare")])
4328 (define_expand "subdi3"
4329 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4330 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "")
4331 (match_operand:DI
2 "reg_or_cint_operand" "")))]
4335 if (GET_CODE (operands[
2]) == CONST_INT)
4337 emit_insn (gen_adddi3 (operands[
0], operands[
1],
4338 negate_rtx (DImode, operands[
2])));
4343 (define_insn "absdi2"
4344 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4345 (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))
4346 (clobber (match_scratch:DI
2 "=&r,&r"))]
4348 "sradi %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
2,%
0"
4349 [(set_attr "length" "
12")])
4352 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4353 (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))
4354 (clobber (match_scratch:DI
2 "=&r,&r"))]
4355 "TARGET_POWERPC64 && reload_completed"
4356 [(set (match_dup
2) (ashiftrt:DI (match_dup
1) (const_int
31)))
4357 (set (match_dup
0) (xor:DI (match_dup
2) (match_dup
1)))
4358 (set (match_dup
0) (minus:DI (match_dup
2) (match_dup
0)))]
4362 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4363 (neg:DI (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0"))))
4364 (clobber (match_scratch:DI
2 "=&r,&r"))]
4366 "sradi %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
0,%
2"
4367 [(set_attr "length" "
12")])
4370 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4371 (neg:DI (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0"))))
4372 (clobber (match_scratch:DI
2 "=&r,&r"))]
4373 "TARGET_POWERPC64 && reload_completed"
4374 [(set (match_dup
2) (ashiftrt:DI (match_dup
1) (const_int
31)))
4375 (set (match_dup
0) (xor:DI (match_dup
2) (match_dup
1)))
4376 (set (match_dup
0) (minus:DI (match_dup
0) (match_dup
2)))]
4379 (define_expand "negdi2"
4380 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4381 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "")))]
4386 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4387 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4392 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4393 (compare:CC (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4395 (clobber (match_scratch:DI
2 "=r"))]
4398 [(set_attr "type" "compare")])
4401 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
4402 (compare:CC (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4404 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4405 (neg:DI (match_dup
1)))]
4408 [(set_attr "type" "compare")])
4410 (define_insn "ffsdi2"
4411 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
4412 (ffs:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4414 "neg %
0,%
1\;and %
0,%
0,%
1\;cntlzd %
0,%
0\;subfic %
0,%
0,
64"
4415 [(set_attr "length" "
16")])
4417 (define_insn "muldi3"
4418 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4419 (mult:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4420 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4423 [(set_attr "type" "imul")])
4425 (define_insn "smuldi3_highpart"
4426 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4428 (lshiftrt:TI (mult:TI (sign_extend:TI
4429 (match_operand:DI
1 "gpc_reg_operand" "%r"))
4431 (match_operand:DI
2 "gpc_reg_operand" "r")))
4435 [(set_attr "type" "imul")])
4437 (define_insn "umuldi3_highpart"
4438 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4440 (lshiftrt:TI (mult:TI (zero_extend:TI
4441 (match_operand:DI
1 "gpc_reg_operand" "%r"))
4443 (match_operand:DI
2 "gpc_reg_operand" "r")))
4447 [(set_attr "type" "imul")])
4449 (define_expand "divdi3"
4450 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4451 (div:DI (match_operand:DI
1 "gpc_reg_operand" "")
4452 (match_operand:DI
2 "reg_or_cint_operand" "")))]
4456 if (GET_CODE (operands[
2]) == CONST_INT
4457 && exact_log2 (INTVAL (operands[
2])) >=
0)
4460 operands[
2] = force_reg (DImode, operands[
2]);
4463 (define_expand "moddi3"
4464 [(use (match_operand:DI
0 "gpc_reg_operand" ""))
4465 (use (match_operand:DI
1 "gpc_reg_operand" ""))
4466 (use (match_operand:DI
2 "reg_or_cint_operand" ""))]
4470 int i = exact_log2 (INTVAL (operands[
2]));
4474 if (GET_CODE (operands[
2]) != CONST_INT || i <
0)
4477 temp1 = gen_reg_rtx (DImode);
4478 temp2 = gen_reg_rtx (DImode);
4480 emit_insn (gen_divdi3 (temp1, operands[
1], operands[
2]));
4481 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
4482 emit_insn (gen_subdi3 (operands[
0], operands[
1], temp2));
4487 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4488 (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4489 (match_operand:DI
2 "const_int_operand" "N")))]
4490 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4491 "sradi %
0,%
1,%p2\;addze %
0,%
0"
4492 [(set_attr "length" "
8")])
4495 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4496 (compare:CC (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4497 (match_operand:DI
2 "const_int_operand" "N"))
4499 (clobber (match_scratch:DI
3 "=r"))]
4500 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4501 "sradi %
3,%
1,%p2\;addze. %
3,%
3"
4502 [(set_attr "type" "compare")
4503 (set_attr "length" "
8")])
4506 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4507 (compare:CC (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4508 (match_operand:DI
2 "const_int_operand" "N"))
4510 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4511 (div:DI (match_dup
1) (match_dup
2)))]
4512 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4513 "sradi %
0,%
1,%p2\;addze. %
0,%
0"
4514 [(set_attr "type" "compare")
4515 (set_attr "length" "
8")])
4518 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4519 (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4520 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4523 [(set_attr "type" "idiv")])
4525 (define_insn "udivdi3"
4526 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4527 (udiv:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4528 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4531 [(set_attr "type" "idiv")])
4533 (define_insn "rotldi3"
4534 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4535 (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4536 (match_operand:DI
2 "reg_or_cint_operand" "ri")))]
4538 "rld%I2cl %
0,%
1,%H2,
0")
4541 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4542 (compare:CC (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4543 (match_operand:DI
2 "reg_or_cint_operand" "ri"))
4545 (clobber (match_scratch:DI
3 "=r"))]
4547 "rld%I2cl. %
3,%
1,%H2,
0"
4548 [(set_attr "type" "delayed_compare")])
4551 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4552 (compare:CC (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4553 (match_operand:DI
2 "reg_or_cint_operand" "ri"))
4555 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4556 (rotate:DI (match_dup
1) (match_dup
2)))]
4558 "rld%I2cl. %
0,%
1,%H2,
0"
4559 [(set_attr "type" "delayed_compare")])
4561 (define_expand "ashldi3"
4562 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4563 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "")
4564 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4565 "TARGET_POWERPC64 || TARGET_POWER"
4568 if (TARGET_POWERPC64)
4570 else if (TARGET_POWER)
4572 emit_insn (gen_ashldi3_power (operands[
0], operands[
1], operands[
2]));
4580 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4581 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4582 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4585 [(set_attr "length" "
8")])
4588 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4589 (compare:CC (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4590 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4592 (clobber (match_scratch:DI
3 "=r"))]
4595 [(set_attr "type" "delayed_compare")])
4598 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4599 (compare:CC (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4600 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4602 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4603 (ashift:DI (match_dup
1) (match_dup
2)))]
4606 [(set_attr "type" "delayed_compare")])
4608 (define_expand "lshrdi3"
4609 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4610 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "")
4611 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4612 "TARGET_POWERPC64 || TARGET_POWER"
4615 if (TARGET_POWERPC64)
4617 else if (TARGET_POWER)
4619 emit_insn (gen_lshrdi3_power (operands[
0], operands[
1], operands[
2]));
4627 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4628 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4629 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4634 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4635 (compare:CC (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4636 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4638 (clobber (match_scratch:DI
3 "=r"))]
4641 [(set_attr "type" "delayed_compare")])
4644 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4645 (compare:CC (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4646 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4648 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4649 (lshiftrt:DI (match_dup
1) (match_dup
2)))]
4652 [(set_attr "type" "delayed_compare")])
4654 (define_expand "ashrdi3"
4655 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4656 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "")
4657 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4658 "TARGET_POWERPC64 || TARGET_POWER"
4661 if (TARGET_POWERPC64)
4663 else if (TARGET_POWER && GET_CODE (operands[
2]) == CONST_INT)
4665 emit_insn (gen_ashrdi3_power (operands[
0], operands[
1], operands[
2]));
4673 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4674 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4675 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4677 "srad%I2 %
0,%
1,%H2")
4680 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4681 (compare:CC (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4682 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4684 (clobber (match_scratch:DI
3 "=r"))]
4686 "srad%I2. %
3,%
1,%H2"
4687 [(set_attr "type" "delayed_compare")])
4690 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4691 (compare:CC (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4692 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4694 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4695 (ashiftrt:DI (match_dup
1) (match_dup
2)))]
4697 "srad%I2. %
0,%
1,%H2"
4698 [(set_attr "type" "delayed_compare")])
4700 (define_insn "anddi3"
4701 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4702 (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4703 (match_operand:DI
2 "and_operand" "?r,K,J")))
4704 (clobber (match_scratch:CC
3 "=X,x,x"))]
4712 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x")
4713 (compare:CC (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4714 (match_operand:DI
2 "and_operand" "r,K,J"))
4716 (clobber (match_scratch:DI
3 "=r,r,r"))]
4722 [(set_attr "type" "compare,compare,compare")])
4725 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x")
4726 (compare:CC (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4727 (match_operand:DI
2 "and_operand" "r,K,J"))
4729 (set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4730 (and:DI (match_dup
1) (match_dup
2)))]
4736 [(set_attr "type" "compare,compare,compare")])
4738 ;; Take a AND with a constant that cannot be done in a single insn and try to
4739 ;; split it into two insns. This does not verify that the insns are valid
4740 ;; since this need not be done as combine will do it.
4743 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4744 (and:DI (match_operand:DI
1 "gpc_reg_operand" "")
4745 (match_operand:DI
2 "non_and_cint_operand" "")))]
4747 [(set (match_dup
0) (and:DI (match_dup
1) (match_dup
3)))
4748 (set (match_dup
0) (and:DI (match_dup
0) (match_dup
4)))]
4751 int maskval = INTVAL (operands[
2]);
4752 int i, transitions, last_bit_value;
4753 int orig = maskval, first_c = maskval, second_c;
4755 /* We know that MASKVAL must have more than
2 bit-transitions. Start at
4756 the low-order bit and count for the third transition. When we get there,
4757 make a first mask that has everything to the left of that position
4758 a one. Then make the second mask to turn off whatever else is needed. */
4760 for (i =
1, transitions =
0, last_bit_value = maskval &
1; i <
32; i++)
4762 if (((maskval >>=
1) &
1) != last_bit_value)
4763 last_bit_value ^=
1, transitions++;
4765 if (transitions >
2)
4767 first_c |= (~
0) << i;
4772 second_c = orig | ~ first_c;
4774 operands[
3] = gen_rtx (CONST_INT, VOIDmode, first_c);
4775 operands[
4] = gen_rtx (CONST_INT, VOIDmode, second_c);
4778 (define_insn "iordi3"
4779 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4780 (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4781 (match_operand:DI
2 "logical_operand" "r,K,J")))]
4789 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4790 (compare:CC (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4791 (match_operand:DI
2 "gpc_reg_operand" "r"))
4793 (clobber (match_scratch:DI
3 "=r"))]
4796 [(set_attr "type" "compare")])
4799 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4800 (compare:CC (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4801 (match_operand:DI
2 "gpc_reg_operand" "r"))
4803 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4804 (ior:DI (match_dup
1) (match_dup
2)))]
4807 [(set_attr "type" "compare")])
4809 ;; Split an IOR that we can't do in one insn into two insns, each of which
4810 ;; does one
16-bit part. This is used by combine.
4813 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4814 (ior:DI (match_operand:DI
1 "gpc_reg_operand" "")
4815 (match_operand:DI
2 "non_logical_cint_operand" "")))]
4817 [(set (match_dup
0) (ior:DI (match_dup
1) (match_dup
3)))
4818 (set (match_dup
0) (ior:DI (match_dup
0) (match_dup
4)))]
4821 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
4822 INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff));
4823 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
4826 (define_insn "xordi3"
4827 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4828 (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4829 (match_operand:DI
2 "logical_operand" "r,K,J")))]
4837 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4838 (compare:CC (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4839 (match_operand:DI
2 "gpc_reg_operand" "r"))
4841 (clobber (match_scratch:DI
3 "=r"))]
4844 [(set_attr "type" "compare")])
4847 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4848 (compare:CC (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4849 (match_operand:DI
2 "gpc_reg_operand" "r"))
4851 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4852 (xor:DI (match_dup
1) (match_dup
2)))]
4855 [(set_attr "type" "compare")])
4857 ;; Split an XOR that we can't do in one insn into two insns, each of which
4858 ;; does one
16-bit part. This is used by combine.
4861 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4862 (xor:DI (match_operand:DI
1 "gpc_reg_operand" "")
4863 (match_operand:DI
2 "non_logical_cint_operand" "")))]
4865 [(set (match_dup
0) (xor:DI (match_dup
1) (match_dup
3)))
4866 (set (match_dup
0) (xor:DI (match_dup
0) (match_dup
4)))]
4869 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
4870 INTVAL (operands[
2]) &
0xffff0000);
4871 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
4875 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4876 (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4877 (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4882 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4883 (compare:CC (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4884 (match_operand:DI
2 "gpc_reg_operand" "r")))
4886 (clobber (match_scratch:DI
3 "=r"))]
4889 [(set_attr "type" "compare")])
4892 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4893 (compare:CC (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4894 (match_operand:DI
2 "gpc_reg_operand" "r")))
4896 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4897 (not:DI (xor:DI (match_dup
1) (match_dup
2))))]
4900 [(set_attr "type" "compare")])
4903 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4904 (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4905 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4910 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4911 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4912 (match_operand:DI
2 "gpc_reg_operand" "r"))
4914 (clobber (match_scratch:DI
3 "=r"))]
4917 [(set_attr "type" "compare")])
4920 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4921 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4922 (match_operand:DI
2 "gpc_reg_operand" "r"))
4924 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4925 (and:DI (not:DI (match_dup
1)) (match_dup
2)))]
4928 [(set_attr "type" "compare")])
4931 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4932 (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4933 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4938 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4939 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4940 (match_operand:DI
2 "gpc_reg_operand" "r"))
4942 (clobber (match_scratch:DI
3 "=r"))]
4945 [(set_attr "type" "compare")])
4948 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4949 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4950 (match_operand:DI
2 "gpc_reg_operand" "r"))
4952 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4953 (ior:DI (not:DI (match_dup
1)) (match_dup
2)))]
4956 [(set_attr "type" "compare")])
4959 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4960 (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4961 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4966 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4967 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4968 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4970 (clobber (match_scratch:DI
3 "=r"))]
4973 [(set_attr "type" "compare")])
4976 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4977 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4978 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4980 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4981 (ior:DI (not:DI (match_dup
1)) (not:DI (match_dup
2))))]
4984 [(set_attr "type" "compare")])
4987 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4988 (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4989 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4994 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4995 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4996 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4998 (clobber (match_scratch:DI
3 "=r"))]
5001 [(set_attr "type" "compare")])
5004 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
5005 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
5006 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
5008 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
5009 (and:DI (not:DI (match_dup
1)) (not:DI (match_dup
2))))]
5012 [(set_attr "type" "compare")])
5014 ;; Now define ways of moving data around.
5016 ;; Elf specific ways of loading addresses for non-PIC code.
5017 ;; The output of this could be r0, but we limit it to base
5018 ;; registers, since almost all uses of this will need it
5019 ;; in a base register shortly.
5020 (define_insn "elf_high"
5021 [(set (match_operand:SI
0 "register_operand" "=b")
5022 (high:SI (match_operand
1 "" "")))]
5023 "TARGET_ELF && !TARGET_64BIT"
5024 "{cau|addis} %
0,
0,%
1@ha")
5026 (define_insn "elf_low"
5027 [(set (match_operand:SI
0 "register_operand" "=r")
5028 (lo_sum:SI (match_operand:SI
1 "register_operand" "b")
5029 (match_operand
2 "" "")))]
5030 "TARGET_ELF && !TARGET_64BIT"
5031 "{cal %
0,%a2@l(%
1)|addi %
0,%
1,%
2@l}")
5033 ;; Set up a register with a value from the GOT table
5035 (define_expand "movsi_got"
5036 [(set (match_operand:SI
0 "register_operand" "")
5037 (unspec [(match_operand:SI
1 "got_operand" "")
5039 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic ==
1"
5042 operands[
2] = rs6000_got_register (operands[
1]);
5045 (define_insn "*movsi_got_internal"
5046 [(set (match_operand:SI
0 "register_operand" "=r")
5047 (unspec [(match_operand:SI
1 "got_operand" "")
5048 (match_operand:SI
2 "register_operand" "b")]
8))]
5049 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic ==
1"
5050 "{l|lwz} %
0,%a1@got(%
2)"
5051 [(set_attr "type" "load")])
5053 ;; For SI, we special-case integers that can't be loaded in one insn. We
5054 ;; do the load
16-bits at a time. We could do this by loading from memory,
5055 ;; and this is even supposed to be faster, but it is simpler not to get
5056 ;; integers in the TOC.
5057 (define_expand "movsi"
5058 [(set (match_operand:SI
0 "general_operand" "")
5059 (match_operand:SI
1 "any_operand" ""))]
5063 if (GET_CODE (operands[
0]) != REG)
5064 operands[
1] = force_reg (SImode, operands[
1]);
5066 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
5067 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
5068 operands[
1] = GEN_INT (CONST_DOUBLE_LOW (operands[
1]));
5070 /* Use default pattern for address of ELF small data */
5072 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5073 && (GET_CODE (operands[
1]) == SYMBOL_REF || GET_CODE (operands[
1]) == CONST)
5074 && small_data_operand (operands[
1], SImode))
5076 emit_insn (gen_rtx (SET, VOIDmode, operands[
0], operands[
1]));
5080 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5081 && flag_pic ==
1 && got_operand (operands[
1], SImode))
5083 emit_insn (gen_movsi_got (operands[
0], operands[
1]));
5087 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
5089 && CONSTANT_P (operands[
1])
5090 && GET_CODE (operands[
1]) != HIGH
5091 && GET_CODE (operands[
1]) != CONST_INT)
5093 rtx target = (reload_completed || reload_in_progress)
5094 ? operands[
0] : gen_reg_rtx (SImode);
5096 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
5097 convert it to the address of the descriptor. */
5098 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
5099 && GET_CODE (operands[
1]) == SYMBOL_REF
5100 && XSTR (operands[
1],
0)[
0] == '.')
5102 char *name = XSTR (operands[
1],
0);
5104 while (*name == '.')
5106 new_ref = gen_rtx (SYMBOL_REF, Pmode, name);
5107 CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[
1]);
5108 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[
1]);
5109 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[
1]);
5110 operands[
1] = new_ref;
5113 emit_insn (gen_elf_high (target, operands[
1]));
5114 emit_insn (gen_elf_low (operands[
0], target, operands[
1]));
5118 if (GET_CODE (operands[
1]) == CONST
5119 && DEFAULT_ABI == ABI_NT
5120 && !side_effects_p (operands[
0]))
5122 rtx const_term = const0_rtx;
5123 rtx sym = eliminate_constant_term (XEXP (operands[
1],
0), &const_term);
5124 if (sym && GET_CODE (const_term) == CONST_INT
5125 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
5127 unsigned HOST_WIDE_INT value = INTVAL (const_term);
5128 int new_reg_p = (flag_expensive_optimizations
5129 && !reload_completed
5130 && !reload_in_progress);
5131 rtx tmp1 = (new_reg_p && value !=
0) ? gen_reg_rtx (SImode) : operands[
0];
5133 emit_insn (gen_movsi (tmp1, sym));
5134 if (INTVAL (const_term) !=
0)
5136 if (value +
0x8000 <
0x10000)
5137 emit_insn (gen_addsi3 (operands[
0], tmp1, GEN_INT (value)));
5141 HOST_WIDE_INT high_int = value & (~ (HOST_WIDE_INT)
0xffff);
5142 HOST_WIDE_INT low_int = value &
0xffff;
5143 rtx tmp2 = (!new_reg_p || !low_int) ? operands[
0] : gen_reg_rtx (Pmode);
5145 if (low_int &
0x8000)
5146 high_int +=
0x10000, low_int |= ((HOST_WIDE_INT) -
1) <<
16;
5148 emit_insn (gen_addsi3 (tmp2, tmp1, GEN_INT (high_int)));
5150 emit_insn (gen_addsi3 (operands[
0], tmp2, GEN_INT (low_int)));
5156 fatal_insn (
\"bad address
\", operands[
1]);
5159 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
5160 && CONSTANT_P (operands[
1])
5161 && GET_CODE (operands[
1]) != CONST_INT
5162 && GET_CODE (operands[
1]) != HIGH
5163 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[
1]))
5165 /* Emit a USE operation so that the constant isn't deleted if
5166 expensive optimizations are turned on because nobody
5167 references it. This should only be done for operands that
5168 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
5169 This should not be done for operands that contain LABEL_REFs.
5170 For now, we just handle the obvious case. */
5171 if (GET_CODE (operands[
1]) != LABEL_REF)
5172 emit_insn (gen_rtx (USE, VOIDmode, operands[
1]));
5174 /* If we are to limit the number of things we put in the TOC and
5175 this is a symbol plus a constant we can add in one insn,
5176 just put the symbol in the TOC and add the constant. Don't do
5177 this if reload is in progress. */
5178 if (GET_CODE (operands[
1]) == CONST
5179 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5180 && GET_CODE (XEXP (operands[
1],
0)) == PLUS
5181 && add_operand (XEXP (XEXP (operands[
1],
0),
1), SImode)
5182 && (GET_CODE (XEXP (XEXP (operands[
1],
0),
0)) == LABEL_REF
5183 || GET_CODE (XEXP (XEXP (operands[
1],
0),
0)) == SYMBOL_REF)
5184 && ! side_effects_p (operands[
0]))
5186 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[
1],
0),
0));
5187 rtx other = XEXP (XEXP (operands[
1],
0),
1);
5189 emit_insn (gen_addsi3 (operands[
0], force_reg (SImode, sym), other));
5193 operands[
1] = force_const_mem (SImode, operands[
1]);
5194 if (! memory_address_p (SImode, XEXP (operands[
1],
0))
5195 && ! reload_in_progress)
5196 operands[
1] = change_address (operands[
1], SImode,
5197 XEXP (operands[
1],
0));
5202 [(set (match_operand:SI
0 "nonimmediate_operand" "=r,r,r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
5203 (match_operand:SI
1 "input_operand" "r,S,T,U,m,r,I,J,n,R,*h,r,r,
0"))]
5204 "gpc_reg_operand (operands[
0], SImode)
5205 || gpc_reg_operand (operands[
1], SImode)"
5208 {l|lwz} %
0,[toc]%
1(
2)
5209 {l|lwz} %
0,[toc]%l1(
2)
5211 {l%U1%X1|lwz%U1%X1} %
0,%
1
5212 {st%U0%X0|stw%U0%X0} %
1,%
0
5221 [(set_attr "type" "*,load,load,*,load,store,*,*,*,*,*,*,mtjmpr,*")
5222 (set_attr "length" "
4,
4,
4,
4,
4,
4,
4,
4,
8,
4,
4,
4,
4,
4")])
5224 ;; Split a load of a large constant into the appropriate two-insn
5228 [(set (match_operand:SI
0 "gpc_reg_operand" "")
5229 (match_operand:SI
1 "const_int_operand" ""))]
5230 "(unsigned) (INTVAL (operands[
1]) +
0x8000) >=
0x10000
5231 && (INTVAL (operands[
1]) &
0xffff) !=
0"
5235 (ior:SI (match_dup
0)
5239 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
5240 INTVAL (operands[
1]) &
0xffff0000);
5241 operands[
3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
1]) &
0xffff);
5245 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
5246 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
5248 (set (match_operand:SI
0 "gpc_reg_operand" "=r") (match_dup
1))]
5251 [(set_attr "type" "compare")])
5253 (define_expand "movhi"
5254 [(set (match_operand:HI
0 "general_operand" "")
5255 (match_operand:HI
1 "any_operand" ""))]
5259 if (GET_CODE (operands[
0]) != REG)
5260 operands[
1] = force_reg (HImode, operands[
1]);
5262 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
5264 operands[
1] = force_const_mem (HImode, operands[
1]);
5265 if (! memory_address_p (HImode, XEXP (operands[
1],
0))
5266 && ! reload_in_progress)
5267 operands[
1] = change_address (operands[
1], HImode,
5268 XEXP (operands[
1],
0));
5273 [(set (match_operand:HI
0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5274 (match_operand:HI
1 "input_operand" "r,m,r,i,*h,r,r,
0"))]
5275 "gpc_reg_operand (operands[
0], HImode)
5276 || gpc_reg_operand (operands[
1], HImode)"
5286 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5288 (define_expand "movqi"
5289 [(set (match_operand:QI
0 "general_operand" "")
5290 (match_operand:QI
1 "any_operand" ""))]
5294 if (GET_CODE (operands[
0]) != REG)
5295 operands[
1] = force_reg (QImode, operands[
1]);
5297 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
5299 operands[
1] = force_const_mem (QImode, operands[
1]);
5300 if (! memory_address_p (QImode, XEXP (operands[
1],
0))
5301 && ! reload_in_progress)
5302 operands[
1] = change_address (operands[
1], QImode,
5303 XEXP (operands[
1],
0));
5308 [(set (match_operand:QI
0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5309 (match_operand:QI
1 "input_operand" "r,m,r,i,*h,r,r,
0"))]
5310 "gpc_reg_operand (operands[
0], QImode)
5311 || gpc_reg_operand (operands[
1], QImode)"
5321 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5323 ;; Here is how to move condition codes around. When we store CC data in
5324 ;; an integer register or memory, we store just the high-order
4 bits.
5325 ;; This lets us not shift in the most common case of CR0.
5326 (define_expand "movcc"
5327 [(set (match_operand:CC
0 "nonimmediate_operand" "")
5328 (match_operand:CC
1 "nonimmediate_operand" ""))]
5333 [(set (match_operand:CC
0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
5334 (match_operand:CC
1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
5335 "register_operand (operands[
0], CCmode)
5336 || register_operand (operands[
1], CCmode)"
5340 {rlinm|rlwinm} %
1,%
1,%F0,
0xffffffff\;mtcrf %R0,%
1\;{rlinm|rlwinm} %
1,%
1,%f0,
0xffffffff
5342 mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%f1,
0xf0000000
5344 {l%U1%X1|lwz%U1%X1} %
0,%
1
5345 {st%U0%U1|stw%U0%U1} %
1,%
0"
5346 [(set_attr "type" "*,*,*,compare,*,*,load,store")
5347 (set_attr "length" "*,*,
12,*,
8,*,*,*")])
5349 ;; For floating-point, we normally deal with the floating-point registers
5350 ;; unless -msoft-float is used. The sole exception is that parameter passing
5351 ;; can produce floating-point values in fixed-point registers. Unless the
5352 ;; value is a simple constant or already in memory, we deal with this by
5353 ;; allocating memory and copying the value explicitly via that memory location.
5354 (define_expand "movsf"
5355 [(set (match_operand:SF
0 "nonimmediate_operand" "")
5356 (match_operand:SF
1 "any_operand" ""))]
5360 /* If we are called from reload, we might be getting a SUBREG of a hard
5361 reg. So expand it. */
5362 if (GET_CODE (operands[
0]) == SUBREG
5363 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5364 && REGNO (SUBREG_REG (operands[
0])) < FIRST_PSEUDO_REGISTER)
5365 operands[
0] = alter_subreg (operands[
0]);
5366 if (GET_CODE (operands[
1]) == SUBREG
5367 && GET_CODE (SUBREG_REG (operands[
1])) == REG
5368 && REGNO (SUBREG_REG (operands[
1])) < FIRST_PSEUDO_REGISTER)
5369 operands[
1] = alter_subreg (operands[
1]);
5371 if (TARGET_SOFT_FLOAT && GET_CODE (operands[
0]) == MEM)
5372 operands[
1] = force_reg (SFmode, operands[
1]);
5374 else if (TARGET_HARD_FLOAT)
5376 if (GET_CODE (operands[
1]) == REG && REGNO (operands[
1]) <
32)
5378 /* If this is a store to memory or another integer register do the
5379 move directly. Otherwise store to a temporary stack slot and
5380 load from there into a floating point register. */
5382 if (GET_CODE (operands[
0]) == MEM
5383 || (GET_CODE (operands[
0]) == REG
5384 && (REGNO (operands[
0]) <
32
5385 || (reload_in_progress
5386 && REGNO (operands[
0]) >= FIRST_PSEUDO_REGISTER))))
5388 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
5389 operand_subword (operands[
1],
0,
0, SFmode));
5394 rtx stack_slot = assign_stack_temp (SFmode,
4,
0);
5396 emit_move_insn (stack_slot, operands[
1]);
5397 emit_move_insn (operands[
0], stack_slot);
5402 if (GET_CODE (operands[
0]) == MEM)
5404 /* If operands[
1] is a register, it may have double-precision data
5405 in it, so truncate it to single precision. We need not do
5406 this for POWERPC. */
5407 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
5408 && GET_CODE (operands[
1]) == REG)
5411 = reload_in_progress ? operands[
1] : gen_reg_rtx (SFmode);
5412 emit_insn (gen_aux_truncdfsf2 (newreg, operands[
1]));
5413 operands[
1] = newreg;
5416 operands[
1] = force_reg (SFmode, operands[
1]);
5419 if (GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <
32)
5421 if (GET_CODE (operands[
1]) == MEM
5422 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
5423 || GET_CODE (operands[
1]) == CONST_DOUBLE
5425 || (GET_CODE (operands[
1]) == REG
5426 && (REGNO (operands[
1]) <
32
5427 || (reload_in_progress
5428 && REGNO (operands[
1]) >= FIRST_PSEUDO_REGISTER))))
5430 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
5431 operand_subword (operands[
1],
0,
0, SFmode));
5436 rtx stack_slot = assign_stack_temp (SFmode,
4,
0);
5438 emit_move_insn (stack_slot, operands[
1]);
5439 emit_move_insn (operands[
0], stack_slot);
5445 if (CONSTANT_P (operands[
1]) && TARGET_HARD_FLOAT)
5447 operands[
1] = force_const_mem (SFmode, operands[
1]);
5448 if (! memory_address_p (SFmode, XEXP (operands[
1],
0))
5449 && ! reload_in_progress)
5450 operands[
1] = change_address (operands[
1], SFmode,
5451 XEXP (operands[
1],
0));
5456 [(set (match_operand:SF
0 "gpc_reg_operand" "")
5457 (match_operand:SF
1 "const_double_operand" ""))]
5458 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], SFmode) <=
1
5459 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5460 || (GET_CODE (operands[
0]) == SUBREG
5461 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5462 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5463 [(set (match_dup
2) (match_dup
3))]
5469 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[
1]);
5470 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5472 operands[
2] = operand_subword (operands[
0],
0,
0, SFmode);
5473 operands[
3] = GEN_INT(l);
5477 [(set (match_operand:SF
0 "gpc_reg_operand" "")
5478 (match_operand:SF
1 "const_double_operand" ""))]
5479 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], SFmode) ==
2
5480 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5481 || (GET_CODE (operands[
0]) == SUBREG
5482 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5483 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5484 [(set (match_dup
2) (match_dup
3))
5485 (set (match_dup
2) (ior:SI (match_dup
2) (match_dup
4)))]
5491 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[
1]);
5492 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5494 operands[
2] = operand_subword (operands[
0],
0,
0, SFmode);
5495 operands[
3] = GEN_INT(l &
0xffff0000);
5496 operands[
4] = GEN_INT(l &
0x0000ffff);
5499 (define_insn "*movsf_hardfloat"
5500 [(set (match_operand:SF
0 "nonimmediate_operand" "=f,f,m,!r,!r")
5501 (match_operand:SF
1 "input_operand" "f,m,f,G,Fn"))]
5502 "(gpc_reg_operand (operands[
0], SFmode)
5503 || gpc_reg_operand (operands[
1], SFmode)) && TARGET_HARD_FLOAT"
5510 [(set_attr "type" "fp,fpload,fpstore,*,*")
5511 (set_attr "length" "
4,
4,
4,
4,
8")])
5513 (define_insn "*movsf_softfloat"
5514 [(set (match_operand:SF
0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
5515 (match_operand:SF
1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
5516 "(gpc_reg_operand (operands[
0], SFmode)
5517 || gpc_reg_operand (operands[
1], SFmode)) && TARGET_SOFT_FLOAT"
5520 {l%U1%X1|lwz%U1%X1} %
0,%
1
5521 {st%U0%X0|stw%U0%X0} %
1,%
0
5527 [(set_attr "type" "*,load,store,*,*,*,*,*")
5528 (set_attr "length" "
4,
4,
4,
4,
4,
4,
4,
8")])
5531 (define_expand "movdf"
5532 [(set (match_operand:DF
0 "nonimmediate_operand" "")
5533 (match_operand:DF
1 "any_operand" ""))]
5537 if (GET_CODE (operands[
0]) != REG)
5538 operands[
1] = force_reg (DFmode, operands[
1]);
5540 /* Stores between FPR and any non-FPR registers must go through a
5541 temporary stack slot. */
5543 if (TARGET_POWERPC64
5544 && GET_CODE (operands[
0]) == REG && GET_CODE (operands[
1]) == REG
5545 && ((FP_REGNO_P (REGNO (operands[
0]))
5546 && ! FP_REGNO_P (REGNO (operands[
1])))
5547 || (FP_REGNO_P (REGNO (operands[
1]))
5548 && ! FP_REGNO_P (REGNO (operands[
0])))))
5550 rtx stack_slot = assign_stack_temp (DFmode,
8,
0);
5552 emit_move_insn (stack_slot, operands[
1]);
5553 emit_move_insn (operands[
0], stack_slot);
5557 if (CONSTANT_P (operands[
1]) && ! easy_fp_constant (operands[
1], DFmode))
5559 operands[
1] = force_const_mem (DFmode, operands[
1]);
5560 if (! memory_address_p (DFmode, XEXP (operands[
1],
0))
5561 && ! reload_in_progress)
5562 operands[
1] = change_address (operands[
1], DFmode,
5563 XEXP (operands[
1],
0));
5568 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5569 (match_operand:DF
1 "const_int_operand" ""))]
5570 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DFmode) <=
1
5571 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5572 || (GET_CODE (operands[
0]) == SUBREG
5573 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5574 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5575 [(set (match_dup
2) (match_dup
4))
5576 (set (match_dup
3) (match_dup
1))]
5579 int endian = (WORDS_BIG_ENDIAN ==
0);
5580 operands[
2] = operand_subword (operands[
0], endian,
0, DFmode);
5581 operands[
3] = operand_subword (operands[
0],
1 - endian,
0, DFmode);
5582 operands[
4] = (INTVAL (operands[
1]) &
0x80000000) ? constm1_rtx : const0_rtx;
5586 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5587 (match_operand:DF
1 "const_int_operand" ""))]
5588 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DFmode) >=
2
5589 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5590 || (GET_CODE (operands[
0]) == SUBREG
5591 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5592 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5593 [(set (match_dup
3) (match_dup
5))
5594 (set (match_dup
2) (match_dup
4))
5595 (set (match_dup
3) (ior:SI (match_dup
3) (match_dup
6)))]
5598 HOST_WIDE_INT value = INTVAL (operands[
1]);
5599 int endian = (WORDS_BIG_ENDIAN ==
0);
5600 operands[
2] = operand_subword (operands[
0], endian,
0, DFmode);
5601 operands[
3] = operand_subword (operands[
0],
1 - endian,
0, DFmode);
5602 operands[
4] = (value &
0x80000000) ? constm1_rtx : const0_rtx;
5603 operands[
5] = GEN_INT (value &
0xffff0000);
5604 operands[
6] = GEN_INT (value &
0x0000ffff);
5608 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5609 (match_operand:DF
1 "const_double_operand" ""))]
5610 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DFmode) <=
2
5611 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5612 || (GET_CODE (operands[
0]) == SUBREG
5613 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5614 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5615 [(set (match_dup
2) (match_dup
4))
5616 (set (match_dup
3) (match_dup
5))]
5619 int endian = (WORDS_BIG_ENDIAN ==
0);
5620 operands[
2] = operand_subword (operands[
0], endian,
0, DFmode);
5621 operands[
3] = operand_subword (operands[
0],
1 - endian,
0, DFmode);
5623 #ifdef HOST_WORDS_BIG_ENDIAN
5624 operands[
4] = GEN_INT (CONST_DOUBLE_LOW (operands[
1]));
5625 operands[
5] = GEN_INT (CONST_DOUBLE_HIGH (operands[
1]));
5627 operands[
4] = GEN_INT (CONST_DOUBLE_HIGH (operands[
1]));
5628 operands[
5] = GEN_INT (CONST_DOUBLE_LOW (operands[
1]));
5633 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5634 (match_operand:DF
1 "const_double_operand" ""))]
5635 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DFmode) ==
3
5636 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5637 || (GET_CODE (operands[
0]) == SUBREG
5638 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5639 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5640 [(set (match_dup
2) (match_dup
4))
5641 (set (match_dup
3) (match_dup
5))
5642 (set (match_dup
2) (ior:SI (match_dup
2) (match_dup
6)))]
5647 int endian = (WORDS_BIG_ENDIAN ==
0);
5648 rtx high_reg = operand_subword (operands[
0], endian,
0, DFmode);
5649 rtx low_reg = operand_subword (operands[
0],
1 - endian,
0, DFmode);
5651 #ifdef HOST_WORDS_BIG_ENDIAN
5652 high = CONST_DOUBLE_LOW (operands[
1]);
5653 low = CONST_DOUBLE_HIGH (operands[
1]);
5655 high = CONST_DOUBLE_HIGH (operands[
1]);
5656 low = CONST_DOUBLE_LOW (operands[
1]);
5659 if (((unsigned HOST_WIDE_INT) (low +
0x8000) <
0x10000)
5660 || (low &
0xffff) ==
0)
5662 operands[
2] = high_reg;
5663 operands[
3] = low_reg;
5664 operands[
4] = GEN_INT (high &
0xffff0000);
5665 operands[
5] = GEN_INT (low);
5666 operands[
6] = GEN_INT (high &
0x0000ffff);
5670 operands[
2] = low_reg;
5671 operands[
3] = high_reg;
5672 operands[
4] = GEN_INT (low &
0xffff0000);
5673 operands[
5] = GEN_INT (high);
5674 operands[
6] = GEN_INT (low &
0x0000ffff);
5679 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5680 (match_operand:DF
1 "const_double_operand" ""))]
5681 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DFmode) >=
4
5682 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5683 || (GET_CODE (operands[
0]) == SUBREG
5684 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5685 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5686 [(set (match_dup
2) (match_dup
4))
5687 (set (match_dup
3) (match_dup
5))
5688 (set (match_dup
2) (ior:SI (match_dup
2) (match_dup
6)))
5689 (set (match_dup
3) (ior:SI (match_dup
3) (match_dup
7)))]
5692 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[
1]);
5693 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[
1]);
5694 int endian = (WORDS_BIG_ENDIAN ==
0);
5696 operands[
2] = operand_subword (operands[
0], endian,
0, DFmode);
5697 operands[
3] = operand_subword (operands[
0],
1 - endian,
0, DFmode);
5698 operands[
4] = GEN_INT (high &
0xffff0000);
5699 operands[
5] = GEN_INT (low &
0xffff0000);
5700 operands[
6] = GEN_INT (high &
0x0000ffff);
5701 operands[
7] = GEN_INT (low &
0x0000ffff);
5705 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5706 (match_operand:DF
1 "easy_fp_constant" ""))]
5707 "TARGET_64BIT && reload_completed
5708 && ((GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <=
31)
5709 || (GET_CODE (operands[
0]) == SUBREG
5710 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5711 && REGNO (SUBREG_REG (operands[
0])) <=
31))"
5712 [(set (match_dup
2) (subreg:DI (match_dup
1)
0))]
5714 { operands[
2] = gen_lowpart (DImode, operands[
0]); }")
5716 ;; Don't have reload use general registers to load a constant. First,
5717 ;; it might not work if the output operand has is the equivalent of
5718 ;; a non-offsettable memref, but also it is less efficient than loading
5719 ;; the constant into an FP register, since it will probably be used there.
5720 ;; The "??" is a kludge until we can figure out a more reasonable way
5721 ;; of handling these non-offsettable values.
5722 (define_insn "*movdf_hardfloat32"
5723 [(set (match_operand:DF
0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
5724 (match_operand:DF
1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
5725 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
5726 && (register_operand (operands[
0], DFmode)
5727 || register_operand (operands[
1], DFmode))"
5730 switch (which_alternative)
5733 /* We normally copy the low-numbered register first. However, if
5734 the first register operand
0 is the same as the second register of
5735 operand
1, we must copy in the opposite order. */
5736 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5737 return
\"mr %L0,%L1\;mr %
0,%
1\";
5739 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5741 /* If the low-address word is used in the address, we must load it
5742 last. Otherwise, load it first. Note that we cannot have
5743 auto-increment in that case since the address register is known to be
5745 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5747 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5749 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5751 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5757 return
\"fmr %
0,%
1\";
5759 return
\"lfd%U1%X1 %
0,%
1\";
5761 return
\"stfd%U0%X0 %
1,%
0\";
5764 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
5765 (set_attr "length" "
8,
8,
8,
8,
12,
16,*,*,*")])
5767 (define_insn "*movdf_softfloat32"
5768 [(set (match_operand:DF
0 "nonimmediate_operand" "=r,r,o,r,r,r")
5769 (match_operand:DF
1 "input_operand" "r,o,r,G,H,F"))]
5770 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5771 && (register_operand (operands[
0], DFmode)
5772 || register_operand (operands[
1], DFmode))"
5775 switch (which_alternative)
5778 /* We normally copy the low-numbered register first. However, if
5779 the first register operand
0 is the same as the second register of
5780 operand
1, we must copy in the opposite order. */
5781 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5782 return
\"mr %L0,%L1\;mr %
0,%
1\";
5784 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5786 /* If the low-address word is used in the address, we must load it
5787 last. Otherwise, load it first. Note that we cannot have
5788 auto-increment in that case since the address register is known to be
5790 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5792 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5794 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5796 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5803 [(set_attr "type" "*,load,store,*,*,*")
5804 (set_attr "length" "
8,
8,
8,
8,
12,
16")])
5806 (define_insn "*movdf_hardfloat64"
5807 [(set (match_operand:DF
0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
5808 (match_operand:DF
1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
5809 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
5810 && (register_operand (operands[
0], DFmode)
5811 || register_operand (operands[
1], DFmode))"
5822 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
5823 (set_attr "length" "
4,
4,
4,
8,
12,
16,
4,
4,
4")])
5825 (define_insn "*movdf_softfloat64"
5826 [(set (match_operand:DF
0 "nonimmediate_operand" "=r,r,o,r,r,r")
5827 (match_operand:DF
1 "input_operand" "r,o,r,G,H,F"))]
5828 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5829 && (register_operand (operands[
0], DFmode)
5830 || register_operand (operands[
1], DFmode))"
5838 [(set_attr "type" "*,load,store,*,*,*")
5839 (set_attr "length" "*,*,*,
8,
12,
16")])
5841 ;; Next come the multi-word integer load and store and the load and store
5843 (define_expand "movdi"
5844 [(set (match_operand:DI
0 "general_operand" "")
5845 (match_operand:DI
1 "any_operand" ""))]
5849 if (GET_CODE (operands[
0]) != REG)
5850 operands[
1] = force_reg (DImode, operands[
1]);
5853 && (GET_CODE (operands[
1]) == CONST_DOUBLE
5854 || GET_CODE (operands[
1]) == CONST_INT))
5859 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
5861 low = CONST_DOUBLE_LOW (operands[
1]);
5862 high = CONST_DOUBLE_HIGH (operands[
1]);
5865 #if HOST_BITS_PER_WIDE_INT == 32
5867 low = INTVAL (operands[
1]);
5868 high = (low <
0) ? ~
0 :
0;
5872 low = INTVAL (operands[
1]) &
0xffffffff;
5873 high = (HOST_WIDE_INT) INTVAL (operands[
1]) >>
32;
5879 emit_move_insn (operands[
0], GEN_INT (high));
5880 emit_insn (gen_ashldi3 (operands[
0], operands[
0], GEN_INT(
32)));
5883 HOST_WIDE_INT low_low = low &
0xffff;
5884 HOST_WIDE_INT low_high = low & (~ (HOST_WIDE_INT)
0xffff);
5886 emit_insn (gen_iordi3 (operands[
0], operands[
0],
5887 GEN_INT (low_high)));
5889 emit_insn (gen_iordi3 (operands[
0], operands[
0],
5890 GEN_INT (low_low)));
5896 /* Stores between FPR and any non-FPR registers must go through a
5897 temporary stack slot. */
5899 if (GET_CODE (operands[
0]) == REG && GET_CODE (operands[
1]) == REG
5900 && ((FP_REGNO_P (REGNO (operands[
0]))
5901 && ! FP_REGNO_P (REGNO (operands[
1])))
5902 || (FP_REGNO_P (REGNO (operands[
1]))
5903 && ! FP_REGNO_P (REGNO (operands[
0])))))
5905 rtx stack_slot = assign_stack_temp (DImode,
8,
0);
5907 emit_move_insn (stack_slot, operands[
1]);
5908 emit_move_insn (operands[
0], stack_slot);
5913 (define_insn "*movdi_32"
5914 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
5915 (match_operand:DI
1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
5917 && (gpc_reg_operand (operands[
0], DImode)
5918 || gpc_reg_operand (operands[
1], DImode))"
5921 switch (which_alternative)
5924 /* We normally copy the low-numbered register first. However, if
5925 the first register operand
0 is the same as the second register of
5926 operand
1, we must copy in the opposite order. */
5927 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5928 return
\"mr %L0,%L1\;mr %
0,%
1\";
5930 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5932 /* If the low-address word is used in the address, we must load it
5933 last. Otherwise, load it first. Note that we cannot have
5934 auto-increment in that case since the address register is known to be
5936 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5938 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5940 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5942 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5944 return
\"fmr %
0,%
1\";
5946 return
\"lfd%U1%X1 %
0,%
1\";
5948 return
\"stfd%U0%X0 %
1,%
0\";
5957 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
5958 (set_attr "length" "
8,
8,
8,*,*,*,
8,
12,
8,
12,
16")])
5961 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5962 (match_operand:DI
1 "const_int_operand" ""))]
5963 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) <=
1"
5964 [(set (match_dup
2) (match_dup
4))
5965 (set (match_dup
3) (match_dup
1))]
5968 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5969 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
5970 operands[
4] = (INTVAL (operands[
1]) &
0x80000000) ? constm1_rtx : const0_rtx;
5974 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5975 (match_operand:DI
1 "const_int_operand" ""))]
5976 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) >=
2"
5977 [(set (match_dup
3) (match_dup
5))
5978 (set (match_dup
2) (match_dup
4))
5979 (set (match_dup
3) (ior:SI (match_dup
3) (match_dup
6)))]
5982 HOST_WIDE_INT value = INTVAL (operands[
1]);
5983 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5984 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
5985 operands[
4] = (value &
0x80000000) ? constm1_rtx : const0_rtx;
5986 operands[
5] = GEN_INT (value &
0xffff0000);
5987 operands[
6] = GEN_INT (value &
0x0000ffff);
5991 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5992 (match_operand:DI
1 "const_double_operand" ""))]
5993 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) <=
2"
5994 [(set (match_dup
2) (match_dup
4))
5995 (set (match_dup
3) (match_dup
5))]
5998 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5999 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
6000 operands[
4] = GEN_INT (CONST_DOUBLE_HIGH (operands[
1]));
6001 operands[
5] = GEN_INT (CONST_DOUBLE_LOW (operands[
1]));
6005 [(set (match_operand:DI
0 "gpc_reg_operand" "")
6006 (match_operand:DI
1 "const_double_operand" ""))]
6007 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) ==
3"
6008 [(set (match_dup
2) (match_dup
4))
6009 (set (match_dup
3) (match_dup
5))
6010 (set (match_dup
2) (ior:SI (match_dup
2) (match_dup
6)))]
6013 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[
1]);
6014 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[
1]);
6015 rtx high_reg = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
6016 rtx low_reg = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
6018 if (((unsigned HOST_WIDE_INT) (low +
0x8000) <
0x10000)
6019 || (low &
0xffff) ==
0)
6021 operands[
2] = high_reg;
6022 operands[
3] = low_reg;
6023 operands[
4] = GEN_INT (high &
0xffff0000);
6024 operands[
5] = GEN_INT (low);
6025 operands[
6] = GEN_INT (high &
0x0000ffff);
6029 operands[
2] = low_reg;
6030 operands[
3] = high_reg;
6031 operands[
4] = GEN_INT (low &
0xffff0000);
6032 operands[
5] = GEN_INT (high);
6033 operands[
6] = GEN_INT (low &
0x0000ffff);
6038 [(set (match_operand:DI
0 "gpc_reg_operand" "")
6039 (match_operand:DI
1 "const_double_operand" ""))]
6040 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) >=
4"
6041 [(set (match_dup
2) (match_dup
4))
6042 (set (match_dup
3) (match_dup
5))
6043 (set (match_dup
2) (ior:SI (match_dup
2) (match_dup
6)))
6044 (set (match_dup
3) (ior:SI (match_dup
3) (match_dup
7)))]
6047 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[
1]);
6048 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[
1]);
6050 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
6051 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
6052 operands[
4] = GEN_INT (high &
0xffff0000);
6053 operands[
5] = GEN_INT (low &
0xffff0000);
6054 operands[
6] = GEN_INT (high &
0x0000ffff);
6055 operands[
7] = GEN_INT (low &
0x0000ffff);
6058 (define_insn "*movdi_64"
6059 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
6060 (match_operand:DI
1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,
0"))]
6062 && (gpc_reg_operand (operands[
0], DImode)
6063 || gpc_reg_operand (operands[
1], DImode))"
6078 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
6079 (set_attr "length" "
4,
4,
4,
4,
4,
20,
4,
4,
4,
4,
4,
4,
4")])
6081 ;; Split a load of a large constant into the appropriate five-instruction
6082 ;; sequence. The expansion in movdi tries to perform the minimum number of
6083 ;; steps, but here we have to handle anything in a constant number of insns.
6086 [(set (match_operand:DI
0 "gpc_reg_operand" "")
6087 (match_operand:DI
1 "const_double_operand" ""))]
6088 "TARGET_64BIT && num_insns_constant (operands[
1], DImode) >
1"
6092 (ior:DI (match_dup
0)
6095 (ashift:DI (match_dup
0)
6098 (ior:DI (match_dup
0)
6101 (ior:DI (match_dup
0)
6108 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
6110 low = CONST_DOUBLE_LOW (operands[
1]);
6111 high = CONST_DOUBLE_HIGH (operands[
1]);
6114 #if HOST_BITS_PER_WIDE_INT == 32
6116 low = INTVAL (operands[
1]);
6117 high = (low <
0) ? ~
0 :
0;
6121 low = INTVAL (operands[
1]) &
0xffffffff;
6122 high = (HOST_WIDE_INT) INTVAL (operands[
1]) >>
32;
6126 if ((high +
0x8000) <
0x10000
6127 && ((low &
0xffff) ==
0 || (low & (~ (HOST_WIDE_INT)
0xffff)) ==
0))
6130 operands[
2] = GEN_INT (high & (~ (HOST_WIDE_INT)
0xffff));
6131 operands[
3] = GEN_INT (high &
0xffff);
6132 operands[
4] = GEN_INT (low & (~ (HOST_WIDE_INT)
0xffff));
6133 operands[
5] = GEN_INT (low &
0xffff);
6137 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
6138 (compare:CC (match_operand:DI
1 "gpc_reg_operand" "r")
6140 (set (match_operand:DI
0 "gpc_reg_operand" "=r") (match_dup
1))]
6143 [(set_attr "type" "compare")])
6145 ;; TImode is similar, except that we usually want to compute the address into
6146 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
6147 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
6148 (define_expand "movti"
6149 [(parallel [(set (match_operand:TI
0 "general_operand" "")
6150 (match_operand:TI
1 "general_operand" ""))
6151 (clobber (scratch:SI))])]
6152 "TARGET_STRING || TARGET_POWERPC64"
6155 if (GET_CODE (operands[
0]) == MEM)
6156 operands[
1] = force_reg (TImode, operands[
1]);
6158 if (GET_CODE (operands[
0]) == MEM
6159 && GET_CODE (XEXP (operands[
0],
0)) != REG
6160 && ! reload_in_progress)
6161 operands[
0] = change_address (operands[
0], TImode,
6162 copy_addr_to_reg (XEXP (operands[
0],
0)));
6164 if (GET_CODE (operands[
1]) == MEM
6165 && GET_CODE (XEXP (operands[
1],
0)) != REG
6166 && ! reload_in_progress)
6167 operands[
1] = change_address (operands[
1], TImode,
6168 copy_addr_to_reg (XEXP (operands[
1],
0)));
6171 ;; We say that MQ is clobbered in the last alternative because the first
6172 ;; alternative would never get used otherwise since it would need a reload
6173 ;; while the
2nd alternative would not. We put memory cases first so they
6174 ;; are preferred. Otherwise, we'd try to reload the output instead of
6175 ;; giving the SCRATCH mq.
6177 [(set (match_operand:TI
0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
6178 (match_operand:TI
1 "reg_or_mem_operand" "r,r,r,Q,m"))
6179 (clobber (match_scratch:SI
2 "=q,q#X,X,X,X"))]
6180 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
6181 && (gpc_reg_operand (operands[
0], TImode) || gpc_reg_operand (operands[
1], TImode))"
6184 switch (which_alternative)
6190 return
\"{stsi|stswi} %
1,%P0,
16\";
6193 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0
\";
6196 /* Normally copy registers with lowest numbered register copied first.
6197 But copy in the other order if the first register of the output
6198 is the second, third, or fourth register in the input. */
6199 if (REGNO (operands[
0]) >= REGNO (operands[
1]) +
1
6200 && REGNO (operands[
0]) <= REGNO (operands[
1]) +
3)
6201 return
\"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %
0,%
1\";
6203 return
\"mr %
0,%
1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1
\";
6205 /* If the address is not used in the output, we can use lsi. Otherwise,
6206 fall through to generating four loads. */
6207 if (! reg_overlap_mentioned_p (operands[
0], operands[
1]))
6208 return
\"{lsi|lswi} %
0,%P1,
16\";
6209 /* ... fall through ... */
6211 /* If the address register is the same as the register for the lowest-
6212 addressed word, load it last. Similarly for the next two words.
6213 Otherwise load lowest address to highest. */
6214 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
6216 return
\"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %
0,%
1\";
6217 else if (refers_to_regno_p (REGNO (operands[
0]) +
1,
6218 REGNO (operands[
0]) +
2, operands[
1],
0))
6219 return
\"{l|lwz} %
0,%
1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1
\";
6220 else if (refers_to_regno_p (REGNO (operands[
0]) +
2,
6221 REGNO (operands[
0]) +
3, operands[
1],
0))
6222 return
\"{l|lwz} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1
\";
6224 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1
\";
6227 [(set_attr "type" "store,store,*,load,load")
6228 (set_attr "length" "*,
16,
16,*,
16")])
6231 [(set (match_operand:TI
0 "reg_or_mem_operand" "=m,????r,????r")
6232 (match_operand:TI
1 "reg_or_mem_operand" "r,r,m"))
6233 (clobber (match_scratch:SI
2 "=X,X,X"))]
6234 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
6235 && (gpc_reg_operand (operands[
0], TImode) || gpc_reg_operand (operands[
1], TImode))"
6238 switch (which_alternative)
6244 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0
\";
6247 /* Normally copy registers with lowest numbered register copied first.
6248 But copy in the other order if the first register of the output
6249 is the second, third, or fourth register in the input. */
6250 if (REGNO (operands[
0]) >= REGNO (operands[
1]) +
1
6251 && REGNO (operands[
0]) <= REGNO (operands[
1]) +
3)
6252 return
\"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %
0,%
1\";
6254 return
\"mr %
0,%
1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1
\";
6256 /* If the address register is the same as the register for the lowest-
6257 addressed word, load it last. Similarly for the next two words.
6258 Otherwise load lowest address to highest. */
6259 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
6261 return
\"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %
0,%
1\";
6262 else if (refers_to_regno_p (REGNO (operands[
0]) +
1,
6263 REGNO (operands[
0]) +
2, operands[
1],
0))
6264 return
\"{l|lwz} %
0,%
1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1
\";
6265 else if (refers_to_regno_p (REGNO (operands[
0]) +
2,
6266 REGNO (operands[
0]) +
3, operands[
1],
0))
6267 return
\"{l|lwz} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1
\";
6269 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1
\";
6272 [(set_attr "type" "store,*,load")
6273 (set_attr "length" "
16,
16,
16")])
6276 [(set (match_operand:TI
0 "nonimmediate_operand" "=r,r,m")
6277 (match_operand:TI
1 "input_operand" "r,m,r"))]
6278 "TARGET_POWERPC64 && (gpc_reg_operand (operands[
0], TImode)
6279 || gpc_reg_operand (operands[
1], TImode))"
6282 switch (which_alternative)
6285 /* We normally copy the low-numbered register first. However, if
6286 the first register operand
0 is the same as the second register of
6287 operand
1, we must copy in the opposite order. */
6288 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
6289 return
\"mr %L0,%L1\;mr %
0,%
1\";
6291 return
\"mr %
0,%
1\;mr %L0,%L1
\";
6293 /* If the low-address word is used in the address, we must load it
6294 last. Otherwise, load it first. Note that we cannot have
6295 auto-increment in that case since the address register is known to be
6297 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
6299 return
\"ld %L0,%L1\;ld %
0,%
1\";
6301 return
\"ld%U1 %
0,%
1\;ld %L0,%L1
\";
6303 return
\"std%U0 %
1,%
0\;std %L1,%L0
\";
6306 [(set_attr "type" "*,load,store")
6307 (set_attr "length" "
8,
8,
8")])
6309 (define_expand "load_multiple"
6310 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
6311 (match_operand:SI
1 "" ""))
6312 (use (match_operand:SI
2 "" ""))])]
6321 /* Support only loading a constant number of fixed-point registers from
6322 memory and only bother with this if more than two; the machine
6323 doesn't support more than eight. */
6324 if (GET_CODE (operands[
2]) != CONST_INT
6325 || INTVAL (operands[
2]) <=
2
6326 || INTVAL (operands[
2]) >
8
6327 || GET_CODE (operands[
1]) != MEM
6328 || GET_CODE (operands[
0]) != REG
6329 || REGNO (operands[
0]) >=
32)
6332 count = INTVAL (operands[
2]);
6333 regno = REGNO (operands[
0]);
6335 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
6336 from = force_reg (SImode, XEXP (operands[
1],
0));
6338 for (i =
0; i < count; i++)
6339 XVECEXP (operands[
3],
0, i)
6340 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
6341 change_address (operands[
1], SImode,
6342 plus_constant (from, i *
4)));
6346 [(match_parallel
0 "load_multiple_operation"
6347 [(set (match_operand:SI
1 "gpc_reg_operand" "=r")
6348 (mem:SI (match_operand:SI
2 "register_operand" "b")))])]
6352 /* We have to handle the case where the pseudo used to contain the address
6353 is assigned to one of the output registers. */
6355 int words = XVECLEN (operands[
0],
0);
6358 if (XVECLEN (operands[
0],
0) ==
1)
6359 return
\"{l|lwz} %
1,
0(%
2)
\";
6361 for (i =
0; i < words; i++)
6362 if (refers_to_regno_p (REGNO (operands[
1]) + i,
6363 REGNO (operands[
1]) + i +
1, operands[
2],
0))
6367 xop[
0] = operands[
1];
6368 xop[
1] = operands[
2];
6369 xop[
2] = GEN_INT (
4 * (words-
1));
6370 output_asm_insn (
\"{lsi|lswi} %
0,%
1,%
2\;{l|lwz} %
1,%
2(%
1)
\", xop);
6375 xop[
0] = operands[
1];
6376 xop[
1] = gen_rtx (REG, SImode, REGNO (operands[
1]) +
1);
6377 xop[
2] = GEN_INT (
4 * (words-
1));
6378 output_asm_insn (
\"{cal %
0,
4(%
0)|addi %
0,%
0,
4}\;{lsi|lswi} %
1,%
0,%
2\;{l|lwz} %
0,-
4(%
0)
\", xop);
6383 for (j =
0; j < words; j++)
6386 xop[
0] = gen_rtx (REG, SImode, REGNO (operands[
1]) + j);
6387 xop[
1] = operands[
2];
6388 xop[
2] = GEN_INT (j *
4);
6389 output_asm_insn (
\"{l|lwz} %
0,%
2(%
1)
\", xop);
6391 xop[
0] = operands[
2];
6392 xop[
1] = GEN_INT (i *
4);
6393 output_asm_insn (
\"{l|lwz} %
0,%
1(%
0)
\", xop);
6398 return
\"{lsi|lswi} %
1,%
2,%N0
\";
6400 [(set_attr "type" "load")
6401 (set_attr "length" "
32")])
6404 (define_expand "store_multiple"
6405 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
6406 (match_operand:SI
1 "" ""))
6407 (clobber (scratch:SI))
6408 (use (match_operand:SI
2 "" ""))])]
6417 /* Support only storing a constant number of fixed-point registers to
6418 memory and only bother with this if more than two; the machine
6419 doesn't support more than eight. */
6420 if (GET_CODE (operands[
2]) != CONST_INT
6421 || INTVAL (operands[
2]) <=
2
6422 || INTVAL (operands[
2]) >
8
6423 || GET_CODE (operands[
0]) != MEM
6424 || GET_CODE (operands[
1]) != REG
6425 || REGNO (operands[
1]) >=
32)
6428 count = INTVAL (operands[
2]);
6429 regno = REGNO (operands[
1]);
6431 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count +
1));
6432 to = force_reg (SImode, XEXP (operands[
0],
0));
6434 XVECEXP (operands[
3],
0,
0)
6435 = gen_rtx (SET, VOIDmode, change_address (operands[
0], SImode, to),
6437 XVECEXP (operands[
3],
0,
1) = gen_rtx (CLOBBER, VOIDmode,
6438 gen_rtx (SCRATCH, SImode));
6440 for (i =
1; i < count; i++)
6441 XVECEXP (operands[
3],
0, i +
1)
6442 = gen_rtx (SET, VOIDmode,
6443 change_address (operands[
0], SImode,
6444 plus_constant (to, i *
4)),
6445 gen_rtx (REG, SImode, regno + i));
6449 [(match_parallel
0 "store_multiple_operation"
6450 [(set (match_operand:SI
1 "indirect_operand" "=Q")
6451 (match_operand:SI
2 "gpc_reg_operand" "r"))
6452 (clobber (match_scratch:SI
3 "=q"))])]
6453 "TARGET_STRING && TARGET_POWER"
6454 "{stsi|stswi} %
2,%P1,%O0"
6455 [(set_attr "type" "store")])
6458 [(match_parallel
0 "store_multiple_operation"
6459 [(set (mem:SI (match_operand:SI
1 "register_operand" "b"))
6460 (match_operand:SI
2 "gpc_reg_operand" "r"))
6461 (clobber (match_scratch:SI
3 "X"))])]
6462 "TARGET_STRING && !TARGET_POWER"
6463 "{stsi|stswi} %
2,%
1,%O0"
6464 [(set_attr "type" "store")])
6467 ;; String/block move insn.
6468 ;; Argument
0 is the destination
6469 ;; Argument
1 is the source
6470 ;; Argument
2 is the length
6471 ;; Argument
3 is the alignment
6473 (define_expand "movstrsi"
6474 [(parallel [(set (match_operand:BLK
0 "" "")
6475 (match_operand:BLK
1 "" ""))
6476 (use (match_operand:SI
2 "" ""))
6477 (use (match_operand:SI
3 "" ""))])]
6481 if (expand_block_move (operands))
6487 ;; Move up to
32 bytes at a time. The fixed registers are needed because the
6488 ;; register allocator doesn't have a clue about allocating
8 word registers
6489 (define_expand "movstrsi_8reg"
6490 [(parallel [(set (match_operand
0 "" "")
6491 (match_operand
1 "" ""))
6492 (use (match_operand
2 "" ""))
6493 (use (match_operand
3 "" ""))
6494 (clobber (reg:SI
5))
6495 (clobber (reg:SI
6))
6496 (clobber (reg:SI
7))
6497 (clobber (reg:SI
8))
6498 (clobber (reg:SI
9))
6499 (clobber (reg:SI
10))
6500 (clobber (reg:SI
11))
6501 (clobber (reg:SI
12))
6502 (clobber (match_scratch:SI
4 ""))])]
6507 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6508 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6509 (use (match_operand:SI
2 "immediate_operand" "i"))
6510 (use (match_operand:SI
3 "immediate_operand" "i"))
6511 (clobber (match_operand:SI
4 "register_operand" "=r"))
6512 (clobber (reg:SI
6))
6513 (clobber (reg:SI
7))
6514 (clobber (reg:SI
8))
6515 (clobber (reg:SI
9))
6516 (clobber (reg:SI
10))
6517 (clobber (reg:SI
11))
6518 (clobber (reg:SI
12))
6519 (clobber (match_scratch:SI
5 "=q"))]
6520 "TARGET_STRING && TARGET_POWER
6521 && ((INTVAL (operands[
2]) >
24 && INTVAL (operands[
2]) <
32) || INTVAL (operands[
2]) ==
0)
6522 && (REGNO (operands[
0]) <
5 || REGNO (operands[
0]) >
12)
6523 && (REGNO (operands[
1]) <
5 || REGNO (operands[
1]) >
12)
6524 && REGNO (operands[
4]) ==
5"
6525 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6526 [(set_attr "type" "load")
6527 (set_attr "length" "
8")])
6530 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6531 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6532 (use (match_operand:SI
2 "immediate_operand" "i"))
6533 (use (match_operand:SI
3 "immediate_operand" "i"))
6534 (clobber (match_operand:SI
4 "register_operand" "=r"))
6535 (clobber (reg:SI
6))
6536 (clobber (reg:SI
7))
6537 (clobber (reg:SI
8))
6538 (clobber (reg:SI
9))
6539 (clobber (reg:SI
10))
6540 (clobber (reg:SI
11))
6541 (clobber (reg:SI
12))
6542 (clobber (match_scratch:SI
5 "X"))]
6543 "TARGET_STRING && !TARGET_POWER
6544 && ((INTVAL (operands[
2]) >
24 && INTVAL (operands[
2]) <
32) || INTVAL (operands[
2]) ==
0)
6545 && (REGNO (operands[
0]) <
5 || REGNO (operands[
0]) >
12)
6546 && (REGNO (operands[
1]) <
5 || REGNO (operands[
1]) >
12)
6547 && REGNO (operands[
4]) ==
5"
6548 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6549 [(set_attr "type" "load")
6550 (set_attr "length" "
8")])
6552 ;; Move up to
24 bytes at a time. The fixed registers are needed because the
6553 ;; register allocator doesn't have a clue about allocating
6 word registers
6554 (define_expand "movstrsi_6reg"
6555 [(parallel [(set (match_operand
0 "" "")
6556 (match_operand
1 "" ""))
6557 (use (match_operand
2 "" ""))
6558 (use (match_operand
3 "" ""))
6559 (clobber (reg:SI
7))
6560 (clobber (reg:SI
8))
6561 (clobber (reg:SI
9))
6562 (clobber (reg:SI
10))
6563 (clobber (reg:SI
11))
6564 (clobber (reg:SI
12))
6565 (clobber (match_scratch:SI
4 ""))])]
6570 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6571 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6572 (use (match_operand:SI
2 "immediate_operand" "i"))
6573 (use (match_operand:SI
3 "immediate_operand" "i"))
6574 (clobber (match_operand:SI
4 "register_operand" "=r"))
6575 (clobber (reg:SI
8))
6576 (clobber (reg:SI
9))
6577 (clobber (reg:SI
10))
6578 (clobber (reg:SI
11))
6579 (clobber (reg:SI
12))
6580 (clobber (match_scratch:SI
5 "=q"))]
6581 "TARGET_STRING && TARGET_POWER
6582 && INTVAL (operands[
2]) >
16 && INTVAL (operands[
2]) <=
24
6583 && (REGNO (operands[
0]) <
7 || REGNO (operands[
0]) >
12)
6584 && (REGNO (operands[
1]) <
7 || REGNO (operands[
1]) >
12)
6585 && REGNO (operands[
4]) ==
7"
6586 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6587 [(set_attr "type" "load")
6588 (set_attr "length" "
8")])
6591 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6592 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6593 (use (match_operand:SI
2 "immediate_operand" "i"))
6594 (use (match_operand:SI
3 "immediate_operand" "i"))
6595 (clobber (match_operand:SI
4 "register_operand" "=r"))
6596 (clobber (reg:SI
8))
6597 (clobber (reg:SI
9))
6598 (clobber (reg:SI
10))
6599 (clobber (reg:SI
11))
6600 (clobber (reg:SI
12))
6601 (clobber (match_scratch:SI
5 "X"))]
6602 "TARGET_STRING && !TARGET_POWER
6603 && INTVAL (operands[
2]) >
16 && INTVAL (operands[
2]) <=
32
6604 && (REGNO (operands[
0]) <
7 || REGNO (operands[
0]) >
12)
6605 && (REGNO (operands[
1]) <
7 || REGNO (operands[
1]) >
12)
6606 && REGNO (operands[
4]) ==
7"
6607 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6608 [(set_attr "type" "load")
6609 (set_attr "length" "
8")])
6611 ;; Move up to
16 bytes at a time, using
4 fixed registers to avoid spill problems
6613 (define_expand "movstrsi_4reg"
6614 [(parallel [(set (match_operand
0 "" "")
6615 (match_operand
1 "" ""))
6616 (use (match_operand
2 "" ""))
6617 (use (match_operand
3 "" ""))
6618 (clobber (reg:SI
9))
6619 (clobber (reg:SI
10))
6620 (clobber (reg:SI
11))
6621 (clobber (reg:SI
12))
6622 (clobber (match_scratch:SI
4 ""))])]
6627 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6628 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6629 (use (match_operand:SI
2 "immediate_operand" "i"))
6630 (use (match_operand:SI
3 "immediate_operand" "i"))
6631 (clobber (match_operand:SI
4 "register_operand" "=r"))
6632 (clobber (reg:SI
10))
6633 (clobber (reg:SI
11))
6634 (clobber (reg:SI
12))
6635 (clobber (match_scratch:SI
5 "=q"))]
6636 "TARGET_STRING && TARGET_POWER
6637 && INTVAL (operands[
2]) >
8 && INTVAL (operands[
2]) <=
16
6638 && (REGNO (operands[
0]) <
9 || REGNO (operands[
0]) >
12)
6639 && (REGNO (operands[
1]) <
9 || REGNO (operands[
1]) >
12)
6640 && REGNO (operands[
4]) ==
9"
6641 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6642 [(set_attr "type" "load")
6643 (set_attr "length" "
8")])
6646 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6647 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6648 (use (match_operand:SI
2 "immediate_operand" "i"))
6649 (use (match_operand:SI
3 "immediate_operand" "i"))
6650 (clobber (match_operand:SI
4 "register_operand" "=r"))
6651 (clobber (reg:SI
10))
6652 (clobber (reg:SI
11))
6653 (clobber (reg:SI
12))
6654 (clobber (match_scratch:SI
5 "X"))]
6655 "TARGET_STRING && !TARGET_POWER
6656 && INTVAL (operands[
2]) >
8 && INTVAL (operands[
2]) <=
16
6657 && (REGNO (operands[
0]) <
9 || REGNO (operands[
0]) >
12)
6658 && (REGNO (operands[
1]) <
9 || REGNO (operands[
1]) >
12)
6659 && REGNO (operands[
4]) ==
9"
6660 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6661 [(set_attr "type" "load")
6662 (set_attr "length" "
8")])
6664 ;; Move up to
8 bytes at a time.
6665 (define_expand "movstrsi_2reg"
6666 [(parallel [(set (match_operand
0 "" "")
6667 (match_operand
1 "" ""))
6668 (use (match_operand
2 "" ""))
6669 (use (match_operand
3 "" ""))
6670 (clobber (match_scratch:DI
4 ""))
6671 (clobber (match_scratch:SI
5 ""))])]
6672 "TARGET_STRING && !TARGET_64BIT"
6676 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6677 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6678 (use (match_operand:SI
2 "immediate_operand" "i"))
6679 (use (match_operand:SI
3 "immediate_operand" "i"))
6680 (clobber (match_scratch:DI
4 "=&r"))
6681 (clobber (match_scratch:SI
5 "=q"))]
6682 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
6683 && INTVAL (operands[
2]) >
4 && INTVAL (operands[
2]) <=
8"
6684 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6685 [(set_attr "type" "load")
6686 (set_attr "length" "
8")])
6689 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6690 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6691 (use (match_operand:SI
2 "immediate_operand" "i"))
6692 (use (match_operand:SI
3 "immediate_operand" "i"))
6693 (clobber (match_scratch:DI
4 "=&r"))
6694 (clobber (match_scratch:SI
5 "X"))]
6695 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
6696 && INTVAL (operands[
2]) >
4 && INTVAL (operands[
2]) <=
8"
6697 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6698 [(set_attr "type" "load")
6699 (set_attr "length" "
8")])
6701 ;; Move up to
4 bytes at a time.
6702 (define_expand "movstrsi_1reg"
6703 [(parallel [(set (match_operand
0 "" "")
6704 (match_operand
1 "" ""))
6705 (use (match_operand
2 "" ""))
6706 (use (match_operand
3 "" ""))
6707 (clobber (match_scratch:SI
4 ""))
6708 (clobber (match_scratch:SI
5 ""))])]
6713 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6714 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6715 (use (match_operand:SI
2 "immediate_operand" "i"))
6716 (use (match_operand:SI
3 "immediate_operand" "i"))
6717 (clobber (match_scratch:SI
4 "=&r"))
6718 (clobber (match_scratch:SI
5 "=q"))]
6719 "TARGET_STRING && TARGET_POWER
6720 && INTVAL (operands[
2]) >
0 && INTVAL (operands[
2]) <=
4"
6721 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6722 [(set_attr "type" "load")
6723 (set_attr "length" "
8")])
6726 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6727 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6728 (use (match_operand:SI
2 "immediate_operand" "i"))
6729 (use (match_operand:SI
3 "immediate_operand" "i"))
6730 (clobber (match_scratch:SI
4 "=&r"))
6731 (clobber (match_scratch:SI
5 "X"))]
6732 "TARGET_STRING && !TARGET_POWER
6733 && INTVAL (operands[
2]) >
0 && INTVAL (operands[
2]) <=
4"
6734 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6735 [(set_attr "type" "load")
6736 (set_attr "length" "
8")])
6739 ;; Define insns that do load or store with update. Some of these we can
6740 ;; get by using pre-decrement or pre-increment, but the hardware can also
6741 ;; do cases where the increment is not the size of the object.
6743 ;; In all these cases, we use operands
0 and
1 for the register being
6744 ;; incremented because those are the operands that local-alloc will
6745 ;; tie and these are the pair most likely to be tieable (and the ones
6746 ;; that will benefit the most).
6749 [(set (match_operand:DI
3 "gpc_reg_operand" "=r,r")
6750 (mem:DI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0,
0")
6751 (match_operand:DI
2 "reg_or_short_operand" "r,I"))))
6752 (set (match_operand:DI
0 "gpc_reg_operand" "=b,b")
6753 (plus:DI (match_dup
1) (match_dup
2)))]
6758 [(set_attr "type" "load")])
6761 [(set (match_operand:DI
3 "gpc_reg_operand" "=r")
6763 (mem:SI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0")
6764 (match_operand:DI
2 "gpc_reg_operand" "r")))))
6765 (set (match_operand:DI
0 "gpc_reg_operand" "=b")
6766 (plus:DI (match_dup
1) (match_dup
2)))]
6769 [(set_attr "type" "load")])
6771 (define_insn "movdi_update"
6772 [(set (mem:DI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0,
0")
6773 (match_operand:DI
2 "reg_or_short_operand" "r,I")))
6774 (match_operand:DI
3 "gpc_reg_operand" "r,r"))
6775 (set (match_operand:DI
0 "gpc_reg_operand" "=b,b")
6776 (plus:DI (match_dup
1) (match_dup
2)))]
6781 [(set_attr "type" "store")])
6784 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6785 (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6786 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6787 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6788 (plus:SI (match_dup
1) (match_dup
2)))]
6791 {lux|lwzux} %
3,%
0,%
2
6792 {lu|lwzu} %
3,%
2(%
0)"
6793 [(set_attr "type" "load")])
6795 (define_insn "movsi_update"
6796 [(set (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6797 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6798 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
6799 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6800 (plus:SI (match_dup
1) (match_dup
2)))]
6803 {stux|stwux} %
3,%
0,%
2
6804 {stu|stwu} %
3,%
2(%
0)"
6805 [(set_attr "type" "store")])
6808 [(set (match_operand:HI
3 "gpc_reg_operand" "=r,r")
6809 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6810 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6811 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6812 (plus:SI (match_dup
1) (match_dup
2)))]
6817 [(set_attr "type" "load")])
6820 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6822 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6823 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6824 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6825 (plus:SI (match_dup
1) (match_dup
2)))]
6830 [(set_attr "type" "load")])
6833 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6835 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6836 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6837 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6838 (plus:SI (match_dup
1) (match_dup
2)))]
6843 [(set_attr "type" "load")])
6846 [(set (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6847 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6848 (match_operand:HI
3 "gpc_reg_operand" "r,r"))
6849 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6850 (plus:SI (match_dup
1) (match_dup
2)))]
6855 [(set_attr "type" "store")])
6858 [(set (match_operand:QI
3 "gpc_reg_operand" "=r,r")
6859 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6860 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6861 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6862 (plus:SI (match_dup
1) (match_dup
2)))]
6867 [(set_attr "type" "load")])
6870 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6872 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6873 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6874 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6875 (plus:SI (match_dup
1) (match_dup
2)))]
6880 [(set_attr "type" "load")])
6883 [(set (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6884 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6885 (match_operand:QI
3 "gpc_reg_operand" "r,r"))
6886 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6887 (plus:SI (match_dup
1) (match_dup
2)))]
6892 [(set_attr "type" "store")])
6895 [(set (match_operand:SF
3 "gpc_reg_operand" "=f,f")
6896 (mem:SF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6897 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6898 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6899 (plus:SI (match_dup
1) (match_dup
2)))]
6904 [(set_attr "type" "fpload")])
6907 [(set (mem:SF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6908 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6909 (match_operand:SF
3 "gpc_reg_operand" "f,f"))
6910 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6911 (plus:SI (match_dup
1) (match_dup
2)))]
6916 [(set_attr "type" "fpstore")])
6919 [(set (match_operand:DF
3 "gpc_reg_operand" "=f,f")
6920 (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6921 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6922 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6923 (plus:SI (match_dup
1) (match_dup
2)))]
6928 [(set_attr "type" "fpload")])
6931 [(set (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6932 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6933 (match_operand:DF
3 "gpc_reg_operand" "f,f"))
6934 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6935 (plus:SI (match_dup
1) (match_dup
2)))]
6940 [(set_attr "type" "fpstore")])
6942 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
6945 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
6946 (match_operand:DF
1 "memory_operand" ""))
6947 (set (match_operand:DF
2 "gpc_reg_operand" "=f")
6948 (match_operand:DF
3 "memory_operand" ""))]
6950 && TARGET_HARD_FLOAT
6951 && registers_ok_for_quad_peep (operands[
0], operands[
2])
6952 && ! MEM_VOLATILE_P (operands[
1]) && ! MEM_VOLATILE_P (operands[
3])
6953 && addrs_ok_for_quad_peep (XEXP (operands[
1],
0), XEXP (operands[
3],
0))"
6957 [(set (match_operand:DF
0 "memory_operand" "")
6958 (match_operand:DF
1 "gpc_reg_operand" "f"))
6959 (set (match_operand:DF
2 "memory_operand" "")
6960 (match_operand:DF
3 "gpc_reg_operand" "f"))]
6962 && TARGET_HARD_FLOAT
6963 && registers_ok_for_quad_peep (operands[
1], operands[
3])
6964 && ! MEM_VOLATILE_P (operands[
0]) && ! MEM_VOLATILE_P (operands[
2])
6965 && addrs_ok_for_quad_peep (XEXP (operands[
0],
0), XEXP (operands[
2],
0))"
6968 ;; Next come insns related to the calling sequence.
6970 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
6971 ;; We move the back-chain and decrement the stack pointer.
6973 (define_expand "allocate_stack"
6975 (minus:SI (reg:SI
1) (match_operand:SI
0 "reg_or_short_operand" "")))]
6978 { rtx chain = gen_reg_rtx (Pmode);
6979 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
6982 emit_move_insn (chain, stack_bot);
6984 /* Under Windows NT, we need to add stack probes for large/variable allocations,
6985 so do it via a call to the external function alloca, instead of doing it
6987 if (DEFAULT_ABI == ABI_NT
6988 && (GET_CODE (operands[
0]) != CONST_INT || INTVAL (operands[
0]) >
4096))
6990 rtx tmp = gen_reg_rtx (SImode);
6991 emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode,
\"__allocate_stack
\"),
6992 tmp,
0, SImode,
1, operands[
0], Pmode);
6993 emit_insn (gen_set_sp (tmp));
6997 if (GET_CODE (operands[
0]) != CONST_INT
6998 || INTVAL (operands[
0]) < -
32767
6999 || INTVAL (operands[
0]) >
32768)
7001 neg_op0 = gen_reg_rtx (Pmode);
7003 emit_insn (gen_negsi2 (neg_op0, operands[
0]));
7005 emit_insn (gen_negdi2 (neg_op0, operands[
0]));
7008 neg_op0 = GEN_INT (- INTVAL (operands[
0]));
7011 emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
7013 emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
7018 ;; Marker to indicate that the stack pointer was changed under NT in
7019 ;; ways not known to the compiler
7021 (define_insn "set_sp"
7023 (unspec [(match_operand:SI
0 "register_operand" "r")]
7))]
7026 [(set_attr "length" "
0")])
7028 ;; These patterns say how to save and restore the stack pointer. We need not
7029 ;; save the stack pointer at function level since we are careful to
7030 ;; preserve the backchain. At block level, we have to restore the backchain
7031 ;; when we restore the stack pointer.
7033 ;; For nonlocal gotos, we must save both the stack pointer and its
7034 ;; backchain and restore both. Note that in the nonlocal case, the
7035 ;; save area is a memory location.
7037 (define_expand "save_stack_function"
7038 [(use (const_int
0))]
7042 (define_expand "restore_stack_function"
7043 [(use (const_int
0))]
7047 (define_expand "restore_stack_block"
7048 [(set (match_dup
2) (mem:SI (match_operand:SI
0 "register_operand" "")))
7049 (set (match_dup
0) (match_operand:SI
1 "register_operand" ""))
7050 (set (mem:SI (match_dup
0)) (match_dup
2))]
7053 { operands[
2] = gen_reg_rtx (SImode); }")
7055 (define_expand "save_stack_nonlocal"
7056 [(match_operand:DI
0 "memory_operand" "")
7057 (match_operand:SI
1 "register_operand" "")]
7061 rtx temp = gen_reg_rtx (SImode);
7063 /* Copy the backchain to the first word, sp to the second. */
7064 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[
1]));
7065 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode), temp);
7066 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode), operands[
1]);
7070 (define_expand "restore_stack_nonlocal"
7071 [(match_operand:SI
0 "register_operand" "")
7072 (match_operand:DI
1 "memory_operand" "")]
7076 rtx temp = gen_reg_rtx (SImode);
7078 /* Restore the backchain from the first word, sp from the second. */
7079 emit_move_insn (temp, operand_subword (operands[
1],
0,
0, DImode));
7080 emit_move_insn (operands[
0], operand_subword (operands[
1],
1,
0, DImode));
7081 emit_move_insn (gen_rtx (MEM, SImode, operands[
0]), temp);
7086 ;; A function pointer under AIX is a pointer to a data area whose first word
7087 ;; contains the actual address of the function, whose second word contains a
7088 ;; pointer to its TOC, and whose third word contains a value to place in the
7089 ;; static chain register (r11). Note that if we load the static chain, our
7090 ;; "trampoline" need not have any executable code.
7092 ;; operands[
0] is a register pointing to the
3 word descriptor (aka, the function address)
7093 ;; operands[
1] is the stack size to clean up
7094 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument (must be
0 for AIX)
7095 ;; operands[
3] is location to store the TOC
7096 ;; operands[
4] is the TOC register
7097 ;; operands[
5] is the static chain register
7099 ;; We do not break this into separate insns, so that the scheduler will not try
7100 ;; to move the load of the new TOC before any loads from the TOC.
7102 (define_insn "call_indirect_aix"
7103 [(call (mem:SI (match_operand:SI
0 "register_operand" "b"))
7104 (match_operand
1 "const_int_operand" "n"))
7105 (use (match_operand
2 "const_int_operand" "n"))
7106 (use (match_operand
3 "offsettable_addr_operand" "p"))
7107 (use (match_operand
4 "register_operand" "r"))
7108 (clobber (match_operand
5 "register_operand" "=r"))
7109 (clobber (match_scratch:SI
6 "=&r"))
7110 (clobber (match_scratch:SI
7 "=l"))]
7111 "DEFAULT_ABI == ABI_AIX
7112 && (INTVAL (operands[
2]) == CALL_NORMAL || (INTVAL (operands[
2]) & CALL_LONG) !=
0)"
7113 "{st|stw} %
4,%a3\;{l|lwz} %
6,
0(%
0)\;{l|lwz} %
4,
4(%
0)\;mt%
7 %
6\;{l|lwz} %
5,
8(%
0)\;{brl|blrl}\;{l|lwz} %
4,%a3"
7114 [(set_attr "type" "load")
7115 (set_attr "length" "
28")])
7117 (define_insn "call_value_indirect_aix"
7118 [(set (match_operand
0 "register_operand" "fg")
7119 (call (mem:SI (match_operand:SI
1 "register_operand" "b"))
7120 (match_operand
2 "const_int_operand" "n")))
7121 (use (match_operand
3 "const_int_operand" "n"))
7122 (use (match_operand
4 "offsettable_addr_operand" "p"))
7123 (use (match_operand
5 "register_operand" "r"))
7124 (clobber (match_operand
6 "register_operand" "=r"))
7125 (clobber (match_scratch:SI
7 "=&r"))
7126 (clobber (match_scratch:SI
8 "=l"))]
7127 "DEFAULT_ABI == ABI_AIX
7128 && (INTVAL (operands[
3]) == CALL_NORMAL || (INTVAL (operands[
3]) & CALL_LONG) !=
0)"
7129 "{st|stw} %
5,%a4\;{l|lwz} %
7,
0(%
1)\;{l|lwz} %
5,
4(%
1);\;mt%
8 %
7\;{l|lwz} %
6,
8(%
1)\;{brl|blrl}\;{l|lwz} %
5,%a4"
7130 [(set_attr "type" "load")
7131 (set_attr "length" "
28")])
7133 ;; A function pointer undef NT is a pointer to a data area whose first word
7134 ;; contains the actual address of the function, whose second word contains a
7135 ;; pointer to its TOC. The static chain is not stored under NT, which means
7136 ;; that we need a trampoline.
7138 ;; operands[
0] is an SImode pseudo in which we place the address of the function.
7139 ;; operands[
1] is the stack size to clean up
7140 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument (must be
0 for NT)
7141 ;; operands[
3] is location to store the TOC
7142 ;; operands[
4] is the TOC register
7144 ;; We do not break this into separate insns, so that the scheduler will not try
7145 ;; to move the load of the new TOC before any loads from the TOC.
7147 (define_insn "call_indirect_nt"
7148 [(call (mem:SI (match_operand:SI
0 "register_operand" "b"))
7149 (match_operand
1 "const_int_operand" "n"))
7150 (use (match_operand
2 "const_int_operand" "n"))
7151 (use (match_operand
3 "offsettable_addr_operand" "p"))
7152 (use (match_operand
4 "register_operand" "r"))
7153 (clobber (match_scratch:SI
5 "=&r"))
7154 (clobber (match_scratch:SI
6 "=l"))]
7155 "DEFAULT_ABI == ABI_NT
7156 && (INTVAL (operands[
2]) == CALL_NORMAL || (INTVAL (operands[
2]) & CALL_LONG) !=
0)"
7157 "{st|stw} %
4,%a3\;{l|lwz} %
5,
0(%
0)\;{l|lwz} %
4,
4(%
0)\;mt%
6 %
5\;{brl|blrl}\;{l|lwz} %
4,%a3"
7158 [(set_attr "type" "load")
7159 (set_attr "length" "
24")])
7161 (define_insn "call_value_indirect_nt"
7162 [(set (match_operand
0 "register_operand" "fg")
7163 (call (mem:SI (match_operand:SI
1 "register_operand" "b"))
7164 (match_operand
2 "const_int_operand" "n")))
7165 (use (match_operand
3 "const_int_operand" "n"))
7166 (use (match_operand
4 "offsettable_addr_operand" "p"))
7167 (use (match_operand
5 "register_operand" "r"))
7168 (clobber (match_scratch:SI
6 "=&r"))
7169 (clobber (match_scratch:SI
7 "=l"))]
7170 "DEFAULT_ABI == ABI_NT
7171 && (INTVAL (operands[
3]) == CALL_NORMAL || (INTVAL (operands[
3]) & CALL_LONG) !=
0)"
7172 "{st|stw} %
5,%a4\;{l|lwz} %
6,
0(%
1)\;{l|lwz} %
5,
4(%
1)\;mt%
7 %
6\;{brl|blrl}\;{l|lwz} %
5,%a4"
7173 [(set_attr "type" "load")
7174 (set_attr "length" "
24")])
7176 ;; A function pointer under System V is just a normal pointer
7177 ;; operands[
0] is the function pointer
7178 ;; operands[
1] is the stack size to clean up
7179 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
7181 (define_insn "call_indirect_sysv"
7182 [(call (mem:SI (match_operand:SI
0 "register_operand" "l,l"))
7183 (match_operand
1 "const_int_operand" "n,n"))
7184 (use (match_operand
2 "const_int_operand" "O,n"))
7185 (clobber (match_scratch:SI
3 "=l,l"))]
7186 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
7189 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
7190 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7192 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
7193 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7195 return
\"{brl|blrl}
\";
7197 [(set_attr "type" "jmpreg")
7198 (set_attr "length" "
4,
8")])
7200 (define_insn "call_value_indirect_sysv"
7201 [(set (match_operand
0 "register_operand" "=fg,fg")
7202 (call (mem:SI (match_operand:SI
1 "register_operand" "l,l"))
7203 (match_operand
2 "const_int_operand" "n,n")))
7204 (use (match_operand
3 "const_int_operand" "O,n"))
7205 (clobber (match_scratch:SI
4 "=l,l"))]
7206 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
7209 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
7210 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7212 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
7213 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7215 return
\"{brl|blrl}
\";
7217 [(set_attr "type" "jmpreg")
7218 (set_attr "length" "
4,
8")])
7220 ;; Now the definitions for the call and call_value insns
7221 (define_expand "call"
7222 [(parallel [(call (mem:SI (match_operand:SI
0 "address_operand" ""))
7223 (match_operand
1 "" ""))
7224 (use (match_operand
2 "" ""))
7225 (clobber (scratch:SI))])]
7229 if (GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != CONST_INT)
7232 operands[
0] = XEXP (operands[
0],
0);
7234 /* Convert NT DLL imports into an indirect call. */
7235 if (GET_CODE (operands[
0]) == SYMBOL_REF
7236 && (INTVAL (operands[
2]) & CALL_NT_DLLIMPORT) !=
0)
7238 operands[
0] = rs6000_dll_import_ref (operands[
0]);
7239 operands[
2] = GEN_INT ((int)CALL_NORMAL);
7242 if (GET_CODE (operands[
0]) != SYMBOL_REF
7243 || (INTVAL (operands[
2]) & CALL_LONG) !=
0)
7245 if (INTVAL (operands[
2]) & CALL_LONG)
7246 operands[
0] = rs6000_longcall_ref (operands[
0]);
7248 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7249 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[
0]),
7250 operands[
1], operands[
2]));
7253 rtx toc_reg = gen_rtx (REG, Pmode,
2);
7254 rtx toc_addr = RS6000_SAVE_TOC;
7256 if (DEFAULT_ABI == ABI_AIX)
7258 /* AIX function pointers are really pointers to a three word area */
7259 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7260 emit_call_insn (gen_call_indirect_aix (force_reg (Pmode, operands[
0]),
7261 operands[
1], operands[
2],
7262 toc_addr, toc_reg, static_chain));
7264 else if (DEFAULT_ABI == ABI_NT)
7266 /* NT function pointers are really pointers to a two word area */
7267 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[
0]),
7268 operands[
1], operands[
2],
7269 toc_addr, toc_reg));
7278 (define_expand "call_value"
7279 [(parallel [(set (match_operand
0 "" "")
7280 (call (mem:SI (match_operand:SI
1 "address_operand" ""))
7281 (match_operand
2 "" "")))
7282 (use (match_operand
3 "" ""))
7283 (clobber (scratch:SI))])]
7287 if (GET_CODE (operands[
1]) != MEM || GET_CODE (operands[
2]) != CONST_INT)
7290 operands[
1] = XEXP (operands[
1],
0);
7292 /* Convert NT DLL imports into an indirect call. */
7293 if (GET_CODE (operands[
1]) == SYMBOL_REF
7294 && (INTVAL (operands[
3]) & CALL_NT_DLLIMPORT) !=
0)
7296 operands[
1] = rs6000_dll_import_ref (operands[
1]);
7297 operands[
3] = GEN_INT ((int)CALL_NORMAL);
7300 if (GET_CODE (operands[
1]) != SYMBOL_REF
7301 || (INTVAL (operands[
3]) & CALL_LONG) !=
0)
7303 if (INTVAL (operands[
2]) & CALL_LONG)
7304 operands[
1] = rs6000_longcall_ref (operands[
1]);
7306 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7307 emit_call_insn (gen_call_value_indirect_sysv (operands[
0], operands[
1],
7308 operands[
2], operands[
3]));
7311 rtx toc_reg = gen_rtx (REG, Pmode,
2);
7312 rtx toc_addr = RS6000_SAVE_TOC;
7314 if (DEFAULT_ABI == ABI_AIX)
7316 /* AIX function pointers are really pointers to a three word area */
7317 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7318 emit_call_insn (gen_call_value_indirect_aix (operands[
0],
7319 force_reg (Pmode, operands[
1]),
7320 operands[
2], operands[
3],
7321 toc_addr, toc_reg, static_chain));
7323 else if (DEFAULT_ABI == ABI_NT)
7325 /* NT function pointers are really pointers to a two word area */
7326 emit_call_insn (gen_call_value_indirect_nt (operands[
0],
7327 force_reg (Pmode, operands[
1]),
7328 operands[
2], operands[
3],
7329 toc_addr, toc_reg));
7338 ;; Call to function in current module. No TOC pointer reload needed.
7339 ;; Operand2 is non-zero if we are using the V
.4 calling sequence and
7340 ;; either the function was not prototyped, or it was prototyped as a
7341 ;; variable argument function. It is >
0 if FP registers were passed
7342 ;; and <
0 if they were not.
7345 [(call (mem:SI (match_operand:SI
0 "current_file_function_operand" "s,s"))
7346 (match_operand
1 "" "g,g"))
7347 (use (match_operand:SI
2 "immediate_operand" "O,n"))
7348 (clobber (match_scratch:SI
3 "=l,l"))]
7349 "(INTVAL (operands[
2]) & CALL_LONG) ==
0"
7352 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
7353 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7355 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
7356 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7360 [(set_attr "type" "branch")
7361 (set_attr "length" "
4,
8")])
7363 ;; Call to function which may be in another module. Restore the TOC
7364 ;; pointer (r2) after the call unless this is System V.
7365 ;; Operand2 is non-zero if we are using the V
.4 calling sequence and
7366 ;; either the function was not prototyped, or it was prototyped as a
7367 ;; variable argument function. It is >
0 if FP registers were passed
7368 ;; and <
0 if they were not.
7371 [(call (mem:SI (match_operand:SI
0 "call_operand" "s,s"))
7372 (match_operand
1 "" "fg,fg"))
7373 (use (match_operand:SI
2 "immediate_operand" "O,n"))
7374 (clobber (match_scratch:SI
3 "=l,l"))]
7375 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7376 && (INTVAL (operands[
2]) & CALL_LONG) ==
0"
7379 /* Indirect calls should go through call_indirect */
7380 if (GET_CODE (operands[
0]) == REG)
7383 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
7384 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7386 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
7387 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7389 return (TARGET_WINDOWS_NT) ?
\"bl %z0\;.znop %z0
\" :
\"bl %z0\;%.
\";
7391 [(set_attr "type" "branch")
7392 (set_attr "length" "
8,
12")])
7395 [(call (mem:SI (match_operand:SI
0 "call_operand" "s,s"))
7396 (match_operand
1 "" "fg,fg"))
7397 (use (match_operand:SI
2 "immediate_operand" "O,n"))
7398 (clobber (match_scratch:SI
3 "=l,l"))]
7399 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7400 && (INTVAL (operands[
2]) & CALL_LONG) ==
0"
7403 /* Indirect calls should go through call_indirect */
7404 if (GET_CODE (operands[
0]) == REG)
7407 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
7408 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7410 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
7411 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7413 return (flag_pic ==
1) ?
\"bl %z0@plt
\" :
\"bl %z0
\";
7415 [(set_attr "type" "branch")
7416 (set_attr "length" "
4,
8")])
7419 [(set (match_operand
0 "" "=fg,fg")
7420 (call (mem:SI (match_operand:SI
1 "current_file_function_operand" "s,s"))
7421 (match_operand
2 "" "g,g")))
7422 (use (match_operand:SI
3 "immediate_operand" "O,n"))
7423 (clobber (match_scratch:SI
4 "=l,l"))]
7424 "(INTVAL (operands[
3]) & CALL_LONG) ==
0"
7427 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
7428 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7430 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
7431 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7435 [(set_attr "type" "branch")
7436 (set_attr "length" "
4,
8")])
7439 [(set (match_operand
0 "" "=fg,fg")
7440 (call (mem:SI (match_operand:SI
1 "call_operand" "s,s"))
7441 (match_operand
2 "" "fg,fg")))
7442 (use (match_operand:SI
3 "immediate_operand" "O,n"))
7443 (clobber (match_scratch:SI
4 "=l,l"))]
7444 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7445 && (INTVAL (operands[
3]) & CALL_LONG) ==
0"
7448 /* This should be handled by call_value_indirect */
7449 if (GET_CODE (operands[
1]) == REG)
7452 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
7453 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7455 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
7456 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7458 return (TARGET_WINDOWS_NT) ?
\"bl %z1\;.znop %z1
\" :
\"bl %z1\;%.
\";
7460 [(set_attr "type" "branch")
7461 (set_attr "length" "
8,
12")])
7464 [(set (match_operand
0 "" "=fg,fg")
7465 (call (mem:SI (match_operand:SI
1 "call_operand" "s,s"))
7466 (match_operand
2 "" "fg,fg")))
7467 (use (match_operand:SI
3 "immediate_operand" "O,n"))
7468 (clobber (match_scratch:SI
4 "=l,l"))]
7469 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7470 && (INTVAL (operands[
3]) & CALL_LONG) ==
0"
7473 /* This should be handled by call_value_indirect */
7474 if (GET_CODE (operands[
1]) == REG)
7477 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
7478 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7480 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
7481 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7483 return (flag_pic ==
1) ?
\"bl %z1@plt
\" :
\"bl %z1
\";
7485 [(set_attr "type" "branch")
7486 (set_attr "length" "
4,
8")])
7488 ;; Call subroutine returning any type.
7489 (define_expand "untyped_call"
7490 [(parallel [(call (match_operand
0 "" "")
7492 (match_operand
1 "" "")
7493 (match_operand
2 "" "")])]
7499 emit_call_insn (gen_call (operands[
0], const0_rtx, const0_rtx, const0_rtx));
7501 for (i =
0; i < XVECLEN (operands[
2],
0); i++)
7503 rtx set = XVECEXP (operands[
2],
0, i);
7504 emit_move_insn (SET_DEST (set), SET_SRC (set));
7507 /* The optimizer does not know that the call sets the function value
7508 registers we stored in the result block. We avoid problems by
7509 claiming that all hard registers are used and clobbered at this
7511 emit_insn (gen_blockage ());
7516 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7517 ;; all of memory. This blocks insns from being moved across this point.
7519 (define_insn "blockage"
7520 [(unspec_volatile [(const_int
0)]
0)]
7524 ;; V
.4 specific code to initialize the PIC register
7526 (define_insn "init_v4_pic"
7527 [(set (match_operand:SI
0 "register_operand" "=l")
7528 (unspec [(const_int
0)]
7))]
7529 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
7530 "bl _GLOBAL_OFFSET_TABLE_@local-
4"
7531 [(set_attr "type" "branch")
7532 (set_attr "length" "
4")])
7535 ;; Compare insns are next. Note that the RS/
6000 has two types of compares,
7536 ;; signed & unsigned, and one type of branch.
7538 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
7539 ;; insns, and branches. We store the operands of compares until we see
7541 (define_expand "cmpsi"
7543 (compare (match_operand:SI
0 "gpc_reg_operand" "")
7544 (match_operand:SI
1 "reg_or_short_operand" "")))]
7548 /* Take care of the possibility that operands[
1] might be negative but
7549 this might be a logical operation. That insn doesn't exist. */
7550 if (GET_CODE (operands[
1]) == CONST_INT
7551 && INTVAL (operands[
1]) <
0)
7552 operands[
1] = force_reg (SImode, operands[
1]);
7554 rs6000_compare_op0 = operands[
0];
7555 rs6000_compare_op1 = operands[
1];
7556 rs6000_compare_fp_p =
0;
7560 (define_expand "cmpdi"
7562 (compare (match_operand:DI
0 "gpc_reg_operand" "")
7563 (match_operand:DI
1 "reg_or_short_operand" "")))]
7567 /* Take care of the possibility that operands[
1] might be negative but
7568 this might be a logical operation. That insn doesn't exist. */
7569 if (GET_CODE (operands[
1]) == CONST_INT
7570 && INTVAL (operands[
1]) <
0)
7571 operands[
1] = force_reg (DImode, operands[
1]);
7573 rs6000_compare_op0 = operands[
0];
7574 rs6000_compare_op1 = operands[
1];
7575 rs6000_compare_fp_p =
0;
7579 (define_expand "cmpsf"
7580 [(set (cc0) (compare (match_operand:SF
0 "gpc_reg_operand" "")
7581 (match_operand:SF
1 "gpc_reg_operand" "")))]
7585 rs6000_compare_op0 = operands[
0];
7586 rs6000_compare_op1 = operands[
1];
7587 rs6000_compare_fp_p =
1;
7591 (define_expand "cmpdf"
7592 [(set (cc0) (compare (match_operand:DF
0 "gpc_reg_operand" "")
7593 (match_operand:DF
1 "gpc_reg_operand" "")))]
7597 rs6000_compare_op0 = operands[
0];
7598 rs6000_compare_op1 = operands[
1];
7599 rs6000_compare_fp_p =
1;
7603 (define_expand "beq"
7604 [(set (match_dup
2) (match_dup
1))
7606 (if_then_else (eq (match_dup
2)
7608 (label_ref (match_operand
0 "" ""))
7612 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7613 operands[
1] = gen_rtx (COMPARE, mode,
7614 rs6000_compare_op0, rs6000_compare_op1);
7615 operands[
2] = gen_reg_rtx (mode);
7618 (define_expand "bne"
7619 [(set (match_dup
2) (match_dup
1))
7621 (if_then_else (ne (match_dup
2)
7623 (label_ref (match_operand
0 "" ""))
7627 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7628 operands[
1] = gen_rtx (COMPARE, mode,
7629 rs6000_compare_op0, rs6000_compare_op1);
7630 operands[
2] = gen_reg_rtx (mode);
7633 (define_expand "blt"
7634 [(set (match_dup
2) (match_dup
1))
7636 (if_then_else (lt (match_dup
2)
7638 (label_ref (match_operand
0 "" ""))
7642 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7643 operands[
1] = gen_rtx (COMPARE, mode,
7644 rs6000_compare_op0, rs6000_compare_op1);
7645 operands[
2] = gen_reg_rtx (mode);
7648 (define_expand "bgt"
7649 [(set (match_dup
2) (match_dup
1))
7651 (if_then_else (gt (match_dup
2)
7653 (label_ref (match_operand
0 "" ""))
7657 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7658 operands[
1] = gen_rtx (COMPARE, mode,
7659 rs6000_compare_op0, rs6000_compare_op1);
7660 operands[
2] = gen_reg_rtx (mode);
7663 (define_expand "ble"
7664 [(set (match_dup
2) (match_dup
1))
7666 (if_then_else (le (match_dup
2)
7668 (label_ref (match_operand
0 "" ""))
7672 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7673 operands[
1] = gen_rtx (COMPARE, mode,
7674 rs6000_compare_op0, rs6000_compare_op1);
7675 operands[
2] = gen_reg_rtx (mode);
7678 (define_expand "bge"
7679 [(set (match_dup
2) (match_dup
1))
7681 (if_then_else (ge (match_dup
2)
7683 (label_ref (match_operand
0 "" ""))
7687 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7688 operands[
1] = gen_rtx (COMPARE, mode,
7689 rs6000_compare_op0, rs6000_compare_op1);
7690 operands[
2] = gen_reg_rtx (mode);
7693 (define_expand "bgtu"
7694 [(set (match_dup
2) (match_dup
1))
7696 (if_then_else (gtu (match_dup
2)
7698 (label_ref (match_operand
0 "" ""))
7702 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7703 rs6000_compare_op0, rs6000_compare_op1);
7704 operands[
2] = gen_reg_rtx (CCUNSmode);
7707 (define_expand "bltu"
7708 [(set (match_dup
2) (match_dup
1))
7710 (if_then_else (ltu (match_dup
2)
7712 (label_ref (match_operand
0 "" ""))
7716 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7717 rs6000_compare_op0, rs6000_compare_op1);
7718 operands[
2] = gen_reg_rtx (CCUNSmode);
7721 (define_expand "bgeu"
7722 [(set (match_dup
2) (match_dup
1))
7724 (if_then_else (geu (match_dup
2)
7726 (label_ref (match_operand
0 "" ""))
7730 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7731 rs6000_compare_op0, rs6000_compare_op1);
7732 operands[
2] = gen_reg_rtx (CCUNSmode);
7735 (define_expand "bleu"
7736 [(set (match_dup
2) (match_dup
1))
7738 (if_then_else (leu (match_dup
2)
7740 (label_ref (match_operand
0 "" ""))
7744 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7745 rs6000_compare_op0, rs6000_compare_op1);
7746 operands[
2] = gen_reg_rtx (CCUNSmode);
7749 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
7750 ;; For SEQ, likewise, except that comparisons with zero should be done
7751 ;; with an scc insns. However, due to the order that combine see the
7752 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
7753 ;; the cases we don't want to handle.
7754 (define_expand "seq"
7755 [(set (match_dup
2) (match_dup
1))
7756 (set (match_operand:SI
0 "gpc_reg_operand" "")
7757 (eq:SI (match_dup
2) (const_int
0)))]
7760 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7761 operands[
1] = gen_rtx (COMPARE, mode,
7762 rs6000_compare_op0, rs6000_compare_op1);
7763 operands[
2] = gen_reg_rtx (mode);
7766 (define_expand "sne"
7767 [(set (match_dup
2) (match_dup
1))
7768 (set (match_operand:SI
0 "gpc_reg_operand" "")
7769 (ne:SI (match_dup
2) (const_int
0)))]
7772 { if (! rs6000_compare_fp_p)
7775 operands[
1] = gen_rtx (COMPARE, CCFPmode,
7776 rs6000_compare_op0, rs6000_compare_op1);
7777 operands[
2] = gen_reg_rtx (CCFPmode);
7780 ;; A >
0 is best done using the portable sequence, so fail in that case.
7781 (define_expand "sgt"
7782 [(set (match_dup
2) (match_dup
1))
7783 (set (match_operand:SI
0 "gpc_reg_operand" "")
7784 (gt:SI (match_dup
2) (const_int
0)))]
7787 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7789 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7792 operands[
1] = gen_rtx (COMPARE, mode,
7793 rs6000_compare_op0, rs6000_compare_op1);
7794 operands[
2] = gen_reg_rtx (mode);
7797 ;; A <
0 is best done in the portable way for A an integer.
7798 (define_expand "slt"
7799 [(set (match_dup
2) (match_dup
1))
7800 (set (match_operand:SI
0 "gpc_reg_operand" "")
7801 (lt:SI (match_dup
2) (const_int
0)))]
7804 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7806 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7809 operands[
1] = gen_rtx (COMPARE, mode,
7810 rs6000_compare_op0, rs6000_compare_op1);
7811 operands[
2] = gen_reg_rtx (mode);
7814 (define_expand "sge"
7815 [(set (match_dup
2) (match_dup
1))
7816 (set (match_operand:SI
0 "gpc_reg_operand" "")
7817 (ge:SI (match_dup
2) (const_int
0)))]
7820 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7821 operands[
1] = gen_rtx (COMPARE, mode,
7822 rs6000_compare_op0, rs6000_compare_op1);
7823 operands[
2] = gen_reg_rtx (mode);
7826 ;; A <=
0 is best done the portable way for A an integer.
7827 (define_expand "sle"
7828 [(set (match_dup
2) (match_dup
1))
7829 (set (match_operand:SI
0 "gpc_reg_operand" "")
7830 (le:SI (match_dup
2) (const_int
0)))]
7833 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7835 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7838 operands[
1] = gen_rtx (COMPARE, mode,
7839 rs6000_compare_op0, rs6000_compare_op1);
7840 operands[
2] = gen_reg_rtx (mode);
7843 (define_expand "sgtu"
7844 [(set (match_dup
2) (match_dup
1))
7845 (set (match_operand:SI
0 "gpc_reg_operand" "")
7846 (gtu:SI (match_dup
2) (const_int
0)))]
7849 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7850 rs6000_compare_op0, rs6000_compare_op1);
7851 operands[
2] = gen_reg_rtx (CCUNSmode);
7854 (define_expand "sltu"
7855 [(set (match_dup
2) (match_dup
1))
7856 (set (match_operand:SI
0 "gpc_reg_operand" "")
7857 (ltu:SI (match_dup
2) (const_int
0)))]
7860 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7861 rs6000_compare_op0, rs6000_compare_op1);
7862 operands[
2] = gen_reg_rtx (CCUNSmode);
7865 (define_expand "sgeu"
7866 [(set (match_dup
2) (match_dup
1))
7867 (set (match_operand:SI
0 "gpc_reg_operand" "")
7868 (geu:SI (match_dup
2) (const_int
0)))]
7871 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7872 rs6000_compare_op0, rs6000_compare_op1);
7873 operands[
2] = gen_reg_rtx (CCUNSmode);
7876 (define_expand "sleu"
7877 [(set (match_dup
2) (match_dup
1))
7878 (set (match_operand:SI
0 "gpc_reg_operand" "")
7879 (leu:SI (match_dup
2) (const_int
0)))]
7882 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7883 rs6000_compare_op0, rs6000_compare_op1);
7884 operands[
2] = gen_reg_rtx (CCUNSmode);
7887 ;; Here are the actual compare insns.
7889 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
7890 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
7891 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
7893 "{cmp%I2|cmpw%I2} %
0,%
1,%
2"
7894 [(set_attr "type" "compare")])
7897 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
7898 (compare:CC (match_operand:DI
1 "gpc_reg_operand" "r")
7899 (match_operand:DI
2 "reg_or_short_operand" "rI")))]
7902 [(set_attr "type" "compare")])
7904 ;; If we are comparing a register for equality with a large constant,
7905 ;; we can do this with an XOR followed by a compare. But we need a scratch
7906 ;; register for the result of the XOR.
7909 [(set (match_operand:CC
0 "cc_reg_operand" "")
7910 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
7911 (match_operand:SI
2 "non_short_cint_operand" "")))
7912 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
7913 "find_single_use (operands[
0], insn,
0)
7914 && (GET_CODE (*find_single_use (operands[
0], insn,
0)) == EQ
7915 || GET_CODE (*find_single_use (operands[
0], insn,
0)) == NE)"
7916 [(set (match_dup
3) (xor:SI (match_dup
1) (match_dup
4)))
7917 (set (match_dup
0) (compare:CC (match_dup
3) (match_dup
5)))]
7920 /* Get the constant we are comparing against, C, and see what it looks like
7921 sign-extended to
16 bits. Then see what constant could be XOR'ed
7922 with C to get the sign-extended value. */
7924 int c = INTVAL (operands[
2]);
7925 int sextc = (c <<
16) >>
16;
7926 int xorv = c ^ sextc;
7928 operands[
4] = gen_rtx (CONST_INT, VOIDmode, xorv);
7929 operands[
5] = gen_rtx (CONST_INT, VOIDmode, sextc);
7933 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
7934 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
7935 (match_operand:SI
2 "reg_or_u_short_operand" "rI")))]
7937 "{cmpl%I2|cmplw%I2} %
0,%
1,%W2"
7938 [(set_attr "type" "compare")])
7941 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
7942 (compare:CCUNS (match_operand:DI
1 "gpc_reg_operand" "r")
7943 (match_operand:DI
2 "reg_or_u_short_operand" "rI")))]
7945 "cmpld%I2 %
0,%
1,%W2"
7946 [(set_attr "type" "compare")])
7948 ;; The following two insns don't exist as single insns, but if we provide
7949 ;; them, we can swap an add and compare, which will enable us to overlap more
7950 ;; of the required delay between a compare and branch. We generate code for
7951 ;; them by splitting.
7954 [(set (match_operand:CC
3 "cc_reg_operand" "=y")
7955 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
7956 (match_operand:SI
2 "short_cint_operand" "i")))
7957 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7958 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
7961 [(set_attr "length" "
8")])
7964 [(set (match_operand:CCUNS
3 "cc_reg_operand" "=y")
7965 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
7966 (match_operand:SI
2 "u_short_cint_operand" "i")))
7967 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7968 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
7971 [(set_attr "length" "
8")])
7974 [(set (match_operand:CC
3 "cc_reg_operand" "")
7975 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
7976 (match_operand:SI
2 "short_cint_operand" "")))
7977 (set (match_operand:SI
0 "gpc_reg_operand" "")
7978 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
7980 [(set (match_dup
3) (compare:CC (match_dup
1) (match_dup
2)))
7981 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
7984 [(set (match_operand:CCUNS
3 "cc_reg_operand" "")
7985 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "")
7986 (match_operand:SI
2 "u_short_cint_operand" "")))
7987 (set (match_operand:SI
0 "gpc_reg_operand" "")
7988 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
7990 [(set (match_dup
3) (compare:CCUNS (match_dup
1) (match_dup
2)))
7991 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
7994 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
7995 (compare:CCFP (match_operand:SF
1 "gpc_reg_operand" "f")
7996 (match_operand:SF
2 "gpc_reg_operand" "f")))]
7999 [(set_attr "type" "fpcompare")])
8002 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
8003 (compare:CCFP (match_operand:DF
1 "gpc_reg_operand" "f")
8004 (match_operand:DF
2 "gpc_reg_operand" "f")))]
8007 [(set_attr "type" "fpcompare")])
8009 ;; Now we have the scc insns. We can do some combinations because of the
8010 ;; way the machine works.
8012 ;; Note that this is probably faster if we can put an insn between the
8013 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
8014 ;; cases the insns below which don't use an intermediate CR field will
8017 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8018 (match_operator:SI
1 "scc_comparison_operator"
8019 [(match_operand
2 "cc_reg_operand" "y")
8022 "%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%J1,
1"
8023 [(set_attr "length" "
12")])
8026 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8027 (compare:CC (match_operator:SI
1 "scc_comparison_operator"
8028 [(match_operand
2 "cc_reg_operand" "y")
8031 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
8032 (match_op_dup
1 [(match_dup
2) (const_int
0)]))]
8034 "%D1mfcr %
3\;{rlinm.|rlwinm.} %
3,%
3,%J1,
1"
8035 [(set_attr "type" "delayed_compare")
8036 (set_attr "length" "
12")])
8039 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8040 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
8041 [(match_operand
2 "cc_reg_operand" "y")
8043 (match_operand:SI
3 "const_int_operand" "n")))]
8047 int is_bit = ccr_bit (operands[
1],
1);
8048 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
8051 if (is_bit >= put_bit)
8052 count = is_bit - put_bit;
8054 count =
32 - (put_bit - is_bit);
8056 operands[
4] = gen_rtx (CONST_INT, VOIDmode, count);
8057 operands[
5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
8059 return
\"%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%
4,%
5,%
5\";
8061 [(set_attr "length" "
12")])
8064 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8066 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
8067 [(match_operand
2 "cc_reg_operand" "y")
8069 (match_operand:SI
3 "const_int_operand" "n"))
8071 (set (match_operand:SI
4 "gpc_reg_operand" "=r")
8072 (ashift:SI (match_op_dup
1 [(match_dup
2) (const_int
0)])
8077 int is_bit = ccr_bit (operands[
1],
1);
8078 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
8081 if (is_bit >= put_bit)
8082 count = is_bit - put_bit;
8084 count =
32 - (put_bit - is_bit);
8086 operands[
5] = gen_rtx (CONST_INT, VOIDmode, count);
8087 operands[
6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
8089 return
\"%D1mfcr %
4\;{rlinm.|rlwinm.} %
4,%
4,%
5,%
6,%
6\";
8091 [(set_attr "type" "delayed_compare")
8092 (set_attr "length" "
12")])
8094 ;; If we are comparing the result of two comparisons, this can be done
8095 ;; using creqv or crxor.
8098 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y")
8099 (compare:CCEQ (match_operator
1 "scc_comparison_operator"
8100 [(match_operand
2 "cc_reg_operand" "y")
8102 (match_operator
3 "scc_comparison_operator"
8103 [(match_operand
4 "cc_reg_operand" "y")
8105 "REGNO (operands[
2]) != REGNO (operands[
4])"
8108 enum rtx_code code1, code2;
8110 code1 = GET_CODE (operands[
1]);
8111 code2 = GET_CODE (operands[
3]);
8113 if ((code1 == EQ || code1 == LT || code1 == GT
8114 || code1 == LTU || code1 == GTU
8115 || (code1 != NE && GET_MODE (operands[
2]) == CCFPmode))
8117 (code2 == EQ || code2 == LT || code2 == GT
8118 || code2 == LTU || code2 == GTU
8119 || (code2 != NE && GET_MODE (operands[
4]) == CCFPmode)))
8120 return
\"%C1%C3crxor %E0,%j1,%j3
\";
8122 return
\"%C1%C3creqv %E0,%j1,%j3
\";
8124 [(set_attr "length" "
12")])
8126 ;; There is a
3 cycle delay between consecutive mfcr instructions
8127 ;; so it is useful to combine
2 scc instructions to use only one mfcr.
8130 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8131 (match_operator:SI
1 "scc_comparison_operator"
8132 [(match_operand
2 "cc_reg_operand" "y")
8134 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
8135 (match_operator:SI
4 "scc_comparison_operator"
8136 [(match_operand
5 "cc_reg_operand" "y")
8138 "REGNO (operands[
2]) != REGNO (operands[
5])"
8139 "%D1%D4mfcr %
3\;{rlinm|rlwinm} %
0,%
3,%J1,
1\;{rlinm|rlwinm} %
3,%
3,%J4,
1"
8140 [(set_attr "length" "
20")])
8142 ;; There are some scc insns that can be done directly, without a compare.
8143 ;; These are faster because they don't involve the communications between
8144 ;; the FXU and branch units. In fact, we will be replacing all of the
8145 ;; integer scc insns here or in the portable methods in emit_store_flag.
8147 ;; Also support (neg (scc ..)) since that construct is used to replace
8148 ;; branches, (plus (scc ..) ..) since that construct is common and
8149 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
8150 ;; cases where it is no more expensive than (neg (scc ..)).
8152 ;; Have reload force a constant into a register for the simple insns that
8153 ;; otherwise won't accept constants. We do this because it is faster than
8154 ;; the cmp/mfcr sequence we would otherwise generate.
8157 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
8158 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8159 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I")))
8160 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
8163 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
8164 {sfi|subfic} %
3,%
1,
0\;{ae|adde} %
0,%
3,%
1
8165 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
8166 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
8167 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0"
8168 [(set_attr "length" "
12,
8,
12,
12,
12")])
8171 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x,x,x,x")
8173 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8174 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
8176 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
8177 (eq:SI (match_dup
1) (match_dup
2)))
8178 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
8181 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
8182 {sfi|subfic} %
3,%
1,
0\;{ae.|adde.} %
0,%
3,%
1
8183 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
8184 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
8185 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0"
8186 [(set_attr "type" "compare")
8187 (set_attr "length" "
12,
8,
12,
12,
12")])
8189 ;; We have insns of the form shown by the first define_insn below. If
8190 ;; there is something inside the comparison operation, we must split it.
8192 [(set (match_operand:SI
0 "gpc_reg_operand" "")
8193 (plus:SI (match_operator
1 "comparison_operator"
8194 [(match_operand:SI
2 "" "")
8196 "reg_or_cint_operand" "")])
8197 (match_operand:SI
4 "gpc_reg_operand" "")))
8198 (clobber (match_operand:SI
5 "register_operand" ""))]
8199 "! gpc_reg_operand (operands[
2], SImode)"
8200 [(set (match_dup
5) (match_dup
2))
8201 (set (match_dup
2) (plus:SI (match_op_dup
1 [(match_dup
2) (match_dup
3)])
8205 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
8206 (plus:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8207 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
8208 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r")))
8209 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
8212 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8213 {sfi|subfic} %
4,%
1,
0\;{aze|addze} %
0,%
3
8214 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8215 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8216 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3"
8217 [(set_attr "length" "
12,
8,
12,
12,
12")])
8220 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x,x")
8223 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8224 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
8225 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
8227 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
8230 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8231 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
0,%
3
8232 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8233 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8234 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
8235 [(set_attr "type" "compare")
8236 (set_attr "length" "
12,
8,
12,
12,
12")])
8239 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x,x,x,x")
8242 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8243 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
8244 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
8246 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
8247 (plus:SI (eq:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8248 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
8251 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8252 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
4,%
3
8253 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8254 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8255 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
8256 [(set_attr "type" "compare")
8257 (set_attr "length" "
12,
8,
12,
12,
12")])
8260 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
8261 (neg:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8262 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))))]
8265 xor %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8266 {ai|addic} %
0,%
1,-
1\;{sfe|subfe} %
0,%
0,%
0
8267 {xoril|xori} %
0,%
1,%b2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8268 {xoriu|xoris} %
0,%
1,%u2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8269 {sfi|subfic} %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
8270 [(set_attr "length" "
12,
8,
12,
12,
12")])
8272 ;; Simplify (ne X (const_int
0)) on the PowerPC. No need to on the Power,
8273 ;; since it nabs/sr is just as fast.
8275 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8276 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8278 (clobber (match_scratch:SI
2 "=&r"))]
8280 "{ai|addic} %
2,%
1,-
1\;{sfe|subfe} %
0,%
2,%
1"
8281 [(set_attr "length" "
8")])
8283 ;; This is what (plus (ne X (const_int
0)) Y) looks like.
8285 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8286 (plus:SI (lshiftrt:SI
8287 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8289 (match_operand:SI
2 "gpc_reg_operand" "r")))
8290 (clobber (match_scratch:SI
3 "=&r"))]
8292 "{ai|addic} %
3,%
1,-
1\;{aze|addze} %
0,%
2"
8293 [(set_attr "length" "
8")])
8296 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8298 (plus:SI (lshiftrt:SI
8299 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8301 (match_operand:SI
2 "gpc_reg_operand" "r"))
8303 (clobber (match_scratch:SI
3 "=&r"))]
8305 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
3,%
2"
8306 [(set_attr "type" "compare")
8307 (set_attr "length" "
8")])
8310 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8312 (plus:SI (lshiftrt:SI
8313 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8315 (match_operand:SI
2 "gpc_reg_operand" "r"))
8317 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8318 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup
1))) (const_int
31))
8320 (clobber (match_scratch:SI
3 "=&r"))]
8322 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
0,%
2"
8323 [(set_attr "type" "compare")
8324 (set_attr "length" "
8")])
8327 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8328 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8329 (match_operand:SI
2 "reg_or_short_operand" "r,O")))
8330 (clobber (match_scratch:SI
3 "=r,X"))]
8333 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3
8334 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8335 [(set_attr "length" "
12")])
8338 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x")
8340 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8341 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8343 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8344 (le:SI (match_dup
1) (match_dup
2)))
8345 (clobber (match_scratch:SI
3 "=r,X"))]
8348 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3
8349 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8350 [(set_attr "type" "compare,delayed_compare")
8351 (set_attr "length" "
12")])
8354 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8355 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8356 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8357 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8358 (clobber (match_scratch:SI
4 "=&r,&r"))]
8361 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8362 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze|addze} %
0,%
3"
8363 [(set_attr "length" "
12")])
8366 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8368 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8369 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8370 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8372 (clobber (match_scratch:SI
4 "=&r,&r"))]
8375 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8376 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
4,%
3"
8377 [(set_attr "type" "compare")
8378 (set_attr "length" "
12")])
8381 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8383 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8384 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8385 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8387 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8388 (plus:SI (le:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8389 (clobber (match_scratch:SI
4 "=&r,&r"))]
8392 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8393 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
0,%
3"
8394 [(set_attr "type" "compare")
8395 (set_attr "length" "
12")])
8398 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8399 (neg:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8400 (match_operand:SI
2 "reg_or_short_operand" "r,O"))))]
8403 doz %
0,%
2,%
1\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8404 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8405 [(set_attr "length" "
12")])
8408 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8409 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8410 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
8412 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
8413 [(set_attr "length" "
12")])
8416 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8418 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8419 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8421 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8422 (leu:SI (match_dup
1) (match_dup
2)))]
8424 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
8425 [(set_attr "type" "compare")
8426 (set_attr "length" "
12")])
8429 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8430 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8431 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8432 (match_operand:SI
3 "gpc_reg_operand" "r")))
8433 (clobber (match_scratch:SI
4 "=&r"))]
8435 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze|addze} %
0,%
3"
8436 [(set_attr "length" "
8")])
8439 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8441 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8442 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8443 (match_operand:SI
3 "gpc_reg_operand" "r"))
8445 (clobber (match_scratch:SI
4 "=&r"))]
8447 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
4,%
3"
8448 [(set_attr "type" "compare")
8449 (set_attr "length" "
8")])
8452 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8454 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8455 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8456 (match_operand:SI
3 "gpc_reg_operand" "r"))
8458 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8459 (plus:SI (leu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8460 (clobber (match_scratch:SI
4 "=&r"))]
8462 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
0,%
3"
8463 [(set_attr "type" "compare")
8464 (set_attr "length" "
8")])
8467 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8468 (neg:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8469 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8471 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0"
8472 [(set_attr "length" "
12")])
8475 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8477 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8478 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8479 (match_operand:SI
3 "gpc_reg_operand" "r")))
8480 (clobber (match_scratch:SI
4 "=&r"))]
8482 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
8483 [(set_attr "length" "
12")])
8486 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8489 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8490 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8491 (match_operand:SI
3 "gpc_reg_operand" "r"))
8493 (clobber (match_scratch:SI
4 "=&r"))]
8495 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
8496 [(set_attr "type" "compare")
8497 (set_attr "length" "
12")])
8500 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8503 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8504 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8505 (match_operand:SI
3 "gpc_reg_operand" "r"))
8507 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8508 (and:SI (neg:SI (leu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
8509 (clobber (match_scratch:SI
4 "=&r"))]
8511 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
8512 [(set_attr "type" "compare")
8513 (set_attr "length" "
12")])
8516 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8517 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8518 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
8520 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8521 [(set_attr "length" "
12")])
8524 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8526 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8527 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8529 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8530 (lt:SI (match_dup
1) (match_dup
2)))]
8532 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8533 [(set_attr "type" "delayed_compare")
8534 (set_attr "length" "
12")])
8537 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8538 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8539 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8540 (match_operand:SI
3 "gpc_reg_operand" "r")))
8541 (clobber (match_scratch:SI
4 "=&r"))]
8543 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
8544 [(set_attr "length" "
12")])
8547 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8549 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8550 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8551 (match_operand:SI
3 "gpc_reg_operand" "r"))
8553 (clobber (match_scratch:SI
4 "=&r"))]
8555 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
8556 [(set_attr "type" "compare")
8557 (set_attr "length" "
12")])
8560 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8562 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8563 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8564 (match_operand:SI
3 "gpc_reg_operand" "r"))
8566 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8567 (plus:SI (lt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8568 (clobber (match_scratch:SI
4 "=&r"))]
8570 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
8571 [(set_attr "type" "compare")
8572 (set_attr "length" "
12")])
8575 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8576 (neg:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8577 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8579 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8580 [(set_attr "length" "
12")])
8583 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8584 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8585 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
8588 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0
8589 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
8590 [(set_attr "length" "
12")])
8593 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
8595 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8596 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8598 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8599 (ltu:SI (match_dup
1) (match_dup
2)))]
8602 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0
8603 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
8604 [(set_attr "type" "compare")
8605 (set_attr "length" "
12")])
8608 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
8609 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r,r")
8610 (match_operand:SI
2 "reg_or_neg_short_operand" "r,r,P,P"))
8611 (match_operand:SI
3 "reg_or_short_operand" "r,I,r,I")))
8612 (clobber (match_scratch:SI
4 "=&r,r,&r,r"))]
8615 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8616 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8617 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8618 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
8619 [(set_attr "length" "
12")])
8622 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8624 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8625 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8626 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8628 (clobber (match_scratch:SI
4 "=&r,&r"))]
8631 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3
8632 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3"
8633 [(set_attr "type" "compare")
8634 (set_attr "length" "
12")])
8637 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8639 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8640 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8641 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8643 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8644 (plus:SI (ltu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8645 (clobber (match_scratch:SI
4 "=&r,&r"))]
8648 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3
8649 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
8650 [(set_attr "type" "compare")
8651 (set_attr "length" "
12")])
8654 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8655 (neg:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8656 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))))]
8659 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0
8660 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0"
8661 [(set_attr "length" "
8")])
8664 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8665 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8666 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8667 (clobber (match_scratch:SI
3 "=r"))]
8669 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3"
8670 [(set_attr "length" "
12")])
8673 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8675 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8676 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8678 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8679 (ge:SI (match_dup
1) (match_dup
2)))
8680 (clobber (match_scratch:SI
3 "=r"))]
8682 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3"
8683 [(set_attr "type" "compare")
8684 (set_attr "length" "
12")])
8687 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8688 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8689 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8690 (match_operand:SI
3 "gpc_reg_operand" "r")))
8691 (clobber (match_scratch:SI
4 "=&r"))]
8693 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3"
8694 [(set_attr "length" "
12")])
8697 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8699 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8700 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8701 (match_operand:SI
3 "gpc_reg_operand" "r"))
8703 (clobber (match_scratch:SI
4 "=&r"))]
8705 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
8706 [(set_attr "type" "compare")
8707 (set_attr "length" "
12")])
8710 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8712 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8713 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8714 (match_operand:SI
3 "gpc_reg_operand" "r"))
8716 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8717 (plus:SI (ge:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8718 (clobber (match_scratch:SI
4 "=&r"))]
8720 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
8721 [(set_attr "type" "compare")
8722 (set_attr "length" "
12")])
8725 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8726 (neg:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8727 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8729 "doz%I2 %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
8730 [(set_attr "length" "
12")])
8732 ;; This is (and (neg (ge X (const_int
0))) Y).
8734 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8737 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8739 (match_operand:SI
2 "gpc_reg_operand" "r")))
8740 (clobber (match_scratch:SI
3 "=&r"))]
8742 "{srai|srawi} %
3,%
1,
31\;andc %
0,%
2,%
3"
8743 [(set_attr "length" "
8")])
8746 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8750 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8752 (match_operand:SI
2 "gpc_reg_operand" "r"))
8754 (clobber (match_scratch:SI
3 "=&r"))]
8756 "{srai|srawi} %
3,%
1,
31\;andc. %
3,%
2,%
3"
8757 [(set_attr "type" "compare")
8758 (set_attr "length" "
8")])
8761 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8765 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8767 (match_operand:SI
2 "gpc_reg_operand" "r"))
8769 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8770 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup
1))
8773 (clobber (match_scratch:SI
3 "=&r"))]
8775 "{srai|srawi} %
3,%
1,
31\;andc. %
0,%
2,%
3"
8776 [(set_attr "type" "compare")
8777 (set_attr "length" "
8")])
8780 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8781 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8782 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
8785 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0
8786 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
8787 [(set_attr "length" "
12")])
8790 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
8792 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8793 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8795 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8796 (geu:SI (match_dup
1) (match_dup
2)))]
8799 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0
8800 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
8801 [(set_attr "type" "compare")
8802 (set_attr "length" "
12")])
8805 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8806 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8807 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8808 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8809 (clobber (match_scratch:SI
4 "=&r,&r"))]
8812 {sf|subfc} %
4,%
2,%
1\;{aze|addze} %
0,%
3
8813 {ai|addic} %
4,%
1,%n2\;{aze|addze} %
0,%
3"
8814 [(set_attr "length" "
8")])
8817 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8819 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8820 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8821 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8823 (clobber (match_scratch:SI
4 "=&r,&r"))]
8826 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
4,%
3
8827 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
8828 [(set_attr "type" "compare")
8829 (set_attr "length" "
8")])
8832 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8834 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8835 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8836 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8838 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8839 (plus:SI (geu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8840 (clobber (match_scratch:SI
4 "=&r,&r"))]
8843 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
0,%
3
8844 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
8845 [(set_attr "type" "compare")
8846 (set_attr "length" "
8")])
8849 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8850 (neg:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8851 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))]
8854 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0
8855 {sfi|subfic} %
0,%
1,-
1\;{a%I2|add%I2c} %
0,%
0,%
2\;{sfe|subfe} %
0,%
0,%
0"
8856 [(set_attr "length" "
12")])
8859 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8861 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8862 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8863 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8864 (clobber (match_scratch:SI
4 "=&r,&r"))]
8867 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4
8868 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
8869 [(set_attr "length" "
12")])
8872 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8875 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8876 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8877 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8879 (clobber (match_scratch:SI
4 "=&r,&r"))]
8882 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4
8883 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
8884 [(set_attr "type" "compare")
8885 (set_attr "length" "
12")])
8888 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8891 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8892 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8893 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8895 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8896 (and:SI (neg:SI (geu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
8897 (clobber (match_scratch:SI
4 "=&r,&r"))]
8900 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4
8901 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
8902 [(set_attr "type" "compare")
8903 (set_attr "length" "
12")])
8906 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8907 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8910 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8911 [(set_attr "length" "
12")])
8914 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
8916 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8919 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8920 (gt:SI (match_dup
1) (const_int
0)))]
8922 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8923 [(set_attr "type" "delayed_compare")
8924 (set_attr "length" "
12")])
8927 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8928 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8929 (match_operand:SI
2 "reg_or_short_operand" "r")))]
8931 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8932 [(set_attr "length" "
12")])
8935 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8937 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8938 (match_operand:SI
2 "reg_or_short_operand" "r"))
8940 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8941 (gt:SI (match_dup
1) (match_dup
2)))]
8943 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8944 [(set_attr "type" "delayed_compare")
8945 (set_attr "length" "
12")])
8948 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8949 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8951 (match_operand:SI
2 "gpc_reg_operand" "r")))
8952 (clobber (match_scratch:SI
3 "=&r"))]
8954 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze|addze} %
0,%
2"
8955 [(set_attr "length" "
12")])
8958 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8960 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8962 (match_operand:SI
2 "gpc_reg_operand" "r"))
8964 (clobber (match_scratch:SI
3 "=&r"))]
8966 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
0,%
2"
8967 [(set_attr "type" "compare")
8968 (set_attr "length" "
12")])
8971 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8973 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8975 (match_operand:SI
2 "gpc_reg_operand" "r"))
8977 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8978 (plus:SI (gt:SI (match_dup
1) (const_int
0)) (match_dup
2)))
8979 (clobber (match_scratch:SI
3 "=&r"))]
8981 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
3,%
2"
8982 [(set_attr "type" "compare")
8983 (set_attr "length" "
12")])
8986 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8987 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8988 (match_operand:SI
2 "reg_or_short_operand" "r"))
8989 (match_operand:SI
3 "gpc_reg_operand" "r")))
8990 (clobber (match_scratch:SI
4 "=&r"))]
8992 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
8993 [(set_attr "length" "
12")])
8996 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8998 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8999 (match_operand:SI
2 "reg_or_short_operand" "r"))
9000 (match_operand:SI
3 "gpc_reg_operand" "r"))
9002 (clobber (match_scratch:SI
4 "=&r"))]
9004 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
9005 [(set_attr "type" "compare")
9006 (set_attr "length" "
12")])
9009 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
9011 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
9012 (match_operand:SI
2 "reg_or_short_operand" "r"))
9013 (match_operand:SI
3 "gpc_reg_operand" "r"))
9015 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
9016 (plus:SI (gt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
9017 (clobber (match_scratch:SI
4 "=&r"))]
9019 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
9020 [(set_attr "type" "compare")
9021 (set_attr "length" "
12")])
9024 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
9025 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
9028 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
9029 [(set_attr "length" "
12")])
9032 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
9033 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
9034 (match_operand:SI
2 "reg_or_short_operand" "r"))))]
9036 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
9037 [(set_attr "length" "
12")])
9040 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
9041 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
9042 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
9044 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
9045 [(set_attr "length" "
12")])
9048 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
9050 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
9051 (match_operand:SI
2 "reg_or_short_operand" "rI"))
9053 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
9054 (gtu:SI (match_dup
1) (match_dup
2)))]
9056 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
9057 [(set_attr "type" "compare")
9058 (set_attr "length" "
12")])
9061 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
9062 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
9063 (match_operand:SI
2 "reg_or_short_operand" "I,r,rI"))
9064 (match_operand:SI
3 "reg_or_short_operand" "r,r,I")))
9065 (clobber (match_scratch:SI
4 "=&r,&r,&r"))]
9068 {ai|addic} %
4,%
1,%k2\;{aze|addze} %
0,%
3
9069 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
9070 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
9071 [(set_attr "length" "
8,
12,
12")])
9074 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
9076 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
9077 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
9078 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
9080 (clobber (match_scratch:SI
4 "=&r,&r"))]
9083 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
9084 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
9085 [(set_attr "type" "compare")
9086 (set_attr "length" "
8,
12")])
9089 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
9091 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
9092 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
9093 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
9095 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
9096 (plus:SI (gtu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
9097 (clobber (match_scratch:SI
4 "=&r,&r"))]
9100 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
9101 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
9102 [(set_attr "type" "compare")
9103 (set_attr "length" "
8,
12")])
9106 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
9107 (neg:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
9108 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
9110 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0"
9111 [(set_attr "length" "
8")])
9113 ;; Define both directions of branch and return. If we need a reload
9114 ;; register, we'd rather use CR0 since it is much easier to copy a
9115 ;; register CC value to there.
9119 (if_then_else (match_operator
1 "branch_comparison_operator"
9121 "cc_reg_operand" "x,?y")
9123 (label_ref (match_operand
0 "" ""))
9128 if (get_attr_length (insn) ==
8)
9129 return
\"%C1bc %t1,%j1,%l0
\";
9131 return
\"%C1bc %T1,%j1,%$+
8\;b %l0
\";
9134 [(set_attr "type" "branch")])
9138 (if_then_else (match_operator
0 "branch_comparison_operator"
9140 "cc_reg_operand" "x,?y")
9145 "{%C0bcr|%C0bclr} %t0,%j0"
9146 [(set_attr "type" "branch")
9147 (set_attr "length" "
8")])
9151 (if_then_else (match_operator
1 "branch_comparison_operator"
9153 "cc_reg_operand" "x,?y")
9156 (label_ref (match_operand
0 "" ""))))]
9160 if (get_attr_length (insn) ==
8)
9161 return
\"%C1bc %T1,%j1,%l0
\";
9163 return
\"%C1bc %t1,%j1,%$+
8\;b %l0
\";
9165 [(set_attr "type" "branch")])
9169 (if_then_else (match_operator
0 "branch_comparison_operator"
9171 "cc_reg_operand" "x,?y")
9176 "{%C0bcr|%C0bclr} %T0,%j0"
9177 [(set_attr "type" "branch")
9178 (set_attr "length" "
8")])
9180 ;; Unconditional branch and return.
9184 (label_ref (match_operand
0 "" "")))]
9187 [(set_attr "type" "branch")])
9189 (define_insn "return"
9193 [(set_attr "type" "jmpreg")])
9195 (define_insn "indirect_jump"
9196 [(set (pc) (match_operand:SI
0 "register_operand" "c,l"))]
9201 [(set_attr "type" "jmpreg")])
9204 [(set (pc) (match_operand:DI
0 "register_operand" "c,l"))]
9209 [(set_attr "type" "jmpreg")])
9211 ;; Table jump for switch statements:
9212 (define_expand "tablejump"
9213 [(use (match_operand
0 "" ""))
9214 (use (label_ref (match_operand
1 "" "")))]
9219 emit_jump_insn (gen_tablejumpsi (operands[
0], operands[
1]));
9221 emit_jump_insn (gen_tablejumpdi (operands[
0], operands[
1]));
9225 (define_expand "tablejumpsi"
9227 (plus:SI (match_operand:SI
0 "" "")
9229 (parallel [(set (pc) (match_dup
3))
9230 (use (label_ref (match_operand
1 "" "")))])]
9233 { operands[
0] = force_reg (SImode, operands[
0]);
9234 operands[
2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[
1]));
9235 operands[
3] = gen_reg_rtx (SImode);
9238 (define_expand "tablejumpdi"
9240 (plus:DI (match_operand:DI
0 "" "")
9242 (parallel [(set (pc) (match_dup
3))
9243 (use (label_ref (match_operand
1 "" "")))])]
9246 { operands[
0] = force_reg (DImode, operands[
0]);
9247 operands[
2] = force_reg (DImode, gen_rtx (LABEL_REF, VOIDmode, operands[
1]));
9248 operands[
3] = gen_reg_rtx (DImode);
9253 (match_operand:SI
0 "register_operand" "c,l"))
9254 (use (label_ref (match_operand
1 "" "")))]
9259 [(set_attr "type" "jmpreg")])
9263 (match_operand:DI
0 "register_operand" "c,l"))
9264 (use (label_ref (match_operand
1 "" "")))]
9269 [(set_attr "type" "jmpreg")])
9276 ;; Define the subtract-one-and-jump insns, starting with the template
9277 ;; so loop.c knows what to generate.
9279 (define_expand "decrement_and_branch_on_count"
9280 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI
0 "register_operand" "")
9282 (label_ref (match_operand
1 "" ""))
9285 (plus:SI (match_dup
0)
9287 (clobber (match_scratch:CC
2 ""))
9288 (clobber (match_scratch:SI
3 ""))])]
9292 ;; We need to be able to do this for any operand, including MEM, or we
9293 ;; will cause reload to blow up since we don't allow output reloads on
9295 ;; In order that the length attribute is calculated correctly, the
9296 ;; label MUST be operand
0.
9300 (if_then_else (ne (match_operand:SI
1 "register_operand" "c,*r,*r")
9302 (label_ref (match_operand
0 "" ""))
9304 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9305 (plus:SI (match_dup
1)
9307 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9308 (clobber (match_scratch:SI
4 "=X,X,r"))]
9312 if (which_alternative !=
0)
9314 else if (get_attr_length (insn) ==
8)
9315 return
\"{bdn|bdnz} %l0
\";
9317 return
\"bdz %$+
8\;b %l0
\";
9319 [(set_attr "type" "branch")
9320 (set_attr "length" "*,
12,
16")])
9324 (if_then_else (ne (match_operand:SI
1 "register_operand" "c,*r,*r")
9327 (label_ref (match_operand
0 "" ""))))
9328 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9329 (plus:SI (match_dup
1)
9331 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9332 (clobber (match_scratch:SI
4 "=X,X,r"))]
9336 if (which_alternative !=
0)
9338 else if (get_attr_length (insn) ==
8)
9341 return
\"{bdn|bdnz} %$+
8\;b %l0
\";
9343 [(set_attr "type" "branch")
9344 (set_attr "length" "*,
12,
16")])
9346 ;; Similar, but we can use GE since we have a REG_NONNEG.
9349 (if_then_else (ge (match_operand:SI
1 "register_operand" "c,*r,*r")
9351 (label_ref (match_operand
0 "" ""))
9353 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9354 (plus:SI (match_dup
1)
9356 (clobber (match_scratch:CC
3 "=X,&x,&X"))
9357 (clobber (match_scratch:SI
4 "=X,X,r"))]
9358 "find_reg_note (insn, REG_NONNEG,
0)"
9361 if (which_alternative !=
0)
9363 else if (get_attr_length (insn) ==
8)
9364 return
\"{bdn|bdnz} %l0
\";
9366 return
\"bdz %$+
8\;b %l0
\";
9368 [(set_attr "type" "branch")
9369 (set_attr "length" "*,
12,
16")])
9373 (if_then_else (ge (match_operand:SI
1 "register_operand" "c,*r,*r")
9376 (label_ref (match_operand
0 "" ""))))
9377 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9378 (plus:SI (match_dup
1)
9380 (clobber (match_scratch:CC
3 "=X,&x,&X"))
9381 (clobber (match_scratch:SI
4 "=X,X,r"))]
9382 "find_reg_note (insn, REG_NONNEG,
0)"
9385 if (which_alternative !=
0)
9387 else if (get_attr_length (insn) ==
8)
9390 return
\"{bdn|bdnz} %$+
8\;b %l0
\";
9392 [(set_attr "type" "branch")
9393 (set_attr "length" "*,
12,
16")])
9397 (if_then_else (eq (match_operand:SI
1 "register_operand" "c,*r,*r")
9399 (label_ref (match_operand
0 "" ""))
9401 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9402 (plus:SI (match_dup
1)
9404 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9405 (clobber (match_scratch:SI
4 "=X,X,r"))]
9409 if (which_alternative !=
0)
9411 else if (get_attr_length (insn) ==
8)
9414 return
\"{bdn|bdnz} %$+
8\;b %l0
\";
9416 [(set_attr "type" "branch")
9417 (set_attr "length" "*,
12,
16")])
9421 (if_then_else (eq (match_operand:SI
1 "register_operand" "c,*r,*r")
9424 (label_ref (match_operand
0 "" ""))))
9425 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9426 (plus:SI (match_dup
1)
9428 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9429 (clobber (match_scratch:SI
4 "=X,X,r"))]
9433 if (which_alternative !=
0)
9435 else if (get_attr_length (insn) ==
8)
9436 return
\"{bdn|bdnz} %l0
\";
9438 return
\"bdz %$+
8\;b %l0
\";
9440 [(set_attr "type" "branch")
9441 (set_attr "length" "*,
12,
16")])
9445 (if_then_else (match_operator
2 "comparison_operator"
9446 [(match_operand:SI
1 "gpc_reg_operand" "")
9448 (match_operand
5 "" "")
9449 (match_operand
6 "" "")))
9450 (set (match_operand:SI
0 "gpc_reg_operand" "")
9451 (plus:SI (match_dup
1)
9453 (clobber (match_scratch:CC
3 ""))
9454 (clobber (match_scratch:SI
4 ""))]
9456 [(parallel [(set (match_dup
3)
9457 (compare:CC (plus:SI (match_dup
1)
9461 (plus:SI (match_dup
1)
9463 (set (pc) (if_then_else (match_dup
7)
9467 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],
9472 (if_then_else (match_operator
2 "comparison_operator"
9473 [(match_operand:SI
1 "gpc_reg_operand" "")
9475 (match_operand
5 "" "")
9476 (match_operand
6 "" "")))
9477 (set (match_operand:SI
0 "general_operand" "")
9478 (plus:SI (match_dup
1) (const_int -
1)))
9479 (clobber (match_scratch:CC
3 ""))
9480 (clobber (match_scratch:SI
4 ""))]
9481 "reload_completed && ! gpc_reg_operand (operands[
0], SImode)"
9482 [(parallel [(set (match_dup
3)
9483 (compare:CC (plus:SI (match_dup
1)
9487 (plus:SI (match_dup
1)
9491 (set (pc) (if_then_else (match_dup
7)
9495 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],