1 ;; Machine description for IBM RISC System
6000 (POWER) for GNU C compiler
2 ;; Copyright (C)
1990,
1991,
1992,
1993,
1994,
1995,
1996,
1997,
1998,
3 ;;
1999,
2000 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version
2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
21 ;; Boston, MA
02111-
1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
`unspec' values used in rs6000.md:
27 ;; 0 frsp for POWER machines
29 ;; 5 used to tie the stack contents and the stack pointer
30 ;; 6 address of a word pointing to the TOC
31 ;; 7 address of the TOC (more-or-less)
38 ;; Define an insn type attribute. This is used in function unit delay
40 (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
41 (const_string "integer"))
44 ; '(pc)' in the following doesn't include the instruction itself; it is
45 ; calculated as if the instruction had zero size.
46 (define_attr "length" ""
47 (if_then_else (eq_attr "type" "branch")
48 (if_then_else (and (ge (minus (match_dup 0) (pc))
50 (lt (minus (match_dup 0) (pc))
56 ;; Processor type -- this attribute must exactly match the processor_type
57 ;; enumeration in rs6000.h.
59 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"
60 (const (symbol_ref "rs6000_cpu_attr")))
62 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
63 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
65 ; Load/Store Unit -- pure PowerPC only
66 ; (POWER and 601 use Integer Unit)
67 (define_function_unit "lsu" 1 0
68 (and (eq_attr "type" "load")
69 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
72 (define_function_unit "lsu" 1 0
73 (and (eq_attr "type" "store,fpstore")
74 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
77 (define_function_unit "lsu" 1 0
78 (and (eq_attr "type" "fpload")
79 (eq_attr "cpu" "mpccore,ppc603,ppc750"))
82 (define_function_unit "lsu" 1 0
83 (and (eq_attr "type" "fpload")
84 (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
87 (define_function_unit "iu" 1 0
88 (and (eq_attr "type" "load")
89 (eq_attr "cpu" "rios1,ppc403,ppc601"))
92 (define_function_unit "iu" 1 0
93 (and (eq_attr "type" "store,fpstore")
94 (eq_attr "cpu" "rios1,ppc403,ppc601"))
97 (define_function_unit "fpu" 1 0
98 (and (eq_attr "type" "fpstore")
99 (eq_attr "cpu" "rios1,ppc601"))
102 (define_function_unit "iu" 1 0
103 (and (eq_attr "type" "fpload")
104 (eq_attr "cpu" "rios1"))
107 (define_function_unit "iu" 1 0
108 (and (eq_attr "type" "fpload")
109 (eq_attr "cpu" "ppc601"))
112 (define_function_unit "iu2" 2 0
113 (and (eq_attr "type" "load,fpload")
114 (eq_attr "cpu" "rios2"))
117 (define_function_unit "iu2" 2 0
118 (and (eq_attr "type" "store,fpstore")
119 (eq_attr "cpu" "rios2"))
122 ; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
123 (define_function_unit "iu" 1 0
124 (and (eq_attr "type" "integer")
125 (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603"))
128 (define_function_unit "iu" 1 0
129 (and (eq_attr "type" "cr_logical")
130 (eq_attr "cpu" "mpccore,ppc403,ppc601"))
133 (define_function_unit "iu" 1 0
134 (and (eq_attr "type" "imul")
135 (eq_attr "cpu" "ppc403"))
138 (define_function_unit "iu" 1 0
139 (and (eq_attr "type" "imul")
140 (eq_attr "cpu" "rios1,ppc601,ppc603"))
143 (define_function_unit "iu" 1 0
144 (and (eq_attr "type" "imul")
145 (eq_attr "cpu" "rs64a"))
148 (define_function_unit "iu" 1 0
149 (and (eq_attr "type" "lmul")
150 (eq_attr "cpu" "rs64a"))
153 (define_function_unit "iu" 1 0
154 (and (eq_attr "type" "idiv")
155 (eq_attr "cpu" "rios1"))
158 (define_function_unit "iu" 1 0
159 (and (eq_attr "type" "idiv")
160 (eq_attr "cpu" "rs64a"))
163 (define_function_unit "iu" 1 0
164 (and (eq_attr "type" "ldiv")
165 (eq_attr "cpu" "rs64a"))
168 (define_function_unit "iu" 1 0
169 (and (eq_attr "type" "idiv")
170 (eq_attr "cpu" "ppc403"))
173 (define_function_unit "iu" 1 0
174 (and (eq_attr "type" "idiv")
175 (eq_attr "cpu" "ppc601"))
178 (define_function_unit "iu" 1 0
179 (and (eq_attr "type" "idiv")
180 (eq_attr "cpu" "ppc603"))
183 ; RIOS2 has two integer units: a primary one which can perform all
184 ; operations and a secondary one which is fed in lock step with the first
185 ; and can perform "simple" integer operations.
186 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
187 ; for the complex insns.
188 (define_function_unit "iu2" 2 0
189 (and (eq_attr "type" "integer")
190 (eq_attr "cpu" "rios2"))
193 (define_function_unit "iu2" 2 0
194 (and (eq_attr "type" "imul")
195 (eq_attr "cpu" "rios2"))
198 (define_function_unit "iu2" 2 0
199 (and (eq_attr "type" "idiv")
200 (eq_attr "cpu" "rios2"))
203 (define_function_unit "imuldiv" 1 0
204 (and (eq_attr "type" "imul")
205 (eq_attr "cpu" "rios2"))
208 (define_function_unit "imuldiv" 1 0
209 (and (eq_attr "type" "idiv")
210 (eq_attr "cpu" "rios2"))
213 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
214 ; Divide latency varies greatly from 2-11, use 6 as average
215 (define_function_unit "imuldiv" 1 0
216 (and (eq_attr "type" "imul")
217 (eq_attr "cpu" "mpccore"))
220 (define_function_unit "imuldiv" 1 0
221 (and (eq_attr "type" "idiv")
222 (eq_attr "cpu" "mpccore"))
225 ; PPC604{,e} has two units that perform integer operations
226 ; and one unit for divide/multiply operations (and move
228 (define_function_unit "iu2" 2 0
229 (and (eq_attr "type" "integer")
230 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
233 (define_function_unit "imuldiv" 1 0
234 (and (eq_attr "type" "imul")
235 (eq_attr "cpu" "ppc604"))
238 (define_function_unit "imuldiv" 1 0
239 (and (eq_attr "type" "imul")
240 (eq_attr "cpu" "ppc620,ppc630"))
243 (define_function_unit "imuldiv" 1 0
244 (and (eq_attr "type" "lmul")
245 (eq_attr "cpu" "ppc620,ppc630"))
248 (define_function_unit "imuldiv" 1 0
249 (and (eq_attr "type" "imul")
250 (eq_attr "cpu" "ppc604e"))
253 (define_function_unit "imuldiv" 1 0
254 (and (eq_attr "type" "idiv")
255 (eq_attr "cpu" "ppc604,ppc604e"))
258 (define_function_unit "imuldiv" 1 0
259 (and (eq_attr "type" "idiv")
260 (eq_attr "cpu" "ppc620"))
263 (define_function_unit "imuldiv" 1 0
264 (and (eq_attr "type" "idiv")
265 (eq_attr "cpu" "ppc630"))
268 (define_function_unit "imuldiv" 1 0
269 (and (eq_attr "type" "ldiv")
270 (eq_attr "cpu" "ppc620,ppc630"))
273 ; PPC750 has two integer units: a primary one which can perform all
274 ; operations and a secondary one which is fed in lock step with the first
275 ; and can perform "simple" integer operations.
276 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
277 ; for the complex insns.
278 (define_function_unit "iu2" 2 0
279 (and (eq_attr "type" "integer")
280 (eq_attr "cpu" "ppc750"))
283 (define_function_unit "iu2" 2 0
284 (and (eq_attr "type" "imul")
285 (eq_attr "cpu" "ppc750"))
288 (define_function_unit "imuldiv" 1 0
289 (and (eq_attr "type" "imul")
290 (eq_attr "cpu" "ppc750"))
293 (define_function_unit "imuldiv" 1 0
294 (and (eq_attr "type" "idiv")
295 (eq_attr "cpu" "ppc750"))
298 ; CR-logical operations are execute-serialized, that is they don't
299 ; start (and block the function unit) until all preceding operations
300 ; have finished. They don't block dispatch of other insns, though.
301 ; I've imitated this by giving them longer latency.
302 (define_function_unit "sru" 1 0
303 (and (eq_attr "type" "cr_logical")
304 (eq_attr "cpu" "ppc603,ppc750"))
307 ; compare is done on integer unit, but feeds insns which
308 ; execute on the branch unit.
309 (define_function_unit "iu" 1 0
310 (and (eq_attr "type" "compare")
311 (eq_attr "cpu" "rios1"))
314 (define_function_unit "iu" 1 0
315 (and (eq_attr "type" "delayed_compare")
316 (eq_attr "cpu" "rios1"))
319 (define_function_unit "iu" 1 0
320 (and (eq_attr "type" "compare,delayed_compare")
321 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
324 (define_function_unit "iu2" 2 0
325 (and (eq_attr "type" "compare,delayed_compare")
326 (eq_attr "cpu" "rios2"))
329 (define_function_unit "iu2" 2 0
330 (and (eq_attr "type" "compare,delayed_compare")
331 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750"))
334 ; fp compare uses fp unit
335 (define_function_unit "fpu" 1 0
336 (and (eq_attr "type" "fpcompare")
337 (eq_attr "cpu" "rios1"))
340 ; rios1 and rios2 have different fpcompare delays
341 (define_function_unit "fpu2" 2 0
342 (and (eq_attr "type" "fpcompare")
343 (eq_attr "cpu" "rios2,ppc630"))
346 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
348 ; here we do not define delays, just occupy the unit. The dependencies
349 ; will be assigned by the fpcompare definition in the fpu.
350 (define_function_unit "iu" 1 0
351 (and (eq_attr "type" "fpcompare")
352 (eq_attr "cpu" "ppc601,ppc603"))
355 ; fp compare uses fp unit
356 (define_function_unit "fpu" 1 0
357 (and (eq_attr "type" "fpcompare")
358 (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
361 (define_function_unit "fpu" 1 0
362 (and (eq_attr "type" "fpcompare")
363 (eq_attr "cpu" "mpccore"))
366 (define_function_unit "bpu" 1 0
367 (and (eq_attr "type" "mtjmpr")
368 (eq_attr "cpu" "rios1,rios2,rs64a"))
371 (define_function_unit "bpu" 1 0
372 (and (eq_attr "type" "mtjmpr")
373 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750"))
376 (define_function_unit "bpu" 1 0
377 (and (eq_attr "type" "cr_logical")
378 (eq_attr "cpu" "rios1,rios2,ppc604"))
381 (define_function_unit "cru" 1 0
382 (and (eq_attr "type" "cr_logical")
383 (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a"))
386 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
387 (define_function_unit "bpu" 1 0
388 (eq_attr "type" "jmpreg")
391 (define_function_unit "bpu" 1 0
392 (eq_attr "type" "branch")
395 ; Floating Point Unit
396 (define_function_unit "fpu" 1 0
397 (and (eq_attr "type" "fp,dmul")
398 (eq_attr "cpu" "rios1"))
401 (define_function_unit "fpu" 1 0
402 (and (eq_attr "type" "fp")
403 (eq_attr "cpu" "rs64a,mpccore"))
406 (define_function_unit "fpu" 1 0
407 (and (eq_attr "type" "fp")
408 (eq_attr "cpu" "ppc601"))
411 (define_function_unit "fpu" 1 0
412 (and (eq_attr "type" "fp")
413 (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620"))
416 (define_function_unit "fpu" 1 0
417 (and (eq_attr "type" "dmul")
418 (eq_attr "cpu" "rs64a"))
421 (define_function_unit "fpu" 1 0
422 (and (eq_attr "type" "dmul")
423 (eq_attr "cpu" "mpccore"))
426 (define_function_unit "fpu" 1 0
427 (and (eq_attr "type" "dmul")
428 (eq_attr "cpu" "ppc601"))
432 (define_function_unit "fpu" 1 0
433 (and (eq_attr "type" "dmul")
434 (eq_attr "cpu" "ppc603,ppc750"))
437 (define_function_unit "fpu" 1 0
438 (and (eq_attr "type" "dmul")
439 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
442 (define_function_unit "fpu" 1 0
443 (and (eq_attr "type" "sdiv,ddiv")
444 (eq_attr "cpu" "rios1"))
447 (define_function_unit "fpu" 1 0
448 (and (eq_attr "type" "sdiv")
449 (eq_attr "cpu" "rs64a"))
452 (define_function_unit "fpu" 1 0
453 (and (eq_attr "type" "sdiv")
454 (eq_attr "cpu" "ppc601"))
457 (define_function_unit "fpu" 1 0
458 (and (eq_attr "type" "sdiv")
459 (eq_attr "cpu" "mpccore"))
462 (define_function_unit "fpu" 1 0
463 (and (eq_attr "type" "sdiv")
464 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
467 (define_function_unit "fpu" 1 0
468 (and (eq_attr "type" "ddiv")
469 (eq_attr "cpu" "mpccore"))
472 (define_function_unit "fpu" 1 0
473 (and (eq_attr "type" "ddiv")
474 (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620"))
477 (define_function_unit "fpu" 1 0
478 (and (eq_attr "type" "ddiv")
479 (eq_attr "cpu" "ppc603"))
482 (define_function_unit "fpu" 1 0
483 (and (eq_attr "type" "ssqrt")
484 (eq_attr "cpu" "ppc620"))
487 (define_function_unit "fpu" 1 0
488 (and (eq_attr "type" "dsqrt")
489 (eq_attr "cpu" "ppc620"))
492 ; RIOS2 has two symmetric FPUs.
493 (define_function_unit "fpu2" 2 0
494 (and (eq_attr "type" "fp")
495 (eq_attr "cpu" "rios2"))
498 (define_function_unit "fpu2" 2 0
499 (and (eq_attr "type" "fp")
500 (eq_attr "cpu" "ppc630"))
503 (define_function_unit "fpu2" 2 0
504 (and (eq_attr "type" "dmul")
505 (eq_attr "cpu" "rios2"))
508 (define_function_unit "fpu2" 2 0
509 (and (eq_attr "type" "dmul")
510 (eq_attr "cpu" "ppc630"))
513 (define_function_unit "fpu2" 2 0
514 (and (eq_attr "type" "sdiv,ddiv")
515 (eq_attr "cpu" "rios2"))
518 (define_function_unit "fpu2" 2 0
519 (and (eq_attr "type" "sdiv")
520 (eq_attr "cpu" "ppc630"))
523 (define_function_unit "fpu2" 2 0
524 (and (eq_attr "type" "ddiv")
525 (eq_attr "cpu" "ppc630"))
528 (define_function_unit "fpu2" 2 0
529 (and (eq_attr "type" "ssqrt,dsqrt")
530 (eq_attr "cpu" "rios2"))
533 (define_function_unit "fpu2" 2 0
534 (and (eq_attr "type" "ssqrt")
535 (eq_attr "cpu" "ppc630"))
538 (define_function_unit "fpu2" 2 0
539 (and (eq_attr "type" "dsqrt")
540 (eq_attr "cpu" "ppc630"))
544 ;; Start with fixed-point load and store insns. Here we put only the more
545 ;; complex forms. Basic data transfer is done later.
547 (define_expand "zero_extendqidi2"
548 [(set (match_operand:DI 0 "gpc_reg_operand" "")
549 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
555 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
560 [(set_attr "type" "load,*")])
563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
564 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
566 (clobber (match_scratch:DI 2 "=r,r"))]
571 [(set_attr "type" "compare")
572 (set_attr "length" "4,8")])
575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
576 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
578 (clobber (match_scratch:DI 2 ""))]
579 "TARGET_POWERPC64 && reload_completed"
581 (zero_extend:DI (match_dup 1)))
583 (compare:CC (match_dup 2)
588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
589 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
591 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
592 (zero_extend:DI (match_dup 1)))]
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
602 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
604 (set (match_operand:DI 0 "gpc_reg_operand" "")
605 (zero_extend:DI (match_dup 1)))]
606 "TARGET_POWERPC64 && reload_completed"
608 (zero_extend:DI (match_dup 1)))
610 (compare:CC (match_dup 0)
614 (define_insn "extendqidi2"
615 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
616 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
621 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
622 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
624 (clobber (match_scratch:DI 2 "=r,r"))]
629 [(set_attr "type" "compare")
630 (set_attr "length" "4,8")])
633 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
634 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
636 (clobber (match_scratch:DI 2 ""))]
637 "TARGET_POWERPC64 && reload_completed"
639 (sign_extend:DI (match_dup 1)))
641 (compare:CC (match_dup 2)
646 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
647 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
649 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
650 (sign_extend:DI (match_dup 1)))]
655 [(set_attr "type" "compare")
656 (set_attr "length" "4,8")])
659 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
660 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
662 (set (match_operand:DI 0 "gpc_reg_operand" "")
663 (sign_extend:DI (match_dup 1)))]
664 "TARGET_POWERPC64 && reload_completed"
666 (sign_extend:DI (match_dup 1)))
668 (compare:CC (match_dup 0)
672 (define_expand "zero_extendhidi2"
673 [(set (match_operand:DI 0 "gpc_reg_operand" "")
674 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
679 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
680 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
685 [(set_attr "type" "load,*")])
688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
689 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
691 (clobber (match_scratch:DI 2 "=r,r"))]
696 [(set_attr "type" "compare")
697 (set_attr "length" "4,8")])
700 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
701 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
703 (clobber (match_scratch:DI 2 ""))]
704 "TARGET_POWERPC64 && reload_completed"
706 (zero_extend:DI (match_dup 1)))
708 (compare:CC (match_dup 2)
713 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
714 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
716 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
717 (zero_extend:DI (match_dup 1)))]
722 [(set_attr "type" "compare")
723 (set_attr "length" "4,8")])
726 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
727 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
729 (set (match_operand:DI 0 "gpc_reg_operand" "")
730 (zero_extend:DI (match_dup 1)))]
731 "TARGET_POWERPC64 && reload_completed"
733 (zero_extend:DI (match_dup 1)))
735 (compare:CC (match_dup 0)
739 (define_expand "extendhidi2"
740 [(set (match_operand:DI 0 "gpc_reg_operand" "")
741 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
746 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
747 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
752 [(set_attr "type" "load,*")])
755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
756 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
758 (clobber (match_scratch:DI 2 "=r,r"))]
763 [(set_attr "type" "compare")
764 (set_attr "length" "4,8")])
767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
768 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
770 (clobber (match_scratch:DI 2 ""))]
771 "TARGET_POWERPC64 && reload_completed"
773 (sign_extend:DI (match_dup 1)))
775 (compare:CC (match_dup 2)
780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
781 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
783 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
784 (sign_extend:DI (match_dup 1)))]
789 [(set_attr "type" "compare")
790 (set_attr "length" "4,8")])
793 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
794 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
796 (set (match_operand:DI 0 "gpc_reg_operand" "")
797 (sign_extend:DI (match_dup 1)))]
798 "TARGET_POWERPC64 && reload_completed"
800 (sign_extend:DI (match_dup 1)))
802 (compare:CC (match_dup 0)
806 (define_expand "zero_extendsidi2"
807 [(set (match_operand:DI 0 "gpc_reg_operand" "")
808 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
813 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
814 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
819 [(set_attr "type" "load,*")])
822 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
823 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
825 (clobber (match_scratch:DI 2 "=r,r"))]
830 [(set_attr "type" "compare")
831 (set_attr "length" "4,8")])
834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
835 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
837 (clobber (match_scratch:DI 2 ""))]
838 "TARGET_POWERPC64 && reload_completed"
840 (zero_extend:DI (match_dup 1)))
842 (compare:CC (match_dup 2)
847 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
848 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
850 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
851 (zero_extend:DI (match_dup 1)))]
856 [(set_attr "type" "compare")
857 (set_attr "length" "4,8")])
860 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
861 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
863 (set (match_operand:DI 0 "gpc_reg_operand" "")
864 (zero_extend:DI (match_dup 1)))]
865 "TARGET_POWERPC64 && reload_completed"
867 (zero_extend:DI (match_dup 1)))
869 (compare:CC (match_dup 0)
873 (define_expand "extendsidi2"
874 [(set (match_operand:DI 0 "gpc_reg_operand" "")
875 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
880 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
881 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
886 [(set_attr "type" "load,*")])
889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
890 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
892 (clobber (match_scratch:DI 2 "=r,r"))]
897 [(set_attr "type" "compare")
898 (set_attr "length" "4,8")])
901 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
902 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
904 (clobber (match_scratch:DI 2 ""))]
905 "TARGET_POWERPC64 && reload_completed"
907 (sign_extend:DI (match_dup 1)))
909 (compare:CC (match_dup 2)
914 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
915 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
917 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
918 (sign_extend:DI (match_dup 1)))]
923 [(set_attr "type" "compare")
924 (set_attr "length" "4,8")])
927 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
928 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
930 (set (match_operand:DI 0 "gpc_reg_operand" "")
931 (sign_extend:DI (match_dup 1)))]
932 "TARGET_POWERPC64 && reload_completed"
934 (sign_extend:DI (match_dup 1)))
936 (compare:CC (match_dup 0)
940 (define_expand "zero_extendqisi2"
941 [(set (match_operand:SI 0 "gpc_reg_operand" "")
942 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
948 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
952 {rlinm|rlwinm} %0,%1,0,0xff"
953 [(set_attr "type" "load,*")])
956 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
957 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
959 (clobber (match_scratch:SI 2 "=r,r"))]
962 {andil.|andi.} %2,%1,0xff
964 [(set_attr "type" "compare")
965 (set_attr "length" "4,8")])
968 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
969 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
971 (clobber (match_scratch:SI 2 ""))]
974 (zero_extend:SI (match_dup 1)))
976 (compare:CC (match_dup 2)
981 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
982 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
985 (zero_extend:SI (match_dup 1)))]
988 {andil.|andi.} %0,%1,0xff
990 [(set_attr "type" "compare")
991 (set_attr "length" "4,8")])
994 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
995 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
997 (set (match_operand:SI 0 "gpc_reg_operand" "")
998 (zero_extend:SI (match_dup 1)))]
1001 (zero_extend:SI (match_dup 1)))
1003 (compare:CC (match_dup 0)
1007 (define_expand "extendqisi2"
1008 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1009 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1014 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
1015 else if (TARGET_POWER)
1016 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
1018 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
1022 (define_insn "extendqisi2_ppc"
1023 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1024 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1030 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1032 (clobber (match_scratch:SI 2 "=r,r"))]
1037 [(set_attr "type" "compare")
1038 (set_attr "length" "4,8")])
1041 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1042 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1044 (clobber (match_scratch:SI 2 ""))]
1045 "TARGET_POWERPC && reload_completed"
1047 (sign_extend:SI (match_dup 1)))
1049 (compare:CC (match_dup 2)
1054 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1055 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1057 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1058 (sign_extend:SI (match_dup 1)))]
1063 [(set_attr "type" "compare")
1064 (set_attr "length" "4,8")])
1067 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1068 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "")
1071 (sign_extend:SI (match_dup 1)))]
1072 "TARGET_POWERPC && reload_completed"
1074 (sign_extend:SI (match_dup 1)))
1076 (compare:CC (match_dup 0)
1080 (define_expand "extendqisi2_power"
1081 [(parallel [(set (match_dup 2)
1082 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1084 (clobber (scratch:SI))])
1085 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1086 (ashiftrt:SI (match_dup 2)
1088 (clobber (scratch:SI))])]
1091 { operands[1] = gen_lowpart (SImode, operands[1]);
1092 operands[2] = gen_reg_rtx (SImode); }")
1094 (define_expand "extendqisi2_no_power"
1096 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1098 (set (match_operand:SI 0 "gpc_reg_operand" "")
1099 (ashiftrt:SI (match_dup 2)
1101 "! TARGET_POWER && ! TARGET_POWERPC"
1103 { operands[1] = gen_lowpart (SImode, operands[1]);
1104 operands[2] = gen_reg_rtx (SImode); }")
1106 (define_expand "zero_extendqihi2"
1107 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1108 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1113 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1114 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1118 {rlinm|rlwinm} %0,%1,0,0xff"
1119 [(set_attr "type" "load,*")])
1122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1123 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1125 (clobber (match_scratch:HI 2 "=r,r"))]
1128 {andil.|andi.} %2,%1,0xff
1130 [(set_attr "type" "compare")
1131 (set_attr "length" "4,8")])
1134 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1135 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1137 (clobber (match_scratch:HI 2 ""))]
1140 (zero_extend:HI (match_dup 1)))
1142 (compare:CC (match_dup 2)
1147 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1148 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1150 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1151 (zero_extend:HI (match_dup 1)))]
1154 {andil.|andi.} %0,%1,0xff
1156 [(set_attr "type" "compare")
1157 (set_attr "length" "4,8")])
1160 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1161 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1163 (set (match_operand:HI 0 "gpc_reg_operand" "")
1164 (zero_extend:HI (match_dup 1)))]
1167 (zero_extend:HI (match_dup 1)))
1169 (compare:CC (match_dup 0)
1173 (define_expand "extendqihi2"
1174 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
1175 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1180 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
1181 else if (TARGET_POWER)
1182 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
1184 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
1188 (define_insn "extendqihi2_ppc"
1189 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1190 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1196 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1198 (clobber (match_scratch:HI 2 "=r,r"))]
1203 [(set_attr "type" "compare")
1204 (set_attr "length" "4,8")])
1207 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1208 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1210 (clobber (match_scratch:HI 2 ""))]
1211 "TARGET_POWERPC && reload_completed"
1213 (sign_extend:HI (match_dup 1)))
1215 (compare:CC (match_dup 2)
1220 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1221 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1223 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1224 (sign_extend:HI (match_dup 1)))]
1229 [(set_attr "type" "compare")
1230 (set_attr "length" "4,8")])
1233 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1234 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1236 (set (match_operand:HI 0 "gpc_reg_operand" "")
1237 (sign_extend:HI (match_dup 1)))]
1238 "TARGET_POWERPC && reload_completed"
1240 (sign_extend:HI (match_dup 1)))
1242 (compare:CC (match_dup 0)
1246 (define_expand "extendqihi2_power"
1247 [(parallel [(set (match_dup 2)
1248 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1250 (clobber (scratch:SI))])
1251 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1252 (ashiftrt:SI (match_dup 2)
1254 (clobber (scratch:SI))])]
1257 { operands[0] = gen_lowpart (SImode, operands[0]);
1258 operands[1] = gen_lowpart (SImode, operands[1]);
1259 operands[2] = gen_reg_rtx (SImode); }")
1261 (define_expand "extendqihi2_no_power"
1263 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1265 (set (match_operand:HI 0 "gpc_reg_operand" "")
1266 (ashiftrt:SI (match_dup 2)
1268 "! TARGET_POWER && ! TARGET_POWERPC"
1270 { operands[0] = gen_lowpart (SImode, operands[0]);
1271 operands[1] = gen_lowpart (SImode, operands[1]);
1272 operands[2] = gen_reg_rtx (SImode); }")
1274 (define_expand "zero_extendhisi2"
1275 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1276 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1282 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1286 {rlinm|rlwinm} %0,%1,0,0xffff"
1287 [(set_attr "type" "load,*")])
1290 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1291 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1293 (clobber (match_scratch:SI 2 "=r,r"))]
1296 {andil.|andi.} %2,%1,0xffff
1298 [(set_attr "type" "compare")
1299 (set_attr "length" "4,8")])
1302 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1303 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1305 (clobber (match_scratch:SI 2 ""))]
1308 (zero_extend:SI (match_dup 1)))
1310 (compare:CC (match_dup 2)
1315 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1316 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1319 (zero_extend:SI (match_dup 1)))]
1322 {andil.|andi.} %0,%1,0xffff
1324 [(set_attr "type" "compare")
1325 (set_attr "length" "4,8")])
1328 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1329 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1331 (set (match_operand:SI 0 "gpc_reg_operand" "")
1332 (zero_extend:SI (match_dup 1)))]
1335 (zero_extend:SI (match_dup 1)))
1337 (compare:CC (match_dup 0)
1341 (define_expand "extendhisi2"
1342 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1343 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1348 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1349 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1354 [(set_attr "type" "load,*")])
1357 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1358 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1360 (clobber (match_scratch:SI 2 "=r,r"))]
1363 {exts.|extsh.} %2,%1
1365 [(set_attr "type" "compare")
1366 (set_attr "length" "4,8")])
1369 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1370 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1372 (clobber (match_scratch:SI 2 ""))]
1375 (sign_extend:SI (match_dup 1)))
1377 (compare:CC (match_dup 2)
1382 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1383 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1385 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1386 (sign_extend:SI (match_dup 1)))]
1389 {exts.|extsh.} %0,%1
1391 [(set_attr "type" "compare")
1392 (set_attr "length" "4,8")])
1395 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1396 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1398 (set (match_operand:SI 0 "gpc_reg_operand" "")
1399 (sign_extend:SI (match_dup 1)))]
1402 (sign_extend:SI (match_dup 1)))
1404 (compare:CC (match_dup 0)
1408 ;; Fixed-point arithmetic insns.
1410 ;; Discourage ai/addic because of carry but provide it in an alternative
1411 ;; allowing register zero as source.
1412 (define_expand "addsi3"
1413 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1414 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1415 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1419 if (GET_CODE (operands[2]) == CONST_INT
1420 && ! add_operand (operands[2], SImode))
1422 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1423 ? operands[0] : gen_reg_rtx (SImode));
1425 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
1426 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
1429 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
1431 /* The ordering here is important for the prolog expander.
1432 When space is allocated from the stack, adding 'low' first may
1433 produce a temporary deallocation (which would be bad). */
1434 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high)));
1435 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1440 (define_insn "*addsi3_internal1"
1441 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1442 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1443 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1447 {cal %0,%2(%1)|addi %0,%1,%2}
1449 {cau|addis} %0,%1,%v2"
1450 [(set_attr "length" "4,4,4,4")])
1452 (define_insn "*addsi3_internal2"
1453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1454 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1455 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1457 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1458 "! TARGET_POWERPC64"
1460 {cax.|add.} %3,%1,%2
1461 {ai.|addic.} %3,%1,%2
1464 [(set_attr "type" "compare")
1465 (set_attr "length" "4,4,8,8")])
1468 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1469 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1470 (match_operand:SI 2 "reg_or_short_operand" ""))
1472 (clobber (match_scratch:SI 3 ""))]
1473 "! TARGET_POWERPC64 && reload_completed"
1475 (plus:SI (match_dup 1)
1478 (compare:CC (match_dup 3)
1482 (define_insn "*addsi3_internal3"
1483 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1484 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1485 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1487 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1488 (plus:SI (match_dup 1)
1490 "! TARGET_POWERPC64"
1492 {cax.|add.} %0,%1,%2
1493 {ai.|addic.} %0,%1,%2
1496 [(set_attr "type" "compare")
1497 (set_attr "length" "4,4,8,8")])
1500 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1501 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1502 (match_operand:SI 2 "reg_or_short_operand" ""))
1504 (set (match_operand:SI 0 "gpc_reg_operand" "")
1505 (plus:SI (match_dup 1) (match_dup 2)))]
1506 "! TARGET_POWERPC64 && reload_completed"
1508 (plus:SI (match_dup 1)
1511 (compare:CC (match_dup 0)
1515 ;; Split an add that we can't do in one insn into two insns, each of which
1516 ;; does one 16-bit part. This is used by combine. Note that the low-order
1517 ;; add should be last in case the result gets used in an address.
1520 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1521 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1522 (match_operand:SI 2 "non_add_cint_operand" "")))]
1524 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1525 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1528 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
1529 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
1532 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
1534 operands[3] = GEN_INT (high);
1535 operands[4] = GEN_INT (low);
1538 (define_insn "one_cmplsi2"
1539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1540 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1546 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1548 (clobber (match_scratch:SI 2 "=r,r"))]
1549 "! TARGET_POWERPC64"
1553 [(set_attr "type" "compare")
1554 (set_attr "length" "4,8")])
1557 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1558 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1560 (clobber (match_scratch:SI 2 ""))]
1561 "! TARGET_POWERPC64 && reload_completed"
1563 (not:SI (match_dup 1)))
1565 (compare:CC (match_dup 2)
1570 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1571 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1573 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1574 (not:SI (match_dup 1)))]
1575 "! TARGET_POWERPC64"
1579 [(set_attr "type" "compare")
1580 (set_attr "length" "4,8")])
1583 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1584 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1586 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1587 (not:SI (match_dup 1)))]
1588 "! TARGET_POWERPC64 && reload_completed"
1590 (not:SI (match_dup 1)))
1592 (compare:CC (match_dup 0)
1597 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1598 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1599 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1601 "{sf%I1|subf%I1c} %0,%2,%1")
1604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1605 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1606 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1613 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1614 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1615 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1617 (clobber (match_scratch:SI 3 "=r,r"))]
1620 {sf.|subfc.} %3,%2,%1
1622 [(set_attr "type" "compare")
1623 (set_attr "length" "4,8")])
1626 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1627 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1628 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1630 (clobber (match_scratch:SI 3 "=r,r"))]
1631 "TARGET_POWERPC && ! TARGET_POWERPC64"
1635 [(set_attr "type" "compare")
1636 (set_attr "length" "4,8")])
1639 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1640 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1641 (match_operand:SI 2 "gpc_reg_operand" ""))
1643 (clobber (match_scratch:SI 3 ""))]
1644 "! TARGET_POWERPC64 && reload_completed"
1646 (minus:SI (match_dup 1)
1649 (compare:CC (match_dup 3)
1654 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1655 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1656 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1658 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1659 (minus:SI (match_dup 1) (match_dup 2)))]
1662 {sf.|subfc.} %0,%2,%1
1664 [(set_attr "type" "compare")
1665 (set_attr "length" "4,8")])
1668 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1669 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1670 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1672 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1673 (minus:SI (match_dup 1)
1675 "TARGET_POWERPC && ! TARGET_POWERPC64"
1679 [(set_attr "type" "compare")
1680 (set_attr "length" "4,8")])
1683 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1684 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1685 (match_operand:SI 2 "gpc_reg_operand" ""))
1687 (set (match_operand:SI 0 "gpc_reg_operand" "")
1688 (minus:SI (match_dup 1)
1690 "! TARGET_POWERPC64 && reload_completed"
1692 (minus:SI (match_dup 1)
1695 (compare:CC (match_dup 0)
1699 (define_expand "subsi3"
1700 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1701 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1702 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1706 if (GET_CODE (operands[2]) == CONST_INT)
1708 emit_insn (gen_addsi3 (operands[0], operands[1],
1709 negate_rtx (SImode, operands[2])));
1714 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1715 ;; instruction and some auxiliary computations. Then we just have a single
1716 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1719 (define_expand "sminsi3"
1721 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1722 (match_operand:SI 2 "reg_or_short_operand" ""))
1724 (minus:SI (match_dup 2) (match_dup 1))))
1725 (set (match_operand:SI 0 "gpc_reg_operand" "")
1726 (minus:SI (match_dup 2) (match_dup 3)))]
1729 { operands[3] = gen_reg_rtx (SImode); }")
1732 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1733 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1734 (match_operand:SI 2 "reg_or_short_operand" "")))
1735 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1738 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1740 (minus:SI (match_dup 2) (match_dup 1))))
1741 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1744 (define_expand "smaxsi3"
1746 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1747 (match_operand:SI 2 "reg_or_short_operand" ""))
1749 (minus:SI (match_dup 2) (match_dup 1))))
1750 (set (match_operand:SI 0 "gpc_reg_operand" "")
1751 (plus:SI (match_dup 3) (match_dup 1)))]
1754 { operands[3] = gen_reg_rtx (SImode); }")
1757 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1758 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1759 (match_operand:SI 2 "reg_or_short_operand" "")))
1760 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1763 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1765 (minus:SI (match_dup 2) (match_dup 1))))
1766 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1769 (define_expand "uminsi3"
1770 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1772 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1774 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1776 (minus:SI (match_dup 4) (match_dup 3))))
1777 (set (match_operand:SI 0 "gpc_reg_operand" "")
1778 (minus:SI (match_dup 2) (match_dup 3)))]
1782 operands[3] = gen_reg_rtx (SImode);
1783 operands[4] = gen_reg_rtx (SImode);
1784 operands[5] = GEN_INT (-2147483647 - 1);
1787 (define_expand "umaxsi3"
1788 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1790 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1792 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1794 (minus:SI (match_dup 4) (match_dup 3))))
1795 (set (match_operand:SI 0 "gpc_reg_operand" "")
1796 (plus:SI (match_dup 3) (match_dup 1)))]
1800 operands[3] = gen_reg_rtx (SImode);
1801 operands[4] = gen_reg_rtx (SImode);
1802 operands[5] = GEN_INT (-2147483647 - 1);
1806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1807 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1808 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1810 (minus:SI (match_dup 2) (match_dup 1))))]
1815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1817 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1818 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1820 (minus:SI (match_dup 2) (match_dup 1)))
1822 (clobber (match_scratch:SI 3 "=r,r"))]
1827 [(set_attr "type" "delayed_compare")
1828 (set_attr "length" "4,8")])
1831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1833 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1834 (match_operand:SI 2 "reg_or_short_operand" ""))
1836 (minus:SI (match_dup 2) (match_dup 1)))
1838 (clobber (match_scratch:SI 3 ""))]
1839 "TARGET_POWER && reload_completed"
1841 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1843 (minus:SI (match_dup 2) (match_dup 1))))
1845 (compare:CC (match_dup 3)
1850 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1852 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1853 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1855 (minus:SI (match_dup 2) (match_dup 1)))
1857 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1858 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1860 (minus:SI (match_dup 2) (match_dup 1))))]
1865 [(set_attr "type" "delayed_compare")
1866 (set_attr "length" "4,8")])
1869 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1871 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1872 (match_operand:SI 2 "reg_or_short_operand" ""))
1874 (minus:SI (match_dup 2) (match_dup 1)))
1876 (set (match_operand:SI 0 "gpc_reg_operand" "")
1877 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1879 (minus:SI (match_dup 2) (match_dup 1))))]
1880 "TARGET_POWER && reload_completed"
1882 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1884 (minus:SI (match_dup 2) (match_dup 1))))
1886 (compare:CC (match_dup 0)
1890 ;; We don't need abs with condition code because such comparisons should
1892 (define_expand "abssi2"
1893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1894 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1900 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1905 (define_insn "abssi2_power"
1906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1907 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1911 (define_insn "abssi2_nopower"
1912 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1913 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1914 (clobber (match_scratch:SI 2 "=&r,&r"))]
1918 return (TARGET_POWERPC)
1919 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1920 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1922 [(set_attr "length" "12")])
1925 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1926 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1927 (clobber (match_scratch:SI 2 "=&r,&r"))]
1928 "! TARGET_POWER && reload_completed"
1929 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1930 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1931 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1934 (define_insn "*nabs_power"
1935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1936 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1940 (define_insn "*nabs_no_power"
1941 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1942 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1943 (clobber (match_scratch:SI 2 "=&r,&r"))]
1947 return (TARGET_POWERPC)
1948 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1949 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1951 [(set_attr "length" "12")])
1954 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1955 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1956 (clobber (match_scratch:SI 2 "=&r,&r"))]
1957 "! TARGET_POWER && reload_completed"
1958 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1959 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1960 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1963 (define_insn "negsi2"
1964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1965 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1970 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1971 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1973 (clobber (match_scratch:SI 2 "=r,r"))]
1974 "! TARGET_POWERPC64"
1978 [(set_attr "type" "compare")
1979 (set_attr "length" "4,8")])
1982 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1983 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1985 (clobber (match_scratch:SI 2 ""))]
1986 "! TARGET_POWERPC64 && reload_completed"
1988 (neg:SI (match_dup 1)))
1990 (compare:CC (match_dup 2)
1995 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1996 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1998 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1999 (neg:SI (match_dup 1)))]
2000 "! TARGET_POWERPC64"
2004 [(set_attr "type" "compare")
2005 (set_attr "length" "4,8")])
2008 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2009 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2011 (set (match_operand:SI 0 "gpc_reg_operand" "")
2012 (neg:SI (match_dup 1)))]
2013 "! TARGET_POWERPC64 && reload_completed"
2015 (neg:SI (match_dup 1)))
2017 (compare:CC (match_dup 0)
2021 (define_insn "ffssi2"
2022 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
2023 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2025 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
2026 [(set_attr "length" "16")])
2028 (define_expand "mulsi3"
2029 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2030 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2031 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2036 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2038 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2042 (define_insn "mulsi3_mq"
2043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2044 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2045 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2046 (clobber (match_scratch:SI 3 "=q,q"))]
2049 {muls|mullw} %0,%1,%2
2050 {muli|mulli} %0,%1,%2"
2051 [(set_attr "type" "imul")])
2053 (define_insn "mulsi3_no_mq"
2054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2055 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2056 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2059 {muls|mullw} %0,%1,%2
2060 {muli|mulli} %0,%1,%2"
2061 [(set_attr "type" "imul")])
2064 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2065 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2066 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2068 (clobber (match_scratch:SI 3 "=r,r"))
2069 (clobber (match_scratch:SI 4 "=q,q"))]
2072 {muls.|mullw.} %3,%1,%2
2074 [(set_attr "type" "delayed_compare")
2075 (set_attr "length" "4,8")])
2078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2079 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2080 (match_operand:SI 2 "gpc_reg_operand" ""))
2082 (clobber (match_scratch:SI 3 ""))
2083 (clobber (match_scratch:SI 4 ""))]
2084 "TARGET_POWER && reload_completed"
2085 [(parallel [(set (match_dup 3)
2086 (mult:SI (match_dup 1) (match_dup 2)))
2087 (clobber (match_dup 4))])
2089 (compare:CC (match_dup 3)
2094 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2095 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2096 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2098 (clobber (match_scratch:SI 3 "=r,r"))]
2101 {muls.|mullw.} %3,%1,%2
2103 [(set_attr "type" "delayed_compare")
2104 (set_attr "length" "4,8")])
2107 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2108 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2109 (match_operand:SI 2 "gpc_reg_operand" ""))
2111 (clobber (match_scratch:SI 3 ""))]
2112 "! TARGET_POWER && reload_completed"
2114 (mult:SI (match_dup 1) (match_dup 2)))
2116 (compare:CC (match_dup 3)
2121 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2122 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2123 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2125 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2126 (mult:SI (match_dup 1) (match_dup 2)))
2127 (clobber (match_scratch:SI 4 "=q,q"))]
2130 {muls.|mullw.} %0,%1,%2
2132 [(set_attr "type" "delayed_compare")
2133 (set_attr "length" "4,8")])
2136 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2137 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2138 (match_operand:SI 2 "gpc_reg_operand" ""))
2140 (set (match_operand:SI 0 "gpc_reg_operand" "")
2141 (mult:SI (match_dup 1) (match_dup 2)))
2142 (clobber (match_scratch:SI 4 ""))]
2143 "TARGET_POWER && reload_completed"
2144 [(parallel [(set (match_dup 0)
2145 (mult:SI (match_dup 1) (match_dup 2)))
2146 (clobber (match_dup 4))])
2148 (compare:CC (match_dup 0)
2153 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2154 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2155 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2157 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2158 (mult:SI (match_dup 1) (match_dup 2)))]
2161 {muls.|mullw.} %0,%1,%2
2163 [(set_attr "type" "delayed_compare")
2164 (set_attr "length" "4,8")])
2167 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2168 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2169 (match_operand:SI 2 "gpc_reg_operand" ""))
2171 (set (match_operand:SI 0 "gpc_reg_operand" "")
2172 (mult:SI (match_dup 1) (match_dup 2)))]
2173 "! TARGET_POWER && reload_completed"
2175 (mult:SI (match_dup 1) (match_dup 2)))
2177 (compare:CC (match_dup 0)
2181 ;; Operand 1 is divided by operand 2; quotient goes to operand
2182 ;; 0 and remainder to operand 3.
2183 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2185 (define_expand "divmodsi4"
2186 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2187 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2188 (match_operand:SI 2 "gpc_reg_operand" "")))
2189 (set (match_operand:SI 3 "gpc_reg_operand" "")
2190 (mod:SI (match_dup 1) (match_dup 2)))])]
2191 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2194 if (! TARGET_POWER && ! TARGET_POWERPC)
2196 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2197 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2198 emit_insn (gen_divss_call ());
2199 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2200 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2206 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2207 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2208 (match_operand:SI 2 "gpc_reg_operand" "r")))
2209 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
2210 (mod:SI (match_dup 1) (match_dup 2)))]
2213 [(set_attr "type" "idiv")])
2215 (define_expand "udivsi3"
2216 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2217 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2218 (match_operand:SI 2 "gpc_reg_operand" "")))]
2219 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2222 if (! TARGET_POWER && ! TARGET_POWERPC)
2224 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2225 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2226 emit_insn (gen_quous_call ());
2227 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2230 else if (TARGET_POWER)
2232 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2237 (define_insn "udivsi3_mq"
2238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2239 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2240 (match_operand:SI 2 "gpc_reg_operand" "r")))
2241 (clobber (match_scratch:SI 3 "=q"))]
2242 "TARGET_POWERPC && TARGET_POWER"
2244 [(set_attr "type" "idiv")])
2246 (define_insn "*udivsi3_no_mq"
2247 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2248 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2249 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2250 "TARGET_POWERPC && ! TARGET_POWER"
2252 [(set_attr "type" "idiv")])
2254 ;; For powers of two we can do srai/aze for divide and then adjust for
2255 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2256 ;; used; for PowerPC, force operands into register and do a normal divide;
2257 ;; for AIX common-mode, use quoss call on register operands.
2258 (define_expand "divsi3"
2259 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2260 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2261 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2265 if (GET_CODE (operands[2]) == CONST_INT
2266 && exact_log2 (INTVAL (operands[2])) >= 0)
2268 else if (TARGET_POWERPC)
2270 operands[2] = force_reg (SImode, operands[2]);
2273 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2277 else if (TARGET_POWER)
2281 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2282 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2283 emit_insn (gen_quoss_call ());
2284 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2289 (define_insn "divsi3_mq"
2290 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2291 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2292 (match_operand:SI 2 "gpc_reg_operand" "r")))
2293 (clobber (match_scratch:SI 3 "=q"))]
2294 "TARGET_POWERPC && TARGET_POWER"
2296 [(set_attr "type" "idiv")])
2298 (define_insn "*divsi3_no_mq"
2299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2300 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2301 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2302 "TARGET_POWERPC && ! TARGET_POWER"
2304 [(set_attr "type" "idiv")])
2306 (define_expand "modsi3"
2307 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2308 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2309 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2317 if (GET_CODE (operands[2]) != CONST_INT)
2320 i = exact_log2 (INTVAL (operands[2]));
2325 temp1 = gen_reg_rtx (SImode);
2326 temp2 = gen_reg_rtx (SImode);
2328 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2329 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2330 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2335 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2336 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2337 (match_operand:SI 2 "const_int_operand" "N")))]
2338 "exact_log2 (INTVAL (operands[2])) >= 0"
2339 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2340 [(set_attr "length" "8")])
2343 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2344 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2345 (match_operand:SI 2 "const_int_operand" "N,N"))
2347 (clobber (match_scratch:SI 3 "=r,r"))]
2348 "exact_log2 (INTVAL (operands[2])) >= 0"
2350 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2352 [(set_attr "type" "compare")
2353 (set_attr "length" "8,12")])
2356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2357 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2358 (match_operand:SI 2 "const_int_operand" ""))
2360 (clobber (match_scratch:SI 3 ""))]
2361 "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
2363 (div:SI (match_dup 1) (match_dup 2)))
2365 (compare:CC (match_dup 3)
2370 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2371 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2372 (match_operand:SI 2 "const_int_operand" "N,N"))
2374 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2375 (div:SI (match_dup 1) (match_dup 2)))]
2376 "exact_log2 (INTVAL (operands[2])) >= 0"
2378 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2380 [(set_attr "type" "compare")
2381 (set_attr "length" "8,12")])
2384 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2385 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2386 (match_operand:SI 2 "const_int_operand" ""))
2388 (set (match_operand:SI 0 "gpc_reg_operand" "")
2389 (div:SI (match_dup 1) (match_dup 2)))]
2390 "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
2392 (div:SI (match_dup 1) (match_dup 2)))
2394 (compare:CC (match_dup 0)
2399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2402 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2404 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2405 (match_operand:SI 3 "gpc_reg_operand" "r")))
2406 (set (match_operand:SI 2 "register_operand" "=*q")
2409 (zero_extend:DI (match_dup 1)) (const_int 32))
2410 (zero_extend:DI (match_dup 4)))
2414 [(set_attr "type" "idiv")])
2416 ;; To do unsigned divide we handle the cases of the divisor looking like a
2417 ;; negative number. If it is a constant that is less than 2**31, we don't
2418 ;; have to worry about the branches. So make a few subroutines here.
2420 ;; First comes the normal case.
2421 (define_expand "udivmodsi4_normal"
2422 [(set (match_dup 4) (const_int 0))
2423 (parallel [(set (match_operand:SI 0 "" "")
2424 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2426 (zero_extend:DI (match_operand:SI 1 "" "")))
2427 (match_operand:SI 2 "" "")))
2428 (set (match_operand:SI 3 "" "")
2429 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2431 (zero_extend:DI (match_dup 1)))
2435 { operands[4] = gen_reg_rtx (SImode); }")
2437 ;; This handles the branches.
2438 (define_expand "udivmodsi4_tests"
2439 [(set (match_operand:SI 0 "" "") (const_int 0))
2440 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2441 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2442 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2443 (label_ref (match_operand:SI 4 "" "")) (pc)))
2444 (set (match_dup 0) (const_int 1))
2445 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2446 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2447 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2448 (label_ref (match_dup 4)) (pc)))]
2451 { operands[5] = gen_reg_rtx (CCUNSmode);
2452 operands[6] = gen_reg_rtx (CCmode);
2455 (define_expand "udivmodsi4"
2456 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2457 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2458 (match_operand:SI 2 "reg_or_cint_operand" "")))
2459 (set (match_operand:SI 3 "gpc_reg_operand" "")
2460 (umod:SI (match_dup 1) (match_dup 2)))])]
2468 if (! TARGET_POWERPC)
2470 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2471 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2472 emit_insn (gen_divus_call ());
2473 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2474 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2481 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2483 operands[2] = force_reg (SImode, operands[2]);
2484 label = gen_label_rtx ();
2485 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2486 operands[3], label));
2489 operands[2] = force_reg (SImode, operands[2]);
2491 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2499 ;; AIX architecture-independent common-mode multiply (DImode),
2500 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2501 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2502 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2503 ;; assumed unused if generating common-mode, so ignore.
2504 (define_insn "mulh_call"
2507 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2508 (sign_extend:DI (reg:SI 4)))
2510 (clobber (match_scratch:SI 0 "=l"))]
2511 "! TARGET_POWER && ! TARGET_POWERPC"
2513 [(set_attr "type" "imul")])
2515 (define_insn "mull_call"
2517 (mult:DI (sign_extend:DI (reg:SI 3))
2518 (sign_extend:DI (reg:SI 4))))
2519 (clobber (match_scratch:SI 0 "=l"))
2520 (clobber (reg:SI 0))]
2521 "! TARGET_POWER && ! TARGET_POWERPC"
2523 [(set_attr "type" "imul")])
2525 (define_insn "divss_call"
2527 (div:SI (reg:SI 3) (reg:SI 4)))
2529 (mod:SI (reg:SI 3) (reg:SI 4)))
2530 (clobber (match_scratch:SI 0 "=l"))
2531 (clobber (reg:SI 0))]
2532 "! TARGET_POWER && ! TARGET_POWERPC"
2534 [(set_attr "type" "idiv")])
2536 (define_insn "divus_call"
2538 (udiv:SI (reg:SI 3) (reg:SI 4)))
2540 (umod:SI (reg:SI 3) (reg:SI 4)))
2541 (clobber (match_scratch:SI 0 "=l"))
2542 (clobber (reg:SI 0))
2543 (clobber (match_scratch:CC 1 "=x"))
2544 (clobber (reg:CC 69))]
2545 "! TARGET_POWER && ! TARGET_POWERPC"
2547 [(set_attr "type" "idiv")])
2549 (define_insn "quoss_call"
2551 (div:SI (reg:SI 3) (reg:SI 4)))
2552 (clobber (match_scratch:SI 0 "=l"))]
2553 "! TARGET_POWER && ! TARGET_POWERPC"
2555 [(set_attr "type" "idiv")])
2557 (define_insn "quous_call"
2559 (udiv:SI (reg:SI 3) (reg:SI 4)))
2560 (clobber (match_scratch:SI 0 "=l"))
2561 (clobber (reg:SI 0))
2562 (clobber (match_scratch:CC 1 "=x"))
2563 (clobber (reg:CC 69))]
2564 "! TARGET_POWER && ! TARGET_POWERPC"
2566 [(set_attr "type" "idiv")])
2568 ;; Logical instructions
2569 ;; The logical instructions are mostly combined by using match_operator,
2570 ;; but the plain AND insns are somewhat different because there is no
2571 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2572 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2574 (define_insn "andsi3"
2575 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2576 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2577 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2578 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2582 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2583 {andil.|andi.} %0,%1,%b2
2584 {andiu.|andis.} %0,%1,%u2")
2586 ;; Note to set cr's other than cr0 we do the and immediate and then
2587 ;; the test again -- this avoids a mcrf which on the higher end
2588 ;; machines causes an execution serialization
2590 (define_insn "*andsi3_internal2"
2591 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2592 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2593 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2595 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2596 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2597 "! TARGET_POWERPC64"
2600 {andil.|andi.} %3,%1,%b2
2601 {andiu.|andis.} %3,%1,%u2
2602 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2607 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2608 (set_attr "length" "4,4,4,4,8,8,8,8")])
2611 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2612 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2613 (match_operand:SI 2 "and_operand" ""))
2615 (clobber (match_scratch:SI 3 ""))
2616 (clobber (match_scratch:CC 4 ""))]
2617 "! TARGET_POWERPC64 && reload_completed"
2618 [(parallel [(set (match_dup 3)
2619 (and:SI (match_dup 1)
2621 (clobber (match_dup 4))])
2623 (compare:CC (match_dup 3)
2627 (define_insn "*andsi3_internal3"
2628 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2629 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2630 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2632 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2633 (and:SI (match_dup 1)
2635 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2636 "! TARGET_POWERPC64"
2639 {andil.|andi.} %0,%1,%b2
2640 {andiu.|andis.} %0,%1,%u2
2641 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2646 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2647 (set_attr "length" "4,4,4,4,8,8,8,8")])
2650 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2651 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2652 (match_operand:SI 2 "and_operand" ""))
2654 (set (match_operand:SI 0 "gpc_reg_operand" "")
2655 (and:SI (match_dup 1)
2657 (clobber (match_scratch:CC 4 ""))]
2658 "! TARGET_POWERPC64 && reload_completed"
2659 [(parallel [(set (match_dup 0)
2660 (and:SI (match_dup 1)
2662 (clobber (match_dup 4))])
2664 (compare:CC (match_dup 0)
2668 (define_expand "iorsi3"
2669 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2670 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2671 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2675 if (GET_CODE (operands[2]) == CONST_INT
2676 && ! logical_operand (operands[2], SImode))
2678 HOST_WIDE_INT value = INTVAL (operands[2]);
2679 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2680 ? operands[0] : gen_reg_rtx (SImode));
2682 emit_insn (gen_iorsi3 (tmp, operands[1],
2683 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2684 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2689 (define_expand "xorsi3"
2690 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2691 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2692 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2696 if (GET_CODE (operands[2]) == CONST_INT
2697 && ! logical_operand (operands[2], SImode))
2699 HOST_WIDE_INT value = INTVAL (operands[2]);
2700 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2701 ? operands[0] : gen_reg_rtx (SImode));
2703 emit_insn (gen_xorsi3 (tmp, operands[1],
2704 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2705 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2710 (define_insn "*boolsi3_internal1"
2711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2712 (match_operator:SI 3 "boolean_or_operator"
2713 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2714 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2718 {%q3il|%q3i} %0,%1,%b2
2719 {%q3iu|%q3is} %0,%1,%u2")
2721 (define_insn "*boolsi3_internal2"
2722 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2723 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2724 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2725 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2727 (clobber (match_scratch:SI 3 "=r,r"))]
2728 "! TARGET_POWERPC64"
2732 [(set_attr "type" "compare")
2733 (set_attr "length" "4,8")])
2736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2737 (compare:CC (match_operator:SI 4 "boolean_operator"
2738 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2739 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2741 (clobber (match_scratch:SI 3 ""))]
2742 "! TARGET_POWERPC64 && reload_completed"
2743 [(set (match_dup 3) (match_dup 4))
2745 (compare:CC (match_dup 3)
2749 (define_insn "*boolsi3_internal3"
2750 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2751 (compare:CC (match_operator:SI 4 "boolean_operator"
2752 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2753 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2757 "! TARGET_POWERPC64"
2761 [(set_attr "type" "compare")
2762 (set_attr "length" "4,8")])
2765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2766 (compare:CC (match_operator:SI 4 "boolean_operator"
2767 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2768 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2770 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2772 "! TARGET_POWERPC64 && reload_completed"
2773 [(set (match_dup 0) (match_dup 4))
2775 (compare:CC (match_dup 0)
2779 ;; Split an logical operation that we can't do in one insn into two insns,
2780 ;; each of which does one 16-bit part. This is used by combine.
2783 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2784 (match_operator:SI 3 "boolean_or_operator"
2785 [(match_operand:SI 1 "gpc_reg_operand" "")
2786 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2788 [(set (match_dup 0) (match_dup 4))
2789 (set (match_dup 0) (match_dup 5))]
2793 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2794 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2796 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2797 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2801 (define_insn "*boolcsi3_internal1"
2802 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2803 (match_operator:SI 3 "boolean_operator"
2804 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2805 (match_operand:SI 2 "logical_operand" "r")]))]
2809 (define_insn "*boolcsi3_internal2"
2810 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2811 (compare:CC (match_operator:SI 4 "boolean_operator"
2812 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2813 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2815 (clobber (match_scratch:SI 3 "=r,r"))]
2816 "! TARGET_POWERPC64"
2820 [(set_attr "type" "compare")
2821 (set_attr "length" "4,8")])
2824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2825 (compare:CC (match_operator:SI 4 "boolean_operator"
2826 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2827 (match_operand:SI 2 "gpc_reg_operand" "r")])
2829 (clobber (match_scratch:SI 3 ""))]
2830 "! TARGET_POWERPC64 && reload_completed"
2831 [(set (match_dup 3) (match_dup 4))
2833 (compare:CC (match_dup 3)
2837 (define_insn "*boolcsi3_internal3"
2838 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2839 (compare:CC (match_operator:SI 4 "boolean_operator"
2840 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2841 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2845 "! TARGET_POWERPC64"
2849 [(set_attr "type" "compare")
2850 (set_attr "length" "4,8")])
2853 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2854 (compare:CC (match_operator:SI 4 "boolean_operator"
2855 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2856 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2858 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2860 "! TARGET_POWERPC64 && reload_completed"
2861 [(set (match_dup 0) (match_dup 4))
2863 (compare:CC (match_dup 0)
2867 (define_insn "*boolccsi3_internal1"
2868 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2869 (match_operator:SI 3 "boolean_operator"
2870 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2871 (not:SI (match_operand:SI 2 "logical_operand" "r"))]))]
2875 (define_insn "*boolccsi3_internal2"
2876 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2877 (compare:CC (match_operator:SI 4 "boolean_operator"
2878 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2879 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2881 (clobber (match_scratch:SI 3 "=r,r"))]
2882 "! TARGET_POWERPC64"
2886 [(set_attr "type" "compare")
2887 (set_attr "length" "4,8")])
2890 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2891 (compare:CC (match_operator:SI 4 "boolean_operator"
2892 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2893 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))])
2895 (clobber (match_scratch:SI 3 ""))]
2896 "! TARGET_POWERPC64 && reload_completed"
2897 [(set (match_dup 3) (match_dup 4))
2899 (compare:CC (match_dup 3)
2903 (define_insn "*boolccsi3_internal3"
2904 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2905 (compare:CC (match_operator:SI 4 "boolean_operator"
2906 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2907 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2909 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2911 "! TARGET_POWERPC64"
2915 [(set_attr "type" "compare")
2916 (set_attr "length" "4,8")])
2919 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2920 (compare:CC (match_operator:SI 4 "boolean_operator"
2921 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2922 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2924 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2926 "! TARGET_POWERPC64 && reload_completed"
2927 [(set (match_dup 0) (match_dup 4))
2929 (compare:CC (match_dup 0)
2933 ;; maskir insn. We need four forms because things might be in arbitrary
2934 ;; orders. Don't define forms that only set CR fields because these
2935 ;; would modify an input register.
2937 (define_insn "*maskir_internal1"
2938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2939 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2940 (match_operand:SI 1 "gpc_reg_operand" "0"))
2941 (and:SI (match_dup 2)
2942 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
2946 (define_insn "*maskir_internal2"
2947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2948 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2949 (match_operand:SI 1 "gpc_reg_operand" "0"))
2950 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2955 (define_insn "*maskir_internal3"
2956 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2957 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2958 (match_operand:SI 3 "gpc_reg_operand" "r"))
2959 (and:SI (not:SI (match_dup 2))
2960 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2964 (define_insn "*maskir_internal4"
2965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2966 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2967 (match_operand:SI 2 "gpc_reg_operand" "r"))
2968 (and:SI (not:SI (match_dup 2))
2969 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
2973 (define_insn "*maskir_internal5"
2974 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
2976 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2977 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2978 (and:SI (match_dup 2)
2979 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
2981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2982 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2983 (and:SI (match_dup 2) (match_dup 3))))]
2988 [(set_attr "type" "compare")
2989 (set_attr "length" "4,8")])
2992 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2994 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2995 (match_operand:SI 1 "gpc_reg_operand" ""))
2996 (and:SI (match_dup 2)
2997 (match_operand:SI 3 "gpc_reg_operand" "")))
2999 (set (match_operand:SI 0 "gpc_reg_operand" "")
3000 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3001 (and:SI (match_dup 2) (match_dup 3))))]
3002 "TARGET_POWER && reload_completed"
3004 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3005 (and:SI (match_dup 2) (match_dup 3))))
3007 (compare:CC (match_dup 0)
3011 (define_insn "*maskir_internal6"
3012 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3014 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3015 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3016 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3019 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3020 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3021 (and:SI (match_dup 3) (match_dup 2))))]
3026 [(set_attr "type" "compare")
3027 (set_attr "length" "4,8")])
3030 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3032 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3033 (match_operand:SI 1 "gpc_reg_operand" ""))
3034 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3037 (set (match_operand:SI 0 "gpc_reg_operand" "")
3038 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3039 (and:SI (match_dup 3) (match_dup 2))))]
3040 "TARGET_POWER && reload_completed"
3042 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3043 (and:SI (match_dup 3) (match_dup 2))))
3045 (compare:CC (match_dup 0)
3049 (define_insn "*maskir_internal7"
3050 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3052 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3053 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3054 (and:SI (not:SI (match_dup 2))
3055 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3057 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3058 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3059 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3064 [(set_attr "type" "compare")
3065 (set_attr "length" "4,8")])
3068 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3070 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3071 (match_operand:SI 3 "gpc_reg_operand" ""))
3072 (and:SI (not:SI (match_dup 2))
3073 (match_operand:SI 1 "gpc_reg_operand" "")))
3075 (set (match_operand:SI 0 "gpc_reg_operand" "")
3076 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3077 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3078 "TARGET_POWER && reload_completed"
3080 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3081 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3083 (compare:CC (match_dup 0)
3087 (define_insn "*maskir_internal8"
3088 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3090 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3091 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3092 (and:SI (not:SI (match_dup 2))
3093 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3095 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3096 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3097 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3102 [(set_attr "type" "compare")
3103 (set_attr "length" "4,8")])
3106 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3108 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3109 (match_operand:SI 2 "gpc_reg_operand" ""))
3110 (and:SI (not:SI (match_dup 2))
3111 (match_operand:SI 1 "gpc_reg_operand" "")))
3113 (set (match_operand:SI 0 "gpc_reg_operand" "")
3114 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3115 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3116 "TARGET_POWER && reload_completed"
3118 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3119 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3121 (compare:CC (match_dup 0)
3125 ;; Rotate and shift insns, in all their variants. These support shifts,
3126 ;; field inserts and extracts, and various combinations thereof.
3127 (define_expand "insv"
3128 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3129 (match_operand:SI 1 "const_int_operand" "")
3130 (match_operand:SI 2 "const_int_operand" ""))
3131 (match_operand 3 "gpc_reg_operand" ""))]
3135 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3136 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3137 compiler if the address of the structure is taken later. */
3138 if (GET_CODE (operands[0]) == SUBREG
3139 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3142 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3143 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3145 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3149 (define_insn "insvsi"
3150 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3151 (match_operand:SI 1 "const_int_operand" "i")
3152 (match_operand:SI 2 "const_int_operand" "i"))
3153 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3157 int start = INTVAL (operands[2]) & 31;
3158 int size = INTVAL (operands[1]) & 31;
3160 operands[4] = GEN_INT (32 - start - size);
3161 operands[1] = GEN_INT (start + size - 1);
3162 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3165 (define_insn "*insvsi_internal1"
3166 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3167 (match_operand:SI 1 "const_int_operand" "i")
3168 (match_operand:SI 2 "const_int_operand" "i"))
3169 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3170 (match_operand:SI 4 "const_int_operand" "i")))]
3171 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3174 int shift = INTVAL (operands[4]) & 31;
3175 int start = INTVAL (operands[2]) & 31;
3176 int size = INTVAL (operands[1]) & 31;
3178 operands[4] = GEN_INT (shift - start - size);
3179 operands[1] = GEN_INT (start + size - 1);
3180 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3183 (define_insn "*insvsi_internal2"
3184 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3185 (match_operand:SI 1 "const_int_operand" "i")
3186 (match_operand:SI 2 "const_int_operand" "i"))
3187 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3188 (match_operand:SI 4 "const_int_operand" "i")))]
3189 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3192 int shift = INTVAL (operands[4]) & 31;
3193 int start = INTVAL (operands[2]) & 31;
3194 int size = INTVAL (operands[1]) & 31;
3196 operands[4] = GEN_INT (32 - shift - start - size);
3197 operands[1] = GEN_INT (start + size - 1);
3198 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3201 (define_insn "*insvsi_internal3"
3202 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3203 (match_operand:SI 1 "const_int_operand" "i")
3204 (match_operand:SI 2 "const_int_operand" "i"))
3205 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3206 (match_operand:SI 4 "const_int_operand" "i")))]
3207 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3210 int shift = INTVAL (operands[4]) & 31;
3211 int start = INTVAL (operands[2]) & 31;
3212 int size = INTVAL (operands[1]) & 31;
3214 operands[4] = GEN_INT (32 - shift - start - size);
3215 operands[1] = GEN_INT (start + size - 1);
3216 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3219 (define_insn "*insvsi_internal4"
3220 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3221 (match_operand:SI 1 "const_int_operand" "i")
3222 (match_operand:SI 2 "const_int_operand" "i"))
3223 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3224 (match_operand:SI 4 "const_int_operand" "i")
3225 (match_operand:SI 5 "const_int_operand" "i")))]
3226 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3229 int extract_start = INTVAL (operands[5]) & 31;
3230 int extract_size = INTVAL (operands[4]) & 31;
3231 int insert_start = INTVAL (operands[2]) & 31;
3232 int insert_size = INTVAL (operands[1]) & 31;
3234 /* Align extract field with insert field */
3235 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3236 operands[1] = GEN_INT (insert_start + insert_size - 1);
3237 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3240 (define_insn "insvdi"
3241 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3242 (match_operand:SI 1 "const_int_operand" "i")
3243 (match_operand:SI 2 "const_int_operand" "i"))
3244 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3248 int start = INTVAL (operands[2]) & 63;
3249 int size = INTVAL (operands[1]) & 63;
3251 operands[1] = GEN_INT (64 - start - size);
3252 return \"rldimi %0,%3,%H1,%H2\";
3255 (define_expand "extzv"
3256 [(set (match_operand 0 "gpc_reg_operand" "")
3257 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3258 (match_operand:SI 2 "const_int_operand" "")
3259 (match_operand:SI 3 "const_int_operand" "")))]
3263 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3264 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3265 compiler if the address of the structure is taken later. */
3266 if (GET_CODE (operands[0]) == SUBREG
3267 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3270 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3271 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3273 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3277 (define_insn "extzvsi"
3278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3279 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3280 (match_operand:SI 2 "const_int_operand" "i")
3281 (match_operand:SI 3 "const_int_operand" "i")))]
3285 int start = INTVAL (operands[3]) & 31;
3286 int size = INTVAL (operands[2]) & 31;
3288 if (start + size >= 32)
3289 operands[3] = const0_rtx;
3291 operands[3] = GEN_INT (start + size);
3292 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3295 (define_insn "*extzvsi_internal1"
3296 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3297 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3298 (match_operand:SI 2 "const_int_operand" "i,i")
3299 (match_operand:SI 3 "const_int_operand" "i,i"))
3301 (clobber (match_scratch:SI 4 "=r,r"))]
3302 "! TARGET_POWERPC64"
3305 int start = INTVAL (operands[3]) & 31;
3306 int size = INTVAL (operands[2]) & 31;
3308 /* Force split for non-cc0 compare. */
3309 if (which_alternative == 1)
3312 /* If the bitfield being tested fits in the upper or lower half of a
3313 word, it is possible to use andiu. or andil. to test it. This is
3314 useful because the condition register set-use delay is smaller for
3315 andi[ul]. than for rlinm. This doesn't work when the starting bit
3316 position is 0 because the LT and GT bits may be set wrong. */
3318 if ((start > 0 && start + size <= 16) || start >= 16)
3320 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3321 - (1 << (16 - (start & 15) - size))));
3323 return \"{andiu.|andis.} %4,%1,%3\";
3325 return \"{andil.|andi.} %4,%1,%3\";
3328 if (start + size >= 32)
3329 operands[3] = const0_rtx;
3331 operands[3] = GEN_INT (start + size);
3332 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3334 [(set_attr "type" "compare")
3335 (set_attr "length" "4,8")])
3338 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3339 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3340 (match_operand:SI 2 "const_int_operand" "")
3341 (match_operand:SI 3 "const_int_operand" ""))
3343 (clobber (match_scratch:SI 4 ""))]
3344 "! TARGET_POWERPC64 && reload_completed"
3346 (zero_extract:SI (match_dup 1) (match_dup 2)
3349 (compare:CC (match_dup 4)
3353 (define_insn "*extzvsi_internal2"
3354 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3355 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3356 (match_operand:SI 2 "const_int_operand" "i,i")
3357 (match_operand:SI 3 "const_int_operand" "i,i"))
3359 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3360 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3361 "! TARGET_POWERPC64"
3364 int start = INTVAL (operands[3]) & 31;
3365 int size = INTVAL (operands[2]) & 31;
3367 /* Force split for non-cc0 compare. */
3368 if (which_alternative == 1)
3371 if (start >= 16 && start + size == 32)
3373 operands[3] = GEN_INT ((1 << (32 - start)) - 1);
3374 return \"{andil.|andi.} %0,%1,%3\";
3377 if (start + size >= 32)
3378 operands[3] = const0_rtx;
3380 operands[3] = GEN_INT (start + size);
3381 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3383 [(set_attr "type" "delayed_compare")
3384 (set_attr "length" "4,8")])
3387 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3388 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3389 (match_operand:SI 2 "const_int_operand" "")
3390 (match_operand:SI 3 "const_int_operand" ""))
3392 (set (match_operand:SI 0 "gpc_reg_operand" "")
3393 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3394 "! TARGET_POWERPC64 && reload_completed"
3396 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3398 (compare:CC (match_dup 0)
3402 (define_insn "extzvdi"
3403 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3404 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3405 (match_operand:SI 2 "const_int_operand" "i")
3406 (match_operand:SI 3 "const_int_operand" "i")))]
3410 int start = INTVAL (operands[3]) & 63;
3411 int size = INTVAL (operands[2]) & 63;
3413 if (start + size >= 64)
3414 operands[3] = const0_rtx;
3416 operands[3] = GEN_INT (start + size);
3417 operands[2] = GEN_INT (64 - size);
3418 return \"rldicl %0,%1,%3,%2\";
3421 (define_insn "*extzvdi_internal1"
3422 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3423 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3424 (match_operand:SI 2 "const_int_operand" "i")
3425 (match_operand:SI 3 "const_int_operand" "i"))
3427 (clobber (match_scratch:DI 4 "=r"))]
3431 int start = INTVAL (operands[3]) & 63;
3432 int size = INTVAL (operands[2]) & 63;
3434 if (start + size >= 64)
3435 operands[3] = const0_rtx;
3437 operands[3] = GEN_INT (start + size);
3438 operands[2] = GEN_INT (64 - size);
3439 return \"rldicl. %4,%1,%3,%2\";
3442 (define_insn "*extzvdi_internal2"
3443 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3444 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3445 (match_operand:SI 2 "const_int_operand" "i")
3446 (match_operand:SI 3 "const_int_operand" "i"))
3448 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3449 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3453 int start = INTVAL (operands[3]) & 63;
3454 int size = INTVAL (operands[2]) & 63;
3456 if (start + size >= 64)
3457 operands[3] = const0_rtx;
3459 operands[3] = GEN_INT (start + size);
3460 operands[2] = GEN_INT (64 - size);
3461 return \"rldicl. %0,%1,%3,%2\";
3464 (define_insn "rotlsi3"
3465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3466 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3467 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3469 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3471 (define_insn "*rotlsi3_internal2"
3472 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3473 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3474 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3476 (clobber (match_scratch:SI 3 "=r,r"))]
3477 "! TARGET_POWERPC64"
3479 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3481 [(set_attr "type" "delayed_compare")
3482 (set_attr "length" "4,8")])
3485 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3486 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3487 (match_operand:SI 2 "reg_or_cint_operand" ""))
3489 (clobber (match_scratch:SI 3 ""))]
3490 "! TARGET_POWERPC64 && reload_completed"
3492 (rotate:SI (match_dup 1) (match_dup 2)))
3494 (compare:CC (match_dup 3)
3498 (define_insn "*rotlsi3_internal3"
3499 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3500 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3501 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3503 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3504 (rotate:SI (match_dup 1) (match_dup 2)))]
3505 "! TARGET_POWERPC64"
3507 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3509 [(set_attr "type" "delayed_compare")
3510 (set_attr "length" "4,8")])
3513 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3514 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3515 (match_operand:SI 2 "reg_or_cint_operand" ""))
3517 (set (match_operand:SI 0 "gpc_reg_operand" "")
3518 (rotate:SI (match_dup 1) (match_dup 2)))]
3519 "! TARGET_POWERPC64 && reload_completed"
3521 (rotate:SI (match_dup 1) (match_dup 2)))
3523 (compare:CC (match_dup 0)
3527 (define_insn "*rotlsi3_internal4"
3528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3529 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3530 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3531 (match_operand:SI 3 "mask_operand" "T")))]
3533 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3535 (define_insn "*rotlsi3_internal5"
3536 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3538 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3539 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3540 (match_operand:SI 3 "mask_operand" "T,T"))
3542 (clobber (match_scratch:SI 4 "=r,r"))]
3543 "! TARGET_POWERPC64"
3545 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3547 [(set_attr "type" "delayed_compare")
3548 (set_attr "length" "4,8")])
3551 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3553 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3554 (match_operand:SI 2 "reg_or_cint_operand" ""))
3555 (match_operand:SI 3 "mask_operand" ""))
3557 (clobber (match_scratch:SI 4 ""))]
3558 "! TARGET_POWERPC64 && reload_completed"
3560 (and:SI (rotate:SI (match_dup 1)
3564 (compare:CC (match_dup 4)
3568 (define_insn "*rotlsi3_internal6"
3569 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3571 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3572 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3573 (match_operand:SI 3 "mask_operand" "T,T"))
3575 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3576 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3577 "! TARGET_POWERPC64"
3579 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3581 [(set_attr "type" "delayed_compare")
3582 (set_attr "length" "4,8")])
3585 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3587 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3588 (match_operand:SI 2 "reg_or_cint_operand" ""))
3589 (match_operand:SI 3 "mask_operand" ""))
3591 (set (match_operand:SI 0 "gpc_reg_operand" "")
3592 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3593 "! TARGET_POWERPC64 && reload_completed"
3595 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3597 (compare:CC (match_dup 0)
3601 (define_insn "*rotlsi3_internal7"
3602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3605 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3606 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3608 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3610 (define_insn "*rotlsi3_internal8"
3611 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3612 (compare:CC (zero_extend:SI
3614 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3615 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3617 (clobber (match_scratch:SI 3 "=r,r"))]
3620 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3622 [(set_attr "type" "delayed_compare")
3623 (set_attr "length" "4,8")])
3626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3627 (compare:CC (zero_extend:SI
3629 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3630 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3632 (clobber (match_scratch:SI 3 ""))]
3635 (zero_extend:SI (subreg:QI
3636 (rotate:SI (match_dup 1)
3639 (compare:CC (match_dup 3)
3643 (define_insn "*rotlsi3_internal9"
3644 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3645 (compare:CC (zero_extend:SI
3647 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3648 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3650 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3651 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3654 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3656 [(set_attr "type" "delayed_compare")
3657 (set_attr "length" "4,8")])
3660 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3661 (compare:CC (zero_extend:SI
3663 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3664 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3666 (set (match_operand:SI 0 "gpc_reg_operand" "")
3667 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3670 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3672 (compare:CC (match_dup 0)
3676 (define_insn "*rotlsi3_internal10"
3677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3680 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3681 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3683 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3685 (define_insn "*rotlsi3_internal11"
3686 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3687 (compare:CC (zero_extend:SI
3689 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3690 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3692 (clobber (match_scratch:SI 3 "=r,r"))]
3695 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3697 [(set_attr "type" "delayed_compare")
3698 (set_attr "length" "4,8")])
3701 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3702 (compare:CC (zero_extend:SI
3704 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3705 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3707 (clobber (match_scratch:SI 3 ""))]
3710 (zero_extend:SI (subreg:HI
3711 (rotate:SI (match_dup 1)
3714 (compare:CC (match_dup 3)
3718 (define_insn "*rotlsi3_internal12"
3719 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3720 (compare:CC (zero_extend:SI
3722 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3723 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3725 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3726 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3729 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3731 [(set_attr "type" "delayed_compare")
3732 (set_attr "length" "4,8")])
3735 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3736 (compare:CC (zero_extend:SI
3738 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3739 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3741 (set (match_operand:SI 0 "gpc_reg_operand" "")
3742 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3745 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3747 (compare:CC (match_dup 0)
3751 ;; Note that we use "sle." instead of "sl." so that we can set
3752 ;; SHIFT_COUNT_TRUNCATED.
3754 (define_expand "ashlsi3"
3755 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3756 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3757 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3762 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3764 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3768 (define_insn "ashlsi3_power"
3769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3770 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3771 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3772 (clobber (match_scratch:SI 3 "=q,X"))]
3776 {sli|slwi} %0,%1,%h2")
3778 (define_insn "ashlsi3_no_power"
3779 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3780 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3781 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3783 "{sl|slw}%I2 %0,%1,%h2")
3786 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3787 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3788 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3790 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3791 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3795 {sli.|slwi.} %3,%1,%h2
3798 [(set_attr "type" "delayed_compare")
3799 (set_attr "length" "4,4,8,8")])
3802 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3803 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3804 (match_operand:SI 2 "reg_or_cint_operand" ""))
3806 (clobber (match_scratch:SI 3 ""))
3807 (clobber (match_scratch:SI 4 ""))]
3808 "TARGET_POWER && reload_completed"
3809 [(parallel [(set (match_dup 3)
3810 (ashift:SI (match_dup 1) (match_dup 2)))
3811 (clobber (match_dup 4))])
3813 (compare:CC (match_dup 3)
3818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3819 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3820 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3822 (clobber (match_scratch:SI 3 "=r,r"))]
3823 "! TARGET_POWER && ! TARGET_POWERPC64"
3825 {sl|slw}%I2. %3,%1,%h2
3827 [(set_attr "type" "delayed_compare")
3828 (set_attr "length" "4,8")])
3831 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3832 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3833 (match_operand:SI 2 "reg_or_cint_operand" ""))
3835 (clobber (match_scratch:SI 3 ""))]
3836 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3838 (ashift:SI (match_dup 1) (match_dup 2)))
3840 (compare:CC (match_dup 3)
3845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3846 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3847 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3849 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3850 (ashift:SI (match_dup 1) (match_dup 2)))
3851 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3855 {sli.|slwi.} %0,%1,%h2
3858 [(set_attr "type" "delayed_compare")
3859 (set_attr "length" "4,4,8,8")])
3862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3863 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3864 (match_operand:SI 2 "reg_or_cint_operand" ""))
3866 (set (match_operand:SI 0 "gpc_reg_operand" "")
3867 (ashift:SI (match_dup 1) (match_dup 2)))
3868 (clobber (match_scratch:SI 4 ""))]
3869 "TARGET_POWER && reload_completed"
3870 [(parallel [(set (match_dup 0)
3871 (ashift:SI (match_dup 1) (match_dup 2)))
3872 (clobber (match_dup 4))])
3874 (compare:CC (match_dup 0)
3879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3880 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3883 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3884 (ashift:SI (match_dup 1) (match_dup 2)))]
3885 "! TARGET_POWER && ! TARGET_POWERPC64"
3887 {sl|slw}%I2. %0,%1,%h2
3889 [(set_attr "type" "delayed_compare")
3890 (set_attr "length" "4,8")])
3893 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3894 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3895 (match_operand:SI 2 "reg_or_cint_operand" ""))
3897 (set (match_operand:SI 0 "gpc_reg_operand" "")
3898 (ashift:SI (match_dup 1) (match_dup 2)))]
3899 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3901 (ashift:SI (match_dup 1) (match_dup 2)))
3903 (compare:CC (match_dup 0)
3908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3909 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3910 (match_operand:SI 2 "const_int_operand" "i"))
3911 (match_operand:SI 3 "mask_operand" "T")))]
3912 "includes_lshift_p (operands[2], operands[3])"
3913 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
3916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3918 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3919 (match_operand:SI 2 "const_int_operand" "i,i"))
3920 (match_operand:SI 3 "mask_operand" "T,T"))
3922 (clobber (match_scratch:SI 4 "=r,r"))]
3923 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
3925 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3927 [(set_attr "type" "delayed_compare")
3928 (set_attr "length" "4,8")])
3931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3933 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3934 (match_operand:SI 2 "const_int_operand" ""))
3935 (match_operand:SI 3 "mask_operand" ""))
3937 (clobber (match_scratch:SI 4 ""))]
3938 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
3940 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3943 (compare:CC (match_dup 4)
3948 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3950 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3951 (match_operand:SI 2 "const_int_operand" "i,i"))
3952 (match_operand:SI 3 "mask_operand" "T,T"))
3954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3955 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3956 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
3958 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3960 [(set_attr "type" "delayed_compare")
3961 (set_attr "length" "4,8")])
3964 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3966 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3967 (match_operand:SI 2 "const_int_operand" ""))
3968 (match_operand:SI 3 "mask_operand" ""))
3970 (set (match_operand:SI 0 "gpc_reg_operand" "")
3971 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3972 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
3974 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3976 (compare:CC (match_dup 0)
3980 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
3982 (define_expand "lshrsi3"
3983 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3984 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3985 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3990 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3992 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
3996 (define_insn "lshrsi3_power"
3997 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3998 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3999 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4000 (clobber (match_scratch:SI 3 "=q,X,X"))]
4005 {s%A2i|s%A2wi} %0,%1,%h2")
4007 (define_insn "lshrsi3_no_power"
4008 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4009 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4010 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4014 {sr|srw}%I2 %0,%1,%h2")
4017 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4018 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4019 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4021 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4022 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4027 {s%A2i.|s%A2wi.} %3,%1,%h2
4031 [(set_attr "type" "delayed_compare")
4032 (set_attr "length" "4,4,4,8,8,8")])
4035 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4036 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4037 (match_operand:SI 2 "reg_or_cint_operand" ""))
4039 (clobber (match_scratch:SI 3 ""))
4040 (clobber (match_scratch:SI 4 ""))]
4041 "TARGET_POWER && reload_completed"
4042 [(parallel [(set (match_dup 3)
4043 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4044 (clobber (match_dup 4))])
4046 (compare:CC (match_dup 3)
4051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4052 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4053 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4055 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4056 "! TARGET_POWER && ! TARGET_POWERPC64"
4059 {sr|srw}%I2. %3,%1,%h2
4062 [(set_attr "type" "delayed_compare")
4063 (set_attr "length" "4,4,8,8")])
4066 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4067 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4068 (match_operand:SI 2 "reg_or_cint_operand" ""))
4070 (clobber (match_scratch:SI 3 ""))]
4071 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4073 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4075 (compare:CC (match_dup 3)
4080 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4081 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4082 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4085 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4086 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4091 {s%A2i.|s%A2wi.} %0,%1,%h2
4095 [(set_attr "type" "delayed_compare")
4096 (set_attr "length" "4,4,4,8,8,8")])
4099 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4100 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4101 (match_operand:SI 2 "reg_or_cint_operand" ""))
4103 (set (match_operand:SI 0 "gpc_reg_operand" "")
4104 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4105 (clobber (match_scratch:SI 4 ""))]
4106 "TARGET_POWER && reload_completed"
4107 [(parallel [(set (match_dup 0)
4108 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4109 (clobber (match_dup 4))])
4111 (compare:CC (match_dup 0)
4116 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4117 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4118 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4120 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4121 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4122 "! TARGET_POWER && ! TARGET_POWERPC64"
4125 {sr|srw}%I2. %0,%1,%h2
4128 [(set_attr "type" "delayed_compare")
4129 (set_attr "length" "4,4,8,8")])
4132 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4133 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "reg_or_cint_operand" ""))
4136 (set (match_operand:SI 0 "gpc_reg_operand" "")
4137 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4138 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4140 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4142 (compare:CC (match_dup 0)
4147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4148 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4149 (match_operand:SI 2 "const_int_operand" "i"))
4150 (match_operand:SI 3 "mask_operand" "T")))]
4151 "includes_rshift_p (operands[2], operands[3])"
4152 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4157 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4158 (match_operand:SI 2 "const_int_operand" "i,i"))
4159 (match_operand:SI 3 "mask_operand" "T,T"))
4161 (clobber (match_scratch:SI 4 "=r,r"))]
4162 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4164 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4166 [(set_attr "type" "delayed_compare")
4167 (set_attr "length" "4,8")])
4170 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4172 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4173 (match_operand:SI 2 "const_int_operand" ""))
4174 (match_operand:SI 3 "mask_operand" ""))
4176 (clobber (match_scratch:SI 4 ""))]
4177 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4179 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4182 (compare:CC (match_dup 4)
4187 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4189 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4190 (match_operand:SI 2 "const_int_operand" "i,i"))
4191 (match_operand:SI 3 "mask_operand" "T,T"))
4193 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4194 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4195 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4197 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4199 [(set_attr "type" "delayed_compare")
4200 (set_attr "length" "4,8")])
4203 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4205 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4206 (match_operand:SI 2 "const_int_operand" ""))
4207 (match_operand:SI 3 "mask_operand" ""))
4209 (set (match_operand:SI 0 "gpc_reg_operand" "")
4210 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4211 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4213 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4215 (compare:CC (match_dup 0)
4220 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4223 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4224 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4225 "includes_rshift_p (operands[2], GEN_INT (255))"
4226 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4229 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4233 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4234 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4236 (clobber (match_scratch:SI 3 "=r,r"))]
4237 "includes_rshift_p (operands[2], GEN_INT (255))"
4239 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4241 [(set_attr "type" "delayed_compare")
4242 (set_attr "length" "4,8")])
4245 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4249 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4250 (match_operand:SI 2 "const_int_operand" "")) 0))
4252 (clobber (match_scratch:SI 3 ""))]
4253 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4255 (zero_extend:SI (subreg:QI
4256 (lshiftrt:SI (match_dup 1)
4259 (compare:CC (match_dup 3)
4264 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4268 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4269 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4271 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4272 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4273 "includes_rshift_p (operands[2], GEN_INT (255))"
4275 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4277 [(set_attr "type" "delayed_compare")
4278 (set_attr "length" "4,8")])
4281 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4285 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4286 (match_operand:SI 2 "const_int_operand" "")) 0))
4288 (set (match_operand:SI 0 "gpc_reg_operand" "")
4289 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4290 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4292 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4294 (compare:CC (match_dup 0)
4299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4302 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4303 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4304 "includes_rshift_p (operands[2], GEN_INT (65535))"
4305 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4308 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4312 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4313 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4315 (clobber (match_scratch:SI 3 "=r,r"))]
4316 "includes_rshift_p (operands[2], GEN_INT (65535))"
4318 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4320 [(set_attr "type" "delayed_compare")
4321 (set_attr "length" "4,8")])
4324 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4328 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4329 (match_operand:SI 2 "const_int_operand" "")) 0))
4331 (clobber (match_scratch:SI 3 ""))]
4332 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4334 (zero_extend:SI (subreg:HI
4335 (lshiftrt:SI (match_dup 1)
4338 (compare:CC (match_dup 3)
4343 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4347 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4348 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4351 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4352 "includes_rshift_p (operands[2], GEN_INT (65535))"
4354 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4356 [(set_attr "type" "delayed_compare")
4357 (set_attr "length" "4,8")])
4360 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4364 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4365 (match_operand:SI 2 "const_int_operand" "")) 0))
4367 (set (match_operand:SI 0 "gpc_reg_operand" "")
4368 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4369 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4371 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4373 (compare:CC (match_dup 0)
4378 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4380 (match_operand:SI 1 "gpc_reg_operand" "r"))
4381 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4387 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4389 (match_operand:SI 1 "gpc_reg_operand" "r"))
4390 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4396 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4398 (match_operand:SI 1 "gpc_reg_operand" "r"))
4399 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4405 (define_expand "ashrsi3"
4406 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4407 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4408 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4413 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4415 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4419 (define_insn "ashrsi3_power"
4420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4421 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4422 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4423 (clobber (match_scratch:SI 3 "=q,X"))]
4427 {srai|srawi} %0,%1,%h2")
4429 (define_insn "ashrsi3_no_power"
4430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4431 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4432 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4434 "{sra|sraw}%I2 %0,%1,%h2")
4437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4438 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4439 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4441 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4442 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4446 {srai.|srawi.} %3,%1,%h2
4449 [(set_attr "type" "delayed_compare")
4450 (set_attr "length" "4,4,8,8")])
4453 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4454 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4455 (match_operand:SI 2 "reg_or_cint_operand" ""))
4457 (clobber (match_scratch:SI 3 ""))
4458 (clobber (match_scratch:SI 4 ""))]
4459 "TARGET_POWER && reload_completed"
4460 [(parallel [(set (match_dup 3)
4461 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4462 (clobber (match_dup 4))])
4464 (compare:CC (match_dup 3)
4469 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4470 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4471 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4473 (clobber (match_scratch:SI 3 "=r,r"))]
4476 {sra|sraw}%I2. %3,%1,%h2
4478 [(set_attr "type" "delayed_compare")
4479 (set_attr "length" "4,8")])
4482 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4483 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4484 (match_operand:SI 2 "reg_or_cint_operand" ""))
4486 (clobber (match_scratch:SI 3 ""))]
4487 "! TARGET_POWER && reload_completed"
4489 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4491 (compare:CC (match_dup 3)
4496 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4497 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4498 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4500 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4501 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4502 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4506 {srai.|srawi.} %0,%1,%h2
4509 [(set_attr "type" "delayed_compare")
4510 (set_attr "length" "4,4,8,8")])
4513 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4514 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4515 (match_operand:SI 2 "reg_or_cint_operand" ""))
4517 (set (match_operand:SI 0 "gpc_reg_operand" "")
4518 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4519 (clobber (match_scratch:SI 4 ""))]
4520 "TARGET_POWER && reload_completed"
4521 [(parallel [(set (match_dup 0)
4522 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4523 (clobber (match_dup 4))])
4525 (compare:CC (match_dup 0)
4530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4531 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4532 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4534 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4535 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4538 {sra|sraw}%I2. %0,%1,%h2
4540 [(set_attr "type" "delayed_compare")
4541 (set_attr "length" "4,8")])
4544 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4545 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4546 (match_operand:SI 2 "reg_or_cint_operand" ""))
4548 (set (match_operand:SI 0 "gpc_reg_operand" "")
4549 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4550 "! TARGET_POWER && reload_completed"
4552 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4554 (compare:CC (match_dup 0)
4558 ;; Floating-point insns, excluding normal data motion.
4560 ;; PowerPC has a full set of single-precision floating point instructions.
4562 ;; For the POWER architecture, we pretend that we have both SFmode and
4563 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4564 ;; The only conversions we will do will be when storing to memory. In that
4565 ;; case, we will use the "frsp" instruction before storing.
4567 ;; Note that when we store into a single-precision memory location, we need to
4568 ;; use the frsp insn first. If the register being stored isn't dead, we
4569 ;; need a scratch register for the frsp. But this is difficult when the store
4570 ;; is done by reload. It is not incorrect to do the frsp on the register in
4571 ;; this case, we just lose precision that we would have otherwise gotten but
4572 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4574 (define_insn "extendsfdf2"
4575 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4576 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4580 if (REGNO (operands[0]) == REGNO (operands[1]))
4583 return \"fmr %0,%1\";
4585 [(set_attr "type" "fp")])
4587 (define_insn "truncdfsf2"
4588 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4589 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4592 [(set_attr "type" "fp")])
4594 (define_insn "aux_truncdfsf2"
4595 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4596 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
4597 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4599 [(set_attr "type" "fp")])
4601 (define_insn "negsf2"
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4606 [(set_attr "type" "fp")])
4608 (define_insn "abssf2"
4609 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4610 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4613 [(set_attr "type" "fp")])
4616 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4617 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4620 [(set_attr "type" "fp")])
4622 (define_expand "addsf3"
4623 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4624 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4625 (match_operand:SF 2 "gpc_reg_operand" "")))]
4630 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4631 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4632 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4633 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4635 [(set_attr "type" "fp")])
4638 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4639 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4640 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4641 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4642 "{fa|fadd} %0,%1,%2"
4643 [(set_attr "type" "fp")])
4645 (define_expand "subsf3"
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4647 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4648 (match_operand:SF 2 "gpc_reg_operand" "")))]
4653 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4654 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4655 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4656 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4658 [(set_attr "type" "fp")])
4661 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4662 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4663 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4664 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4665 "{fs|fsub} %0,%1,%2"
4666 [(set_attr "type" "fp")])
4668 (define_expand "mulsf3"
4669 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4670 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4671 (match_operand:SF 2 "gpc_reg_operand" "")))]
4676 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4677 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4678 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4679 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4681 [(set_attr "type" "fp")])
4684 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4685 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4686 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4687 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4688 "{fm|fmul} %0,%1,%2"
4689 [(set_attr "type" "dmul")])
4691 (define_expand "divsf3"
4692 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4693 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4694 (match_operand:SF 2 "gpc_reg_operand" "")))]
4699 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4700 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4701 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4702 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4704 [(set_attr "type" "sdiv")])
4707 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4708 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4709 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4710 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4711 "{fd|fdiv} %0,%1,%2"
4712 [(set_attr "type" "ddiv")])
4715 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4716 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4717 (match_operand:SF 2 "gpc_reg_operand" "f"))
4718 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4719 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4720 "fmadds %0,%1,%2,%3"
4721 [(set_attr "type" "fp")])
4724 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4725 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4726 (match_operand:SF 2 "gpc_reg_operand" "f"))
4727 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4728 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4729 "{fma|fmadd} %0,%1,%2,%3"
4730 [(set_attr "type" "dmul")])
4733 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4734 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4735 (match_operand:SF 2 "gpc_reg_operand" "f"))
4736 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4737 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4738 "fmsubs %0,%1,%2,%3"
4739 [(set_attr "type" "fp")])
4742 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4743 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4744 (match_operand:SF 2 "gpc_reg_operand" "f"))
4745 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4746 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4747 "{fms|fmsub} %0,%1,%2,%3"
4748 [(set_attr "type" "dmul")])
4751 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4752 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4753 (match_operand:SF 2 "gpc_reg_operand" "f"))
4754 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4755 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4756 "fnmadds %0,%1,%2,%3"
4757 [(set_attr "type" "fp")])
4760 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4761 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4762 (match_operand:SF 2 "gpc_reg_operand" "f"))
4763 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4764 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4765 "{fnma|fnmadd} %0,%1,%2,%3"
4766 [(set_attr "type" "dmul")])
4769 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4770 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4771 (match_operand:SF 2 "gpc_reg_operand" "f"))
4772 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4773 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4774 "fnmsubs %0,%1,%2,%3"
4775 [(set_attr "type" "fp")])
4778 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4779 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4780 (match_operand:SF 2 "gpc_reg_operand" "f"))
4781 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4782 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4783 "{fnms|fnmsub} %0,%1,%2,%3"
4784 [(set_attr "type" "dmul")])
4786 (define_expand "sqrtsf2"
4787 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4788 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4789 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
4793 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4794 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4795 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
4797 [(set_attr "type" "ssqrt")])
4800 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4801 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4802 "TARGET_POWER2 && TARGET_HARD_FLOAT"
4804 [(set_attr "type" "dsqrt")])
4806 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4807 ;; fsel instruction and some auxiliary computations. Then we just have a
4808 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4810 (define_expand "maxsf3"
4812 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4813 (match_operand:SF 2 "gpc_reg_operand" "")))
4814 (set (match_operand:SF 0 "gpc_reg_operand" "")
4815 (if_then_else:SF (ge (match_dup 3)
4819 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4821 { operands[3] = gen_reg_rtx (SFmode); }")
4824 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4825 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
4826 (match_operand:SF 2 "gpc_reg_operand" "")))
4827 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
4828 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4830 (minus:SF (match_dup 1) (match_dup 2)))
4832 (if_then_else:SF (ge (match_dup 3)
4838 (define_expand "minsf3"
4840 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
4841 (match_operand:SF 1 "gpc_reg_operand" "")))
4842 (set (match_operand:SF 0 "gpc_reg_operand" "")
4843 (if_then_else:SF (ge (match_dup 3)
4847 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4849 { operands[3] = gen_reg_rtx (SFmode); }")
4852 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4853 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
4854 (match_operand:SF 2 "gpc_reg_operand" "")))
4855 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
4856 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4858 (minus:SF (match_dup 2) (match_dup 1)))
4860 (if_then_else:SF (ge (match_dup 3)
4866 (define_expand "movsfcc"
4867 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4868 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4869 (match_operand:SF 2 "gpc_reg_operand" "")
4870 (match_operand:SF 3 "gpc_reg_operand" "")))]
4871 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4875 enum rtx_code code = GET_CODE (operands[1]);
4876 if (! rs6000_compare_fp_p)
4880 case GE: case EQ: case NE:
4881 op0 = rs6000_compare_op0;
4882 op1 = rs6000_compare_op1;
4885 op0 = rs6000_compare_op1;
4886 op1 = rs6000_compare_op0;
4887 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
4890 op0 = rs6000_compare_op1;
4891 op1 = rs6000_compare_op0;
4894 op0 = rs6000_compare_op0;
4895 op1 = rs6000_compare_op1;
4896 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
4901 if (GET_MODE (rs6000_compare_op0) == DFmode)
4903 temp = gen_reg_rtx (DFmode);
4904 emit_insn (gen_subdf3 (temp, op0, op1));
4905 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
4908 emit_insn (gen_negdf2 (temp, temp));
4909 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
4911 else if (code == NE)
4913 emit_insn (gen_negdf2 (temp, temp));
4914 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
4919 temp = gen_reg_rtx (SFmode);
4920 emit_insn (gen_subsf3 (temp, op0, op1));
4921 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
4924 emit_insn (gen_negsf2 (temp, temp));
4925 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
4927 else if (code == NE)
4929 emit_insn (gen_negsf2 (temp, temp));
4930 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
4936 (define_insn "fselsfsf4"
4937 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4938 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4940 (match_operand:SF 2 "gpc_reg_operand" "f")
4941 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4942 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4944 [(set_attr "type" "fp")])
4946 (define_insn "fseldfsf4"
4947 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4948 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4950 (match_operand:SF 2 "gpc_reg_operand" "f")
4951 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4952 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4954 [(set_attr "type" "fp")])
4956 (define_insn "negdf2"
4957 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4958 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4961 [(set_attr "type" "fp")])
4963 (define_insn "absdf2"
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4965 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4968 [(set_attr "type" "fp")])
4971 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4972 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4975 [(set_attr "type" "fp")])
4977 (define_insn "adddf3"
4978 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4979 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4980 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4982 "{fa|fadd} %0,%1,%2"
4983 [(set_attr "type" "fp")])
4985 (define_insn "subdf3"
4986 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4987 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4988 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4990 "{fs|fsub} %0,%1,%2"
4991 [(set_attr "type" "fp")])
4993 (define_insn "muldf3"
4994 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4995 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4996 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4998 "{fm|fmul} %0,%1,%2"
4999 [(set_attr "type" "dmul")])
5001 (define_insn "divdf3"
5002 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5003 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5004 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5006 "{fd|fdiv} %0,%1,%2"
5007 [(set_attr "type" "ddiv")])
5010 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5011 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5012 (match_operand:DF 2 "gpc_reg_operand" "f"))
5013 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5014 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5015 "{fma|fmadd} %0,%1,%2,%3"
5016 [(set_attr "type" "dmul")])
5019 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5020 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5021 (match_operand:DF 2 "gpc_reg_operand" "f"))
5022 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5023 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5024 "{fms|fmsub} %0,%1,%2,%3"
5025 [(set_attr "type" "dmul")])
5028 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5029 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5030 (match_operand:DF 2 "gpc_reg_operand" "f"))
5031 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5032 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5033 "{fnma|fnmadd} %0,%1,%2,%3"
5034 [(set_attr "type" "dmul")])
5037 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5038 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5039 (match_operand:DF 2 "gpc_reg_operand" "f"))
5040 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5041 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5042 "{fnms|fnmsub} %0,%1,%2,%3"
5043 [(set_attr "type" "dmul")])
5045 (define_insn "sqrtdf2"
5046 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5047 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5048 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
5050 [(set_attr "type" "dsqrt")])
5052 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5053 ;; fsel instruction and some auxiliary computations. Then we just have a
5054 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5057 (define_expand "maxdf3"
5059 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5060 (match_operand:DF 2 "gpc_reg_operand" "")))
5061 (set (match_operand:DF 0 "gpc_reg_operand" "")
5062 (if_then_else:DF (ge (match_dup 3)
5066 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5068 { operands[3] = gen_reg_rtx (DFmode); }")
5071 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5072 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
5073 (match_operand:DF 2 "gpc_reg_operand" "")))
5074 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
5075 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5077 (minus:DF (match_dup 1) (match_dup 2)))
5079 (if_then_else:DF (ge (match_dup 3)
5085 (define_expand "mindf3"
5087 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
5088 (match_operand:DF 1 "gpc_reg_operand" "")))
5089 (set (match_operand:DF 0 "gpc_reg_operand" "")
5090 (if_then_else:DF (ge (match_dup 3)
5094 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5096 { operands[3] = gen_reg_rtx (DFmode); }")
5099 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5100 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
5101 (match_operand:DF 2 "gpc_reg_operand" "")))
5102 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
5103 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5105 (minus:DF (match_dup 2) (match_dup 1)))
5107 (if_then_else:DF (ge (match_dup 3)
5113 (define_expand "movdfcc"
5114 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5115 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5116 (match_operand:DF 2 "gpc_reg_operand" "")
5117 (match_operand:DF 3 "gpc_reg_operand" "")))]
5118 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5122 enum rtx_code code = GET_CODE (operands[1]);
5123 if (! rs6000_compare_fp_p)
5127 case GE: case EQ: case NE:
5128 op0 = rs6000_compare_op0;
5129 op1 = rs6000_compare_op1;
5132 op0 = rs6000_compare_op1;
5133 op1 = rs6000_compare_op0;
5134 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
5137 op0 = rs6000_compare_op1;
5138 op1 = rs6000_compare_op0;
5141 op0 = rs6000_compare_op0;
5142 op1 = rs6000_compare_op1;
5143 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
5148 if (GET_MODE (rs6000_compare_op0) == DFmode)
5150 temp = gen_reg_rtx (DFmode);
5151 emit_insn (gen_subdf3 (temp, op0, op1));
5152 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
5155 emit_insn (gen_negdf2 (temp, temp));
5156 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
5158 else if (code == NE)
5160 emit_insn (gen_negdf2 (temp, temp));
5161 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
5166 temp = gen_reg_rtx (SFmode);
5167 emit_insn (gen_subsf3 (temp, op0, op1));
5168 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
5171 emit_insn (gen_negsf2 (temp, temp));
5172 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
5174 else if (code == NE)
5176 emit_insn (gen_negsf2 (temp, temp));
5177 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
5183 (define_insn "fseldfdf4"
5184 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5185 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5187 (match_operand:DF 2 "gpc_reg_operand" "f")
5188 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5189 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5191 [(set_attr "type" "fp")])
5193 (define_insn "fselsfdf4"
5194 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5195 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5197 (match_operand:DF 2 "gpc_reg_operand" "f")
5198 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5201 [(set_attr "type" "fp")])
5203 ;; Conversions to and from floating-point.
5205 ; For each of these conversions, there is a define_expand, a define_insn
5206 ; with a '#' template, and a define_split (with C code). The idea is
5207 ; to allow constant folding with the template of the define_insn,
5208 ; then to have the insns split later (between sched1 and final).
5210 (define_expand "floatsidf2"
5211 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5212 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5215 (clobber (match_dup 4))
5216 (clobber (match_dup 5))
5217 (clobber (match_dup 6))])]
5218 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5221 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5222 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
5223 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5224 operands[5] = gen_reg_rtx (DFmode);
5225 operands[6] = gen_reg_rtx (SImode);
5228 (define_insn "*floatsidf2_internal"
5229 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5230 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5231 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5232 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5233 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5234 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))
5235 (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))]
5236 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5238 [(set_attr "length" "24")])
5241 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5242 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5243 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5244 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5245 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5246 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5247 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5248 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5249 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5250 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5251 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5252 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5253 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5254 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5255 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5258 rtx lowword, highword;
5259 if (GET_CODE (operands[4]) != MEM)
5261 highword = XEXP (operands[4], 0);
5262 lowword = plus_constant (highword, 4);
5263 if (! WORDS_BIG_ENDIAN)
5266 tmp = highword; highword = lowword; lowword = tmp;
5269 emit_insn (gen_xorsi3 (operands[6], operands[1],
5270 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5271 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5272 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5273 emit_move_insn (operands[5], operands[4]);
5274 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5278 (define_expand "floatunssidf2"
5279 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5280 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5283 (clobber (match_dup 4))
5284 (clobber (match_dup 5))])]
5285 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5288 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5289 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
5290 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5291 operands[5] = gen_reg_rtx (DFmode);
5294 (define_insn "*floatunssidf2_internal"
5295 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5296 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5297 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5298 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5299 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5300 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))]
5301 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5303 [(set_attr "length" "20")])
5306 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5307 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5308 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5309 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5310 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5311 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5312 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5313 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5314 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5315 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5316 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5317 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5318 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5321 rtx lowword, highword;
5322 if (GET_CODE (operands[4]) != MEM)
5324 highword = XEXP (operands[4], 0);
5325 lowword = plus_constant (highword, 4);
5326 if (! WORDS_BIG_ENDIAN)
5329 tmp = highword; highword = lowword; lowword = tmp;
5332 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5333 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5334 emit_move_insn (operands[5], operands[4]);
5335 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5339 (define_expand "fix_truncdfsi2"
5340 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5341 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5342 (clobber (match_dup 2))
5343 (clobber (match_dup 3))])]
5344 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5347 operands[2] = gen_reg_rtx (DImode);
5348 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5351 (define_insn "*fix_truncdfsi2_internal"
5352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5353 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5354 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5355 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5356 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5358 [(set_attr "length" "16")])
5361 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5362 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5363 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5364 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5365 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5366 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5367 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5368 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5369 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5373 if (GET_CODE (operands[3]) != MEM)
5375 lowword = XEXP (operands[3], 0);
5376 if (WORDS_BIG_ENDIAN)
5377 lowword = plus_constant (lowword, 4);
5379 emit_insn (gen_fctiwz (operands[2], operands[1]));
5380 emit_move_insn (operands[3], operands[2]);
5381 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5385 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5386 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5387 ; because the first makes it clear that operand 0 is not live
5388 ; before the instruction.
5389 (define_insn "fctiwz"
5390 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5391 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
5392 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5393 "{fcirz|fctiwz} %0,%1"
5394 [(set_attr "type" "fp")])
5396 (define_insn "floatdidf2"
5397 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5398 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
5399 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5401 [(set_attr "type" "fp")])
5403 (define_insn "fix_truncdfdi2"
5404 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5405 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5406 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5408 [(set_attr "type" "fp")])
5410 ;; Define the DImode operations that can be done in a small number
5411 ;; of instructions. The & constraints are to prevent the register
5412 ;; allocator from allocating registers that overlap with the inputs
5413 ;; (for example, having an input in 7,8 and an output in 6,7). We
5414 ;; also allow for the output being the same as one of the inputs.
5416 (define_insn "*adddi3_noppc64"
5417 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5418 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5419 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5420 "! TARGET_POWERPC64"
5423 if (WORDS_BIG_ENDIAN)
5424 return (GET_CODE (operands[2])) != CONST_INT
5425 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5426 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5428 return (GET_CODE (operands[2])) != CONST_INT
5429 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5430 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5432 [(set_attr "length" "8")])
5434 (define_insn "*subdi3_noppc64"
5435 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5436 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5437 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5438 "! TARGET_POWERPC64"
5441 if (WORDS_BIG_ENDIAN)
5442 return (GET_CODE (operands[1]) != CONST_INT)
5443 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5444 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5446 return (GET_CODE (operands[1]) != CONST_INT)
5447 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5448 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5450 [(set_attr "length" "8")])
5452 (define_insn "*negdi2_noppc64"
5453 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5454 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5455 "! TARGET_POWERPC64"
5458 return (WORDS_BIG_ENDIAN)
5459 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5460 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5462 [(set_attr "length" "8")])
5464 (define_expand "mulsidi3"
5465 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5466 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5467 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5468 "! TARGET_POWERPC64"
5471 if (! TARGET_POWER && ! TARGET_POWERPC)
5473 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5474 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5475 emit_insn (gen_mull_call ());
5476 if (WORDS_BIG_ENDIAN)
5477 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5480 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5481 gen_rtx_REG (SImode, 3));
5482 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5483 gen_rtx_REG (SImode, 4));
5487 else if (TARGET_POWER)
5489 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5494 (define_insn "mulsidi3_mq"
5495 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5496 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5497 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5498 (clobber (match_scratch:SI 3 "=q"))]
5500 "mul %0,%1,%2\;mfmq %L0"
5501 [(set_attr "type" "imul")
5502 (set_attr "length" "8")])
5504 (define_insn "*mulsidi3_no_mq"
5505 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5506 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5507 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5508 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5511 return (WORDS_BIG_ENDIAN)
5512 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5513 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5515 [(set_attr "type" "imul")
5516 (set_attr "length" "8")])
5519 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5520 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5521 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5522 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5525 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5526 (sign_extend:DI (match_dup 2)))
5529 (mult:SI (match_dup 1)
5533 int endian = (WORDS_BIG_ENDIAN == 0);
5534 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5535 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5538 (define_expand "umulsidi3"
5539 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5540 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5541 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5542 "TARGET_POWERPC && ! TARGET_POWERPC64"
5547 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5552 (define_insn "umulsidi3_mq"
5553 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5554 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5555 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5556 (clobber (match_scratch:SI 3 "=q"))]
5557 "TARGET_POWERPC && TARGET_POWER"
5560 return (WORDS_BIG_ENDIAN)
5561 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5562 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5564 [(set_attr "type" "imul")
5565 (set_attr "length" "8")])
5567 (define_insn "*umulsidi3_no_mq"
5568 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5569 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5570 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5571 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5574 return (WORDS_BIG_ENDIAN)
5575 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5576 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5578 [(set_attr "type" "imul")
5579 (set_attr "length" "8")])
5582 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5583 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5584 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5585 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5588 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5589 (zero_extend:DI (match_dup 2)))
5592 (mult:SI (match_dup 1)
5596 int endian = (WORDS_BIG_ENDIAN == 0);
5597 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5598 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5601 (define_expand "smulsi3_highpart"
5602 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5604 (lshiftrt:DI (mult:DI (sign_extend:DI
5605 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5607 (match_operand:SI 2 "gpc_reg_operand" "r")))
5612 if (! TARGET_POWER && ! TARGET_POWERPC)
5614 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5615 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5616 emit_insn (gen_mulh_call ());
5617 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5620 else if (TARGET_POWER)
5622 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5627 (define_insn "smulsi3_highpart_mq"
5628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5630 (lshiftrt:DI (mult:DI (sign_extend:DI
5631 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5633 (match_operand:SI 2 "gpc_reg_operand" "r")))
5635 (clobber (match_scratch:SI 3 "=q"))]
5638 [(set_attr "type" "imul")])
5640 (define_insn "*smulsi3_highpart_no_mq"
5641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5643 (lshiftrt:DI (mult:DI (sign_extend:DI
5644 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5646 (match_operand:SI 2 "gpc_reg_operand" "r")))
5648 "TARGET_POWERPC && ! TARGET_POWER"
5650 [(set_attr "type" "imul")])
5652 (define_expand "umulsi3_highpart"
5653 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5655 (lshiftrt:DI (mult:DI (zero_extend:DI
5656 (match_operand:SI 1 "gpc_reg_operand" ""))
5658 (match_operand:SI 2 "gpc_reg_operand" "")))
5665 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5670 (define_insn "umulsi3_highpart_mq"
5671 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5673 (lshiftrt:DI (mult:DI (zero_extend:DI
5674 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5676 (match_operand:SI 2 "gpc_reg_operand" "r")))
5678 (clobber (match_scratch:SI 3 "=q"))]
5679 "TARGET_POWERPC && TARGET_POWER"
5681 [(set_attr "type" "imul")])
5683 (define_insn "*umulsi3_highpart_no_mq"
5684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5686 (lshiftrt:DI (mult:DI (zero_extend:DI
5687 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5689 (match_operand:SI 2 "gpc_reg_operand" "r")))
5691 "TARGET_POWERPC && ! TARGET_POWER"
5693 [(set_attr "type" "imul")])
5695 ;; If operands 0 and 2 are in the same register, we have a problem. But
5696 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5697 ;; why we have the strange constraints below.
5698 (define_insn "ashldi3_power"
5699 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5700 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5701 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5702 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5705 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5706 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5707 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5708 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5709 [(set_attr "length" "8")])
5711 (define_insn "lshrdi3_power"
5712 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5713 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5714 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5715 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5718 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5719 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5720 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5721 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5722 [(set_attr "length" "8")])
5724 ;; Shift by a variable amount is too complex to be worth open-coding. We
5725 ;; just handle shifts by constants.
5726 (define_insn "ashrdi3_power"
5727 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5728 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5729 (match_operand:SI 2 "const_int_operand" "M,i")))
5730 (clobber (match_scratch:SI 3 "=X,q"))]
5733 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5734 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5735 [(set_attr "length" "8")])
5737 ;; PowerPC64 DImode operations.
5739 (define_expand "adddi3"
5740 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5741 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5742 (match_operand:DI 2 "reg_or_arith_cint_operand" "")))]
5746 if (! TARGET_POWERPC64)
5748 if (non_short_cint_operand (operands[2], DImode))
5752 if (GET_CODE (operands[2]) == CONST_INT
5753 && ! add_operand (operands[2], DImode))
5755 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5756 ? operands[0] : gen_reg_rtx (DImode));
5758 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
5759 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
5762 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
5764 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high)));
5765 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5770 ;; Discourage ai/addic because of carry but provide it in an alternative
5771 ;; allowing register zero as source.
5773 (define_insn "*adddi3_internal1"
5774 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5775 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5776 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5784 (define_insn "*adddi3_internal2"
5785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5786 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5787 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5789 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5796 [(set_attr "type" "compare")
5797 (set_attr "length" "4,4,8,8")])
5800 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5801 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5802 (match_operand:DI 2 "reg_or_short_operand" ""))
5804 (clobber (match_scratch:DI 3 ""))]
5805 "TARGET_POWERPC64 && reload_completed"
5807 (plus:DI (match_dup 1) (match_dup 2)))
5809 (compare:CC (match_dup 3)
5813 (define_insn "*adddi3_internal3"
5814 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5815 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5816 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5818 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5819 (plus:DI (match_dup 1) (match_dup 2)))]
5826 [(set_attr "type" "compare")
5827 (set_attr "length" "4,4,8,8")])
5830 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5831 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5832 (match_operand:DI 2 "reg_or_short_operand" ""))
5834 (set (match_operand:DI 0 "gpc_reg_operand" "")
5835 (plus:DI (match_dup 1) (match_dup 2)))]
5836 "TARGET_POWERPC64 && reload_completed"
5838 (plus:DI (match_dup 1) (match_dup 2)))
5840 (compare:CC (match_dup 0)
5844 ;; Split an add that we can't do in one insn into two insns, each of which
5845 ;; does one 16-bit part. This is used by combine. Note that the low-order
5846 ;; add should be last in case the result gets used in an address.
5849 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5850 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5851 (match_operand:DI 2 "non_add_cint_operand" "")))]
5853 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5854 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5857 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
5858 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
5861 high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
5863 operands[3] = GEN_INT (high);
5864 operands[4] = GEN_INT (low);
5867 (define_insn "one_cmpldi2"
5868 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5869 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5874 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5875 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5877 (clobber (match_scratch:DI 2 "=r,r"))]
5882 [(set_attr "type" "compare")
5883 (set_attr "length" "4,8")])
5886 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5887 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5889 (clobber (match_scratch:DI 2 ""))]
5890 "TARGET_POWERPC64 && reload_completed"
5892 (not:DI (match_dup 1)))
5894 (compare:CC (match_dup 2)
5899 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5900 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5902 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5903 (not:DI (match_dup 1)))]
5908 [(set_attr "type" "compare")
5909 (set_attr "length" "4,8")])
5912 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5913 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5915 (set (match_operand:DI 0 "gpc_reg_operand" "")
5916 (not:DI (match_dup 1)))]
5917 "TARGET_POWERPC64 && reload_completed"
5919 (not:DI (match_dup 1)))
5921 (compare:CC (match_dup 0)
5926 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5927 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5928 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5936 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5937 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5939 (clobber (match_scratch:DI 3 "=r,r"))]
5944 [(set_attr "type" "compare")
5945 (set_attr "length" "4,8")])
5948 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5949 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5950 (match_operand:DI 2 "gpc_reg_operand" ""))
5952 (clobber (match_scratch:DI 3 ""))]
5953 "TARGET_POWERPC64 && reload_completed"
5955 (minus:DI (match_dup 1) (match_dup 2)))
5957 (compare:CC (match_dup 3)
5962 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5963 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5964 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5966 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5967 (minus:DI (match_dup 1) (match_dup 2)))]
5972 [(set_attr "type" "compare")
5973 (set_attr "length" "4,8")])
5976 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5977 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5978 (match_operand:DI 2 "gpc_reg_operand" ""))
5980 (set (match_operand:DI 0 "gpc_reg_operand" "")
5981 (minus:DI (match_dup 1) (match_dup 2)))]
5982 "TARGET_POWERPC64 && reload_completed"
5984 (minus:DI (match_dup 1) (match_dup 2)))
5986 (compare:CC (match_dup 0)
5990 (define_expand "subdi3"
5991 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5992 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5993 (match_operand:DI 2 "reg_or_arith_cint_operand" "")))]
5997 if (GET_CODE (operands[2]) == CONST_INT)
5999 emit_insn (gen_adddi3 (operands[0], operands[1],
6000 negate_rtx (DImode, operands[2])));
6005 (define_insn "absdi2"
6006 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6007 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6008 (clobber (match_scratch:DI 2 "=&r,&r"))]
6010 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
6011 [(set_attr "length" "12")])
6014 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6015 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6016 (clobber (match_scratch:DI 2 "=&r,&r"))]
6017 "TARGET_POWERPC64 && reload_completed"
6018 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6019 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6020 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6023 (define_insn "*nabsdi2"
6024 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6025 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6026 (clobber (match_scratch:DI 2 "=&r,&r"))]
6028 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
6029 [(set_attr "length" "12")])
6032 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6033 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6034 (clobber (match_scratch:DI 2 "=&r,&r"))]
6035 "TARGET_POWERPC64 && reload_completed"
6036 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6037 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6038 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6041 (define_expand "negdi2"
6042 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6043 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6049 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6054 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6055 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6057 (clobber (match_scratch:DI 2 "=r,r"))]
6062 [(set_attr "type" "compare")
6063 (set_attr "length" "4,8")])
6066 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6067 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6069 (clobber (match_scratch:DI 2 ""))]
6070 "TARGET_POWERPC64 && reload_completed"
6072 (neg:DI (match_dup 1)))
6074 (compare:CC (match_dup 2)
6079 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6080 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6082 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6083 (neg:DI (match_dup 1)))]
6088 [(set_attr "type" "compare")
6089 (set_attr "length" "4,8")])
6092 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6093 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6095 (set (match_operand:DI 0 "gpc_reg_operand" "")
6096 (neg:DI (match_dup 1)))]
6097 "TARGET_POWERPC64 && reload_completed"
6099 (neg:DI (match_dup 1)))
6101 (compare:CC (match_dup 0)
6105 (define_insn "ffsdi2"
6106 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6107 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6109 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
6110 [(set_attr "length" "16")])
6112 (define_insn "muldi3"
6113 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6114 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6115 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6118 [(set_attr "type" "lmul")])
6120 (define_insn "smuldi3_highpart"
6121 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6123 (lshiftrt:TI (mult:TI (sign_extend:TI
6124 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6126 (match_operand:DI 2 "gpc_reg_operand" "r")))
6130 [(set_attr "type" "lmul")])
6132 (define_insn "umuldi3_highpart"
6133 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6135 (lshiftrt:TI (mult:TI (zero_extend:TI
6136 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6138 (match_operand:DI 2 "gpc_reg_operand" "r")))
6142 [(set_attr "type" "lmul")])
6144 (define_expand "divdi3"
6145 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6146 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6147 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6151 if (GET_CODE (operands[2]) == CONST_INT
6152 && exact_log2 (INTVAL (operands[2])) >= 0)
6155 operands[2] = force_reg (DImode, operands[2]);
6158 (define_expand "moddi3"
6159 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6160 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6161 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6165 int i = exact_log2 (INTVAL (operands[2]));
6169 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
6172 temp1 = gen_reg_rtx (DImode);
6173 temp2 = gen_reg_rtx (DImode);
6175 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6176 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6177 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6182 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6183 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6184 (match_operand:DI 2 "const_int_operand" "N")))]
6185 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
6186 "sradi %0,%1,%p2\;addze %0,%0"
6187 [(set_attr "length" "8")])
6190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6191 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6192 (match_operand:DI 2 "const_int_operand" "N,N"))
6194 (clobber (match_scratch:DI 3 "=r,r"))]
6195 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
6197 sradi %3,%1,%p2\;addze. %3,%3
6199 [(set_attr "type" "compare")
6200 (set_attr "length" "8,12")])
6203 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6204 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6205 (match_operand:DI 2 "const_int_operand" ""))
6207 (clobber (match_scratch:DI 3 ""))]
6208 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
6210 (div:DI (match_dup 1) (match_dup 2)))
6212 (compare:CC (match_dup 3)
6217 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6218 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6219 (match_operand:DI 2 "const_int_operand" "N,N"))
6221 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6222 (div:DI (match_dup 1) (match_dup 2)))]
6223 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
6225 sradi %0,%1,%p2\;addze. %0,%0
6227 [(set_attr "type" "compare")
6228 (set_attr "length" "8,12")])
6231 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6232 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6233 (match_operand:DI 2 "const_int_operand" ""))
6235 (set (match_operand:DI 0 "gpc_reg_operand" "")
6236 (div:DI (match_dup 1) (match_dup 2)))]
6237 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed"
6239 (div:DI (match_dup 1) (match_dup 2)))
6241 (compare:CC (match_dup 0)
6246 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6247 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6248 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6251 [(set_attr "type" "ldiv")])
6253 (define_insn "udivdi3"
6254 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6255 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6256 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6259 [(set_attr "type" "ldiv")])
6261 (define_insn "rotldi3"
6262 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6263 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6264 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6266 "rld%I2cl %0,%1,%H2,0")
6268 (define_insn "*rotldi3_internal2"
6269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6270 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6271 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6273 (clobber (match_scratch:DI 3 "=r,r"))]
6276 rld%I2cl. %3,%1,%H2,0
6278 [(set_attr "type" "delayed_compare")
6279 (set_attr "length" "4,8")])
6282 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6283 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6284 (match_operand:DI 2 "reg_or_cint_operand" ""))
6286 (clobber (match_scratch:DI 3 ""))]
6287 "TARGET_POWERPC64 && reload_completed"
6289 (rotate:DI (match_dup 1) (match_dup 2)))
6291 (compare:CC (match_dup 3)
6295 (define_insn "*rotldi3_internal3"
6296 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6297 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6298 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6300 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6301 (rotate:DI (match_dup 1) (match_dup 2)))]
6304 rld%I2cl. %0,%1,%H2,0
6306 [(set_attr "type" "delayed_compare")
6307 (set_attr "length" "4,8")])
6310 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6311 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6312 (match_operand:DI 2 "reg_or_cint_operand" ""))
6314 (set (match_operand:DI 0 "gpc_reg_operand" "")
6315 (rotate:DI (match_dup 1) (match_dup 2)))]
6316 "TARGET_POWERPC64 && reload_completed"
6318 (rotate:DI (match_dup 1) (match_dup 2)))
6320 (compare:CC (match_dup 0)
6324 (define_insn "*rotldi3_internal4"
6325 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6326 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6327 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6328 (match_operand:DI 3 "mask64_operand" "S")))]
6330 "rld%I2c%B3 %0,%1,%H2,%S3")
6332 (define_insn "*rotldi3_internal5"
6333 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6335 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6336 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6337 (match_operand:DI 3 "mask64_operand" "S,S"))
6339 (clobber (match_scratch:DI 4 "=r,r"))]
6342 rld%I2c%B3. %4,%1,%H2,%S3
6344 [(set_attr "type" "delayed_compare")
6345 (set_attr "length" "4,8")])
6348 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6350 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6351 (match_operand:DI 2 "reg_or_cint_operand" ""))
6352 (match_operand:DI 3 "mask64_operand" ""))
6354 (clobber (match_scratch:DI 4 ""))]
6355 "TARGET_POWERPC64 && reload_completed"
6357 (and:DI (rotate:DI (match_dup 1)
6361 (compare:CC (match_dup 4)
6365 (define_insn "*rotldi3_internal6"
6366 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6368 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6369 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6370 (match_operand:DI 3 "mask64_operand" "S,S"))
6372 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6373 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6376 rld%I2c%B3. %0,%1,%H2,%S3
6378 [(set_attr "type" "delayed_compare")
6379 (set_attr "length" "4,8")])
6382 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6384 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6385 (match_operand:DI 2 "reg_or_cint_operand" ""))
6386 (match_operand:DI 3 "mask64_operand" ""))
6388 (set (match_operand:DI 0 "gpc_reg_operand" "")
6389 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6390 "TARGET_POWERPC64 && reload_completed"
6392 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6394 (compare:CC (match_dup 0)
6398 (define_insn "*rotldi3_internal7"
6399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6402 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6403 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6405 "rld%I2cl %0,%1,%H2,56")
6407 (define_insn "*rotldi3_internal8"
6408 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6409 (compare:CC (zero_extend:DI
6411 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6412 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6414 (clobber (match_scratch:DI 3 "=r,r"))]
6417 rld%I2cl. %3,%1,%H2,56
6419 [(set_attr "type" "delayed_compare")
6420 (set_attr "length" "4,8")])
6423 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6424 (compare:CC (zero_extend:DI
6426 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6427 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6429 (clobber (match_scratch:DI 3 ""))]
6430 "TARGET_POWERPC64 && reload_completed"
6432 (zero_extend:DI (subreg:QI
6433 (rotate:DI (match_dup 1)
6436 (compare:CC (match_dup 3)
6440 (define_insn "*rotldi3_internal9"
6441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6442 (compare:CC (zero_extend:DI
6444 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6445 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6447 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6448 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6451 rld%I2cl. %0,%1,%H2,56
6453 [(set_attr "type" "delayed_compare")
6454 (set_attr "length" "4,8")])
6457 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6458 (compare:CC (zero_extend:DI
6460 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6461 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6463 (set (match_operand:DI 0 "gpc_reg_operand" "")
6464 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6465 "TARGET_POWERPC64 && reload_completed"
6467 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6469 (compare:CC (match_dup 0)
6473 (define_insn "*rotldi3_internal10"
6474 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6477 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6478 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6480 "rld%I2cl %0,%1,%H2,48")
6482 (define_insn "*rotldi3_internal11"
6483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6484 (compare:CC (zero_extend:DI
6486 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6487 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6489 (clobber (match_scratch:DI 3 "=r,r"))]
6492 rld%I2cl. %3,%1,%H2,48
6494 [(set_attr "type" "delayed_compare")
6495 (set_attr "length" "4,8")])
6498 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6499 (compare:CC (zero_extend:DI
6501 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6502 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6504 (clobber (match_scratch:DI 3 ""))]
6505 "TARGET_POWERPC64 && reload_completed"
6507 (zero_extend:DI (subreg:HI
6508 (rotate:DI (match_dup 1)
6511 (compare:CC (match_dup 3)
6515 (define_insn "*rotldi3_internal12"
6516 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6517 (compare:CC (zero_extend:DI
6519 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6520 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6522 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6523 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6526 rld%I2cl. %0,%1,%H2,48
6528 [(set_attr "type" "delayed_compare")
6529 (set_attr "length" "4,8")])
6532 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6533 (compare:CC (zero_extend:DI
6535 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6536 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6538 (set (match_operand:DI 0 "gpc_reg_operand" "")
6539 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6540 "TARGET_POWERPC64 && reload_completed"
6542 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6544 (compare:CC (match_dup 0)
6548 (define_insn "*rotldi3_internal13"
6549 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6552 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6553 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6555 "rld%I2cl %0,%1,%H2,32")
6557 (define_insn "*rotldi3_internal14"
6558 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6559 (compare:CC (zero_extend:DI
6561 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6562 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6564 (clobber (match_scratch:DI 3 "=r,r"))]
6567 rld%I2cl. %3,%1,%H2,32
6569 [(set_attr "type" "delayed_compare")
6570 (set_attr "length" "4,8")])
6573 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6574 (compare:CC (zero_extend:DI
6576 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6577 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6579 (clobber (match_scratch:DI 3 ""))]
6580 "TARGET_POWERPC64 && reload_completed"
6582 (zero_extend:DI (subreg:SI
6583 (rotate:DI (match_dup 1)
6586 (compare:CC (match_dup 3)
6590 (define_insn "*rotldi3_internal15"
6591 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6592 (compare:CC (zero_extend:DI
6594 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6595 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6597 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6598 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6601 rld%I2cl. %0,%1,%H2,32
6603 [(set_attr "type" "delayed_compare")
6604 (set_attr "length" "4,8")])
6607 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6608 (compare:CC (zero_extend:DI
6610 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6611 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6613 (set (match_operand:DI 0 "gpc_reg_operand" "")
6614 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6615 "TARGET_POWERPC64 && reload_completed"
6617 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6619 (compare:CC (match_dup 0)
6623 (define_expand "ashldi3"
6624 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6625 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6626 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6627 "TARGET_POWERPC64 || TARGET_POWER"
6630 if (TARGET_POWERPC64)
6632 else if (TARGET_POWER)
6634 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6641 (define_insn "*ashldi3_internal1"
6642 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6643 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6644 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6647 [(set_attr "length" "8")])
6649 (define_insn "*ashldi3_internal2"
6650 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6651 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6652 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6654 (clobber (match_scratch:DI 3 "=r,r"))]
6659 [(set_attr "type" "delayed_compare")
6660 (set_attr "length" "4,8")])
6663 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6664 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6665 (match_operand:SI 2 "reg_or_cint_operand" ""))
6667 (clobber (match_scratch:DI 3 ""))]
6668 "TARGET_POWERPC64 && reload_completed"
6670 (ashift:DI (match_dup 1) (match_dup 2)))
6672 (compare:CC (match_dup 3)
6676 (define_insn "*ashldi3_internal3"
6677 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6678 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6679 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6681 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6682 (ashift:DI (match_dup 1) (match_dup 2)))]
6687 [(set_attr "type" "delayed_compare")
6688 (set_attr "length" "4,8")])
6691 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6692 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6693 (match_operand:SI 2 "reg_or_cint_operand" ""))
6695 (set (match_operand:DI 0 "gpc_reg_operand" "")
6696 (ashift:DI (match_dup 1) (match_dup 2)))]
6697 "TARGET_POWERPC64 && reload_completed"
6699 (ashift:DI (match_dup 1) (match_dup 2)))
6701 (compare:CC (match_dup 0)
6705 (define_insn "*ashldi3_internal4"
6706 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6707 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6708 (match_operand:SI 2 "const_int_operand" "i"))
6709 (match_operand:DI 3 "rldic_operand" "n")))]
6710 "includes_lshift64_p (operands[2], operands[3])"
6711 "rldic %0,%1,%H2,%W3")
6713 (define_insn "ashldi3_internal5"
6714 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6716 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6717 (match_operand:SI 2 "const_int_operand" "i,i"))
6718 (match_operand:DI 3 "rldic_operand" "n,n"))
6720 (clobber (match_scratch:DI 4 "=r,r"))]
6721 "includes_lshift64_p (operands[2], operands[3])"
6723 rldic. %4,%1,%H2,%W3
6725 [(set_attr "type" "delayed_compare")
6726 (set_attr "length" "4,8")])
6729 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6731 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6732 (match_operand:SI 2 "const_int_operand" ""))
6733 (match_operand:DI 3 "rldic_operand" ""))
6735 (clobber (match_scratch:DI 4 ""))]
6736 "includes_lshift64_p (operands[2], operands[3]) && reload_completed"
6738 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6741 (compare:CC (match_dup 4)
6745 (define_insn "*ashldi3_internal6"
6746 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6748 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6749 (match_operand:SI 2 "const_int_operand" "i,i"))
6750 (match_operand:DI 3 "rldic_operand" "n,n"))
6752 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6753 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6754 "includes_lshift64_p (operands[2], operands[3])"
6756 rldic. %0,%1,%H2,%W3
6758 [(set_attr "type" "delayed_compare")
6759 (set_attr "length" "4,8")])
6762 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6764 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6765 (match_operand:SI 2 "const_int_operand" ""))
6766 (match_operand:DI 3 "rldic_operand" ""))
6768 (set (match_operand:DI 0 "gpc_reg_operand" "")
6769 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6770 "includes_lshift64_p (operands[2], operands[3]) && reload_completed"
6772 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6775 (compare:CC (match_dup 0)
6779 (define_expand "lshrdi3"
6780 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6781 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6782 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6783 "TARGET_POWERPC64 || TARGET_POWER"
6786 if (TARGET_POWERPC64)
6788 else if (TARGET_POWER)
6790 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6797 (define_insn "*lshrdi3_internal1"
6798 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6799 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6800 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6804 (define_insn "*lshrdi3_internal2"
6805 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6806 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6807 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6809 (clobber (match_scratch:DI 3 "=r,r"))]
6814 [(set_attr "type" "delayed_compare")
6815 (set_attr "length" "4,8")])
6818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6819 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6820 (match_operand:SI 2 "reg_or_cint_operand" ""))
6822 (clobber (match_scratch:DI 3 ""))]
6823 "TARGET_POWERPC64 && reload_completed"
6825 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6827 (compare:CC (match_dup 3)
6831 (define_insn "*lshrdi3_internal3"
6832 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6833 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6834 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6836 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6837 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6842 [(set_attr "type" "delayed_compare")
6843 (set_attr "length" "4,8")])
6846 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6847 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6848 (match_operand:SI 2 "reg_or_cint_operand" ""))
6850 (set (match_operand:DI 0 "gpc_reg_operand" "")
6851 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6852 "TARGET_POWERPC64 && reload_completed"
6854 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6856 (compare:CC (match_dup 0)
6860 (define_expand "ashrdi3"
6861 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6862 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6863 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6864 "TARGET_POWERPC64 || TARGET_POWER"
6867 if (TARGET_POWERPC64)
6869 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6871 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6878 (define_insn "*ashrdi3_internal1"
6879 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6880 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6881 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6883 "srad%I2 %0,%1,%H2")
6885 (define_insn "*ashrdi3_internal2"
6886 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6887 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6888 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6890 (clobber (match_scratch:DI 3 "=r,r"))]
6895 [(set_attr "type" "delayed_compare")
6896 (set_attr "length" "4,8")])
6899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6900 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6901 (match_operand:SI 2 "reg_or_cint_operand" ""))
6903 (clobber (match_scratch:DI 3 ""))]
6904 "TARGET_POWERPC64 && reload_completed"
6906 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6908 (compare:CC (match_dup 3)
6912 (define_insn "*ashrdi3_internal3"
6913 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6914 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6915 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6917 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6918 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6923 [(set_attr "type" "delayed_compare")
6924 (set_attr "length" "4,8")])
6927 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6928 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6929 (match_operand:SI 2 "reg_or_cint_operand" ""))
6931 (set (match_operand:DI 0 "gpc_reg_operand" "")
6932 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6933 "TARGET_POWERPC64 && reload_completed"
6935 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6937 (compare:CC (match_dup 0)
6941 (define_insn "anddi3"
6942 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6943 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
6944 (match_operand:DI 2 "and64_operand" "?r,S,K,J")))
6945 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
6949 rldic%B2 %0,%1,0,%S2
6953 (define_insn "*anddi3_internal2"
6954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
6955 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,")
6956 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
6958 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r"))
6959 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
6963 rldic%B2. %3,%1,0,%S2
6970 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
6971 (set_attr "length" "4,4,4,4,8,8,8,8")])
6974 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6975 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6976 (match_operand:DI 2 "and64_operand" ""))
6978 (clobber (match_scratch:DI 3 ""))
6979 (clobber (match_scratch:CC 4 ""))]
6980 "TARGET_POWERPC64 && reload_completed"
6981 [(parallel [(set (match_dup 3)
6982 (and:DI (match_dup 1)
6984 (clobber (match_dup 4))])
6986 (compare:CC (match_dup 3)
6990 (define_insn "*anddi3_internal3"
6991 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
6992 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
6993 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
6995 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
6996 (and:DI (match_dup 1) (match_dup 2)))
6997 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
7001 rldic%B2. %0,%1,0,%S2
7008 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
7009 (set_attr "length" "4,4,4,4,8,8,8,8")])
7012 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7013 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7014 (match_operand:DI 2 "and64_operand" ""))
7016 (set (match_operand:DI 0 "gpc_reg_operand" "")
7017 (and:DI (match_dup 1) (match_dup 2)))
7018 (clobber (match_scratch:CC 4 ""))]
7019 "TARGET_POWERPC64 && reload_completed"
7020 [(parallel [(set (match_dup 0)
7021 (and:DI (match_dup 1) (match_dup 2)))
7022 (clobber (match_dup 4))])
7024 (compare:CC (match_dup 0)
7028 (define_expand "iordi3"
7029 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7030 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7031 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7035 if (non_logical_cint_operand (operands[2], DImode))
7037 HOST_WIDE_INT value;
7038 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7039 ? operands[0] : gen_reg_rtx (DImode));
7041 if (GET_CODE (operands[2]) == CONST_INT)
7043 value = INTVAL (operands[2]);
7044 emit_insn (gen_iordi3 (tmp, operands[1],
7045 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7049 value = CONST_DOUBLE_LOW (operands[2]);
7050 emit_insn (gen_iordi3 (tmp, operands[1],
7051 immed_double_const (value
7052 & (~ (HOST_WIDE_INT) 0xffff),
7056 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7061 (define_expand "xordi3"
7062 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7063 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7064 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7068 if (non_logical_cint_operand (operands[2], DImode))
7070 HOST_WIDE_INT value;
7071 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7072 ? operands[0] : gen_reg_rtx (DImode));
7074 if (GET_CODE (operands[2]) == CONST_INT)
7076 value = INTVAL (operands[2]);
7077 emit_insn (gen_xordi3 (tmp, operands[1],
7078 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7082 value = CONST_DOUBLE_LOW (operands[2]);
7083 emit_insn (gen_xordi3 (tmp, operands[1],
7084 immed_double_const (value
7085 & (~ (HOST_WIDE_INT) 0xffff),
7089 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7094 (define_insn "*booldi3_internal1"
7095 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7096 (match_operator:DI 3 "boolean_or_operator"
7097 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7098 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7105 (define_insn "*booldi3_internal2"
7106 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7107 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7108 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7109 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7111 (clobber (match_scratch:DI 3 "=r,r"))]
7116 [(set_attr "type" "compare")
7117 (set_attr "length" "4,8")])
7120 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7121 (compare:CC (match_operator:DI 4 "boolean_operator"
7122 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7123 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7125 (clobber (match_scratch:DI 3 ""))]
7126 "TARGET_POWERPC64 && reload_completed"
7127 [(set (match_dup 3) (match_dup 4))
7129 (compare:CC (match_dup 3)
7133 (define_insn "*booldi3_internal3"
7134 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7135 (compare:CC (match_operator:DI 4 "boolean_operator"
7136 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7137 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7139 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7145 [(set_attr "type" "compare")
7146 (set_attr "length" "4,8")])
7149 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7150 (compare:CC (match_operator:DI 4 "boolean_operator"
7151 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7152 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7154 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7156 "TARGET_POWERPC64 && reload_completed"
7157 [(set (match_dup 0) (match_dup 4))
7159 (compare:CC (match_dup 0)
7163 ;; Split an logical operation that we can't do in one insn into two insns,
7164 ;; each of which does one 16-bit part. This is used by combine.
7167 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7168 (match_operator:DI 3 "boolean_or_operator"
7169 [(match_operand:DI 1 "gpc_reg_operand" "")
7170 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7172 [(set (match_dup 0) (match_dup 4))
7173 (set (match_dup 0) (match_dup 5))]
7178 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7180 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7181 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7183 i4 = GEN_INT (value & 0xffff);
7187 i3 = GEN_INT (INTVAL (operands[2])
7188 & (~ (HOST_WIDE_INT) 0xffff));
7189 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7191 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7193 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7197 (define_insn "*boolcdi3_internal1"
7198 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7199 (match_operator:DI 3 "boolean_operator"
7200 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7201 (match_operand:DI 2 "logical_operand" "r")]))]
7205 (define_insn "*boolcdi3_internal2"
7206 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7207 (compare:CC (match_operator:DI 4 "boolean_operator"
7208 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7209 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7211 (clobber (match_scratch:DI 3 "=r,r"))]
7216 [(set_attr "type" "compare")
7217 (set_attr "length" "4,8")])
7220 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7221 (compare:CC (match_operator:DI 4 "boolean_operator"
7222 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7223 (match_operand:DI 2 "gpc_reg_operand" "r")])
7225 (clobber (match_scratch:DI 3 ""))]
7226 "TARGET_POWERPC64 && reload_completed"
7227 [(set (match_dup 3) (match_dup 4))
7229 (compare:CC (match_dup 3)
7233 (define_insn "*boolcdi3_internal3"
7234 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7235 (compare:CC (match_operator:DI 4 "boolean_operator"
7236 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7237 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7239 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7245 [(set_attr "type" "compare")
7246 (set_attr "length" "4,8")])
7249 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7250 (compare:CC (match_operator:DI 4 "boolean_operator"
7251 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7252 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7254 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7256 "TARGET_POWERPC64 && reload_completed"
7257 [(set (match_dup 0) (match_dup 4))
7259 (compare:CC (match_dup 0)
7263 (define_insn "*boolccdi3_internal1"
7264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7265 (match_operator:DI 3 "boolean_operator"
7266 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7267 (not:DI (match_operand:DI 2 "logical_operand" "r"))]))]
7271 (define_insn "*boolccdi3_internal2"
7272 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7273 (compare:CC (match_operator:DI 4 "boolean_operator"
7274 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7275 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7277 (clobber (match_scratch:DI 3 "=r,r"))]
7282 [(set_attr "type" "compare")
7283 (set_attr "length" "4,8")])
7286 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7287 (compare:CC (match_operator:DI 4 "boolean_operator"
7288 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7289 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))])
7291 (clobber (match_scratch:DI 3 ""))]
7292 "TARGET_POWERPC64 && reload_completed"
7293 [(set (match_dup 3) (match_dup 4))
7295 (compare:CC (match_dup 3)
7299 (define_insn "*boolccdi3_internal3"
7300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7301 (compare:CC (match_operator:DI 4 "boolean_operator"
7302 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7303 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7305 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7311 [(set_attr "type" "compare")
7312 (set_attr "length" "4,8")])
7315 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7316 (compare:CC (match_operator:DI 4 "boolean_operator"
7317 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7318 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7320 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7322 "TARGET_POWERPC64 && reload_completed"
7323 [(set (match_dup 0) (match_dup 4))
7325 (compare:CC (match_dup 0)
7329 ;; Now define ways of moving data around.
7331 ;; Elf specific ways of loading addresses for non-PIC code.
7332 ;; The output of this could be r0, but we make a very strong
7333 ;; preference for a base register because it will usually
7335 (define_insn "elf_high"
7336 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7337 (high:SI (match_operand 1 "" "")))]
7338 "TARGET_ELF && ! TARGET_64BIT"
7339 "{liu|lis} %0,%1@ha")
7341 (define_insn "elf_low"
7342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7343 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7344 (match_operand 2 "" "")))]
7345 "TARGET_ELF && ! TARGET_64BIT"
7347 {cal|la} %0,%2@l(%1)
7348 {ai|addic} %0,%1,%K2")
7350 ;; Set up a register with a value from the GOT table
7352 (define_expand "movsi_got"
7353 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7354 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7356 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
7359 if (GET_CODE (operands[1]) == CONST)
7361 rtx offset = const0_rtx;
7362 HOST_WIDE_INT value;
7364 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7365 value = INTVAL (offset);
7368 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7369 emit_insn (gen_movsi_got (tmp, operands[1]));
7370 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7375 operands[2] = rs6000_got_register (operands[1]);
7378 (define_insn "*movsi_got_internal"
7379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7380 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7381 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
7382 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
7383 "{l|lwz} %0,%a1@got(%2)"
7384 [(set_attr "type" "load")])
7386 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7387 ;; didn't get allocated to a hard register.
7389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7390 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7391 (match_operand:SI 2 "memory_operand" "m")] 8))]
7392 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7394 && (reload_in_progress || reload_completed)"
7395 [(set (match_dup 0) (match_dup 2))
7396 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
7399 ;; For SI, we special-case integers that can't be loaded in one insn. We
7400 ;; do the load 16-bits at a time. We could do this by loading from memory,
7401 ;; and this is even supposed to be faster, but it is simpler not to get
7402 ;; integers in the TOC.
7403 (define_expand "movsi"
7404 [(set (match_operand:SI 0 "general_operand" "")
7405 (match_operand:SI 1 "any_operand" ""))]
7407 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7409 (define_insn "*movsi_internal1"
7410 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
7411 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
7412 "gpc_reg_operand (operands[0], SImode)
7413 || gpc_reg_operand (operands[1], SImode)"
7417 {l%U1%X1|lwz%U1%X1} %0,%1
7418 {st%U0%X0|stw%U0%X0} %1,%0
7427 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
7428 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
7430 ;; Split a load of a large constant into the appropriate two-insn
7434 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7435 (match_operand:SI 1 "const_int_operand" ""))]
7436 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7437 && (INTVAL (operands[1]) & 0xffff) != 0"
7441 (ior:SI (match_dup 0)
7445 operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff));
7446 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
7449 (define_insn "*movsi_internal2"
7450 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
7451 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
7453 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
7454 "! TARGET_POWERPC64"
7458 [(set_attr "type" "compare")
7459 (set_attr "length" "4,8")])
7462 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7463 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7465 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7466 "! TARGET_POWERPC64 && reload_completed"
7467 [(set (match_dup 0) (match_dup 1))
7469 (compare:CC (match_dup 0)
7473 (define_expand "movhi"
7474 [(set (match_operand:HI 0 "general_operand" "")
7475 (match_operand:HI 1 "any_operand" ""))]
7477 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7480 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7481 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7482 "gpc_reg_operand (operands[0], HImode)
7483 || gpc_reg_operand (operands[1], HImode)"
7493 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7495 (define_expand "movqi"
7496 [(set (match_operand:QI 0 "general_operand" "")
7497 (match_operand:QI 1 "any_operand" ""))]
7499 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7502 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7503 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7504 "gpc_reg_operand (operands[0], QImode)
7505 || gpc_reg_operand (operands[1], QImode)"
7515 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7517 ;; Here is how to move condition codes around. When we store CC data in
7518 ;; an integer register or memory, we store just the high-order 4 bits.
7519 ;; This lets us not shift in the most common case of CR0.
7520 (define_expand "movcc"
7521 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7522 (match_operand:CC 1 "nonimmediate_operand" ""))]
7527 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
7528 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
7529 "register_operand (operands[0], CCmode)
7530 || register_operand (operands[1], CCmode)"
7534 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7536 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7538 {l%U1%X1|lwz%U1%X1} %0,%1
7539 {st%U0%U1|stw%U0%U1} %1,%0"
7540 [(set_attr "type" "*,*,*,compare,*,*,load,store")
7541 (set_attr "length" "*,*,12,*,8,*,*,*")])
7543 ;; For floating-point, we normally deal with the floating-point registers
7544 ;; unless -msoft-float is used. The sole exception is that parameter passing
7545 ;; can produce floating-point values in fixed-point registers. Unless the
7546 ;; value is a simple constant or already in memory, we deal with this by
7547 ;; allocating memory and copying the value explicitly via that memory location.
7548 (define_expand "movsf"
7549 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7550 (match_operand:SF 1 "any_operand" ""))]
7552 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7555 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7556 (match_operand:SF 1 "const_double_operand" ""))]
7558 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7559 || (GET_CODE (operands[0]) == SUBREG
7560 && GET_CODE (SUBREG_REG (operands[0])) == REG
7561 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7562 [(set (match_dup 2) (match_dup 3))]
7568 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7569 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7571 if (! TARGET_POWERPC64)
7572 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7574 operands[2] = gen_lowpart (SImode, operands[0]);
7576 operands[3] = GEN_INT(l);
7579 (define_insn "*movsf_hardfloat"
7580 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
7581 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
7582 "(gpc_reg_operand (operands[0], SFmode)
7583 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
7586 {l%U1%X1|lwz%U1%X1} %0,%1
7587 {st%U0%X0|stw%U0%X0} %1,%0
7593 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
7594 (set_attr "length" "4,4,4,4,4,4,4,8")])
7596 (define_insn "*movsf_softfloat"
7597 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
7598 (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
7599 "(gpc_reg_operand (operands[0], SFmode)
7600 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
7603 {l%U1%X1|lwz%U1%X1} %0,%1
7604 {st%U0%X0|stw%U0%X0} %1,%0
7610 [(set_attr "type" "*,load,store,*,*,*,*,*")
7611 (set_attr "length" "4,4,4,4,4,4,4,8")])
7614 (define_expand "movdf"
7615 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7616 (match_operand:DF 1 "any_operand" ""))]
7618 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7621 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7622 (match_operand:DF 1 "const_int_operand" ""))]
7623 "! TARGET_POWERPC64 && reload_completed
7624 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7625 || (GET_CODE (operands[0]) == SUBREG
7626 && GET_CODE (SUBREG_REG (operands[0])) == REG
7627 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7628 [(set (match_dup 2) (match_dup 4))
7629 (set (match_dup 3) (match_dup 1))]
7632 int endian = (WORDS_BIG_ENDIAN == 0);
7633 HOST_WIDE_INT value = INTVAL (operands[1]);
7635 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7636 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7637 #if HOST_BITS_PER_WIDE_INT == 32
7638 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7640 operands[4] = GEN_INT (value >> 32);
7641 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
7646 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7647 (match_operand:DF 1 "const_double_operand" ""))]
7648 "! TARGET_POWERPC64 && reload_completed
7649 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7650 || (GET_CODE (operands[0]) == SUBREG
7651 && GET_CODE (SUBREG_REG (operands[0])) == REG
7652 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7653 [(set (match_dup 2) (match_dup 4))
7654 (set (match_dup 3) (match_dup 5))]
7657 int endian = (WORDS_BIG_ENDIAN == 0);
7661 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7662 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7664 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7665 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7666 operands[4] = GEN_INT (l[endian]);
7667 operands[5] = GEN_INT (l[1 - endian]);
7671 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7672 (match_operand:DF 1 "easy_fp_constant" ""))]
7673 "TARGET_POWERPC64 && reload_completed
7674 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7675 || (GET_CODE (operands[0]) == SUBREG
7676 && GET_CODE (SUBREG_REG (operands[0])) == REG
7677 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7678 [(set (match_dup 2) (match_dup 3))]
7681 int endian = (WORDS_BIG_ENDIAN == 0);
7685 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7686 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7688 operands[2] = gen_lowpart (DImode, operands[0]);
7689 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7690 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7693 ;; Don't have reload use general registers to load a constant. First,
7694 ;; it might not work if the output operand is the equivalent of
7695 ;; a non-offsettable memref, but also it is less efficient than loading
7696 ;; the constant into an FP register, since it will probably be used there.
7697 ;; The "??" is a kludge until we can figure out a more reasonable way
7698 ;; of handling these non-offsettable values.
7699 (define_insn "*movdf_hardfloat32"
7700 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
7701 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
7702 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
7703 && (gpc_reg_operand (operands[0], DFmode)
7704 || gpc_reg_operand (operands[1], DFmode))"
7707 switch (which_alternative)
7712 /* We normally copy the low-numbered register first. However, if
7713 the first register operand 0 is the same as the second register
7714 of operand 1, we must copy in the opposite order. */
7715 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7716 return \"mr %L0,%L1\;mr %0,%1\";
7718 return \"mr %0,%1\;mr %L0,%L1\";
7720 if (offsettable_memref_p (operands[1])
7721 || (GET_CODE (operands[1]) == MEM
7722 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7723 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7724 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
7726 /* If the low-address word is used in the address, we must load
7727 it last. Otherwise, load it first. Note that we cannot have
7728 auto-increment in that case since the address register is
7729 known to be dead. */
7730 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7732 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7734 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7740 addreg = find_addr_reg (XEXP (operands[1], 0));
7741 if (refers_to_regno_p (REGNO (operands[0]),
7742 REGNO (operands[0]) + 1,
7745 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7746 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7747 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7748 return \"{lx|lwzx} %0,%1\";
7752 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7753 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7754 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7755 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7760 if (offsettable_memref_p (operands[0])
7761 || (GET_CODE (operands[0]) == MEM
7762 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7763 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7764 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
7765 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7770 addreg = find_addr_reg (XEXP (operands[0], 0));
7771 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7772 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7773 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7774 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7782 return \"fmr %0,%1\";
7784 return \"lfd%U1%X1 %0,%1\";
7786 return \"stfd%U0%X0 %1,%0\";
7789 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
7790 (set_attr "length" "8,16,16,8,12,16,*,*,*")])
7792 (define_insn "*movdf_softfloat32"
7793 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7794 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7795 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
7796 && (gpc_reg_operand (operands[0], DFmode)
7797 || gpc_reg_operand (operands[1], DFmode))"
7800 switch (which_alternative)
7805 /* We normally copy the low-numbered register first. However, if
7806 the first register operand 0 is the same as the second register of
7807 operand 1, we must copy in the opposite order. */
7808 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7809 return \"mr %L0,%L1\;mr %0,%1\";
7811 return \"mr %0,%1\;mr %L0,%L1\";
7813 /* If the low-address word is used in the address, we must load
7814 it last. Otherwise, load it first. Note that we cannot have
7815 auto-increment in that case since the address register is
7816 known to be dead. */
7817 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7819 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7821 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7823 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7830 [(set_attr "type" "*,load,store,*,*,*")
7831 (set_attr "length" "8,8,8,8,12,16")])
7833 (define_insn "*movdf_hardfloat64"
7834 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
7835 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
7836 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
7837 && (gpc_reg_operand (operands[0], DFmode)
7838 || gpc_reg_operand (operands[1], DFmode))"
7849 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
7850 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
7852 (define_insn "*movdf_softfloat64"
7853 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7854 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7855 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
7856 && (gpc_reg_operand (operands[0], DFmode)
7857 || gpc_reg_operand (operands[1], DFmode))"
7865 [(set_attr "type" "*,load,store,*,*,*")
7866 (set_attr "length" "*,*,*,8,12,16")])
7868 ;; Next come the multi-word integer load and store and the load and store
7870 (define_expand "movdi"
7871 [(set (match_operand:DI 0 "general_operand" "")
7872 (match_operand:DI 1 "any_operand" ""))]
7874 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
7876 (define_insn "*movdi_internal32"
7877 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
7878 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
7880 && (gpc_reg_operand (operands[0], DImode)
7881 || gpc_reg_operand (operands[1], DImode))"
7884 switch (which_alternative)
7889 /* We normally copy the low-numbered register first. However, if
7890 the first register operand 0 is the same as the second register of
7891 operand 1, we must copy in the opposite order. */
7892 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7893 return \"mr %L0,%L1\;mr %0,%1\";
7895 return \"mr %0,%1\;mr %L0,%L1\";
7897 /* If the low-address word is used in the address, we must load it
7898 last. Otherwise, load it first. Note that we cannot have
7899 auto-increment in that case since the address register is known to be
7901 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7903 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7905 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7907 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7909 return \"fmr %0,%1\";
7911 return \"lfd%U1%X1 %0,%1\";
7913 return \"stfd%U0%X0 %1,%0\";
7922 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
7923 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
7926 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7927 (match_operand:DI 1 "const_int_operand" ""))]
7928 "! TARGET_POWERPC64 && reload_completed"
7929 [(set (match_dup 2) (match_dup 4))
7930 (set (match_dup 3) (match_dup 1))]
7933 HOST_WIDE_INT value = INTVAL (operands[1]);
7934 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7936 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7938 #if HOST_BITS_PER_WIDE_INT == 32
7939 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7941 operands[4] = GEN_INT (value >> 32);
7942 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
7947 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7948 (match_operand:DI 1 "const_double_operand" ""))]
7949 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
7950 [(set (match_dup 2) (match_dup 4))
7951 (set (match_dup 3) (match_dup 5))]
7954 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7956 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7958 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7959 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7962 (define_insn "*movdi_internal64"
7963 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
7964 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
7966 && (gpc_reg_operand (operands[0], DImode)
7967 || gpc_reg_operand (operands[1], DImode))"
7982 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
7983 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
7985 ;; immediate value valid for a single instruction hiding in a const_double
7987 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7988 (match_operand:DI 1 "const_double_operand" "F"))]
7989 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
7990 && GET_CODE (operands[1]) == CONST_DOUBLE
7991 && num_insns_constant (operands[1], DImode) == 1"
7994 return ((unsigned HOST_WIDE_INT)
7995 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
7996 ? \"li %0,%1\" : \"lis %0,%v1\";
7999 ;; sign-extended 32-bit value
8001 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8002 (match_operand:DI 1 "const_int_operand" ""))]
8003 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8004 && num_insns_constant (operands[1], DImode) > 1"
8008 (ior:DI (match_dup 0)
8012 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
8013 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
8017 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8018 (match_operand:DI 1 "const_double_operand" ""))]
8019 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8020 && GET_CODE (operands[1]) == CONST_DOUBLE
8021 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
8022 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
8023 || (CONST_DOUBLE_HIGH (operands[1]) == -1
8024 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))"
8028 (ior:DI (match_dup 0)
8032 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000);
8033 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff);
8037 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8038 (match_operand:DI 1 "const_int_operand" ""))]
8039 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
8040 && GET_CODE (operands[1]) == CONST_INT
8041 && (((INTVAL (operands[1]) >> 32) == 0
8042 && (INTVAL (operands[1]) & 0x80000000) == 0)
8043 || ((INTVAL (operands[1]) >> 32) == -1
8044 && (INTVAL (operands[1]) & 0x80000000) != 0))
8045 && num_insns_constant (operands[1], DImode) > 1"
8049 (ior:DI (match_dup 0)
8053 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
8054 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
8057 ;; zero-extended 32-bit value
8059 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8060 (match_operand:DI 1 "const_double_operand" ""))]
8061 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8062 && GET_CODE (operands[1]) == CONST_DOUBLE
8063 && CONST_DOUBLE_HIGH (operands[1]) == 0
8064 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0"
8068 (zero_extend:DI (match_dup 3)))]
8071 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8072 operands[3] = gen_lowpart_common (SImode, operands[0]);
8076 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8077 (match_operand:DI 1 "const_int_operand" ""))]
8078 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
8079 && GET_CODE (operands[1]) == CONST_INT
8080 && INTVAL (operands[1]) >> 32 == 0
8081 && (INTVAL (operands[1]) & 0x80000000) != 0
8082 && num_insns_constant (operands[1], DImode) > 1"
8086 (zero_extend:DI (match_dup 3)))]
8089 #if HOST_BITS_PER_WIDE_INT != 32
8090 operands[2] = GEN_INT ((INTVAL (operands[1]) << 32) >> 32);
8092 operands[3] = gen_lowpart_common (SImode, operands[0]);
8095 ;; 32-bit value in upper half of doubleword
8097 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8098 (match_operand:DI 1 "const_double_operand" ""))]
8099 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8100 && GET_CODE (operands[1]) == CONST_DOUBLE
8101 && CONST_DOUBLE_LOW (operands[1]) == 0"
8105 (ashift:DI (match_dup 0)
8108 { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }")
8111 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8112 (match_operand:DI 1 "const_int_operand" ""))]
8113 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
8114 && GET_CODE (operands[1]) == CONST_INT
8115 && (INTVAL (operands[1]) & 0xffffffff) == 0"
8119 (ashift:DI (match_dup 0)
8123 #if HOST_BITS_PER_WIDE_INT != 32
8124 operands[2] = GEN_INT (INTVAL (operands[1]) >> 32);
8128 ;; Generate all one-bits and clear left or right.
8129 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8131 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8132 (match_operand:DI 1 "mask64_operand" ""))]
8133 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8134 [(set (match_dup 0) (const_int -1))
8136 (and:DI (rotate:DI (match_dup 0)
8141 ;; Split a load of a large constant into the appropriate five-instruction
8142 ;; sequence. Handle anything in a constant number of insns.
8143 ;; When non-easy constants can go in the TOC, this should use
8144 ;; easy_fp_constant predicate.
8146 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8147 (match_operand:DI 1 "const_double_operand" ""))]
8148 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8149 && num_insns_constant (operands[1], DImode) > 1"
8153 (ashift:DI (match_dup 0)
8156 (ior:DI (match_dup 0)
8160 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8162 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8163 operands[3] = immed_double_const (CONST_DOUBLE_LOW (operands[1]),
8168 HOST_WIDE_INT value = INTVAL (operands[1]);
8169 operands[2] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8170 operands[3] = immed_double_const (value, 0, DImode);
8175 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8176 (match_operand:DI 1 "const_int_operand" ""))]
8177 "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64
8178 && num_insns_constant (operands[1], DImode) > 1"
8182 (ashift:DI (match_dup 0)
8185 (ior:DI (match_dup 0)
8189 #if HOST_BITS_PER_WIDE_INT != 32
8190 HOST_WIDE_INT value = INTVAL (operands[1]);
8191 operands[2] = GEN_INT (value >> 32);
8192 operands[3] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
8196 (define_insn "*movdi_internal2"
8197 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8198 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
8200 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8205 [(set_attr "type" "compare")
8206 (set_attr "length" "4,8")])
8209 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8210 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8212 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8213 "TARGET_POWERPC64 && reload_completed"
8214 [(set (match_dup 0) (match_dup 1))
8216 (compare:CC (match_dup 0)
8220 ;; TImode is similar, except that we usually want to compute the address into
8221 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8222 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8223 (define_expand "movti"
8224 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8225 (match_operand:TI 1 "general_operand" ""))
8226 (clobber (scratch:SI))])]
8227 "TARGET_STRING || TARGET_POWERPC64"
8228 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8230 ;; We say that MQ is clobbered in the last alternative because the first
8231 ;; alternative would never get used otherwise since it would need a reload
8232 ;; while the 2nd alternative would not. We put memory cases first so they
8233 ;; are preferred. Otherwise, we'd try to reload the output instead of
8234 ;; giving the SCRATCH mq.
8235 (define_insn "*movti_power"
8236 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8237 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8238 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8239 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8240 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8243 switch (which_alternative)
8249 return \"{stsi|stswi} %1,%P0,16\";
8252 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8255 /* Normally copy registers with lowest numbered register copied first.
8256 But copy in the other order if the first register of the output
8257 is the second, third, or fourth register in the input. */
8258 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8259 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8260 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8262 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8264 /* If the address is not used in the output, we can use lsi. Otherwise,
8265 fall through to generating four loads. */
8266 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8267 return \"{lsi|lswi} %0,%P1,16\";
8268 /* ... fall through ... */
8270 /* If the address register is the same as the register for the lowest-
8271 addressed word, load it last. Similarly for the next two words.
8272 Otherwise load lowest address to highest. */
8273 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8275 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8276 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8277 REGNO (operands[0]) + 2, operands[1], 0))
8278 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8279 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8280 REGNO (operands[0]) + 3, operands[1], 0))
8281 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8283 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8286 [(set_attr "type" "store,store,*,load,load")
8287 (set_attr "length" "*,16,16,*,16")])
8289 (define_insn "*movti_string"
8290 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
8291 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
8292 (clobber (match_scratch:SI 2 "=X,X,X"))]
8293 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8294 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8297 switch (which_alternative)
8303 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8306 /* Normally copy registers with lowest numbered register copied first.
8307 But copy in the other order if the first register of the output
8308 is the second, third, or fourth register in the input. */
8309 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8310 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8311 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8313 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8315 /* If the address register is the same as the register for the lowest-
8316 addressed word, load it last. Similarly for the next two words.
8317 Otherwise load lowest address to highest. */
8318 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8320 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8321 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8322 REGNO (operands[0]) + 2, operands[1], 0))
8323 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8324 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8325 REGNO (operands[0]) + 3, operands[1], 0))
8326 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8328 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8331 [(set_attr "type" "store,*,load")
8332 (set_attr "length" "16,16,16")])
8334 (define_insn "*movti_ppc64"
8335 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
8336 (match_operand:TI 1 "input_operand" "r,m,r"))]
8337 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8338 || gpc_reg_operand (operands[1], TImode))"
8341 switch (which_alternative)
8346 /* We normally copy the low-numbered register first. However, if
8347 the first register operand 0 is the same as the second register of
8348 operand 1, we must copy in the opposite order. */
8349 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8350 return \"mr %L0,%L1\;mr %0,%1\";
8352 return \"mr %0,%1\;mr %L0,%L1\";
8354 /* If the low-address word is used in the address, we must load it
8355 last. Otherwise, load it first. Note that we cannot have
8356 auto-increment in that case since the address register is known to be
8358 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8360 return \"ld %L0,%L1\;ld %0,%1\";
8362 return \"ld%U1 %0,%1\;ld %L0,%L1\";
8364 return \"std%U0 %1,%0\;std %L1,%L0\";
8367 [(set_attr "type" "*,load,store")
8368 (set_attr "length" "8,8,8")])
8370 (define_expand "load_multiple"
8371 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8372 (match_operand:SI 1 "" ""))
8373 (use (match_operand:SI 2 "" ""))])]
8382 /* Support only loading a constant number of fixed-point registers from
8383 memory and only bother with this if more than two; the machine
8384 doesn't support more than eight. */
8385 if (GET_CODE (operands[2]) != CONST_INT
8386 || INTVAL (operands[2]) <= 2
8387 || INTVAL (operands[2]) > 8
8388 || GET_CODE (operands[1]) != MEM
8389 || GET_CODE (operands[0]) != REG
8390 || REGNO (operands[0]) >= 32)
8393 count = INTVAL (operands[2]);
8394 regno = REGNO (operands[0]);
8396 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8397 from = force_reg (SImode, XEXP (operands[1], 0));
8399 for (i = 0; i < count; i++)
8400 XVECEXP (operands[3], 0, i)
8401 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8402 change_address (operands[1], SImode,
8403 plus_constant (from, i * 4)));
8407 [(match_parallel 0 "load_multiple_operation"
8408 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8409 (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])]
8413 /* We have to handle the case where the pseudo used to contain the address
8414 is assigned to one of the output registers. */
8416 int words = XVECLEN (operands[0], 0);
8419 if (XVECLEN (operands[0], 0) == 1)
8420 return \"{l|lwz} %1,0(%2)\";
8422 for (i = 0; i < words; i++)
8423 if (refers_to_regno_p (REGNO (operands[1]) + i,
8424 REGNO (operands[1]) + i + 1, operands[2], 0))
8428 xop[0] = operands[1];
8429 xop[1] = operands[2];
8430 xop[2] = GEN_INT (4 * (words-1));
8431 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
8436 xop[0] = operands[1];
8437 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8438 xop[2] = GEN_INT (4 * (words-1));
8439 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
8444 for (j = 0; j < words; j++)
8447 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
8448 xop[1] = operands[2];
8449 xop[2] = GEN_INT (j * 4);
8450 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
8452 xop[0] = operands[2];
8453 xop[1] = GEN_INT (i * 4);
8454 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
8459 return \"{lsi|lswi} %1,%2,%N0\";
8461 [(set_attr "type" "load")
8462 (set_attr "length" "32")])
8465 (define_expand "store_multiple"
8466 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8467 (match_operand:SI 1 "" ""))
8468 (clobber (scratch:SI))
8469 (use (match_operand:SI 2 "" ""))])]
8478 /* Support only storing a constant number of fixed-point registers to
8479 memory and only bother with this if more than two; the machine
8480 doesn't support more than eight. */
8481 if (GET_CODE (operands[2]) != CONST_INT
8482 || INTVAL (operands[2]) <= 2
8483 || INTVAL (operands[2]) > 8
8484 || GET_CODE (operands[0]) != MEM
8485 || GET_CODE (operands[1]) != REG
8486 || REGNO (operands[1]) >= 32)
8489 count = INTVAL (operands[2]);
8490 regno = REGNO (operands[1]);
8492 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8493 to = force_reg (SImode, XEXP (operands[0], 0));
8495 XVECEXP (operands[3], 0, 0)
8496 = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to),
8498 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8499 gen_rtx_SCRATCH (SImode));
8501 for (i = 1; i < count; i++)
8502 XVECEXP (operands[3], 0, i + 1)
8503 = gen_rtx_SET (VOIDmode,
8504 change_address (operands[0], SImode,
8505 plus_constant (to, i * 4)),
8506 gen_rtx_REG (SImode, regno + i));
8510 [(match_parallel 0 "store_multiple_operation"
8511 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8512 (match_operand:SI 2 "gpc_reg_operand" "r"))
8513 (clobber (match_scratch:SI 3 "=q"))])]
8514 "TARGET_STRING && TARGET_POWER"
8515 "{stsi|stswi} %2,%P1,%O0"
8516 [(set_attr "type" "store")])
8519 [(match_parallel 0 "store_multiple_operation"
8520 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8521 (match_operand:SI 2 "gpc_reg_operand" "r"))
8522 (clobber (match_scratch:SI 3 "X"))])]
8523 "TARGET_STRING && ! TARGET_POWER"
8524 "{stsi|stswi} %2,%1,%O0"
8525 [(set_attr "type" "store")])
8528 ;; String/block move insn.
8529 ;; Argument 0 is the destination
8530 ;; Argument 1 is the source
8531 ;; Argument 2 is the length
8532 ;; Argument 3 is the alignment
8534 (define_expand "movstrsi"
8535 [(parallel [(set (match_operand:BLK 0 "" "")
8536 (match_operand:BLK 1 "" ""))
8537 (use (match_operand:SI 2 "" ""))
8538 (use (match_operand:SI 3 "" ""))])]
8542 if (expand_block_move (operands))
8548 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8549 ;; register allocator doesn't have a clue about allocating 8 word registers.
8550 ;; rD/rS = r5 is preferred, efficient form.
8551 (define_expand "movstrsi_8reg"
8552 [(parallel [(set (match_operand 0 "" "")
8553 (match_operand 1 "" ""))
8554 (use (match_operand 2 "" ""))
8555 (use (match_operand 3 "" ""))
8556 (clobber (reg:SI 5))
8557 (clobber (reg:SI 6))
8558 (clobber (reg:SI 7))
8559 (clobber (reg:SI 8))
8560 (clobber (reg:SI 9))
8561 (clobber (reg:SI 10))
8562 (clobber (reg:SI 11))
8563 (clobber (reg:SI 12))
8564 (clobber (match_scratch:SI 4 ""))])]
8569 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8570 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8571 (use (match_operand:SI 2 "immediate_operand" "i"))
8572 (use (match_operand:SI 3 "immediate_operand" "i"))
8573 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8574 (clobber (reg:SI 6))
8575 (clobber (reg:SI 7))
8576 (clobber (reg:SI 8))
8577 (clobber (reg:SI 9))
8578 (clobber (reg:SI 10))
8579 (clobber (reg:SI 11))
8580 (clobber (reg:SI 12))
8581 (clobber (match_scratch:SI 5 "=q"))]
8582 "TARGET_STRING && TARGET_POWER
8583 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8584 || INTVAL (operands[2]) == 0)
8585 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8586 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8587 && REGNO (operands[4]) == 5"
8588 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8589 [(set_attr "type" "load")
8590 (set_attr "length" "8")])
8593 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8594 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8595 (use (match_operand:SI 2 "immediate_operand" "i"))
8596 (use (match_operand:SI 3 "immediate_operand" "i"))
8597 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8598 (clobber (reg:SI 6))
8599 (clobber (reg:SI 7))
8600 (clobber (reg:SI 8))
8601 (clobber (reg:SI 9))
8602 (clobber (reg:SI 10))
8603 (clobber (reg:SI 11))
8604 (clobber (reg:SI 12))
8605 (clobber (match_scratch:SI 5 "X"))]
8606 "TARGET_STRING && ! TARGET_POWER
8607 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8608 || INTVAL (operands[2]) == 0)
8609 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8610 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8611 && REGNO (operands[4]) == 5"
8612 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8613 [(set_attr "type" "load")
8614 (set_attr "length" "8")])
8616 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8617 ;; register allocator doesn't have a clue about allocating 6 word registers.
8618 ;; rD/rS = r5 is preferred, efficient form.
8619 (define_expand "movstrsi_6reg"
8620 [(parallel [(set (match_operand 0 "" "")
8621 (match_operand 1 "" ""))
8622 (use (match_operand 2 "" ""))
8623 (use (match_operand 3 "" ""))
8624 (clobber (reg:SI 5))
8625 (clobber (reg:SI 6))
8626 (clobber (reg:SI 7))
8627 (clobber (reg:SI 8))
8628 (clobber (reg:SI 9))
8629 (clobber (reg:SI 10))
8630 (clobber (match_scratch:SI 4 ""))])]
8635 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8636 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8637 (use (match_operand:SI 2 "immediate_operand" "i"))
8638 (use (match_operand:SI 3 "immediate_operand" "i"))
8639 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8640 (clobber (reg:SI 6))
8641 (clobber (reg:SI 7))
8642 (clobber (reg:SI 8))
8643 (clobber (reg:SI 9))
8644 (clobber (reg:SI 10))
8645 (clobber (match_scratch:SI 5 "=q"))]
8646 "TARGET_STRING && TARGET_POWER
8647 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8648 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8649 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8650 && REGNO (operands[4]) == 5"
8651 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8652 [(set_attr "type" "load")
8653 (set_attr "length" "8")])
8656 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8657 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8658 (use (match_operand:SI 2 "immediate_operand" "i"))
8659 (use (match_operand:SI 3 "immediate_operand" "i"))
8660 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8661 (clobber (reg:SI 6))
8662 (clobber (reg:SI 7))
8663 (clobber (reg:SI 8))
8664 (clobber (reg:SI 9))
8665 (clobber (reg:SI 10))
8666 (clobber (match_scratch:SI 5 "X"))]
8667 "TARGET_STRING && ! TARGET_POWER
8668 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8669 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8670 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8671 && REGNO (operands[4]) == 5"
8672 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8673 [(set_attr "type" "load")
8674 (set_attr "length" "8")])
8676 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8677 ;; problems with TImode.
8678 ;; rD/rS = r5 is preferred, efficient form.
8679 (define_expand "movstrsi_4reg"
8680 [(parallel [(set (match_operand 0 "" "")
8681 (match_operand 1 "" ""))
8682 (use (match_operand 2 "" ""))
8683 (use (match_operand 3 "" ""))
8684 (clobber (reg:SI 5))
8685 (clobber (reg:SI 6))
8686 (clobber (reg:SI 7))
8687 (clobber (reg:SI 8))
8688 (clobber (match_scratch:SI 4 ""))])]
8693 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8694 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8695 (use (match_operand:SI 2 "immediate_operand" "i"))
8696 (use (match_operand:SI 3 "immediate_operand" "i"))
8697 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8698 (clobber (reg:SI 6))
8699 (clobber (reg:SI 7))
8700 (clobber (reg:SI 8))
8701 (clobber (match_scratch:SI 5 "=q"))]
8702 "TARGET_STRING && TARGET_POWER
8703 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8704 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8705 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8706 && REGNO (operands[4]) == 5"
8707 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8708 [(set_attr "type" "load")
8709 (set_attr "length" "8")])
8712 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8713 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8714 (use (match_operand:SI 2 "immediate_operand" "i"))
8715 (use (match_operand:SI 3 "immediate_operand" "i"))
8716 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8717 (clobber (reg:SI 6))
8718 (clobber (reg:SI 7))
8719 (clobber (reg:SI 8))
8720 (clobber (match_scratch:SI 5 "X"))]
8721 "TARGET_STRING && ! TARGET_POWER
8722 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8723 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8724 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8725 && REGNO (operands[4]) == 5"
8726 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8727 [(set_attr "type" "load")
8728 (set_attr "length" "8")])
8730 ;; Move up to 8 bytes at a time.
8731 (define_expand "movstrsi_2reg"
8732 [(parallel [(set (match_operand 0 "" "")
8733 (match_operand 1 "" ""))
8734 (use (match_operand 2 "" ""))
8735 (use (match_operand 3 "" ""))
8736 (clobber (match_scratch:DI 4 ""))
8737 (clobber (match_scratch:SI 5 ""))])]
8738 "TARGET_STRING && ! TARGET_POWERPC64"
8742 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8743 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8744 (use (match_operand:SI 2 "immediate_operand" "i"))
8745 (use (match_operand:SI 3 "immediate_operand" "i"))
8746 (clobber (match_scratch:DI 4 "=&r"))
8747 (clobber (match_scratch:SI 5 "=q"))]
8748 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8749 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8750 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8751 [(set_attr "type" "load")
8752 (set_attr "length" "8")])
8755 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8756 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8757 (use (match_operand:SI 2 "immediate_operand" "i"))
8758 (use (match_operand:SI 3 "immediate_operand" "i"))
8759 (clobber (match_scratch:DI 4 "=&r"))
8760 (clobber (match_scratch:SI 5 "X"))]
8761 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8762 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8763 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8764 [(set_attr "type" "load")
8765 (set_attr "length" "8")])
8767 ;; Move up to 4 bytes at a time.
8768 (define_expand "movstrsi_1reg"
8769 [(parallel [(set (match_operand 0 "" "")
8770 (match_operand 1 "" ""))
8771 (use (match_operand 2 "" ""))
8772 (use (match_operand 3 "" ""))
8773 (clobber (match_scratch:SI 4 ""))
8774 (clobber (match_scratch:SI 5 ""))])]
8779 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8780 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8781 (use (match_operand:SI 2 "immediate_operand" "i"))
8782 (use (match_operand:SI 3 "immediate_operand" "i"))
8783 (clobber (match_scratch:SI 4 "=&r"))
8784 (clobber (match_scratch:SI 5 "=q"))]
8785 "TARGET_STRING && TARGET_POWER
8786 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8787 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8788 [(set_attr "type" "load")
8789 (set_attr "length" "8")])
8792 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8793 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8794 (use (match_operand:SI 2 "immediate_operand" "i"))
8795 (use (match_operand:SI 3 "immediate_operand" "i"))
8796 (clobber (match_scratch:SI 4 "=&r"))
8797 (clobber (match_scratch:SI 5 "X"))]
8798 "TARGET_STRING && ! TARGET_POWER
8799 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8800 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8801 [(set_attr "type" "load")
8802 (set_attr "length" "8")])
8805 ;; Define insns that do load or store with update. Some of these we can
8806 ;; get by using pre-decrement or pre-increment, but the hardware can also
8807 ;; do cases where the increment is not the size of the object.
8809 ;; In all these cases, we use operands 0 and 1 for the register being
8810 ;; incremented because those are the operands that local-alloc will
8811 ;; tie and these are the pair most likely to be tieable (and the ones
8812 ;; that will benefit the most).
8814 (define_insn "*movdi_update1"
8815 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8816 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8817 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
8818 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8819 (plus:DI (match_dup 1) (match_dup 2)))]
8820 "TARGET_POWERPC64 && TARGET_UPDATE"
8824 [(set_attr "type" "load")])
8826 (define_insn "*movdi_update2"
8827 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8829 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8830 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8831 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8832 (plus:DI (match_dup 1) (match_dup 2)))]
8835 [(set_attr "type" "load")])
8837 (define_insn "movdi_update"
8838 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8839 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
8840 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8841 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8842 (plus:DI (match_dup 1) (match_dup 2)))]
8843 "TARGET_POWERPC64 && TARGET_UPDATE"
8847 [(set_attr "type" "store")])
8849 (define_insn "*movsi_update1"
8850 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8851 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8852 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8853 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8854 (plus:SI (match_dup 1) (match_dup 2)))]
8857 {lux|lwzux} %3,%0,%2
8858 {lu|lwzu} %3,%2(%0)"
8859 [(set_attr "type" "load")])
8861 (define_insn "movsi_update"
8862 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8863 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8864 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8865 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8866 (plus:SI (match_dup 1) (match_dup 2)))]
8869 {stux|stwux} %3,%0,%2
8870 {stu|stwu} %3,%2(%0)"
8871 [(set_attr "type" "store")])
8873 (define_insn "*movhi_update"
8874 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8875 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8876 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8877 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8878 (plus:SI (match_dup 1) (match_dup 2)))]
8883 [(set_attr "type" "load")])
8885 (define_insn "*movhi_update2"
8886 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8888 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8889 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8890 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8891 (plus:SI (match_dup 1) (match_dup 2)))]
8896 [(set_attr "type" "load")])
8898 (define_insn "*movhi_update3"
8899 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8901 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8902 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8903 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8904 (plus:SI (match_dup 1) (match_dup 2)))]
8909 [(set_attr "type" "load")])
8911 (define_insn "*movhi_update4"
8912 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8913 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8914 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8915 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8916 (plus:SI (match_dup 1) (match_dup 2)))]
8921 [(set_attr "type" "store")])
8923 (define_insn "*movqi_update1"
8924 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8925 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8926 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8927 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8928 (plus:SI (match_dup 1) (match_dup 2)))]
8933 [(set_attr "type" "load")])
8935 (define_insn "*movqi_update2"
8936 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8938 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8939 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8940 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8941 (plus:SI (match_dup 1) (match_dup 2)))]
8946 [(set_attr "type" "load")])
8948 (define_insn "*movqi_update3"
8949 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8950 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8951 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8952 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8953 (plus:SI (match_dup 1) (match_dup 2)))]
8958 [(set_attr "type" "store")])
8960 (define_insn "*movsf_update1"
8961 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
8962 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8963 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8964 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8965 (plus:SI (match_dup 1) (match_dup 2)))]
8966 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8970 [(set_attr "type" "fpload")])
8972 (define_insn "*movsf_update2"
8973 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8974 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8975 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
8976 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8977 (plus:SI (match_dup 1) (match_dup 2)))]
8978 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8982 [(set_attr "type" "fpstore")])
8984 (define_insn "*movsf_update3"
8985 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
8986 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8987 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8988 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8989 (plus:SI (match_dup 1) (match_dup 2)))]
8990 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
8992 {lux|lwzux} %3,%0,%2
8993 {lu|lwzu} %3,%2(%0)"
8994 [(set_attr "type" "load")])
8996 (define_insn "*movsf_update4"
8997 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8998 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8999 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9000 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9001 (plus:SI (match_dup 1) (match_dup 2)))]
9002 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
9004 {stux|stwux} %3,%0,%2
9005 {stu|stwu} %3,%2(%0)"
9006 [(set_attr "type" "store")])
9008 (define_insn "*movdf_update1"
9009 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9010 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9011 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9012 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9013 (plus:SI (match_dup 1) (match_dup 2)))]
9014 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9018 [(set_attr "type" "fpload")])
9020 (define_insn "*movdf_update2"
9021 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9022 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9023 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9024 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9025 (plus:SI (match_dup 1) (match_dup 2)))]
9026 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9030 [(set_attr "type" "fpstore")])
9032 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9035 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9036 (match_operand:DF 1 "memory_operand" ""))
9037 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9038 (match_operand:DF 3 "memory_operand" ""))]
9040 && TARGET_HARD_FLOAT
9041 && registers_ok_for_quad_peep (operands[0], operands[2])
9042 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9043 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9047 [(set (match_operand:DF 0 "memory_operand" "")
9048 (match_operand:DF 1 "gpc_reg_operand" "f"))
9049 (set (match_operand:DF 2 "memory_operand" "")
9050 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9052 && TARGET_HARD_FLOAT
9053 && registers_ok_for_quad_peep (operands[1], operands[3])
9054 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9055 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9058 ;; Next come insns related to the calling sequence.
9060 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9061 ;; We move the back-chain and decrement the stack pointer.
9063 (define_expand "allocate_stack"
9064 [(set (match_operand 0 "gpc_reg_operand" "=r")
9065 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9067 (minus (reg 1) (match_dup 1)))]
9070 { rtx chain = gen_reg_rtx (Pmode);
9071 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9074 emit_move_insn (chain, stack_bot);
9076 /* Check stack bounds if necessary. */
9077 if (current_function_limit_stack)
9080 available = expand_binop (Pmode, sub_optab,
9081 stack_pointer_rtx, stack_limit_rtx,
9082 NULL_RTX, 1, OPTAB_WIDEN);
9083 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9086 if (GET_CODE (operands[1]) != CONST_INT
9087 || INTVAL (operands[1]) < -32767
9088 || INTVAL (operands[1]) > 32768)
9090 neg_op0 = gen_reg_rtx (Pmode);
9092 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9094 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9097 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9100 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9101 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
9105 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9106 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
9107 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9110 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9114 ;; These patterns say how to save and restore the stack pointer. We need not
9115 ;; save the stack pointer at function level since we are careful to
9116 ;; preserve the backchain. At block level, we have to restore the backchain
9117 ;; when we restore the stack pointer.
9119 ;; For nonlocal gotos, we must save both the stack pointer and its
9120 ;; backchain and restore both. Note that in the nonlocal case, the
9121 ;; save area is a memory location.
9123 (define_expand "save_stack_function"
9124 [(match_operand 0 "any_operand" "")
9125 (match_operand 1 "any_operand" "")]
9129 (define_expand "restore_stack_function"
9130 [(match_operand 0 "any_operand" "")
9131 (match_operand 1 "any_operand" "")]
9135 (define_expand "restore_stack_block"
9136 [(use (match_operand 0 "register_operand" ""))
9137 (set (match_dup 2) (match_dup 3))
9138 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9139 (set (match_dup 3) (match_dup 2))]
9143 operands[2] = gen_reg_rtx (Pmode);
9144 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9147 (define_expand "save_stack_nonlocal"
9148 [(match_operand 0 "memory_operand" "")
9149 (match_operand 1 "register_operand" "")]
9153 rtx temp = gen_reg_rtx (Pmode);
9155 /* Copy the backchain to the first word, sp to the second. */
9156 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9157 emit_move_insn (operand_subword (operands[0], 0, 0,
9158 (TARGET_32BIT ? DImode : TImode)),
9160 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
9165 (define_expand "restore_stack_nonlocal"
9166 [(match_operand 0 "register_operand" "")
9167 (match_operand 1 "memory_operand" "")]
9171 rtx temp = gen_reg_rtx (Pmode);
9173 /* Restore the backchain from the first word, sp from the second. */
9174 emit_move_insn (temp,
9175 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
9176 emit_move_insn (operands[0],
9177 operand_subword (operands[1], 1, 0,
9178 (TARGET_32BIT ? DImode : TImode)));
9179 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9183 ;; TOC register handling.
9185 ;; Code to initialize the TOC register...
9187 (define_insn "load_toc_aix_si"
9188 [(set (match_operand:SI 0 "register_operand" "=r")
9189 (unspec:SI [(const_int 0)] 7))]
9190 "! TARGET_ELF && TARGET_32BIT"
9194 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9195 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9196 operands[2] = gen_rtx_REG (Pmode, 2);
9197 return \"{l|lwz} %0,%1(%2)\";
9199 [(set_attr "type" "load")])
9201 (define_insn "load_toc_aix_di"
9202 [(set (match_operand:DI 0 "register_operand" "=r")
9203 (unspec:DI [(const_int 0)] 7))]
9204 "! TARGET_ELF && TARGET_64BIT"
9208 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9209 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9210 operands[2] = gen_rtx_REG (Pmode, 2);
9211 return \"ld %0,%1(%2)\";
9213 [(set_attr "type" "load")])
9215 (define_insn "load_toc_v4_pic_si"
9216 [(set (match_operand:SI 0 "register_operand" "=l")
9217 (unspec:SI [(const_int 0)] 7))]
9218 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1
9220 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9221 [(set_attr "type" "branch")
9222 (set_attr "length" "4")])
9224 (define_insn "load_toc_v4_pic_di"
9225 [(set (match_operand:DI 0 "register_operand" "=l")
9226 (unspec:DI [(const_int 0)] 7))]
9227 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1
9229 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9230 [(set_attr "type" "branch")
9231 (set_attr "length" "4")])
9233 (define_insn "load_toc_v4_PIC_1"
9234 [(set (match_operand:SI 0 "register_operand" "=l")
9235 (match_operand:SI 1 "immediate_operand" "s"))
9236 (unspec [(match_dup 1)] 7)]
9237 "TARGET_ELF && flag_pic == 2"
9239 [(set_attr "type" "branch")
9240 (set_attr "length" "4")])
9242 (define_insn "load_toc_v4_PIC_1b"
9243 [(set (match_operand:SI 0 "register_operand" "=l")
9244 (match_operand:SI 1 "immediate_operand" "s"))
9245 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
9246 "TARGET_ELF && flag_pic == 2"
9247 "bl %1\\n\\t.long %2-%1+4\\n%1:"
9248 [(set_attr "type" "branch")
9249 (set_attr "length" "8")])
9251 (define_insn "load_toc_v4_PIC_2"
9252 [(set (match_operand:SI 0 "register_operand" "=r")
9253 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
9254 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9255 (match_operand:SI 3 "immediate_operand" "s")))))]
9256 "TARGET_ELF && flag_pic == 2"
9257 "{l|lwz} %0,%2-%3(%1)"
9258 [(set_attr "type" "load")])
9260 ;; If the TOC is shared over a translation unit, as happens with all
9261 ;; the kinds of PIC that we support, we need to restore the TOC
9262 ;; pointer only when jumping over units of translation.
9264 (define_expand "builtin_setjmp_receiver"
9265 [(use (label_ref (match_operand 0 "" "")))]
9266 "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1)
9267 || (TARGET_TOC && TARGET_MINIMAL_TOC)"
9270 rs6000_emit_load_toc_table (FALSE);
9274 ;; A function pointer under AIX is a pointer to a data area whose first word
9275 ;; contains the actual address of the function, whose second word contains a
9276 ;; pointer to its TOC, and whose third word contains a value to place in the
9277 ;; static chain register (r11). Note that if we load the static chain, our
9278 ;; "trampoline" need not have any executable code.
9280 (define_expand "call_indirect_aix32"
9282 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9283 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9286 (mem:SI (plus:SI (match_dup 0)
9289 (mem:SI (plus:SI (match_dup 0)
9291 (parallel [(call (mem:SI (match_dup 2))
9292 (match_operand 1 "" ""))
9296 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9297 (clobber (scratch:SI))])]
9300 { operands[2] = gen_reg_rtx (SImode); }")
9302 (define_expand "call_indirect_aix64"
9304 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9305 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9308 (mem:DI (plus:DI (match_dup 0)
9311 (mem:DI (plus:DI (match_dup 0)
9313 (parallel [(call (mem:SI (match_dup 2))
9314 (match_operand 1 "" ""))
9318 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9319 (clobber (scratch:SI))])]
9322 { operands[2] = gen_reg_rtx (DImode); }")
9324 (define_expand "call_value_indirect_aix32"
9326 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9327 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9330 (mem:SI (plus:SI (match_dup 1)
9333 (mem:SI (plus:SI (match_dup 1)
9335 (parallel [(set (match_operand 0 "" "")
9336 (call (mem:SI (match_dup 3))
9337 (match_operand 2 "" "")))
9341 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9342 (clobber (scratch:SI))])]
9345 { operands[3] = gen_reg_rtx (SImode); }")
9347 (define_expand "call_value_indirect_aix64"
9349 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9350 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9353 (mem:DI (plus:DI (match_dup 1)
9356 (mem:DI (plus:DI (match_dup 1)
9358 (parallel [(set (match_operand 0 "" "")
9359 (call (mem:SI (match_dup 3))
9360 (match_operand 2 "" "")))
9364 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9365 (clobber (scratch:SI))])]
9368 { operands[3] = gen_reg_rtx (DImode); }")
9370 ;; Now the definitions for the call and call_value insns
9371 (define_expand "call"
9372 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9373 (match_operand 1 "" ""))
9374 (use (match_operand 2 "" ""))
9375 (clobber (scratch:SI))])]
9379 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
9382 operands[0] = XEXP (operands[0], 0);
9384 if (GET_CODE (operands[0]) != SYMBOL_REF
9385 || (INTVAL (operands[2]) & CALL_LONG) != 0)
9387 if (INTVAL (operands[2]) & CALL_LONG)
9388 operands[0] = rs6000_longcall_ref (operands[0]);
9390 if (DEFAULT_ABI == ABI_V4
9391 || DEFAULT_ABI == ABI_AIX_NODESC
9392 || DEFAULT_ABI == ABI_SOLARIS)
9393 operands[0] = force_reg (Pmode, operands[0]);
9395 else if (DEFAULT_ABI == ABI_AIX)
9397 /* AIX function pointers are really pointers to a three word
9399 emit_call_insn (TARGET_32BIT
9400 ? gen_call_indirect_aix32 (force_reg (SImode,
9403 : gen_call_indirect_aix64 (force_reg (DImode,
9413 (define_expand "call_value"
9414 [(parallel [(set (match_operand 0 "" "")
9415 (call (mem:SI (match_operand 1 "address_operand" ""))
9416 (match_operand 2 "" "")))
9417 (use (match_operand 3 "" ""))
9418 (clobber (scratch:SI))])]
9422 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
9425 operands[1] = XEXP (operands[1], 0);
9427 if (GET_CODE (operands[1]) != SYMBOL_REF
9428 || (INTVAL (operands[3]) & CALL_LONG) != 0)
9430 if (INTVAL (operands[3]) & CALL_LONG)
9431 operands[1] = rs6000_longcall_ref (operands[1]);
9433 if (DEFAULT_ABI == ABI_V4
9434 || DEFAULT_ABI == ABI_AIX_NODESC
9435 || DEFAULT_ABI == ABI_SOLARIS)
9436 operands[0] = force_reg (Pmode, operands[0]);
9438 else if (DEFAULT_ABI == ABI_AIX)
9440 /* AIX function pointers are really pointers to a three word
9442 emit_call_insn (TARGET_32BIT
9443 ? gen_call_value_indirect_aix32 (operands[0],
9447 : gen_call_value_indirect_aix64 (operands[0],
9458 ;; Call to function in current module. No TOC pointer reload needed.
9459 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9460 ;; either the function was not prototyped, or it was prototyped as a
9461 ;; variable argument function. It is > 0 if FP registers were passed
9462 ;; and < 0 if they were not.
9464 (define_insn "*call_local32"
9465 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9466 (match_operand 1 "" "g,g"))
9467 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9468 (clobber (match_scratch:SI 3 "=l,l"))]
9469 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9472 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9473 output_asm_insn (\"crxor 6,6,6\", operands);
9475 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9476 output_asm_insn (\"creqv 6,6,6\", operands);
9478 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9480 [(set_attr "type" "branch")
9481 (set_attr "length" "4,8")])
9483 (define_insn "*call_local64"
9484 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9485 (match_operand 1 "" "g,g"))
9486 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9487 (clobber (match_scratch:SI 3 "=l,l"))]
9488 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9491 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9492 output_asm_insn (\"crxor 6,6,6\", operands);
9494 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9495 output_asm_insn (\"creqv 6,6,6\", operands);
9497 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9499 [(set_attr "type" "branch")
9500 (set_attr "length" "4,8")])
9502 (define_insn "*call_value_local32"
9503 [(set (match_operand 0 "" "=fg,fg")
9504 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9505 (match_operand 2 "" "g,g")))
9506 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9507 (clobber (match_scratch:SI 4 "=l,l"))]
9508 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9511 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9512 output_asm_insn (\"crxor 6,6,6\", operands);
9514 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9515 output_asm_insn (\"creqv 6,6,6\", operands);
9517 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9519 [(set_attr "type" "branch")
9520 (set_attr "length" "4,8")])
9523 (define_insn "*call_value_local64"
9524 [(set (match_operand 0 "" "=fg,fg")
9525 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9526 (match_operand 2 "" "g,g")))
9527 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9528 (clobber (match_scratch:SI 4 "=l,l"))]
9529 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9532 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9533 output_asm_insn (\"crxor 6,6,6\", operands);
9535 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9536 output_asm_insn (\"creqv 6,6,6\", operands);
9538 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9540 [(set_attr "type" "branch")
9541 (set_attr "length" "4,8")])
9543 ;; Call to function which may be in another module. Restore the TOC
9544 ;; pointer (r2) after the call unless this is System V.
9545 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9546 ;; either the function was not prototyped, or it was prototyped as a
9547 ;; variable argument function. It is > 0 if FP registers were passed
9548 ;; and < 0 if they were not.
9550 (define_insn "*call_indirect_nonlocal_aix32"
9551 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
9552 (match_operand 1 "" "g"))
9556 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9557 (clobber (match_scratch:SI 2 "=l"))]
9558 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9559 "b%T0l\;{l|lwz} 2,20(1)"
9560 [(set_attr "type" "jmpreg")
9561 (set_attr "length" "8")])
9563 (define_insn "*call_nonlocal_aix32"
9564 [(call (mem:SI (match_operand:SI 0 "call_operand" "s"))
9565 (match_operand 1 "" "g"))
9566 (use (match_operand:SI 2 "immediate_operand" "O"))
9567 (clobber (match_scratch:SI 3 "=l"))]
9569 && DEFAULT_ABI == ABI_AIX
9570 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9572 [(set_attr "type" "branch")
9573 (set_attr "length" "8")])
9575 (define_insn "*call_indirect_nonlocal_aix64"
9576 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
9577 (match_operand 1 "" "g"))
9581 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9582 (clobber (match_scratch:SI 2 "=l"))]
9583 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9585 [(set_attr "type" "jmpreg")
9586 (set_attr "length" "8")])
9588 (define_insn "*call_nonlocal_aix64"
9589 [(call (mem:SI (match_operand:DI 0 "call_operand" "s"))
9590 (match_operand 1 "" "g"))
9591 (use (match_operand:SI 2 "immediate_operand" "O"))
9592 (clobber (match_scratch:SI 3 "=l"))]
9594 && DEFAULT_ABI == ABI_AIX
9595 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9597 [(set_attr "type" "branch")
9598 (set_attr "length" "8")])
9600 (define_insn "*call_value_indirect_nonlocal_aix32"
9601 [(set (match_operand 0 "" "=fg")
9602 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
9603 (match_operand 2 "" "g")))
9607 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9608 (clobber (match_scratch:SI 3 "=l"))]
9609 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9610 "b%T1l\;{l|lwz} 2,20(1)"
9611 [(set_attr "type" "jmpreg")
9612 (set_attr "length" "8")])
9614 (define_insn "*call_value_nonlocal_aix32"
9615 [(set (match_operand 0 "" "=fg")
9616 (call (mem:SI (match_operand:SI 1 "call_operand" "s"))
9617 (match_operand 2 "" "g")))
9618 (use (match_operand:SI 3 "immediate_operand" "O"))
9619 (clobber (match_scratch:SI 4 "=l"))]
9621 && DEFAULT_ABI == ABI_AIX
9622 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9624 [(set_attr "type" "branch")
9625 (set_attr "length" "8")])
9627 (define_insn "*call_value_indirect_nonlocal_aix64"
9628 [(set (match_operand 0 "" "=fg")
9629 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
9630 (match_operand 2 "" "g")))
9634 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9635 (clobber (match_scratch:SI 3 "=l"))]
9636 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9638 [(set_attr "type" "jmpreg")
9639 (set_attr "length" "8")])
9641 (define_insn "*call_value_nonlocal_aix64"
9642 [(set (match_operand 0 "" "=fg")
9643 (call (mem:SI (match_operand:DI 1 "call_operand" "s"))
9644 (match_operand 2 "" "g")))
9645 (use (match_operand:SI 3 "immediate_operand" "O"))
9646 (clobber (match_scratch:SI 4 "=l"))]
9648 && DEFAULT_ABI == ABI_AIX
9649 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9651 [(set_attr "type" "branch")
9652 (set_attr "length" "8")])
9654 ;; A function pointer under System V is just a normal pointer
9655 ;; operands[0] is the function pointer
9656 ;; operands[1] is the stack size to clean up
9657 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
9658 ;; which indicates how to set cr1
9660 (define_insn "*call_nonlocal_sysv"
9661 [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s"))
9662 (match_operand 1 "" "g,g,g,g"))
9663 (use (match_operand:SI 2 "immediate_operand" "O,n,O,n"))
9664 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
9665 "DEFAULT_ABI == ABI_AIX_NODESC
9666 || DEFAULT_ABI == ABI_V4
9667 || DEFAULT_ABI == ABI_SOLARIS"
9670 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9671 output_asm_insn (\"crxor 6,6,6\", operands);
9673 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9674 output_asm_insn (\"creqv 6,6,6\", operands);
9676 switch (which_alternative)
9685 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
9688 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
9689 (set_attr "length" "4,8,4,8")])
9691 (define_insn "*call_value_nonlocal_sysv"
9692 [(set (match_operand 0 "" "=fg,fg,fg,fg")
9693 (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s"))
9694 (match_operand 2 "" "g,g,g,g")))
9695 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
9696 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
9697 "DEFAULT_ABI == ABI_AIX_NODESC
9698 || DEFAULT_ABI == ABI_V4
9699 || DEFAULT_ABI == ABI_SOLARIS"
9702 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9703 output_asm_insn (\"crxor 6,6,6\", operands);
9705 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9706 output_asm_insn (\"creqv 6,6,6\", operands);
9708 switch (which_alternative)
9717 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
9720 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
9721 (set_attr "length" "4,8,4,8")])
9723 ;; Call subroutine returning any type.
9724 (define_expand "untyped_call"
9725 [(parallel [(call (match_operand 0 "" "")
9727 (match_operand 1 "" "")
9728 (match_operand 2 "" "")])]
9734 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
9736 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9738 rtx set = XVECEXP (operands[2], 0, i);
9739 emit_move_insn (SET_DEST (set), SET_SRC (set));
9742 /* The optimizer does not know that the call sets the function value
9743 registers we stored in the result block. We avoid problems by
9744 claiming that all hard registers are used and clobbered at this
9746 emit_insn (gen_blockage ());
9751 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9752 ;; all of memory. This blocks insns from being moved across this point.
9754 (define_insn "blockage"
9755 [(unspec_volatile [(const_int 0)] 0)]
9759 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
9760 ;; signed & unsigned, and one type of branch.
9762 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
9763 ;; insns, and branches. We store the operands of compares until we see
9765 (define_expand "cmpsi"
9767 (compare (match_operand:SI 0 "gpc_reg_operand" "")
9768 (match_operand:SI 1 "reg_or_short_operand" "")))]
9772 /* Take care of the possibility that operands[1] might be negative but
9773 this might be a logical operation. That insn doesn't exist. */
9774 if (GET_CODE (operands[1]) == CONST_INT
9775 && INTVAL (operands[1]) < 0)
9776 operands[1] = force_reg (SImode, operands[1]);
9778 rs6000_compare_op0 = operands[0];
9779 rs6000_compare_op1 = operands[1];
9780 rs6000_compare_fp_p = 0;
9784 (define_expand "cmpdi"
9786 (compare (match_operand:DI 0 "gpc_reg_operand" "")
9787 (match_operand:DI 1 "reg_or_short_operand" "")))]
9791 /* Take care of the possibility that operands[1] might be negative but
9792 this might be a logical operation. That insn doesn't exist. */
9793 if (GET_CODE (operands[1]) == CONST_INT
9794 && INTVAL (operands[1]) < 0)
9795 operands[1] = force_reg (DImode, operands[1]);
9797 rs6000_compare_op0 = operands[0];
9798 rs6000_compare_op1 = operands[1];
9799 rs6000_compare_fp_p = 0;
9803 (define_expand "cmpsf"
9804 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
9805 (match_operand:SF 1 "gpc_reg_operand" "")))]
9809 rs6000_compare_op0 = operands[0];
9810 rs6000_compare_op1 = operands[1];
9811 rs6000_compare_fp_p = 1;
9815 (define_expand "cmpdf"
9816 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
9817 (match_operand:DF 1 "gpc_reg_operand" "")))]
9821 rs6000_compare_op0 = operands[0];
9822 rs6000_compare_op1 = operands[1];
9823 rs6000_compare_fp_p = 1;
9827 (define_expand "beq"
9828 [(use (match_operand 0 "" ""))]
9830 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
9832 (define_expand "bne"
9833 [(use (match_operand 0 "" ""))]
9835 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
9837 (define_expand "bge"
9838 [(use (match_operand 0 "" ""))]
9840 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
9842 (define_expand "bgt"
9843 [(use (match_operand 0 "" ""))]
9845 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
9847 (define_expand "ble"
9848 [(use (match_operand 0 "" ""))]
9850 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
9852 (define_expand "blt"
9853 [(use (match_operand 0 "" ""))]
9855 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
9857 (define_expand "bgeu"
9858 [(use (match_operand 0 "" ""))]
9860 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
9862 (define_expand "bgtu"
9863 [(use (match_operand 0 "" ""))]
9865 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
9867 (define_expand "bleu"
9868 [(use (match_operand 0 "" ""))]
9870 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
9872 (define_expand "bltu"
9873 [(use (match_operand 0 "" ""))]
9875 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
9877 (define_expand "bunordered"
9878 [(use (match_operand 0 "" ""))]
9880 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
9882 (define_expand "bordered"
9883 [(use (match_operand 0 "" ""))]
9885 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
9887 (define_expand "buneq"
9888 [(use (match_operand 0 "" ""))]
9890 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
9892 (define_expand "bunge"
9893 [(use (match_operand 0 "" ""))]
9895 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
9897 (define_expand "bungt"
9898 [(use (match_operand 0 "" ""))]
9900 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
9902 (define_expand "bunle"
9903 [(use (match_operand 0 "" ""))]
9905 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
9907 (define_expand "bunlt"
9908 [(use (match_operand 0 "" ""))]
9910 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
9912 (define_expand "bltgt"
9913 [(use (match_operand 0 "" ""))]
9915 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
9917 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
9918 ;; For SEQ, likewise, except that comparisons with zero should be done
9919 ;; with an scc insns. However, due to the order that combine see the
9920 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
9921 ;; the cases we don't want to handle.
9922 (define_expand "seq"
9923 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9925 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
9927 (define_expand "sne"
9928 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9932 if (! rs6000_compare_fp_p)
9935 rs6000_emit_sCOND (NE, operands[0]);
9939 ;; A > 0 is best done using the portable sequence, so fail in that case.
9940 (define_expand "sgt"
9941 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9945 if (! rs6000_compare_fp_p
9946 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9949 rs6000_emit_sCOND (GT, operands[0]);
9953 ;; A < 0 is best done in the portable way for A an integer.
9954 (define_expand "slt"
9955 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9959 if (! rs6000_compare_fp_p
9960 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9963 rs6000_emit_sCOND (LT, operands[0]);
9967 ;; A >= 0 is best done the portable way for A an integer.
9968 (define_expand "sge"
9969 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9973 if (! rs6000_compare_fp_p
9974 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9977 rs6000_emit_sCOND (GE, operands[0]);
9981 ;; A <= 0 is best done the portable way for A an integer.
9982 (define_expand "sle"
9983 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9987 if (! rs6000_compare_fp_p
9988 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9991 rs6000_emit_sCOND (LE, operands[0]);
9995 (define_expand "sgtu"
9996 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9998 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
10000 (define_expand "sltu"
10001 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10003 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
10005 (define_expand "sgeu"
10006 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10008 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
10010 (define_expand "sleu"
10011 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
10013 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
10015 ;; Here are the actual compare insns.
10016 (define_insn "*cmpsi_internal1"
10017 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10018 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10019 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10021 "{cmp%I2|cmpw%I2} %0,%1,%2"
10022 [(set_attr "type" "compare")])
10024 (define_insn "*cmpdi_internal1"
10025 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10026 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
10027 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10030 [(set_attr "type" "compare")])
10032 ;; If we are comparing a register for equality with a large constant,
10033 ;; we can do this with an XOR followed by a compare. But we need a scratch
10034 ;; register for the result of the XOR.
10037 [(set (match_operand:CC 0 "cc_reg_operand" "")
10038 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10039 (match_operand:SI 2 "non_short_cint_operand" "")))
10040 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
10041 "find_single_use (operands[0], insn, 0)
10042 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10043 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10044 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10045 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10048 /* Get the constant we are comparing against, C, and see what it looks like
10049 sign-extended to 16 bits. Then see what constant could be XOR'ed
10050 with C to get the sign-extended value. */
10052 HOST_WIDE_INT c = INTVAL (operands[2]);
10053 HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000);
10054 HOST_WIDE_INT xorv = c ^ sextc;
10056 operands[4] = GEN_INT (xorv);
10057 operands[5] = GEN_INT (sextc);
10060 (define_insn "*cmpsi_internal2"
10061 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10062 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10063 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
10065 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
10066 [(set_attr "type" "compare")])
10068 (define_insn "*cmpdi_internal2"
10069 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10070 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
10071 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
10073 "cmpld%I2 %0,%1,%b2"
10074 [(set_attr "type" "compare")])
10076 ;; The following two insns don't exist as single insns, but if we provide
10077 ;; them, we can swap an add and compare, which will enable us to overlap more
10078 ;; of the required delay between a compare and branch. We generate code for
10079 ;; them by splitting.
10082 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
10083 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10084 (match_operand:SI 2 "short_cint_operand" "i")))
10085 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10086 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10089 [(set_attr "length" "8")])
10092 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10093 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10094 (match_operand:SI 2 "u_short_cint_operand" "i")))
10095 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10096 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10099 [(set_attr "length" "8")])
10102 [(set (match_operand:CC 3 "cc_reg_operand" "")
10103 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10104 (match_operand:SI 2 "short_cint_operand" "")))
10105 (set (match_operand:SI 0 "gpc_reg_operand" "")
10106 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10108 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10109 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10112 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10113 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10114 (match_operand:SI 2 "u_short_cint_operand" "")))
10115 (set (match_operand:SI 0 "gpc_reg_operand" "")
10116 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10118 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10119 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10121 (define_insn "*cmpsf_internal1"
10122 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10123 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10124 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10125 "TARGET_HARD_FLOAT"
10127 [(set_attr "type" "fpcompare")])
10129 (define_insn "*cmpdf_internal1"
10130 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10131 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10132 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10133 "TARGET_HARD_FLOAT"
10135 [(set_attr "type" "fpcompare")])
10137 ;; Now we have the scc insns. We can do some combinations because of the
10138 ;; way the machine works.
10140 ;; Note that this is probably faster if we can put an insn between the
10141 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10142 ;; cases the insns below which don't use an intermediate CR field will
10143 ;; be used instead.
10145 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10146 (match_operator:SI 1 "scc_comparison_operator"
10147 [(match_operand 2 "cc_reg_operand" "y")
10150 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
10151 [(set_attr "length" "12")])
10154 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10155 (match_operator:DI 1 "scc_comparison_operator"
10156 [(match_operand 2 "cc_reg_operand" "y")
10159 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
10160 [(set_attr "length" "12")])
10163 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10164 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10165 [(match_operand 2 "cc_reg_operand" "y,y")
10168 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10169 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10170 "! TARGET_POWERPC64"
10172 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
10174 [(set_attr "type" "delayed_compare")
10175 (set_attr "length" "12,16")])
10178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10179 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10180 [(match_operand 2 "cc_reg_operand" "")
10183 (set (match_operand:SI 3 "gpc_reg_operand" "")
10184 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10185 "! TARGET_POWERPC64 && reload_completed"
10186 [(set (match_dup 3)
10187 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
10189 (compare:CC (match_dup 3)
10194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10195 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10196 [(match_operand 2 "cc_reg_operand" "y")
10198 (match_operand:SI 3 "const_int_operand" "n")))]
10202 int is_bit = ccr_bit (operands[1], 1);
10203 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10206 if (is_bit >= put_bit)
10207 count = is_bit - put_bit;
10209 count = 32 - (put_bit - is_bit);
10211 operands[4] = GEN_INT (count);
10212 operands[5] = GEN_INT (put_bit);
10214 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
10216 [(set_attr "length" "12")])
10219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10221 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10222 [(match_operand 2 "cc_reg_operand" "y,y")
10224 (match_operand:SI 3 "const_int_operand" "n,n"))
10226 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
10227 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10229 "! TARGET_POWERPC64"
10232 int is_bit = ccr_bit (operands[1], 1);
10233 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10236 /* Force split for non-cc0 compare. */
10237 if (which_alternative == 1)
10240 if (is_bit >= put_bit)
10241 count = is_bit - put_bit;
10243 count = 32 - (put_bit - is_bit);
10245 operands[5] = GEN_INT (count);
10246 operands[6] = GEN_INT (put_bit);
10248 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
10250 [(set_attr "type" "delayed_compare")
10251 (set_attr "length" "12,16")])
10254 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10256 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10257 [(match_operand 2 "cc_reg_operand" "")
10259 (match_operand:SI 3 "const_int_operand" ""))
10261 (set (match_operand:SI 4 "gpc_reg_operand" "")
10262 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10264 "! TARGET_POWERPC64 && reload_completed"
10265 [(set (match_dup 4)
10266 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10269 (compare:CC (match_dup 4)
10273 ;; There is a 3 cycle delay between consecutive mfcr instructions
10274 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
10277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10278 (match_operator:SI 1 "scc_comparison_operator"
10279 [(match_operand 2 "cc_reg_operand" "y")
10281 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
10282 (match_operator:SI 4 "scc_comparison_operator"
10283 [(match_operand 5 "cc_reg_operand" "y")
10285 "REGNO (operands[2]) != REGNO (operands[5])"
10286 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10287 [(set_attr "length" "20")])
10290 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10291 (match_operator:DI 1 "scc_comparison_operator"
10292 [(match_operand 2 "cc_reg_operand" "y")
10294 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
10295 (match_operator:DI 4 "scc_comparison_operator"
10296 [(match_operand 5 "cc_reg_operand" "y")
10298 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
10299 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10300 [(set_attr "length" "20")])
10302 ;; There are some scc insns that can be done directly, without a compare.
10303 ;; These are faster because they don't involve the communications between
10304 ;; the FXU and branch units. In fact, we will be replacing all of the
10305 ;; integer scc insns here or in the portable methods in emit_store_flag.
10307 ;; Also support (neg (scc ..)) since that construct is used to replace
10308 ;; branches, (plus (scc ..) ..) since that construct is common and
10309 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
10310 ;; cases where it is no more expensive than (neg (scc ..)).
10312 ;; Have reload force a constant into a register for the simple insns that
10313 ;; otherwise won't accept constants. We do this because it is faster than
10314 ;; the cmp/mfcr sequence we would otherwise generate.
10317 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10318 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10319 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
10320 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
10321 "! TARGET_POWERPC64"
10323 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10324 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
10325 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10326 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10327 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
10328 [(set_attr "length" "12,8,12,12,12")])
10331 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
10332 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
10333 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
10334 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
10337 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
10338 subfic %3,%1,0\;adde %0,%3,%1
10339 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
10340 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
10341 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
10342 [(set_attr "length" "12,8,12,12,12")])
10345 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10347 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10348 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10351 (eq:SI (match_dup 1) (match_dup 2)))
10352 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10353 "! TARGET_POWERPC64"
10355 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10356 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
10357 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10358 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10359 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10365 [(set_attr "type" "compare")
10366 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10369 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10371 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10372 (match_operand:SI 2 "reg_or_cint_operand" ""))
10374 (set (match_operand:SI 0 "gpc_reg_operand" "")
10375 (eq:SI (match_dup 1) (match_dup 2)))
10376 (clobber (match_scratch:SI 3 ""))]
10377 "! TARGET_POWERPC64 && reload_completed"
10378 [(parallel [(set (match_dup 0)
10379 (eq:SI (match_dup 1) (match_dup 2)))
10380 (clobber (match_dup 3))])
10382 (compare:CC (match_dup 0)
10387 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10389 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10390 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
10392 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10393 (eq:DI (match_dup 1) (match_dup 2)))
10394 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10397 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10398 subfic %3,%1,0\;adde. %0,%3,%1
10399 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
10400 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
10401 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10407 [(set_attr "type" "compare")
10408 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10411 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10413 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
10414 (match_operand:DI 2 "reg_or_cint_operand" ""))
10416 (set (match_operand:DI 0 "gpc_reg_operand" "")
10417 (eq:DI (match_dup 1) (match_dup 2)))
10418 (clobber (match_scratch:DI 3 ""))]
10419 "TARGET_POWERPC64 && reload_completed"
10420 [(parallel [(set (match_dup 0)
10421 (eq:DI (match_dup 1) (match_dup 2)))
10422 (clobber (match_dup 3))])
10424 (compare:CC (match_dup 0)
10428 ;; We have insns of the form shown by the first define_insn below. If
10429 ;; there is something inside the comparison operation, we must split it.
10431 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10432 (plus:SI (match_operator 1 "comparison_operator"
10433 [(match_operand:SI 2 "" "")
10434 (match_operand:SI 3
10435 "reg_or_cint_operand" "")])
10436 (match_operand:SI 4 "gpc_reg_operand" "")))
10437 (clobber (match_operand:SI 5 "register_operand" ""))]
10438 "! gpc_reg_operand (operands[2], SImode)"
10439 [(set (match_dup 5) (match_dup 2))
10440 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
10444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10445 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10446 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
10447 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
10448 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
10449 "! TARGET_POWERPC64"
10451 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10452 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
10453 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10454 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10455 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
10456 [(set_attr "length" "12,8,12,12,12")])
10459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10462 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10463 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10464 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10466 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
10467 "! TARGET_POWERPC64"
10469 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10470 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
10471 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10472 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10473 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10479 [(set_attr "type" "compare")
10480 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10483 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10486 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10487 (match_operand:SI 2 "reg_or_cint_operand" ""))
10488 (match_operand:SI 3 "gpc_reg_operand" ""))
10490 (clobber (match_scratch:SI 4 ""))]
10491 "! TARGET_POWERPC64 && reload_completed"
10492 [(set (match_dup 4)
10493 (plus:SI (eq:SI (match_dup 1)
10497 (compare:CC (match_dup 4)
10502 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10505 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10506 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10507 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10509 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10510 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10511 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
10512 "! TARGET_POWERPC64"
10514 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10515 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
10516 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10517 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10518 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10524 [(set_attr "type" "compare")
10525 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10528 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10531 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10532 (match_operand:SI 2 "reg_or_cint_operand" ""))
10533 (match_operand:SI 3 "gpc_reg_operand" ""))
10535 (set (match_operand:SI 0 "gpc_reg_operand" "")
10536 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10537 (clobber (match_scratch:SI 4 ""))]
10538 "! TARGET_POWERPC64 && reload_completed"
10539 [(parallel [(set (match_dup 0)
10540 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10541 (clobber (match_dup 4))])
10543 (compare:CC (match_dup 0)
10548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10549 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10550 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
10551 "! TARGET_POWERPC64"
10553 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10554 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
10555 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10556 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10557 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
10558 [(set_attr "length" "12,8,12,12,12")])
10560 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
10561 ;; since it nabs/sr is just as fast.
10562 (define_insn "*ne0"
10563 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
10564 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10566 (clobber (match_scratch:SI 2 "=&r"))]
10567 "! TARGET_POWER && ! TARGET_POWERPC64"
10568 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
10569 [(set_attr "length" "8")])
10572 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10573 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10575 (clobber (match_scratch:DI 2 "=&r"))]
10577 "addic %2,%1,-1\;subfe %0,%2,%1"
10578 [(set_attr "length" "8")])
10580 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
10582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10583 (plus:SI (lshiftrt:SI
10584 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10586 (match_operand:SI 2 "gpc_reg_operand" "r")))
10587 (clobber (match_scratch:SI 3 "=&r"))]
10588 "! TARGET_POWERPC64"
10589 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
10590 [(set_attr "length" "8")])
10593 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10594 (plus:DI (lshiftrt:DI
10595 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10597 (match_operand:DI 2 "gpc_reg_operand" "r")))
10598 (clobber (match_scratch:DI 3 "=&r"))]
10600 "addic %3,%1,-1\;addze %0,%2"
10601 [(set_attr "length" "8")])
10604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10606 (plus:SI (lshiftrt:SI
10607 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
10609 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
10611 (clobber (match_scratch:SI 3 "=&r,&r"))]
10612 "! TARGET_POWERPC64"
10614 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
10616 [(set_attr "type" "compare")
10617 (set_attr "length" "8,12")])
10620 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10622 (plus:SI (lshiftrt:SI
10623 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10625 (match_operand:SI 2 "gpc_reg_operand" ""))
10627 (clobber (match_scratch:SI 3 ""))]
10628 "! TARGET_POWERPC64 && reload_completed"
10629 [(set (match_dup 3)
10630 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
10634 (compare:CC (match_dup 3)
10639 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10641 (plus:DI (lshiftrt:DI
10642 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
10644 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
10646 (clobber (match_scratch:DI 3 "=&r,&r"))]
10649 addic %3,%1,-1\;addze. %3,%2
10651 [(set_attr "type" "compare")
10652 (set_attr "length" "8,12")])
10655 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10657 (plus:DI (lshiftrt:DI
10658 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10660 (match_operand:DI 2 "gpc_reg_operand" ""))
10662 (clobber (match_scratch:DI 3 ""))]
10663 "TARGET_POWERPC64 && reload_completed"
10664 [(set (match_dup 3)
10665 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
10669 (compare:CC (match_dup 3)
10674 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
10676 (plus:SI (lshiftrt:SI
10677 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
10679 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
10681 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10682 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10684 (clobber (match_scratch:SI 3 "=&r,&r"))]
10685 "! TARGET_POWERPC64"
10687 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
10689 [(set_attr "type" "compare")
10690 (set_attr "length" "8,12")])
10693 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10695 (plus:SI (lshiftrt:SI
10696 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10698 (match_operand:SI 2 "gpc_reg_operand" ""))
10700 (set (match_operand:SI 0 "gpc_reg_operand" "")
10701 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10703 (clobber (match_scratch:SI 3 ""))]
10704 "! TARGET_POWERPC64 && reload_completed"
10705 [(parallel [(set (match_dup 0)
10706 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10708 (clobber (match_dup 3))])
10710 (compare:CC (match_dup 0)
10715 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
10717 (plus:DI (lshiftrt:DI
10718 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
10720 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
10722 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10723 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10725 (clobber (match_scratch:DI 3 "=&r,&r"))]
10728 addic %3,%1,-1\;addze. %0,%2
10730 [(set_attr "type" "compare")
10731 (set_attr "length" "8,12")])
10734 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10736 (plus:DI (lshiftrt:DI
10737 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10739 (match_operand:DI 2 "gpc_reg_operand" ""))
10741 (set (match_operand:DI 0 "gpc_reg_operand" "")
10742 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10744 (clobber (match_scratch:DI 3 ""))]
10745 "TARGET_POWERPC64 && reload_completed"
10746 [(parallel [(set (match_dup 0)
10747 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10749 (clobber (match_dup 3))])
10751 (compare:CC (match_dup 0)
10756 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10757 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10758 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
10759 (clobber (match_scratch:SI 3 "=r,X"))]
10762 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
10763 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
10764 [(set_attr "length" "12")])
10767 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
10769 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10770 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10772 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
10773 (le:SI (match_dup 1) (match_dup 2)))
10774 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
10777 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
10778 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
10781 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
10782 (set_attr "length" "12,12,16,16")])
10785 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10787 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10788 (match_operand:SI 2 "reg_or_short_operand" ""))
10790 (set (match_operand:SI 0 "gpc_reg_operand" "")
10791 (le:SI (match_dup 1) (match_dup 2)))
10792 (clobber (match_scratch:SI 3 ""))]
10793 "TARGET_POWER && reload_completed"
10794 [(parallel [(set (match_dup 0)
10795 (le:SI (match_dup 1) (match_dup 2)))
10796 (clobber (match_dup 3))])
10798 (compare:CC (match_dup 0)
10803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10804 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10805 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
10806 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
10807 (clobber (match_scratch:SI 4 "=&r,&r"))]
10810 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10811 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
10812 [(set_attr "length" "12")])
10815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
10817 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10818 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10819 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
10821 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
10824 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10825 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
10828 [(set_attr "type" "compare")
10829 (set_attr "length" "12,12,16,16")])
10832 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10834 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10835 (match_operand:SI 2 "reg_or_short_operand" ""))
10836 (match_operand:SI 3 "gpc_reg_operand" ""))
10838 (clobber (match_scratch:SI 4 ""))]
10839 "TARGET_POWER && reload_completed"
10840 [(set (match_dup 4)
10841 (plus:SI (le:SI (match_dup 1) (match_dup 2))
10844 (compare:CC (match_dup 4)
10849 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
10851 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10852 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10853 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
10855 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
10856 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10857 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
10860 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10861 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
10864 [(set_attr "type" "compare")
10865 (set_attr "length" "12,12,16,16")])
10868 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10870 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10871 (match_operand:SI 2 "reg_or_short_operand" ""))
10872 (match_operand:SI 3 "gpc_reg_operand" ""))
10874 (set (match_operand:SI 0 "gpc_reg_operand" "")
10875 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10876 (clobber (match_scratch:SI 4 ""))]
10877 "TARGET_POWER && reload_completed"
10878 [(parallel [(set (match_dup 0)
10879 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10880 (clobber (match_dup 4))])
10882 (compare:CC (match_dup 0)
10887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10888 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10889 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
10892 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10893 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
10894 [(set_attr "length" "12")])
10897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10898 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10899 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10900 "! TARGET_POWERPC64"
10901 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
10902 [(set_attr "length" "12")])
10905 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10906 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10907 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10909 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
10910 [(set_attr "length" "12")])
10913 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10915 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10916 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
10918 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10919 (leu:DI (match_dup 1) (match_dup 2)))]
10922 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
10924 [(set_attr "type" "compare")
10925 (set_attr "length" "12,16")])
10928 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
10930 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
10931 (match_operand:DI 2 "reg_or_short_operand" ""))
10933 (set (match_operand:DI 0 "gpc_reg_operand" "")
10934 (leu:DI (match_dup 1) (match_dup 2)))]
10935 "TARGET_POWERPC64 && reload_completed"
10936 [(set (match_dup 0)
10937 (leu:DI (match_dup 1) (match_dup 2)))
10939 (compare:CC (match_dup 0)
10944 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10946 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
10949 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10950 (leu:SI (match_dup 1) (match_dup 2)))]
10951 "! TARGET_POWERPC64"
10953 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
10955 [(set_attr "type" "compare")
10956 (set_attr "length" "12,16")])
10959 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
10961 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10962 (match_operand:SI 2 "reg_or_short_operand" ""))
10964 (set (match_operand:SI 0 "gpc_reg_operand" "")
10965 (leu:SI (match_dup 1) (match_dup 2)))]
10966 "! TARGET_POWERPC64 && reload_completed"
10967 [(set (match_dup 0)
10968 (leu:SI (match_dup 1) (match_dup 2)))
10970 (compare:CC (match_dup 0)
10975 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10977 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10978 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
10980 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10981 (leu:DI (match_dup 1) (match_dup 2)))]
10984 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
10986 [(set_attr "type" "compare")
10987 (set_attr "length" "12,16")])
10990 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10991 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10992 (match_operand:SI 2 "reg_or_short_operand" "rI"))
10993 (match_operand:SI 3 "gpc_reg_operand" "r")))
10994 (clobber (match_scratch:SI 4 "=&r"))]
10995 "! TARGET_POWERPC64"
10996 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
10997 [(set_attr "length" "8")])
11000 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11002 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11003 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11004 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11006 (clobber (match_scratch:SI 4 "=&r,&r"))]
11007 "! TARGET_POWERPC64"
11009 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11011 [(set_attr "type" "compare")
11012 (set_attr "length" "8,12")])
11015 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11017 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11018 (match_operand:SI 2 "reg_or_short_operand" ""))
11019 (match_operand:SI 3 "gpc_reg_operand" ""))
11021 (clobber (match_scratch:SI 4 ""))]
11022 "! TARGET_POWERPC64 && reload_completed"
11023 [(set (match_dup 4)
11024 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11027 (compare:CC (match_dup 4)
11032 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11034 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11035 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11036 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11038 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11039 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11040 (clobber (match_scratch:SI 4 "=&r,&r"))]
11041 "! TARGET_POWERPC64"
11043 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
11045 [(set_attr "type" "compare")
11046 (set_attr "length" "8,12")])
11049 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11051 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11052 (match_operand:SI 2 "reg_or_short_operand" ""))
11053 (match_operand:SI 3 "gpc_reg_operand" ""))
11055 (set (match_operand:SI 0 "gpc_reg_operand" "")
11056 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11057 (clobber (match_scratch:SI 4 ""))]
11058 "! TARGET_POWERPC64 && reload_completed"
11059 [(parallel [(set (match_dup 0)
11060 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11061 (clobber (match_dup 4))])
11063 (compare:CC (match_dup 0)
11068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11069 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11070 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11071 "! TARGET_POWERPC64"
11072 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11073 [(set_attr "length" "12")])
11076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11078 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11079 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11080 (match_operand:SI 3 "gpc_reg_operand" "r")))
11081 (clobber (match_scratch:SI 4 "=&r"))]
11082 "! TARGET_POWERPC64"
11083 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
11084 [(set_attr "length" "12")])
11087 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11090 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11091 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11092 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11094 (clobber (match_scratch:SI 4 "=&r,&r"))]
11095 "! TARGET_POWERPC64"
11097 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11099 [(set_attr "type" "compare")
11100 (set_attr "length" "12,16")])
11103 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11106 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11107 (match_operand:SI 2 "reg_or_short_operand" "")))
11108 (match_operand:SI 3 "gpc_reg_operand" ""))
11110 (clobber (match_scratch:SI 4 ""))]
11111 "! TARGET_POWERPC64 && reload_completed"
11112 [(set (match_dup 4)
11113 (and:SI (neg:SI (leu:SI (match_dup 1)
11117 (compare:CC (match_dup 4)
11122 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11125 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11126 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11127 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11129 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11130 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11131 (clobber (match_scratch:SI 4 "=&r,&r"))]
11132 "! TARGET_POWERPC64"
11134 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11136 [(set_attr "type" "compare")
11137 (set_attr "length" "12,16")])
11140 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11143 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11144 (match_operand:SI 2 "reg_or_short_operand" "")))
11145 (match_operand:SI 3 "gpc_reg_operand" ""))
11147 (set (match_operand:SI 0 "gpc_reg_operand" "")
11148 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11149 (clobber (match_scratch:SI 4 ""))]
11150 "! TARGET_POWERPC64 && reload_completed"
11151 [(parallel [(set (match_dup 0)
11152 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11153 (clobber (match_dup 4))])
11155 (compare:CC (match_dup 0)
11160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11161 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11162 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11164 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11165 [(set_attr "length" "12")])
11168 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11170 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11171 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11173 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11174 (lt:SI (match_dup 1) (match_dup 2)))]
11177 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11179 [(set_attr "type" "delayed_compare")
11180 (set_attr "length" "12,16")])
11183 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11185 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11186 (match_operand:SI 2 "reg_or_short_operand" ""))
11188 (set (match_operand:SI 0 "gpc_reg_operand" "")
11189 (lt:SI (match_dup 1) (match_dup 2)))]
11190 "TARGET_POWER && reload_completed"
11191 [(set (match_dup 0)
11192 (lt:SI (match_dup 1) (match_dup 2)))
11194 (compare:CC (match_dup 0)
11199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11200 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11201 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11202 (match_operand:SI 3 "gpc_reg_operand" "r")))
11203 (clobber (match_scratch:SI 4 "=&r"))]
11205 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
11206 [(set_attr "length" "12")])
11209 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11211 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11212 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11213 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11215 (clobber (match_scratch:SI 4 "=&r,&r"))]
11218 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11220 [(set_attr "type" "compare")
11221 (set_attr "length" "12,16")])
11224 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11226 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11227 (match_operand:SI 2 "reg_or_short_operand" ""))
11228 (match_operand:SI 3 "gpc_reg_operand" ""))
11230 (clobber (match_scratch:SI 4 ""))]
11231 "TARGET_POWER && reload_completed"
11232 [(set (match_dup 4)
11233 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
11236 (compare:CC (match_dup 4)
11241 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11243 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11244 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11245 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11247 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11248 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11249 (clobber (match_scratch:SI 4 "=&r,&r"))]
11252 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
11254 [(set_attr "type" "compare")
11255 (set_attr "length" "12,16")])
11258 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11260 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11261 (match_operand:SI 2 "reg_or_short_operand" ""))
11262 (match_operand:SI 3 "gpc_reg_operand" ""))
11264 (set (match_operand:SI 0 "gpc_reg_operand" "")
11265 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11266 (clobber (match_scratch:SI 4 ""))]
11267 "TARGET_POWER && reload_completed"
11268 [(parallel [(set (match_dup 0)
11269 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11270 (clobber (match_dup 4))])
11272 (compare:CC (match_dup 0)
11277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11278 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11279 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11281 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
11282 [(set_attr "length" "12")])
11285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11286 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11287 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11288 "! TARGET_POWERPC64"
11290 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
11291 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
11292 [(set_attr "length" "12")])
11295 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11297 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11298 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11300 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11301 (ltu:SI (match_dup 1) (match_dup 2)))]
11302 "! TARGET_POWERPC64"
11304 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11305 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11308 [(set_attr "type" "compare")
11309 (set_attr "length" "12,12,16,16")])
11312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11314 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11315 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11317 (set (match_operand:SI 0 "gpc_reg_operand" "")
11318 (ltu:SI (match_dup 1) (match_dup 2)))]
11319 "! TARGET_POWERPC64 && reload_completed"
11320 [(set (match_dup 0)
11321 (ltu:SI (match_dup 1) (match_dup 2)))
11323 (compare:CC (match_dup 0)
11328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11329 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11330 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
11331 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
11332 (clobber (match_scratch:SI 4 "=&r,&r"))]
11333 "! TARGET_POWERPC64"
11335 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
11336 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
11337 [(set_attr "length" "12")])
11340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11342 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11343 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11344 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11346 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11347 "! TARGET_POWERPC64"
11349 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11350 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11353 [(set_attr "type" "compare")
11354 (set_attr "length" "12,12,16,16")])
11357 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11359 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11360 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11361 (match_operand:SI 3 "gpc_reg_operand" ""))
11363 (clobber (match_scratch:SI 4 ""))]
11364 "! TARGET_POWERPC64 && reload_completed"
11365 [(set (match_dup 4)
11366 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
11369 (compare:CC (match_dup 4)
11374 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11376 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11377 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11378 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11380 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11381 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11382 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11383 "! TARGET_POWERPC64"
11385 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11386 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11389 [(set_attr "type" "compare")
11390 (set_attr "length" "12,12,16,16")])
11393 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11395 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11396 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11397 (match_operand:SI 3 "gpc_reg_operand" ""))
11399 (set (match_operand:SI 0 "gpc_reg_operand" "")
11400 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11401 (clobber (match_scratch:SI 4 ""))]
11402 "! TARGET_POWERPC64 && reload_completed"
11403 [(parallel [(set (match_dup 0)
11404 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11405 (clobber (match_dup 4))])
11407 (compare:CC (match_dup 0)
11412 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11413 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11414 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
11415 "! TARGET_POWERPC64"
11417 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
11418 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
11419 [(set_attr "length" "8")])
11422 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11423 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11424 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11425 (clobber (match_scratch:SI 3 "=r"))]
11427 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
11428 [(set_attr "length" "12")])
11431 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11433 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11434 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11436 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11437 (ge:SI (match_dup 1) (match_dup 2)))
11438 (clobber (match_scratch:SI 3 "=r,r"))]
11441 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11443 [(set_attr "type" "compare")
11444 (set_attr "length" "12,16")])
11447 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11449 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11450 (match_operand:SI 2 "reg_or_short_operand" ""))
11452 (set (match_operand:SI 0 "gpc_reg_operand" "")
11453 (ge:SI (match_dup 1) (match_dup 2)))
11454 (clobber (match_scratch:SI 3 ""))]
11455 "TARGET_POWER && reload_completed"
11456 [(parallel [(set (match_dup 0)
11457 (ge:SI (match_dup 1) (match_dup 2)))
11458 (clobber (match_dup 3))])
11460 (compare:CC (match_dup 0)
11465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11466 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11467 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11468 (match_operand:SI 3 "gpc_reg_operand" "r")))
11469 (clobber (match_scratch:SI 4 "=&r"))]
11471 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
11472 [(set_attr "length" "12")])
11475 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11477 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11478 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11479 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11481 (clobber (match_scratch:SI 4 "=&r,&r"))]
11484 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11486 [(set_attr "type" "compare")
11487 (set_attr "length" "12,16")])
11490 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11492 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11493 (match_operand:SI 2 "reg_or_short_operand" ""))
11494 (match_operand:SI 3 "gpc_reg_operand" ""))
11496 (clobber (match_scratch:SI 4 ""))]
11497 "TARGET_POWER && reload_completed"
11498 [(set (match_dup 4)
11499 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
11502 (compare:CC (match_dup 4)
11507 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11509 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11510 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11511 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11513 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11514 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11515 (clobber (match_scratch:SI 4 "=&r,&r"))]
11518 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11520 [(set_attr "type" "compare")
11521 (set_attr "length" "12,16")])
11524 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11526 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11527 (match_operand:SI 2 "reg_or_short_operand" ""))
11528 (match_operand:SI 3 "gpc_reg_operand" ""))
11530 (set (match_operand:SI 0 "gpc_reg_operand" "")
11531 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11532 (clobber (match_scratch:SI 4 ""))]
11533 "TARGET_POWER && reload_completed"
11534 [(parallel [(set (match_dup 0)
11535 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11536 (clobber (match_dup 4))])
11538 (compare:CC (match_dup 0)
11543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11544 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11545 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11547 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11548 [(set_attr "length" "12")])
11551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11552 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11553 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11554 "! TARGET_POWERPC64"
11556 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
11557 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11558 [(set_attr "length" "12")])
11561 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11562 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11563 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
11566 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
11567 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
11568 [(set_attr "length" "12")])
11571 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11573 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11574 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11576 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11577 (geu:SI (match_dup 1) (match_dup 2)))]
11578 "! TARGET_POWERPC64"
11580 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11581 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11584 [(set_attr "type" "compare")
11585 (set_attr "length" "12,12,16,16")])
11588 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11590 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11591 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11593 (set (match_operand:SI 0 "gpc_reg_operand" "")
11594 (geu:SI (match_dup 1) (match_dup 2)))]
11595 "! TARGET_POWERPC64 && reload_completed"
11596 [(set (match_dup 0)
11597 (geu:SI (match_dup 1) (match_dup 2)))
11599 (compare:CC (match_dup 0)
11604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11606 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
11607 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11609 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
11610 (geu:DI (match_dup 1) (match_dup 2)))]
11613 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
11614 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
11617 [(set_attr "type" "compare")
11618 (set_attr "length" "12,12,16,16")])
11621 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11623 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11624 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
11626 (set (match_operand:DI 0 "gpc_reg_operand" "")
11627 (geu:DI (match_dup 1) (match_dup 2)))]
11628 "TARGET_POWERPC64 && reload_completed"
11629 [(set (match_dup 0)
11630 (geu:DI (match_dup 1) (match_dup 2)))
11632 (compare:CC (match_dup 0)
11637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11638 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11639 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
11640 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11641 (clobber (match_scratch:SI 4 "=&r,&r"))]
11642 "! TARGET_POWERPC64"
11644 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
11645 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
11646 [(set_attr "length" "8")])
11649 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11651 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11652 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11653 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11655 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11656 "! TARGET_POWERPC64"
11658 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
11659 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
11662 [(set_attr "type" "compare")
11663 (set_attr "length" "8,8,12,12")])
11666 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11668 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11669 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11670 (match_operand:SI 3 "gpc_reg_operand" ""))
11672 (clobber (match_scratch:SI 4 ""))]
11673 "! TARGET_POWERPC64 && reload_completed"
11674 [(set (match_dup 4)
11675 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
11678 (compare:CC (match_dup 4)
11683 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11685 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11686 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11687 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11689 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11690 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11691 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11692 "! TARGET_POWERPC64"
11694 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
11695 {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3
11698 [(set_attr "type" "compare")
11699 (set_attr "length" "8,8,12,12")])
11702 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11704 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11705 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11706 (match_operand:SI 3 "gpc_reg_operand" ""))
11708 (set (match_operand:SI 0 "gpc_reg_operand" "")
11709 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11710 (clobber (match_scratch:SI 4 ""))]
11711 "! TARGET_POWERPC64 && reload_completed"
11712 [(parallel [(set (match_dup 0)
11713 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11714 (clobber (match_dup 4))])
11716 (compare:CC (match_dup 0)
11721 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11722 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11723 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
11724 "! TARGET_POWERPC64"
11726 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
11727 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
11728 [(set_attr "length" "12")])
11731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11733 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11734 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
11735 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11736 (clobber (match_scratch:SI 4 "=&r,&r"))]
11737 "! TARGET_POWERPC64"
11739 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
11740 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
11741 [(set_attr "length" "12")])
11744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11747 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11748 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
11749 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11751 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11752 "! TARGET_POWERPC64"
11754 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11755 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11758 [(set_attr "type" "compare")
11759 (set_attr "length" "12,12,16,16")])
11762 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11765 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11766 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
11767 (match_operand:SI 3 "gpc_reg_operand" ""))
11769 (clobber (match_scratch:SI 4 ""))]
11770 "! TARGET_POWERPC64 && reload_completed"
11771 [(set (match_dup 4)
11772 (and:SI (neg:SI (geu:SI (match_dup 1)
11776 (compare:CC (match_dup 4)
11781 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11784 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11785 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
11786 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11788 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11789 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11790 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11791 "! TARGET_POWERPC64"
11793 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11794 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11797 [(set_attr "type" "compare")
11798 (set_attr "length" "12,12,16,16")])
11801 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11804 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11805 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
11806 (match_operand:SI 3 "gpc_reg_operand" ""))
11808 (set (match_operand:SI 0 "gpc_reg_operand" "")
11809 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11810 (clobber (match_scratch:SI 4 ""))]
11811 "! TARGET_POWERPC64 && reload_completed"
11812 [(parallel [(set (match_dup 0)
11813 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11814 (clobber (match_dup 4))])
11816 (compare:CC (match_dup 0)
11821 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11822 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11824 "! TARGET_POWERPC64"
11825 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
11826 [(set_attr "length" "12")])
11829 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11830 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11833 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
11834 [(set_attr "length" "12")])
11837 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
11839 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11842 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11843 (gt:SI (match_dup 1) (const_int 0)))]
11844 "! TARGET_POWERPC64"
11846 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
11848 [(set_attr "type" "delayed_compare")
11849 (set_attr "length" "12,16")])
11852 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
11854 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11857 (set (match_operand:SI 0 "gpc_reg_operand" "")
11858 (gt:SI (match_dup 1) (const_int 0)))]
11859 "! TARGET_POWERPC64 && reload_completed"
11860 [(set (match_dup 0)
11861 (gt:SI (match_dup 1) (const_int 0)))
11863 (compare:CC (match_dup 0)
11868 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
11870 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11873 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11874 (gt:DI (match_dup 1) (const_int 0)))]
11877 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
11879 [(set_attr "type" "delayed_compare")
11880 (set_attr "length" "12,16")])
11883 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
11885 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
11888 (set (match_operand:DI 0 "gpc_reg_operand" "")
11889 (gt:DI (match_dup 1) (const_int 0)))]
11890 "TARGET_POWERPC64 && reload_completed"
11891 [(set (match_dup 0)
11892 (gt:DI (match_dup 1) (const_int 0)))
11894 (compare:CC (match_dup 0)
11899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11900 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11901 (match_operand:SI 2 "reg_or_short_operand" "r")))]
11903 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11904 [(set_attr "length" "12")])
11907 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11909 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11910 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
11912 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11913 (gt:SI (match_dup 1) (match_dup 2)))]
11916 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11918 [(set_attr "type" "delayed_compare")
11919 (set_attr "length" "12,16")])
11922 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11924 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11925 (match_operand:SI 2 "reg_or_short_operand" ""))
11927 (set (match_operand:SI 0 "gpc_reg_operand" "")
11928 (gt:SI (match_dup 1) (match_dup 2)))]
11929 "TARGET_POWER && reload_completed"
11930 [(set (match_dup 0)
11931 (gt:SI (match_dup 1) (match_dup 2)))
11933 (compare:CC (match_dup 0)
11938 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11939 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11941 (match_operand:SI 2 "gpc_reg_operand" "r")))
11942 (clobber (match_scratch:SI 3 "=&r"))]
11943 "! TARGET_POWERPC64"
11944 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
11945 [(set_attr "length" "12")])
11948 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11949 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11951 (match_operand:DI 2 "gpc_reg_operand" "r")))
11952 (clobber (match_scratch:DI 3 "=&r"))]
11954 "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
11955 [(set_attr "length" "12")])
11958 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11960 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11962 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11964 (clobber (match_scratch:SI 3 "=&r,&r"))]
11965 "! TARGET_POWERPC64"
11967 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
11969 [(set_attr "type" "compare")
11970 (set_attr "length" "12,16")])
11973 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11975 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11977 (match_operand:SI 2 "gpc_reg_operand" ""))
11979 (clobber (match_scratch:SI 3 ""))]
11980 "! TARGET_POWERPC64 && reload_completed"
11981 [(set (match_dup 3)
11982 (plus:SI (gt:SI (match_dup 1) (const_int 0))
11985 (compare:CC (match_dup 3)
11990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11992 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11994 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11996 (clobber (match_scratch:DI 3 "=&r,&r"))]
11999 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12001 [(set_attr "type" "compare")
12002 (set_attr "length" "12,16")])
12005 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12007 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12009 (match_operand:DI 2 "gpc_reg_operand" ""))
12011 (clobber (match_scratch:DI 3 ""))]
12012 "TARGET_POWERPC64 && reload_completed"
12013 [(set (match_dup 3)
12014 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12017 (compare:CC (match_dup 3)
12022 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12024 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12026 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12028 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12029 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12030 (clobber (match_scratch:SI 3 "=&r,&r"))]
12031 "! TARGET_POWERPC64"
12033 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2
12035 [(set_attr "type" "compare")
12036 (set_attr "length" "12,16")])
12039 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12041 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12043 (match_operand:SI 2 "gpc_reg_operand" ""))
12045 (set (match_operand:SI 0 "gpc_reg_operand" "")
12046 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12047 (clobber (match_scratch:SI 3 ""))]
12048 "! TARGET_POWERPC64 && reload_completed"
12049 [(parallel [(set (match_dup 0)
12050 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12051 (clobber (match_dup 3))])
12053 (compare:CC (match_dup 0)
12058 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12060 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12062 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12064 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12065 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12066 (clobber (match_scratch:DI 3 "=&r,&r"))]
12069 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2
12071 [(set_attr "type" "compare")
12072 (set_attr "length" "12,16")])
12075 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12077 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12079 (match_operand:DI 2 "gpc_reg_operand" ""))
12081 (set (match_operand:DI 0 "gpc_reg_operand" "")
12082 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12083 (clobber (match_scratch:DI 3 ""))]
12084 "TARGET_POWERPC64 && reload_completed"
12085 [(parallel [(set (match_dup 0)
12086 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12087 (clobber (match_dup 3))])
12089 (compare:CC (match_dup 0)
12094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12095 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12096 (match_operand:SI 2 "reg_or_short_operand" "r"))
12097 (match_operand:SI 3 "gpc_reg_operand" "r")))
12098 (clobber (match_scratch:SI 4 "=&r"))]
12100 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
12101 [(set_attr "length" "12")])
12104 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12106 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12107 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12108 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12110 (clobber (match_scratch:SI 4 "=&r,&r"))]
12113 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12115 [(set_attr "type" "compare")
12116 (set_attr "length" "12,16")])
12119 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12121 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12122 (match_operand:SI 2 "reg_or_short_operand" ""))
12123 (match_operand:SI 3 "gpc_reg_operand" ""))
12125 (clobber (match_scratch:SI 4 ""))]
12126 "TARGET_POWER && reload_completed"
12127 [(set (match_dup 4)
12128 (plus:SI (gt:SI (match_dup 1) (match_dup 2))
12131 (compare:CC (match_dup 4)
12136 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
12138 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12139 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12140 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12142 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12143 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12144 (clobber (match_scratch:SI 4 "=&r,&r"))]
12147 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
12149 [(set_attr "type" "compare")
12150 (set_attr "length" "12,16")])
12153 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12155 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12156 (match_operand:SI 2 "reg_or_short_operand" ""))
12157 (match_operand:SI 3 "gpc_reg_operand" ""))
12159 (set (match_operand:SI 0 "gpc_reg_operand" "")
12160 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12161 (clobber (match_scratch:SI 4 ""))]
12162 "TARGET_POWER && reload_completed"
12163 [(parallel [(set (match_dup 0)
12164 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12165 (clobber (match_dup 4))])
12167 (compare:CC (match_dup 0)
12172 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12173 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12175 "! TARGET_POWERPC64"
12176 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
12177 [(set_attr "length" "12")])
12180 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12181 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12184 "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63"
12185 [(set_attr "length" "12")])
12188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12189 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12190 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12192 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12193 [(set_attr "length" "12")])
12196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12197 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12198 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12199 "! TARGET_POWERPC64"
12200 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12201 [(set_attr "length" "12")])
12204 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12205 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12206 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12208 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
12209 [(set_attr "length" "12")])
12212 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12214 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12215 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12217 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12218 (gtu:SI (match_dup 1) (match_dup 2)))]
12219 "! TARGET_POWERPC64"
12221 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12223 [(set_attr "type" "compare")
12224 (set_attr "length" "12,16")])
12227 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12229 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12230 (match_operand:SI 2 "reg_or_short_operand" ""))
12232 (set (match_operand:SI 0 "gpc_reg_operand" "")
12233 (gtu:SI (match_dup 1) (match_dup 2)))]
12234 "! TARGET_POWERPC64 && reload_completed"
12235 [(set (match_dup 0)
12236 (gtu:SI (match_dup 1) (match_dup 2)))
12238 (compare:CC (match_dup 0)
12243 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12245 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12246 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12248 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12249 (gtu:DI (match_dup 1) (match_dup 2)))]
12252 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
12254 [(set_attr "type" "compare")
12255 (set_attr "length" "12,16")])
12258 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12260 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12261 (match_operand:DI 2 "reg_or_short_operand" ""))
12263 (set (match_operand:DI 0 "gpc_reg_operand" "")
12264 (gtu:DI (match_dup 1) (match_dup 2)))]
12265 "TARGET_POWERPC64 && reload_completed"
12266 [(set (match_dup 0)
12267 (gtu:DI (match_dup 1) (match_dup 2)))
12269 (compare:CC (match_dup 0)
12274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12275 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12276 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
12277 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
12278 (clobber (match_scratch:SI 4 "=&r,&r"))]
12279 "! TARGET_POWERPC64"
12281 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
12282 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
12283 [(set_attr "length" "8,12")])
12286 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12287 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12288 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
12289 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))
12290 (clobber (match_scratch:DI 4 "=&r,&r"))]
12293 addic %4,%1,%k2\;addze %0,%3
12294 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
12295 [(set_attr "length" "8,12")])
12298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12300 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12301 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12302 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12304 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12305 "! TARGET_POWERPC64"
12307 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
12308 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12311 [(set_attr "type" "compare")
12312 (set_attr "length" "8,12,12,16")])
12315 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12317 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12318 (match_operand:SI 2 "reg_or_short_operand" ""))
12319 (match_operand:SI 3 "gpc_reg_operand" ""))
12321 (clobber (match_scratch:SI 4 ""))]
12322 "! TARGET_POWERPC64 && reload_completed"
12323 [(set (match_dup 4)
12324 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
12327 (compare:CC (match_dup 4)
12332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12334 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12335 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12336 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12338 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12341 addic %4,%1,%k2\;addze. %4,%3
12342 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
12345 [(set_attr "type" "compare")
12346 (set_attr "length" "8,12,12,16")])
12349 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12351 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12352 (match_operand:DI 2 "reg_or_short_operand" ""))
12353 (match_operand:DI 3 "gpc_reg_operand" ""))
12355 (clobber (match_scratch:DI 4 ""))]
12356 "TARGET_POWERPC64 && reload_completed"
12357 [(set (match_dup 4)
12358 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
12361 (compare:CC (match_dup 4)
12366 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12368 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12369 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12370 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12372 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12373 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12374 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12375 "! TARGET_POWERPC64"
12377 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
12378 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
12381 [(set_attr "type" "compare")
12382 (set_attr "length" "8,12,12,16")])
12385 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12387 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12388 (match_operand:SI 2 "reg_or_short_operand" ""))
12389 (match_operand:SI 3 "gpc_reg_operand" ""))
12391 (set (match_operand:SI 0 "gpc_reg_operand" "")
12392 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12393 (clobber (match_scratch:SI 4 ""))]
12394 "! TARGET_POWERPC64 && reload_completed"
12395 [(parallel [(set (match_dup 0)
12396 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12397 (clobber (match_dup 4))])
12399 (compare:CC (match_dup 0)
12404 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12406 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12407 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12408 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12410 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12411 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12412 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12415 addic %4,%1,%k2\;addze. %0,%3
12416 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3
12419 [(set_attr "type" "compare")
12420 (set_attr "length" "8,12,12,16")])
12423 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12425 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12426 (match_operand:DI 2 "reg_or_short_operand" ""))
12427 (match_operand:DI 3 "gpc_reg_operand" ""))
12429 (set (match_operand:DI 0 "gpc_reg_operand" "")
12430 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12431 (clobber (match_scratch:DI 4 ""))]
12432 "TARGET_POWERPC64 && reload_completed"
12433 [(parallel [(set (match_dup 0)
12434 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12435 (clobber (match_dup 4))])
12437 (compare:CC (match_dup 0)
12442 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12443 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12444 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12445 "! TARGET_POWERPC64"
12446 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12447 [(set_attr "length" "8")])
12450 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12451 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12452 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
12454 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12455 [(set_attr "length" "8")])
12457 ;; Define both directions of branch and return. If we need a reload
12458 ;; register, we'd rather use CR0 since it is much easier to copy a
12459 ;; register CC value to there.
12463 (if_then_else (match_operator 1 "branch_comparison_operator"
12465 "cc_reg_operand" "x,?y")
12467 (label_ref (match_operand 0 "" ""))
12472 return output_cbranch (operands[1], \"%l0\", 0, insn);
12474 [(set_attr "type" "branch")])
12478 (if_then_else (match_operator 0 "branch_comparison_operator"
12480 "cc_reg_operand" "x,?y")
12487 return output_cbranch (operands[0], NULL, 0, insn);
12489 [(set_attr "type" "branch")
12490 (set_attr "length" "4")])
12494 (if_then_else (match_operator 1 "branch_comparison_operator"
12496 "cc_reg_operand" "x,?y")
12499 (label_ref (match_operand 0 "" ""))))]
12503 return output_cbranch (operands[1], \"%l0\", 1, insn);
12505 [(set_attr "type" "branch")])
12509 (if_then_else (match_operator 0 "branch_comparison_operator"
12511 "cc_reg_operand" "x,?y")
12518 return output_cbranch (operands[0], NULL, 1, insn);
12520 [(set_attr "type" "branch")
12521 (set_attr "length" "4")])
12523 ;; Logic on condition register values.
12525 ; This pattern matches things like
12526 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12527 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12529 ; which are generated by the branch logic.
12532 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12533 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12534 [(match_operator:SI 2
12535 "branch_positive_comparison_operator"
12537 "cc_reg_operand" "y")
12539 (match_operator:SI 4
12540 "branch_positive_comparison_operator"
12542 "cc_reg_operand" "y")
12546 "cr%q1 %E0,%j2,%j4"
12547 [(set_attr "type" "cr_logical")])
12549 ; Why is the constant -1 here, but 1 in the previous pattern?
12550 ; Because ~1 has all but the low bit set.
12552 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12553 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12554 [(not:SI (match_operator:SI 2
12555 "branch_positive_comparison_operator"
12557 "cc_reg_operand" "y")
12559 (match_operator:SI 4
12560 "branch_positive_comparison_operator"
12562 "cc_reg_operand" "y")
12566 "cr%q1 %E0,%j2,%j4"
12567 [(set_attr "type" "cr_logical")])
12570 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12571 (compare:CCEQ (match_operator:SI 1
12572 "branch_positive_comparison_operator"
12574 "cc_reg_operand" "y")
12578 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
12579 [(set_attr "type" "cr_logical")])
12581 ;; If we are comparing the result of two comparisons, this can be done
12582 ;; using creqv or crxor.
12584 (define_insn_and_split ""
12585 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12586 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12587 [(match_operand 2 "cc_reg_operand" "y")
12589 (match_operator 3 "branch_comparison_operator"
12590 [(match_operand 4 "cc_reg_operand" "y")
12595 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12599 int positive_1, positive_2;
12601 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
12602 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
12605 operands[1] = gen_rtx (SImode,
12606 rs6000_reverse_condition (GET_MODE (operands[2]),
12607 GET_CODE (operands[1])),
12609 else if (GET_MODE (operands[1]) != SImode)
12610 operands[1] = gen_rtx (SImode,
12611 GET_CODE (operands[1]),
12615 operands[3] = gen_rtx (SImode,
12616 rs6000_reverse_condition (GET_MODE (operands[4]),
12617 GET_CODE (operands[3])),
12619 else if (GET_MODE (operands[3]) != SImode)
12620 operands[3] = gen_rtx (SImode,
12621 GET_CODE (operands[3]),
12624 if (positive_1 == positive_2)
12626 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12627 operands[5] = constm1_rtx;
12631 operands[5] = const1_rtx;
12635 ;; Unconditional branch and return.
12637 (define_insn "jump"
12639 (label_ref (match_operand 0 "" "")))]
12642 [(set_attr "type" "branch")])
12644 (define_insn "return"
12648 [(set_attr "type" "jmpreg")])
12650 (define_expand "indirect_jump"
12651 [(set (pc) (match_operand 0 "register_operand" ""))]
12656 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
12658 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
12662 (define_insn "indirect_jumpsi"
12663 [(set (pc) (match_operand:SI 0 "register_operand" "cl"))]
12666 [(set_attr "type" "jmpreg")])
12668 (define_insn "indirect_jumpdi"
12669 [(set (pc) (match_operand:DI 0 "register_operand" "cl"))]
12672 [(set_attr "type" "jmpreg")])
12674 ;; Table jump for switch statements:
12675 (define_expand "tablejump"
12676 [(use (match_operand 0 "" ""))
12677 (use (label_ref (match_operand 1 "" "")))]
12682 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12684 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12688 (define_expand "tablejumpsi"
12689 [(set (match_dup 3)
12690 (plus:SI (match_operand:SI 0 "" "")
12692 (parallel [(set (pc) (match_dup 3))
12693 (use (label_ref (match_operand 1 "" "")))])]
12696 { operands[0] = force_reg (SImode, operands[0]);
12697 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
12698 operands[3] = gen_reg_rtx (SImode);
12701 (define_expand "tablejumpdi"
12702 [(set (match_dup 4)
12703 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
12705 (plus:DI (match_dup 4)
12707 (parallel [(set (pc) (match_dup 3))
12708 (use (label_ref (match_operand 1 "" "")))])]
12711 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
12712 operands[3] = gen_reg_rtx (DImode);
12713 operands[4] = gen_reg_rtx (DImode);
12718 (match_operand:SI 0 "register_operand" "cl"))
12719 (use (label_ref (match_operand 1 "" "")))]
12722 [(set_attr "type" "jmpreg")])
12726 (match_operand:DI 0 "register_operand" "cl"))
12727 (use (label_ref (match_operand 1 "" "")))]
12730 [(set_attr "type" "jmpreg")])
12735 "{cror 0,0,0|nop}")
12737 ;; Define the subtract-one-and-jump insns, starting with the template
12738 ;; so loop.c knows what to generate.
12740 (define_expand "doloop_end"
12741 [(use (match_operand 0 "" "")) ; loop pseudo
12742 (use (match_operand 1 "" "")) ; iterations; zero if unknown
12743 (use (match_operand 2 "" "")) ; max iterations
12744 (use (match_operand 3 "" "")) ; loop level
12745 (use (match_operand 4 "" ""))] ; label
12749 /* Only use this on innermost loops. */
12750 if (INTVAL (operands[3]) > 1)
12752 if (TARGET_POWERPC64)
12754 if (GET_MODE (operands[0]) != DImode)
12756 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
12760 if (GET_MODE (operands[0]) != SImode)
12762 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
12767 (define_expand "ctrsi"
12768 [(parallel [(set (pc)
12769 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
12771 (label_ref (match_operand 1 "" ""))
12774 (plus:SI (match_dup 0)
12776 (clobber (match_scratch:CC 2 ""))
12777 (clobber (match_scratch:SI 3 ""))])]
12778 "! TARGET_POWERPC64"
12781 (define_expand "ctrdi"
12782 [(parallel [(set (pc)
12783 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
12785 (label_ref (match_operand 1 "" ""))
12788 (plus:DI (match_dup 0)
12790 (clobber (match_scratch:CC 2 ""))
12791 (clobber (match_scratch:DI 3 ""))])]
12795 ;; We need to be able to do this for any operand, including MEM, or we
12796 ;; will cause reload to blow up since we don't allow output reloads on
12798 ;; For the length attribute to be calculated correctly, the
12799 ;; label MUST be operand 0.
12801 (define_insn "*ctrsi_internal1"
12803 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12805 (label_ref (match_operand 0 "" ""))
12807 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12808 (plus:SI (match_dup 1)
12810 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12811 (clobber (match_scratch:SI 4 "=X,X,r"))]
12812 "! TARGET_POWERPC64"
12815 if (which_alternative != 0)
12817 else if (get_attr_length (insn) == 8)
12818 return \"{bdn|bdnz} %l0\";
12820 return \"bdz %$+8\;b %l0\";
12822 [(set_attr "type" "branch")
12823 (set_attr "length" "*,12,16")])
12825 (define_insn "*ctrsi_internal2"
12827 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12830 (label_ref (match_operand 0 "" ""))))
12831 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12832 (plus:SI (match_dup 1)
12834 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12835 (clobber (match_scratch:SI 4 "=X,X,r"))]
12836 "! TARGET_POWERPC64"
12839 if (which_alternative != 0)
12841 else if (get_attr_length (insn) == 8)
12842 return \"bdz %l0\";
12844 return \"{bdn|bdnz} %$+8\;b %l0\";
12846 [(set_attr "type" "branch")
12847 (set_attr "length" "*,12,16")])
12849 (define_insn "*ctrdi_internal1"
12851 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
12853 (label_ref (match_operand 0 "" ""))
12855 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12856 (plus:DI (match_dup 1)
12858 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12859 (clobber (match_scratch:DI 4 "=X,X,r"))]
12863 if (which_alternative != 0)
12865 else if (get_attr_length (insn) == 8)
12866 return \"{bdn|bdnz} %l0\";
12868 return \"bdz %$+8\;b %l0\";
12870 [(set_attr "type" "branch")
12871 (set_attr "length" "*,12,16")])
12873 (define_insn "*ctrdi_internal2"
12875 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
12878 (label_ref (match_operand 0 "" ""))))
12879 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12880 (plus:DI (match_dup 1)
12882 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12883 (clobber (match_scratch:DI 4 "=X,X,r"))]
12887 if (which_alternative != 0)
12889 else if (get_attr_length (insn) == 8)
12890 return \"bdz %l0\";
12892 return \"{bdn|bdnz} %$+8\;b %l0\";
12894 [(set_attr "type" "branch")
12895 (set_attr "length" "*,12,16")])
12897 ;; Similar, but we can use GE since we have a REG_NONNEG.
12899 (define_insn "*ctrsi_internal3"
12901 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12903 (label_ref (match_operand 0 "" ""))
12905 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12906 (plus:SI (match_dup 1)
12908 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12909 (clobber (match_scratch:SI 4 "=X,X,r"))]
12910 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12913 if (which_alternative != 0)
12915 else if (get_attr_length (insn) == 8)
12916 return \"{bdn|bdnz} %l0\";
12918 return \"bdz %$+8\;b %l0\";
12920 [(set_attr "type" "branch")
12921 (set_attr "length" "*,12,16")])
12923 (define_insn "*ctrsi_internal4"
12925 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12928 (label_ref (match_operand 0 "" ""))))
12929 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12930 (plus:SI (match_dup 1)
12932 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12933 (clobber (match_scratch:SI 4 "=X,X,r"))]
12934 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12937 if (which_alternative != 0)
12939 else if (get_attr_length (insn) == 8)
12940 return \"bdz %l0\";
12942 return \"{bdn|bdnz} %$+8\;b %l0\";
12944 [(set_attr "type" "branch")
12945 (set_attr "length" "*,12,16")])
12947 (define_insn "*ctrdi_internal3"
12949 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
12951 (label_ref (match_operand 0 "" ""))
12953 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12954 (plus:DI (match_dup 1)
12956 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12957 (clobber (match_scratch:DI 4 "=X,X,r"))]
12958 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12961 if (which_alternative != 0)
12963 else if (get_attr_length (insn) == 8)
12964 return \"{bdn|bdnz} %l0\";
12966 return \"bdz %$+8\;b %l0\";
12968 [(set_attr "type" "branch")
12969 (set_attr "length" "*,12,16")])
12971 (define_insn "*ctrdi_internal4"
12973 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
12976 (label_ref (match_operand 0 "" ""))))
12977 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12978 (plus:DI (match_dup 1)
12980 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12981 (clobber (match_scratch:DI 4 "=X,X,r"))]
12982 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12985 if (which_alternative != 0)
12987 else if (get_attr_length (insn) == 8)
12988 return \"bdz %l0\";
12990 return \"{bdn|bdnz} %$+8\;b %l0\";
12992 [(set_attr "type" "branch")
12993 (set_attr "length" "*,12,16")])
12995 ;; Similar but use EQ
12997 (define_insn "*ctrsi_internal5"
12999 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13001 (label_ref (match_operand 0 "" ""))
13003 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13004 (plus:SI (match_dup 1)
13006 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13007 (clobber (match_scratch:SI 4 "=X,X,r"))]
13008 "! TARGET_POWERPC64"
13011 if (which_alternative != 0)
13013 else if (get_attr_length (insn) == 8)
13014 return \"bdz %l0\";
13016 return \"{bdn|bdnz} %$+8\;b %l0\";
13018 [(set_attr "type" "branch")
13019 (set_attr "length" "*,12,16")])
13021 (define_insn "*ctrsi_internal6"
13023 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13026 (label_ref (match_operand 0 "" ""))))
13027 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13028 (plus:SI (match_dup 1)
13030 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13031 (clobber (match_scratch:SI 4 "=X,X,r"))]
13032 "! TARGET_POWERPC64"
13035 if (which_alternative != 0)
13037 else if (get_attr_length (insn) == 8)
13038 return \"{bdn|bdnz} %l0\";
13040 return \"bdz %$+8\;b %l0\";
13042 [(set_attr "type" "branch")
13043 (set_attr "length" "*,12,16")])
13045 (define_insn "*ctrdi_internal5"
13047 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
13049 (label_ref (match_operand 0 "" ""))
13051 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
13052 (plus:DI (match_dup 1)
13054 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13055 (clobber (match_scratch:DI 4 "=X,X,r"))]
13059 if (which_alternative != 0)
13061 else if (get_attr_length (insn) == 8)
13062 return \"bdz %l0\";
13064 return \"{bdn|bdnz} %$+8\;b %l0\";
13066 [(set_attr "type" "branch")
13067 (set_attr "length" "*,12,16")])
13069 (define_insn "*ctrdi_internal6"
13071 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
13074 (label_ref (match_operand 0 "" ""))))
13075 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
13076 (plus:DI (match_dup 1)
13078 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13079 (clobber (match_scratch:DI 4 "=X,X,r"))]
13083 if (which_alternative != 0)
13085 else if (get_attr_length (insn) == 8)
13086 return \"{bdn|bdnz} %l0\";
13088 return \"bdz %$+8\;b %l0\";
13090 [(set_attr "type" "branch")
13091 (set_attr "length" "*,12,16")])
13093 ;; Now the splitters if we could not allocate the CTR register
13097 (if_then_else (match_operator 2 "comparison_operator"
13098 [(match_operand:SI 1 "gpc_reg_operand" "")
13100 (match_operand 5 "" "")
13101 (match_operand 6 "" "")))
13102 (set (match_operand:SI 0 "gpc_reg_operand" "")
13103 (plus:SI (match_dup 1)
13105 (clobber (match_scratch:CC 3 ""))
13106 (clobber (match_scratch:SI 4 ""))]
13107 "! TARGET_POWERPC64 && reload_completed"
13108 [(parallel [(set (match_dup 3)
13109 (compare:CC (plus:SI (match_dup 1)
13113 (plus:SI (match_dup 1)
13115 (set (pc) (if_then_else (match_dup 7)
13119 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13124 (if_then_else (match_operator 2 "comparison_operator"
13125 [(match_operand:SI 1 "gpc_reg_operand" "")
13127 (match_operand 5 "" "")
13128 (match_operand 6 "" "")))
13129 (set (match_operand:SI 0 "nonimmediate_operand" "")
13130 (plus:SI (match_dup 1) (const_int -1)))
13131 (clobber (match_scratch:CC 3 ""))
13132 (clobber (match_scratch:SI 4 ""))]
13133 "! TARGET_POWERPC64 && reload_completed
13134 && ! gpc_reg_operand (operands[0], SImode)"
13135 [(parallel [(set (match_dup 3)
13136 (compare:CC (plus:SI (match_dup 1)
13140 (plus:SI (match_dup 1)
13144 (set (pc) (if_then_else (match_dup 7)
13148 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13152 (if_then_else (match_operator 2 "comparison_operator"
13153 [(match_operand:DI 1 "gpc_reg_operand" "")
13155 (match_operand 5 "" "")
13156 (match_operand 6 "" "")))
13157 (set (match_operand:DI 0 "gpc_reg_operand" "")
13158 (plus:DI (match_dup 1)
13160 (clobber (match_scratch:CC 3 ""))
13161 (clobber (match_scratch:DI 4 ""))]
13162 "TARGET_POWERPC64 && reload_completed"
13163 [(parallel [(set (match_dup 3)
13164 (compare:CC (plus:DI (match_dup 1)
13168 (plus:DI (match_dup 1)
13170 (set (pc) (if_then_else (match_dup 7)
13174 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13179 (if_then_else (match_operator 2 "comparison_operator"
13180 [(match_operand:DI 1 "gpc_reg_operand" "")
13182 (match_operand 5 "" "")
13183 (match_operand 6 "" "")))
13184 (set (match_operand:DI 0 "nonimmediate_operand" "")
13185 (plus:DI (match_dup 1) (const_int -1)))
13186 (clobber (match_scratch:CC 3 ""))
13187 (clobber (match_scratch:DI 4 ""))]
13188 "TARGET_POWERPC64 && reload_completed
13189 && ! gpc_reg_operand (operands[0], DImode)"
13190 [(parallel [(set (match_dup 3)
13191 (compare:CC (plus:DI (match_dup 1)
13195 (plus:DI (match_dup 1)
13199 (set (pc) (if_then_else (match_dup 7)
13203 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13206 (define_insn "trap"
13207 [(trap_if (const_int 1) (const_int 0))]
13211 (define_expand "conditional_trap"
13212 [(trap_if (match_operator 0 "trap_comparison_operator"
13213 [(match_dup 2) (match_dup 3)])
13214 (match_operand 1 "const_int_operand" ""))]
13216 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13217 operands[2] = rs6000_compare_op0;
13218 operands[3] = rs6000_compare_op1;")
13221 [(trap_if (match_operator 0 "trap_comparison_operator"
13222 [(match_operand:SI 1 "register_operand" "r")
13223 (match_operand:SI 2 "reg_or_short_operand" "rI")])
13226 "{t|tw}%V0%I2 %1,%2")
13229 [(trap_if (match_operator 0 "trap_comparison_operator"
13230 [(match_operand:DI 1 "register_operand" "r")
13231 (match_operand:DI 2 "reg_or_short_operand" "rI")])
13236 ;; Insns related to generating the function prologue and epilogue.
13238 (define_expand "prologue"
13239 [(use (const_int 0))]
13240 "TARGET_SCHED_PROLOG"
13243 rs6000_emit_prologue ();
13247 (define_insn "movesi_from_cr"
13248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13249 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13250 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
13254 (define_insn "*stmw"
13255 [(match_parallel 0 "stmw_operation"
13256 [(set (match_operand:SI 1 "memory_operand" "=m")
13257 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13259 "{stm|stmw} %2,%1")
13261 (define_insn "*save_fpregs_si"
13262 [(match_parallel 0 "any_operand"
13263 [(clobber (match_operand:SI 1 "register_operand" "=l"))
13264 (use (match_operand:SI 2 "call_operand" "s"))
13265 (set (match_operand:DF 3 "memory_operand" "=m")
13266 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13270 (define_insn "*save_fpregs_di"
13271 [(match_parallel 0 "any_operand"
13272 [(clobber (match_operand:DI 1 "register_operand" "=l"))
13273 (use (match_operand:DI 2 "call_operand" "s"))
13274 (set (match_operand:DF 3 "memory_operand" "=m")
13275 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13279 ; These are to explain that changes to the stack pointer should
13280 ; not be moved over stores to stack memory.
13281 (define_insn "stack_tie"
13282 [(set (match_operand:BLK 0 "memory_operand" "+m")
13283 (unspec:BLK [(match_dup 0)] 5))]
13286 [(set_attr "length" "0")])
13289 (define_expand "epilogue"
13290 [(use (const_int 0))]
13291 "TARGET_SCHED_PROLOG"
13294 rs6000_emit_epilogue (FALSE);
13298 ; On some processors, doing the mtcrf one CC register at a time is
13299 ; faster (like on the 604e). On others, doing them all at once is
13300 ; faster; for instance, on the 601 and 750.
13302 (define_expand "movsi_to_cr_one"
13303 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13304 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13305 (match_dup 2)] 20))]
13307 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13309 (define_insn "*movsi_to_cr"
13310 [(match_parallel 0 "mtcrf_operation"
13311 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13312 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13313 (match_operand 3 "immediate_operand" "n")]
13320 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13321 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13322 operands[4] = GEN_INT (mask);
13323 return \"mtcrf %4,%2\";
13327 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13328 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13329 (match_operand 2 "immediate_operand" "n")] 20))]
13330 "GET_CODE (operands[0]) == REG
13331 && CR_REGNO_P (REGNO (operands[0]))
13332 && GET_CODE (operands[2]) == CONST_INT
13333 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13336 ; The load-multiple instructions have similar properties.
13337 ; Note that "load_multiple" is a name known to the machine-independent
13338 ; code that actually corresponds to the powerpc load-string.
13340 (define_insn "*lmw"
13341 [(match_parallel 0 "lmw_operation"
13342 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13343 (match_operand:SI 2 "memory_operand" "m"))])]
13347 (define_insn "*return_internal_si"
13349 (use (match_operand:SI 0 "register_operand" "lc"))]
13352 [(set_attr "type" "jmpreg")])
13354 (define_insn "*return_internal_di"
13356 (use (match_operand:DI 0 "register_operand" "lc"))]
13359 [(set_attr "type" "jmpreg")])
13361 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13362 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
13364 (define_insn "*return_and_restore_fpregs_si"
13365 [(match_parallel 0 "any_operand"
13367 (use (match_operand:SI 1 "register_operand" "l"))
13368 (use (match_operand:SI 2 "call_operand" "s"))
13369 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13370 (match_operand:DF 4 "memory_operand" "m"))])]
13374 (define_insn "*return_and_restore_fpregs_di"
13375 [(match_parallel 0 "any_operand"
13377 (use (match_operand:DI 1 "register_operand" "l"))
13378 (use (match_operand:DI 2 "call_operand" "s"))
13379 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13380 (match_operand:DF 4 "memory_operand" "m"))])]
13384 ; This is used in compiling the routines __throw and __rethrow.
13385 ; It's a little different to the usual definition...
13387 (define_expand "eh_epilogue"
13388 [(use (match_operand 0 "general_operand" "r"))
13389 (use (match_operand 1 "general_operand" "r"))
13390 (use (match_operand 2 "general_operand" "c"))]
13394 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13397 /* This is required for binary compatibility. If it's wrong,
13398 it probably means that eh_regs() in except.c is broken. */
13399 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 3)
13402 /* These can be anything that doesn't interfere with the epilogue. */
13403 if (GET_CODE (operands[1]) != REG || REGNO (operands[1]) != 4)
13405 rtx r = gen_rtx_REG (Pmode, 4);
13406 emit_move_insn (r, operands[1]);
13410 if (GET_CODE (operands[2]) != REG
13411 || REGNO (operands[2]) != COUNT_REGISTER_REGNUM)
13413 rtx r = gen_rtx_REG (Pmode, COUNT_REGISTER_REGNUM);
13414 emit_move_insn (r, operands[2]);
13419 rs6000_emit_eh_toc_restore (operands[1]);
13422 emit_insn (gen_eh_reg_restore ());
13424 if (Pmode == SImode)
13425 emit_insn (gen_addsi3 (stack_reg, stack_reg, operands[1]));
13427 emit_insn (gen_adddi3 (stack_reg, stack_reg, operands[1]));
13429 if (Pmode == SImode)
13430 insn = emit_jump_insn (gen_return_eh_si (operands[2]));
13432 insn = emit_jump_insn (gen_return_eh_di (operands[2]));
13433 emit_barrier_after (insn);
13438 ; We can't expand this before we know which registers are restored,
13439 ; but we do want to expand it before flow2 because that way flow2 can
13440 ; remove the redundant loads of the link register.
13441 (define_expand "eh_reg_restore"
13442 [(unspec_volatile [(const_int 0)] 9)]
13447 [(unspec_volatile [(const_int 0)] 9)]
13448 "reload_completed && TARGET_SCHED_PROLOG"
13449 [(unspec_volatile [(const_int 0)] 9)]
13452 rs6000_emit_epilogue (TRUE);
13457 [(unspec_volatile [(const_int 0)] 9)]
13461 if (TARGET_SCHED_PROLOG)
13464 /* This is slightly ugly, but at least we don't have multiple
13465 copies of the epilogue-emitting code. */
13468 /* A NOTE_INSN_DELETED is supposed to be at the start
13469 and end of the \"toplevel\" insn chain. */
13470 emit_note (0, NOTE_INSN_DELETED);
13471 rs6000_emit_epilogue (TRUE);
13472 emit_note (0, NOTE_INSN_DELETED);
13474 if (TARGET_DEBUG_STACK)
13475 debug_rtx_list (get_insns(), 100);
13476 final (get_insns(), asm_out_file, FALSE, FALSE);
13482 (define_insn "return_eh_si"
13484 (use (match_operand:SI 0 "register_operand" "lc"))
13489 [(set_attr "type" "jmpreg")])
13491 (define_insn "return_eh_di"
13493 (use (match_operand:DI 0 "register_operand" "lc"))
13498 [(set_attr "type" "jmpreg")])