1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2024 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/rs6000/rs6000-opts.h"
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
35 #include "config/rs6000/rs6000-modes.h"
38 /* Definitions for the object file format. These are set at
41 #define OBJECT_XCOFF 1
43 #define OBJECT_MACHO 4
45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
54 #define TARGET_AIX_OS 0
57 /* Turn off TOC support if pc-relative addressing is used. */
58 #define TARGET_TOC (TARGET_HAS_TOC && !TARGET_PCREL)
60 /* On 32-bit systems without a TOC or pc-relative addressing, we need to use
61 ADDIS/ADDI to load up the address of a symbol. */
62 #define TARGET_NO_TOC_OR_PCREL (!TARGET_HAS_TOC && !TARGET_PCREL)
64 /* Control whether function entry points use a "dot" symbol when
68 /* Default string to use for cpu if not specified. */
69 #ifndef TARGET_CPU_DEFAULT
70 #define TARGET_CPU_DEFAULT ((char *)0)
73 /* If configured for PPC405, support PPC405CR Erratum77. */
74 #ifdef CONFIG_PPC405CR
75 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
77 #define PPC405_ERRATUM77 0
80 #ifndef SUBTARGET_DRIVER_SELF_SPECS
81 # define SUBTARGET_DRIVER_SELF_SPECS ""
84 /* Only for use in the testsuite: -mdejagnu-cpu=<value> filters out all
85 -mcpu= as well as -mtune= options then simply adds -mcpu=<value>,
86 while -mdejagnu-tune=<value> filters out all -mtune= options then
87 simply adds -mtune=<value>.
88 With older versions of Dejagnu the command line arguments you set in
89 RUNTESTFLAGS override those set in the testcases; with these options,
90 the testcase will always win. */
91 #define DRIVER_SELF_SPECS \
92 "%{mdejagnu-cpu=*: %<mcpu=* %<mtune=* -mcpu=%*}", \
93 "%{mdejagnu-tune=*: %<mtune=* -mtune=%*}", \
94 "%{mdejagnu-*: %<mdejagnu-*}", \
95 SUBTARGET_DRIVER_SELF_SPECS
98 #define ASM_OPT_ANY ""
100 #define ASM_OPT_ANY " -many"
103 /* Common ASM definitions used by ASM_SPEC among the various targets for
104 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.cc to
105 provide the default assembler options if the user uses -mcpu=native, so if
106 you make changes here, make them also there. */
107 #define ASM_CPU_SPEC \
108 "%{mcpu=native: %(asm_cpu_native); \
109 mcpu=power11: -mpower11; \
110 mcpu=power10: -mpower10; \
111 mcpu=power9: -mpower9; \
112 mcpu=power8|mcpu=powerpc64le: -mpower8; \
113 mcpu=power7: -mpower7; \
114 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
115 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
116 mcpu=power5+: -mpower5; \
117 mcpu=power5: -mpower5; \
118 mcpu=power4: -mpower4; \
119 mcpu=power3: -mppc64; \
120 mcpu=powerpc: -mppc; \
121 mcpu=powerpc64: -mppc64; \
124 mcpu=rs64: -mppc64; \
140 mcpu=ec603e: -mppc; \
148 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
149 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
150 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
155 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
156 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
159 mcpu=e300c2: -me300; \
160 mcpu=e300c3: -me300; \
161 mcpu=e500mc: -me500mc; \
162 mcpu=e500mc64: -me500mc64; \
163 mcpu=e5500: -me5500; \
164 mcpu=e6500: -me6500; \
165 mcpu=titan: -mtitan; \
166 !mcpu*: %{mcrypto|mdirect-move|mhtm: -mpower8; \
168 mpowerpc64: -mppc64;: %(asm_default)}; \
169 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \
170 %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \
173 #define CPP_DEFAULT_SPEC ""
175 #define ASM_DEFAULT_SPEC ""
176 #define ASM_DEFAULT_EXTRA ""
178 /* This macro defines names of additional specifications to put in the specs
179 that can be used in various specifications like CC1_SPEC. Its definition
180 is an initializer with a subgrouping for each command option.
182 Each subgrouping contains a string constant, that defines the
183 specification name, and a string constant that used by the GCC driver
186 Do not define this macro if it does not need to do anything. */
188 #define SUBTARGET_EXTRA_SPECS
190 #define EXTRA_SPECS \
191 { "cpp_default", CPP_DEFAULT_SPEC }, \
192 { "asm_cpu", ASM_CPU_SPEC }, \
193 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
194 { "asm_default", ASM_DEFAULT_SPEC ASM_DEFAULT_EXTRA }, \
195 { "cc1_cpu", CC1_CPU_SPEC }, \
196 SUBTARGET_EXTRA_SPECS
198 /* -mcpu=native handling only makes sense with compiler running on
199 an PowerPC chip. If changing this condition, also change
200 the condition in driver-rs6000.cc. */
201 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
202 /* In driver-rs6000.cc. */
203 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
204 #define EXTRA_SPEC_FUNCTIONS \
205 { "local_cpu_detect", host_detect_local_cpu },
206 #define HAVE_LOCAL_CPU_DETECT
207 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
210 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
214 #ifdef HAVE_LOCAL_CPU_DETECT
215 #define CC1_CPU_SPEC \
216 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
217 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
219 #define CC1_CPU_SPEC ""
223 /* Architecture type. */
225 /* Define TARGET_MFCRF if the target assembler does not support the
226 optional field operand for mfcr. */
228 #ifndef HAVE_AS_MFCRF
230 #define TARGET_MFCRF 0
233 #ifndef TARGET_SECURE_PLT
234 #define TARGET_SECURE_PLT 0
237 #ifndef TARGET_CMODEL
238 #define TARGET_CMODEL CMODEL_SMALL
241 #define TARGET_32BIT (! TARGET_64BIT)
244 #define HAVE_AS_TLS 0
247 #ifndef HAVE_AS_PLTSEQ
248 #define HAVE_AS_PLTSEQ 0
251 #ifndef TARGET_PLTSEQ
252 #define TARGET_PLTSEQ 0
255 #ifndef TARGET_LINK_STACK
256 #define TARGET_LINK_STACK 0
259 #ifndef SET_TARGET_LINK_STACK
260 #define SET_TARGET_LINK_STACK(X) do { } while (0)
263 #ifndef TARGET_FLOAT128_ENABLE_TYPE
264 #define TARGET_FLOAT128_ENABLE_TYPE 0
267 /* Return 1 for a symbol ref for a thread-local storage symbol. */
268 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
269 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0)
272 /* For libgcc2 we make sure this is a compile time constant */
273 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
274 #undef TARGET_POWERPC64
275 #define TARGET_POWERPC64 1
277 #undef TARGET_POWERPC64
278 #define TARGET_POWERPC64 0
281 /* The option machinery will define this. */
284 #define TARGET_DEFAULT (OPTION_MASK_MULTIPLE)
286 /* Define generic processor types based upon current deployment. */
287 #define PROCESSOR_COMMON PROCESSOR_PPC601
288 #define PROCESSOR_POWERPC PROCESSOR_PPC604
289 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
291 /* Define the default processor. This is overridden by other tm.h files. */
292 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
293 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
295 /* Specify the dialect of assembler to use. Only new mnemonics are supported
296 starting with GCC 4.8, i.e. just one dialect, but for backwards
297 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
299 #define ASSEMBLER_DIALECT 1
302 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
303 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
304 #define MASK_DEBUG_REG 0x04 /* debug register handling */
305 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
306 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
307 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
308 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
309 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
314 | MASK_DEBUG_TARGET \
315 | MASK_DEBUG_BUILTIN)
317 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
318 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
319 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
320 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
321 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
322 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
323 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
325 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
326 long double format that uses a pair of doubles, or IEEE 128-bit floating
327 point. KFmode was added as a way to represent IEEE 128-bit floating point,
328 even if the default for long double is the IBM long double format.
329 Similarly IFmode is the IBM long double format even if the default is IEEE
330 128-bit. Don't allow IFmode if -msoft-float. */
331 #define FLOAT128_IEEE_P(MODE) \
332 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
333 && ((MODE) == TFmode || (MODE) == TCmode)) \
334 || ((MODE) == KFmode) || ((MODE) == KCmode))
336 #define FLOAT128_IBM_P(MODE) \
337 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
338 && ((MODE) == TFmode || (MODE) == TCmode)) \
339 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
341 /* Helper macros to say whether a 128-bit floating point type can go in a
342 single vector register, or whether it needs paired scalar values. */
343 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
345 #define FLOAT128_2REG_P(MODE) \
346 (FLOAT128_IBM_P (MODE) \
347 || ((MODE) == TDmode) \
348 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
350 /* Return true for floating point that does not use a vector register. */
351 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
352 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
354 /* Describe the vector unit used for arithmetic operations. */
355 extern enum rs6000_vector rs6000_vector_unit
[];
357 #define VECTOR_UNIT_NONE_P(MODE) \
358 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
360 #define VECTOR_UNIT_VSX_P(MODE) \
361 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
363 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
364 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
366 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
367 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
369 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
370 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
372 (int)VECTOR_P8_VECTOR))
374 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
375 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
376 compatible, so allow it as well, rather than changing all of the uses of the
378 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
379 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
380 (int)VECTOR_ALTIVEC, \
381 (int)VECTOR_P8_VECTOR))
383 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
384 same unit as the vector unit we are using, but we may want to migrate to
385 using VSX style loads even for types handled by altivec. */
386 extern enum rs6000_vector rs6000_vector_mem
[];
388 #define VECTOR_MEM_NONE_P(MODE) \
389 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
391 #define VECTOR_MEM_VSX_P(MODE) \
392 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
394 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
395 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
397 #define VECTOR_MEM_ALTIVEC_P(MODE) \
398 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
400 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
401 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
403 (int)VECTOR_P8_VECTOR))
405 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
406 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
407 (int)VECTOR_ALTIVEC, \
408 (int)VECTOR_P8_VECTOR))
410 /* Return the alignment of a given vector type, which is set based on the
411 vector unit use. VSX for instance can load 32 or 64 bit aligned words
412 without problems, while Altivec requires 128-bit aligned vectors. */
413 extern int rs6000_vector_align
[];
415 #define VECTOR_ALIGN(MODE) \
416 ((rs6000_vector_align[(MODE)] != 0) \
417 ? rs6000_vector_align[(MODE)] \
418 : (int)GET_MODE_BITSIZE ((MODE)))
420 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
421 with scalar instructions. */
422 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
424 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
425 with the ISA 3.0 MFVSRLD instructions. */
426 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
428 /* Alignment options for fields in structures for sub-targets following
430 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
431 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
433 Override the macro definitions when compiling libobjc to avoid undefined
434 reference to rs6000_alignment_flags due to library's use of GCC alignment
435 macros which use the macros below. */
437 #ifndef IN_TARGET_LIBS
438 #define MASK_ALIGN_POWER 0x00000000
439 #define MASK_ALIGN_NATURAL 0x00000001
440 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
442 #define TARGET_ALIGN_NATURAL 0
445 /* We use values 126..128 to pick the appropriate long double type (IFmode,
447 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
448 #define TARGET_IEEEQUAD rs6000_ieeequad
449 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
450 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
452 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
453 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
454 #define TARGET_FCFID (TARGET_POWERPC64 \
455 || TARGET_PPC_GPOPT /* 970/power4 */ \
456 || TARGET_POPCNTB /* ISA 2.02 */ \
457 || TARGET_CMPB /* ISA 2.05 */ \
458 || TARGET_POPCNTD) /* ISA 2.06 */
460 #define TARGET_FCTIDZ TARGET_FCFID
461 #define TARGET_STFIWX TARGET_PPC_GFXOPT
462 #define TARGET_LFIWAX TARGET_CMPB
463 #define TARGET_LFIWZX TARGET_POPCNTD
464 #define TARGET_FCFIDS TARGET_POPCNTD
465 #define TARGET_FCFIDU TARGET_POPCNTD
466 #define TARGET_FCFIDUS TARGET_POPCNTD
467 #define TARGET_FCTIDUZ TARGET_POPCNTD
468 #define TARGET_FCTIWUZ TARGET_POPCNTD
469 /* Only powerpc64 and powerpc476 support fctid. */
470 #define TARGET_FCTID (TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
471 #define TARGET_CTZ TARGET_MODULO
472 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
473 #define TARGET_MADDLD TARGET_MODULO
475 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
476 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
477 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
478 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
480 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
483 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
484 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
485 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
487 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
488 in power7, so conditionalize them on p8 features. TImode syncs need quad
490 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
491 || TARGET_QUAD_MEMORY_ATOMIC \
492 || TARGET_DIRECT_MOVE)
494 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
496 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
497 to allocate the SDmode stack slot to get the value into the proper location
499 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
501 /* ISA 3.0 has new min/max functions that don't need fast math that are being
502 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
503 answers if the arguments are not in the normal range. */
504 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
505 && (TARGET_P9_MINMAX || !flag_trapping_math))
507 /* In switching from using target_flags to using rs6000_isa_flags, the options
508 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx>
509 options that have not yet been replaced by their OPTION_MASK_<xxx>
510 equivalents are defined here. */
512 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
515 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
519 #define MASK_64BIT OPTION_MASK_64BIT
522 #ifdef TARGET_LITTLE_ENDIAN
523 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
526 /* For power systems, we want to enable Altivec and VSX builtins even if the
527 user did not use -maltivec or -mvsx to allow the builtins to be used inside
528 of #pragma GCC target or the target attribute to change the code level for a
531 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
532 || TARGET_PPC_GPOPT /* 970/power4 */ \
533 || TARGET_POPCNTB /* ISA 2.02 */ \
534 || TARGET_CMPB /* ISA 2.05 */ \
535 || TARGET_POPCNTD /* ISA 2.06 */ \
538 || TARGET_HARD_FLOAT)
540 /* E500 cores only support plain "sync", not lwsync. */
541 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
542 || rs6000_cpu == PROCESSOR_PPC8548)
545 /* Which machine supports the various reciprocal estimate instructions. */
546 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
548 #define TARGET_FRE (TARGET_HARD_FLOAT \
549 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
551 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
552 && TARGET_PPC_GFXOPT)
554 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
555 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
557 /* Macro to say whether we can do optimizations where we need to do parts of
558 the calculation in 64-bit GPRs and then is transfered to the vector
560 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
561 && TARGET_P8_VECTOR \
564 /* Inlining allows targets to define the meanings of bits in target_info
565 field of ipa_fn_summary by itself, the used bits for rs6000 are listed
567 #define RS6000_FN_TARGET_INFO_HTM 1
569 /* Whether the various reciprocal divide/square root estimate instructions
570 exist, and whether we should automatically generate code for the instruction
572 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
573 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
574 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
575 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
577 extern unsigned char rs6000_recip_bits
[];
579 #define RS6000_RECIP_HAVE_RE_P(MODE) \
580 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
582 #define RS6000_RECIP_AUTO_RE_P(MODE) \
583 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
585 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
586 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
588 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
589 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
591 /* The default CPU for TARGET_OPTION_OVERRIDE. */
592 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
595 #define REGISTER_TARGET_PRAGMAS() do { \
596 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
597 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
598 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
599 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
602 /* Target #defines. */
603 #define TARGET_CPU_CPP_BUILTINS() \
604 rs6000_cpu_cpp_builtins (pfile)
606 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
607 we're compiling for. Some configurations may need to override it. */
608 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
611 if (BYTES_BIG_ENDIAN) \
613 builtin_define ("__BIG_ENDIAN__"); \
614 builtin_define ("_BIG_ENDIAN"); \
615 builtin_assert ("machine=bigendian"); \
619 builtin_define ("__LITTLE_ENDIAN__"); \
620 builtin_define ("_LITTLE_ENDIAN"); \
621 builtin_assert ("machine=littleendian"); \
626 /* Target machine storage layout. */
628 /* Define this if most significant bit is lowest numbered
629 in instructions that operate on numbered bit-fields. */
630 /* That is true on RS/6000. */
631 #define BITS_BIG_ENDIAN 1
633 /* Define this if most significant byte of a word is the lowest numbered. */
634 /* That is true on RS/6000. */
635 #define BYTES_BIG_ENDIAN 1
637 /* Define this if most significant word of a multiword number is lowest
640 For RS/6000 we can decide arbitrarily since there are no machine
641 instructions for them. Might as well be consistent with bits and bytes. */
642 #define WORDS_BIG_ENDIAN 1
644 /* This says that for the IBM long double the larger magnitude double
645 comes first. It's really a two element double array, and arrays
646 don't index differently between little- and big-endian. */
647 #define LONG_DOUBLE_LARGE_FIRST 1
649 #define MAX_BITS_PER_WORD 64
651 /* Width of a word, in units (bytes). */
652 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
654 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
656 #define MIN_UNITS_PER_WORD 4
658 #define UNITS_PER_FP_WORD 8
659 #define UNITS_PER_ALTIVEC_WORD 16
660 #define UNITS_PER_VSX_WORD 16
662 /* Type used for ptrdiff_t, as a string used in a declaration. */
663 #define PTRDIFF_TYPE "int"
665 /* Type used for size_t, as a string used in a declaration. */
666 #define SIZE_TYPE "long unsigned int"
668 /* Type used for wchar_t, as a string used in a declaration. */
669 #define WCHAR_TYPE "short unsigned int"
671 /* Width of wchar_t in bits. */
672 #define WCHAR_TYPE_SIZE 16
674 /* A C expression for the size in bits of the type `short' on the
675 target machine. If you don't define this, the default is half a
676 word. (If this would be less than one storage unit, it is
677 rounded up to one unit.) */
678 #define SHORT_TYPE_SIZE 16
680 /* A C expression for the size in bits of the type `int' on the
681 target machine. If you don't define this, the default is one
683 #define INT_TYPE_SIZE 32
685 /* A C expression for the size in bits of the type `long' on the
686 target machine. If you don't define this, the default is one
688 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
690 /* A C expression for the size in bits of the type `long long' on the
691 target machine. If you don't define this, the default is two
693 #define LONG_LONG_TYPE_SIZE 64
695 /* A C expression for the size in bits of the type `float' on the
696 target machine. If you don't define this, the default is one
698 #define FLOAT_TYPE_SIZE 32
700 /* A C expression for the size in bits of the type `double' on the
701 target machine. If you don't define this, the default is two
703 #define DOUBLE_TYPE_SIZE 64
705 /* A C expression for the size in bits of the type `long double' on the target
706 machine. If you don't define this, the default is two words. */
707 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
709 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.cc. */
710 #define WIDEST_HARDWARE_FP_SIZE 64
712 /* Width in bits of a pointer.
713 See also the macro `Pmode' defined below. */
714 extern unsigned rs6000_pointer_size
;
715 #define POINTER_SIZE rs6000_pointer_size
717 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
718 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
720 /* Boundary (in *bits*) on which stack pointer should be aligned. */
721 #define STACK_BOUNDARY \
722 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
725 /* Allocation boundary (in *bits*) for the code of a function. */
726 #define FUNCTION_BOUNDARY 32
728 /* No data type is required to be aligned rounder than this. Warning, if
729 BIGGEST_ALIGNMENT is changed, then this may be an ABI break. An example
730 of where this can break an ABI is in GLIBC's struct _Unwind_Exception. */
731 #define BIGGEST_ALIGNMENT 128
733 /* Alignment of field after `int : 0' in a structure. */
734 #define EMPTY_FIELD_BOUNDARY 32
736 /* Every structure's size must be a multiple of this. */
737 #define STRUCTURE_SIZE_BOUNDARY 8
739 /* A bit-field declared as `int' forces `int' alignment for the struct. */
740 #define PCC_BITFIELD_TYPE_MATTERS 1
742 enum data_align
{ align_abi
, align_opt
, align_both
};
744 /* A C expression to compute the alignment for a variables in the
745 local store. TYPE is the data type, and ALIGN is the alignment
746 that the object would ordinarily have. */
747 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
748 rs6000_data_alignment (TYPE, ALIGN, align_both)
750 /* Make arrays of chars word-aligned for the same reasons. */
751 #define DATA_ALIGNMENT(TYPE, ALIGN) \
752 rs6000_data_alignment (TYPE, ALIGN, align_opt)
754 /* Align vectors to 128 bits. */
755 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
756 rs6000_data_alignment (TYPE, ALIGN, align_abi)
758 /* Nonzero if move instructions will actually fail to work
759 when given unaligned data. */
760 #define STRICT_ALIGNMENT 0
762 /* Standard register usage. */
764 /* Number of actual hardware registers.
765 The hardware registers are assigned numbers for the compiler
766 from 0 to just below FIRST_PSEUDO_REGISTER.
767 All registers that the compiler knows about must be given numbers,
768 even those that are not normally considered general registers.
770 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
771 a count register, a link register, and 8 condition register fields,
772 which we view here as separate registers. AltiVec adds 32 vector
773 registers and a VRsave register.
775 In addition, the difference between the frame and argument pointers is
776 a function of the number of registers saved, so we need to have a
777 register for AP that will later be eliminated in favor of SP or FP.
778 This is a normal register, but it is fixed.
780 We also create a pseudo register for float/int conversions, that will
781 really represent the memory location used. It is represented here as
782 a register, in order to work around problems in allocating stack storage
785 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
786 pointer, which is eventually eliminated in favor of SP or FP. */
788 #define FIRST_PSEUDO_REGISTER 111
790 /* Use standard DWARF numbering for DWARF debugging information. */
791 #define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)
793 /* Use gcc hard register numbering for eh_frame. */
794 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
796 /* Map register numbers held in the call frame info that gcc has
797 collected using DWARF_FRAME_REGNUM to those that should be output in
798 .debug_frame and .eh_frame. */
799 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
800 rs6000_debugger_regno ((REGNO), (FOR_EH) ? 2 : 1)
802 /* 1 for registers that have pervasive standard uses
803 and are not available for the register allocator.
805 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
806 as a local register; for all other OS's r2 is the TOC pointer.
808 On System V implementations, r13 is fixed and not available for use. */
810 #define FIXED_REGISTERS \
812 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
813 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
815 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
816 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
818 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
819 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
823 0, 0, 0, 0, 0, 0, 0, 0, \
824 /* vrsave vscr sfp */ \
828 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
829 the entire set of `FIXED_REGISTERS' be included.
830 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
831 This macro is optional. If not specified, it defaults to the value
832 of `CALL_USED_REGISTERS'. */
834 #define CALL_REALLY_USED_REGISTERS \
836 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
837 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
839 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
840 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
842 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
843 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
847 1, 1, 0, 0, 0, 1, 1, 1, \
848 /* vrsave vscr sfp */ \
852 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
854 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
855 #define FIRST_SAVED_FP_REGNO (14+32)
856 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
858 /* List the order in which to allocate registers. Each register must be
859 listed once, even those in FIXED_REGISTERS.
861 We allocate in the following order:
862 fp0 (not saved or used for anything)
863 fp13 - fp2 (not saved; incoming fp arg registers)
864 fp1 (not saved; return value)
865 fp31 - fp14 (saved; order given to save least number)
866 cr7, cr5 (not saved or special)
867 cr6 (not saved, but used for vector operations)
868 cr1 (not saved, but used for FP operations)
869 cr0 (not saved, but used for arithmetic operations)
870 cr4, cr3, cr2 (saved)
871 r9 (not saved; best for TImode)
872 r10, r8-r4 (not saved; highest first for less conflict with params)
873 r3 (not saved; return value register)
874 r11 (not saved; later alloc to help shrink-wrap)
875 r0 (not saved; cannot be base reg)
876 r31 - r13 (saved; order given to save least number)
877 r12 (not saved; if used for DImode or DFmode would use r13)
878 ctr (not saved; when we have the choice ctr is better)
880 r1, r2, ap, ca (fixed)
881 v0 - v1 (not saved or used for anything)
882 v13 - v3 (not saved; incoming vector arg registers)
883 v2 (not saved; incoming vector arg reg; return value)
884 v19 - v14 (not saved or used for anything)
885 v31 - v20 (saved; order given to save least number)
891 #define MAYBE_R2_AVAILABLE
892 #define MAYBE_R2_FIXED 2,
894 #define MAYBE_R2_AVAILABLE 2,
895 #define MAYBE_R2_FIXED
899 #define EARLY_R12 12,
906 #define REG_ALLOC_ORDER \
908 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
909 /* not use fr14 which is a saved register. */ \
910 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
912 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
913 50, 49, 48, 47, 46, \
914 100, 107, 105, 106, 101, 104, 103, 102, \
916 9, 10, 8, 7, 6, 5, 4, \
917 3, EARLY_R12 11, 0, \
918 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
919 18, 17, 16, 15, 14, 13, LATE_R12 \
921 1, MAYBE_R2_FIXED 99, 98, \
922 /* AltiVec registers. */ \
924 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \
926 83, 82, 81, 80, 79, 78, \
927 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \
932 /* True if register is floating-point. */
933 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
935 /* True if register is a condition register. */
936 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
938 /* True if register is a condition register, but not cr0. */
939 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
941 /* True if register is an integer register. */
942 #define INT_REGNO_P(N) \
943 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
945 /* True if register is the CA register. */
946 #define CA_REGNO_P(N) ((N) == CA_REGNO)
948 /* True if register is an AltiVec register. */
949 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
951 /* True if register is a VSX register. */
952 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
954 /* Alternate name for any vector register supporting floating point, no matter
955 which instruction set(s) are available. */
956 #define VFLOAT_REGNO_P(N) \
957 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
959 /* Alternate name for any vector register supporting integer, no matter which
960 instruction set(s) are available. */
961 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
963 /* Alternate name for any vector register supporting logical operations, no
964 matter which instruction set(s) are available. Allow GPRs as well as the
966 #define VLOGICAL_REGNO_P(N) \
967 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
968 || (TARGET_VSX && FP_REGNO_P (N))) \
970 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
971 enough space to account for vectors in FP regs. However, TFmode/TDmode
972 should not use VSX instructions to do a caller save. */
973 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
974 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
977 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
978 && FP_REGNO_P (REGNO) \
980 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
982 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
984 : choose_hard_reg_mode ((REGNO), (NREGS), NULL))
986 #define VSX_VECTOR_MODE(MODE) \
987 ((MODE) == V4SFmode \
988 || (MODE) == V2DFmode) \
990 /* Modes that are not vectors, but require vector alignment. Treat these like
991 vectors in terms of loads and stores. */
992 #define VECTOR_ALIGNMENT_P(MODE) \
993 (FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode)
995 #define ALTIVEC_VECTOR_MODE(MODE) \
996 ((MODE) == V16QImode \
997 || (MODE) == V8HImode \
998 || (MODE) == V4SFmode \
999 || (MODE) == V4SImode \
1000 || VECTOR_ALIGNMENT_P (MODE))
1002 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1003 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1004 || (MODE) == V2DImode || (MODE) == V1TImode)
1006 /* Post-reload, we can't use any new AltiVec registers, as we already
1007 emitted the vrsave mask. */
1009 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1010 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1012 /* Specify the cost of a branch insn; roughly the number of extra insns that
1013 should be added to avoid a branch.
1015 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1016 unscheduled conditional branch. */
1018 #define BRANCH_COST(speed_p, predictable_p) 3
1020 /* Override BRANCH_COST heuristic which empirically produces worse
1021 performance for removing short circuiting from the logical ops. */
1023 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1025 /* Specify the registers used for certain standard purposes.
1026 The values of these macros are register numbers. */
1028 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1029 /* #define PC_REGNUM */
1031 /* Register to use for pushing function arguments. */
1032 #define STACK_POINTER_REGNUM 1
1034 /* Base register for access to local variables of the function. */
1035 #define HARD_FRAME_POINTER_REGNUM 31
1037 /* Base register for access to local variables of the function. */
1038 #define FRAME_POINTER_REGNUM 110
1040 /* Base register for access to arguments of the function. */
1041 #define ARG_POINTER_REGNUM 99
1043 /* Place to put static chain when calling a function that requires it. */
1044 #define STATIC_CHAIN_REGNUM 11
1046 /* Base register for access to thread local storage variables. */
1047 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1050 /* Define the classes of registers for register constraints in the
1051 machine description. Also define ranges of constants.
1053 One of the classes must always be named ALL_REGS and include all hard regs.
1054 If there is more than one class, another class must be named NO_REGS
1055 and contain no registers.
1057 The name GENERAL_REGS must be the name of a class (or an alias for
1058 another name such as ALL_REGS). This is the class of registers
1059 that is allowed by "g" or "r" in a register constraint.
1060 Also, registers outside this class are allocated only when
1061 instructions express preferences for them.
1063 The classes must be numbered in nondecreasing order; that is,
1064 a larger-numbered class must never be contained completely
1065 in a smaller-numbered class.
1067 For any two classes, it is very desirable that there be another
1068 class that represents their union. */
1070 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1071 condition registers, plus three special registers, CTR, and the link
1072 register. AltiVec adds a vector register class. VSX registers overlap the
1073 FPR registers and the Altivec registers.
1075 However, r0 is special in that it cannot be used as a base register.
1076 So make a class for registers valid as base registers.
1078 Also, cr0 is the only condition code register that can be used in
1079 arithmetic insns, so make a separate class for it. */
1106 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1108 /* Give names of register classes as strings for dump file. */
1110 #define REG_CLASS_NAMES \
1120 "GEN_OR_FLOAT_REGS", \
1121 "GEN_OR_VSX_REGS", \
1124 "LINK_OR_CTR_REGS", \
1126 "SPEC_OR_GEN_REGS", \
1134 /* Define which registers fit in which classes.
1135 This is an initializer for a vector of HARD_REG_SET
1136 of length N_REG_CLASSES. */
1138 #define REG_CLASS_CONTENTS \
1141 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1143 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \
1144 /* GENERAL_REGS. */ \
1145 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \
1147 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1148 /* ALTIVEC_REGS. */ \
1149 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \
1151 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1152 /* VRSAVE_REGS. */ \
1153 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \
1155 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1156 /* GEN_OR_FLOAT_REGS. */ \
1157 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \
1158 /* GEN_OR_VSX_REGS. */ \
1159 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \
1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \
1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \
1164 /* LINK_OR_CTR_REGS. */ \
1165 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \
1166 /* SPECIAL_REGS. */ \
1167 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \
1168 /* SPEC_OR_GEN_REGS. */ \
1169 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \
1171 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \
1173 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \
1174 /* NON_FLOAT_REGS. */ \
1175 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \
1177 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
1179 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
1182 /* The same information, inverted:
1183 Return the class number of the smallest class containing
1184 reg number REGNO. This could be a conditional expression
1185 or could index an array. */
1187 extern enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
1189 #define REGNO_REG_CLASS(REGNO) \
1190 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1191 rs6000_regno_regclass[(REGNO)])
1193 /* Register classes for various constraints that are based on the target
1195 enum r6000_reg_class_enum
{
1196 RS6000_CONSTRAINT_d
, /* FPR registers */
1197 RS6000_CONSTRAINT_v
, /* Altivec registers */
1198 RS6000_CONSTRAINT_wa
, /* Any VSX register */
1199 RS6000_CONSTRAINT_we
, /* VSX register if ISA 3.0 vector. */
1200 RS6000_CONSTRAINT_wr
, /* GPR register if 64-bit */
1201 RS6000_CONSTRAINT_wx
, /* FPR register for STFIWX */
1202 RS6000_CONSTRAINT_wA
, /* BASE_REGS if 64-bit. */
1203 RS6000_CONSTRAINT_MAX
1206 extern enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
1208 /* The class value for index registers, and the one for base regs. */
1209 #define INDEX_REG_CLASS GENERAL_REGS
1210 #define BASE_REG_CLASS BASE_REGS
1212 /* Return whether a given register class can hold VSX objects. */
1213 #define VSX_REG_CLASS_P(CLASS) \
1214 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1216 /* Return whether a given register class targets general purpose registers. */
1217 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1219 /* Given an rtx X being reloaded into a reg required to be
1220 in class CLASS, return the class of reg to actually use.
1221 In general this is just CLASS; but on some machines
1222 in some cases it is preferable to use a more restrictive class.
1224 On the RS/6000, we have to return NO_REGS when we want to reload a
1225 floating-point CONST_DOUBLE to force it to be copied to memory.
1227 We also don't want to reload integer values into floating-point
1228 registers if we can at all help it. In fact, this can
1229 cause reload to die, if it tries to generate a reload of CTR
1230 into a FP register and discovers it doesn't have the memory location
1233 ??? Would it be a good idea to have reload do the converse, that is
1234 try to reload floating modes into FP registers if possible?
1237 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1238 rs6000_preferred_reload_class_ptr (X, CLASS)
1240 /* Return the register class of a scratch register needed to copy IN into
1241 or out of a register in CLASS in MODE. If it can be done directly,
1242 NO_REGS is returned. */
1244 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1245 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1247 /* Return the maximum number of consecutive registers
1248 needed to represent mode MODE in a register of class CLASS.
1250 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1251 a single reg is enough for two words, unless we have VSX, where the FP
1252 registers can hold 128 bits. */
1253 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1255 /* Stack layout; function entry, exit and calling. */
1257 /* Define this if pushing a word on the stack
1258 makes the stack pointer a smaller address. */
1259 #define STACK_GROWS_DOWNWARD 1
1261 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1262 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1264 /* Define this to nonzero if the nominal address of the stack frame
1265 is at the high-address end of the local variables;
1266 that is, each additional local variable allocated
1267 goes at a more negative offset in the frame.
1269 On the RS/6000, we grow upwards, from the area after the outgoing
1271 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1272 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1274 /* Size of the fixed area on the stack */
1275 #define RS6000_SAVE_AREA \
1276 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1277 << (TARGET_64BIT ? 1 : 0))
1279 /* Stack offset for toc save slot. */
1280 #define RS6000_TOC_SAVE_SLOT \
1281 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1283 /* Align an address */
1284 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1286 /* Offset within stack frame to start allocating local variables at.
1287 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1288 first local allocated. Otherwise, it is the offset to the BEGINNING
1289 of the first local allocated.
1291 On the RS/6000, the frame pointer is the same as the stack pointer,
1292 except for dynamic allocations. So we start after the fixed area and
1293 outgoing parameter area.
1295 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1296 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1297 sizes of the fixed area and the parameter area must be a multiple of
1300 #define RS6000_STARTING_FRAME_OFFSET \
1301 (cfun->calls_alloca \
1302 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1303 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1304 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1305 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1306 + RS6000_SAVE_AREA))
1308 /* Offset from the stack pointer register to an item dynamically
1309 allocated on the stack, e.g., by `alloca'.
1311 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1312 length of the outgoing arguments. The default is correct for most
1313 machines. See `function.cc' for details.
1315 This value must be a multiple of STACK_BOUNDARY (hard coded in
1317 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1318 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1319 + STACK_POINTER_OFFSET, \
1320 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1322 /* If we generate an insn to push BYTES bytes,
1323 this says how many the stack pointer really advances by.
1324 On RS/6000, don't define this because there are no push insns. */
1325 /* #define PUSH_ROUNDING(BYTES) */
1327 /* Offset of first parameter from the argument pointer register value.
1328 On the RS/6000, we define the argument pointer to the start of the fixed
1330 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1332 /* Offset from the argument pointer register value to the top of
1333 stack. This is different from FIRST_PARM_OFFSET because of the
1334 register save area. */
1335 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1337 /* Define this if stack space is still allocated for a parameter passed
1338 in a register. The value is the number of bytes allocated to this
1340 #define REG_PARM_STACK_SPACE(FNDECL) \
1341 rs6000_reg_parm_stack_space ((FNDECL), false)
1343 /* Define this macro if space guaranteed when compiling a function body
1344 is different to space required when making a call, a situation that
1345 can arise with K&R style function definitions. */
1346 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1347 rs6000_reg_parm_stack_space ((FNDECL), true)
1349 /* Define this if the above stack space is to be considered part of the
1350 space allocated by the caller. */
1351 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1353 /* This is the difference between the logical top of stack and the actual sp.
1355 For the RS/6000, sp points past the fixed area. */
1356 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1358 /* Define this if the maximum size of all the outgoing args is to be
1359 accumulated and pushed during the prologue. The amount can be
1360 found in the variable crtl->outgoing_args_size. */
1361 #define ACCUMULATE_OUTGOING_ARGS 1
1363 /* Define how to find the value returned by a library function
1364 assuming the value has mode MODE. */
1366 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1368 /* DRAFT_V4_STRUCT_RET defaults off. */
1369 #define DRAFT_V4_STRUCT_RET 0
1371 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1372 #define DEFAULT_PCC_STRUCT_RETURN 0
1374 /* Mode of stack savearea.
1375 FUNCTION is VOIDmode because calling convention maintains SP.
1376 BLOCK needs Pmode for SP.
1377 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1378 #define STACK_SAVEAREA_MODE(LEVEL) \
1379 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1380 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1382 /* Minimum and maximum general purpose registers used to hold arguments. */
1383 #define GP_ARG_MIN_REG 3
1384 #define GP_ARG_MAX_REG 10
1385 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1387 /* Minimum and maximum floating point registers used to hold arguments. */
1388 #define FP_ARG_MIN_REG 33
1389 #define FP_ARG_AIX_MAX_REG 45
1390 #define FP_ARG_V4_MAX_REG 40
1391 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1392 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1393 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1395 /* Minimum and maximum AltiVec registers used to hold arguments. */
1396 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1397 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1398 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1400 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1401 #define AGGR_ARG_NUM_REG 8
1403 /* Return registers */
1404 #define GP_ARG_RETURN GP_ARG_MIN_REG
1405 #define FP_ARG_RETURN FP_ARG_MIN_REG
1406 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1407 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1408 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1409 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1410 ? (ALTIVEC_ARG_RETURN \
1411 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1412 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1414 /* Flags for the call/call_value rtl operations set up by function_arg */
1415 #define CALL_NORMAL 0x00000000 /* no special processing */
1416 /* Bits in 0x00000001 are unused. */
1417 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1418 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1419 #define CALL_LONG 0x00000008 /* always call indirect */
1420 #define CALL_LIBCALL 0x00000010 /* libcall */
1422 /* Identify PLT sequence for rs6000_pltseq_template. */
1423 enum rs6000_pltseq_enum
{
1424 RS6000_PLTSEQ_TOCSAVE
,
1425 RS6000_PLTSEQ_PLT16_HA
,
1426 RS6000_PLTSEQ_PLT16_LO
,
1427 RS6000_PLTSEQ_MTCTR
,
1428 RS6000_PLTSEQ_PLT_PCREL34
1431 #define IS_V4_FP_ARGS(OP) \
1432 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0)
1434 /* We don't have prologue and epilogue functions to save/restore
1435 everything for most ABIs. */
1436 #define WORLD_SAVE_P(INFO) 0
1438 /* 1 if N is a possible register number for a function value
1439 as seen by the caller.
1441 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1442 #define FUNCTION_VALUE_REGNO_P(N) \
1443 ((N) == GP_ARG_RETURN \
1444 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1445 && TARGET_HARD_FLOAT) \
1446 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1447 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1449 /* 1 if N is a possible register number for function argument passing.
1450 On RS/6000, these are r3-r10 and fp1-fp13.
1451 On AltiVec, v2 - v13 are used for passing vectors. */
1452 #define FUNCTION_ARG_REGNO_P(N) \
1453 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1454 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1455 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1456 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1457 && TARGET_HARD_FLOAT))
1459 /* Define a data type for recording info about an argument list
1460 during the scan of that argument list. This data type should
1461 hold all necessary information about the function itself
1462 and about the args processed so far, enough to enable macros
1463 such as FUNCTION_ARG to determine where the next arg should go.
1465 On the RS/6000, this is a structure. The first element is the number of
1466 total argument words, the second is used to store the next
1467 floating-point register number, and the third says how many more args we
1468 have prototype types for.
1470 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1471 the next available GP register, `fregno' is the next available FP
1472 register, and `words' is the number of words used on the stack.
1474 The varargs/stdarg support requires that this structure's size
1475 be a multiple of sizeof(int). */
1477 typedef struct rs6000_args
1479 int words
; /* # words used for passing GP registers */
1480 int fregno
; /* next available FP register */
1481 int vregno
; /* next available AltiVec register */
1482 int nargs_prototype
; /* # args left in the current prototype */
1483 int prototype
; /* Whether a prototype was defined */
1484 int stdarg
; /* Whether function is a stdarg function. */
1485 int call_cookie
; /* Do special things for this call */
1486 int sysv_gregno
; /* next available GP register */
1487 int intoffset
; /* running offset in struct (darwin64) */
1488 int use_stack
; /* any part of struct on stack (darwin64) */
1489 int floats_in_gpr
; /* count of SFmode floats taking up
1490 GPR space (darwin64) */
1491 int named
; /* false for varargs params */
1492 int escapes
; /* if function visible outside tu */
1493 int libcall
; /* If this is a compiler generated call. */
1496 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1497 for a call to a function whose data type is FNTYPE.
1498 For a library call, FNTYPE is 0. */
1500 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1501 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1502 N_NAMED_ARGS, FNDECL, VOIDmode)
1504 /* Similar, but when scanning the definition of a procedure. We always
1505 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1507 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1508 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1509 1000, current_function_decl, VOIDmode)
1511 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1513 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1514 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1517 #define PAD_VARARGS_DOWN \
1518 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1520 /* Output assembler code to FILE to increment profiler label # LABELNO
1521 for profiling a function entry. */
1523 #define FUNCTION_PROFILER(FILE, LABELNO) \
1524 output_function_profiler ((FILE), (LABELNO));
1526 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1527 the stack pointer does not matter. No definition is equivalent to
1530 On the RS/6000, this is nonzero because we can restore the stack from
1531 its backpointer, which we maintain. */
1532 #define EXIT_IGNORE_STACK 1
1534 /* Define this macro as a C expression that is nonzero for registers
1535 that are used by the epilogue or the return' pattern. The stack
1536 and frame pointer registers are already be assumed to be used as
1539 #define EPILOGUE_USES(REGNO) \
1540 ((reload_completed && (REGNO) == LR_REGNO) \
1541 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1542 || (crtl->calls_eh_return \
1547 /* Length in units of the trampoline for entering a nested function. */
1549 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1551 /* Definitions for __builtin_return_address and __builtin_frame_address.
1552 __builtin_return_address (0) should give link register (LR_REGNO), enable
1554 /* This should be uncommented, so that the link register is used, but
1555 currently this would result in unmatched insns and spilling fixed
1556 registers so we'll leave it for another day. When these problems are
1557 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1559 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1561 /* Number of bytes into the frame return addresses can be found. See
1562 rs6000_stack_info in rs6000.cc for more information on how the different
1563 abi's store the return address. */
1564 #define RETURN_ADDRESS_OFFSET \
1565 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1567 /* The current return address is in the link register. The return address
1568 of anything farther back is accessed normally at an offset of 8 from the
1570 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1571 (rs6000_return_addr (COUNT, FRAME))
1574 /* Definitions for register eliminations.
1576 We have two registers that can be eliminated on the RS/6000. First, the
1577 frame pointer register can often be eliminated in favor of the stack
1578 pointer register. Secondly, the argument pointer register can always be
1579 eliminated; it is replaced with either the stack or frame pointer.
1581 In addition, we use the elimination mechanism to see if r30 is needed
1582 Initially we assume that it isn't. If it is, we spill it. This is done
1583 by making it an eliminable register. We replace it with itself so that
1584 if it isn't needed, then existing uses won't be modified. */
1586 /* This is an array of structures. Each structure initializes one pair
1587 of eliminable registers. The "from" register number is given first,
1588 followed by "to". Eliminations of the same "from" register are listed
1589 in order of preference. */
1590 #define ELIMINABLE_REGS \
1591 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1592 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1593 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1594 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1595 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1596 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1598 /* Define the offset between two registers, one to be eliminated, and the other
1599 its replacement, at the start of a routine. */
1600 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1601 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1603 /* Addressing modes, and classification of registers for them. */
1605 #define HAVE_PRE_DECREMENT 1
1606 #define HAVE_PRE_INCREMENT 1
1607 #define HAVE_PRE_MODIFY_DISP 1
1608 #define HAVE_PRE_MODIFY_REG 1
1610 /* Macros to check register numbers against specific register classes. */
1612 /* These assume that REGNO is a hard or pseudo reg number.
1613 They give nonzero only if REGNO is a hard reg of the suitable class
1614 or a pseudo reg currently allocated to a suitable hard reg.
1615 Since they use reg_renumber, they are safe only once reg_renumber
1616 has been allocated, which happens in reginfo.cc during register
1619 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1620 (HARD_REGISTER_NUM_P (REGNO) \
1622 || (REGNO) == ARG_POINTER_REGNUM \
1623 || (REGNO) == FRAME_POINTER_REGNUM \
1624 : (reg_renumber[REGNO] >= 0 \
1625 && (reg_renumber[REGNO] <= 31 \
1626 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1627 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1629 #define REGNO_OK_FOR_BASE_P(REGNO) \
1630 (HARD_REGISTER_NUM_P (REGNO) \
1631 ? ((REGNO) > 0 && (REGNO) <= 31) \
1632 || (REGNO) == ARG_POINTER_REGNUM \
1633 || (REGNO) == FRAME_POINTER_REGNUM \
1634 : (reg_renumber[REGNO] > 0 \
1635 && (reg_renumber[REGNO] <= 31 \
1636 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1637 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1639 /* Nonzero if X is a hard reg that can be used as an index
1640 or if it is a pseudo reg in the non-strict case. */
1641 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1642 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1643 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1645 /* Nonzero if X is a hard reg that can be used as a base reg
1646 or if it is a pseudo reg in the non-strict case. */
1647 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1648 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1649 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1652 /* Maximum number of registers that can appear in a valid memory address. */
1654 #define MAX_REGS_PER_ADDRESS 2
1656 /* Recognize any constant value that is a valid address. */
1658 #define CONSTANT_ADDRESS_P(X) \
1659 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \
1660 || CONST_INT_P (X) || GET_CODE (X) == CONST \
1661 || GET_CODE (X) == HIGH)
1663 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1664 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1665 && EASY_VECTOR_15((n) >> 1) \
1668 #define EASY_VECTOR_MSB(n,mode) \
1669 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1670 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1673 #define FIND_BASE_TERM rs6000_find_base_term
1675 /* The register number of the register used to address a table of
1676 static data addresses in memory. In some cases this register is
1677 defined by a processor's "application binary interface" (ABI).
1678 When this macro is defined, RTL is generated for this register
1679 once, as with the stack pointer and frame pointer registers. If
1680 this macro is not defined, it is up to the machine-dependent files
1681 to allocate such a register (if necessary). */
1683 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1684 #define PIC_OFFSET_TABLE_REGNUM \
1685 (TARGET_TOC ? TOC_REGISTER \
1686 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1689 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1691 /* Define this macro if the register defined by
1692 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1693 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1695 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1697 /* A C expression that is nonzero if X is a legitimate immediate
1698 operand on the target machine when generating position independent
1699 code. You can assume that X satisfies `CONSTANT_P', so you need
1700 not check this. You can also assume FLAG_PIC is true, so you need
1701 not check it either. You need not define this macro if all
1702 constants (including `SYMBOL_REF') can be immediate operands when
1703 generating position independent code. */
1705 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1707 /* Define as C expression which evaluates to nonzero if the tablejump
1708 instruction expects the table to contain offsets from the address of the
1710 Do not define this if the table should contain absolute addresses. */
1711 #define CASE_VECTOR_PC_RELATIVE rs6000_relative_jumptables
1713 /* Specify the machine mode that this machine uses
1714 for the index in the tablejump instruction. */
1715 #define CASE_VECTOR_MODE (rs6000_relative_jumptables ? SImode : Pmode)
1717 /* Define this as 1 if `char' should by default be signed; else as 0. */
1718 #define DEFAULT_SIGNED_CHAR 0
1720 /* An integer expression for the size in bits of the largest integer machine
1721 mode that should actually be used. */
1723 /* Allow pairs of registers to be used, which is the intent of the default. */
1724 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1726 /* Max number of bytes we can move from memory to memory
1727 in one reasonably fast instruction. */
1728 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1729 #define MAX_MOVE_MAX 8
1730 #define MOVE_MAX_PIECES (TARGET_EFFICIENT_UNALIGNED_VSX \
1731 ? 16 : (TARGET_POWERPC64 ? 8 : 4))
1732 #define STORE_MAX_PIECES (TARGET_POWERPC64 ? 8 : 4)
1734 /* Nonzero if access to memory by bytes is no faster than for words.
1735 Also nonzero if doing byte operations (specifically shifts) in registers
1737 #define SLOW_BYTE_ACCESS 1
1739 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1740 will either zero-extend or sign-extend. The value of this macro should
1741 be the code that says which one of the two operations is implicitly
1742 done, UNKNOWN if none. */
1743 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1745 /* Define if loading short immediate values into registers sign extends. */
1746 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1748 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1749 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1750 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1752 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1753 zero. The hardware instructions added in Power9 and the sequences using
1754 popcount return 32 or 64. */
1755 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1756 (TARGET_CTZ || TARGET_POPCNTD \
1757 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1758 : ((VALUE) = -1, 2))
1760 /* Specify the machine mode that pointers have.
1761 After generation of rtl, the compiler makes no further distinction
1762 between pointers and any other objects of this machine mode. */
1763 extern scalar_int_mode rs6000_pmode
;
1764 #define Pmode rs6000_pmode
1766 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1767 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1769 /* Mode of a function address in a call instruction (for indexing purposes).
1770 Doesn't matter on RS/6000. */
1771 #define FUNCTION_MODE SImode
1773 /* Define this if addresses of constant functions
1774 shouldn't be put through pseudo regs where they can be cse'd.
1775 Desirable on machines where ordinary constants are expensive
1776 but a CALL with constant address is cheap. */
1777 #define NO_FUNCTION_CSE 1
1779 /* Define this to be nonzero if shift instructions ignore all but the low-order
1782 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1783 have been dropped from the PowerPC architecture. */
1784 #define SHIFT_COUNT_TRUNCATED 0
1786 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1787 should be adjusted to reflect any required changes. This macro is used when
1788 there is some systematic length adjustment required that would be difficult
1789 to express in the length attribute.
1791 In the PowerPC, we use this to adjust the length of an instruction if one or
1792 more prefixed instructions are generated, using the attribute
1793 num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the
1794 hardware requires that a prefied instruciton does not cross a 64-byte
1795 boundary. This means the compiler has to assume the length of the first
1796 prefixed instruction is 12 bytes instead of 8 bytes. Since the length is
1797 already set for the non-prefixed instruction, we just need to udpate for the
1800 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \
1801 (LENGTH) = rs6000_adjust_insn_length ((INSN), (LENGTH))
1803 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1804 COMPARE, return the mode to be used for the comparison. For
1805 floating-point, CCFPmode should be used. CCUNSmode should be used
1806 for unsigned comparisons. CCEQmode should be used when we are
1807 doing an inequality comparison on the result of a
1808 comparison. CCmode should be used in all other cases. */
1810 #define SELECT_CC_MODE(OP,X,Y) \
1811 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1812 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1813 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1814 ? CCEQmode : CCmode))
1816 /* Can the condition code MODE be safely reversed? This is safe in
1817 all cases on this port, because at present it doesn't use the
1818 trapping FP comparisons (fcmpo). */
1819 #define REVERSIBLE_CC_MODE(MODE) 1
1821 /* Given a condition code and a mode, return the inverse condition. */
1822 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1825 /* Target cpu costs. */
1827 struct processor_costs
{
1828 const int mulsi
; /* cost of SImode multiplication. */
1829 const int mulsi_const
; /* cost of SImode multiplication by constant. */
1830 const int mulsi_const9
; /* cost of SImode mult by short constant. */
1831 const int muldi
; /* cost of DImode multiplication. */
1832 const int divsi
; /* cost of SImode division. */
1833 const int divdi
; /* cost of DImode division. */
1834 const int fp
; /* cost of simple SFmode and DFmode insns. */
1835 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
1836 const int sdiv
; /* cost of SFmode division (fdivs). */
1837 const int ddiv
; /* cost of DFmode division (fdiv). */
1838 const int cache_line_size
; /* cache line size in bytes. */
1839 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
1840 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
1841 const int simultaneous_prefetches
; /* number of parallel prefetch
1843 const int sfdf_convert
; /* cost of SF->DF conversion. */
1846 extern const struct processor_costs
*rs6000_cost
;
1848 /* Control the assembler format that we output. */
1850 /* A C string constant describing how to begin a comment in the target
1851 assembler language. The compiler assumes that the comment will end at
1852 the end of the line. */
1853 #define ASM_COMMENT_START " #"
1855 /* Flag to say the TOC is initialized */
1856 extern int toc_initialized
;
1858 /* Macro to output a special constant pool entry. Go to WIN if we output
1859 it. Otherwise, it is written the usual way.
1861 On the RS/6000, toc entries are handled this way. */
1863 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1864 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1866 output_toc (FILE, X, LABELNO, MODE); \
1871 #ifdef HAVE_GAS_WEAK
1872 #define RS6000_WEAK 1
1874 #define RS6000_WEAK 0
1878 /* Used in lieu of ASM_WEAKEN_LABEL. */
1879 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1880 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
1883 #if HAVE_GAS_WEAKREF
1884 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1887 fputs ("\t.weakref\t", (FILE)); \
1888 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1889 fputs (", ", (FILE)); \
1890 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1891 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1892 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1894 fputs ("\n\t.weakref\t.", (FILE)); \
1895 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1896 fputs (", .", (FILE)); \
1897 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1899 fputc ('\n', (FILE)); \
1903 /* This implements the `alias' attribute. */
1904 #undef ASM_OUTPUT_DEF_FROM_DECLS
1905 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1908 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1909 const char *name = IDENTIFIER_POINTER (TARGET); \
1910 if (TREE_CODE (DECL) == FUNCTION_DECL \
1911 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1913 if (TREE_PUBLIC (DECL)) \
1915 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1917 fputs ("\t.globl\t.", FILE); \
1918 RS6000_OUTPUT_BASENAME (FILE, alias); \
1919 putc ('\n', FILE); \
1922 else if (TARGET_XCOFF) \
1924 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1926 fputs ("\t.lglobl\t.", FILE); \
1927 RS6000_OUTPUT_BASENAME (FILE, alias); \
1928 putc ('\n', FILE); \
1929 fputs ("\t.lglobl\t", FILE); \
1930 RS6000_OUTPUT_BASENAME (FILE, alias); \
1931 putc ('\n', FILE); \
1934 fputs ("\t.set\t.", FILE); \
1935 RS6000_OUTPUT_BASENAME (FILE, alias); \
1936 fputs (",.", FILE); \
1937 RS6000_OUTPUT_BASENAME (FILE, name); \
1938 fputc ('\n', FILE); \
1940 ASM_OUTPUT_DEF (FILE, alias, name); \
1944 #define TARGET_ASM_FILE_START rs6000_file_start
1946 /* Output to assembler file text saying following lines
1947 may contain character constants, extra white space, comments, etc. */
1949 #define ASM_APP_ON ""
1951 /* Output to assembler file text saying following lines
1952 no longer contain unusual constructs. */
1954 #define ASM_APP_OFF ""
1956 /* How to refer to registers in assembler output.
1957 This sequence is indexed by compiler's hard-register-number (see above). */
1959 extern char rs6000_reg_names
[][8]; /* register names (0 vs. %r0). */
1961 #define REGISTER_NAMES \
1963 &rs6000_reg_names[ 0][0], /* r0 */ \
1964 &rs6000_reg_names[ 1][0], /* r1 */ \
1965 &rs6000_reg_names[ 2][0], /* r2 */ \
1966 &rs6000_reg_names[ 3][0], /* r3 */ \
1967 &rs6000_reg_names[ 4][0], /* r4 */ \
1968 &rs6000_reg_names[ 5][0], /* r5 */ \
1969 &rs6000_reg_names[ 6][0], /* r6 */ \
1970 &rs6000_reg_names[ 7][0], /* r7 */ \
1971 &rs6000_reg_names[ 8][0], /* r8 */ \
1972 &rs6000_reg_names[ 9][0], /* r9 */ \
1973 &rs6000_reg_names[10][0], /* r10 */ \
1974 &rs6000_reg_names[11][0], /* r11 */ \
1975 &rs6000_reg_names[12][0], /* r12 */ \
1976 &rs6000_reg_names[13][0], /* r13 */ \
1977 &rs6000_reg_names[14][0], /* r14 */ \
1978 &rs6000_reg_names[15][0], /* r15 */ \
1979 &rs6000_reg_names[16][0], /* r16 */ \
1980 &rs6000_reg_names[17][0], /* r17 */ \
1981 &rs6000_reg_names[18][0], /* r18 */ \
1982 &rs6000_reg_names[19][0], /* r19 */ \
1983 &rs6000_reg_names[20][0], /* r20 */ \
1984 &rs6000_reg_names[21][0], /* r21 */ \
1985 &rs6000_reg_names[22][0], /* r22 */ \
1986 &rs6000_reg_names[23][0], /* r23 */ \
1987 &rs6000_reg_names[24][0], /* r24 */ \
1988 &rs6000_reg_names[25][0], /* r25 */ \
1989 &rs6000_reg_names[26][0], /* r26 */ \
1990 &rs6000_reg_names[27][0], /* r27 */ \
1991 &rs6000_reg_names[28][0], /* r28 */ \
1992 &rs6000_reg_names[29][0], /* r29 */ \
1993 &rs6000_reg_names[30][0], /* r30 */ \
1994 &rs6000_reg_names[31][0], /* r31 */ \
1996 &rs6000_reg_names[32][0], /* fr0 */ \
1997 &rs6000_reg_names[33][0], /* fr1 */ \
1998 &rs6000_reg_names[34][0], /* fr2 */ \
1999 &rs6000_reg_names[35][0], /* fr3 */ \
2000 &rs6000_reg_names[36][0], /* fr4 */ \
2001 &rs6000_reg_names[37][0], /* fr5 */ \
2002 &rs6000_reg_names[38][0], /* fr6 */ \
2003 &rs6000_reg_names[39][0], /* fr7 */ \
2004 &rs6000_reg_names[40][0], /* fr8 */ \
2005 &rs6000_reg_names[41][0], /* fr9 */ \
2006 &rs6000_reg_names[42][0], /* fr10 */ \
2007 &rs6000_reg_names[43][0], /* fr11 */ \
2008 &rs6000_reg_names[44][0], /* fr12 */ \
2009 &rs6000_reg_names[45][0], /* fr13 */ \
2010 &rs6000_reg_names[46][0], /* fr14 */ \
2011 &rs6000_reg_names[47][0], /* fr15 */ \
2012 &rs6000_reg_names[48][0], /* fr16 */ \
2013 &rs6000_reg_names[49][0], /* fr17 */ \
2014 &rs6000_reg_names[50][0], /* fr18 */ \
2015 &rs6000_reg_names[51][0], /* fr19 */ \
2016 &rs6000_reg_names[52][0], /* fr20 */ \
2017 &rs6000_reg_names[53][0], /* fr21 */ \
2018 &rs6000_reg_names[54][0], /* fr22 */ \
2019 &rs6000_reg_names[55][0], /* fr23 */ \
2020 &rs6000_reg_names[56][0], /* fr24 */ \
2021 &rs6000_reg_names[57][0], /* fr25 */ \
2022 &rs6000_reg_names[58][0], /* fr26 */ \
2023 &rs6000_reg_names[59][0], /* fr27 */ \
2024 &rs6000_reg_names[60][0], /* fr28 */ \
2025 &rs6000_reg_names[61][0], /* fr29 */ \
2026 &rs6000_reg_names[62][0], /* fr30 */ \
2027 &rs6000_reg_names[63][0], /* fr31 */ \
2029 &rs6000_reg_names[64][0], /* vr0 */ \
2030 &rs6000_reg_names[65][0], /* vr1 */ \
2031 &rs6000_reg_names[66][0], /* vr2 */ \
2032 &rs6000_reg_names[67][0], /* vr3 */ \
2033 &rs6000_reg_names[68][0], /* vr4 */ \
2034 &rs6000_reg_names[69][0], /* vr5 */ \
2035 &rs6000_reg_names[70][0], /* vr6 */ \
2036 &rs6000_reg_names[71][0], /* vr7 */ \
2037 &rs6000_reg_names[72][0], /* vr8 */ \
2038 &rs6000_reg_names[73][0], /* vr9 */ \
2039 &rs6000_reg_names[74][0], /* vr10 */ \
2040 &rs6000_reg_names[75][0], /* vr11 */ \
2041 &rs6000_reg_names[76][0], /* vr12 */ \
2042 &rs6000_reg_names[77][0], /* vr13 */ \
2043 &rs6000_reg_names[78][0], /* vr14 */ \
2044 &rs6000_reg_names[79][0], /* vr15 */ \
2045 &rs6000_reg_names[80][0], /* vr16 */ \
2046 &rs6000_reg_names[81][0], /* vr17 */ \
2047 &rs6000_reg_names[82][0], /* vr18 */ \
2048 &rs6000_reg_names[83][0], /* vr19 */ \
2049 &rs6000_reg_names[84][0], /* vr20 */ \
2050 &rs6000_reg_names[85][0], /* vr21 */ \
2051 &rs6000_reg_names[86][0], /* vr22 */ \
2052 &rs6000_reg_names[87][0], /* vr23 */ \
2053 &rs6000_reg_names[88][0], /* vr24 */ \
2054 &rs6000_reg_names[89][0], /* vr25 */ \
2055 &rs6000_reg_names[90][0], /* vr26 */ \
2056 &rs6000_reg_names[91][0], /* vr27 */ \
2057 &rs6000_reg_names[92][0], /* vr28 */ \
2058 &rs6000_reg_names[93][0], /* vr29 */ \
2059 &rs6000_reg_names[94][0], /* vr30 */ \
2060 &rs6000_reg_names[95][0], /* vr31 */ \
2062 &rs6000_reg_names[96][0], /* lr */ \
2063 &rs6000_reg_names[97][0], /* ctr */ \
2064 &rs6000_reg_names[98][0], /* ca */ \
2065 &rs6000_reg_names[99][0], /* ap */ \
2067 &rs6000_reg_names[100][0], /* cr0 */ \
2068 &rs6000_reg_names[101][0], /* cr1 */ \
2069 &rs6000_reg_names[102][0], /* cr2 */ \
2070 &rs6000_reg_names[103][0], /* cr3 */ \
2071 &rs6000_reg_names[104][0], /* cr4 */ \
2072 &rs6000_reg_names[105][0], /* cr5 */ \
2073 &rs6000_reg_names[106][0], /* cr6 */ \
2074 &rs6000_reg_names[107][0], /* cr7 */ \
2076 &rs6000_reg_names[108][0], /* vrsave */ \
2077 &rs6000_reg_names[109][0], /* vscr */ \
2079 &rs6000_reg_names[110][0] /* sfp */ \
2082 /* Table of additional register names to use in user input. */
2084 #define ADDITIONAL_REGISTER_NAMES \
2085 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2086 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2087 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2088 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2089 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2090 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2091 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2092 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2093 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2094 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2095 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2096 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2097 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2098 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2099 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2100 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2101 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \
2102 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \
2103 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \
2104 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \
2105 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \
2106 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \
2107 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \
2108 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \
2109 {"vrsave", 108}, {"vscr", 109}, \
2110 /* no additional names for: lr, ctr, ap */ \
2111 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \
2112 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \
2113 {"cc", 100},{"sp", 1}, {"toc", 2}, \
2114 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2116 /* VSX registers overlaid on top of FR, Altivec registers */ \
2117 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2118 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2119 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2120 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2121 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2122 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2123 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2124 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2125 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \
2126 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \
2127 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \
2128 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \
2129 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \
2130 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \
2131 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \
2132 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \
2135 /* This is how to output an element of a case-vector that is relative. */
2137 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2138 do { char buf[100]; \
2139 fputs ("\t.long ", FILE); \
2140 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2141 assemble_name (FILE, buf); \
2143 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2144 assemble_name (FILE, buf); \
2145 putc ('\n', FILE); \
2148 /* This is how to output an element of a case-vector
2149 that is non-relative. */
2150 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2151 rs6000_output_addr_vec_elt ((FILE), (VALUE))
2153 /* This is how to output an assembler line
2154 that says to advance the location counter
2155 to a multiple of 2**LOG bytes. */
2157 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2159 fprintf (FILE, "\t.align %d\n", (LOG))
2161 /* How to align the given loop. */
2162 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2164 /* Alignment guaranteed by __builtin_malloc. */
2165 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2166 However, specifying the stronger guarantee currently leads to
2167 a regression in SPEC CPU2006 437.leslie3d. The stronger
2168 guarantee should be implemented here once that's fixed. */
2169 #define MALLOC_ABI_ALIGNMENT (64)
2171 /* Pick up the return address upon entry to a procedure. Used for
2172 dwarf2 unwind information. This also enables the table driven
2175 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2176 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2178 /* Describe how we implement __builtin_eh_return. */
2179 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2180 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2182 /* Print operand X (an rtx) in assembler syntax to file FILE.
2183 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2184 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2186 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2188 /* Define which CODE values are valid. */
2190 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2192 /* Print a memory address as an operand to reference that memory location. */
2194 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2196 /* For switching between functions with different target attributes. */
2197 #define SWITCHABLE_TARGET 1
2199 /* uncomment for disabling the corresponding default options */
2200 /* #define MACHINE_no_sched_interblock */
2201 /* #define MACHINE_no_sched_speculative */
2202 /* #define MACHINE_no_sched_speculative_load */
2204 /* General flags. */
2205 extern int frame_pointer_needed
;
2207 enum rs6000_builtin_type_index
2209 RS6000_BTI_NOT_OPAQUE
,
2210 RS6000_BTI_opaque_V4SI
,
2211 RS6000_BTI_V16QI
, /* __vector signed char */
2219 RS6000_BTI_unsigned_V16QI
, /* __vector unsigned char */
2220 RS6000_BTI_unsigned_V1TI
,
2221 RS6000_BTI_unsigned_V8HI
,
2222 RS6000_BTI_unsigned_V4SI
,
2223 RS6000_BTI_unsigned_V2DI
,
2224 RS6000_BTI_bool_char
, /* __bool char */
2225 RS6000_BTI_bool_short
, /* __bool short */
2226 RS6000_BTI_bool_int
, /* __bool int */
2227 RS6000_BTI_bool_long_long
, /* __bool long long */
2228 RS6000_BTI_pixel
, /* __pixel (16 bits arranged as 4
2229 channels of 1, 5, 5, and 5 bits
2230 respectively as packed with the
2231 vpkpx insn. __pixel is only
2232 meaningful as a vector type.
2233 There is no corresponding scalar
2234 __pixel data type.) */
2235 RS6000_BTI_bool_V16QI
, /* __vector __bool char */
2236 RS6000_BTI_bool_V8HI
, /* __vector __bool short */
2237 RS6000_BTI_bool_V4SI
, /* __vector __bool int */
2238 RS6000_BTI_bool_V2DI
, /* __vector __bool long */
2239 RS6000_BTI_bool_V1TI
, /* __vector __bool 128-bit */
2240 RS6000_BTI_pixel_V8HI
, /* __vector __pixel */
2241 RS6000_BTI_long
, /* long_integer_type_node */
2242 RS6000_BTI_unsigned_long
, /* long_unsigned_type_node */
2243 RS6000_BTI_long_long
, /* long_long_integer_type_node */
2244 RS6000_BTI_unsigned_long_long
, /* long_long_unsigned_type_node */
2245 RS6000_BTI_INTQI
, /* (signed) intQI_type_node */
2246 RS6000_BTI_UINTQI
, /* unsigned_intQI_type_node */
2247 RS6000_BTI_INTHI
, /* intHI_type_node */
2248 RS6000_BTI_UINTHI
, /* unsigned_intHI_type_node */
2249 RS6000_BTI_INTSI
, /* intSI_type_node (signed) */
2250 RS6000_BTI_UINTSI
, /* unsigned_intSI_type_node */
2251 RS6000_BTI_INTDI
, /* intDI_type_node */
2252 RS6000_BTI_UINTDI
, /* unsigned_intDI_type_node */
2253 RS6000_BTI_INTTI
, /* intTI_type_node */
2254 RS6000_BTI_UINTTI
, /* unsigned_intTI_type_node */
2255 RS6000_BTI_float
, /* float_type_node */
2256 RS6000_BTI_double
, /* double_type_node */
2257 RS6000_BTI_long_double
, /* long_double_type_node */
2258 RS6000_BTI_dfloat64
, /* dfloat64_type_node */
2259 RS6000_BTI_dfloat128
, /* dfloat128_type_node */
2260 RS6000_BTI_void
, /* void_type_node */
2261 RS6000_BTI_ieee128_float
, /* ieee 128-bit floating point */
2262 RS6000_BTI_ibm128_float
, /* IBM 128-bit floating point */
2263 RS6000_BTI_const_str
, /* pointer to const char * */
2264 RS6000_BTI_vector_pair
, /* unsigned 256-bit types (vector pair). */
2265 RS6000_BTI_vector_quad
, /* unsigned 512-bit types (vector quad). */
2266 RS6000_BTI_const_ptr_void
, /* const pointer to void */
2267 RS6000_BTI_ptr_V16QI
,
2268 RS6000_BTI_ptr_V1TI
,
2269 RS6000_BTI_ptr_V2DI
,
2270 RS6000_BTI_ptr_V2DF
,
2271 RS6000_BTI_ptr_V4SI
,
2272 RS6000_BTI_ptr_V4SF
,
2273 RS6000_BTI_ptr_V8HI
,
2274 RS6000_BTI_ptr_unsigned_V16QI
,
2275 RS6000_BTI_ptr_unsigned_V1TI
,
2276 RS6000_BTI_ptr_unsigned_V8HI
,
2277 RS6000_BTI_ptr_unsigned_V4SI
,
2278 RS6000_BTI_ptr_unsigned_V2DI
,
2279 RS6000_BTI_ptr_bool_V16QI
,
2280 RS6000_BTI_ptr_bool_V8HI
,
2281 RS6000_BTI_ptr_bool_V4SI
,
2282 RS6000_BTI_ptr_bool_V2DI
,
2283 RS6000_BTI_ptr_bool_V1TI
,
2284 RS6000_BTI_ptr_pixel_V8HI
,
2285 RS6000_BTI_ptr_INTQI
,
2286 RS6000_BTI_ptr_UINTQI
,
2287 RS6000_BTI_ptr_INTHI
,
2288 RS6000_BTI_ptr_UINTHI
,
2289 RS6000_BTI_ptr_INTSI
,
2290 RS6000_BTI_ptr_UINTSI
,
2291 RS6000_BTI_ptr_INTDI
,
2292 RS6000_BTI_ptr_UINTDI
,
2293 RS6000_BTI_ptr_INTTI
,
2294 RS6000_BTI_ptr_UINTTI
,
2295 RS6000_BTI_ptr_long_integer
,
2296 RS6000_BTI_ptr_long_unsigned
,
2297 RS6000_BTI_ptr_float
,
2298 RS6000_BTI_ptr_double
,
2299 RS6000_BTI_ptr_long_double
,
2300 RS6000_BTI_ptr_dfloat64
,
2301 RS6000_BTI_ptr_dfloat128
,
2302 RS6000_BTI_ptr_vector_pair
,
2303 RS6000_BTI_ptr_vector_quad
,
2304 RS6000_BTI_ptr_long_long
,
2305 RS6000_BTI_ptr_long_long_unsigned
,
2310 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2311 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2312 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2313 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2314 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2315 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2316 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2317 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2318 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2319 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2320 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2321 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2322 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2323 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2324 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2325 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2326 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2327 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2328 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2329 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2330 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2331 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2332 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2333 #define bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V1TI])
2334 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2336 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2337 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2338 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2339 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2340 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2341 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2342 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2343 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2344 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2345 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2346 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2347 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2348 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2349 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2350 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2351 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2352 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2353 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2354 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2355 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2356 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2357 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2358 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2359 #define vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_vector_pair])
2360 #define vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_vector_quad])
2361 #define pcvoid_type_node (rs6000_builtin_types[RS6000_BTI_const_ptr_void])
2362 #define ptr_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V16QI])
2363 #define ptr_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V1TI])
2364 #define ptr_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DI])
2365 #define ptr_V2DF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DF])
2366 #define ptr_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SI])
2367 #define ptr_V4SF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SF])
2368 #define ptr_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V8HI])
2369 #define ptr_unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V16QI])
2370 #define ptr_unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V1TI])
2371 #define ptr_unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V8HI])
2372 #define ptr_unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V4SI])
2373 #define ptr_unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V2DI])
2374 #define ptr_bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V16QI])
2375 #define ptr_bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V8HI])
2376 #define ptr_bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V4SI])
2377 #define ptr_bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V2DI])
2378 #define ptr_bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V1TI])
2379 #define ptr_pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_pixel_V8HI])
2380 #define ptr_intQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTQI])
2381 #define ptr_uintQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTQI])
2382 #define ptr_intHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTHI])
2383 #define ptr_uintHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTHI])
2384 #define ptr_intSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTSI])
2385 #define ptr_uintSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTSI])
2386 #define ptr_intDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTDI])
2387 #define ptr_uintDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTDI])
2388 #define ptr_intTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTTI])
2389 #define ptr_uintTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTTI])
2390 #define ptr_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_integer])
2391 #define ptr_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_unsigned])
2392 #define ptr_float_type_node (rs6000_builtin_types[RS6000_BTI_ptr_float])
2393 #define ptr_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_double])
2394 #define ptr_long_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_double])
2395 #define ptr_dfloat64_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat64])
2396 #define ptr_dfloat128_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat128])
2397 #define ptr_vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_pair])
2398 #define ptr_vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_quad])
2399 #define ptr_long_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long])
2400 #define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned])
2402 extern GTY(()) tree rs6000_builtin_types
[RS6000_BTI_MAX
];
2404 #ifndef USED_FOR_TARGET
2405 extern GTY(()) tree altivec_builtin_mask_for_load
;
2406 extern GTY(()) section
*toc_section
;
2408 /* A C structure for machine-specific, per-function data.
2409 This is added to the cfun structure. */
2410 typedef struct GTY(()) machine_function
2412 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
2413 int ra_needs_full_frame
;
2414 /* Flags if __builtin_return_address (0) was used. */
2416 /* Cache lr_save_p after expansion of builtin_eh_return. */
2418 /* Whether we need to save the TOC to the reserved stack location in the
2419 function prologue. */
2420 bool save_toc_in_prologue
;
2421 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
2422 varargs save area. */
2423 HOST_WIDE_INT varargs_save_offset
;
2424 /* Alternative internal arg pointer for -fsplit-stack. */
2425 rtx split_stack_arg_pointer
;
2426 bool split_stack_argp_used
;
2427 /* Flag if r2 setup is needed with ELFv2 ABI. */
2428 bool r2_setup_needed
;
2429 /* The number of components we use for separate shrink-wrapping. */
2431 /* The components already handled by separate shrink-wrapping, which should
2432 not be considered by the prologue and epilogue. */
2433 bool gpr_is_wrapped_separately
[32];
2434 bool fpr_is_wrapped_separately
[32];
2435 bool lr_is_wrapped_separately
;
2436 bool toc_is_wrapped_separately
;
2437 bool mma_return_type_error
;
2438 /* Indicate global entry is emitted, only useful when the function requires
2439 global entry. It helps to control the patchable area before and after
2441 bool global_entry_emitted
;
2446 #define TARGET_SUPPORTS_WIDE_INT 1
2448 #if (GCC_VERSION >= 3000)
2449 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128
2452 /* Whether a given VALUE is a valid 16 or 34-bit signed integer. */
2453 #define SIGNED_INTEGER_NBIT_P(VALUE, N) \
2454 IN_RANGE ((VALUE), \
2455 -(HOST_WIDE_INT_1 << ((N)-1)), \
2456 (HOST_WIDE_INT_1 << ((N)-1)) - 1)
2458 #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16)
2459 #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34)
2461 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra
2462 argument that gives a length to validate a range of addresses, to allow for
2463 splitting insns into several insns, each of which has an offsettable
2465 #define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \
2466 IN_RANGE ((VALUE), \
2467 -(HOST_WIDE_INT_1 << 15), \
2468 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA))
2470 #define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \
2471 IN_RANGE ((VALUE), \
2472 -(HOST_WIDE_INT_1 << 33), \
2473 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA))
2475 /* Define this if some processing needs to be done before outputting the
2476 assembler code. On the PowerPC, we remember if the current insn is a normal
2477 prefixed insn where we need to emit a 'p' before the insn. */
2478 #define FINAL_PRESCAN_INSN(INSN, OPERANDS, NOPERANDS) \
2481 if (TARGET_PREFIXED) \
2482 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS); \
2486 /* Do anything special before emitting an opcode. We use it to emit a 'p' for
2487 prefixed insns that is set in FINAL_PRESCAN_INSN. */
2488 #define ASM_OUTPUT_OPCODE(STREAM, OPCODE) \
2491 if (TARGET_PREFIXED) \
2492 rs6000_asm_output_opcode (STREAM); \
2496 /* Disable generation of scalar modulo instructions due to performance issues
2497 with certain input values. This can be removed in the future when the
2498 issues have been resolved. */
2499 #define RS6000_DISABLE_SCALAR_MODULO 1