1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
38 extern char *language_string
;
39 extern int profile_block_flag
;
41 #define min(A,B) ((A) < (B) ? (A) : (B))
42 #define max(A,B) ((A) > (B) ? (A) : (B))
46 enum processor_type rs6000_cpu
;
47 char *rs6000_cpu_string
;
49 /* Set to non-zero by "fix" operation to indicate that itrunc and
50 uitrunc must be defined. */
52 int rs6000_trunc_used
;
54 /* Set to non-zero once they have been defined. */
56 static int trunc_defined
;
58 /* Set to non-zero once AIX common-mode calls have been defined. */
59 static int common_mode_defined
;
60 /* Save information from a "cmpxx" operation until the branch or scc is
63 rtx rs6000_compare_op0
, rs6000_compare_op1
;
64 int rs6000_compare_fp_p
;
66 /* Override command line options. Mostly we process the processor
67 type and sometimes adjust other TARGET_ options. */
70 rs6000_override_options ()
74 /* Simplify the entries below by making a mask for any POWER
75 variant and any PowerPC variant. */
77 #define POWER_MASKS (MASK_POWER | MASK_POWER2)
78 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
79 | MASK_PPC_GFXOPT | MASK_POWERPC64)
80 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
84 char *name
; /* Canonical processor name. */
85 enum processor_type processor
; /* Processor type enum value. */
86 int target_enable
; /* Target flags to enable. */
87 int target_disable
; /* Target flags to disable. */
88 } processor_target_table
[]
89 = {{"common", PROCESSOR_COMMON
, 0, POWER_MASKS
| POWERPC_MASKS
},
90 {"power", PROCESSOR_POWER
,
92 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
93 {"powerpc", PROCESSOR_POWERPC
,
94 MASK_POWERPC
| MASK_NEW_MNEMONICS
,
95 POWER_MASKS
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
96 {"rios", PROCESSOR_RIOS1
,
98 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
99 {"rios1", PROCESSOR_RIOS1
,
101 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
102 {"rsc", PROCESSOR_PPC601
,
104 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
105 {"rsc1", PROCESSOR_PPC601
,
107 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
108 {"rios2", PROCESSOR_RIOS2
,
109 MASK_POWER
| MASK_POWER2
,
110 POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
111 {"601", PROCESSOR_PPC601
,
112 MASK_POWER
| MASK_POWERPC
| MASK_NEW_MNEMONICS
,
113 MASK_POWER2
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
114 {"mpc601", PROCESSOR_PPC601
,
115 MASK_POWER
| MASK_POWERPC
| MASK_NEW_MNEMONICS
,
116 MASK_POWER2
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
117 {"ppc601", PROCESSOR_PPC601
,
118 MASK_POWER
| MASK_POWERPC
| MASK_NEW_MNEMONICS
,
119 MASK_POWER2
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
120 {"603", PROCESSOR_PPC603
,
121 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
122 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
123 {"mpc603", PROCESSOR_PPC603
,
124 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
125 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
126 {"ppc603", PROCESSOR_PPC603
,
127 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
128 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
129 {"604", PROCESSOR_PPC604
,
130 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
131 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
132 {"mpc604", PROCESSOR_PPC604
,
133 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
134 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
135 {"ppc604", PROCESSOR_PPC604
,
136 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
137 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
}};
139 int ptt_size
= sizeof (processor_target_table
) / sizeof (struct ptt
);
141 profile_block_flag
= 0;
143 /* Identify the processor type */
144 if (rs6000_cpu_string
== 0)
145 rs6000_cpu
= PROCESSOR_DEFAULT
;
148 for (i
= 0; i
< ptt_size
; i
++)
149 if (! strcmp (rs6000_cpu_string
, processor_target_table
[i
].name
))
151 rs6000_cpu
= processor_target_table
[i
].processor
;
152 target_flags
|= processor_target_table
[i
].target_enable
;
153 target_flags
&= ~processor_target_table
[i
].target_disable
;
159 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string
);
160 rs6000_cpu_string
= "default";
161 rs6000_cpu
= PROCESSOR_DEFAULT
;
166 /* Return non-zero if this function is known to have a null epilogue. */
171 return (reload_completed
172 && first_reg_to_save () == 32
173 && first_fp_reg_to_save () == 64
174 && ! regs_ever_live
[65]
175 && ! rs6000_pushes_stack ());
178 /* Returns 1 always. */
181 any_operand (op
, mode
)
183 enum machine_mode mode
;
188 /* Return 1 if OP is a constant that can fit in a D field. */
191 short_cint_operand (op
, mode
)
193 enum machine_mode mode
;
195 return (GET_CODE (op
) == CONST_INT
196 && (unsigned) (INTVAL (op
) + 0x8000) < 0x10000);
199 /* Similar for a unsigned D field. */
202 u_short_cint_operand (op
, mode
)
204 enum machine_mode mode
;
206 return (GET_CODE (op
) == CONST_INT
&& (INTVAL (op
) & 0xffff0000) == 0);
209 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
212 non_short_cint_operand (op
, mode
)
214 enum machine_mode mode
;
216 return (GET_CODE (op
) == CONST_INT
217 && (unsigned) (INTVAL (op
) + 0x8000) >= 0x10000);
220 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
224 gpc_reg_operand (op
, mode
)
226 enum machine_mode mode
;
228 return (register_operand (op
, mode
)
229 && (GET_CODE (op
) != REG
|| REGNO (op
) >= 67 || REGNO (op
) < 64));
232 /* Returns 1 if OP is either a pseudo-register or a register denoting a
236 cc_reg_operand (op
, mode
)
238 enum machine_mode mode
;
240 return (register_operand (op
, mode
)
241 && (GET_CODE (op
) != REG
242 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
243 || CR_REGNO_P (REGNO (op
))));
246 /* Returns 1 if OP is either a constant integer valid for a D-field or a
247 non-special register. If a register, it must be in the proper mode unless
251 reg_or_short_operand (op
, mode
)
253 enum machine_mode mode
;
255 return short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
258 /* Similar, except check if the negation of the constant would be valid for
262 reg_or_neg_short_operand (op
, mode
)
264 enum machine_mode mode
;
266 if (GET_CODE (op
) == CONST_INT
)
267 return CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P');
269 return gpc_reg_operand (op
, mode
);
272 /* Return 1 if the operand is either a register or an integer whose high-order
276 reg_or_u_short_operand (op
, mode
)
278 enum machine_mode mode
;
280 if (GET_CODE (op
) == CONST_INT
281 && (INTVAL (op
) & 0xffff0000) == 0)
284 return gpc_reg_operand (op
, mode
);
287 /* Return 1 is the operand is either a non-special register or ANY
291 reg_or_cint_operand (op
, mode
)
293 enum machine_mode mode
;
295 return GET_CODE (op
) == CONST_INT
|| gpc_reg_operand (op
, mode
);
298 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
299 with one instruction per word. We only do this if we can safely read
300 CONST_DOUBLE_{LOW,HIGH}. */
303 easy_fp_constant (op
, mode
)
305 register enum machine_mode mode
;
309 if (GET_CODE (op
) != CONST_DOUBLE
310 || GET_MODE (op
) != mode
311 || GET_MODE_CLASS (mode
) != MODE_FLOAT
)
314 high
= operand_subword (op
, 0, 0, mode
);
315 low
= operand_subword (op
, 1, 0, mode
);
317 if (high
== 0 || ! input_operand (high
, word_mode
))
320 return (mode
== SFmode
321 || (low
!= 0 && input_operand (low
, word_mode
)));
324 /* Return 1 if the operand is either a floating-point register, a pseudo
325 register, or memory. */
328 fp_reg_or_mem_operand (op
, mode
)
330 enum machine_mode mode
;
332 return (memory_operand (op
, mode
)
333 || (register_operand (op
, mode
)
334 && (GET_CODE (op
) != REG
335 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
336 || FP_REGNO_P (REGNO (op
)))));
339 /* Return 1 if the operand is either an easy FP constant (see above) or
343 mem_or_easy_const_operand (op
, mode
)
345 enum machine_mode mode
;
347 return memory_operand (op
, mode
) || easy_fp_constant (op
, mode
);
350 /* Return 1 if the operand is either a non-special register or an item
351 that can be used as the operand of an SI add insn. */
354 add_operand (op
, mode
)
356 enum machine_mode mode
;
358 return (reg_or_short_operand (op
, mode
)
359 || (GET_CODE (op
) == CONST_INT
&& (INTVAL (op
) & 0xffff) == 0));
362 /* Return 1 if OP is a constant but not a valid add_operand. */
365 non_add_cint_operand (op
, mode
)
367 enum machine_mode mode
;
369 return (GET_CODE (op
) == CONST_INT
370 && (unsigned) (INTVAL (op
) + 0x8000) >= 0x10000
371 && (INTVAL (op
) & 0xffff) != 0);
374 /* Return 1 if the operand is a non-special register or a constant that
375 can be used as the operand of an OR or XOR insn on the RS/6000. */
378 logical_operand (op
, mode
)
380 enum machine_mode mode
;
382 return (gpc_reg_operand (op
, mode
)
383 || (GET_CODE (op
) == CONST_INT
384 && ((INTVAL (op
) & 0xffff0000) == 0
385 || (INTVAL (op
) & 0xffff) == 0)));
388 /* Return 1 if C is a constant that is not a logical operand (as
392 non_logical_cint_operand (op
, mode
)
394 enum machine_mode mode
;
396 return (GET_CODE (op
) == CONST_INT
397 && (INTVAL (op
) & 0xffff0000) != 0
398 && (INTVAL (op
) & 0xffff) != 0);
401 /* Return 1 if C is a constant that can be encoded in a mask on the
402 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
403 Reject all ones and all zeros, since these should have been optimized
404 away and confuse the making of MB and ME. */
414 if (c
== 0 || c
== ~0)
417 last_bit_value
= c
& 1;
419 for (i
= 1; i
< 32; i
++)
420 if (((c
>>= 1) & 1) != last_bit_value
)
421 last_bit_value
^= 1, transitions
++;
423 return transitions
<= 2;
426 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
429 mask_operand (op
, mode
)
431 enum machine_mode mode
;
433 return GET_CODE (op
) == CONST_INT
&& mask_constant (INTVAL (op
));
436 /* Return 1 if the operand is either a non-special register or a
437 constant that can be used as the operand of an RS/6000 logical AND insn. */
440 and_operand (op
, mode
)
442 enum machine_mode mode
;
444 return (reg_or_short_operand (op
, mode
)
445 || logical_operand (op
, mode
)
446 || mask_operand (op
, mode
));
449 /* Return 1 if the operand is a constant but not a valid operand for an AND
453 non_and_cint_operand (op
, mode
)
455 enum machine_mode mode
;
457 return GET_CODE (op
) == CONST_INT
&& ! and_operand (op
, mode
);
460 /* Return 1 if the operand is a general register or memory operand. */
463 reg_or_mem_operand (op
, mode
)
465 register enum machine_mode mode
;
467 return gpc_reg_operand (op
, mode
) || memory_operand (op
, mode
);
470 /* Return 1 if the operand, used inside a MEM, is a valid first argument
471 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
475 call_operand (op
, mode
)
477 enum machine_mode mode
;
479 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
482 return (GET_CODE (op
) == SYMBOL_REF
483 || (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
));
487 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
491 current_file_function_operand (op
, mode
)
493 enum machine_mode mode
;
495 return (GET_CODE (op
) == SYMBOL_REF
496 && (SYMBOL_REF_FLAG (op
)
497 || op
== XEXP (DECL_RTL (current_function_decl
), 0)));
501 /* Return 1 if this operand is a valid input for a move insn. */
504 input_operand (op
, mode
)
506 enum machine_mode mode
;
508 /* Memory is always valid. */
509 if (memory_operand (op
, mode
))
512 /* For floating-point, easy constants are valid. */
513 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
515 && easy_fp_constant (op
, mode
))
518 /* For floating-point or multi-word mode, the only remaining valid type
520 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
521 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
522 return register_operand (op
, mode
);
524 /* The only cases left are integral modes one word or smaller (we
525 do not get called for MODE_CC values). These can be in any
527 if (register_operand (op
, mode
))
530 /* For HImode and QImode, any constant is valid. */
531 if ((mode
== HImode
|| mode
== QImode
)
532 && GET_CODE (op
) == CONST_INT
)
535 /* Otherwise, we will be doing this SET with an add, so anything valid
536 for an add will be valid. */
537 return add_operand (op
, mode
);
540 /* Return 1 if OP is a load multiple operation. It is known to be a
541 PARALLEL and the first section will be tested. */
544 load_multiple_operation (op
, mode
)
546 enum machine_mode mode
;
548 int count
= XVECLEN (op
, 0);
553 /* Perform a quick check so we don't blow up below. */
555 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
556 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
557 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
560 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
561 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
563 for (i
= 1; i
< count
; i
++)
565 rtx elt
= XVECEXP (op
, 0, i
);
567 if (GET_CODE (elt
) != SET
568 || GET_CODE (SET_DEST (elt
)) != REG
569 || GET_MODE (SET_DEST (elt
)) != SImode
570 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
571 || GET_CODE (SET_SRC (elt
)) != MEM
572 || GET_MODE (SET_SRC (elt
)) != SImode
573 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
574 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
575 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
576 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != i
* 4)
583 /* Similar, but tests for store multiple. Here, the second vector element
584 is a CLOBBER. It will be tested later. */
587 store_multiple_operation (op
, mode
)
589 enum machine_mode mode
;
591 int count
= XVECLEN (op
, 0) - 1;
596 /* Perform a quick check so we don't blow up below. */
598 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
599 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
600 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
603 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
604 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
606 for (i
= 1; i
< count
; i
++)
608 rtx elt
= XVECEXP (op
, 0, i
+ 1);
610 if (GET_CODE (elt
) != SET
611 || GET_CODE (SET_SRC (elt
)) != REG
612 || GET_MODE (SET_SRC (elt
)) != SImode
613 || REGNO (SET_SRC (elt
)) != src_regno
+ i
614 || GET_CODE (SET_DEST (elt
)) != MEM
615 || GET_MODE (SET_DEST (elt
)) != SImode
616 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
617 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
618 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
619 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != i
* 4)
626 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
627 We only check the opcode against the mode of the CC value here. */
630 branch_comparison_operator (op
, mode
)
632 enum machine_mode mode
;
634 enum rtx_code code
= GET_CODE (op
);
635 enum machine_mode cc_mode
;
637 if (GET_RTX_CLASS (code
) != '<')
640 cc_mode
= GET_MODE (XEXP (op
, 0));
641 if (GET_MODE_CLASS (cc_mode
) != MODE_CC
)
644 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
645 && cc_mode
== CCUNSmode
)
648 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
649 && (cc_mode
!= CCUNSmode
))
655 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
656 We check the opcode against the mode of the CC value and disallow EQ or
657 NE comparisons for integers. */
660 scc_comparison_operator (op
, mode
)
662 enum machine_mode mode
;
664 enum rtx_code code
= GET_CODE (op
);
665 enum machine_mode cc_mode
;
667 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
670 if (GET_RTX_CLASS (code
) != '<')
673 cc_mode
= GET_MODE (XEXP (op
, 0));
674 if (GET_MODE_CLASS (cc_mode
) != MODE_CC
)
677 if (code
== NE
&& cc_mode
!= CCFPmode
)
680 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
681 && cc_mode
== CCUNSmode
)
684 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
685 && (cc_mode
!= CCUNSmode
))
688 if (cc_mode
== CCEQmode
&& code
!= EQ
&& code
!= NE
)
694 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
695 mask required to convert the result of a rotate insn into a shift
696 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
699 includes_lshift_p (shiftop
, andop
)
700 register rtx shiftop
;
703 int shift_mask
= (~0 << INTVAL (shiftop
));
705 return (INTVAL (andop
) & ~shift_mask
) == 0;
708 /* Similar, but for right shift. */
711 includes_rshift_p (shiftop
, andop
)
712 register rtx shiftop
;
715 unsigned shift_mask
= ~0;
717 shift_mask
>>= INTVAL (shiftop
);
719 return (INTVAL (andop
) & ~ shift_mask
) == 0;
722 /* Return the register class of a scratch register needed to copy IN into
723 or out of a register in CLASS in MODE. If it can be done directly,
724 NO_REGS is returned. */
727 secondary_reload_class (class, mode
, in
)
728 enum reg_class
class;
729 enum machine_mode mode
;
732 int regno
= true_regnum (in
);
734 if (regno
>= FIRST_PSEUDO_REGISTER
)
737 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
739 if (class == GENERAL_REGS
|| class == BASE_REGS
740 || (regno
>= 0 && INT_REGNO_P (regno
)))
743 /* Constants, memory, and FP registers can go into FP registers. */
744 if ((regno
== -1 || FP_REGNO_P (regno
))
745 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
748 /* We can copy among the CR registers. */
749 if ((class == CR_REGS
|| class == CR0_REGS
)
750 && regno
>= 0 && CR_REGNO_P (regno
))
753 /* Otherwise, we need GENERAL_REGS. */
757 /* Given a comparison operation, return the bit number in CCR to test. We
758 know this is a valid comparison.
760 SCC_P is 1 if this is for an scc. That means that %D will have been
761 used instead of %C, so the bits will be in different places.
763 Return -1 if OP isn't a valid comparison for some reason. */
770 enum rtx_code code
= GET_CODE (op
);
771 enum machine_mode cc_mode
;
775 if (GET_RTX_CLASS (code
) != '<')
778 cc_mode
= GET_MODE (XEXP (op
, 0));
779 cc_regnum
= REGNO (XEXP (op
, 0));
780 base_bit
= 4 * (cc_regnum
- 68);
782 /* In CCEQmode cases we have made sure that the result is always in the
783 third bit of the CR field. */
785 if (cc_mode
== CCEQmode
)
791 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
800 /* If floating-point, we will have done a cror to put the bit in the
801 unordered position. So test that bit. For integer, this is ! LT
802 unless this is an scc insn. */
803 return cc_mode
== CCFPmode
|| scc_p
? base_bit
+ 3 : base_bit
;
806 return cc_mode
== CCFPmode
|| scc_p
? base_bit
+ 3 : base_bit
+ 1;
813 /* Print an operand. Recognize special options, documented below. */
816 print_operand (file
, x
, code
)
824 /* These macros test for integers and extract the low-order bits. */
826 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
827 && GET_MODE (X) == VOIDmode)
829 #define INT_LOWPART(X) \
830 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
835 /* Write out an instruction after the call which may be replaced
836 with glue code by the loader. This depends on the AIX version. */
837 asm_fprintf (file
, RS6000_CALL_GLUE
);
841 /* If X is a constant integer whose low-order 5 bits are zero,
842 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
843 in the AIX assembler where "sri" with a zero shift count
844 write a trash instruction. */
845 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
852 /* Low-order 16 bits of constant, unsigned. */
854 output_operand_lossage ("invalid %%b value");
856 fprintf (file
, "%d", INT_LOWPART (x
) & 0xffff);
860 /* This is an optional cror needed for LE or GE floating-point
861 comparisons. Otherwise write nothing. */
862 if ((GET_CODE (x
) == LE
|| GET_CODE (x
) == GE
)
863 && GET_MODE (XEXP (x
, 0)) == CCFPmode
)
865 int base_bit
= 4 * (REGNO (XEXP (x
, 0)) - 68);
867 fprintf (file
, "cror %d,%d,%d\n\t", base_bit
+ 3,
868 base_bit
+ 2, base_bit
+ (GET_CODE (x
) == GE
));
873 /* Similar, except that this is for an scc, so we must be able to
874 encode the test in a single bit that is one. We do the above
875 for any LE, GE, GEU, or LEU and invert the bit for NE. */
876 if (GET_CODE (x
) == LE
|| GET_CODE (x
) == GE
877 || GET_CODE (x
) == LEU
|| GET_CODE (x
) == GEU
)
879 int base_bit
= 4 * (REGNO (XEXP (x
, 0)) - 68);
881 fprintf (file
, "cror %d,%d,%d\n\t", base_bit
+ 3,
883 base_bit
+ (GET_CODE (x
) == GE
|| GET_CODE (x
) == GEU
));
886 else if (GET_CODE (x
) == NE
)
888 int base_bit
= 4 * (REGNO (XEXP (x
, 0)) - 68);
890 fprintf (file
, "crnor %d,%d,%d\n\t", base_bit
+ 3,
891 base_bit
+ 2, base_bit
+ 2);
896 /* X is a CR register. Print the number of the third bit of the CR */
897 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
898 output_operand_lossage ("invalid %%E value");
900 fprintf(file
, "%d", 4 * (REGNO (x
) - 68) + 3);
904 /* X is a CR register. Print the shift count needed to move it
905 to the high-order four bits. */
906 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
907 output_operand_lossage ("invalid %%f value");
909 fprintf (file
, "%d", 4 * (REGNO (x
) - 68));
913 /* Similar, but print the count for the rotate in the opposite
915 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
916 output_operand_lossage ("invalid %%F value");
918 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - 68));
922 /* X is a constant integer. If it is negative, print "m",
923 otherwise print "z". This is to make a aze or ame insn. */
924 if (GET_CODE (x
) != CONST_INT
)
925 output_operand_lossage ("invalid %%G value");
926 else if (INTVAL (x
) >= 0)
933 /* If constant, output low-order five bits. Otherwise,
936 fprintf (file
, "%d", INT_LOWPART (x
) & 31);
938 print_operand (file
, x
, 0);
942 /* X must be a constant. Output the low order 5 bits plus 24. */
944 output_operand_lossage ("invalid %%H value");
946 fprintf (file
, "%d", (INT_LOWPART (x
) + 24) & 31);
950 /* Print `i' if this is a constant, else nothing. */
956 /* Write the bit number in CCR for jump. */
959 output_operand_lossage ("invalid %%j code");
961 fprintf (file
, "%d", i
);
965 /* Similar, but add one for shift count in rlinm for scc and pass
966 scc flag to `ccr_bit'. */
969 output_operand_lossage ("invalid %%J code");
971 /* If we want bit 31, write a shift count of zero, not 32. */
972 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
976 /* X must be a constant. Write the 1's complement of the
979 output_operand_lossage ("invalid %%k value");
981 fprintf (file
, "%d", ~ INT_LOWPART (x
));
985 /* Write second word of DImode or DFmode reference. Works on register
986 or non-indexed memory only. */
987 if (GET_CODE (x
) == REG
)
988 fprintf (file
, "%d", REGNO (x
) + 1);
989 else if (GET_CODE (x
) == MEM
)
991 /* Handle possible auto-increment. Since it is pre-increment and
992 we have already done it, we can just use an offset of four. */
993 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
994 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
995 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
997 output_address (plus_constant (XEXP (x
, 0), 4));
1002 /* MB value for a mask operand. */
1003 if (! mask_operand (x
, VOIDmode
))
1004 output_operand_lossage ("invalid %%m value");
1006 val
= INT_LOWPART (x
);
1008 /* If the high bit is set and the low bit is not, the value is zero.
1009 If the high bit is zero, the value is the first 1 bit we find from
1011 if (val
< 0 && (val
& 1) == 0)
1013 fprintf (file
, "0");
1018 for (i
= 1; i
< 32; i
++)
1019 if ((val
<<= 1) < 0)
1021 fprintf (file
, "%d", i
);
1025 /* Otherwise, look for the first 0 bit from the right. The result is its
1026 number plus 1. We know the low-order bit is one. */
1027 for (i
= 0; i
< 32; i
++)
1028 if (((val
>>= 1) & 1) == 0)
1031 /* If we ended in ...01, I would be 0. The correct value is 31, so
1033 fprintf (file
, "%d", 31 - i
);
1037 /* ME value for a mask operand. */
1038 if (! mask_operand (x
, VOIDmode
))
1039 output_operand_lossage ("invalid %%m value");
1041 val
= INT_LOWPART (x
);
1043 /* If the low bit is set and the high bit is not, the value is 31.
1044 If the low bit is zero, the value is the first 1 bit we find from
1046 if ((val
& 1) && val
>= 0)
1051 else if ((val
& 1) == 0)
1053 for (i
= 0; i
< 32; i
++)
1054 if ((val
>>= 1) & 1)
1057 /* If we had ....10, I would be 0. The result should be
1058 30, so we need 30 - i. */
1059 fprintf (file
, "%d", 30 - i
);
1063 /* Otherwise, look for the first 0 bit from the left. The result is its
1064 number minus 1. We know the high-order bit is one. */
1065 for (i
= 0; i
< 32; i
++)
1066 if ((val
<<= 1) >= 0)
1069 fprintf (file
, "%d", i
);
1073 /* Write the number of elements in the vector times 4. */
1074 if (GET_CODE (x
) != PARALLEL
)
1075 output_operand_lossage ("invalid %%N value");
1077 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
1081 /* Similar, but subtract 1 first. */
1082 if (GET_CODE (x
) != PARALLEL
)
1083 output_operand_lossage ("invalid %%N value");
1085 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
1089 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1091 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
1092 output_operand_lossage ("invalid %%p value");
1094 fprintf (file
, "%d", i
);
1098 /* The operand must be an indirect memory reference. The result
1099 is the register number. */
1100 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
1101 || REGNO (XEXP (x
, 0)) >= 32)
1102 output_operand_lossage ("invalid %%P value");
1104 fprintf (file
, "%d", REGNO (XEXP (x
, 0)));
1108 /* X is a CR register. Print the mask for `mtcrf'. */
1109 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
1110 output_operand_lossage ("invalid %%R value");
1112 fprintf (file
, "%d", 128 >> (REGNO (x
) - 68));
1116 /* Low 5 bits of 32 - value */
1118 output_operand_lossage ("invalid %%s value");
1120 fprintf (file
, "%d", (32 - INT_LOWPART (x
)) & 31);
1124 /* Low 5 bits of 31 - value */
1126 output_operand_lossage ("invalid %%S value");
1128 fprintf (file
, "%d", (31 - INT_LOWPART (x
)) & 31);
1132 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1133 All floating-point operations except NE branch true and integer
1134 EQ, LT, GT, LTU and GTU also branch true. */
1135 if (GET_RTX_CLASS (GET_CODE (x
)) != '<')
1136 output_operand_lossage ("invalid %%t value");
1138 else if ((GET_MODE (XEXP (x
, 0)) == CCFPmode
1139 && GET_CODE (x
) != NE
)
1140 || GET_CODE (x
) == EQ
1141 || GET_CODE (x
) == LT
|| GET_CODE (x
) == GT
1142 || GET_CODE (x
) == LTU
|| GET_CODE (x
) == GTU
)
1149 /* Opposite of 't': write 4 if this jump operation will branch if true,
1151 if (GET_RTX_CLASS (GET_CODE (x
)) != '<')
1152 output_operand_lossage ("invalid %%t value");
1154 else if ((GET_MODE (XEXP (x
, 0)) == CCFPmode
1155 && GET_CODE (x
) != NE
)
1156 || GET_CODE (x
) == EQ
1157 || GET_CODE (x
) == LT
|| GET_CODE (x
) == GT
1158 || GET_CODE (x
) == LTU
|| GET_CODE (x
) == GTU
)
1165 /* High-order 16 bits of constant. */
1167 output_operand_lossage ("invalid %%u value");
1169 fprintf (file
, "0x%x", (INT_LOWPART (x
) >> 16) & 0xffff);
1173 /* Print `u' if this has an auto-increment or auto-decrement. */
1174 if (GET_CODE (x
) == MEM
1175 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
1176 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
))
1181 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1184 fprintf (file
, "%d",
1185 (INT_LOWPART (x
) & 0xffff) - 2 * (INT_LOWPART (x
) & 0x8000));
1187 print_operand (file
, x
, 0);
1191 /* If constant, low-order 16 bits of constant, unsigned.
1192 Otherwise, write normally. */
1194 fprintf (file
, "%d", INT_LOWPART (x
) & 0xffff);
1196 print_operand (file
, x
, 0);
1200 if (GET_CODE (x
) == MEM
1201 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x
, 0)))
1206 /* Like 'L', for third word of TImode */
1207 if (GET_CODE (x
) == REG
)
1208 fprintf (file
, "%d", REGNO (x
) + 2);
1209 else if (GET_CODE (x
) == MEM
)
1211 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1212 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1213 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
1215 output_address (plus_constant (XEXP (x
, 0), 8));
1220 /* X is a SYMBOL_REF. Write out the name preceded by a
1221 period and without any trailing data in brackets. Used for function
1223 if (GET_CODE (x
) != SYMBOL_REF
)
1227 RS6000_OUTPUT_BASENAME (file
, XSTR (x
, 0));
1231 /* Like 'L', for last word of TImode. */
1232 if (GET_CODE (x
) == REG
)
1233 fprintf (file
, "%d", REGNO (x
) + 3);
1234 else if (GET_CODE (x
) == MEM
)
1236 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1237 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1238 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
1240 output_address (plus_constant (XEXP (x
, 0), 12));
1245 if (GET_CODE (x
) == REG
)
1246 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1247 else if (GET_CODE (x
) == MEM
)
1249 /* We need to handle PRE_INC and PRE_DEC here, since we need to
1250 know the width from the mode. */
1251 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
1252 fprintf (file
, "%d(%d)", GET_MODE_SIZE (GET_MODE (x
)),
1253 REGNO (XEXP (XEXP (x
, 0), 0)));
1254 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1255 fprintf (file
, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x
)),
1256 REGNO (XEXP (XEXP (x
, 0), 0)));
1258 output_address (XEXP (x
, 0));
1261 output_addr_const (file
, x
);
1265 output_operand_lossage ("invalid %%xn code");
1269 /* Print the address of an operand. */
1272 print_operand_address (file
, x
)
1276 if (GET_CODE (x
) == REG
)
1277 fprintf (file
, "0(%d)", REGNO (x
));
1278 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
1280 output_addr_const (file
, x
);
1281 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
1282 of the toc pointer. */
1283 if (TARGET_MINIMAL_TOC
)
1284 fprintf (file
, "(30)");
1286 fprintf (file
, "(2)");
1288 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
1290 if (REGNO (XEXP (x
, 0)) == 0)
1291 fprintf (file
, "%d,%d", REGNO (XEXP (x
, 1)), REGNO (XEXP (x
, 0)));
1293 fprintf (file
, "%d,%d", REGNO (XEXP (x
, 0)), REGNO (XEXP (x
, 1)));
1295 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1296 fprintf (file
, "%d(%d)", INTVAL (XEXP (x
, 1)), REGNO (XEXP (x
, 0)));
1301 /* This page contains routines that are used to determine what the function
1302 prologue and epilogue code will do and write them out. */
1304 /* Return the first fixed-point register that is required to be saved. 32 if
1308 first_reg_to_save ()
1312 /* Find lowest numbered live register. */
1313 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
1314 if (regs_ever_live
[first_reg
])
1317 /* If profiling, then we must save/restore every register that contains
1318 a parameter before/after the .mcount call. Use registers from 30 down
1319 to 23 to do this. Don't use the frame pointer in reg 31.
1321 For now, save enough room for all of the parameter registers. */
1329 /* Similar, for FP regs. */
1332 first_fp_reg_to_save ()
1336 /* Find lowest numbered live register. */
1337 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
1338 if (regs_ever_live
[first_reg
])
1344 /* Return 1 if we need to save CR. */
1349 return regs_ever_live
[70] || regs_ever_live
[71] || regs_ever_live
[72];
1352 /* Compute the size of the save area in the stack, including the space for
1360 /* We have the six fixed words, plus the size of the register save
1361 areas, rounded to a double-word. */
1362 size
= 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2;
1369 /* Return non-zero if this function makes calls. */
1372 rs6000_makes_calls ()
1376 /* If we are profiling, we will be making a call to mcount. */
1380 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
1381 if (GET_CODE (insn
) == CALL_INSN
)
1387 /* Return non-zero if this function needs to push space on the stack. */
1390 rs6000_pushes_stack ()
1392 int total_size
= (rs6000_sa_size () + get_frame_size ()
1393 + current_function_outgoing_args_size
);
1395 /* We need to push the stack if a frame pointer is needed (because the
1396 stack might be dynamically adjusted), if we are debugging, if the
1397 total stack size is more than 220 bytes, or if we make calls. */
1399 return (frame_pointer_needed
|| write_symbols
!= NO_DEBUG
1401 || rs6000_makes_calls ());
1404 /* Write function prologue. */
1407 output_prolog (file
, size
)
1411 int first_reg
= first_reg_to_save ();
1412 int must_push
= rs6000_pushes_stack ();
1413 int first_fp_reg
= first_fp_reg_to_save ();
1414 int basic_size
= rs6000_sa_size ();
1415 int total_size
= (basic_size
+ size
+ current_function_outgoing_args_size
);
1417 /* Round size to multiple of 8 bytes. */
1418 total_size
= (total_size
+ 7) & ~7;
1420 /* Write .extern for any function we will call to save and restore fp
1422 if (first_fp_reg
< 62)
1423 fprintf (file
, "\t.extern ._savef%d\n\t.extern ._restf%d\n",
1424 first_fp_reg
- 32, first_fp_reg
- 32);
1426 /* Write .extern for truncation routines, if needed. */
1427 if (rs6000_trunc_used
&& ! trunc_defined
)
1429 fprintf (file
, "\t.extern .%s\n\t.extern .%s\n",
1430 RS6000_ITRUNC
, RS6000_UITRUNC
);
1433 /* Write .extern for AIX common mode routines, if needed. */
1434 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
1436 fputs ("\t.extern __mulh\n", file
);
1437 fputs ("\t.extern __mull\n", file
);
1438 fputs ("\t.extern __divss\n", file
);
1439 fputs ("\t.extern __divus\n", file
);
1440 fputs ("\t.extern __quoss\n", file
);
1441 fputs ("\t.extern __quous\n", file
);
1442 common_mode_defined
= 1;
1445 /* If we have to call a function to save fpr's, or if we are doing profiling,
1446 then we will be using LR. */
1447 if (first_fp_reg
< 62 || profile_flag
)
1448 regs_ever_live
[65] = 1;
1450 /* If we use the link register, get it into r0. */
1451 if (regs_ever_live
[65])
1452 asm_fprintf (file
, "\tmflr 0\n");
1454 /* If we need to save CR, put it into r12. */
1455 if (must_save_cr ())
1456 asm_fprintf (file
, "\tmfcr 12\n");
1458 /* Do any required saving of fpr's. If only one or two to save, do it
1459 ourself. Otherwise, call function. Note that since they are statically
1460 linked, we do not need a nop following them. */
1461 if (first_fp_reg
== 62)
1462 asm_fprintf (file
, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n");
1463 else if (first_fp_reg
== 63)
1464 asm_fprintf (file
, "\tstfd 31,-8(1)\n");
1465 else if (first_fp_reg
!= 64)
1466 asm_fprintf (file
, "\tbl ._savef%d\n", first_fp_reg
- 32);
1468 /* Now save gpr's. */
1469 if (! TARGET_POWER
|| first_reg
== 31)
1473 for (regno
= first_reg
,
1474 loc
= - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8;
1477 asm_fprintf (file
, "\t{st|stw} %d,%d(1)\n", regno
, loc
);
1480 else if (first_reg
!= 32)
1481 asm_fprintf (file
, "\t{stm|stmw} %d,%d(1)\n", first_reg
,
1482 - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8);
1484 /* Save lr if we used it. */
1485 if (regs_ever_live
[65])
1486 asm_fprintf (file
, "\t{st|stw} 0,8(1)\n");
1488 /* Save CR if we use any that must be preserved. */
1489 if (must_save_cr ())
1490 asm_fprintf (file
, "\t{st|stw} 12,4(1)\n");
1492 /* Update stack and set back pointer. */
1495 if (total_size
< 32767)
1496 asm_fprintf (file
, "\t{stu|stwu} 1,%d(1)\n", - total_size
);
1499 asm_fprintf (file
, "\t{cau 0,0,%d|lis 0,%d}\n\t{oril|ori} 0,0,%d\n",
1500 (total_size
>> 16) & 0xffff, total_size
& 0xffff);
1502 asm_fprintf (file
, "\tsubf 12,0,1\n");
1504 asm_fprintf (file
, "\t{sf|subfc} 12,0,1\n");
1505 asm_fprintf (file
, "\t{st|stw} 1,0(12)\n\tmr 1,12\n");
1509 /* Set frame pointer, if needed. */
1510 if (frame_pointer_needed
)
1511 asm_fprintf (file
, "\tmr 31,1\n");
1513 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
1514 TOC_TABLE address into register 30. */
1515 if (TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
1519 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 0);
1520 asm_fprintf (file
, "\t{l|lwz} 30,");
1521 assemble_name (file
, buf
);
1522 asm_fprintf (file
, "(2)\n");
1526 /* Write function epilogue. */
1529 output_epilog (file
, size
)
1533 int first_reg
= first_reg_to_save ();
1534 int must_push
= rs6000_pushes_stack ();
1535 int first_fp_reg
= first_fp_reg_to_save ();
1536 int basic_size
= rs6000_sa_size ();
1537 int total_size
= (basic_size
+ size
+ current_function_outgoing_args_size
);
1538 rtx insn
= get_last_insn ();
1540 /* Round size to multiple of 8 bytes. */
1541 total_size
= (total_size
+ 7) & ~7;
1543 /* If the last insn was a BARRIER, we don't have to write anything except
1545 if (GET_CODE (insn
) == NOTE
)
1546 insn
= prev_nonnote_insn (insn
);
1547 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
1549 /* If we have a frame pointer, a call to alloca, or a large stack
1550 frame, restore the old stack pointer using the backchain. Otherwise,
1551 we know what size to update it with. */
1552 if (frame_pointer_needed
|| current_function_calls_alloca
1553 || total_size
> 32767)
1554 asm_fprintf (file
, "\t{l|lwz} 1,0(1)\n");
1556 asm_fprintf (file
, "\t{cal 1,%d(1)|addi 1,1,%d}\n", total_size
);
1558 /* Get the old lr if we saved it. */
1559 if (regs_ever_live
[65])
1560 asm_fprintf (file
, "\t{l|lwz} 0,8(1)\n");
1562 /* Get the old cr if we saved it. */
1563 if (must_save_cr ())
1564 asm_fprintf (file
, "\t{l|lwz} 12,4(1)\n");
1566 /* Set LR here to try to overlap restores below. */
1567 if (regs_ever_live
[65])
1568 asm_fprintf (file
, "\tmtlr 0\n");
1570 /* Restore gpr's. */
1571 if (! TARGET_POWER
|| first_reg
== 31)
1575 for (regno
= first_reg
,
1576 loc
= - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8;
1579 asm_fprintf (file
, "\t{l|lwz} %d,%d(1)\n", regno
, loc
);
1582 else if (first_reg
!= 32)
1583 asm_fprintf (file
, "\t{lm|lmw} %d,%d(1)\n", first_reg
,
1584 - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8);
1586 /* Restore fpr's if we can do it without calling a function. */
1587 if (first_fp_reg
== 62)
1588 asm_fprintf (file
, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n");
1589 else if (first_fp_reg
== 63)
1590 asm_fprintf (file
, "\tlfd 31,-8(1)\n");
1592 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
1594 if (must_save_cr ())
1595 asm_fprintf (file
, "\tmtcrf %d,12\n",
1596 (regs_ever_live
[70] != 0) * 0x20
1597 + (regs_ever_live
[71] != 0) * 0x10
1598 + (regs_ever_live
[72] != 0) * 0x8);
1600 /* If we have to restore more than two FP registers, branch to the
1601 restore function. It will return to our caller. */
1602 if (first_fp_reg
< 62)
1603 asm_fprintf (file
, "\tb ._restf%d\n", first_fp_reg
- 32);
1605 asm_fprintf (file
, "\t{br|blr}\n");
1608 /* Output a traceback table here. See /usr/include/sys/debug.h for info
1611 We don't output a traceback table if -finhibit-size-directive was
1612 used. The documentation for -finhibit-size-directive reads
1613 ``don't output a @code{.size} assembler directive, or anything
1614 else that would cause trouble if the function is split in the
1615 middle, and the two halves are placed at locations far apart in
1616 memory.'' The traceback table has this property, since it
1617 includes the offset from the start of the function to the
1618 traceback table itself. */
1619 if (! flag_inhibit_size_directive
)
1621 char *fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
1622 int fixed_parms
, float_parms
, parm_info
;
1625 /* Need label immediately before tbtab, so we can compute its offset
1626 from the function start. */
1629 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
1630 ASM_OUTPUT_LABEL (file
, fname
);
1632 /* The .tbtab pseudo-op can only be used for the first eight
1633 expressions, since it can't handle the possibly variable
1634 length fields that follow. However, if you omit the optional
1635 fields, the assembler outputs zeros for all optional fields
1636 anyways, giving each variable length field is minimum length
1637 (as defined in sys/debug.h). Thus we can not use the .tbtab
1638 pseudo-op at all. */
1640 /* An all-zero word flags the start of the tbtab, for debuggers
1641 that have to find it by searching forward from the entry
1642 point or from the current pc. */
1643 fprintf (file
, "\t.long 0\n");
1645 /* Tbtab format type. Use format type 0. */
1646 fprintf (file
, "\t.byte 0,");
1648 /* Language type. Unfortunately, there doesn't seem to be any
1649 official way to get this info, so we use language_string. C
1650 is 0. C++ is 9. No number defined for Obj-C, so use the
1651 value for C for now. */
1652 if (! strcmp (language_string
, "GNU C")
1653 || ! strcmp (language_string
, "GNU Obj-C"))
1655 else if (! strcmp (language_string
, "GNU F77"))
1657 else if (! strcmp (language_string
, "GNU Ada"))
1659 else if (! strcmp (language_string
, "GNU PASCAL"))
1661 else if (! strcmp (language_string
, "GNU C++"))
1665 fprintf (file
, "%d,", i
);
1667 /* 8 single bit fields: global linkage (not set for C extern linkage,
1668 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
1669 from start of procedure stored in tbtab, internal function, function
1670 has controlled storage, function has no toc, function uses fp,
1671 function logs/aborts fp operations. */
1672 /* Assume that fp operations are used if any fp reg must be saved. */
1673 fprintf (file
, "%d,", (1 << 5) | ((first_fp_reg
!= 64) << 1));
1675 /* 6 bitfields: function is interrupt handler, name present in
1676 proc table, function calls alloca, on condition directives
1677 (controls stack walks, 3 bits), saves condition reg, saves
1679 /* The `function calls alloca' bit seems to be set whenever reg 31 is
1680 set up as a frame pointer, even when there is no alloca call. */
1681 fprintf (file
, "%d,",
1682 ((1 << 6) | (frame_pointer_needed
<< 5)
1683 | (must_save_cr () << 1) | (regs_ever_live
[65])));
1685 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
1687 fprintf (file
, "%d,",
1688 (must_push
<< 7) | (64 - first_fp_reg_to_save ()));
1690 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
1691 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
1694 /* Compute the parameter info from the function decl argument
1697 int next_parm_info_bit
;
1699 next_parm_info_bit
= 31;
1704 for (decl
= DECL_ARGUMENTS (current_function_decl
);
1705 decl
; decl
= TREE_CHAIN (decl
))
1707 rtx parameter
= DECL_INCOMING_RTL (decl
);
1708 enum machine_mode mode
= GET_MODE (parameter
);
1710 if (GET_CODE (parameter
) == REG
)
1712 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1720 else if (mode
== DFmode
)
1725 /* If only one bit will fit, don't or in this entry. */
1726 if (next_parm_info_bit
> 0)
1727 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
1728 next_parm_info_bit
-= 2;
1732 fixed_parms
+= ((GET_MODE_SIZE (mode
)
1733 + (UNITS_PER_WORD
- 1))
1735 next_parm_info_bit
-= 1;
1741 /* Number of fixed point parameters. */
1742 /* This is actually the number of words of fixed point parameters; thus
1743 an 8 byte struct counts as 2; and thus the maximum value is 8. */
1744 fprintf (file
, "%d,", fixed_parms
);
1746 /* 2 bitfields: number of floating point parameters (7 bits), parameters
1748 /* This is actually the number of fp registers that hold parameters;
1749 and thus the maximum value is 13. */
1750 /* Set parameters on stack bit if parameters are not in their original
1751 registers, regardless of whether they are on the stack? Xlc
1752 seems to set the bit when not optimizing. */
1753 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
1755 /* Optional fields follow. Some are variable length. */
1757 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
1759 /* There is an entry for each parameter in a register, in the order that
1760 they occur in the parameter list. Any intervening arguments on the
1761 stack are ignored. If the list overflows a long (max possible length
1762 34 bits) then completely leave off all elements that don't fit. */
1763 /* Only emit this long if there was at least one parameter. */
1764 if (fixed_parms
|| float_parms
)
1765 fprintf (file
, "\t.long %d\n", parm_info
);
1767 /* Offset from start of code to tb table. */
1768 fprintf (file
, "\t.long ");
1769 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
1770 RS6000_OUTPUT_BASENAME (file
, fname
);
1771 fprintf (file
, "-.");
1772 RS6000_OUTPUT_BASENAME (file
, fname
);
1773 fprintf (file
, "\n");
1775 /* Interrupt handler mask. */
1776 /* Omit this long, since we never set the interrupt handler bit
1779 /* Number of CTL (controlled storage) anchors. */
1780 /* Omit this long, since the has_ctl bit is never set above. */
1782 /* Displacement into stack of each CTL anchor. */
1783 /* Omit this list of longs, because there are no CTL anchors. */
1785 /* Length of function name. */
1786 fprintf (file
, "\t.short %d\n", strlen (fname
));
1788 /* Function name. */
1789 assemble_string (fname
, strlen (fname
));
1791 /* Register for alloca automatic storage; this is always reg 31.
1792 Only emit this if the alloca bit was set above. */
1793 if (frame_pointer_needed
)
1794 fprintf (file
, "\t.byte 31\n");
1798 /* Output a TOC entry. We derive the entry name from what is
1802 output_toc (file
, x
, labelno
)
1812 ASM_OUTPUT_INTERNAL_LABEL (file
, "LC", labelno
);
1814 /* Handle FP constants specially. Note that if we have a minimal
1815 TOC, things we put here aren't actually in the TOC, so we can allow
1817 if (GET_CODE (x
) == CONST_DOUBLE
1818 && GET_MODE (x
) == DFmode
1819 && TARGET_FLOAT_FORMAT
== HOST_FLOAT_FORMAT
1820 && BITS_PER_WORD
== HOST_BITS_PER_INT
1821 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
))
1823 if (TARGET_MINIMAL_TOC
)
1824 fprintf (file
, "\t.long %d\n\t.long %d\n",
1825 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
1827 fprintf (file
, "\t.tc FD_%x_%x[TC],%d,%d\n",
1828 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
),
1829 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
1832 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
1833 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
))
1835 rtx val
= operand_subword (x
, 0, 0, SFmode
);
1837 if (val
== 0 || GET_CODE (val
) != CONST_INT
)
1840 if (TARGET_MINIMAL_TOC
)
1841 fprintf (file
, "\t.long %d\n", INTVAL (val
));
1843 fprintf (file
, "\t.tc FS_%x[TC],%d\n", INTVAL (val
), INTVAL (val
));
1847 if (GET_CODE (x
) == CONST
)
1849 base
= XEXP (XEXP (x
, 0), 0);
1850 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
1853 if (GET_CODE (base
) == SYMBOL_REF
)
1854 name
= XSTR (base
, 0);
1855 else if (GET_CODE (base
) == LABEL_REF
)
1856 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (base
, 0)));
1857 else if (GET_CODE (base
) == CODE_LABEL
)
1858 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
1862 if (TARGET_MINIMAL_TOC
)
1863 fprintf (file
, "\t.long ");
1866 fprintf (file
, "\t.tc ");
1867 RS6000_OUTPUT_BASENAME (file
, name
);
1870 fprintf (file
, ".N%d", - offset
);
1872 fprintf (file
, ".P%d", offset
);
1874 fprintf (file
, "[TC],");
1876 output_addr_const (file
, x
);
1877 fprintf (file
, "\n");
1880 /* Output an assembler pseudo-op to write an ASCII string of N characters
1881 starting at P to FILE.
1883 On the RS/6000, we have to do this using the .byte operation and
1884 write out special characters outside the quoted string.
1885 Also, the assembler is broken; very long strings are truncated,
1886 so we must artificially break them up early. */
1889 output_ascii (file
, p
, n
)
1895 int i
, count_string
;
1896 char *for_string
= "\t.byte \"";
1897 char *for_decimal
= "\t.byte ";
1898 char *to_close
= NULL
;
1901 for (i
= 0; i
< n
; i
++)
1904 if (c
>= ' ' && c
< 0177)
1907 fputs (for_string
, file
);
1910 /* Write two quotes to get one. */
1918 for_decimal
= "\"\n\t.byte ";
1922 if (count_string
>= 512)
1924 fputs (to_close
, file
);
1926 for_string
= "\t.byte \"";
1927 for_decimal
= "\t.byte ";
1935 fputs (for_decimal
, file
);
1936 fprintf (file
, "%d", c
);
1938 for_string
= "\n\t.byte \"";
1945 /* Now close the string if we have written one. Then end the line. */
1947 fprintf (file
, to_close
);
1950 /* Generate a unique section name for FILENAME for a section type
1951 represented by SECTION_DESC. Output goes into BUF.
1953 SECTION_DESC can be any string, as long as it is different for each
1954 possible section type.
1956 We name the section in the same manner as xlc. The name begins with an
1957 underscore followed by the filename (after stripping any leading directory
1958 names) with the last period replaced by the string SECTION_DESC. If
1959 FILENAME does not contain a period, SECTION_DESC is appended to the end of
1963 rs6000_gen_section_name (buf
, filename
, section_desc
)
1968 char *q
, *after_last_slash
, *last_period
;
1972 after_last_slash
= filename
;
1973 for (q
= filename
; *q
; q
++)
1976 after_last_slash
= q
+ 1;
1981 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
1982 *buf
= (char *) permalloc (len
);
1987 for (q
= after_last_slash
; *q
; q
++)
1989 if (q
== last_period
)
1991 strcpy (p
, section_desc
);
1992 p
+= strlen (section_desc
);
1995 else if (isalnum (*q
))
1999 if (last_period
== 0)
2000 strcpy (p
, section_desc
);
2005 /* Write function profiler code. */
2008 output_function_profiler (file
, labelno
)
2012 /* The last used parameter register. */
2017 /* Set up a TOC entry for the profiler label. */
2019 ASM_OUTPUT_INTERNAL_LABEL (file
, "LPC", labelno
);
2020 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
2021 if (TARGET_MINIMAL_TOC
)
2023 fprintf (file
, "\t.long ");
2024 assemble_name (file
, buf
);
2025 fprintf (file
, "\n");
2029 fprintf (file
, "\t.tc\t");
2030 assemble_name (file
, buf
);
2031 fprintf (file
, "[TC],");
2032 assemble_name (file
, buf
);
2033 fprintf (file
, "\n");
2037 /* Figure out last used parameter register. The proper thing to do is
2038 to walk incoming args of the function. A function might have live
2039 parameter registers even if it has no incoming args. */
2041 for (last_parm_reg
= 10;
2042 last_parm_reg
> 2 && ! regs_ever_live
[last_parm_reg
];
2046 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
2047 it might be set up as the frame pointer. */
2049 for (i
= 3, j
= 30; i
<= last_parm_reg
; i
++, j
--)
2050 fprintf (file
, "\tai %d,%d,0\n", j
, i
);
2052 /* Load location address into r3, and call mcount. */
2054 ASM_GENERATE_INTERNAL_LABEL (buf
, "LPC", labelno
);
2055 fprintf (file
, "\tl 3,");
2056 assemble_name (file
, buf
);
2057 fprintf (file
, "(2)\n\tbl .mcount\n");
2059 /* Restore parameter registers. */
2061 for (i
= 3, j
= 30; i
<= last_parm_reg
; i
++, j
--)
2062 fprintf (file
, "\tai %d,%d,0\n", i
, j
);
2065 /* Adjust the cost of a scheduling dependency. Return the new cost of
2066 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2069 rs6000_adjust_cost (insn
, link
, dep_insn
, cost
)
2075 if (! recog_memoized (insn
))
2078 if (REG_NOTE_KIND (link
) != 0)
2081 if (REG_NOTE_KIND (link
) == 0)
2083 /* Data dependency; DEP_INSN writes a register that INSN reads some
2086 /* Tell the first scheduling pass about the latency between a mtctr
2087 and bctr (and mtlr and br/blr). The first scheduling pass will not
2088 know about this latency since the mtctr instruction, which has the
2089 latency associated to it, will be generated by reload. */
2090 if (get_attr_type (insn
) == TYPE_JMPREG
)
2091 return TARGET_POWER
? 5 : 4;
2093 /* Fall out to return default cost. */