1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "hard-reg-set.h"
27 #include "insn-config.h"
28 #include "conditions.h"
29 #include "insn-flags.h"
31 #include "insn-attr.h"
38 extern char *language_string
;
39 extern int profile_block_flag
;
41 #define min(A,B) ((A) < (B) ? (A) : (B))
42 #define max(A,B) ((A) > (B) ? (A) : (B))
46 enum processor_type rs6000_cpu
;
47 char *rs6000_cpu_string
;
49 /* Set to non-zero by "fix" operation to indicate that itrunc and
50 uitrunc must be defined. */
52 int rs6000_trunc_used
;
54 /* Set to non-zero once they have been defined. */
56 static int trunc_defined
;
58 /* Set to non-zero once AIX common-mode calls have been defined. */
59 static int common_mode_defined
;
60 /* Save information from a "cmpxx" operation until the branch or scc is
63 rtx rs6000_compare_op0
, rs6000_compare_op1
;
64 int rs6000_compare_fp_p
;
66 /* Override command line options. Mostly we process the processor
67 type and sometimes adjust other TARGET_ options. */
70 rs6000_override_options ()
74 /* Simplify the entries below by making a mask for any POWER
75 variant and any PowerPC variant. */
77 #define POWER_MASKS (MASK_POWER | MASK_POWER2)
78 #define POWERPC_MASKS (MASK_POWERPC | MASK_PPC_GPOPT \
79 | MASK_PPC_GFXOPT | MASK_POWERPC64)
80 #define POWERPC_OPT_MASKS (MASK_PPC_GPOPT | MASK_PPC_GFXOPT)
84 char *name
; /* Canonical processor name. */
85 enum processor_type processor
; /* Processor type enum value. */
86 int target_enable
; /* Target flags to enable. */
87 int target_disable
; /* Target flags to disable. */
88 } processor_target_table
[]
89 = {{"common", PROCESSOR_COMMON
, 0, POWER_MASKS
| POWERPC_MASKS
},
90 {"power", PROCESSOR_POWER
,
92 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
93 {"powerpc", PROCESSOR_POWERPC
,
94 MASK_POWERPC
| MASK_NEW_MNEMONICS
,
95 POWER_MASKS
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
96 {"rios", PROCESSOR_RIOS1
,
98 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
99 {"rios1", PROCESSOR_RIOS1
,
101 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
102 {"rsc", PROCESSOR_PPC601
,
104 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
105 {"rsc1", PROCESSOR_PPC601
,
107 MASK_POWER2
| POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
108 {"rios2", PROCESSOR_RIOS2
,
109 MASK_POWER
| MASK_POWER2
,
110 POWERPC_MASKS
| MASK_NEW_MNEMONICS
},
111 {"601", PROCESSOR_PPC601
,
112 MASK_POWER
| MASK_POWERPC
| MASK_NEW_MNEMONICS
,
113 MASK_POWER2
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
114 {"mpc601", PROCESSOR_PPC601
,
115 MASK_POWER
| MASK_POWERPC
| MASK_NEW_MNEMONICS
,
116 MASK_POWER2
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
117 {"ppc601", PROCESSOR_PPC601
,
118 MASK_POWER
| MASK_POWERPC
| MASK_NEW_MNEMONICS
,
119 MASK_POWER2
| POWERPC_OPT_MASKS
| MASK_POWERPC64
},
120 {"603", PROCESSOR_PPC603
,
121 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
122 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
123 {"mpc603", PROCESSOR_PPC603
,
124 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
125 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
126 {"ppc603", PROCESSOR_PPC603
,
127 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
128 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
129 {"604", PROCESSOR_PPC604
,
130 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
131 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
132 {"mpc604", PROCESSOR_PPC604
,
133 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
134 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
135 {"ppc604", PROCESSOR_PPC604
,
136 MASK_POWERPC
| MASK_PPC_GFXOPT
| MASK_NEW_MNEMONICS
,
137 POWER_MASKS
| MASK_PPC_GPOPT
| MASK_POWERPC64
},
138 {"620", PROCESSOR_PPC620
,
139 (MASK_POWERPC
| POWERPC_OPT_MASKS
| MASK_POWERPC64
140 | MASK_NEW_MNEMONICS
),
142 {"mpc620", PROCESSOR_PPC620
,
143 (MASK_POWERPC
| POWERPC_OPT_MASKS
| MASK_POWERPC64
144 | MASK_NEW_MNEMONICS
),
146 {"ppc620", PROCESSOR_PPC620
,
147 (MASK_POWERPC
| POWERPC_OPT_MASKS
| MASK_POWERPC64
148 | MASK_NEW_MNEMONICS
),
151 int ptt_size
= sizeof (processor_target_table
) / sizeof (struct ptt
);
153 profile_block_flag
= 0;
155 /* Identify the processor type */
156 if (rs6000_cpu_string
== 0)
157 rs6000_cpu
= PROCESSOR_DEFAULT
;
160 for (i
= 0; i
< ptt_size
; i
++)
161 if (! strcmp (rs6000_cpu_string
, processor_target_table
[i
].name
))
163 rs6000_cpu
= processor_target_table
[i
].processor
;
164 target_flags
|= processor_target_table
[i
].target_enable
;
165 target_flags
&= ~processor_target_table
[i
].target_disable
;
171 error ("bad value (%s) for -mcpu= switch", rs6000_cpu_string
);
172 rs6000_cpu_string
= "default";
173 rs6000_cpu
= PROCESSOR_DEFAULT
;
178 /* Return non-zero if this function is known to have a null epilogue. */
183 return (reload_completed
184 && first_reg_to_save () == 32
185 && first_fp_reg_to_save () == 64
186 && ! regs_ever_live
[65]
187 && ! rs6000_pushes_stack ());
190 /* Returns 1 always. */
193 any_operand (op
, mode
)
195 enum machine_mode mode
;
200 /* Return 1 if OP is a constant that can fit in a D field. */
203 short_cint_operand (op
, mode
)
205 enum machine_mode mode
;
207 return (GET_CODE (op
) == CONST_INT
208 && (unsigned) (INTVAL (op
) + 0x8000) < 0x10000);
211 /* Similar for a unsigned D field. */
214 u_short_cint_operand (op
, mode
)
216 enum machine_mode mode
;
218 return (GET_CODE (op
) == CONST_INT
&& (INTVAL (op
) & 0xffff0000) == 0);
221 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
224 non_short_cint_operand (op
, mode
)
226 enum machine_mode mode
;
228 return (GET_CODE (op
) == CONST_INT
229 && (unsigned) (INTVAL (op
) + 0x8000) >= 0x10000);
232 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
236 gpc_reg_operand (op
, mode
)
238 enum machine_mode mode
;
240 return (register_operand (op
, mode
)
241 && (GET_CODE (op
) != REG
|| REGNO (op
) >= 67 || REGNO (op
) < 64));
244 /* Returns 1 if OP is either a pseudo-register or a register denoting a
248 cc_reg_operand (op
, mode
)
250 enum machine_mode mode
;
252 return (register_operand (op
, mode
)
253 && (GET_CODE (op
) != REG
254 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
255 || CR_REGNO_P (REGNO (op
))));
258 /* Returns 1 if OP is either a constant integer valid for a D-field or a
259 non-special register. If a register, it must be in the proper mode unless
263 reg_or_short_operand (op
, mode
)
265 enum machine_mode mode
;
267 return short_cint_operand (op
, mode
) || gpc_reg_operand (op
, mode
);
270 /* Similar, except check if the negation of the constant would be valid for
274 reg_or_neg_short_operand (op
, mode
)
276 enum machine_mode mode
;
278 if (GET_CODE (op
) == CONST_INT
)
279 return CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P');
281 return gpc_reg_operand (op
, mode
);
284 /* Return 1 if the operand is either a register or an integer whose high-order
288 reg_or_u_short_operand (op
, mode
)
290 enum machine_mode mode
;
292 if (GET_CODE (op
) == CONST_INT
293 && (INTVAL (op
) & 0xffff0000) == 0)
296 return gpc_reg_operand (op
, mode
);
299 /* Return 1 is the operand is either a non-special register or ANY
303 reg_or_cint_operand (op
, mode
)
305 enum machine_mode mode
;
307 return GET_CODE (op
) == CONST_INT
|| gpc_reg_operand (op
, mode
);
310 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a register
311 with one instruction per word. We only do this if we can safely read
312 CONST_DOUBLE_{LOW,HIGH}. */
315 easy_fp_constant (op
, mode
)
317 register enum machine_mode mode
;
321 if (GET_CODE (op
) != CONST_DOUBLE
322 || GET_MODE (op
) != mode
323 || GET_MODE_CLASS (mode
) != MODE_FLOAT
)
326 high
= operand_subword (op
, 0, 0, mode
);
327 low
= operand_subword (op
, 1, 0, mode
);
329 if (high
== 0 || ! input_operand (high
, word_mode
))
332 return (mode
== SFmode
333 || (low
!= 0 && input_operand (low
, word_mode
)));
336 /* Return 1 if the operand is either a floating-point register, a pseudo
337 register, or memory. */
340 fp_reg_or_mem_operand (op
, mode
)
342 enum machine_mode mode
;
344 return (memory_operand (op
, mode
)
345 || (register_operand (op
, mode
)
346 && (GET_CODE (op
) != REG
347 || REGNO (op
) >= FIRST_PSEUDO_REGISTER
348 || FP_REGNO_P (REGNO (op
)))));
351 /* Return 1 if the operand is either an easy FP constant (see above) or
355 mem_or_easy_const_operand (op
, mode
)
357 enum machine_mode mode
;
359 return memory_operand (op
, mode
) || easy_fp_constant (op
, mode
);
362 /* Return 1 if the operand is either a non-special register or an item
363 that can be used as the operand of an SI add insn. */
366 add_operand (op
, mode
)
368 enum machine_mode mode
;
370 return (reg_or_short_operand (op
, mode
)
371 || (GET_CODE (op
) == CONST_INT
&& (INTVAL (op
) & 0xffff) == 0));
374 /* Return 1 if OP is a constant but not a valid add_operand. */
377 non_add_cint_operand (op
, mode
)
379 enum machine_mode mode
;
381 return (GET_CODE (op
) == CONST_INT
382 && (unsigned) (INTVAL (op
) + 0x8000) >= 0x10000
383 && (INTVAL (op
) & 0xffff) != 0);
386 /* Return 1 if the operand is a non-special register or a constant that
387 can be used as the operand of an OR or XOR insn on the RS/6000. */
390 logical_operand (op
, mode
)
392 enum machine_mode mode
;
394 return (gpc_reg_operand (op
, mode
)
395 || (GET_CODE (op
) == CONST_INT
396 && ((INTVAL (op
) & 0xffff0000) == 0
397 || (INTVAL (op
) & 0xffff) == 0)));
400 /* Return 1 if C is a constant that is not a logical operand (as
404 non_logical_cint_operand (op
, mode
)
406 enum machine_mode mode
;
408 return (GET_CODE (op
) == CONST_INT
409 && (INTVAL (op
) & 0xffff0000) != 0
410 && (INTVAL (op
) & 0xffff) != 0);
413 /* Return 1 if C is a constant that can be encoded in a mask on the
414 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
415 Reject all ones and all zeros, since these should have been optimized
416 away and confuse the making of MB and ME. */
426 if (c
== 0 || c
== ~0)
429 last_bit_value
= c
& 1;
431 for (i
= 1; i
< 32; i
++)
432 if (((c
>>= 1) & 1) != last_bit_value
)
433 last_bit_value
^= 1, transitions
++;
435 return transitions
<= 2;
438 /* Return 1 if the operand is a constant that is a mask on the RS/6000. */
441 mask_operand (op
, mode
)
443 enum machine_mode mode
;
445 return GET_CODE (op
) == CONST_INT
&& mask_constant (INTVAL (op
));
448 /* Return 1 if the operand is either a non-special register or a
449 constant that can be used as the operand of an RS/6000 logical AND insn. */
452 and_operand (op
, mode
)
454 enum machine_mode mode
;
456 return (reg_or_short_operand (op
, mode
)
457 || logical_operand (op
, mode
)
458 || mask_operand (op
, mode
));
461 /* Return 1 if the operand is a constant but not a valid operand for an AND
465 non_and_cint_operand (op
, mode
)
467 enum machine_mode mode
;
469 return GET_CODE (op
) == CONST_INT
&& ! and_operand (op
, mode
);
472 /* Return 1 if the operand is a general register or memory operand. */
475 reg_or_mem_operand (op
, mode
)
477 register enum machine_mode mode
;
479 return gpc_reg_operand (op
, mode
) || memory_operand (op
, mode
);
482 /* Return 1 if the operand, used inside a MEM, is a valid first argument
483 to CALL. This is a SYMBOL_REF or a pseudo-register, which will be
487 call_operand (op
, mode
)
489 enum machine_mode mode
;
491 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
494 return (GET_CODE (op
) == SYMBOL_REF
495 || (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
));
499 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
503 current_file_function_operand (op
, mode
)
505 enum machine_mode mode
;
507 return (GET_CODE (op
) == SYMBOL_REF
508 && (SYMBOL_REF_FLAG (op
)
509 || op
== XEXP (DECL_RTL (current_function_decl
), 0)));
513 /* Return 1 if this operand is a valid input for a move insn. */
516 input_operand (op
, mode
)
518 enum machine_mode mode
;
520 /* Memory is always valid. */
521 if (memory_operand (op
, mode
))
524 /* For floating-point, easy constants are valid. */
525 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
527 && easy_fp_constant (op
, mode
))
530 /* For floating-point or multi-word mode, the only remaining valid type
532 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
533 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
534 return register_operand (op
, mode
);
536 /* The only cases left are integral modes one word or smaller (we
537 do not get called for MODE_CC values). These can be in any
539 if (register_operand (op
, mode
))
542 /* For HImode and QImode, any constant is valid. */
543 if ((mode
== HImode
|| mode
== QImode
)
544 && GET_CODE (op
) == CONST_INT
)
547 /* Otherwise, we will be doing this SET with an add, so anything valid
548 for an add will be valid. */
549 return add_operand (op
, mode
);
552 /* Return 1 if OP is a load multiple operation. It is known to be a
553 PARALLEL and the first section will be tested. */
556 load_multiple_operation (op
, mode
)
558 enum machine_mode mode
;
560 int count
= XVECLEN (op
, 0);
565 /* Perform a quick check so we don't blow up below. */
567 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
568 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != REG
569 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != MEM
)
572 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, 0)));
573 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, 0)), 0);
575 for (i
= 1; i
< count
; i
++)
577 rtx elt
= XVECEXP (op
, 0, i
);
579 if (GET_CODE (elt
) != SET
580 || GET_CODE (SET_DEST (elt
)) != REG
581 || GET_MODE (SET_DEST (elt
)) != SImode
582 || REGNO (SET_DEST (elt
)) != dest_regno
+ i
583 || GET_CODE (SET_SRC (elt
)) != MEM
584 || GET_MODE (SET_SRC (elt
)) != SImode
585 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
586 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
587 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
588 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != i
* 4)
595 /* Similar, but tests for store multiple. Here, the second vector element
596 is a CLOBBER. It will be tested later. */
599 store_multiple_operation (op
, mode
)
601 enum machine_mode mode
;
603 int count
= XVECLEN (op
, 0) - 1;
608 /* Perform a quick check so we don't blow up below. */
610 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
611 || GET_CODE (SET_DEST (XVECEXP (op
, 0, 0))) != MEM
612 || GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != REG
)
615 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, 0)));
616 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, 0)), 0);
618 for (i
= 1; i
< count
; i
++)
620 rtx elt
= XVECEXP (op
, 0, i
+ 1);
622 if (GET_CODE (elt
) != SET
623 || GET_CODE (SET_SRC (elt
)) != REG
624 || GET_MODE (SET_SRC (elt
)) != SImode
625 || REGNO (SET_SRC (elt
)) != src_regno
+ i
626 || GET_CODE (SET_DEST (elt
)) != MEM
627 || GET_MODE (SET_DEST (elt
)) != SImode
628 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
629 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
630 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
631 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != i
* 4)
638 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
639 We only check the opcode against the mode of the CC value here. */
642 branch_comparison_operator (op
, mode
)
644 enum machine_mode mode
;
646 enum rtx_code code
= GET_CODE (op
);
647 enum machine_mode cc_mode
;
649 if (GET_RTX_CLASS (code
) != '<')
652 cc_mode
= GET_MODE (XEXP (op
, 0));
653 if (GET_MODE_CLASS (cc_mode
) != MODE_CC
)
656 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
657 && cc_mode
== CCUNSmode
)
660 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
661 && (cc_mode
!= CCUNSmode
))
667 /* Return 1 if OP is a comparison operation that is valid for an scc insn.
668 We check the opcode against the mode of the CC value and disallow EQ or
669 NE comparisons for integers. */
672 scc_comparison_operator (op
, mode
)
674 enum machine_mode mode
;
676 enum rtx_code code
= GET_CODE (op
);
677 enum machine_mode cc_mode
;
679 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
682 if (GET_RTX_CLASS (code
) != '<')
685 cc_mode
= GET_MODE (XEXP (op
, 0));
686 if (GET_MODE_CLASS (cc_mode
) != MODE_CC
)
689 if (code
== NE
&& cc_mode
!= CCFPmode
)
692 if ((code
== GT
|| code
== LT
|| code
== GE
|| code
== LE
)
693 && cc_mode
== CCUNSmode
)
696 if ((code
== GTU
|| code
== LTU
|| code
== GEU
|| code
== LEU
)
697 && (cc_mode
!= CCUNSmode
))
700 if (cc_mode
== CCEQmode
&& code
!= EQ
&& code
!= NE
)
706 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
707 mask required to convert the result of a rotate insn into a shift
708 left insn of SHIFTOP bits. Both are known to be CONST_INT. */
711 includes_lshift_p (shiftop
, andop
)
712 register rtx shiftop
;
715 int shift_mask
= (~0 << INTVAL (shiftop
));
717 return (INTVAL (andop
) & ~shift_mask
) == 0;
720 /* Similar, but for right shift. */
723 includes_rshift_p (shiftop
, andop
)
724 register rtx shiftop
;
727 unsigned shift_mask
= ~0;
729 shift_mask
>>= INTVAL (shiftop
);
731 return (INTVAL (andop
) & ~ shift_mask
) == 0;
734 /* Return the register class of a scratch register needed to copy IN into
735 or out of a register in CLASS in MODE. If it can be done directly,
736 NO_REGS is returned. */
739 secondary_reload_class (class, mode
, in
)
740 enum reg_class
class;
741 enum machine_mode mode
;
744 int regno
= true_regnum (in
);
746 if (regno
>= FIRST_PSEUDO_REGISTER
)
749 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
751 if (class == GENERAL_REGS
|| class == BASE_REGS
752 || (regno
>= 0 && INT_REGNO_P (regno
)))
755 /* Constants, memory, and FP registers can go into FP registers. */
756 if ((regno
== -1 || FP_REGNO_P (regno
))
757 && (class == FLOAT_REGS
|| class == NON_SPECIAL_REGS
))
760 /* We can copy among the CR registers. */
761 if ((class == CR_REGS
|| class == CR0_REGS
)
762 && regno
>= 0 && CR_REGNO_P (regno
))
765 /* Otherwise, we need GENERAL_REGS. */
769 /* Given a comparison operation, return the bit number in CCR to test. We
770 know this is a valid comparison.
772 SCC_P is 1 if this is for an scc. That means that %D will have been
773 used instead of %C, so the bits will be in different places.
775 Return -1 if OP isn't a valid comparison for some reason. */
782 enum rtx_code code
= GET_CODE (op
);
783 enum machine_mode cc_mode
;
787 if (GET_RTX_CLASS (code
) != '<')
790 cc_mode
= GET_MODE (XEXP (op
, 0));
791 cc_regnum
= REGNO (XEXP (op
, 0));
792 base_bit
= 4 * (cc_regnum
- 68);
794 /* In CCEQmode cases we have made sure that the result is always in the
795 third bit of the CR field. */
797 if (cc_mode
== CCEQmode
)
803 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
812 /* If floating-point, we will have done a cror to put the bit in the
813 unordered position. So test that bit. For integer, this is ! LT
814 unless this is an scc insn. */
815 return cc_mode
== CCFPmode
|| scc_p
? base_bit
+ 3 : base_bit
;
818 return cc_mode
== CCFPmode
|| scc_p
? base_bit
+ 3 : base_bit
+ 1;
825 /* Print an operand. Recognize special options, documented below. */
828 print_operand (file
, x
, code
)
836 /* These macros test for integers and extract the low-order bits. */
838 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
839 && GET_MODE (X) == VOIDmode)
841 #define INT_LOWPART(X) \
842 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
847 /* Write out an instruction after the call which may be replaced
848 with glue code by the loader. This depends on the AIX version. */
849 asm_fprintf (file
, RS6000_CALL_GLUE
);
853 /* If X is a constant integer whose low-order 5 bits are zero,
854 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
855 in the AIX assembler where "sri" with a zero shift count
856 write a trash instruction. */
857 if (GET_CODE (x
) == CONST_INT
&& (INTVAL (x
) & 31) == 0)
864 /* Low-order 16 bits of constant, unsigned. */
866 output_operand_lossage ("invalid %%b value");
868 fprintf (file
, "%d", INT_LOWPART (x
) & 0xffff);
872 /* This is an optional cror needed for LE or GE floating-point
873 comparisons. Otherwise write nothing. */
874 if ((GET_CODE (x
) == LE
|| GET_CODE (x
) == GE
)
875 && GET_MODE (XEXP (x
, 0)) == CCFPmode
)
877 int base_bit
= 4 * (REGNO (XEXP (x
, 0)) - 68);
879 fprintf (file
, "cror %d,%d,%d\n\t", base_bit
+ 3,
880 base_bit
+ 2, base_bit
+ (GET_CODE (x
) == GE
));
885 /* Similar, except that this is for an scc, so we must be able to
886 encode the test in a single bit that is one. We do the above
887 for any LE, GE, GEU, or LEU and invert the bit for NE. */
888 if (GET_CODE (x
) == LE
|| GET_CODE (x
) == GE
889 || GET_CODE (x
) == LEU
|| GET_CODE (x
) == GEU
)
891 int base_bit
= 4 * (REGNO (XEXP (x
, 0)) - 68);
893 fprintf (file
, "cror %d,%d,%d\n\t", base_bit
+ 3,
895 base_bit
+ (GET_CODE (x
) == GE
|| GET_CODE (x
) == GEU
));
898 else if (GET_CODE (x
) == NE
)
900 int base_bit
= 4 * (REGNO (XEXP (x
, 0)) - 68);
902 fprintf (file
, "crnor %d,%d,%d\n\t", base_bit
+ 3,
903 base_bit
+ 2, base_bit
+ 2);
908 /* X is a CR register. Print the number of the third bit of the CR */
909 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
910 output_operand_lossage ("invalid %%E value");
912 fprintf(file
, "%d", 4 * (REGNO (x
) - 68) + 3);
916 /* X is a CR register. Print the shift count needed to move it
917 to the high-order four bits. */
918 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
919 output_operand_lossage ("invalid %%f value");
921 fprintf (file
, "%d", 4 * (REGNO (x
) - 68));
925 /* Similar, but print the count for the rotate in the opposite
927 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
928 output_operand_lossage ("invalid %%F value");
930 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - 68));
934 /* X is a constant integer. If it is negative, print "m",
935 otherwise print "z". This is to make a aze or ame insn. */
936 if (GET_CODE (x
) != CONST_INT
)
937 output_operand_lossage ("invalid %%G value");
938 else if (INTVAL (x
) >= 0)
945 /* If constant, output low-order five bits. Otherwise,
948 fprintf (file
, "%d", INT_LOWPART (x
) & 31);
950 print_operand (file
, x
, 0);
954 /* X must be a constant. Output the low order 5 bits plus 24. */
956 output_operand_lossage ("invalid %%H value");
958 fprintf (file
, "%d", (INT_LOWPART (x
) + 24) & 31);
962 /* Print `i' if this is a constant, else nothing. */
968 /* Write the bit number in CCR for jump. */
971 output_operand_lossage ("invalid %%j code");
973 fprintf (file
, "%d", i
);
977 /* Similar, but add one for shift count in rlinm for scc and pass
978 scc flag to `ccr_bit'. */
981 output_operand_lossage ("invalid %%J code");
983 /* If we want bit 31, write a shift count of zero, not 32. */
984 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
988 /* X must be a constant. Write the 1's complement of the
991 output_operand_lossage ("invalid %%k value");
993 fprintf (file
, "%d", ~ INT_LOWPART (x
));
997 /* Write second word of DImode or DFmode reference. Works on register
998 or non-indexed memory only. */
999 if (GET_CODE (x
) == REG
)
1000 fprintf (file
, "%d", REGNO (x
) + 1);
1001 else if (GET_CODE (x
) == MEM
)
1003 /* Handle possible auto-increment. Since it is pre-increment and
1004 we have already done it, we can just use an offset of four. */
1005 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1006 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1007 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
1009 output_address (plus_constant (XEXP (x
, 0), 4));
1014 /* MB value for a mask operand. */
1015 if (! mask_operand (x
, VOIDmode
))
1016 output_operand_lossage ("invalid %%m value");
1018 val
= INT_LOWPART (x
);
1020 /* If the high bit is set and the low bit is not, the value is zero.
1021 If the high bit is zero, the value is the first 1 bit we find from
1023 if (val
< 0 && (val
& 1) == 0)
1025 fprintf (file
, "0");
1030 for (i
= 1; i
< 32; i
++)
1031 if ((val
<<= 1) < 0)
1033 fprintf (file
, "%d", i
);
1037 /* Otherwise, look for the first 0 bit from the right. The result is its
1038 number plus 1. We know the low-order bit is one. */
1039 for (i
= 0; i
< 32; i
++)
1040 if (((val
>>= 1) & 1) == 0)
1043 /* If we ended in ...01, I would be 0. The correct value is 31, so
1045 fprintf (file
, "%d", 31 - i
);
1049 /* ME value for a mask operand. */
1050 if (! mask_operand (x
, VOIDmode
))
1051 output_operand_lossage ("invalid %%m value");
1053 val
= INT_LOWPART (x
);
1055 /* If the low bit is set and the high bit is not, the value is 31.
1056 If the low bit is zero, the value is the first 1 bit we find from
1058 if ((val
& 1) && val
>= 0)
1063 else if ((val
& 1) == 0)
1065 for (i
= 0; i
< 32; i
++)
1066 if ((val
>>= 1) & 1)
1069 /* If we had ....10, I would be 0. The result should be
1070 30, so we need 30 - i. */
1071 fprintf (file
, "%d", 30 - i
);
1075 /* Otherwise, look for the first 0 bit from the left. The result is its
1076 number minus 1. We know the high-order bit is one. */
1077 for (i
= 0; i
< 32; i
++)
1078 if ((val
<<= 1) >= 0)
1081 fprintf (file
, "%d", i
);
1085 /* Write the number of elements in the vector times 4. */
1086 if (GET_CODE (x
) != PARALLEL
)
1087 output_operand_lossage ("invalid %%N value");
1089 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
1093 /* Similar, but subtract 1 first. */
1094 if (GET_CODE (x
) != PARALLEL
)
1095 output_operand_lossage ("invalid %%N value");
1097 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
1101 /* X is a CONST_INT that is a power of two. Output the logarithm. */
1103 || (i
= exact_log2 (INT_LOWPART (x
))) < 0)
1104 output_operand_lossage ("invalid %%p value");
1106 fprintf (file
, "%d", i
);
1110 /* The operand must be an indirect memory reference. The result
1111 is the register number. */
1112 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
1113 || REGNO (XEXP (x
, 0)) >= 32)
1114 output_operand_lossage ("invalid %%P value");
1116 fprintf (file
, "%d", REGNO (XEXP (x
, 0)));
1120 /* X is a CR register. Print the mask for `mtcrf'. */
1121 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
1122 output_operand_lossage ("invalid %%R value");
1124 fprintf (file
, "%d", 128 >> (REGNO (x
) - 68));
1128 /* Low 5 bits of 32 - value */
1130 output_operand_lossage ("invalid %%s value");
1132 fprintf (file
, "%d", (32 - INT_LOWPART (x
)) & 31);
1136 /* Low 5 bits of 31 - value */
1138 output_operand_lossage ("invalid %%S value");
1140 fprintf (file
, "%d", (31 - INT_LOWPART (x
)) & 31);
1144 /* Write 12 if this jump operation will branch if true, 4 otherwise.
1145 All floating-point operations except NE branch true and integer
1146 EQ, LT, GT, LTU and GTU also branch true. */
1147 if (GET_RTX_CLASS (GET_CODE (x
)) != '<')
1148 output_operand_lossage ("invalid %%t value");
1150 else if ((GET_MODE (XEXP (x
, 0)) == CCFPmode
1151 && GET_CODE (x
) != NE
)
1152 || GET_CODE (x
) == EQ
1153 || GET_CODE (x
) == LT
|| GET_CODE (x
) == GT
1154 || GET_CODE (x
) == LTU
|| GET_CODE (x
) == GTU
)
1161 /* Opposite of 't': write 4 if this jump operation will branch if true,
1163 if (GET_RTX_CLASS (GET_CODE (x
)) != '<')
1164 output_operand_lossage ("invalid %%t value");
1166 else if ((GET_MODE (XEXP (x
, 0)) == CCFPmode
1167 && GET_CODE (x
) != NE
)
1168 || GET_CODE (x
) == EQ
1169 || GET_CODE (x
) == LT
|| GET_CODE (x
) == GT
1170 || GET_CODE (x
) == LTU
|| GET_CODE (x
) == GTU
)
1177 /* High-order 16 bits of constant. */
1179 output_operand_lossage ("invalid %%u value");
1181 fprintf (file
, "0x%x", (INT_LOWPART (x
) >> 16) & 0xffff);
1185 /* Print `u' if this has an auto-increment or auto-decrement. */
1186 if (GET_CODE (x
) == MEM
1187 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
1188 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
))
1193 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
1196 fprintf (file
, "%d",
1197 (INT_LOWPART (x
) & 0xffff) - 2 * (INT_LOWPART (x
) & 0x8000));
1199 print_operand (file
, x
, 0);
1203 /* If constant, low-order 16 bits of constant, unsigned.
1204 Otherwise, write normally. */
1206 fprintf (file
, "%d", INT_LOWPART (x
) & 0xffff);
1208 print_operand (file
, x
, 0);
1212 if (GET_CODE (x
) == MEM
1213 && LEGITIMATE_INDEXED_ADDRESS_P (XEXP (x
, 0)))
1218 /* Like 'L', for third word of TImode */
1219 if (GET_CODE (x
) == REG
)
1220 fprintf (file
, "%d", REGNO (x
) + 2);
1221 else if (GET_CODE (x
) == MEM
)
1223 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1224 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1225 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 8));
1227 output_address (plus_constant (XEXP (x
, 0), 8));
1232 /* X is a SYMBOL_REF. Write out the name preceded by a
1233 period and without any trailing data in brackets. Used for function
1235 if (GET_CODE (x
) != SYMBOL_REF
)
1239 RS6000_OUTPUT_BASENAME (file
, XSTR (x
, 0));
1243 /* Like 'L', for last word of TImode. */
1244 if (GET_CODE (x
) == REG
)
1245 fprintf (file
, "%d", REGNO (x
) + 3);
1246 else if (GET_CODE (x
) == MEM
)
1248 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1249 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1250 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 12));
1252 output_address (plus_constant (XEXP (x
, 0), 12));
1257 if (GET_CODE (x
) == REG
)
1258 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1259 else if (GET_CODE (x
) == MEM
)
1261 /* We need to handle PRE_INC and PRE_DEC here, since we need to
1262 know the width from the mode. */
1263 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
1264 fprintf (file
, "%d(%d)", GET_MODE_SIZE (GET_MODE (x
)),
1265 REGNO (XEXP (XEXP (x
, 0), 0)));
1266 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1267 fprintf (file
, "%d(%d)", - GET_MODE_SIZE (GET_MODE (x
)),
1268 REGNO (XEXP (XEXP (x
, 0), 0)));
1270 output_address (XEXP (x
, 0));
1273 output_addr_const (file
, x
);
1277 output_operand_lossage ("invalid %%xn code");
1281 /* Print the address of an operand. */
1284 print_operand_address (file
, x
)
1288 if (GET_CODE (x
) == REG
)
1289 fprintf (file
, "0(%d)", REGNO (x
));
1290 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
1292 output_addr_const (file
, x
);
1293 /* When TARGET_MINIMAL_TOC, use the indirected toc table pointer instead
1294 of the toc pointer. */
1295 if (TARGET_MINIMAL_TOC
)
1296 fprintf (file
, "(30)");
1298 fprintf (file
, "(2)");
1300 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == REG
)
1302 if (REGNO (XEXP (x
, 0)) == 0)
1303 fprintf (file
, "%d,%d", REGNO (XEXP (x
, 1)), REGNO (XEXP (x
, 0)));
1305 fprintf (file
, "%d,%d", REGNO (XEXP (x
, 0)), REGNO (XEXP (x
, 1)));
1307 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1308 fprintf (file
, "%d(%d)", INTVAL (XEXP (x
, 1)), REGNO (XEXP (x
, 0)));
1313 /* This page contains routines that are used to determine what the function
1314 prologue and epilogue code will do and write them out. */
1316 /* Return the first fixed-point register that is required to be saved. 32 if
1320 first_reg_to_save ()
1324 /* Find lowest numbered live register. */
1325 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
1326 if (regs_ever_live
[first_reg
])
1329 /* If profiling, then we must save/restore every register that contains
1330 a parameter before/after the .mcount call. Use registers from 30 down
1331 to 23 to do this. Don't use the frame pointer in reg 31.
1333 For now, save enough room for all of the parameter registers. */
1341 /* Similar, for FP regs. */
1344 first_fp_reg_to_save ()
1348 /* Find lowest numbered live register. */
1349 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
1350 if (regs_ever_live
[first_reg
])
1356 /* Return 1 if we need to save CR. */
1361 return regs_ever_live
[70] || regs_ever_live
[71] || regs_ever_live
[72];
1364 /* Compute the size of the save area in the stack, including the space for
1372 /* We have the six fixed words, plus the size of the register save
1373 areas, rounded to a double-word. */
1374 size
= 6 + (32 - first_reg_to_save ()) + (64 - first_fp_reg_to_save ()) * 2;
1381 /* Return non-zero if this function makes calls. */
1384 rs6000_makes_calls ()
1388 /* If we are profiling, we will be making a call to mcount. */
1392 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
1393 if (GET_CODE (insn
) == CALL_INSN
)
1399 /* Return non-zero if this function needs to push space on the stack. */
1402 rs6000_pushes_stack ()
1404 int total_size
= (rs6000_sa_size () + get_frame_size ()
1405 + current_function_outgoing_args_size
);
1407 /* We need to push the stack if a frame pointer is needed (because the
1408 stack might be dynamically adjusted), if we are debugging, if the
1409 total stack size is more than 220 bytes, or if we make calls. */
1411 return (frame_pointer_needed
|| write_symbols
!= NO_DEBUG
1413 || rs6000_makes_calls ());
1416 /* Write function prologue. */
1419 output_prolog (file
, size
)
1423 int first_reg
= first_reg_to_save ();
1424 int must_push
= rs6000_pushes_stack ();
1425 int first_fp_reg
= first_fp_reg_to_save ();
1426 int basic_size
= rs6000_sa_size ();
1427 int total_size
= (basic_size
+ size
+ current_function_outgoing_args_size
);
1429 /* Round size to multiple of 8 bytes. */
1430 total_size
= (total_size
+ 7) & ~7;
1432 /* Write .extern for any function we will call to save and restore fp
1434 if (first_fp_reg
< 62)
1435 fprintf (file
, "\t.extern ._savef%d\n\t.extern ._restf%d\n",
1436 first_fp_reg
- 32, first_fp_reg
- 32);
1438 /* Write .extern for truncation routines, if needed. */
1439 if (rs6000_trunc_used
&& ! trunc_defined
)
1441 fprintf (file
, "\t.extern .%s\n\t.extern .%s\n",
1442 RS6000_ITRUNC
, RS6000_UITRUNC
);
1445 /* Write .extern for AIX common mode routines, if needed. */
1446 if (! TARGET_POWER
&& ! TARGET_POWERPC
&& ! common_mode_defined
)
1448 fputs ("\t.extern __mulh\n", file
);
1449 fputs ("\t.extern __mull\n", file
);
1450 fputs ("\t.extern __divss\n", file
);
1451 fputs ("\t.extern __divus\n", file
);
1452 fputs ("\t.extern __quoss\n", file
);
1453 fputs ("\t.extern __quous\n", file
);
1454 common_mode_defined
= 1;
1457 /* If we have to call a function to save fpr's, or if we are doing profiling,
1458 then we will be using LR. */
1459 if (first_fp_reg
< 62 || profile_flag
)
1460 regs_ever_live
[65] = 1;
1462 /* If we use the link register, get it into r0. */
1463 if (regs_ever_live
[65])
1464 asm_fprintf (file
, "\tmflr 0\n");
1466 /* If we need to save CR, put it into r12. */
1467 if (must_save_cr ())
1468 asm_fprintf (file
, "\tmfcr 12\n");
1470 /* Do any required saving of fpr's. If only one or two to save, do it
1471 ourself. Otherwise, call function. Note that since they are statically
1472 linked, we do not need a nop following them. */
1473 if (first_fp_reg
== 62)
1474 asm_fprintf (file
, "\tstfd 30,-16(1)\n\tstfd 31,-8(1)\n");
1475 else if (first_fp_reg
== 63)
1476 asm_fprintf (file
, "\tstfd 31,-8(1)\n");
1477 else if (first_fp_reg
!= 64)
1478 asm_fprintf (file
, "\tbl ._savef%d\n", first_fp_reg
- 32);
1480 /* Now save gpr's. */
1481 if (! TARGET_POWER
|| first_reg
== 31)
1485 for (regno
= first_reg
,
1486 loc
= - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8;
1489 asm_fprintf (file
, "\t{st|stw} %d,%d(1)\n", regno
, loc
);
1492 else if (first_reg
!= 32)
1493 asm_fprintf (file
, "\t{stm|stmw} %d,%d(1)\n", first_reg
,
1494 - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8);
1496 /* Save lr if we used it. */
1497 if (regs_ever_live
[65])
1498 asm_fprintf (file
, "\t{st|stw} 0,8(1)\n");
1500 /* Save CR if we use any that must be preserved. */
1501 if (must_save_cr ())
1502 asm_fprintf (file
, "\t{st|stw} 12,4(1)\n");
1504 /* Update stack and set back pointer. */
1507 if (total_size
< 32767)
1508 asm_fprintf (file
, "\t{stu|stwu} 1,%d(1)\n", - total_size
);
1511 asm_fprintf (file
, "\t{cau 0,0,%d|lis 0,%d}\n\t{oril 0,0,%d|li 0,%d}\n",
1512 (total_size
>> 16) & 0xffff, total_size
& 0xffff);
1514 asm_fprintf (file
, "\tsubf 12,0,1\n");
1516 asm_fprintf (file
, "\t{sf|subfc} 12,0,1\n");
1517 asm_fprintf (file
, "\t{st|stw} 1,0(12)\n\tmr 1,12\n");
1521 /* Set frame pointer, if needed. */
1522 if (frame_pointer_needed
)
1523 asm_fprintf (file
, "\tmr 31,1\n");
1525 /* If TARGET_MINIMAL_TOC, and the constant pool is needed, then load the
1526 TOC_TABLE address into register 30. */
1527 if (TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
1531 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 0);
1532 asm_fprintf (file
, "\t{l|lwz} 30,");
1533 assemble_name (file
, buf
);
1534 asm_fprintf (file
, "(2)\n");
1538 /* Write function epilogue. */
1541 output_epilog (file
, size
)
1545 int first_reg
= first_reg_to_save ();
1546 int must_push
= rs6000_pushes_stack ();
1547 int first_fp_reg
= first_fp_reg_to_save ();
1548 int basic_size
= rs6000_sa_size ();
1549 int total_size
= (basic_size
+ size
+ current_function_outgoing_args_size
);
1550 rtx insn
= get_last_insn ();
1552 /* Round size to multiple of 8 bytes. */
1553 total_size
= (total_size
+ 7) & ~7;
1555 /* If the last insn was a BARRIER, we don't have to write anything except
1557 if (GET_CODE (insn
) == NOTE
)
1558 insn
= prev_nonnote_insn (insn
);
1559 if (insn
== 0 || GET_CODE (insn
) != BARRIER
)
1561 /* If we have a frame pointer, a call to alloca, or a large stack
1562 frame, restore the old stack pointer using the backchain. Otherwise,
1563 we know what size to update it with. */
1564 if (frame_pointer_needed
|| current_function_calls_alloca
1565 || total_size
> 32767)
1566 asm_fprintf (file
, "\t{l|lwz} 1,0(1)\n");
1568 asm_fprintf (file
, "\t{cal 1,%d(1)|addi 1,1,%d}\n", total_size
);
1570 /* Get the old lr if we saved it. */
1571 if (regs_ever_live
[65])
1572 asm_fprintf (file
, "\t{l|lwz} 0,8(1)\n");
1574 /* Get the old cr if we saved it. */
1575 if (must_save_cr ())
1576 asm_fprintf (file
, "\t{l|lwz} 12,4(1)\n");
1578 /* Set LR here to try to overlap restores below. */
1579 if (regs_ever_live
[65])
1580 asm_fprintf (file
, "\tmtlr 0\n");
1582 /* Restore gpr's. */
1583 if (! TARGET_POWER
|| first_reg
== 31)
1587 for (regno
= first_reg
,
1588 loc
= - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8;
1591 asm_fprintf (file
, "\t{l|lwz} %d,%d(1)\n", regno
, loc
);
1594 else if (first_reg
!= 32)
1595 asm_fprintf (file
, "\t{lm|lmw} %d,%d(1)\n", first_reg
,
1596 - (32 - first_reg
) * 4 - (64 - first_fp_reg
) * 8);
1598 /* Restore fpr's if we can do it without calling a function. */
1599 if (first_fp_reg
== 62)
1600 asm_fprintf (file
, "\tlfd 30,-16(1)\n\tlfd 31,-8(1)\n");
1601 else if (first_fp_reg
== 63)
1602 asm_fprintf (file
, "\tlfd 31,-8(1)\n");
1604 /* If we saved cr, restore it here. Just those of cr2, cr3, and cr4
1606 if (must_save_cr ())
1607 asm_fprintf (file
, "\tmtcrf %d,12\n",
1608 (regs_ever_live
[70] != 0) * 0x20
1609 + (regs_ever_live
[71] != 0) * 0x10
1610 + (regs_ever_live
[72] != 0) * 0x8);
1612 /* If we have to restore more than two FP registers, branch to the
1613 restore function. It will return to our caller. */
1614 if (first_fp_reg
< 62)
1615 asm_fprintf (file
, "\tb ._restf%d\n", first_fp_reg
- 32);
1617 asm_fprintf (file
, "\t{br|blr}\n");
1620 /* Output a traceback table here. See /usr/include/sys/debug.h for info
1623 We don't output a traceback table if -finhibit-size-directive was
1624 used. The documentation for -finhibit-size-directive reads
1625 ``don't output a @code{.size} assembler directive, or anything
1626 else that would cause trouble if the function is split in the
1627 middle, and the two halves are placed at locations far apart in
1628 memory.'' The traceback table has this property, since it
1629 includes the offset from the start of the function to the
1630 traceback table itself. */
1631 if (! flag_inhibit_size_directive
)
1633 char *fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
1634 int fixed_parms
, float_parms
, parm_info
;
1637 /* Need label immediately before tbtab, so we can compute its offset
1638 from the function start. */
1641 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
1642 ASM_OUTPUT_LABEL (file
, fname
);
1644 /* The .tbtab pseudo-op can only be used for the first eight
1645 expressions, since it can't handle the possibly variable
1646 length fields that follow. However, if you omit the optional
1647 fields, the assembler outputs zeros for all optional fields
1648 anyways, giving each variable length field is minimum length
1649 (as defined in sys/debug.h). Thus we can not use the .tbtab
1650 pseudo-op at all. */
1652 /* An all-zero word flags the start of the tbtab, for debuggers
1653 that have to find it by searching forward from the entry
1654 point or from the current pc. */
1655 fprintf (file
, "\t.long 0\n");
1657 /* Tbtab format type. Use format type 0. */
1658 fprintf (file
, "\t.byte 0,");
1660 /* Language type. Unfortunately, there doesn't seem to be any
1661 official way to get this info, so we use language_string. C
1662 is 0. C++ is 9. No number defined for Obj-C, so use the
1663 value for C for now. */
1664 if (! strcmp (language_string
, "GNU C")
1665 || ! strcmp (language_string
, "GNU Obj-C"))
1667 else if (! strcmp (language_string
, "GNU F77"))
1669 else if (! strcmp (language_string
, "GNU Ada"))
1671 else if (! strcmp (language_string
, "GNU PASCAL"))
1673 else if (! strcmp (language_string
, "GNU C++"))
1677 fprintf (file
, "%d,", i
);
1679 /* 8 single bit fields: global linkage (not set for C extern linkage,
1680 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
1681 from start of procedure stored in tbtab, internal function, function
1682 has controlled storage, function has no toc, function uses fp,
1683 function logs/aborts fp operations. */
1684 /* Assume that fp operations are used if any fp reg must be saved. */
1685 fprintf (file
, "%d,", (1 << 5) | ((first_fp_reg
!= 64) << 1));
1687 /* 6 bitfields: function is interrupt handler, name present in
1688 proc table, function calls alloca, on condition directives
1689 (controls stack walks, 3 bits), saves condition reg, saves
1691 /* The `function calls alloca' bit seems to be set whenever reg 31 is
1692 set up as a frame pointer, even when there is no alloca call. */
1693 fprintf (file
, "%d,",
1694 ((1 << 6) | (frame_pointer_needed
<< 5)
1695 | (must_save_cr () << 1) | (regs_ever_live
[65])));
1697 /* 3 bitfields: saves backchain, spare bit, number of fpr saved
1699 fprintf (file
, "%d,",
1700 (must_push
<< 7) | (64 - first_fp_reg_to_save ()));
1702 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
1703 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
1706 /* Compute the parameter info from the function decl argument
1709 int next_parm_info_bit
;
1711 next_parm_info_bit
= 31;
1716 for (decl
= DECL_ARGUMENTS (current_function_decl
);
1717 decl
; decl
= TREE_CHAIN (decl
))
1719 rtx parameter
= DECL_INCOMING_RTL (decl
);
1720 enum machine_mode mode
= GET_MODE (parameter
);
1722 if (GET_CODE (parameter
) == REG
)
1724 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1732 else if (mode
== DFmode
)
1737 /* If only one bit will fit, don't or in this entry. */
1738 if (next_parm_info_bit
> 0)
1739 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
1740 next_parm_info_bit
-= 2;
1744 fixed_parms
+= ((GET_MODE_SIZE (mode
)
1745 + (UNITS_PER_WORD
- 1))
1747 next_parm_info_bit
-= 1;
1753 /* Number of fixed point parameters. */
1754 /* This is actually the number of words of fixed point parameters; thus
1755 an 8 byte struct counts as 2; and thus the maximum value is 8. */
1756 fprintf (file
, "%d,", fixed_parms
);
1758 /* 2 bitfields: number of floating point parameters (7 bits), parameters
1760 /* This is actually the number of fp registers that hold parameters;
1761 and thus the maximum value is 13. */
1762 /* Set parameters on stack bit if parameters are not in their original
1763 registers, regardless of whether they are on the stack? Xlc
1764 seems to set the bit when not optimizing. */
1765 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
1767 /* Optional fields follow. Some are variable length. */
1769 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
1771 /* There is an entry for each parameter in a register, in the order that
1772 they occur in the parameter list. Any intervening arguments on the
1773 stack are ignored. If the list overflows a long (max possible length
1774 34 bits) then completely leave off all elements that don't fit. */
1775 /* Only emit this long if there was at least one parameter. */
1776 if (fixed_parms
|| float_parms
)
1777 fprintf (file
, "\t.long %d\n", parm_info
);
1779 /* Offset from start of code to tb table. */
1780 fprintf (file
, "\t.long ");
1781 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
1782 RS6000_OUTPUT_BASENAME (file
, fname
);
1783 fprintf (file
, "-.");
1784 RS6000_OUTPUT_BASENAME (file
, fname
);
1785 fprintf (file
, "\n");
1787 /* Interrupt handler mask. */
1788 /* Omit this long, since we never set the interrupt handler bit
1791 /* Number of CTL (controlled storage) anchors. */
1792 /* Omit this long, since the has_ctl bit is never set above. */
1794 /* Displacement into stack of each CTL anchor. */
1795 /* Omit this list of longs, because there are no CTL anchors. */
1797 /* Length of function name. */
1798 fprintf (file
, "\t.short %d\n", strlen (fname
));
1800 /* Function name. */
1801 assemble_string (fname
, strlen (fname
));
1803 /* Register for alloca automatic storage; this is always reg 31.
1804 Only emit this if the alloca bit was set above. */
1805 if (frame_pointer_needed
)
1806 fprintf (file
, "\t.byte 31\n");
1810 /* Output a TOC entry. We derive the entry name from what is
1814 output_toc (file
, x
, labelno
)
1824 ASM_OUTPUT_INTERNAL_LABEL (file
, "LC", labelno
);
1826 /* Handle FP constants specially. Note that if we have a minimal
1827 TOC, things we put here aren't actually in the TOC, so we can allow
1829 if (GET_CODE (x
) == CONST_DOUBLE
1830 && GET_MODE (x
) == DFmode
1831 && TARGET_FLOAT_FORMAT
== HOST_FLOAT_FORMAT
1832 && BITS_PER_WORD
== HOST_BITS_PER_INT
1833 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
))
1835 if (TARGET_MINIMAL_TOC
)
1836 fprintf (file
, "\t.long %d\n\t.long %d\n",
1837 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
1839 fprintf (file
, "\t.tc FD_%x_%x[TC],%d,%d\n",
1840 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
),
1841 CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
1844 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
1845 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
))
1847 rtx val
= operand_subword (x
, 0, 0, SFmode
);
1849 if (val
== 0 || GET_CODE (val
) != CONST_INT
)
1852 if (TARGET_MINIMAL_TOC
)
1853 fprintf (file
, "\t.long %d\n", INTVAL (val
));
1855 fprintf (file
, "\t.tc FS_%x[TC],%d\n", INTVAL (val
), INTVAL (val
));
1859 if (GET_CODE (x
) == CONST
)
1861 base
= XEXP (XEXP (x
, 0), 0);
1862 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
1865 if (GET_CODE (base
) == SYMBOL_REF
)
1866 name
= XSTR (base
, 0);
1867 else if (GET_CODE (base
) == LABEL_REF
)
1868 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (base
, 0)));
1869 else if (GET_CODE (base
) == CODE_LABEL
)
1870 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
1874 if (TARGET_MINIMAL_TOC
)
1875 fprintf (file
, "\t.long ");
1878 fprintf (file
, "\t.tc ");
1879 RS6000_OUTPUT_BASENAME (file
, name
);
1882 fprintf (file
, ".N%d", - offset
);
1884 fprintf (file
, ".P%d", offset
);
1886 fprintf (file
, "[TC],");
1888 output_addr_const (file
, x
);
1889 fprintf (file
, "\n");
1892 /* Output an assembler pseudo-op to write an ASCII string of N characters
1893 starting at P to FILE.
1895 On the RS/6000, we have to do this using the .byte operation and
1896 write out special characters outside the quoted string.
1897 Also, the assembler is broken; very long strings are truncated,
1898 so we must artificially break them up early. */
1901 output_ascii (file
, p
, n
)
1907 int i
, count_string
;
1908 char *for_string
= "\t.byte \"";
1909 char *for_decimal
= "\t.byte ";
1910 char *to_close
= NULL
;
1913 for (i
= 0; i
< n
; i
++)
1916 if (c
>= ' ' && c
< 0177)
1919 fputs (for_string
, file
);
1922 /* Write two quotes to get one. */
1930 for_decimal
= "\"\n\t.byte ";
1934 if (count_string
>= 512)
1936 fputs (to_close
, file
);
1938 for_string
= "\t.byte \"";
1939 for_decimal
= "\t.byte ";
1947 fputs (for_decimal
, file
);
1948 fprintf (file
, "%d", c
);
1950 for_string
= "\n\t.byte \"";
1957 /* Now close the string if we have written one. Then end the line. */
1959 fprintf (file
, to_close
);
1962 /* Generate a unique section name for FILENAME for a section type
1963 represented by SECTION_DESC. Output goes into BUF.
1965 SECTION_DESC can be any string, as long as it is different for each
1966 possible section type.
1968 We name the section in the same manner as xlc. The name begins with an
1969 underscore followed by the filename (after stripping any leading directory
1970 names) with the last period replaced by the string SECTION_DESC. If
1971 FILENAME does not contain a period, SECTION_DESC is appended to the end of
1975 rs6000_gen_section_name (buf
, filename
, section_desc
)
1980 char *q
, *after_last_slash
, *last_period
;
1984 after_last_slash
= filename
;
1985 for (q
= filename
; *q
; q
++)
1988 after_last_slash
= q
+ 1;
1993 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
1994 *buf
= (char *) permalloc (len
);
1999 for (q
= after_last_slash
; *q
; q
++)
2001 if (q
== last_period
)
2003 strcpy (p
, section_desc
);
2004 p
+= strlen (section_desc
);
2007 else if (isalnum (*q
))
2011 if (last_period
== 0)
2012 strcpy (p
, section_desc
);
2017 /* Write function profiler code. */
2020 output_function_profiler (file
, labelno
)
2024 /* The last used parameter register. */
2029 /* Set up a TOC entry for the profiler label. */
2031 ASM_OUTPUT_INTERNAL_LABEL (file
, "LPC", labelno
);
2032 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
2033 if (TARGET_MINIMAL_TOC
)
2035 fprintf (file
, "\t.long ");
2036 assemble_name (file
, buf
);
2037 fprintf (file
, "\n");
2041 fprintf (file
, "\t.tc\t");
2042 assemble_name (file
, buf
);
2043 fprintf (file
, "[TC],");
2044 assemble_name (file
, buf
);
2045 fprintf (file
, "\n");
2049 /* Figure out last used parameter register. The proper thing to do is
2050 to walk incoming args of the function. A function might have live
2051 parameter registers even if it has no incoming args. */
2053 for (last_parm_reg
= 10;
2054 last_parm_reg
> 2 && ! regs_ever_live
[last_parm_reg
];
2058 /* Save parameter registers in regs 23-30. Don't overwrite reg 31, since
2059 it might be set up as the frame pointer. */
2061 for (i
= 3, j
= 30; i
<= last_parm_reg
; i
++, j
--)
2062 fprintf (file
, "\tai %d,%d,0\n", j
, i
);
2064 /* Load location address into r3, and call mcount. */
2066 ASM_GENERATE_INTERNAL_LABEL (buf
, "LPC", labelno
);
2067 fprintf (file
, "\tl 3,");
2068 assemble_name (file
, buf
);
2069 fprintf (file
, "(2)\n\tbl .mcount\n");
2071 /* Restore parameter registers. */
2073 for (i
= 3, j
= 30; i
<= last_parm_reg
; i
++, j
--)
2074 fprintf (file
, "\tai %d,%d,0\n", i
, j
);
2077 /* Adjust the cost of a scheduling dependency. Return the new cost of
2078 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2081 rs6000_adjust_cost (insn
, link
, dep_insn
, cost
)
2087 if (! recog_memoized (insn
))
2090 if (REG_NOTE_KIND (link
) != 0)
2093 if (REG_NOTE_KIND (link
) == 0)
2095 /* Data dependency; DEP_INSN writes a register that INSN reads some
2098 /* Tell the first scheduling pass about the latency between a mtctr
2099 and bctr (and mtlr and br/blr). The first scheduling pass will not
2100 know about this latency since the mtctr instruction, which has the
2101 latency associated to it, will be generated by reload. */
2102 if (get_attr_type (insn
) == TYPE_JMPREG
)
2103 return TARGET_POWER
? 5 : 4;
2105 /* Fall out to return default cost. */