1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2015 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
37 #include "double-int.h"
44 #include "fold-const.h"
45 #include "stringpool.h"
46 #include "stor-layout.h"
48 #include "print-tree.h"
52 #include "statistics.h"
54 #include "fixed-value.h"
61 #include "insn-codes.h"
67 #include "dominance.h"
73 #include "cfgcleanup.h"
74 #include "basic-block.h"
75 #include "diagnostic-core.h"
80 #include "target-def.h"
81 #include "common/common-target.h"
82 #include "langhooks.h"
85 #include "sched-int.h"
86 #include "hash-table.h"
87 #include "tree-ssa-alias.h"
88 #include "internal-fn.h"
89 #include "gimple-fold.h"
91 #include "gimple-expr.h"
95 #include "gimple-iterator.h"
96 #include "gimple-walk.h"
99 #include "tm-constrs.h"
102 #include "tree-vectorizer.h"
103 #include "dumpfile.h"
104 #include "hash-map.h"
105 #include "plugin-api.h"
108 #include "target-globals.h"
109 #include "builtins.h"
111 #include "tree-pass.h"
113 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
116 #include "gstab.h" /* for N_SLINE */
119 #ifndef TARGET_NO_PROTOTYPE
120 #define TARGET_NO_PROTOTYPE 0
123 #define min(A,B) ((A) < (B) ? (A) : (B))
124 #define max(A,B) ((A) > (B) ? (A) : (B))
126 /* Structure used to define the rs6000 stack */
127 typedef struct rs6000_stack
{
128 int reload_completed
; /* stack info won't change from here on */
129 int first_gp_reg_save
; /* first callee saved GP register used */
130 int first_fp_reg_save
; /* first callee saved FP register used */
131 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
132 int lr_save_p
; /* true if the link reg needs to be saved */
133 int cr_save_p
; /* true if the CR reg needs to be saved */
134 unsigned int vrsave_mask
; /* mask of vec registers to save */
135 int push_p
; /* true if we need to allocate stack space */
136 int calls_p
; /* true if the function makes any calls */
137 int world_save_p
; /* true if we're saving *everything*:
138 r13-r31, cr, f14-f31, vrsave, v20-v31 */
139 enum rs6000_abi abi
; /* which ABI to use */
140 int gp_save_offset
; /* offset to save GP regs from initial SP */
141 int fp_save_offset
; /* offset to save FP regs from initial SP */
142 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
143 int lr_save_offset
; /* offset to save LR from initial SP */
144 int cr_save_offset
; /* offset to save CR from initial SP */
145 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
146 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
147 int varargs_save_offset
; /* offset to save the varargs registers */
148 int ehrd_offset
; /* offset to EH return data */
149 int ehcr_offset
; /* offset to EH CR field data */
150 int reg_size
; /* register size (4 or 8) */
151 HOST_WIDE_INT vars_size
; /* variable save area size */
152 int parm_size
; /* outgoing parameter size */
153 int save_size
; /* save area size */
154 int fixed_size
; /* fixed size of stack frame */
155 int gp_size
; /* size of saved GP registers */
156 int fp_size
; /* size of saved FP registers */
157 int altivec_size
; /* size of saved AltiVec registers */
158 int cr_size
; /* size to hold CR if not in save_size */
159 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
160 int altivec_padding_size
; /* size of altivec alignment padding if
162 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
163 int spe_padding_size
;
164 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
165 int spe_64bit_regs_used
;
169 /* A C structure for machine-specific, per-function data.
170 This is added to the cfun structure. */
171 typedef struct GTY(()) machine_function
173 /* Whether the instruction chain has been scanned already. */
174 int insn_chain_scanned_p
;
175 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
176 int ra_needs_full_frame
;
177 /* Flags if __builtin_return_address (0) was used. */
179 /* Cache lr_save_p after expansion of builtin_eh_return. */
181 /* Whether we need to save the TOC to the reserved stack location in the
182 function prologue. */
183 bool save_toc_in_prologue
;
184 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
185 varargs save area. */
186 HOST_WIDE_INT varargs_save_offset
;
187 /* Temporary stack slot to use for SDmode copies. This slot is
188 64-bits wide and is allocated early enough so that the offset
189 does not overflow the 16-bit load/store offset field. */
190 rtx sdmode_stack_slot
;
191 /* Flag if r2 setup is needed with ELFv2 ABI. */
192 bool r2_setup_needed
;
195 /* Support targetm.vectorize.builtin_mask_for_load. */
196 static GTY(()) tree altivec_builtin_mask_for_load
;
198 /* Set to nonzero once AIX common-mode calls have been defined. */
199 static GTY(()) int common_mode_defined
;
201 /* Label number of label created for -mrelocatable, to call to so we can
202 get the address of the GOT section */
203 static int rs6000_pic_labelno
;
206 /* Counter for labels which are to be placed in .fixup. */
207 int fixuplabelno
= 0;
210 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
213 /* Specify the machine mode that pointers have. After generation of rtl, the
214 compiler makes no further distinction between pointers and any other objects
215 of this machine mode. The type is unsigned since not all things that
216 include rs6000.h also include machmode.h. */
217 unsigned rs6000_pmode
;
219 /* Width in bits of a pointer. */
220 unsigned rs6000_pointer_size
;
222 #ifdef HAVE_AS_GNU_ATTRIBUTE
223 /* Flag whether floating point values have been passed/returned. */
224 static bool rs6000_passes_float
;
225 /* Flag whether vector values have been passed/returned. */
226 static bool rs6000_passes_vector
;
227 /* Flag whether small (<= 8 byte) structures have been returned. */
228 static bool rs6000_returns_struct
;
231 /* Value is TRUE if register/mode pair is acceptable. */
232 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
234 /* Maximum number of registers needed for a given register class and mode. */
235 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
237 /* How many registers are needed for a given register and mode. */
238 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
240 /* Map register number to register class. */
241 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
243 static int dbg_cost_ctrl
;
245 /* Built in types. */
246 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
247 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
249 /* Flag to say the TOC is initialized */
251 char toc_label_name
[10];
253 /* Cached value of rs6000_variable_issue. This is cached in
254 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
255 static short cached_can_issue_more
;
257 static GTY(()) section
*read_only_data_section
;
258 static GTY(()) section
*private_data_section
;
259 static GTY(()) section
*tls_data_section
;
260 static GTY(()) section
*tls_private_data_section
;
261 static GTY(()) section
*read_only_private_data_section
;
262 static GTY(()) section
*sdata2_section
;
263 static GTY(()) section
*toc_section
;
265 struct builtin_description
267 const HOST_WIDE_INT mask
;
268 const enum insn_code icode
;
269 const char *const name
;
270 const enum rs6000_builtins code
;
273 /* Describe the vector unit used for modes. */
274 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
275 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
277 /* Register classes for various constraints that are based on the target
279 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
281 /* Describe the alignment of a vector. */
282 int rs6000_vector_align
[NUM_MACHINE_MODES
];
284 /* Map selected modes to types for builtins. */
285 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
287 /* What modes to automatically generate reciprocal divide estimate (fre) and
288 reciprocal sqrt (frsqrte) for. */
289 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
291 /* Masks to determine which reciprocal esitmate instructions to generate
293 enum rs6000_recip_mask
{
294 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
295 RECIP_DF_DIV
= 0x002,
296 RECIP_V4SF_DIV
= 0x004,
297 RECIP_V2DF_DIV
= 0x008,
299 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
300 RECIP_DF_RSQRT
= 0x020,
301 RECIP_V4SF_RSQRT
= 0x040,
302 RECIP_V2DF_RSQRT
= 0x080,
304 /* Various combination of flags for -mrecip=xxx. */
306 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
307 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
308 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
310 RECIP_HIGH_PRECISION
= RECIP_ALL
,
312 /* On low precision machines like the power5, don't enable double precision
313 reciprocal square root estimate, since it isn't accurate enough. */
314 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
317 /* -mrecip options. */
320 const char *string
; /* option name */
321 unsigned int mask
; /* mask bits to set */
322 } recip_options
[] = {
323 { "all", RECIP_ALL
},
324 { "none", RECIP_NONE
},
325 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
327 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
328 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
329 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
330 | RECIP_V2DF_RSQRT
) },
331 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
332 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
335 /* Pointer to function (in rs6000-c.c) that can define or undefine target
336 macros that have changed. Languages that don't support the preprocessor
337 don't link in rs6000-c.c, so we can't call it directly. */
338 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
340 /* Simplfy register classes into simpler classifications. We assume
341 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
342 check for standard register classes (gpr/floating/altivec/vsx) and
343 floating/vector classes (float/altivec/vsx). */
345 enum rs6000_reg_type
{
358 /* Map register class to register type. */
359 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
361 /* First/last register type for the 'normal' register types (i.e. general
362 purpose, floating point, altivec, and VSX registers). */
363 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
365 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
368 /* Register classes we care about in secondary reload or go if legitimate
369 address. We only need to worry about GPR, FPR, and Altivec registers here,
370 along an ANY field that is the OR of the 3 register classes. */
372 enum rs6000_reload_reg_type
{
373 RELOAD_REG_GPR
, /* General purpose registers. */
374 RELOAD_REG_FPR
, /* Traditional floating point regs. */
375 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
376 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
380 /* For setting up register classes, loop through the 3 register classes mapping
381 into real registers, and skip the ANY class, which is just an OR of the
383 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
384 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
386 /* Map reload register type to a register in the register class. */
387 struct reload_reg_map_type
{
388 const char *name
; /* Register class name. */
389 int reg
; /* Register in the register class. */
392 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
393 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
394 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
395 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
396 { "Any", -1 }, /* RELOAD_REG_ANY. */
399 /* Mask bits for each register class, indexed per mode. Historically the
400 compiler has been more restrictive which types can do PRE_MODIFY instead of
401 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
402 typedef unsigned char addr_mask_type
;
404 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
405 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
406 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
407 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
408 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
409 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
410 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
412 /* Register type masks based on the type, of valid addressing modes. */
413 struct rs6000_reg_addr
{
414 enum insn_code reload_load
; /* INSN to reload for loading. */
415 enum insn_code reload_store
; /* INSN to reload for storing. */
416 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
417 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
418 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
419 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
420 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
423 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
425 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
427 mode_supports_pre_incdec_p (machine_mode mode
)
429 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
433 /* Helper function to say whether a mode supports PRE_MODIFY. */
435 mode_supports_pre_modify_p (machine_mode mode
)
437 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
442 /* Target cpu costs. */
444 struct processor_costs
{
445 const int mulsi
; /* cost of SImode multiplication. */
446 const int mulsi_const
; /* cost of SImode multiplication by constant. */
447 const int mulsi_const9
; /* cost of SImode mult by short constant. */
448 const int muldi
; /* cost of DImode multiplication. */
449 const int divsi
; /* cost of SImode division. */
450 const int divdi
; /* cost of DImode division. */
451 const int fp
; /* cost of simple SFmode and DFmode insns. */
452 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
453 const int sdiv
; /* cost of SFmode division (fdivs). */
454 const int ddiv
; /* cost of DFmode division (fdiv). */
455 const int cache_line_size
; /* cache line size in bytes. */
456 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
457 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
458 const int simultaneous_prefetches
; /* number of parallel prefetch
460 const int sfdf_convert
; /* cost of SF->DF conversion. */
463 const struct processor_costs
*rs6000_cost
;
465 /* Processor costs (relative to an add) */
467 /* Instruction size costs on 32bit processors. */
469 struct processor_costs size32_cost
= {
470 COSTS_N_INSNS (1), /* mulsi */
471 COSTS_N_INSNS (1), /* mulsi_const */
472 COSTS_N_INSNS (1), /* mulsi_const9 */
473 COSTS_N_INSNS (1), /* muldi */
474 COSTS_N_INSNS (1), /* divsi */
475 COSTS_N_INSNS (1), /* divdi */
476 COSTS_N_INSNS (1), /* fp */
477 COSTS_N_INSNS (1), /* dmul */
478 COSTS_N_INSNS (1), /* sdiv */
479 COSTS_N_INSNS (1), /* ddiv */
480 32, /* cache line size */
484 0, /* SF->DF convert */
487 /* Instruction size costs on 64bit processors. */
489 struct processor_costs size64_cost
= {
490 COSTS_N_INSNS (1), /* mulsi */
491 COSTS_N_INSNS (1), /* mulsi_const */
492 COSTS_N_INSNS (1), /* mulsi_const9 */
493 COSTS_N_INSNS (1), /* muldi */
494 COSTS_N_INSNS (1), /* divsi */
495 COSTS_N_INSNS (1), /* divdi */
496 COSTS_N_INSNS (1), /* fp */
497 COSTS_N_INSNS (1), /* dmul */
498 COSTS_N_INSNS (1), /* sdiv */
499 COSTS_N_INSNS (1), /* ddiv */
500 128, /* cache line size */
504 0, /* SF->DF convert */
507 /* Instruction costs on RS64A processors. */
509 struct processor_costs rs64a_cost
= {
510 COSTS_N_INSNS (20), /* mulsi */
511 COSTS_N_INSNS (12), /* mulsi_const */
512 COSTS_N_INSNS (8), /* mulsi_const9 */
513 COSTS_N_INSNS (34), /* muldi */
514 COSTS_N_INSNS (65), /* divsi */
515 COSTS_N_INSNS (67), /* divdi */
516 COSTS_N_INSNS (4), /* fp */
517 COSTS_N_INSNS (4), /* dmul */
518 COSTS_N_INSNS (31), /* sdiv */
519 COSTS_N_INSNS (31), /* ddiv */
520 128, /* cache line size */
524 0, /* SF->DF convert */
527 /* Instruction costs on MPCCORE processors. */
529 struct processor_costs mpccore_cost
= {
530 COSTS_N_INSNS (2), /* mulsi */
531 COSTS_N_INSNS (2), /* mulsi_const */
532 COSTS_N_INSNS (2), /* mulsi_const9 */
533 COSTS_N_INSNS (2), /* muldi */
534 COSTS_N_INSNS (6), /* divsi */
535 COSTS_N_INSNS (6), /* divdi */
536 COSTS_N_INSNS (4), /* fp */
537 COSTS_N_INSNS (5), /* dmul */
538 COSTS_N_INSNS (10), /* sdiv */
539 COSTS_N_INSNS (17), /* ddiv */
540 32, /* cache line size */
544 0, /* SF->DF convert */
547 /* Instruction costs on PPC403 processors. */
549 struct processor_costs ppc403_cost
= {
550 COSTS_N_INSNS (4), /* mulsi */
551 COSTS_N_INSNS (4), /* mulsi_const */
552 COSTS_N_INSNS (4), /* mulsi_const9 */
553 COSTS_N_INSNS (4), /* muldi */
554 COSTS_N_INSNS (33), /* divsi */
555 COSTS_N_INSNS (33), /* divdi */
556 COSTS_N_INSNS (11), /* fp */
557 COSTS_N_INSNS (11), /* dmul */
558 COSTS_N_INSNS (11), /* sdiv */
559 COSTS_N_INSNS (11), /* ddiv */
560 32, /* cache line size */
564 0, /* SF->DF convert */
567 /* Instruction costs on PPC405 processors. */
569 struct processor_costs ppc405_cost
= {
570 COSTS_N_INSNS (5), /* mulsi */
571 COSTS_N_INSNS (4), /* mulsi_const */
572 COSTS_N_INSNS (3), /* mulsi_const9 */
573 COSTS_N_INSNS (5), /* muldi */
574 COSTS_N_INSNS (35), /* divsi */
575 COSTS_N_INSNS (35), /* divdi */
576 COSTS_N_INSNS (11), /* fp */
577 COSTS_N_INSNS (11), /* dmul */
578 COSTS_N_INSNS (11), /* sdiv */
579 COSTS_N_INSNS (11), /* ddiv */
580 32, /* cache line size */
584 0, /* SF->DF convert */
587 /* Instruction costs on PPC440 processors. */
589 struct processor_costs ppc440_cost
= {
590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (3), /* muldi */
594 COSTS_N_INSNS (34), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (5), /* fp */
597 COSTS_N_INSNS (5), /* dmul */
598 COSTS_N_INSNS (19), /* sdiv */
599 COSTS_N_INSNS (33), /* ddiv */
600 32, /* cache line size */
604 0, /* SF->DF convert */
607 /* Instruction costs on PPC476 processors. */
609 struct processor_costs ppc476_cost
= {
610 COSTS_N_INSNS (4), /* mulsi */
611 COSTS_N_INSNS (4), /* mulsi_const */
612 COSTS_N_INSNS (4), /* mulsi_const9 */
613 COSTS_N_INSNS (4), /* muldi */
614 COSTS_N_INSNS (11), /* divsi */
615 COSTS_N_INSNS (11), /* divdi */
616 COSTS_N_INSNS (6), /* fp */
617 COSTS_N_INSNS (6), /* dmul */
618 COSTS_N_INSNS (19), /* sdiv */
619 COSTS_N_INSNS (33), /* ddiv */
620 32, /* l1 cache line size */
624 0, /* SF->DF convert */
627 /* Instruction costs on PPC601 processors. */
629 struct processor_costs ppc601_cost
= {
630 COSTS_N_INSNS (5), /* mulsi */
631 COSTS_N_INSNS (5), /* mulsi_const */
632 COSTS_N_INSNS (5), /* mulsi_const9 */
633 COSTS_N_INSNS (5), /* muldi */
634 COSTS_N_INSNS (36), /* divsi */
635 COSTS_N_INSNS (36), /* divdi */
636 COSTS_N_INSNS (4), /* fp */
637 COSTS_N_INSNS (5), /* dmul */
638 COSTS_N_INSNS (17), /* sdiv */
639 COSTS_N_INSNS (31), /* ddiv */
640 32, /* cache line size */
644 0, /* SF->DF convert */
647 /* Instruction costs on PPC603 processors. */
649 struct processor_costs ppc603_cost
= {
650 COSTS_N_INSNS (5), /* mulsi */
651 COSTS_N_INSNS (3), /* mulsi_const */
652 COSTS_N_INSNS (2), /* mulsi_const9 */
653 COSTS_N_INSNS (5), /* muldi */
654 COSTS_N_INSNS (37), /* divsi */
655 COSTS_N_INSNS (37), /* divdi */
656 COSTS_N_INSNS (3), /* fp */
657 COSTS_N_INSNS (4), /* dmul */
658 COSTS_N_INSNS (18), /* sdiv */
659 COSTS_N_INSNS (33), /* ddiv */
660 32, /* cache line size */
664 0, /* SF->DF convert */
667 /* Instruction costs on PPC604 processors. */
669 struct processor_costs ppc604_cost
= {
670 COSTS_N_INSNS (4), /* mulsi */
671 COSTS_N_INSNS (4), /* mulsi_const */
672 COSTS_N_INSNS (4), /* mulsi_const9 */
673 COSTS_N_INSNS (4), /* muldi */
674 COSTS_N_INSNS (20), /* divsi */
675 COSTS_N_INSNS (20), /* divdi */
676 COSTS_N_INSNS (3), /* fp */
677 COSTS_N_INSNS (3), /* dmul */
678 COSTS_N_INSNS (18), /* sdiv */
679 COSTS_N_INSNS (32), /* ddiv */
680 32, /* cache line size */
684 0, /* SF->DF convert */
687 /* Instruction costs on PPC604e processors. */
689 struct processor_costs ppc604e_cost
= {
690 COSTS_N_INSNS (2), /* mulsi */
691 COSTS_N_INSNS (2), /* mulsi_const */
692 COSTS_N_INSNS (2), /* mulsi_const9 */
693 COSTS_N_INSNS (2), /* muldi */
694 COSTS_N_INSNS (20), /* divsi */
695 COSTS_N_INSNS (20), /* divdi */
696 COSTS_N_INSNS (3), /* fp */
697 COSTS_N_INSNS (3), /* dmul */
698 COSTS_N_INSNS (18), /* sdiv */
699 COSTS_N_INSNS (32), /* ddiv */
700 32, /* cache line size */
704 0, /* SF->DF convert */
707 /* Instruction costs on PPC620 processors. */
709 struct processor_costs ppc620_cost
= {
710 COSTS_N_INSNS (5), /* mulsi */
711 COSTS_N_INSNS (4), /* mulsi_const */
712 COSTS_N_INSNS (3), /* mulsi_const9 */
713 COSTS_N_INSNS (7), /* muldi */
714 COSTS_N_INSNS (21), /* divsi */
715 COSTS_N_INSNS (37), /* divdi */
716 COSTS_N_INSNS (3), /* fp */
717 COSTS_N_INSNS (3), /* dmul */
718 COSTS_N_INSNS (18), /* sdiv */
719 COSTS_N_INSNS (32), /* ddiv */
720 128, /* cache line size */
724 0, /* SF->DF convert */
727 /* Instruction costs on PPC630 processors. */
729 struct processor_costs ppc630_cost
= {
730 COSTS_N_INSNS (5), /* mulsi */
731 COSTS_N_INSNS (4), /* mulsi_const */
732 COSTS_N_INSNS (3), /* mulsi_const9 */
733 COSTS_N_INSNS (7), /* muldi */
734 COSTS_N_INSNS (21), /* divsi */
735 COSTS_N_INSNS (37), /* divdi */
736 COSTS_N_INSNS (3), /* fp */
737 COSTS_N_INSNS (3), /* dmul */
738 COSTS_N_INSNS (17), /* sdiv */
739 COSTS_N_INSNS (21), /* ddiv */
740 128, /* cache line size */
744 0, /* SF->DF convert */
747 /* Instruction costs on Cell processor. */
748 /* COSTS_N_INSNS (1) ~ one add. */
750 struct processor_costs ppccell_cost
= {
751 COSTS_N_INSNS (9/2)+2, /* mulsi */
752 COSTS_N_INSNS (6/2), /* mulsi_const */
753 COSTS_N_INSNS (6/2), /* mulsi_const9 */
754 COSTS_N_INSNS (15/2)+2, /* muldi */
755 COSTS_N_INSNS (38/2), /* divsi */
756 COSTS_N_INSNS (70/2), /* divdi */
757 COSTS_N_INSNS (10/2), /* fp */
758 COSTS_N_INSNS (10/2), /* dmul */
759 COSTS_N_INSNS (74/2), /* sdiv */
760 COSTS_N_INSNS (74/2), /* ddiv */
761 128, /* cache line size */
765 0, /* SF->DF convert */
768 /* Instruction costs on PPC750 and PPC7400 processors. */
770 struct processor_costs ppc750_cost
= {
771 COSTS_N_INSNS (5), /* mulsi */
772 COSTS_N_INSNS (3), /* mulsi_const */
773 COSTS_N_INSNS (2), /* mulsi_const9 */
774 COSTS_N_INSNS (5), /* muldi */
775 COSTS_N_INSNS (17), /* divsi */
776 COSTS_N_INSNS (17), /* divdi */
777 COSTS_N_INSNS (3), /* fp */
778 COSTS_N_INSNS (3), /* dmul */
779 COSTS_N_INSNS (17), /* sdiv */
780 COSTS_N_INSNS (31), /* ddiv */
781 32, /* cache line size */
785 0, /* SF->DF convert */
788 /* Instruction costs on PPC7450 processors. */
790 struct processor_costs ppc7450_cost
= {
791 COSTS_N_INSNS (4), /* mulsi */
792 COSTS_N_INSNS (3), /* mulsi_const */
793 COSTS_N_INSNS (3), /* mulsi_const9 */
794 COSTS_N_INSNS (4), /* muldi */
795 COSTS_N_INSNS (23), /* divsi */
796 COSTS_N_INSNS (23), /* divdi */
797 COSTS_N_INSNS (5), /* fp */
798 COSTS_N_INSNS (5), /* dmul */
799 COSTS_N_INSNS (21), /* sdiv */
800 COSTS_N_INSNS (35), /* ddiv */
801 32, /* cache line size */
805 0, /* SF->DF convert */
808 /* Instruction costs on PPC8540 processors. */
810 struct processor_costs ppc8540_cost
= {
811 COSTS_N_INSNS (4), /* mulsi */
812 COSTS_N_INSNS (4), /* mulsi_const */
813 COSTS_N_INSNS (4), /* mulsi_const9 */
814 COSTS_N_INSNS (4), /* muldi */
815 COSTS_N_INSNS (19), /* divsi */
816 COSTS_N_INSNS (19), /* divdi */
817 COSTS_N_INSNS (4), /* fp */
818 COSTS_N_INSNS (4), /* dmul */
819 COSTS_N_INSNS (29), /* sdiv */
820 COSTS_N_INSNS (29), /* ddiv */
821 32, /* cache line size */
824 1, /* prefetch streams /*/
825 0, /* SF->DF convert */
828 /* Instruction costs on E300C2 and E300C3 cores. */
830 struct processor_costs ppce300c2c3_cost
= {
831 COSTS_N_INSNS (4), /* mulsi */
832 COSTS_N_INSNS (4), /* mulsi_const */
833 COSTS_N_INSNS (4), /* mulsi_const9 */
834 COSTS_N_INSNS (4), /* muldi */
835 COSTS_N_INSNS (19), /* divsi */
836 COSTS_N_INSNS (19), /* divdi */
837 COSTS_N_INSNS (3), /* fp */
838 COSTS_N_INSNS (4), /* dmul */
839 COSTS_N_INSNS (18), /* sdiv */
840 COSTS_N_INSNS (33), /* ddiv */
844 1, /* prefetch streams /*/
845 0, /* SF->DF convert */
848 /* Instruction costs on PPCE500MC processors. */
850 struct processor_costs ppce500mc_cost
= {
851 COSTS_N_INSNS (4), /* mulsi */
852 COSTS_N_INSNS (4), /* mulsi_const */
853 COSTS_N_INSNS (4), /* mulsi_const9 */
854 COSTS_N_INSNS (4), /* muldi */
855 COSTS_N_INSNS (14), /* divsi */
856 COSTS_N_INSNS (14), /* divdi */
857 COSTS_N_INSNS (8), /* fp */
858 COSTS_N_INSNS (10), /* dmul */
859 COSTS_N_INSNS (36), /* sdiv */
860 COSTS_N_INSNS (66), /* ddiv */
861 64, /* cache line size */
864 1, /* prefetch streams /*/
865 0, /* SF->DF convert */
868 /* Instruction costs on PPCE500MC64 processors. */
870 struct processor_costs ppce500mc64_cost
= {
871 COSTS_N_INSNS (4), /* mulsi */
872 COSTS_N_INSNS (4), /* mulsi_const */
873 COSTS_N_INSNS (4), /* mulsi_const9 */
874 COSTS_N_INSNS (4), /* muldi */
875 COSTS_N_INSNS (14), /* divsi */
876 COSTS_N_INSNS (14), /* divdi */
877 COSTS_N_INSNS (4), /* fp */
878 COSTS_N_INSNS (10), /* dmul */
879 COSTS_N_INSNS (36), /* sdiv */
880 COSTS_N_INSNS (66), /* ddiv */
881 64, /* cache line size */
884 1, /* prefetch streams /*/
885 0, /* SF->DF convert */
888 /* Instruction costs on PPCE5500 processors. */
890 struct processor_costs ppce5500_cost
= {
891 COSTS_N_INSNS (5), /* mulsi */
892 COSTS_N_INSNS (5), /* mulsi_const */
893 COSTS_N_INSNS (4), /* mulsi_const9 */
894 COSTS_N_INSNS (5), /* muldi */
895 COSTS_N_INSNS (14), /* divsi */
896 COSTS_N_INSNS (14), /* divdi */
897 COSTS_N_INSNS (7), /* fp */
898 COSTS_N_INSNS (10), /* dmul */
899 COSTS_N_INSNS (36), /* sdiv */
900 COSTS_N_INSNS (66), /* ddiv */
901 64, /* cache line size */
904 1, /* prefetch streams /*/
905 0, /* SF->DF convert */
908 /* Instruction costs on PPCE6500 processors. */
910 struct processor_costs ppce6500_cost
= {
911 COSTS_N_INSNS (5), /* mulsi */
912 COSTS_N_INSNS (5), /* mulsi_const */
913 COSTS_N_INSNS (4), /* mulsi_const9 */
914 COSTS_N_INSNS (5), /* muldi */
915 COSTS_N_INSNS (14), /* divsi */
916 COSTS_N_INSNS (14), /* divdi */
917 COSTS_N_INSNS (7), /* fp */
918 COSTS_N_INSNS (10), /* dmul */
919 COSTS_N_INSNS (36), /* sdiv */
920 COSTS_N_INSNS (66), /* ddiv */
921 64, /* cache line size */
924 1, /* prefetch streams /*/
925 0, /* SF->DF convert */
928 /* Instruction costs on AppliedMicro Titan processors. */
930 struct processor_costs titan_cost
= {
931 COSTS_N_INSNS (5), /* mulsi */
932 COSTS_N_INSNS (5), /* mulsi_const */
933 COSTS_N_INSNS (5), /* mulsi_const9 */
934 COSTS_N_INSNS (5), /* muldi */
935 COSTS_N_INSNS (18), /* divsi */
936 COSTS_N_INSNS (18), /* divdi */
937 COSTS_N_INSNS (10), /* fp */
938 COSTS_N_INSNS (10), /* dmul */
939 COSTS_N_INSNS (46), /* sdiv */
940 COSTS_N_INSNS (72), /* ddiv */
941 32, /* cache line size */
944 1, /* prefetch streams /*/
945 0, /* SF->DF convert */
948 /* Instruction costs on POWER4 and POWER5 processors. */
950 struct processor_costs power4_cost
= {
951 COSTS_N_INSNS (3), /* mulsi */
952 COSTS_N_INSNS (2), /* mulsi_const */
953 COSTS_N_INSNS (2), /* mulsi_const9 */
954 COSTS_N_INSNS (4), /* muldi */
955 COSTS_N_INSNS (18), /* divsi */
956 COSTS_N_INSNS (34), /* divdi */
957 COSTS_N_INSNS (3), /* fp */
958 COSTS_N_INSNS (3), /* dmul */
959 COSTS_N_INSNS (17), /* sdiv */
960 COSTS_N_INSNS (17), /* ddiv */
961 128, /* cache line size */
964 8, /* prefetch streams /*/
965 0, /* SF->DF convert */
968 /* Instruction costs on POWER6 processors. */
970 struct processor_costs power6_cost
= {
971 COSTS_N_INSNS (8), /* mulsi */
972 COSTS_N_INSNS (8), /* mulsi_const */
973 COSTS_N_INSNS (8), /* mulsi_const9 */
974 COSTS_N_INSNS (8), /* muldi */
975 COSTS_N_INSNS (22), /* divsi */
976 COSTS_N_INSNS (28), /* divdi */
977 COSTS_N_INSNS (3), /* fp */
978 COSTS_N_INSNS (3), /* dmul */
979 COSTS_N_INSNS (13), /* sdiv */
980 COSTS_N_INSNS (16), /* ddiv */
981 128, /* cache line size */
984 16, /* prefetch streams */
985 0, /* SF->DF convert */
988 /* Instruction costs on POWER7 processors. */
990 struct processor_costs power7_cost
= {
991 COSTS_N_INSNS (2), /* mulsi */
992 COSTS_N_INSNS (2), /* mulsi_const */
993 COSTS_N_INSNS (2), /* mulsi_const9 */
994 COSTS_N_INSNS (2), /* muldi */
995 COSTS_N_INSNS (18), /* divsi */
996 COSTS_N_INSNS (34), /* divdi */
997 COSTS_N_INSNS (3), /* fp */
998 COSTS_N_INSNS (3), /* dmul */
999 COSTS_N_INSNS (13), /* sdiv */
1000 COSTS_N_INSNS (16), /* ddiv */
1001 128, /* cache line size */
1004 12, /* prefetch streams */
1005 COSTS_N_INSNS (3), /* SF->DF convert */
1008 /* Instruction costs on POWER8 processors. */
1010 struct processor_costs power8_cost
= {
1011 COSTS_N_INSNS (3), /* mulsi */
1012 COSTS_N_INSNS (3), /* mulsi_const */
1013 COSTS_N_INSNS (3), /* mulsi_const9 */
1014 COSTS_N_INSNS (3), /* muldi */
1015 COSTS_N_INSNS (19), /* divsi */
1016 COSTS_N_INSNS (35), /* divdi */
1017 COSTS_N_INSNS (3), /* fp */
1018 COSTS_N_INSNS (3), /* dmul */
1019 COSTS_N_INSNS (14), /* sdiv */
1020 COSTS_N_INSNS (17), /* ddiv */
1021 128, /* cache line size */
1024 12, /* prefetch streams */
1025 COSTS_N_INSNS (3), /* SF->DF convert */
1028 /* Instruction costs on POWER A2 processors. */
1030 struct processor_costs ppca2_cost
= {
1031 COSTS_N_INSNS (16), /* mulsi */
1032 COSTS_N_INSNS (16), /* mulsi_const */
1033 COSTS_N_INSNS (16), /* mulsi_const9 */
1034 COSTS_N_INSNS (16), /* muldi */
1035 COSTS_N_INSNS (22), /* divsi */
1036 COSTS_N_INSNS (28), /* divdi */
1037 COSTS_N_INSNS (3), /* fp */
1038 COSTS_N_INSNS (3), /* dmul */
1039 COSTS_N_INSNS (59), /* sdiv */
1040 COSTS_N_INSNS (72), /* ddiv */
1043 2048, /* l2 cache */
1044 16, /* prefetch streams */
1045 0, /* SF->DF convert */
1049 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1050 #undef RS6000_BUILTIN_1
1051 #undef RS6000_BUILTIN_2
1052 #undef RS6000_BUILTIN_3
1053 #undef RS6000_BUILTIN_A
1054 #undef RS6000_BUILTIN_D
1055 #undef RS6000_BUILTIN_E
1056 #undef RS6000_BUILTIN_H
1057 #undef RS6000_BUILTIN_P
1058 #undef RS6000_BUILTIN_Q
1059 #undef RS6000_BUILTIN_S
1060 #undef RS6000_BUILTIN_X
1062 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1063 { NAME, ICODE, MASK, ATTR },
1065 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1066 { NAME, ICODE, MASK, ATTR },
1068 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1069 { NAME, ICODE, MASK, ATTR },
1071 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1072 { NAME, ICODE, MASK, ATTR },
1074 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1075 { NAME, ICODE, MASK, ATTR },
1077 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1078 { NAME, ICODE, MASK, ATTR },
1080 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1081 { NAME, ICODE, MASK, ATTR },
1083 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1084 { NAME, ICODE, MASK, ATTR },
1086 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1087 { NAME, ICODE, MASK, ATTR },
1089 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1090 { NAME, ICODE, MASK, ATTR },
1092 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1093 { NAME, ICODE, MASK, ATTR },
1095 struct rs6000_builtin_info_type
{
1097 const enum insn_code icode
;
1098 const HOST_WIDE_INT mask
;
1099 const unsigned attr
;
1102 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1104 #include "rs6000-builtin.def"
1107 #undef RS6000_BUILTIN_1
1108 #undef RS6000_BUILTIN_2
1109 #undef RS6000_BUILTIN_3
1110 #undef RS6000_BUILTIN_A
1111 #undef RS6000_BUILTIN_D
1112 #undef RS6000_BUILTIN_E
1113 #undef RS6000_BUILTIN_H
1114 #undef RS6000_BUILTIN_P
1115 #undef RS6000_BUILTIN_Q
1116 #undef RS6000_BUILTIN_S
1117 #undef RS6000_BUILTIN_X
1119 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1120 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1123 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1124 static bool spe_func_has_64bit_regs_p (void);
1125 static struct machine_function
* rs6000_init_machine_status (void);
1126 static int rs6000_ra_ever_killed (void);
1127 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1128 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1129 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1130 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1131 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1132 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1133 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1134 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1136 static int rs6000_debug_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
1137 static bool is_microcoded_insn (rtx_insn
*);
1138 static bool is_nonpipeline_insn (rtx_insn
*);
1139 static bool is_cracked_insn (rtx_insn
*);
1140 static bool is_load_insn (rtx
, rtx
*);
1141 static bool is_store_insn (rtx
, rtx
*);
1142 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1143 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1144 static bool insn_must_be_first_in_group (rtx_insn
*);
1145 static bool insn_must_be_last_in_group (rtx_insn
*);
1146 static void altivec_init_builtins (void);
1147 static tree
builtin_function_type (machine_mode
, machine_mode
,
1148 machine_mode
, machine_mode
,
1149 enum rs6000_builtins
, const char *name
);
1150 static void rs6000_common_init_builtins (void);
1151 static void paired_init_builtins (void);
1152 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1153 static void spe_init_builtins (void);
1154 static void htm_init_builtins (void);
1155 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1156 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1157 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1158 static rs6000_stack_t
*rs6000_stack_info (void);
1159 static void is_altivec_return_reg (rtx
, void *);
1160 int easy_vector_constant (rtx
, machine_mode
);
1161 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1162 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1163 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1166 static void macho_branch_islands (void);
1168 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1170 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1172 static bool rs6000_mode_dependent_address (const_rtx
);
1173 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1174 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1176 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1179 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1180 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1182 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1184 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1187 static bool rs6000_cannot_change_mode_class (machine_mode
,
1190 static bool rs6000_debug_cannot_change_mode_class (machine_mode
,
1193 static bool rs6000_save_toc_in_prologue_p (void);
1195 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1197 = rs6000_legitimize_reload_address
;
1199 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1200 = rs6000_mode_dependent_address
;
1202 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1204 = rs6000_secondary_reload_class
;
1206 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1207 = rs6000_preferred_reload_class
;
1209 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1211 = rs6000_secondary_memory_needed
;
1213 bool (*rs6000_cannot_change_mode_class_ptr
) (machine_mode
,
1216 = rs6000_cannot_change_mode_class
;
1218 const int INSN_NOT_AVAILABLE
= -1;
1220 static void rs6000_print_isa_options (FILE *, int, const char *,
1222 static void rs6000_print_builtin_options (FILE *, int, const char *,
1225 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1226 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1227 enum rs6000_reg_type
,
1229 secondary_reload_info
*,
1231 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1233 /* Hash table stuff for keeping track of TOC entries. */
1235 struct GTY((for_user
)) toc_hash_struct
1237 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1238 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1240 machine_mode key_mode
;
1244 struct toc_hasher
: ggc_hasher
<toc_hash_struct
*>
1246 static hashval_t
hash (toc_hash_struct
*);
1247 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1250 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1252 /* Hash table to keep track of the argument types for builtin functions. */
1254 struct GTY((for_user
)) builtin_hash_struct
1257 machine_mode mode
[4]; /* return value + 3 arguments. */
1258 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1261 struct builtin_hasher
: ggc_hasher
<builtin_hash_struct
*>
1263 static hashval_t
hash (builtin_hash_struct
*);
1264 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1267 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1270 /* Default register names. */
1271 char rs6000_reg_names
[][8] =
1273 "0", "1", "2", "3", "4", "5", "6", "7",
1274 "8", "9", "10", "11", "12", "13", "14", "15",
1275 "16", "17", "18", "19", "20", "21", "22", "23",
1276 "24", "25", "26", "27", "28", "29", "30", "31",
1277 "0", "1", "2", "3", "4", "5", "6", "7",
1278 "8", "9", "10", "11", "12", "13", "14", "15",
1279 "16", "17", "18", "19", "20", "21", "22", "23",
1280 "24", "25", "26", "27", "28", "29", "30", "31",
1281 "mq", "lr", "ctr","ap",
1282 "0", "1", "2", "3", "4", "5", "6", "7",
1284 /* AltiVec registers. */
1285 "0", "1", "2", "3", "4", "5", "6", "7",
1286 "8", "9", "10", "11", "12", "13", "14", "15",
1287 "16", "17", "18", "19", "20", "21", "22", "23",
1288 "24", "25", "26", "27", "28", "29", "30", "31",
1290 /* SPE registers. */
1291 "spe_acc", "spefscr",
1292 /* Soft frame pointer. */
1294 /* HTM SPR registers. */
1295 "tfhar", "tfiar", "texasr",
1296 /* SPE High registers. */
1297 "0", "1", "2", "3", "4", "5", "6", "7",
1298 "8", "9", "10", "11", "12", "13", "14", "15",
1299 "16", "17", "18", "19", "20", "21", "22", "23",
1300 "24", "25", "26", "27", "28", "29", "30", "31"
1303 #ifdef TARGET_REGNAMES
1304 static const char alt_reg_names
[][8] =
1306 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1307 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1308 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1309 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1310 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1311 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1312 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1313 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1314 "mq", "lr", "ctr", "ap",
1315 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1317 /* AltiVec registers. */
1318 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1319 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1320 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1321 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1323 /* SPE registers. */
1324 "spe_acc", "spefscr",
1325 /* Soft frame pointer. */
1327 /* HTM SPR registers. */
1328 "tfhar", "tfiar", "texasr",
1329 /* SPE High registers. */
1330 "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
1331 "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
1332 "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
1333 "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
1337 /* Table of valid machine attributes. */
1339 static const struct attribute_spec rs6000_attribute_table
[] =
1341 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1342 affects_type_identity } */
1343 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1345 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1347 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1349 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1351 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1353 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1354 SUBTARGET_ATTRIBUTE_TABLE
,
1356 { NULL
, 0, 0, false, false, false, NULL
, false }
1359 #ifndef TARGET_PROFILE_KERNEL
1360 #define TARGET_PROFILE_KERNEL 0
1363 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1364 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1366 /* Initialize the GCC target structure. */
1367 #undef TARGET_ATTRIBUTE_TABLE
1368 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1369 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1370 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1371 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1372 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1374 #undef TARGET_ASM_ALIGNED_DI_OP
1375 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1377 /* Default unaligned ops are only provided for ELF. Find the ops needed
1378 for non-ELF systems. */
1379 #ifndef OBJECT_FORMAT_ELF
1381 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1383 #undef TARGET_ASM_UNALIGNED_HI_OP
1384 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1385 #undef TARGET_ASM_UNALIGNED_SI_OP
1386 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1387 #undef TARGET_ASM_UNALIGNED_DI_OP
1388 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1391 #undef TARGET_ASM_UNALIGNED_HI_OP
1392 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1393 #undef TARGET_ASM_UNALIGNED_SI_OP
1394 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1395 #undef TARGET_ASM_UNALIGNED_DI_OP
1396 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1397 #undef TARGET_ASM_ALIGNED_DI_OP
1398 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1402 /* This hook deals with fixups for relocatable code and DI-mode objects
1404 #undef TARGET_ASM_INTEGER
1405 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1407 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1408 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1409 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1412 #undef TARGET_SET_UP_BY_PROLOGUE
1413 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1415 #undef TARGET_HAVE_TLS
1416 #define TARGET_HAVE_TLS HAVE_AS_TLS
1418 #undef TARGET_CANNOT_FORCE_CONST_MEM
1419 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1421 #undef TARGET_DELEGITIMIZE_ADDRESS
1422 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1424 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1425 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1427 #undef TARGET_ASM_FUNCTION_PROLOGUE
1428 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1429 #undef TARGET_ASM_FUNCTION_EPILOGUE
1430 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1432 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1433 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1435 #undef TARGET_LEGITIMIZE_ADDRESS
1436 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1438 #undef TARGET_SCHED_VARIABLE_ISSUE
1439 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1441 #undef TARGET_SCHED_ISSUE_RATE
1442 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1443 #undef TARGET_SCHED_ADJUST_COST
1444 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1445 #undef TARGET_SCHED_ADJUST_PRIORITY
1446 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1447 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1448 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1449 #undef TARGET_SCHED_INIT
1450 #define TARGET_SCHED_INIT rs6000_sched_init
1451 #undef TARGET_SCHED_FINISH
1452 #define TARGET_SCHED_FINISH rs6000_sched_finish
1453 #undef TARGET_SCHED_REORDER
1454 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1455 #undef TARGET_SCHED_REORDER2
1456 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1458 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1459 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1461 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1462 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1464 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1465 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1466 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1467 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1468 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1469 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1470 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1471 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1473 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1474 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1475 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1476 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1477 rs6000_builtin_support_vector_misalignment
1478 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1479 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1480 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1481 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1482 rs6000_builtin_vectorization_cost
1483 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1484 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1485 rs6000_preferred_simd_mode
1486 #undef TARGET_VECTORIZE_INIT_COST
1487 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1488 #undef TARGET_VECTORIZE_ADD_STMT_COST
1489 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1490 #undef TARGET_VECTORIZE_FINISH_COST
1491 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1492 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1493 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1495 #undef TARGET_INIT_BUILTINS
1496 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1497 #undef TARGET_BUILTIN_DECL
1498 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1500 #undef TARGET_EXPAND_BUILTIN
1501 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1503 #undef TARGET_MANGLE_TYPE
1504 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1506 #undef TARGET_INIT_LIBFUNCS
1507 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1510 #undef TARGET_BINDS_LOCAL_P
1511 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1514 #undef TARGET_MS_BITFIELD_LAYOUT_P
1515 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1517 #undef TARGET_ASM_OUTPUT_MI_THUNK
1518 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1520 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1521 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1523 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1524 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1526 #undef TARGET_REGISTER_MOVE_COST
1527 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1528 #undef TARGET_MEMORY_MOVE_COST
1529 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1530 #undef TARGET_RTX_COSTS
1531 #define TARGET_RTX_COSTS rs6000_rtx_costs
1532 #undef TARGET_ADDRESS_COST
1533 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1535 #undef TARGET_DWARF_REGISTER_SPAN
1536 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1538 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1539 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1541 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1542 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1544 #undef TARGET_PROMOTE_FUNCTION_MODE
1545 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1547 #undef TARGET_RETURN_IN_MEMORY
1548 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1550 #undef TARGET_RETURN_IN_MSB
1551 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1553 #undef TARGET_SETUP_INCOMING_VARARGS
1554 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1556 /* Always strict argument naming on rs6000. */
1557 #undef TARGET_STRICT_ARGUMENT_NAMING
1558 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1559 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1560 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1561 #undef TARGET_SPLIT_COMPLEX_ARG
1562 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1563 #undef TARGET_MUST_PASS_IN_STACK
1564 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1565 #undef TARGET_PASS_BY_REFERENCE
1566 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1567 #undef TARGET_ARG_PARTIAL_BYTES
1568 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1569 #undef TARGET_FUNCTION_ARG_ADVANCE
1570 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1571 #undef TARGET_FUNCTION_ARG
1572 #define TARGET_FUNCTION_ARG rs6000_function_arg
1573 #undef TARGET_FUNCTION_ARG_BOUNDARY
1574 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1576 #undef TARGET_BUILD_BUILTIN_VA_LIST
1577 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1579 #undef TARGET_EXPAND_BUILTIN_VA_START
1580 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1582 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1583 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1585 #undef TARGET_EH_RETURN_FILTER_MODE
1586 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1588 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1589 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1591 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1592 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1594 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1595 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1597 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1598 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1600 #undef TARGET_MD_ASM_ADJUST
1601 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1603 #undef TARGET_OPTION_OVERRIDE
1604 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1606 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1607 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1608 rs6000_builtin_vectorized_function
1611 #undef TARGET_STACK_PROTECT_FAIL
1612 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1615 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1616 The PowerPC architecture requires only weak consistency among
1617 processors--that is, memory accesses between processors need not be
1618 sequentially consistent and memory accesses among processors can occur
1619 in any order. The ability to order memory accesses weakly provides
1620 opportunities for more efficient use of the system bus. Unless a
1621 dependency exists, the 604e allows read operations to precede store
1623 #undef TARGET_RELAXED_ORDERING
1624 #define TARGET_RELAXED_ORDERING true
1627 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1628 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1631 /* Use a 32-bit anchor range. This leads to sequences like:
1633 addis tmp,anchor,high
1636 where tmp itself acts as an anchor, and can be shared between
1637 accesses to the same 64k page. */
1638 #undef TARGET_MIN_ANCHOR_OFFSET
1639 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1640 #undef TARGET_MAX_ANCHOR_OFFSET
1641 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1642 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1643 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1644 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1645 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1647 #undef TARGET_BUILTIN_RECIPROCAL
1648 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1650 #undef TARGET_EXPAND_TO_RTL_HOOK
1651 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1653 #undef TARGET_INSTANTIATE_DECLS
1654 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1656 #undef TARGET_SECONDARY_RELOAD
1657 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1659 #undef TARGET_LEGITIMATE_ADDRESS_P
1660 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1662 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1663 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1666 #define TARGET_LRA_P rs6000_lra_p
1668 #undef TARGET_CAN_ELIMINATE
1669 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1671 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1672 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1674 #undef TARGET_TRAMPOLINE_INIT
1675 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1677 #undef TARGET_FUNCTION_VALUE
1678 #define TARGET_FUNCTION_VALUE rs6000_function_value
1680 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1681 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1683 #undef TARGET_OPTION_SAVE
1684 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1686 #undef TARGET_OPTION_RESTORE
1687 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1689 #undef TARGET_OPTION_PRINT
1690 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1692 #undef TARGET_CAN_INLINE_P
1693 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1695 #undef TARGET_SET_CURRENT_FUNCTION
1696 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1698 #undef TARGET_LEGITIMATE_CONSTANT_P
1699 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1701 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1702 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1704 #undef TARGET_CAN_USE_DOLOOP_P
1705 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1707 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1708 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1710 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1711 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1712 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1713 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1714 #undef TARGET_UNWIND_WORD_MODE
1715 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1718 /* Processor table. */
1721 const char *const name
; /* Canonical processor name. */
1722 const enum processor_type processor
; /* Processor type enum value. */
1723 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1726 static struct rs6000_ptt
const processor_target_table
[] =
1728 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1729 #include "rs6000-cpus.def"
1733 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1737 rs6000_cpu_name_lookup (const char *name
)
1743 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1744 if (! strcmp (name
, processor_target_table
[i
].name
))
1752 /* Return number of consecutive hard regs needed starting at reg REGNO
1753 to hold something of mode MODE.
1754 This is ordinarily the length in words of a value of mode MODE
1755 but can be less for certain modes in special long registers.
1757 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1758 scalar instructions. The upper 32 bits are only available to the
1761 POWER and PowerPC GPRs hold 32 bits worth;
1762 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1765 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
1767 unsigned HOST_WIDE_INT reg_size
;
1769 /* TF/TD modes are special in that they always take 2 registers. */
1770 if (FP_REGNO_P (regno
))
1771 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1772 ? UNITS_PER_VSX_WORD
1773 : UNITS_PER_FP_WORD
);
1775 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1776 reg_size
= UNITS_PER_SPE_WORD
;
1778 else if (ALTIVEC_REGNO_P (regno
))
1779 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1781 /* The value returned for SCmode in the E500 double case is 2 for
1782 ABI compatibility; storing an SCmode value in a single register
1783 would require function_arg and rs6000_spe_function_arg to handle
1784 SCmode so as to pass the value correctly in a pair of
1786 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1787 && !DECIMAL_FLOAT_MODE_P (mode
) && SPE_SIMD_REGNO_P (regno
))
1788 reg_size
= UNITS_PER_FP_WORD
;
1791 reg_size
= UNITS_PER_WORD
;
1793 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1796 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1799 rs6000_hard_regno_mode_ok (int regno
, machine_mode mode
)
1801 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1803 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1804 register combinations, and use PTImode where we need to deal with quad
1805 word memory operations. Don't allow quad words in the argument or frame
1806 pointer registers, just registers 0..31. */
1807 if (mode
== PTImode
)
1808 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1809 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1810 && ((regno
& 1) == 0));
1812 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1813 implementations. Don't allow an item to be split between a FP register
1814 and an Altivec register. Allow TImode in all VSX registers if the user
1816 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1817 && (VECTOR_MEM_VSX_P (mode
)
1818 || reg_addr
[mode
].scalar_in_vmx_p
1819 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1820 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1822 if (FP_REGNO_P (regno
))
1823 return FP_REGNO_P (last_regno
);
1825 if (ALTIVEC_REGNO_P (regno
))
1827 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
1830 return ALTIVEC_REGNO_P (last_regno
);
1834 /* The GPRs can hold any mode, but values bigger than one register
1835 cannot go past R31. */
1836 if (INT_REGNO_P (regno
))
1837 return INT_REGNO_P (last_regno
);
1839 /* The float registers (except for VSX vector modes) can only hold floating
1840 modes and DImode. */
1841 if (FP_REGNO_P (regno
))
1843 if (SCALAR_FLOAT_MODE_P (mode
)
1844 && (mode
!= TDmode
|| (regno
% 2) == 0)
1845 && FP_REGNO_P (last_regno
))
1848 if (GET_MODE_CLASS (mode
) == MODE_INT
1849 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1852 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1853 && PAIRED_VECTOR_MODE (mode
))
1859 /* The CR register can only hold CC modes. */
1860 if (CR_REGNO_P (regno
))
1861 return GET_MODE_CLASS (mode
) == MODE_CC
;
1863 if (CA_REGNO_P (regno
))
1864 return mode
== Pmode
|| mode
== SImode
;
1866 /* AltiVec only in AldyVec registers. */
1867 if (ALTIVEC_REGNO_P (regno
))
1868 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
1869 || mode
== V1TImode
);
1871 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1872 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1875 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1876 and it must be able to fit within the register set. */
1878 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1881 /* Print interesting facts about registers. */
1883 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1887 for (r
= first_regno
; r
<= last_regno
; ++r
)
1889 const char *comma
= "";
1892 if (first_regno
== last_regno
)
1893 fprintf (stderr
, "%s:\t", reg_name
);
1895 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1898 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1899 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1903 fprintf (stderr
, ",\n\t");
1908 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1909 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1910 rs6000_hard_regno_nregs
[m
][r
]);
1912 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1917 if (call_used_regs
[r
])
1921 fprintf (stderr
, ",\n\t");
1926 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1934 fprintf (stderr
, ",\n\t");
1939 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1945 fprintf (stderr
, ",\n\t");
1949 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1950 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1955 fprintf (stderr
, ",\n\t");
1959 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1964 rs6000_debug_vector_unit (enum rs6000_vector v
)
1970 case VECTOR_NONE
: ret
= "none"; break;
1971 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1972 case VECTOR_VSX
: ret
= "vsx"; break;
1973 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1974 case VECTOR_PAIRED
: ret
= "paired"; break;
1975 case VECTOR_SPE
: ret
= "spe"; break;
1976 case VECTOR_OTHER
: ret
= "other"; break;
1977 default: ret
= "unknown"; break;
1983 /* Inner function printing just the address mask for a particular reload
1985 DEBUG_FUNCTION
char *
1986 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
1991 if ((mask
& RELOAD_REG_VALID
) != 0)
1993 else if (keep_spaces
)
1996 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
1998 else if (keep_spaces
)
2001 if ((mask
& RELOAD_REG_INDEXED
) != 0)
2003 else if (keep_spaces
)
2006 if ((mask
& RELOAD_REG_OFFSET
) != 0)
2008 else if (keep_spaces
)
2011 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2013 else if (keep_spaces
)
2016 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2018 else if (keep_spaces
)
2021 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2023 else if (keep_spaces
)
2031 /* Print the address masks in a human readble fashion. */
2033 rs6000_debug_print_mode (ssize_t m
)
2037 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2038 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2039 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2040 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2042 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2043 || rs6000_vector_mem
[m
] != VECTOR_NONE
2044 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2045 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
)
2046 || reg_addr
[m
].scalar_in_vmx_p
)
2049 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c",
2050 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2051 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
2052 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2053 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*',
2054 (reg_addr
[m
].scalar_in_vmx_p
) ? 'y' : 'n');
2057 fputs ("\n", stderr
);
2060 #define DEBUG_FMT_ID "%-32s= "
2061 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2062 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2063 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2065 /* Print various interesting information with -mdebug=reg. */
2067 rs6000_debug_reg_global (void)
2069 static const char *const tf
[2] = { "false", "true" };
2070 const char *nl
= (const char *)0;
2073 char costly_num
[20];
2075 char flags_buffer
[40];
2076 const char *costly_str
;
2077 const char *nop_str
;
2078 const char *trace_str
;
2079 const char *abi_str
;
2080 const char *cmodel_str
;
2081 struct cl_target_option cl_opts
;
2083 /* Modes we want tieable information on. */
2084 static const machine_mode print_tieable_modes
[] = {
2120 /* Virtual regs we are interested in. */
2121 const static struct {
2122 int regno
; /* register number. */
2123 const char *name
; /* register name. */
2124 } virtual_regs
[] = {
2125 { STACK_POINTER_REGNUM
, "stack pointer:" },
2126 { TOC_REGNUM
, "toc: " },
2127 { STATIC_CHAIN_REGNUM
, "static chain: " },
2128 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2129 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2130 { ARG_POINTER_REGNUM
, "arg pointer: " },
2131 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2132 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2133 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2134 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2135 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2136 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2137 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2138 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2139 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2140 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2143 fputs ("\nHard register information:\n", stderr
);
2144 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2145 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2146 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2149 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2150 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2151 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2152 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2153 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2154 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2155 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2156 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2158 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2159 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2160 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2164 "d reg_class = %s\n"
2165 "f reg_class = %s\n"
2166 "v reg_class = %s\n"
2167 "wa reg_class = %s\n"
2168 "wd reg_class = %s\n"
2169 "wf reg_class = %s\n"
2170 "wg reg_class = %s\n"
2171 "wh reg_class = %s\n"
2172 "wi reg_class = %s\n"
2173 "wj reg_class = %s\n"
2174 "wk reg_class = %s\n"
2175 "wl reg_class = %s\n"
2176 "wm reg_class = %s\n"
2177 "wr reg_class = %s\n"
2178 "ws reg_class = %s\n"
2179 "wt reg_class = %s\n"
2180 "wu reg_class = %s\n"
2181 "wv reg_class = %s\n"
2182 "ww reg_class = %s\n"
2183 "wx reg_class = %s\n"
2184 "wy reg_class = %s\n"
2185 "wz reg_class = %s\n"
2187 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2188 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2189 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2190 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2191 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2192 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2193 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2194 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2195 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2196 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2197 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2198 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2199 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2200 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2201 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2202 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2203 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2204 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2205 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2206 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2207 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2208 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2211 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2212 rs6000_debug_print_mode (m
);
2214 fputs ("\n", stderr
);
2216 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2218 machine_mode mode1
= print_tieable_modes
[m1
];
2219 bool first_time
= true;
2221 nl
= (const char *)0;
2222 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2224 machine_mode mode2
= print_tieable_modes
[m2
];
2225 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2229 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2234 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2239 fputs ("\n", stderr
);
2245 if (rs6000_recip_control
)
2247 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2249 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2250 if (rs6000_recip_bits
[m
])
2253 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2255 (RS6000_RECIP_AUTO_RE_P (m
)
2257 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2258 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2260 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2263 fputs ("\n", stderr
);
2266 if (rs6000_cpu_index
>= 0)
2268 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2270 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2272 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2273 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2276 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2278 if (rs6000_tune_index
>= 0)
2280 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2282 = processor_target_table
[rs6000_tune_index
].target_enable
;
2284 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2285 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2288 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2290 cl_target_option_save (&cl_opts
, &global_options
);
2291 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2294 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2295 rs6000_isa_flags_explicit
);
2297 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2298 rs6000_builtin_mask
);
2300 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2302 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2303 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2305 switch (rs6000_sched_costly_dep
)
2307 case max_dep_latency
:
2308 costly_str
= "max_dep_latency";
2312 costly_str
= "no_dep_costly";
2315 case all_deps_costly
:
2316 costly_str
= "all_deps_costly";
2319 case true_store_to_load_dep_costly
:
2320 costly_str
= "true_store_to_load_dep_costly";
2323 case store_to_load_dep_costly
:
2324 costly_str
= "store_to_load_dep_costly";
2328 costly_str
= costly_num
;
2329 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2333 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2335 switch (rs6000_sched_insert_nops
)
2337 case sched_finish_regroup_exact
:
2338 nop_str
= "sched_finish_regroup_exact";
2341 case sched_finish_pad_groups
:
2342 nop_str
= "sched_finish_pad_groups";
2345 case sched_finish_none
:
2346 nop_str
= "sched_finish_none";
2351 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2355 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2357 switch (rs6000_sdata
)
2364 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2368 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2372 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2377 switch (rs6000_traceback
)
2379 case traceback_default
: trace_str
= "default"; break;
2380 case traceback_none
: trace_str
= "none"; break;
2381 case traceback_part
: trace_str
= "part"; break;
2382 case traceback_full
: trace_str
= "full"; break;
2383 default: trace_str
= "unknown"; break;
2386 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2388 switch (rs6000_current_cmodel
)
2390 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2391 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2392 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2393 default: cmodel_str
= "unknown"; break;
2396 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2398 switch (rs6000_current_abi
)
2400 case ABI_NONE
: abi_str
= "none"; break;
2401 case ABI_AIX
: abi_str
= "aix"; break;
2402 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2403 case ABI_V4
: abi_str
= "V4"; break;
2404 case ABI_DARWIN
: abi_str
= "darwin"; break;
2405 default: abi_str
= "unknown"; break;
2408 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2410 if (rs6000_altivec_abi
)
2411 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2414 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2416 if (rs6000_darwin64_abi
)
2417 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2419 if (rs6000_float_gprs
)
2420 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2422 fprintf (stderr
, DEBUG_FMT_S
, "fprs",
2423 (TARGET_FPRS
? "true" : "false"));
2425 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2426 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2428 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2429 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2431 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2432 (TARGET_SOFT_FLOAT
? "true" : "false"));
2434 fprintf (stderr
, DEBUG_FMT_S
, "e500_single",
2435 (TARGET_E500_SINGLE
? "true" : "false"));
2437 fprintf (stderr
, DEBUG_FMT_S
, "e500_double",
2438 (TARGET_E500_DOUBLE
? "true" : "false"));
2440 if (TARGET_LINK_STACK
)
2441 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2443 if (targetm
.lra_p ())
2444 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2446 if (TARGET_P8_FUSION
)
2447 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2448 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2450 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2451 TARGET_SECURE_PLT
? "secure" : "bss");
2452 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2453 aix_struct_return
? "aix" : "sysv");
2454 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2455 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2456 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2457 tf
[!!rs6000_align_branch_targets
]);
2458 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2459 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2460 rs6000_long_double_type_size
);
2461 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2462 (int)rs6000_sched_restricted_insns_priority
);
2463 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2465 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2466 (int)RS6000_BUILTIN_COUNT
);
2469 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2470 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2474 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2475 legitimate address support to figure out the appropriate addressing to
2479 rs6000_setup_reg_addr_masks (void)
2481 ssize_t rc
, reg
, m
, nregs
;
2482 addr_mask_type any_addr_mask
, addr_mask
;
2484 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2486 machine_mode m2
= (machine_mode
)m
;
2488 /* SDmode is special in that we want to access it only via REG+REG
2489 addressing on power7 and above, since we want to use the LFIWZX and
2490 STFIWZX instructions to load it. */
2491 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2494 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2497 reg
= reload_reg_map
[rc
].reg
;
2499 /* Can mode values go in the GPR/FPR/Altivec registers? */
2500 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2502 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2503 addr_mask
|= RELOAD_REG_VALID
;
2505 /* Indicate if the mode takes more than 1 physical register. If
2506 it takes a single register, indicate it can do REG+REG
2508 if (nregs
> 1 || m
== BLKmode
)
2509 addr_mask
|= RELOAD_REG_MULTIPLE
;
2511 addr_mask
|= RELOAD_REG_INDEXED
;
2513 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2514 addressing. Restrict addressing on SPE for 64-bit types
2515 because of the SUBREG hackery used to address 64-bit floats in
2519 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2520 && GET_MODE_SIZE (m2
) <= 8
2521 && !VECTOR_MODE_P (m2
)
2522 && !COMPLEX_MODE_P (m2
)
2524 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m2
) == 8))
2526 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2528 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2529 we don't allow PRE_MODIFY for some multi-register
2534 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2538 if (TARGET_POWERPC64
)
2539 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2545 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2551 /* GPR and FPR registers can do REG+OFFSET addressing, except
2552 possibly for SDmode. */
2553 if ((addr_mask
!= 0) && !indexed_only_p
2554 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2555 addr_mask
|= RELOAD_REG_OFFSET
;
2557 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2558 addressing on 128-bit types. */
2559 if (rc
== RELOAD_REG_VMX
&& GET_MODE_SIZE (m2
) == 16
2560 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2561 addr_mask
|= RELOAD_REG_AND_M16
;
2563 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2564 any_addr_mask
|= addr_mask
;
2567 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2572 /* Initialize the various global tables that are based on register size. */
2574 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2580 /* Precalculate REGNO_REG_CLASS. */
2581 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2582 for (r
= 1; r
< 32; ++r
)
2583 rs6000_regno_regclass
[r
] = BASE_REGS
;
2585 for (r
= 32; r
< 64; ++r
)
2586 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2588 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2589 rs6000_regno_regclass
[r
] = NO_REGS
;
2591 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2592 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2594 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2595 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2596 rs6000_regno_regclass
[r
] = CR_REGS
;
2598 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2599 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2600 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
2601 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2602 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2603 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2604 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2605 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2606 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2607 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2608 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2609 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2611 /* Precalculate register class to simpler reload register class. We don't
2612 need all of the register classes that are combinations of different
2613 classes, just the simple ones that have constraint letters. */
2614 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2615 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2617 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2618 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2619 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2620 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2621 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2622 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2623 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2624 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2625 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2626 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2627 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2628 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2632 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2633 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2637 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2638 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2641 /* Precalculate the valid memory formats as well as the vector information,
2642 this must be set up before the rs6000_hard_regno_nregs_internal calls
2644 gcc_assert ((int)VECTOR_NONE
== 0);
2645 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2646 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2648 gcc_assert ((int)CODE_FOR_nothing
== 0);
2649 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2651 gcc_assert ((int)NO_REGS
== 0);
2652 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2654 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2655 believes it can use native alignment or still uses 128-bit alignment. */
2656 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2667 /* V2DF mode, VSX only. */
2670 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2671 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2672 rs6000_vector_align
[V2DFmode
] = align64
;
2675 /* V4SF mode, either VSX or Altivec. */
2678 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2679 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2680 rs6000_vector_align
[V4SFmode
] = align32
;
2682 else if (TARGET_ALTIVEC
)
2684 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2685 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2686 rs6000_vector_align
[V4SFmode
] = align32
;
2689 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2693 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2694 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2695 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2696 rs6000_vector_align
[V4SImode
] = align32
;
2697 rs6000_vector_align
[V8HImode
] = align32
;
2698 rs6000_vector_align
[V16QImode
] = align32
;
2702 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2703 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2704 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2708 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2709 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2710 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2714 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2715 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2718 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2719 rs6000_vector_unit
[V2DImode
]
2720 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2721 rs6000_vector_align
[V2DImode
] = align64
;
2723 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
2724 rs6000_vector_unit
[V1TImode
]
2725 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2726 rs6000_vector_align
[V1TImode
] = 128;
2729 /* DFmode, see if we want to use the VSX unit. Memory is handled
2730 differently, so don't set rs6000_vector_mem. */
2731 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2733 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2734 rs6000_vector_align
[DFmode
] = 64;
2737 /* SFmode, see if we want to use the VSX unit. */
2738 if (TARGET_P8_VECTOR
&& TARGET_VSX_SCALAR_FLOAT
)
2740 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
2741 rs6000_vector_align
[SFmode
] = 32;
2744 /* Allow TImode in VSX register and set the VSX memory macros. */
2745 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2747 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2748 rs6000_vector_align
[TImode
] = align64
;
2751 /* TODO add SPE and paired floating point vector support. */
2753 /* Register class constraints for the constraints that depend on compile
2754 switches. When the VSX code was added, different constraints were added
2755 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2756 of the VSX registers are used. The register classes for scalar floating
2757 point types is set, based on whether we allow that type into the upper
2758 (Altivec) registers. GCC has register classes to target the Altivec
2759 registers for load/store operations, to select using a VSX memory
2760 operation instead of the traditional floating point operation. The
2763 d - Register class to use with traditional DFmode instructions.
2764 f - Register class to use with traditional SFmode instructions.
2765 v - Altivec register.
2766 wa - Any VSX register.
2767 wc - Reserved to represent individual CR bits (used in LLVM).
2768 wd - Preferred register class for V2DFmode.
2769 wf - Preferred register class for V4SFmode.
2770 wg - Float register for power6x move insns.
2771 wh - FP register for direct move instructions.
2772 wi - FP or VSX register to hold 64-bit integers for VSX insns.
2773 wj - FP or VSX register to hold 64-bit integers for direct moves.
2774 wk - FP or VSX register to hold 64-bit doubles for direct moves.
2775 wl - Float register if we can do 32-bit signed int loads.
2776 wm - VSX register for ISA 2.07 direct move operations.
2777 wn - always NO_REGS.
2778 wr - GPR if 64-bit mode is permitted.
2779 ws - Register class to do ISA 2.06 DF operations.
2780 wt - VSX register for TImode in VSX registers.
2781 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2782 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2783 ww - Register class to do SF conversions in with VSX operations.
2784 wx - Float register if we can do 32-bit int stores.
2785 wy - Register class to do ISA 2.07 SF operations.
2786 wz - Float register if we can do 32-bit unsigned int loads. */
2788 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2789 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
2791 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2792 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
2796 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2797 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
2798 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
2799 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = FLOAT_REGS
; /* DImode */
2801 if (TARGET_VSX_TIMODE
)
2802 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
2804 if (TARGET_UPPER_REGS_DF
) /* DFmode */
2806 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2807 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2810 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2813 /* Add conditional constraints based on various options, to allow us to
2814 collapse multiple insn patterns. */
2816 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2818 if (TARGET_MFPGPR
) /* DFmode */
2819 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2822 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
2824 if (TARGET_DIRECT_MOVE
)
2826 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
2827 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
2828 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
2829 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
2830 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
2831 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2834 if (TARGET_POWERPC64
)
2835 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2837 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
) /* SFmode */
2839 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2840 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2841 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2843 else if (TARGET_P8_VECTOR
)
2845 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2846 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2848 else if (TARGET_VSX
)
2849 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2852 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
2855 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
2857 /* Set up the reload helper and direct move functions. */
2858 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2862 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2863 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2864 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2865 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2866 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2867 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2868 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2869 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2870 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
2871 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
2872 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2873 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2874 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2875 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2876 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2877 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2878 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2879 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2880 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2881 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2883 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
2885 if (TARGET_NO_SDMODE_STACK
)
2887 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2888 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2891 if (TARGET_VSX_TIMODE
)
2893 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2894 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2897 if (TARGET_DIRECT_MOVE
)
2899 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2900 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
2901 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2902 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2903 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2904 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2905 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2906 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2907 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2909 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2910 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
2911 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2912 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2913 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2914 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2915 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2916 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2917 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2922 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2923 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2924 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2925 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2926 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2927 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2928 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2929 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2930 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
2931 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
2932 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2933 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2934 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2935 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2936 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2937 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2938 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2939 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2940 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2941 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2943 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
2945 if (TARGET_NO_SDMODE_STACK
)
2947 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2948 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2951 if (TARGET_VSX_TIMODE
)
2953 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2954 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2957 if (TARGET_DIRECT_MOVE
)
2959 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2960 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2961 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2965 if (TARGET_UPPER_REGS_DF
)
2966 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
2968 if (TARGET_UPPER_REGS_SF
)
2969 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
2972 /* Precalculate HARD_REGNO_NREGS. */
2973 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2974 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2975 rs6000_hard_regno_nregs
[m
][r
]
2976 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
)m
);
2978 /* Precalculate HARD_REGNO_MODE_OK. */
2979 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2980 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2981 if (rs6000_hard_regno_mode_ok (r
, (machine_mode
)m
))
2982 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2984 /* Precalculate CLASS_MAX_NREGS sizes. */
2985 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2989 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2990 reg_size
= UNITS_PER_VSX_WORD
;
2992 else if (c
== ALTIVEC_REGS
)
2993 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2995 else if (c
== FLOAT_REGS
)
2996 reg_size
= UNITS_PER_FP_WORD
;
2999 reg_size
= UNITS_PER_WORD
;
3001 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3003 machine_mode m2
= (machine_mode
)m
;
3004 int reg_size2
= reg_size
;
3006 /* TFmode/TDmode always takes 2 registers, even in VSX. */
3007 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
3008 && (m
== TDmode
|| m
== TFmode
))
3009 reg_size2
= UNITS_PER_FP_WORD
;
3011 rs6000_class_max_nregs
[m
][c
]
3012 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3016 if (TARGET_E500_DOUBLE
)
3017 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
3019 /* Calculate which modes to automatically generate code to use a the
3020 reciprocal divide and square root instructions. In the future, possibly
3021 automatically generate the instructions even if the user did not specify
3022 -mrecip. The older machines double precision reciprocal sqrt estimate is
3023 not accurate enough. */
3024 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3026 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3028 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3029 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3030 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3031 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3032 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3034 if (TARGET_FRSQRTES
)
3035 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3037 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3038 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3039 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3040 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3041 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3043 if (rs6000_recip_control
)
3045 if (!flag_finite_math_only
)
3046 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
3047 if (flag_trapping_math
)
3048 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
3049 if (!flag_reciprocal_math
)
3050 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
3051 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3053 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3054 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3055 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3057 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3058 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3059 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3061 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3062 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3063 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3065 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3066 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3067 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3069 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3070 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3071 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3073 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3074 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3075 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3077 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3078 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3079 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3081 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3082 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3083 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3087 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3088 legitimate address support to figure out the appropriate addressing to
3090 rs6000_setup_reg_addr_masks ();
3092 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3094 if (TARGET_DEBUG_REG
)
3095 rs6000_debug_reg_global ();
3097 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3099 "SImode variable mult cost = %d\n"
3100 "SImode constant mult cost = %d\n"
3101 "SImode short constant mult cost = %d\n"
3102 "DImode multipliciation cost = %d\n"
3103 "SImode division cost = %d\n"
3104 "DImode division cost = %d\n"
3105 "Simple fp operation cost = %d\n"
3106 "DFmode multiplication cost = %d\n"
3107 "SFmode division cost = %d\n"
3108 "DFmode division cost = %d\n"
3109 "cache line size = %d\n"
3110 "l1 cache size = %d\n"
3111 "l2 cache size = %d\n"
3112 "simultaneous prefetches = %d\n"
3115 rs6000_cost
->mulsi_const
,
3116 rs6000_cost
->mulsi_const9
,
3124 rs6000_cost
->cache_line_size
,
3125 rs6000_cost
->l1_cache_size
,
3126 rs6000_cost
->l2_cache_size
,
3127 rs6000_cost
->simultaneous_prefetches
);
3132 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3135 darwin_rs6000_override_options (void)
3137 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3139 rs6000_altivec_abi
= 1;
3140 TARGET_ALTIVEC_VRSAVE
= 1;
3141 rs6000_current_abi
= ABI_DARWIN
;
3143 if (DEFAULT_ABI
== ABI_DARWIN
3145 darwin_one_byte_bool
= 1;
3147 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3149 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3150 warning (0, "-m64 requires PowerPC64 architecture, enabling");
3154 rs6000_default_long_calls
= 1;
3155 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3158 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3160 if (!flag_mkernel
&& !flag_apple_kext
3162 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3163 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3165 /* Unless the user (not the configurer) has explicitly overridden
3166 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3167 G4 unless targeting the kernel. */
3170 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3171 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3172 && ! global_options_set
.x_rs6000_cpu_index
)
3174 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3179 /* If not otherwise specified by a target, make 'long double' equivalent to
3182 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3183 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3186 /* Return the builtin mask of the various options used that could affect which
3187 builtins were used. In the past we used target_flags, but we've run out of
3188 bits, and some options like SPE and PAIRED are no longer in
3192 rs6000_builtin_mask_calculate (void)
3194 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3195 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3196 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3197 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3198 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3199 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3200 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3201 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3202 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3203 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3204 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3205 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3206 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3207 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3208 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3209 | ((TARGET_LONG_DOUBLE_128
) ? RS6000_BTM_LDBL128
: 0));
3212 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3213 to clobber the XER[CA] bit because clobbering that bit without telling
3214 the compiler worked just fine with versions of GCC before GCC 5, and
3215 breaking a lot of older code in ways that are hard to track down is
3216 not such a great idea. */
3219 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3220 vec
<const char *> &/*constraints*/,
3221 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3223 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3224 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3228 /* Override command line options. Mostly we process the processor type and
3229 sometimes adjust other TARGET_ options. */
3232 rs6000_option_override_internal (bool global_init_p
)
3235 bool have_cpu
= false;
3237 /* The default cpu requested at configure time, if any. */
3238 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3240 HOST_WIDE_INT set_masks
;
3243 struct cl_target_option
*main_target_opt
3244 = ((global_init_p
|| target_option_default_node
== NULL
)
3245 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3247 /* Print defaults. */
3248 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3249 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3251 /* Remember the explicit arguments. */
3253 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3255 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3256 library functions, so warn about it. The flag may be useful for
3257 performance studies from time to time though, so don't disable it
3259 if (global_options_set
.x_rs6000_alignment_flags
3260 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3261 && DEFAULT_ABI
== ABI_DARWIN
3263 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3264 " it is incompatible with the installed C and C++ libraries");
3266 /* Numerous experiment shows that IRA based loop pressure
3267 calculation works better for RTL loop invariant motion on targets
3268 with enough (>= 32) registers. It is an expensive optimization.
3269 So it is on only for peak performance. */
3270 if (optimize
>= 3 && global_init_p
3271 && !global_options_set
.x_flag_ira_loop_pressure
)
3272 flag_ira_loop_pressure
= 1;
3274 /* Set the pointer size. */
3277 rs6000_pmode
= (int)DImode
;
3278 rs6000_pointer_size
= 64;
3282 rs6000_pmode
= (int)SImode
;
3283 rs6000_pointer_size
= 32;
3286 /* Some OSs don't support saving the high part of 64-bit registers on context
3287 switch. Other OSs don't support saving Altivec registers. On those OSs,
3288 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3289 if the user wants either, the user must explicitly specify them and we
3290 won't interfere with the user's specification. */
3292 set_masks
= POWERPC_MASKS
;
3293 #ifdef OS_MISSING_POWERPC64
3294 if (OS_MISSING_POWERPC64
)
3295 set_masks
&= ~OPTION_MASK_POWERPC64
;
3297 #ifdef OS_MISSING_ALTIVEC
3298 if (OS_MISSING_ALTIVEC
)
3299 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3302 /* Don't override by the processor default if given explicitly. */
3303 set_masks
&= ~rs6000_isa_flags_explicit
;
3305 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3306 the cpu in a target attribute or pragma, but did not specify a tuning
3307 option, use the cpu for the tuning option rather than the option specified
3308 with -mtune on the command line. Process a '--with-cpu' configuration
3309 request as an implicit --cpu. */
3310 if (rs6000_cpu_index
>= 0)
3312 cpu_index
= rs6000_cpu_index
;
3315 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3317 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3320 else if (implicit_cpu
)
3322 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3327 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3328 const char *default_cpu
= ((!TARGET_POWERPC64
)
3330 : ((BYTES_BIG_ENDIAN
)
3334 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3338 gcc_assert (cpu_index
>= 0);
3340 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3341 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3342 with those from the cpu, except for options that were explicitly set. If
3343 we don't have a cpu, do not override the target bits set in
3347 rs6000_isa_flags
&= ~set_masks
;
3348 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3353 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3354 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3355 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3356 to using rs6000_isa_flags, we need to do the initialization here.
3358 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3359 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3360 HOST_WIDE_INT flags
= ((TARGET_DEFAULT
) ? TARGET_DEFAULT
3361 : processor_target_table
[cpu_index
].target_enable
);
3362 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
3365 if (rs6000_tune_index
>= 0)
3366 tune_index
= rs6000_tune_index
;
3368 rs6000_tune_index
= tune_index
= cpu_index
;
3372 enum processor_type tune_proc
3373 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3376 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3377 if (processor_target_table
[i
].processor
== tune_proc
)
3379 rs6000_tune_index
= tune_index
= i
;
3384 gcc_assert (tune_index
>= 0);
3385 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3387 /* Pick defaults for SPE related control flags. Do this early to make sure
3388 that the TARGET_ macros are representative ASAP. */
3390 int spe_capable_cpu
=
3391 (rs6000_cpu
== PROCESSOR_PPC8540
3392 || rs6000_cpu
== PROCESSOR_PPC8548
);
3394 if (!global_options_set
.x_rs6000_spe_abi
)
3395 rs6000_spe_abi
= spe_capable_cpu
;
3397 if (!global_options_set
.x_rs6000_spe
)
3398 rs6000_spe
= spe_capable_cpu
;
3400 if (!global_options_set
.x_rs6000_float_gprs
)
3402 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3403 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3407 if (global_options_set
.x_rs6000_spe_abi
3410 error ("not configured for SPE ABI");
3412 if (global_options_set
.x_rs6000_spe
3415 error ("not configured for SPE instruction set");
3417 if (main_target_opt
!= NULL
3418 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3419 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3420 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3421 error ("target attribute or pragma changes SPE ABI");
3423 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3424 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3425 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3428 error ("AltiVec not supported in this target");
3430 error ("SPE not supported in this target");
3432 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3435 error ("SPE not supported in this target");
3438 /* Disable Cell microcode if we are optimizing for the Cell
3439 and not optimizing for size. */
3440 if (rs6000_gen_cell_microcode
== -1)
3441 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3444 /* If we are optimizing big endian systems for space and it's OK to
3445 use instructions that would be microcoded on the Cell, use the
3446 load/store multiple and string instructions. */
3447 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3448 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3449 | OPTION_MASK_STRING
);
3451 /* Don't allow -mmultiple or -mstring on little endian systems
3452 unless the cpu is a 750, because the hardware doesn't support the
3453 instructions used in little endian mode, and causes an alignment
3454 trap. The 750 does not cause an alignment trap (except when the
3455 target is unaligned). */
3457 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3459 if (TARGET_MULTIPLE
)
3461 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3462 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3463 warning (0, "-mmultiple is not supported on little endian systems");
3468 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3469 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3470 warning (0, "-mstring is not supported on little endian systems");
3474 /* If little-endian, default to -mstrict-align on older processors.
3475 Testing for htm matches power8 and later. */
3476 if (!BYTES_BIG_ENDIAN
3477 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3478 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3480 /* -maltivec={le,be} implies -maltivec. */
3481 if (rs6000_altivec_element_order
!= 0)
3482 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3484 /* Disallow -maltivec=le in big endian mode for now. This is not
3485 known to be useful for anyone. */
3486 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
3488 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3489 rs6000_altivec_element_order
= 0;
3492 /* Add some warnings for VSX. */
3495 const char *msg
= NULL
;
3496 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3497 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3499 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3500 msg
= N_("-mvsx requires hardware floating point");
3503 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3504 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3507 else if (TARGET_PAIRED_FLOAT
)
3508 msg
= N_("-mvsx and -mpaired are incompatible");
3509 else if (TARGET_AVOID_XFORM
> 0)
3510 msg
= N_("-mvsx needs indexed addressing");
3511 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3512 & OPTION_MASK_ALTIVEC
))
3514 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3515 msg
= N_("-mvsx and -mno-altivec are incompatible");
3517 msg
= N_("-mno-altivec disables vsx");
3523 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3524 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3528 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3529 the -mcpu setting to enable options that conflict. */
3530 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3531 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3532 | OPTION_MASK_ALTIVEC
3533 | OPTION_MASK_VSX
)) != 0)
3534 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3535 | OPTION_MASK_DIRECT_MOVE
)
3536 & ~rs6000_isa_flags_explicit
);
3538 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3539 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3541 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3542 unless the user explicitly used the -mno-<option> to disable the code. */
3543 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3544 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3545 else if (TARGET_VSX
)
3546 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3547 else if (TARGET_POPCNTD
)
3548 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3549 else if (TARGET_DFP
)
3550 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3551 else if (TARGET_CMPB
)
3552 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3553 else if (TARGET_FPRND
)
3554 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3555 else if (TARGET_POPCNTB
)
3556 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3557 else if (TARGET_ALTIVEC
)
3558 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3560 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3562 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3563 error ("-mcrypto requires -maltivec");
3564 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3567 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3569 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3570 error ("-mdirect-move requires -mvsx");
3571 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3574 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3576 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3577 error ("-mpower8-vector requires -maltivec");
3578 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3581 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3583 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3584 error ("-mpower8-vector requires -mvsx");
3585 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3588 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3590 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3591 error ("-mvsx-timode requires -mvsx");
3592 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3595 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
3597 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
3598 error ("-mhard-dfp requires -mhard-float");
3599 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
3602 /* Allow an explicit -mupper-regs to set both -mupper-regs-df and
3603 -mupper-regs-sf, depending on the cpu, unless the user explicitly also set
3604 the individual option. */
3605 if (TARGET_UPPER_REGS
> 0)
3608 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
3610 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_DF
;
3611 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
3613 if (TARGET_P8_VECTOR
3614 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
3616 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_SF
;
3617 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
3620 else if (TARGET_UPPER_REGS
== 0)
3623 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
3625 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
3626 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
3628 if (TARGET_P8_VECTOR
3629 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
3631 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
3632 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
3636 if (TARGET_UPPER_REGS_DF
&& !TARGET_VSX
)
3638 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
)
3639 error ("-mupper-regs-df requires -mvsx");
3640 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
3643 if (TARGET_UPPER_REGS_SF
&& !TARGET_P8_VECTOR
)
3645 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
)
3646 error ("-mupper-regs-sf requires -mpower8-vector");
3647 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
3650 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3651 silently turn off quad memory mode. */
3652 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
3654 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3655 warning (0, N_("-mquad-memory requires 64-bit mode"));
3657 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
3658 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3660 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
3661 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
3664 /* Non-atomic quad memory load/store are disabled for little endian, since
3665 the words are reversed, but atomic operations can still be done by
3666 swapping the words. */
3667 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
3669 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3670 warning (0, N_("-mquad-memory is not available in little endian mode"));
3672 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3675 /* Assume if the user asked for normal quad memory instructions, they want
3676 the atomic versions as well, unless they explicity told us not to use quad
3677 word atomic instructions. */
3678 if (TARGET_QUAD_MEMORY
3679 && !TARGET_QUAD_MEMORY_ATOMIC
3680 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
3681 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
3683 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3684 generating power8 instructions. */
3685 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3686 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3687 & OPTION_MASK_P8_FUSION
);
3689 /* Power8 does not fuse sign extended loads with the addis. If we are
3690 optimizing at high levels for speed, convert a sign extended load into a
3691 zero extending load, and an explicit sign extension. */
3692 if (TARGET_P8_FUSION
3693 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3694 && optimize_function_for_speed_p (cfun
)
3696 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3698 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3699 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3701 /* E500mc does "better" if we inline more aggressively. Respect the
3702 user's opinion, though. */
3703 if (rs6000_block_move_inline_limit
== 0
3704 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3705 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3706 || rs6000_cpu
== PROCESSOR_PPCE5500
3707 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3708 rs6000_block_move_inline_limit
= 128;
3710 /* store_one_arg depends on expand_block_move to handle at least the
3711 size of reg_parm_stack_space. */
3712 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3713 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3717 /* If the appropriate debug option is enabled, replace the target hooks
3718 with debug versions that call the real version and then prints
3719 debugging information. */
3720 if (TARGET_DEBUG_COST
)
3722 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3723 targetm
.address_cost
= rs6000_debug_address_cost
;
3724 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3727 if (TARGET_DEBUG_ADDR
)
3729 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3730 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3731 rs6000_secondary_reload_class_ptr
3732 = rs6000_debug_secondary_reload_class
;
3733 rs6000_secondary_memory_needed_ptr
3734 = rs6000_debug_secondary_memory_needed
;
3735 rs6000_cannot_change_mode_class_ptr
3736 = rs6000_debug_cannot_change_mode_class
;
3737 rs6000_preferred_reload_class_ptr
3738 = rs6000_debug_preferred_reload_class
;
3739 rs6000_legitimize_reload_address_ptr
3740 = rs6000_debug_legitimize_reload_address
;
3741 rs6000_mode_dependent_address_ptr
3742 = rs6000_debug_mode_dependent_address
;
3745 if (rs6000_veclibabi_name
)
3747 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3748 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3751 error ("unknown vectorization library ABI type (%s) for "
3752 "-mveclibabi= switch", rs6000_veclibabi_name
);
3758 if (!global_options_set
.x_rs6000_long_double_type_size
)
3760 if (main_target_opt
!= NULL
3761 && (main_target_opt
->x_rs6000_long_double_type_size
3762 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3763 error ("target attribute or pragma changes long double size");
3765 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3768 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3769 if (!global_options_set
.x_rs6000_ieeequad
)
3770 rs6000_ieeequad
= 1;
3773 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3774 target attribute or pragma which automatically enables both options,
3775 unless the altivec ABI was set. This is set by default for 64-bit, but
3777 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3778 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3779 & ~rs6000_isa_flags_explicit
);
3781 /* Enable Altivec ABI for AIX -maltivec. */
3782 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3784 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3785 error ("target attribute or pragma changes AltiVec ABI");
3787 rs6000_altivec_abi
= 1;
3790 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3791 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3792 be explicitly overridden in either case. */
3795 if (!global_options_set
.x_rs6000_altivec_abi
3796 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3798 if (main_target_opt
!= NULL
&&
3799 !main_target_opt
->x_rs6000_altivec_abi
)
3800 error ("target attribute or pragma changes AltiVec ABI");
3802 rs6000_altivec_abi
= 1;
3806 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3807 So far, the only darwin64 targets are also MACH-O. */
3809 && DEFAULT_ABI
== ABI_DARWIN
3812 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3813 error ("target attribute or pragma changes darwin64 ABI");
3816 rs6000_darwin64_abi
= 1;
3817 /* Default to natural alignment, for better performance. */
3818 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3822 /* Place FP constants in the constant pool instead of TOC
3823 if section anchors enabled. */
3824 if (flag_section_anchors
3825 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3826 TARGET_NO_FP_IN_TOC
= 1;
3828 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3829 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3831 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3832 SUBTARGET_OVERRIDE_OPTIONS
;
3834 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3835 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3837 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3838 SUB3TARGET_OVERRIDE_OPTIONS
;
3841 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3842 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3844 /* For the E500 family of cores, reset the single/double FP flags to let us
3845 check that they remain constant across attributes or pragmas. Also,
3846 clear a possible request for string instructions, not supported and which
3847 we might have silently queried above for -Os.
3849 For other families, clear ISEL in case it was set implicitly.
3854 case PROCESSOR_PPC8540
:
3855 case PROCESSOR_PPC8548
:
3856 case PROCESSOR_PPCE500MC
:
3857 case PROCESSOR_PPCE500MC64
:
3858 case PROCESSOR_PPCE5500
:
3859 case PROCESSOR_PPCE6500
:
3861 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3862 rs6000_double_float
= TARGET_E500_DOUBLE
;
3864 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3870 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3871 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3876 if (main_target_opt
)
3878 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3879 error ("target attribute or pragma changes single precision floating "
3881 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3882 error ("target attribute or pragma changes double precision floating "
3886 /* Detect invalid option combinations with E500. */
3889 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3890 && rs6000_cpu
!= PROCESSOR_POWER5
3891 && rs6000_cpu
!= PROCESSOR_POWER6
3892 && rs6000_cpu
!= PROCESSOR_POWER7
3893 && rs6000_cpu
!= PROCESSOR_POWER8
3894 && rs6000_cpu
!= PROCESSOR_PPCA2
3895 && rs6000_cpu
!= PROCESSOR_CELL
3896 && rs6000_cpu
!= PROCESSOR_PPC476
);
3897 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3898 || rs6000_cpu
== PROCESSOR_POWER5
3899 || rs6000_cpu
== PROCESSOR_POWER7
3900 || rs6000_cpu
== PROCESSOR_POWER8
);
3901 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3902 || rs6000_cpu
== PROCESSOR_POWER5
3903 || rs6000_cpu
== PROCESSOR_POWER6
3904 || rs6000_cpu
== PROCESSOR_POWER7
3905 || rs6000_cpu
== PROCESSOR_POWER8
3906 || rs6000_cpu
== PROCESSOR_PPCE500MC
3907 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3908 || rs6000_cpu
== PROCESSOR_PPCE5500
3909 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3911 /* Allow debug switches to override the above settings. These are set to -1
3912 in rs6000.opt to indicate the user hasn't directly set the switch. */
3913 if (TARGET_ALWAYS_HINT
>= 0)
3914 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3916 if (TARGET_SCHED_GROUPS
>= 0)
3917 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3919 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3920 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3922 rs6000_sched_restricted_insns_priority
3923 = (rs6000_sched_groups
? 1 : 0);
3925 /* Handle -msched-costly-dep option. */
3926 rs6000_sched_costly_dep
3927 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3929 if (rs6000_sched_costly_dep_str
)
3931 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3932 rs6000_sched_costly_dep
= no_dep_costly
;
3933 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3934 rs6000_sched_costly_dep
= all_deps_costly
;
3935 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3936 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3937 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3938 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3940 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3941 atoi (rs6000_sched_costly_dep_str
));
3944 /* Handle -minsert-sched-nops option. */
3945 rs6000_sched_insert_nops
3946 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3948 if (rs6000_sched_insert_nops_str
)
3950 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3951 rs6000_sched_insert_nops
= sched_finish_none
;
3952 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3953 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3954 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3955 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3957 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3958 atoi (rs6000_sched_insert_nops_str
));
3963 #ifdef TARGET_REGNAMES
3964 /* If the user desires alternate register names, copy in the
3965 alternate names now. */
3966 if (TARGET_REGNAMES
)
3967 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3970 /* Set aix_struct_return last, after the ABI is determined.
3971 If -maix-struct-return or -msvr4-struct-return was explicitly
3972 used, don't override with the ABI default. */
3973 if (!global_options_set
.x_aix_struct_return
)
3974 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3977 /* IBM XL compiler defaults to unsigned bitfields. */
3978 if (TARGET_XL_COMPAT
)
3979 flag_signed_bitfields
= 0;
3982 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3983 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3986 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3988 /* We can only guarantee the availability of DI pseudo-ops when
3989 assembling for 64-bit targets. */
3992 targetm
.asm_out
.aligned_op
.di
= NULL
;
3993 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3997 /* Set branch target alignment, if not optimizing for size. */
4000 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4001 aligned 8byte to avoid misprediction by the branch predictor. */
4002 if (rs6000_cpu
== PROCESSOR_TITAN
4003 || rs6000_cpu
== PROCESSOR_CELL
)
4005 if (align_functions
<= 0)
4006 align_functions
= 8;
4007 if (align_jumps
<= 0)
4009 if (align_loops
<= 0)
4012 if (rs6000_align_branch_targets
)
4014 if (align_functions
<= 0)
4015 align_functions
= 16;
4016 if (align_jumps
<= 0)
4018 if (align_loops
<= 0)
4020 can_override_loop_align
= 1;
4024 if (align_jumps_max_skip
<= 0)
4025 align_jumps_max_skip
= 15;
4026 if (align_loops_max_skip
<= 0)
4027 align_loops_max_skip
= 15;
4030 /* Arrange to save and restore machine status around nested functions. */
4031 init_machine_status
= rs6000_init_machine_status
;
4033 /* We should always be splitting complex arguments, but we can't break
4034 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4035 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
4036 targetm
.calls
.split_complex_arg
= NULL
;
4039 /* Initialize rs6000_cost with the appropriate target costs. */
4041 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
4045 case PROCESSOR_RS64A
:
4046 rs6000_cost
= &rs64a_cost
;
4049 case PROCESSOR_MPCCORE
:
4050 rs6000_cost
= &mpccore_cost
;
4053 case PROCESSOR_PPC403
:
4054 rs6000_cost
= &ppc403_cost
;
4057 case PROCESSOR_PPC405
:
4058 rs6000_cost
= &ppc405_cost
;
4061 case PROCESSOR_PPC440
:
4062 rs6000_cost
= &ppc440_cost
;
4065 case PROCESSOR_PPC476
:
4066 rs6000_cost
= &ppc476_cost
;
4069 case PROCESSOR_PPC601
:
4070 rs6000_cost
= &ppc601_cost
;
4073 case PROCESSOR_PPC603
:
4074 rs6000_cost
= &ppc603_cost
;
4077 case PROCESSOR_PPC604
:
4078 rs6000_cost
= &ppc604_cost
;
4081 case PROCESSOR_PPC604e
:
4082 rs6000_cost
= &ppc604e_cost
;
4085 case PROCESSOR_PPC620
:
4086 rs6000_cost
= &ppc620_cost
;
4089 case PROCESSOR_PPC630
:
4090 rs6000_cost
= &ppc630_cost
;
4093 case PROCESSOR_CELL
:
4094 rs6000_cost
= &ppccell_cost
;
4097 case PROCESSOR_PPC750
:
4098 case PROCESSOR_PPC7400
:
4099 rs6000_cost
= &ppc750_cost
;
4102 case PROCESSOR_PPC7450
:
4103 rs6000_cost
= &ppc7450_cost
;
4106 case PROCESSOR_PPC8540
:
4107 case PROCESSOR_PPC8548
:
4108 rs6000_cost
= &ppc8540_cost
;
4111 case PROCESSOR_PPCE300C2
:
4112 case PROCESSOR_PPCE300C3
:
4113 rs6000_cost
= &ppce300c2c3_cost
;
4116 case PROCESSOR_PPCE500MC
:
4117 rs6000_cost
= &ppce500mc_cost
;
4120 case PROCESSOR_PPCE500MC64
:
4121 rs6000_cost
= &ppce500mc64_cost
;
4124 case PROCESSOR_PPCE5500
:
4125 rs6000_cost
= &ppce5500_cost
;
4128 case PROCESSOR_PPCE6500
:
4129 rs6000_cost
= &ppce6500_cost
;
4132 case PROCESSOR_TITAN
:
4133 rs6000_cost
= &titan_cost
;
4136 case PROCESSOR_POWER4
:
4137 case PROCESSOR_POWER5
:
4138 rs6000_cost
= &power4_cost
;
4141 case PROCESSOR_POWER6
:
4142 rs6000_cost
= &power6_cost
;
4145 case PROCESSOR_POWER7
:
4146 rs6000_cost
= &power7_cost
;
4149 case PROCESSOR_POWER8
:
4150 rs6000_cost
= &power8_cost
;
4153 case PROCESSOR_PPCA2
:
4154 rs6000_cost
= &ppca2_cost
;
4163 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
4164 rs6000_cost
->simultaneous_prefetches
,
4165 global_options
.x_param_values
,
4166 global_options_set
.x_param_values
);
4167 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
4168 global_options
.x_param_values
,
4169 global_options_set
.x_param_values
);
4170 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
4171 rs6000_cost
->cache_line_size
,
4172 global_options
.x_param_values
,
4173 global_options_set
.x_param_values
);
4174 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
4175 global_options
.x_param_values
,
4176 global_options_set
.x_param_values
);
4178 /* Increase loop peeling limits based on performance analysis. */
4179 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
4180 global_options
.x_param_values
,
4181 global_options_set
.x_param_values
);
4182 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
4183 global_options
.x_param_values
,
4184 global_options_set
.x_param_values
);
4186 /* If using typedef char *va_list, signal that
4187 __builtin_va_start (&ap, 0) can be optimized to
4188 ap = __builtin_next_arg (0). */
4189 if (DEFAULT_ABI
!= ABI_V4
)
4190 targetm
.expand_builtin_va_start
= NULL
;
4193 /* Set up single/double float flags.
4194 If TARGET_HARD_FLOAT is set, but neither single or double is set,
4195 then set both flags. */
4196 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
4197 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
4198 rs6000_single_float
= rs6000_double_float
= 1;
4200 /* If not explicitly specified via option, decide whether to generate indexed
4201 load/store instructions. */
4202 if (TARGET_AVOID_XFORM
== -1)
4203 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4204 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4205 need indexed accesses and the type used is the scalar type of the element
4206 being loaded or stored. */
4207 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
4208 && !TARGET_ALTIVEC
);
4210 /* Set the -mrecip options. */
4211 if (rs6000_recip_name
)
4213 char *p
= ASTRDUP (rs6000_recip_name
);
4215 unsigned int mask
, i
;
4218 while ((q
= strtok (p
, ",")) != NULL
)
4229 if (!strcmp (q
, "default"))
4230 mask
= ((TARGET_RECIP_PRECISION
)
4231 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
4234 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
4235 if (!strcmp (q
, recip_options
[i
].string
))
4237 mask
= recip_options
[i
].mask
;
4241 if (i
== ARRAY_SIZE (recip_options
))
4243 error ("unknown option for -mrecip=%s", q
);
4251 rs6000_recip_control
&= ~mask
;
4253 rs6000_recip_control
|= mask
;
4257 /* Determine when unaligned vector accesses are permitted, and when
4258 they are preferred over masked Altivec loads. Note that if
4259 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4260 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4262 if (TARGET_EFFICIENT_UNALIGNED_VSX
== -1) {
4263 if (TARGET_VSX
&& rs6000_cpu
== PROCESSOR_POWER8
4264 && TARGET_ALLOW_MOVMISALIGN
!= 0)
4265 TARGET_EFFICIENT_UNALIGNED_VSX
= 1;
4267 TARGET_EFFICIENT_UNALIGNED_VSX
= 0;
4270 if (TARGET_ALLOW_MOVMISALIGN
== -1 && rs6000_cpu
== PROCESSOR_POWER8
)
4271 TARGET_ALLOW_MOVMISALIGN
= 1;
4273 /* Set the builtin mask of the various options used that could affect which
4274 builtins were used. In the past we used target_flags, but we've run out
4275 of bits, and some options like SPE and PAIRED are no longer in
4277 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
4278 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
4279 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
4280 rs6000_builtin_mask
);
4282 /* Initialize all of the registers. */
4283 rs6000_init_hard_regno_mode_ok (global_init_p
);
4285 /* Save the initial options in case the user does function specific options */
4287 target_option_default_node
= target_option_current_node
4288 = build_target_option_node (&global_options
);
4290 /* If not explicitly specified via option, decide whether to generate the
4291 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4292 if (TARGET_LINK_STACK
== -1)
4293 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
4298 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4299 define the target cpu type. */
4302 rs6000_option_override (void)
4304 (void) rs6000_option_override_internal (true);
4306 /* Register machine-specific passes. This needs to be done at start-up.
4307 It's convenient to do it here (like i386 does). */
4308 opt_pass
*pass_analyze_swaps
= make_pass_analyze_swaps (g
);
4310 struct register_pass_info analyze_swaps_info
4311 = { pass_analyze_swaps
, "cse1", 1, PASS_POS_INSERT_BEFORE
};
4313 register_pass (&analyze_swaps_info
);
4317 /* Implement targetm.vectorize.builtin_mask_for_load. */
4319 rs6000_builtin_mask_for_load (void)
4321 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4322 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
4323 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
4324 return altivec_builtin_mask_for_load
;
4329 /* Implement LOOP_ALIGN. */
4331 rs6000_loop_align (rtx label
)
4336 /* Don't override loop alignment if -falign-loops was specified. */
4337 if (!can_override_loop_align
)
4338 return align_loops_log
;
4340 bb
= BLOCK_FOR_INSN (label
);
4341 ninsns
= num_loop_insns(bb
->loop_father
);
4343 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4344 if (ninsns
> 4 && ninsns
<= 8
4345 && (rs6000_cpu
== PROCESSOR_POWER4
4346 || rs6000_cpu
== PROCESSOR_POWER5
4347 || rs6000_cpu
== PROCESSOR_POWER6
4348 || rs6000_cpu
== PROCESSOR_POWER7
4349 || rs6000_cpu
== PROCESSOR_POWER8
))
4352 return align_loops_log
;
4355 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4357 rs6000_loop_align_max_skip (rtx_insn
*label
)
4359 return (1 << rs6000_loop_align (label
)) - 1;
4362 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4363 after applying N number of iterations. This routine does not determine
4364 how may iterations are required to reach desired alignment. */
4367 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4374 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4377 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4387 /* Assuming that all other types are naturally aligned. CHECKME! */
4392 /* Return true if the vector misalignment factor is supported by the
4395 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
4402 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4405 /* Return if movmisalign pattern is not supported for this mode. */
4406 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4409 if (misalignment
== -1)
4411 /* Misalignment factor is unknown at compile time but we know
4412 it's word aligned. */
4413 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4415 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4417 if (element_size
== 64 || element_size
== 32)
4424 /* VSX supports word-aligned vector. */
4425 if (misalignment
% 4 == 0)
4431 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4433 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4434 tree vectype
, int misalign
)
4439 switch (type_of_cost
)
4449 case cond_branch_not_taken
:
4458 case vec_promote_demote
:
4464 case cond_branch_taken
:
4467 case unaligned_load
:
4468 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4471 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4473 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4475 /* Double word aligned. */
4483 /* Double word aligned. */
4487 /* Unknown misalignment. */
4500 /* Misaligned loads are not supported. */
4505 case unaligned_store
:
4506 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4509 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4511 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4513 /* Double word aligned. */
4521 /* Double word aligned. */
4525 /* Unknown misalignment. */
4538 /* Misaligned stores are not supported. */
4544 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4545 elem_type
= TREE_TYPE (vectype
);
4546 /* 32-bit vectors loaded into registers are stored as double
4547 precision, so we need n/2 converts in addition to the usual
4548 n/2 merges to construct a vector of short floats from them. */
4549 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4550 && TYPE_PRECISION (elem_type
) == 32)
4551 return elements
+ 1;
4553 return elements
/ 2 + 1;
4560 /* Implement targetm.vectorize.preferred_simd_mode. */
4563 rs6000_preferred_simd_mode (machine_mode mode
)
4572 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4598 if (TARGET_PAIRED_FLOAT
4604 typedef struct _rs6000_cost_data
4606 struct loop
*loop_info
;
4610 /* Test for likely overcommitment of vector hardware resources. If a
4611 loop iteration is relatively large, and too large a percentage of
4612 instructions in the loop are vectorized, the cost model may not
4613 adequately reflect delays from unavailable vector resources.
4614 Penalize the loop body cost for this case. */
4617 rs6000_density_test (rs6000_cost_data
*data
)
4619 const int DENSITY_PCT_THRESHOLD
= 85;
4620 const int DENSITY_SIZE_THRESHOLD
= 70;
4621 const int DENSITY_PENALTY
= 10;
4622 struct loop
*loop
= data
->loop_info
;
4623 basic_block
*bbs
= get_loop_body (loop
);
4624 int nbbs
= loop
->num_nodes
;
4625 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4628 for (i
= 0; i
< nbbs
; i
++)
4630 basic_block bb
= bbs
[i
];
4631 gimple_stmt_iterator gsi
;
4633 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4635 gimple stmt
= gsi_stmt (gsi
);
4636 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4638 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4639 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4645 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4647 if (density_pct
> DENSITY_PCT_THRESHOLD
4648 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4650 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4651 if (dump_enabled_p ())
4652 dump_printf_loc (MSG_NOTE
, vect_location
,
4653 "density %d%%, cost %d exceeds threshold, penalizing "
4654 "loop body cost by %d%%", density_pct
,
4655 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4659 /* Implement targetm.vectorize.init_cost. */
4662 rs6000_init_cost (struct loop
*loop_info
)
4664 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4665 data
->loop_info
= loop_info
;
4666 data
->cost
[vect_prologue
] = 0;
4667 data
->cost
[vect_body
] = 0;
4668 data
->cost
[vect_epilogue
] = 0;
4672 /* Implement targetm.vectorize.add_stmt_cost. */
4675 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4676 struct _stmt_vec_info
*stmt_info
, int misalign
,
4677 enum vect_cost_model_location where
)
4679 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4680 unsigned retval
= 0;
4682 if (flag_vect_cost_model
)
4684 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4685 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4687 /* Statements in an inner loop relative to the loop being
4688 vectorized are weighted more heavily. The value here is
4689 arbitrary and could potentially be improved with analysis. */
4690 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4691 count
*= 50; /* FIXME. */
4693 retval
= (unsigned) (count
* stmt_cost
);
4694 cost_data
->cost
[where
] += retval
;
4700 /* Implement targetm.vectorize.finish_cost. */
4703 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4704 unsigned *body_cost
, unsigned *epilogue_cost
)
4706 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4708 if (cost_data
->loop_info
)
4709 rs6000_density_test (cost_data
);
4711 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4712 *body_cost
= cost_data
->cost
[vect_body
];
4713 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4716 /* Implement targetm.vectorize.destroy_cost_data. */
4719 rs6000_destroy_cost_data (void *data
)
4724 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4725 library with vectorized intrinsics. */
4728 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4731 const char *suffix
= NULL
;
4732 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4735 machine_mode el_mode
, in_mode
;
4738 /* Libmass is suitable for unsafe math only as it does not correctly support
4739 parts of IEEE with the required precision such as denormals. Only support
4740 it if we have VSX to use the simd d2 or f4 functions.
4741 XXX: Add variable length support. */
4742 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4745 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4746 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4747 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4748 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4749 if (el_mode
!= in_mode
4753 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4755 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4758 case BUILT_IN_ATAN2
:
4759 case BUILT_IN_HYPOT
:
4765 case BUILT_IN_ACOSH
:
4767 case BUILT_IN_ASINH
:
4769 case BUILT_IN_ATANH
:
4777 case BUILT_IN_EXPM1
:
4778 case BUILT_IN_LGAMMA
:
4779 case BUILT_IN_LOG10
:
4780 case BUILT_IN_LOG1P
:
4788 bdecl
= builtin_decl_implicit (fn
);
4789 suffix
= "d2"; /* pow -> powd2 */
4790 if (el_mode
!= DFmode
4796 case BUILT_IN_ATAN2F
:
4797 case BUILT_IN_HYPOTF
:
4802 case BUILT_IN_ACOSF
:
4803 case BUILT_IN_ACOSHF
:
4804 case BUILT_IN_ASINF
:
4805 case BUILT_IN_ASINHF
:
4806 case BUILT_IN_ATANF
:
4807 case BUILT_IN_ATANHF
:
4808 case BUILT_IN_CBRTF
:
4810 case BUILT_IN_COSHF
:
4812 case BUILT_IN_ERFCF
:
4813 case BUILT_IN_EXP2F
:
4815 case BUILT_IN_EXPM1F
:
4816 case BUILT_IN_LGAMMAF
:
4817 case BUILT_IN_LOG10F
:
4818 case BUILT_IN_LOG1PF
:
4819 case BUILT_IN_LOG2F
:
4822 case BUILT_IN_SINHF
:
4823 case BUILT_IN_SQRTF
:
4825 case BUILT_IN_TANHF
:
4826 bdecl
= builtin_decl_implicit (fn
);
4827 suffix
= "4"; /* powf -> powf4 */
4828 if (el_mode
!= SFmode
4841 gcc_assert (suffix
!= NULL
);
4842 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4846 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4847 strcat (name
, suffix
);
4850 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4851 else if (n_args
== 2)
4852 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4856 /* Build a function declaration for the vectorized function. */
4857 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4858 FUNCTION_DECL
, get_identifier (name
), fntype
);
4859 TREE_PUBLIC (new_fndecl
) = 1;
4860 DECL_EXTERNAL (new_fndecl
) = 1;
4861 DECL_IS_NOVOPS (new_fndecl
) = 1;
4862 TREE_READONLY (new_fndecl
) = 1;
4867 /* Returns a function decl for a vectorized version of the builtin function
4868 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4869 if it is not available. */
4872 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4875 machine_mode in_mode
, out_mode
;
4878 if (TARGET_DEBUG_BUILTIN
)
4879 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4880 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4881 GET_MODE_NAME (TYPE_MODE (type_out
)),
4882 GET_MODE_NAME (TYPE_MODE (type_in
)));
4884 if (TREE_CODE (type_out
) != VECTOR_TYPE
4885 || TREE_CODE (type_in
) != VECTOR_TYPE
4886 || !TARGET_VECTORIZE_BUILTINS
)
4889 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4890 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4891 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4892 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4894 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4896 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4899 case BUILT_IN_CLZIMAX
:
4900 case BUILT_IN_CLZLL
:
4903 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4905 if (out_mode
== QImode
&& out_n
== 16)
4906 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4907 else if (out_mode
== HImode
&& out_n
== 8)
4908 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4909 else if (out_mode
== SImode
&& out_n
== 4)
4910 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4911 else if (out_mode
== DImode
&& out_n
== 2)
4912 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4915 case BUILT_IN_COPYSIGN
:
4916 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4917 && out_mode
== DFmode
&& out_n
== 2
4918 && in_mode
== DFmode
&& in_n
== 2)
4919 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4921 case BUILT_IN_COPYSIGNF
:
4922 if (out_mode
!= SFmode
|| out_n
!= 4
4923 || in_mode
!= SFmode
|| in_n
!= 4)
4925 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4926 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4927 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4928 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4930 case BUILT_IN_POPCOUNTIMAX
:
4931 case BUILT_IN_POPCOUNTLL
:
4932 case BUILT_IN_POPCOUNTL
:
4933 case BUILT_IN_POPCOUNT
:
4934 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4936 if (out_mode
== QImode
&& out_n
== 16)
4937 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4938 else if (out_mode
== HImode
&& out_n
== 8)
4939 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4940 else if (out_mode
== SImode
&& out_n
== 4)
4941 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4942 else if (out_mode
== DImode
&& out_n
== 2)
4943 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4947 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4948 && out_mode
== DFmode
&& out_n
== 2
4949 && in_mode
== DFmode
&& in_n
== 2)
4950 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4952 case BUILT_IN_SQRTF
:
4953 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4954 && out_mode
== SFmode
&& out_n
== 4
4955 && in_mode
== SFmode
&& in_n
== 4)
4956 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4959 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4960 && out_mode
== DFmode
&& out_n
== 2
4961 && in_mode
== DFmode
&& in_n
== 2)
4962 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4964 case BUILT_IN_CEILF
:
4965 if (out_mode
!= SFmode
|| out_n
!= 4
4966 || in_mode
!= SFmode
|| in_n
!= 4)
4968 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4969 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4970 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4971 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4973 case BUILT_IN_FLOOR
:
4974 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4975 && out_mode
== DFmode
&& out_n
== 2
4976 && in_mode
== DFmode
&& in_n
== 2)
4977 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4979 case BUILT_IN_FLOORF
:
4980 if (out_mode
!= SFmode
|| out_n
!= 4
4981 || in_mode
!= SFmode
|| in_n
!= 4)
4983 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4984 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4985 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4986 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4989 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4990 && out_mode
== DFmode
&& out_n
== 2
4991 && in_mode
== DFmode
&& in_n
== 2)
4992 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4995 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4996 && out_mode
== SFmode
&& out_n
== 4
4997 && in_mode
== SFmode
&& in_n
== 4)
4998 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4999 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5000 && out_mode
== SFmode
&& out_n
== 4
5001 && in_mode
== SFmode
&& in_n
== 4)
5002 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5004 case BUILT_IN_TRUNC
:
5005 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5006 && out_mode
== DFmode
&& out_n
== 2
5007 && in_mode
== DFmode
&& in_n
== 2)
5008 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5010 case BUILT_IN_TRUNCF
:
5011 if (out_mode
!= SFmode
|| out_n
!= 4
5012 || in_mode
!= SFmode
|| in_n
!= 4)
5014 if (VECTOR_UNIT_VSX_P (V4SFmode
))
5015 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5016 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
5017 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5019 case BUILT_IN_NEARBYINT
:
5020 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5021 && flag_unsafe_math_optimizations
5022 && out_mode
== DFmode
&& out_n
== 2
5023 && in_mode
== DFmode
&& in_n
== 2)
5024 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5026 case BUILT_IN_NEARBYINTF
:
5027 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5028 && flag_unsafe_math_optimizations
5029 && out_mode
== SFmode
&& out_n
== 4
5030 && in_mode
== SFmode
&& in_n
== 4)
5031 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
5034 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5035 && !flag_trapping_math
5036 && out_mode
== DFmode
&& out_n
== 2
5037 && in_mode
== DFmode
&& in_n
== 2)
5038 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
5040 case BUILT_IN_RINTF
:
5041 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5042 && !flag_trapping_math
5043 && out_mode
== SFmode
&& out_n
== 4
5044 && in_mode
== SFmode
&& in_n
== 4)
5045 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
5052 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
5054 enum rs6000_builtins fn
5055 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
5058 case RS6000_BUILTIN_RSQRTF
:
5059 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5060 && out_mode
== SFmode
&& out_n
== 4
5061 && in_mode
== SFmode
&& in_n
== 4)
5062 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
5064 case RS6000_BUILTIN_RSQRT
:
5065 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5066 && out_mode
== DFmode
&& out_n
== 2
5067 && in_mode
== DFmode
&& in_n
== 2)
5068 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
5070 case RS6000_BUILTIN_RECIPF
:
5071 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5072 && out_mode
== SFmode
&& out_n
== 4
5073 && in_mode
== SFmode
&& in_n
== 4)
5074 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
5076 case RS6000_BUILTIN_RECIP
:
5077 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5078 && out_mode
== DFmode
&& out_n
== 2
5079 && in_mode
== DFmode
&& in_n
== 2)
5080 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
5087 /* Generate calls to libmass if appropriate. */
5088 if (rs6000_veclib_handler
)
5089 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
5094 /* Default CPU string for rs6000*_file_start functions. */
5095 static const char *rs6000_default_cpu
;
5097 /* Do anything needed at the start of the asm file. */
5100 rs6000_file_start (void)
5103 const char *start
= buffer
;
5104 FILE *file
= asm_out_file
;
5106 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
5108 default_file_start ();
5110 if (flag_verbose_asm
)
5112 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
5114 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
5116 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
5120 if (global_options_set
.x_rs6000_cpu_index
)
5122 fprintf (file
, "%s -mcpu=%s", start
,
5123 processor_target_table
[rs6000_cpu_index
].name
);
5127 if (global_options_set
.x_rs6000_tune_index
)
5129 fprintf (file
, "%s -mtune=%s", start
,
5130 processor_target_table
[rs6000_tune_index
].name
);
5134 if (PPC405_ERRATUM77
)
5136 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
5140 #ifdef USING_ELFOS_H
5141 switch (rs6000_sdata
)
5143 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
5144 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
5145 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
5146 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
5149 if (rs6000_sdata
&& g_switch_value
)
5151 fprintf (file
, "%s -G %d", start
,
5161 #ifdef USING_ELFOS_H
5162 if (rs6000_default_cpu
== 0 || rs6000_default_cpu
[0] == '\0'
5163 || !global_options_set
.x_rs6000_cpu_index
)
5165 fputs ("\t.machine ", asm_out_file
);
5166 if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
5167 fputs ("power8\n", asm_out_file
);
5168 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
5169 fputs ("power7\n", asm_out_file
);
5170 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
5171 fputs ("power6\n", asm_out_file
);
5172 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
5173 fputs ("power5\n", asm_out_file
);
5174 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
5175 fputs ("power4\n", asm_out_file
);
5176 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
5177 fputs ("ppc64\n", asm_out_file
);
5179 fputs ("ppc\n", asm_out_file
);
5183 if (DEFAULT_ABI
== ABI_ELFv2
)
5184 fprintf (file
, "\t.abiversion 2\n");
5186 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
5187 || (TARGET_ELF
&& flag_pic
== 2))
5189 switch_to_section (toc_section
);
5190 switch_to_section (text_section
);
5195 /* Return nonzero if this function is known to have a null epilogue. */
5198 direct_return (void)
5200 if (reload_completed
)
5202 rs6000_stack_t
*info
= rs6000_stack_info ();
5204 if (info
->first_gp_reg_save
== 32
5205 && info
->first_fp_reg_save
== 64
5206 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
5207 && ! info
->lr_save_p
5208 && ! info
->cr_save_p
5209 && info
->vrsave_mask
== 0
5217 /* Return the number of instructions it takes to form a constant in an
5218 integer register. */
5221 num_insns_constant_wide (HOST_WIDE_INT value
)
5223 /* signed constant loadable with addi */
5224 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
5227 /* constant loadable with addis */
5228 else if ((value
& 0xffff) == 0
5229 && (value
>> 31 == -1 || value
>> 31 == 0))
5232 else if (TARGET_POWERPC64
)
5234 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
5235 HOST_WIDE_INT high
= value
>> 31;
5237 if (high
== 0 || high
== -1)
5243 return num_insns_constant_wide (high
) + 1;
5245 return num_insns_constant_wide (low
) + 1;
5247 return (num_insns_constant_wide (high
)
5248 + num_insns_constant_wide (low
) + 1);
5256 num_insns_constant (rtx op
, machine_mode mode
)
5258 HOST_WIDE_INT low
, high
;
5260 switch (GET_CODE (op
))
5263 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
5264 && mask64_operand (op
, mode
))
5267 return num_insns_constant_wide (INTVAL (op
));
5269 case CONST_WIDE_INT
:
5272 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
5273 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
5274 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
5279 if (mode
== SFmode
|| mode
== SDmode
)
5284 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
5285 if (DECIMAL_FLOAT_MODE_P (mode
))
5286 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
5288 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
5289 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
5295 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
5296 if (DECIMAL_FLOAT_MODE_P (mode
))
5297 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
5299 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
5300 high
= l
[WORDS_BIG_ENDIAN
== 0];
5301 low
= l
[WORDS_BIG_ENDIAN
!= 0];
5304 return (num_insns_constant_wide (low
)
5305 + num_insns_constant_wide (high
));
5308 if ((high
== 0 && low
>= 0)
5309 || (high
== -1 && low
< 0))
5310 return num_insns_constant_wide (low
);
5312 else if (mask64_operand (op
, mode
))
5316 return num_insns_constant_wide (high
) + 1;
5319 return (num_insns_constant_wide (high
)
5320 + num_insns_constant_wide (low
) + 1);
5328 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5329 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5330 corresponding element of the vector, but for V4SFmode and V2SFmode,
5331 the corresponding "float" is interpreted as an SImode integer. */
5334 const_vector_elt_as_int (rtx op
, unsigned int elt
)
5338 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5339 gcc_assert (GET_MODE (op
) != V2DImode
5340 && GET_MODE (op
) != V2DFmode
);
5342 tmp
= CONST_VECTOR_ELT (op
, elt
);
5343 if (GET_MODE (op
) == V4SFmode
5344 || GET_MODE (op
) == V2SFmode
)
5345 tmp
= gen_lowpart (SImode
, tmp
);
5346 return INTVAL (tmp
);
5349 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5350 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5351 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5352 all items are set to the same value and contain COPIES replicas of the
5353 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5354 operand and the others are set to the value of the operand's msb. */
5357 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
5359 machine_mode mode
= GET_MODE (op
);
5360 machine_mode inner
= GET_MODE_INNER (mode
);
5368 HOST_WIDE_INT splat_val
;
5369 HOST_WIDE_INT msb_val
;
5371 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
5374 nunits
= GET_MODE_NUNITS (mode
);
5375 bitsize
= GET_MODE_BITSIZE (inner
);
5376 mask
= GET_MODE_MASK (inner
);
5378 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5380 msb_val
= val
>= 0 ? 0 : -1;
5382 /* Construct the value to be splatted, if possible. If not, return 0. */
5383 for (i
= 2; i
<= copies
; i
*= 2)
5385 HOST_WIDE_INT small_val
;
5387 small_val
= splat_val
>> bitsize
;
5389 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
5391 splat_val
= small_val
;
5394 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5395 if (EASY_VECTOR_15 (splat_val
))
5398 /* Also check if we can splat, and then add the result to itself. Do so if
5399 the value is positive, of if the splat instruction is using OP's mode;
5400 for splat_val < 0, the splat and the add should use the same mode. */
5401 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5402 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5405 /* Also check if are loading up the most significant bit which can be done by
5406 loading up -1 and shifting the value left by -1. */
5407 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5413 /* Check if VAL is present in every STEP-th element, and the
5414 other elements are filled with its most significant bit. */
5415 for (i
= 1; i
< nunits
; ++i
)
5417 HOST_WIDE_INT desired_val
;
5418 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5419 if ((i
& (step
- 1)) == 0)
5422 desired_val
= msb_val
;
5424 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5432 /* Return true if OP is of the given MODE and can be synthesized
5433 with a vspltisb, vspltish or vspltisw. */
5436 easy_altivec_constant (rtx op
, machine_mode mode
)
5438 unsigned step
, copies
;
5440 if (mode
== VOIDmode
)
5441 mode
= GET_MODE (op
);
5442 else if (mode
!= GET_MODE (op
))
5445 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5447 if (mode
== V2DFmode
)
5448 return zero_constant (op
, mode
);
5450 else if (mode
== V2DImode
)
5452 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5453 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5456 if (zero_constant (op
, mode
))
5459 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5460 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5466 /* V1TImode is a special container for TImode. Ignore for now. */
5467 else if (mode
== V1TImode
)
5470 /* Start with a vspltisw. */
5471 step
= GET_MODE_NUNITS (mode
) / 4;
5474 if (vspltis_constant (op
, step
, copies
))
5477 /* Then try with a vspltish. */
5483 if (vspltis_constant (op
, step
, copies
))
5486 /* And finally a vspltisb. */
5492 if (vspltis_constant (op
, step
, copies
))
5498 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5499 result is OP. Abort if it is not possible. */
5502 gen_easy_altivec_constant (rtx op
)
5504 machine_mode mode
= GET_MODE (op
);
5505 int nunits
= GET_MODE_NUNITS (mode
);
5506 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5507 unsigned step
= nunits
/ 4;
5508 unsigned copies
= 1;
5510 /* Start with a vspltisw. */
5511 if (vspltis_constant (op
, step
, copies
))
5512 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5514 /* Then try with a vspltish. */
5520 if (vspltis_constant (op
, step
, copies
))
5521 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5523 /* And finally a vspltisb. */
5529 if (vspltis_constant (op
, step
, copies
))
5530 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5536 output_vec_const_move (rtx
*operands
)
5544 mode
= GET_MODE (dest
);
5548 if (zero_constant (vec
, mode
))
5549 return "xxlxor %x0,%x0,%x0";
5551 if ((mode
== V2DImode
|| mode
== V1TImode
)
5552 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5553 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5554 return "vspltisw %0,-1";
5560 if (zero_constant (vec
, mode
))
5561 return "vxor %0,%0,%0";
5563 splat_vec
= gen_easy_altivec_constant (vec
);
5564 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5565 operands
[1] = XEXP (splat_vec
, 0);
5566 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5569 switch (GET_MODE (splat_vec
))
5572 return "vspltisw %0,%1";
5575 return "vspltish %0,%1";
5578 return "vspltisb %0,%1";
5585 gcc_assert (TARGET_SPE
);
5587 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5588 pattern of V1DI, V4HI, and V2SF.
5590 FIXME: We should probably return # and add post reload
5591 splitters for these, but this way is so easy ;-). */
5592 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5593 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5594 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5595 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5597 return "li %0,%1\n\tevmergelo %0,%0,%0";
5598 else if (WORDS_BIG_ENDIAN
)
5599 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5601 return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1";
5604 /* Initialize TARGET of vector PAIRED to VALS. */
5607 paired_expand_vector_init (rtx target
, rtx vals
)
5609 machine_mode mode
= GET_MODE (target
);
5610 int n_elts
= GET_MODE_NUNITS (mode
);
5612 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5615 for (i
= 0; i
< n_elts
; ++i
)
5617 x
= XVECEXP (vals
, 0, i
);
5618 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
5623 /* Load from constant pool. */
5624 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5630 /* The vector is initialized only with non-constants. */
5631 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5632 XVECEXP (vals
, 0, 1));
5634 emit_move_insn (target
, new_rtx
);
5638 /* One field is non-constant and the other one is a constant. Load the
5639 constant from the constant pool and use ps_merge instruction to
5640 construct the whole vector. */
5641 op1
= XVECEXP (vals
, 0, 0);
5642 op2
= XVECEXP (vals
, 0, 1);
5644 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5646 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5647 emit_move_insn (tmp
, constant_op
);
5649 if (CONSTANT_P (op1
))
5650 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5652 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5654 emit_move_insn (target
, new_rtx
);
5658 paired_expand_vector_move (rtx operands
[])
5660 rtx op0
= operands
[0], op1
= operands
[1];
5662 emit_move_insn (op0
, op1
);
5665 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5666 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5667 operands for the relation operation COND. This is a recursive
5671 paired_emit_vector_compare (enum rtx_code rcode
,
5672 rtx dest
, rtx op0
, rtx op1
,
5673 rtx cc_op0
, rtx cc_op1
)
5675 rtx tmp
= gen_reg_rtx (V2SFmode
);
5678 gcc_assert (TARGET_PAIRED_FLOAT
);
5679 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5685 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5689 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5690 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5694 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5697 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5700 tmp1
= gen_reg_rtx (V2SFmode
);
5701 max
= gen_reg_rtx (V2SFmode
);
5702 min
= gen_reg_rtx (V2SFmode
);
5703 gen_reg_rtx (V2SFmode
);
5705 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5706 emit_insn (gen_selv2sf4
5707 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5708 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5709 emit_insn (gen_selv2sf4
5710 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5711 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5712 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5715 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5718 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5721 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5724 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5727 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5736 /* Emit vector conditional expression.
5737 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5738 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5741 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5742 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5744 enum rtx_code rcode
= GET_CODE (cond
);
5746 if (!TARGET_PAIRED_FLOAT
)
5749 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5754 /* Initialize vector TARGET to VALS. */
5757 rs6000_expand_vector_init (rtx target
, rtx vals
)
5759 machine_mode mode
= GET_MODE (target
);
5760 machine_mode inner_mode
= GET_MODE_INNER (mode
);
5761 int n_elts
= GET_MODE_NUNITS (mode
);
5762 int n_var
= 0, one_var
= -1;
5763 bool all_same
= true, all_const_zero
= true;
5767 for (i
= 0; i
< n_elts
; ++i
)
5769 x
= XVECEXP (vals
, 0, i
);
5770 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
5771 ++n_var
, one_var
= i
;
5772 else if (x
!= CONST0_RTX (inner_mode
))
5773 all_const_zero
= false;
5775 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5781 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5782 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5783 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5785 /* Zero register. */
5786 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (mode
, target
, target
)));
5789 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5791 /* Splat immediate. */
5792 emit_insn (gen_rtx_SET (target
, const_vec
));
5797 /* Load from constant pool. */
5798 emit_move_insn (target
, const_vec
);
5803 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5804 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5806 rtx op0
= XVECEXP (vals
, 0, 0);
5807 rtx op1
= XVECEXP (vals
, 0, 1);
5810 if (!MEM_P (op0
) && !REG_P (op0
))
5811 op0
= force_reg (inner_mode
, op0
);
5812 if (mode
== V2DFmode
)
5813 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5815 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5819 op0
= force_reg (inner_mode
, op0
);
5820 op1
= force_reg (inner_mode
, op1
);
5821 if (mode
== V2DFmode
)
5822 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5824 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5829 /* With single precision floating point on VSX, know that internally single
5830 precision is actually represented as a double, and either make 2 V2DF
5831 vectors, and convert these vectors to single precision, or do one
5832 conversion, and splat the result to the other elements. */
5833 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5837 rtx freg
= gen_reg_rtx (V4SFmode
);
5838 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5839 rtx cvt
= ((TARGET_XSCVDPSPN
)
5840 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5841 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5844 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
, const0_rtx
));
5848 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5849 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5850 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5851 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5852 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5853 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5854 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5855 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5857 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5858 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5859 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5860 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5861 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5866 /* Store value to stack temp. Load vector element. Splat. However, splat
5867 of 64-bit items is not supported on Altivec. */
5868 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5870 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5871 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5872 XVECEXP (vals
, 0, 0));
5873 x
= gen_rtx_UNSPEC (VOIDmode
,
5874 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5875 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5877 gen_rtx_SET (target
, mem
),
5879 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5880 gen_rtx_PARALLEL (VOIDmode
,
5881 gen_rtvec (1, const0_rtx
)));
5882 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
5886 /* One field is non-constant. Load constant then overwrite
5890 rtx copy
= copy_rtx (vals
);
5892 /* Load constant part of vector, substitute neighboring value for
5894 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5895 rs6000_expand_vector_init (target
, copy
);
5897 /* Insert variable. */
5898 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5902 /* Construct the vector in memory one field at a time
5903 and load the whole vector. */
5904 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5905 for (i
= 0; i
< n_elts
; i
++)
5906 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5907 i
* GET_MODE_SIZE (inner_mode
)),
5908 XVECEXP (vals
, 0, i
));
5909 emit_move_insn (target
, mem
);
5912 /* Set field ELT of TARGET to VAL. */
5915 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5917 machine_mode mode
= GET_MODE (target
);
5918 machine_mode inner_mode
= GET_MODE_INNER (mode
);
5919 rtx reg
= gen_reg_rtx (mode
);
5921 int width
= GET_MODE_SIZE (inner_mode
);
5924 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5926 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5927 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5928 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5932 /* Simplify setting single element vectors like V1TImode. */
5933 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
5935 emit_move_insn (target
, gen_lowpart (mode
, val
));
5939 /* Load single variable value. */
5940 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5941 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5942 x
= gen_rtx_UNSPEC (VOIDmode
,
5943 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5944 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5946 gen_rtx_SET (reg
, mem
),
5949 /* Linear sequence. */
5950 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5951 for (i
= 0; i
< 16; ++i
)
5952 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5954 /* Set permute mask to insert element into target. */
5955 for (i
= 0; i
< width
; ++i
)
5956 XVECEXP (mask
, 0, elt
*width
+ i
)
5957 = GEN_INT (i
+ 0x10);
5958 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5960 if (BYTES_BIG_ENDIAN
)
5961 x
= gen_rtx_UNSPEC (mode
,
5962 gen_rtvec (3, target
, reg
,
5963 force_reg (V16QImode
, x
)),
5967 /* Invert selector. We prefer to generate VNAND on P8 so
5968 that future fusion opportunities can kick in, but must
5969 generate VNOR elsewhere. */
5970 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
5971 rtx iorx
= (TARGET_P8_VECTOR
5972 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
5973 : gen_rtx_AND (V16QImode
, notx
, notx
));
5974 rtx tmp
= gen_reg_rtx (V16QImode
);
5975 emit_insn (gen_rtx_SET (tmp
, iorx
));
5977 /* Permute with operands reversed and adjusted selector. */
5978 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5982 emit_insn (gen_rtx_SET (target
, x
));
5985 /* Extract field ELT from VEC into TARGET. */
5988 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5990 machine_mode mode
= GET_MODE (vec
);
5991 machine_mode inner_mode
= GET_MODE_INNER (mode
);
5994 if (VECTOR_MEM_VSX_P (mode
))
6001 gcc_assert (elt
== 0 && inner_mode
== TImode
);
6002 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
6005 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
6008 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
6011 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
6016 /* Allocate mode-sized buffer. */
6017 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
6019 emit_move_insn (mem
, vec
);
6021 /* Add offset to field within buffer matching vector element. */
6022 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
6024 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
6027 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
6028 implement ANDing by the mask IN. */
6030 build_mask64_2_operands (rtx in
, rtx
*out
)
6032 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
6035 gcc_assert (GET_CODE (in
) == CONST_INT
);
6040 /* Assume c initially something like 0x00fff000000fffff. The idea
6041 is to rotate the word so that the middle ^^^^^^ group of zeros
6042 is at the MS end and can be cleared with an rldicl mask. We then
6043 rotate back and clear off the MS ^^ group of zeros with a
6045 c
= ~c
; /* c == 0xff000ffffff00000 */
6046 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
6047 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
6048 c
= ~c
; /* c == 0x00fff000000fffff */
6049 c
&= -lsb
; /* c == 0x00fff00000000000 */
6050 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
6051 c
= ~c
; /* c == 0xff000fffffffffff */
6052 c
&= -lsb
; /* c == 0xff00000000000000 */
6054 while ((lsb
>>= 1) != 0)
6055 shift
++; /* shift == 44 on exit from loop */
6056 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
6057 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
6058 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
6062 /* Assume c initially something like 0xff000f0000000000. The idea
6063 is to rotate the word so that the ^^^ middle group of zeros
6064 is at the LS end and can be cleared with an rldicr mask. We then
6065 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
6067 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
6068 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
6069 c
= ~c
; /* c == 0x00fff0ffffffffff */
6070 c
&= -lsb
; /* c == 0x00fff00000000000 */
6071 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
6072 c
= ~c
; /* c == 0xff000fffffffffff */
6073 c
&= -lsb
; /* c == 0xff00000000000000 */
6075 while ((lsb
>>= 1) != 0)
6076 shift
++; /* shift == 44 on exit from loop */
6077 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
6078 m1
>>= shift
; /* m1 == 0x0000000000000fff */
6079 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
6082 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
6083 masks will be all 1's. We are guaranteed more than one transition. */
6084 out
[0] = GEN_INT (64 - shift
);
6085 out
[1] = GEN_INT (m1
);
6086 out
[2] = GEN_INT (shift
);
6087 out
[3] = GEN_INT (m2
);
6090 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
6093 invalid_e500_subreg (rtx op
, machine_mode mode
)
6095 if (TARGET_E500_DOUBLE
)
6097 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
6098 subreg:TI and reg:TF. Decimal float modes are like integer
6099 modes (only low part of each register used) for this
6101 if (GET_CODE (op
) == SUBREG
6102 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
6103 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
6104 && REG_P (SUBREG_REG (op
))
6105 && (GET_MODE (SUBREG_REG (op
)) == DFmode
6106 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
6109 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
6111 if (GET_CODE (op
) == SUBREG
6112 && (mode
== DFmode
|| mode
== TFmode
)
6113 && REG_P (SUBREG_REG (op
))
6114 && (GET_MODE (SUBREG_REG (op
)) == DImode
6115 || GET_MODE (SUBREG_REG (op
)) == TImode
6116 || GET_MODE (SUBREG_REG (op
)) == PTImode
6117 || GET_MODE (SUBREG_REG (op
)) == DDmode
6118 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
6123 && GET_CODE (op
) == SUBREG
6125 && REG_P (SUBREG_REG (op
))
6126 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
6132 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
6133 selects whether the alignment is abi mandated, optional, or
6134 both abi and optional alignment. */
6137 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
6139 if (how
!= align_opt
)
6141 if (TREE_CODE (type
) == VECTOR_TYPE
)
6143 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
6144 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
6149 else if (align
< 128)
6152 else if (TARGET_E500_DOUBLE
6153 && TREE_CODE (type
) == REAL_TYPE
6154 && TYPE_MODE (type
) == DFmode
)
6161 if (how
!= align_abi
)
6163 if (TREE_CODE (type
) == ARRAY_TYPE
6164 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
6166 if (align
< BITS_PER_WORD
)
6167 align
= BITS_PER_WORD
;
6174 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
6177 rs6000_special_adjust_field_align_p (tree field
, unsigned int computed
)
6179 if (TARGET_ALTIVEC
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6181 if (computed
!= 128)
6184 if (!warned
&& warn_psabi
)
6187 inform (input_location
,
6188 "the layout of aggregates containing vectors with"
6189 " %d-byte alignment has changed in GCC 5",
6190 computed
/ BITS_PER_UNIT
);
6193 /* In current GCC there is no special case. */
6200 /* AIX increases natural record alignment to doubleword if the first
6201 field is an FP double while the FP fields remain word aligned. */
6204 rs6000_special_round_type_align (tree type
, unsigned int computed
,
6205 unsigned int specified
)
6207 unsigned int align
= MAX (computed
, specified
);
6208 tree field
= TYPE_FIELDS (type
);
6210 /* Skip all non field decls */
6211 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
6212 field
= DECL_CHAIN (field
);
6214 if (field
!= NULL
&& field
!= type
)
6216 type
= TREE_TYPE (field
);
6217 while (TREE_CODE (type
) == ARRAY_TYPE
)
6218 type
= TREE_TYPE (type
);
6220 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
6221 align
= MAX (align
, 64);
6227 /* Darwin increases record alignment to the natural alignment of
6231 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
6232 unsigned int specified
)
6234 unsigned int align
= MAX (computed
, specified
);
6236 if (TYPE_PACKED (type
))
6239 /* Find the first field, looking down into aggregates. */
6241 tree field
= TYPE_FIELDS (type
);
6242 /* Skip all non field decls */
6243 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
6244 field
= DECL_CHAIN (field
);
6247 /* A packed field does not contribute any extra alignment. */
6248 if (DECL_PACKED (field
))
6250 type
= TREE_TYPE (field
);
6251 while (TREE_CODE (type
) == ARRAY_TYPE
)
6252 type
= TREE_TYPE (type
);
6253 } while (AGGREGATE_TYPE_P (type
));
6255 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
6256 align
= MAX (align
, TYPE_ALIGN (type
));
6261 /* Return 1 for an operand in small memory on V.4/eabi. */
6264 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
6265 machine_mode mode ATTRIBUTE_UNUSED
)
6270 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
6273 if (DEFAULT_ABI
!= ABI_V4
)
6276 /* Vector and float memory instructions have a limited offset on the
6277 SPE, so using a vector or float variable directly as an operand is
6280 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
6283 if (GET_CODE (op
) == SYMBOL_REF
)
6286 else if (GET_CODE (op
) != CONST
6287 || GET_CODE (XEXP (op
, 0)) != PLUS
6288 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
6289 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
6294 rtx sum
= XEXP (op
, 0);
6295 HOST_WIDE_INT summand
;
6297 /* We have to be careful here, because it is the referenced address
6298 that must be 32k from _SDA_BASE_, not just the symbol. */
6299 summand
= INTVAL (XEXP (sum
, 1));
6300 if (summand
< 0 || summand
> g_switch_value
)
6303 sym_ref
= XEXP (sum
, 0);
6306 return SYMBOL_REF_SMALL_P (sym_ref
);
6312 /* Return true if either operand is a general purpose register. */
6315 gpr_or_gpr_p (rtx op0
, rtx op1
)
6317 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
6318 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
6321 /* Return true if this is a move direct operation between GPR registers and
6322 floating point/VSX registers. */
6325 direct_move_p (rtx op0
, rtx op1
)
6329 if (!REG_P (op0
) || !REG_P (op1
))
6332 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
6335 regno0
= REGNO (op0
);
6336 regno1
= REGNO (op1
);
6337 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
6340 if (INT_REGNO_P (regno0
))
6341 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
6343 else if (INT_REGNO_P (regno1
))
6345 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
6348 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
6355 /* Return true if this is a load or store quad operation. This function does
6356 not handle the atomic quad memory instructions. */
6359 quad_load_store_p (rtx op0
, rtx op1
)
6363 if (!TARGET_QUAD_MEMORY
)
6366 else if (REG_P (op0
) && MEM_P (op1
))
6367 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
6368 && quad_memory_operand (op1
, GET_MODE (op1
))
6369 && !reg_overlap_mentioned_p (op0
, op1
));
6371 else if (MEM_P (op0
) && REG_P (op1
))
6372 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
6373 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
6378 if (TARGET_DEBUG_ADDR
)
6380 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
6381 ret
? "true" : "false");
6382 debug_rtx (gen_rtx_SET (op0
, op1
));
6388 /* Given an address, return a constant offset term if one exists. */
6391 address_offset (rtx op
)
6393 if (GET_CODE (op
) == PRE_INC
6394 || GET_CODE (op
) == PRE_DEC
)
6396 else if (GET_CODE (op
) == PRE_MODIFY
6397 || GET_CODE (op
) == LO_SUM
)
6400 if (GET_CODE (op
) == CONST
)
6403 if (GET_CODE (op
) == PLUS
)
6406 if (CONST_INT_P (op
))
6412 /* Return true if the MEM operand is a memory operand suitable for use
6413 with a (full width, possibly multiple) gpr load/store. On
6414 powerpc64 this means the offset must be divisible by 4.
6415 Implements 'Y' constraint.
6417 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6418 a constraint function we know the operand has satisfied a suitable
6419 memory predicate. Also accept some odd rtl generated by reload
6420 (see rs6000_legitimize_reload_address for various forms). It is
6421 important that reload rtl be accepted by appropriate constraints
6422 but not by the operand predicate.
6424 Offsetting a lo_sum should not be allowed, except where we know by
6425 alignment that a 32k boundary is not crossed, but see the ???
6426 comment in rs6000_legitimize_reload_address. Note that by
6427 "offsetting" here we mean a further offset to access parts of the
6428 MEM. It's fine to have a lo_sum where the inner address is offset
6429 from a sym, since the same sym+offset will appear in the high part
6430 of the address calculation. */
6433 mem_operand_gpr (rtx op
, machine_mode mode
)
6435 unsigned HOST_WIDE_INT offset
;
6437 rtx addr
= XEXP (op
, 0);
6439 op
= address_offset (addr
);
6443 offset
= INTVAL (op
);
6444 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6447 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6451 if (GET_CODE (addr
) == LO_SUM
)
6452 /* For lo_sum addresses, we must allow any offset except one that
6453 causes a wrap, so test only the low 16 bits. */
6454 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6456 return offset
+ 0x8000 < 0x10000u
- extra
;
6459 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6462 reg_offset_addressing_ok_p (machine_mode mode
)
6474 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6475 TImode is not a vector mode, if we want to use the VSX registers to
6476 move it around, we need to restrict ourselves to reg+reg
6478 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6486 /* Paired vector modes. Only reg+reg addressing is valid. */
6487 if (TARGET_PAIRED_FLOAT
)
6492 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6493 addressing for the LFIWZX and STFIWX instructions. */
6494 if (TARGET_NO_SDMODE_STACK
)
6506 virtual_stack_registers_memory_p (rtx op
)
6510 if (GET_CODE (op
) == REG
)
6511 regnum
= REGNO (op
);
6513 else if (GET_CODE (op
) == PLUS
6514 && GET_CODE (XEXP (op
, 0)) == REG
6515 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6516 regnum
= REGNO (XEXP (op
, 0));
6521 return (regnum
>= FIRST_VIRTUAL_REGISTER
6522 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6525 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6526 is known to not straddle a 32k boundary. This function is used
6527 to determine whether -mcmodel=medium code can use TOC pointer
6528 relative addressing for OP. This means the alignment of the TOC
6529 pointer must also be taken into account, and unfortunately that is
6532 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
6533 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
6537 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6541 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6543 if (GET_CODE (op
) != SYMBOL_REF
)
6546 dsize
= GET_MODE_SIZE (mode
);
6547 decl
= SYMBOL_REF_DECL (op
);
6553 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6554 replacing memory addresses with an anchor plus offset. We
6555 could find the decl by rummaging around in the block->objects
6556 VEC for the given offset but that seems like too much work. */
6557 dalign
= BITS_PER_UNIT
;
6558 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6559 && SYMBOL_REF_ANCHOR_P (op
)
6560 && SYMBOL_REF_BLOCK (op
) != NULL
)
6562 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6564 dalign
= block
->alignment
;
6565 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6567 else if (CONSTANT_POOL_ADDRESS_P (op
))
6569 /* It would be nice to have get_pool_align().. */
6570 machine_mode cmode
= get_pool_mode (op
);
6572 dalign
= GET_MODE_ALIGNMENT (cmode
);
6575 else if (DECL_P (decl
))
6577 dalign
= DECL_ALIGN (decl
);
6581 /* Allow BLKmode when the entire object is known to not
6582 cross a 32k boundary. */
6583 if (!DECL_SIZE_UNIT (decl
))
6586 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6589 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6593 dalign
/= BITS_PER_UNIT
;
6594 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
6595 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
6596 return dalign
>= dsize
;
6602 /* Find how many bits of the alignment we know for this access. */
6603 dalign
/= BITS_PER_UNIT
;
6604 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
6605 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
6607 lsb
= offset
& -offset
;
6611 return dalign
>= dsize
;
6615 constant_pool_expr_p (rtx op
)
6619 split_const (op
, &base
, &offset
);
6620 return (GET_CODE (base
) == SYMBOL_REF
6621 && CONSTANT_POOL_ADDRESS_P (base
)
6622 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6625 static const_rtx tocrel_base
, tocrel_offset
;
6627 /* Return true if OP is a toc pointer relative address (the output
6628 of create_TOC_reference). If STRICT, do not match high part or
6629 non-split -mcmodel=large/medium toc pointer relative addresses. */
6632 toc_relative_expr_p (const_rtx op
, bool strict
)
6637 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6639 /* Only match the low part. */
6640 if (GET_CODE (op
) == LO_SUM
6641 && REG_P (XEXP (op
, 0))
6642 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6649 tocrel_offset
= const0_rtx
;
6650 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6652 tocrel_base
= XEXP (op
, 0);
6653 tocrel_offset
= XEXP (op
, 1);
6656 return (GET_CODE (tocrel_base
) == UNSPEC
6657 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6660 /* Return true if X is a constant pool address, and also for cmodel=medium
6661 if X is a toc-relative address known to be offsettable within MODE. */
6664 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
6667 return (toc_relative_expr_p (x
, strict
)
6668 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6669 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6671 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6672 INTVAL (tocrel_offset
), mode
)));
6676 legitimate_small_data_p (machine_mode mode
, rtx x
)
6678 return (DEFAULT_ABI
== ABI_V4
6679 && !flag_pic
&& !TARGET_TOC
6680 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6681 && small_data_operand (x
, mode
));
6684 /* SPE offset addressing is limited to 5-bits worth of double words. */
6685 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6688 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
6689 bool strict
, bool worst_case
)
6691 unsigned HOST_WIDE_INT offset
;
6694 if (GET_CODE (x
) != PLUS
)
6696 if (!REG_P (XEXP (x
, 0)))
6698 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6700 if (!reg_offset_addressing_ok_p (mode
))
6701 return virtual_stack_registers_memory_p (x
);
6702 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6704 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6707 offset
= INTVAL (XEXP (x
, 1));
6715 /* SPE vector modes. */
6716 return SPE_CONST_OFFSET_OK (offset
);
6721 /* On e500v2, we may have:
6723 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6725 Which gets addressed with evldd instructions. */
6726 if (TARGET_E500_DOUBLE
)
6727 return SPE_CONST_OFFSET_OK (offset
);
6729 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6731 if (VECTOR_MEM_VSX_P (mode
))
6736 if (!TARGET_POWERPC64
)
6738 else if (offset
& 3)
6743 if (TARGET_E500_DOUBLE
)
6744 return (SPE_CONST_OFFSET_OK (offset
)
6745 && SPE_CONST_OFFSET_OK (offset
+ 8));
6754 if (!TARGET_POWERPC64
)
6756 else if (offset
& 3)
6765 return offset
< 0x10000 - extra
;
6769 legitimate_indexed_address_p (rtx x
, int strict
)
6773 if (GET_CODE (x
) != PLUS
)
6779 /* Recognize the rtl generated by reload which we know will later be
6780 replaced with proper base and index regs. */
6782 && reload_in_progress
6783 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6787 return (REG_P (op0
) && REG_P (op1
)
6788 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6789 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6790 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6791 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6795 avoiding_indexed_address_p (machine_mode mode
)
6797 /* Avoid indexed addressing for modes that have non-indexed
6798 load/store instruction forms. */
6799 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6803 legitimate_indirect_address_p (rtx x
, int strict
)
6805 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6809 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
6811 if (!TARGET_MACHO
|| !flag_pic
6812 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6816 if (GET_CODE (x
) != LO_SUM
)
6818 if (GET_CODE (XEXP (x
, 0)) != REG
)
6820 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6824 return CONSTANT_P (x
);
6828 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
6830 if (GET_CODE (x
) != LO_SUM
)
6832 if (GET_CODE (XEXP (x
, 0)) != REG
)
6834 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6836 /* Restrict addressing for DI because of our SUBREG hackery. */
6837 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6841 if (TARGET_ELF
|| TARGET_MACHO
)
6845 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6847 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6848 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6849 recognizes some LO_SUM addresses as valid although this
6850 function says opposite. In most cases, LRA through different
6851 transformations can generate correct code for address reloads.
6852 It can not manage only some LO_SUM cases. So we need to add
6853 code analogous to one in rs6000_legitimize_reload_address for
6854 LOW_SUM here saying that some addresses are still valid. */
6855 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6856 && small_toc_ref (x
, VOIDmode
));
6857 if (TARGET_TOC
&& ! large_toc_ok
)
6859 if (GET_MODE_NUNITS (mode
) != 1)
6861 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6862 && !(/* ??? Assume floating point reg based on mode? */
6863 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6864 && (mode
== DFmode
|| mode
== DDmode
)))
6867 return CONSTANT_P (x
) || large_toc_ok
;
6874 /* Try machine-dependent ways of modifying an illegitimate address
6875 to be legitimate. If we find one, return the new, valid address.
6876 This is used from only one place: `memory_address' in explow.c.
6878 OLDX is the address as it was before break_out_memory_refs was
6879 called. In some cases it is useful to look at this to decide what
6882 It is always safe for this function to do nothing. It exists to
6883 recognize opportunities to optimize the output.
6885 On RS/6000, first check for the sum of a register with a constant
6886 integer that is out of range. If so, generate code to add the
6887 constant with the low-order 16 bits masked to the register and force
6888 this result into another register (this can be done with `cau').
6889 Then generate an address of REG+(CONST&0xffff), allowing for the
6890 possibility of bit 16 being a one.
6892 Then check for the sum of a register and something not constant, try to
6893 load the other things into a register and return the sum. */
6896 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6901 if (!reg_offset_addressing_ok_p (mode
))
6903 if (virtual_stack_registers_memory_p (x
))
6906 /* In theory we should not be seeing addresses of the form reg+0,
6907 but just in case it is generated, optimize it away. */
6908 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6909 return force_reg (Pmode
, XEXP (x
, 0));
6911 /* For TImode with load/store quad, restrict addresses to just a single
6912 pointer, so it works with both GPRs and VSX registers. */
6913 /* Make sure both operands are registers. */
6914 else if (GET_CODE (x
) == PLUS
6915 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6916 return gen_rtx_PLUS (Pmode
,
6917 force_reg (Pmode
, XEXP (x
, 0)),
6918 force_reg (Pmode
, XEXP (x
, 1)));
6920 return force_reg (Pmode
, x
);
6922 if (GET_CODE (x
) == SYMBOL_REF
)
6924 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6926 return rs6000_legitimize_tls_address (x
, model
);
6936 /* As in legitimate_offset_address_p we do not assume
6937 worst-case. The mode here is just a hint as to the registers
6938 used. A TImode is usually in gprs, but may actually be in
6939 fprs. Leave worst-case scenario for reload to handle via
6940 insn constraints. PTImode is only GPRs. */
6947 if (GET_CODE (x
) == PLUS
6948 && GET_CODE (XEXP (x
, 0)) == REG
6949 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6950 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6952 && !(SPE_VECTOR_MODE (mode
)
6953 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6955 HOST_WIDE_INT high_int
, low_int
;
6957 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6958 if (low_int
>= 0x8000 - extra
)
6960 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6961 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6962 GEN_INT (high_int
)), 0);
6963 return plus_constant (Pmode
, sum
, low_int
);
6965 else if (GET_CODE (x
) == PLUS
6966 && GET_CODE (XEXP (x
, 0)) == REG
6967 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6968 && GET_MODE_NUNITS (mode
) == 1
6969 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6970 || (/* ??? Assume floating point reg based on mode? */
6971 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6972 && (mode
== DFmode
|| mode
== DDmode
)))
6973 && !avoiding_indexed_address_p (mode
))
6975 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6976 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6978 else if (SPE_VECTOR_MODE (mode
)
6979 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6983 /* We accept [reg + reg] and [reg + OFFSET]. */
6985 if (GET_CODE (x
) == PLUS
)
6987 rtx op1
= XEXP (x
, 0);
6988 rtx op2
= XEXP (x
, 1);
6991 op1
= force_reg (Pmode
, op1
);
6993 if (GET_CODE (op2
) != REG
6994 && (GET_CODE (op2
) != CONST_INT
6995 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6996 || (GET_MODE_SIZE (mode
) > 8
6997 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6998 op2
= force_reg (Pmode
, op2
);
7000 /* We can't always do [reg + reg] for these, because [reg +
7001 reg + offset] is not a legitimate addressing mode. */
7002 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
7004 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
7005 return force_reg (Pmode
, y
);
7010 return force_reg (Pmode
, x
);
7012 else if ((TARGET_ELF
7014 || !MACHO_DYNAMIC_NO_PIC_P
7020 && GET_CODE (x
) != CONST_INT
7021 && GET_CODE (x
) != CONST_WIDE_INT
7022 && GET_CODE (x
) != CONST_DOUBLE
7024 && GET_MODE_NUNITS (mode
) == 1
7025 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
7026 || (/* ??? Assume floating point reg based on mode? */
7027 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7028 && (mode
== DFmode
|| mode
== DDmode
))))
7030 rtx reg
= gen_reg_rtx (Pmode
);
7032 emit_insn (gen_elf_high (reg
, x
));
7034 emit_insn (gen_macho_high (reg
, x
));
7035 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
7038 && GET_CODE (x
) == SYMBOL_REF
7039 && constant_pool_expr_p (x
)
7040 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
7041 return create_TOC_reference (x
, NULL_RTX
);
7046 /* Debug version of rs6000_legitimize_address. */
7048 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
7054 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
7055 insns
= get_insns ();
7061 "\nrs6000_legitimize_address: mode %s, old code %s, "
7062 "new code %s, modified\n",
7063 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
7064 GET_RTX_NAME (GET_CODE (ret
)));
7066 fprintf (stderr
, "Original address:\n");
7069 fprintf (stderr
, "oldx:\n");
7072 fprintf (stderr
, "New address:\n");
7077 fprintf (stderr
, "Insns added:\n");
7078 debug_rtx_list (insns
, 20);
7084 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
7085 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
7096 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7097 We need to emit DTP-relative relocations. */
7099 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
7101 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7106 fputs ("\t.long\t", file
);
7109 fputs (DOUBLE_INT_ASM_OP
, file
);
7114 output_addr_const (file
, x
);
7115 fputs ("@dtprel+0x8000", file
);
7118 /* Return true if X is a symbol that refers to real (rather than emulated)
7122 rs6000_real_tls_symbol_ref_p (rtx x
)
7124 return (GET_CODE (x
) == SYMBOL_REF
7125 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
7128 /* In the name of slightly smaller debug output, and to cater to
7129 general assembler lossage, recognize various UNSPEC sequences
7130 and turn them back into a direct symbol reference. */
7133 rs6000_delegitimize_address (rtx orig_x
)
7137 orig_x
= delegitimize_mem_from_attrs (orig_x
);
7143 if (TARGET_CMODEL
!= CMODEL_SMALL
7144 && GET_CODE (y
) == LO_SUM
)
7148 if (GET_CODE (y
) == PLUS
7149 && GET_MODE (y
) == Pmode
7150 && CONST_INT_P (XEXP (y
, 1)))
7152 offset
= XEXP (y
, 1);
7156 if (GET_CODE (y
) == UNSPEC
7157 && XINT (y
, 1) == UNSPEC_TOCREL
)
7159 y
= XVECEXP (y
, 0, 0);
7162 /* Do not associate thread-local symbols with the original
7163 constant pool symbol. */
7165 && GET_CODE (y
) == SYMBOL_REF
7166 && CONSTANT_POOL_ADDRESS_P (y
)
7167 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
7171 if (offset
!= NULL_RTX
)
7172 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
7173 if (!MEM_P (orig_x
))
7176 return replace_equiv_address_nv (orig_x
, y
);
7180 && GET_CODE (orig_x
) == LO_SUM
7181 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
7183 y
= XEXP (XEXP (orig_x
, 1), 0);
7184 if (GET_CODE (y
) == UNSPEC
7185 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
7186 return XVECEXP (y
, 0, 0);
7192 /* Return true if X shouldn't be emitted into the debug info.
7193 The linker doesn't like .toc section references from
7194 .debug_* sections, so reject .toc section symbols. */
7197 rs6000_const_not_ok_for_debug_p (rtx x
)
7199 if (GET_CODE (x
) == SYMBOL_REF
7200 && CONSTANT_POOL_ADDRESS_P (x
))
7202 rtx c
= get_pool_constant (x
);
7203 machine_mode cmode
= get_pool_mode (x
);
7204 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
7211 /* Construct the SYMBOL_REF for the tls_get_addr function. */
7213 static GTY(()) rtx rs6000_tls_symbol
;
7215 rs6000_tls_get_addr (void)
7217 if (!rs6000_tls_symbol
)
7218 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
7220 return rs6000_tls_symbol
;
7223 /* Construct the SYMBOL_REF for TLS GOT references. */
7225 static GTY(()) rtx rs6000_got_symbol
;
7227 rs6000_got_sym (void)
7229 if (!rs6000_got_symbol
)
7231 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7232 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
7233 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
7236 return rs6000_got_symbol
;
7239 /* AIX Thread-Local Address support. */
7242 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
7244 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
7248 name
= XSTR (addr
, 0);
7249 /* Append TLS CSECT qualifier, unless the symbol already is qualified
7250 or the symbol will be in TLS private data section. */
7251 if (name
[strlen (name
) - 1] != ']'
7252 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
7253 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
7255 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
7256 strcpy (tlsname
, name
);
7258 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
7259 tlsaddr
= copy_rtx (addr
);
7260 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
7265 /* Place addr into TOC constant pool. */
7266 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
7268 /* Output the TOC entry and create the MEM referencing the value. */
7269 if (constant_pool_expr_p (XEXP (sym
, 0))
7270 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
7272 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
7273 mem
= gen_const_mem (Pmode
, tocref
);
7274 set_mem_alias_set (mem
, get_TOC_alias_set ());
7279 /* Use global-dynamic for local-dynamic. */
7280 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
7281 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
7283 /* Create new TOC reference for @m symbol. */
7284 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
7285 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
7286 strcpy (tlsname
, "*LCM");
7287 strcat (tlsname
, name
+ 3);
7288 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
7289 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
7290 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
7291 rtx modmem
= gen_const_mem (Pmode
, tocref
);
7292 set_mem_alias_set (modmem
, get_TOC_alias_set ());
7294 rtx modreg
= gen_reg_rtx (Pmode
);
7295 emit_insn (gen_rtx_SET (modreg
, modmem
));
7297 tmpreg
= gen_reg_rtx (Pmode
);
7298 emit_insn (gen_rtx_SET (tmpreg
, mem
));
7300 dest
= gen_reg_rtx (Pmode
);
7302 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
7304 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
7307 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
7308 else if (TARGET_32BIT
)
7310 tlsreg
= gen_reg_rtx (SImode
);
7311 emit_insn (gen_tls_get_tpointer (tlsreg
));
7314 tlsreg
= gen_rtx_REG (DImode
, 13);
7316 /* Load the TOC value into temporary register. */
7317 tmpreg
= gen_reg_rtx (Pmode
);
7318 emit_insn (gen_rtx_SET (tmpreg
, mem
));
7319 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
7320 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
7322 /* Add TOC symbol value to TLS pointer. */
7323 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
7328 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
7329 this (thread-local) address. */
7332 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
7337 return rs6000_legitimize_tls_address_aix (addr
, model
);
7339 dest
= gen_reg_rtx (Pmode
);
7340 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
7346 tlsreg
= gen_rtx_REG (Pmode
, 13);
7347 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
7351 tlsreg
= gen_rtx_REG (Pmode
, 2);
7352 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
7356 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
7360 tmp
= gen_reg_rtx (Pmode
);
7363 tlsreg
= gen_rtx_REG (Pmode
, 13);
7364 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
7368 tlsreg
= gen_rtx_REG (Pmode
, 2);
7369 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
7373 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
7375 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
7380 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
7382 /* We currently use relocations like @got@tlsgd for tls, which
7383 means the linker will handle allocation of tls entries, placing
7384 them in the .got section. So use a pointer to the .got section,
7385 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7386 or to secondary GOT sections used by 32-bit -fPIC. */
7388 got
= gen_rtx_REG (Pmode
, 2);
7392 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
7395 rtx gsym
= rs6000_got_sym ();
7396 got
= gen_reg_rtx (Pmode
);
7398 rs6000_emit_move (got
, gsym
, Pmode
);
7403 tmp1
= gen_reg_rtx (Pmode
);
7404 tmp2
= gen_reg_rtx (Pmode
);
7405 mem
= gen_const_mem (Pmode
, tmp1
);
7406 lab
= gen_label_rtx ();
7407 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
7408 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
7409 if (TARGET_LINK_STACK
)
7410 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
7411 emit_move_insn (tmp2
, mem
);
7412 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7413 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7418 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7420 tga
= rs6000_tls_get_addr ();
7421 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7422 1, const0_rtx
, Pmode
);
7424 r3
= gen_rtx_REG (Pmode
, 3);
7425 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7428 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7430 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7432 else if (DEFAULT_ABI
== ABI_V4
)
7433 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7436 call_insn
= last_call_insn ();
7437 PATTERN (call_insn
) = insn
;
7438 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7439 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7440 pic_offset_table_rtx
);
7442 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7444 tga
= rs6000_tls_get_addr ();
7445 tmp1
= gen_reg_rtx (Pmode
);
7446 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7447 1, const0_rtx
, Pmode
);
7449 r3
= gen_rtx_REG (Pmode
, 3);
7450 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7453 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7455 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7457 else if (DEFAULT_ABI
== ABI_V4
)
7458 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7461 call_insn
= last_call_insn ();
7462 PATTERN (call_insn
) = insn
;
7463 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7464 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7465 pic_offset_table_rtx
);
7467 if (rs6000_tls_size
== 16)
7470 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7472 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7474 else if (rs6000_tls_size
== 32)
7476 tmp2
= gen_reg_rtx (Pmode
);
7478 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7480 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7483 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7485 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7489 tmp2
= gen_reg_rtx (Pmode
);
7491 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7493 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7495 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7501 /* IE, or 64-bit offset LE. */
7502 tmp2
= gen_reg_rtx (Pmode
);
7504 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7506 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7509 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7511 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7519 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7522 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7524 if (GET_CODE (x
) == HIGH
7525 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7528 /* A TLS symbol in the TOC cannot contain a sum. */
7529 if (GET_CODE (x
) == CONST
7530 && GET_CODE (XEXP (x
, 0)) == PLUS
7531 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7532 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7535 /* Do not place an ELF TLS symbol in the constant pool. */
7536 return TARGET_ELF
&& tls_referenced_p (x
);
7539 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7540 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7541 can be addressed relative to the toc pointer. */
7544 use_toc_relative_ref (rtx sym
, machine_mode mode
)
7546 return ((constant_pool_expr_p (sym
)
7547 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7548 get_pool_mode (sym
)))
7549 || (TARGET_CMODEL
== CMODEL_MEDIUM
7550 && SYMBOL_REF_LOCAL_P (sym
)
7551 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
7554 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7555 replace the input X, or the original X if no replacement is called for.
7556 The output parameter *WIN is 1 if the calling macro should goto WIN,
7559 For RS/6000, we wish to handle large displacements off a base
7560 register by splitting the addend across an addiu/addis and the mem insn.
7561 This cuts number of extra insns needed from 3 to 1.
7563 On Darwin, we use this to generate code for floating point constants.
7564 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7565 The Darwin code is inside #if TARGET_MACHO because only then are the
7566 machopic_* functions defined. */
7568 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
7569 int opnum
, int type
,
7570 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7572 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7574 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7575 DFmode/DImode MEM. */
7578 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7579 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7580 reg_offset_p
= false;
7582 /* We must recognize output that we have already generated ourselves. */
7583 if (GET_CODE (x
) == PLUS
7584 && GET_CODE (XEXP (x
, 0)) == PLUS
7585 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7586 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7587 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7589 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7590 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7591 opnum
, (enum reload_type
) type
);
7596 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7597 if (GET_CODE (x
) == LO_SUM
7598 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7600 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7601 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7602 opnum
, (enum reload_type
) type
);
7608 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7609 && GET_CODE (x
) == LO_SUM
7610 && GET_CODE (XEXP (x
, 0)) == PLUS
7611 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7612 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7613 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7614 && machopic_operand_p (XEXP (x
, 1)))
7616 /* Result of previous invocation of this function on Darwin
7617 floating point constant. */
7618 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7619 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7620 opnum
, (enum reload_type
) type
);
7626 if (TARGET_CMODEL
!= CMODEL_SMALL
7628 && small_toc_ref (x
, VOIDmode
))
7630 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7631 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7632 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7633 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7634 opnum
, (enum reload_type
) type
);
7639 if (GET_CODE (x
) == PLUS
7640 && GET_CODE (XEXP (x
, 0)) == REG
7641 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7642 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7643 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7645 && !SPE_VECTOR_MODE (mode
)
7646 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7647 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7649 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7650 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7652 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7654 /* Check for 32-bit overflow. */
7655 if (high
+ low
!= val
)
7661 /* Reload the high part into a base reg; leave the low part
7662 in the mem directly. */
7664 x
= gen_rtx_PLUS (GET_MODE (x
),
7665 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7669 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7670 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7671 opnum
, (enum reload_type
) type
);
7676 if (GET_CODE (x
) == SYMBOL_REF
7678 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7679 && !SPE_VECTOR_MODE (mode
)
7681 && DEFAULT_ABI
== ABI_DARWIN
7682 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7683 && machopic_symbol_defined_p (x
)
7685 && DEFAULT_ABI
== ABI_V4
7688 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7689 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7691 ??? Assume floating point reg based on mode? This assumption is
7692 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7693 where reload ends up doing a DFmode load of a constant from
7694 mem using two gprs. Unfortunately, at this point reload
7695 hasn't yet selected regs so poking around in reload data
7696 won't help and even if we could figure out the regs reliably,
7697 we'd still want to allow this transformation when the mem is
7698 naturally aligned. Since we say the address is good here, we
7699 can't disable offsets from LO_SUMs in mem_operand_gpr.
7700 FIXME: Allow offset from lo_sum for other modes too, when
7701 mem is sufficiently aligned.
7703 Also disallow this if the type can go in VMX/Altivec registers, since
7704 those registers do not have d-form (reg+offset) address modes. */
7705 && !reg_addr
[mode
].scalar_in_vmx_p
7708 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7710 && (mode
!= DImode
|| TARGET_POWERPC64
)
7711 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7712 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7717 rtx offset
= machopic_gen_offset (x
);
7718 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7719 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7720 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7724 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7725 gen_rtx_HIGH (Pmode
, x
), x
);
7727 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7728 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7729 opnum
, (enum reload_type
) type
);
7734 /* Reload an offset address wrapped by an AND that represents the
7735 masking of the lower bits. Strip the outer AND and let reload
7736 convert the offset address into an indirect address. For VSX,
7737 force reload to create the address with an AND in a separate
7738 register, because we can't guarantee an altivec register will
7740 if (VECTOR_MEM_ALTIVEC_P (mode
)
7741 && GET_CODE (x
) == AND
7742 && GET_CODE (XEXP (x
, 0)) == PLUS
7743 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7744 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7745 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7746 && INTVAL (XEXP (x
, 1)) == -16)
7755 && GET_CODE (x
) == SYMBOL_REF
7756 && use_toc_relative_ref (x
, mode
))
7758 x
= create_TOC_reference (x
, NULL_RTX
);
7759 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7760 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7761 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7762 opnum
, (enum reload_type
) type
);
7770 /* Debug version of rs6000_legitimize_reload_address. */
7772 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
7773 int opnum
, int type
,
7774 int ind_levels
, int *win
)
7776 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7779 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7780 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7781 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7785 fprintf (stderr
, "Same address returned\n");
7787 fprintf (stderr
, "NULL returned\n");
7790 fprintf (stderr
, "New address:\n");
7797 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7798 that is a valid memory address for an instruction.
7799 The MODE argument is the machine mode for the MEM expression
7800 that wants to use this address.
7802 On the RS/6000, there are four valid address: a SYMBOL_REF that
7803 refers to a constant pool entry of an address (or the sum of it
7804 plus a constant), a short (16-bit signed) constant plus a register,
7805 the sum of two registers, or a register indirect, possibly with an
7806 auto-increment. For DFmode, DDmode and DImode with a constant plus
7807 register, we must ensure that both words are addressable or PowerPC64
7808 with offset word aligned.
7810 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7811 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7812 because adjacent memory cells are accessed by adding word-sized offsets
7813 during assembly output. */
7815 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
7817 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7819 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7820 if (VECTOR_MEM_ALTIVEC_P (mode
)
7821 && GET_CODE (x
) == AND
7822 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7823 && INTVAL (XEXP (x
, 1)) == -16)
7826 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7828 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7831 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7832 && mode_supports_pre_incdec_p (mode
)
7833 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7835 if (virtual_stack_registers_memory_p (x
))
7837 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7840 && legitimate_constant_pool_address_p (x
, mode
,
7841 reg_ok_strict
|| lra_in_progress
))
7843 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7844 allow register indirect addresses. This will allow the values to go in
7845 either GPRs or VSX registers without reloading. The vector types would
7846 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7847 somewhat split, in that some uses are GPR based, and some VSX based. */
7848 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7850 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7853 && GET_CODE (x
) == PLUS
7854 && GET_CODE (XEXP (x
, 0)) == REG
7855 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7856 || XEXP (x
, 0) == arg_pointer_rtx
)
7857 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7859 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7863 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7865 || (mode
!= DFmode
&& mode
!= DDmode
)
7866 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7867 && (TARGET_POWERPC64
|| mode
!= DImode
)
7868 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7870 && !avoiding_indexed_address_p (mode
)
7871 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7873 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7874 && mode_supports_pre_modify_p (mode
)
7875 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7876 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7877 reg_ok_strict
, false)
7878 || (!avoiding_indexed_address_p (mode
)
7879 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7880 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7882 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7887 /* Debug version of rs6000_legitimate_address_p. */
7889 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
7892 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7894 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7895 "strict = %d, reload = %s, code = %s\n",
7896 ret
? "true" : "false",
7897 GET_MODE_NAME (mode
),
7901 : (reload_in_progress
? "progress" : "before")),
7902 GET_RTX_NAME (GET_CODE (x
)));
7908 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7911 rs6000_mode_dependent_address_p (const_rtx addr
,
7912 addr_space_t as ATTRIBUTE_UNUSED
)
7914 return rs6000_mode_dependent_address_ptr (addr
);
7917 /* Go to LABEL if ADDR (a legitimate address expression)
7918 has an effect that depends on the machine mode it is used for.
7920 On the RS/6000 this is true of all integral offsets (since AltiVec
7921 and VSX modes don't allow them) or is a pre-increment or decrement.
7923 ??? Except that due to conceptual problems in offsettable_address_p
7924 we can't really report the problems of integral offsets. So leave
7925 this assuming that the adjustable offset must be valid for the
7926 sub-words of a TFmode operand, which is what we had before. */
7929 rs6000_mode_dependent_address (const_rtx addr
)
7931 switch (GET_CODE (addr
))
7934 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7935 is considered a legitimate address before reload, so there
7936 are no offset restrictions in that case. Note that this
7937 condition is safe in strict mode because any address involving
7938 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7939 been rejected as illegitimate. */
7940 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7941 && XEXP (addr
, 0) != arg_pointer_rtx
7942 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7944 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7945 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7950 /* Anything in the constant pool is sufficiently aligned that
7951 all bytes have the same high part address. */
7952 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7954 /* Auto-increment cases are now treated generically in recog.c. */
7956 return TARGET_UPDATE
;
7958 /* AND is only allowed in Altivec loads. */
7969 /* Debug version of rs6000_mode_dependent_address. */
7971 rs6000_debug_mode_dependent_address (const_rtx addr
)
7973 bool ret
= rs6000_mode_dependent_address (addr
);
7975 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7976 ret
? "true" : "false");
7982 /* Implement FIND_BASE_TERM. */
7985 rs6000_find_base_term (rtx op
)
7990 if (GET_CODE (base
) == CONST
)
7991 base
= XEXP (base
, 0);
7992 if (GET_CODE (base
) == PLUS
)
7993 base
= XEXP (base
, 0);
7994 if (GET_CODE (base
) == UNSPEC
)
7995 switch (XINT (base
, 1))
7998 case UNSPEC_MACHOPIC_OFFSET
:
7999 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
8000 for aliasing purposes. */
8001 return XVECEXP (base
, 0, 0);
8007 /* More elaborate version of recog's offsettable_memref_p predicate
8008 that works around the ??? note of rs6000_mode_dependent_address.
8009 In particular it accepts
8011 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
8013 in 32-bit mode, that the recog predicate rejects. */
8016 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
)
8023 /* First mimic offsettable_memref_p. */
8024 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
8027 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
8028 the latter predicate knows nothing about the mode of the memory
8029 reference and, therefore, assumes that it is the largest supported
8030 mode (TFmode). As a consequence, legitimate offsettable memory
8031 references are rejected. rs6000_legitimate_offset_address_p contains
8032 the correct logic for the PLUS case of rs6000_mode_dependent_address,
8033 at least with a little bit of help here given that we know the
8034 actual registers used. */
8035 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
8036 || GET_MODE_SIZE (reg_mode
) == 4);
8037 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
8041 /* Change register usage conditional on target flags. */
8043 rs6000_conditional_register_usage (void)
8047 if (TARGET_DEBUG_TARGET
)
8048 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
8050 /* Set MQ register fixed (already call_used) so that it will not be
8054 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
8056 fixed_regs
[13] = call_used_regs
[13]
8057 = call_really_used_regs
[13] = 1;
8059 /* Conditionally disable FPRs. */
8060 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
8061 for (i
= 32; i
< 64; i
++)
8062 fixed_regs
[i
] = call_used_regs
[i
]
8063 = call_really_used_regs
[i
] = 1;
8065 /* The TOC register is not killed across calls in a way that is
8066 visible to the compiler. */
8067 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
8068 call_really_used_regs
[2] = 0;
8070 if (DEFAULT_ABI
== ABI_V4
8071 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
8073 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8075 if (DEFAULT_ABI
== ABI_V4
8076 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
8078 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8079 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8080 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8082 if (DEFAULT_ABI
== ABI_DARWIN
8083 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
8084 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8085 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8086 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8088 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
8089 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
8090 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
8094 global_regs
[SPEFSCR_REGNO
] = 1;
8095 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
8096 registers in prologues and epilogues. We no longer use r14
8097 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
8098 pool for link-compatibility with older versions of GCC. Once
8099 "old" code has died out, we can return r14 to the allocation
8102 = call_used_regs
[14]
8103 = call_really_used_regs
[14] = 1;
8106 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
8108 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
8109 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8110 call_really_used_regs
[VRSAVE_REGNO
] = 1;
8113 if (TARGET_ALTIVEC
|| TARGET_VSX
)
8114 global_regs
[VSCR_REGNO
] = 1;
8116 if (TARGET_ALTIVEC_ABI
)
8118 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
8119 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8121 /* AIX reserves VR20:31 in non-extended ABI mode. */
8123 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
8124 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
8129 /* Output insns to set DEST equal to the constant SOURCE as a series of
8130 lis, ori and shl instructions and return TRUE. */
8133 rs6000_emit_set_const (rtx dest
, rtx source
)
8135 machine_mode mode
= GET_MODE (dest
);
8140 gcc_checking_assert (CONST_INT_P (source
));
8141 c
= INTVAL (source
);
8146 emit_insn (gen_rtx_SET (dest
, source
));
8150 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
8152 emit_insn (gen_rtx_SET (copy_rtx (temp
),
8153 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
8154 emit_insn (gen_rtx_SET (dest
,
8155 gen_rtx_IOR (SImode
, copy_rtx (temp
),
8156 GEN_INT (c
& 0xffff))));
8160 if (!TARGET_POWERPC64
)
8164 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
8166 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
8168 emit_move_insn (hi
, GEN_INT (c
>> 32));
8169 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
8170 emit_move_insn (lo
, GEN_INT (c
));
8173 rs6000_emit_set_long_const (dest
, c
);
8180 insn
= get_last_insn ();
8181 set
= single_set (insn
);
8182 if (! CONSTANT_P (SET_SRC (set
)))
8183 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
8188 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
8189 Output insns to set DEST equal to the constant C as a series of
8190 lis, ori and shl instructions. */
8193 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
8196 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
8206 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
8207 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
8208 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
8210 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
8211 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
8213 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8215 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8216 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
8218 emit_move_insn (dest
,
8219 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8222 else if (ud3
== 0 && ud4
== 0)
8224 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8226 gcc_assert (ud2
& 0x8000);
8227 emit_move_insn (copy_rtx (temp
),
8228 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
8230 emit_move_insn (copy_rtx (temp
),
8231 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8233 emit_move_insn (dest
,
8234 gen_rtx_ZERO_EXTEND (DImode
,
8235 gen_lowpart (SImode
,
8238 else if ((ud4
== 0xffff && (ud3
& 0x8000))
8239 || (ud4
== 0 && ! (ud3
& 0x8000)))
8241 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8243 emit_move_insn (copy_rtx (temp
),
8244 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
8246 emit_move_insn (copy_rtx (temp
),
8247 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8249 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8250 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8253 emit_move_insn (dest
,
8254 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8259 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
8261 emit_move_insn (copy_rtx (temp
),
8262 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
8264 emit_move_insn (copy_rtx (temp
),
8265 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8268 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
8269 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
8272 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
8273 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8274 GEN_INT (ud2
<< 16)));
8276 emit_move_insn (dest
,
8277 gen_rtx_IOR (DImode
, copy_rtx (temp
),
8282 /* Helper for the following. Get rid of [r+r] memory refs
8283 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
8286 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
8288 if (reload_in_progress
)
8291 if (GET_CODE (operands
[0]) == MEM
8292 && GET_CODE (XEXP (operands
[0], 0)) != REG
8293 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
8294 GET_MODE (operands
[0]), false))
8296 = replace_equiv_address (operands
[0],
8297 copy_addr_to_reg (XEXP (operands
[0], 0)));
8299 if (GET_CODE (operands
[1]) == MEM
8300 && GET_CODE (XEXP (operands
[1], 0)) != REG
8301 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
8302 GET_MODE (operands
[1]), false))
8304 = replace_equiv_address (operands
[1],
8305 copy_addr_to_reg (XEXP (operands
[1], 0)));
8308 /* Generate a vector of constants to permute MODE for a little-endian
8309 storage operation by swapping the two halves of a vector. */
8311 rs6000_const_vec (machine_mode mode
)
8339 v
= rtvec_alloc (subparts
);
8341 for (i
= 0; i
< subparts
/ 2; ++i
)
8342 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
8343 for (i
= subparts
/ 2; i
< subparts
; ++i
)
8344 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
8349 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8350 for a VSX load or store operation. */
8352 rs6000_gen_le_vsx_permute (rtx source
, machine_mode mode
)
8354 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
8355 return gen_rtx_VEC_SELECT (mode
, source
, par
);
8358 /* Emit a little-endian load from vector memory location SOURCE to VSX
8359 register DEST in mode MODE. The load is done with two permuting
8360 insn's that represent an lxvd2x and xxpermdi. */
8362 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
8364 rtx tmp
, permute_mem
, permute_reg
;
8366 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8368 if (mode
== TImode
|| mode
== V1TImode
)
8371 dest
= gen_lowpart (V2DImode
, dest
);
8372 source
= adjust_address (source
, V2DImode
, 0);
8375 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
8376 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
8377 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8378 emit_insn (gen_rtx_SET (tmp
, permute_mem
));
8379 emit_insn (gen_rtx_SET (dest
, permute_reg
));
8382 /* Emit a little-endian store to vector memory location DEST from VSX
8383 register SOURCE in mode MODE. The store is done with two permuting
8384 insn's that represent an xxpermdi and an stxvd2x. */
8386 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
8388 rtx tmp
, permute_src
, permute_tmp
;
8390 /* This should never be called during or after reload, because it does
8391 not re-permute the source register. It is intended only for use
8393 gcc_assert (!reload_in_progress
&& !lra_in_progress
&& !reload_completed
);
8395 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8397 if (mode
== TImode
|| mode
== V1TImode
)
8400 dest
= adjust_address (dest
, V2DImode
, 0);
8401 source
= gen_lowpart (V2DImode
, source
);
8404 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
8405 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
8406 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
8407 emit_insn (gen_rtx_SET (tmp
, permute_src
));
8408 emit_insn (gen_rtx_SET (dest
, permute_tmp
));
8411 /* Emit a sequence representing a little-endian VSX load or store,
8412 moving data from SOURCE to DEST in mode MODE. This is done
8413 separately from rs6000_emit_move to ensure it is called only
8414 during expand. LE VSX loads and stores introduced later are
8415 handled with a split. The expand-time RTL generation allows
8416 us to optimize away redundant pairs of register-permutes. */
8418 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
8420 gcc_assert (!BYTES_BIG_ENDIAN
8421 && VECTOR_MEM_VSX_P (mode
)
8422 && !gpr_or_gpr_p (dest
, source
)
8423 && (MEM_P (source
) ^ MEM_P (dest
)));
8427 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
8428 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8432 if (!REG_P (source
))
8433 source
= force_reg (mode
, source
);
8434 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8438 /* Emit a move from SOURCE to DEST in mode MODE. */
8440 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
8444 operands
[1] = source
;
8446 if (TARGET_DEBUG_ADDR
)
8449 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8450 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8451 GET_MODE_NAME (mode
),
8454 can_create_pseudo_p ());
8456 fprintf (stderr
, "source:\n");
8460 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8461 if (CONST_WIDE_INT_P (operands
[1])
8462 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8464 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8468 /* Check if GCC is setting up a block move that will end up using FP
8469 registers as temporaries. We must make sure this is acceptable. */
8470 if (GET_CODE (operands
[0]) == MEM
8471 && GET_CODE (operands
[1]) == MEM
8473 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8474 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8475 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8476 ? 32 : MEM_ALIGN (operands
[0])))
8477 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8479 : MEM_ALIGN (operands
[1]))))
8480 && ! MEM_VOLATILE_P (operands
[0])
8481 && ! MEM_VOLATILE_P (operands
[1]))
8483 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8484 adjust_address (operands
[1], SImode
, 0));
8485 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8486 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8490 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8491 && !gpc_reg_operand (operands
[1], mode
))
8492 operands
[1] = force_reg (mode
, operands
[1]);
8494 /* Recognize the case where operand[1] is a reference to thread-local
8495 data and load its address to a register. */
8496 if (tls_referenced_p (operands
[1]))
8498 enum tls_model model
;
8499 rtx tmp
= operands
[1];
8502 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8504 addend
= XEXP (XEXP (tmp
, 0), 1);
8505 tmp
= XEXP (XEXP (tmp
, 0), 0);
8508 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8509 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8510 gcc_assert (model
!= 0);
8512 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8515 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8516 tmp
= force_operand (tmp
, operands
[0]);
8521 /* Handle the case where reload calls us with an invalid address. */
8522 if (reload_in_progress
&& mode
== Pmode
8523 && (! general_operand (operands
[1], mode
)
8524 || ! nonimmediate_operand (operands
[0], mode
)))
8527 /* 128-bit constant floating-point values on Darwin should really be loaded
8528 as two parts. However, this premature splitting is a problem when DFmode
8529 values can go into Altivec registers. */
8530 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8531 && !reg_addr
[DFmode
].scalar_in_vmx_p
8532 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8534 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8535 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8537 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8538 GET_MODE_SIZE (DFmode
)),
8539 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8540 GET_MODE_SIZE (DFmode
)),
8545 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8546 cfun
->machine
->sdmode_stack_slot
=
8547 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8550 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
8551 p1:SD) if p1 is not of floating point class and p0 is spilled as
8552 we can have no analogous movsd_store for this. */
8553 if (lra_in_progress
&& mode
== DDmode
8554 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8555 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8556 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
8557 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
8560 int regno
= REGNO (SUBREG_REG (operands
[1]));
8562 if (regno
>= FIRST_PSEUDO_REGISTER
)
8564 cl
= reg_preferred_class (regno
);
8565 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
8567 if (regno
>= 0 && ! FP_REGNO_P (regno
))
8570 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
8571 operands
[1] = SUBREG_REG (operands
[1]);
8576 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8577 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8578 && (REG_P (operands
[1])
8579 || (GET_CODE (operands
[1]) == SUBREG
8580 && REG_P (SUBREG_REG (operands
[1])))))
8582 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8583 ? SUBREG_REG (operands
[1]) : operands
[1]);
8586 if (regno
>= FIRST_PSEUDO_REGISTER
)
8588 cl
= reg_preferred_class (regno
);
8589 gcc_assert (cl
!= NO_REGS
);
8590 regno
= ira_class_hard_regs
[cl
][0];
8592 if (FP_REGNO_P (regno
))
8594 if (GET_MODE (operands
[0]) != DDmode
)
8595 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8596 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8598 else if (INT_REGNO_P (regno
))
8599 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8604 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
8605 p:DD)) if p0 is not of floating point class and p1 is spilled as
8606 we can have no analogous movsd_load for this. */
8607 if (lra_in_progress
&& mode
== DDmode
8608 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
8609 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
8610 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8611 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8614 int regno
= REGNO (SUBREG_REG (operands
[0]));
8616 if (regno
>= FIRST_PSEUDO_REGISTER
)
8618 cl
= reg_preferred_class (regno
);
8619 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
8621 if (regno
>= 0 && ! FP_REGNO_P (regno
))
8624 operands
[0] = SUBREG_REG (operands
[0]);
8625 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
8630 && (REG_P (operands
[0])
8631 || (GET_CODE (operands
[0]) == SUBREG
8632 && REG_P (SUBREG_REG (operands
[0]))))
8633 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8634 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8636 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8637 ? SUBREG_REG (operands
[0]) : operands
[0]);
8640 if (regno
>= FIRST_PSEUDO_REGISTER
)
8642 cl
= reg_preferred_class (regno
);
8643 gcc_assert (cl
!= NO_REGS
);
8644 regno
= ira_class_hard_regs
[cl
][0];
8646 if (FP_REGNO_P (regno
))
8648 if (GET_MODE (operands
[1]) != DDmode
)
8649 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8650 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8652 else if (INT_REGNO_P (regno
))
8653 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8659 if (reload_in_progress
8661 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8662 && MEM_P (operands
[0])
8663 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8664 && REG_P (operands
[1]))
8666 if (FP_REGNO_P (REGNO (operands
[1])))
8668 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8669 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8670 emit_insn (gen_movsd_store (mem
, operands
[1]));
8672 else if (INT_REGNO_P (REGNO (operands
[1])))
8674 rtx mem
= operands
[0];
8675 if (BYTES_BIG_ENDIAN
)
8676 mem
= adjust_address_nv (mem
, mode
, 4);
8677 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8678 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8684 if (reload_in_progress
8686 && REG_P (operands
[0])
8687 && MEM_P (operands
[1])
8688 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8689 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8691 if (FP_REGNO_P (REGNO (operands
[0])))
8693 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8694 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8695 emit_insn (gen_movsd_load (operands
[0], mem
));
8697 else if (INT_REGNO_P (REGNO (operands
[0])))
8699 rtx mem
= operands
[1];
8700 if (BYTES_BIG_ENDIAN
)
8701 mem
= adjust_address_nv (mem
, mode
, 4);
8702 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8703 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8710 /* FIXME: In the long term, this switch statement should go away
8711 and be replaced by a sequence of tests based on things like
8717 if (CONSTANT_P (operands
[1])
8718 && GET_CODE (operands
[1]) != CONST_INT
)
8719 operands
[1] = force_const_mem (mode
, operands
[1]);
8724 rs6000_eliminate_indexed_memrefs (operands
);
8731 if (CONSTANT_P (operands
[1])
8732 && ! easy_fp_constant (operands
[1], mode
))
8733 operands
[1] = force_const_mem (mode
, operands
[1]);
8747 if (CONSTANT_P (operands
[1])
8748 && !easy_vector_constant (operands
[1], mode
))
8749 operands
[1] = force_const_mem (mode
, operands
[1]);
8754 /* Use default pattern for address of ELF small data */
8757 && DEFAULT_ABI
== ABI_V4
8758 && (GET_CODE (operands
[1]) == SYMBOL_REF
8759 || GET_CODE (operands
[1]) == CONST
)
8760 && small_data_operand (operands
[1], mode
))
8762 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8766 if (DEFAULT_ABI
== ABI_V4
8767 && mode
== Pmode
&& mode
== SImode
8768 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8770 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8774 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8778 && CONSTANT_P (operands
[1])
8779 && GET_CODE (operands
[1]) != HIGH
8780 && GET_CODE (operands
[1]) != CONST_INT
)
8782 rtx target
= (!can_create_pseudo_p ()
8784 : gen_reg_rtx (mode
));
8786 /* If this is a function address on -mcall-aixdesc,
8787 convert it to the address of the descriptor. */
8788 if (DEFAULT_ABI
== ABI_AIX
8789 && GET_CODE (operands
[1]) == SYMBOL_REF
8790 && XSTR (operands
[1], 0)[0] == '.')
8792 const char *name
= XSTR (operands
[1], 0);
8794 while (*name
== '.')
8796 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8797 CONSTANT_POOL_ADDRESS_P (new_ref
)
8798 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8799 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8800 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8801 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8802 operands
[1] = new_ref
;
8805 if (DEFAULT_ABI
== ABI_DARWIN
)
8808 if (MACHO_DYNAMIC_NO_PIC_P
)
8810 /* Take care of any required data indirection. */
8811 operands
[1] = rs6000_machopic_legitimize_pic_address (
8812 operands
[1], mode
, operands
[0]);
8813 if (operands
[0] != operands
[1])
8814 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8818 emit_insn (gen_macho_high (target
, operands
[1]));
8819 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8823 emit_insn (gen_elf_high (target
, operands
[1]));
8824 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8828 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8829 and we have put it in the TOC, we just need to make a TOC-relative
8832 && GET_CODE (operands
[1]) == SYMBOL_REF
8833 && use_toc_relative_ref (operands
[1], mode
))
8834 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8835 else if (mode
== Pmode
8836 && CONSTANT_P (operands
[1])
8837 && GET_CODE (operands
[1]) != HIGH
8838 && ((GET_CODE (operands
[1]) != CONST_INT
8839 && ! easy_fp_constant (operands
[1], mode
))
8840 || (GET_CODE (operands
[1]) == CONST_INT
8841 && (num_insns_constant (operands
[1], mode
)
8842 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8843 || (GET_CODE (operands
[0]) == REG
8844 && FP_REGNO_P (REGNO (operands
[0]))))
8845 && !toc_relative_expr_p (operands
[1], false)
8846 && (TARGET_CMODEL
== CMODEL_SMALL
8847 || can_create_pseudo_p ()
8848 || (REG_P (operands
[0])
8849 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8853 /* Darwin uses a special PIC legitimizer. */
8854 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8857 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8859 if (operands
[0] != operands
[1])
8860 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8865 /* If we are to limit the number of things we put in the TOC and
8866 this is a symbol plus a constant we can add in one insn,
8867 just put the symbol in the TOC and add the constant. Don't do
8868 this if reload is in progress. */
8869 if (GET_CODE (operands
[1]) == CONST
8870 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8871 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8872 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8873 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8874 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8875 && ! side_effects_p (operands
[0]))
8878 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8879 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8881 sym
= force_reg (mode
, sym
);
8882 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8886 operands
[1] = force_const_mem (mode
, operands
[1]);
8889 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8890 && constant_pool_expr_p (XEXP (operands
[1], 0))
8891 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8892 get_pool_constant (XEXP (operands
[1], 0)),
8893 get_pool_mode (XEXP (operands
[1], 0))))
8895 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8897 operands
[1] = gen_const_mem (mode
, tocref
);
8898 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8904 if (!VECTOR_MEM_VSX_P (TImode
))
8905 rs6000_eliminate_indexed_memrefs (operands
);
8909 rs6000_eliminate_indexed_memrefs (operands
);
8913 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
8916 /* Above, we may have called force_const_mem which may have returned
8917 an invalid address. If we can, fix this up; otherwise, reload will
8918 have to deal with it. */
8919 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8920 operands
[1] = validize_mem (operands
[1]);
8923 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
8926 /* Return true if a structure, union or array containing FIELD should be
8927 accessed using `BLKMODE'.
8929 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8930 entire thing in a DI and use subregs to access the internals.
8931 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8932 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8933 best thing to do is set structs to BLKmode and avoid Severe Tire
8936 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8937 fit into 1, whereas DI still needs two. */
8940 rs6000_member_type_forces_blk (const_tree field
, machine_mode mode
)
8942 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8943 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8946 /* Nonzero if we can use a floating-point register to pass this arg. */
8947 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8948 (SCALAR_FLOAT_MODE_P (MODE) \
8949 && (CUM)->fregno <= FP_ARG_MAX_REG \
8950 && TARGET_HARD_FLOAT && TARGET_FPRS)
8952 /* Nonzero if we can use an AltiVec register to pass this arg. */
8953 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8954 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8955 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8956 && TARGET_ALTIVEC_ABI \
8959 /* Walk down the type tree of TYPE counting consecutive base elements.
8960 If *MODEP is VOIDmode, then set it to the first valid floating point
8961 or vector type. If a non-floating point or vector type is found, or
8962 if a floating point or vector type that doesn't match a non-VOIDmode
8963 *MODEP is found, then return -1, otherwise return the count in the
8967 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
8972 switch (TREE_CODE (type
))
8975 mode
= TYPE_MODE (type
);
8976 if (!SCALAR_FLOAT_MODE_P (mode
))
8979 if (*modep
== VOIDmode
)
8988 mode
= TYPE_MODE (TREE_TYPE (type
));
8989 if (!SCALAR_FLOAT_MODE_P (mode
))
8992 if (*modep
== VOIDmode
)
9001 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
9004 /* Use V4SImode as representative of all 128-bit vector types. */
9005 size
= int_size_in_bytes (type
);
9015 if (*modep
== VOIDmode
)
9018 /* Vector modes are considered to be opaque: two vectors are
9019 equivalent for the purposes of being homogeneous aggregates
9020 if they are the same size. */
9029 tree index
= TYPE_DOMAIN (type
);
9031 /* Can't handle incomplete types nor sizes that are not
9033 if (!COMPLETE_TYPE_P (type
)
9034 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9037 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
9040 || !TYPE_MAX_VALUE (index
)
9041 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
9042 || !TYPE_MIN_VALUE (index
)
9043 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
9047 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
9048 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
9050 /* There must be no padding. */
9051 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9063 /* Can't handle incomplete types nor sizes that are not
9065 if (!COMPLETE_TYPE_P (type
)
9066 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9069 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
9071 if (TREE_CODE (field
) != FIELD_DECL
)
9074 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
9080 /* There must be no padding. */
9081 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9088 case QUAL_UNION_TYPE
:
9090 /* These aren't very interesting except in a degenerate case. */
9095 /* Can't handle incomplete types nor sizes that are not
9097 if (!COMPLETE_TYPE_P (type
)
9098 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
9101 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
9103 if (TREE_CODE (field
) != FIELD_DECL
)
9106 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
9109 count
= count
> sub_count
? count
: sub_count
;
9112 /* There must be no padding. */
9113 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
9126 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
9127 float or vector aggregate that shall be passed in FP/vector registers
9128 according to the ELFv2 ABI, return the homogeneous element mode in
9129 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
9131 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
9134 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
9135 machine_mode
*elt_mode
,
9138 /* Note that we do not accept complex types at the top level as
9139 homogeneous aggregates; these types are handled via the
9140 targetm.calls.split_complex_arg mechanism. Complex types
9141 can be elements of homogeneous aggregates, however. */
9142 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
9144 machine_mode field_mode
= VOIDmode
;
9145 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
9147 if (field_count
> 0)
9149 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
9150 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
9152 /* The ELFv2 ABI allows homogeneous aggregates to occupy
9153 up to AGGR_ARG_NUM_REG registers. */
9154 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
9157 *elt_mode
= field_mode
;
9159 *n_elts
= field_count
;
9172 /* Return a nonzero value to say to return the function value in
9173 memory, just as large structures are always returned. TYPE will be
9174 the data type of the value, and FNTYPE will be the type of the
9175 function doing the returning, or @code{NULL} for libcalls.
9177 The AIX ABI for the RS/6000 specifies that all structures are
9178 returned in memory. The Darwin ABI does the same.
9180 For the Darwin 64 Bit ABI, a function result can be returned in
9181 registers or in memory, depending on the size of the return data
9182 type. If it is returned in registers, the value occupies the same
9183 registers as it would if it were the first and only function
9184 argument. Otherwise, the function places its result in memory at
9185 the location pointed to by GPR3.
9187 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
9188 but a draft put them in memory, and GCC used to implement the draft
9189 instead of the final standard. Therefore, aix_struct_return
9190 controls this instead of DEFAULT_ABI; V.4 targets needing backward
9191 compatibility can change DRAFT_V4_STRUCT_RET to override the
9192 default, and -m switches get the final word. See
9193 rs6000_option_override_internal for more details.
9195 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
9196 long double support is enabled. These values are returned in memory.
9198 int_size_in_bytes returns -1 for variable size objects, which go in
9199 memory always. The cast to unsigned makes -1 > 8. */
9202 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
9204 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
9206 && rs6000_darwin64_abi
9207 && TREE_CODE (type
) == RECORD_TYPE
9208 && int_size_in_bytes (type
) > 0)
9210 CUMULATIVE_ARGS valcum
;
9214 valcum
.fregno
= FP_ARG_MIN_REG
;
9215 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
9216 /* Do a trial code generation as if this were going to be passed
9217 as an argument; if any part goes in memory, we return NULL. */
9218 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
9221 /* Otherwise fall through to more conventional ABI rules. */
9224 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
9225 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
9229 /* The ELFv2 ABI returns aggregates up to 16B in registers */
9230 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
9231 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
9234 if (AGGREGATE_TYPE_P (type
)
9235 && (aix_struct_return
9236 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
9239 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9240 modes only exist for GCC vector types if -maltivec. */
9241 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
9242 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
9245 /* Return synthetic vectors in memory. */
9246 if (TREE_CODE (type
) == VECTOR_TYPE
9247 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
9249 static bool warned_for_return_big_vectors
= false;
9250 if (!warned_for_return_big_vectors
)
9252 warning (0, "GCC vector returned by reference: "
9253 "non-standard ABI extension with no compatibility guarantee");
9254 warned_for_return_big_vectors
= true;
9259 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
9265 /* Specify whether values returned in registers should be at the most
9266 significant end of a register. We want aggregates returned by
9267 value to match the way aggregates are passed to functions. */
9270 rs6000_return_in_msb (const_tree valtype
)
9272 return (DEFAULT_ABI
== ABI_ELFv2
9274 && AGGREGATE_TYPE_P (valtype
)
9275 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
9278 #ifdef HAVE_AS_GNU_ATTRIBUTE
9279 /* Return TRUE if a call to function FNDECL may be one that
9280 potentially affects the function calling ABI of the object file. */
9283 call_ABI_of_interest (tree fndecl
)
9285 if (symtab
->state
== EXPANSION
)
9287 struct cgraph_node
*c_node
;
9289 /* Libcalls are always interesting. */
9290 if (fndecl
== NULL_TREE
)
9293 /* Any call to an external function is interesting. */
9294 if (DECL_EXTERNAL (fndecl
))
9297 /* Interesting functions that we are emitting in this object file. */
9298 c_node
= cgraph_node::get (fndecl
);
9299 c_node
= c_node
->ultimate_alias_target ();
9300 return !c_node
->only_called_directly_p ();
9306 /* Initialize a variable CUM of type CUMULATIVE_ARGS
9307 for a call to a function whose data type is FNTYPE.
9308 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
9310 For incoming args we set the number of arguments in the prototype large
9311 so we never return a PARALLEL. */
9314 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
9315 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
9316 int libcall
, int n_named_args
,
9317 tree fndecl ATTRIBUTE_UNUSED
,
9318 machine_mode return_mode ATTRIBUTE_UNUSED
)
9320 static CUMULATIVE_ARGS zero_cumulative
;
9322 *cum
= zero_cumulative
;
9324 cum
->fregno
= FP_ARG_MIN_REG
;
9325 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
9326 cum
->prototype
= (fntype
&& prototype_p (fntype
));
9327 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
9328 ? CALL_LIBCALL
: CALL_NORMAL
);
9329 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
9330 cum
->stdarg
= stdarg_p (fntype
);
9332 cum
->nargs_prototype
= 0;
9333 if (incoming
|| cum
->prototype
)
9334 cum
->nargs_prototype
= n_named_args
;
9336 /* Check for a longcall attribute. */
9337 if ((!fntype
&& rs6000_default_long_calls
)
9339 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
9340 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
9341 cum
->call_cookie
|= CALL_LONG
;
9343 if (TARGET_DEBUG_ARG
)
9345 fprintf (stderr
, "\ninit_cumulative_args:");
9348 tree ret_type
= TREE_TYPE (fntype
);
9349 fprintf (stderr
, " ret code = %s,",
9350 get_tree_code_name (TREE_CODE (ret_type
)));
9353 if (cum
->call_cookie
& CALL_LONG
)
9354 fprintf (stderr
, " longcall,");
9356 fprintf (stderr
, " proto = %d, nargs = %d\n",
9357 cum
->prototype
, cum
->nargs_prototype
);
9360 #ifdef HAVE_AS_GNU_ATTRIBUTE
9361 if (DEFAULT_ABI
== ABI_V4
)
9363 cum
->escapes
= call_ABI_of_interest (fndecl
);
9370 return_type
= TREE_TYPE (fntype
);
9371 return_mode
= TYPE_MODE (return_type
);
9374 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
9376 if (return_type
!= NULL
)
9378 if (TREE_CODE (return_type
) == RECORD_TYPE
9379 && TYPE_TRANSPARENT_AGGR (return_type
))
9381 return_type
= TREE_TYPE (first_field (return_type
));
9382 return_mode
= TYPE_MODE (return_type
);
9384 if (AGGREGATE_TYPE_P (return_type
)
9385 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
9387 rs6000_returns_struct
= true;
9389 if (SCALAR_FLOAT_MODE_P (return_mode
))
9390 rs6000_passes_float
= true;
9391 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
9392 || SPE_VECTOR_MODE (return_mode
))
9393 rs6000_passes_vector
= true;
9400 && TARGET_ALTIVEC_ABI
9401 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
9403 error ("cannot return value in vector register because"
9404 " altivec instructions are disabled, use -maltivec"
9409 /* The mode the ABI uses for a word. This is not the same as word_mode
9410 for -m32 -mpowerpc64. This is used to implement various target hooks. */
9413 rs6000_abi_word_mode (void)
9415 return TARGET_32BIT
? SImode
: DImode
;
9418 /* On rs6000, function arguments are promoted, as are function return
9422 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
9424 int *punsignedp ATTRIBUTE_UNUSED
,
9427 PROMOTE_MODE (mode
, *punsignedp
, type
);
9432 /* Return true if TYPE must be passed on the stack and not in registers. */
9435 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
9437 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
9438 return must_pass_in_stack_var_size (mode
, type
);
9440 return must_pass_in_stack_var_size_or_pad (mode
, type
);
9443 /* If defined, a C expression which determines whether, and in which
9444 direction, to pad out an argument with extra space. The value
9445 should be of type `enum direction': either `upward' to pad above
9446 the argument, `downward' to pad below, or `none' to inhibit
9449 For the AIX ABI structs are always stored left shifted in their
9453 function_arg_padding (machine_mode mode
, const_tree type
)
9455 #ifndef AGGREGATE_PADDING_FIXED
9456 #define AGGREGATE_PADDING_FIXED 0
9458 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9459 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9462 if (!AGGREGATE_PADDING_FIXED
)
9464 /* GCC used to pass structures of the same size as integer types as
9465 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9466 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9467 passed padded downward, except that -mstrict-align further
9468 muddied the water in that multi-component structures of 2 and 4
9469 bytes in size were passed padded upward.
9471 The following arranges for best compatibility with previous
9472 versions of gcc, but removes the -mstrict-align dependency. */
9473 if (BYTES_BIG_ENDIAN
)
9475 HOST_WIDE_INT size
= 0;
9477 if (mode
== BLKmode
)
9479 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
9480 size
= int_size_in_bytes (type
);
9483 size
= GET_MODE_SIZE (mode
);
9485 if (size
== 1 || size
== 2 || size
== 4)
9491 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9493 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
9497 /* Fall back to the default. */
9498 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9501 /* If defined, a C expression that gives the alignment boundary, in bits,
9502 of an argument with the specified mode and type. If it is not defined,
9503 PARM_BOUNDARY is used for all arguments.
9505 V.4 wants long longs and doubles to be double word aligned. Just
9506 testing the mode size is a boneheaded way to do this as it means
9507 that other types such as complex int are also double word aligned.
9508 However, we're stuck with this because changing the ABI might break
9509 existing library interfaces.
9511 Doubleword align SPE vectors.
9512 Quadword align Altivec/VSX vectors.
9513 Quadword align large synthetic vector types. */
9516 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
9518 machine_mode elt_mode
;
9521 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9523 if (DEFAULT_ABI
== ABI_V4
9524 && (GET_MODE_SIZE (mode
) == 8
9525 || (TARGET_HARD_FLOAT
9527 && (mode
== TFmode
|| mode
== TDmode
))))
9529 else if (SPE_VECTOR_MODE (mode
)
9530 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9531 && int_size_in_bytes (type
) >= 8
9532 && int_size_in_bytes (type
) < 16))
9534 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9535 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9536 && int_size_in_bytes (type
) >= 16))
9539 /* Aggregate types that need > 8 byte alignment are quadword-aligned
9540 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
9541 -mcompat-align-parm is used. */
9542 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
9543 || DEFAULT_ABI
== ABI_ELFv2
)
9544 && type
&& TYPE_ALIGN (type
) > 64)
9546 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
9547 or homogeneous float/vector aggregates here. We already handled
9548 vector aggregates above, but still need to check for float here. */
9549 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
9550 && !SCALAR_FLOAT_MODE_P (elt_mode
));
9552 /* We used to check for BLKmode instead of the above aggregate type
9553 check. Warn when this results in any difference to the ABI. */
9554 if (aggregate_p
!= (mode
== BLKmode
))
9557 if (!warned
&& warn_psabi
)
9560 inform (input_location
,
9561 "the ABI of passing aggregates with %d-byte alignment"
9562 " has changed in GCC 5",
9563 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
9571 /* Similar for the Darwin64 ABI. Note that for historical reasons we
9572 implement the "aggregate type" check as a BLKmode check here; this
9573 means certain aggregate types are in fact not aligned. */
9574 if (TARGET_MACHO
&& rs6000_darwin64_abi
9576 && type
&& TYPE_ALIGN (type
) > 64)
9579 return PARM_BOUNDARY
;
9582 /* The offset in words to the start of the parameter save area. */
9585 rs6000_parm_offset (void)
9587 return (DEFAULT_ABI
== ABI_V4
? 2
9588 : DEFAULT_ABI
== ABI_ELFv2
? 4
9592 /* For a function parm of MODE and TYPE, return the starting word in
9593 the parameter area. NWORDS of the parameter area are already used. */
9596 rs6000_parm_start (machine_mode mode
, const_tree type
,
9597 unsigned int nwords
)
9601 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9602 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9605 /* Compute the size (in words) of a function argument. */
9607 static unsigned long
9608 rs6000_arg_size (machine_mode mode
, const_tree type
)
9612 if (mode
!= BLKmode
)
9613 size
= GET_MODE_SIZE (mode
);
9615 size
= int_size_in_bytes (type
);
9618 return (size
+ 3) >> 2;
9620 return (size
+ 7) >> 3;
9623 /* Use this to flush pending int fields. */
9626 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9627 HOST_WIDE_INT bitpos
, int final
)
9629 unsigned int startbit
, endbit
;
9630 int intregs
, intoffset
;
9633 /* Handle the situations where a float is taking up the first half
9634 of the GPR, and the other half is empty (typically due to
9635 alignment restrictions). We can detect this by a 8-byte-aligned
9636 int field, or by seeing that this is the final flush for this
9637 argument. Count the word and continue on. */
9638 if (cum
->floats_in_gpr
== 1
9639 && (cum
->intoffset
% 64 == 0
9640 || (cum
->intoffset
== -1 && final
)))
9643 cum
->floats_in_gpr
= 0;
9646 if (cum
->intoffset
== -1)
9649 intoffset
= cum
->intoffset
;
9650 cum
->intoffset
= -1;
9651 cum
->floats_in_gpr
= 0;
9653 if (intoffset
% BITS_PER_WORD
!= 0)
9655 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9657 if (mode
== BLKmode
)
9659 /* We couldn't find an appropriate mode, which happens,
9660 e.g., in packed structs when there are 3 bytes to load.
9661 Back intoffset back to the beginning of the word in this
9663 intoffset
= intoffset
& -BITS_PER_WORD
;
9667 startbit
= intoffset
& -BITS_PER_WORD
;
9668 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9669 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9670 cum
->words
+= intregs
;
9671 /* words should be unsigned. */
9672 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9674 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9679 /* The darwin64 ABI calls for us to recurse down through structs,
9680 looking for elements passed in registers. Unfortunately, we have
9681 to track int register count here also because of misalignments
9682 in powerpc alignment mode. */
9685 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9687 HOST_WIDE_INT startbitpos
)
9691 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9692 if (TREE_CODE (f
) == FIELD_DECL
)
9694 HOST_WIDE_INT bitpos
= startbitpos
;
9695 tree ftype
= TREE_TYPE (f
);
9697 if (ftype
== error_mark_node
)
9699 mode
= TYPE_MODE (ftype
);
9701 if (DECL_SIZE (f
) != 0
9702 && tree_fits_uhwi_p (bit_position (f
)))
9703 bitpos
+= int_bit_position (f
);
9705 /* ??? FIXME: else assume zero offset. */
9707 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9708 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9709 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9711 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9712 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9713 cum
->fregno
+= n_fpregs
;
9714 /* Single-precision floats present a special problem for
9715 us, because they are smaller than an 8-byte GPR, and so
9716 the structure-packing rules combined with the standard
9717 varargs behavior mean that we want to pack float/float
9718 and float/int combinations into a single register's
9719 space. This is complicated by the arg advance flushing,
9720 which works on arbitrarily large groups of int-type
9724 if (cum
->floats_in_gpr
== 1)
9726 /* Two floats in a word; count the word and reset
9729 cum
->floats_in_gpr
= 0;
9731 else if (bitpos
% 64 == 0)
9733 /* A float at the beginning of an 8-byte word;
9734 count it and put off adjusting cum->words until
9735 we see if a arg advance flush is going to do it
9737 cum
->floats_in_gpr
++;
9741 /* The float is at the end of a word, preceded
9742 by integer fields, so the arg advance flush
9743 just above has already set cum->words and
9744 everything is taken care of. */
9748 cum
->words
+= n_fpregs
;
9750 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9752 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9756 else if (cum
->intoffset
== -1)
9757 cum
->intoffset
= bitpos
;
9761 /* Check for an item that needs to be considered specially under the darwin 64
9762 bit ABI. These are record types where the mode is BLK or the structure is
9765 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
9767 return rs6000_darwin64_abi
9768 && ((mode
== BLKmode
9769 && TREE_CODE (type
) == RECORD_TYPE
9770 && int_size_in_bytes (type
) > 0)
9771 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9772 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9775 /* Update the data in CUM to advance over an argument
9776 of mode MODE and data type TYPE.
9777 (TYPE is null for libcalls where that information may not be available.)
9779 Note that for args passed by reference, function_arg will be called
9780 with MODE and TYPE set to that of the pointer to the arg, not the arg
9784 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
9785 const_tree type
, bool named
, int depth
)
9787 machine_mode elt_mode
;
9790 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9792 /* Only tick off an argument if we're not recursing. */
9794 cum
->nargs_prototype
--;
9796 #ifdef HAVE_AS_GNU_ATTRIBUTE
9797 if (DEFAULT_ABI
== ABI_V4
9800 if (SCALAR_FLOAT_MODE_P (mode
))
9801 rs6000_passes_float
= true;
9802 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9803 rs6000_passes_vector
= true;
9804 else if (SPE_VECTOR_MODE (mode
)
9806 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9807 rs6000_passes_vector
= true;
9811 if (TARGET_ALTIVEC_ABI
9812 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9813 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9814 && int_size_in_bytes (type
) == 16)))
9818 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9820 cum
->vregno
+= n_elts
;
9822 if (!TARGET_ALTIVEC
)
9823 error ("cannot pass argument in vector register because"
9824 " altivec instructions are disabled, use -maltivec"
9827 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9828 even if it is going to be passed in a vector register.
9829 Darwin does the same for variable-argument functions. */
9830 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9832 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9842 /* Vector parameters must be 16-byte aligned. In 32-bit
9843 mode this means we need to take into account the offset
9844 to the parameter save area. In 64-bit mode, they just
9845 have to start on an even word, since the parameter save
9846 area is 16-byte aligned. */
9848 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9850 align
= cum
->words
& 1;
9851 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9853 if (TARGET_DEBUG_ARG
)
9855 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9857 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9858 cum
->nargs_prototype
, cum
->prototype
,
9859 GET_MODE_NAME (mode
));
9863 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9865 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9868 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9870 int size
= int_size_in_bytes (type
);
9871 /* Variable sized types have size == -1 and are
9872 treated as if consisting entirely of ints.
9873 Pad to 16 byte boundary if needed. */
9874 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9875 && (cum
->words
% 2) != 0)
9877 /* For varargs, we can just go up by the size of the struct. */
9879 cum
->words
+= (size
+ 7) / 8;
9882 /* It is tempting to say int register count just goes up by
9883 sizeof(type)/8, but this is wrong in a case such as
9884 { int; double; int; } [powerpc alignment]. We have to
9885 grovel through the fields for these too. */
9887 cum
->floats_in_gpr
= 0;
9888 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9889 rs6000_darwin64_record_arg_advance_flush (cum
,
9890 size
* BITS_PER_UNIT
, 1);
9892 if (TARGET_DEBUG_ARG
)
9894 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9895 cum
->words
, TYPE_ALIGN (type
), size
);
9897 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9898 cum
->nargs_prototype
, cum
->prototype
,
9899 GET_MODE_NAME (mode
));
9902 else if (DEFAULT_ABI
== ABI_V4
)
9904 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9905 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9906 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9907 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9908 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9910 /* _Decimal128 must use an even/odd register pair. This assumes
9911 that the register number is odd when fregno is odd. */
9912 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9915 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9916 <= FP_ARG_V4_MAX_REG
)
9917 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9920 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9921 if (mode
== DFmode
|| mode
== TFmode
9922 || mode
== DDmode
|| mode
== TDmode
)
9923 cum
->words
+= cum
->words
& 1;
9924 cum
->words
+= rs6000_arg_size (mode
, type
);
9929 int n_words
= rs6000_arg_size (mode
, type
);
9930 int gregno
= cum
->sysv_gregno
;
9932 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9933 (r7,r8) or (r9,r10). As does any other 2 word item such
9934 as complex int due to a historical mistake. */
9936 gregno
+= (1 - gregno
) & 1;
9938 /* Multi-reg args are not split between registers and stack. */
9939 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9941 /* Long long and SPE vectors are aligned on the stack.
9942 So are other 2 word items such as complex int due to
9943 a historical mistake. */
9945 cum
->words
+= cum
->words
& 1;
9946 cum
->words
+= n_words
;
9949 /* Note: continuing to accumulate gregno past when we've started
9950 spilling to the stack indicates the fact that we've started
9951 spilling to the stack to expand_builtin_saveregs. */
9952 cum
->sysv_gregno
= gregno
+ n_words
;
9955 if (TARGET_DEBUG_ARG
)
9957 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9958 cum
->words
, cum
->fregno
);
9959 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9960 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9961 fprintf (stderr
, "mode = %4s, named = %d\n",
9962 GET_MODE_NAME (mode
), named
);
9967 int n_words
= rs6000_arg_size (mode
, type
);
9968 int start_words
= cum
->words
;
9969 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9971 cum
->words
= align_words
+ n_words
;
9973 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9974 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9976 /* _Decimal128 must be passed in an even/odd float register pair.
9977 This assumes that the register number is odd when fregno is
9979 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9981 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9984 if (TARGET_DEBUG_ARG
)
9986 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9987 cum
->words
, cum
->fregno
);
9988 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9989 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9990 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9991 named
, align_words
- start_words
, depth
);
9997 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
9998 const_tree type
, bool named
)
10000 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
10005 spe_build_register_parallel (machine_mode mode
, int gregno
)
10007 rtx r1
, r3
, r5
, r7
;
10012 r1
= gen_rtx_REG (DImode
, gregno
);
10013 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10014 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
10018 r1
= gen_rtx_REG (DImode
, gregno
);
10019 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10020 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
10021 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
10022 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
10025 r1
= gen_rtx_REG (DImode
, gregno
);
10026 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
10027 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
10028 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
10029 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
10030 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
10031 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
10032 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
10033 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
10036 gcc_unreachable ();
10040 /* Determine where to put a SIMD argument on the SPE. */
10042 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, machine_mode mode
,
10045 int gregno
= cum
->sysv_gregno
;
10047 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
10048 are passed and returned in a pair of GPRs for ABI compatibility. */
10049 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
10050 || mode
== DCmode
|| mode
== TCmode
))
10052 int n_words
= rs6000_arg_size (mode
, type
);
10054 /* Doubles go in an odd/even register pair (r5/r6, etc). */
10055 if (mode
== DFmode
)
10056 gregno
+= (1 - gregno
) & 1;
10058 /* Multi-reg args are not split between registers and stack. */
10059 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10062 return spe_build_register_parallel (mode
, gregno
);
10066 int n_words
= rs6000_arg_size (mode
, type
);
10068 /* SPE vectors are put in odd registers. */
10069 if (n_words
== 2 && (gregno
& 1) == 0)
10072 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
10075 machine_mode m
= SImode
;
10077 r1
= gen_rtx_REG (m
, gregno
);
10078 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
10079 r2
= gen_rtx_REG (m
, gregno
+ 1);
10080 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
10081 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
10088 if (gregno
<= GP_ARG_MAX_REG
)
10089 return gen_rtx_REG (mode
, gregno
);
10095 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
10096 structure between cum->intoffset and bitpos to integer registers. */
10099 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
10100 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
10103 unsigned int regno
;
10104 unsigned int startbit
, endbit
;
10105 int this_regno
, intregs
, intoffset
;
10108 if (cum
->intoffset
== -1)
10111 intoffset
= cum
->intoffset
;
10112 cum
->intoffset
= -1;
10114 /* If this is the trailing part of a word, try to only load that
10115 much into the register. Otherwise load the whole register. Note
10116 that in the latter case we may pick up unwanted bits. It's not a
10117 problem at the moment but may wish to revisit. */
10119 if (intoffset
% BITS_PER_WORD
!= 0)
10121 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
10123 if (mode
== BLKmode
)
10125 /* We couldn't find an appropriate mode, which happens,
10126 e.g., in packed structs when there are 3 bytes to load.
10127 Back intoffset back to the beginning of the word in this
10129 intoffset
= intoffset
& -BITS_PER_WORD
;
10136 startbit
= intoffset
& -BITS_PER_WORD
;
10137 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
10138 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
10139 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
10141 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
10142 cum
->use_stack
= 1;
10144 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
10148 intoffset
/= BITS_PER_UNIT
;
10151 regno
= GP_ARG_MIN_REG
+ this_regno
;
10152 reg
= gen_rtx_REG (mode
, regno
);
10154 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
10157 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
10161 while (intregs
> 0);
10164 /* Recursive workhorse for the following. */
10167 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
10168 HOST_WIDE_INT startbitpos
, rtx rvec
[],
10173 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
10174 if (TREE_CODE (f
) == FIELD_DECL
)
10176 HOST_WIDE_INT bitpos
= startbitpos
;
10177 tree ftype
= TREE_TYPE (f
);
10179 if (ftype
== error_mark_node
)
10181 mode
= TYPE_MODE (ftype
);
10183 if (DECL_SIZE (f
) != 0
10184 && tree_fits_uhwi_p (bit_position (f
)))
10185 bitpos
+= int_bit_position (f
);
10187 /* ??? FIXME: else assume zero offset. */
10189 if (TREE_CODE (ftype
) == RECORD_TYPE
)
10190 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
10191 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
10193 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
10197 case SCmode
: mode
= SFmode
; break;
10198 case DCmode
: mode
= DFmode
; break;
10199 case TCmode
: mode
= TFmode
; break;
10203 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
10204 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
10206 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
10207 && (mode
== TFmode
|| mode
== TDmode
));
10208 /* Long double or _Decimal128 split over regs and memory. */
10209 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
10213 = gen_rtx_EXPR_LIST (VOIDmode
,
10214 gen_rtx_REG (mode
, cum
->fregno
++),
10215 GEN_INT (bitpos
/ BITS_PER_UNIT
));
10216 if (mode
== TFmode
|| mode
== TDmode
)
10219 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
10221 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
10223 = gen_rtx_EXPR_LIST (VOIDmode
,
10224 gen_rtx_REG (mode
, cum
->vregno
++),
10225 GEN_INT (bitpos
/ BITS_PER_UNIT
));
10227 else if (cum
->intoffset
== -1)
10228 cum
->intoffset
= bitpos
;
10232 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
10233 the register(s) to be used for each field and subfield of a struct
10234 being passed by value, along with the offset of where the
10235 register's value may be found in the block. FP fields go in FP
10236 register, vector fields go in vector registers, and everything
10237 else goes in int registers, packed as in memory.
10239 This code is also used for function return values. RETVAL indicates
10240 whether this is the case.
10242 Much of this is taken from the SPARC V9 port, which has a similar
10243 calling convention. */
10246 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
10247 bool named
, bool retval
)
10249 rtx rvec
[FIRST_PSEUDO_REGISTER
];
10250 int k
= 1, kbase
= 1;
10251 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
10252 /* This is a copy; modifications are not visible to our caller. */
10253 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
10254 CUMULATIVE_ARGS
*cum
= ©_cum
;
10256 /* Pad to 16 byte boundary if needed. */
10257 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
10258 && (cum
->words
% 2) != 0)
10261 cum
->intoffset
= 0;
10262 cum
->use_stack
= 0;
10263 cum
->named
= named
;
10265 /* Put entries into rvec[] for individual FP and vector fields, and
10266 for the chunks of memory that go in int regs. Note we start at
10267 element 1; 0 is reserved for an indication of using memory, and
10268 may or may not be filled in below. */
10269 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
10270 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
10272 /* If any part of the struct went on the stack put all of it there.
10273 This hack is because the generic code for
10274 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
10275 parts of the struct are not at the beginning. */
10276 if (cum
->use_stack
)
10279 return NULL_RTX
; /* doesn't go in registers at all */
10281 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10283 if (k
> 1 || cum
->use_stack
)
10284 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
10289 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
10292 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
10297 rtx rvec
[GP_ARG_NUM_REG
+ 1];
10299 if (align_words
>= GP_ARG_NUM_REG
)
10302 n_units
= rs6000_arg_size (mode
, type
);
10304 /* Optimize the simple case where the arg fits in one gpr, except in
10305 the case of BLKmode due to assign_parms assuming that registers are
10306 BITS_PER_WORD wide. */
10308 || (n_units
== 1 && mode
!= BLKmode
))
10309 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10312 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
10313 /* Not all of the arg fits in gprs. Say that it goes in memory too,
10314 using a magic NULL_RTX component.
10315 This is not strictly correct. Only some of the arg belongs in
10316 memory, not all of it. However, the normal scheme using
10317 function_arg_partial_nregs can result in unusual subregs, eg.
10318 (subreg:SI (reg:DF) 4), which are not handled well. The code to
10319 store the whole arg to memory is often more efficient than code
10320 to store pieces, and we know that space is available in the right
10321 place for the whole arg. */
10322 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10327 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
10328 rtx off
= GEN_INT (i
++ * 4);
10329 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10331 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
10333 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10336 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
10337 but must also be copied into the parameter save area starting at
10338 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
10339 to the GPRs and/or memory. Return the number of elements used. */
10342 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
10343 int align_words
, rtx
*rvec
)
10347 if (align_words
< GP_ARG_NUM_REG
)
10349 int n_words
= rs6000_arg_size (mode
, type
);
10351 if (align_words
+ n_words
> GP_ARG_NUM_REG
10353 || (TARGET_32BIT
&& TARGET_POWERPC64
))
10355 /* If this is partially on the stack, then we only
10356 include the portion actually in registers here. */
10357 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
10360 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10362 /* Not all of the arg fits in gprs. Say that it goes in memory
10363 too, using a magic NULL_RTX component. Also see comment in
10364 rs6000_mixed_function_arg for why the normal
10365 function_arg_partial_nregs scheme doesn't work in this case. */
10366 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10371 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
10372 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
10373 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10375 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
10379 /* The whole arg fits in gprs. */
10380 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10381 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
10386 /* It's entirely in memory. */
10387 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
10393 /* RVEC is a vector of K components of an argument of mode MODE.
10394 Construct the final function_arg return value from it. */
10397 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
10399 gcc_assert (k
>= 1);
10401 /* Avoid returning a PARALLEL in the trivial cases. */
10404 if (XEXP (rvec
[0], 0) == NULL_RTX
)
10407 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
10408 return XEXP (rvec
[0], 0);
10411 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
10414 /* Determine where to put an argument to a function.
10415 Value is zero to push the argument on the stack,
10416 or a hard register in which to store the argument.
10418 MODE is the argument's machine mode.
10419 TYPE is the data type of the argument (as a tree).
10420 This is null for libcalls where that information may
10422 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10423 the preceding args and about the function being called. It is
10424 not modified in this routine.
10425 NAMED is nonzero if this argument is a named parameter
10426 (otherwise it is an extra parameter matching an ellipsis).
10428 On RS/6000 the first eight words of non-FP are normally in registers
10429 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10430 Under V.4, the first 8 FP args are in registers.
10432 If this is floating-point and no prototype is specified, we use
10433 both an FP and integer register (or possibly FP reg and stack). Library
10434 functions (when CALL_LIBCALL is set) always have the proper types for args,
10435 so we can pass the FP value just in one register. emit_library_function
10436 doesn't support PARALLEL anyway.
10438 Note that for args passed by reference, function_arg will be called
10439 with MODE and TYPE set to that of the pointer to the arg, not the arg
10443 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
10444 const_tree type
, bool named
)
10446 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10447 enum rs6000_abi abi
= DEFAULT_ABI
;
10448 machine_mode elt_mode
;
10451 /* Return a marker to indicate whether CR1 needs to set or clear the
10452 bit that V.4 uses to say fp args were passed in registers.
10453 Assume that we don't need the marker for software floating point,
10454 or compiler generated library calls. */
10455 if (mode
== VOIDmode
)
10458 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
10460 || (cum
->nargs_prototype
< 0
10461 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
10463 /* For the SPE, we need to crxor CR6 always. */
10464 if (TARGET_SPE_ABI
)
10465 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
10466 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
10467 return GEN_INT (cum
->call_cookie
10468 | ((cum
->fregno
== FP_ARG_MIN_REG
)
10469 ? CALL_V4_SET_FP_ARGS
10470 : CALL_V4_CLEAR_FP_ARGS
));
10473 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
10476 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10478 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10480 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
10481 if (rslt
!= NULL_RTX
)
10483 /* Else fall through to usual handling. */
10486 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10488 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10492 /* Do we also need to pass this argument in the parameter
10494 if (TARGET_64BIT
&& ! cum
->prototype
)
10496 int align_words
= (cum
->words
+ 1) & ~1;
10497 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10500 /* Describe where this argument goes in the vector registers. */
10501 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
10503 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
10504 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10505 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10508 return rs6000_finish_function_arg (mode
, rvec
, k
);
10510 else if (TARGET_ALTIVEC_ABI
10511 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
10512 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
10513 && int_size_in_bytes (type
) == 16)))
10515 if (named
|| abi
== ABI_V4
)
10519 /* Vector parameters to varargs functions under AIX or Darwin
10520 get passed in memory and possibly also in GPRs. */
10521 int align
, align_words
, n_words
;
10522 machine_mode part_mode
;
10524 /* Vector parameters must be 16-byte aligned. In 32-bit
10525 mode this means we need to take into account the offset
10526 to the parameter save area. In 64-bit mode, they just
10527 have to start on an even word, since the parameter save
10528 area is 16-byte aligned. */
10530 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10532 align
= cum
->words
& 1;
10533 align_words
= cum
->words
+ align
;
10535 /* Out of registers? Memory, then. */
10536 if (align_words
>= GP_ARG_NUM_REG
)
10539 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10540 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10542 /* The vector value goes in GPRs. Only the part of the
10543 value in GPRs is reported here. */
10545 n_words
= rs6000_arg_size (mode
, type
);
10546 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10547 /* Fortunately, there are only two possibilities, the value
10548 is either wholly in GPRs or half in GPRs and half not. */
10549 part_mode
= DImode
;
10551 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10554 else if (TARGET_SPE_ABI
&& TARGET_SPE
10555 && (SPE_VECTOR_MODE (mode
)
10556 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10559 || mode
== TCmode
))))
10560 return rs6000_spe_function_arg (cum
, mode
, type
);
10562 else if (abi
== ABI_V4
)
10564 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10565 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10566 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10567 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10568 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10570 /* _Decimal128 must use an even/odd register pair. This assumes
10571 that the register number is odd when fregno is odd. */
10572 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10575 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10576 <= FP_ARG_V4_MAX_REG
)
10577 return gen_rtx_REG (mode
, cum
->fregno
);
10583 int n_words
= rs6000_arg_size (mode
, type
);
10584 int gregno
= cum
->sysv_gregno
;
10586 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10587 (r7,r8) or (r9,r10). As does any other 2 word item such
10588 as complex int due to a historical mistake. */
10590 gregno
+= (1 - gregno
) & 1;
10592 /* Multi-reg args are not split between registers and stack. */
10593 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10596 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10597 return rs6000_mixed_function_arg (mode
, type
,
10598 gregno
- GP_ARG_MIN_REG
);
10599 return gen_rtx_REG (mode
, gregno
);
10604 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10606 /* _Decimal128 must be passed in an even/odd float register pair.
10607 This assumes that the register number is odd when fregno is odd. */
10608 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10611 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10613 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10616 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10619 /* Do we also need to pass this argument in the parameter
10621 if (type
&& (cum
->nargs_prototype
<= 0
10622 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10623 && TARGET_XL_COMPAT
10624 && align_words
>= GP_ARG_NUM_REG
)))
10625 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10627 /* Describe where this argument goes in the fprs. */
10628 for (i
= 0; i
< n_elts
10629 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10631 /* Check if the argument is split over registers and memory.
10632 This can only ever happen for long double or _Decimal128;
10633 complex types are handled via split_complex_arg. */
10634 machine_mode fmode
= elt_mode
;
10635 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10637 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10638 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10641 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10642 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10643 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10646 /* If there were not enough FPRs to hold the argument, the rest
10647 usually goes into memory. However, if the current position
10648 is still within the register parameter area, a portion may
10649 actually have to go into GPRs.
10651 Note that it may happen that the portion of the argument
10652 passed in the first "half" of the first GPR was already
10653 passed in the last FPR as well.
10655 For unnamed arguments, we already set up GPRs to cover the
10656 whole argument in rs6000_psave_function_arg, so there is
10657 nothing further to do at this point. */
10658 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
10659 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
10660 && cum
->nargs_prototype
> 0)
10662 static bool warned
;
10664 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
10665 int n_words
= rs6000_arg_size (mode
, type
);
10667 align_words
+= fpr_words
;
10668 n_words
-= fpr_words
;
10672 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
10673 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
10674 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10676 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
10678 if (!warned
&& warn_psabi
)
10681 inform (input_location
,
10682 "the ABI of passing homogeneous float aggregates"
10683 " has changed in GCC 5");
10687 return rs6000_finish_function_arg (mode
, rvec
, k
);
10689 else if (align_words
< GP_ARG_NUM_REG
)
10691 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10692 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10694 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10701 /* For an arg passed partly in registers and partly in memory, this is
10702 the number of bytes passed in registers. For args passed entirely in
10703 registers or entirely in memory, zero. When an arg is described by a
10704 PARALLEL, perhaps using more than one register type, this function
10705 returns the number of bytes used by the first element of the PARALLEL. */
10708 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
10709 tree type
, bool named
)
10711 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10712 bool passed_in_gprs
= true;
10715 machine_mode elt_mode
;
10718 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10720 if (DEFAULT_ABI
== ABI_V4
)
10723 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10725 /* If we are passing this arg in the fixed parameter save area
10726 (gprs or memory) as well as VRs, we do not use the partial
10727 bytes mechanism; instead, rs6000_function_arg will return a
10728 PARALLEL including a memory element as necessary. */
10729 if (TARGET_64BIT
&& ! cum
->prototype
)
10732 /* Otherwise, we pass in VRs only. Check for partial copies. */
10733 passed_in_gprs
= false;
10734 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10735 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10738 /* In this complicated case we just disable the partial_nregs code. */
10739 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10742 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10744 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10746 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10748 /* If we are passing this arg in the fixed parameter save area
10749 (gprs or memory) as well as FPRs, we do not use the partial
10750 bytes mechanism; instead, rs6000_function_arg will return a
10751 PARALLEL including a memory element as necessary. */
10753 && (cum
->nargs_prototype
<= 0
10754 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10755 && TARGET_XL_COMPAT
10756 && align_words
>= GP_ARG_NUM_REG
)))
10759 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10760 passed_in_gprs
= false;
10761 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10763 /* Compute number of bytes / words passed in FPRs. If there
10764 is still space available in the register parameter area
10765 *after* that amount, a part of the argument will be passed
10766 in GPRs. In that case, the total amount passed in any
10767 registers is equal to the amount that would have been passed
10768 in GPRs if everything were passed there, so we fall back to
10769 the GPR code below to compute the appropriate value. */
10770 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10771 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10772 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
10774 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
10775 passed_in_gprs
= true;
10782 && align_words
< GP_ARG_NUM_REG
10783 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10784 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10786 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10787 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10792 /* A C expression that indicates when an argument must be passed by
10793 reference. If nonzero for an argument, a copy of that argument is
10794 made in memory and a pointer to the argument is passed instead of
10795 the argument itself. The pointer is passed in whatever way is
10796 appropriate for passing a pointer to that type.
10798 Under V.4, aggregates and long double are passed by reference.
10800 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10801 reference unless the AltiVec vector extension ABI is in force.
10803 As an extension to all ABIs, variable sized types are passed by
10807 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10808 machine_mode mode
, const_tree type
,
10809 bool named ATTRIBUTE_UNUSED
)
10811 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10813 if (TARGET_DEBUG_ARG
)
10814 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10821 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10823 if (TARGET_DEBUG_ARG
)
10824 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10828 if (int_size_in_bytes (type
) < 0)
10830 if (TARGET_DEBUG_ARG
)
10831 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10835 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10836 modes only exist for GCC vector types if -maltivec. */
10837 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10839 if (TARGET_DEBUG_ARG
)
10840 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10844 /* Pass synthetic vectors in memory. */
10845 if (TREE_CODE (type
) == VECTOR_TYPE
10846 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10848 static bool warned_for_pass_big_vectors
= false;
10849 if (TARGET_DEBUG_ARG
)
10850 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10851 if (!warned_for_pass_big_vectors
)
10853 warning (0, "GCC vector passed by reference: "
10854 "non-standard ABI extension with no compatibility guarantee");
10855 warned_for_pass_big_vectors
= true;
10863 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10864 already processes. Return true if the parameter must be passed
10865 (fully or partially) on the stack. */
10868 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10874 /* Catch errors. */
10875 if (type
== NULL
|| type
== error_mark_node
)
10878 /* Handle types with no storage requirement. */
10879 if (TYPE_MODE (type
) == VOIDmode
)
10882 /* Handle complex types. */
10883 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10884 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10885 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10887 /* Handle transparent aggregates. */
10888 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10889 && TYPE_TRANSPARENT_AGGR (type
))
10890 type
= TREE_TYPE (first_field (type
));
10892 /* See if this arg was passed by invisible reference. */
10893 if (pass_by_reference (get_cumulative_args (args_so_far
),
10894 TYPE_MODE (type
), type
, true))
10895 type
= build_pointer_type (type
);
10897 /* Find mode as it is passed by the ABI. */
10898 unsignedp
= TYPE_UNSIGNED (type
);
10899 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10901 /* If we must pass in stack, we need a stack. */
10902 if (rs6000_must_pass_in_stack (mode
, type
))
10905 /* If there is no incoming register, we need a stack. */
10906 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10907 if (entry_parm
== NULL
)
10910 /* Likewise if we need to pass both in registers and on the stack. */
10911 if (GET_CODE (entry_parm
) == PARALLEL
10912 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10915 /* Also true if we're partially in registers and partially not. */
10916 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10919 /* Update info on where next arg arrives in registers. */
10920 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10924 /* Return true if FUN has no prototype, has a variable argument
10925 list, or passes any parameter in memory. */
10928 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
10930 tree fntype
, result
;
10931 CUMULATIVE_ARGS args_so_far_v
;
10932 cumulative_args_t args_so_far
;
10935 /* Must be a libcall, all of which only use reg parms. */
10940 fntype
= TREE_TYPE (fun
);
10942 /* Varargs functions need the parameter save area. */
10943 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
10946 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
10947 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10949 /* When incoming, we will have been passed the function decl.
10950 It is necessary to use the decl to handle K&R style functions,
10951 where TYPE_ARG_TYPES may not be available. */
10954 gcc_assert (DECL_P (fun
));
10955 result
= DECL_RESULT (fun
);
10958 result
= TREE_TYPE (fntype
);
10960 if (result
&& aggregate_value_p (result
, fntype
))
10962 if (!TYPE_P (result
))
10963 result
= TREE_TYPE (result
);
10964 result
= build_pointer_type (result
);
10965 rs6000_parm_needs_stack (args_so_far
, result
);
10972 for (parm
= DECL_ARGUMENTS (fun
);
10973 parm
&& parm
!= void_list_node
;
10974 parm
= TREE_CHAIN (parm
))
10975 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
10980 function_args_iterator args_iter
;
10983 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
10984 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10991 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10992 usually a constant depending on the ABI. However, in the ELFv2 ABI
10993 the register parameter area is optional when calling a function that
10994 has a prototype is scope, has no variable argument list, and passes
10995 all parameters in registers. */
10998 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
11000 int reg_parm_stack_space
;
11002 switch (DEFAULT_ABI
)
11005 reg_parm_stack_space
= 0;
11010 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
11014 /* ??? Recomputing this every time is a bit expensive. Is there
11015 a place to cache this information? */
11016 if (rs6000_function_parms_need_stack (fun
, incoming
))
11017 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
11019 reg_parm_stack_space
= 0;
11023 return reg_parm_stack_space
;
11027 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
11030 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
11035 for (i
= 0; i
< nregs
; i
++)
11037 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
11038 if (reload_completed
)
11040 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
11043 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
11044 i
* GET_MODE_SIZE (reg_mode
));
11047 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
11051 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
11055 /* Perform any needed actions needed for a function that is receiving a
11056 variable number of arguments.
11060 MODE and TYPE are the mode and type of the current parameter.
11062 PRETEND_SIZE is a variable that should be set to the amount of stack
11063 that must be pushed by the prolog to pretend that our caller pushed
11066 Normally, this macro will push all remaining incoming registers on the
11067 stack and set PRETEND_SIZE to the length of the registers pushed. */
11070 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
11071 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
11074 CUMULATIVE_ARGS next_cum
;
11075 int reg_size
= TARGET_32BIT
? 4 : 8;
11076 rtx save_area
= NULL_RTX
, mem
;
11077 int first_reg_offset
;
11078 alias_set_type set
;
11080 /* Skip the last named argument. */
11081 next_cum
= *get_cumulative_args (cum
);
11082 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
11084 if (DEFAULT_ABI
== ABI_V4
)
11086 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
11090 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
11091 HOST_WIDE_INT offset
= 0;
11093 /* Try to optimize the size of the varargs save area.
11094 The ABI requires that ap.reg_save_area is doubleword
11095 aligned, but we don't need to allocate space for all
11096 the bytes, only those to which we actually will save
11098 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
11099 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
11100 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11101 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
11102 && cfun
->va_list_fpr_size
)
11105 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
11106 * UNITS_PER_FP_WORD
;
11107 if (cfun
->va_list_fpr_size
11108 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
11109 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
11111 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
11112 * UNITS_PER_FP_WORD
;
11116 offset
= -((first_reg_offset
* reg_size
) & ~7);
11117 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
11119 gpr_reg_num
= cfun
->va_list_gpr_size
;
11120 if (reg_size
== 4 && (first_reg_offset
& 1))
11123 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
11126 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
11127 * UNITS_PER_FP_WORD
11128 - (int) (GP_ARG_NUM_REG
* reg_size
);
11130 if (gpr_size
+ fpr_size
)
11133 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
11134 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
11135 reg_save_area
= XEXP (reg_save_area
, 0);
11136 if (GET_CODE (reg_save_area
) == PLUS
)
11138 gcc_assert (XEXP (reg_save_area
, 0)
11139 == virtual_stack_vars_rtx
);
11140 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
11141 offset
+= INTVAL (XEXP (reg_save_area
, 1));
11144 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
11147 cfun
->machine
->varargs_save_offset
= offset
;
11148 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
11153 first_reg_offset
= next_cum
.words
;
11154 save_area
= virtual_incoming_args_rtx
;
11156 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
11157 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
11160 set
= get_varargs_alias_set ();
11161 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
11162 && cfun
->va_list_gpr_size
)
11164 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
11166 if (va_list_gpr_counter_field
)
11167 /* V4 va_list_gpr_size counts number of registers needed. */
11168 n_gpr
= cfun
->va_list_gpr_size
;
11170 /* char * va_list instead counts number of bytes needed. */
11171 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
11176 mem
= gen_rtx_MEM (BLKmode
,
11177 plus_constant (Pmode
, save_area
,
11178 first_reg_offset
* reg_size
));
11179 MEM_NOTRAP_P (mem
) = 1;
11180 set_mem_alias_set (mem
, set
);
11181 set_mem_align (mem
, BITS_PER_WORD
);
11183 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
11187 /* Save FP registers if needed. */
11188 if (DEFAULT_ABI
== ABI_V4
11189 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11191 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
11192 && cfun
->va_list_fpr_size
)
11194 int fregno
= next_cum
.fregno
, nregs
;
11195 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
11196 rtx lab
= gen_label_rtx ();
11197 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
11198 * UNITS_PER_FP_WORD
);
11201 (gen_rtx_SET (pc_rtx
,
11202 gen_rtx_IF_THEN_ELSE (VOIDmode
,
11203 gen_rtx_NE (VOIDmode
, cr1
,
11205 gen_rtx_LABEL_REF (VOIDmode
, lab
),
11209 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
11210 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
11212 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11214 plus_constant (Pmode
, save_area
, off
));
11215 MEM_NOTRAP_P (mem
) = 1;
11216 set_mem_alias_set (mem
, set
);
11217 set_mem_align (mem
, GET_MODE_ALIGNMENT (
11218 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11219 ? DFmode
: SFmode
));
11220 emit_move_insn (mem
, gen_rtx_REG (
11221 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
11222 ? DFmode
: SFmode
, fregno
));
11229 /* Create the va_list data type. */
11232 rs6000_build_builtin_va_list (void)
11234 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
11236 /* For AIX, prefer 'char *' because that's what the system
11237 header files like. */
11238 if (DEFAULT_ABI
!= ABI_V4
)
11239 return build_pointer_type (char_type_node
);
11241 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
11242 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
11243 get_identifier ("__va_list_tag"), record
);
11245 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
11246 unsigned_char_type_node
);
11247 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
11248 unsigned_char_type_node
);
11249 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
11250 every user file. */
11251 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11252 get_identifier ("reserved"), short_unsigned_type_node
);
11253 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11254 get_identifier ("overflow_arg_area"),
11256 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
11257 get_identifier ("reg_save_area"),
11260 va_list_gpr_counter_field
= f_gpr
;
11261 va_list_fpr_counter_field
= f_fpr
;
11263 DECL_FIELD_CONTEXT (f_gpr
) = record
;
11264 DECL_FIELD_CONTEXT (f_fpr
) = record
;
11265 DECL_FIELD_CONTEXT (f_res
) = record
;
11266 DECL_FIELD_CONTEXT (f_ovf
) = record
;
11267 DECL_FIELD_CONTEXT (f_sav
) = record
;
11269 TYPE_STUB_DECL (record
) = type_decl
;
11270 TYPE_NAME (record
) = type_decl
;
11271 TYPE_FIELDS (record
) = f_gpr
;
11272 DECL_CHAIN (f_gpr
) = f_fpr
;
11273 DECL_CHAIN (f_fpr
) = f_res
;
11274 DECL_CHAIN (f_res
) = f_ovf
;
11275 DECL_CHAIN (f_ovf
) = f_sav
;
11277 layout_type (record
);
11279 /* The correct type is an array type of one element. */
11280 return build_array_type (record
, build_index_type (size_zero_node
));
11283 /* Implement va_start. */
11286 rs6000_va_start (tree valist
, rtx nextarg
)
11288 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
11289 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11290 tree gpr
, fpr
, ovf
, sav
, t
;
11292 /* Only SVR4 needs something special. */
11293 if (DEFAULT_ABI
!= ABI_V4
)
11295 std_expand_builtin_va_start (valist
, nextarg
);
11299 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11300 f_fpr
= DECL_CHAIN (f_gpr
);
11301 f_res
= DECL_CHAIN (f_fpr
);
11302 f_ovf
= DECL_CHAIN (f_res
);
11303 f_sav
= DECL_CHAIN (f_ovf
);
11305 valist
= build_simple_mem_ref (valist
);
11306 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11307 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11309 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11311 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11314 /* Count number of gp and fp argument registers used. */
11315 words
= crtl
->args
.info
.words
;
11316 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
11318 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
11321 if (TARGET_DEBUG_ARG
)
11322 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
11323 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
11324 words
, n_gpr
, n_fpr
);
11326 if (cfun
->va_list_gpr_size
)
11328 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
11329 build_int_cst (NULL_TREE
, n_gpr
));
11330 TREE_SIDE_EFFECTS (t
) = 1;
11331 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11334 if (cfun
->va_list_fpr_size
)
11336 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
11337 build_int_cst (NULL_TREE
, n_fpr
));
11338 TREE_SIDE_EFFECTS (t
) = 1;
11339 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11341 #ifdef HAVE_AS_GNU_ATTRIBUTE
11342 if (call_ABI_of_interest (cfun
->decl
))
11343 rs6000_passes_float
= true;
11347 /* Find the overflow area. */
11348 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
11350 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
11351 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
11352 TREE_SIDE_EFFECTS (t
) = 1;
11353 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11355 /* If there were no va_arg invocations, don't set up the register
11357 if (!cfun
->va_list_gpr_size
11358 && !cfun
->va_list_fpr_size
11359 && n_gpr
< GP_ARG_NUM_REG
11360 && n_fpr
< FP_ARG_V4_MAX_REG
)
11363 /* Find the register save area. */
11364 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
11365 if (cfun
->machine
->varargs_save_offset
)
11366 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
11367 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
11368 TREE_SIDE_EFFECTS (t
) = 1;
11369 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11372 /* Implement va_arg. */
11375 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
11376 gimple_seq
*post_p
)
11378 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
11379 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
11380 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
11381 tree lab_false
, lab_over
, addr
;
11383 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
11387 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
11389 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
11390 return build_va_arg_indirect_ref (t
);
11393 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
11394 earlier version of gcc, with the property that it always applied alignment
11395 adjustments to the va-args (even for zero-sized types). The cheapest way
11396 to deal with this is to replicate the effect of the part of
11397 std_gimplify_va_arg_expr that carries out the align adjust, for the case
11399 We don't need to check for pass-by-reference because of the test above.
11400 We can return a simplifed answer, since we know there's no offset to add. */
11403 && rs6000_darwin64_abi
)
11404 || DEFAULT_ABI
== ABI_ELFv2
11405 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
11406 && integer_zerop (TYPE_SIZE (type
)))
11408 unsigned HOST_WIDE_INT align
, boundary
;
11409 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
11410 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
11411 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
11412 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
11413 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
11414 boundary
/= BITS_PER_UNIT
;
11415 if (boundary
> align
)
11418 /* This updates arg ptr by the amount that would be necessary
11419 to align the zero-sized (but not zero-alignment) item. */
11420 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11421 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
11422 gimplify_and_add (t
, pre_p
);
11424 t
= fold_convert (sizetype
, valist_tmp
);
11425 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
11426 fold_convert (TREE_TYPE (valist
),
11427 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
11428 size_int (-boundary
))));
11429 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
11430 gimplify_and_add (t
, pre_p
);
11432 /* Since it is zero-sized there's no increment for the item itself. */
11433 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
11434 return build_va_arg_indirect_ref (valist_tmp
);
11437 if (DEFAULT_ABI
!= ABI_V4
)
11439 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
11441 tree elem_type
= TREE_TYPE (type
);
11442 machine_mode elem_mode
= TYPE_MODE (elem_type
);
11443 int elem_size
= GET_MODE_SIZE (elem_mode
);
11445 if (elem_size
< UNITS_PER_WORD
)
11447 tree real_part
, imag_part
;
11448 gimple_seq post
= NULL
;
11450 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11452 /* Copy the value into a temporary, lest the formal temporary
11453 be reused out from under us. */
11454 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
11455 gimple_seq_add_seq (pre_p
, post
);
11457 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
11460 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
11464 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
11467 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11468 f_fpr
= DECL_CHAIN (f_gpr
);
11469 f_res
= DECL_CHAIN (f_fpr
);
11470 f_ovf
= DECL_CHAIN (f_res
);
11471 f_sav
= DECL_CHAIN (f_ovf
);
11473 valist
= build_va_arg_indirect_ref (valist
);
11474 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11475 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
11477 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
11479 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
11482 size
= int_size_in_bytes (type
);
11483 rsize
= (size
+ 3) / 4;
11486 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
11487 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
11488 || (TARGET_DOUBLE_FLOAT
11489 && (TYPE_MODE (type
) == DFmode
11490 || TYPE_MODE (type
) == TFmode
11491 || TYPE_MODE (type
) == SDmode
11492 || TYPE_MODE (type
) == DDmode
11493 || TYPE_MODE (type
) == TDmode
))))
11495 /* FP args go in FP registers, if present. */
11497 n_reg
= (size
+ 7) / 8;
11498 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
11499 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
11500 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
11505 /* Otherwise into GP registers. */
11514 /* Pull the value out of the saved registers.... */
11517 addr
= create_tmp_var (ptr_type_node
, "addr");
11519 /* AltiVec vectors never go in registers when -mabi=altivec. */
11520 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11524 lab_false
= create_artificial_label (input_location
);
11525 lab_over
= create_artificial_label (input_location
);
11527 /* Long long and SPE vectors are aligned in the registers.
11528 As are any other 2 gpr item such as complex int due to a
11529 historical mistake. */
11531 if (n_reg
== 2 && reg
== gpr
)
11534 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11535 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
11536 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
11537 unshare_expr (reg
), u
);
11539 /* _Decimal128 is passed in even/odd fpr pairs; the stored
11540 reg number is 0 for f1, so we want to make it odd. */
11541 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
11543 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11544 build_int_cst (TREE_TYPE (reg
), 1));
11545 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
11548 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
11549 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
11550 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11551 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11552 gimplify_and_add (t
, pre_p
);
11556 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11558 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
11559 build_int_cst (TREE_TYPE (reg
), n_reg
));
11560 u
= fold_convert (sizetype
, u
);
11561 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
11562 t
= fold_build_pointer_plus (t
, u
);
11564 /* _Decimal32 varargs are located in the second word of the 64-bit
11565 FP register for 32-bit binaries. */
11567 && TARGET_HARD_FLOAT
&& TARGET_FPRS
11568 && TYPE_MODE (type
) == SDmode
)
11569 t
= fold_build_pointer_plus_hwi (t
, size
);
11571 gimplify_assign (addr
, t
, pre_p
);
11573 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11575 stmt
= gimple_build_label (lab_false
);
11576 gimple_seq_add_stmt (pre_p
, stmt
);
11578 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
11580 /* Ensure that we don't find any more args in regs.
11581 Alignment has taken care of for special cases. */
11582 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
11586 /* ... otherwise out of the overflow area. */
11588 /* Care for on-stack alignment if needed. */
11592 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
11593 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
11594 build_int_cst (TREE_TYPE (t
), -align
));
11596 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11598 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
11600 t
= fold_build_pointer_plus_hwi (t
, size
);
11601 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
11605 stmt
= gimple_build_label (lab_over
);
11606 gimple_seq_add_stmt (pre_p
, stmt
);
11609 if (STRICT_ALIGNMENT
11610 && (TYPE_ALIGN (type
)
11611 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11613 /* The value (of type complex double, for example) may not be
11614 aligned in memory in the saved registers, so copy via a
11615 temporary. (This is the same code as used for SPARC.) */
11616 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11617 tree dest_addr
= build_fold_addr_expr (tmp
);
11619 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11620 3, dest_addr
, addr
, size_int (rsize
* 4));
11622 gimplify_and_add (copy
, pre_p
);
11626 addr
= fold_convert (ptrtype
, addr
);
11627 return build_va_arg_indirect_ref (addr
);
11633 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11636 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11637 const char *attr_string
= "";
11639 gcc_assert (name
!= NULL
);
11640 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11642 if (rs6000_builtin_decls
[(int)code
])
11643 fatal_error (input_location
,
11644 "internal error: builtin function %s already processed", name
);
11646 rs6000_builtin_decls
[(int)code
] = t
=
11647 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11649 /* Set any special attributes. */
11650 if ((classify
& RS6000_BTC_CONST
) != 0)
11652 /* const function, function only depends on the inputs. */
11653 TREE_READONLY (t
) = 1;
11654 TREE_NOTHROW (t
) = 1;
11655 attr_string
= ", pure";
11657 else if ((classify
& RS6000_BTC_PURE
) != 0)
11659 /* pure function, function can read global memory, but does not set any
11661 DECL_PURE_P (t
) = 1;
11662 TREE_NOTHROW (t
) = 1;
11663 attr_string
= ", const";
11665 else if ((classify
& RS6000_BTC_FP
) != 0)
11667 /* Function is a math function. If rounding mode is on, then treat the
11668 function as not reading global memory, but it can have arbitrary side
11669 effects. If it is off, then assume the function is a const function.
11670 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11671 builtin-attribute.def that is used for the math functions. */
11672 TREE_NOTHROW (t
) = 1;
11673 if (flag_rounding_math
)
11675 DECL_PURE_P (t
) = 1;
11676 DECL_IS_NOVOPS (t
) = 1;
11677 attr_string
= ", fp, pure";
11681 TREE_READONLY (t
) = 1;
11682 attr_string
= ", fp, const";
11685 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11686 gcc_unreachable ();
11688 if (TARGET_DEBUG_BUILTIN
)
11689 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11690 (int)code
, name
, attr_string
);
11693 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11695 #undef RS6000_BUILTIN_1
11696 #undef RS6000_BUILTIN_2
11697 #undef RS6000_BUILTIN_3
11698 #undef RS6000_BUILTIN_A
11699 #undef RS6000_BUILTIN_D
11700 #undef RS6000_BUILTIN_E
11701 #undef RS6000_BUILTIN_H
11702 #undef RS6000_BUILTIN_P
11703 #undef RS6000_BUILTIN_Q
11704 #undef RS6000_BUILTIN_S
11705 #undef RS6000_BUILTIN_X
11707 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11708 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11709 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11710 { MASK, ICODE, NAME, ENUM },
11712 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11713 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11714 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11715 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11716 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11717 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11718 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11719 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11721 static const struct builtin_description bdesc_3arg
[] =
11723 #include "rs6000-builtin.def"
11726 /* DST operations: void foo (void *, const int, const char). */
11728 #undef RS6000_BUILTIN_1
11729 #undef RS6000_BUILTIN_2
11730 #undef RS6000_BUILTIN_3
11731 #undef RS6000_BUILTIN_A
11732 #undef RS6000_BUILTIN_D
11733 #undef RS6000_BUILTIN_E
11734 #undef RS6000_BUILTIN_H
11735 #undef RS6000_BUILTIN_P
11736 #undef RS6000_BUILTIN_Q
11737 #undef RS6000_BUILTIN_S
11738 #undef RS6000_BUILTIN_X
11740 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11741 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11742 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11743 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11744 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11745 { MASK, ICODE, NAME, ENUM },
11747 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11748 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11749 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11750 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11751 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11752 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11754 static const struct builtin_description bdesc_dst
[] =
11756 #include "rs6000-builtin.def"
11759 /* Simple binary operations: VECc = foo (VECa, VECb). */
11761 #undef RS6000_BUILTIN_1
11762 #undef RS6000_BUILTIN_2
11763 #undef RS6000_BUILTIN_3
11764 #undef RS6000_BUILTIN_A
11765 #undef RS6000_BUILTIN_D
11766 #undef RS6000_BUILTIN_E
11767 #undef RS6000_BUILTIN_H
11768 #undef RS6000_BUILTIN_P
11769 #undef RS6000_BUILTIN_Q
11770 #undef RS6000_BUILTIN_S
11771 #undef RS6000_BUILTIN_X
11773 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11774 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11775 { MASK, ICODE, NAME, ENUM },
11777 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11778 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11779 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11780 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11781 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11782 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11783 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11784 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11785 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11787 static const struct builtin_description bdesc_2arg
[] =
11789 #include "rs6000-builtin.def"
11792 #undef RS6000_BUILTIN_1
11793 #undef RS6000_BUILTIN_2
11794 #undef RS6000_BUILTIN_3
11795 #undef RS6000_BUILTIN_A
11796 #undef RS6000_BUILTIN_D
11797 #undef RS6000_BUILTIN_E
11798 #undef RS6000_BUILTIN_H
11799 #undef RS6000_BUILTIN_P
11800 #undef RS6000_BUILTIN_Q
11801 #undef RS6000_BUILTIN_S
11802 #undef RS6000_BUILTIN_X
11804 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11805 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11806 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11807 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11808 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11809 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11810 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11811 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11812 { MASK, ICODE, NAME, ENUM },
11814 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11815 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11816 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11818 /* AltiVec predicates. */
11820 static const struct builtin_description bdesc_altivec_preds
[] =
11822 #include "rs6000-builtin.def"
11825 /* SPE predicates. */
11826 #undef RS6000_BUILTIN_1
11827 #undef RS6000_BUILTIN_2
11828 #undef RS6000_BUILTIN_3
11829 #undef RS6000_BUILTIN_A
11830 #undef RS6000_BUILTIN_D
11831 #undef RS6000_BUILTIN_E
11832 #undef RS6000_BUILTIN_H
11833 #undef RS6000_BUILTIN_P
11834 #undef RS6000_BUILTIN_Q
11835 #undef RS6000_BUILTIN_S
11836 #undef RS6000_BUILTIN_X
11838 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11839 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11840 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11841 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11842 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11843 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11844 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11845 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11846 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11847 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11848 { MASK, ICODE, NAME, ENUM },
11850 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11852 static const struct builtin_description bdesc_spe_predicates
[] =
11854 #include "rs6000-builtin.def"
11857 /* SPE evsel predicates. */
11858 #undef RS6000_BUILTIN_1
11859 #undef RS6000_BUILTIN_2
11860 #undef RS6000_BUILTIN_3
11861 #undef RS6000_BUILTIN_A
11862 #undef RS6000_BUILTIN_D
11863 #undef RS6000_BUILTIN_E
11864 #undef RS6000_BUILTIN_H
11865 #undef RS6000_BUILTIN_P
11866 #undef RS6000_BUILTIN_Q
11867 #undef RS6000_BUILTIN_S
11868 #undef RS6000_BUILTIN_X
11870 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11871 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11872 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11873 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11874 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11875 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11876 { MASK, ICODE, NAME, ENUM },
11878 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11879 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11880 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11881 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11882 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11884 static const struct builtin_description bdesc_spe_evsel
[] =
11886 #include "rs6000-builtin.def"
11889 /* PAIRED predicates. */
11890 #undef RS6000_BUILTIN_1
11891 #undef RS6000_BUILTIN_2
11892 #undef RS6000_BUILTIN_3
11893 #undef RS6000_BUILTIN_A
11894 #undef RS6000_BUILTIN_D
11895 #undef RS6000_BUILTIN_E
11896 #undef RS6000_BUILTIN_H
11897 #undef RS6000_BUILTIN_P
11898 #undef RS6000_BUILTIN_Q
11899 #undef RS6000_BUILTIN_S
11900 #undef RS6000_BUILTIN_X
11902 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11903 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11904 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11905 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11906 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11907 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11908 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11909 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11910 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11911 { MASK, ICODE, NAME, ENUM },
11913 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11914 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11916 static const struct builtin_description bdesc_paired_preds
[] =
11918 #include "rs6000-builtin.def"
11921 /* ABS* operations. */
11923 #undef RS6000_BUILTIN_1
11924 #undef RS6000_BUILTIN_2
11925 #undef RS6000_BUILTIN_3
11926 #undef RS6000_BUILTIN_A
11927 #undef RS6000_BUILTIN_D
11928 #undef RS6000_BUILTIN_E
11929 #undef RS6000_BUILTIN_H
11930 #undef RS6000_BUILTIN_P
11931 #undef RS6000_BUILTIN_Q
11932 #undef RS6000_BUILTIN_S
11933 #undef RS6000_BUILTIN_X
11935 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11936 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11937 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11938 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11939 { MASK, ICODE, NAME, ENUM },
11941 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11942 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11943 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11944 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11945 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11946 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11947 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11949 static const struct builtin_description bdesc_abs
[] =
11951 #include "rs6000-builtin.def"
11954 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11957 #undef RS6000_BUILTIN_1
11958 #undef RS6000_BUILTIN_2
11959 #undef RS6000_BUILTIN_3
11960 #undef RS6000_BUILTIN_A
11961 #undef RS6000_BUILTIN_D
11962 #undef RS6000_BUILTIN_E
11963 #undef RS6000_BUILTIN_H
11964 #undef RS6000_BUILTIN_P
11965 #undef RS6000_BUILTIN_Q
11966 #undef RS6000_BUILTIN_S
11967 #undef RS6000_BUILTIN_X
11969 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11970 { MASK, ICODE, NAME, ENUM },
11972 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11973 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11974 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11975 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11976 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11977 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11978 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11979 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11980 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11981 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11983 static const struct builtin_description bdesc_1arg
[] =
11985 #include "rs6000-builtin.def"
11988 /* HTM builtins. */
11989 #undef RS6000_BUILTIN_1
11990 #undef RS6000_BUILTIN_2
11991 #undef RS6000_BUILTIN_3
11992 #undef RS6000_BUILTIN_A
11993 #undef RS6000_BUILTIN_D
11994 #undef RS6000_BUILTIN_E
11995 #undef RS6000_BUILTIN_H
11996 #undef RS6000_BUILTIN_P
11997 #undef RS6000_BUILTIN_Q
11998 #undef RS6000_BUILTIN_S
11999 #undef RS6000_BUILTIN_X
12001 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12002 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12003 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12004 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12005 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12006 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
12007 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12008 { MASK, ICODE, NAME, ENUM },
12010 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12011 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
12012 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
12013 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12015 static const struct builtin_description bdesc_htm
[] =
12017 #include "rs6000-builtin.def"
12020 #undef RS6000_BUILTIN_1
12021 #undef RS6000_BUILTIN_2
12022 #undef RS6000_BUILTIN_3
12023 #undef RS6000_BUILTIN_A
12024 #undef RS6000_BUILTIN_D
12025 #undef RS6000_BUILTIN_E
12026 #undef RS6000_BUILTIN_H
12027 #undef RS6000_BUILTIN_P
12028 #undef RS6000_BUILTIN_Q
12029 #undef RS6000_BUILTIN_S
12031 /* Return true if a builtin function is overloaded. */
12033 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
12035 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
12038 /* Expand an expression EXP that calls a builtin without arguments. */
12040 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
12043 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12045 if (icode
== CODE_FOR_nothing
)
12046 /* Builtin not supported on this processor. */
12050 || GET_MODE (target
) != tmode
12051 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12052 target
= gen_reg_rtx (tmode
);
12054 pat
= GEN_FCN (icode
) (target
);
12064 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
12067 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12068 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12069 rtx op0
= expand_normal (arg0
);
12070 rtx op1
= expand_normal (arg1
);
12071 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12072 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12074 if (icode
== CODE_FOR_nothing
)
12075 /* Builtin not supported on this processor. */
12078 /* If we got invalid arguments bail out before generating bad rtl. */
12079 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12082 if (GET_CODE (op0
) != CONST_INT
12083 || INTVAL (op0
) > 255
12084 || INTVAL (op0
) < 0)
12086 error ("argument 1 must be an 8-bit field value");
12090 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12091 op0
= copy_to_mode_reg (mode0
, op0
);
12093 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12094 op1
= copy_to_mode_reg (mode1
, op1
);
12096 pat
= GEN_FCN (icode
) (op0
, op1
);
12106 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12109 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12110 rtx op0
= expand_normal (arg0
);
12111 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12112 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12114 if (icode
== CODE_FOR_nothing
)
12115 /* Builtin not supported on this processor. */
12118 /* If we got invalid arguments bail out before generating bad rtl. */
12119 if (arg0
== error_mark_node
)
12122 if (icode
== CODE_FOR_altivec_vspltisb
12123 || icode
== CODE_FOR_altivec_vspltish
12124 || icode
== CODE_FOR_altivec_vspltisw
12125 || icode
== CODE_FOR_spe_evsplatfi
12126 || icode
== CODE_FOR_spe_evsplati
)
12128 /* Only allow 5-bit *signed* literals. */
12129 if (GET_CODE (op0
) != CONST_INT
12130 || INTVAL (op0
) > 15
12131 || INTVAL (op0
) < -16)
12133 error ("argument 1 must be a 5-bit signed literal");
12139 || GET_MODE (target
) != tmode
12140 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12141 target
= gen_reg_rtx (tmode
);
12143 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12144 op0
= copy_to_mode_reg (mode0
, op0
);
12146 pat
= GEN_FCN (icode
) (target
, op0
);
12155 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
12157 rtx pat
, scratch1
, scratch2
;
12158 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12159 rtx op0
= expand_normal (arg0
);
12160 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12161 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12163 /* If we have invalid arguments, bail out before generating bad rtl. */
12164 if (arg0
== error_mark_node
)
12168 || GET_MODE (target
) != tmode
12169 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12170 target
= gen_reg_rtx (tmode
);
12172 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12173 op0
= copy_to_mode_reg (mode0
, op0
);
12175 scratch1
= gen_reg_rtx (mode0
);
12176 scratch2
= gen_reg_rtx (mode0
);
12178 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
12187 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12190 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12191 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12192 rtx op0
= expand_normal (arg0
);
12193 rtx op1
= expand_normal (arg1
);
12194 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12195 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12196 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12198 if (icode
== CODE_FOR_nothing
)
12199 /* Builtin not supported on this processor. */
12202 /* If we got invalid arguments bail out before generating bad rtl. */
12203 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12206 if (icode
== CODE_FOR_altivec_vcfux
12207 || icode
== CODE_FOR_altivec_vcfsx
12208 || icode
== CODE_FOR_altivec_vctsxs
12209 || icode
== CODE_FOR_altivec_vctuxs
12210 || icode
== CODE_FOR_altivec_vspltb
12211 || icode
== CODE_FOR_altivec_vsplth
12212 || icode
== CODE_FOR_altivec_vspltw
12213 || icode
== CODE_FOR_spe_evaddiw
12214 || icode
== CODE_FOR_spe_evldd
12215 || icode
== CODE_FOR_spe_evldh
12216 || icode
== CODE_FOR_spe_evldw
12217 || icode
== CODE_FOR_spe_evlhhesplat
12218 || icode
== CODE_FOR_spe_evlhhossplat
12219 || icode
== CODE_FOR_spe_evlhhousplat
12220 || icode
== CODE_FOR_spe_evlwhe
12221 || icode
== CODE_FOR_spe_evlwhos
12222 || icode
== CODE_FOR_spe_evlwhou
12223 || icode
== CODE_FOR_spe_evlwhsplat
12224 || icode
== CODE_FOR_spe_evlwwsplat
12225 || icode
== CODE_FOR_spe_evrlwi
12226 || icode
== CODE_FOR_spe_evslwi
12227 || icode
== CODE_FOR_spe_evsrwis
12228 || icode
== CODE_FOR_spe_evsubifw
12229 || icode
== CODE_FOR_spe_evsrwiu
)
12231 /* Only allow 5-bit unsigned literals. */
12233 if (TREE_CODE (arg1
) != INTEGER_CST
12234 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
12236 error ("argument 2 must be a 5-bit unsigned literal");
12242 || GET_MODE (target
) != tmode
12243 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12244 target
= gen_reg_rtx (tmode
);
12246 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12247 op0
= copy_to_mode_reg (mode0
, op0
);
12248 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12249 op1
= copy_to_mode_reg (mode1
, op1
);
12251 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12260 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12263 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
12264 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12265 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12266 rtx op0
= expand_normal (arg0
);
12267 rtx op1
= expand_normal (arg1
);
12268 machine_mode tmode
= SImode
;
12269 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12270 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12273 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
12275 error ("argument 1 of __builtin_altivec_predicate must be a constant");
12279 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
12281 gcc_assert (mode0
== mode1
);
12283 /* If we have invalid arguments, bail out before generating bad rtl. */
12284 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12288 || GET_MODE (target
) != tmode
12289 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12290 target
= gen_reg_rtx (tmode
);
12292 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12293 op0
= copy_to_mode_reg (mode0
, op0
);
12294 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12295 op1
= copy_to_mode_reg (mode1
, op1
);
12297 scratch
= gen_reg_rtx (mode0
);
12299 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12304 /* The vec_any* and vec_all* predicates use the same opcodes for two
12305 different operations, but the bits in CR6 will be different
12306 depending on what information we want. So we have to play tricks
12307 with CR6 to get the right bits out.
12309 If you think this is disgusting, look at the specs for the
12310 AltiVec predicates. */
12312 switch (cr6_form_int
)
12315 emit_insn (gen_cr6_test_for_zero (target
));
12318 emit_insn (gen_cr6_test_for_zero_reverse (target
));
12321 emit_insn (gen_cr6_test_for_lt (target
));
12324 emit_insn (gen_cr6_test_for_lt_reverse (target
));
12327 error ("argument 1 of __builtin_altivec_predicate is out of range");
12335 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
12338 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12339 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12340 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12341 machine_mode mode0
= Pmode
;
12342 machine_mode mode1
= Pmode
;
12343 rtx op0
= expand_normal (arg0
);
12344 rtx op1
= expand_normal (arg1
);
12346 if (icode
== CODE_FOR_nothing
)
12347 /* Builtin not supported on this processor. */
12350 /* If we got invalid arguments bail out before generating bad rtl. */
12351 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12355 || GET_MODE (target
) != tmode
12356 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12357 target
= gen_reg_rtx (tmode
);
12359 op1
= copy_to_mode_reg (mode1
, op1
);
12361 if (op0
== const0_rtx
)
12363 addr
= gen_rtx_MEM (tmode
, op1
);
12367 op0
= copy_to_mode_reg (mode0
, op0
);
12368 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12371 pat
= GEN_FCN (icode
) (target
, addr
);
12380 /* Return a constant vector for use as a little-endian permute control vector
12381 to reverse the order of elements of the given vector mode. */
12383 swap_selector_for_mode (machine_mode mode
)
12385 /* These are little endian vectors, so their elements are reversed
12386 from what you would normally expect for a permute control vector. */
12387 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
12388 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
12389 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
12390 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
12391 unsigned int *swaparray
, i
;
12408 swaparray
= swap16
;
12411 gcc_unreachable ();
12414 for (i
= 0; i
< 16; ++i
)
12415 perm
[i
] = GEN_INT (swaparray
[i
]);
12417 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
12420 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
12421 with -maltivec=be specified. Issue the load followed by an element-reversing
12424 altivec_expand_lvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12426 rtx tmp
= gen_reg_rtx (mode
);
12427 rtx load
= gen_rtx_SET (tmp
, op1
);
12428 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12429 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
12430 rtx sel
= swap_selector_for_mode (mode
);
12431 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
12433 gcc_assert (REG_P (op0
));
12435 emit_insn (gen_rtx_SET (op0
, vperm
));
12438 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
12439 with -maltivec=be specified. Issue the store preceded by an element-reversing
12442 altivec_expand_stvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12444 rtx tmp
= gen_reg_rtx (mode
);
12445 rtx store
= gen_rtx_SET (op0
, tmp
);
12446 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
12447 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
12448 rtx sel
= swap_selector_for_mode (mode
);
12451 gcc_assert (REG_P (op1
));
12452 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12453 emit_insn (gen_rtx_SET (tmp
, vperm
));
12457 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
12458 specified. Issue the store preceded by an element-reversing permute. */
12460 altivec_expand_stvex_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
12462 machine_mode inner_mode
= GET_MODE_INNER (mode
);
12463 rtx tmp
= gen_reg_rtx (mode
);
12464 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
12465 rtx sel
= swap_selector_for_mode (mode
);
12468 gcc_assert (REG_P (op1
));
12469 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
12470 emit_insn (gen_rtx_SET (tmp
, vperm
));
12471 emit_insn (gen_rtx_SET (op0
, stvx
));
12475 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
12478 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12479 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12480 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12481 machine_mode mode0
= Pmode
;
12482 machine_mode mode1
= Pmode
;
12483 rtx op0
= expand_normal (arg0
);
12484 rtx op1
= expand_normal (arg1
);
12486 if (icode
== CODE_FOR_nothing
)
12487 /* Builtin not supported on this processor. */
12490 /* If we got invalid arguments bail out before generating bad rtl. */
12491 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12495 || GET_MODE (target
) != tmode
12496 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12497 target
= gen_reg_rtx (tmode
);
12499 op1
= copy_to_mode_reg (mode1
, op1
);
12501 if (op0
== const0_rtx
)
12503 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
12507 op0
= copy_to_mode_reg (mode0
, op0
);
12508 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
12511 pat
= GEN_FCN (icode
) (target
, addr
);
12521 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
12523 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12524 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12525 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12526 rtx op0
= expand_normal (arg0
);
12527 rtx op1
= expand_normal (arg1
);
12528 rtx op2
= expand_normal (arg2
);
12530 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12531 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12532 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
12534 /* Invalid arguments. Bail before doing anything stoopid! */
12535 if (arg0
== error_mark_node
12536 || arg1
== error_mark_node
12537 || arg2
== error_mark_node
)
12540 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
12541 op0
= copy_to_mode_reg (mode2
, op0
);
12542 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
12543 op1
= copy_to_mode_reg (mode0
, op1
);
12544 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
12545 op2
= copy_to_mode_reg (mode1
, op2
);
12547 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
12554 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
12556 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12557 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12558 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12559 rtx op0
= expand_normal (arg0
);
12560 rtx op1
= expand_normal (arg1
);
12561 rtx op2
= expand_normal (arg2
);
12563 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12564 machine_mode mode1
= Pmode
;
12565 machine_mode mode2
= Pmode
;
12567 /* Invalid arguments. Bail before doing anything stoopid! */
12568 if (arg0
== error_mark_node
12569 || arg1
== error_mark_node
12570 || arg2
== error_mark_node
)
12573 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
12574 op0
= copy_to_mode_reg (tmode
, op0
);
12576 op2
= copy_to_mode_reg (mode2
, op2
);
12578 if (op1
== const0_rtx
)
12580 addr
= gen_rtx_MEM (tmode
, op2
);
12584 op1
= copy_to_mode_reg (mode1
, op1
);
12585 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12588 pat
= GEN_FCN (icode
) (addr
, op0
);
12595 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
12597 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12598 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12599 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12600 rtx op0
= expand_normal (arg0
);
12601 rtx op1
= expand_normal (arg1
);
12602 rtx op2
= expand_normal (arg2
);
12604 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12605 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
12606 machine_mode mode1
= Pmode
;
12607 machine_mode mode2
= Pmode
;
12609 /* Invalid arguments. Bail before doing anything stoopid! */
12610 if (arg0
== error_mark_node
12611 || arg1
== error_mark_node
12612 || arg2
== error_mark_node
)
12615 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
12616 op0
= copy_to_mode_reg (smode
, op0
);
12618 op2
= copy_to_mode_reg (mode2
, op2
);
12620 if (op1
== const0_rtx
)
12622 addr
= gen_rtx_MEM (tmode
, op2
);
12626 op1
= copy_to_mode_reg (mode1
, op1
);
12627 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
12630 pat
= GEN_FCN (icode
) (addr
, op0
);
12636 /* Return the appropriate SPR number associated with the given builtin. */
12637 static inline HOST_WIDE_INT
12638 htm_spr_num (enum rs6000_builtins code
)
12640 if (code
== HTM_BUILTIN_GET_TFHAR
12641 || code
== HTM_BUILTIN_SET_TFHAR
)
12643 else if (code
== HTM_BUILTIN_GET_TFIAR
12644 || code
== HTM_BUILTIN_SET_TFIAR
)
12646 else if (code
== HTM_BUILTIN_GET_TEXASR
12647 || code
== HTM_BUILTIN_SET_TEXASR
)
12649 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
12650 || code
== HTM_BUILTIN_SET_TEXASRU
);
12651 return TEXASRU_SPR
;
12654 /* Return the appropriate SPR regno associated with the given builtin. */
12655 static inline HOST_WIDE_INT
12656 htm_spr_regno (enum rs6000_builtins code
)
12658 if (code
== HTM_BUILTIN_GET_TFHAR
12659 || code
== HTM_BUILTIN_SET_TFHAR
)
12660 return TFHAR_REGNO
;
12661 else if (code
== HTM_BUILTIN_GET_TFIAR
12662 || code
== HTM_BUILTIN_SET_TFIAR
)
12663 return TFIAR_REGNO
;
12664 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
12665 || code
== HTM_BUILTIN_SET_TEXASR
12666 || code
== HTM_BUILTIN_GET_TEXASRU
12667 || code
== HTM_BUILTIN_SET_TEXASRU
);
12668 return TEXASR_REGNO
;
12671 /* Return the correct ICODE value depending on whether we are
12672 setting or reading the HTM SPRs. */
12673 static inline enum insn_code
12674 rs6000_htm_spr_icode (bool nonvoid
)
12677 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
12679 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
12682 /* Expand the HTM builtin in EXP and store the result in TARGET.
12683 Store true in *EXPANDEDP if we found a builtin to expand. */
12685 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12687 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12688 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
12689 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12690 const struct builtin_description
*d
;
12695 if (!TARGET_POWERPC64
12696 && (fcode
== HTM_BUILTIN_TABORTDC
12697 || fcode
== HTM_BUILTIN_TABORTDCI
))
12699 size_t uns_fcode
= (size_t)fcode
;
12700 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
12701 error ("builtin %s is only valid in 64-bit mode", name
);
12705 /* Expand the HTM builtins. */
12707 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
12708 if (d
->code
== fcode
)
12710 rtx op
[MAX_HTM_OPERANDS
], pat
;
12713 call_expr_arg_iterator iter
;
12714 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
12715 enum insn_code icode
= d
->icode
;
12716 const struct insn_operand_data
*insn_op
;
12717 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
12721 icode
= rs6000_htm_spr_icode (nonvoid
);
12722 insn_op
= &insn_data
[icode
].operand
[0];
12726 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: SImode
;
12728 || GET_MODE (target
) != tmode
12729 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
12730 target
= gen_reg_rtx (tmode
);
12732 op
[nopnds
++] = target
;
12735 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
12737 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
12740 insn_op
= &insn_data
[icode
].operand
[nopnds
];
12742 op
[nopnds
] = expand_normal (arg
);
12744 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
12746 if (!strcmp (insn_op
->constraint
, "n"))
12748 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
12749 if (!CONST_INT_P (op
[nopnds
]))
12750 error ("argument %d must be an unsigned literal", arg_num
);
12752 error ("argument %d is an unsigned literal that is "
12753 "out of range", arg_num
);
12756 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12762 /* Handle the builtins for extended mnemonics. These accept
12763 no arguments, but map to builtins that take arguments. */
12766 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12767 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12768 op
[nopnds
++] = GEN_INT (1);
12769 #ifdef ENABLE_CHECKING
12770 attr
|= RS6000_BTC_UNARY
;
12773 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12774 op
[nopnds
++] = GEN_INT (0);
12775 #ifdef ENABLE_CHECKING
12776 attr
|= RS6000_BTC_UNARY
;
12783 /* If this builtin accesses SPRs, then pass in the appropriate
12784 SPR number and SPR regno as the last two operands. */
12787 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
12788 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
12789 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
12791 /* If this builtin accesses a CR, then pass in a scratch
12792 CR as the last operand. */
12793 else if (attr
& RS6000_BTC_CR
)
12794 { cr
= gen_reg_rtx (CCmode
);
12798 #ifdef ENABLE_CHECKING
12799 int expected_nopnds
= 0;
12800 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12801 expected_nopnds
= 1;
12802 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12803 expected_nopnds
= 2;
12804 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12805 expected_nopnds
= 3;
12806 if (!(attr
& RS6000_BTC_VOID
))
12807 expected_nopnds
+= 1;
12809 expected_nopnds
+= 2;
12811 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12817 pat
= GEN_FCN (icode
) (op
[0]);
12820 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12823 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12826 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12829 gcc_unreachable ();
12835 if (attr
& RS6000_BTC_CR
)
12837 if (fcode
== HTM_BUILTIN_TBEGIN
)
12839 /* Emit code to set TARGET to true or false depending on
12840 whether the tbegin. instruction successfully or failed
12841 to start a transaction. We do this by placing the 1's
12842 complement of CR's EQ bit into TARGET. */
12843 rtx scratch
= gen_reg_rtx (SImode
);
12844 emit_insn (gen_rtx_SET (scratch
,
12845 gen_rtx_EQ (SImode
, cr
,
12847 emit_insn (gen_rtx_SET (target
,
12848 gen_rtx_XOR (SImode
, scratch
,
12853 /* Emit code to copy the 4-bit condition register field
12854 CR into the least significant end of register TARGET. */
12855 rtx scratch1
= gen_reg_rtx (SImode
);
12856 rtx scratch2
= gen_reg_rtx (SImode
);
12857 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
12858 emit_insn (gen_movcc (subreg
, cr
));
12859 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
12860 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
12869 *expandedp
= false;
12874 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12877 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12878 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12879 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12880 rtx op0
= expand_normal (arg0
);
12881 rtx op1
= expand_normal (arg1
);
12882 rtx op2
= expand_normal (arg2
);
12883 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12884 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12885 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12886 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12888 if (icode
== CODE_FOR_nothing
)
12889 /* Builtin not supported on this processor. */
12892 /* If we got invalid arguments bail out before generating bad rtl. */
12893 if (arg0
== error_mark_node
12894 || arg1
== error_mark_node
12895 || arg2
== error_mark_node
)
12898 /* Check and prepare argument depending on the instruction code.
12900 Note that a switch statement instead of the sequence of tests
12901 would be incorrect as many of the CODE_FOR values could be
12902 CODE_FOR_nothing and that would yield multiple alternatives
12903 with identical values. We'd never reach here at runtime in
12905 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12906 || icode
== CODE_FOR_altivec_vsldoi_v4si
12907 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12908 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12910 /* Only allow 4-bit unsigned literals. */
12912 if (TREE_CODE (arg2
) != INTEGER_CST
12913 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12915 error ("argument 3 must be a 4-bit unsigned literal");
12919 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12920 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12921 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12922 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12923 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12924 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12925 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12926 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12928 /* Only allow 2-bit unsigned literals. */
12930 if (TREE_CODE (arg2
) != INTEGER_CST
12931 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12933 error ("argument 3 must be a 2-bit unsigned literal");
12937 else if (icode
== CODE_FOR_vsx_set_v2df
12938 || icode
== CODE_FOR_vsx_set_v2di
12939 || icode
== CODE_FOR_bcdadd
12940 || icode
== CODE_FOR_bcdadd_lt
12941 || icode
== CODE_FOR_bcdadd_eq
12942 || icode
== CODE_FOR_bcdadd_gt
12943 || icode
== CODE_FOR_bcdsub
12944 || icode
== CODE_FOR_bcdsub_lt
12945 || icode
== CODE_FOR_bcdsub_eq
12946 || icode
== CODE_FOR_bcdsub_gt
)
12948 /* Only allow 1-bit unsigned literals. */
12950 if (TREE_CODE (arg2
) != INTEGER_CST
12951 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12953 error ("argument 3 must be a 1-bit unsigned literal");
12957 else if (icode
== CODE_FOR_dfp_ddedpd_dd
12958 || icode
== CODE_FOR_dfp_ddedpd_td
)
12960 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
12962 if (TREE_CODE (arg0
) != INTEGER_CST
12963 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12965 error ("argument 1 must be 0 or 2");
12969 else if (icode
== CODE_FOR_dfp_denbcd_dd
12970 || icode
== CODE_FOR_dfp_denbcd_td
)
12972 /* Only allow 1-bit unsigned literals. */
12974 if (TREE_CODE (arg0
) != INTEGER_CST
12975 || TREE_INT_CST_LOW (arg0
) & ~0x1)
12977 error ("argument 1 must be a 1-bit unsigned literal");
12981 else if (icode
== CODE_FOR_dfp_dscli_dd
12982 || icode
== CODE_FOR_dfp_dscli_td
12983 || icode
== CODE_FOR_dfp_dscri_dd
12984 || icode
== CODE_FOR_dfp_dscri_td
)
12986 /* Only allow 6-bit unsigned literals. */
12988 if (TREE_CODE (arg1
) != INTEGER_CST
12989 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
12991 error ("argument 2 must be a 6-bit unsigned literal");
12995 else if (icode
== CODE_FOR_crypto_vshasigmaw
12996 || icode
== CODE_FOR_crypto_vshasigmad
)
12998 /* Check whether the 2nd and 3rd arguments are integer constants and in
12999 range and prepare arguments. */
13001 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
13003 error ("argument 2 must be 0 or 1");
13008 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg1
, 16))
13010 error ("argument 3 must be in the range 0..15");
13016 || GET_MODE (target
) != tmode
13017 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13018 target
= gen_reg_rtx (tmode
);
13020 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13021 op0
= copy_to_mode_reg (mode0
, op0
);
13022 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13023 op1
= copy_to_mode_reg (mode1
, op1
);
13024 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13025 op2
= copy_to_mode_reg (mode2
, op2
);
13027 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
13028 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
13030 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13038 /* Expand the lvx builtins. */
13040 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
13042 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13043 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13045 machine_mode tmode
, mode0
;
13047 enum insn_code icode
;
13051 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
13052 icode
= CODE_FOR_vector_altivec_load_v16qi
;
13054 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
13055 icode
= CODE_FOR_vector_altivec_load_v8hi
;
13057 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
13058 icode
= CODE_FOR_vector_altivec_load_v4si
;
13060 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
13061 icode
= CODE_FOR_vector_altivec_load_v4sf
;
13063 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
13064 icode
= CODE_FOR_vector_altivec_load_v2df
;
13066 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
13067 icode
= CODE_FOR_vector_altivec_load_v2di
;
13068 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
13069 icode
= CODE_FOR_vector_altivec_load_v1ti
;
13072 *expandedp
= false;
13078 arg0
= CALL_EXPR_ARG (exp
, 0);
13079 op0
= expand_normal (arg0
);
13080 tmode
= insn_data
[icode
].operand
[0].mode
;
13081 mode0
= insn_data
[icode
].operand
[1].mode
;
13084 || GET_MODE (target
) != tmode
13085 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13086 target
= gen_reg_rtx (tmode
);
13088 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13089 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13091 pat
= GEN_FCN (icode
) (target
, op0
);
13098 /* Expand the stvx builtins. */
13100 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
13103 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13104 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13106 machine_mode mode0
, mode1
;
13108 enum insn_code icode
;
13112 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
13113 icode
= CODE_FOR_vector_altivec_store_v16qi
;
13115 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
13116 icode
= CODE_FOR_vector_altivec_store_v8hi
;
13118 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
13119 icode
= CODE_FOR_vector_altivec_store_v4si
;
13121 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
13122 icode
= CODE_FOR_vector_altivec_store_v4sf
;
13124 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
13125 icode
= CODE_FOR_vector_altivec_store_v2df
;
13127 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
13128 icode
= CODE_FOR_vector_altivec_store_v2di
;
13129 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
13130 icode
= CODE_FOR_vector_altivec_store_v1ti
;
13133 *expandedp
= false;
13137 arg0
= CALL_EXPR_ARG (exp
, 0);
13138 arg1
= CALL_EXPR_ARG (exp
, 1);
13139 op0
= expand_normal (arg0
);
13140 op1
= expand_normal (arg1
);
13141 mode0
= insn_data
[icode
].operand
[0].mode
;
13142 mode1
= insn_data
[icode
].operand
[1].mode
;
13144 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13145 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13146 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13147 op1
= copy_to_mode_reg (mode1
, op1
);
13149 pat
= GEN_FCN (icode
) (op0
, op1
);
13157 /* Expand the dst builtins. */
13159 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
13162 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13163 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13164 tree arg0
, arg1
, arg2
;
13165 machine_mode mode0
, mode1
;
13166 rtx pat
, op0
, op1
, op2
;
13167 const struct builtin_description
*d
;
13170 *expandedp
= false;
13172 /* Handle DST variants. */
13174 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
13175 if (d
->code
== fcode
)
13177 arg0
= CALL_EXPR_ARG (exp
, 0);
13178 arg1
= CALL_EXPR_ARG (exp
, 1);
13179 arg2
= CALL_EXPR_ARG (exp
, 2);
13180 op0
= expand_normal (arg0
);
13181 op1
= expand_normal (arg1
);
13182 op2
= expand_normal (arg2
);
13183 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
13184 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
13186 /* Invalid arguments, bail out before generating bad rtl. */
13187 if (arg0
== error_mark_node
13188 || arg1
== error_mark_node
13189 || arg2
== error_mark_node
)
13194 if (TREE_CODE (arg2
) != INTEGER_CST
13195 || TREE_INT_CST_LOW (arg2
) & ~0x3)
13197 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
13201 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
13202 op0
= copy_to_mode_reg (Pmode
, op0
);
13203 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
13204 op1
= copy_to_mode_reg (mode1
, op1
);
13206 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
13216 /* Expand vec_init builtin. */
13218 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
13220 machine_mode tmode
= TYPE_MODE (type
);
13221 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
13222 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
13224 gcc_assert (VECTOR_MODE_P (tmode
));
13225 gcc_assert (n_elt
== call_expr_nargs (exp
));
13227 if (!target
|| !register_operand (target
, tmode
))
13228 target
= gen_reg_rtx (tmode
);
13230 /* If we have a vector compromised of a single element, such as V1TImode, do
13231 the initialization directly. */
13232 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
13234 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
13235 emit_move_insn (target
, gen_lowpart (tmode
, x
));
13239 rtvec v
= rtvec_alloc (n_elt
);
13241 for (i
= 0; i
< n_elt
; ++i
)
13243 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
13244 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
13247 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
13253 /* Return the integer constant in ARG. Constrain it to be in the range
13254 of the subparts of VEC_TYPE; issue an error if not. */
13257 get_element_number (tree vec_type
, tree arg
)
13259 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
13261 if (!tree_fits_uhwi_p (arg
)
13262 || (elt
= tree_to_uhwi (arg
), elt
> max
))
13264 error ("selector must be an integer constant in the range 0..%wi", max
);
13271 /* Expand vec_set builtin. */
13273 altivec_expand_vec_set_builtin (tree exp
)
13275 machine_mode tmode
, mode1
;
13276 tree arg0
, arg1
, arg2
;
13280 arg0
= CALL_EXPR_ARG (exp
, 0);
13281 arg1
= CALL_EXPR_ARG (exp
, 1);
13282 arg2
= CALL_EXPR_ARG (exp
, 2);
13284 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
13285 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
13286 gcc_assert (VECTOR_MODE_P (tmode
));
13288 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
13289 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
13290 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
13292 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
13293 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
13295 op0
= force_reg (tmode
, op0
);
13296 op1
= force_reg (mode1
, op1
);
13298 rs6000_expand_vector_set (op0
, op1
, elt
);
13303 /* Expand vec_ext builtin. */
13305 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
13307 machine_mode tmode
, mode0
;
13312 arg0
= CALL_EXPR_ARG (exp
, 0);
13313 arg1
= CALL_EXPR_ARG (exp
, 1);
13315 op0
= expand_normal (arg0
);
13316 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
13318 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
13319 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
13320 gcc_assert (VECTOR_MODE_P (mode0
));
13322 op0
= force_reg (mode0
, op0
);
13324 if (optimize
|| !target
|| !register_operand (target
, tmode
))
13325 target
= gen_reg_rtx (tmode
);
13327 rs6000_expand_vector_extract (target
, op0
, elt
);
13332 /* Expand the builtin in EXP and store the result in TARGET. Store
13333 true in *EXPANDEDP if we found a builtin to expand. */
13335 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13337 const struct builtin_description
*d
;
13339 enum insn_code icode
;
13340 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13343 machine_mode tmode
, mode0
;
13344 enum rs6000_builtins fcode
13345 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13347 if (rs6000_overloaded_builtin_p (fcode
))
13350 error ("unresolved overload for Altivec builtin %qF", fndecl
);
13352 /* Given it is invalid, just generate a normal call. */
13353 return expand_call (exp
, target
, false);
13356 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
13360 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
13364 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
13372 case ALTIVEC_BUILTIN_STVX_V2DF
:
13373 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df
, exp
);
13374 case ALTIVEC_BUILTIN_STVX_V2DI
:
13375 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di
, exp
);
13376 case ALTIVEC_BUILTIN_STVX_V4SF
:
13377 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf
, exp
);
13378 case ALTIVEC_BUILTIN_STVX
:
13379 case ALTIVEC_BUILTIN_STVX_V4SI
:
13380 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
13381 case ALTIVEC_BUILTIN_STVX_V8HI
:
13382 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi
, exp
);
13383 case ALTIVEC_BUILTIN_STVX_V16QI
:
13384 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi
, exp
);
13385 case ALTIVEC_BUILTIN_STVEBX
:
13386 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
13387 case ALTIVEC_BUILTIN_STVEHX
:
13388 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
13389 case ALTIVEC_BUILTIN_STVEWX
:
13390 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
13391 case ALTIVEC_BUILTIN_STVXL_V2DF
:
13392 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
13393 case ALTIVEC_BUILTIN_STVXL_V2DI
:
13394 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
13395 case ALTIVEC_BUILTIN_STVXL_V4SF
:
13396 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
13397 case ALTIVEC_BUILTIN_STVXL
:
13398 case ALTIVEC_BUILTIN_STVXL_V4SI
:
13399 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
13400 case ALTIVEC_BUILTIN_STVXL_V8HI
:
13401 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
13402 case ALTIVEC_BUILTIN_STVXL_V16QI
:
13403 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
13405 case ALTIVEC_BUILTIN_STVLX
:
13406 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
13407 case ALTIVEC_BUILTIN_STVLXL
:
13408 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
13409 case ALTIVEC_BUILTIN_STVRX
:
13410 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
13411 case ALTIVEC_BUILTIN_STVRXL
:
13412 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
13414 case VSX_BUILTIN_STXVD2X_V1TI
:
13415 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
13416 case VSX_BUILTIN_STXVD2X_V2DF
:
13417 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
13418 case VSX_BUILTIN_STXVD2X_V2DI
:
13419 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
13420 case VSX_BUILTIN_STXVW4X_V4SF
:
13421 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
13422 case VSX_BUILTIN_STXVW4X_V4SI
:
13423 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
13424 case VSX_BUILTIN_STXVW4X_V8HI
:
13425 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
13426 case VSX_BUILTIN_STXVW4X_V16QI
:
13427 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
13429 case ALTIVEC_BUILTIN_MFVSCR
:
13430 icode
= CODE_FOR_altivec_mfvscr
;
13431 tmode
= insn_data
[icode
].operand
[0].mode
;
13434 || GET_MODE (target
) != tmode
13435 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13436 target
= gen_reg_rtx (tmode
);
13438 pat
= GEN_FCN (icode
) (target
);
13444 case ALTIVEC_BUILTIN_MTVSCR
:
13445 icode
= CODE_FOR_altivec_mtvscr
;
13446 arg0
= CALL_EXPR_ARG (exp
, 0);
13447 op0
= expand_normal (arg0
);
13448 mode0
= insn_data
[icode
].operand
[0].mode
;
13450 /* If we got invalid arguments bail out before generating bad rtl. */
13451 if (arg0
== error_mark_node
)
13454 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13455 op0
= copy_to_mode_reg (mode0
, op0
);
13457 pat
= GEN_FCN (icode
) (op0
);
13462 case ALTIVEC_BUILTIN_DSSALL
:
13463 emit_insn (gen_altivec_dssall ());
13466 case ALTIVEC_BUILTIN_DSS
:
13467 icode
= CODE_FOR_altivec_dss
;
13468 arg0
= CALL_EXPR_ARG (exp
, 0);
13470 op0
= expand_normal (arg0
);
13471 mode0
= insn_data
[icode
].operand
[0].mode
;
13473 /* If we got invalid arguments bail out before generating bad rtl. */
13474 if (arg0
== error_mark_node
)
13477 if (TREE_CODE (arg0
) != INTEGER_CST
13478 || TREE_INT_CST_LOW (arg0
) & ~0x3)
13480 error ("argument to dss must be a 2-bit unsigned literal");
13484 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13485 op0
= copy_to_mode_reg (mode0
, op0
);
13487 emit_insn (gen_altivec_dss (op0
));
13490 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
13491 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
13492 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
13493 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
13494 case VSX_BUILTIN_VEC_INIT_V2DF
:
13495 case VSX_BUILTIN_VEC_INIT_V2DI
:
13496 case VSX_BUILTIN_VEC_INIT_V1TI
:
13497 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
13499 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
13500 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
13501 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
13502 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
13503 case VSX_BUILTIN_VEC_SET_V2DF
:
13504 case VSX_BUILTIN_VEC_SET_V2DI
:
13505 case VSX_BUILTIN_VEC_SET_V1TI
:
13506 return altivec_expand_vec_set_builtin (exp
);
13508 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
13509 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
13510 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
13511 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
13512 case VSX_BUILTIN_VEC_EXT_V2DF
:
13513 case VSX_BUILTIN_VEC_EXT_V2DI
:
13514 case VSX_BUILTIN_VEC_EXT_V1TI
:
13515 return altivec_expand_vec_ext_builtin (exp
, target
);
13519 /* Fall through. */
13522 /* Expand abs* operations. */
13524 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
13525 if (d
->code
== fcode
)
13526 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
13528 /* Expand the AltiVec predicates. */
13529 d
= bdesc_altivec_preds
;
13530 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
13531 if (d
->code
== fcode
)
13532 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
13534 /* LV* are funky. We initialized them differently. */
13537 case ALTIVEC_BUILTIN_LVSL
:
13538 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
13539 exp
, target
, false);
13540 case ALTIVEC_BUILTIN_LVSR
:
13541 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
13542 exp
, target
, false);
13543 case ALTIVEC_BUILTIN_LVEBX
:
13544 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
13545 exp
, target
, false);
13546 case ALTIVEC_BUILTIN_LVEHX
:
13547 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
13548 exp
, target
, false);
13549 case ALTIVEC_BUILTIN_LVEWX
:
13550 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
13551 exp
, target
, false);
13552 case ALTIVEC_BUILTIN_LVXL_V2DF
:
13553 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
13554 exp
, target
, false);
13555 case ALTIVEC_BUILTIN_LVXL_V2DI
:
13556 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
13557 exp
, target
, false);
13558 case ALTIVEC_BUILTIN_LVXL_V4SF
:
13559 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
13560 exp
, target
, false);
13561 case ALTIVEC_BUILTIN_LVXL
:
13562 case ALTIVEC_BUILTIN_LVXL_V4SI
:
13563 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
13564 exp
, target
, false);
13565 case ALTIVEC_BUILTIN_LVXL_V8HI
:
13566 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
13567 exp
, target
, false);
13568 case ALTIVEC_BUILTIN_LVXL_V16QI
:
13569 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
13570 exp
, target
, false);
13571 case ALTIVEC_BUILTIN_LVX_V2DF
:
13572 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df
,
13573 exp
, target
, false);
13574 case ALTIVEC_BUILTIN_LVX_V2DI
:
13575 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di
,
13576 exp
, target
, false);
13577 case ALTIVEC_BUILTIN_LVX_V4SF
:
13578 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf
,
13579 exp
, target
, false);
13580 case ALTIVEC_BUILTIN_LVX
:
13581 case ALTIVEC_BUILTIN_LVX_V4SI
:
13582 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
13583 exp
, target
, false);
13584 case ALTIVEC_BUILTIN_LVX_V8HI
:
13585 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi
,
13586 exp
, target
, false);
13587 case ALTIVEC_BUILTIN_LVX_V16QI
:
13588 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi
,
13589 exp
, target
, false);
13590 case ALTIVEC_BUILTIN_LVLX
:
13591 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
13592 exp
, target
, true);
13593 case ALTIVEC_BUILTIN_LVLXL
:
13594 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
13595 exp
, target
, true);
13596 case ALTIVEC_BUILTIN_LVRX
:
13597 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
13598 exp
, target
, true);
13599 case ALTIVEC_BUILTIN_LVRXL
:
13600 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
13601 exp
, target
, true);
13602 case VSX_BUILTIN_LXVD2X_V1TI
:
13603 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
13604 exp
, target
, false);
13605 case VSX_BUILTIN_LXVD2X_V2DF
:
13606 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
13607 exp
, target
, false);
13608 case VSX_BUILTIN_LXVD2X_V2DI
:
13609 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
13610 exp
, target
, false);
13611 case VSX_BUILTIN_LXVW4X_V4SF
:
13612 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
13613 exp
, target
, false);
13614 case VSX_BUILTIN_LXVW4X_V4SI
:
13615 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
13616 exp
, target
, false);
13617 case VSX_BUILTIN_LXVW4X_V8HI
:
13618 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
13619 exp
, target
, false);
13620 case VSX_BUILTIN_LXVW4X_V16QI
:
13621 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
13622 exp
, target
, false);
13626 /* Fall through. */
13629 *expandedp
= false;
13633 /* Expand the builtin in EXP and store the result in TARGET. Store
13634 true in *EXPANDEDP if we found a builtin to expand. */
13636 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
13638 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13639 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13640 const struct builtin_description
*d
;
13647 case PAIRED_BUILTIN_STX
:
13648 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
13649 case PAIRED_BUILTIN_LX
:
13650 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
13653 /* Fall through. */
13656 /* Expand the paired predicates. */
13657 d
= bdesc_paired_preds
;
13658 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
13659 if (d
->code
== fcode
)
13660 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
13662 *expandedp
= false;
13666 /* Binops that need to be initialized manually, but can be expanded
13667 automagically by rs6000_expand_binop_builtin. */
13668 static const struct builtin_description bdesc_2arg_spe
[] =
13670 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
13671 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
13672 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
13673 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
13674 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
13675 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
13676 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
13677 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
13678 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
13679 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
13680 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
13681 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
13682 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
13683 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
13684 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
13685 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
13686 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
13687 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
13688 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
13689 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
13690 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
13691 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
13694 /* Expand the builtin in EXP and store the result in TARGET. Store
13695 true in *EXPANDEDP if we found a builtin to expand.
13697 This expands the SPE builtins that are not simple unary and binary
13700 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
13702 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13704 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
13705 enum insn_code icode
;
13706 machine_mode tmode
, mode0
;
13708 const struct builtin_description
*d
;
13713 /* Syntax check for a 5-bit unsigned immediate. */
13716 case SPE_BUILTIN_EVSTDD
:
13717 case SPE_BUILTIN_EVSTDH
:
13718 case SPE_BUILTIN_EVSTDW
:
13719 case SPE_BUILTIN_EVSTWHE
:
13720 case SPE_BUILTIN_EVSTWHO
:
13721 case SPE_BUILTIN_EVSTWWE
:
13722 case SPE_BUILTIN_EVSTWWO
:
13723 arg1
= CALL_EXPR_ARG (exp
, 2);
13724 if (TREE_CODE (arg1
) != INTEGER_CST
13725 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
13727 error ("argument 2 must be a 5-bit unsigned literal");
13735 /* The evsplat*i instructions are not quite generic. */
13738 case SPE_BUILTIN_EVSPLATFI
:
13739 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
13741 case SPE_BUILTIN_EVSPLATI
:
13742 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
13748 d
= bdesc_2arg_spe
;
13749 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
13750 if (d
->code
== fcode
)
13751 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13753 d
= bdesc_spe_predicates
;
13754 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
13755 if (d
->code
== fcode
)
13756 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
13758 d
= bdesc_spe_evsel
;
13759 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
13760 if (d
->code
== fcode
)
13761 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
13765 case SPE_BUILTIN_EVSTDDX
:
13766 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
13767 case SPE_BUILTIN_EVSTDHX
:
13768 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
13769 case SPE_BUILTIN_EVSTDWX
:
13770 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
13771 case SPE_BUILTIN_EVSTWHEX
:
13772 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
13773 case SPE_BUILTIN_EVSTWHOX
:
13774 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
13775 case SPE_BUILTIN_EVSTWWEX
:
13776 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
13777 case SPE_BUILTIN_EVSTWWOX
:
13778 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
13779 case SPE_BUILTIN_EVSTDD
:
13780 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
13781 case SPE_BUILTIN_EVSTDH
:
13782 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
13783 case SPE_BUILTIN_EVSTDW
:
13784 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
13785 case SPE_BUILTIN_EVSTWHE
:
13786 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
13787 case SPE_BUILTIN_EVSTWHO
:
13788 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
13789 case SPE_BUILTIN_EVSTWWE
:
13790 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
13791 case SPE_BUILTIN_EVSTWWO
:
13792 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
13793 case SPE_BUILTIN_MFSPEFSCR
:
13794 icode
= CODE_FOR_spe_mfspefscr
;
13795 tmode
= insn_data
[icode
].operand
[0].mode
;
13798 || GET_MODE (target
) != tmode
13799 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13800 target
= gen_reg_rtx (tmode
);
13802 pat
= GEN_FCN (icode
) (target
);
13807 case SPE_BUILTIN_MTSPEFSCR
:
13808 icode
= CODE_FOR_spe_mtspefscr
;
13809 arg0
= CALL_EXPR_ARG (exp
, 0);
13810 op0
= expand_normal (arg0
);
13811 mode0
= insn_data
[icode
].operand
[0].mode
;
13813 if (arg0
== error_mark_node
)
13816 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13817 op0
= copy_to_mode_reg (mode0
, op0
);
13819 pat
= GEN_FCN (icode
) (op0
);
13827 *expandedp
= false;
13832 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13834 rtx pat
, scratch
, tmp
;
13835 tree form
= CALL_EXPR_ARG (exp
, 0);
13836 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13837 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13838 rtx op0
= expand_normal (arg0
);
13839 rtx op1
= expand_normal (arg1
);
13840 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13841 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13843 enum rtx_code code
;
13845 if (TREE_CODE (form
) != INTEGER_CST
)
13847 error ("argument 1 of __builtin_paired_predicate must be a constant");
13851 form_int
= TREE_INT_CST_LOW (form
);
13853 gcc_assert (mode0
== mode1
);
13855 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13859 || GET_MODE (target
) != SImode
13860 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13861 target
= gen_reg_rtx (SImode
);
13862 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13863 op0
= copy_to_mode_reg (mode0
, op0
);
13864 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13865 op1
= copy_to_mode_reg (mode1
, op1
);
13867 scratch
= gen_reg_rtx (CCFPmode
);
13869 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13891 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13894 error ("argument 1 of __builtin_paired_predicate is out of range");
13898 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13899 emit_move_insn (target
, tmp
);
13904 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
13906 rtx pat
, scratch
, tmp
;
13907 tree form
= CALL_EXPR_ARG (exp
, 0);
13908 tree arg0
= CALL_EXPR_ARG (exp
, 1);
13909 tree arg1
= CALL_EXPR_ARG (exp
, 2);
13910 rtx op0
= expand_normal (arg0
);
13911 rtx op1
= expand_normal (arg1
);
13912 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13913 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13915 enum rtx_code code
;
13917 if (TREE_CODE (form
) != INTEGER_CST
)
13919 error ("argument 1 of __builtin_spe_predicate must be a constant");
13923 form_int
= TREE_INT_CST_LOW (form
);
13925 gcc_assert (mode0
== mode1
);
13927 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13931 || GET_MODE (target
) != SImode
13932 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13933 target
= gen_reg_rtx (SImode
);
13935 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13936 op0
= copy_to_mode_reg (mode0
, op0
);
13937 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13938 op1
= copy_to_mode_reg (mode1
, op1
);
13940 scratch
= gen_reg_rtx (CCmode
);
13942 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13947 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13948 _lower_. We use one compare, but look in different bits of the
13949 CR for each variant.
13951 There are 2 elements in each SPE simd type (upper/lower). The CR
13952 bits are set as follows:
13954 BIT0 | BIT 1 | BIT 2 | BIT 3
13955 U | L | (U | L) | (U & L)
13957 So, for an "all" relationship, BIT 3 would be set.
13958 For an "any" relationship, BIT 2 would be set. Etc.
13960 Following traditional nomenclature, these bits map to:
13962 BIT0 | BIT 1 | BIT 2 | BIT 3
13965 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13970 /* All variant. OV bit. */
13972 /* We need to get to the OV bit, which is the ORDERED bit. We
13973 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13974 that's ugly and will make validate_condition_mode die.
13975 So let's just use another pattern. */
13976 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13978 /* Any variant. EQ bit. */
13982 /* Upper variant. LT bit. */
13986 /* Lower variant. GT bit. */
13991 error ("argument 1 of __builtin_spe_predicate is out of range");
13995 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13996 emit_move_insn (target
, tmp
);
14001 /* The evsel builtins look like this:
14003 e = __builtin_spe_evsel_OP (a, b, c, d);
14005 and work like this:
14007 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
14008 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
14012 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
14015 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14016 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14017 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14018 tree arg3
= CALL_EXPR_ARG (exp
, 3);
14019 rtx op0
= expand_normal (arg0
);
14020 rtx op1
= expand_normal (arg1
);
14021 rtx op2
= expand_normal (arg2
);
14022 rtx op3
= expand_normal (arg3
);
14023 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14024 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14026 gcc_assert (mode0
== mode1
);
14028 if (arg0
== error_mark_node
|| arg1
== error_mark_node
14029 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
14033 || GET_MODE (target
) != mode0
14034 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
14035 target
= gen_reg_rtx (mode0
);
14037 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14038 op0
= copy_to_mode_reg (mode0
, op0
);
14039 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
14040 op1
= copy_to_mode_reg (mode0
, op1
);
14041 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
14042 op2
= copy_to_mode_reg (mode0
, op2
);
14043 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
14044 op3
= copy_to_mode_reg (mode0
, op3
);
14046 /* Generate the compare. */
14047 scratch
= gen_reg_rtx (CCmode
);
14048 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14053 if (mode0
== V2SImode
)
14054 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
14056 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
14061 /* Raise an error message for a builtin function that is called without the
14062 appropriate target options being set. */
14065 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
14067 size_t uns_fncode
= (size_t)fncode
;
14068 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
14069 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
14071 gcc_assert (name
!= NULL
);
14072 if ((fnmask
& RS6000_BTM_CELL
) != 0)
14073 error ("Builtin function %s is only valid for the cell processor", name
);
14074 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
14075 error ("Builtin function %s requires the -mvsx option", name
);
14076 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
14077 error ("Builtin function %s requires the -mhtm option", name
);
14078 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
14079 error ("Builtin function %s requires the -maltivec option", name
);
14080 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
14081 error ("Builtin function %s requires the -mpaired option", name
);
14082 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
14083 error ("Builtin function %s requires the -mspe option", name
);
14084 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
14085 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
14086 error ("Builtin function %s requires the -mhard-dfp and"
14087 " -mpower8-vector options", name
);
14088 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
14089 error ("Builtin function %s requires the -mhard-dfp option", name
);
14090 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
14091 error ("Builtin function %s requires the -mpower8-vector option", name
);
14092 else if ((fnmask
& (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
14093 == (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
14094 error ("Builtin function %s requires the -mhard-float and"
14095 " -mlong-double-128 options", name
);
14096 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
14097 error ("Builtin function %s requires the -mhard-float option", name
);
14099 error ("Builtin function %s is not supported with the current options",
14103 /* Expand an expression EXP that calls a built-in function,
14104 with result going to TARGET if that's convenient
14105 (and in mode MODE if that's convenient).
14106 SUBTARGET may be used as the target for computing one of EXP's operands.
14107 IGNORE is nonzero if the value is to be ignored. */
14110 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14111 machine_mode mode ATTRIBUTE_UNUSED
,
14112 int ignore ATTRIBUTE_UNUSED
)
14114 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14115 enum rs6000_builtins fcode
14116 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
14117 size_t uns_fcode
= (size_t)fcode
;
14118 const struct builtin_description
*d
;
14122 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
14123 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
14125 if (TARGET_DEBUG_BUILTIN
)
14127 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
14128 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
14129 const char *name2
= ((icode
!= CODE_FOR_nothing
)
14130 ? get_insn_name ((int)icode
)
14134 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
14136 default: name3
= "unknown"; break;
14137 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
14138 case RS6000_BTC_UNARY
: name3
= "unary"; break;
14139 case RS6000_BTC_BINARY
: name3
= "binary"; break;
14140 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
14141 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
14142 case RS6000_BTC_ABS
: name3
= "abs"; break;
14143 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
14144 case RS6000_BTC_DST
: name3
= "dst"; break;
14149 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
14150 (name1
) ? name1
: "---", fcode
,
14151 (name2
) ? name2
: "---", (int)icode
,
14153 func_valid_p
? "" : ", not valid");
14158 rs6000_invalid_builtin (fcode
);
14160 /* Given it is invalid, just generate a normal call. */
14161 return expand_call (exp
, target
, ignore
);
14166 case RS6000_BUILTIN_RECIP
:
14167 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
14169 case RS6000_BUILTIN_RECIPF
:
14170 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
14172 case RS6000_BUILTIN_RSQRTF
:
14173 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
14175 case RS6000_BUILTIN_RSQRT
:
14176 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
14178 case POWER7_BUILTIN_BPERMD
:
14179 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
14180 ? CODE_FOR_bpermd_di
14181 : CODE_FOR_bpermd_si
), exp
, target
);
14183 case RS6000_BUILTIN_GET_TB
:
14184 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
14187 case RS6000_BUILTIN_MFTB
:
14188 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
14189 ? CODE_FOR_rs6000_mftb_di
14190 : CODE_FOR_rs6000_mftb_si
),
14193 case RS6000_BUILTIN_MFFS
:
14194 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
14196 case RS6000_BUILTIN_MTFSF
:
14197 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
14199 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
14200 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
14202 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
14203 : (int) CODE_FOR_altivec_lvsl_direct
);
14204 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14205 machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
14209 gcc_assert (TARGET_ALTIVEC
);
14211 arg
= CALL_EXPR_ARG (exp
, 0);
14212 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
14213 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
14214 addr
= memory_address (mode
, op
);
14215 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
14219 /* For the load case need to negate the address. */
14220 op
= gen_reg_rtx (GET_MODE (addr
));
14221 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
14223 op
= gen_rtx_MEM (mode
, op
);
14226 || GET_MODE (target
) != tmode
14227 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14228 target
= gen_reg_rtx (tmode
);
14230 pat
= GEN_FCN (icode
) (target
, op
);
14238 case ALTIVEC_BUILTIN_VCFUX
:
14239 case ALTIVEC_BUILTIN_VCFSX
:
14240 case ALTIVEC_BUILTIN_VCTUXS
:
14241 case ALTIVEC_BUILTIN_VCTSXS
:
14242 /* FIXME: There's got to be a nicer way to handle this case than
14243 constructing a new CALL_EXPR. */
14244 if (call_expr_nargs (exp
) == 1)
14246 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
14247 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
14255 if (TARGET_ALTIVEC
)
14257 ret
= altivec_expand_builtin (exp
, target
, &success
);
14264 ret
= spe_expand_builtin (exp
, target
, &success
);
14269 if (TARGET_PAIRED_FLOAT
)
14271 ret
= paired_expand_builtin (exp
, target
, &success
);
14278 ret
= htm_expand_builtin (exp
, target
, &success
);
14284 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
14285 gcc_assert (attr
== RS6000_BTC_UNARY
14286 || attr
== RS6000_BTC_BINARY
14287 || attr
== RS6000_BTC_TERNARY
);
14289 /* Handle simple unary operations. */
14291 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
14292 if (d
->code
== fcode
)
14293 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
14295 /* Handle simple binary operations. */
14297 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
14298 if (d
->code
== fcode
)
14299 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
14301 /* Handle simple ternary operations. */
14303 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14304 if (d
->code
== fcode
)
14305 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
14307 gcc_unreachable ();
14311 rs6000_init_builtins (void)
14317 if (TARGET_DEBUG_BUILTIN
)
14318 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
14319 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
14320 (TARGET_SPE
) ? ", spe" : "",
14321 (TARGET_ALTIVEC
) ? ", altivec" : "",
14322 (TARGET_VSX
) ? ", vsx" : "");
14324 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
14325 V2SF_type_node
= build_vector_type (float_type_node
, 2);
14326 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
14327 V2DF_type_node
= build_vector_type (double_type_node
, 2);
14328 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
14329 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
14330 V4SF_type_node
= build_vector_type (float_type_node
, 4);
14331 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
14332 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
14334 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
14335 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
14336 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
14337 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
14339 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
14340 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
14341 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
14342 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
14344 /* We use V1TI mode as a special container to hold __int128_t items that
14345 must live in VSX registers. */
14346 if (intTI_type_node
)
14348 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
14349 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
14352 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
14353 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
14354 'vector unsigned short'. */
14356 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
14357 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14358 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
14359 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
14360 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
14362 long_integer_type_internal_node
= long_integer_type_node
;
14363 long_unsigned_type_internal_node
= long_unsigned_type_node
;
14364 long_long_integer_type_internal_node
= long_long_integer_type_node
;
14365 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
14366 intQI_type_internal_node
= intQI_type_node
;
14367 uintQI_type_internal_node
= unsigned_intQI_type_node
;
14368 intHI_type_internal_node
= intHI_type_node
;
14369 uintHI_type_internal_node
= unsigned_intHI_type_node
;
14370 intSI_type_internal_node
= intSI_type_node
;
14371 uintSI_type_internal_node
= unsigned_intSI_type_node
;
14372 intDI_type_internal_node
= intDI_type_node
;
14373 uintDI_type_internal_node
= unsigned_intDI_type_node
;
14374 intTI_type_internal_node
= intTI_type_node
;
14375 uintTI_type_internal_node
= unsigned_intTI_type_node
;
14376 float_type_internal_node
= float_type_node
;
14377 double_type_internal_node
= double_type_node
;
14378 long_double_type_internal_node
= long_double_type_node
;
14379 dfloat64_type_internal_node
= dfloat64_type_node
;
14380 dfloat128_type_internal_node
= dfloat128_type_node
;
14381 void_type_internal_node
= void_type_node
;
14383 /* Initialize the modes for builtin_function_type, mapping a machine mode to
14385 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
14386 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
14387 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
14388 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
14389 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
14390 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
14391 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
14392 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
14393 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
14394 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
14395 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
14396 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
14397 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
14398 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
14399 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
14400 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
14401 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
14402 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
14403 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
14404 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
14405 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
14406 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
14407 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
14408 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
14409 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
14410 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
14411 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
14412 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
14414 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
14415 TYPE_NAME (bool_char_type_node
) = tdecl
;
14417 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
14418 TYPE_NAME (bool_short_type_node
) = tdecl
;
14420 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
14421 TYPE_NAME (bool_int_type_node
) = tdecl
;
14423 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
14424 TYPE_NAME (pixel_type_node
) = tdecl
;
14426 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
14427 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
14428 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
14429 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
14430 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
14432 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
14433 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
14435 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
14436 TYPE_NAME (V16QI_type_node
) = tdecl
;
14438 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
14439 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
14441 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
14442 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
14444 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
14445 TYPE_NAME (V8HI_type_node
) = tdecl
;
14447 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
14448 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
14450 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
14451 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
14453 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
14454 TYPE_NAME (V4SI_type_node
) = tdecl
;
14456 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
14457 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
14459 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
14460 TYPE_NAME (V4SF_type_node
) = tdecl
;
14462 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
14463 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
14465 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
14466 TYPE_NAME (V2DF_type_node
) = tdecl
;
14468 if (TARGET_POWERPC64
)
14470 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
14471 TYPE_NAME (V2DI_type_node
) = tdecl
;
14473 tdecl
= add_builtin_type ("__vector unsigned long",
14474 unsigned_V2DI_type_node
);
14475 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
14477 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
14478 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
14482 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
14483 TYPE_NAME (V2DI_type_node
) = tdecl
;
14485 tdecl
= add_builtin_type ("__vector unsigned long long",
14486 unsigned_V2DI_type_node
);
14487 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
14489 tdecl
= add_builtin_type ("__vector __bool long long",
14490 bool_V2DI_type_node
);
14491 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
14494 if (V1TI_type_node
)
14496 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
14497 TYPE_NAME (V1TI_type_node
) = tdecl
;
14499 tdecl
= add_builtin_type ("__vector unsigned __int128",
14500 unsigned_V1TI_type_node
);
14501 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
14504 /* Paired and SPE builtins are only available if you build a compiler with
14505 the appropriate options, so only create those builtins with the
14506 appropriate compiler option. Create Altivec and VSX builtins on machines
14507 with at least the general purpose extensions (970 and newer) to allow the
14508 use of the target attribute. */
14509 if (TARGET_PAIRED_FLOAT
)
14510 paired_init_builtins ();
14512 spe_init_builtins ();
14513 if (TARGET_EXTRA_BUILTINS
)
14514 altivec_init_builtins ();
14516 htm_init_builtins ();
14518 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
14519 rs6000_common_init_builtins ();
14521 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
14522 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
14523 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
14525 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
14526 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
14527 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
14529 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
14530 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
14531 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
14533 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
14534 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
14535 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
14537 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
14538 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
14539 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
14540 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
14542 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14544 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
14547 ftype
= build_function_type_list (unsigned_intDI_type_node
,
14550 ftype
= build_function_type_list (unsigned_intSI_type_node
,
14552 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
14554 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
14555 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
14557 ftype
= build_function_type_list (void_type_node
,
14558 intSI_type_node
, double_type_node
,
14560 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
14563 /* AIX libm provides clog as __clog. */
14564 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
14565 set_user_assembler_name (tdecl
, "__clog");
14568 #ifdef SUBTARGET_INIT_BUILTINS
14569 SUBTARGET_INIT_BUILTINS
;
14573 /* Returns the rs6000 builtin decl for CODE. */
14576 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
14578 HOST_WIDE_INT fnmask
;
14580 if (code
>= RS6000_BUILTIN_COUNT
)
14581 return error_mark_node
;
14583 fnmask
= rs6000_builtin_info
[code
].mask
;
14584 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
14586 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
14587 return error_mark_node
;
14590 return rs6000_builtin_decls
[code
];
14594 spe_init_builtins (void)
14596 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
14597 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
14598 const struct builtin_description
*d
;
14601 tree v2si_ftype_4_v2si
14602 = build_function_type_list (opaque_V2SI_type_node
,
14603 opaque_V2SI_type_node
,
14604 opaque_V2SI_type_node
,
14605 opaque_V2SI_type_node
,
14606 opaque_V2SI_type_node
,
14609 tree v2sf_ftype_4_v2sf
14610 = build_function_type_list (opaque_V2SF_type_node
,
14611 opaque_V2SF_type_node
,
14612 opaque_V2SF_type_node
,
14613 opaque_V2SF_type_node
,
14614 opaque_V2SF_type_node
,
14617 tree int_ftype_int_v2si_v2si
14618 = build_function_type_list (integer_type_node
,
14620 opaque_V2SI_type_node
,
14621 opaque_V2SI_type_node
,
14624 tree int_ftype_int_v2sf_v2sf
14625 = build_function_type_list (integer_type_node
,
14627 opaque_V2SF_type_node
,
14628 opaque_V2SF_type_node
,
14631 tree void_ftype_v2si_puint_int
14632 = build_function_type_list (void_type_node
,
14633 opaque_V2SI_type_node
,
14638 tree void_ftype_v2si_puint_char
14639 = build_function_type_list (void_type_node
,
14640 opaque_V2SI_type_node
,
14645 tree void_ftype_v2si_pv2si_int
14646 = build_function_type_list (void_type_node
,
14647 opaque_V2SI_type_node
,
14648 opaque_p_V2SI_type_node
,
14652 tree void_ftype_v2si_pv2si_char
14653 = build_function_type_list (void_type_node
,
14654 opaque_V2SI_type_node
,
14655 opaque_p_V2SI_type_node
,
14659 tree void_ftype_int
14660 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14662 tree int_ftype_void
14663 = build_function_type_list (integer_type_node
, NULL_TREE
);
14665 tree v2si_ftype_pv2si_int
14666 = build_function_type_list (opaque_V2SI_type_node
,
14667 opaque_p_V2SI_type_node
,
14671 tree v2si_ftype_puint_int
14672 = build_function_type_list (opaque_V2SI_type_node
,
14677 tree v2si_ftype_pushort_int
14678 = build_function_type_list (opaque_V2SI_type_node
,
14683 tree v2si_ftype_signed_char
14684 = build_function_type_list (opaque_V2SI_type_node
,
14685 signed_char_type_node
,
14688 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
14690 /* Initialize irregular SPE builtins. */
14692 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
14693 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
14694 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
14695 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
14696 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
14697 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
14698 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
14699 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
14700 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
14701 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
14702 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
14703 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
14704 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
14705 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
14706 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
14707 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
14708 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
14709 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
14712 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
14713 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
14714 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
14715 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
14716 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
14717 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
14718 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
14719 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
14720 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
14721 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
14722 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
14723 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
14724 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
14725 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
14726 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
14727 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
14728 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
14729 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
14730 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
14731 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
14732 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
14733 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
14736 d
= bdesc_spe_predicates
;
14737 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
14741 switch (insn_data
[d
->icode
].operand
[1].mode
)
14744 type
= int_ftype_int_v2si_v2si
;
14747 type
= int_ftype_int_v2sf_v2sf
;
14750 gcc_unreachable ();
14753 def_builtin (d
->name
, type
, d
->code
);
14756 /* Evsel predicates. */
14757 d
= bdesc_spe_evsel
;
14758 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
14762 switch (insn_data
[d
->icode
].operand
[1].mode
)
14765 type
= v2si_ftype_4_v2si
;
14768 type
= v2sf_ftype_4_v2sf
;
14771 gcc_unreachable ();
14774 def_builtin (d
->name
, type
, d
->code
);
14779 paired_init_builtins (void)
14781 const struct builtin_description
*d
;
14784 tree int_ftype_int_v2sf_v2sf
14785 = build_function_type_list (integer_type_node
,
14790 tree pcfloat_type_node
=
14791 build_pointer_type (build_qualified_type
14792 (float_type_node
, TYPE_QUAL_CONST
));
14794 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
14795 long_integer_type_node
,
14798 tree void_ftype_v2sf_long_pcfloat
=
14799 build_function_type_list (void_type_node
,
14801 long_integer_type_node
,
14806 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
14807 PAIRED_BUILTIN_LX
);
14810 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
14811 PAIRED_BUILTIN_STX
);
14814 d
= bdesc_paired_preds
;
14815 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
14819 if (TARGET_DEBUG_BUILTIN
)
14820 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
14821 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
14822 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
14824 switch (insn_data
[d
->icode
].operand
[1].mode
)
14827 type
= int_ftype_int_v2sf_v2sf
;
14830 gcc_unreachable ();
14833 def_builtin (d
->name
, type
, d
->code
);
14838 altivec_init_builtins (void)
14840 const struct builtin_description
*d
;
14845 tree pvoid_type_node
= build_pointer_type (void_type_node
);
14847 tree pcvoid_type_node
14848 = build_pointer_type (build_qualified_type (void_type_node
,
14851 tree int_ftype_opaque
14852 = build_function_type_list (integer_type_node
,
14853 opaque_V4SI_type_node
, NULL_TREE
);
14854 tree opaque_ftype_opaque
14855 = build_function_type_list (integer_type_node
, NULL_TREE
);
14856 tree opaque_ftype_opaque_int
14857 = build_function_type_list (opaque_V4SI_type_node
,
14858 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
14859 tree opaque_ftype_opaque_opaque_int
14860 = build_function_type_list (opaque_V4SI_type_node
,
14861 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
14862 integer_type_node
, NULL_TREE
);
14863 tree int_ftype_int_opaque_opaque
14864 = build_function_type_list (integer_type_node
,
14865 integer_type_node
, opaque_V4SI_type_node
,
14866 opaque_V4SI_type_node
, NULL_TREE
);
14867 tree int_ftype_int_v4si_v4si
14868 = build_function_type_list (integer_type_node
,
14869 integer_type_node
, V4SI_type_node
,
14870 V4SI_type_node
, NULL_TREE
);
14871 tree int_ftype_int_v2di_v2di
14872 = build_function_type_list (integer_type_node
,
14873 integer_type_node
, V2DI_type_node
,
14874 V2DI_type_node
, NULL_TREE
);
14875 tree void_ftype_v4si
14876 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
14877 tree v8hi_ftype_void
14878 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
14879 tree void_ftype_void
14880 = build_function_type_list (void_type_node
, NULL_TREE
);
14881 tree void_ftype_int
14882 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
14884 tree opaque_ftype_long_pcvoid
14885 = build_function_type_list (opaque_V4SI_type_node
,
14886 long_integer_type_node
, pcvoid_type_node
,
14888 tree v16qi_ftype_long_pcvoid
14889 = build_function_type_list (V16QI_type_node
,
14890 long_integer_type_node
, pcvoid_type_node
,
14892 tree v8hi_ftype_long_pcvoid
14893 = build_function_type_list (V8HI_type_node
,
14894 long_integer_type_node
, pcvoid_type_node
,
14896 tree v4si_ftype_long_pcvoid
14897 = build_function_type_list (V4SI_type_node
,
14898 long_integer_type_node
, pcvoid_type_node
,
14900 tree v4sf_ftype_long_pcvoid
14901 = build_function_type_list (V4SF_type_node
,
14902 long_integer_type_node
, pcvoid_type_node
,
14904 tree v2df_ftype_long_pcvoid
14905 = build_function_type_list (V2DF_type_node
,
14906 long_integer_type_node
, pcvoid_type_node
,
14908 tree v2di_ftype_long_pcvoid
14909 = build_function_type_list (V2DI_type_node
,
14910 long_integer_type_node
, pcvoid_type_node
,
14913 tree void_ftype_opaque_long_pvoid
14914 = build_function_type_list (void_type_node
,
14915 opaque_V4SI_type_node
, long_integer_type_node
,
14916 pvoid_type_node
, NULL_TREE
);
14917 tree void_ftype_v4si_long_pvoid
14918 = build_function_type_list (void_type_node
,
14919 V4SI_type_node
, long_integer_type_node
,
14920 pvoid_type_node
, NULL_TREE
);
14921 tree void_ftype_v16qi_long_pvoid
14922 = build_function_type_list (void_type_node
,
14923 V16QI_type_node
, long_integer_type_node
,
14924 pvoid_type_node
, NULL_TREE
);
14925 tree void_ftype_v8hi_long_pvoid
14926 = build_function_type_list (void_type_node
,
14927 V8HI_type_node
, long_integer_type_node
,
14928 pvoid_type_node
, NULL_TREE
);
14929 tree void_ftype_v4sf_long_pvoid
14930 = build_function_type_list (void_type_node
,
14931 V4SF_type_node
, long_integer_type_node
,
14932 pvoid_type_node
, NULL_TREE
);
14933 tree void_ftype_v2df_long_pvoid
14934 = build_function_type_list (void_type_node
,
14935 V2DF_type_node
, long_integer_type_node
,
14936 pvoid_type_node
, NULL_TREE
);
14937 tree void_ftype_v2di_long_pvoid
14938 = build_function_type_list (void_type_node
,
14939 V2DI_type_node
, long_integer_type_node
,
14940 pvoid_type_node
, NULL_TREE
);
14941 tree int_ftype_int_v8hi_v8hi
14942 = build_function_type_list (integer_type_node
,
14943 integer_type_node
, V8HI_type_node
,
14944 V8HI_type_node
, NULL_TREE
);
14945 tree int_ftype_int_v16qi_v16qi
14946 = build_function_type_list (integer_type_node
,
14947 integer_type_node
, V16QI_type_node
,
14948 V16QI_type_node
, NULL_TREE
);
14949 tree int_ftype_int_v4sf_v4sf
14950 = build_function_type_list (integer_type_node
,
14951 integer_type_node
, V4SF_type_node
,
14952 V4SF_type_node
, NULL_TREE
);
14953 tree int_ftype_int_v2df_v2df
14954 = build_function_type_list (integer_type_node
,
14955 integer_type_node
, V2DF_type_node
,
14956 V2DF_type_node
, NULL_TREE
);
14957 tree v2di_ftype_v2di
14958 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
14959 tree v4si_ftype_v4si
14960 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
14961 tree v8hi_ftype_v8hi
14962 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
14963 tree v16qi_ftype_v16qi
14964 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
14965 tree v4sf_ftype_v4sf
14966 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
14967 tree v2df_ftype_v2df
14968 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
14969 tree void_ftype_pcvoid_int_int
14970 = build_function_type_list (void_type_node
,
14971 pcvoid_type_node
, integer_type_node
,
14972 integer_type_node
, NULL_TREE
);
14974 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
14975 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
14976 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
14977 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
14978 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
14979 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
14980 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
14981 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
14982 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
14983 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
14984 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
14985 ALTIVEC_BUILTIN_LVXL_V2DF
);
14986 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
14987 ALTIVEC_BUILTIN_LVXL_V2DI
);
14988 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
14989 ALTIVEC_BUILTIN_LVXL_V4SF
);
14990 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
14991 ALTIVEC_BUILTIN_LVXL_V4SI
);
14992 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
14993 ALTIVEC_BUILTIN_LVXL_V8HI
);
14994 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
14995 ALTIVEC_BUILTIN_LVXL_V16QI
);
14996 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
14997 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
14998 ALTIVEC_BUILTIN_LVX_V2DF
);
14999 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
15000 ALTIVEC_BUILTIN_LVX_V2DI
);
15001 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
15002 ALTIVEC_BUILTIN_LVX_V4SF
);
15003 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
15004 ALTIVEC_BUILTIN_LVX_V4SI
);
15005 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
15006 ALTIVEC_BUILTIN_LVX_V8HI
);
15007 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
15008 ALTIVEC_BUILTIN_LVX_V16QI
);
15009 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
15010 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
15011 ALTIVEC_BUILTIN_STVX_V2DF
);
15012 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
15013 ALTIVEC_BUILTIN_STVX_V2DI
);
15014 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
15015 ALTIVEC_BUILTIN_STVX_V4SF
);
15016 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
15017 ALTIVEC_BUILTIN_STVX_V4SI
);
15018 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
15019 ALTIVEC_BUILTIN_STVX_V8HI
);
15020 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
15021 ALTIVEC_BUILTIN_STVX_V16QI
);
15022 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
15023 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
15024 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
15025 ALTIVEC_BUILTIN_STVXL_V2DF
);
15026 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
15027 ALTIVEC_BUILTIN_STVXL_V2DI
);
15028 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
15029 ALTIVEC_BUILTIN_STVXL_V4SF
);
15030 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
15031 ALTIVEC_BUILTIN_STVXL_V4SI
);
15032 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
15033 ALTIVEC_BUILTIN_STVXL_V8HI
);
15034 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
15035 ALTIVEC_BUILTIN_STVXL_V16QI
);
15036 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
15037 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
15038 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
15039 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
15040 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
15041 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
15042 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
15043 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
15044 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
15045 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
15046 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
15047 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
15048 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
15049 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
15050 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
15051 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
15053 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
15054 VSX_BUILTIN_LXVD2X_V2DF
);
15055 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
15056 VSX_BUILTIN_LXVD2X_V2DI
);
15057 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
15058 VSX_BUILTIN_LXVW4X_V4SF
);
15059 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
15060 VSX_BUILTIN_LXVW4X_V4SI
);
15061 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
15062 VSX_BUILTIN_LXVW4X_V8HI
);
15063 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
15064 VSX_BUILTIN_LXVW4X_V16QI
);
15065 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
15066 VSX_BUILTIN_STXVD2X_V2DF
);
15067 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
15068 VSX_BUILTIN_STXVD2X_V2DI
);
15069 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
15070 VSX_BUILTIN_STXVW4X_V4SF
);
15071 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
15072 VSX_BUILTIN_STXVW4X_V4SI
);
15073 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
15074 VSX_BUILTIN_STXVW4X_V8HI
);
15075 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
15076 VSX_BUILTIN_STXVW4X_V16QI
);
15077 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
15078 VSX_BUILTIN_VEC_LD
);
15079 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
15080 VSX_BUILTIN_VEC_ST
);
15082 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
15083 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
15084 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
15086 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
15087 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
15088 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
15089 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
15090 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
15091 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
15092 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
15093 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
15094 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
15095 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
15096 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
15097 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
15099 /* Cell builtins. */
15100 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
15101 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
15102 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
15103 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
15105 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
15106 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
15107 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
15108 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
15110 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
15111 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
15112 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
15113 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
15115 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
15116 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
15117 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
15118 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
15120 /* Add the DST variants. */
15122 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
15123 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
15125 /* Initialize the predicates. */
15126 d
= bdesc_altivec_preds
;
15127 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
15129 machine_mode mode1
;
15132 if (rs6000_overloaded_builtin_p (d
->code
))
15135 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
15140 type
= int_ftype_int_opaque_opaque
;
15143 type
= int_ftype_int_v2di_v2di
;
15146 type
= int_ftype_int_v4si_v4si
;
15149 type
= int_ftype_int_v8hi_v8hi
;
15152 type
= int_ftype_int_v16qi_v16qi
;
15155 type
= int_ftype_int_v4sf_v4sf
;
15158 type
= int_ftype_int_v2df_v2df
;
15161 gcc_unreachable ();
15164 def_builtin (d
->name
, type
, d
->code
);
15167 /* Initialize the abs* operators. */
15169 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
15171 machine_mode mode0
;
15174 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
15179 type
= v2di_ftype_v2di
;
15182 type
= v4si_ftype_v4si
;
15185 type
= v8hi_ftype_v8hi
;
15188 type
= v16qi_ftype_v16qi
;
15191 type
= v4sf_ftype_v4sf
;
15194 type
= v2df_ftype_v2df
;
15197 gcc_unreachable ();
15200 def_builtin (d
->name
, type
, d
->code
);
15203 /* Initialize target builtin that implements
15204 targetm.vectorize.builtin_mask_for_load. */
15206 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
15207 v16qi_ftype_long_pcvoid
,
15208 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
15209 BUILT_IN_MD
, NULL
, NULL_TREE
);
15210 TREE_READONLY (decl
) = 1;
15211 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
15212 altivec_builtin_mask_for_load
= decl
;
15214 /* Access to the vec_init patterns. */
15215 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
15216 integer_type_node
, integer_type_node
,
15217 integer_type_node
, NULL_TREE
);
15218 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
15220 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
15221 short_integer_type_node
,
15222 short_integer_type_node
,
15223 short_integer_type_node
,
15224 short_integer_type_node
,
15225 short_integer_type_node
,
15226 short_integer_type_node
,
15227 short_integer_type_node
, NULL_TREE
);
15228 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
15230 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
15231 char_type_node
, char_type_node
,
15232 char_type_node
, char_type_node
,
15233 char_type_node
, char_type_node
,
15234 char_type_node
, char_type_node
,
15235 char_type_node
, char_type_node
,
15236 char_type_node
, char_type_node
,
15237 char_type_node
, char_type_node
,
15238 char_type_node
, NULL_TREE
);
15239 def_builtin ("__builtin_vec_init_v16qi", ftype
,
15240 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
15242 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
15243 float_type_node
, float_type_node
,
15244 float_type_node
, NULL_TREE
);
15245 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
15247 /* VSX builtins. */
15248 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
15249 double_type_node
, NULL_TREE
);
15250 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
15252 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
15253 intDI_type_node
, NULL_TREE
);
15254 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
15256 /* Access to the vec_set patterns. */
15257 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
15259 integer_type_node
, NULL_TREE
);
15260 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
15262 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
15264 integer_type_node
, NULL_TREE
);
15265 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
15267 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
15269 integer_type_node
, NULL_TREE
);
15270 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
15272 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
15274 integer_type_node
, NULL_TREE
);
15275 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
15277 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
15279 integer_type_node
, NULL_TREE
);
15280 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
15282 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
15284 integer_type_node
, NULL_TREE
);
15285 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
15287 /* Access to the vec_extract patterns. */
15288 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
15289 integer_type_node
, NULL_TREE
);
15290 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
15292 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
15293 integer_type_node
, NULL_TREE
);
15294 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
15296 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
15297 integer_type_node
, NULL_TREE
);
15298 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
15300 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
15301 integer_type_node
, NULL_TREE
);
15302 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
15304 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
15305 integer_type_node
, NULL_TREE
);
15306 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
15308 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
15309 integer_type_node
, NULL_TREE
);
15310 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
15313 if (V1TI_type_node
)
15315 tree v1ti_ftype_long_pcvoid
15316 = build_function_type_list (V1TI_type_node
,
15317 long_integer_type_node
, pcvoid_type_node
,
15319 tree void_ftype_v1ti_long_pvoid
15320 = build_function_type_list (void_type_node
,
15321 V1TI_type_node
, long_integer_type_node
,
15322 pvoid_type_node
, NULL_TREE
);
15323 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
15324 VSX_BUILTIN_LXVD2X_V1TI
);
15325 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
15326 VSX_BUILTIN_STXVD2X_V1TI
);
15327 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
15328 NULL_TREE
, NULL_TREE
);
15329 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
15330 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
15332 integer_type_node
, NULL_TREE
);
15333 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
15334 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
15335 integer_type_node
, NULL_TREE
);
15336 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
15342 htm_init_builtins (void)
15344 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15345 const struct builtin_description
*d
;
15349 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
15351 tree op
[MAX_HTM_OPERANDS
], type
;
15352 HOST_WIDE_INT mask
= d
->mask
;
15353 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
15354 bool void_func
= (attr
& RS6000_BTC_VOID
);
15355 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
15357 tree gpr_type_node
;
15361 if (TARGET_32BIT
&& TARGET_POWERPC64
)
15362 gpr_type_node
= long_long_unsigned_type_node
;
15364 gpr_type_node
= long_unsigned_type_node
;
15366 if (attr
& RS6000_BTC_SPR
)
15368 rettype
= gpr_type_node
;
15369 argtype
= gpr_type_node
;
15371 else if (d
->code
== HTM_BUILTIN_TABORTDC
15372 || d
->code
== HTM_BUILTIN_TABORTDCI
)
15374 rettype
= unsigned_type_node
;
15375 argtype
= gpr_type_node
;
15379 rettype
= unsigned_type_node
;
15380 argtype
= unsigned_type_node
;
15383 if ((mask
& builtin_mask
) != mask
)
15385 if (TARGET_DEBUG_BUILTIN
)
15386 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
15392 if (TARGET_DEBUG_BUILTIN
)
15393 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
15394 (long unsigned) i
);
15398 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
15400 if (attr_args
== RS6000_BTC_UNARY
)
15401 op
[nopnds
++] = argtype
;
15402 else if (attr_args
== RS6000_BTC_BINARY
)
15404 op
[nopnds
++] = argtype
;
15405 op
[nopnds
++] = argtype
;
15407 else if (attr_args
== RS6000_BTC_TERNARY
)
15409 op
[nopnds
++] = argtype
;
15410 op
[nopnds
++] = argtype
;
15411 op
[nopnds
++] = argtype
;
15417 type
= build_function_type_list (op
[0], NULL_TREE
);
15420 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
15423 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
15426 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
15430 gcc_unreachable ();
15433 def_builtin (d
->name
, type
, d
->code
);
15437 /* Hash function for builtin functions with up to 3 arguments and a return
15440 builtin_hasher::hash (builtin_hash_struct
*bh
)
15445 for (i
= 0; i
< 4; i
++)
15447 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
15448 ret
= (ret
* 2) + bh
->uns_p
[i
];
15454 /* Compare builtin hash entries H1 and H2 for equivalence. */
15456 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
15458 return ((p1
->mode
[0] == p2
->mode
[0])
15459 && (p1
->mode
[1] == p2
->mode
[1])
15460 && (p1
->mode
[2] == p2
->mode
[2])
15461 && (p1
->mode
[3] == p2
->mode
[3])
15462 && (p1
->uns_p
[0] == p2
->uns_p
[0])
15463 && (p1
->uns_p
[1] == p2
->uns_p
[1])
15464 && (p1
->uns_p
[2] == p2
->uns_p
[2])
15465 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
15468 /* Map types for builtin functions with an explicit return type and up to 3
15469 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
15470 of the argument. */
15472 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
15473 machine_mode mode_arg1
, machine_mode mode_arg2
,
15474 enum rs6000_builtins builtin
, const char *name
)
15476 struct builtin_hash_struct h
;
15477 struct builtin_hash_struct
*h2
;
15480 tree ret_type
= NULL_TREE
;
15481 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
15483 /* Create builtin_hash_table. */
15484 if (builtin_hash_table
== NULL
)
15485 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
15487 h
.type
= NULL_TREE
;
15488 h
.mode
[0] = mode_ret
;
15489 h
.mode
[1] = mode_arg0
;
15490 h
.mode
[2] = mode_arg1
;
15491 h
.mode
[3] = mode_arg2
;
15497 /* If the builtin is a type that produces unsigned results or takes unsigned
15498 arguments, and it is returned as a decl for the vectorizer (such as
15499 widening multiplies, permute), make sure the arguments and return value
15500 are type correct. */
15503 /* unsigned 1 argument functions. */
15504 case CRYPTO_BUILTIN_VSBOX
:
15505 case P8V_BUILTIN_VGBBD
:
15506 case MISC_BUILTIN_CDTBCD
:
15507 case MISC_BUILTIN_CBCDTD
:
15512 /* unsigned 2 argument functions. */
15513 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
15514 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
15515 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
15516 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
15517 case CRYPTO_BUILTIN_VCIPHER
:
15518 case CRYPTO_BUILTIN_VCIPHERLAST
:
15519 case CRYPTO_BUILTIN_VNCIPHER
:
15520 case CRYPTO_BUILTIN_VNCIPHERLAST
:
15521 case CRYPTO_BUILTIN_VPMSUMB
:
15522 case CRYPTO_BUILTIN_VPMSUMH
:
15523 case CRYPTO_BUILTIN_VPMSUMW
:
15524 case CRYPTO_BUILTIN_VPMSUMD
:
15525 case CRYPTO_BUILTIN_VPMSUM
:
15526 case MISC_BUILTIN_ADDG6S
:
15527 case MISC_BUILTIN_DIVWEU
:
15528 case MISC_BUILTIN_DIVWEUO
:
15529 case MISC_BUILTIN_DIVDEU
:
15530 case MISC_BUILTIN_DIVDEUO
:
15536 /* unsigned 3 argument functions. */
15537 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
15538 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
15539 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
15540 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
15541 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
15542 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
15543 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
15544 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
15545 case VSX_BUILTIN_VPERM_16QI_UNS
:
15546 case VSX_BUILTIN_VPERM_8HI_UNS
:
15547 case VSX_BUILTIN_VPERM_4SI_UNS
:
15548 case VSX_BUILTIN_VPERM_2DI_UNS
:
15549 case VSX_BUILTIN_XXSEL_16QI_UNS
:
15550 case VSX_BUILTIN_XXSEL_8HI_UNS
:
15551 case VSX_BUILTIN_XXSEL_4SI_UNS
:
15552 case VSX_BUILTIN_XXSEL_2DI_UNS
:
15553 case CRYPTO_BUILTIN_VPERMXOR
:
15554 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
15555 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
15556 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
15557 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
15558 case CRYPTO_BUILTIN_VSHASIGMAW
:
15559 case CRYPTO_BUILTIN_VSHASIGMAD
:
15560 case CRYPTO_BUILTIN_VSHASIGMA
:
15567 /* signed permute functions with unsigned char mask. */
15568 case ALTIVEC_BUILTIN_VPERM_16QI
:
15569 case ALTIVEC_BUILTIN_VPERM_8HI
:
15570 case ALTIVEC_BUILTIN_VPERM_4SI
:
15571 case ALTIVEC_BUILTIN_VPERM_4SF
:
15572 case ALTIVEC_BUILTIN_VPERM_2DI
:
15573 case ALTIVEC_BUILTIN_VPERM_2DF
:
15574 case VSX_BUILTIN_VPERM_16QI
:
15575 case VSX_BUILTIN_VPERM_8HI
:
15576 case VSX_BUILTIN_VPERM_4SI
:
15577 case VSX_BUILTIN_VPERM_4SF
:
15578 case VSX_BUILTIN_VPERM_2DI
:
15579 case VSX_BUILTIN_VPERM_2DF
:
15583 /* unsigned args, signed return. */
15584 case VSX_BUILTIN_XVCVUXDDP_UNS
:
15585 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
15589 /* signed args, unsigned return. */
15590 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
15591 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
15592 case MISC_BUILTIN_UNPACK_TD
:
15593 case MISC_BUILTIN_UNPACK_V1TI
:
15597 /* unsigned arguments for 128-bit pack instructions. */
15598 case MISC_BUILTIN_PACK_TD
:
15599 case MISC_BUILTIN_PACK_V1TI
:
15608 /* Figure out how many args are present. */
15609 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
15613 fatal_error (input_location
,
15614 "internal error: builtin function %s had no type", name
);
15616 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
15617 if (!ret_type
&& h
.uns_p
[0])
15618 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
15621 fatal_error (input_location
,
15622 "internal error: builtin function %s had an unexpected "
15623 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
15625 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
15626 arg_type
[i
] = NULL_TREE
;
15628 for (i
= 0; i
< num_args
; i
++)
15630 int m
= (int) h
.mode
[i
+1];
15631 int uns_p
= h
.uns_p
[i
+1];
15633 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
15634 if (!arg_type
[i
] && uns_p
)
15635 arg_type
[i
] = builtin_mode_to_type
[m
][0];
15638 fatal_error (input_location
,
15639 "internal error: builtin function %s, argument %d "
15640 "had unexpected argument type %s", name
, i
,
15641 GET_MODE_NAME (m
));
15644 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
15645 if (*found
== NULL
)
15647 h2
= ggc_alloc
<builtin_hash_struct
> ();
15651 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
15652 arg_type
[2], NULL_TREE
);
15655 return (*found
)->type
;
15659 rs6000_common_init_builtins (void)
15661 const struct builtin_description
*d
;
15664 tree opaque_ftype_opaque
= NULL_TREE
;
15665 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
15666 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
15667 tree v2si_ftype_qi
= NULL_TREE
;
15668 tree v2si_ftype_v2si_qi
= NULL_TREE
;
15669 tree v2si_ftype_int_qi
= NULL_TREE
;
15670 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
15672 if (!TARGET_PAIRED_FLOAT
)
15674 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
15675 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
15678 /* Paired and SPE builtins are only available if you build a compiler with
15679 the appropriate options, so only create those builtins with the
15680 appropriate compiler option. Create Altivec and VSX builtins on machines
15681 with at least the general purpose extensions (970 and newer) to allow the
15682 use of the target attribute.. */
15684 if (TARGET_EXTRA_BUILTINS
)
15685 builtin_mask
|= RS6000_BTM_COMMON
;
15687 /* Add the ternary operators. */
15689 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
15692 HOST_WIDE_INT mask
= d
->mask
;
15694 if ((mask
& builtin_mask
) != mask
)
15696 if (TARGET_DEBUG_BUILTIN
)
15697 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
15701 if (rs6000_overloaded_builtin_p (d
->code
))
15703 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
15704 type
= opaque_ftype_opaque_opaque_opaque
15705 = build_function_type_list (opaque_V4SI_type_node
,
15706 opaque_V4SI_type_node
,
15707 opaque_V4SI_type_node
,
15708 opaque_V4SI_type_node
,
15713 enum insn_code icode
= d
->icode
;
15716 if (TARGET_DEBUG_BUILTIN
)
15717 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15723 if (icode
== CODE_FOR_nothing
)
15725 if (TARGET_DEBUG_BUILTIN
)
15726 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
15732 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
15733 insn_data
[icode
].operand
[1].mode
,
15734 insn_data
[icode
].operand
[2].mode
,
15735 insn_data
[icode
].operand
[3].mode
,
15739 def_builtin (d
->name
, type
, d
->code
);
15742 /* Add the binary operators. */
15744 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
15746 machine_mode mode0
, mode1
, mode2
;
15748 HOST_WIDE_INT mask
= d
->mask
;
15750 if ((mask
& builtin_mask
) != mask
)
15752 if (TARGET_DEBUG_BUILTIN
)
15753 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
15757 if (rs6000_overloaded_builtin_p (d
->code
))
15759 if (! (type
= opaque_ftype_opaque_opaque
))
15760 type
= opaque_ftype_opaque_opaque
15761 = build_function_type_list (opaque_V4SI_type_node
,
15762 opaque_V4SI_type_node
,
15763 opaque_V4SI_type_node
,
15768 enum insn_code icode
= d
->icode
;
15771 if (TARGET_DEBUG_BUILTIN
)
15772 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15778 if (icode
== CODE_FOR_nothing
)
15780 if (TARGET_DEBUG_BUILTIN
)
15781 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
15787 mode0
= insn_data
[icode
].operand
[0].mode
;
15788 mode1
= insn_data
[icode
].operand
[1].mode
;
15789 mode2
= insn_data
[icode
].operand
[2].mode
;
15791 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
15793 if (! (type
= v2si_ftype_v2si_qi
))
15794 type
= v2si_ftype_v2si_qi
15795 = build_function_type_list (opaque_V2SI_type_node
,
15796 opaque_V2SI_type_node
,
15801 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
15802 && mode2
== QImode
)
15804 if (! (type
= v2si_ftype_int_qi
))
15805 type
= v2si_ftype_int_qi
15806 = build_function_type_list (opaque_V2SI_type_node
,
15813 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
15817 def_builtin (d
->name
, type
, d
->code
);
15820 /* Add the simple unary operators. */
15822 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
15824 machine_mode mode0
, mode1
;
15826 HOST_WIDE_INT mask
= d
->mask
;
15828 if ((mask
& builtin_mask
) != mask
)
15830 if (TARGET_DEBUG_BUILTIN
)
15831 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
15835 if (rs6000_overloaded_builtin_p (d
->code
))
15837 if (! (type
= opaque_ftype_opaque
))
15838 type
= opaque_ftype_opaque
15839 = build_function_type_list (opaque_V4SI_type_node
,
15840 opaque_V4SI_type_node
,
15845 enum insn_code icode
= d
->icode
;
15848 if (TARGET_DEBUG_BUILTIN
)
15849 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
15855 if (icode
== CODE_FOR_nothing
)
15857 if (TARGET_DEBUG_BUILTIN
)
15858 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
15864 mode0
= insn_data
[icode
].operand
[0].mode
;
15865 mode1
= insn_data
[icode
].operand
[1].mode
;
15867 if (mode0
== V2SImode
&& mode1
== QImode
)
15869 if (! (type
= v2si_ftype_qi
))
15870 type
= v2si_ftype_qi
15871 = build_function_type_list (opaque_V2SI_type_node
,
15877 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
15881 def_builtin (d
->name
, type
, d
->code
);
15886 rs6000_init_libfuncs (void)
15888 if (!TARGET_IEEEQUAD
)
15889 /* AIX/Darwin/64-bit Linux quad floating point routines. */
15890 if (!TARGET_XL_COMPAT
)
15892 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
15893 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
15894 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
15895 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
15897 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
15899 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
15900 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
15901 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
15902 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
15903 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
15904 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
15905 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
15907 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
15908 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
15909 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
15910 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
15911 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
15912 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
15913 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
15914 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
15917 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
15918 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
15922 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
15923 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
15924 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
15925 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
15929 /* 32-bit SVR4 quad floating point routines. */
15931 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
15932 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
15933 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
15934 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
15935 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
15936 if (TARGET_PPC_GPOPT
)
15937 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
15939 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
15940 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
15941 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
15942 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
15943 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
15944 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
15946 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
15947 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
15948 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
15949 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
15950 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
15951 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
15952 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
15953 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
15958 /* Expand a block clear operation, and return 1 if successful. Return 0
15959 if we should let the compiler generate normal code.
15961 operands[0] is the destination
15962 operands[1] is the length
15963 operands[3] is the alignment */
15966 expand_block_clear (rtx operands
[])
15968 rtx orig_dest
= operands
[0];
15969 rtx bytes_rtx
= operands
[1];
15970 rtx align_rtx
= operands
[3];
15971 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
15972 HOST_WIDE_INT align
;
15973 HOST_WIDE_INT bytes
;
15978 /* If this is not a fixed size move, just call memcpy */
15982 /* This must be a fixed size alignment */
15983 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
15984 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
15986 /* Anything to clear? */
15987 bytes
= INTVAL (bytes_rtx
);
15991 /* Use the builtin memset after a point, to avoid huge code bloat.
15992 When optimize_size, avoid any significant code bloat; calling
15993 memset is about 4 instructions, so allow for one instruction to
15994 load zero and three to do clearing. */
15995 if (TARGET_ALTIVEC
&& align
>= 128)
15997 else if (TARGET_POWERPC64
&& (align
>= 64 || !STRICT_ALIGNMENT
))
15999 else if (TARGET_SPE
&& align
>= 64)
16004 if (optimize_size
&& bytes
> 3 * clear_step
)
16006 if (! optimize_size
&& bytes
> 8 * clear_step
)
16009 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
16011 machine_mode mode
= BLKmode
;
16014 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
16019 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
16024 else if (bytes
>= 8 && TARGET_POWERPC64
16025 && (align
>= 64 || !STRICT_ALIGNMENT
))
16029 if (offset
== 0 && align
< 64)
16033 /* If the address form is reg+offset with offset not a
16034 multiple of four, reload into reg indirect form here
16035 rather than waiting for reload. This way we get one
16036 reload, not one per store. */
16037 addr
= XEXP (orig_dest
, 0);
16038 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16039 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16040 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16042 addr
= copy_addr_to_reg (addr
);
16043 orig_dest
= replace_equiv_address (orig_dest
, addr
);
16047 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
16048 { /* move 4 bytes */
16052 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
16053 { /* move 2 bytes */
16057 else /* move 1 byte at a time */
16063 dest
= adjust_address (orig_dest
, mode
, offset
);
16065 emit_move_insn (dest
, CONST0_RTX (mode
));
16072 /* Expand a block move operation, and return 1 if successful. Return 0
16073 if we should let the compiler generate normal code.
16075 operands[0] is the destination
16076 operands[1] is the source
16077 operands[2] is the length
16078 operands[3] is the alignment */
16080 #define MAX_MOVE_REG 4
16083 expand_block_move (rtx operands
[])
16085 rtx orig_dest
= operands
[0];
16086 rtx orig_src
= operands
[1];
16087 rtx bytes_rtx
= operands
[2];
16088 rtx align_rtx
= operands
[3];
16089 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
16094 rtx stores
[MAX_MOVE_REG
];
16097 /* If this is not a fixed size move, just call memcpy */
16101 /* This must be a fixed size alignment */
16102 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
16103 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
16105 /* Anything to move? */
16106 bytes
= INTVAL (bytes_rtx
);
16110 if (bytes
> rs6000_block_move_inline_limit
)
16113 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
16116 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
16117 rtx (*mov
) (rtx
, rtx
);
16119 machine_mode mode
= BLKmode
;
16122 /* Altivec first, since it will be faster than a string move
16123 when it applies, and usually not significantly larger. */
16124 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
16128 gen_func
.mov
= gen_movv4si
;
16130 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
16134 gen_func
.mov
= gen_movv2si
;
16136 else if (TARGET_STRING
16137 && bytes
> 24 /* move up to 32 bytes at a time */
16143 && ! fixed_regs
[10]
16144 && ! fixed_regs
[11]
16145 && ! fixed_regs
[12])
16147 move_bytes
= (bytes
> 32) ? 32 : bytes
;
16148 gen_func
.movmemsi
= gen_movmemsi_8reg
;
16150 else if (TARGET_STRING
16151 && bytes
> 16 /* move up to 24 bytes at a time */
16157 && ! fixed_regs
[10])
16159 move_bytes
= (bytes
> 24) ? 24 : bytes
;
16160 gen_func
.movmemsi
= gen_movmemsi_6reg
;
16162 else if (TARGET_STRING
16163 && bytes
> 8 /* move up to 16 bytes at a time */
16167 && ! fixed_regs
[8])
16169 move_bytes
= (bytes
> 16) ? 16 : bytes
;
16170 gen_func
.movmemsi
= gen_movmemsi_4reg
;
16172 else if (bytes
>= 8 && TARGET_POWERPC64
16173 && (align
>= 64 || !STRICT_ALIGNMENT
))
16177 gen_func
.mov
= gen_movdi
;
16178 if (offset
== 0 && align
< 64)
16182 /* If the address form is reg+offset with offset not a
16183 multiple of four, reload into reg indirect form here
16184 rather than waiting for reload. This way we get one
16185 reload, not one per load and/or store. */
16186 addr
= XEXP (orig_dest
, 0);
16187 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16188 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16189 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16191 addr
= copy_addr_to_reg (addr
);
16192 orig_dest
= replace_equiv_address (orig_dest
, addr
);
16194 addr
= XEXP (orig_src
, 0);
16195 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
16196 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16197 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
16199 addr
= copy_addr_to_reg (addr
);
16200 orig_src
= replace_equiv_address (orig_src
, addr
);
16204 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
16205 { /* move up to 8 bytes at a time */
16206 move_bytes
= (bytes
> 8) ? 8 : bytes
;
16207 gen_func
.movmemsi
= gen_movmemsi_2reg
;
16209 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
16210 { /* move 4 bytes */
16213 gen_func
.mov
= gen_movsi
;
16215 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
16216 { /* move 2 bytes */
16219 gen_func
.mov
= gen_movhi
;
16221 else if (TARGET_STRING
&& bytes
> 1)
16222 { /* move up to 4 bytes at a time */
16223 move_bytes
= (bytes
> 4) ? 4 : bytes
;
16224 gen_func
.movmemsi
= gen_movmemsi_1reg
;
16226 else /* move 1 byte at a time */
16230 gen_func
.mov
= gen_movqi
;
16233 src
= adjust_address (orig_src
, mode
, offset
);
16234 dest
= adjust_address (orig_dest
, mode
, offset
);
16236 if (mode
!= BLKmode
)
16238 rtx tmp_reg
= gen_reg_rtx (mode
);
16240 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
16241 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
16244 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
16247 for (i
= 0; i
< num_reg
; i
++)
16248 emit_insn (stores
[i
]);
16252 if (mode
== BLKmode
)
16254 /* Move the address into scratch registers. The movmemsi
16255 patterns require zero offset. */
16256 if (!REG_P (XEXP (src
, 0)))
16258 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
16259 src
= replace_equiv_address (src
, src_reg
);
16261 set_mem_size (src
, move_bytes
);
16263 if (!REG_P (XEXP (dest
, 0)))
16265 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
16266 dest
= replace_equiv_address (dest
, dest_reg
);
16268 set_mem_size (dest
, move_bytes
);
16270 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
16271 GEN_INT (move_bytes
& 31),
16280 /* Return a string to perform a load_multiple operation.
16281 operands[0] is the vector.
16282 operands[1] is the source address.
16283 operands[2] is the first destination register. */
16286 rs6000_output_load_multiple (rtx operands
[3])
16288 /* We have to handle the case where the pseudo used to contain the address
16289 is assigned to one of the output registers. */
16291 int words
= XVECLEN (operands
[0], 0);
16294 if (XVECLEN (operands
[0], 0) == 1)
16295 return "lwz %2,0(%1)";
16297 for (i
= 0; i
< words
; i
++)
16298 if (refers_to_regno_p (REGNO (operands
[2]) + i
, operands
[1]))
16302 xop
[0] = GEN_INT (4 * (words
-1));
16303 xop
[1] = operands
[1];
16304 xop
[2] = operands
[2];
16305 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
16310 xop
[0] = GEN_INT (4 * (words
-1));
16311 xop
[1] = operands
[1];
16312 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
16313 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
16318 for (j
= 0; j
< words
; j
++)
16321 xop
[0] = GEN_INT (j
* 4);
16322 xop
[1] = operands
[1];
16323 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
16324 output_asm_insn ("lwz %2,%0(%1)", xop
);
16326 xop
[0] = GEN_INT (i
* 4);
16327 xop
[1] = operands
[1];
16328 output_asm_insn ("lwz %1,%0(%1)", xop
);
16333 return "lswi %2,%1,%N0";
16337 /* A validation routine: say whether CODE, a condition code, and MODE
16338 match. The other alternatives either don't make sense or should
16339 never be generated. */
16342 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
16344 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
16345 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
16346 && GET_MODE_CLASS (mode
) == MODE_CC
);
16348 /* These don't make sense. */
16349 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
16350 || mode
!= CCUNSmode
);
16352 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
16353 || mode
== CCUNSmode
);
16355 gcc_assert (mode
== CCFPmode
16356 || (code
!= ORDERED
&& code
!= UNORDERED
16357 && code
!= UNEQ
&& code
!= LTGT
16358 && code
!= UNGT
&& code
!= UNLT
16359 && code
!= UNGE
&& code
!= UNLE
));
16361 /* These should never be generated except for
16362 flag_finite_math_only. */
16363 gcc_assert (mode
!= CCFPmode
16364 || flag_finite_math_only
16365 || (code
!= LE
&& code
!= GE
16366 && code
!= UNEQ
&& code
!= LTGT
16367 && code
!= UNGT
&& code
!= UNLT
));
16369 /* These are invalid; the information is not there. */
16370 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
16374 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
16375 mask required to convert the result of a rotate insn into a shift
16376 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
16379 includes_lshift_p (rtx shiftop
, rtx andop
)
16381 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
16383 shift_mask
<<= INTVAL (shiftop
);
16385 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
16388 /* Similar, but for right shift. */
16391 includes_rshift_p (rtx shiftop
, rtx andop
)
16393 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
16395 shift_mask
>>= INTVAL (shiftop
);
16397 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
16400 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
16401 to perform a left shift. It must have exactly SHIFTOP least
16402 significant 0's, then one or more 1's, then zero or more 0's. */
16405 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
16407 if (GET_CODE (andop
) == CONST_INT
)
16409 unsigned HOST_WIDE_INT c
, lsb
, shift_mask
;
16411 c
= INTVAL (andop
);
16412 if (c
== 0 || c
== HOST_WIDE_INT_M1U
)
16415 shift_mask
= HOST_WIDE_INT_M1U
;
16416 shift_mask
<<= INTVAL (shiftop
);
16418 /* Find the least significant one bit. */
16421 /* It must coincide with the LSB of the shift mask. */
16422 if (-lsb
!= shift_mask
)
16425 /* Invert to look for the next transition (if any). */
16428 /* Remove the low group of ones (originally low group of zeros). */
16431 /* Again find the lsb, and check we have all 1's above. */
16439 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
16440 to perform a left shift. It must have SHIFTOP or more least
16441 significant 0's, with the remainder of the word 1's. */
16444 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
16446 if (GET_CODE (andop
) == CONST_INT
)
16448 unsigned HOST_WIDE_INT c
, lsb
, shift_mask
;
16450 shift_mask
= HOST_WIDE_INT_M1U
;
16451 shift_mask
<<= INTVAL (shiftop
);
16452 c
= INTVAL (andop
);
16454 /* Find the least significant one bit. */
16457 /* It must be covered by the shift mask.
16458 This test also rejects c == 0. */
16459 if ((lsb
& shift_mask
) == 0)
16462 /* Check we have all 1's above the transition, and reject all 1's. */
16463 return c
== -lsb
&& lsb
!= 1;
16469 /* Return 1 if operands will generate a valid arguments to rlwimi
16470 instruction for insert with right shift in 64-bit mode. The mask may
16471 not start on the first bit or stop on the last bit because wrap-around
16472 effects of instruction do not correspond to semantics of RTL insn. */
16475 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
16477 if (INTVAL (startop
) > 32
16478 && INTVAL (startop
) < 64
16479 && INTVAL (sizeop
) > 1
16480 && INTVAL (sizeop
) + INTVAL (startop
) < 64
16481 && INTVAL (shiftop
) > 0
16482 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
16483 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
16489 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
16490 for lfq and stfq insns iff the registers are hard registers. */
16493 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
16495 /* We might have been passed a SUBREG. */
16496 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
16499 /* We might have been passed non floating point registers. */
16500 if (!FP_REGNO_P (REGNO (reg1
))
16501 || !FP_REGNO_P (REGNO (reg2
)))
16504 return (REGNO (reg1
) == REGNO (reg2
) - 1);
16507 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
16508 addr1 and addr2 must be in consecutive memory locations
16509 (addr2 == addr1 + 8). */
16512 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
16515 unsigned int reg1
, reg2
;
16516 int offset1
, offset2
;
16518 /* The mems cannot be volatile. */
16519 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
16522 addr1
= XEXP (mem1
, 0);
16523 addr2
= XEXP (mem2
, 0);
16525 /* Extract an offset (if used) from the first addr. */
16526 if (GET_CODE (addr1
) == PLUS
)
16528 /* If not a REG, return zero. */
16529 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
16533 reg1
= REGNO (XEXP (addr1
, 0));
16534 /* The offset must be constant! */
16535 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
16537 offset1
= INTVAL (XEXP (addr1
, 1));
16540 else if (GET_CODE (addr1
) != REG
)
16544 reg1
= REGNO (addr1
);
16545 /* This was a simple (mem (reg)) expression. Offset is 0. */
16549 /* And now for the second addr. */
16550 if (GET_CODE (addr2
) == PLUS
)
16552 /* If not a REG, return zero. */
16553 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
16557 reg2
= REGNO (XEXP (addr2
, 0));
16558 /* The offset must be constant. */
16559 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
16561 offset2
= INTVAL (XEXP (addr2
, 1));
16564 else if (GET_CODE (addr2
) != REG
)
16568 reg2
= REGNO (addr2
);
16569 /* This was a simple (mem (reg)) expression. Offset is 0. */
16573 /* Both of these must have the same base register. */
16577 /* The offset for the second addr must be 8 more than the first addr. */
16578 if (offset2
!= offset1
+ 8)
16581 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
16588 rs6000_secondary_memory_needed_rtx (machine_mode mode
)
16590 static bool eliminated
= false;
16593 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
16594 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
16597 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
16598 gcc_assert (mem
!= NULL_RTX
);
16602 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
16603 cfun
->machine
->sdmode_stack_slot
= mem
;
16609 if (TARGET_DEBUG_ADDR
)
16611 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
16612 GET_MODE_NAME (mode
));
16614 fprintf (stderr
, "\tNULL_RTX\n");
16622 /* Return the mode to be used for memory when a secondary memory
16623 location is needed. For SDmode values we need to use DDmode, in
16624 all other cases we can use the same mode. */
16626 rs6000_secondary_memory_needed_mode (machine_mode mode
)
16628 if (lra_in_progress
&& mode
== SDmode
)
16634 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
16636 /* Don't walk into types. */
16637 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
16639 *walk_subtrees
= 0;
16643 switch (TREE_CODE (*tp
))
16652 case VIEW_CONVERT_EXPR
:
16653 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
16663 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
16664 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
16665 only work on the traditional altivec registers, note if an altivec register
16668 static enum rs6000_reg_type
16669 register_to_reg_type (rtx reg
, bool *is_altivec
)
16671 HOST_WIDE_INT regno
;
16672 enum reg_class rclass
;
16674 if (GET_CODE (reg
) == SUBREG
)
16675 reg
= SUBREG_REG (reg
);
16678 return NO_REG_TYPE
;
16680 regno
= REGNO (reg
);
16681 if (regno
>= FIRST_PSEUDO_REGISTER
)
16683 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
16684 return PSEUDO_REG_TYPE
;
16686 regno
= true_regnum (reg
);
16687 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16688 return PSEUDO_REG_TYPE
;
16691 gcc_assert (regno
>= 0);
16693 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
16694 *is_altivec
= true;
16696 rclass
= rs6000_regno_regclass
[regno
];
16697 return reg_class_to_reg_type
[(int)rclass
];
16700 /* Helper function to return the cost of adding a TOC entry address. */
16703 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
16707 if (TARGET_CMODEL
!= CMODEL_SMALL
)
16708 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
16711 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
16716 /* Helper function for rs6000_secondary_reload to determine whether the memory
16717 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
16718 needs reloading. Return negative if the memory is not handled by the memory
16719 helper functions and to try a different reload method, 0 if no additional
16720 instructions are need, and positive to give the extra cost for the
16724 rs6000_secondary_reload_memory (rtx addr
,
16725 enum reg_class rclass
,
16726 enum machine_mode mode
)
16728 int extra_cost
= 0;
16729 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
16730 addr_mask_type addr_mask
;
16731 const char *type
= NULL
;
16732 const char *fail_msg
= NULL
;
16734 if (GPR_REG_CLASS_P (rclass
))
16735 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
16737 else if (rclass
== FLOAT_REGS
)
16738 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
16740 else if (rclass
== ALTIVEC_REGS
)
16741 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
16743 /* For the combined VSX_REGS, turn off Altivec AND -16. */
16744 else if (rclass
== VSX_REGS
)
16745 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
16746 & ~RELOAD_REG_AND_M16
);
16750 if (TARGET_DEBUG_ADDR
)
16752 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
16753 "class is not GPR, FPR, VMX\n",
16754 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
16759 /* If the register isn't valid in this register class, just return now. */
16760 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
16762 if (TARGET_DEBUG_ADDR
)
16764 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
16765 "not valid in class\n",
16766 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
16771 switch (GET_CODE (addr
))
16773 /* Does the register class supports auto update forms for this mode? We
16774 don't need a scratch register, since the powerpc only supports
16775 PRE_INC, PRE_DEC, and PRE_MODIFY. */
16778 reg
= XEXP (addr
, 0);
16779 if (!base_reg_operand (addr
, GET_MODE (reg
)))
16781 fail_msg
= "no base register #1";
16785 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
16793 reg
= XEXP (addr
, 0);
16794 plus_arg1
= XEXP (addr
, 1);
16795 if (!base_reg_operand (reg
, GET_MODE (reg
))
16796 || GET_CODE (plus_arg1
) != PLUS
16797 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
16799 fail_msg
= "bad PRE_MODIFY";
16803 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
16810 /* Do we need to simulate AND -16 to clear the bottom address bits used
16811 in VMX load/stores? Only allow the AND for vector sizes. */
16813 and_arg
= XEXP (addr
, 0);
16814 if (GET_MODE_SIZE (mode
) != 16
16815 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
16816 || INTVAL (XEXP (addr
, 1)) != -16)
16818 fail_msg
= "bad Altivec AND #1";
16822 if (rclass
!= ALTIVEC_REGS
)
16824 if (legitimate_indirect_address_p (and_arg
, false))
16827 else if (legitimate_indexed_address_p (and_arg
, false))
16832 fail_msg
= "bad Altivec AND #2";
16840 /* If this is an indirect address, make sure it is a base register. */
16843 if (!legitimate_indirect_address_p (addr
, false))
16850 /* If this is an indexed address, make sure the register class can handle
16851 indexed addresses for this mode. */
16853 plus_arg0
= XEXP (addr
, 0);
16854 plus_arg1
= XEXP (addr
, 1);
16856 /* (plus (plus (reg) (constant)) (constant)) is generated during
16857 push_reload processing, so handle it now. */
16858 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
16860 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
16867 /* (plus (plus (reg) (constant)) (reg)) is also generated during
16868 push_reload processing, so handle it now. */
16869 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
16871 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
16874 type
= "indexed #2";
16878 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
16880 fail_msg
= "no base register #2";
16884 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
16886 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
16887 || !legitimate_indexed_address_p (addr
, false))
16894 /* Make sure the register class can handle offset addresses. */
16895 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
16897 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
16906 fail_msg
= "bad PLUS";
16913 if (!legitimate_lo_sum_address_p (mode
, addr
, false))
16915 fail_msg
= "bad LO_SUM";
16919 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
16926 /* Static addresses need to create a TOC entry. */
16931 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
16934 /* TOC references look like offsetable memory. */
16936 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
16938 fail_msg
= "bad UNSPEC";
16942 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
16945 type
= "toc reference";
16951 fail_msg
= "bad address";
16956 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
16958 if (extra_cost
< 0)
16960 "rs6000_secondary_reload_memory error: mode = %s, "
16961 "class = %s, addr_mask = '%s', %s\n",
16962 GET_MODE_NAME (mode
),
16963 reg_class_names
[rclass
],
16964 rs6000_debug_addr_mask (addr_mask
, false),
16965 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
16969 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
16970 "addr_mask = '%s', extra cost = %d, %s\n",
16971 GET_MODE_NAME (mode
),
16972 reg_class_names
[rclass
],
16973 rs6000_debug_addr_mask (addr_mask
, false),
16975 (type
) ? type
: "<none>");
16983 /* Helper function for rs6000_secondary_reload to return true if a move to a
16984 different register classe is really a simple move. */
16987 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
16988 enum rs6000_reg_type from_type
,
16993 /* Add support for various direct moves available. In this function, we only
16994 look at cases where we don't need any extra registers, and one or more
16995 simple move insns are issued. At present, 32-bit integers are not allowed
16996 in FPR/VSX registers. Single precision binary floating is not a simple
16997 move because we need to convert to the single precision memory layout.
16998 The 4-byte SDmode can be moved. */
16999 size
= GET_MODE_SIZE (mode
);
17000 if (TARGET_DIRECT_MOVE
17001 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
17002 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17003 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
17006 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
17007 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
17008 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
17011 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
17012 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
17013 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
17019 /* Power8 helper function for rs6000_secondary_reload, handle all of the
17020 special direct moves that involve allocating an extra register, return the
17021 insn code of the helper function if there is such a function or
17022 CODE_FOR_nothing if not. */
17025 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
17026 enum rs6000_reg_type from_type
,
17028 secondary_reload_info
*sri
,
17032 enum insn_code icode
= CODE_FOR_nothing
;
17034 int size
= GET_MODE_SIZE (mode
);
17036 if (TARGET_POWERPC64
)
17040 /* Handle moving 128-bit values from GPRs to VSX point registers on
17041 power8 when running in 64-bit mode using XXPERMDI to glue the two
17042 64-bit values back together. */
17043 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
17045 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
17046 icode
= reg_addr
[mode
].reload_vsx_gpr
;
17049 /* Handle moving 128-bit values from VSX point registers to GPRs on
17050 power8 when running in 64-bit mode using XXPERMDI to get access to the
17051 bottom 64-bit value. */
17052 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17054 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
17055 icode
= reg_addr
[mode
].reload_gpr_vsx
;
17059 else if (mode
== SFmode
)
17061 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17063 cost
= 3; /* xscvdpspn, mfvsrd, and. */
17064 icode
= reg_addr
[mode
].reload_gpr_vsx
;
17067 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
17069 cost
= 2; /* mtvsrz, xscvspdpn. */
17070 icode
= reg_addr
[mode
].reload_vsx_gpr
;
17075 if (TARGET_POWERPC64
&& size
== 16)
17077 /* Handle moving 128-bit values from GPRs to VSX point registers on
17078 power8 when running in 64-bit mode using XXPERMDI to glue the two
17079 64-bit values back together. */
17080 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
17082 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
17083 icode
= reg_addr
[mode
].reload_vsx_gpr
;
17086 /* Handle moving 128-bit values from VSX point registers to GPRs on
17087 power8 when running in 64-bit mode using XXPERMDI to get access to the
17088 bottom 64-bit value. */
17089 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
17091 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
17092 icode
= reg_addr
[mode
].reload_gpr_vsx
;
17096 else if (!TARGET_POWERPC64
&& size
== 8)
17098 /* Handle moving 64-bit values from GPRs to floating point registers on
17099 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
17100 values back together. Altivec register classes must be handled
17101 specially since a different instruction is used, and the secondary
17102 reload support requires a single instruction class in the scratch
17103 register constraint. However, right now TFmode is not allowed in
17104 Altivec registers, so the pattern will never match. */
17105 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
17107 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
17108 icode
= reg_addr
[mode
].reload_fpr_gpr
;
17112 if (icode
!= CODE_FOR_nothing
)
17117 sri
->icode
= icode
;
17118 sri
->extra_cost
= cost
;
17125 /* Return whether a move between two register classes can be done either
17126 directly (simple move) or via a pattern that uses a single extra temporary
17127 (using power8's direct move in this case. */
17130 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
17131 enum rs6000_reg_type from_type
,
17133 secondary_reload_info
*sri
,
17136 /* Fall back to load/store reloads if either type is not a register. */
17137 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
17140 /* If we haven't allocated registers yet, assume the move can be done for the
17141 standard register types. */
17142 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
17143 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
17144 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
17147 /* Moves to the same set of registers is a simple move for non-specialized
17149 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
17152 /* Check whether a simple move can be done directly. */
17153 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
17157 sri
->icode
= CODE_FOR_nothing
;
17158 sri
->extra_cost
= 0;
17163 /* Now check if we can do it in a few steps. */
17164 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
17168 /* Inform reload about cases where moving X with a mode MODE to a register in
17169 RCLASS requires an extra scratch or immediate register. Return the class
17170 needed for the immediate register.
17172 For VSX and Altivec, we may need a register to convert sp+offset into
17175 For misaligned 64-bit gpr loads and stores we need a register to
17176 convert an offset address to indirect. */
17179 rs6000_secondary_reload (bool in_p
,
17181 reg_class_t rclass_i
,
17183 secondary_reload_info
*sri
)
17185 enum reg_class rclass
= (enum reg_class
) rclass_i
;
17186 reg_class_t ret
= ALL_REGS
;
17187 enum insn_code icode
;
17188 bool default_p
= false;
17189 bool done_p
= false;
17191 /* Allow subreg of memory before/during reload. */
17192 bool memory_p
= (MEM_P (x
)
17193 || (!reload_completed
&& GET_CODE (x
) == SUBREG
17194 && MEM_P (SUBREG_REG (x
))));
17196 sri
->icode
= CODE_FOR_nothing
;
17197 sri
->extra_cost
= 0;
17199 ? reg_addr
[mode
].reload_load
17200 : reg_addr
[mode
].reload_store
);
17202 if (REG_P (x
) || register_operand (x
, mode
))
17204 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
17205 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
17206 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
17210 enum rs6000_reg_type exchange
= to_type
;
17211 to_type
= from_type
;
17212 from_type
= exchange
;
17215 /* Can we do a direct move of some sort? */
17216 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
17219 icode
= (enum insn_code
)sri
->icode
;
17226 /* Make sure 0.0 is not reloaded or forced into memory. */
17227 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
17234 /* If this is a scalar floating point value and we want to load it into the
17235 traditional Altivec registers, do it via a move via a traditional floating
17236 point register. Also make sure that non-zero constants use a FPR. */
17237 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
17238 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
17239 && (memory_p
|| (GET_CODE (x
) == CONST_DOUBLE
)))
17246 /* Handle reload of load/stores if we have reload helper functions. */
17247 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
17249 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
17252 if (extra_cost
>= 0)
17256 if (extra_cost
> 0)
17258 sri
->extra_cost
= extra_cost
;
17259 sri
->icode
= icode
;
17264 /* Handle unaligned loads and stores of integer registers. */
17265 if (!done_p
&& TARGET_POWERPC64
17266 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
17268 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
17270 rtx addr
= XEXP (x
, 0);
17271 rtx off
= address_offset (addr
);
17273 if (off
!= NULL_RTX
)
17275 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
17276 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
17278 /* We need a secondary reload when our legitimate_address_p
17279 says the address is good (as otherwise the entire address
17280 will be reloaded), and the offset is not a multiple of
17281 four or we have an address wrap. Address wrap will only
17282 occur for LO_SUMs since legitimate_offset_address_p
17283 rejects addresses for 16-byte mems that will wrap. */
17284 if (GET_CODE (addr
) == LO_SUM
17285 ? (1 /* legitimate_address_p allows any offset for lo_sum */
17286 && ((offset
& 3) != 0
17287 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
17288 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
17289 && (offset
& 3) != 0))
17291 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
17293 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
17294 : CODE_FOR_reload_di_load
);
17296 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
17297 : CODE_FOR_reload_di_store
);
17298 sri
->extra_cost
= 2;
17309 if (!done_p
&& !TARGET_POWERPC64
17310 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
17312 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
17314 rtx addr
= XEXP (x
, 0);
17315 rtx off
= address_offset (addr
);
17317 if (off
!= NULL_RTX
)
17319 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
17320 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
17322 /* We need a secondary reload when our legitimate_address_p
17323 says the address is good (as otherwise the entire address
17324 will be reloaded), and we have a wrap.
17326 legitimate_lo_sum_address_p allows LO_SUM addresses to
17327 have any offset so test for wrap in the low 16 bits.
17329 legitimate_offset_address_p checks for the range
17330 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
17331 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
17332 [0x7ff4,0x7fff] respectively, so test for the
17333 intersection of these ranges, [0x7ffc,0x7fff] and
17334 [0x7ff4,0x7ff7] respectively.
17336 Note that the address we see here may have been
17337 manipulated by legitimize_reload_address. */
17338 if (GET_CODE (addr
) == LO_SUM
17339 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
17340 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
17343 sri
->icode
= CODE_FOR_reload_si_load
;
17345 sri
->icode
= CODE_FOR_reload_si_store
;
17346 sri
->extra_cost
= 2;
17361 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
17363 gcc_assert (ret
!= ALL_REGS
);
17365 if (TARGET_DEBUG_ADDR
)
17368 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
17370 reg_class_names
[ret
],
17371 in_p
? "true" : "false",
17372 reg_class_names
[rclass
],
17373 GET_MODE_NAME (mode
));
17375 if (reload_completed
)
17376 fputs (", after reload", stderr
);
17379 fputs (", done_p not set", stderr
);
17382 fputs (", default secondary reload", stderr
);
17384 if (sri
->icode
!= CODE_FOR_nothing
)
17385 fprintf (stderr
, ", reload func = %s, extra cost = %d",
17386 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
17388 fputs ("\n", stderr
);
17395 /* Better tracing for rs6000_secondary_reload_inner. */
17398 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
17403 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
17405 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
17406 store_p
? "store" : "load");
17409 set
= gen_rtx_SET (mem
, reg
);
17411 set
= gen_rtx_SET (reg
, mem
);
17413 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
17414 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
17417 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
17418 ATTRIBUTE_NORETURN
;
17421 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
17424 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
17425 gcc_unreachable ();
17428 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
17429 reload helper functions. These were identified in
17430 rs6000_secondary_reload_memory, and if reload decided to use the secondary
17431 reload, it calls the insns:
17432 reload_<RELOAD:mode>_<P:mptrsize>_store
17433 reload_<RELOAD:mode>_<P:mptrsize>_load
17435 which in turn calls this function, to do whatever is necessary to create
17436 valid addresses. */
17439 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
17441 int regno
= true_regnum (reg
);
17442 machine_mode mode
= GET_MODE (reg
);
17443 addr_mask_type addr_mask
;
17446 rtx op_reg
, op0
, op1
;
17451 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
|| !MEM_P (mem
)
17452 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
17453 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17455 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
17456 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
17458 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
17459 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
17461 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
17462 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
17465 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17467 /* Make sure the mode is valid in this register class. */
17468 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
17469 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17471 if (TARGET_DEBUG_ADDR
)
17472 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
17474 new_addr
= addr
= XEXP (mem
, 0);
17475 switch (GET_CODE (addr
))
17477 /* Does the register class support auto update forms for this mode? If
17478 not, do the update now. We don't need a scratch register, since the
17479 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
17482 op_reg
= XEXP (addr
, 0);
17483 if (!base_reg_operand (op_reg
, Pmode
))
17484 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17486 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
17488 emit_insn (gen_add2_insn (op_reg
, GEN_INT (GET_MODE_SIZE (mode
))));
17494 op0
= XEXP (addr
, 0);
17495 op1
= XEXP (addr
, 1);
17496 if (!base_reg_operand (op0
, Pmode
)
17497 || GET_CODE (op1
) != PLUS
17498 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
17499 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17501 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
17503 emit_insn (gen_rtx_SET (op0
, op1
));
17508 /* Do we need to simulate AND -16 to clear the bottom address bits used
17509 in VMX load/stores? */
17511 op0
= XEXP (addr
, 0);
17512 op1
= XEXP (addr
, 1);
17513 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
17515 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
17518 else if (GET_CODE (op1
) == PLUS
)
17520 emit_insn (gen_rtx_SET (scratch
, op1
));
17525 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17527 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
17528 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
17529 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
17530 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
17531 new_addr
= scratch
;
17535 /* If this is an indirect address, make sure it is a base register. */
17538 if (!base_reg_operand (addr
, GET_MODE (addr
)))
17540 emit_insn (gen_rtx_SET (scratch
, addr
));
17541 new_addr
= scratch
;
17545 /* If this is an indexed address, make sure the register class can handle
17546 indexed addresses for this mode. */
17548 op0
= XEXP (addr
, 0);
17549 op1
= XEXP (addr
, 1);
17550 if (!base_reg_operand (op0
, Pmode
))
17551 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17553 else if (int_reg_operand (op1
, Pmode
))
17555 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
17557 emit_insn (gen_rtx_SET (scratch
, addr
));
17558 new_addr
= scratch
;
17562 /* Make sure the register class can handle offset addresses. */
17563 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
17565 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17567 emit_insn (gen_rtx_SET (scratch
, addr
));
17568 new_addr
= scratch
;
17573 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17578 op0
= XEXP (addr
, 0);
17579 op1
= XEXP (addr
, 1);
17580 if (!base_reg_operand (op0
, Pmode
))
17581 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17583 else if (int_reg_operand (op1
, Pmode
))
17585 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
17587 emit_insn (gen_rtx_SET (scratch
, addr
));
17588 new_addr
= scratch
;
17592 /* Make sure the register class can handle offset addresses. */
17593 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
17595 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
17597 emit_insn (gen_rtx_SET (scratch
, addr
));
17598 new_addr
= scratch
;
17603 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17610 rs6000_emit_move (scratch
, addr
, Pmode
);
17611 new_addr
= scratch
;
17615 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
17618 /* Adjust the address if it changed. */
17619 if (addr
!= new_addr
)
17621 mem
= replace_equiv_address_nv (mem
, new_addr
);
17622 if (TARGET_DEBUG_ADDR
)
17623 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
17626 /* Now create the move. */
17628 emit_insn (gen_rtx_SET (mem
, reg
));
17630 emit_insn (gen_rtx_SET (reg
, mem
));
17635 /* Convert reloads involving 64-bit gprs and misaligned offset
17636 addressing, or multiple 32-bit gprs and offsets that are too large,
17637 to use indirect addressing. */
17640 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
17642 int regno
= true_regnum (reg
);
17643 enum reg_class rclass
;
17645 rtx scratch_or_premodify
= scratch
;
17647 if (TARGET_DEBUG_ADDR
)
17649 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
17650 store_p
? "store" : "load");
17651 fprintf (stderr
, "reg:\n");
17653 fprintf (stderr
, "mem:\n");
17655 fprintf (stderr
, "scratch:\n");
17656 debug_rtx (scratch
);
17659 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
17660 gcc_assert (GET_CODE (mem
) == MEM
);
17661 rclass
= REGNO_REG_CLASS (regno
);
17662 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
17663 addr
= XEXP (mem
, 0);
17665 if (GET_CODE (addr
) == PRE_MODIFY
)
17667 scratch_or_premodify
= XEXP (addr
, 0);
17668 gcc_assert (REG_P (scratch_or_premodify
));
17669 addr
= XEXP (addr
, 1);
17671 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
17673 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
17675 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
17677 /* Now create the move. */
17679 emit_insn (gen_rtx_SET (mem
, reg
));
17681 emit_insn (gen_rtx_SET (reg
, mem
));
17686 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
17687 this function has any SDmode references. If we are on a power7 or later, we
17688 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
17689 can load/store the value. */
17692 rs6000_alloc_sdmode_stack_slot (void)
17696 gimple_stmt_iterator gsi
;
17698 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
17699 /* We use a different approach for dealing with the secondary
17704 if (TARGET_NO_SDMODE_STACK
)
17707 FOR_EACH_BB_FN (bb
, cfun
)
17708 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
17710 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
17713 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17714 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17720 /* Check for any SDmode parameters of the function. */
17721 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
17723 if (TREE_TYPE (t
) == error_mark_node
)
17726 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
17727 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
17729 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
17730 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
17738 rs6000_instantiate_decls (void)
17740 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
17741 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
17744 /* Given an rtx X being reloaded into a reg required to be
17745 in class CLASS, return the class of reg to actually use.
17746 In general this is just CLASS; but on some machines
17747 in some cases it is preferable to use a more restrictive class.
17749 On the RS/6000, we have to return NO_REGS when we want to reload a
17750 floating-point CONST_DOUBLE to force it to be copied to memory.
17752 We also don't want to reload integer values into floating-point
17753 registers if we can at all help it. In fact, this can
17754 cause reload to die, if it tries to generate a reload of CTR
17755 into a FP register and discovers it doesn't have the memory location
17758 ??? Would it be a good idea to have reload do the converse, that is
17759 try to reload floating modes into FP registers if possible?
17762 static enum reg_class
17763 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
17765 machine_mode mode
= GET_MODE (x
);
17766 bool is_constant
= CONSTANT_P (x
);
17768 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
17769 the reloading of address expressions using PLUS into floating point
17771 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
17775 /* Zero is always allowed in all VSX registers. */
17776 if (x
== CONST0_RTX (mode
))
17779 /* If this is a vector constant that can be formed with a few Altivec
17780 instructions, we want altivec registers. */
17781 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
17782 return ALTIVEC_REGS
;
17784 /* Force constant to memory. */
17788 /* If this is a scalar floating point value, prefer the traditional
17789 floating point registers so that we can use D-form (register+offset)
17791 if (GET_MODE_SIZE (mode
) < 16)
17794 /* Prefer the Altivec registers if Altivec is handling the vector
17795 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
17797 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
17798 || mode
== V1TImode
)
17799 return ALTIVEC_REGS
;
17804 if (is_constant
|| GET_CODE (x
) == PLUS
)
17806 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
17807 return GENERAL_REGS
;
17808 if (reg_class_subset_p (BASE_REGS
, rclass
))
17813 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
17814 return GENERAL_REGS
;
17819 /* Debug version of rs6000_preferred_reload_class. */
17820 static enum reg_class
17821 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
17823 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
17826 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
17828 reg_class_names
[ret
], reg_class_names
[rclass
],
17829 GET_MODE_NAME (GET_MODE (x
)));
17835 /* If we are copying between FP or AltiVec registers and anything else, we need
17836 a memory location. The exception is when we are targeting ppc64 and the
17837 move to/from fpr to gpr instructions are available. Also, under VSX, you
17838 can copy vector registers from the FP register set to the Altivec register
17839 set and vice versa. */
17842 rs6000_secondary_memory_needed (enum reg_class from_class
,
17843 enum reg_class to_class
,
17846 enum rs6000_reg_type from_type
, to_type
;
17847 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
17848 || (to_class
== ALTIVEC_REGS
));
17850 /* If a simple/direct move is available, we don't need secondary memory */
17851 from_type
= reg_class_to_reg_type
[(int)from_class
];
17852 to_type
= reg_class_to_reg_type
[(int)to_class
];
17854 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
17855 (secondary_reload_info
*)0, altivec_p
))
17858 /* If we have a floating point or vector register class, we need to use
17859 memory to transfer the data. */
17860 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
17866 /* Debug version of rs6000_secondary_memory_needed. */
17868 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
17869 enum reg_class to_class
,
17872 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
17875 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
17876 "to_class = %s, mode = %s\n",
17877 ret
? "true" : "false",
17878 reg_class_names
[from_class
],
17879 reg_class_names
[to_class
],
17880 GET_MODE_NAME (mode
));
17885 /* Return the register class of a scratch register needed to copy IN into
17886 or out of a register in RCLASS in MODE. If it can be done directly,
17887 NO_REGS is returned. */
17889 static enum reg_class
17890 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
17895 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
17897 && MACHOPIC_INDIRECT
17901 /* We cannot copy a symbolic operand directly into anything
17902 other than BASE_REGS for TARGET_ELF. So indicate that a
17903 register from BASE_REGS is needed as an intermediate
17906 On Darwin, pic addresses require a load from memory, which
17907 needs a base register. */
17908 if (rclass
!= BASE_REGS
17909 && (GET_CODE (in
) == SYMBOL_REF
17910 || GET_CODE (in
) == HIGH
17911 || GET_CODE (in
) == LABEL_REF
17912 || GET_CODE (in
) == CONST
))
17916 if (GET_CODE (in
) == REG
)
17918 regno
= REGNO (in
);
17919 if (regno
>= FIRST_PSEUDO_REGISTER
)
17921 regno
= true_regnum (in
);
17922 if (regno
>= FIRST_PSEUDO_REGISTER
)
17926 else if (GET_CODE (in
) == SUBREG
)
17928 regno
= true_regnum (in
);
17929 if (regno
>= FIRST_PSEUDO_REGISTER
)
17935 /* If we have VSX register moves, prefer moving scalar values between
17936 Altivec registers and GPR by going via an FPR (and then via memory)
17937 instead of reloading the secondary memory address for Altivec moves. */
17939 && GET_MODE_SIZE (mode
) < 16
17940 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
17941 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
17942 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
17943 && (regno
>= 0 && INT_REGNO_P (regno
)))))
17946 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
17948 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
17949 || (regno
>= 0 && INT_REGNO_P (regno
)))
17952 /* Constants, memory, and VSX registers can go into VSX registers (both the
17953 traditional floating point and the altivec registers). */
17954 if (rclass
== VSX_REGS
17955 && (regno
== -1 || VSX_REGNO_P (regno
)))
17958 /* Constants, memory, and FP registers can go into FP registers. */
17959 if ((regno
== -1 || FP_REGNO_P (regno
))
17960 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
17961 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
17963 /* Memory, and AltiVec registers can go into AltiVec registers. */
17964 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
17965 && rclass
== ALTIVEC_REGS
)
17968 /* We can copy among the CR registers. */
17969 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
17970 && regno
>= 0 && CR_REGNO_P (regno
))
17973 /* Otherwise, we need GENERAL_REGS. */
17974 return GENERAL_REGS
;
17977 /* Debug version of rs6000_secondary_reload_class. */
17978 static enum reg_class
17979 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
17980 machine_mode mode
, rtx in
)
17982 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
17984 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
17985 "mode = %s, input rtx:\n",
17986 reg_class_names
[ret
], reg_class_names
[rclass
],
17987 GET_MODE_NAME (mode
));
17993 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
17996 rs6000_cannot_change_mode_class (machine_mode from
,
17998 enum reg_class rclass
)
18000 unsigned from_size
= GET_MODE_SIZE (from
);
18001 unsigned to_size
= GET_MODE_SIZE (to
);
18003 if (from_size
!= to_size
)
18005 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
18007 if (reg_classes_intersect_p (xclass
, rclass
))
18009 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
18010 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
18012 /* Don't allow 64-bit types to overlap with 128-bit types that take a
18013 single register under VSX because the scalar part of the register
18014 is in the upper 64-bits, and not the lower 64-bits. Types like
18015 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
18016 IEEE floating point can't overlap, and neither can small
18019 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
18022 /* TDmode in floating-mode registers must always go into a register
18023 pair with the most significant word in the even-numbered register
18024 to match ISA requirements. In little-endian mode, this does not
18025 match subreg numbering, so we cannot allow subregs. */
18026 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
18029 if (from_size
< 8 || to_size
< 8)
18032 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
18035 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
18044 if (TARGET_E500_DOUBLE
18045 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
18046 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
18047 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
18048 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
18049 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
18052 /* Since the VSX register set includes traditional floating point registers
18053 and altivec registers, just check for the size being different instead of
18054 trying to check whether the modes are vector modes. Otherwise it won't
18055 allow say DF and DI to change classes. For types like TFmode and TDmode
18056 that take 2 64-bit registers, rather than a single 128-bit register, don't
18057 allow subregs of those types to other 128 bit types. */
18058 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
18060 unsigned num_regs
= (from_size
+ 15) / 16;
18061 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
18062 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
18065 return (from_size
!= 8 && from_size
!= 16);
18068 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
18069 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
18072 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
18073 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
18079 /* Debug version of rs6000_cannot_change_mode_class. */
18081 rs6000_debug_cannot_change_mode_class (machine_mode from
,
18083 enum reg_class rclass
)
18085 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
18088 "rs6000_cannot_change_mode_class, return %s, from = %s, "
18089 "to = %s, rclass = %s\n",
18090 ret
? "true" : "false",
18091 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
18092 reg_class_names
[rclass
]);
18097 /* Return a string to do a move operation of 128 bits of data. */
18100 rs6000_output_move_128bit (rtx operands
[])
18102 rtx dest
= operands
[0];
18103 rtx src
= operands
[1];
18104 machine_mode mode
= GET_MODE (dest
);
18107 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
18108 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
18112 dest_regno
= REGNO (dest
);
18113 dest_gpr_p
= INT_REGNO_P (dest_regno
);
18114 dest_fp_p
= FP_REGNO_P (dest_regno
);
18115 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
18116 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
18121 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
18126 src_regno
= REGNO (src
);
18127 src_gpr_p
= INT_REGNO_P (src_regno
);
18128 src_fp_p
= FP_REGNO_P (src_regno
);
18129 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
18130 src_vsx_p
= src_fp_p
| src_vmx_p
;
18135 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
18138 /* Register moves. */
18139 if (dest_regno
>= 0 && src_regno
>= 0)
18146 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
18150 else if (TARGET_VSX
&& dest_vsx_p
)
18153 return "xxlor %x0,%x1,%x1";
18155 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
18159 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
18160 return "vor %0,%1,%1";
18162 else if (dest_fp_p
&& src_fp_p
)
18167 else if (dest_regno
>= 0 && MEM_P (src
))
18171 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
18177 else if (TARGET_ALTIVEC
&& dest_vmx_p
18178 && altivec_indexed_or_indirect_operand (src
, mode
))
18179 return "lvx %0,%y1";
18181 else if (TARGET_VSX
&& dest_vsx_p
)
18183 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
18184 return "lxvw4x %x0,%y1";
18186 return "lxvd2x %x0,%y1";
18189 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
18190 return "lvx %0,%y1";
18192 else if (dest_fp_p
)
18197 else if (src_regno
>= 0 && MEM_P (dest
))
18201 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
18202 return "stq %1,%0";
18207 else if (TARGET_ALTIVEC
&& src_vmx_p
18208 && altivec_indexed_or_indirect_operand (src
, mode
))
18209 return "stvx %1,%y0";
18211 else if (TARGET_VSX
&& src_vsx_p
)
18213 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
18214 return "stxvw4x %x1,%y0";
18216 return "stxvd2x %x1,%y0";
18219 else if (TARGET_ALTIVEC
&& src_vmx_p
)
18220 return "stvx %1,%y0";
18227 else if (dest_regno
>= 0
18228 && (GET_CODE (src
) == CONST_INT
18229 || GET_CODE (src
) == CONST_WIDE_INT
18230 || GET_CODE (src
) == CONST_DOUBLE
18231 || GET_CODE (src
) == CONST_VECTOR
))
18236 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
18237 return "xxlxor %x0,%x0,%x0";
18239 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
18240 return output_vec_const_move (operands
);
18243 if (TARGET_DEBUG_ADDR
)
18245 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
18246 debug_rtx (gen_rtx_SET (dest
, src
));
18249 gcc_unreachable ();
18252 /* Validate a 128-bit move. */
18254 rs6000_move_128bit_ok_p (rtx operands
[])
18256 machine_mode mode
= GET_MODE (operands
[0]);
18257 return (gpc_reg_operand (operands
[0], mode
)
18258 || gpc_reg_operand (operands
[1], mode
));
18261 /* Return true if a 128-bit move needs to be split. */
18263 rs6000_split_128bit_ok_p (rtx operands
[])
18265 if (!reload_completed
)
18268 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
18271 if (quad_load_store_p (operands
[0], operands
[1]))
18278 /* Given a comparison operation, return the bit number in CCR to test. We
18279 know this is a valid comparison.
18281 SCC_P is 1 if this is for an scc. That means that %D will have been
18282 used instead of %C, so the bits will be in different places.
18284 Return -1 if OP isn't a valid comparison for some reason. */
18287 ccr_bit (rtx op
, int scc_p
)
18289 enum rtx_code code
= GET_CODE (op
);
18290 machine_mode cc_mode
;
18295 if (!COMPARISON_P (op
))
18298 reg
= XEXP (op
, 0);
18300 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
18302 cc_mode
= GET_MODE (reg
);
18303 cc_regnum
= REGNO (reg
);
18304 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
18306 validate_condition_mode (code
, cc_mode
);
18308 /* When generating a sCOND operation, only positive conditions are
18311 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
18312 || code
== GTU
|| code
== LTU
);
18317 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
18319 return base_bit
+ 2;
18320 case GT
: case GTU
: case UNLE
:
18321 return base_bit
+ 1;
18322 case LT
: case LTU
: case UNGE
:
18324 case ORDERED
: case UNORDERED
:
18325 return base_bit
+ 3;
18328 /* If scc, we will have done a cror to put the bit in the
18329 unordered position. So test that bit. For integer, this is ! LT
18330 unless this is an scc insn. */
18331 return scc_p
? base_bit
+ 3 : base_bit
;
18334 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
18337 gcc_unreachable ();
18341 /* Return the GOT register. */
18344 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
18346 /* The second flow pass currently (June 1999) can't update
18347 regs_ever_live without disturbing other parts of the compiler, so
18348 update it here to make the prolog/epilogue code happy. */
18349 if (!can_create_pseudo_p ()
18350 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
18351 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
18353 crtl
->uses_pic_offset_table
= 1;
18355 return pic_offset_table_rtx
;
18358 static rs6000_stack_t stack_info
;
18360 /* Function to init struct machine_function.
18361 This will be called, via a pointer variable,
18362 from push_function_context. */
18364 static struct machine_function
*
18365 rs6000_init_machine_status (void)
18367 stack_info
.reload_completed
= 0;
18368 return ggc_cleared_alloc
<machine_function
> ();
18371 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
18374 extract_MB (rtx op
)
18377 unsigned long val
= INTVAL (op
);
18379 /* If the high bit is zero, the value is the first 1 bit we find
18381 if ((val
& 0x80000000) == 0)
18383 gcc_assert (val
& 0xffffffff);
18386 while (((val
<<= 1) & 0x80000000) == 0)
18391 /* If the high bit is set and the low bit is not, or the mask is all
18392 1's, the value is zero. */
18393 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
18396 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
18399 while (((val
>>= 1) & 1) != 0)
18406 extract_ME (rtx op
)
18409 unsigned long val
= INTVAL (op
);
18411 /* If the low bit is zero, the value is the first 1 bit we find from
18413 if ((val
& 1) == 0)
18415 gcc_assert (val
& 0xffffffff);
18418 while (((val
>>= 1) & 1) == 0)
18424 /* If the low bit is set and the high bit is not, or the mask is all
18425 1's, the value is 31. */
18426 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
18429 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
18432 while (((val
<<= 1) & 0x80000000) != 0)
18438 /* Write out a function code label. */
18441 rs6000_output_function_entry (FILE *file
, const char *fname
)
18443 if (fname
[0] != '.')
18445 switch (DEFAULT_ABI
)
18448 gcc_unreachable ();
18454 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
18464 RS6000_OUTPUT_BASENAME (file
, fname
);
18467 /* Print an operand. Recognize special options, documented below. */
18470 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
18471 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
18473 #define SMALL_DATA_RELOC "sda21"
18474 #define SMALL_DATA_REG 0
18478 print_operand (FILE *file
, rtx x
, int code
)
18481 unsigned HOST_WIDE_INT uval
;
18485 /* %a is output_address. */
18488 /* If constant, low-order 16 bits of constant, unsigned.
18489 Otherwise, write normally. */
18491 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
18493 print_operand (file
, x
, 0);
18497 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
18498 for 64-bit mask direction. */
18499 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
18502 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
18506 /* Like 'J' but get to the GT bit only. */
18507 gcc_assert (REG_P (x
));
18509 /* Bit 1 is GT bit. */
18510 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
18512 /* Add one for shift count in rlinm for scc. */
18513 fprintf (file
, "%d", i
+ 1);
18517 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
18520 output_operand_lossage ("invalid %%e value");
18525 if ((uval
& 0xffff) == 0 && uval
!= 0)
18530 /* X is a CR register. Print the number of the EQ bit of the CR */
18531 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18532 output_operand_lossage ("invalid %%E value");
18534 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
18538 /* X is a CR register. Print the shift count needed to move it
18539 to the high-order four bits. */
18540 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18541 output_operand_lossage ("invalid %%f value");
18543 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
18547 /* Similar, but print the count for the rotate in the opposite
18549 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18550 output_operand_lossage ("invalid %%F value");
18552 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
18556 /* X is a constant integer. If it is negative, print "m",
18557 otherwise print "z". This is to make an aze or ame insn. */
18558 if (GET_CODE (x
) != CONST_INT
)
18559 output_operand_lossage ("invalid %%G value");
18560 else if (INTVAL (x
) >= 0)
18567 /* If constant, output low-order five bits. Otherwise, write
18570 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
18572 print_operand (file
, x
, 0);
18576 /* If constant, output low-order six bits. Otherwise, write
18579 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
18581 print_operand (file
, x
, 0);
18585 /* Print `i' if this is a constant, else nothing. */
18591 /* Write the bit number in CCR for jump. */
18592 i
= ccr_bit (x
, 0);
18594 output_operand_lossage ("invalid %%j code");
18596 fprintf (file
, "%d", i
);
18600 /* Similar, but add one for shift count in rlinm for scc and pass
18601 scc flag to `ccr_bit'. */
18602 i
= ccr_bit (x
, 1);
18604 output_operand_lossage ("invalid %%J code");
18606 /* If we want bit 31, write a shift count of zero, not 32. */
18607 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
18611 /* X must be a constant. Write the 1's complement of the
18614 output_operand_lossage ("invalid %%k value");
18616 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
18620 /* X must be a symbolic constant on ELF. Write an
18621 expression suitable for an 'addi' that adds in the low 16
18622 bits of the MEM. */
18623 if (GET_CODE (x
) == CONST
)
18625 if (GET_CODE (XEXP (x
, 0)) != PLUS
18626 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
18627 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
18628 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
18629 output_operand_lossage ("invalid %%K value");
18631 print_operand_address (file
, x
);
18632 fputs ("@l", file
);
18635 /* %l is output_asm_label. */
18638 /* Write second word of DImode or DFmode reference. Works on register
18639 or non-indexed memory only. */
18641 fputs (reg_names
[REGNO (x
) + 1], file
);
18642 else if (MEM_P (x
))
18644 /* Handle possible auto-increment. Since it is pre-increment and
18645 we have already done it, we can just use an offset of word. */
18646 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18647 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18648 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
18650 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18651 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
18654 output_address (XEXP (adjust_address_nv (x
, SImode
,
18658 if (small_data_operand (x
, GET_MODE (x
)))
18659 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18660 reg_names
[SMALL_DATA_REG
]);
18665 /* MB value for a mask operand. */
18666 if (! mask_operand (x
, SImode
))
18667 output_operand_lossage ("invalid %%m value");
18669 fprintf (file
, "%d", extract_MB (x
));
18673 /* ME value for a mask operand. */
18674 if (! mask_operand (x
, SImode
))
18675 output_operand_lossage ("invalid %%M value");
18677 fprintf (file
, "%d", extract_ME (x
));
18680 /* %n outputs the negative of its operand. */
18683 /* Write the number of elements in the vector times 4. */
18684 if (GET_CODE (x
) != PARALLEL
)
18685 output_operand_lossage ("invalid %%N value");
18687 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
18691 /* Similar, but subtract 1 first. */
18692 if (GET_CODE (x
) != PARALLEL
)
18693 output_operand_lossage ("invalid %%O value");
18695 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
18699 /* X is a CONST_INT that is a power of two. Output the logarithm. */
18702 || (i
= exact_log2 (INTVAL (x
))) < 0)
18703 output_operand_lossage ("invalid %%p value");
18705 fprintf (file
, "%d", i
);
18709 /* The operand must be an indirect memory reference. The result
18710 is the register name. */
18711 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
18712 || REGNO (XEXP (x
, 0)) >= 32)
18713 output_operand_lossage ("invalid %%P value");
18715 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
18719 /* This outputs the logical code corresponding to a boolean
18720 expression. The expression may have one or both operands
18721 negated (if one, only the first one). For condition register
18722 logical operations, it will also treat the negated
18723 CR codes as NOTs, but not handle NOTs of them. */
18725 const char *const *t
= 0;
18727 enum rtx_code code
= GET_CODE (x
);
18728 static const char * const tbl
[3][3] = {
18729 { "and", "andc", "nor" },
18730 { "or", "orc", "nand" },
18731 { "xor", "eqv", "xor" } };
18735 else if (code
== IOR
)
18737 else if (code
== XOR
)
18740 output_operand_lossage ("invalid %%q value");
18742 if (GET_CODE (XEXP (x
, 0)) != NOT
)
18746 if (GET_CODE (XEXP (x
, 1)) == NOT
)
18757 if (! TARGET_MFCRF
)
18763 /* X is a CR register. Print the mask for `mtcrf'. */
18764 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
18765 output_operand_lossage ("invalid %%R value");
18767 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
18771 /* Low 5 bits of 32 - value */
18773 output_operand_lossage ("invalid %%s value");
18775 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
18779 /* PowerPC64 mask position. All 0's is excluded.
18780 CONST_INT 32-bit mask is considered sign-extended so any
18781 transition must occur within the CONST_INT, not on the boundary. */
18782 if (! mask64_operand (x
, DImode
))
18783 output_operand_lossage ("invalid %%S value");
18787 if (uval
& 1) /* Clear Left */
18789 #if HOST_BITS_PER_WIDE_INT > 64
18790 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18794 else /* Clear Right */
18797 #if HOST_BITS_PER_WIDE_INT > 64
18798 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
18804 gcc_assert (i
>= 0);
18805 fprintf (file
, "%d", i
);
18809 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
18810 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
18812 /* Bit 3 is OV bit. */
18813 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
18815 /* If we want bit 31, write a shift count of zero, not 32. */
18816 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
18820 /* Print the symbolic name of a branch target register. */
18821 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
18822 && REGNO (x
) != CTR_REGNO
))
18823 output_operand_lossage ("invalid %%T value");
18824 else if (REGNO (x
) == LR_REGNO
)
18825 fputs ("lr", file
);
18827 fputs ("ctr", file
);
18831 /* High-order or low-order 16 bits of constant, whichever is non-zero,
18832 for use in unsigned operand. */
18835 output_operand_lossage ("invalid %%u value");
18840 if ((uval
& 0xffff) == 0)
18843 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
18847 /* High-order 16 bits of constant for use in signed operand. */
18849 output_operand_lossage ("invalid %%v value");
18851 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
18852 (INTVAL (x
) >> 16) & 0xffff);
18856 /* Print `u' if this has an auto-increment or auto-decrement. */
18858 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
18859 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
18860 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
18865 /* Print the trap code for this operand. */
18866 switch (GET_CODE (x
))
18869 fputs ("eq", file
); /* 4 */
18872 fputs ("ne", file
); /* 24 */
18875 fputs ("lt", file
); /* 16 */
18878 fputs ("le", file
); /* 20 */
18881 fputs ("gt", file
); /* 8 */
18884 fputs ("ge", file
); /* 12 */
18887 fputs ("llt", file
); /* 2 */
18890 fputs ("lle", file
); /* 6 */
18893 fputs ("lgt", file
); /* 1 */
18896 fputs ("lge", file
); /* 5 */
18899 gcc_unreachable ();
18904 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
18907 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
18908 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
18910 print_operand (file
, x
, 0);
18914 /* MB value for a PowerPC64 rldic operand. */
18915 i
= clz_hwi (INTVAL (x
));
18917 fprintf (file
, "%d", i
);
18921 /* X is a FPR or Altivec register used in a VSX context. */
18922 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
18923 output_operand_lossage ("invalid %%x value");
18926 int reg
= REGNO (x
);
18927 int vsx_reg
= (FP_REGNO_P (reg
)
18929 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
18931 #ifdef TARGET_REGNAMES
18932 if (TARGET_REGNAMES
)
18933 fprintf (file
, "%%vs%d", vsx_reg
);
18936 fprintf (file
, "%d", vsx_reg
);
18942 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
18943 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
18944 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
18949 /* Like 'L', for third word of TImode/PTImode */
18951 fputs (reg_names
[REGNO (x
) + 2], file
);
18952 else if (MEM_P (x
))
18954 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
18955 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
18956 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18957 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
18958 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
18960 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
18961 if (small_data_operand (x
, GET_MODE (x
)))
18962 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
18963 reg_names
[SMALL_DATA_REG
]);
18968 /* X is a SYMBOL_REF. Write out the name preceded by a
18969 period and without any trailing data in brackets. Used for function
18970 names. If we are configured for System V (or the embedded ABI) on
18971 the PowerPC, do not emit the period, since those systems do not use
18972 TOCs and the like. */
18973 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
18975 /* For macho, check to see if we need a stub. */
18978 const char *name
= XSTR (x
, 0);
18980 if (darwin_emit_branch_islands
18981 && MACHOPIC_INDIRECT
18982 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
18983 name
= machopic_indirection_name (x
, /*stub_p=*/true);
18985 assemble_name (file
, name
);
18987 else if (!DOT_SYMBOLS
)
18988 assemble_name (file
, XSTR (x
, 0));
18990 rs6000_output_function_entry (file
, XSTR (x
, 0));
18994 /* Like 'L', for last word of TImode/PTImode. */
18996 fputs (reg_names
[REGNO (x
) + 3], file
);
18997 else if (MEM_P (x
))
18999 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
19000 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19001 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
19002 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19003 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
19005 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
19006 if (small_data_operand (x
, GET_MODE (x
)))
19007 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19008 reg_names
[SMALL_DATA_REG
]);
19012 /* Print AltiVec or SPE memory operand. */
19017 gcc_assert (MEM_P (x
));
19021 /* Ugly hack because %y is overloaded. */
19022 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
19023 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
19024 || GET_MODE (x
) == TFmode
19025 || GET_MODE (x
) == TImode
19026 || GET_MODE (x
) == PTImode
))
19028 /* Handle [reg]. */
19031 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
19034 /* Handle [reg+UIMM]. */
19035 else if (GET_CODE (tmp
) == PLUS
&&
19036 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
19040 gcc_assert (REG_P (XEXP (tmp
, 0)));
19042 x
= INTVAL (XEXP (tmp
, 1));
19043 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
19047 /* Fall through. Must be [reg+reg]. */
19049 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
19050 && GET_CODE (tmp
) == AND
19051 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
19052 && INTVAL (XEXP (tmp
, 1)) == -16)
19053 tmp
= XEXP (tmp
, 0);
19054 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
19055 && GET_CODE (tmp
) == PRE_MODIFY
)
19056 tmp
= XEXP (tmp
, 1);
19058 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
19061 if (GET_CODE (tmp
) != PLUS
19062 || !REG_P (XEXP (tmp
, 0))
19063 || !REG_P (XEXP (tmp
, 1)))
19065 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
19069 if (REGNO (XEXP (tmp
, 0)) == 0)
19070 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
19071 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
19073 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
19074 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
19081 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
19082 else if (MEM_P (x
))
19084 /* We need to handle PRE_INC and PRE_DEC here, since we need to
19085 know the width from the mode. */
19086 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
19087 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
19088 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
19089 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
19090 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
19091 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
19092 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
19093 output_address (XEXP (XEXP (x
, 0), 1));
19095 output_address (XEXP (x
, 0));
19099 if (toc_relative_expr_p (x
, false))
19100 /* This hack along with a corresponding hack in
19101 rs6000_output_addr_const_extra arranges to output addends
19102 where the assembler expects to find them. eg.
19103 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
19104 without this hack would be output as "x@toc+4". We
19106 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
19108 output_addr_const (file
, x
);
19113 if (const char *name
= get_some_local_dynamic_name ())
19114 assemble_name (file
, name
);
19116 output_operand_lossage ("'%%&' used without any "
19117 "local dynamic TLS references");
19121 output_operand_lossage ("invalid %%xn code");
19125 /* Print the address of an operand. */
19128 print_operand_address (FILE *file
, rtx x
)
19131 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
19132 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
19133 || GET_CODE (x
) == LABEL_REF
)
19135 output_addr_const (file
, x
);
19136 if (small_data_operand (x
, GET_MODE (x
)))
19137 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
19138 reg_names
[SMALL_DATA_REG
]);
19140 gcc_assert (!TARGET_TOC
);
19142 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
19143 && REG_P (XEXP (x
, 1)))
19145 if (REGNO (XEXP (x
, 0)) == 0)
19146 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
19147 reg_names
[ REGNO (XEXP (x
, 0)) ]);
19149 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
19150 reg_names
[ REGNO (XEXP (x
, 1)) ]);
19152 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
19153 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
19154 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
19155 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
19157 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
19158 && CONSTANT_P (XEXP (x
, 1)))
19160 fprintf (file
, "lo16(");
19161 output_addr_const (file
, XEXP (x
, 1));
19162 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
19166 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
19167 && CONSTANT_P (XEXP (x
, 1)))
19169 output_addr_const (file
, XEXP (x
, 1));
19170 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
19173 else if (toc_relative_expr_p (x
, false))
19175 /* This hack along with a corresponding hack in
19176 rs6000_output_addr_const_extra arranges to output addends
19177 where the assembler expects to find them. eg.
19179 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
19180 without this hack would be output as "x@toc+8@l(9)". We
19181 want "x+8@toc@l(9)". */
19182 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
19183 if (GET_CODE (x
) == LO_SUM
)
19184 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
19186 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
19189 gcc_unreachable ();
19192 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
19195 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
19197 if (GET_CODE (x
) == UNSPEC
)
19198 switch (XINT (x
, 1))
19200 case UNSPEC_TOCREL
:
19201 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
19202 && REG_P (XVECEXP (x
, 0, 1))
19203 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
19204 output_addr_const (file
, XVECEXP (x
, 0, 0));
19205 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
19207 if (INTVAL (tocrel_offset
) >= 0)
19208 fprintf (file
, "+");
19209 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
19211 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
19214 assemble_name (file
, toc_label_name
);
19216 else if (TARGET_ELF
)
19217 fputs ("@toc", file
);
19221 case UNSPEC_MACHOPIC_OFFSET
:
19222 output_addr_const (file
, XVECEXP (x
, 0, 0));
19224 machopic_output_function_base_name (file
);
19231 /* Target hook for assembling integer objects. The PowerPC version has
19232 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
19233 is defined. It also needs to handle DI-mode objects on 64-bit
19237 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
19239 #ifdef RELOCATABLE_NEEDS_FIXUP
19240 /* Special handling for SI values. */
19241 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
19243 static int recurse
= 0;
19245 /* For -mrelocatable, we mark all addresses that need to be fixed up in
19246 the .fixup section. Since the TOC section is already relocated, we
19247 don't need to mark it here. We used to skip the text section, but it
19248 should never be valid for relocated addresses to be placed in the text
19250 if (TARGET_RELOCATABLE
19251 && in_section
!= toc_section
19253 && !CONST_SCALAR_INT_P (x
)
19259 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
19261 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
19262 fprintf (asm_out_file
, "\t.long\t(");
19263 output_addr_const (asm_out_file
, x
);
19264 fprintf (asm_out_file
, ")@fixup\n");
19265 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
19266 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
19267 fprintf (asm_out_file
, "\t.long\t");
19268 assemble_name (asm_out_file
, buf
);
19269 fprintf (asm_out_file
, "\n\t.previous\n");
19273 /* Remove initial .'s to turn a -mcall-aixdesc function
19274 address into the address of the descriptor, not the function
19276 else if (GET_CODE (x
) == SYMBOL_REF
19277 && XSTR (x
, 0)[0] == '.'
19278 && DEFAULT_ABI
== ABI_AIX
)
19280 const char *name
= XSTR (x
, 0);
19281 while (*name
== '.')
19284 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
19288 #endif /* RELOCATABLE_NEEDS_FIXUP */
19289 return default_assemble_integer (x
, size
, aligned_p
);
19292 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
19293 /* Emit an assembler directive to set symbol visibility for DECL to
19294 VISIBILITY_TYPE. */
19297 rs6000_assemble_visibility (tree decl
, int vis
)
19302 /* Functions need to have their entry point symbol visibility set as
19303 well as their descriptor symbol visibility. */
19304 if (DEFAULT_ABI
== ABI_AIX
19306 && TREE_CODE (decl
) == FUNCTION_DECL
)
19308 static const char * const visibility_types
[] = {
19309 NULL
, "internal", "hidden", "protected"
19312 const char *name
, *type
;
19314 name
= ((* targetm
.strip_name_encoding
)
19315 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
19316 type
= visibility_types
[vis
];
19318 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
19319 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
19322 default_assemble_visibility (decl
, vis
);
19327 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
19329 /* Reversal of FP compares takes care -- an ordered compare
19330 becomes an unordered compare and vice versa. */
19331 if (mode
== CCFPmode
19332 && (!flag_finite_math_only
19333 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
19334 || code
== UNEQ
|| code
== LTGT
))
19335 return reverse_condition_maybe_unordered (code
);
19337 return reverse_condition (code
);
19340 /* Generate a compare for CODE. Return a brand-new rtx that
19341 represents the result of the compare. */
19344 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
19346 machine_mode comp_mode
;
19347 rtx compare_result
;
19348 enum rtx_code code
= GET_CODE (cmp
);
19349 rtx op0
= XEXP (cmp
, 0);
19350 rtx op1
= XEXP (cmp
, 1);
19352 if (FLOAT_MODE_P (mode
))
19353 comp_mode
= CCFPmode
;
19354 else if (code
== GTU
|| code
== LTU
19355 || code
== GEU
|| code
== LEU
)
19356 comp_mode
= CCUNSmode
;
19357 else if ((code
== EQ
|| code
== NE
)
19358 && unsigned_reg_p (op0
)
19359 && (unsigned_reg_p (op1
)
19360 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
19361 /* These are unsigned values, perhaps there will be a later
19362 ordering compare that can be shared with this one. */
19363 comp_mode
= CCUNSmode
;
19365 comp_mode
= CCmode
;
19367 /* If we have an unsigned compare, make sure we don't have a signed value as
19369 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
19370 && INTVAL (op1
) < 0)
19372 op0
= copy_rtx_if_shared (op0
);
19373 op1
= force_reg (GET_MODE (op0
), op1
);
19374 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
19377 /* First, the compare. */
19378 compare_result
= gen_reg_rtx (comp_mode
);
19380 /* E500 FP compare instructions on the GPRs. Yuck! */
19381 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
19382 && FLOAT_MODE_P (mode
))
19384 rtx cmp
, or_result
, compare_result2
;
19385 machine_mode op_mode
= GET_MODE (op0
);
19388 if (op_mode
== VOIDmode
)
19389 op_mode
= GET_MODE (op1
);
19391 /* First reverse the condition codes that aren't directly supported. */
19399 code
= reverse_condition_maybe_unordered (code
);
19412 gcc_unreachable ();
19415 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
19416 This explains the following mess. */
19424 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19425 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
19426 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
19430 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19431 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
19432 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
19436 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19437 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
19438 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
19442 gcc_unreachable ();
19451 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19452 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
19453 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
19457 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19458 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
19459 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
19463 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19464 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
19465 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
19469 gcc_unreachable ();
19478 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19479 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
19480 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
19484 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19485 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
19486 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
19490 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19491 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
19492 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
19496 gcc_unreachable ();
19501 gcc_unreachable ();
19504 /* Synthesize LE and GE from LT/GT || EQ. */
19505 if (code
== LE
|| code
== GE
)
19509 compare_result2
= gen_reg_rtx (CCFPmode
);
19515 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19516 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
19517 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
19521 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19522 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
19523 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
19527 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
19528 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
19529 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
19533 gcc_unreachable ();
19538 /* OR them together. */
19539 or_result
= gen_reg_rtx (CCFPmode
);
19540 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
19542 compare_result
= or_result
;
19545 code
= reverse_p
? NE
: EQ
;
19551 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
19552 CLOBBERs to match cmptf_internal2 pattern. */
19553 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
19554 && GET_MODE (op0
) == TFmode
19555 && !TARGET_IEEEQUAD
19556 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
19557 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
19559 gen_rtx_SET (compare_result
,
19560 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
19561 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19562 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19563 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19564 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19565 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19566 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19567 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19568 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
19569 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
19570 else if (GET_CODE (op1
) == UNSPEC
19571 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
19573 rtx op1b
= XVECEXP (op1
, 0, 0);
19574 comp_mode
= CCEQmode
;
19575 compare_result
= gen_reg_rtx (CCEQmode
);
19577 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
19579 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
19582 emit_insn (gen_rtx_SET (compare_result
,
19583 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
19586 /* Some kinds of FP comparisons need an OR operation;
19587 under flag_finite_math_only we don't bother. */
19588 if (FLOAT_MODE_P (mode
)
19589 && !flag_finite_math_only
19590 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
19591 && (code
== LE
|| code
== GE
19592 || code
== UNEQ
|| code
== LTGT
19593 || code
== UNGT
|| code
== UNLT
))
19595 enum rtx_code or1
, or2
;
19596 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
19597 rtx or_result
= gen_reg_rtx (CCEQmode
);
19601 case LE
: or1
= LT
; or2
= EQ
; break;
19602 case GE
: or1
= GT
; or2
= EQ
; break;
19603 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
19604 case LTGT
: or1
= LT
; or2
= GT
; break;
19605 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
19606 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
19607 default: gcc_unreachable ();
19609 validate_condition_mode (or1
, comp_mode
);
19610 validate_condition_mode (or2
, comp_mode
);
19611 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
19612 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
19613 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
19614 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
19616 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
19618 compare_result
= or_result
;
19622 validate_condition_mode (code
, GET_MODE (compare_result
));
19624 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
19628 /* Emit the RTL for an sISEL pattern. */
19631 rs6000_emit_sISEL (machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
19633 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
19636 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
19637 can be used as that dest register. Return the dest register. */
19640 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
19642 if (op2
== const0_rtx
)
19645 if (GET_CODE (scratch
) == SCRATCH
)
19646 scratch
= gen_reg_rtx (mode
);
19648 if (logical_operand (op2
, mode
))
19649 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
19651 emit_insn (gen_rtx_SET (scratch
,
19652 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
19658 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
19661 machine_mode op_mode
;
19662 enum rtx_code cond_code
;
19663 rtx result
= operands
[0];
19665 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
19666 cond_code
= GET_CODE (condition_rtx
);
19668 if (FLOAT_MODE_P (mode
)
19669 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
19673 PUT_MODE (condition_rtx
, SImode
);
19674 t
= XEXP (condition_rtx
, 0);
19676 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
19678 if (cond_code
== NE
)
19679 emit_insn (gen_e500_flip_gt_bit (t
, t
));
19681 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
19685 if (cond_code
== NE
19686 || cond_code
== GE
|| cond_code
== LE
19687 || cond_code
== GEU
|| cond_code
== LEU
19688 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
19690 rtx not_result
= gen_reg_rtx (CCEQmode
);
19691 rtx not_op
, rev_cond_rtx
;
19692 machine_mode cc_mode
;
19694 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
19696 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
19697 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
19698 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
19699 emit_insn (gen_rtx_SET (not_result
, not_op
));
19700 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
19703 op_mode
= GET_MODE (XEXP (operands
[1], 0));
19704 if (op_mode
== VOIDmode
)
19705 op_mode
= GET_MODE (XEXP (operands
[1], 1));
19707 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
19709 PUT_MODE (condition_rtx
, DImode
);
19710 convert_move (result
, condition_rtx
, 0);
19714 PUT_MODE (condition_rtx
, SImode
);
19715 emit_insn (gen_rtx_SET (result
, condition_rtx
));
19719 /* Emit a branch of kind CODE to location LOC. */
19722 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
19724 rtx condition_rtx
, loc_ref
;
19726 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
19727 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
19728 emit_jump_insn (gen_rtx_SET (pc_rtx
,
19729 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
19730 loc_ref
, pc_rtx
)));
19733 /* Return the string to output a conditional branch to LABEL, which is
19734 the operand template of the label, or NULL if the branch is really a
19735 conditional return.
19737 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
19738 condition code register and its mode specifies what kind of
19739 comparison we made.
19741 REVERSED is nonzero if we should reverse the sense of the comparison.
19743 INSN is the insn. */
19746 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
19748 static char string
[64];
19749 enum rtx_code code
= GET_CODE (op
);
19750 rtx cc_reg
= XEXP (op
, 0);
19751 machine_mode mode
= GET_MODE (cc_reg
);
19752 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
19753 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
19754 int really_reversed
= reversed
^ need_longbranch
;
19760 validate_condition_mode (code
, mode
);
19762 /* Work out which way this really branches. We could use
19763 reverse_condition_maybe_unordered here always but this
19764 makes the resulting assembler clearer. */
19765 if (really_reversed
)
19767 /* Reversal of FP compares takes care -- an ordered compare
19768 becomes an unordered compare and vice versa. */
19769 if (mode
== CCFPmode
)
19770 code
= reverse_condition_maybe_unordered (code
);
19772 code
= reverse_condition (code
);
19775 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
19777 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
19782 /* Opposite of GT. */
19791 gcc_unreachable ();
19797 /* Not all of these are actually distinct opcodes, but
19798 we distinguish them for clarity of the resulting assembler. */
19799 case NE
: case LTGT
:
19800 ccode
= "ne"; break;
19801 case EQ
: case UNEQ
:
19802 ccode
= "eq"; break;
19804 ccode
= "ge"; break;
19805 case GT
: case GTU
: case UNGT
:
19806 ccode
= "gt"; break;
19808 ccode
= "le"; break;
19809 case LT
: case LTU
: case UNLT
:
19810 ccode
= "lt"; break;
19811 case UNORDERED
: ccode
= "un"; break;
19812 case ORDERED
: ccode
= "nu"; break;
19813 case UNGE
: ccode
= "nl"; break;
19814 case UNLE
: ccode
= "ng"; break;
19816 gcc_unreachable ();
19819 /* Maybe we have a guess as to how likely the branch is. */
19821 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
19822 if (note
!= NULL_RTX
)
19824 /* PROB is the difference from 50%. */
19825 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
19827 /* Only hint for highly probable/improbable branches on newer
19828 cpus as static prediction overrides processor dynamic
19829 prediction. For older cpus we may as well always hint, but
19830 assume not taken for branches that are very close to 50% as a
19831 mispredicted taken branch is more expensive than a
19832 mispredicted not-taken branch. */
19833 if (rs6000_always_hint
19834 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
19835 && br_prob_note_reliable_p (note
)))
19837 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
19838 && ((prob
> 0) ^ need_longbranch
))
19846 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
19848 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
19850 /* We need to escape any '%' characters in the reg_names string.
19851 Assume they'd only be the first character.... */
19852 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
19854 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
19858 /* If the branch distance was too far, we may have to use an
19859 unconditional branch to go the distance. */
19860 if (need_longbranch
)
19861 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
19863 s
+= sprintf (s
, ",%s", label
);
19869 /* Return the string to flip the GT bit on a CR. */
19871 output_e500_flip_gt_bit (rtx dst
, rtx src
)
19873 static char string
[64];
19876 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
19877 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
19880 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
19881 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
19883 sprintf (string
, "crnot %d,%d", a
, b
);
19887 /* Return insn for VSX or Altivec comparisons. */
19890 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
19893 machine_mode mode
= GET_MODE (op0
);
19901 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
19911 mask
= gen_reg_rtx (mode
);
19912 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19919 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
19920 DMODE is expected destination mode. This is a recursive function. */
19923 rs6000_emit_vector_compare (enum rtx_code rcode
,
19925 machine_mode dmode
)
19928 bool swap_operands
= false;
19929 bool try_again
= false;
19931 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
19932 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
19934 /* See if the comparison works as is. */
19935 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
19943 swap_operands
= true;
19948 swap_operands
= true;
19956 /* Invert condition and try again.
19957 e.g., A != B becomes ~(A==B). */
19959 enum rtx_code rev_code
;
19960 enum insn_code nor_code
;
19963 rev_code
= reverse_condition_maybe_unordered (rcode
);
19964 if (rev_code
== UNKNOWN
)
19967 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
19968 if (nor_code
== CODE_FOR_nothing
)
19971 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
19975 mask
= gen_reg_rtx (dmode
);
19976 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
19984 /* Try GT/GTU/LT/LTU OR EQ */
19987 enum insn_code ior_code
;
19988 enum rtx_code new_code
;
20009 gcc_unreachable ();
20012 ior_code
= optab_handler (ior_optab
, dmode
);
20013 if (ior_code
== CODE_FOR_nothing
)
20016 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
20020 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
20024 mask
= gen_reg_rtx (dmode
);
20025 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
20036 std::swap (op0
, op1
);
20038 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
20043 /* You only get two chances. */
20047 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
20048 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
20049 operands for the relation operation COND. */
20052 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
20053 rtx cond
, rtx cc_op0
, rtx cc_op1
)
20055 machine_mode dest_mode
= GET_MODE (dest
);
20056 machine_mode mask_mode
= GET_MODE (cc_op0
);
20057 enum rtx_code rcode
= GET_CODE (cond
);
20058 machine_mode cc_mode
= CCmode
;
20062 bool invert_move
= false;
20064 if (VECTOR_UNIT_NONE_P (dest_mode
))
20067 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
20068 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
20072 /* Swap operands if we can, and fall back to doing the operation as
20073 specified, and doing a NOR to invert the test. */
20079 /* Invert condition and try again.
20080 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
20081 invert_move
= true;
20082 rcode
= reverse_condition_maybe_unordered (rcode
);
20083 if (rcode
== UNKNOWN
)
20087 /* Mark unsigned tests with CCUNSmode. */
20092 cc_mode
= CCUNSmode
;
20099 /* Get the vector mask for the given relational operations. */
20100 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
20108 op_true
= op_false
;
20112 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
20113 CONST0_RTX (dest_mode
));
20114 emit_insn (gen_rtx_SET (dest
,
20115 gen_rtx_IF_THEN_ELSE (dest_mode
,
20122 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
20123 operands of the last comparison is nonzero/true, FALSE_COND if it
20124 is zero/false. Return 0 if the hardware has no such operation. */
20127 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
20129 enum rtx_code code
= GET_CODE (op
);
20130 rtx op0
= XEXP (op
, 0);
20131 rtx op1
= XEXP (op
, 1);
20132 REAL_VALUE_TYPE c1
;
20133 machine_mode compare_mode
= GET_MODE (op0
);
20134 machine_mode result_mode
= GET_MODE (dest
);
20136 bool is_against_zero
;
20138 /* These modes should always match. */
20139 if (GET_MODE (op1
) != compare_mode
20140 /* In the isel case however, we can use a compare immediate, so
20141 op1 may be a small constant. */
20142 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
20144 if (GET_MODE (true_cond
) != result_mode
)
20146 if (GET_MODE (false_cond
) != result_mode
)
20149 /* Don't allow using floating point comparisons for integer results for
20151 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
20154 /* First, work out if the hardware can do this at all, or
20155 if it's too slow.... */
20156 if (!FLOAT_MODE_P (compare_mode
))
20159 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
20162 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
20163 && SCALAR_FLOAT_MODE_P (compare_mode
))
20166 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
20168 /* A floating-point subtract might overflow, underflow, or produce
20169 an inexact result, thus changing the floating-point flags, so it
20170 can't be generated if we care about that. It's safe if one side
20171 of the construct is zero, since then no subtract will be
20173 if (SCALAR_FLOAT_MODE_P (compare_mode
)
20174 && flag_trapping_math
&& ! is_against_zero
)
20177 /* Eliminate half of the comparisons by switching operands, this
20178 makes the remaining code simpler. */
20179 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
20180 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
20182 code
= reverse_condition_maybe_unordered (code
);
20184 true_cond
= false_cond
;
20188 /* UNEQ and LTGT take four instructions for a comparison with zero,
20189 it'll probably be faster to use a branch here too. */
20190 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
20193 if (GET_CODE (op1
) == CONST_DOUBLE
)
20194 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
20196 /* We're going to try to implement comparisons by performing
20197 a subtract, then comparing against zero. Unfortunately,
20198 Inf - Inf is NaN which is not zero, and so if we don't
20199 know that the operand is finite and the comparison
20200 would treat EQ different to UNORDERED, we can't do it. */
20201 if (HONOR_INFINITIES (compare_mode
)
20202 && code
!= GT
&& code
!= UNGE
20203 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
20204 /* Constructs of the form (a OP b ? a : b) are safe. */
20205 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
20206 || (! rtx_equal_p (op0
, true_cond
)
20207 && ! rtx_equal_p (op1
, true_cond
))))
20210 /* At this point we know we can use fsel. */
20212 /* Reduce the comparison to a comparison against zero. */
20213 if (! is_against_zero
)
20215 temp
= gen_reg_rtx (compare_mode
);
20216 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
20218 op1
= CONST0_RTX (compare_mode
);
20221 /* If we don't care about NaNs we can reduce some of the comparisons
20222 down to faster ones. */
20223 if (! HONOR_NANS (compare_mode
))
20229 true_cond
= false_cond
;
20242 /* Now, reduce everything down to a GE. */
20249 temp
= gen_reg_rtx (compare_mode
);
20250 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
20255 temp
= gen_reg_rtx (compare_mode
);
20256 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
20261 temp
= gen_reg_rtx (compare_mode
);
20262 emit_insn (gen_rtx_SET (temp
,
20263 gen_rtx_NEG (compare_mode
,
20264 gen_rtx_ABS (compare_mode
, op0
))));
20269 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
20270 temp
= gen_reg_rtx (result_mode
);
20271 emit_insn (gen_rtx_SET (temp
,
20272 gen_rtx_IF_THEN_ELSE (result_mode
,
20273 gen_rtx_GE (VOIDmode
,
20275 true_cond
, false_cond
)));
20276 false_cond
= true_cond
;
20279 temp
= gen_reg_rtx (compare_mode
);
20280 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
20285 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
20286 temp
= gen_reg_rtx (result_mode
);
20287 emit_insn (gen_rtx_SET (temp
,
20288 gen_rtx_IF_THEN_ELSE (result_mode
,
20289 gen_rtx_GE (VOIDmode
,
20291 true_cond
, false_cond
)));
20292 true_cond
= false_cond
;
20295 temp
= gen_reg_rtx (compare_mode
);
20296 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
20301 gcc_unreachable ();
20304 emit_insn (gen_rtx_SET (dest
,
20305 gen_rtx_IF_THEN_ELSE (result_mode
,
20306 gen_rtx_GE (VOIDmode
,
20308 true_cond
, false_cond
)));
20312 /* Same as above, but for ints (isel). */
20315 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
20317 rtx condition_rtx
, cr
;
20318 machine_mode mode
= GET_MODE (dest
);
20319 enum rtx_code cond_code
;
20320 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
20323 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
20326 /* We still have to do the compare, because isel doesn't do a
20327 compare, it just looks at the CRx bits set by a previous compare
20329 condition_rtx
= rs6000_generate_compare (op
, mode
);
20330 cond_code
= GET_CODE (condition_rtx
);
20331 cr
= XEXP (condition_rtx
, 0);
20332 signedp
= GET_MODE (cr
) == CCmode
;
20334 isel_func
= (mode
== SImode
20335 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
20336 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
20340 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
20341 /* isel handles these directly. */
20345 /* We need to swap the sense of the comparison. */
20347 std::swap (false_cond
, true_cond
);
20348 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
20353 false_cond
= force_reg (mode
, false_cond
);
20354 if (true_cond
!= const0_rtx
)
20355 true_cond
= force_reg (mode
, true_cond
);
20357 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
20363 output_isel (rtx
*operands
)
20365 enum rtx_code code
;
20367 code
= GET_CODE (operands
[1]);
20369 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
20371 gcc_assert (GET_CODE (operands
[2]) == REG
20372 && GET_CODE (operands
[3]) == REG
);
20373 PUT_CODE (operands
[1], reverse_condition (code
));
20374 return "isel %0,%3,%2,%j1";
20377 return "isel %0,%2,%3,%j1";
20381 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
20383 machine_mode mode
= GET_MODE (op0
);
20387 /* VSX/altivec have direct min/max insns. */
20388 if ((code
== SMAX
|| code
== SMIN
)
20389 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
20390 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
20392 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
20396 if (code
== SMAX
|| code
== SMIN
)
20401 if (code
== SMAX
|| code
== UMAX
)
20402 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
20403 op0
, op1
, mode
, 0);
20405 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
20406 op1
, op0
, mode
, 0);
20407 gcc_assert (target
);
20408 if (target
!= dest
)
20409 emit_move_insn (dest
, target
);
20412 /* A subroutine of the atomic operation splitters. Jump to LABEL if
20413 COND is true. Mark the jump as unlikely to be taken. */
20416 emit_unlikely_jump (rtx cond
, rtx label
)
20418 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
20421 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
20422 x
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
20423 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
20426 /* A subroutine of the atomic operation splitters. Emit a load-locked
20427 instruction in MODE. For QI/HImode, possibly use a pattern than includes
20428 the zero_extend operation. */
20431 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
20433 rtx (*fn
) (rtx
, rtx
) = NULL
;
20438 fn
= gen_load_lockedqi
;
20441 fn
= gen_load_lockedhi
;
20444 if (GET_MODE (mem
) == QImode
)
20445 fn
= gen_load_lockedqi_si
;
20446 else if (GET_MODE (mem
) == HImode
)
20447 fn
= gen_load_lockedhi_si
;
20449 fn
= gen_load_lockedsi
;
20452 fn
= gen_load_lockeddi
;
20455 fn
= gen_load_lockedti
;
20458 gcc_unreachable ();
20460 emit_insn (fn (reg
, mem
));
20463 /* A subroutine of the atomic operation splitters. Emit a store-conditional
20464 instruction in MODE. */
20467 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
20469 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
20474 fn
= gen_store_conditionalqi
;
20477 fn
= gen_store_conditionalhi
;
20480 fn
= gen_store_conditionalsi
;
20483 fn
= gen_store_conditionaldi
;
20486 fn
= gen_store_conditionalti
;
20489 gcc_unreachable ();
20492 /* Emit sync before stwcx. to address PPC405 Erratum. */
20493 if (PPC405_ERRATUM77
)
20494 emit_insn (gen_hwsync ());
20496 emit_insn (fn (res
, mem
, val
));
20499 /* Expand barriers before and after a load_locked/store_cond sequence. */
20502 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
20504 rtx addr
= XEXP (mem
, 0);
20505 int strict_p
= (reload_in_progress
|| reload_completed
);
20507 if (!legitimate_indirect_address_p (addr
, strict_p
)
20508 && !legitimate_indexed_address_p (addr
, strict_p
))
20510 addr
= force_reg (Pmode
, addr
);
20511 mem
= replace_equiv_address_nv (mem
, addr
);
20516 case MEMMODEL_RELAXED
:
20517 case MEMMODEL_CONSUME
:
20518 case MEMMODEL_ACQUIRE
:
20519 case MEMMODEL_SYNC_ACQUIRE
:
20521 case MEMMODEL_RELEASE
:
20522 case MEMMODEL_SYNC_RELEASE
:
20523 case MEMMODEL_ACQ_REL
:
20524 emit_insn (gen_lwsync ());
20526 case MEMMODEL_SEQ_CST
:
20527 case MEMMODEL_SYNC_SEQ_CST
:
20528 emit_insn (gen_hwsync ());
20531 gcc_unreachable ();
20537 rs6000_post_atomic_barrier (enum memmodel model
)
20541 case MEMMODEL_RELAXED
:
20542 case MEMMODEL_CONSUME
:
20543 case MEMMODEL_RELEASE
:
20544 case MEMMODEL_SYNC_RELEASE
:
20546 case MEMMODEL_ACQUIRE
:
20547 case MEMMODEL_SYNC_ACQUIRE
:
20548 case MEMMODEL_ACQ_REL
:
20549 case MEMMODEL_SEQ_CST
:
20550 case MEMMODEL_SYNC_SEQ_CST
:
20551 emit_insn (gen_isync ());
20554 gcc_unreachable ();
20558 /* A subroutine of the various atomic expanders. For sub-word operations,
20559 we must adjust things to operate on SImode. Given the original MEM,
20560 return a new aligned memory. Also build and return the quantities by
20561 which to shift and mask. */
20564 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
20566 rtx addr
, align
, shift
, mask
, mem
;
20567 HOST_WIDE_INT shift_mask
;
20568 machine_mode mode
= GET_MODE (orig_mem
);
20570 /* For smaller modes, we have to implement this via SImode. */
20571 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
20573 addr
= XEXP (orig_mem
, 0);
20574 addr
= force_reg (GET_MODE (addr
), addr
);
20576 /* Aligned memory containing subword. Generate a new memory. We
20577 do not want any of the existing MEM_ATTR data, as we're now
20578 accessing memory outside the original object. */
20579 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
20580 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20581 mem
= gen_rtx_MEM (SImode
, align
);
20582 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
20583 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
20584 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
20586 /* Shift amount for subword relative to aligned word. */
20587 shift
= gen_reg_rtx (SImode
);
20588 addr
= gen_lowpart (SImode
, addr
);
20589 rtx tmp
= gen_reg_rtx (SImode
);
20590 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
20591 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
20592 if (BYTES_BIG_ENDIAN
)
20593 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
20594 shift
, 1, OPTAB_LIB_WIDEN
);
20597 /* Mask for insertion. */
20598 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
20599 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20605 /* A subroutine of the various atomic expanders. For sub-word operands,
20606 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
20609 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
20613 x
= gen_reg_rtx (SImode
);
20614 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
20615 gen_rtx_NOT (SImode
, mask
),
20618 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
20623 /* A subroutine of the various atomic expanders. For sub-word operands,
20624 extract WIDE to NARROW via SHIFT. */
20627 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
20629 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
20630 wide
, 1, OPTAB_LIB_WIDEN
);
20631 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
20634 /* Expand an atomic compare and swap operation. */
20637 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
20639 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
20640 rtx label1
, label2
, x
, mask
, shift
;
20641 machine_mode mode
, orig_mode
;
20642 enum memmodel mod_s
, mod_f
;
20645 boolval
= operands
[0];
20646 retval
= operands
[1];
20648 oldval
= operands
[3];
20649 newval
= operands
[4];
20650 is_weak
= (INTVAL (operands
[5]) != 0);
20651 mod_s
= memmodel_from_int (INTVAL (operands
[6]));
20652 mod_f
= memmodel_from_int (INTVAL (operands
[7]));
20653 orig_mode
= mode
= GET_MODE (mem
);
20655 mask
= shift
= NULL_RTX
;
20656 if (mode
== QImode
|| mode
== HImode
)
20658 /* Before power8, we didn't have access to lbarx/lharx, so generate a
20659 lwarx and shift/mask operations. With power8, we need to do the
20660 comparison in SImode, but the store is still done in QI/HImode. */
20661 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
20663 if (!TARGET_SYNC_HI_QI
)
20665 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20667 /* Shift and mask OLDVAL into position with the word. */
20668 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
20669 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20671 /* Shift and mask NEWVAL into position within the word. */
20672 newval
= convert_modes (SImode
, mode
, newval
, 1);
20673 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
20674 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20677 /* Prepare to adjust the return value. */
20678 retval
= gen_reg_rtx (SImode
);
20681 else if (reg_overlap_mentioned_p (retval
, oldval
))
20682 oldval
= copy_to_reg (oldval
);
20684 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
20689 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20690 emit_label (XEXP (label1
, 0));
20692 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20694 emit_load_locked (mode
, retval
, mem
);
20699 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
20700 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20703 cond
= gen_reg_rtx (CCmode
);
20704 /* If we have TImode, synthesize a comparison. */
20705 if (mode
!= TImode
)
20706 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
20709 rtx xor1_result
= gen_reg_rtx (DImode
);
20710 rtx xor2_result
= gen_reg_rtx (DImode
);
20711 rtx or_result
= gen_reg_rtx (DImode
);
20712 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
20713 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
20714 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
20715 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
20717 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
20718 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
20719 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
20720 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
20723 emit_insn (gen_rtx_SET (cond
, x
));
20725 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20726 emit_unlikely_jump (x
, label2
);
20730 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
20732 emit_store_conditional (orig_mode
, cond
, mem
, x
);
20736 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20737 emit_unlikely_jump (x
, label1
);
20740 if (!is_mm_relaxed (mod_f
))
20741 emit_label (XEXP (label2
, 0));
20743 rs6000_post_atomic_barrier (mod_s
);
20745 if (is_mm_relaxed (mod_f
))
20746 emit_label (XEXP (label2
, 0));
20749 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
20750 else if (mode
!= GET_MODE (operands
[1]))
20751 convert_move (operands
[1], retval
, 1);
20753 /* In all cases, CR0 contains EQ on success, and NE on failure. */
20754 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
20755 emit_insn (gen_rtx_SET (boolval
, x
));
20758 /* Expand an atomic exchange operation. */
20761 rs6000_expand_atomic_exchange (rtx operands
[])
20763 rtx retval
, mem
, val
, cond
;
20765 enum memmodel model
;
20766 rtx label
, x
, mask
, shift
;
20768 retval
= operands
[0];
20771 model
= (enum memmodel
) INTVAL (operands
[3]);
20772 mode
= GET_MODE (mem
);
20774 mask
= shift
= NULL_RTX
;
20775 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
20777 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20779 /* Shift and mask VAL into position with the word. */
20780 val
= convert_modes (SImode
, mode
, val
, 1);
20781 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20782 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20784 /* Prepare to adjust the return value. */
20785 retval
= gen_reg_rtx (SImode
);
20789 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20791 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
20792 emit_label (XEXP (label
, 0));
20794 emit_load_locked (mode
, retval
, mem
);
20798 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
20800 cond
= gen_reg_rtx (CCmode
);
20801 emit_store_conditional (mode
, cond
, mem
, x
);
20803 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20804 emit_unlikely_jump (x
, label
);
20806 rs6000_post_atomic_barrier (model
);
20809 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
20812 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
20813 to perform. MEM is the memory on which to operate. VAL is the second
20814 operand of the binary operator. BEFORE and AFTER are optional locations to
20815 return the value of MEM either before of after the operation. MODEL_RTX
20816 is a CONST_INT containing the memory model to use. */
20819 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
20820 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
20822 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
20823 machine_mode mode
= GET_MODE (mem
);
20824 machine_mode store_mode
= mode
;
20825 rtx label
, x
, cond
, mask
, shift
;
20826 rtx before
= orig_before
, after
= orig_after
;
20828 mask
= shift
= NULL_RTX
;
20829 /* On power8, we want to use SImode for the operation. On previous systems,
20830 use the operation in a subword and shift/mask to get the proper byte or
20832 if (mode
== QImode
|| mode
== HImode
)
20834 if (TARGET_SYNC_HI_QI
)
20836 val
= convert_modes (SImode
, mode
, val
, 1);
20838 /* Prepare to adjust the return value. */
20839 before
= gen_reg_rtx (SImode
);
20841 after
= gen_reg_rtx (SImode
);
20846 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
20848 /* Shift and mask VAL into position with the word. */
20849 val
= convert_modes (SImode
, mode
, val
, 1);
20850 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
20851 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20857 /* We've already zero-extended VAL. That is sufficient to
20858 make certain that it does not affect other bits. */
20863 /* If we make certain that all of the other bits in VAL are
20864 set, that will be sufficient to not affect other bits. */
20865 x
= gen_rtx_NOT (SImode
, mask
);
20866 x
= gen_rtx_IOR (SImode
, x
, val
);
20867 emit_insn (gen_rtx_SET (val
, x
));
20874 /* These will all affect bits outside the field and need
20875 adjustment via MASK within the loop. */
20879 gcc_unreachable ();
20882 /* Prepare to adjust the return value. */
20883 before
= gen_reg_rtx (SImode
);
20885 after
= gen_reg_rtx (SImode
);
20886 store_mode
= mode
= SImode
;
20890 mem
= rs6000_pre_atomic_barrier (mem
, model
);
20892 label
= gen_label_rtx ();
20893 emit_label (label
);
20894 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
20896 if (before
== NULL_RTX
)
20897 before
= gen_reg_rtx (mode
);
20899 emit_load_locked (mode
, before
, mem
);
20903 x
= expand_simple_binop (mode
, AND
, before
, val
,
20904 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20905 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
20909 after
= expand_simple_binop (mode
, code
, before
, val
,
20910 after
, 1, OPTAB_LIB_WIDEN
);
20916 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
20917 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
20918 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
20920 else if (store_mode
!= mode
)
20921 x
= convert_modes (store_mode
, mode
, x
, 1);
20923 cond
= gen_reg_rtx (CCmode
);
20924 emit_store_conditional (store_mode
, cond
, mem
, x
);
20926 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
20927 emit_unlikely_jump (x
, label
);
20929 rs6000_post_atomic_barrier (model
);
20933 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
20934 then do the calcuations in a SImode register. */
20936 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
20938 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
20940 else if (store_mode
!= mode
)
20942 /* QImode/HImode on machines with lbarx/lharx where we do the native
20943 operation and then do the calcuations in a SImode register. */
20945 convert_move (orig_before
, before
, 1);
20947 convert_move (orig_after
, after
, 1);
20949 else if (orig_after
&& after
!= orig_after
)
20950 emit_move_insn (orig_after
, after
);
20953 /* Emit instructions to move SRC to DST. Called by splitters for
20954 multi-register moves. It will emit at most one instruction for
20955 each register that is accessed; that is, it won't emit li/lis pairs
20956 (or equivalent for 64-bit code). One of SRC or DST must be a hard
20960 rs6000_split_multireg_move (rtx dst
, rtx src
)
20962 /* The register number of the first register being moved. */
20964 /* The mode that is to be moved. */
20966 /* The mode that the move is being done in, and its size. */
20967 machine_mode reg_mode
;
20969 /* The number of registers that will be moved. */
20972 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
20973 mode
= GET_MODE (dst
);
20974 nregs
= hard_regno_nregs
[reg
][mode
];
20975 if (FP_REGNO_P (reg
))
20976 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
20977 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
20978 else if (ALTIVEC_REGNO_P (reg
))
20979 reg_mode
= V16QImode
;
20980 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
20983 reg_mode
= word_mode
;
20984 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
20986 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
20988 /* TDmode residing in FP registers is special, since the ISA requires that
20989 the lower-numbered word of a register pair is always the most significant
20990 word, even in little-endian mode. This does not match the usual subreg
20991 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
20992 the appropriate constituent registers "by hand" in little-endian mode.
20994 Note we do not need to check for destructive overlap here since TDmode
20995 can only reside in even/odd register pairs. */
20996 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
21001 for (i
= 0; i
< nregs
; i
++)
21003 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
21004 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
21006 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
21007 i
* reg_mode_size
);
21009 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
21010 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
21012 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
21013 i
* reg_mode_size
);
21015 emit_insn (gen_rtx_SET (p_dst
, p_src
));
21021 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
21023 /* Move register range backwards, if we might have destructive
21026 for (i
= nregs
- 1; i
>= 0; i
--)
21027 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
21028 i
* reg_mode_size
),
21029 simplify_gen_subreg (reg_mode
, src
, mode
,
21030 i
* reg_mode_size
)));
21036 bool used_update
= false;
21037 rtx restore_basereg
= NULL_RTX
;
21039 if (MEM_P (src
) && INT_REGNO_P (reg
))
21043 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
21044 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
21047 breg
= XEXP (XEXP (src
, 0), 0);
21048 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
21049 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
21050 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
21051 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
21052 src
= replace_equiv_address (src
, breg
);
21054 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
21056 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
21058 rtx basereg
= XEXP (XEXP (src
, 0), 0);
21061 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
21062 emit_insn (gen_rtx_SET (ndst
,
21063 gen_rtx_MEM (reg_mode
,
21065 used_update
= true;
21068 emit_insn (gen_rtx_SET (basereg
,
21069 XEXP (XEXP (src
, 0), 1)));
21070 src
= replace_equiv_address (src
, basereg
);
21074 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
21075 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
21076 src
= replace_equiv_address (src
, basereg
);
21080 breg
= XEXP (src
, 0);
21081 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
21082 breg
= XEXP (breg
, 0);
21084 /* If the base register we are using to address memory is
21085 also a destination reg, then change that register last. */
21087 && REGNO (breg
) >= REGNO (dst
)
21088 && REGNO (breg
) < REGNO (dst
) + nregs
)
21089 j
= REGNO (breg
) - REGNO (dst
);
21091 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
21095 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
21096 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
21099 breg
= XEXP (XEXP (dst
, 0), 0);
21100 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
21101 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
21102 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
21104 /* We have to update the breg before doing the store.
21105 Use store with update, if available. */
21109 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
21110 emit_insn (TARGET_32BIT
21111 ? (TARGET_POWERPC64
21112 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
21113 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
21114 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
21115 used_update
= true;
21118 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
21119 dst
= replace_equiv_address (dst
, breg
);
21121 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
21122 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
21124 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
21126 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
21129 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
21130 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
21133 used_update
= true;
21136 emit_insn (gen_rtx_SET (basereg
,
21137 XEXP (XEXP (dst
, 0), 1)));
21138 dst
= replace_equiv_address (dst
, basereg
);
21142 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
21143 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
21144 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
21146 && REG_P (offsetreg
)
21147 && REGNO (basereg
) != REGNO (offsetreg
));
21148 if (REGNO (basereg
) == 0)
21150 rtx tmp
= offsetreg
;
21151 offsetreg
= basereg
;
21154 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
21155 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
21156 dst
= replace_equiv_address (dst
, basereg
);
21159 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
21160 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
21163 for (i
= 0; i
< nregs
; i
++)
21165 /* Calculate index to next subword. */
21170 /* If compiler already emitted move of first word by
21171 store with update, no need to do anything. */
21172 if (j
== 0 && used_update
)
21175 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
21176 j
* reg_mode_size
),
21177 simplify_gen_subreg (reg_mode
, src
, mode
,
21178 j
* reg_mode_size
)));
21180 if (restore_basereg
!= NULL_RTX
)
21181 emit_insn (restore_basereg
);
21186 /* This page contains routines that are used to determine what the
21187 function prologue and epilogue code will do and write them out. */
21192 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
21195 /* Return the first fixed-point register that is required to be
21196 saved. 32 if none. */
21199 first_reg_to_save (void)
21203 /* Find lowest numbered live register. */
21204 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
21205 if (save_reg_p (first_reg
))
21208 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
21209 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
21210 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
21211 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
21212 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
21213 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
21217 && crtl
->uses_pic_offset_table
21218 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
21219 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
21225 /* Similar, for FP regs. */
21228 first_fp_reg_to_save (void)
21232 /* Find lowest numbered live register. */
21233 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
21234 if (save_reg_p (first_reg
))
21240 /* Similar, for AltiVec regs. */
21243 first_altivec_reg_to_save (void)
21247 /* Stack frame remains as is unless we are in AltiVec ABI. */
21248 if (! TARGET_ALTIVEC_ABI
)
21249 return LAST_ALTIVEC_REGNO
+ 1;
21251 /* On Darwin, the unwind routines are compiled without
21252 TARGET_ALTIVEC, and use save_world to save/restore the
21253 altivec registers when necessary. */
21254 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
21255 && ! TARGET_ALTIVEC
)
21256 return FIRST_ALTIVEC_REGNO
+ 20;
21258 /* Find lowest numbered live register. */
21259 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21260 if (save_reg_p (i
))
21266 /* Return a 32-bit mask of the AltiVec registers we need to set in
21267 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
21268 the 32-bit word is 0. */
21270 static unsigned int
21271 compute_vrsave_mask (void)
21273 unsigned int i
, mask
= 0;
21275 /* On Darwin, the unwind routines are compiled without
21276 TARGET_ALTIVEC, and use save_world to save/restore the
21277 call-saved altivec registers when necessary. */
21278 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
21279 && ! TARGET_ALTIVEC
)
21282 /* First, find out if we use _any_ altivec registers. */
21283 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21284 if (df_regs_ever_live_p (i
))
21285 mask
|= ALTIVEC_REG_BIT (i
);
21290 /* Next, remove the argument registers from the set. These must
21291 be in the VRSAVE mask set by the caller, so we don't need to add
21292 them in again. More importantly, the mask we compute here is
21293 used to generate CLOBBERs in the set_vrsave insn, and we do not
21294 wish the argument registers to die. */
21295 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
21296 mask
&= ~ALTIVEC_REG_BIT (i
);
21298 /* Similarly, remove the return value from the set. */
21301 diddle_return_value (is_altivec_return_reg
, &yes
);
21303 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
21309 /* For a very restricted set of circumstances, we can cut down the
21310 size of prologues/epilogues by calling our own save/restore-the-world
21314 compute_save_world_info (rs6000_stack_t
*info_ptr
)
21316 info_ptr
->world_save_p
= 1;
21317 info_ptr
->world_save_p
21318 = (WORLD_SAVE_P (info_ptr
)
21319 && DEFAULT_ABI
== ABI_DARWIN
21320 && !cfun
->has_nonlocal_label
21321 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
21322 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
21323 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
21324 && info_ptr
->cr_save_p
);
21326 /* This will not work in conjunction with sibcalls. Make sure there
21327 are none. (This check is expensive, but seldom executed.) */
21328 if (WORLD_SAVE_P (info_ptr
))
21331 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
21332 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
21334 info_ptr
->world_save_p
= 0;
21339 if (WORLD_SAVE_P (info_ptr
))
21341 /* Even if we're not touching VRsave, make sure there's room on the
21342 stack for it, if it looks like we're calling SAVE_WORLD, which
21343 will attempt to save it. */
21344 info_ptr
->vrsave_size
= 4;
21346 /* If we are going to save the world, we need to save the link register too. */
21347 info_ptr
->lr_save_p
= 1;
21349 /* "Save" the VRsave register too if we're saving the world. */
21350 if (info_ptr
->vrsave_mask
== 0)
21351 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
21353 /* Because the Darwin register save/restore routines only handle
21354 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
21356 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
21357 && (info_ptr
->first_altivec_reg_save
21358 >= FIRST_SAVED_ALTIVEC_REGNO
));
21365 is_altivec_return_reg (rtx reg
, void *xyes
)
21367 bool *yes
= (bool *) xyes
;
21368 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
21373 /* Look for user-defined global regs in the range FIRST to LAST-1.
21374 We should not restore these, and so cannot use lmw or out-of-line
21375 restore functions if there are any. We also can't save them
21376 (well, emit frame notes for them), because frame unwinding during
21377 exception handling will restore saved registers. */
21380 global_regs_p (unsigned first
, unsigned last
)
21382 while (first
< last
)
21383 if (global_regs
[first
++])
21388 /* Determine the strategy for savings/restoring registers. */
21391 SAVRES_MULTIPLE
= 0x1,
21392 SAVE_INLINE_FPRS
= 0x2,
21393 SAVE_INLINE_GPRS
= 0x4,
21394 REST_INLINE_FPRS
= 0x8,
21395 REST_INLINE_GPRS
= 0x10,
21396 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
21397 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
21398 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
21399 SAVE_INLINE_VRS
= 0x100,
21400 REST_INLINE_VRS
= 0x200
21404 rs6000_savres_strategy (rs6000_stack_t
*info
,
21405 bool using_static_chain_p
)
21410 if (TARGET_MULTIPLE
21411 && !TARGET_POWERPC64
21412 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
21413 && info
->first_gp_reg_save
< 31
21414 && !global_regs_p (info
->first_gp_reg_save
, 32))
21415 strategy
|= SAVRES_MULTIPLE
;
21417 if (crtl
->calls_eh_return
21418 || cfun
->machine
->ra_need_lr
)
21419 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
21420 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
21421 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
21423 if (info
->first_fp_reg_save
== 64
21424 /* The out-of-line FP routines use double-precision stores;
21425 we can't use those routines if we don't have such stores. */
21426 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
21427 || global_regs_p (info
->first_fp_reg_save
, 64))
21428 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
21430 if (info
->first_gp_reg_save
== 32
21431 || (!(strategy
& SAVRES_MULTIPLE
)
21432 && global_regs_p (info
->first_gp_reg_save
, 32)))
21433 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
21435 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
21436 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
21437 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
21439 /* Define cutoff for using out-of-line functions to save registers. */
21440 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
21442 if (!optimize_size
)
21444 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
21445 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
21446 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
21450 /* Prefer out-of-line restore if it will exit. */
21451 if (info
->first_fp_reg_save
> 61)
21452 strategy
|= SAVE_INLINE_FPRS
;
21453 if (info
->first_gp_reg_save
> 29)
21455 if (info
->first_fp_reg_save
== 64)
21456 strategy
|= SAVE_INLINE_GPRS
;
21458 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
21460 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
21461 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
21464 else if (DEFAULT_ABI
== ABI_DARWIN
)
21466 if (info
->first_fp_reg_save
> 60)
21467 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
21468 if (info
->first_gp_reg_save
> 29)
21469 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
21470 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
21474 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21475 if (info
->first_fp_reg_save
> 61)
21476 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
21477 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
21478 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
21481 /* Don't bother to try to save things out-of-line if r11 is occupied
21482 by the static chain. It would require too much fiddling and the
21483 static chain is rarely used anyway. FPRs are saved w.r.t the stack
21484 pointer on Darwin, and AIX uses r1 or r12. */
21485 if (using_static_chain_p
21486 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
21487 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
21489 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
21491 /* We can only use the out-of-line routines to restore if we've
21492 saved all the registers from first_fp_reg_save in the prologue.
21493 Otherwise, we risk loading garbage. */
21494 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
21498 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
21499 if (!save_reg_p (i
))
21501 strategy
|= REST_INLINE_FPRS
;
21506 /* If we are going to use store multiple, then don't even bother
21507 with the out-of-line routines, since the store-multiple
21508 instruction will always be smaller. */
21509 if ((strategy
& SAVRES_MULTIPLE
))
21510 strategy
|= SAVE_INLINE_GPRS
;
21512 /* info->lr_save_p isn't yet set if the only reason lr needs to be
21513 saved is an out-of-line save or restore. Set up the value for
21514 the next test (excluding out-of-line gpr restore). */
21515 lr_save_p
= (info
->lr_save_p
21516 || !(strategy
& SAVE_INLINE_GPRS
)
21517 || !(strategy
& SAVE_INLINE_FPRS
)
21518 || !(strategy
& SAVE_INLINE_VRS
)
21519 || !(strategy
& REST_INLINE_FPRS
)
21520 || !(strategy
& REST_INLINE_VRS
));
21522 /* The situation is more complicated with load multiple. We'd
21523 prefer to use the out-of-line routines for restores, since the
21524 "exit" out-of-line routines can handle the restore of LR and the
21525 frame teardown. However if doesn't make sense to use the
21526 out-of-line routine if that is the only reason we'd need to save
21527 LR, and we can't use the "exit" out-of-line gpr restore if we
21528 have saved some fprs; In those cases it is advantageous to use
21529 load multiple when available. */
21530 if ((strategy
& SAVRES_MULTIPLE
)
21532 || info
->first_fp_reg_save
!= 64))
21533 strategy
|= REST_INLINE_GPRS
;
21535 /* Saving CR interferes with the exit routines used on the SPE, so
21538 && info
->spe_64bit_regs_used
21539 && info
->cr_save_p
)
21540 strategy
|= REST_INLINE_GPRS
;
21542 /* We can only use load multiple or the out-of-line routines to
21543 restore if we've used store multiple or out-of-line routines
21544 in the prologue, i.e. if we've saved all the registers from
21545 first_gp_reg_save. Otherwise, we risk loading garbage. */
21546 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
21547 == SAVE_INLINE_GPRS
)
21551 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
21552 if (!save_reg_p (i
))
21554 strategy
|= REST_INLINE_GPRS
;
21559 if (TARGET_ELF
&& TARGET_64BIT
)
21561 if (!(strategy
& SAVE_INLINE_FPRS
))
21562 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
21563 else if (!(strategy
& SAVE_INLINE_GPRS
)
21564 && info
->first_fp_reg_save
== 64)
21565 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
21567 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
21568 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
21570 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
21571 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
21576 /* Calculate the stack information for the current function. This is
21577 complicated by having two separate calling sequences, the AIX calling
21578 sequence and the V.4 calling sequence.
21580 AIX (and Darwin/Mac OS X) stack frames look like:
21582 SP----> +---------------------------------------+
21583 | back chain to caller | 0 0
21584 +---------------------------------------+
21585 | saved CR | 4 8 (8-11)
21586 +---------------------------------------+
21588 +---------------------------------------+
21589 | reserved for compilers | 12 24
21590 +---------------------------------------+
21591 | reserved for binders | 16 32
21592 +---------------------------------------+
21593 | saved TOC pointer | 20 40
21594 +---------------------------------------+
21595 | Parameter save area (P) | 24 48
21596 +---------------------------------------+
21597 | Alloca space (A) | 24+P etc.
21598 +---------------------------------------+
21599 | Local variable space (L) | 24+P+A
21600 +---------------------------------------+
21601 | Float/int conversion temporary (X) | 24+P+A+L
21602 +---------------------------------------+
21603 | Save area for AltiVec registers (W) | 24+P+A+L+X
21604 +---------------------------------------+
21605 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
21606 +---------------------------------------+
21607 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
21608 +---------------------------------------+
21609 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
21610 +---------------------------------------+
21611 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
21612 +---------------------------------------+
21613 old SP->| back chain to caller's caller |
21614 +---------------------------------------+
21616 The required alignment for AIX configurations is two words (i.e., 8
21619 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
21621 SP----> +---------------------------------------+
21622 | Back chain to caller | 0
21623 +---------------------------------------+
21624 | Save area for CR | 8
21625 +---------------------------------------+
21627 +---------------------------------------+
21628 | Saved TOC pointer | 24
21629 +---------------------------------------+
21630 | Parameter save area (P) | 32
21631 +---------------------------------------+
21632 | Alloca space (A) | 32+P
21633 +---------------------------------------+
21634 | Local variable space (L) | 32+P+A
21635 +---------------------------------------+
21636 | Save area for AltiVec registers (W) | 32+P+A+L
21637 +---------------------------------------+
21638 | AltiVec alignment padding (Y) | 32+P+A+L+W
21639 +---------------------------------------+
21640 | Save area for GP registers (G) | 32+P+A+L+W+Y
21641 +---------------------------------------+
21642 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
21643 +---------------------------------------+
21644 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
21645 +---------------------------------------+
21648 V.4 stack frames look like:
21650 SP----> +---------------------------------------+
21651 | back chain to caller | 0
21652 +---------------------------------------+
21653 | caller's saved LR | 4
21654 +---------------------------------------+
21655 | Parameter save area (P) | 8
21656 +---------------------------------------+
21657 | Alloca space (A) | 8+P
21658 +---------------------------------------+
21659 | Varargs save area (V) | 8+P+A
21660 +---------------------------------------+
21661 | Local variable space (L) | 8+P+A+V
21662 +---------------------------------------+
21663 | Float/int conversion temporary (X) | 8+P+A+V+L
21664 +---------------------------------------+
21665 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
21666 +---------------------------------------+
21667 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
21668 +---------------------------------------+
21669 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
21670 +---------------------------------------+
21671 | SPE: area for 64-bit GP registers |
21672 +---------------------------------------+
21673 | SPE alignment padding |
21674 +---------------------------------------+
21675 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
21676 +---------------------------------------+
21677 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
21678 +---------------------------------------+
21679 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
21680 +---------------------------------------+
21681 old SP->| back chain to caller's caller |
21682 +---------------------------------------+
21684 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
21685 given. (But note below and in sysv4.h that we require only 8 and
21686 may round up the size of our stack frame anyways. The historical
21687 reason is early versions of powerpc-linux which didn't properly
21688 align the stack at program startup. A happy side-effect is that
21689 -mno-eabi libraries can be used with -meabi programs.)
21691 The EABI configuration defaults to the V.4 layout. However,
21692 the stack alignment requirements may differ. If -mno-eabi is not
21693 given, the required stack alignment is 8 bytes; if -mno-eabi is
21694 given, the required alignment is 16 bytes. (But see V.4 comment
21697 #ifndef ABI_STACK_BOUNDARY
21698 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
21701 static rs6000_stack_t
*
21702 rs6000_stack_info (void)
21704 /* We should never be called for thunks, we are not set up for that. */
21705 gcc_assert (!cfun
->is_thunk
);
21707 rs6000_stack_t
*info_ptr
= &stack_info
;
21708 int reg_size
= TARGET_32BIT
? 4 : 8;
21713 HOST_WIDE_INT non_fixed_size
;
21714 bool using_static_chain_p
;
21716 if (reload_completed
&& info_ptr
->reload_completed
)
21719 memset (info_ptr
, 0, sizeof (*info_ptr
));
21720 info_ptr
->reload_completed
= reload_completed
;
21724 /* Cache value so we don't rescan instruction chain over and over. */
21725 if (cfun
->machine
->insn_chain_scanned_p
== 0)
21726 cfun
->machine
->insn_chain_scanned_p
21727 = spe_func_has_64bit_regs_p () + 1;
21728 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
21731 /* Select which calling sequence. */
21732 info_ptr
->abi
= DEFAULT_ABI
;
21734 /* Calculate which registers need to be saved & save area size. */
21735 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
21736 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
21737 even if it currently looks like we won't. Reload may need it to
21738 get at a constant; if so, it will have already created a constant
21739 pool entry for it. */
21740 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
21741 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
21742 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
21743 && crtl
->uses_const_pool
21744 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
21745 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
21747 first_gp
= info_ptr
->first_gp_reg_save
;
21749 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
21751 /* For the SPE, we have an additional upper 32-bits on each GPR.
21752 Ideally we should save the entire 64-bits only when the upper
21753 half is used in SIMD instructions. Since we only record
21754 registers live (not the size they are used in), this proves
21755 difficult because we'd have to traverse the instruction chain at
21756 the right time, taking reload into account. This is a real pain,
21757 so we opt to save the GPRs in 64-bits always if but one register
21758 gets used in 64-bits. Otherwise, all the registers in the frame
21759 get saved in 32-bits.
21761 So... since when we save all GPRs (except the SP) in 64-bits, the
21762 traditional GP save area will be empty. */
21763 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21764 info_ptr
->gp_size
= 0;
21766 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
21767 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
21769 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
21770 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
21771 - info_ptr
->first_altivec_reg_save
);
21773 /* Does this function call anything? */
21774 info_ptr
->calls_p
= (! crtl
->is_leaf
21775 || cfun
->machine
->ra_needs_full_frame
);
21777 /* Determine if we need to save the condition code registers. */
21778 if (df_regs_ever_live_p (CR2_REGNO
)
21779 || df_regs_ever_live_p (CR3_REGNO
)
21780 || df_regs_ever_live_p (CR4_REGNO
))
21782 info_ptr
->cr_save_p
= 1;
21783 if (DEFAULT_ABI
== ABI_V4
)
21784 info_ptr
->cr_size
= reg_size
;
21787 /* If the current function calls __builtin_eh_return, then we need
21788 to allocate stack space for registers that will hold data for
21789 the exception handler. */
21790 if (crtl
->calls_eh_return
)
21793 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
21796 /* SPE saves EH registers in 64-bits. */
21797 ehrd_size
= i
* (TARGET_SPE_ABI
21798 && info_ptr
->spe_64bit_regs_used
!= 0
21799 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
21804 /* In the ELFv2 ABI, we also need to allocate space for separate
21805 CR field save areas if the function calls __builtin_eh_return. */
21806 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
21808 /* This hard-codes that we have three call-saved CR fields. */
21809 ehcr_size
= 3 * reg_size
;
21810 /* We do *not* use the regular CR save mechanism. */
21811 info_ptr
->cr_save_p
= 0;
21816 /* Determine various sizes. */
21817 info_ptr
->reg_size
= reg_size
;
21818 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
21819 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
21820 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
21821 TARGET_ALTIVEC
? 16 : 8);
21822 if (FRAME_GROWS_DOWNWARD
)
21823 info_ptr
->vars_size
21824 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
21825 + info_ptr
->parm_size
,
21826 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
21827 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
21828 + info_ptr
->parm_size
);
21830 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21831 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
21833 info_ptr
->spe_gp_size
= 0;
21835 if (TARGET_ALTIVEC_ABI
)
21836 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
21838 info_ptr
->vrsave_mask
= 0;
21840 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
21841 info_ptr
->vrsave_size
= 4;
21843 info_ptr
->vrsave_size
= 0;
21845 compute_save_world_info (info_ptr
);
21847 /* Calculate the offsets. */
21848 switch (DEFAULT_ABI
)
21852 gcc_unreachable ();
21857 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21858 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21860 if (TARGET_ALTIVEC_ABI
)
21862 info_ptr
->vrsave_save_offset
21863 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
21865 /* Align stack so vector save area is on a quadword boundary.
21866 The padding goes above the vectors. */
21867 if (info_ptr
->altivec_size
!= 0)
21868 info_ptr
->altivec_padding_size
21869 = info_ptr
->vrsave_save_offset
& 0xF;
21871 info_ptr
->altivec_padding_size
= 0;
21873 info_ptr
->altivec_save_offset
21874 = info_ptr
->vrsave_save_offset
21875 - info_ptr
->altivec_padding_size
21876 - info_ptr
->altivec_size
;
21877 gcc_assert (info_ptr
->altivec_size
== 0
21878 || info_ptr
->altivec_save_offset
% 16 == 0);
21880 /* Adjust for AltiVec case. */
21881 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
21884 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
21886 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
21887 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
21888 info_ptr
->lr_save_offset
= 2*reg_size
;
21892 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
21893 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
21894 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
21896 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
21898 /* Align stack so SPE GPR save area is aligned on a
21899 double-word boundary. */
21900 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
21901 info_ptr
->spe_padding_size
21902 = 8 - (-info_ptr
->cr_save_offset
% 8);
21904 info_ptr
->spe_padding_size
= 0;
21906 info_ptr
->spe_gp_save_offset
21907 = info_ptr
->cr_save_offset
21908 - info_ptr
->spe_padding_size
21909 - info_ptr
->spe_gp_size
;
21911 /* Adjust for SPE case. */
21912 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
21914 else if (TARGET_ALTIVEC_ABI
)
21916 info_ptr
->vrsave_save_offset
21917 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
21919 /* Align stack so vector save area is on a quadword boundary. */
21920 if (info_ptr
->altivec_size
!= 0)
21921 info_ptr
->altivec_padding_size
21922 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
21924 info_ptr
->altivec_padding_size
= 0;
21926 info_ptr
->altivec_save_offset
21927 = info_ptr
->vrsave_save_offset
21928 - info_ptr
->altivec_padding_size
21929 - info_ptr
->altivec_size
;
21931 /* Adjust for AltiVec case. */
21932 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
21935 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
21936 info_ptr
->ehrd_offset
-= ehrd_size
;
21937 info_ptr
->lr_save_offset
= reg_size
;
21941 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
21942 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
21943 + info_ptr
->gp_size
21944 + info_ptr
->altivec_size
21945 + info_ptr
->altivec_padding_size
21946 + info_ptr
->spe_gp_size
21947 + info_ptr
->spe_padding_size
21950 + info_ptr
->cr_size
21951 + info_ptr
->vrsave_size
,
21954 non_fixed_size
= (info_ptr
->vars_size
21955 + info_ptr
->parm_size
21956 + info_ptr
->save_size
);
21958 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
21959 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
21961 /* Determine if we need to save the link register. */
21962 if (info_ptr
->calls_p
21963 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21965 && !TARGET_PROFILE_KERNEL
)
21966 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
21967 #ifdef TARGET_RELOCATABLE
21968 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
21970 || rs6000_ra_ever_killed ())
21971 info_ptr
->lr_save_p
= 1;
21973 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
21974 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
21975 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
21976 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
21977 using_static_chain_p
);
21979 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
21980 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
21981 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
21982 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
21983 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
21984 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
21985 info_ptr
->lr_save_p
= 1;
21987 if (info_ptr
->lr_save_p
)
21988 df_set_regs_ever_live (LR_REGNO
, true);
21990 /* Determine if we need to allocate any stack frame:
21992 For AIX we need to push the stack if a frame pointer is needed
21993 (because the stack might be dynamically adjusted), if we are
21994 debugging, if we make calls, or if the sum of fp_save, gp_save,
21995 and local variables are more than the space needed to save all
21996 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
21997 + 18*8 = 288 (GPR13 reserved).
21999 For V.4 we don't have the stack cushion that AIX uses, but assume
22000 that the debugger can handle stackless frames. */
22002 if (info_ptr
->calls_p
)
22003 info_ptr
->push_p
= 1;
22005 else if (DEFAULT_ABI
== ABI_V4
)
22006 info_ptr
->push_p
= non_fixed_size
!= 0;
22008 else if (frame_pointer_needed
)
22009 info_ptr
->push_p
= 1;
22011 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
22012 info_ptr
->push_p
= 1;
22015 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
22017 /* Zero offsets if we're not saving those registers. */
22018 if (info_ptr
->fp_size
== 0)
22019 info_ptr
->fp_save_offset
= 0;
22021 if (info_ptr
->gp_size
== 0)
22022 info_ptr
->gp_save_offset
= 0;
22024 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
22025 info_ptr
->altivec_save_offset
= 0;
22027 /* Zero VRSAVE offset if not saved and restored. */
22028 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
22029 info_ptr
->vrsave_save_offset
= 0;
22031 if (! TARGET_SPE_ABI
22032 || info_ptr
->spe_64bit_regs_used
== 0
22033 || info_ptr
->spe_gp_size
== 0)
22034 info_ptr
->spe_gp_save_offset
= 0;
22036 if (! info_ptr
->lr_save_p
)
22037 info_ptr
->lr_save_offset
= 0;
22039 if (! info_ptr
->cr_save_p
)
22040 info_ptr
->cr_save_offset
= 0;
22045 /* Return true if the current function uses any GPRs in 64-bit SIMD
22049 spe_func_has_64bit_regs_p (void)
22051 rtx_insn
*insns
, *insn
;
22053 /* Functions that save and restore all the call-saved registers will
22054 need to save/restore the registers in 64-bits. */
22055 if (crtl
->calls_eh_return
22056 || cfun
->calls_setjmp
22057 || crtl
->has_nonlocal_goto
)
22060 insns
= get_insns ();
22062 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
22068 /* FIXME: This should be implemented with attributes...
22070 (set_attr "spe64" "true")....then,
22071 if (get_spe64(insn)) return true;
22073 It's the only reliable way to do the stuff below. */
22075 i
= PATTERN (insn
);
22076 if (GET_CODE (i
) == SET
)
22078 machine_mode mode
= GET_MODE (SET_SRC (i
));
22080 if (SPE_VECTOR_MODE (mode
))
22082 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
22092 debug_stack_info (rs6000_stack_t
*info
)
22094 const char *abi_string
;
22097 info
= rs6000_stack_info ();
22099 fprintf (stderr
, "\nStack information for function %s:\n",
22100 ((current_function_decl
&& DECL_NAME (current_function_decl
))
22101 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
22106 default: abi_string
= "Unknown"; break;
22107 case ABI_NONE
: abi_string
= "NONE"; break;
22108 case ABI_AIX
: abi_string
= "AIX"; break;
22109 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
22110 case ABI_DARWIN
: abi_string
= "Darwin"; break;
22111 case ABI_V4
: abi_string
= "V.4"; break;
22114 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
22116 if (TARGET_ALTIVEC_ABI
)
22117 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
22119 if (TARGET_SPE_ABI
)
22120 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
22122 if (info
->first_gp_reg_save
!= 32)
22123 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
22125 if (info
->first_fp_reg_save
!= 64)
22126 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
22128 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
22129 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
22130 info
->first_altivec_reg_save
);
22132 if (info
->lr_save_p
)
22133 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
22135 if (info
->cr_save_p
)
22136 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
22138 if (info
->vrsave_mask
)
22139 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
22142 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
22145 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
22147 if (info
->gp_save_offset
)
22148 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
22150 if (info
->fp_save_offset
)
22151 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
22153 if (info
->altivec_save_offset
)
22154 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
22155 info
->altivec_save_offset
);
22157 if (info
->spe_gp_save_offset
)
22158 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
22159 info
->spe_gp_save_offset
);
22161 if (info
->vrsave_save_offset
)
22162 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
22163 info
->vrsave_save_offset
);
22165 if (info
->lr_save_offset
)
22166 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
22168 if (info
->cr_save_offset
)
22169 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
22171 if (info
->varargs_save_offset
)
22172 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
22174 if (info
->total_size
)
22175 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
22178 if (info
->vars_size
)
22179 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
22182 if (info
->parm_size
)
22183 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
22185 if (info
->fixed_size
)
22186 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
22189 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
22191 if (info
->spe_gp_size
)
22192 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
22195 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
22197 if (info
->altivec_size
)
22198 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
22200 if (info
->vrsave_size
)
22201 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
22203 if (info
->altivec_padding_size
)
22204 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
22205 info
->altivec_padding_size
);
22207 if (info
->spe_padding_size
)
22208 fprintf (stderr
, "\tspe_padding_size = %5d\n",
22209 info
->spe_padding_size
);
22212 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
22214 if (info
->save_size
)
22215 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
22217 if (info
->reg_size
!= 4)
22218 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
22220 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
22222 fprintf (stderr
, "\n");
22226 rs6000_return_addr (int count
, rtx frame
)
22228 /* Currently we don't optimize very well between prolog and body
22229 code and for PIC code the code can be actually quite bad, so
22230 don't try to be too clever here. */
22232 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
22234 cfun
->machine
->ra_needs_full_frame
= 1;
22241 plus_constant (Pmode
,
22243 (gen_rtx_MEM (Pmode
,
22244 memory_address (Pmode
, frame
))),
22245 RETURN_ADDRESS_OFFSET
)));
22248 cfun
->machine
->ra_need_lr
= 1;
22249 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
22252 /* Say whether a function is a candidate for sibcall handling or not. */
22255 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
22260 fntype
= TREE_TYPE (decl
);
22262 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
22264 /* We can't do it if the called function has more vector parameters
22265 than the current function; there's nowhere to put the VRsave code. */
22266 if (TARGET_ALTIVEC_ABI
22267 && TARGET_ALTIVEC_VRSAVE
22268 && !(decl
&& decl
== current_function_decl
))
22270 function_args_iterator args_iter
;
22274 /* Functions with vector parameters are required to have a
22275 prototype, so the argument type info must be available
22277 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
22278 if (TREE_CODE (type
) == VECTOR_TYPE
22279 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
22282 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
22283 if (TREE_CODE (type
) == VECTOR_TYPE
22284 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
22291 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
22292 functions, because the callee may have a different TOC pointer to
22293 the caller and there's no way to ensure we restore the TOC when
22294 we return. With the secure-plt SYSV ABI we can't make non-local
22295 calls when -fpic/PIC because the plt call stubs use r30. */
22296 if (DEFAULT_ABI
== ABI_DARWIN
22297 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22299 && !DECL_EXTERNAL (decl
)
22300 && (*targetm
.binds_local_p
) (decl
))
22301 || (DEFAULT_ABI
== ABI_V4
22302 && (!TARGET_SECURE_PLT
22305 && (*targetm
.binds_local_p
) (decl
)))))
22307 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
22309 if (!lookup_attribute ("longcall", attr_list
)
22310 || lookup_attribute ("shortcall", attr_list
))
22318 rs6000_ra_ever_killed (void)
22324 if (cfun
->is_thunk
)
22327 if (cfun
->machine
->lr_save_state
)
22328 return cfun
->machine
->lr_save_state
- 1;
22330 /* regs_ever_live has LR marked as used if any sibcalls are present,
22331 but this should not force saving and restoring in the
22332 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
22333 clobbers LR, so that is inappropriate. */
22335 /* Also, the prologue can generate a store into LR that
22336 doesn't really count, like this:
22339 bcl to set PIC register
22343 When we're called from the epilogue, we need to avoid counting
22344 this as a store. */
22346 push_topmost_sequence ();
22347 top
= get_insns ();
22348 pop_topmost_sequence ();
22349 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
22351 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
22357 if (!SIBLING_CALL_P (insn
))
22360 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
22362 else if (set_of (reg
, insn
) != NULL_RTX
22363 && !prologue_epilogue_contains (insn
))
22370 /* Emit instructions needed to load the TOC register.
22371 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
22372 a constant pool; or for SVR4 -fpic. */
22375 rs6000_emit_load_toc_table (int fromprolog
)
22378 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
22380 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
22383 rtx lab
, tmp1
, tmp2
, got
;
22385 lab
= gen_label_rtx ();
22386 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
22387 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
22389 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
22391 got
= rs6000_got_sym ();
22392 tmp1
= tmp2
= dest
;
22395 tmp1
= gen_reg_rtx (Pmode
);
22396 tmp2
= gen_reg_rtx (Pmode
);
22398 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
22399 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
22400 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
22401 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
22403 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
22405 emit_insn (gen_load_toc_v4_pic_si ());
22406 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
22408 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
22411 rtx temp0
= (fromprolog
22412 ? gen_rtx_REG (Pmode
, 0)
22413 : gen_reg_rtx (Pmode
));
22419 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
22420 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
22422 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
22423 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
22425 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
22426 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
22427 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
22433 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
22434 lab
= gen_label_rtx ();
22435 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
22436 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
22437 if (TARGET_LINK_STACK
)
22438 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
22439 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
22441 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
22443 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
22445 /* This is for AIX code running in non-PIC ELF32. */
22448 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
22449 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
22451 emit_insn (gen_elf_high (dest
, realsym
));
22452 emit_insn (gen_elf_low (dest
, dest
, realsym
));
22456 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
22459 emit_insn (gen_load_toc_aix_si (dest
));
22461 emit_insn (gen_load_toc_aix_di (dest
));
22465 /* Emit instructions to restore the link register after determining where
22466 its value has been stored. */
22469 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
22471 rs6000_stack_t
*info
= rs6000_stack_info ();
22474 operands
[0] = source
;
22475 operands
[1] = scratch
;
22477 if (info
->lr_save_p
)
22479 rtx frame_rtx
= stack_pointer_rtx
;
22480 HOST_WIDE_INT sp_offset
= 0;
22483 if (frame_pointer_needed
22484 || cfun
->calls_alloca
22485 || info
->total_size
> 32767)
22487 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
22488 emit_move_insn (operands
[1], tmp
);
22489 frame_rtx
= operands
[1];
22491 else if (info
->push_p
)
22492 sp_offset
= info
->total_size
;
22494 tmp
= plus_constant (Pmode
, frame_rtx
,
22495 info
->lr_save_offset
+ sp_offset
);
22496 tmp
= gen_frame_mem (Pmode
, tmp
);
22497 emit_move_insn (tmp
, operands
[0]);
22500 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
22502 /* Freeze lr_save_p. We've just emitted rtl that depends on the
22503 state of lr_save_p so any change from here on would be a bug. In
22504 particular, stop rs6000_ra_ever_killed from considering the SET
22505 of lr we may have added just above. */
22506 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
22509 static GTY(()) alias_set_type set
= -1;
22512 get_TOC_alias_set (void)
22515 set
= new_alias_set ();
22519 /* This returns nonzero if the current function uses the TOC. This is
22520 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
22521 is generated by the ABI_V4 load_toc_* patterns. */
22528 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
22531 rtx pat
= PATTERN (insn
);
22534 if (GET_CODE (pat
) == PARALLEL
)
22535 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
22537 rtx sub
= XVECEXP (pat
, 0, i
);
22538 if (GET_CODE (sub
) == USE
)
22540 sub
= XEXP (sub
, 0);
22541 if (GET_CODE (sub
) == UNSPEC
22542 && XINT (sub
, 1) == UNSPEC_TOC
)
22552 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
22554 rtx tocrel
, tocreg
, hi
;
22556 if (TARGET_DEBUG_ADDR
)
22558 if (GET_CODE (symbol
) == SYMBOL_REF
)
22559 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
22563 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
22564 GET_RTX_NAME (GET_CODE (symbol
)));
22565 debug_rtx (symbol
);
22569 if (!can_create_pseudo_p ())
22570 df_set_regs_ever_live (TOC_REGISTER
, true);
22572 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
22573 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
22574 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
22577 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
22578 if (largetoc_reg
!= NULL
)
22580 emit_move_insn (largetoc_reg
, hi
);
22583 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
22586 /* Issue assembly directives that create a reference to the given DWARF
22587 FRAME_TABLE_LABEL from the current function section. */
22589 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
22591 fprintf (asm_out_file
, "\t.ref %s\n",
22592 (* targetm
.strip_name_encoding
) (frame_table_label
));
22595 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
22596 and the change to the stack pointer. */
22599 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
22606 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22607 if (hard_frame_needed
)
22608 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
22609 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
22610 || (hard_frame_needed
22611 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
22614 p
= rtvec_alloc (i
);
22617 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
22618 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
22621 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
22624 /* Emit the correct code for allocating stack space, as insns.
22625 If COPY_REG, make sure a copy of the old frame is left there.
22626 The generated code may use hard register 0 as a temporary. */
22629 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
22632 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22633 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
22634 rtx todec
= gen_int_mode (-size
, Pmode
);
22637 if (INTVAL (todec
) != -size
)
22639 warning (0, "stack frame too large");
22640 emit_insn (gen_trap ());
22644 if (crtl
->limit_stack
)
22646 if (REG_P (stack_limit_rtx
)
22647 && REGNO (stack_limit_rtx
) > 1
22648 && REGNO (stack_limit_rtx
) <= 31)
22650 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
22651 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
22654 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
22656 && DEFAULT_ABI
== ABI_V4
)
22658 rtx toload
= gen_rtx_CONST (VOIDmode
,
22659 gen_rtx_PLUS (Pmode
,
22663 emit_insn (gen_elf_high (tmp_reg
, toload
));
22664 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
22665 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
22669 warning (0, "stack limit expression is not supported");
22675 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
22677 emit_move_insn (copy_reg
, stack_reg
);
22682 /* Need a note here so that try_split doesn't get confused. */
22683 if (get_last_insn () == NULL_RTX
)
22684 emit_note (NOTE_INSN_DELETED
);
22685 insn
= emit_move_insn (tmp_reg
, todec
);
22686 try_split (PATTERN (insn
), insn
, 0);
22690 insn
= emit_insn (TARGET_32BIT
22691 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
22693 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
22694 todec
, stack_reg
));
22695 /* Since we didn't use gen_frame_mem to generate the MEM, grab
22696 it now and set the alias set/attributes. The above gen_*_update
22697 calls will generate a PARALLEL with the MEM set being the first
22699 par
= PATTERN (insn
);
22700 gcc_assert (GET_CODE (par
) == PARALLEL
);
22701 set
= XVECEXP (par
, 0, 0);
22702 gcc_assert (GET_CODE (set
) == SET
);
22703 mem
= SET_DEST (set
);
22704 gcc_assert (MEM_P (mem
));
22705 MEM_NOTRAP_P (mem
) = 1;
22706 set_mem_alias_set (mem
, get_frame_alias_set ());
22708 RTX_FRAME_RELATED_P (insn
) = 1;
22709 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22710 gen_rtx_SET (stack_reg
, gen_rtx_PLUS (Pmode
, stack_reg
,
22711 GEN_INT (-size
))));
22714 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
22716 #if PROBE_INTERVAL > 32768
22717 #error Cannot use indexed addressing mode for stack probing
22720 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
22721 inclusive. These are offsets from the current stack pointer. */
22724 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
22726 /* See if we have a constant small number of probes to generate. If so,
22727 that's the easy case. */
22728 if (first
+ size
<= 32768)
22732 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
22733 it exceeds SIZE. If only one probe is needed, this will not
22734 generate any code. Then probe at FIRST + SIZE. */
22735 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
22736 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22739 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
22743 /* Otherwise, do the same as above, but in a loop. Note that we must be
22744 extra careful with variables wrapping around because we might be at
22745 the very top (or the very bottom) of the address space and we have
22746 to be able to handle this case properly; in particular, we use an
22747 equality test for the loop condition. */
22750 HOST_WIDE_INT rounded_size
;
22751 rtx r12
= gen_rtx_REG (Pmode
, 12);
22752 rtx r0
= gen_rtx_REG (Pmode
, 0);
22754 /* Sanity check for the addressing mode we're going to use. */
22755 gcc_assert (first
<= 32768);
22757 /* Step 1: round SIZE to the previous multiple of the interval. */
22759 rounded_size
= size
& -PROBE_INTERVAL
;
22762 /* Step 2: compute initial and final value of the loop counter. */
22764 /* TEST_ADDR = SP + FIRST. */
22765 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
22768 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
22769 if (rounded_size
> 32768)
22771 emit_move_insn (r0
, GEN_INT (-rounded_size
));
22772 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
22775 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
22779 /* Step 3: the loop
22781 while (TEST_ADDR != LAST_ADDR)
22783 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
22787 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
22788 until it is equal to ROUNDED_SIZE. */
22791 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
22793 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
22796 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
22797 that SIZE is equal to ROUNDED_SIZE. */
22799 if (size
!= rounded_size
)
22800 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
22804 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
22805 absolute addresses. */
22808 output_probe_stack_range (rtx reg1
, rtx reg2
)
22810 static int labelno
= 0;
22811 char loop_lab
[32], end_lab
[32];
22814 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
22815 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
22817 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
22819 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
22823 output_asm_insn ("cmpd 0,%0,%1", xops
);
22825 output_asm_insn ("cmpw 0,%0,%1", xops
);
22827 fputs ("\tbeq 0,", asm_out_file
);
22828 assemble_name_raw (asm_out_file
, end_lab
);
22829 fputc ('\n', asm_out_file
);
22831 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
22832 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
22833 output_asm_insn ("addi %0,%0,%1", xops
);
22835 /* Probe at TEST_ADDR and branch. */
22836 xops
[1] = gen_rtx_REG (Pmode
, 0);
22837 output_asm_insn ("stw %1,0(%0)", xops
);
22838 fprintf (asm_out_file
, "\tb ");
22839 assemble_name_raw (asm_out_file
, loop_lab
);
22840 fputc ('\n', asm_out_file
);
22842 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
22847 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
22848 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
22849 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
22850 deduce these equivalences by itself so it wasn't necessary to hold
22851 its hand so much. Don't be tempted to always supply d2_f_d_e with
22852 the actual cfa register, ie. r31 when we are using a hard frame
22853 pointer. That fails when saving regs off r1, and sched moves the
22854 r31 setup past the reg saves. */
22857 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
22858 rtx reg2
, rtx rreg
)
22862 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
22864 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
22867 gcc_checking_assert (val
== 0);
22868 real
= PATTERN (insn
);
22869 if (GET_CODE (real
) == PARALLEL
)
22870 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22871 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22873 rtx set
= XVECEXP (real
, 0, i
);
22875 RTX_FRAME_RELATED_P (set
) = 1;
22877 RTX_FRAME_RELATED_P (insn
) = 1;
22881 /* copy_rtx will not make unique copies of registers, so we need to
22882 ensure we don't have unwanted sharing here. */
22884 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22887 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
22889 real
= copy_rtx (PATTERN (insn
));
22891 if (reg2
!= NULL_RTX
)
22892 real
= replace_rtx (real
, reg2
, rreg
);
22894 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
22895 gcc_checking_assert (val
== 0);
22897 real
= replace_rtx (real
, reg
,
22898 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
22899 STACK_POINTER_REGNUM
),
22902 /* We expect that 'real' is either a SET or a PARALLEL containing
22903 SETs (and possibly other stuff). In a PARALLEL, all the SETs
22904 are important so they all have to be marked RTX_FRAME_RELATED_P. */
22906 if (GET_CODE (real
) == SET
)
22910 temp
= simplify_rtx (SET_SRC (set
));
22912 SET_SRC (set
) = temp
;
22913 temp
= simplify_rtx (SET_DEST (set
));
22915 SET_DEST (set
) = temp
;
22916 if (GET_CODE (SET_DEST (set
)) == MEM
)
22918 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22920 XEXP (SET_DEST (set
), 0) = temp
;
22927 gcc_assert (GET_CODE (real
) == PARALLEL
);
22928 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
22929 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
22931 rtx set
= XVECEXP (real
, 0, i
);
22933 temp
= simplify_rtx (SET_SRC (set
));
22935 SET_SRC (set
) = temp
;
22936 temp
= simplify_rtx (SET_DEST (set
));
22938 SET_DEST (set
) = temp
;
22939 if (GET_CODE (SET_DEST (set
)) == MEM
)
22941 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
22943 XEXP (SET_DEST (set
), 0) = temp
;
22945 RTX_FRAME_RELATED_P (set
) = 1;
22949 RTX_FRAME_RELATED_P (insn
) = 1;
22950 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
22955 /* Returns an insn that has a vrsave set operation with the
22956 appropriate CLOBBERs. */
22959 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
22962 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
22963 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22966 = gen_rtx_SET (vrsave
,
22967 gen_rtx_UNSPEC_VOLATILE (SImode
,
22968 gen_rtvec (2, reg
, vrsave
),
22969 UNSPECV_SET_VRSAVE
));
22973 /* We need to clobber the registers in the mask so the scheduler
22974 does not move sets to VRSAVE before sets of AltiVec registers.
22976 However, if the function receives nonlocal gotos, reload will set
22977 all call saved registers live. We will end up with:
22979 (set (reg 999) (mem))
22980 (parallel [ (set (reg vrsave) (unspec blah))
22981 (clobber (reg 999))])
22983 The clobber will cause the store into reg 999 to be dead, and
22984 flow will attempt to delete an epilogue insn. In this case, we
22985 need an unspec use/set of the register. */
22987 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22988 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22990 if (!epiloguep
|| call_used_regs
[i
])
22991 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
22992 gen_rtx_REG (V4SImode
, i
));
22995 rtx reg
= gen_rtx_REG (V4SImode
, i
);
22998 = gen_rtx_SET (reg
,
22999 gen_rtx_UNSPEC (V4SImode
,
23000 gen_rtvec (1, reg
), 27));
23004 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
23006 for (i
= 0; i
< nclobs
; ++i
)
23007 XVECEXP (insn
, 0, i
) = clobs
[i
];
23013 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
23017 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
23018 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
23019 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
23023 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
23025 return gen_frame_set (reg
, frame_reg
, offset
, false);
23029 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
23031 return gen_frame_set (reg
, frame_reg
, offset
, true);
23034 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
23035 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
23038 emit_frame_save (rtx frame_reg
, machine_mode mode
,
23039 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
23043 /* Some cases that need register indexed addressing. */
23044 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
23045 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
23046 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
23048 && SPE_VECTOR_MODE (mode
)
23049 && !SPE_CONST_OFFSET_OK (offset
))));
23051 reg
= gen_rtx_REG (mode
, regno
);
23052 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
23053 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
23054 NULL_RTX
, NULL_RTX
);
23057 /* Emit an offset memory reference suitable for a frame store, while
23058 converting to a valid addressing mode. */
23061 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
23063 rtx int_rtx
, offset_rtx
;
23065 int_rtx
= GEN_INT (offset
);
23067 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
23068 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
23070 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
23071 emit_move_insn (offset_rtx
, int_rtx
);
23074 offset_rtx
= int_rtx
;
23076 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
23079 #ifndef TARGET_FIX_AND_CONTINUE
23080 #define TARGET_FIX_AND_CONTINUE 0
23083 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
23084 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
23085 #define LAST_SAVRES_REGISTER 31
23086 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
23097 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
23099 /* Temporary holding space for an out-of-line register save/restore
23101 static char savres_routine_name
[30];
23103 /* Return the name for an out-of-line register save/restore routine.
23104 We are saving/restoring GPRs if GPR is true. */
23107 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
23109 const char *prefix
= "";
23110 const char *suffix
= "";
23112 /* Different targets are supposed to define
23113 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
23114 routine name could be defined with:
23116 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
23118 This is a nice idea in practice, but in reality, things are
23119 complicated in several ways:
23121 - ELF targets have save/restore routines for GPRs.
23123 - SPE targets use different prefixes for 32/64-bit registers, and
23124 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
23126 - PPC64 ELF targets have routines for save/restore of GPRs that
23127 differ in what they do with the link register, so having a set
23128 prefix doesn't work. (We only use one of the save routines at
23129 the moment, though.)
23131 - PPC32 elf targets have "exit" versions of the restore routines
23132 that restore the link register and can save some extra space.
23133 These require an extra suffix. (There are also "tail" versions
23134 of the restore routines and "GOT" versions of the save routines,
23135 but we don't generate those at present. Same problems apply,
23138 We deal with all this by synthesizing our own prefix/suffix and
23139 using that for the simple sprintf call shown above. */
23142 /* No floating point saves on the SPE. */
23143 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
23145 if ((sel
& SAVRES_SAVE
))
23146 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
23148 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
23150 if ((sel
& SAVRES_LR
))
23153 else if (DEFAULT_ABI
== ABI_V4
)
23158 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
23159 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
23160 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
23161 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
23162 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23163 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
23167 if ((sel
& SAVRES_LR
))
23170 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23172 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
23173 /* No out-of-line save/restore routines for GPRs on AIX. */
23174 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
23178 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
23179 prefix
= ((sel
& SAVRES_SAVE
)
23180 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
23181 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
23182 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
23184 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
23185 if ((sel
& SAVRES_LR
))
23186 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
23190 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
23191 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
23194 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23195 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
23200 if (DEFAULT_ABI
== ABI_DARWIN
)
23202 /* The Darwin approach is (slightly) different, in order to be
23203 compatible with code generated by the system toolchain. There is a
23204 single symbol for the start of save sequence, and the code here
23205 embeds an offset into that code on the basis of the first register
23207 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
23208 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
23209 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
23210 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
23211 (regno
- 13) * 4, prefix
, regno
);
23212 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
23213 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
23214 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
23215 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23216 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
23217 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
23222 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
23224 return savres_routine_name
;
23227 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
23228 We are saving/restoring GPRs if GPR is true. */
23231 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
23233 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
23234 ? info
->first_gp_reg_save
23235 : (sel
& SAVRES_REG
) == SAVRES_FPR
23236 ? info
->first_fp_reg_save
- 32
23237 : (sel
& SAVRES_REG
) == SAVRES_VR
23238 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
23243 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
23244 versions of the gpr routines. */
23245 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
23246 && info
->spe_64bit_regs_used
)
23247 select
^= SAVRES_FPR
^ SAVRES_GPR
;
23249 /* Don't generate bogus routine names. */
23250 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
23251 && regno
<= LAST_SAVRES_REGISTER
23252 && select
>= 0 && select
<= 12);
23254 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
23260 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23262 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
23263 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
23264 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
23270 /* Emit a sequence of insns, including a stack tie if needed, for
23271 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
23272 reset the stack pointer, but move the base of the frame into
23273 reg UPDT_REGNO for use by out-of-line register restore routines. */
23276 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
23277 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
23278 unsigned updt_regno
)
23282 /* This blockage is needed so that sched doesn't decide to move
23283 the sp change before the register restores. */
23284 if (DEFAULT_ABI
== ABI_V4
23286 && info
->spe_64bit_regs_used
!= 0
23287 && info
->first_gp_reg_save
!= 32))
23288 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
23290 /* If we are restoring registers out-of-line, we will be using the
23291 "exit" variants of the restore routines, which will reset the
23292 stack for us. But we do need to point updt_reg into the
23293 right place for those routines. */
23294 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
23296 if (frame_off
!= 0)
23297 return emit_insn (gen_add3_insn (updt_reg_rtx
,
23298 frame_reg_rtx
, GEN_INT (frame_off
)));
23299 else if (REGNO (frame_reg_rtx
) != updt_regno
)
23300 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
23305 /* Return the register number used as a pointer by out-of-line
23306 save/restore functions. */
23308 static inline unsigned
23309 ptr_regno_for_savres (int sel
)
23311 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23312 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
23313 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
23316 /* Construct a parallel rtx describing the effect of a call to an
23317 out-of-line register save/restore routine, and emit the insn
23318 or jump_insn as appropriate. */
23321 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
23322 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
23323 machine_mode reg_mode
, int sel
)
23326 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
23327 int reg_size
= GET_MODE_SIZE (reg_mode
);
23333 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
23334 ? info
->first_gp_reg_save
23335 : (sel
& SAVRES_REG
) == SAVRES_FPR
23336 ? info
->first_fp_reg_save
23337 : (sel
& SAVRES_REG
) == SAVRES_VR
23338 ? info
->first_altivec_reg_save
23340 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
23342 : (sel
& SAVRES_REG
) == SAVRES_FPR
23344 : (sel
& SAVRES_REG
) == SAVRES_VR
23345 ? LAST_ALTIVEC_REGNO
+ 1
23347 n_regs
= end_reg
- start_reg
;
23348 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
23349 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
23352 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
23353 RTVEC_ELT (p
, offset
++) = ret_rtx
;
23355 RTVEC_ELT (p
, offset
++)
23356 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
23358 sym
= rs6000_savres_routine_sym (info
, sel
);
23359 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
23361 use_reg
= ptr_regno_for_savres (sel
);
23362 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
23364 /* Vector regs are saved/restored using [reg+reg] addressing. */
23365 RTVEC_ELT (p
, offset
++)
23366 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
23367 RTVEC_ELT (p
, offset
++)
23368 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
23371 RTVEC_ELT (p
, offset
++)
23372 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
23374 for (i
= 0; i
< end_reg
- start_reg
; i
++)
23375 RTVEC_ELT (p
, i
+ offset
)
23376 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
23377 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
23378 (sel
& SAVRES_SAVE
) != 0);
23380 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
23381 RTVEC_ELT (p
, i
+ offset
)
23382 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
23384 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
23386 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
23388 insn
= emit_jump_insn (par
);
23389 JUMP_LABEL (insn
) = ret_rtx
;
23392 insn
= emit_insn (par
);
23396 /* Emit code to store CR fields that need to be saved into REG. */
23399 rs6000_emit_move_from_cr (rtx reg
)
23401 /* Only the ELFv2 ABI allows storing only selected fields. */
23402 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
23404 int i
, cr_reg
[8], count
= 0;
23406 /* Collect CR fields that must be saved. */
23407 for (i
= 0; i
< 8; i
++)
23408 if (save_reg_p (CR0_REGNO
+ i
))
23409 cr_reg
[count
++] = i
;
23411 /* If it's just a single one, use mfcrf. */
23414 rtvec p
= rtvec_alloc (1);
23415 rtvec r
= rtvec_alloc (2);
23416 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
23417 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
23419 = gen_rtx_SET (reg
,
23420 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
23422 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23426 /* ??? It might be better to handle count == 2 / 3 cases here
23427 as well, using logical operations to combine the values. */
23430 emit_insn (gen_movesi_from_cr (reg
));
23433 /* Determine whether the gp REG is really used. */
23436 rs6000_reg_live_or_pic_offset_p (int reg
)
23438 /* If the function calls eh_return, claim used all the registers that would
23439 be checked for liveness otherwise. This is required for the PIC offset
23440 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
23441 register allocation purposes in this case. */
23443 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
23444 && (!call_used_regs
[reg
]
23445 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
23446 && !TARGET_SINGLE_PIC_BASE
23447 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
23448 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
23449 && !TARGET_SINGLE_PIC_BASE
23450 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
23451 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
23454 /* Emit function prologue as insns. */
23457 rs6000_emit_prologue (void)
23459 rs6000_stack_t
*info
= rs6000_stack_info ();
23460 machine_mode reg_mode
= Pmode
;
23461 int reg_size
= TARGET_32BIT
? 4 : 8;
23462 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
23463 rtx frame_reg_rtx
= sp_reg_rtx
;
23464 unsigned int cr_save_regno
;
23465 rtx cr_save_rtx
= NULL_RTX
;
23468 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
23469 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
23470 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
23471 /* Offset to top of frame for frame_reg and sp respectively. */
23472 HOST_WIDE_INT frame_off
= 0;
23473 HOST_WIDE_INT sp_off
= 0;
23475 #ifdef ENABLE_CHECKING
23476 /* Track and check usage of r0, r11, r12. */
23477 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
23478 #define START_USE(R) do \
23480 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
23481 reg_inuse |= 1 << (R); \
23483 #define END_USE(R) do \
23485 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
23486 reg_inuse &= ~(1 << (R)); \
23488 #define NOT_INUSE(R) do \
23490 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
23493 #define START_USE(R) do {} while (0)
23494 #define END_USE(R) do {} while (0)
23495 #define NOT_INUSE(R) do {} while (0)
23498 if (DEFAULT_ABI
== ABI_ELFv2
)
23500 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
23502 /* With -mminimal-toc we may generate an extra use of r2 below. */
23503 if (!TARGET_SINGLE_PIC_BASE
23504 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
23505 cfun
->machine
->r2_setup_needed
= true;
23509 if (flag_stack_usage_info
)
23510 current_function_static_stack_size
= info
->total_size
;
23512 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
23514 HOST_WIDE_INT size
= info
->total_size
;
23516 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
23518 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
23519 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
23520 size
- STACK_CHECK_PROTECT
);
23523 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
23526 if (TARGET_FIX_AND_CONTINUE
)
23528 /* gdb on darwin arranges to forward a function from the old
23529 address by modifying the first 5 instructions of the function
23530 to branch to the overriding function. This is necessary to
23531 permit function pointers that point to the old function to
23532 actually forward to the new function. */
23533 emit_insn (gen_nop ());
23534 emit_insn (gen_nop ());
23535 emit_insn (gen_nop ());
23536 emit_insn (gen_nop ());
23537 emit_insn (gen_nop ());
23540 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
23542 reg_mode
= V2SImode
;
23546 /* Handle world saves specially here. */
23547 if (WORLD_SAVE_P (info
))
23554 /* save_world expects lr in r0. */
23555 reg0
= gen_rtx_REG (Pmode
, 0);
23556 if (info
->lr_save_p
)
23558 insn
= emit_move_insn (reg0
,
23559 gen_rtx_REG (Pmode
, LR_REGNO
));
23560 RTX_FRAME_RELATED_P (insn
) = 1;
23563 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
23564 assumptions about the offsets of various bits of the stack
23566 gcc_assert (info
->gp_save_offset
== -220
23567 && info
->fp_save_offset
== -144
23568 && info
->lr_save_offset
== 8
23569 && info
->cr_save_offset
== 4
23572 && (!crtl
->calls_eh_return
23573 || info
->ehrd_offset
== -432)
23574 && info
->vrsave_save_offset
== -224
23575 && info
->altivec_save_offset
== -416);
23577 treg
= gen_rtx_REG (SImode
, 11);
23578 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
23580 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
23581 in R11. It also clobbers R12, so beware! */
23583 /* Preserve CR2 for save_world prologues */
23585 sz
+= 32 - info
->first_gp_reg_save
;
23586 sz
+= 64 - info
->first_fp_reg_save
;
23587 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
23588 p
= rtvec_alloc (sz
);
23590 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
23591 gen_rtx_REG (SImode
,
23593 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
23594 gen_rtx_SYMBOL_REF (Pmode
,
23596 /* We do floats first so that the instruction pattern matches
23598 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23600 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23602 info
->first_fp_reg_save
+ i
),
23604 info
->fp_save_offset
+ frame_off
+ 8 * i
);
23605 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
23607 = gen_frame_store (gen_rtx_REG (V4SImode
,
23608 info
->first_altivec_reg_save
+ i
),
23610 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
23611 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23613 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23615 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23617 /* CR register traditionally saved as CR2. */
23619 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
23620 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
23621 /* Explain about use of R0. */
23622 if (info
->lr_save_p
)
23624 = gen_frame_store (reg0
,
23625 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
23626 /* Explain what happens to the stack pointer. */
23628 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
23629 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
23632 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23633 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23634 treg
, GEN_INT (-info
->total_size
));
23635 sp_off
= frame_off
= info
->total_size
;
23638 strategy
= info
->savres_strategy
;
23640 /* For V.4, update stack before we do any saving and set back pointer. */
23641 if (! WORLD_SAVE_P (info
)
23643 && (DEFAULT_ABI
== ABI_V4
23644 || crtl
->calls_eh_return
))
23646 bool need_r11
= (TARGET_SPE
23647 ? (!(strategy
& SAVE_INLINE_GPRS
)
23648 && info
->spe_64bit_regs_used
== 0)
23649 : (!(strategy
& SAVE_INLINE_FPRS
)
23650 || !(strategy
& SAVE_INLINE_GPRS
)
23651 || !(strategy
& SAVE_INLINE_VRS
)));
23652 int ptr_regno
= -1;
23653 rtx ptr_reg
= NULL_RTX
;
23656 if (info
->total_size
< 32767)
23657 frame_off
= info
->total_size
;
23660 else if (info
->cr_save_p
23662 || info
->first_fp_reg_save
< 64
23663 || info
->first_gp_reg_save
< 32
23664 || info
->altivec_size
!= 0
23665 || info
->vrsave_mask
!= 0
23666 || crtl
->calls_eh_return
)
23670 /* The prologue won't be saving any regs so there is no need
23671 to set up a frame register to access any frame save area.
23672 We also won't be using frame_off anywhere below, but set
23673 the correct value anyway to protect against future
23674 changes to this function. */
23675 frame_off
= info
->total_size
;
23677 if (ptr_regno
!= -1)
23679 /* Set up the frame offset to that needed by the first
23680 out-of-line save function. */
23681 START_USE (ptr_regno
);
23682 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23683 frame_reg_rtx
= ptr_reg
;
23684 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
23685 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
23686 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
23687 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
23688 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
23689 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
23690 frame_off
= -ptr_off
;
23692 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
23693 sp_off
= info
->total_size
;
23694 if (frame_reg_rtx
!= sp_reg_rtx
)
23695 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23698 /* If we use the link register, get it into r0. */
23699 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
23701 rtx addr
, reg
, mem
;
23703 reg
= gen_rtx_REG (Pmode
, 0);
23705 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23706 RTX_FRAME_RELATED_P (insn
) = 1;
23708 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
23709 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
23711 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
23712 GEN_INT (info
->lr_save_offset
+ frame_off
));
23713 mem
= gen_rtx_MEM (Pmode
, addr
);
23714 /* This should not be of rs6000_sr_alias_set, because of
23715 __builtin_return_address. */
23717 insn
= emit_move_insn (mem
, reg
);
23718 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23719 NULL_RTX
, NULL_RTX
);
23724 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
23725 r12 will be needed by out-of-line gpr restore. */
23726 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
23727 && !(strategy
& (SAVE_INLINE_GPRS
23728 | SAVE_NOINLINE_GPRS_SAVES_LR
))
23730 if (!WORLD_SAVE_P (info
)
23732 && REGNO (frame_reg_rtx
) != cr_save_regno
23733 && !(using_static_chain_p
&& cr_save_regno
== 11))
23735 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
23736 START_USE (cr_save_regno
);
23737 rs6000_emit_move_from_cr (cr_save_rtx
);
23740 /* Do any required saving of fpr's. If only one or two to save, do
23741 it ourselves. Otherwise, call function. */
23742 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
23745 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
23746 if (save_reg_p (info
->first_fp_reg_save
+ i
))
23747 emit_frame_save (frame_reg_rtx
,
23748 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23749 ? DFmode
: SFmode
),
23750 info
->first_fp_reg_save
+ i
,
23751 info
->fp_save_offset
+ frame_off
+ 8 * i
,
23752 sp_off
- frame_off
);
23754 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
23756 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23757 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23758 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23759 rtx ptr_reg
= frame_reg_rtx
;
23761 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23762 gcc_checking_assert (frame_off
== 0);
23765 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23766 NOT_INUSE (ptr_regno
);
23767 emit_insn (gen_add3_insn (ptr_reg
,
23768 frame_reg_rtx
, GEN_INT (frame_off
)));
23770 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23771 info
->fp_save_offset
,
23772 info
->lr_save_offset
,
23774 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
23775 NULL_RTX
, NULL_RTX
);
23780 /* Save GPRs. This is done as a PARALLEL if we are using
23781 the store-multiple instructions. */
23782 if (!WORLD_SAVE_P (info
)
23784 && info
->spe_64bit_regs_used
!= 0
23785 && info
->first_gp_reg_save
!= 32)
23788 rtx spe_save_area_ptr
;
23789 HOST_WIDE_INT save_off
;
23790 int ool_adjust
= 0;
23792 /* Determine whether we can address all of the registers that need
23793 to be saved with an offset from frame_reg_rtx that fits in
23794 the small const field for SPE memory instructions. */
23795 int spe_regs_addressable
23796 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23797 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23798 && (strategy
& SAVE_INLINE_GPRS
));
23800 if (spe_regs_addressable
)
23802 spe_save_area_ptr
= frame_reg_rtx
;
23803 save_off
= frame_off
;
23807 /* Make r11 point to the start of the SPE save area. We need
23808 to be careful here if r11 is holding the static chain. If
23809 it is, then temporarily save it in r0. */
23810 HOST_WIDE_INT offset
;
23812 if (!(strategy
& SAVE_INLINE_GPRS
))
23813 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23814 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
23815 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
23816 save_off
= frame_off
- offset
;
23818 if (using_static_chain_p
)
23820 rtx r0
= gen_rtx_REG (Pmode
, 0);
23823 gcc_assert (info
->first_gp_reg_save
> 11);
23825 emit_move_insn (r0
, spe_save_area_ptr
);
23827 else if (REGNO (frame_reg_rtx
) != 11)
23830 emit_insn (gen_addsi3 (spe_save_area_ptr
,
23831 frame_reg_rtx
, GEN_INT (offset
)));
23832 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
23833 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23836 if ((strategy
& SAVE_INLINE_GPRS
))
23838 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23839 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23840 emit_frame_save (spe_save_area_ptr
, reg_mode
,
23841 info
->first_gp_reg_save
+ i
,
23842 (info
->spe_gp_save_offset
+ save_off
23844 sp_off
- save_off
);
23848 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
23849 info
->spe_gp_save_offset
+ save_off
,
23851 SAVRES_SAVE
| SAVRES_GPR
);
23853 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
23854 NULL_RTX
, NULL_RTX
);
23857 /* Move the static chain pointer back. */
23858 if (!spe_regs_addressable
)
23860 if (using_static_chain_p
)
23862 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
23865 else if (REGNO (frame_reg_rtx
) != 11)
23869 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
23871 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
23872 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23873 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
23874 rtx ptr_reg
= frame_reg_rtx
;
23875 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
23876 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23880 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23882 /* Need to adjust r11 (r12) if we saved any FPRs. */
23883 if (end_save
+ frame_off
!= 0)
23885 rtx offset
= GEN_INT (end_save
+ frame_off
);
23888 frame_off
= -end_save
;
23890 NOT_INUSE (ptr_regno
);
23891 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23893 else if (!ptr_set_up
)
23895 NOT_INUSE (ptr_regno
);
23896 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23898 ptr_off
= -end_save
;
23899 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
23900 info
->gp_save_offset
+ ptr_off
,
23901 info
->lr_save_offset
+ ptr_off
,
23903 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
23904 NULL_RTX
, NULL_RTX
);
23908 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
23912 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23913 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23915 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23917 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23918 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23919 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
23920 NULL_RTX
, NULL_RTX
);
23922 else if (!WORLD_SAVE_P (info
))
23925 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23926 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23927 emit_frame_save (frame_reg_rtx
, reg_mode
,
23928 info
->first_gp_reg_save
+ i
,
23929 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
23930 sp_off
- frame_off
);
23933 if (crtl
->calls_eh_return
)
23940 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23941 if (regno
== INVALID_REGNUM
)
23945 p
= rtvec_alloc (i
);
23949 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
23950 if (regno
== INVALID_REGNUM
)
23954 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
23956 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
23957 RTVEC_ELT (p
, i
) = insn
;
23958 RTX_FRAME_RELATED_P (insn
) = 1;
23961 insn
= emit_insn (gen_blockage ());
23962 RTX_FRAME_RELATED_P (insn
) = 1;
23963 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
23966 /* In AIX ABI we need to make sure r2 is really saved. */
23967 if (TARGET_AIX
&& crtl
->calls_eh_return
)
23969 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
23970 rtx save_insn
, join_insn
, note
;
23971 long toc_restore_insn
;
23973 tmp_reg
= gen_rtx_REG (Pmode
, 11);
23974 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
23975 if (using_static_chain_p
)
23978 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
23982 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
23983 /* Peek at instruction to which this function returns. If it's
23984 restoring r2, then we know we've already saved r2. We can't
23985 unconditionally save r2 because the value we have will already
23986 be updated if we arrived at this function via a plt call or
23987 toc adjusting stub. */
23988 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
23989 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
23990 + RS6000_TOC_SAVE_SLOT
);
23991 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
23992 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
23993 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
23994 validate_condition_mode (EQ
, CCUNSmode
);
23995 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
23996 emit_insn (gen_rtx_SET (compare_result
,
23997 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
23998 toc_save_done
= gen_label_rtx ();
23999 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
24000 gen_rtx_EQ (VOIDmode
, compare_result
,
24002 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
24004 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
24005 JUMP_LABEL (jump
) = toc_save_done
;
24006 LABEL_NUSES (toc_save_done
) += 1;
24008 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
24009 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
24010 sp_off
- frame_off
);
24012 emit_label (toc_save_done
);
24014 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
24015 have a CFG that has different saves along different paths.
24016 Move the note to a dummy blockage insn, which describes that
24017 R2 is unconditionally saved after the label. */
24018 /* ??? An alternate representation might be a special insn pattern
24019 containing both the branch and the store. That might let the
24020 code that minimizes the number of DW_CFA_advance opcodes better
24021 freedom in placing the annotations. */
24022 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
24024 remove_note (save_insn
, note
);
24026 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
24027 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
24028 RTX_FRAME_RELATED_P (save_insn
) = 0;
24030 join_insn
= emit_insn (gen_blockage ());
24031 REG_NOTES (join_insn
) = note
;
24032 RTX_FRAME_RELATED_P (join_insn
) = 1;
24034 if (using_static_chain_p
)
24036 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
24043 /* Save CR if we use any that must be preserved. */
24044 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
24046 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
24047 GEN_INT (info
->cr_save_offset
+ frame_off
));
24048 rtx mem
= gen_frame_mem (SImode
, addr
);
24050 /* If we didn't copy cr before, do so now using r0. */
24051 if (cr_save_rtx
== NULL_RTX
)
24054 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
24055 rs6000_emit_move_from_cr (cr_save_rtx
);
24058 /* Saving CR requires a two-instruction sequence: one instruction
24059 to move the CR to a general-purpose register, and a second
24060 instruction that stores the GPR to memory.
24062 We do not emit any DWARF CFI records for the first of these,
24063 because we cannot properly represent the fact that CR is saved in
24064 a register. One reason is that we cannot express that multiple
24065 CR fields are saved; another reason is that on 64-bit, the size
24066 of the CR register in DWARF (4 bytes) differs from the size of
24067 a general-purpose register.
24069 This means if any intervening instruction were to clobber one of
24070 the call-saved CR fields, we'd have incorrect CFI. To prevent
24071 this from happening, we mark the store to memory as a use of
24072 those CR fields, which prevents any such instruction from being
24073 scheduled in between the two instructions. */
24078 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
24079 for (i
= 0; i
< 8; i
++)
24080 if (save_reg_p (CR0_REGNO
+ i
))
24081 crsave_v
[n_crsave
++]
24082 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
24084 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
24085 gen_rtvec_v (n_crsave
, crsave_v
)));
24086 END_USE (REGNO (cr_save_rtx
));
24088 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
24089 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
24090 so we need to construct a frame expression manually. */
24091 RTX_FRAME_RELATED_P (insn
) = 1;
24093 /* Update address to be stack-pointer relative, like
24094 rs6000_frame_related would do. */
24095 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
24096 GEN_INT (info
->cr_save_offset
+ sp_off
));
24097 mem
= gen_frame_mem (SImode
, addr
);
24099 if (DEFAULT_ABI
== ABI_ELFv2
)
24101 /* In the ELFv2 ABI we generate separate CFI records for each
24102 CR field that was actually saved. They all point to the
24103 same 32-bit stack slot. */
24107 for (i
= 0; i
< 8; i
++)
24108 if (save_reg_p (CR0_REGNO
+ i
))
24111 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24113 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
24117 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
24118 gen_rtx_PARALLEL (VOIDmode
,
24119 gen_rtvec_v (n_crframe
, crframe
)));
24123 /* In other ABIs, by convention, we use a single CR regnum to
24124 represent the fact that all call-saved CR fields are saved.
24125 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
24126 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
24127 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
24131 /* In the ELFv2 ABI we need to save all call-saved CR fields into
24132 *separate* slots if the routine calls __builtin_eh_return, so
24133 that they can be independently restored by the unwinder. */
24134 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
24136 int i
, cr_off
= info
->ehcr_offset
;
24139 /* ??? We might get better performance by using multiple mfocrf
24141 crsave
= gen_rtx_REG (SImode
, 0);
24142 emit_insn (gen_movesi_from_cr (crsave
));
24144 for (i
= 0; i
< 8; i
++)
24145 if (!call_used_regs
[CR0_REGNO
+ i
])
24147 rtvec p
= rtvec_alloc (2);
24149 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
24151 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
24153 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24155 RTX_FRAME_RELATED_P (insn
) = 1;
24156 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
24157 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
24158 sp_reg_rtx
, cr_off
+ sp_off
));
24160 cr_off
+= reg_size
;
24164 /* Update stack and set back pointer unless this is V.4,
24165 for which it was done previously. */
24166 if (!WORLD_SAVE_P (info
) && info
->push_p
24167 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
24169 rtx ptr_reg
= NULL
;
24172 /* If saving altivec regs we need to be able to address all save
24173 locations using a 16-bit offset. */
24174 if ((strategy
& SAVE_INLINE_VRS
) == 0
24175 || (info
->altivec_size
!= 0
24176 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
24177 + info
->total_size
- frame_off
) > 32767)
24178 || (info
->vrsave_size
!= 0
24179 && (info
->vrsave_save_offset
24180 + info
->total_size
- frame_off
) > 32767))
24182 int sel
= SAVRES_SAVE
| SAVRES_VR
;
24183 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
24185 if (using_static_chain_p
24186 && ptr_regno
== STATIC_CHAIN_REGNUM
)
24188 if (REGNO (frame_reg_rtx
) != ptr_regno
)
24189 START_USE (ptr_regno
);
24190 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
24191 frame_reg_rtx
= ptr_reg
;
24192 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
24193 frame_off
= -ptr_off
;
24195 else if (REGNO (frame_reg_rtx
) == 1)
24196 frame_off
= info
->total_size
;
24197 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
24198 sp_off
= info
->total_size
;
24199 if (frame_reg_rtx
!= sp_reg_rtx
)
24200 rs6000_emit_stack_tie (frame_reg_rtx
, false);
24203 /* Set frame pointer, if needed. */
24204 if (frame_pointer_needed
)
24206 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
24208 RTX_FRAME_RELATED_P (insn
) = 1;
24211 /* Save AltiVec registers if needed. Save here because the red zone does
24212 not always include AltiVec registers. */
24213 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
24214 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
24216 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24218 /* Oddly, the vector save/restore functions point r0 at the end
24219 of the save area, then use r11 or r12 to load offsets for
24220 [reg+reg] addressing. */
24221 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24222 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
24223 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24225 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
24227 if (end_save
+ frame_off
!= 0)
24229 rtx offset
= GEN_INT (end_save
+ frame_off
);
24231 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24234 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24236 ptr_off
= -end_save
;
24237 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24238 info
->altivec_save_offset
+ ptr_off
,
24239 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
24240 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
24241 NULL_RTX
, NULL_RTX
);
24242 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
24244 /* The oddity mentioned above clobbered our frame reg. */
24245 emit_move_insn (frame_reg_rtx
, ptr_reg
);
24246 frame_off
= ptr_off
;
24249 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
24250 && info
->altivec_size
!= 0)
24254 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24255 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24257 rtx areg
, savereg
, mem
;
24260 offset
= (info
->altivec_save_offset
+ frame_off
24261 + 16 * (i
- info
->first_altivec_reg_save
));
24263 savereg
= gen_rtx_REG (V4SImode
, i
);
24266 areg
= gen_rtx_REG (Pmode
, 0);
24267 emit_move_insn (areg
, GEN_INT (offset
));
24269 /* AltiVec addressing mode is [reg+reg]. */
24270 mem
= gen_frame_mem (V4SImode
,
24271 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
24273 /* Rather than emitting a generic move, force use of the stvx
24274 instruction, which we always want. In particular we don't
24275 want xxpermdi/stxvd2x for little endian. */
24276 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
24278 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
24279 areg
, GEN_INT (offset
));
24283 /* VRSAVE is a bit vector representing which AltiVec registers
24284 are used. The OS uses this to determine which vector
24285 registers to save on a context switch. We need to save
24286 VRSAVE on the stack frame, add whatever AltiVec registers we
24287 used in this function, and do the corresponding magic in the
24290 if (!WORLD_SAVE_P (info
)
24292 && TARGET_ALTIVEC_VRSAVE
24293 && info
->vrsave_mask
!= 0)
24299 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
24300 be using r12 as frame_reg_rtx and r11 as the static chain
24301 pointer for nested functions. */
24303 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24304 && !using_static_chain_p
)
24306 else if (REGNO (frame_reg_rtx
) == 12)
24309 if (using_static_chain_p
)
24313 NOT_INUSE (save_regno
);
24314 reg
= gen_rtx_REG (SImode
, save_regno
);
24315 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
24317 emit_insn (gen_get_vrsave_internal (reg
));
24319 emit_insn (gen_rtx_SET (reg
, vrsave
));
24322 offset
= info
->vrsave_save_offset
+ frame_off
;
24323 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
24325 /* Include the registers in the mask. */
24326 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
24328 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
24331 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
24332 if (!TARGET_SINGLE_PIC_BASE
24333 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
24334 || (DEFAULT_ABI
== ABI_V4
24335 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
24336 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
24338 /* If emit_load_toc_table will use the link register, we need to save
24339 it. We use R12 for this purpose because emit_load_toc_table
24340 can use register 0. This allows us to use a plain 'blr' to return
24341 from the procedure more often. */
24342 int save_LR_around_toc_setup
= (TARGET_ELF
24343 && DEFAULT_ABI
== ABI_V4
24345 && ! info
->lr_save_p
24346 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
24347 if (save_LR_around_toc_setup
)
24349 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
24350 rtx tmp
= gen_rtx_REG (Pmode
, 12);
24352 insn
= emit_move_insn (tmp
, lr
);
24353 RTX_FRAME_RELATED_P (insn
) = 1;
24355 rs6000_emit_load_toc_table (TRUE
);
24357 insn
= emit_move_insn (lr
, tmp
);
24358 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
24359 RTX_FRAME_RELATED_P (insn
) = 1;
24362 rs6000_emit_load_toc_table (TRUE
);
24366 if (!TARGET_SINGLE_PIC_BASE
24367 && DEFAULT_ABI
== ABI_DARWIN
24368 && flag_pic
&& crtl
->uses_pic_offset_table
)
24370 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
24371 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
24373 /* Save and restore LR locally around this call (in R0). */
24374 if (!info
->lr_save_p
)
24375 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
24377 emit_insn (gen_load_macho_picbase (src
));
24379 emit_move_insn (gen_rtx_REG (Pmode
,
24380 RS6000_PIC_OFFSET_TABLE_REGNUM
),
24383 if (!info
->lr_save_p
)
24384 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
24388 /* If we need to, save the TOC register after doing the stack setup.
24389 Do not emit eh frame info for this save. The unwinder wants info,
24390 conceptually attached to instructions in this function, about
24391 register values in the caller of this function. This R2 may have
24392 already been changed from the value in the caller.
24393 We don't attempt to write accurate DWARF EH frame info for R2
24394 because code emitted by gcc for a (non-pointer) function call
24395 doesn't save and restore R2. Instead, R2 is managed out-of-line
24396 by a linker generated plt call stub when the function resides in
24397 a shared library. This behaviour is costly to describe in DWARF,
24398 both in terms of the size of DWARF info and the time taken in the
24399 unwinder to interpret it. R2 changes, apart from the
24400 calls_eh_return case earlier in this function, are handled by
24401 linux-unwind.h frob_update_context. */
24402 if (rs6000_save_toc_in_prologue_p ())
24404 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
24405 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
24409 /* Output .extern statements for the save/restore routines we use. */
24412 rs6000_output_savres_externs (FILE *file
)
24414 rs6000_stack_t
*info
= rs6000_stack_info ();
24416 if (TARGET_DEBUG_STACK
)
24417 debug_stack_info (info
);
24419 /* Write .extern for any function we will call to save and restore
24421 if (info
->first_fp_reg_save
< 64
24426 int regno
= info
->first_fp_reg_save
- 32;
24428 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
24430 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
24431 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24432 name
= rs6000_savres_routine_name (info
, regno
, sel
);
24433 fprintf (file
, "\t.extern %s\n", name
);
24435 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
24437 bool lr
= (info
->savres_strategy
24438 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24439 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24440 name
= rs6000_savres_routine_name (info
, regno
, sel
);
24441 fprintf (file
, "\t.extern %s\n", name
);
24446 /* Write function prologue. */
24449 rs6000_output_function_prologue (FILE *file
,
24450 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
24452 if (!cfun
->is_thunk
)
24453 rs6000_output_savres_externs (file
);
24455 /* ELFv2 ABI r2 setup code and local entry point. This must follow
24456 immediately after the global entry point label. */
24457 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
24459 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24461 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
24462 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
24464 fputs ("\t.localentry\t", file
);
24465 assemble_name (file
, name
);
24466 fputs (",.-", file
);
24467 assemble_name (file
, name
);
24468 fputs ("\n", file
);
24471 /* Output -mprofile-kernel code. This needs to be done here instead of
24472 in output_function_profile since it must go after the ELFv2 ABI
24473 local entry point. */
24474 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
24476 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
24477 gcc_assert (!TARGET_32BIT
);
24479 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
24481 /* In the ELFv2 ABI we have no compiler stack word. It must be
24482 the resposibility of _mcount to preserve the static chain
24483 register if required. */
24484 if (DEFAULT_ABI
!= ABI_ELFv2
24485 && cfun
->static_chain_decl
!= NULL
)
24487 asm_fprintf (file
, "\tstd %s,24(%s)\n",
24488 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
24489 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
24490 asm_fprintf (file
, "\tld %s,24(%s)\n",
24491 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
24494 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
24497 rs6000_pic_labelno
++;
24500 /* Non-zero if vmx regs are restored before the frame pop, zero if
24501 we restore after the pop when possible. */
24502 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
24504 /* Restoring cr is a two step process: loading a reg from the frame
24505 save, then moving the reg to cr. For ABI_V4 we must let the
24506 unwinder know that the stack location is no longer valid at or
24507 before the stack deallocation, but we can't emit a cfa_restore for
24508 cr at the stack deallocation like we do for other registers.
24509 The trouble is that it is possible for the move to cr to be
24510 scheduled after the stack deallocation. So say exactly where cr
24511 is located on each of the two insns. */
24514 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
24516 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
24517 rtx reg
= gen_rtx_REG (SImode
, regno
);
24518 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
24520 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
24522 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
24523 rtx set
= gen_rtx_SET (reg
, cr
);
24525 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
24526 RTX_FRAME_RELATED_P (insn
) = 1;
24531 /* Reload CR from REG. */
24534 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
24539 if (using_mfcr_multiple
)
24541 for (i
= 0; i
< 8; i
++)
24542 if (save_reg_p (CR0_REGNO
+ i
))
24544 gcc_assert (count
);
24547 if (using_mfcr_multiple
&& count
> 1)
24553 p
= rtvec_alloc (count
);
24556 for (i
= 0; i
< 8; i
++)
24557 if (save_reg_p (CR0_REGNO
+ i
))
24559 rtvec r
= rtvec_alloc (2);
24560 RTVEC_ELT (r
, 0) = reg
;
24561 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
24562 RTVEC_ELT (p
, ndx
) =
24563 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
24564 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
24567 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24568 gcc_assert (ndx
== count
);
24570 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
24571 CR field separately. */
24572 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
24574 for (i
= 0; i
< 8; i
++)
24575 if (save_reg_p (CR0_REGNO
+ i
))
24576 add_reg_note (insn
, REG_CFA_RESTORE
,
24577 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24579 RTX_FRAME_RELATED_P (insn
) = 1;
24583 for (i
= 0; i
< 8; i
++)
24584 if (save_reg_p (CR0_REGNO
+ i
))
24586 rtx insn
= emit_insn (gen_movsi_to_cr_one
24587 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
24589 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
24590 CR field separately, attached to the insn that in fact
24591 restores this particular CR field. */
24592 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
24594 add_reg_note (insn
, REG_CFA_RESTORE
,
24595 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
24597 RTX_FRAME_RELATED_P (insn
) = 1;
24601 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
24602 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
24603 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
24605 rtx_insn
*insn
= get_last_insn ();
24606 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
24608 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
24609 RTX_FRAME_RELATED_P (insn
) = 1;
24613 /* Like cr, the move to lr instruction can be scheduled after the
24614 stack deallocation, but unlike cr, its stack frame save is still
24615 valid. So we only need to emit the cfa_restore on the correct
24619 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
24621 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
24622 rtx reg
= gen_rtx_REG (Pmode
, regno
);
24624 emit_move_insn (reg
, mem
);
24628 restore_saved_lr (int regno
, bool exit_func
)
24630 rtx reg
= gen_rtx_REG (Pmode
, regno
);
24631 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
24632 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
24634 if (!exit_func
&& flag_shrink_wrap
)
24636 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
24637 RTX_FRAME_RELATED_P (insn
) = 1;
24642 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
24644 if (DEFAULT_ABI
== ABI_ELFv2
)
24647 for (i
= 0; i
< 8; i
++)
24648 if (save_reg_p (CR0_REGNO
+ i
))
24650 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
24651 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
24655 else if (info
->cr_save_p
)
24656 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24657 gen_rtx_REG (SImode
, CR2_REGNO
),
24660 if (info
->lr_save_p
)
24661 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24662 gen_rtx_REG (Pmode
, LR_REGNO
),
24664 return cfa_restores
;
24667 /* Return true if OFFSET from stack pointer can be clobbered by signals.
24668 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
24669 below stack pointer not cloberred by signals. */
24672 offset_below_red_zone_p (HOST_WIDE_INT offset
)
24674 return offset
< (DEFAULT_ABI
== ABI_V4
24676 : TARGET_32BIT
? -220 : -288);
24679 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
24682 emit_cfa_restores (rtx cfa_restores
)
24684 rtx_insn
*insn
= get_last_insn ();
24685 rtx
*loc
= ®_NOTES (insn
);
24688 loc
= &XEXP (*loc
, 1);
24689 *loc
= cfa_restores
;
24690 RTX_FRAME_RELATED_P (insn
) = 1;
24693 /* Emit function epilogue as insns. */
24696 rs6000_emit_epilogue (int sibcall
)
24698 rs6000_stack_t
*info
;
24699 int restoring_GPRs_inline
;
24700 int restoring_FPRs_inline
;
24701 int using_load_multiple
;
24702 int using_mtcr_multiple
;
24703 int use_backchain_to_restore_sp
;
24706 HOST_WIDE_INT frame_off
= 0;
24707 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
24708 rtx frame_reg_rtx
= sp_reg_rtx
;
24709 rtx cfa_restores
= NULL_RTX
;
24711 rtx cr_save_reg
= NULL_RTX
;
24712 machine_mode reg_mode
= Pmode
;
24713 int reg_size
= TARGET_32BIT
? 4 : 8;
24716 unsigned ptr_regno
;
24718 info
= rs6000_stack_info ();
24720 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
24722 reg_mode
= V2SImode
;
24726 strategy
= info
->savres_strategy
;
24727 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
24728 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
24729 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
24730 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
24731 || rs6000_cpu
== PROCESSOR_PPC603
24732 || rs6000_cpu
== PROCESSOR_PPC750
24734 /* Restore via the backchain when we have a large frame, since this
24735 is more efficient than an addis, addi pair. The second condition
24736 here will not trigger at the moment; We don't actually need a
24737 frame pointer for alloca, but the generic parts of the compiler
24738 give us one anyway. */
24739 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
24740 || (cfun
->calls_alloca
24741 && !frame_pointer_needed
));
24742 restore_lr
= (info
->lr_save_p
24743 && (restoring_FPRs_inline
24744 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
24745 && (restoring_GPRs_inline
24746 || info
->first_fp_reg_save
< 64));
24748 if (WORLD_SAVE_P (info
))
24752 const char *alloc_rname
;
24755 /* eh_rest_world_r10 will return to the location saved in the LR
24756 stack slot (which is not likely to be our caller.)
24757 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
24758 rest_world is similar, except any R10 parameter is ignored.
24759 The exception-handling stuff that was here in 2.95 is no
24760 longer necessary. */
24764 + 32 - info
->first_gp_reg_save
24765 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
24766 + 63 + 1 - info
->first_fp_reg_save
);
24768 strcpy (rname
, ((crtl
->calls_eh_return
) ?
24769 "*eh_rest_world_r10" : "*rest_world"));
24770 alloc_rname
= ggc_strdup (rname
);
24773 RTVEC_ELT (p
, j
++) = ret_rtx
;
24774 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
24775 gen_rtx_REG (Pmode
,
24778 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
24779 /* The instruction pattern requires a clobber here;
24780 it is shared with the restVEC helper. */
24782 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
24785 /* CR register traditionally saved as CR2. */
24786 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
24788 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
24789 if (flag_shrink_wrap
)
24791 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
24792 gen_rtx_REG (Pmode
, LR_REGNO
),
24794 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24798 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24800 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
24802 = gen_frame_load (reg
,
24803 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
24804 if (flag_shrink_wrap
)
24805 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24807 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
24809 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
24811 = gen_frame_load (reg
,
24812 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
24813 if (flag_shrink_wrap
)
24814 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24816 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
24818 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24819 ? DFmode
: SFmode
),
24820 info
->first_fp_reg_save
+ i
);
24822 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24823 if (flag_shrink_wrap
)
24824 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24827 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
24829 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
24831 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
24833 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
24835 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
24836 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24838 if (flag_shrink_wrap
)
24840 REG_NOTES (insn
) = cfa_restores
;
24841 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24842 RTX_FRAME_RELATED_P (insn
) = 1;
24847 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
24849 frame_off
= info
->total_size
;
24851 /* Restore AltiVec registers if we must do so before adjusting the
24853 if (TARGET_ALTIVEC_ABI
24854 && info
->altivec_size
!= 0
24855 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24856 || (DEFAULT_ABI
!= ABI_V4
24857 && offset_below_red_zone_p (info
->altivec_save_offset
))))
24860 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
24862 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
24863 if (use_backchain_to_restore_sp
)
24865 int frame_regno
= 11;
24867 if ((strategy
& REST_INLINE_VRS
) == 0)
24869 /* Of r11 and r12, select the one not clobbered by an
24870 out-of-line restore function for the frame register. */
24871 frame_regno
= 11 + 12 - scratch_regno
;
24873 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
24874 emit_move_insn (frame_reg_rtx
,
24875 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24878 else if (frame_pointer_needed
)
24879 frame_reg_rtx
= hard_frame_pointer_rtx
;
24881 if ((strategy
& REST_INLINE_VRS
) == 0)
24883 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
24885 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
24886 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
24888 if (end_save
+ frame_off
!= 0)
24890 rtx offset
= GEN_INT (end_save
+ frame_off
);
24892 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
24895 emit_move_insn (ptr_reg
, frame_reg_rtx
);
24897 ptr_off
= -end_save
;
24898 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
24899 info
->altivec_save_offset
+ ptr_off
,
24900 0, V4SImode
, SAVRES_VR
);
24904 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24905 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
24907 rtx addr
, areg
, mem
, reg
;
24909 areg
= gen_rtx_REG (Pmode
, 0);
24911 (areg
, GEN_INT (info
->altivec_save_offset
24913 + 16 * (i
- info
->first_altivec_reg_save
)));
24915 /* AltiVec addressing mode is [reg+reg]. */
24916 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
24917 mem
= gen_frame_mem (V4SImode
, addr
);
24919 reg
= gen_rtx_REG (V4SImode
, i
);
24920 /* Rather than emitting a generic move, force use of the
24921 lvx instruction, which we always want. In particular
24922 we don't want lxvd2x/xxpermdi for little endian. */
24923 (void) emit_insn (gen_altivec_lvx_v4si_internal (reg
, mem
));
24927 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
24928 if (((strategy
& REST_INLINE_VRS
) == 0
24929 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
24930 && (flag_shrink_wrap
24931 || (offset_below_red_zone_p
24932 (info
->altivec_save_offset
24933 + 16 * (i
- info
->first_altivec_reg_save
)))))
24935 rtx reg
= gen_rtx_REG (V4SImode
, i
);
24936 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24940 /* Restore VRSAVE if we must do so before adjusting the stack. */
24942 && TARGET_ALTIVEC_VRSAVE
24943 && info
->vrsave_mask
!= 0
24944 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24945 || (DEFAULT_ABI
!= ABI_V4
24946 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
24950 if (frame_reg_rtx
== sp_reg_rtx
)
24952 if (use_backchain_to_restore_sp
)
24954 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24955 emit_move_insn (frame_reg_rtx
,
24956 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24959 else if (frame_pointer_needed
)
24960 frame_reg_rtx
= hard_frame_pointer_rtx
;
24963 reg
= gen_rtx_REG (SImode
, 12);
24964 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24965 info
->vrsave_save_offset
+ frame_off
));
24967 emit_insn (generate_set_vrsave (reg
, info
, 1));
24971 /* If we have a large stack frame, restore the old stack pointer
24972 using the backchain. */
24973 if (use_backchain_to_restore_sp
)
24975 if (frame_reg_rtx
== sp_reg_rtx
)
24977 /* Under V.4, don't reset the stack pointer until after we're done
24978 loading the saved registers. */
24979 if (DEFAULT_ABI
== ABI_V4
)
24980 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
24982 insn
= emit_move_insn (frame_reg_rtx
,
24983 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
24986 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24987 && DEFAULT_ABI
== ABI_V4
)
24988 /* frame_reg_rtx has been set up by the altivec restore. */
24992 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
24993 frame_reg_rtx
= sp_reg_rtx
;
24996 /* If we have a frame pointer, we can restore the old stack pointer
24998 else if (frame_pointer_needed
)
25000 frame_reg_rtx
= sp_reg_rtx
;
25001 if (DEFAULT_ABI
== ABI_V4
)
25002 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
25003 /* Prevent reordering memory accesses against stack pointer restore. */
25004 else if (cfun
->calls_alloca
25005 || offset_below_red_zone_p (-info
->total_size
))
25006 rs6000_emit_stack_tie (frame_reg_rtx
, true);
25008 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
25009 GEN_INT (info
->total_size
)));
25012 else if (info
->push_p
25013 && DEFAULT_ABI
!= ABI_V4
25014 && !crtl
->calls_eh_return
)
25016 /* Prevent reordering memory accesses against stack pointer restore. */
25017 if (cfun
->calls_alloca
25018 || offset_below_red_zone_p (-info
->total_size
))
25019 rs6000_emit_stack_tie (frame_reg_rtx
, false);
25020 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
25021 GEN_INT (info
->total_size
)));
25024 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
25028 REG_NOTES (insn
) = cfa_restores
;
25029 cfa_restores
= NULL_RTX
;
25031 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
25032 RTX_FRAME_RELATED_P (insn
) = 1;
25035 /* Restore AltiVec registers if we have not done so already. */
25036 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
25037 && TARGET_ALTIVEC_ABI
25038 && info
->altivec_size
!= 0
25039 && (DEFAULT_ABI
== ABI_V4
25040 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
25044 if ((strategy
& REST_INLINE_VRS
) == 0)
25046 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
25048 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
25049 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
25050 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
25052 if (end_save
+ frame_off
!= 0)
25054 rtx offset
= GEN_INT (end_save
+ frame_off
);
25056 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
25059 emit_move_insn (ptr_reg
, frame_reg_rtx
);
25061 ptr_off
= -end_save
;
25062 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
25063 info
->altivec_save_offset
+ ptr_off
,
25064 0, V4SImode
, SAVRES_VR
);
25065 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
25067 /* Frame reg was clobbered by out-of-line save. Restore it
25068 from ptr_reg, and if we are calling out-of-line gpr or
25069 fpr restore set up the correct pointer and offset. */
25070 unsigned newptr_regno
= 1;
25071 if (!restoring_GPRs_inline
)
25073 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
25074 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
25075 newptr_regno
= ptr_regno_for_savres (sel
);
25076 end_save
= info
->gp_save_offset
+ info
->gp_size
;
25078 else if (!restoring_FPRs_inline
)
25080 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
25081 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25082 newptr_regno
= ptr_regno_for_savres (sel
);
25083 end_save
= info
->fp_save_offset
+ info
->fp_size
;
25086 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
25087 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
25089 if (end_save
+ ptr_off
!= 0)
25091 rtx offset
= GEN_INT (end_save
+ ptr_off
);
25093 frame_off
= -end_save
;
25095 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
25098 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
25103 frame_off
= ptr_off
;
25104 emit_move_insn (frame_reg_rtx
, ptr_reg
);
25110 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25111 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
25113 rtx addr
, areg
, mem
, reg
;
25115 areg
= gen_rtx_REG (Pmode
, 0);
25117 (areg
, GEN_INT (info
->altivec_save_offset
25119 + 16 * (i
- info
->first_altivec_reg_save
)));
25121 /* AltiVec addressing mode is [reg+reg]. */
25122 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
25123 mem
= gen_frame_mem (V4SImode
, addr
);
25125 reg
= gen_rtx_REG (V4SImode
, i
);
25126 /* Rather than emitting a generic move, force use of the
25127 lvx instruction, which we always want. In particular
25128 we don't want lxvd2x/xxpermdi for little endian. */
25129 (void) emit_insn (gen_altivec_lvx_v4si_internal (reg
, mem
));
25133 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25134 if (((strategy
& REST_INLINE_VRS
) == 0
25135 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
25136 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
25138 rtx reg
= gen_rtx_REG (V4SImode
, i
);
25139 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25143 /* Restore VRSAVE if we have not done so already. */
25144 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
25146 && TARGET_ALTIVEC_VRSAVE
25147 && info
->vrsave_mask
!= 0
25148 && (DEFAULT_ABI
== ABI_V4
25149 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
25153 reg
= gen_rtx_REG (SImode
, 12);
25154 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25155 info
->vrsave_save_offset
+ frame_off
));
25157 emit_insn (generate_set_vrsave (reg
, info
, 1));
25160 /* If we exit by an out-of-line restore function on ABI_V4 then that
25161 function will deallocate the stack, so we don't need to worry
25162 about the unwinder restoring cr from an invalid stack frame
25164 exit_func
= (!restoring_FPRs_inline
25165 || (!restoring_GPRs_inline
25166 && info
->first_fp_reg_save
== 64));
25168 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
25169 *separate* slots if the routine calls __builtin_eh_return, so
25170 that they can be independently restored by the unwinder. */
25171 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
25173 int i
, cr_off
= info
->ehcr_offset
;
25175 for (i
= 0; i
< 8; i
++)
25176 if (!call_used_regs
[CR0_REGNO
+ i
])
25178 rtx reg
= gen_rtx_REG (SImode
, 0);
25179 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25180 cr_off
+ frame_off
));
25182 insn
= emit_insn (gen_movsi_to_cr_one
25183 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
25185 if (!exit_func
&& flag_shrink_wrap
)
25187 add_reg_note (insn
, REG_CFA_RESTORE
,
25188 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
25190 RTX_FRAME_RELATED_P (insn
) = 1;
25193 cr_off
+= reg_size
;
25197 /* Get the old lr if we saved it. If we are restoring registers
25198 out-of-line, then the out-of-line routines can do this for us. */
25199 if (restore_lr
&& restoring_GPRs_inline
)
25200 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
25202 /* Get the old cr if we saved it. */
25203 if (info
->cr_save_p
)
25205 unsigned cr_save_regno
= 12;
25207 if (!restoring_GPRs_inline
)
25209 /* Ensure we don't use the register used by the out-of-line
25210 gpr register restore below. */
25211 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
25212 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
25213 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
25215 if (gpr_ptr_regno
== 12)
25216 cr_save_regno
= 11;
25217 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
25219 else if (REGNO (frame_reg_rtx
) == 12)
25220 cr_save_regno
= 11;
25222 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
25223 info
->cr_save_offset
+ frame_off
,
25227 /* Set LR here to try to overlap restores below. */
25228 if (restore_lr
&& restoring_GPRs_inline
)
25229 restore_saved_lr (0, exit_func
);
25231 /* Load exception handler data registers, if needed. */
25232 if (crtl
->calls_eh_return
)
25234 unsigned int i
, regno
;
25238 rtx reg
= gen_rtx_REG (reg_mode
, 2);
25239 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25240 frame_off
+ RS6000_TOC_SAVE_SLOT
));
25247 regno
= EH_RETURN_DATA_REGNO (i
);
25248 if (regno
== INVALID_REGNUM
)
25251 /* Note: possible use of r0 here to address SPE regs. */
25252 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
25253 info
->ehrd_offset
+ frame_off
25254 + reg_size
* (int) i
);
25256 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
25260 /* Restore GPRs. This is done as a PARALLEL if we are using
25261 the load-multiple instructions. */
25263 && info
->spe_64bit_regs_used
25264 && info
->first_gp_reg_save
!= 32)
25266 /* Determine whether we can address all of the registers that need
25267 to be saved with an offset from frame_reg_rtx that fits in
25268 the small const field for SPE memory instructions. */
25269 int spe_regs_addressable
25270 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
25271 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
25272 && restoring_GPRs_inline
);
25274 if (!spe_regs_addressable
)
25276 int ool_adjust
= 0;
25277 rtx old_frame_reg_rtx
= frame_reg_rtx
;
25278 /* Make r11 point to the start of the SPE save area. We worried about
25279 not clobbering it when we were saving registers in the prologue.
25280 There's no need to worry here because the static chain is passed
25281 anew to every function. */
25283 if (!restoring_GPRs_inline
)
25284 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
25285 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
25286 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
25287 GEN_INT (info
->spe_gp_save_offset
25290 /* Keep the invariant that frame_reg_rtx + frame_off points
25291 at the top of the stack frame. */
25292 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
25295 if (restoring_GPRs_inline
)
25297 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
25299 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25300 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
25302 rtx offset
, addr
, mem
, reg
;
25304 /* We're doing all this to ensure that the immediate offset
25305 fits into the immediate field of 'evldd'. */
25306 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
25308 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
25309 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
25310 mem
= gen_rtx_MEM (V2SImode
, addr
);
25311 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
25313 emit_move_insn (reg
, mem
);
25317 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
25318 info
->spe_gp_save_offset
+ frame_off
,
25319 info
->lr_save_offset
+ frame_off
,
25321 SAVRES_GPR
| SAVRES_LR
);
25323 else if (!restoring_GPRs_inline
)
25325 /* We are jumping to an out-of-line function. */
25327 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
25328 bool can_use_exit
= end_save
== 0;
25329 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
25332 /* Emit stack reset code if we need it. */
25333 ptr_regno
= ptr_regno_for_savres (sel
);
25334 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
25336 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
25337 else if (end_save
+ frame_off
!= 0)
25338 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
25339 GEN_INT (end_save
+ frame_off
)));
25340 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
25341 emit_move_insn (ptr_reg
, frame_reg_rtx
);
25342 if (REGNO (frame_reg_rtx
) == ptr_regno
)
25343 frame_off
= -end_save
;
25345 if (can_use_exit
&& info
->cr_save_p
)
25346 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
25348 ptr_off
= -end_save
;
25349 rs6000_emit_savres_rtx (info
, ptr_reg
,
25350 info
->gp_save_offset
+ ptr_off
,
25351 info
->lr_save_offset
+ ptr_off
,
25354 else if (using_load_multiple
)
25357 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
25358 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25360 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
25362 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
25363 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25367 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
25368 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
25369 emit_insn (gen_frame_load
25370 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
25372 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
25375 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
25377 /* If the frame pointer was used then we can't delay emitting
25378 a REG_CFA_DEF_CFA note. This must happen on the insn that
25379 restores the frame pointer, r31. We may have already emitted
25380 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
25381 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
25382 be harmless if emitted. */
25383 if (frame_pointer_needed
)
25385 insn
= get_last_insn ();
25386 add_reg_note (insn
, REG_CFA_DEF_CFA
,
25387 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
25388 RTX_FRAME_RELATED_P (insn
) = 1;
25391 /* Set up cfa_restores. We always need these when
25392 shrink-wrapping. If not shrink-wrapping then we only need
25393 the cfa_restore when the stack location is no longer valid.
25394 The cfa_restores must be emitted on or before the insn that
25395 invalidates the stack, and of course must not be emitted
25396 before the insn that actually does the restore. The latter
25397 is why it is a bad idea to emit the cfa_restores as a group
25398 on the last instruction here that actually does a restore:
25399 That insn may be reordered with respect to others doing
25401 if (flag_shrink_wrap
25402 && !restoring_GPRs_inline
25403 && info
->first_fp_reg_save
== 64)
25404 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
25406 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
25407 if (!restoring_GPRs_inline
25408 || using_load_multiple
25409 || rs6000_reg_live_or_pic_offset_p (i
))
25411 rtx reg
= gen_rtx_REG (reg_mode
, i
);
25413 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25417 if (!restoring_GPRs_inline
25418 && info
->first_fp_reg_save
== 64)
25420 /* We are jumping to an out-of-line function. */
25422 emit_cfa_restores (cfa_restores
);
25426 if (restore_lr
&& !restoring_GPRs_inline
)
25428 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
25429 restore_saved_lr (0, exit_func
);
25432 /* Restore fpr's if we need to do it without calling a function. */
25433 if (restoring_FPRs_inline
)
25434 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
25435 if (save_reg_p (info
->first_fp_reg_save
+ i
))
25437 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
25438 ? DFmode
: SFmode
),
25439 info
->first_fp_reg_save
+ i
);
25440 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
25441 info
->fp_save_offset
+ frame_off
+ 8 * i
));
25442 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
25443 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
25446 /* If we saved cr, restore it here. Just those that were used. */
25447 if (info
->cr_save_p
)
25448 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
25450 /* If this is V.4, unwind the stack pointer after all of the loads
25451 have been done, or set up r11 if we are restoring fp out of line. */
25453 if (!restoring_FPRs_inline
)
25455 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
25456 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
25457 ptr_regno
= ptr_regno_for_savres (sel
);
25460 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
25461 if (REGNO (frame_reg_rtx
) == ptr_regno
)
25464 if (insn
&& restoring_FPRs_inline
)
25468 REG_NOTES (insn
) = cfa_restores
;
25469 cfa_restores
= NULL_RTX
;
25471 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
25472 RTX_FRAME_RELATED_P (insn
) = 1;
25475 if (crtl
->calls_eh_return
)
25477 rtx sa
= EH_RETURN_STACKADJ_RTX
;
25478 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
25484 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
25485 if (! restoring_FPRs_inline
)
25487 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
25488 RTVEC_ELT (p
, 0) = ret_rtx
;
25494 /* We can't hang the cfa_restores off a simple return,
25495 since the shrink-wrap code sometimes uses an existing
25496 return. This means there might be a path from
25497 pre-prologue code to this return, and dwarf2cfi code
25498 wants the eh_frame unwinder state to be the same on
25499 all paths to any point. So we need to emit the
25500 cfa_restores before the return. For -m64 we really
25501 don't need epilogue cfa_restores at all, except for
25502 this irritating dwarf2cfi with shrink-wrap
25503 requirement; The stack red-zone means eh_frame info
25504 from the prologue telling the unwinder to restore
25505 from the stack is perfectly good right to the end of
25507 emit_insn (gen_blockage ());
25508 emit_cfa_restores (cfa_restores
);
25509 cfa_restores
= NULL_RTX
;
25511 p
= rtvec_alloc (2);
25512 RTVEC_ELT (p
, 0) = simple_return_rtx
;
25515 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
25516 ? gen_rtx_USE (VOIDmode
,
25517 gen_rtx_REG (Pmode
, LR_REGNO
))
25518 : gen_rtx_CLOBBER (VOIDmode
,
25519 gen_rtx_REG (Pmode
, LR_REGNO
)));
25521 /* If we have to restore more than two FP registers, branch to the
25522 restore function. It will return to our caller. */
25523 if (! restoring_FPRs_inline
)
25529 if (flag_shrink_wrap
)
25530 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
25532 sym
= rs6000_savres_routine_sym (info
,
25533 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
25534 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
25535 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
25536 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
25538 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
25540 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
25542 RTVEC_ELT (p
, i
+ 4)
25543 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
25544 if (flag_shrink_wrap
)
25545 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
25550 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
25556 /* Ensure the cfa_restores are hung off an insn that won't
25557 be reordered above other restores. */
25558 emit_insn (gen_blockage ());
25560 emit_cfa_restores (cfa_restores
);
25564 /* Write function epilogue. */
25567 rs6000_output_function_epilogue (FILE *file
,
25568 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
25571 macho_branch_islands ();
25572 /* Mach-O doesn't support labels at the end of objects, so if
25573 it looks like we might want one, insert a NOP. */
25575 rtx_insn
*insn
= get_last_insn ();
25576 rtx_insn
*deleted_debug_label
= NULL
;
25579 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
25581 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
25582 notes only, instead set their CODE_LABEL_NUMBER to -1,
25583 otherwise there would be code generation differences
25584 in between -g and -g0. */
25585 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
25586 deleted_debug_label
= insn
;
25587 insn
= PREV_INSN (insn
);
25592 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
25593 fputs ("\tnop\n", file
);
25594 else if (deleted_debug_label
)
25595 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
25596 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
25597 CODE_LABEL_NUMBER (insn
) = -1;
25601 /* Output a traceback table here. See /usr/include/sys/debug.h for info
25604 We don't output a traceback table if -finhibit-size-directive was
25605 used. The documentation for -finhibit-size-directive reads
25606 ``don't output a @code{.size} assembler directive, or anything
25607 else that would cause trouble if the function is split in the
25608 middle, and the two halves are placed at locations far apart in
25609 memory.'' The traceback table has this property, since it
25610 includes the offset from the start of the function to the
25611 traceback table itself.
25613 System V.4 Powerpc's (and the embedded ABI derived from it) use a
25614 different traceback table. */
25615 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25616 && ! flag_inhibit_size_directive
25617 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
25619 const char *fname
= NULL
;
25620 const char *language_string
= lang_hooks
.name
;
25621 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
25623 int optional_tbtab
;
25624 rs6000_stack_t
*info
= rs6000_stack_info ();
25626 if (rs6000_traceback
== traceback_full
)
25627 optional_tbtab
= 1;
25628 else if (rs6000_traceback
== traceback_part
)
25629 optional_tbtab
= 0;
25631 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
25633 if (optional_tbtab
)
25635 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
25636 while (*fname
== '.') /* V.4 encodes . in the name */
25639 /* Need label immediately before tbtab, so we can compute
25640 its offset from the function start. */
25641 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
25642 ASM_OUTPUT_LABEL (file
, fname
);
25645 /* The .tbtab pseudo-op can only be used for the first eight
25646 expressions, since it can't handle the possibly variable
25647 length fields that follow. However, if you omit the optional
25648 fields, the assembler outputs zeros for all optional fields
25649 anyways, giving each variable length field is minimum length
25650 (as defined in sys/debug.h). Thus we can not use the .tbtab
25651 pseudo-op at all. */
25653 /* An all-zero word flags the start of the tbtab, for debuggers
25654 that have to find it by searching forward from the entry
25655 point or from the current pc. */
25656 fputs ("\t.long 0\n", file
);
25658 /* Tbtab format type. Use format type 0. */
25659 fputs ("\t.byte 0,", file
);
25661 /* Language type. Unfortunately, there does not seem to be any
25662 official way to discover the language being compiled, so we
25663 use language_string.
25664 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
25665 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
25666 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
25667 either, so for now use 0. */
25669 || ! strcmp (language_string
, "GNU GIMPLE")
25670 || ! strcmp (language_string
, "GNU Go")
25671 || ! strcmp (language_string
, "libgccjit"))
25673 else if (! strcmp (language_string
, "GNU F77")
25674 || lang_GNU_Fortran ())
25676 else if (! strcmp (language_string
, "GNU Pascal"))
25678 else if (! strcmp (language_string
, "GNU Ada"))
25680 else if (lang_GNU_CXX ()
25681 || ! strcmp (language_string
, "GNU Objective-C++"))
25683 else if (! strcmp (language_string
, "GNU Java"))
25685 else if (! strcmp (language_string
, "GNU Objective-C"))
25688 gcc_unreachable ();
25689 fprintf (file
, "%d,", i
);
25691 /* 8 single bit fields: global linkage (not set for C extern linkage,
25692 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
25693 from start of procedure stored in tbtab, internal function, function
25694 has controlled storage, function has no toc, function uses fp,
25695 function logs/aborts fp operations. */
25696 /* Assume that fp operations are used if any fp reg must be saved. */
25697 fprintf (file
, "%d,",
25698 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
25700 /* 6 bitfields: function is interrupt handler, name present in
25701 proc table, function calls alloca, on condition directives
25702 (controls stack walks, 3 bits), saves condition reg, saves
25704 /* The `function calls alloca' bit seems to be set whenever reg 31 is
25705 set up as a frame pointer, even when there is no alloca call. */
25706 fprintf (file
, "%d,",
25707 ((optional_tbtab
<< 6)
25708 | ((optional_tbtab
& frame_pointer_needed
) << 5)
25709 | (info
->cr_save_p
<< 1)
25710 | (info
->lr_save_p
)));
25712 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
25714 fprintf (file
, "%d,",
25715 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
25717 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
25718 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
25720 if (optional_tbtab
)
25722 /* Compute the parameter info from the function decl argument
25725 int next_parm_info_bit
= 31;
25727 for (decl
= DECL_ARGUMENTS (current_function_decl
);
25728 decl
; decl
= DECL_CHAIN (decl
))
25730 rtx parameter
= DECL_INCOMING_RTL (decl
);
25731 machine_mode mode
= GET_MODE (parameter
);
25733 if (GET_CODE (parameter
) == REG
)
25735 if (SCALAR_FLOAT_MODE_P (mode
))
25756 gcc_unreachable ();
25759 /* If only one bit will fit, don't or in this entry. */
25760 if (next_parm_info_bit
> 0)
25761 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
25762 next_parm_info_bit
-= 2;
25766 fixed_parms
+= ((GET_MODE_SIZE (mode
)
25767 + (UNITS_PER_WORD
- 1))
25769 next_parm_info_bit
-= 1;
25775 /* Number of fixed point parameters. */
25776 /* This is actually the number of words of fixed point parameters; thus
25777 an 8 byte struct counts as 2; and thus the maximum value is 8. */
25778 fprintf (file
, "%d,", fixed_parms
);
25780 /* 2 bitfields: number of floating point parameters (7 bits), parameters
25782 /* This is actually the number of fp registers that hold parameters;
25783 and thus the maximum value is 13. */
25784 /* Set parameters on stack bit if parameters are not in their original
25785 registers, regardless of whether they are on the stack? Xlc
25786 seems to set the bit when not optimizing. */
25787 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
25789 if (! optional_tbtab
)
25792 /* Optional fields follow. Some are variable length. */
25794 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
25795 11 double float. */
25796 /* There is an entry for each parameter in a register, in the order that
25797 they occur in the parameter list. Any intervening arguments on the
25798 stack are ignored. If the list overflows a long (max possible length
25799 34 bits) then completely leave off all elements that don't fit. */
25800 /* Only emit this long if there was at least one parameter. */
25801 if (fixed_parms
|| float_parms
)
25802 fprintf (file
, "\t.long %d\n", parm_info
);
25804 /* Offset from start of code to tb table. */
25805 fputs ("\t.long ", file
);
25806 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
25807 RS6000_OUTPUT_BASENAME (file
, fname
);
25809 rs6000_output_function_entry (file
, fname
);
25812 /* Interrupt handler mask. */
25813 /* Omit this long, since we never set the interrupt handler bit
25816 /* Number of CTL (controlled storage) anchors. */
25817 /* Omit this long, since the has_ctl bit is never set above. */
25819 /* Displacement into stack of each CTL anchor. */
25820 /* Omit this list of longs, because there are no CTL anchors. */
25822 /* Length of function name. */
25825 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
25827 /* Function name. */
25828 assemble_string (fname
, strlen (fname
));
25830 /* Register for alloca automatic storage; this is always reg 31.
25831 Only emit this if the alloca bit was set above. */
25832 if (frame_pointer_needed
)
25833 fputs ("\t.byte 31\n", file
);
25835 fputs ("\t.align 2\n", file
);
25839 /* A C compound statement that outputs the assembler code for a thunk
25840 function, used to implement C++ virtual function calls with
25841 multiple inheritance. The thunk acts as a wrapper around a virtual
25842 function, adjusting the implicit object parameter before handing
25843 control off to the real function.
25845 First, emit code to add the integer DELTA to the location that
25846 contains the incoming first argument. Assume that this argument
25847 contains a pointer, and is the one used to pass the `this' pointer
25848 in C++. This is the incoming argument *before* the function
25849 prologue, e.g. `%o0' on a sparc. The addition must preserve the
25850 values of all other incoming arguments.
25852 After the addition, emit code to jump to FUNCTION, which is a
25853 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
25854 not touch the return address. Hence returning from FUNCTION will
25855 return to whoever called the current `thunk'.
25857 The effect must be as if FUNCTION had been called directly with the
25858 adjusted first argument. This macro is responsible for emitting
25859 all of the code for a thunk function; output_function_prologue()
25860 and output_function_epilogue() are not invoked.
25862 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
25863 been extracted from it.) It might possibly be useful on some
25864 targets, but probably not.
25866 If you do not define this macro, the target-independent code in the
25867 C++ frontend will generate a less efficient heavyweight thunk that
25868 calls FUNCTION instead of jumping to it. The generic approach does
25869 not support varargs. */
25872 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
25873 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
25876 rtx this_rtx
, funexp
;
25879 reload_completed
= 1;
25880 epilogue_completed
= 1;
25882 /* Mark the end of the (empty) prologue. */
25883 emit_note (NOTE_INSN_PROLOGUE_END
);
25885 /* Find the "this" pointer. If the function returns a structure,
25886 the structure return pointer is in r3. */
25887 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
25888 this_rtx
= gen_rtx_REG (Pmode
, 4);
25890 this_rtx
= gen_rtx_REG (Pmode
, 3);
25892 /* Apply the constant offset, if required. */
25894 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
25896 /* Apply the offset from the vtable, if required. */
25899 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
25900 rtx tmp
= gen_rtx_REG (Pmode
, 12);
25902 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
25903 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
25905 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
25906 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
25910 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
25912 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
25914 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
25917 /* Generate a tail call to the target function. */
25918 if (!TREE_USED (function
))
25920 assemble_external (function
);
25921 TREE_USED (function
) = 1;
25923 funexp
= XEXP (DECL_RTL (function
), 0);
25924 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
25927 if (MACHOPIC_INDIRECT
)
25928 funexp
= machopic_indirect_call_target (funexp
);
25931 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
25932 generate sibcall RTL explicitly. */
25933 insn
= emit_call_insn (
25934 gen_rtx_PARALLEL (VOIDmode
,
25936 gen_rtx_CALL (VOIDmode
,
25937 funexp
, const0_rtx
),
25938 gen_rtx_USE (VOIDmode
, const0_rtx
),
25939 gen_rtx_USE (VOIDmode
,
25940 gen_rtx_REG (SImode
,
25942 simple_return_rtx
)));
25943 SIBLING_CALL_P (insn
) = 1;
25946 /* Ensure we have a global entry point for the thunk. ??? We could
25947 avoid that if the target routine doesn't need a global entry point,
25948 but we do not know whether this is the case at this point. */
25949 if (DEFAULT_ABI
== ABI_ELFv2
)
25950 cfun
->machine
->r2_setup_needed
= true;
25952 /* Run just enough of rest_of_compilation to get the insns emitted.
25953 There's not really enough bulk here to make other passes such as
25954 instruction scheduling worth while. Note that use_thunk calls
25955 assemble_start_function and assemble_end_function. */
25956 insn
= get_insns ();
25957 shorten_branches (insn
);
25958 final_start_function (insn
, file
, 1);
25959 final (insn
, file
, 1);
25960 final_end_function ();
25962 reload_completed
= 0;
25963 epilogue_completed
= 0;
25966 /* A quick summary of the various types of 'constant-pool tables'
25969 Target Flags Name One table per
25970 AIX (none) AIX TOC object file
25971 AIX -mfull-toc AIX TOC object file
25972 AIX -mminimal-toc AIX minimal TOC translation unit
25973 SVR4/EABI (none) SVR4 SDATA object file
25974 SVR4/EABI -fpic SVR4 pic object file
25975 SVR4/EABI -fPIC SVR4 PIC translation unit
25976 SVR4/EABI -mrelocatable EABI TOC function
25977 SVR4/EABI -maix AIX TOC object file
25978 SVR4/EABI -maix -mminimal-toc
25979 AIX minimal TOC translation unit
25981 Name Reg. Set by entries contains:
25982 made by addrs? fp? sum?
25984 AIX TOC 2 crt0 as Y option option
25985 AIX minimal TOC 30 prolog gcc Y Y option
25986 SVR4 SDATA 13 crt0 gcc N Y N
25987 SVR4 pic 30 prolog ld Y not yet N
25988 SVR4 PIC 30 prolog gcc Y option option
25989 EABI TOC 30 prolog gcc Y option option
25993 /* Hash functions for the hash table. */
25996 rs6000_hash_constant (rtx k
)
25998 enum rtx_code code
= GET_CODE (k
);
25999 machine_mode mode
= GET_MODE (k
);
26000 unsigned result
= (code
<< 3) ^ mode
;
26001 const char *format
;
26004 format
= GET_RTX_FORMAT (code
);
26005 flen
= strlen (format
);
26011 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
26013 case CONST_WIDE_INT
:
26016 flen
= CONST_WIDE_INT_NUNITS (k
);
26017 for (i
= 0; i
< flen
; i
++)
26018 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
26023 if (mode
!= VOIDmode
)
26024 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
26036 for (; fidx
< flen
; fidx
++)
26037 switch (format
[fidx
])
26042 const char *str
= XSTR (k
, fidx
);
26043 len
= strlen (str
);
26044 result
= result
* 613 + len
;
26045 for (i
= 0; i
< len
; i
++)
26046 result
= result
* 613 + (unsigned) str
[i
];
26051 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
26055 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
26058 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
26059 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
26063 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
26064 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
26071 gcc_unreachable ();
26078 toc_hasher::hash (toc_hash_struct
*thc
)
26080 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
26083 /* Compare H1 and H2 for equivalence. */
26086 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
26091 if (h1
->key_mode
!= h2
->key_mode
)
26094 return rtx_equal_p (r1
, r2
);
26097 /* These are the names given by the C++ front-end to vtables, and
26098 vtable-like objects. Ideally, this logic should not be here;
26099 instead, there should be some programmatic way of inquiring as
26100 to whether or not an object is a vtable. */
26102 #define VTABLE_NAME_P(NAME) \
26103 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
26104 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
26105 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
26106 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
26107 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
26109 #ifdef NO_DOLLAR_IN_LABEL
26110 /* Return a GGC-allocated character string translating dollar signs in
26111 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
26114 rs6000_xcoff_strip_dollar (const char *name
)
26120 q
= (const char *) strchr (name
, '$');
26122 if (q
== 0 || q
== name
)
26125 len
= strlen (name
);
26126 strip
= XALLOCAVEC (char, len
+ 1);
26127 strcpy (strip
, name
);
26128 p
= strip
+ (q
- name
);
26132 p
= strchr (p
+ 1, '$');
26135 return ggc_alloc_string (strip
, len
);
26140 rs6000_output_symbol_ref (FILE *file
, rtx x
)
26142 /* Currently C++ toc references to vtables can be emitted before it
26143 is decided whether the vtable is public or private. If this is
26144 the case, then the linker will eventually complain that there is
26145 a reference to an unknown section. Thus, for vtables only,
26146 we emit the TOC reference to reference the symbol and not the
26148 const char *name
= XSTR (x
, 0);
26150 tree decl
= SYMBOL_REF_DECL (x
);
26151 if (decl
/* sync condition with assemble_external () */
26152 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
26153 && (TREE_CODE (decl
) == VAR_DECL
26154 || TREE_CODE (decl
) == FUNCTION_DECL
)
26155 && name
[strlen (name
) - 1] != ']')
26157 name
= concat (name
,
26158 (TREE_CODE (decl
) == FUNCTION_DECL
26159 ? "[DS]" : "[UA]"),
26161 XSTR (x
, 0) = name
;
26164 if (VTABLE_NAME_P (name
))
26166 RS6000_OUTPUT_BASENAME (file
, name
);
26169 assemble_name (file
, name
);
26172 /* Output a TOC entry. We derive the entry name from what is being
26176 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
26179 const char *name
= buf
;
26181 HOST_WIDE_INT offset
= 0;
26183 gcc_assert (!TARGET_NO_TOC
);
26185 /* When the linker won't eliminate them, don't output duplicate
26186 TOC entries (this happens on AIX if there is any kind of TOC,
26187 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
26189 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
26191 struct toc_hash_struct
*h
;
26193 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
26194 time because GGC is not initialized at that point. */
26195 if (toc_hash_table
== NULL
)
26196 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
26198 h
= ggc_alloc
<toc_hash_struct
> ();
26200 h
->key_mode
= mode
;
26201 h
->labelno
= labelno
;
26203 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
26204 if (*found
== NULL
)
26206 else /* This is indeed a duplicate.
26207 Set this label equal to that label. */
26209 fputs ("\t.set ", file
);
26210 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
26211 fprintf (file
, "%d,", labelno
);
26212 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
26213 fprintf (file
, "%d\n", ((*found
)->labelno
));
26216 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
26217 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
26218 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
26220 fputs ("\t.set ", file
);
26221 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
26222 fprintf (file
, "%d,", labelno
);
26223 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
26224 fprintf (file
, "%d\n", ((*found
)->labelno
));
26231 /* If we're going to put a double constant in the TOC, make sure it's
26232 aligned properly when strict alignment is on. */
26233 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
26234 && STRICT_ALIGNMENT
26235 && GET_MODE_BITSIZE (mode
) >= 64
26236 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
26237 ASM_OUTPUT_ALIGN (file
, 3);
26240 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
26242 /* Handle FP constants specially. Note that if we have a minimal
26243 TOC, things we put here aren't actually in the TOC, so we can allow
26245 if (GET_CODE (x
) == CONST_DOUBLE
&&
26246 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
26248 REAL_VALUE_TYPE rv
;
26251 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
26252 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
26253 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
26255 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
26259 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26260 fputs (DOUBLE_INT_ASM_OP
, file
);
26262 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
26263 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
26264 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
26265 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
26266 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
26267 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
26268 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
26269 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
26274 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26275 fputs ("\t.long ", file
);
26277 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
26278 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
26279 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
26280 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
26281 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
26282 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
26286 else if (GET_CODE (x
) == CONST_DOUBLE
&&
26287 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
26289 REAL_VALUE_TYPE rv
;
26292 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
26294 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
26295 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
26297 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
26301 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26302 fputs (DOUBLE_INT_ASM_OP
, file
);
26304 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
26305 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
26306 fprintf (file
, "0x%lx%08lx\n",
26307 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
26308 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
26313 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26314 fputs ("\t.long ", file
);
26316 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
26317 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
26318 fprintf (file
, "0x%lx,0x%lx\n",
26319 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
26323 else if (GET_CODE (x
) == CONST_DOUBLE
&&
26324 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
26326 REAL_VALUE_TYPE rv
;
26329 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
26330 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
26331 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
26333 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
26337 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26338 fputs (DOUBLE_INT_ASM_OP
, file
);
26340 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
26341 if (WORDS_BIG_ENDIAN
)
26342 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
26344 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
26349 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26350 fputs ("\t.long ", file
);
26352 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
26353 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
26357 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
26359 unsigned HOST_WIDE_INT low
;
26360 HOST_WIDE_INT high
;
26362 low
= INTVAL (x
) & 0xffffffff;
26363 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
26365 /* TOC entries are always Pmode-sized, so when big-endian
26366 smaller integer constants in the TOC need to be padded.
26367 (This is still a win over putting the constants in
26368 a separate constant pool, because then we'd have
26369 to have both a TOC entry _and_ the actual constant.)
26371 For a 32-bit target, CONST_INT values are loaded and shifted
26372 entirely within `low' and can be stored in one TOC entry. */
26374 /* It would be easy to make this work, but it doesn't now. */
26375 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
26377 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
26380 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
26381 high
= (HOST_WIDE_INT
) low
>> 32;
26387 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26388 fputs (DOUBLE_INT_ASM_OP
, file
);
26390 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
26391 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
26392 fprintf (file
, "0x%lx%08lx\n",
26393 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
26398 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
26400 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26401 fputs ("\t.long ", file
);
26403 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
26404 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
26405 fprintf (file
, "0x%lx,0x%lx\n",
26406 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
26410 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26411 fputs ("\t.long ", file
);
26413 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
26414 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
26420 if (GET_CODE (x
) == CONST
)
26422 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
26423 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
26425 base
= XEXP (XEXP (x
, 0), 0);
26426 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
26429 switch (GET_CODE (base
))
26432 name
= XSTR (base
, 0);
26436 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
26437 CODE_LABEL_NUMBER (XEXP (base
, 0)));
26441 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
26445 gcc_unreachable ();
26448 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
26449 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
26452 fputs ("\t.tc ", file
);
26453 RS6000_OUTPUT_BASENAME (file
, name
);
26456 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
26458 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
26460 /* Mark large TOC symbols on AIX with [TE] so they are mapped
26461 after other TOC symbols, reducing overflow of small TOC access
26462 to [TC] symbols. */
26463 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
26464 ? "[TE]," : "[TC],", file
);
26467 /* Currently C++ toc references to vtables can be emitted before it
26468 is decided whether the vtable is public or private. If this is
26469 the case, then the linker will eventually complain that there is
26470 a TOC reference to an unknown section. Thus, for vtables only,
26471 we emit the TOC reference to reference the symbol and not the
26473 if (VTABLE_NAME_P (name
))
26475 RS6000_OUTPUT_BASENAME (file
, name
);
26477 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
26478 else if (offset
> 0)
26479 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
26482 output_addr_const (file
, x
);
26485 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
26486 && SYMBOL_REF_TLS_MODEL (base
) != 0)
26488 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
26489 fputs ("@le", file
);
26490 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
26491 fputs ("@ie", file
);
26492 /* Use global-dynamic for local-dynamic. */
26493 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
26494 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
26497 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
26498 fputs ("\t.tc .", file
);
26499 RS6000_OUTPUT_BASENAME (file
, name
);
26500 fputs ("[TC],", file
);
26501 output_addr_const (file
, x
);
26502 fputs ("@m", file
);
26510 /* Output an assembler pseudo-op to write an ASCII string of N characters
26511 starting at P to FILE.
26513 On the RS/6000, we have to do this using the .byte operation and
26514 write out special characters outside the quoted string.
26515 Also, the assembler is broken; very long strings are truncated,
26516 so we must artificially break them up early. */
26519 output_ascii (FILE *file
, const char *p
, int n
)
26522 int i
, count_string
;
26523 const char *for_string
= "\t.byte \"";
26524 const char *for_decimal
= "\t.byte ";
26525 const char *to_close
= NULL
;
26528 for (i
= 0; i
< n
; i
++)
26531 if (c
>= ' ' && c
< 0177)
26534 fputs (for_string
, file
);
26537 /* Write two quotes to get one. */
26545 for_decimal
= "\"\n\t.byte ";
26549 if (count_string
>= 512)
26551 fputs (to_close
, file
);
26553 for_string
= "\t.byte \"";
26554 for_decimal
= "\t.byte ";
26562 fputs (for_decimal
, file
);
26563 fprintf (file
, "%d", c
);
26565 for_string
= "\n\t.byte \"";
26566 for_decimal
= ", ";
26572 /* Now close the string if we have written one. Then end the line. */
26574 fputs (to_close
, file
);
26577 /* Generate a unique section name for FILENAME for a section type
26578 represented by SECTION_DESC. Output goes into BUF.
26580 SECTION_DESC can be any string, as long as it is different for each
26581 possible section type.
26583 We name the section in the same manner as xlc. The name begins with an
26584 underscore followed by the filename (after stripping any leading directory
26585 names) with the last period replaced by the string SECTION_DESC. If
26586 FILENAME does not contain a period, SECTION_DESC is appended to the end of
26590 rs6000_gen_section_name (char **buf
, const char *filename
,
26591 const char *section_desc
)
26593 const char *q
, *after_last_slash
, *last_period
= 0;
26597 after_last_slash
= filename
;
26598 for (q
= filename
; *q
; q
++)
26601 after_last_slash
= q
+ 1;
26602 else if (*q
== '.')
26606 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
26607 *buf
= (char *) xmalloc (len
);
26612 for (q
= after_last_slash
; *q
; q
++)
26614 if (q
== last_period
)
26616 strcpy (p
, section_desc
);
26617 p
+= strlen (section_desc
);
26621 else if (ISALNUM (*q
))
26625 if (last_period
== 0)
26626 strcpy (p
, section_desc
);
26631 /* Emit profile function. */
26634 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
26636 /* Non-standard profiling for kernels, which just saves LR then calls
26637 _mcount without worrying about arg saves. The idea is to change
26638 the function prologue as little as possible as it isn't easy to
26639 account for arg save/restore code added just for _mcount. */
26640 if (TARGET_PROFILE_KERNEL
)
26643 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26645 #ifndef NO_PROFILE_COUNTERS
26646 # define NO_PROFILE_COUNTERS 0
26648 if (NO_PROFILE_COUNTERS
)
26649 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
26650 LCT_NORMAL
, VOIDmode
, 0);
26654 const char *label_name
;
26657 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
26658 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
26659 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
26661 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
26662 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
26665 else if (DEFAULT_ABI
== ABI_DARWIN
)
26667 const char *mcount_name
= RS6000_MCOUNT
;
26668 int caller_addr_regno
= LR_REGNO
;
26670 /* Be conservative and always set this, at least for now. */
26671 crtl
->uses_pic_offset_table
= 1;
26674 /* For PIC code, set up a stub and collect the caller's address
26675 from r0, which is where the prologue puts it. */
26676 if (MACHOPIC_INDIRECT
26677 && crtl
->uses_pic_offset_table
)
26678 caller_addr_regno
= 0;
26680 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
26681 LCT_NORMAL
, VOIDmode
, 1,
26682 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
26686 /* Write function profiler code. */
26689 output_function_profiler (FILE *file
, int labelno
)
26693 switch (DEFAULT_ABI
)
26696 gcc_unreachable ();
26701 warning (0, "no profiling of 64-bit code for this ABI");
26704 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
26705 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
26706 if (NO_PROFILE_COUNTERS
)
26708 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26709 reg_names
[0], reg_names
[1]);
26711 else if (TARGET_SECURE_PLT
&& flag_pic
)
26713 if (TARGET_LINK_STACK
)
26716 get_ppc476_thunk_name (name
);
26717 asm_fprintf (file
, "\tbl %s\n", name
);
26720 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
26721 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26722 reg_names
[0], reg_names
[1]);
26723 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
26724 asm_fprintf (file
, "\taddis %s,%s,",
26725 reg_names
[12], reg_names
[12]);
26726 assemble_name (file
, buf
);
26727 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
26728 assemble_name (file
, buf
);
26729 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
26731 else if (flag_pic
== 1)
26733 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
26734 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26735 reg_names
[0], reg_names
[1]);
26736 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
26737 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
26738 assemble_name (file
, buf
);
26739 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
26741 else if (flag_pic
> 1)
26743 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26744 reg_names
[0], reg_names
[1]);
26745 /* Now, we need to get the address of the label. */
26746 if (TARGET_LINK_STACK
)
26749 get_ppc476_thunk_name (name
);
26750 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
26751 assemble_name (file
, buf
);
26752 fputs ("-.\n1:", file
);
26753 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26754 asm_fprintf (file
, "\taddi %s,%s,4\n",
26755 reg_names
[11], reg_names
[11]);
26759 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
26760 assemble_name (file
, buf
);
26761 fputs ("-.\n1:", file
);
26762 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
26764 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
26765 reg_names
[0], reg_names
[11]);
26766 asm_fprintf (file
, "\tadd %s,%s,%s\n",
26767 reg_names
[0], reg_names
[0], reg_names
[11]);
26771 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
26772 assemble_name (file
, buf
);
26773 fputs ("@ha\n", file
);
26774 asm_fprintf (file
, "\tstw %s,4(%s)\n",
26775 reg_names
[0], reg_names
[1]);
26776 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
26777 assemble_name (file
, buf
);
26778 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
26781 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
26782 fprintf (file
, "\tbl %s%s\n",
26783 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
26789 /* Don't do anything, done in output_profile_hook (). */
26796 /* The following variable value is the last issued insn. */
26798 static rtx last_scheduled_insn
;
26800 /* The following variable helps to balance issuing of load and
26801 store instructions */
26803 static int load_store_pendulum
;
26805 /* Power4 load update and store update instructions are cracked into a
26806 load or store and an integer insn which are executed in the same cycle.
26807 Branches have their own dispatch slot which does not count against the
26808 GCC issue rate, but it changes the program flow so there are no other
26809 instructions to issue in this cycle. */
26812 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
26814 last_scheduled_insn
= insn
;
26815 if (GET_CODE (PATTERN (insn
)) == USE
26816 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26818 cached_can_issue_more
= more
;
26819 return cached_can_issue_more
;
26822 if (insn_terminates_group_p (insn
, current_group
))
26824 cached_can_issue_more
= 0;
26825 return cached_can_issue_more
;
26828 /* If no reservation, but reach here */
26829 if (recog_memoized (insn
) < 0)
26832 if (rs6000_sched_groups
)
26834 if (is_microcoded_insn (insn
))
26835 cached_can_issue_more
= 0;
26836 else if (is_cracked_insn (insn
))
26837 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
26839 cached_can_issue_more
= more
- 1;
26841 return cached_can_issue_more
;
26844 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
26847 cached_can_issue_more
= more
- 1;
26848 return cached_can_issue_more
;
26852 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
26854 int r
= rs6000_variable_issue_1 (insn
, more
);
26856 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
26860 /* Adjust the cost of a scheduling dependency. Return the new cost of
26861 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
26864 rs6000_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
26866 enum attr_type attr_type
;
26868 if (! recog_memoized (insn
))
26871 switch (REG_NOTE_KIND (link
))
26875 /* Data dependency; DEP_INSN writes a register that INSN reads
26876 some cycles later. */
26878 /* Separate a load from a narrower, dependent store. */
26879 if (rs6000_sched_groups
26880 && GET_CODE (PATTERN (insn
)) == SET
26881 && GET_CODE (PATTERN (dep_insn
)) == SET
26882 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
26883 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
26884 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
26885 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
26888 attr_type
= get_attr_type (insn
);
26893 /* Tell the first scheduling pass about the latency between
26894 a mtctr and bctr (and mtlr and br/blr). The first
26895 scheduling pass will not know about this latency since
26896 the mtctr instruction, which has the latency associated
26897 to it, will be generated by reload. */
26900 /* Leave some extra cycles between a compare and its
26901 dependent branch, to inhibit expensive mispredicts. */
26902 if ((rs6000_cpu_attr
== CPU_PPC603
26903 || rs6000_cpu_attr
== CPU_PPC604
26904 || rs6000_cpu_attr
== CPU_PPC604E
26905 || rs6000_cpu_attr
== CPU_PPC620
26906 || rs6000_cpu_attr
== CPU_PPC630
26907 || rs6000_cpu_attr
== CPU_PPC750
26908 || rs6000_cpu_attr
== CPU_PPC7400
26909 || rs6000_cpu_attr
== CPU_PPC7450
26910 || rs6000_cpu_attr
== CPU_PPCE5500
26911 || rs6000_cpu_attr
== CPU_PPCE6500
26912 || rs6000_cpu_attr
== CPU_POWER4
26913 || rs6000_cpu_attr
== CPU_POWER5
26914 || rs6000_cpu_attr
== CPU_POWER7
26915 || rs6000_cpu_attr
== CPU_POWER8
26916 || rs6000_cpu_attr
== CPU_CELL
)
26917 && recog_memoized (dep_insn
)
26918 && (INSN_CODE (dep_insn
) >= 0))
26920 switch (get_attr_type (dep_insn
))
26923 case TYPE_FPCOMPARE
:
26924 case TYPE_CR_LOGICAL
:
26925 case TYPE_DELAYED_CR
:
26929 if (get_attr_dot (dep_insn
) == DOT_YES
)
26934 if (get_attr_dot (dep_insn
) == DOT_YES
26935 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
26946 if ((rs6000_cpu
== PROCESSOR_POWER6
)
26947 && recog_memoized (dep_insn
)
26948 && (INSN_CODE (dep_insn
) >= 0))
26951 if (GET_CODE (PATTERN (insn
)) != SET
)
26952 /* If this happens, we have to extend this to schedule
26953 optimally. Return default for now. */
26956 /* Adjust the cost for the case where the value written
26957 by a fixed point operation is used as the address
26958 gen value on a store. */
26959 switch (get_attr_type (dep_insn
))
26964 if (! store_data_bypass_p (dep_insn
, insn
))
26965 return get_attr_sign_extend (dep_insn
)
26966 == SIGN_EXTEND_YES
? 6 : 4;
26971 if (! store_data_bypass_p (dep_insn
, insn
))
26972 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
26982 if (! store_data_bypass_p (dep_insn
, insn
))
26990 if (get_attr_update (dep_insn
) == UPDATE_YES
26991 && ! store_data_bypass_p (dep_insn
, insn
))
26997 if (! store_data_bypass_p (dep_insn
, insn
))
27003 if (! store_data_bypass_p (dep_insn
, insn
))
27004 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
27014 if ((rs6000_cpu
== PROCESSOR_POWER6
)
27015 && recog_memoized (dep_insn
)
27016 && (INSN_CODE (dep_insn
) >= 0))
27019 /* Adjust the cost for the case where the value written
27020 by a fixed point instruction is used within the address
27021 gen portion of a subsequent load(u)(x) */
27022 switch (get_attr_type (dep_insn
))
27027 if (set_to_load_agen (dep_insn
, insn
))
27028 return get_attr_sign_extend (dep_insn
)
27029 == SIGN_EXTEND_YES
? 6 : 4;
27034 if (set_to_load_agen (dep_insn
, insn
))
27035 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
27045 if (set_to_load_agen (dep_insn
, insn
))
27053 if (get_attr_update (dep_insn
) == UPDATE_YES
27054 && set_to_load_agen (dep_insn
, insn
))
27060 if (set_to_load_agen (dep_insn
, insn
))
27066 if (set_to_load_agen (dep_insn
, insn
))
27067 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
27077 if ((rs6000_cpu
== PROCESSOR_POWER6
)
27078 && get_attr_update (insn
) == UPDATE_NO
27079 && recog_memoized (dep_insn
)
27080 && (INSN_CODE (dep_insn
) >= 0)
27081 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
27088 /* Fall out to return default cost. */
27092 case REG_DEP_OUTPUT
:
27093 /* Output dependency; DEP_INSN writes a register that INSN writes some
27095 if ((rs6000_cpu
== PROCESSOR_POWER6
)
27096 && recog_memoized (dep_insn
)
27097 && (INSN_CODE (dep_insn
) >= 0))
27099 attr_type
= get_attr_type (insn
);
27104 if (get_attr_type (dep_insn
) == TYPE_FP
)
27108 if (get_attr_update (insn
) == UPDATE_NO
27109 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
27117 /* Anti dependency; DEP_INSN reads a register that INSN writes some
27122 gcc_unreachable ();
27128 /* Debug version of rs6000_adjust_cost. */
27131 rs6000_debug_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
,
27134 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
27140 switch (REG_NOTE_KIND (link
))
27142 default: dep
= "unknown depencency"; break;
27143 case REG_DEP_TRUE
: dep
= "data dependency"; break;
27144 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
27145 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
27149 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
27150 "%s, insn:\n", ret
, cost
, dep
);
27158 /* The function returns a true if INSN is microcoded.
27159 Return false otherwise. */
27162 is_microcoded_insn (rtx_insn
*insn
)
27164 if (!insn
|| !NONDEBUG_INSN_P (insn
)
27165 || GET_CODE (PATTERN (insn
)) == USE
27166 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27169 if (rs6000_cpu_attr
== CPU_CELL
)
27170 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
27172 if (rs6000_sched_groups
27173 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
27175 enum attr_type type
= get_attr_type (insn
);
27176 if ((type
== TYPE_LOAD
27177 && get_attr_update (insn
) == UPDATE_YES
27178 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
27179 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
27180 && get_attr_update (insn
) == UPDATE_YES
27181 && get_attr_indexed (insn
) == INDEXED_YES
)
27182 || type
== TYPE_MFCR
)
27189 /* The function returns true if INSN is cracked into 2 instructions
27190 by the processor (and therefore occupies 2 issue slots). */
27193 is_cracked_insn (rtx_insn
*insn
)
27195 if (!insn
|| !NONDEBUG_INSN_P (insn
)
27196 || GET_CODE (PATTERN (insn
)) == USE
27197 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27200 if (rs6000_sched_groups
27201 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
27203 enum attr_type type
= get_attr_type (insn
);
27204 if ((type
== TYPE_LOAD
27205 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
27206 && get_attr_update (insn
) == UPDATE_NO
)
27207 || (type
== TYPE_LOAD
27208 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
27209 && get_attr_update (insn
) == UPDATE_YES
27210 && get_attr_indexed (insn
) == INDEXED_NO
)
27211 || (type
== TYPE_STORE
27212 && get_attr_update (insn
) == UPDATE_YES
27213 && get_attr_indexed (insn
) == INDEXED_NO
)
27214 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
27215 && get_attr_update (insn
) == UPDATE_YES
)
27216 || type
== TYPE_DELAYED_CR
27217 || (type
== TYPE_EXTS
27218 && get_attr_dot (insn
) == DOT_YES
)
27219 || (type
== TYPE_SHIFT
27220 && get_attr_dot (insn
) == DOT_YES
27221 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
27222 || (type
== TYPE_MUL
27223 && get_attr_dot (insn
) == DOT_YES
)
27224 || type
== TYPE_DIV
27225 || (type
== TYPE_INSERT
27226 && get_attr_size (insn
) == SIZE_32
))
27233 /* The function returns true if INSN can be issued only from
27234 the branch slot. */
27237 is_branch_slot_insn (rtx_insn
*insn
)
27239 if (!insn
|| !NONDEBUG_INSN_P (insn
)
27240 || GET_CODE (PATTERN (insn
)) == USE
27241 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27244 if (rs6000_sched_groups
)
27246 enum attr_type type
= get_attr_type (insn
);
27247 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
27255 /* The function returns true if out_inst sets a value that is
27256 used in the address generation computation of in_insn */
27258 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
27260 rtx out_set
, in_set
;
27262 /* For performance reasons, only handle the simple case where
27263 both loads are a single_set. */
27264 out_set
= single_set (out_insn
);
27267 in_set
= single_set (in_insn
);
27269 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
27275 /* Try to determine base/offset/size parts of the given MEM.
27276 Return true if successful, false if all the values couldn't
27279 This function only looks for REG or REG+CONST address forms.
27280 REG+REG address form will return false. */
27283 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
27284 HOST_WIDE_INT
*size
)
27287 if MEM_SIZE_KNOWN_P (mem
)
27288 *size
= MEM_SIZE (mem
);
27292 addr_rtx
= (XEXP (mem
, 0));
27293 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
27294 addr_rtx
= XEXP (addr_rtx
, 1);
27297 while (GET_CODE (addr_rtx
) == PLUS
27298 && CONST_INT_P (XEXP (addr_rtx
, 1)))
27300 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
27301 addr_rtx
= XEXP (addr_rtx
, 0);
27303 if (!REG_P (addr_rtx
))
27310 /* The function returns true if the target storage location of
27311 mem1 is adjacent to the target storage location of mem2 */
27312 /* Return 1 if memory locations are adjacent. */
27315 adjacent_mem_locations (rtx mem1
, rtx mem2
)
27318 HOST_WIDE_INT off1
, size1
, off2
, size2
;
27320 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
27321 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
27322 return ((REGNO (reg1
) == REGNO (reg2
))
27323 && ((off1
+ size1
== off2
)
27324 || (off2
+ size2
== off1
)));
27329 /* This function returns true if it can be determined that the two MEM
27330 locations overlap by at least 1 byte based on base reg/offset/size. */
27333 mem_locations_overlap (rtx mem1
, rtx mem2
)
27336 HOST_WIDE_INT off1
, size1
, off2
, size2
;
27338 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
27339 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
27340 return ((REGNO (reg1
) == REGNO (reg2
))
27341 && (((off1
<= off2
) && (off1
+ size1
> off2
))
27342 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
27347 /* A C statement (sans semicolon) to update the integer scheduling
27348 priority INSN_PRIORITY (INSN). Increase the priority to execute the
27349 INSN earlier, reduce the priority to execute INSN later. Do not
27350 define this macro if you do not need to adjust the scheduling
27351 priorities of insns. */
27354 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
27356 rtx load_mem
, str_mem
;
27357 /* On machines (like the 750) which have asymmetric integer units,
27358 where one integer unit can do multiply and divides and the other
27359 can't, reduce the priority of multiply/divide so it is scheduled
27360 before other integer operations. */
27363 if (! INSN_P (insn
))
27366 if (GET_CODE (PATTERN (insn
)) == USE
)
27369 switch (rs6000_cpu_attr
) {
27371 switch (get_attr_type (insn
))
27378 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
27379 priority
, priority
);
27380 if (priority
>= 0 && priority
< 0x01000000)
27387 if (insn_must_be_first_in_group (insn
)
27388 && reload_completed
27389 && current_sched_info
->sched_max_insns_priority
27390 && rs6000_sched_restricted_insns_priority
)
27393 /* Prioritize insns that can be dispatched only in the first
27395 if (rs6000_sched_restricted_insns_priority
== 1)
27396 /* Attach highest priority to insn. This means that in
27397 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
27398 precede 'priority' (critical path) considerations. */
27399 return current_sched_info
->sched_max_insns_priority
;
27400 else if (rs6000_sched_restricted_insns_priority
== 2)
27401 /* Increase priority of insn by a minimal amount. This means that in
27402 haifa-sched.c:ready_sort(), only 'priority' (critical path)
27403 considerations precede dispatch-slot restriction considerations. */
27404 return (priority
+ 1);
27407 if (rs6000_cpu
== PROCESSOR_POWER6
27408 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
27409 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
27410 /* Attach highest priority to insn if the scheduler has just issued two
27411 stores and this instruction is a load, or two loads and this instruction
27412 is a store. Power6 wants loads and stores scheduled alternately
27414 return current_sched_info
->sched_max_insns_priority
;
27419 /* Return true if the instruction is nonpipelined on the Cell. */
27421 is_nonpipeline_insn (rtx_insn
*insn
)
27423 enum attr_type type
;
27424 if (!insn
|| !NONDEBUG_INSN_P (insn
)
27425 || GET_CODE (PATTERN (insn
)) == USE
27426 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
27429 type
= get_attr_type (insn
);
27430 if (type
== TYPE_MUL
27431 || type
== TYPE_DIV
27432 || type
== TYPE_SDIV
27433 || type
== TYPE_DDIV
27434 || type
== TYPE_SSQRT
27435 || type
== TYPE_DSQRT
27436 || type
== TYPE_MFCR
27437 || type
== TYPE_MFCRF
27438 || type
== TYPE_MFJMPR
)
27446 /* Return how many instructions the machine can issue per cycle. */
27449 rs6000_issue_rate (void)
27451 /* Unless scheduling for register pressure, use issue rate of 1 for
27452 first scheduling pass to decrease degradation. */
27453 if (!reload_completed
&& !flag_sched_pressure
)
27456 switch (rs6000_cpu_attr
) {
27458 case CPU_PPC601
: /* ? */
27468 case CPU_PPCE300C2
:
27469 case CPU_PPCE300C3
:
27470 case CPU_PPCE500MC
:
27471 case CPU_PPCE500MC64
:
27494 /* Return how many instructions to look ahead for better insn
27498 rs6000_use_sched_lookahead (void)
27500 switch (rs6000_cpu_attr
)
27507 return (reload_completed
? 8 : 0);
27514 /* We are choosing insn from the ready queue. Return zero if INSN can be
27517 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
27519 if (ready_index
== 0)
27522 if (rs6000_cpu_attr
!= CPU_CELL
)
27525 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
27527 if (!reload_completed
27528 || is_nonpipeline_insn (insn
)
27529 || is_microcoded_insn (insn
))
27535 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
27536 and return true. */
27539 find_mem_ref (rtx pat
, rtx
*mem_ref
)
27544 /* stack_tie does not produce any real memory traffic. */
27545 if (tie_operand (pat
, VOIDmode
))
27548 if (GET_CODE (pat
) == MEM
)
27554 /* Recursively process the pattern. */
27555 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
27557 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
27561 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
27564 else if (fmt
[i
] == 'E')
27565 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
27567 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
27575 /* Determine if PAT is a PATTERN of a load insn. */
27578 is_load_insn1 (rtx pat
, rtx
*load_mem
)
27580 if (!pat
|| pat
== NULL_RTX
)
27583 if (GET_CODE (pat
) == SET
)
27584 return find_mem_ref (SET_SRC (pat
), load_mem
);
27586 if (GET_CODE (pat
) == PARALLEL
)
27590 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
27591 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
27598 /* Determine if INSN loads from memory. */
27601 is_load_insn (rtx insn
, rtx
*load_mem
)
27603 if (!insn
|| !INSN_P (insn
))
27609 return is_load_insn1 (PATTERN (insn
), load_mem
);
27612 /* Determine if PAT is a PATTERN of a store insn. */
27615 is_store_insn1 (rtx pat
, rtx
*str_mem
)
27617 if (!pat
|| pat
== NULL_RTX
)
27620 if (GET_CODE (pat
) == SET
)
27621 return find_mem_ref (SET_DEST (pat
), str_mem
);
27623 if (GET_CODE (pat
) == PARALLEL
)
27627 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
27628 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
27635 /* Determine if INSN stores to memory. */
27638 is_store_insn (rtx insn
, rtx
*str_mem
)
27640 if (!insn
|| !INSN_P (insn
))
27643 return is_store_insn1 (PATTERN (insn
), str_mem
);
27646 /* Returns whether the dependence between INSN and NEXT is considered
27647 costly by the given target. */
27650 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
27654 rtx load_mem
, str_mem
;
27656 /* If the flag is not enabled - no dependence is considered costly;
27657 allow all dependent insns in the same group.
27658 This is the most aggressive option. */
27659 if (rs6000_sched_costly_dep
== no_dep_costly
)
27662 /* If the flag is set to 1 - a dependence is always considered costly;
27663 do not allow dependent instructions in the same group.
27664 This is the most conservative option. */
27665 if (rs6000_sched_costly_dep
== all_deps_costly
)
27668 insn
= DEP_PRO (dep
);
27669 next
= DEP_CON (dep
);
27671 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
27672 && is_load_insn (next
, &load_mem
)
27673 && is_store_insn (insn
, &str_mem
))
27674 /* Prevent load after store in the same group. */
27677 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
27678 && is_load_insn (next
, &load_mem
)
27679 && is_store_insn (insn
, &str_mem
)
27680 && DEP_TYPE (dep
) == REG_DEP_TRUE
27681 && mem_locations_overlap(str_mem
, load_mem
))
27682 /* Prevent load after store in the same group if it is a true
27686 /* The flag is set to X; dependences with latency >= X are considered costly,
27687 and will not be scheduled in the same group. */
27688 if (rs6000_sched_costly_dep
<= max_dep_latency
27689 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
27695 /* Return the next insn after INSN that is found before TAIL is reached,
27696 skipping any "non-active" insns - insns that will not actually occupy
27697 an issue slot. Return NULL_RTX if such an insn is not found. */
27700 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
27702 if (insn
== NULL_RTX
|| insn
== tail
)
27707 insn
= NEXT_INSN (insn
);
27708 if (insn
== NULL_RTX
|| insn
== tail
)
27712 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
27713 || (NONJUMP_INSN_P (insn
)
27714 && GET_CODE (PATTERN (insn
)) != USE
27715 && GET_CODE (PATTERN (insn
)) != CLOBBER
27716 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
27722 /* We are about to begin issuing insns for this clock cycle. */
27725 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
27726 rtx_insn
**ready ATTRIBUTE_UNUSED
,
27727 int *pn_ready ATTRIBUTE_UNUSED
,
27728 int clock_var ATTRIBUTE_UNUSED
)
27730 int n_ready
= *pn_ready
;
27733 fprintf (dump
, "// rs6000_sched_reorder :\n");
27735 /* Reorder the ready list, if the second to last ready insn
27736 is a nonepipeline insn. */
27737 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
27739 if (is_nonpipeline_insn (ready
[n_ready
- 1])
27740 && (recog_memoized (ready
[n_ready
- 2]) > 0))
27741 /* Simply swap first two insns. */
27742 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
27745 if (rs6000_cpu
== PROCESSOR_POWER6
)
27746 load_store_pendulum
= 0;
27748 return rs6000_issue_rate ();
27751 /* Like rs6000_sched_reorder, but called after issuing each insn. */
27754 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
27755 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
27758 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
27760 /* For Power6, we need to handle some special cases to try and keep the
27761 store queue from overflowing and triggering expensive flushes.
27763 This code monitors how load and store instructions are being issued
27764 and skews the ready list one way or the other to increase the likelihood
27765 that a desired instruction is issued at the proper time.
27767 A couple of things are done. First, we maintain a "load_store_pendulum"
27768 to track the current state of load/store issue.
27770 - If the pendulum is at zero, then no loads or stores have been
27771 issued in the current cycle so we do nothing.
27773 - If the pendulum is 1, then a single load has been issued in this
27774 cycle and we attempt to locate another load in the ready list to
27777 - If the pendulum is -2, then two stores have already been
27778 issued in this cycle, so we increase the priority of the first load
27779 in the ready list to increase it's likelihood of being chosen first
27782 - If the pendulum is -1, then a single store has been issued in this
27783 cycle and we attempt to locate another store in the ready list to
27784 issue with it, preferring a store to an adjacent memory location to
27785 facilitate store pairing in the store queue.
27787 - If the pendulum is 2, then two loads have already been
27788 issued in this cycle, so we increase the priority of the first store
27789 in the ready list to increase it's likelihood of being chosen first
27792 - If the pendulum < -2 or > 2, then do nothing.
27794 Note: This code covers the most common scenarios. There exist non
27795 load/store instructions which make use of the LSU and which
27796 would need to be accounted for to strictly model the behavior
27797 of the machine. Those instructions are currently unaccounted
27798 for to help minimize compile time overhead of this code.
27800 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
27805 rtx load_mem
, str_mem
;
27807 if (is_store_insn (last_scheduled_insn
, &str_mem
))
27808 /* Issuing a store, swing the load_store_pendulum to the left */
27809 load_store_pendulum
--;
27810 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
27811 /* Issuing a load, swing the load_store_pendulum to the right */
27812 load_store_pendulum
++;
27814 return cached_can_issue_more
;
27816 /* If the pendulum is balanced, or there is only one instruction on
27817 the ready list, then all is well, so return. */
27818 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
27819 return cached_can_issue_more
;
27821 if (load_store_pendulum
== 1)
27823 /* A load has been issued in this cycle. Scan the ready list
27824 for another load to issue with it */
27829 if (is_load_insn (ready
[pos
], &load_mem
))
27831 /* Found a load. Move it to the head of the ready list,
27832 and adjust it's priority so that it is more likely to
27835 for (i
=pos
; i
<*pn_ready
-1; i
++)
27836 ready
[i
] = ready
[i
+ 1];
27837 ready
[*pn_ready
-1] = tmp
;
27839 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27840 INSN_PRIORITY (tmp
)++;
27846 else if (load_store_pendulum
== -2)
27848 /* Two stores have been issued in this cycle. Increase the
27849 priority of the first load in the ready list to favor it for
27850 issuing in the next cycle. */
27855 if (is_load_insn (ready
[pos
], &load_mem
)
27857 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27859 INSN_PRIORITY (ready
[pos
])++;
27861 /* Adjust the pendulum to account for the fact that a load
27862 was found and increased in priority. This is to prevent
27863 increasing the priority of multiple loads */
27864 load_store_pendulum
--;
27871 else if (load_store_pendulum
== -1)
27873 /* A store has been issued in this cycle. Scan the ready list for
27874 another store to issue with it, preferring a store to an adjacent
27876 int first_store_pos
= -1;
27882 if (is_store_insn (ready
[pos
], &str_mem
))
27885 /* Maintain the index of the first store found on the
27887 if (first_store_pos
== -1)
27888 first_store_pos
= pos
;
27890 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
27891 && adjacent_mem_locations (str_mem
, str_mem2
))
27893 /* Found an adjacent store. Move it to the head of the
27894 ready list, and adjust it's priority so that it is
27895 more likely to stay there */
27897 for (i
=pos
; i
<*pn_ready
-1; i
++)
27898 ready
[i
] = ready
[i
+ 1];
27899 ready
[*pn_ready
-1] = tmp
;
27901 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27902 INSN_PRIORITY (tmp
)++;
27904 first_store_pos
= -1;
27912 if (first_store_pos
>= 0)
27914 /* An adjacent store wasn't found, but a non-adjacent store was,
27915 so move the non-adjacent store to the front of the ready
27916 list, and adjust its priority so that it is more likely to
27918 tmp
= ready
[first_store_pos
];
27919 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
27920 ready
[i
] = ready
[i
+ 1];
27921 ready
[*pn_ready
-1] = tmp
;
27922 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
27923 INSN_PRIORITY (tmp
)++;
27926 else if (load_store_pendulum
== 2)
27928 /* Two loads have been issued in this cycle. Increase the priority
27929 of the first store in the ready list to favor it for issuing in
27935 if (is_store_insn (ready
[pos
], &str_mem
)
27937 && INSN_PRIORITY_KNOWN (ready
[pos
]))
27939 INSN_PRIORITY (ready
[pos
])++;
27941 /* Adjust the pendulum to account for the fact that a store
27942 was found and increased in priority. This is to prevent
27943 increasing the priority of multiple stores */
27944 load_store_pendulum
++;
27953 return cached_can_issue_more
;
27956 /* Return whether the presence of INSN causes a dispatch group termination
27957 of group WHICH_GROUP.
27959 If WHICH_GROUP == current_group, this function will return true if INSN
27960 causes the termination of the current group (i.e, the dispatch group to
27961 which INSN belongs). This means that INSN will be the last insn in the
27962 group it belongs to.
27964 If WHICH_GROUP == previous_group, this function will return true if INSN
27965 causes the termination of the previous group (i.e, the dispatch group that
27966 precedes the group to which INSN belongs). This means that INSN will be
27967 the first insn in the group it belongs to). */
27970 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
27977 first
= insn_must_be_first_in_group (insn
);
27978 last
= insn_must_be_last_in_group (insn
);
27983 if (which_group
== current_group
)
27985 else if (which_group
== previous_group
)
27993 insn_must_be_first_in_group (rtx_insn
*insn
)
27995 enum attr_type type
;
27999 || DEBUG_INSN_P (insn
)
28000 || GET_CODE (PATTERN (insn
)) == USE
28001 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28004 switch (rs6000_cpu
)
28006 case PROCESSOR_POWER5
:
28007 if (is_cracked_insn (insn
))
28009 case PROCESSOR_POWER4
:
28010 if (is_microcoded_insn (insn
))
28013 if (!rs6000_sched_groups
)
28016 type
= get_attr_type (insn
);
28023 case TYPE_DELAYED_CR
:
28024 case TYPE_CR_LOGICAL
:
28037 case PROCESSOR_POWER6
:
28038 type
= get_attr_type (insn
);
28047 case TYPE_FPCOMPARE
:
28058 if (get_attr_dot (insn
) == DOT_NO
28059 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
28064 if (get_attr_size (insn
) == SIZE_32
)
28072 if (get_attr_update (insn
) == UPDATE_YES
)
28080 case PROCESSOR_POWER7
:
28081 type
= get_attr_type (insn
);
28085 case TYPE_CR_LOGICAL
:
28099 if (get_attr_dot (insn
) == DOT_YES
)
28104 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
28105 || get_attr_update (insn
) == UPDATE_YES
)
28112 if (get_attr_update (insn
) == UPDATE_YES
)
28120 case PROCESSOR_POWER8
:
28121 type
= get_attr_type (insn
);
28125 case TYPE_CR_LOGICAL
:
28126 case TYPE_DELAYED_CR
:
28134 case TYPE_VECSTORE
:
28141 if (get_attr_dot (insn
) == DOT_YES
)
28146 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
28147 || get_attr_update (insn
) == UPDATE_YES
)
28152 if (get_attr_update (insn
) == UPDATE_YES
28153 && get_attr_indexed (insn
) == INDEXED_YES
)
28169 insn_must_be_last_in_group (rtx_insn
*insn
)
28171 enum attr_type type
;
28175 || DEBUG_INSN_P (insn
)
28176 || GET_CODE (PATTERN (insn
)) == USE
28177 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
28180 switch (rs6000_cpu
) {
28181 case PROCESSOR_POWER4
:
28182 case PROCESSOR_POWER5
:
28183 if (is_microcoded_insn (insn
))
28186 if (is_branch_slot_insn (insn
))
28190 case PROCESSOR_POWER6
:
28191 type
= get_attr_type (insn
);
28199 case TYPE_FPCOMPARE
:
28210 if (get_attr_dot (insn
) == DOT_NO
28211 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
28216 if (get_attr_size (insn
) == SIZE_32
)
28224 case PROCESSOR_POWER7
:
28225 type
= get_attr_type (insn
);
28235 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
28236 && get_attr_update (insn
) == UPDATE_YES
)
28241 if (get_attr_update (insn
) == UPDATE_YES
28242 && get_attr_indexed (insn
) == INDEXED_YES
)
28250 case PROCESSOR_POWER8
:
28251 type
= get_attr_type (insn
);
28263 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
28264 && get_attr_update (insn
) == UPDATE_YES
)
28269 if (get_attr_update (insn
) == UPDATE_YES
28270 && get_attr_indexed (insn
) == INDEXED_YES
)
28285 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
28286 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
28289 is_costly_group (rtx
*group_insns
, rtx next_insn
)
28292 int issue_rate
= rs6000_issue_rate ();
28294 for (i
= 0; i
< issue_rate
; i
++)
28296 sd_iterator_def sd_it
;
28298 rtx insn
= group_insns
[i
];
28303 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
28305 rtx next
= DEP_CON (dep
);
28307 if (next
== next_insn
28308 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
28316 /* Utility of the function redefine_groups.
28317 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
28318 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
28319 to keep it "far" (in a separate group) from GROUP_INSNS, following
28320 one of the following schemes, depending on the value of the flag
28321 -minsert_sched_nops = X:
28322 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
28323 in order to force NEXT_INSN into a separate group.
28324 (2) X < sched_finish_regroup_exact: insert exactly X nops.
28325 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
28326 insertion (has a group just ended, how many vacant issue slots remain in the
28327 last group, and how many dispatch groups were encountered so far). */
28330 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
28331 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
28336 int issue_rate
= rs6000_issue_rate ();
28337 bool end
= *group_end
;
28340 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
28341 return can_issue_more
;
28343 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
28344 return can_issue_more
;
28346 force
= is_costly_group (group_insns
, next_insn
);
28348 return can_issue_more
;
28350 if (sched_verbose
> 6)
28351 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
28352 *group_count
,can_issue_more
);
28354 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
28357 can_issue_more
= 0;
28359 /* Since only a branch can be issued in the last issue_slot, it is
28360 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
28361 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
28362 in this case the last nop will start a new group and the branch
28363 will be forced to the new group. */
28364 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
28367 /* Do we have a special group ending nop? */
28368 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
28369 || rs6000_cpu_attr
== CPU_POWER8
)
28371 nop
= gen_group_ending_nop ();
28372 emit_insn_before (nop
, next_insn
);
28373 can_issue_more
= 0;
28376 while (can_issue_more
> 0)
28379 emit_insn_before (nop
, next_insn
);
28387 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
28389 int n_nops
= rs6000_sched_insert_nops
;
28391 /* Nops can't be issued from the branch slot, so the effective
28392 issue_rate for nops is 'issue_rate - 1'. */
28393 if (can_issue_more
== 0)
28394 can_issue_more
= issue_rate
;
28396 if (can_issue_more
== 0)
28398 can_issue_more
= issue_rate
- 1;
28401 for (i
= 0; i
< issue_rate
; i
++)
28403 group_insns
[i
] = 0;
28410 emit_insn_before (nop
, next_insn
);
28411 if (can_issue_more
== issue_rate
- 1) /* new group begins */
28414 if (can_issue_more
== 0)
28416 can_issue_more
= issue_rate
- 1;
28419 for (i
= 0; i
< issue_rate
; i
++)
28421 group_insns
[i
] = 0;
28427 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
28430 /* Is next_insn going to start a new group? */
28433 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
28434 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
28435 || (can_issue_more
< issue_rate
&&
28436 insn_terminates_group_p (next_insn
, previous_group
)));
28437 if (*group_end
&& end
)
28440 if (sched_verbose
> 6)
28441 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
28442 *group_count
, can_issue_more
);
28443 return can_issue_more
;
28446 return can_issue_more
;
28449 /* This function tries to synch the dispatch groups that the compiler "sees"
28450 with the dispatch groups that the processor dispatcher is expected to
28451 form in practice. It tries to achieve this synchronization by forcing the
28452 estimated processor grouping on the compiler (as opposed to the function
28453 'pad_goups' which tries to force the scheduler's grouping on the processor).
28455 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
28456 examines the (estimated) dispatch groups that will be formed by the processor
28457 dispatcher. It marks these group boundaries to reflect the estimated
28458 processor grouping, overriding the grouping that the scheduler had marked.
28459 Depending on the value of the flag '-minsert-sched-nops' this function can
28460 force certain insns into separate groups or force a certain distance between
28461 them by inserting nops, for example, if there exists a "costly dependence"
28464 The function estimates the group boundaries that the processor will form as
28465 follows: It keeps track of how many vacant issue slots are available after
28466 each insn. A subsequent insn will start a new group if one of the following
28468 - no more vacant issue slots remain in the current dispatch group.
28469 - only the last issue slot, which is the branch slot, is vacant, but the next
28470 insn is not a branch.
28471 - only the last 2 or less issue slots, including the branch slot, are vacant,
28472 which means that a cracked insn (which occupies two issue slots) can't be
28473 issued in this group.
28474 - less than 'issue_rate' slots are vacant, and the next insn always needs to
28475 start a new group. */
28478 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
28481 rtx_insn
*insn
, *next_insn
;
28483 int can_issue_more
;
28486 int group_count
= 0;
28490 issue_rate
= rs6000_issue_rate ();
28491 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
28492 for (i
= 0; i
< issue_rate
; i
++)
28494 group_insns
[i
] = 0;
28496 can_issue_more
= issue_rate
;
28498 insn
= get_next_active_insn (prev_head_insn
, tail
);
28501 while (insn
!= NULL_RTX
)
28503 slot
= (issue_rate
- can_issue_more
);
28504 group_insns
[slot
] = insn
;
28506 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
28507 if (insn_terminates_group_p (insn
, current_group
))
28508 can_issue_more
= 0;
28510 next_insn
= get_next_active_insn (insn
, tail
);
28511 if (next_insn
== NULL_RTX
)
28512 return group_count
+ 1;
28514 /* Is next_insn going to start a new group? */
28516 = (can_issue_more
== 0
28517 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
28518 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
28519 || (can_issue_more
< issue_rate
&&
28520 insn_terminates_group_p (next_insn
, previous_group
)));
28522 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
28523 next_insn
, &group_end
, can_issue_more
,
28529 can_issue_more
= 0;
28530 for (i
= 0; i
< issue_rate
; i
++)
28532 group_insns
[i
] = 0;
28536 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
28537 PUT_MODE (next_insn
, VOIDmode
);
28538 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
28539 PUT_MODE (next_insn
, TImode
);
28542 if (can_issue_more
== 0)
28543 can_issue_more
= issue_rate
;
28546 return group_count
;
28549 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
28550 dispatch group boundaries that the scheduler had marked. Pad with nops
28551 any dispatch groups which have vacant issue slots, in order to force the
28552 scheduler's grouping on the processor dispatcher. The function
28553 returns the number of dispatch groups found. */
28556 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
28559 rtx_insn
*insn
, *next_insn
;
28562 int can_issue_more
;
28564 int group_count
= 0;
28566 /* Initialize issue_rate. */
28567 issue_rate
= rs6000_issue_rate ();
28568 can_issue_more
= issue_rate
;
28570 insn
= get_next_active_insn (prev_head_insn
, tail
);
28571 next_insn
= get_next_active_insn (insn
, tail
);
28573 while (insn
!= NULL_RTX
)
28576 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
28578 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
28580 if (next_insn
== NULL_RTX
)
28585 /* If the scheduler had marked group termination at this location
28586 (between insn and next_insn), and neither insn nor next_insn will
28587 force group termination, pad the group with nops to force group
28590 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
28591 && !insn_terminates_group_p (insn
, current_group
)
28592 && !insn_terminates_group_p (next_insn
, previous_group
))
28594 if (!is_branch_slot_insn (next_insn
))
28597 while (can_issue_more
)
28600 emit_insn_before (nop
, next_insn
);
28605 can_issue_more
= issue_rate
;
28610 next_insn
= get_next_active_insn (insn
, tail
);
28613 return group_count
;
28616 /* We're beginning a new block. Initialize data structures as necessary. */
28619 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
28620 int sched_verbose ATTRIBUTE_UNUSED
,
28621 int max_ready ATTRIBUTE_UNUSED
)
28623 last_scheduled_insn
= NULL_RTX
;
28624 load_store_pendulum
= 0;
28627 /* The following function is called at the end of scheduling BB.
28628 After reload, it inserts nops at insn group bundling. */
28631 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
28636 fprintf (dump
, "=== Finishing schedule.\n");
28638 if (reload_completed
&& rs6000_sched_groups
)
28640 /* Do not run sched_finish hook when selective scheduling enabled. */
28641 if (sel_sched_p ())
28644 if (rs6000_sched_insert_nops
== sched_finish_none
)
28647 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
28648 n_groups
= pad_groups (dump
, sched_verbose
,
28649 current_sched_info
->prev_head
,
28650 current_sched_info
->next_tail
);
28652 n_groups
= redefine_groups (dump
, sched_verbose
,
28653 current_sched_info
->prev_head
,
28654 current_sched_info
->next_tail
);
28656 if (sched_verbose
>= 6)
28658 fprintf (dump
, "ngroups = %d\n", n_groups
);
28659 print_rtl (dump
, current_sched_info
->prev_head
);
28660 fprintf (dump
, "Done finish_sched\n");
28665 struct _rs6000_sched_context
28667 short cached_can_issue_more
;
28668 rtx last_scheduled_insn
;
28669 int load_store_pendulum
;
28672 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
28673 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
28675 /* Allocate store for new scheduling context. */
28677 rs6000_alloc_sched_context (void)
28679 return xmalloc (sizeof (rs6000_sched_context_def
));
28682 /* If CLEAN_P is true then initializes _SC with clean data,
28683 and from the global context otherwise. */
28685 rs6000_init_sched_context (void *_sc
, bool clean_p
)
28687 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
28691 sc
->cached_can_issue_more
= 0;
28692 sc
->last_scheduled_insn
= NULL_RTX
;
28693 sc
->load_store_pendulum
= 0;
28697 sc
->cached_can_issue_more
= cached_can_issue_more
;
28698 sc
->last_scheduled_insn
= last_scheduled_insn
;
28699 sc
->load_store_pendulum
= load_store_pendulum
;
28703 /* Sets the global scheduling context to the one pointed to by _SC. */
28705 rs6000_set_sched_context (void *_sc
)
28707 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
28709 gcc_assert (sc
!= NULL
);
28711 cached_can_issue_more
= sc
->cached_can_issue_more
;
28712 last_scheduled_insn
= sc
->last_scheduled_insn
;
28713 load_store_pendulum
= sc
->load_store_pendulum
;
28718 rs6000_free_sched_context (void *_sc
)
28720 gcc_assert (_sc
!= NULL
);
28726 /* Length in units of the trampoline for entering a nested function. */
28729 rs6000_trampoline_size (void)
28733 switch (DEFAULT_ABI
)
28736 gcc_unreachable ();
28739 ret
= (TARGET_32BIT
) ? 12 : 24;
28743 gcc_assert (!TARGET_32BIT
);
28749 ret
= (TARGET_32BIT
) ? 40 : 48;
28756 /* Emit RTL insns to initialize the variable parts of a trampoline.
28757 FNADDR is an RTX for the address of the function's pure code.
28758 CXT is an RTX for the static chain value for the function. */
28761 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
28763 int regsize
= (TARGET_32BIT
) ? 4 : 8;
28764 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
28765 rtx ctx_reg
= force_reg (Pmode
, cxt
);
28766 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
28768 switch (DEFAULT_ABI
)
28771 gcc_unreachable ();
28773 /* Under AIX, just build the 3 word function descriptor */
28776 rtx fnmem
, fn_reg
, toc_reg
;
28778 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
28779 error ("You cannot take the address of a nested function if you use "
28780 "the -mno-pointers-to-nested-functions option.");
28782 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
28783 fn_reg
= gen_reg_rtx (Pmode
);
28784 toc_reg
= gen_reg_rtx (Pmode
);
28786 /* Macro to shorten the code expansions below. */
28787 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
28789 m_tramp
= replace_equiv_address (m_tramp
, addr
);
28791 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
28792 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
28793 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
28794 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
28795 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
28801 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
28805 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
28806 LCT_NORMAL
, VOIDmode
, 4,
28808 GEN_INT (rs6000_trampoline_size ()), SImode
,
28816 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
28817 identifier as an argument, so the front end shouldn't look it up. */
28820 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
28822 return is_attribute_p ("altivec", attr_id
);
28825 /* Handle the "altivec" attribute. The attribute may have
28826 arguments as follows:
28828 __attribute__((altivec(vector__)))
28829 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
28830 __attribute__((altivec(bool__))) (always followed by 'unsigned')
28832 and may appear more than once (e.g., 'vector bool char') in a
28833 given declaration. */
28836 rs6000_handle_altivec_attribute (tree
*node
,
28837 tree name ATTRIBUTE_UNUSED
,
28839 int flags ATTRIBUTE_UNUSED
,
28840 bool *no_add_attrs
)
28842 tree type
= *node
, result
= NULL_TREE
;
28846 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
28847 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
28848 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
28851 while (POINTER_TYPE_P (type
)
28852 || TREE_CODE (type
) == FUNCTION_TYPE
28853 || TREE_CODE (type
) == METHOD_TYPE
28854 || TREE_CODE (type
) == ARRAY_TYPE
)
28855 type
= TREE_TYPE (type
);
28857 mode
= TYPE_MODE (type
);
28859 /* Check for invalid AltiVec type qualifiers. */
28860 if (type
== long_double_type_node
)
28861 error ("use of %<long double%> in AltiVec types is invalid");
28862 else if (type
== boolean_type_node
)
28863 error ("use of boolean types in AltiVec types is invalid");
28864 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
28865 error ("use of %<complex%> in AltiVec types is invalid");
28866 else if (DECIMAL_FLOAT_MODE_P (mode
))
28867 error ("use of decimal floating point types in AltiVec types is invalid");
28868 else if (!TARGET_VSX
)
28870 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
28873 error ("use of %<long%> in AltiVec types is invalid for "
28874 "64-bit code without -mvsx");
28875 else if (rs6000_warn_altivec_long
)
28876 warning (0, "use of %<long%> in AltiVec types is deprecated; "
28879 else if (type
== long_long_unsigned_type_node
28880 || type
== long_long_integer_type_node
)
28881 error ("use of %<long long%> in AltiVec types is invalid without "
28883 else if (type
== double_type_node
)
28884 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
28887 switch (altivec_type
)
28890 unsigned_p
= TYPE_UNSIGNED (type
);
28894 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
28897 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
28900 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
28903 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
28906 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
28908 case SFmode
: result
= V4SF_type_node
; break;
28909 case DFmode
: result
= V2DF_type_node
; break;
28910 /* If the user says 'vector int bool', we may be handed the 'bool'
28911 attribute _before_ the 'vector' attribute, and so select the
28912 proper type in the 'b' case below. */
28913 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
28914 case V2DImode
: case V2DFmode
:
28922 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
28923 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
28924 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
28925 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
28932 case V8HImode
: result
= pixel_V8HI_type_node
;
28938 /* Propagate qualifiers attached to the element type
28939 onto the vector type. */
28940 if (result
&& result
!= type
&& TYPE_QUALS (type
))
28941 result
= build_qualified_type (result
, TYPE_QUALS (type
));
28943 *no_add_attrs
= true; /* No need to hang on to the attribute. */
28946 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
28951 /* AltiVec defines four built-in scalar types that serve as vector
28952 elements; we must teach the compiler how to mangle them. */
28954 static const char *
28955 rs6000_mangle_type (const_tree type
)
28957 type
= TYPE_MAIN_VARIANT (type
);
28959 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
28960 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
28963 if (type
== bool_char_type_node
) return "U6__boolc";
28964 if (type
== bool_short_type_node
) return "U6__bools";
28965 if (type
== pixel_type_node
) return "u7__pixel";
28966 if (type
== bool_int_type_node
) return "U6__booli";
28967 if (type
== bool_long_type_node
) return "U6__booll";
28969 /* Mangle IBM extended float long double as `g' (__float128) on
28970 powerpc*-linux where long-double-64 previously was the default. */
28971 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
28973 && TARGET_LONG_DOUBLE_128
28974 && !TARGET_IEEEQUAD
)
28977 /* For all other types, use normal C++ mangling. */
28981 /* Handle a "longcall" or "shortcall" attribute; arguments as in
28982 struct attribute_spec.handler. */
28985 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
28986 tree args ATTRIBUTE_UNUSED
,
28987 int flags ATTRIBUTE_UNUSED
,
28988 bool *no_add_attrs
)
28990 if (TREE_CODE (*node
) != FUNCTION_TYPE
28991 && TREE_CODE (*node
) != FIELD_DECL
28992 && TREE_CODE (*node
) != TYPE_DECL
)
28994 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
28996 *no_add_attrs
= true;
29002 /* Set longcall attributes on all functions declared when
29003 rs6000_default_long_calls is true. */
29005 rs6000_set_default_type_attributes (tree type
)
29007 if (rs6000_default_long_calls
29008 && (TREE_CODE (type
) == FUNCTION_TYPE
29009 || TREE_CODE (type
) == METHOD_TYPE
))
29010 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
29012 TYPE_ATTRIBUTES (type
));
29015 darwin_set_default_type_attributes (type
);
29019 /* Return a reference suitable for calling a function with the
29020 longcall attribute. */
29023 rs6000_longcall_ref (rtx call_ref
)
29025 const char *call_name
;
29028 if (GET_CODE (call_ref
) != SYMBOL_REF
)
29031 /* System V adds '.' to the internal name, so skip them. */
29032 call_name
= XSTR (call_ref
, 0);
29033 if (*call_name
== '.')
29035 while (*call_name
== '.')
29038 node
= get_identifier (call_name
);
29039 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
29042 return force_reg (Pmode
, call_ref
);
29045 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
29046 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
29049 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
29050 struct attribute_spec.handler. */
29052 rs6000_handle_struct_attribute (tree
*node
, tree name
,
29053 tree args ATTRIBUTE_UNUSED
,
29054 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
29057 if (DECL_P (*node
))
29059 if (TREE_CODE (*node
) == TYPE_DECL
)
29060 type
= &TREE_TYPE (*node
);
29065 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
29066 || TREE_CODE (*type
) == UNION_TYPE
)))
29068 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
29069 *no_add_attrs
= true;
29072 else if ((is_attribute_p ("ms_struct", name
)
29073 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
29074 || ((is_attribute_p ("gcc_struct", name
)
29075 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
29077 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
29079 *no_add_attrs
= true;
29086 rs6000_ms_bitfield_layout_p (const_tree record_type
)
29088 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
29089 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
29090 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
29093 #ifdef USING_ELFOS_H
29095 /* A get_unnamed_section callback, used for switching to toc_section. */
29098 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
29100 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29101 && TARGET_MINIMAL_TOC
29102 && !TARGET_RELOCATABLE
)
29104 if (!toc_initialized
)
29106 toc_initialized
= 1;
29107 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
29108 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
29109 fprintf (asm_out_file
, "\t.tc ");
29110 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
29111 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
29112 fprintf (asm_out_file
, "\n");
29114 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29115 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
29116 fprintf (asm_out_file
, " = .+32768\n");
29119 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29121 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29122 && !TARGET_RELOCATABLE
)
29123 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
29126 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29127 if (!toc_initialized
)
29129 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
29130 fprintf (asm_out_file
, " = .+32768\n");
29131 toc_initialized
= 1;
29136 /* Implement TARGET_ASM_INIT_SECTIONS. */
29139 rs6000_elf_asm_init_sections (void)
29142 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
29145 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
29146 SDATA2_SECTION_ASM_OP
);
29149 /* Implement TARGET_SELECT_RTX_SECTION. */
29152 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
29153 unsigned HOST_WIDE_INT align
)
29155 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
29156 return toc_section
;
29158 return default_elf_select_rtx_section (mode
, x
, align
);
29161 /* For a SYMBOL_REF, set generic flags and then perform some
29162 target-specific processing.
29164 When the AIX ABI is requested on a non-AIX system, replace the
29165 function name with the real name (with a leading .) rather than the
29166 function descriptor name. This saves a lot of overriding code to
29167 read the prefixes. */
29169 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
29171 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
29173 default_encode_section_info (decl
, rtl
, first
);
29176 && TREE_CODE (decl
) == FUNCTION_DECL
29178 && DEFAULT_ABI
== ABI_AIX
)
29180 rtx sym_ref
= XEXP (rtl
, 0);
29181 size_t len
= strlen (XSTR (sym_ref
, 0));
29182 char *str
= XALLOCAVEC (char, len
+ 2);
29184 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
29185 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
29190 compare_section_name (const char *section
, const char *templ
)
29194 len
= strlen (templ
);
29195 return (strncmp (section
, templ
, len
) == 0
29196 && (section
[len
] == 0 || section
[len
] == '.'));
29200 rs6000_elf_in_small_data_p (const_tree decl
)
29202 if (rs6000_sdata
== SDATA_NONE
)
29205 /* We want to merge strings, so we never consider them small data. */
29206 if (TREE_CODE (decl
) == STRING_CST
)
29209 /* Functions are never in the small data area. */
29210 if (TREE_CODE (decl
) == FUNCTION_DECL
)
29213 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
29215 const char *section
= DECL_SECTION_NAME (decl
);
29216 if (compare_section_name (section
, ".sdata")
29217 || compare_section_name (section
, ".sdata2")
29218 || compare_section_name (section
, ".gnu.linkonce.s")
29219 || compare_section_name (section
, ".sbss")
29220 || compare_section_name (section
, ".sbss2")
29221 || compare_section_name (section
, ".gnu.linkonce.sb")
29222 || strcmp (section
, ".PPC.EMB.sdata0") == 0
29223 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
29228 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
29231 && size
<= g_switch_value
29232 /* If it's not public, and we're not going to reference it there,
29233 there's no need to put it in the small data section. */
29234 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
29241 #endif /* USING_ELFOS_H */
29243 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
29246 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
29248 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
29251 /* Do not place thread-local symbols refs in the object blocks. */
29254 rs6000_use_blocks_for_decl_p (const_tree decl
)
29256 return !DECL_THREAD_LOCAL_P (decl
);
29259 /* Return a REG that occurs in ADDR with coefficient 1.
29260 ADDR can be effectively incremented by incrementing REG.
29262 r0 is special and we must not select it as an address
29263 register by this routine since our caller will try to
29264 increment the returned register via an "la" instruction. */
29267 find_addr_reg (rtx addr
)
29269 while (GET_CODE (addr
) == PLUS
)
29271 if (GET_CODE (XEXP (addr
, 0)) == REG
29272 && REGNO (XEXP (addr
, 0)) != 0)
29273 addr
= XEXP (addr
, 0);
29274 else if (GET_CODE (XEXP (addr
, 1)) == REG
29275 && REGNO (XEXP (addr
, 1)) != 0)
29276 addr
= XEXP (addr
, 1);
29277 else if (CONSTANT_P (XEXP (addr
, 0)))
29278 addr
= XEXP (addr
, 1);
29279 else if (CONSTANT_P (XEXP (addr
, 1)))
29280 addr
= XEXP (addr
, 0);
29282 gcc_unreachable ();
29284 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
29289 rs6000_fatal_bad_address (rtx op
)
29291 fatal_insn ("bad address", op
);
29296 typedef struct branch_island_d
{
29297 tree function_name
;
29303 static vec
<branch_island
, va_gc
> *branch_islands
;
29305 /* Remember to generate a branch island for far calls to the given
29309 add_compiler_branch_island (tree label_name
, tree function_name
,
29312 branch_island bi
= {function_name
, label_name
, line_number
};
29313 vec_safe_push (branch_islands
, bi
);
29316 /* Generate far-jump branch islands for everything recorded in
29317 branch_islands. Invoked immediately after the last instruction of
29318 the epilogue has been emitted; the branch islands must be appended
29319 to, and contiguous with, the function body. Mach-O stubs are
29320 generated in machopic_output_stub(). */
29323 macho_branch_islands (void)
29327 while (!vec_safe_is_empty (branch_islands
))
29329 branch_island
*bi
= &branch_islands
->last ();
29330 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
29331 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
29332 char name_buf
[512];
29333 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
29334 if (name
[0] == '*' || name
[0] == '&')
29335 strcpy (name_buf
, name
+1);
29339 strcpy (name_buf
+1, name
);
29341 strcpy (tmp_buf
, "\n");
29342 strcat (tmp_buf
, label
);
29343 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
29344 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
29345 dbxout_stabd (N_SLINE
, bi
->line_number
);
29346 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
29349 if (TARGET_LINK_STACK
)
29352 get_ppc476_thunk_name (name
);
29353 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
29354 strcat (tmp_buf
, name
);
29355 strcat (tmp_buf
, "\n");
29356 strcat (tmp_buf
, label
);
29357 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
29361 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
29362 strcat (tmp_buf
, label
);
29363 strcat (tmp_buf
, "_pic\n");
29364 strcat (tmp_buf
, label
);
29365 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
29368 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
29369 strcat (tmp_buf
, name_buf
);
29370 strcat (tmp_buf
, " - ");
29371 strcat (tmp_buf
, label
);
29372 strcat (tmp_buf
, "_pic)\n");
29374 strcat (tmp_buf
, "\tmtlr r0\n");
29376 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
29377 strcat (tmp_buf
, name_buf
);
29378 strcat (tmp_buf
, " - ");
29379 strcat (tmp_buf
, label
);
29380 strcat (tmp_buf
, "_pic)\n");
29382 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
29386 strcat (tmp_buf
, ":\nlis r12,hi16(");
29387 strcat (tmp_buf
, name_buf
);
29388 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
29389 strcat (tmp_buf
, name_buf
);
29390 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
29392 output_asm_insn (tmp_buf
, 0);
29393 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
29394 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
29395 dbxout_stabd (N_SLINE
, bi
->line_number
);
29396 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
29397 branch_islands
->pop ();
29401 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
29402 already there or not. */
29405 no_previous_def (tree function_name
)
29410 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
29411 if (function_name
== bi
->function_name
)
29416 /* GET_PREV_LABEL gets the label name from the previous definition of
29420 get_prev_label (tree function_name
)
29425 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
29426 if (function_name
== bi
->function_name
)
29427 return bi
->label_name
;
29431 /* INSN is either a function call or a millicode call. It may have an
29432 unconditional jump in its delay slot.
29434 CALL_DEST is the routine we are calling. */
29437 output_call (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
29438 int cookie_operand_number
)
29440 static char buf
[256];
29441 if (darwin_emit_branch_islands
29442 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
29443 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
29446 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
29448 if (no_previous_def (funname
))
29450 rtx label_rtx
= gen_label_rtx ();
29451 char *label_buf
, temp_buf
[256];
29452 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
29453 CODE_LABEL_NUMBER (label_rtx
));
29454 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
29455 labelname
= get_identifier (label_buf
);
29456 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
29459 labelname
= get_prev_label (funname
);
29461 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
29462 instruction will reach 'foo', otherwise link as 'bl L42'".
29463 "L42" should be a 'branch island', that will do a far jump to
29464 'foo'. Branch islands are generated in
29465 macho_branch_islands(). */
29466 sprintf (buf
, "jbsr %%z%d,%.246s",
29467 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
29470 sprintf (buf
, "bl %%z%d", dest_operand_number
);
29474 /* Generate PIC and indirect symbol stubs. */
29477 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
29479 unsigned int length
;
29480 char *symbol_name
, *lazy_ptr_name
;
29481 char *local_label_0
;
29482 static int label
= 0;
29484 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
29485 symb
= (*targetm
.strip_name_encoding
) (symb
);
29488 length
= strlen (symb
);
29489 symbol_name
= XALLOCAVEC (char, length
+ 32);
29490 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
29492 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
29493 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
29496 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
29498 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
29502 fprintf (file
, "\t.align 5\n");
29504 fprintf (file
, "%s:\n", stub
);
29505 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
29508 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
29509 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
29511 fprintf (file
, "\tmflr r0\n");
29512 if (TARGET_LINK_STACK
)
29515 get_ppc476_thunk_name (name
);
29516 fprintf (file
, "\tbl %s\n", name
);
29517 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
29521 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
29522 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
29524 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
29525 lazy_ptr_name
, local_label_0
);
29526 fprintf (file
, "\tmtlr r0\n");
29527 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
29528 (TARGET_64BIT
? "ldu" : "lwzu"),
29529 lazy_ptr_name
, local_label_0
);
29530 fprintf (file
, "\tmtctr r12\n");
29531 fprintf (file
, "\tbctr\n");
29535 fprintf (file
, "\t.align 4\n");
29537 fprintf (file
, "%s:\n", stub
);
29538 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
29540 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
29541 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
29542 (TARGET_64BIT
? "ldu" : "lwzu"),
29544 fprintf (file
, "\tmtctr r12\n");
29545 fprintf (file
, "\tbctr\n");
29548 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
29549 fprintf (file
, "%s:\n", lazy_ptr_name
);
29550 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
29551 fprintf (file
, "%sdyld_stub_binding_helper\n",
29552 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
29555 /* Legitimize PIC addresses. If the address is already
29556 position-independent, we return ORIG. Newly generated
29557 position-independent addresses go into a reg. This is REG if non
29558 zero, otherwise we allocate register(s) as necessary. */
29560 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
29563 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
29568 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
29569 reg
= gen_reg_rtx (Pmode
);
29571 if (GET_CODE (orig
) == CONST
)
29575 if (GET_CODE (XEXP (orig
, 0)) == PLUS
29576 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
29579 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
29581 /* Use a different reg for the intermediate value, as
29582 it will be marked UNCHANGING. */
29583 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
29584 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
29587 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
29590 if (GET_CODE (offset
) == CONST_INT
)
29592 if (SMALL_INT (offset
))
29593 return plus_constant (Pmode
, base
, INTVAL (offset
));
29594 else if (! reload_in_progress
&& ! reload_completed
)
29595 offset
= force_reg (Pmode
, offset
);
29598 rtx mem
= force_const_mem (Pmode
, orig
);
29599 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
29602 return gen_rtx_PLUS (Pmode
, base
, offset
);
29605 /* Fall back on generic machopic code. */
29606 return machopic_legitimize_pic_address (orig
, mode
, reg
);
29609 /* Output a .machine directive for the Darwin assembler, and call
29610 the generic start_file routine. */
29613 rs6000_darwin_file_start (void)
29615 static const struct
29619 HOST_WIDE_INT if_set
;
29621 { "ppc64", "ppc64", MASK_64BIT
},
29622 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
29623 { "power4", "ppc970", 0 },
29624 { "G5", "ppc970", 0 },
29625 { "7450", "ppc7450", 0 },
29626 { "7400", "ppc7400", MASK_ALTIVEC
},
29627 { "G4", "ppc7400", 0 },
29628 { "750", "ppc750", 0 },
29629 { "740", "ppc750", 0 },
29630 { "G3", "ppc750", 0 },
29631 { "604e", "ppc604e", 0 },
29632 { "604", "ppc604", 0 },
29633 { "603e", "ppc603", 0 },
29634 { "603", "ppc603", 0 },
29635 { "601", "ppc601", 0 },
29636 { NULL
, "ppc", 0 } };
29637 const char *cpu_id
= "";
29640 rs6000_file_start ();
29641 darwin_file_start ();
29643 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
29645 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
29646 cpu_id
= rs6000_default_cpu
;
29648 if (global_options_set
.x_rs6000_cpu_index
)
29649 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
29651 /* Look through the mapping array. Pick the first name that either
29652 matches the argument, has a bit set in IF_SET that is also set
29653 in the target flags, or has a NULL name. */
29656 while (mapping
[i
].arg
!= NULL
29657 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
29658 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
29661 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
29664 #endif /* TARGET_MACHO */
29668 rs6000_elf_reloc_rw_mask (void)
29672 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
29678 /* Record an element in the table of global constructors. SYMBOL is
29679 a SYMBOL_REF of the function to be called; PRIORITY is a number
29680 between 0 and MAX_INIT_PRIORITY.
29682 This differs from default_named_section_asm_out_constructor in
29683 that we have special handling for -mrelocatable. */
29685 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
29687 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
29689 const char *section
= ".ctors";
29692 if (priority
!= DEFAULT_INIT_PRIORITY
)
29694 sprintf (buf
, ".ctors.%.5u",
29695 /* Invert the numbering so the linker puts us in the proper
29696 order; constructors are run from right to left, and the
29697 linker sorts in increasing order. */
29698 MAX_INIT_PRIORITY
- priority
);
29702 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
29703 assemble_align (POINTER_SIZE
);
29705 if (TARGET_RELOCATABLE
)
29707 fputs ("\t.long (", asm_out_file
);
29708 output_addr_const (asm_out_file
, symbol
);
29709 fputs (")@fixup\n", asm_out_file
);
29712 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
29715 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
29717 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
29719 const char *section
= ".dtors";
29722 if (priority
!= DEFAULT_INIT_PRIORITY
)
29724 sprintf (buf
, ".dtors.%.5u",
29725 /* Invert the numbering so the linker puts us in the proper
29726 order; constructors are run from right to left, and the
29727 linker sorts in increasing order. */
29728 MAX_INIT_PRIORITY
- priority
);
29732 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
29733 assemble_align (POINTER_SIZE
);
29735 if (TARGET_RELOCATABLE
)
29737 fputs ("\t.long (", asm_out_file
);
29738 output_addr_const (asm_out_file
, symbol
);
29739 fputs (")@fixup\n", asm_out_file
);
29742 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
29746 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
29748 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
29750 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
29751 ASM_OUTPUT_LABEL (file
, name
);
29752 fputs (DOUBLE_INT_ASM_OP
, file
);
29753 rs6000_output_function_entry (file
, name
);
29754 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
29757 fputs ("\t.size\t", file
);
29758 assemble_name (file
, name
);
29759 fputs (",24\n\t.type\t.", file
);
29760 assemble_name (file
, name
);
29761 fputs (",@function\n", file
);
29762 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
29764 fputs ("\t.globl\t.", file
);
29765 assemble_name (file
, name
);
29770 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29771 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29772 rs6000_output_function_entry (file
, name
);
29773 fputs (":\n", file
);
29777 if (TARGET_RELOCATABLE
29778 && !TARGET_SECURE_PLT
29779 && (get_pool_size () != 0 || crtl
->profile
)
29784 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
29786 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
29787 fprintf (file
, "\t.long ");
29788 assemble_name (file
, buf
);
29790 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
29791 assemble_name (file
, buf
);
29795 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
29796 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
29798 if (DEFAULT_ABI
== ABI_AIX
)
29800 const char *desc_name
, *orig_name
;
29802 orig_name
= (*targetm
.strip_name_encoding
) (name
);
29803 desc_name
= orig_name
;
29804 while (*desc_name
== '.')
29807 if (TREE_PUBLIC (decl
))
29808 fprintf (file
, "\t.globl %s\n", desc_name
);
29810 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
29811 fprintf (file
, "%s:\n", desc_name
);
29812 fprintf (file
, "\t.long %s\n", orig_name
);
29813 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
29814 fputs ("\t.long 0\n", file
);
29815 fprintf (file
, "\t.previous\n");
29817 ASM_OUTPUT_LABEL (file
, name
);
29820 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
29822 rs6000_elf_file_end (void)
29824 #ifdef HAVE_AS_GNU_ATTRIBUTE
29825 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
29827 if (rs6000_passes_float
)
29828 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
29829 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
29830 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
29832 if (rs6000_passes_vector
)
29833 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
29834 (TARGET_ALTIVEC_ABI
? 2
29835 : TARGET_SPE_ABI
? 3
29837 if (rs6000_returns_struct
)
29838 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
29839 aix_struct_return
? 2 : 1);
29842 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
29843 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
29844 file_end_indicate_exec_stack ();
29851 rs6000_xcoff_asm_output_anchor (rtx symbol
)
29855 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
29856 SYMBOL_REF_BLOCK_OFFSET (symbol
));
29857 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
29858 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
29859 fprintf (asm_out_file
, ",");
29860 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
29861 fprintf (asm_out_file
, "\n");
29865 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
29867 fputs (GLOBAL_ASM_OP
, stream
);
29868 RS6000_OUTPUT_BASENAME (stream
, name
);
29869 putc ('\n', stream
);
29872 /* A get_unnamed_decl callback, used for read-only sections. PTR
29873 points to the section string variable. */
29876 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
29878 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
29879 *(const char *const *) directive
,
29880 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29883 /* Likewise for read-write sections. */
29886 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
29888 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
29889 *(const char *const *) directive
,
29890 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29894 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
29896 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
29897 *(const char *const *) directive
,
29898 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
29901 /* A get_unnamed_section callback, used for switching to toc_section. */
29904 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
29906 if (TARGET_MINIMAL_TOC
)
29908 /* toc_section is always selected at least once from
29909 rs6000_xcoff_file_start, so this is guaranteed to
29910 always be defined once and only once in each file. */
29911 if (!toc_initialized
)
29913 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
29914 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
29915 toc_initialized
= 1;
29917 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
29918 (TARGET_32BIT
? "" : ",3"));
29921 fputs ("\t.toc\n", asm_out_file
);
29924 /* Implement TARGET_ASM_INIT_SECTIONS. */
29927 rs6000_xcoff_asm_init_sections (void)
29929 read_only_data_section
29930 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29931 &xcoff_read_only_section_name
);
29933 private_data_section
29934 = get_unnamed_section (SECTION_WRITE
,
29935 rs6000_xcoff_output_readwrite_section_asm_op
,
29936 &xcoff_private_data_section_name
);
29939 = get_unnamed_section (SECTION_TLS
,
29940 rs6000_xcoff_output_tls_section_asm_op
,
29941 &xcoff_tls_data_section_name
);
29943 tls_private_data_section
29944 = get_unnamed_section (SECTION_TLS
,
29945 rs6000_xcoff_output_tls_section_asm_op
,
29946 &xcoff_private_data_section_name
);
29948 read_only_private_data_section
29949 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
29950 &xcoff_private_data_section_name
);
29953 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
29955 readonly_data_section
= read_only_data_section
;
29956 exception_section
= data_section
;
29960 rs6000_xcoff_reloc_rw_mask (void)
29966 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
29967 tree decl ATTRIBUTE_UNUSED
)
29970 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
29972 if (flags
& SECTION_CODE
)
29974 else if (flags
& SECTION_TLS
)
29976 else if (flags
& SECTION_WRITE
)
29981 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
29982 (flags
& SECTION_CODE
) ? "." : "",
29983 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
29986 #define IN_NAMED_SECTION(DECL) \
29987 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
29988 && DECL_SECTION_NAME (DECL) != NULL)
29991 rs6000_xcoff_select_section (tree decl
, int reloc
,
29992 unsigned HOST_WIDE_INT align
)
29994 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
29996 if (align
> BIGGEST_ALIGNMENT
)
29998 resolve_unique_section (decl
, reloc
, true);
29999 if (IN_NAMED_SECTION (decl
))
30000 return get_named_section (decl
, NULL
, reloc
);
30003 if (decl_readonly_section (decl
, reloc
))
30005 if (TREE_PUBLIC (decl
))
30006 return read_only_data_section
;
30008 return read_only_private_data_section
;
30013 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
30015 if (TREE_PUBLIC (decl
))
30016 return tls_data_section
;
30017 else if (bss_initializer_p (decl
))
30019 /* Convert to COMMON to emit in BSS. */
30020 DECL_COMMON (decl
) = 1;
30021 return tls_comm_section
;
30024 return tls_private_data_section
;
30028 if (TREE_PUBLIC (decl
))
30029 return data_section
;
30031 return private_data_section
;
30036 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
30040 /* Use select_section for private data and uninitialized data with
30041 alignment <= BIGGEST_ALIGNMENT. */
30042 if (!TREE_PUBLIC (decl
)
30043 || DECL_COMMON (decl
)
30044 || (DECL_INITIAL (decl
) == NULL_TREE
30045 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
30046 || DECL_INITIAL (decl
) == error_mark_node
30047 || (flag_zero_initialized_in_bss
30048 && initializer_zerop (DECL_INITIAL (decl
))))
30051 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
30052 name
= (*targetm
.strip_name_encoding
) (name
);
30053 set_decl_section_name (decl
, name
);
30056 /* Select section for constant in constant pool.
30058 On RS/6000, all constants are in the private read-only data area.
30059 However, if this is being placed in the TOC it must be output as a
30063 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
30064 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
30066 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
30067 return toc_section
;
30069 return read_only_private_data_section
;
30072 /* Remove any trailing [DS] or the like from the symbol name. */
30074 static const char *
30075 rs6000_xcoff_strip_name_encoding (const char *name
)
30080 len
= strlen (name
);
30081 if (name
[len
- 1] == ']')
30082 return ggc_alloc_string (name
, len
- 4);
30087 /* Section attributes. AIX is always PIC. */
30089 static unsigned int
30090 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
30092 unsigned int align
;
30093 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
30095 /* Align to at least UNIT size. */
30096 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
30097 align
= MIN_UNITS_PER_WORD
;
30099 /* Increase alignment of large objects if not already stricter. */
30100 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
30101 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
30102 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
30104 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
30107 /* Output at beginning of assembler file.
30109 Initialize the section names for the RS/6000 at this point.
30111 Specify filename, including full path, to assembler.
30113 We want to go into the TOC section so at least one .toc will be emitted.
30114 Also, in order to output proper .bs/.es pairs, we need at least one static
30115 [RW] section emitted.
30117 Finally, declare mcount when profiling to make the assembler happy. */
30120 rs6000_xcoff_file_start (void)
30122 rs6000_gen_section_name (&xcoff_bss_section_name
,
30123 main_input_filename
, ".bss_");
30124 rs6000_gen_section_name (&xcoff_private_data_section_name
,
30125 main_input_filename
, ".rw_");
30126 rs6000_gen_section_name (&xcoff_read_only_section_name
,
30127 main_input_filename
, ".ro_");
30128 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
30129 main_input_filename
, ".tls_");
30130 rs6000_gen_section_name (&xcoff_tbss_section_name
,
30131 main_input_filename
, ".tbss_[UL]");
30133 fputs ("\t.file\t", asm_out_file
);
30134 output_quoted_string (asm_out_file
, main_input_filename
);
30135 fputc ('\n', asm_out_file
);
30136 if (write_symbols
!= NO_DEBUG
)
30137 switch_to_section (private_data_section
);
30138 switch_to_section (text_section
);
30140 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
30141 rs6000_file_start ();
30144 /* Output at end of assembler file.
30145 On the RS/6000, referencing data should automatically pull in text. */
30148 rs6000_xcoff_file_end (void)
30150 switch_to_section (text_section
);
30151 fputs ("_section_.text:\n", asm_out_file
);
30152 switch_to_section (data_section
);
30153 fputs (TARGET_32BIT
30154 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
30158 struct declare_alias_data
30161 bool function_descriptor
;
30164 /* Declare alias N. A helper function for for_node_and_aliases. */
30167 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
30169 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
30170 /* Main symbol is output specially, because varasm machinery does part of
30171 the job for us - we do not need to declare .globl/lglobs and such. */
30172 if (!n
->alias
|| n
->weakref
)
30175 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
30178 /* Prevent assemble_alias from trying to use .set pseudo operation
30179 that does not behave as expected by the middle-end. */
30180 TREE_ASM_WRITTEN (n
->decl
) = true;
30182 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
30183 char *buffer
= (char *) alloca (strlen (name
) + 2);
30185 int dollar_inside
= 0;
30187 strcpy (buffer
, name
);
30188 p
= strchr (buffer
, '$');
30192 p
= strchr (p
+ 1, '$');
30194 if (TREE_PUBLIC (n
->decl
))
30196 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
30198 if (dollar_inside
) {
30199 if (data
->function_descriptor
)
30200 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
30202 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
30204 if (data
->function_descriptor
)
30205 fputs ("\t.globl .", data
->file
);
30207 fputs ("\t.globl ", data
->file
);
30208 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
30209 putc ('\n', data
->file
);
30211 #ifdef ASM_WEAKEN_DECL
30212 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
30213 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
30220 if (data
->function_descriptor
)
30221 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
30223 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
30225 if (data
->function_descriptor
)
30226 fputs ("\t.lglobl .", data
->file
);
30228 fputs ("\t.lglobl ", data
->file
);
30229 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
30230 putc ('\n', data
->file
);
30232 if (data
->function_descriptor
)
30233 fputs (".", data
->file
);
30234 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
30235 fputs (":\n", data
->file
);
30239 /* This macro produces the initial definition of a function name.
30240 On the RS/6000, we need to place an extra '.' in the function name and
30241 output the function descriptor.
30242 Dollar signs are converted to underscores.
30244 The csect for the function will have already been created when
30245 text_section was selected. We do have to go back to that csect, however.
30247 The third and fourth parameters to the .function pseudo-op (16 and 044)
30248 are placeholders which no longer have any use.
30250 Because AIX assembler's .set command has unexpected semantics, we output
30251 all aliases as alternative labels in front of the definition. */
30254 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
30256 char *buffer
= (char *) alloca (strlen (name
) + 1);
30258 int dollar_inside
= 0;
30259 struct declare_alias_data data
= {file
, false};
30261 strcpy (buffer
, name
);
30262 p
= strchr (buffer
, '$');
30266 p
= strchr (p
+ 1, '$');
30268 if (TREE_PUBLIC (decl
))
30270 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
30272 if (dollar_inside
) {
30273 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
30274 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
30276 fputs ("\t.globl .", file
);
30277 RS6000_OUTPUT_BASENAME (file
, buffer
);
30283 if (dollar_inside
) {
30284 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
30285 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
30287 fputs ("\t.lglobl .", file
);
30288 RS6000_OUTPUT_BASENAME (file
, buffer
);
30291 fputs ("\t.csect ", file
);
30292 RS6000_OUTPUT_BASENAME (file
, buffer
);
30293 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
30294 RS6000_OUTPUT_BASENAME (file
, buffer
);
30295 fputs (":\n", file
);
30296 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
30297 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
30298 RS6000_OUTPUT_BASENAME (file
, buffer
);
30299 fputs (", TOC[tc0], 0\n", file
);
30301 switch_to_section (function_section (decl
));
30303 RS6000_OUTPUT_BASENAME (file
, buffer
);
30304 fputs (":\n", file
);
30305 data
.function_descriptor
= true;
30306 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
30307 if (write_symbols
!= NO_DEBUG
&& !DECL_IGNORED_P (decl
))
30308 xcoffout_declare_function (file
, decl
, buffer
);
30312 /* This macro produces the initial definition of a object (variable) name.
30313 Because AIX assembler's .set command has unexpected semantics, we output
30314 all aliases as alternative labels in front of the definition. */
30317 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
30319 struct declare_alias_data data
= {file
, false};
30320 RS6000_OUTPUT_BASENAME (file
, name
);
30321 fputs (":\n", file
);
30322 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
, &data
, true);
30327 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
30332 default_encode_section_info (decl
, rtl
, first
);
30334 /* Careful not to prod global register variables. */
30337 symbol
= XEXP (rtl
, 0);
30338 if (GET_CODE (symbol
) != SYMBOL_REF
)
30341 flags
= SYMBOL_REF_FLAGS (symbol
);
30343 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
30344 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
30346 SYMBOL_REF_FLAGS (symbol
) = flags
;
30348 #endif /* HAVE_AS_TLS */
30349 #endif /* TARGET_XCOFF */
30351 /* Compute a (partial) cost for rtx X. Return true if the complete
30352 cost has been computed, and false if subexpressions should be
30353 scanned. In either case, *TOTAL contains the cost result. */
30356 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
30357 int *total
, bool speed
)
30359 machine_mode mode
= GET_MODE (x
);
30363 /* On the RS/6000, if it is valid in the insn, it is free. */
30365 if (((outer_code
== SET
30366 || outer_code
== PLUS
30367 || outer_code
== MINUS
)
30368 && (satisfies_constraint_I (x
)
30369 || satisfies_constraint_L (x
)))
30370 || (outer_code
== AND
30371 && (satisfies_constraint_K (x
)
30373 ? satisfies_constraint_L (x
)
30374 : satisfies_constraint_J (x
))
30375 || mask_operand (x
, mode
)
30377 && mask64_operand (x
, DImode
))))
30378 || ((outer_code
== IOR
|| outer_code
== XOR
)
30379 && (satisfies_constraint_K (x
)
30381 ? satisfies_constraint_L (x
)
30382 : satisfies_constraint_J (x
))))
30383 || outer_code
== ASHIFT
30384 || outer_code
== ASHIFTRT
30385 || outer_code
== LSHIFTRT
30386 || outer_code
== ROTATE
30387 || outer_code
== ROTATERT
30388 || outer_code
== ZERO_EXTRACT
30389 || (outer_code
== MULT
30390 && satisfies_constraint_I (x
))
30391 || ((outer_code
== DIV
|| outer_code
== UDIV
30392 || outer_code
== MOD
|| outer_code
== UMOD
)
30393 && exact_log2 (INTVAL (x
)) >= 0)
30394 || (outer_code
== COMPARE
30395 && (satisfies_constraint_I (x
)
30396 || satisfies_constraint_K (x
)))
30397 || ((outer_code
== EQ
|| outer_code
== NE
)
30398 && (satisfies_constraint_I (x
)
30399 || satisfies_constraint_K (x
)
30401 ? satisfies_constraint_L (x
)
30402 : satisfies_constraint_J (x
))))
30403 || (outer_code
== GTU
30404 && satisfies_constraint_I (x
))
30405 || (outer_code
== LTU
30406 && satisfies_constraint_P (x
)))
30411 else if ((outer_code
== PLUS
30412 && reg_or_add_cint_operand (x
, VOIDmode
))
30413 || (outer_code
== MINUS
30414 && reg_or_sub_cint_operand (x
, VOIDmode
))
30415 || ((outer_code
== SET
30416 || outer_code
== IOR
30417 || outer_code
== XOR
)
30419 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
30421 *total
= COSTS_N_INSNS (1);
30427 case CONST_WIDE_INT
:
30432 /* When optimizing for size, MEM should be slightly more expensive
30433 than generating address, e.g., (plus (reg) (const)).
30434 L1 cache latency is about two instructions. */
30435 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
30444 if (FLOAT_MODE_P (mode
))
30445 *total
= rs6000_cost
->fp
;
30447 *total
= COSTS_N_INSNS (1);
30451 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
30452 && satisfies_constraint_I (XEXP (x
, 1)))
30454 if (INTVAL (XEXP (x
, 1)) >= -256
30455 && INTVAL (XEXP (x
, 1)) <= 255)
30456 *total
= rs6000_cost
->mulsi_const9
;
30458 *total
= rs6000_cost
->mulsi_const
;
30460 else if (mode
== SFmode
)
30461 *total
= rs6000_cost
->fp
;
30462 else if (FLOAT_MODE_P (mode
))
30463 *total
= rs6000_cost
->dmul
;
30464 else if (mode
== DImode
)
30465 *total
= rs6000_cost
->muldi
;
30467 *total
= rs6000_cost
->mulsi
;
30471 if (mode
== SFmode
)
30472 *total
= rs6000_cost
->fp
;
30474 *total
= rs6000_cost
->dmul
;
30479 if (FLOAT_MODE_P (mode
))
30481 *total
= mode
== DFmode
? rs6000_cost
->ddiv
30482 : rs6000_cost
->sdiv
;
30489 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
30490 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
30492 if (code
== DIV
|| code
== MOD
)
30494 *total
= COSTS_N_INSNS (2);
30497 *total
= COSTS_N_INSNS (1);
30501 if (GET_MODE (XEXP (x
, 1)) == DImode
)
30502 *total
= rs6000_cost
->divdi
;
30504 *total
= rs6000_cost
->divsi
;
30506 /* Add in shift and subtract for MOD. */
30507 if (code
== MOD
|| code
== UMOD
)
30508 *total
+= COSTS_N_INSNS (2);
30513 *total
= COSTS_N_INSNS (4);
30517 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
30521 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
30525 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
30537 *total
= COSTS_N_INSNS (1);
30545 /* Handle mul_highpart. */
30546 if (outer_code
== TRUNCATE
30547 && GET_CODE (XEXP (x
, 0)) == MULT
)
30549 if (mode
== DImode
)
30550 *total
= rs6000_cost
->muldi
;
30552 *total
= rs6000_cost
->mulsi
;
30555 else if (outer_code
== AND
)
30558 *total
= COSTS_N_INSNS (1);
30563 if (GET_CODE (XEXP (x
, 0)) == MEM
)
30566 *total
= COSTS_N_INSNS (1);
30572 if (!FLOAT_MODE_P (mode
))
30574 *total
= COSTS_N_INSNS (1);
30580 case UNSIGNED_FLOAT
:
30583 case FLOAT_TRUNCATE
:
30584 *total
= rs6000_cost
->fp
;
30588 if (mode
== DFmode
)
30589 *total
= rs6000_cost
->sfdf_convert
;
30591 *total
= rs6000_cost
->fp
;
30595 switch (XINT (x
, 1))
30598 *total
= rs6000_cost
->fp
;
30610 *total
= COSTS_N_INSNS (1);
30613 else if (FLOAT_MODE_P (mode
)
30614 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30616 *total
= rs6000_cost
->fp
;
30625 /* Carry bit requires mode == Pmode.
30626 NEG or PLUS already counted so only add one. */
30628 && (outer_code
== NEG
|| outer_code
== PLUS
))
30630 *total
= COSTS_N_INSNS (1);
30633 if (outer_code
== SET
)
30635 if (XEXP (x
, 1) == const0_rtx
)
30637 if (TARGET_ISEL
&& !TARGET_MFCRF
)
30638 *total
= COSTS_N_INSNS (8);
30640 *total
= COSTS_N_INSNS (2);
30645 *total
= COSTS_N_INSNS (3);
30654 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
30656 if (TARGET_ISEL
&& !TARGET_MFCRF
)
30657 *total
= COSTS_N_INSNS (8);
30659 *total
= COSTS_N_INSNS (2);
30663 if (outer_code
== COMPARE
)
30677 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
30680 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
30683 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
30686 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
30687 "opno = %d, total = %d, speed = %s, x:\n",
30688 ret
? "complete" : "scan inner",
30689 GET_RTX_NAME (code
),
30690 GET_RTX_NAME (outer_code
),
30693 speed
? "true" : "false");
30700 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
30703 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
30704 addr_space_t as
, bool speed
)
30706 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
30708 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
30709 ret
, speed
? "true" : "false");
30716 /* A C expression returning the cost of moving data from a register of class
30717 CLASS1 to one of CLASS2. */
30720 rs6000_register_move_cost (machine_mode mode
,
30721 reg_class_t from
, reg_class_t to
)
30725 if (TARGET_DEBUG_COST
)
30728 /* Moves from/to GENERAL_REGS. */
30729 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
30730 || reg_classes_intersect_p (from
, GENERAL_REGS
))
30732 reg_class_t rclass
= from
;
30734 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
30737 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
30738 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
30739 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
30741 /* It's more expensive to move CR_REGS than CR0_REGS because of the
30743 else if (rclass
== CR_REGS
)
30746 /* For those processors that have slow LR/CTR moves, make them more
30747 expensive than memory in order to bias spills to memory .*/
30748 else if ((rs6000_cpu
== PROCESSOR_POWER6
30749 || rs6000_cpu
== PROCESSOR_POWER7
30750 || rs6000_cpu
== PROCESSOR_POWER8
)
30751 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
30752 ret
= 6 * hard_regno_nregs
[0][mode
];
30755 /* A move will cost one instruction per GPR moved. */
30756 ret
= 2 * hard_regno_nregs
[0][mode
];
30759 /* If we have VSX, we can easily move between FPR or Altivec registers. */
30760 else if (VECTOR_MEM_VSX_P (mode
)
30761 && reg_classes_intersect_p (to
, VSX_REGS
)
30762 && reg_classes_intersect_p (from
, VSX_REGS
))
30763 ret
= 2 * hard_regno_nregs
[32][mode
];
30765 /* Moving between two similar registers is just one instruction. */
30766 else if (reg_classes_intersect_p (to
, from
))
30767 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
30769 /* Everything else has to go through GENERAL_REGS. */
30771 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
30772 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
30774 if (TARGET_DEBUG_COST
)
30776 if (dbg_cost_ctrl
== 1)
30778 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
30779 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
30780 reg_class_names
[to
]);
30787 /* A C expressions returning the cost of moving data of MODE from a register to
30791 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
30792 bool in ATTRIBUTE_UNUSED
)
30796 if (TARGET_DEBUG_COST
)
30799 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
30800 ret
= 4 * hard_regno_nregs
[0][mode
];
30801 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
30802 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
30803 ret
= 4 * hard_regno_nregs
[32][mode
];
30804 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
30805 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
30807 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
30809 if (TARGET_DEBUG_COST
)
30811 if (dbg_cost_ctrl
== 1)
30813 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
30814 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
30821 /* Returns a code for a target-specific builtin that implements
30822 reciprocal of the function, or NULL_TREE if not available. */
30825 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
30826 bool sqrt ATTRIBUTE_UNUSED
)
30828 if (optimize_insn_for_size_p ())
30834 case VSX_BUILTIN_XVSQRTDP
:
30835 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
30838 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
30840 case VSX_BUILTIN_XVSQRTSP
:
30841 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
30844 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
30853 case BUILT_IN_SQRT
:
30854 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
30857 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
30859 case BUILT_IN_SQRTF
:
30860 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
30863 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
30870 /* Load up a constant. If the mode is a vector mode, splat the value across
30871 all of the vector elements. */
30874 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
30878 if (mode
== SFmode
|| mode
== DFmode
)
30880 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
30881 reg
= force_reg (mode
, d
);
30883 else if (mode
== V4SFmode
)
30885 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
30886 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
30887 reg
= gen_reg_rtx (mode
);
30888 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
30890 else if (mode
== V2DFmode
)
30892 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
30893 rtvec v
= gen_rtvec (2, d
, d
);
30894 reg
= gen_reg_rtx (mode
);
30895 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
30898 gcc_unreachable ();
30903 /* Generate an FMA instruction. */
30906 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
30908 machine_mode mode
= GET_MODE (target
);
30911 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30912 gcc_assert (dst
!= NULL
);
30915 emit_move_insn (target
, dst
);
30918 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
30921 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
30923 machine_mode mode
= GET_MODE (target
);
30926 /* Altivec does not support fms directly;
30927 generate in terms of fma in that case. */
30928 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
30929 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
30932 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
30933 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
30935 gcc_assert (dst
!= NULL
);
30938 emit_move_insn (target
, dst
);
30941 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
30944 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
30946 machine_mode mode
= GET_MODE (dst
);
30949 /* This is a tad more complicated, since the fnma_optab is for
30950 a different expression: fma(-m1, m2, a), which is the same
30951 thing except in the case of signed zeros.
30953 Fortunately we know that if FMA is supported that FNMSUB is
30954 also supported in the ISA. Just expand it directly. */
30956 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
30958 r
= gen_rtx_NEG (mode
, a
);
30959 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
30960 r
= gen_rtx_NEG (mode
, r
);
30961 emit_insn (gen_rtx_SET (dst
, r
));
30964 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
30965 add a reg_note saying that this was a division. Support both scalar and
30966 vector divide. Assumes no trapping math and finite arguments. */
30969 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
30971 machine_mode mode
= GET_MODE (dst
);
30972 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
30975 /* Low precision estimates guarantee 5 bits of accuracy. High
30976 precision estimates guarantee 14 bits of accuracy. SFmode
30977 requires 23 bits of accuracy. DFmode requires 52 bits of
30978 accuracy. Each pass at least doubles the accuracy, leading
30979 to the following. */
30980 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
30981 if (mode
== DFmode
|| mode
== V2DFmode
)
30984 enum insn_code code
= optab_handler (smul_optab
, mode
);
30985 insn_gen_fn gen_mul
= GEN_FCN (code
);
30987 gcc_assert (code
!= CODE_FOR_nothing
);
30989 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
30991 /* x0 = 1./d estimate */
30992 x0
= gen_reg_rtx (mode
);
30993 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
30996 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
30999 /* e0 = 1. - d * x0 */
31000 e0
= gen_reg_rtx (mode
);
31001 rs6000_emit_nmsub (e0
, d
, x0
, one
);
31003 /* x1 = x0 + e0 * x0 */
31004 x1
= gen_reg_rtx (mode
);
31005 rs6000_emit_madd (x1
, e0
, x0
, x0
);
31007 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
31008 ++i
, xprev
= xnext
, eprev
= enext
) {
31010 /* enext = eprev * eprev */
31011 enext
= gen_reg_rtx (mode
);
31012 emit_insn (gen_mul (enext
, eprev
, eprev
));
31014 /* xnext = xprev + enext * xprev */
31015 xnext
= gen_reg_rtx (mode
);
31016 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
31022 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
31024 /* u = n * xprev */
31025 u
= gen_reg_rtx (mode
);
31026 emit_insn (gen_mul (u
, n
, xprev
));
31028 /* v = n - (d * u) */
31029 v
= gen_reg_rtx (mode
);
31030 rs6000_emit_nmsub (v
, d
, u
, n
);
31032 /* dst = (v * xprev) + u */
31033 rs6000_emit_madd (dst
, v
, xprev
, u
);
31036 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
31039 /* Newton-Raphson approximation of single/double-precision floating point
31040 rsqrt. Assumes no trapping math and finite arguments. */
31043 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
31045 machine_mode mode
= GET_MODE (src
);
31046 rtx x0
= gen_reg_rtx (mode
);
31047 rtx y
= gen_reg_rtx (mode
);
31049 /* Low precision estimates guarantee 5 bits of accuracy. High
31050 precision estimates guarantee 14 bits of accuracy. SFmode
31051 requires 23 bits of accuracy. DFmode requires 52 bits of
31052 accuracy. Each pass at least doubles the accuracy, leading
31053 to the following. */
31054 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
31055 if (mode
== DFmode
|| mode
== V2DFmode
)
31058 REAL_VALUE_TYPE dconst3_2
;
31061 enum insn_code code
= optab_handler (smul_optab
, mode
);
31062 insn_gen_fn gen_mul
= GEN_FCN (code
);
31064 gcc_assert (code
!= CODE_FOR_nothing
);
31066 /* Load up the constant 1.5 either as a scalar, or as a vector. */
31067 real_from_integer (&dconst3_2
, VOIDmode
, 3, SIGNED
);
31068 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
31070 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
31072 /* x0 = rsqrt estimate */
31073 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
31076 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
31077 rs6000_emit_msub (y
, src
, halfthree
, src
);
31079 for (i
= 0; i
< passes
; i
++)
31081 rtx x1
= gen_reg_rtx (mode
);
31082 rtx u
= gen_reg_rtx (mode
);
31083 rtx v
= gen_reg_rtx (mode
);
31085 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
31086 emit_insn (gen_mul (u
, x0
, x0
));
31087 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
31088 emit_insn (gen_mul (x1
, x0
, v
));
31092 emit_move_insn (dst
, x0
);
31096 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
31097 (Power7) targets. DST is the target, and SRC is the argument operand. */
31100 rs6000_emit_popcount (rtx dst
, rtx src
)
31102 machine_mode mode
= GET_MODE (dst
);
31105 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
31106 if (TARGET_POPCNTD
)
31108 if (mode
== SImode
)
31109 emit_insn (gen_popcntdsi2 (dst
, src
));
31111 emit_insn (gen_popcntddi2 (dst
, src
));
31115 tmp1
= gen_reg_rtx (mode
);
31117 if (mode
== SImode
)
31119 emit_insn (gen_popcntbsi2 (tmp1
, src
));
31120 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
31122 tmp2
= force_reg (SImode
, tmp2
);
31123 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
31127 emit_insn (gen_popcntbdi2 (tmp1
, src
));
31128 tmp2
= expand_mult (DImode
, tmp1
,
31129 GEN_INT ((HOST_WIDE_INT
)
31130 0x01010101 << 32 | 0x01010101),
31132 tmp2
= force_reg (DImode
, tmp2
);
31133 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
31138 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
31139 target, and SRC is the argument operand. */
31142 rs6000_emit_parity (rtx dst
, rtx src
)
31144 machine_mode mode
= GET_MODE (dst
);
31147 tmp
= gen_reg_rtx (mode
);
31149 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
31152 if (mode
== SImode
)
31154 emit_insn (gen_popcntbsi2 (tmp
, src
));
31155 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
31159 emit_insn (gen_popcntbdi2 (tmp
, src
));
31160 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
31165 if (mode
== SImode
)
31167 /* Is mult+shift >= shift+xor+shift+xor? */
31168 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
31170 rtx tmp1
, tmp2
, tmp3
, tmp4
;
31172 tmp1
= gen_reg_rtx (SImode
);
31173 emit_insn (gen_popcntbsi2 (tmp1
, src
));
31175 tmp2
= gen_reg_rtx (SImode
);
31176 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
31177 tmp3
= gen_reg_rtx (SImode
);
31178 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
31180 tmp4
= gen_reg_rtx (SImode
);
31181 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
31182 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
31185 rs6000_emit_popcount (tmp
, src
);
31186 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
31190 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
31191 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
31193 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
31195 tmp1
= gen_reg_rtx (DImode
);
31196 emit_insn (gen_popcntbdi2 (tmp1
, src
));
31198 tmp2
= gen_reg_rtx (DImode
);
31199 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
31200 tmp3
= gen_reg_rtx (DImode
);
31201 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
31203 tmp4
= gen_reg_rtx (DImode
);
31204 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
31205 tmp5
= gen_reg_rtx (DImode
);
31206 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
31208 tmp6
= gen_reg_rtx (DImode
);
31209 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
31210 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
31213 rs6000_emit_popcount (tmp
, src
);
31214 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
31218 /* Expand an Altivec constant permutation for little endian mode.
31219 There are two issues: First, the two input operands must be
31220 swapped so that together they form a double-wide array in LE
31221 order. Second, the vperm instruction has surprising behavior
31222 in LE mode: it interprets the elements of the source vectors
31223 in BE mode ("left to right") and interprets the elements of
31224 the destination vector in LE mode ("right to left"). To
31225 correct for this, we must subtract each element of the permute
31226 control vector from 31.
31228 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
31229 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
31230 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
31231 serve as the permute control vector. Then, in BE mode,
31235 places the desired result in vr9. However, in LE mode the
31236 vector contents will be
31238 vr10 = 00000003 00000002 00000001 00000000
31239 vr11 = 00000007 00000006 00000005 00000004
31241 The result of the vperm using the same permute control vector is
31243 vr9 = 05000000 07000000 01000000 03000000
31245 That is, the leftmost 4 bytes of vr10 are interpreted as the
31246 source for the rightmost 4 bytes of vr9, and so on.
31248 If we change the permute control vector to
31250 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
31258 vr9 = 00000006 00000004 00000002 00000000. */
31261 altivec_expand_vec_perm_const_le (rtx operands
[4])
31265 rtx constv
, unspec
;
31266 rtx target
= operands
[0];
31267 rtx op0
= operands
[1];
31268 rtx op1
= operands
[2];
31269 rtx sel
= operands
[3];
31271 /* Unpack and adjust the constant selector. */
31272 for (i
= 0; i
< 16; ++i
)
31274 rtx e
= XVECEXP (sel
, 0, i
);
31275 unsigned int elt
= 31 - (INTVAL (e
) & 31);
31276 perm
[i
] = GEN_INT (elt
);
31279 /* Expand to a permute, swapping the inputs and using the
31280 adjusted selector. */
31282 op0
= force_reg (V16QImode
, op0
);
31284 op1
= force_reg (V16QImode
, op1
);
31286 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
31287 constv
= force_reg (V16QImode
, constv
);
31288 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
31290 if (!REG_P (target
))
31292 rtx tmp
= gen_reg_rtx (V16QImode
);
31293 emit_move_insn (tmp
, unspec
);
31297 emit_move_insn (target
, unspec
);
31300 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
31301 permute control vector. But here it's not a constant, so we must
31302 generate a vector NAND or NOR to do the adjustment. */
31305 altivec_expand_vec_perm_le (rtx operands
[4])
31307 rtx notx
, iorx
, unspec
;
31308 rtx target
= operands
[0];
31309 rtx op0
= operands
[1];
31310 rtx op1
= operands
[2];
31311 rtx sel
= operands
[3];
31313 rtx norreg
= gen_reg_rtx (V16QImode
);
31314 machine_mode mode
= GET_MODE (target
);
31316 /* Get everything in regs so the pattern matches. */
31318 op0
= force_reg (mode
, op0
);
31320 op1
= force_reg (mode
, op1
);
31322 sel
= force_reg (V16QImode
, sel
);
31323 if (!REG_P (target
))
31324 tmp
= gen_reg_rtx (mode
);
31326 /* Invert the selector with a VNAND if available, else a VNOR.
31327 The VNAND is preferred for future fusion opportunities. */
31328 notx
= gen_rtx_NOT (V16QImode
, sel
);
31329 iorx
= (TARGET_P8_VECTOR
31330 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
31331 : gen_rtx_AND (V16QImode
, notx
, notx
));
31332 emit_insn (gen_rtx_SET (norreg
, iorx
));
31334 /* Permute with operands reversed and adjusted selector. */
31335 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
31338 /* Copy into target, possibly by way of a register. */
31339 if (!REG_P (target
))
31341 emit_move_insn (tmp
, unspec
);
31345 emit_move_insn (target
, unspec
);
31348 /* Expand an Altivec constant permutation. Return true if we match
31349 an efficient implementation; false to fall back to VPERM. */
31352 altivec_expand_vec_perm_const (rtx operands
[4])
31354 struct altivec_perm_insn
{
31355 HOST_WIDE_INT mask
;
31356 enum insn_code impl
;
31357 unsigned char perm
[16];
31359 static const struct altivec_perm_insn patterns
[] = {
31360 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
31361 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
31362 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
31363 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
31364 { OPTION_MASK_ALTIVEC
,
31365 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
31366 : CODE_FOR_altivec_vmrglb_direct
),
31367 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
31368 { OPTION_MASK_ALTIVEC
,
31369 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
31370 : CODE_FOR_altivec_vmrglh_direct
),
31371 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
31372 { OPTION_MASK_ALTIVEC
,
31373 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
31374 : CODE_FOR_altivec_vmrglw_direct
),
31375 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
31376 { OPTION_MASK_ALTIVEC
,
31377 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
31378 : CODE_FOR_altivec_vmrghb_direct
),
31379 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
31380 { OPTION_MASK_ALTIVEC
,
31381 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
31382 : CODE_FOR_altivec_vmrghh_direct
),
31383 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
31384 { OPTION_MASK_ALTIVEC
,
31385 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
31386 : CODE_FOR_altivec_vmrghw_direct
),
31387 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
31388 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
31389 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
31390 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
31391 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
31394 unsigned int i
, j
, elt
, which
;
31395 unsigned char perm
[16];
31396 rtx target
, op0
, op1
, sel
, x
;
31399 target
= operands
[0];
31404 /* Unpack the constant selector. */
31405 for (i
= which
= 0; i
< 16; ++i
)
31407 rtx e
= XVECEXP (sel
, 0, i
);
31408 elt
= INTVAL (e
) & 31;
31409 which
|= (elt
< 16 ? 1 : 2);
31413 /* Simplify the constant selector based on operands. */
31417 gcc_unreachable ();
31421 if (!rtx_equal_p (op0
, op1
))
31426 for (i
= 0; i
< 16; ++i
)
31438 /* Look for splat patterns. */
31443 for (i
= 0; i
< 16; ++i
)
31444 if (perm
[i
] != elt
)
31448 if (!BYTES_BIG_ENDIAN
)
31450 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
31456 for (i
= 0; i
< 16; i
+= 2)
31457 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
31461 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
31462 x
= gen_reg_rtx (V8HImode
);
31463 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
31465 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
31472 for (i
= 0; i
< 16; i
+= 4)
31474 || perm
[i
+ 1] != elt
+ 1
31475 || perm
[i
+ 2] != elt
+ 2
31476 || perm
[i
+ 3] != elt
+ 3)
31480 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
31481 x
= gen_reg_rtx (V4SImode
);
31482 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
31484 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
31490 /* Look for merge and pack patterns. */
31491 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
31495 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
31498 elt
= patterns
[j
].perm
[0];
31499 if (perm
[0] == elt
)
31501 else if (perm
[0] == elt
+ 16)
31505 for (i
= 1; i
< 16; ++i
)
31507 elt
= patterns
[j
].perm
[i
];
31509 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
31510 else if (one_vec
&& elt
>= 16)
31512 if (perm
[i
] != elt
)
31517 enum insn_code icode
= patterns
[j
].impl
;
31518 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
31519 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
31521 /* For little-endian, don't use vpkuwum and vpkuhum if the
31522 underlying vector type is not V4SI and V8HI, respectively.
31523 For example, using vpkuwum with a V8HI picks up the even
31524 halfwords (BE numbering) when the even halfwords (LE
31525 numbering) are what we need. */
31526 if (!BYTES_BIG_ENDIAN
31527 && icode
== CODE_FOR_altivec_vpkuwum_direct
31528 && ((GET_CODE (op0
) == REG
31529 && GET_MODE (op0
) != V4SImode
)
31530 || (GET_CODE (op0
) == SUBREG
31531 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
31533 if (!BYTES_BIG_ENDIAN
31534 && icode
== CODE_FOR_altivec_vpkuhum_direct
31535 && ((GET_CODE (op0
) == REG
31536 && GET_MODE (op0
) != V8HImode
)
31537 || (GET_CODE (op0
) == SUBREG
31538 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
31541 /* For little-endian, the two input operands must be swapped
31542 (or swapped back) to ensure proper right-to-left numbering
31544 if (swapped
^ !BYTES_BIG_ENDIAN
)
31545 std::swap (op0
, op1
);
31546 if (imode
!= V16QImode
)
31548 op0
= gen_lowpart (imode
, op0
);
31549 op1
= gen_lowpart (imode
, op1
);
31551 if (omode
== V16QImode
)
31554 x
= gen_reg_rtx (omode
);
31555 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
31556 if (omode
!= V16QImode
)
31557 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
31562 if (!BYTES_BIG_ENDIAN
)
31564 altivec_expand_vec_perm_const_le (operands
);
31571 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
31572 Return true if we match an efficient implementation. */
31575 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
31576 unsigned char perm0
, unsigned char perm1
)
31580 /* If both selectors come from the same operand, fold to single op. */
31581 if ((perm0
& 2) == (perm1
& 2))
31588 /* If both operands are equal, fold to simpler permutation. */
31589 if (rtx_equal_p (op0
, op1
))
31592 perm1
= (perm1
& 1) + 2;
31594 /* If the first selector comes from the second operand, swap. */
31595 else if (perm0
& 2)
31601 std::swap (op0
, op1
);
31603 /* If the second selector does not come from the second operand, fail. */
31604 else if ((perm1
& 2) == 0)
31608 if (target
!= NULL
)
31610 machine_mode vmode
, dmode
;
31613 vmode
= GET_MODE (target
);
31614 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
31615 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
31616 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
31617 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
31618 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
31619 emit_insn (gen_rtx_SET (target
, x
));
31625 rs6000_expand_vec_perm_const (rtx operands
[4])
31627 rtx target
, op0
, op1
, sel
;
31628 unsigned char perm0
, perm1
;
31630 target
= operands
[0];
31635 /* Unpack the constant selector. */
31636 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
31637 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
31639 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
31642 /* Test whether a constant permutation is supported. */
31645 rs6000_vectorize_vec_perm_const_ok (machine_mode vmode
,
31646 const unsigned char *sel
)
31648 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
31649 if (TARGET_ALTIVEC
)
31652 /* Check for ps_merge* or evmerge* insns. */
31653 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
31654 || (TARGET_SPE
&& vmode
== V2SImode
))
31656 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
31657 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
31658 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
31664 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
31667 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
31668 machine_mode vmode
, unsigned nelt
, rtx perm
[])
31670 machine_mode imode
;
31674 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
31676 imode
= GET_MODE_INNER (vmode
);
31677 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
31678 imode
= mode_for_vector (imode
, nelt
);
31681 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
31682 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
31684 emit_move_insn (target
, x
);
31687 /* Expand an extract even operation. */
31690 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
31692 machine_mode vmode
= GET_MODE (target
);
31693 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
31696 for (i
= 0; i
< nelt
; i
++)
31697 perm
[i
] = GEN_INT (i
* 2);
31699 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
31702 /* Expand a vector interleave operation. */
31705 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
31707 machine_mode vmode
= GET_MODE (target
);
31708 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
31711 high
= (highp
? 0 : nelt
/ 2);
31712 for (i
= 0; i
< nelt
/ 2; i
++)
31714 perm
[i
* 2] = GEN_INT (i
+ high
);
31715 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
31718 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
31721 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
31723 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
31725 HOST_WIDE_INT
hwi_scale (scale
);
31726 REAL_VALUE_TYPE r_pow
;
31727 rtvec v
= rtvec_alloc (2);
31729 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
31730 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
31731 elt
= CONST_DOUBLE_FROM_REAL_VALUE (r_pow
, DFmode
);
31732 RTVEC_ELT (v
, 0) = elt
;
31733 RTVEC_ELT (v
, 1) = elt
;
31734 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
31735 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
31738 /* Return an RTX representing where to find the function value of a
31739 function returning MODE. */
31741 rs6000_complex_function_value (machine_mode mode
)
31743 unsigned int regno
;
31745 machine_mode inner
= GET_MODE_INNER (mode
);
31746 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
31748 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31749 regno
= FP_ARG_RETURN
;
31752 regno
= GP_ARG_RETURN
;
31754 /* 32-bit is OK since it'll go in r3/r4. */
31755 if (TARGET_32BIT
&& inner_bytes
>= 4)
31756 return gen_rtx_REG (mode
, regno
);
31759 if (inner_bytes
>= 8)
31760 return gen_rtx_REG (mode
, regno
);
31762 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
31764 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
31765 GEN_INT (inner_bytes
));
31766 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
31769 /* Return an rtx describing a return value of MODE as a PARALLEL
31770 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
31771 stride REG_STRIDE. */
31774 rs6000_parallel_return (machine_mode mode
,
31775 int n_elts
, machine_mode elt_mode
,
31776 unsigned int regno
, unsigned int reg_stride
)
31778 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
31781 for (i
= 0; i
< n_elts
; i
++)
31783 rtx r
= gen_rtx_REG (elt_mode
, regno
);
31784 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
31785 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
31786 regno
+= reg_stride
;
31792 /* Target hook for TARGET_FUNCTION_VALUE.
31794 On the SPE, both FPs and vectors are returned in r3.
31796 On RS/6000 an integer value is in r3 and a floating-point value is in
31797 fp1, unless -msoft-float. */
31800 rs6000_function_value (const_tree valtype
,
31801 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
31802 bool outgoing ATTRIBUTE_UNUSED
)
31805 unsigned int regno
;
31806 machine_mode elt_mode
;
31809 /* Special handling for structs in darwin64. */
31811 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
31813 CUMULATIVE_ARGS valcum
;
31817 valcum
.fregno
= FP_ARG_MIN_REG
;
31818 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
31819 /* Do a trial code generation as if this were going to be passed as
31820 an argument; if any part goes in memory, we return NULL. */
31821 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
31824 /* Otherwise fall through to standard ABI rules. */
31827 mode
= TYPE_MODE (valtype
);
31829 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
31830 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
31832 int first_reg
, n_regs
;
31834 if (SCALAR_FLOAT_MODE_P (elt_mode
))
31836 /* _Decimal128 must use even/odd register pairs. */
31837 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31838 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
31842 first_reg
= ALTIVEC_ARG_RETURN
;
31846 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
31849 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
31850 if (TARGET_32BIT
&& TARGET_POWERPC64
)
31859 int count
= GET_MODE_SIZE (mode
) / 4;
31860 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
31863 if ((INTEGRAL_TYPE_P (valtype
)
31864 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
31865 || POINTER_TYPE_P (valtype
))
31866 mode
= TARGET_32BIT
? SImode
: DImode
;
31868 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31869 /* _Decimal128 must use an even/odd register pair. */
31870 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31871 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
31872 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
31873 regno
= FP_ARG_RETURN
;
31874 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
31875 && targetm
.calls
.split_complex_arg
)
31876 return rs6000_complex_function_value (mode
);
31877 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31878 return register is used in both cases, and we won't see V2DImode/V2DFmode
31879 for pure altivec, combine the two cases. */
31880 else if (TREE_CODE (valtype
) == VECTOR_TYPE
31881 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
31882 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
31883 regno
= ALTIVEC_ARG_RETURN
;
31884 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
31885 && (mode
== DFmode
|| mode
== DCmode
31886 || mode
== TFmode
|| mode
== TCmode
))
31887 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
31889 regno
= GP_ARG_RETURN
;
31891 return gen_rtx_REG (mode
, regno
);
31894 /* Define how to find the value returned by a library function
31895 assuming the value has mode MODE. */
31897 rs6000_libcall_value (machine_mode mode
)
31899 unsigned int regno
;
31901 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
31902 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
31903 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
31905 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
31906 /* _Decimal128 must use an even/odd register pair. */
31907 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
31908 else if (SCALAR_FLOAT_MODE_P (mode
)
31909 && TARGET_HARD_FLOAT
&& TARGET_FPRS
31910 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
31911 regno
= FP_ARG_RETURN
;
31912 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31913 return register is used in both cases, and we won't see V2DImode/V2DFmode
31914 for pure altivec, combine the two cases. */
31915 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
31916 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
31917 regno
= ALTIVEC_ARG_RETURN
;
31918 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
31919 return rs6000_complex_function_value (mode
);
31920 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
31921 && (mode
== DFmode
|| mode
== DCmode
31922 || mode
== TFmode
|| mode
== TCmode
))
31923 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
31925 regno
= GP_ARG_RETURN
;
31927 return gen_rtx_REG (mode
, regno
);
31931 /* Return true if we use LRA instead of reload pass. */
31933 rs6000_lra_p (void)
31935 return rs6000_lra_flag
;
31938 /* Given FROM and TO register numbers, say whether this elimination is allowed.
31939 Frame pointer elimination is automatically handled.
31941 For the RS/6000, if frame pointer elimination is being done, we would like
31942 to convert ap into fp, not sp.
31944 We need r30 if -mminimal-toc was specified, and there are constant pool
31948 rs6000_can_eliminate (const int from
, const int to
)
31950 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
31951 ? ! frame_pointer_needed
31952 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
31953 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
31957 /* Define the offset between two registers, FROM to be eliminated and its
31958 replacement TO, at the start of a routine. */
31960 rs6000_initial_elimination_offset (int from
, int to
)
31962 rs6000_stack_t
*info
= rs6000_stack_info ();
31963 HOST_WIDE_INT offset
;
31965 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31966 offset
= info
->push_p
? 0 : -info
->total_size
;
31967 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31969 offset
= info
->push_p
? 0 : -info
->total_size
;
31970 if (FRAME_GROWS_DOWNWARD
)
31971 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
31973 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31974 offset
= FRAME_GROWS_DOWNWARD
31975 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
31977 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
31978 offset
= info
->total_size
;
31979 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
31980 offset
= info
->push_p
? info
->total_size
: 0;
31981 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
31984 gcc_unreachable ();
31990 rs6000_dwarf_register_span (rtx reg
)
31994 unsigned regno
= REGNO (reg
);
31995 machine_mode mode
= GET_MODE (reg
);
31999 && (SPE_VECTOR_MODE (GET_MODE (reg
))
32000 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
32001 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
32006 regno
= REGNO (reg
);
32008 /* The duality of the SPE register size wreaks all kinds of havoc.
32009 This is a way of distinguishing r0 in 32-bits from r0 in
32011 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
32012 gcc_assert (words
<= 4);
32013 for (i
= 0; i
< words
; i
++, regno
++)
32015 if (BYTES_BIG_ENDIAN
)
32017 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
32018 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
32022 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
32023 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
32027 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
32030 /* Fill in sizes for SPE register high parts in table used by unwinder. */
32033 rs6000_init_dwarf_reg_sizes_extra (tree address
)
32038 machine_mode mode
= TYPE_MODE (char_type_node
);
32039 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
32040 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
32041 rtx value
= gen_int_mode (4, mode
);
32043 for (i
= FIRST_SPE_HIGH_REGNO
; i
< LAST_SPE_HIGH_REGNO
+1; i
++)
32045 int column
= DWARF_REG_TO_UNWIND_COLUMN
32046 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
32047 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
32049 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
32053 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
32056 machine_mode mode
= TYPE_MODE (char_type_node
);
32057 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
32058 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
32059 rtx value
= gen_int_mode (16, mode
);
32061 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
32062 The unwinder still needs to know the size of Altivec registers. */
32064 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
32066 int column
= DWARF_REG_TO_UNWIND_COLUMN
32067 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
32068 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
32070 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
32075 /* Map internal gcc register numbers to debug format register numbers.
32076 FORMAT specifies the type of debug register number to use:
32077 0 -- debug information, except for frame-related sections
32078 1 -- DWARF .debug_frame section
32079 2 -- DWARF .eh_frame section */
32082 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
32084 /* We never use the GCC internal number for SPE high registers.
32085 Those are mapped to the 1200..1231 range for all debug formats. */
32086 if (SPE_HIGH_REGNO_P (regno
))
32087 return regno
- FIRST_SPE_HIGH_REGNO
+ 1200;
32089 /* Except for the above, we use the internal number for non-DWARF
32090 debug information, and also for .eh_frame. */
32091 if ((format
== 0 && write_symbols
!= DWARF2_DEBUG
) || format
== 2)
32094 /* On some platforms, we use the standard DWARF register
32095 numbering for .debug_info and .debug_frame. */
32096 #ifdef RS6000_USE_DWARF_NUMBERING
32099 if (regno
== LR_REGNO
)
32101 if (regno
== CTR_REGNO
)
32103 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
32104 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
32105 The actual code emitted saves the whole of CR, so we map CR2_REGNO
32106 to the DWARF reg for CR. */
32107 if (format
== 1 && regno
== CR2_REGNO
)
32109 if (CR_REGNO_P (regno
))
32110 return regno
- CR0_REGNO
+ 86;
32111 if (regno
== CA_REGNO
)
32112 return 101; /* XER */
32113 if (ALTIVEC_REGNO_P (regno
))
32114 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
32115 if (regno
== VRSAVE_REGNO
)
32117 if (regno
== VSCR_REGNO
)
32119 if (regno
== SPE_ACC_REGNO
)
32121 if (regno
== SPEFSCR_REGNO
)
32127 /* target hook eh_return_filter_mode */
32128 static machine_mode
32129 rs6000_eh_return_filter_mode (void)
32131 return TARGET_32BIT
? SImode
: word_mode
;
32134 /* Target hook for scalar_mode_supported_p. */
32136 rs6000_scalar_mode_supported_p (machine_mode mode
)
32138 /* -m32 does not support TImode. This is the default, from
32139 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
32140 same ABI as for -m32. But default_scalar_mode_supported_p allows
32141 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
32142 for -mpowerpc64. */
32143 if (TARGET_32BIT
&& mode
== TImode
)
32146 if (DECIMAL_FLOAT_MODE_P (mode
))
32147 return default_decimal_float_supported_p ();
32149 return default_scalar_mode_supported_p (mode
);
32152 /* Target hook for vector_mode_supported_p. */
32154 rs6000_vector_mode_supported_p (machine_mode mode
)
32157 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
32160 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
32163 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
32170 /* Target hook for invalid_arg_for_unprototyped_fn. */
32171 static const char *
32172 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
32174 return (!rs6000_darwin64_abi
32176 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
32177 && (funcdecl
== NULL_TREE
32178 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
32179 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
32180 ? N_("AltiVec argument passed to unprototyped function")
32184 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
32185 setup by using __stack_chk_fail_local hidden function instead of
32186 calling __stack_chk_fail directly. Otherwise it is better to call
32187 __stack_chk_fail directly. */
32189 static tree ATTRIBUTE_UNUSED
32190 rs6000_stack_protect_fail (void)
32192 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
32193 ? default_hidden_stack_protect_fail ()
32194 : default_external_stack_protect_fail ();
32198 rs6000_final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
32199 int num_operands ATTRIBUTE_UNUSED
)
32201 if (rs6000_warn_cell_microcode
)
32204 int insn_code_number
= recog_memoized (insn
);
32205 location_t location
= INSN_LOCATION (insn
);
32207 /* Punt on insns we cannot recognize. */
32208 if (insn_code_number
< 0)
32211 temp
= get_insn_template (insn_code_number
, insn
);
32213 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
32214 warning_at (location
, OPT_mwarn_cell_microcode
,
32215 "emitting microcode insn %s\t[%s] #%d",
32216 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
32217 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
32218 warning_at (location
, OPT_mwarn_cell_microcode
,
32219 "emitting conditional microcode insn %s\t[%s] #%d",
32220 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
32224 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
32227 static unsigned HOST_WIDE_INT
32228 rs6000_asan_shadow_offset (void)
32230 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
32234 /* Mask options that we want to support inside of attribute((target)) and
32235 #pragma GCC target operations. Note, we do not include things like
32236 64/32-bit, endianess, hard/soft floating point, etc. that would have
32237 different calling sequences. */
32239 struct rs6000_opt_mask
{
32240 const char *name
; /* option name */
32241 HOST_WIDE_INT mask
; /* mask to set */
32242 bool invert
; /* invert sense of mask */
32243 bool valid_target
; /* option is a target option */
32246 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
32248 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
32249 { "cmpb", OPTION_MASK_CMPB
, false, true },
32250 { "crypto", OPTION_MASK_CRYPTO
, false, true },
32251 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
32252 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
32253 { "fprnd", OPTION_MASK_FPRND
, false, true },
32254 { "hard-dfp", OPTION_MASK_DFP
, false, true },
32255 { "htm", OPTION_MASK_HTM
, false, true },
32256 { "isel", OPTION_MASK_ISEL
, false, true },
32257 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
32258 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
32259 { "mulhw", OPTION_MASK_MULHW
, false, true },
32260 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
32261 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
32262 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
32263 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
32264 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
32265 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
32266 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
32267 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
32268 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
32269 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
32270 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
32271 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
32272 { "string", OPTION_MASK_STRING
, false, true },
32273 { "update", OPTION_MASK_NO_UPDATE
, true , true },
32274 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, true },
32275 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, true },
32276 { "vsx", OPTION_MASK_VSX
, false, true },
32277 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
32278 #ifdef OPTION_MASK_64BIT
32280 { "aix64", OPTION_MASK_64BIT
, false, false },
32281 { "aix32", OPTION_MASK_64BIT
, true, false },
32283 { "64", OPTION_MASK_64BIT
, false, false },
32284 { "32", OPTION_MASK_64BIT
, true, false },
32287 #ifdef OPTION_MASK_EABI
32288 { "eabi", OPTION_MASK_EABI
, false, false },
32290 #ifdef OPTION_MASK_LITTLE_ENDIAN
32291 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
32292 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
32294 #ifdef OPTION_MASK_RELOCATABLE
32295 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
32297 #ifdef OPTION_MASK_STRICT_ALIGN
32298 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
32300 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
32301 { "string", OPTION_MASK_STRING
, false, false },
32304 /* Builtin mask mapping for printing the flags. */
32305 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
32307 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
32308 { "vsx", RS6000_BTM_VSX
, false, false },
32309 { "spe", RS6000_BTM_SPE
, false, false },
32310 { "paired", RS6000_BTM_PAIRED
, false, false },
32311 { "fre", RS6000_BTM_FRE
, false, false },
32312 { "fres", RS6000_BTM_FRES
, false, false },
32313 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
32314 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
32315 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
32316 { "cell", RS6000_BTM_CELL
, false, false },
32317 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
32318 { "crypto", RS6000_BTM_CRYPTO
, false, false },
32319 { "htm", RS6000_BTM_HTM
, false, false },
32320 { "hard-dfp", RS6000_BTM_DFP
, false, false },
32321 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
32322 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
32325 /* Option variables that we want to support inside attribute((target)) and
32326 #pragma GCC target operations. */
32328 struct rs6000_opt_var
{
32329 const char *name
; /* option name */
32330 size_t global_offset
; /* offset of the option in global_options. */
32331 size_t target_offset
; /* offset of the option in target optiosn. */
32334 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
32337 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
32338 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
32339 { "avoid-indexed-addresses",
32340 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
32341 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
32343 offsetof (struct gcc_options
, x_rs6000_paired_float
),
32344 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
32346 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
32347 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
32348 { "optimize-swaps",
32349 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
32350 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
32351 { "allow-movmisalign",
32352 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
32353 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
32354 { "allow-df-permute",
32355 offsetof (struct gcc_options
, x_TARGET_ALLOW_DF_PERMUTE
),
32356 offsetof (struct cl_target_option
, x_TARGET_ALLOW_DF_PERMUTE
), },
32358 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
32359 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
32361 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
32362 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
32363 { "align-branch-targets",
32364 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
32365 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
32366 { "vectorize-builtins",
32367 offsetof (struct gcc_options
, x_TARGET_VECTORIZE_BUILTINS
),
32368 offsetof (struct cl_target_option
, x_TARGET_VECTORIZE_BUILTINS
), },
32370 offsetof (struct gcc_options
, x_tls_markers
),
32371 offsetof (struct cl_target_option
, x_tls_markers
), },
32373 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
32374 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
32376 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
32377 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
32378 { "gen-cell-microcode",
32379 offsetof (struct gcc_options
, x_rs6000_gen_cell_microcode
),
32380 offsetof (struct cl_target_option
, x_rs6000_gen_cell_microcode
), },
32381 { "warn-cell-microcode",
32382 offsetof (struct gcc_options
, x_rs6000_warn_cell_microcode
),
32383 offsetof (struct cl_target_option
, x_rs6000_warn_cell_microcode
), },
32386 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
32387 parsing. Return true if there were no errors. */
32390 rs6000_inner_target_options (tree args
, bool attr_p
)
32394 if (args
== NULL_TREE
)
32397 else if (TREE_CODE (args
) == STRING_CST
)
32399 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
32402 while ((q
= strtok (p
, ",")) != NULL
)
32404 bool error_p
= false;
32405 bool not_valid_p
= false;
32406 const char *cpu_opt
= NULL
;
32409 if (strncmp (q
, "cpu=", 4) == 0)
32411 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
32412 if (cpu_index
>= 0)
32413 rs6000_cpu_index
= cpu_index
;
32420 else if (strncmp (q
, "tune=", 5) == 0)
32422 int tune_index
= rs6000_cpu_name_lookup (q
+5);
32423 if (tune_index
>= 0)
32424 rs6000_tune_index
= tune_index
;
32434 bool invert
= false;
32438 if (strncmp (r
, "no-", 3) == 0)
32444 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
32445 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
32447 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
32449 if (!rs6000_opt_masks
[i
].valid_target
)
32450 not_valid_p
= true;
32454 rs6000_isa_flags_explicit
|= mask
;
32456 /* VSX needs altivec, so -mvsx automagically sets
32457 altivec and disables -mavoid-indexed-addresses. */
32460 if (mask
== OPTION_MASK_VSX
)
32462 mask
|= OPTION_MASK_ALTIVEC
;
32463 TARGET_AVOID_XFORM
= 0;
32467 if (rs6000_opt_masks
[i
].invert
)
32471 rs6000_isa_flags
&= ~mask
;
32473 rs6000_isa_flags
|= mask
;
32478 if (error_p
&& !not_valid_p
)
32480 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
32481 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
32483 size_t j
= rs6000_opt_vars
[i
].global_offset
;
32484 *((int *) ((char *)&global_options
+ j
)) = !invert
;
32486 not_valid_p
= false;
32494 const char *eprefix
, *esuffix
;
32499 eprefix
= "__attribute__((__target__(";
32504 eprefix
= "#pragma GCC target ";
32509 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
32511 else if (not_valid_p
)
32512 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
32514 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
32519 else if (TREE_CODE (args
) == TREE_LIST
)
32523 tree value
= TREE_VALUE (args
);
32526 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
32530 args
= TREE_CHAIN (args
);
32532 while (args
!= NULL_TREE
);
32536 gcc_unreachable ();
32541 /* Print out the target options as a list for -mdebug=target. */
32544 rs6000_debug_target_options (tree args
, const char *prefix
)
32546 if (args
== NULL_TREE
)
32547 fprintf (stderr
, "%s<NULL>", prefix
);
32549 else if (TREE_CODE (args
) == STRING_CST
)
32551 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
32554 while ((q
= strtok (p
, ",")) != NULL
)
32557 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
32562 else if (TREE_CODE (args
) == TREE_LIST
)
32566 tree value
= TREE_VALUE (args
);
32569 rs6000_debug_target_options (value
, prefix
);
32572 args
= TREE_CHAIN (args
);
32574 while (args
!= NULL_TREE
);
32578 gcc_unreachable ();
32584 /* Hook to validate attribute((target("..."))). */
32587 rs6000_valid_attribute_p (tree fndecl
,
32588 tree
ARG_UNUSED (name
),
32592 struct cl_target_option cur_target
;
32594 tree old_optimize
= build_optimization_node (&global_options
);
32595 tree new_target
, new_optimize
;
32596 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
32598 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
32600 if (TARGET_DEBUG_TARGET
)
32602 tree tname
= DECL_NAME (fndecl
);
32603 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
32605 fprintf (stderr
, "function: %.*s\n",
32606 (int) IDENTIFIER_LENGTH (tname
),
32607 IDENTIFIER_POINTER (tname
));
32609 fprintf (stderr
, "function: unknown\n");
32611 fprintf (stderr
, "args:");
32612 rs6000_debug_target_options (args
, " ");
32613 fprintf (stderr
, "\n");
32616 fprintf (stderr
, "flags: 0x%x\n", flags
);
32618 fprintf (stderr
, "--------------------\n");
32621 old_optimize
= build_optimization_node (&global_options
);
32622 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
32624 /* If the function changed the optimization levels as well as setting target
32625 options, start with the optimizations specified. */
32626 if (func_optimize
&& func_optimize
!= old_optimize
)
32627 cl_optimization_restore (&global_options
,
32628 TREE_OPTIMIZATION (func_optimize
));
32630 /* The target attributes may also change some optimization flags, so update
32631 the optimization options if necessary. */
32632 cl_target_option_save (&cur_target
, &global_options
);
32633 rs6000_cpu_index
= rs6000_tune_index
= -1;
32634 ret
= rs6000_inner_target_options (args
, true);
32636 /* Set up any additional state. */
32639 ret
= rs6000_option_override_internal (false);
32640 new_target
= build_target_option_node (&global_options
);
32645 new_optimize
= build_optimization_node (&global_options
);
32652 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
32654 if (old_optimize
!= new_optimize
)
32655 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
32658 cl_target_option_restore (&global_options
, &cur_target
);
32660 if (old_optimize
!= new_optimize
)
32661 cl_optimization_restore (&global_options
,
32662 TREE_OPTIMIZATION (old_optimize
));
32668 /* Hook to validate the current #pragma GCC target and set the state, and
32669 update the macros based on what was changed. If ARGS is NULL, then
32670 POP_TARGET is used to reset the options. */
32673 rs6000_pragma_target_parse (tree args
, tree pop_target
)
32675 tree prev_tree
= build_target_option_node (&global_options
);
32677 struct cl_target_option
*prev_opt
, *cur_opt
;
32678 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
32679 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
32681 if (TARGET_DEBUG_TARGET
)
32683 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
32684 fprintf (stderr
, "args:");
32685 rs6000_debug_target_options (args
, " ");
32686 fprintf (stderr
, "\n");
32690 fprintf (stderr
, "pop_target:\n");
32691 debug_tree (pop_target
);
32694 fprintf (stderr
, "pop_target: <NULL>\n");
32696 fprintf (stderr
, "--------------------\n");
32701 cur_tree
= ((pop_target
)
32703 : target_option_default_node
);
32704 cl_target_option_restore (&global_options
,
32705 TREE_TARGET_OPTION (cur_tree
));
32709 rs6000_cpu_index
= rs6000_tune_index
= -1;
32710 if (!rs6000_inner_target_options (args
, false)
32711 || !rs6000_option_override_internal (false)
32712 || (cur_tree
= build_target_option_node (&global_options
))
32715 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
32716 fprintf (stderr
, "invalid pragma\n");
32722 target_option_current_node
= cur_tree
;
32724 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
32725 change the macros that are defined. */
32726 if (rs6000_target_modify_macros_ptr
)
32728 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
32729 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
32730 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
32732 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
32733 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
32734 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
32736 diff_bumask
= (prev_bumask
^ cur_bumask
);
32737 diff_flags
= (prev_flags
^ cur_flags
);
32739 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
32741 /* Delete old macros. */
32742 rs6000_target_modify_macros_ptr (false,
32743 prev_flags
& diff_flags
,
32744 prev_bumask
& diff_bumask
);
32746 /* Define new macros. */
32747 rs6000_target_modify_macros_ptr (true,
32748 cur_flags
& diff_flags
,
32749 cur_bumask
& diff_bumask
);
32757 /* Remember the last target of rs6000_set_current_function. */
32758 static GTY(()) tree rs6000_previous_fndecl
;
32760 /* Establish appropriate back-end context for processing the function
32761 FNDECL. The argument might be NULL to indicate processing at top
32762 level, outside of any function scope. */
32764 rs6000_set_current_function (tree fndecl
)
32766 tree old_tree
= (rs6000_previous_fndecl
32767 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
32770 tree new_tree
= (fndecl
32771 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
32774 if (TARGET_DEBUG_TARGET
)
32776 bool print_final
= false;
32777 fprintf (stderr
, "\n==================== rs6000_set_current_function");
32780 fprintf (stderr
, ", fndecl %s (%p)",
32781 (DECL_NAME (fndecl
)
32782 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
32783 : "<unknown>"), (void *)fndecl
);
32785 if (rs6000_previous_fndecl
)
32786 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
32788 fprintf (stderr
, "\n");
32791 fprintf (stderr
, "\nnew fndecl target specific options:\n");
32792 debug_tree (new_tree
);
32793 print_final
= true;
32798 fprintf (stderr
, "\nold fndecl target specific options:\n");
32799 debug_tree (old_tree
);
32800 print_final
= true;
32804 fprintf (stderr
, "--------------------\n");
32807 /* Only change the context if the function changes. This hook is called
32808 several times in the course of compiling a function, and we don't want to
32809 slow things down too much or call target_reinit when it isn't safe. */
32810 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
32812 rs6000_previous_fndecl
= fndecl
;
32813 if (old_tree
== new_tree
)
32816 else if (new_tree
&& new_tree
!= target_option_default_node
)
32818 cl_target_option_restore (&global_options
,
32819 TREE_TARGET_OPTION (new_tree
));
32820 if (TREE_TARGET_GLOBALS (new_tree
))
32821 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
32823 TREE_TARGET_GLOBALS (new_tree
)
32824 = save_target_globals_default_opts ();
32827 else if (old_tree
&& old_tree
!= target_option_default_node
)
32829 new_tree
= target_option_current_node
;
32830 cl_target_option_restore (&global_options
,
32831 TREE_TARGET_OPTION (new_tree
));
32832 if (TREE_TARGET_GLOBALS (new_tree
))
32833 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
32834 else if (new_tree
== target_option_default_node
)
32835 restore_target_globals (&default_target_globals
);
32837 TREE_TARGET_GLOBALS (new_tree
)
32838 = save_target_globals_default_opts ();
32844 /* Save the current options */
32847 rs6000_function_specific_save (struct cl_target_option
*ptr
,
32848 struct gcc_options
*opts
)
32850 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
32851 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
32854 /* Restore the current options */
32857 rs6000_function_specific_restore (struct gcc_options
*opts
,
32858 struct cl_target_option
*ptr
)
32861 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
32862 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
32863 (void) rs6000_option_override_internal (false);
32866 /* Print the current options */
32869 rs6000_function_specific_print (FILE *file
, int indent
,
32870 struct cl_target_option
*ptr
)
32872 rs6000_print_isa_options (file
, indent
, "Isa options set",
32873 ptr
->x_rs6000_isa_flags
);
32875 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
32876 ptr
->x_rs6000_isa_flags_explicit
);
32879 /* Helper function to print the current isa or misc options on a line. */
32882 rs6000_print_options_internal (FILE *file
,
32884 const char *string
,
32885 HOST_WIDE_INT flags
,
32886 const char *prefix
,
32887 const struct rs6000_opt_mask
*opts
,
32888 size_t num_elements
)
32891 size_t start_column
= 0;
32893 size_t max_column
= 76;
32894 const char *comma
= "";
32897 start_column
+= fprintf (file
, "%*s", indent
, "");
32901 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
32905 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
32907 /* Print the various mask options. */
32908 cur_column
= start_column
;
32909 for (i
= 0; i
< num_elements
; i
++)
32911 if ((flags
& opts
[i
].mask
) != 0)
32913 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
32914 size_t len
= (strlen (comma
)
32917 + strlen (rs6000_opt_masks
[i
].name
));
32920 if (cur_column
> max_column
)
32922 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
32923 cur_column
= start_column
+ len
;
32927 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
32928 rs6000_opt_masks
[i
].name
);
32929 flags
&= ~ opts
[i
].mask
;
32934 fputs ("\n", file
);
32937 /* Helper function to print the current isa options on a line. */
32940 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
32941 HOST_WIDE_INT flags
)
32943 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
32944 &rs6000_opt_masks
[0],
32945 ARRAY_SIZE (rs6000_opt_masks
));
32949 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
32950 HOST_WIDE_INT flags
)
32952 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
32953 &rs6000_builtin_mask_names
[0],
32954 ARRAY_SIZE (rs6000_builtin_mask_names
));
32958 /* Hook to determine if one function can safely inline another. */
32961 rs6000_can_inline_p (tree caller
, tree callee
)
32964 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
32965 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
32967 /* If callee has no option attributes, then it is ok to inline. */
32971 /* If caller has no option attributes, but callee does then it is not ok to
32973 else if (!caller_tree
)
32978 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
32979 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
32981 /* Callee's options should a subset of the caller's, i.e. a vsx function
32982 can inline an altivec function but a non-vsx function can't inline a
32984 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
32985 == callee_opts
->x_rs6000_isa_flags
)
32989 if (TARGET_DEBUG_TARGET
)
32990 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
32991 (DECL_NAME (caller
)
32992 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
32994 (DECL_NAME (callee
)
32995 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
32997 (ret
? "can" : "cannot"));
33002 /* Allocate a stack temp and fixup the address so it meets the particular
33003 memory requirements (either offetable or REG+REG addressing). */
33006 rs6000_allocate_stack_temp (machine_mode mode
,
33007 bool offsettable_p
,
33010 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
33011 rtx addr
= XEXP (stack
, 0);
33012 int strict_p
= (reload_in_progress
|| reload_completed
);
33014 if (!legitimate_indirect_address_p (addr
, strict_p
))
33017 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
33018 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
33020 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
33021 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
33027 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
33028 to such a form to deal with memory reference instructions like STFIWX that
33029 only take reg+reg addressing. */
33032 rs6000_address_for_fpconvert (rtx x
)
33034 int strict_p
= (reload_in_progress
|| reload_completed
);
33037 gcc_assert (MEM_P (x
));
33038 addr
= XEXP (x
, 0);
33039 if (! legitimate_indirect_address_p (addr
, strict_p
)
33040 && ! legitimate_indexed_address_p (addr
, strict_p
))
33042 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
33044 rtx reg
= XEXP (addr
, 0);
33045 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
33046 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
33047 gcc_assert (REG_P (reg
));
33048 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
33051 else if (GET_CODE (addr
) == PRE_MODIFY
)
33053 rtx reg
= XEXP (addr
, 0);
33054 rtx expr
= XEXP (addr
, 1);
33055 gcc_assert (REG_P (reg
));
33056 gcc_assert (GET_CODE (expr
) == PLUS
);
33057 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
33061 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
33067 /* Given a memory reference, if it is not in the form for altivec memory
33068 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
33069 convert to the altivec format. */
33072 rs6000_address_for_altivec (rtx x
)
33074 gcc_assert (MEM_P (x
));
33075 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
33077 rtx addr
= XEXP (x
, 0);
33078 int strict_p
= (reload_in_progress
|| reload_completed
);
33080 if (!legitimate_indexed_address_p (addr
, strict_p
)
33081 && !legitimate_indirect_address_p (addr
, strict_p
))
33082 addr
= copy_to_mode_reg (Pmode
, addr
);
33084 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
33085 x
= change_address (x
, GET_MODE (x
), addr
);
33091 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
33093 On the RS/6000, all integer constants are acceptable, most won't be valid
33094 for particular insns, though. Only easy FP constants are acceptable. */
33097 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
33099 if (TARGET_ELF
&& tls_referenced_p (x
))
33102 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
33103 || GET_MODE (x
) == VOIDmode
33104 || (TARGET_POWERPC64
&& mode
== DImode
)
33105 || easy_fp_constant (x
, mode
)
33106 || easy_vector_constant (x
, mode
));
33110 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
33113 chain_already_loaded (rtx_insn
*last
)
33115 for (; last
!= NULL
; last
= PREV_INSN (last
))
33117 if (NONJUMP_INSN_P (last
))
33119 rtx patt
= PATTERN (last
);
33121 if (GET_CODE (patt
) == SET
)
33123 rtx lhs
= XEXP (patt
, 0);
33125 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
33133 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
33136 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
33138 const bool direct_call_p
33139 = GET_CODE (func_desc
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (func_desc
);
33140 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
33141 rtx toc_load
= NULL_RTX
;
33142 rtx toc_restore
= NULL_RTX
;
33144 rtx abi_reg
= NULL_RTX
;
33149 /* Handle longcall attributes. */
33150 if (INTVAL (cookie
) & CALL_LONG
)
33151 func_desc
= rs6000_longcall_ref (func_desc
);
33153 /* Handle indirect calls. */
33154 if (GET_CODE (func_desc
) != SYMBOL_REF
33155 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
33157 /* Save the TOC into its reserved slot before the call,
33158 and prepare to restore it after the call. */
33159 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
33160 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
33161 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
33162 gen_rtx_PLUS (Pmode
, stack_ptr
,
33163 stack_toc_offset
));
33164 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
33165 gen_rtvec (1, stack_toc_offset
),
33167 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
33169 /* Can we optimize saving the TOC in the prologue or
33170 do we need to do it at every call? */
33171 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
33172 cfun
->machine
->save_toc_in_prologue
= true;
33175 MEM_VOLATILE_P (stack_toc_mem
) = 1;
33176 emit_move_insn (stack_toc_mem
, toc_reg
);
33179 if (DEFAULT_ABI
== ABI_ELFv2
)
33181 /* A function pointer in the ELFv2 ABI is just a plain address, but
33182 the ABI requires it to be loaded into r12 before the call. */
33183 func_addr
= gen_rtx_REG (Pmode
, 12);
33184 emit_move_insn (func_addr
, func_desc
);
33185 abi_reg
= func_addr
;
33189 /* A function pointer under AIX is a pointer to a data area whose
33190 first word contains the actual address of the function, whose
33191 second word contains a pointer to its TOC, and whose third word
33192 contains a value to place in the static chain register (r11).
33193 Note that if we load the static chain, our "trampoline" need
33194 not have any executable code. */
33196 /* Load up address of the actual function. */
33197 func_desc
= force_reg (Pmode
, func_desc
);
33198 func_addr
= gen_reg_rtx (Pmode
);
33199 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
33201 /* Prepare to load the TOC of the called function. Note that the
33202 TOC load must happen immediately before the actual call so
33203 that unwinding the TOC registers works correctly. See the
33204 comment in frob_update_context. */
33205 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
33206 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
33207 gen_rtx_PLUS (Pmode
, func_desc
,
33209 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
33211 /* If we have a static chain, load it up. But, if the call was
33212 originally direct, the 3rd word has not been written since no
33213 trampoline has been built, so we ought not to load it, lest we
33214 override a static chain value. */
33216 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
33217 && !chain_already_loaded (get_current_sequence ()->next
->last
))
33219 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
33220 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
33221 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
33222 gen_rtx_PLUS (Pmode
, func_desc
,
33224 emit_move_insn (sc_reg
, func_sc_mem
);
33231 /* Direct calls use the TOC: for local calls, the callee will
33232 assume the TOC register is set; for non-local calls, the
33233 PLT stub needs the TOC register. */
33235 func_addr
= func_desc
;
33238 /* Create the call. */
33239 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
33240 if (value
!= NULL_RTX
)
33241 call
[0] = gen_rtx_SET (value
, call
[0]);
33245 call
[n_call
++] = toc_load
;
33247 call
[n_call
++] = toc_restore
;
33249 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
33251 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
33252 insn
= emit_call_insn (insn
);
33254 /* Mention all registers defined by the ABI to hold information
33255 as uses in CALL_INSN_FUNCTION_USAGE. */
33257 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
33260 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
33263 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
33268 gcc_assert (INTVAL (cookie
) == 0);
33270 /* Create the call. */
33271 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
33272 if (value
!= NULL_RTX
)
33273 call
[0] = gen_rtx_SET (value
, call
[0]);
33275 call
[1] = simple_return_rtx
;
33277 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
33278 insn
= emit_call_insn (insn
);
33280 /* Note use of the TOC register. */
33281 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
33282 /* We need to also mark a use of the link register since the function we
33283 sibling-call to will use it to return to our caller. */
33284 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
33287 /* Return whether we need to always update the saved TOC pointer when we update
33288 the stack pointer. */
33291 rs6000_save_toc_in_prologue_p (void)
33293 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
33296 #ifdef HAVE_GAS_HIDDEN
33297 # define USE_HIDDEN_LINKONCE 1
33299 # define USE_HIDDEN_LINKONCE 0
33302 /* Fills in the label name that should be used for a 476 link stack thunk. */
33305 get_ppc476_thunk_name (char name
[32])
33307 gcc_assert (TARGET_LINK_STACK
);
33309 if (USE_HIDDEN_LINKONCE
)
33310 sprintf (name
, "__ppc476.get_thunk");
33312 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
33315 /* This function emits the simple thunk routine that is used to preserve
33316 the link stack on the 476 cpu. */
33318 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
33320 rs6000_code_end (void)
33325 if (!TARGET_LINK_STACK
)
33328 get_ppc476_thunk_name (name
);
33330 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
33331 build_function_type_list (void_type_node
, NULL_TREE
));
33332 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
33333 NULL_TREE
, void_type_node
);
33334 TREE_PUBLIC (decl
) = 1;
33335 TREE_STATIC (decl
) = 1;
33338 if (USE_HIDDEN_LINKONCE
)
33340 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
33341 targetm
.asm_out
.unique_section (decl
, 0);
33342 switch_to_section (get_named_section (decl
, NULL
, 0));
33343 DECL_WEAK (decl
) = 1;
33344 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
33345 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
33346 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
33347 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
33352 switch_to_section (text_section
);
33353 ASM_OUTPUT_LABEL (asm_out_file
, name
);
33356 DECL_INITIAL (decl
) = make_node (BLOCK
);
33357 current_function_decl
= decl
;
33358 init_function_start (decl
);
33359 first_function_block_is_cold
= false;
33360 /* Make sure unwind info is emitted for the thunk if needed. */
33361 final_start_function (emit_barrier (), asm_out_file
, 1);
33363 fputs ("\tblr\n", asm_out_file
);
33365 final_end_function ();
33366 init_insn_lengths ();
33367 free_after_compilation (cfun
);
33369 current_function_decl
= NULL
;
33372 /* Add r30 to hard reg set if the prologue sets it up and it is not
33373 pic_offset_table_rtx. */
33376 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
33378 if (!TARGET_SINGLE_PIC_BASE
33380 && TARGET_MINIMAL_TOC
33381 && get_pool_size () != 0)
33382 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
33386 /* Helper function for rs6000_split_logical to emit a logical instruction after
33387 spliting the operation to single GPR registers.
33389 DEST is the destination register.
33390 OP1 and OP2 are the input source registers.
33391 CODE is the base operation (AND, IOR, XOR, NOT).
33392 MODE is the machine mode.
33393 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
33394 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
33395 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
33398 rs6000_split_logical_inner (rtx dest
,
33401 enum rtx_code code
,
33403 bool complement_final_p
,
33404 bool complement_op1_p
,
33405 bool complement_op2_p
)
33409 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
33410 if (op2
&& GET_CODE (op2
) == CONST_INT
33411 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
33412 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
33414 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
33415 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
33417 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
33422 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
33426 else if (value
== mask
)
33428 if (!rtx_equal_p (dest
, op1
))
33429 emit_insn (gen_rtx_SET (dest
, op1
));
33434 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
33435 into separate ORI/ORIS or XORI/XORIS instrucitons. */
33436 else if (code
== IOR
|| code
== XOR
)
33440 if (!rtx_equal_p (dest
, op1
))
33441 emit_insn (gen_rtx_SET (dest
, op1
));
33447 if (code
== AND
&& mode
== SImode
33448 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
33450 emit_insn (gen_andsi3 (dest
, op1
, op2
));
33454 if (complement_op1_p
)
33455 op1
= gen_rtx_NOT (mode
, op1
);
33457 if (complement_op2_p
)
33458 op2
= gen_rtx_NOT (mode
, op2
);
33460 /* For canonical RTL, if only one arm is inverted it is the first. */
33461 if (!complement_op1_p
&& complement_op2_p
)
33462 std::swap (op1
, op2
);
33464 bool_rtx
= ((code
== NOT
)
33465 ? gen_rtx_NOT (mode
, op1
)
33466 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
33468 if (complement_final_p
)
33469 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
33471 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
33474 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
33475 operations are split immediately during RTL generation to allow for more
33476 optimizations of the AND/IOR/XOR.
33478 OPERANDS is an array containing the destination and two input operands.
33479 CODE is the base operation (AND, IOR, XOR, NOT).
33480 MODE is the machine mode.
33481 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
33482 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
33483 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
33484 CLOBBER_REG is either NULL or a scratch register of type CC to allow
33485 formation of the AND instructions. */
33488 rs6000_split_logical_di (rtx operands
[3],
33489 enum rtx_code code
,
33490 bool complement_final_p
,
33491 bool complement_op1_p
,
33492 bool complement_op2_p
)
33494 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
33495 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
33496 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
33497 enum hi_lo
{ hi
= 0, lo
= 1 };
33498 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
33501 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
33502 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
33503 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
33504 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
33507 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
33510 if (GET_CODE (operands
[2]) != CONST_INT
)
33512 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
33513 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
33517 HOST_WIDE_INT value
= INTVAL (operands
[2]);
33518 HOST_WIDE_INT value_hi_lo
[2];
33520 gcc_assert (!complement_final_p
);
33521 gcc_assert (!complement_op1_p
);
33522 gcc_assert (!complement_op2_p
);
33524 value_hi_lo
[hi
] = value
>> 32;
33525 value_hi_lo
[lo
] = value
& lower_32bits
;
33527 for (i
= 0; i
< 2; i
++)
33529 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
33531 if (sub_value
& sign_bit
)
33532 sub_value
|= upper_32bits
;
33534 op2_hi_lo
[i
] = GEN_INT (sub_value
);
33536 /* If this is an AND instruction, check to see if we need to load
33537 the value in a register. */
33538 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
33539 && !and_operand (op2_hi_lo
[i
], SImode
))
33540 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
33545 for (i
= 0; i
< 2; i
++)
33547 /* Split large IOR/XOR operations. */
33548 if ((code
== IOR
|| code
== XOR
)
33549 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
33550 && !complement_final_p
33551 && !complement_op1_p
33552 && !complement_op2_p
33553 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
33555 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
33556 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
33557 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
33558 rtx tmp
= gen_reg_rtx (SImode
);
33560 /* Make sure the constant is sign extended. */
33561 if ((hi_16bits
& sign_bit
) != 0)
33562 hi_16bits
|= upper_32bits
;
33564 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
33565 code
, SImode
, false, false, false);
33567 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
33568 code
, SImode
, false, false, false);
33571 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
33572 code
, SImode
, complement_final_p
,
33573 complement_op1_p
, complement_op2_p
);
33579 /* Split the insns that make up boolean operations operating on multiple GPR
33580 registers. The boolean MD patterns ensure that the inputs either are
33581 exactly the same as the output registers, or there is no overlap.
33583 OPERANDS is an array containing the destination and two input operands.
33584 CODE is the base operation (AND, IOR, XOR, NOT).
33585 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
33586 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
33587 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
33590 rs6000_split_logical (rtx operands
[3],
33591 enum rtx_code code
,
33592 bool complement_final_p
,
33593 bool complement_op1_p
,
33594 bool complement_op2_p
)
33596 machine_mode mode
= GET_MODE (operands
[0]);
33597 machine_mode sub_mode
;
33599 int sub_size
, regno0
, regno1
, nregs
, i
;
33601 /* If this is DImode, use the specialized version that can run before
33602 register allocation. */
33603 if (mode
== DImode
&& !TARGET_POWERPC64
)
33605 rs6000_split_logical_di (operands
, code
, complement_final_p
,
33606 complement_op1_p
, complement_op2_p
);
33612 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
33613 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
33614 sub_size
= GET_MODE_SIZE (sub_mode
);
33615 regno0
= REGNO (op0
);
33616 regno1
= REGNO (op1
);
33618 gcc_assert (reload_completed
);
33619 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
33620 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
33622 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
33623 gcc_assert (nregs
> 1);
33625 if (op2
&& REG_P (op2
))
33626 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
33628 for (i
= 0; i
< nregs
; i
++)
33630 int offset
= i
* sub_size
;
33631 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
33632 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
33633 rtx sub_op2
= ((code
== NOT
)
33635 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
33637 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
33638 complement_final_p
, complement_op1_p
,
33646 /* Return true if the peephole2 can combine a load involving a combination of
33647 an addis instruction and a load with an offset that can be fused together on
33651 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
33652 rtx addis_value
, /* addis value. */
33653 rtx target
, /* target register that is loaded. */
33654 rtx mem
) /* bottom part of the memory addr. */
33659 /* Validate arguments. */
33660 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
33663 if (!base_reg_operand (target
, GET_MODE (target
)))
33666 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
33669 /* Allow sign/zero extension. */
33670 if (GET_CODE (mem
) == ZERO_EXTEND
33671 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
33672 mem
= XEXP (mem
, 0);
33677 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
33680 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
33681 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
33684 /* Validate that the register used to load the high value is either the
33685 register being loaded, or we can safely replace its use.
33687 This function is only called from the peephole2 pass and we assume that
33688 there are 2 instructions in the peephole (addis and load), so we want to
33689 check if the target register was not used in the memory address and the
33690 register to hold the addis result is dead after the peephole. */
33691 if (REGNO (addis_reg
) != REGNO (target
))
33693 if (reg_mentioned_p (target
, mem
))
33696 if (!peep2_reg_dead_p (2, addis_reg
))
33699 /* If the target register being loaded is the stack pointer, we must
33700 avoid loading any other value into it, even temporarily. */
33701 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
33705 base_reg
= XEXP (addr
, 0);
33706 return REGNO (addis_reg
) == REGNO (base_reg
);
33709 /* During the peephole2 pass, adjust and expand the insns for a load fusion
33710 sequence. We adjust the addis register to use the target register. If the
33711 load sign extends, we adjust the code to do the zero extending load, and an
33712 explicit sign extension later since the fusion only covers zero extending
33716 operands[0] register set with addis (to be replaced with target)
33717 operands[1] value set via addis
33718 operands[2] target register being loaded
33719 operands[3] D-form memory reference using operands[0]. */
33722 expand_fusion_gpr_load (rtx
*operands
)
33724 rtx addis_value
= operands
[1];
33725 rtx target
= operands
[2];
33726 rtx orig_mem
= operands
[3];
33727 rtx new_addr
, new_mem
, orig_addr
, offset
;
33728 enum rtx_code plus_or_lo_sum
;
33729 machine_mode target_mode
= GET_MODE (target
);
33730 machine_mode extend_mode
= target_mode
;
33731 machine_mode ptr_mode
= Pmode
;
33732 enum rtx_code extend
= UNKNOWN
;
33734 if (GET_CODE (orig_mem
) == ZERO_EXTEND
33735 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
33737 extend
= GET_CODE (orig_mem
);
33738 orig_mem
= XEXP (orig_mem
, 0);
33739 target_mode
= GET_MODE (orig_mem
);
33742 gcc_assert (MEM_P (orig_mem
));
33744 orig_addr
= XEXP (orig_mem
, 0);
33745 plus_or_lo_sum
= GET_CODE (orig_addr
);
33746 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
33748 offset
= XEXP (orig_addr
, 1);
33749 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
33750 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
33752 if (extend
!= UNKNOWN
)
33753 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
33755 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
33756 UNSPEC_FUSION_GPR
);
33757 emit_insn (gen_rtx_SET (target
, new_mem
));
33759 if (extend
== SIGN_EXTEND
)
33761 int sub_off
= ((BYTES_BIG_ENDIAN
)
33762 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
33765 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
33767 emit_insn (gen_rtx_SET (target
,
33768 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
33774 /* Return a string to fuse an addis instruction with a gpr load to the same
33775 register that we loaded up the addis instruction. The address that is used
33776 is the logical address that was formed during peephole2:
33777 (lo_sum (high) (low-part))
33779 The code is complicated, so we call output_asm_insn directly, and just
33783 emit_fusion_gpr_load (rtx target
, rtx mem
)
33789 const char *addis_str
= NULL
;
33790 const char *load_str
= NULL
;
33791 const char *mode_name
= NULL
;
33792 char insn_template
[80];
33794 const char *comment_str
= ASM_COMMENT_START
;
33796 if (GET_CODE (mem
) == ZERO_EXTEND
)
33797 mem
= XEXP (mem
, 0);
33799 gcc_assert (REG_P (target
) && MEM_P (mem
));
33801 if (*comment_str
== ' ')
33804 addr
= XEXP (mem
, 0);
33805 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
33806 gcc_unreachable ();
33808 addis_value
= XEXP (addr
, 0);
33809 load_offset
= XEXP (addr
, 1);
33811 /* Now emit the load instruction to the same register. */
33812 mode
= GET_MODE (mem
);
33816 mode_name
= "char";
33821 mode_name
= "short";
33831 gcc_assert (TARGET_POWERPC64
);
33832 mode_name
= "long";
33837 gcc_unreachable ();
33840 /* Emit the addis instruction. */
33841 fuse_ops
[0] = target
;
33842 if (satisfies_constraint_L (addis_value
))
33844 fuse_ops
[1] = addis_value
;
33845 addis_str
= "lis %0,%v1";
33848 else if (GET_CODE (addis_value
) == PLUS
)
33850 rtx op0
= XEXP (addis_value
, 0);
33851 rtx op1
= XEXP (addis_value
, 1);
33853 if (REG_P (op0
) && CONST_INT_P (op1
)
33854 && satisfies_constraint_L (op1
))
33858 addis_str
= "addis %0,%1,%v2";
33862 else if (GET_CODE (addis_value
) == HIGH
)
33864 rtx value
= XEXP (addis_value
, 0);
33865 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
33867 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
33868 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
33870 addis_str
= "addis %0,%2,%1@toc@ha";
33872 else if (TARGET_XCOFF
)
33873 addis_str
= "addis %0,%1@u(%2)";
33876 gcc_unreachable ();
33879 else if (GET_CODE (value
) == PLUS
)
33881 rtx op0
= XEXP (value
, 0);
33882 rtx op1
= XEXP (value
, 1);
33884 if (GET_CODE (op0
) == UNSPEC
33885 && XINT (op0
, 1) == UNSPEC_TOCREL
33886 && CONST_INT_P (op1
))
33888 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
33889 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
33892 addis_str
= "addis %0,%2,%1+%3@toc@ha";
33894 else if (TARGET_XCOFF
)
33895 addis_str
= "addis %0,%1+%3@u(%2)";
33898 gcc_unreachable ();
33902 else if (satisfies_constraint_L (value
))
33904 fuse_ops
[1] = value
;
33905 addis_str
= "lis %0,%v1";
33908 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
33910 fuse_ops
[1] = value
;
33911 addis_str
= "lis %0,%1@ha";
33916 fatal_insn ("Could not generate addis value for fusion", addis_value
);
33918 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
33919 comment_str
, mode_name
);
33920 output_asm_insn (insn_template
, fuse_ops
);
33922 /* Emit the D-form load instruction. */
33923 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
33925 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
33926 fuse_ops
[1] = load_offset
;
33927 output_asm_insn (insn_template
, fuse_ops
);
33930 else if (GET_CODE (load_offset
) == UNSPEC
33931 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
33934 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
33936 else if (TARGET_XCOFF
)
33937 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
33940 gcc_unreachable ();
33942 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
33943 output_asm_insn (insn_template
, fuse_ops
);
33946 else if (GET_CODE (load_offset
) == PLUS
33947 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
33948 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
33949 && CONST_INT_P (XEXP (load_offset
, 1)))
33951 rtx tocrel_unspec
= XEXP (load_offset
, 0);
33953 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
33955 else if (TARGET_XCOFF
)
33956 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
33959 gcc_unreachable ();
33961 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
33962 fuse_ops
[2] = XEXP (load_offset
, 1);
33963 output_asm_insn (insn_template
, fuse_ops
);
33966 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
33968 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
33970 fuse_ops
[1] = load_offset
;
33971 output_asm_insn (insn_template
, fuse_ops
);
33975 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
33980 /* Analyze vector computations and remove unnecessary doubleword
33981 swaps (xxswapdi instructions). This pass is performed only
33982 for little-endian VSX code generation.
33984 For this specific case, loads and stores of 4x32 and 2x64 vectors
33985 are inefficient. These are implemented using the lvx2dx and
33986 stvx2dx instructions, which invert the order of doublewords in
33987 a vector register. Thus the code generation inserts an xxswapdi
33988 after each such load, and prior to each such store. (For spill
33989 code after register assignment, an additional xxswapdi is inserted
33990 following each store in order to return a hard register to its
33993 The extra xxswapdi instructions reduce performance. This can be
33994 particularly bad for vectorized code. The purpose of this pass
33995 is to reduce the number of xxswapdi instructions required for
33998 The primary insight is that much code that operates on vectors
33999 does not care about the relative order of elements in a register,
34000 so long as the correct memory order is preserved. If we have
34001 a computation where all input values are provided by lvxd2x/xxswapdi
34002 sequences, all outputs are stored using xxswapdi/stvxd2x sequences,
34003 and all intermediate computations are pure SIMD (independent of
34004 element order), then all the xxswapdi's associated with the loads
34005 and stores may be removed.
34007 This pass uses some of the infrastructure and logical ideas from
34008 the "web" pass in web.c. We create maximal webs of computations
34009 fitting the description above using union-find. Each such web is
34010 then optimized by removing its unnecessary xxswapdi instructions.
34012 The pass is placed prior to global optimization so that we can
34013 perform the optimization in the safest and simplest way possible;
34014 that is, by replacing each xxswapdi insn with a register copy insn.
34015 Subsequent forward propagation will remove copies where possible.
34017 There are some operations sensitive to element order for which we
34018 can still allow the operation, provided we modify those operations.
34019 These include CONST_VECTORs, for which we must swap the first and
34020 second halves of the constant vector; and SUBREGs, for which we
34021 must adjust the byte offset to account for the swapped doublewords.
34022 A remaining opportunity would be non-immediate-form splats, for
34023 which we should adjust the selected lane of the input. We should
34024 also make code generation adjustments for sum-across operations,
34025 since this is a common vectorizer reduction.
34027 Because we run prior to the first split, we can see loads and stores
34028 here that match *vsx_le_perm_{load,store}_<mode>. These are vanilla
34029 vector loads and stores that have not yet been split into a permuting
34030 load/store and a swap. (One way this can happen is with a builtin
34031 call to vec_vsx_{ld,st}.) We can handle these as well, but rather
34032 than deleting a swap, we convert the load/store into a permuting
34033 load/store (which effectively removes the swap). */
34035 /* Notes on Permutes
34037 We do not currently handle computations that contain permutes. There
34038 is a general transformation that can be performed correctly, but it
34039 may introduce more expensive code than it replaces. To handle these
34040 would require a cost model to determine when to perform the optimization.
34041 This commentary records how this could be done if desired.
34043 The most general permute is something like this (example for V16QI):
34045 (vec_select:V16QI (vec_concat:V32QI (op1:V16QI) (op2:V16QI))
34046 (parallel [(const_int a0) (const_int a1)
34048 (const_int a14) (const_int a15)]))
34050 where a0,...,a15 are in [0,31] and select elements from op1 and op2
34051 to produce in the result.
34053 Regardless of mode, we can convert the PARALLEL to a mask of 16
34054 byte-element selectors. Let's call this M, with M[i] representing
34055 the ith byte-element selector value. Then if we swap doublewords
34056 throughout the computation, we can get correct behavior by replacing
34057 M with M' as follows:
34059 { M[i+8]+8 : i < 8, M[i+8] in [0,7] U [16,23]
34060 M'[i] = { M[i+8]-8 : i < 8, M[i+8] in [8,15] U [24,31]
34061 { M[i-8]+8 : i >= 8, M[i-8] in [0,7] U [16,23]
34062 { M[i-8]-8 : i >= 8, M[i-8] in [8,15] U [24,31]
34064 This seems promising at first, since we are just replacing one mask
34065 with another. But certain masks are preferable to others. If M
34066 is a mask that matches a vmrghh pattern, for example, M' certainly
34067 will not. Instead of a single vmrghh, we would generate a load of
34068 M' and a vperm. So we would need to know how many xxswapd's we can
34069 remove as a result of this transformation to determine if it's
34070 profitable; and preferably the logic would need to be aware of all
34071 the special preferable masks.
34073 Another form of permute is an UNSPEC_VPERM, in which the mask is
34074 already in a register. In some cases, this mask may be a constant
34075 that we can discover with ud-chains, in which case the above
34076 transformation is ok. However, the common usage here is for the
34077 mask to be produced by an UNSPEC_LVSL, in which case the mask
34078 cannot be known at compile time. In such a case we would have to
34079 generate several instructions to compute M' as above at run time,
34080 and a cost model is needed again. */
34082 /* This is based on the union-find logic in web.c. web_entry_base is
34083 defined in df.h. */
34084 class swap_web_entry
: public web_entry_base
34087 /* Pointer to the insn. */
34089 /* Set if insn contains a mention of a vector register. All other
34090 fields are undefined if this field is unset. */
34091 unsigned int is_relevant
: 1;
34092 /* Set if insn is a load. */
34093 unsigned int is_load
: 1;
34094 /* Set if insn is a store. */
34095 unsigned int is_store
: 1;
34096 /* Set if insn is a doubleword swap. This can either be a register swap
34097 or a permuting load or store (test is_load and is_store for this). */
34098 unsigned int is_swap
: 1;
34099 /* Set if the insn has a live-in use of a parameter register. */
34100 unsigned int is_live_in
: 1;
34101 /* Set if the insn has a live-out def of a return register. */
34102 unsigned int is_live_out
: 1;
34103 /* Set if the insn contains a subreg reference of a vector register. */
34104 unsigned int contains_subreg
: 1;
34105 /* Set if the insn contains a 128-bit integer operand. */
34106 unsigned int is_128_int
: 1;
34107 /* Set if this is a call-insn. */
34108 unsigned int is_call
: 1;
34109 /* Set if this insn does not perform a vector operation for which
34110 element order matters, or if we know how to fix it up if it does.
34111 Undefined if is_swap is set. */
34112 unsigned int is_swappable
: 1;
34113 /* A nonzero value indicates what kind of special handling for this
34114 insn is required if doublewords are swapped. Undefined if
34115 is_swappable is not set. */
34116 unsigned int special_handling
: 3;
34117 /* Set if the web represented by this entry cannot be optimized. */
34118 unsigned int web_not_optimizable
: 1;
34119 /* Set if this insn should be deleted. */
34120 unsigned int will_delete
: 1;
34123 enum special_handling_values
{
34133 /* Union INSN with all insns containing definitions that reach USE.
34134 Detect whether USE is live-in to the current function. */
34136 union_defs (swap_web_entry
*insn_entry
, rtx insn
, df_ref use
)
34138 struct df_link
*link
= DF_REF_CHAIN (use
);
34141 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
34145 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
34146 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
34148 if (DF_REF_INSN_INFO (link
->ref
))
34150 rtx def_insn
= DF_REF_INSN (link
->ref
);
34151 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
34152 insn_entry
+ INSN_UID (def_insn
));
34159 /* Union INSN with all insns containing uses reached from DEF.
34160 Detect whether DEF is live-out from the current function. */
34162 union_uses (swap_web_entry
*insn_entry
, rtx insn
, df_ref def
)
34164 struct df_link
*link
= DF_REF_CHAIN (def
);
34167 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
34171 /* This could be an eh use or some other artificial use;
34172 we treat these all the same (killing the optimization). */
34173 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
34174 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
34176 if (DF_REF_INSN_INFO (link
->ref
))
34178 rtx use_insn
= DF_REF_INSN (link
->ref
);
34179 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
34180 insn_entry
+ INSN_UID (use_insn
));
34187 /* Return 1 iff INSN is a load insn, including permuting loads that
34188 represent an lvxd2x instruction; else return 0. */
34189 static unsigned int
34190 insn_is_load_p (rtx insn
)
34192 rtx body
= PATTERN (insn
);
34194 if (GET_CODE (body
) == SET
)
34196 if (GET_CODE (SET_SRC (body
)) == MEM
)
34199 if (GET_CODE (SET_SRC (body
)) == VEC_SELECT
34200 && GET_CODE (XEXP (SET_SRC (body
), 0)) == MEM
)
34206 if (GET_CODE (body
) != PARALLEL
)
34209 rtx set
= XVECEXP (body
, 0, 0);
34211 if (GET_CODE (set
) == SET
&& GET_CODE (SET_SRC (set
)) == MEM
)
34217 /* Return 1 iff INSN is a store insn, including permuting stores that
34218 represent an stvxd2x instruction; else return 0. */
34219 static unsigned int
34220 insn_is_store_p (rtx insn
)
34222 rtx body
= PATTERN (insn
);
34223 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == MEM
)
34225 if (GET_CODE (body
) != PARALLEL
)
34227 rtx set
= XVECEXP (body
, 0, 0);
34228 if (GET_CODE (set
) == SET
&& GET_CODE (SET_DEST (set
)) == MEM
)
34233 /* Return 1 iff INSN swaps doublewords. This may be a reg-reg swap,
34234 a permuting load, or a permuting store. */
34235 static unsigned int
34236 insn_is_swap_p (rtx insn
)
34238 rtx body
= PATTERN (insn
);
34239 if (GET_CODE (body
) != SET
)
34241 rtx rhs
= SET_SRC (body
);
34242 if (GET_CODE (rhs
) != VEC_SELECT
)
34244 rtx parallel
= XEXP (rhs
, 1);
34245 if (GET_CODE (parallel
) != PARALLEL
)
34247 unsigned int len
= XVECLEN (parallel
, 0);
34248 if (len
!= 2 && len
!= 4 && len
!= 8 && len
!= 16)
34250 for (unsigned int i
= 0; i
< len
/ 2; ++i
)
34252 rtx op
= XVECEXP (parallel
, 0, i
);
34253 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != len
/ 2 + i
)
34256 for (unsigned int i
= len
/ 2; i
< len
; ++i
)
34258 rtx op
= XVECEXP (parallel
, 0, i
);
34259 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != i
- len
/ 2)
34265 /* Return 1 iff OP is an operand that will not be affected by having
34266 vector doublewords swapped in memory. */
34267 static unsigned int
34268 rtx_is_swappable_p (rtx op
, unsigned int *special
)
34270 enum rtx_code code
= GET_CODE (op
);
34289 *special
= SH_CONST_VECTOR
;
34293 case VEC_DUPLICATE
:
34294 /* Opportunity: If XEXP (op, 0) has the same mode as the result,
34295 and XEXP (op, 1) is a PARALLEL with a single QImode const int,
34296 it represents a vector splat for which we can do special
34298 if (GET_CODE (XEXP (op
, 0)) == CONST_INT
)
34300 else if (GET_CODE (XEXP (op
, 0)) == REG
34301 && GET_MODE_INNER (GET_MODE (op
)) == GET_MODE (XEXP (op
, 0)))
34302 /* This catches V2DF and V2DI splat, at a minimum. */
34304 else if (GET_CODE (XEXP (op
, 0)) == VEC_SELECT
)
34305 /* If the duplicated item is from a select, defer to the select
34306 processing to see if we can change the lane for the splat. */
34307 return rtx_is_swappable_p (XEXP (op
, 0), special
);
34312 /* A vec_extract operation is ok if we change the lane. */
34313 if (GET_CODE (XEXP (op
, 0)) == REG
34314 && GET_MODE_INNER (GET_MODE (XEXP (op
, 0))) == GET_MODE (op
)
34315 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
34316 && XVECLEN (parallel
, 0) == 1
34317 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
)
34319 *special
= SH_EXTRACT
;
34327 /* Various operations are unsafe for this optimization, at least
34328 without significant additional work. Permutes are obviously
34329 problematic, as both the permute control vector and the ordering
34330 of the target values are invalidated by doubleword swapping.
34331 Vector pack and unpack modify the number of vector lanes.
34332 Merge-high/low will not operate correctly on swapped operands.
34333 Vector shifts across element boundaries are clearly uncool,
34334 as are vector select and concatenate operations. Vector
34335 sum-across instructions define one operand with a specific
34336 order-dependent element, so additional fixup code would be
34337 needed to make those work. Vector set and non-immediate-form
34338 vector splat are element-order sensitive. A few of these
34339 cases might be workable with special handling if required.
34340 Adding cost modeling would be appropriate in some cases. */
34341 int val
= XINT (op
, 1);
34346 case UNSPEC_VMRGH_DIRECT
:
34347 case UNSPEC_VMRGL_DIRECT
:
34348 case UNSPEC_VPACK_SIGN_SIGN_SAT
:
34349 case UNSPEC_VPACK_SIGN_UNS_SAT
:
34350 case UNSPEC_VPACK_UNS_UNS_MOD
:
34351 case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
:
34352 case UNSPEC_VPACK_UNS_UNS_SAT
:
34354 case UNSPEC_VPERM_UNS
:
34355 case UNSPEC_VPERMHI
:
34356 case UNSPEC_VPERMSI
:
34358 case UNSPEC_VSLDOI
:
34361 case UNSPEC_VSUM2SWS
:
34362 case UNSPEC_VSUM4S
:
34363 case UNSPEC_VSUM4UBS
:
34364 case UNSPEC_VSUMSWS
:
34365 case UNSPEC_VSUMSWS_DIRECT
:
34366 case UNSPEC_VSX_CONCAT
:
34367 case UNSPEC_VSX_SET
:
34368 case UNSPEC_VSX_SLDWI
:
34369 case UNSPEC_VUNPACK_HI_SIGN
:
34370 case UNSPEC_VUNPACK_HI_SIGN_DIRECT
:
34371 case UNSPEC_VUNPACK_LO_SIGN
:
34372 case UNSPEC_VUNPACK_LO_SIGN_DIRECT
:
34373 case UNSPEC_VUPKHPX
:
34374 case UNSPEC_VUPKHS_V4SF
:
34375 case UNSPEC_VUPKHU_V4SF
:
34376 case UNSPEC_VUPKLPX
:
34377 case UNSPEC_VUPKLS_V4SF
:
34378 case UNSPEC_VUPKLU_V4SF
:
34379 case UNSPEC_VSX_CVDPSPN
:
34380 case UNSPEC_VSX_CVSPDP
:
34381 case UNSPEC_VSX_CVSPDPN
:
34383 case UNSPEC_VSPLT_DIRECT
:
34384 *special
= SH_SPLAT
;
34393 const char *fmt
= GET_RTX_FORMAT (code
);
34396 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
34397 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
34399 unsigned int special_op
= SH_NONE
;
34400 ok
&= rtx_is_swappable_p (XEXP (op
, i
), &special_op
);
34401 if (special_op
== SH_NONE
)
34403 /* Ensure we never have two kinds of special handling
34404 for the same insn. */
34405 if (*special
!= SH_NONE
&& *special
!= special_op
)
34407 *special
= special_op
;
34409 else if (fmt
[i
] == 'E')
34410 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
34412 unsigned int special_op
= SH_NONE
;
34413 ok
&= rtx_is_swappable_p (XVECEXP (op
, i
, j
), &special_op
);
34414 if (special_op
== SH_NONE
)
34416 /* Ensure we never have two kinds of special handling
34417 for the same insn. */
34418 if (*special
!= SH_NONE
&& *special
!= special_op
)
34420 *special
= special_op
;
34426 /* Return 1 iff INSN is an operand that will not be affected by
34427 having vector doublewords swapped in memory (in which case
34428 *SPECIAL is unchanged), or that can be modified to be correct
34429 if vector doublewords are swapped in memory (in which case
34430 *SPECIAL is changed to a value indicating how). */
34431 static unsigned int
34432 insn_is_swappable_p (swap_web_entry
*insn_entry
, rtx insn
,
34433 unsigned int *special
)
34435 /* Calls are always bad. */
34436 if (GET_CODE (insn
) == CALL_INSN
)
34439 /* Loads and stores seen here are not permuting, but we can still
34440 fix them up by converting them to permuting ones. Exceptions:
34441 UNSPEC_LVE, UNSPEC_LVX, and UNSPEC_STVX, which have a PARALLEL
34442 body instead of a SET; and UNSPEC_STVE, which has an UNSPEC
34443 for the SET source. */
34444 rtx body
= PATTERN (insn
);
34445 int i
= INSN_UID (insn
);
34447 if (insn_entry
[i
].is_load
)
34449 if (GET_CODE (body
) == SET
)
34451 *special
= SH_NOSWAP_LD
;
34458 if (insn_entry
[i
].is_store
)
34460 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) != UNSPEC
)
34462 *special
= SH_NOSWAP_ST
;
34469 /* A convert to single precision can be left as is provided that
34470 all of its uses are in xxspltw instructions that splat BE element
34472 if (GET_CODE (body
) == SET
34473 && GET_CODE (SET_SRC (body
)) == UNSPEC
34474 && XINT (SET_SRC (body
), 1) == UNSPEC_VSX_CVDPSPN
)
34477 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
34479 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
34481 struct df_link
*link
= DF_REF_CHAIN (def
);
34485 for (; link
; link
= link
->next
) {
34486 rtx use_insn
= DF_REF_INSN (link
->ref
);
34487 rtx use_body
= PATTERN (use_insn
);
34488 if (GET_CODE (use_body
) != SET
34489 || GET_CODE (SET_SRC (use_body
)) != UNSPEC
34490 || XINT (SET_SRC (use_body
), 1) != UNSPEC_VSX_XXSPLTW
34491 || XEXP (XEXP (SET_SRC (use_body
), 0), 1) != const0_rtx
)
34499 /* Otherwise check the operands for vector lane violations. */
34500 return rtx_is_swappable_p (body
, special
);
34503 enum chain_purpose
{ FOR_LOADS
, FOR_STORES
};
34505 /* Return true if the UD or DU chain headed by LINK is non-empty,
34506 and every entry on the chain references an insn that is a
34507 register swap. Furthermore, if PURPOSE is FOR_LOADS, each such
34508 register swap must have only permuting loads as reaching defs.
34509 If PURPOSE is FOR_STORES, each such register swap must have only
34510 register swaps or permuting stores as reached uses. */
34512 chain_contains_only_swaps (swap_web_entry
*insn_entry
, struct df_link
*link
,
34513 enum chain_purpose purpose
)
34518 for (; link
; link
= link
->next
)
34520 if (!VECTOR_MODE_P (GET_MODE (DF_REF_REG (link
->ref
))))
34523 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
34526 rtx reached_insn
= DF_REF_INSN (link
->ref
);
34527 unsigned uid
= INSN_UID (reached_insn
);
34528 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (reached_insn
);
34530 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
34531 || insn_entry
[uid
].is_store
)
34534 if (purpose
== FOR_LOADS
)
34537 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
34539 struct df_link
*swap_link
= DF_REF_CHAIN (use
);
34543 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
34546 rtx swap_def_insn
= DF_REF_INSN (swap_link
->ref
);
34547 unsigned uid2
= INSN_UID (swap_def_insn
);
34549 /* Only permuting loads are allowed. */
34550 if (!insn_entry
[uid2
].is_swap
|| !insn_entry
[uid2
].is_load
)
34553 swap_link
= swap_link
->next
;
34557 else if (purpose
== FOR_STORES
)
34560 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
34562 struct df_link
*swap_link
= DF_REF_CHAIN (def
);
34566 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
34569 rtx swap_use_insn
= DF_REF_INSN (swap_link
->ref
);
34570 unsigned uid2
= INSN_UID (swap_use_insn
);
34572 /* Permuting stores or register swaps are allowed. */
34573 if (!insn_entry
[uid2
].is_swap
|| insn_entry
[uid2
].is_load
)
34576 swap_link
= swap_link
->next
;
34585 /* Mark the xxswapdi instructions associated with permuting loads and
34586 stores for removal. Note that we only flag them for deletion here,
34587 as there is a possibility of a swap being reached from multiple
34590 mark_swaps_for_removal (swap_web_entry
*insn_entry
, unsigned int i
)
34592 rtx insn
= insn_entry
[i
].insn
;
34593 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
34595 if (insn_entry
[i
].is_load
)
34598 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
34600 struct df_link
*link
= DF_REF_CHAIN (def
);
34602 /* We know by now that these are swaps, so we can delete
34603 them confidently. */
34606 rtx use_insn
= DF_REF_INSN (link
->ref
);
34607 insn_entry
[INSN_UID (use_insn
)].will_delete
= 1;
34612 else if (insn_entry
[i
].is_store
)
34615 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
34617 /* Ignore uses for addressability. */
34618 machine_mode mode
= GET_MODE (DF_REF_REG (use
));
34619 if (!VECTOR_MODE_P (mode
))
34622 struct df_link
*link
= DF_REF_CHAIN (use
);
34624 /* We know by now that these are swaps, so we can delete
34625 them confidently. */
34628 rtx def_insn
= DF_REF_INSN (link
->ref
);
34629 insn_entry
[INSN_UID (def_insn
)].will_delete
= 1;
34636 /* OP is either a CONST_VECTOR or an expression containing one.
34637 Swap the first half of the vector with the second in the first
34638 case. Recurse to find it in the second. */
34640 swap_const_vector_halves (rtx op
)
34643 enum rtx_code code
= GET_CODE (op
);
34644 if (GET_CODE (op
) == CONST_VECTOR
)
34646 int half_units
= GET_MODE_NUNITS (GET_MODE (op
)) / 2;
34647 for (i
= 0; i
< half_units
; ++i
)
34649 rtx temp
= CONST_VECTOR_ELT (op
, i
);
34650 CONST_VECTOR_ELT (op
, i
) = CONST_VECTOR_ELT (op
, i
+ half_units
);
34651 CONST_VECTOR_ELT (op
, i
+ half_units
) = temp
;
34657 const char *fmt
= GET_RTX_FORMAT (code
);
34658 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
34659 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
34660 swap_const_vector_halves (XEXP (op
, i
));
34661 else if (fmt
[i
] == 'E')
34662 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
34663 swap_const_vector_halves (XVECEXP (op
, i
, j
));
34667 /* Find all subregs of a vector expression that perform a narrowing,
34668 and adjust the subreg index to account for doubleword swapping. */
34670 adjust_subreg_index (rtx op
)
34672 enum rtx_code code
= GET_CODE (op
);
34674 && (GET_MODE_SIZE (GET_MODE (op
))
34675 < GET_MODE_SIZE (GET_MODE (XEXP (op
, 0)))))
34677 unsigned int index
= SUBREG_BYTE (op
);
34682 SUBREG_BYTE (op
) = index
;
34685 const char *fmt
= GET_RTX_FORMAT (code
);
34687 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
34688 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
34689 adjust_subreg_index (XEXP (op
, i
));
34690 else if (fmt
[i
] == 'E')
34691 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
34692 adjust_subreg_index (XVECEXP (op
, i
, j
));
34695 /* Convert the non-permuting load INSN to a permuting one. */
34697 permute_load (rtx_insn
*insn
)
34699 rtx body
= PATTERN (insn
);
34700 rtx mem_op
= SET_SRC (body
);
34701 rtx tgt_reg
= SET_DEST (body
);
34702 machine_mode mode
= GET_MODE (tgt_reg
);
34703 int n_elts
= GET_MODE_NUNITS (mode
);
34704 int half_elts
= n_elts
/ 2;
34705 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
34707 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
34708 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34709 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
34710 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34711 rtx sel
= gen_rtx_VEC_SELECT (mode
, mem_op
, par
);
34712 SET_SRC (body
) = sel
;
34713 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34714 df_insn_rescan (insn
);
34717 fprintf (dump_file
, "Replacing load %d with permuted load\n",
34721 /* Convert the non-permuting store INSN to a permuting one. */
34723 permute_store (rtx_insn
*insn
)
34725 rtx body
= PATTERN (insn
);
34726 rtx src_reg
= SET_SRC (body
);
34727 machine_mode mode
= GET_MODE (src_reg
);
34728 int n_elts
= GET_MODE_NUNITS (mode
);
34729 int half_elts
= n_elts
/ 2;
34730 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
34732 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
34733 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34734 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
34735 XVECEXP (par
, 0, i
) = GEN_INT (j
);
34736 rtx sel
= gen_rtx_VEC_SELECT (mode
, src_reg
, par
);
34737 SET_SRC (body
) = sel
;
34738 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34739 df_insn_rescan (insn
);
34742 fprintf (dump_file
, "Replacing store %d with permuted store\n",
34746 /* Given OP that contains a vector extract operation, adjust the index
34747 of the extracted lane to account for the doubleword swap. */
34749 adjust_extract (rtx_insn
*insn
)
34751 rtx pattern
= PATTERN (insn
);
34752 if (GET_CODE (pattern
) == PARALLEL
)
34753 pattern
= XVECEXP (pattern
, 0, 0);
34754 rtx src
= SET_SRC (pattern
);
34755 /* The vec_select may be wrapped in a vec_duplicate for a splat, so
34756 account for that. */
34757 rtx sel
= GET_CODE (src
) == VEC_DUPLICATE
? XEXP (src
, 0) : src
;
34758 rtx par
= XEXP (sel
, 1);
34759 int half_elts
= GET_MODE_NUNITS (GET_MODE (XEXP (sel
, 0))) >> 1;
34760 int lane
= INTVAL (XVECEXP (par
, 0, 0));
34761 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
34762 XVECEXP (par
, 0, 0) = GEN_INT (lane
);
34763 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34764 df_insn_rescan (insn
);
34767 fprintf (dump_file
, "Changing lane for extract %d\n", INSN_UID (insn
));
34770 /* Given OP that contains a vector direct-splat operation, adjust the index
34771 of the source lane to account for the doubleword swap. */
34773 adjust_splat (rtx_insn
*insn
)
34775 rtx body
= PATTERN (insn
);
34776 rtx unspec
= XEXP (body
, 1);
34777 int half_elts
= GET_MODE_NUNITS (GET_MODE (unspec
)) >> 1;
34778 int lane
= INTVAL (XVECEXP (unspec
, 0, 1));
34779 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
34780 XVECEXP (unspec
, 0, 1) = GEN_INT (lane
);
34781 INSN_CODE (insn
) = -1; /* Force re-recognition. */
34782 df_insn_rescan (insn
);
34785 fprintf (dump_file
, "Changing lane for splat %d\n", INSN_UID (insn
));
34788 /* The insn described by INSN_ENTRY[I] can be swapped, but only
34789 with special handling. Take care of that here. */
34791 handle_special_swappables (swap_web_entry
*insn_entry
, unsigned i
)
34793 rtx_insn
*insn
= insn_entry
[i
].insn
;
34794 rtx body
= PATTERN (insn
);
34796 switch (insn_entry
[i
].special_handling
)
34799 gcc_unreachable ();
34800 case SH_CONST_VECTOR
:
34802 /* A CONST_VECTOR will only show up somewhere in the RHS of a SET. */
34803 gcc_assert (GET_CODE (body
) == SET
);
34804 rtx rhs
= SET_SRC (body
);
34805 swap_const_vector_halves (rhs
);
34807 fprintf (dump_file
, "Swapping constant halves in insn %d\n", i
);
34811 /* A subreg of the same size is already safe. For subregs that
34812 select a smaller portion of a reg, adjust the index for
34813 swapped doublewords. */
34814 adjust_subreg_index (body
);
34816 fprintf (dump_file
, "Adjusting subreg in insn %d\n", i
);
34819 /* Convert a non-permuting load to a permuting one. */
34820 permute_load (insn
);
34823 /* Convert a non-permuting store to a permuting one. */
34824 permute_store (insn
);
34827 /* Change the lane on an extract operation. */
34828 adjust_extract (insn
);
34831 /* Change the lane on a direct-splat operation. */
34832 adjust_splat (insn
);
34837 /* Find the insn from the Ith table entry, which is known to be a
34838 register swap Y = SWAP(X). Replace it with a copy Y = X. */
34840 replace_swap_with_copy (swap_web_entry
*insn_entry
, unsigned i
)
34842 rtx_insn
*insn
= insn_entry
[i
].insn
;
34843 rtx body
= PATTERN (insn
);
34844 rtx src_reg
= XEXP (SET_SRC (body
), 0);
34845 rtx copy
= gen_rtx_SET (SET_DEST (body
), src_reg
);
34846 rtx_insn
*new_insn
= emit_insn_before (copy
, insn
);
34847 set_block_for_insn (new_insn
, BLOCK_FOR_INSN (insn
));
34848 df_insn_rescan (new_insn
);
34852 unsigned int new_uid
= INSN_UID (new_insn
);
34853 fprintf (dump_file
, "Replacing swap %d with copy %d\n", i
, new_uid
);
34856 df_insn_delete (insn
);
34857 remove_insn (insn
);
34858 insn
->set_deleted ();
34861 /* Dump the swap table to DUMP_FILE. */
34863 dump_swap_insn_table (swap_web_entry
*insn_entry
)
34865 int e
= get_max_uid ();
34866 fprintf (dump_file
, "\nRelevant insns with their flag settings\n\n");
34868 for (int i
= 0; i
< e
; ++i
)
34869 if (insn_entry
[i
].is_relevant
)
34871 swap_web_entry
*pred_entry
= (swap_web_entry
*)insn_entry
[i
].pred ();
34872 fprintf (dump_file
, "%6d %6d ", i
,
34873 pred_entry
&& pred_entry
->insn
34874 ? INSN_UID (pred_entry
->insn
) : 0);
34875 if (insn_entry
[i
].is_load
)
34876 fputs ("load ", dump_file
);
34877 if (insn_entry
[i
].is_store
)
34878 fputs ("store ", dump_file
);
34879 if (insn_entry
[i
].is_swap
)
34880 fputs ("swap ", dump_file
);
34881 if (insn_entry
[i
].is_live_in
)
34882 fputs ("live-in ", dump_file
);
34883 if (insn_entry
[i
].is_live_out
)
34884 fputs ("live-out ", dump_file
);
34885 if (insn_entry
[i
].contains_subreg
)
34886 fputs ("subreg ", dump_file
);
34887 if (insn_entry
[i
].is_128_int
)
34888 fputs ("int128 ", dump_file
);
34889 if (insn_entry
[i
].is_call
)
34890 fputs ("call ", dump_file
);
34891 if (insn_entry
[i
].is_swappable
)
34893 fputs ("swappable ", dump_file
);
34894 if (insn_entry
[i
].special_handling
== SH_CONST_VECTOR
)
34895 fputs ("special:constvec ", dump_file
);
34896 else if (insn_entry
[i
].special_handling
== SH_SUBREG
)
34897 fputs ("special:subreg ", dump_file
);
34898 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_LD
)
34899 fputs ("special:load ", dump_file
);
34900 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_ST
)
34901 fputs ("special:store ", dump_file
);
34902 else if (insn_entry
[i
].special_handling
== SH_EXTRACT
)
34903 fputs ("special:extract ", dump_file
);
34904 else if (insn_entry
[i
].special_handling
== SH_SPLAT
)
34905 fputs ("special:splat ", dump_file
);
34907 if (insn_entry
[i
].web_not_optimizable
)
34908 fputs ("unoptimizable ", dump_file
);
34909 if (insn_entry
[i
].will_delete
)
34910 fputs ("delete ", dump_file
);
34911 fputs ("\n", dump_file
);
34913 fputs ("\n", dump_file
);
34916 /* Main entry point for this pass. */
34918 rs6000_analyze_swaps (function
*fun
)
34920 swap_web_entry
*insn_entry
;
34924 /* Dataflow analysis for use-def chains. */
34925 df_set_flags (DF_RD_PRUNE_DEAD_DEFS
);
34926 df_chain_add_problem (DF_DU_CHAIN
| DF_UD_CHAIN
);
34928 df_set_flags (DF_DEFER_INSN_RESCAN
);
34930 /* Allocate structure to represent webs of insns. */
34931 insn_entry
= XCNEWVEC (swap_web_entry
, get_max_uid ());
34933 /* Walk the insns to gather basic data. */
34934 FOR_ALL_BB_FN (bb
, fun
)
34935 FOR_BB_INSNS (bb
, insn
)
34937 unsigned int uid
= INSN_UID (insn
);
34938 if (NONDEBUG_INSN_P (insn
))
34940 insn_entry
[uid
].insn
= insn
;
34942 if (GET_CODE (insn
) == CALL_INSN
)
34943 insn_entry
[uid
].is_call
= 1;
34945 /* Walk the uses and defs to see if we mention vector regs.
34946 Record any constraints on optimization of such mentions. */
34947 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
34949 FOR_EACH_INSN_INFO_USE (mention
, insn_info
)
34951 /* We use DF_REF_REAL_REG here to get inside any subregs. */
34952 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
34954 /* If a use gets its value from a call insn, it will be
34955 a hard register and will look like (reg:V4SI 3 3).
34956 The df analysis creates two mentions for GPR3 and GPR4,
34957 both DImode. We must recognize this and treat it as a
34958 vector mention to ensure the call is unioned with this
34960 if (mode
== DImode
&& DF_REF_INSN_INFO (mention
))
34962 rtx feeder
= DF_REF_INSN (mention
);
34963 /* FIXME: It is pretty hard to get from the df mention
34964 to the mode of the use in the insn. We arbitrarily
34965 pick a vector mode here, even though the use might
34966 be a real DImode. We can be too conservative
34967 (create a web larger than necessary) because of
34968 this, so consider eventually fixing this. */
34969 if (GET_CODE (feeder
) == CALL_INSN
)
34973 if (VECTOR_MODE_P (mode
) || mode
== TImode
)
34975 insn_entry
[uid
].is_relevant
= 1;
34976 if (mode
== TImode
|| mode
== V1TImode
)
34977 insn_entry
[uid
].is_128_int
= 1;
34978 if (DF_REF_INSN_INFO (mention
))
34979 insn_entry
[uid
].contains_subreg
34980 = !rtx_equal_p (DF_REF_REG (mention
),
34981 DF_REF_REAL_REG (mention
));
34982 union_defs (insn_entry
, insn
, mention
);
34985 FOR_EACH_INSN_INFO_DEF (mention
, insn_info
)
34987 /* We use DF_REF_REAL_REG here to get inside any subregs. */
34988 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
34990 /* If we're loading up a hard vector register for a call,
34991 it looks like (set (reg:V4SI 9 9) (...)). The df
34992 analysis creates two mentions for GPR9 and GPR10, both
34993 DImode. So relying on the mode from the mentions
34994 isn't sufficient to ensure we union the call into the
34995 web with the parameter setup code. */
34996 if (mode
== DImode
&& GET_CODE (insn
) == SET
34997 && VECTOR_MODE_P (GET_MODE (SET_DEST (insn
))))
34998 mode
= GET_MODE (SET_DEST (insn
));
35000 if (VECTOR_MODE_P (mode
) || mode
== TImode
)
35002 insn_entry
[uid
].is_relevant
= 1;
35003 if (mode
== TImode
|| mode
== V1TImode
)
35004 insn_entry
[uid
].is_128_int
= 1;
35005 if (DF_REF_INSN_INFO (mention
))
35006 insn_entry
[uid
].contains_subreg
35007 = !rtx_equal_p (DF_REF_REG (mention
),
35008 DF_REF_REAL_REG (mention
));
35009 /* REG_FUNCTION_VALUE_P is not valid for subregs. */
35010 else if (REG_FUNCTION_VALUE_P (DF_REF_REG (mention
)))
35011 insn_entry
[uid
].is_live_out
= 1;
35012 union_uses (insn_entry
, insn
, mention
);
35016 if (insn_entry
[uid
].is_relevant
)
35018 /* Determine if this is a load or store. */
35019 insn_entry
[uid
].is_load
= insn_is_load_p (insn
);
35020 insn_entry
[uid
].is_store
= insn_is_store_p (insn
);
35022 /* Determine if this is a doubleword swap. If not,
35023 determine whether it can legally be swapped. */
35024 if (insn_is_swap_p (insn
))
35025 insn_entry
[uid
].is_swap
= 1;
35028 unsigned int special
= SH_NONE
;
35029 insn_entry
[uid
].is_swappable
35030 = insn_is_swappable_p (insn_entry
, insn
, &special
);
35031 if (special
!= SH_NONE
&& insn_entry
[uid
].contains_subreg
)
35032 insn_entry
[uid
].is_swappable
= 0;
35033 else if (special
!= SH_NONE
)
35034 insn_entry
[uid
].special_handling
= special
;
35035 else if (insn_entry
[uid
].contains_subreg
)
35036 insn_entry
[uid
].special_handling
= SH_SUBREG
;
35044 fprintf (dump_file
, "\nSwap insn entry table when first built\n");
35045 dump_swap_insn_table (insn_entry
);
35048 /* Record unoptimizable webs. */
35049 unsigned e
= get_max_uid (), i
;
35050 for (i
= 0; i
< e
; ++i
)
35052 if (!insn_entry
[i
].is_relevant
)
35055 swap_web_entry
*root
35056 = (swap_web_entry
*)(&insn_entry
[i
])->unionfind_root ();
35058 if (insn_entry
[i
].is_live_in
|| insn_entry
[i
].is_live_out
35059 || (insn_entry
[i
].contains_subreg
35060 && insn_entry
[i
].special_handling
!= SH_SUBREG
)
35061 || insn_entry
[i
].is_128_int
|| insn_entry
[i
].is_call
35062 || !(insn_entry
[i
].is_swappable
|| insn_entry
[i
].is_swap
))
35063 root
->web_not_optimizable
= 1;
35065 /* If we have loads or stores that aren't permuting then the
35066 optimization isn't appropriate. */
35067 else if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
35068 && !insn_entry
[i
].is_swap
&& !insn_entry
[i
].is_swappable
)
35069 root
->web_not_optimizable
= 1;
35071 /* If we have permuting loads or stores that are not accompanied
35072 by a register swap, the optimization isn't appropriate. */
35073 else if (insn_entry
[i
].is_load
&& insn_entry
[i
].is_swap
)
35075 rtx insn
= insn_entry
[i
].insn
;
35076 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
35079 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
35081 struct df_link
*link
= DF_REF_CHAIN (def
);
35083 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_LOADS
))
35085 root
->web_not_optimizable
= 1;
35090 else if (insn_entry
[i
].is_store
&& insn_entry
[i
].is_swap
)
35092 rtx insn
= insn_entry
[i
].insn
;
35093 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
35096 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
35098 struct df_link
*link
= DF_REF_CHAIN (use
);
35100 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_STORES
))
35102 root
->web_not_optimizable
= 1;
35111 fprintf (dump_file
, "\nSwap insn entry table after web analysis\n");
35112 dump_swap_insn_table (insn_entry
);
35115 /* For each load and store in an optimizable web (which implies
35116 the loads and stores are permuting), find the associated
35117 register swaps and mark them for removal. Due to various
35118 optimizations we may mark the same swap more than once. Also
35119 perform special handling for swappable insns that require it. */
35120 for (i
= 0; i
< e
; ++i
)
35121 if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
35122 && insn_entry
[i
].is_swap
)
35124 swap_web_entry
* root_entry
35125 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
35126 if (!root_entry
->web_not_optimizable
)
35127 mark_swaps_for_removal (insn_entry
, i
);
35129 else if (insn_entry
[i
].is_swappable
&& insn_entry
[i
].special_handling
)
35131 swap_web_entry
* root_entry
35132 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
35133 if (!root_entry
->web_not_optimizable
)
35134 handle_special_swappables (insn_entry
, i
);
35137 /* Now delete the swaps marked for removal. */
35138 for (i
= 0; i
< e
; ++i
)
35139 if (insn_entry
[i
].will_delete
)
35140 replace_swap_with_copy (insn_entry
, i
);
35147 const pass_data pass_data_analyze_swaps
=
35149 RTL_PASS
, /* type */
35150 "swaps", /* name */
35151 OPTGROUP_NONE
, /* optinfo_flags */
35152 TV_NONE
, /* tv_id */
35153 0, /* properties_required */
35154 0, /* properties_provided */
35155 0, /* properties_destroyed */
35156 0, /* todo_flags_start */
35157 TODO_df_finish
, /* todo_flags_finish */
35160 class pass_analyze_swaps
: public rtl_opt_pass
35163 pass_analyze_swaps(gcc::context
*ctxt
)
35164 : rtl_opt_pass(pass_data_analyze_swaps
, ctxt
)
35167 /* opt_pass methods: */
35168 virtual bool gate (function
*)
35170 return (optimize
> 0 && !BYTES_BIG_ENDIAN
&& TARGET_VSX
35171 && rs6000_optimize_swaps
);
35174 virtual unsigned int execute (function
*fun
)
35176 return rs6000_analyze_swaps (fun
);
35179 }; // class pass_analyze_swaps
35182 make_pass_analyze_swaps (gcc::context
*ctxt
)
35184 return new pass_analyze_swaps (ctxt
);
35187 #ifdef RS6000_GLIBC_ATOMIC_FENV
35188 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
35189 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
35192 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
35195 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
35197 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
)
35199 #ifdef RS6000_GLIBC_ATOMIC_FENV
35200 if (atomic_hold_decl
== NULL_TREE
)
35203 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
35204 get_identifier ("__atomic_feholdexcept"),
35205 build_function_type_list (void_type_node
,
35206 double_ptr_type_node
,
35208 TREE_PUBLIC (atomic_hold_decl
) = 1;
35209 DECL_EXTERNAL (atomic_hold_decl
) = 1;
35212 if (atomic_clear_decl
== NULL_TREE
)
35215 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
35216 get_identifier ("__atomic_feclearexcept"),
35217 build_function_type_list (void_type_node
,
35219 TREE_PUBLIC (atomic_clear_decl
) = 1;
35220 DECL_EXTERNAL (atomic_clear_decl
) = 1;
35223 tree const_double
= build_qualified_type (double_type_node
,
35225 tree const_double_ptr
= build_pointer_type (const_double
);
35226 if (atomic_update_decl
== NULL_TREE
)
35229 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
35230 get_identifier ("__atomic_feupdateenv"),
35231 build_function_type_list (void_type_node
,
35234 TREE_PUBLIC (atomic_update_decl
) = 1;
35235 DECL_EXTERNAL (atomic_update_decl
) = 1;
35238 tree fenv_var
= create_tmp_var (double_type_node
);
35239 mark_addressable (fenv_var
);
35240 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
35242 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
35243 *clear
= build_call_expr (atomic_clear_decl
, 0);
35244 *update
= build_call_expr (atomic_update_decl
, 1,
35245 fold_convert (const_double_ptr
, fenv_addr
));
35250 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
35251 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
35252 tree call_mffs
= build_call_expr (mffs
, 0);
35254 /* Generates the equivalent of feholdexcept (&fenv_var)
35256 *fenv_var = __builtin_mffs ();
35258 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
35259 __builtin_mtfsf (0xff, fenv_hold); */
35261 /* Mask to clear everything except for the rounding modes and non-IEEE
35262 arithmetic flag. */
35263 const unsigned HOST_WIDE_INT hold_exception_mask
=
35264 HOST_WIDE_INT_C (0xffffffff00000007);
35266 tree fenv_var
= create_tmp_var (double_type_node
);
35268 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
35270 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
35271 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
35272 build_int_cst (uint64_type_node
,
35273 hold_exception_mask
));
35275 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
35278 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
35279 build_int_cst (unsigned_type_node
, 0xff),
35282 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
35284 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
35286 double fenv_clear = __builtin_mffs ();
35287 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
35288 __builtin_mtfsf (0xff, fenv_clear); */
35290 /* Mask to clear everything except for the rounding modes and non-IEEE
35291 arithmetic flag. */
35292 const unsigned HOST_WIDE_INT clear_exception_mask
=
35293 HOST_WIDE_INT_C (0xffffffff00000000);
35295 tree fenv_clear
= create_tmp_var (double_type_node
);
35297 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
35299 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
35300 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
35302 build_int_cst (uint64_type_node
,
35303 clear_exception_mask
));
35305 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
35306 fenv_clear_llu_and
);
35308 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
35309 build_int_cst (unsigned_type_node
, 0xff),
35312 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
35314 /* Generates the equivalent of feupdateenv (&fenv_var)
35316 double old_fenv = __builtin_mffs ();
35317 double fenv_update;
35318 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
35319 (*(uint64_t*)fenv_var 0x1ff80fff);
35320 __builtin_mtfsf (0xff, fenv_update); */
35322 const unsigned HOST_WIDE_INT update_exception_mask
=
35323 HOST_WIDE_INT_C (0xffffffff1fffff00);
35324 const unsigned HOST_WIDE_INT new_exception_mask
=
35325 HOST_WIDE_INT_C (0x1ff80fff);
35327 tree old_fenv
= create_tmp_var (double_type_node
);
35328 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
35330 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
35331 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
35332 build_int_cst (uint64_type_node
,
35333 update_exception_mask
));
35335 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
35336 build_int_cst (uint64_type_node
,
35337 new_exception_mask
));
35339 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
35340 old_llu_and
, new_llu_and
);
35342 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
35345 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
35346 build_int_cst (unsigned_type_node
, 0xff),
35347 fenv_update_mtfsf
);
35349 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
35353 struct gcc_target targetm
= TARGET_INITIALIZER
;
35355 #include "gt-rs6000.h"