1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C)
2005-
2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version
3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return
1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return
1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return
1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return
1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have
64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return
1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand
0 "register_operand")
68 if (GET_CODE (op) == SUBREG)
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return
1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand
0 "register_operand")
89 if (GET_CODE (op) == SUBREG)
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand
0 "register_operand")
110 if (GET_CODE (op) == SUBREG)
111 op = SUBREG_REG (op);
116 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return
1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand
0 "register_operand")
127 if (GET_CODE (op) == SUBREG)
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return
1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand
0 "register_operand")
149 if (GET_CODE (op) == SUBREG)
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return
1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand
0 "register_operand")
171 if (GET_CODE (op) == SUBREG)
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return
1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand
0 "register_operand")
193 if (GET_CODE (op) == SUBREG)
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return
1 if op is a signed
5-bit constant integer.
203 (define_predicate "s5bit_cint_operand"
204 (and (match_code "const_int")
205 (match_test "INTVAL (op) >= -
16 && INTVAL (op) <=
15")))
207 ;; Return
1 if op is a unsigned
3-bit constant integer.
208 (define_predicate "u3bit_cint_operand"
209 (and (match_code "const_int")
210 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
7")))
212 ;; Return
1 if op is a unsigned
5-bit constant integer.
213 (define_predicate "u5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
31")))
217 ;; Return
1 if op is a unsigned
6-bit constant integer.
218 (define_predicate "u6bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
63")))
222 ;; Return
1 if op is an unsigned
7-bit constant integer.
223 (define_predicate "u7bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "IN_RANGE (INTVAL (op),
0,
127)")))
227 ;; Return
1 if op is a signed
8-bit constant integer.
228 ;; Integer multiplication complete more quickly
229 (define_predicate "s8bit_cint_operand"
230 (and (match_code "const_int")
231 (match_test "INTVAL (op) >= -
128 && INTVAL (op) <=
127")))
233 ;; Return
1 if op is a unsigned
10-bit constant integer.
234 (define_predicate "u10bit_cint_operand"
235 (and (match_code "const_int")
236 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1023")))
238 ;; Return
1 if op is a constant integer that can fit in a D field.
239 (define_predicate "short_cint_operand"
240 (and (match_code "const_int")
241 (match_test "satisfies_constraint_I (op)")))
243 ;; Return
1 if op is a constant integer that can fit in an unsigned D field.
244 (define_predicate "u_short_cint_operand"
245 (and (match_code "const_int")
246 (match_test "satisfies_constraint_K (op)")))
248 ;; Return
1 if op is a constant integer that is a signed
16-bit constant
249 ;; shifted left
16 bits
250 (define_predicate "upper16_cint_operand"
251 (and (match_code "const_int")
252 (match_test "satisfies_constraint_L (op)")))
254 ;; Return
1 if op is a constant integer that cannot fit in a signed D field.
255 (define_predicate "non_short_cint_operand"
256 (and (match_code "const_int")
257 (match_test "(unsigned HOST_WIDE_INT)
258 (INTVAL (op) +
0x8000) >=
0x10000")))
260 ;; Return
1 if op is a positive constant integer that is an exact power of
2.
261 (define_predicate "exact_log2_cint_operand"
262 (and (match_code "const_int")
263 (match_test "INTVAL (op) >
0 && exact_log2 (INTVAL (op)) >=
0")))
265 ;; Match op =
0 or op =
1.
266 (define_predicate "const_0_to_1_operand"
267 (and (match_code "const_int")
268 (match_test "IN_RANGE (INTVAL (op),
0,
1)")))
271 (define_predicate "const_0_to_3_operand"
272 (and (match_code "const_int")
273 (match_test "IN_RANGE (INTVAL (op),
0,
3)")))
275 ;; Match op =
2 or op =
3.
276 (define_predicate "const_2_to_3_operand"
277 (and (match_code "const_int")
278 (match_test "IN_RANGE (INTVAL (op),
2,
3)")))
281 (define_predicate "const_0_to_7_operand"
282 (and (match_code "const_int")
283 (match_test "IN_RANGE (INTVAL (op),
0,
7)")))
286 (define_predicate "const_0_to_12_operand"
287 (and (match_code "const_int")
288 (match_test "IN_RANGE (INTVAL (op),
0,
12)")))
291 (define_predicate "const_0_to_15_operand"
292 (and (match_code "const_int")
293 (match_test "IN_RANGE (INTVAL (op),
0,
15)")))
295 ;; Return
1 if op is a register that is not special.
296 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
297 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
298 ;; the fact that SFmode is represented as DFmode in the VSX registers.
299 (define_predicate "gpc_reg_operand"
300 (match_operand
0 "register_operand")
302 if (GET_CODE (op) == SUBREG)
304 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
307 op = SUBREG_REG (op);
313 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
316 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
319 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
322 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
325 ;; Return
1 if op is a general purpose register. Unlike gpc_reg_operand, don't
326 ;; allow floating point or vector registers. Since vector registers are not
327 ;; allowed, we don't have to reject SFmode/SImode subregs.
328 (define_predicate "int_reg_operand"
329 (match_operand
0 "register_operand")
331 if (GET_CODE (op) == SUBREG)
333 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
336 op = SUBREG_REG (op);
342 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
345 return INT_REGNO_P (REGNO (op));
348 ;; Like int_reg_operand, but don't return true for pseudo registers
349 ;; We don't have to check for SF SUBREGS because pseudo registers
350 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
351 (define_predicate "int_reg_operand_not_pseudo"
352 (match_operand
0 "register_operand")
354 if (GET_CODE (op) == SUBREG)
355 op = SUBREG_REG (op);
360 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
363 return INT_REGNO_P (REGNO (op));
366 ;; Like int_reg_operand, but only return true for base registers
367 (define_predicate "base_reg_operand"
368 (match_operand
0 "int_reg_operand")
370 if (GET_CODE (op) == SUBREG)
371 op = SUBREG_REG (op);
376 return (REGNO (op) != FIRST_GPR_REGNO);
380 ;; Return true if this is a traditional floating point register
381 (define_predicate "fpr_reg_operand"
382 (match_code "reg,subreg")
386 if (GET_CODE (op) == SUBREG)
387 op = SUBREG_REG (op);
393 if (r >= FIRST_PSEUDO_REGISTER)
396 return FP_REGNO_P (r);
399 ;; Return true if this is a register that can has D-form addressing (GPR and
400 ;; traditional FPR registers for scalars). ISA
3.0 (power9) adds D-form
401 ;; addressing for scalars in Altivec registers.
403 ;; If this is a pseudo only allow for GPR fusion in power8. If we have the
404 ;; power9 fusion allow the floating point types.
405 (define_predicate "toc_fusion_or_p9_reg_operand"
406 (match_code "reg,subreg")
409 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode
411 || (TARGET_POWERPC64 && (mode == DImode || mode == DFmode)));
412 bool fpr_p = (TARGET_P9_FUSION
413 && (mode == DFmode || mode == SFmode
414 || (TARGET_POWERPC64 && mode == DImode)));
415 bool vmx_p = (TARGET_P9_FUSION && TARGET_P9_VECTOR
416 && (mode == DFmode || mode == SFmode));
418 if (!TARGET_P8_FUSION)
421 if (GET_CODE (op) == SUBREG)
422 op = SUBREG_REG (op);
428 if (r >= FIRST_PSEUDO_REGISTER)
429 return (gpr_p || fpr_p || vmx_p);
437 if (ALTIVEC_REGNO_P (r))
443 ;; Return
1 if op is a HTM specific SPR register.
444 (define_predicate "htm_spr_reg_operand"
445 (match_operand
0 "register_operand")
450 if (GET_CODE (op) == SUBREG)
451 op = SUBREG_REG (op);
470 ;; Return
1 if op is a general purpose register that is an even register
471 ;; which suitable for a load/store quad operation
472 ;; Subregs are not allowed here because when they are combine can
473 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
474 ;; think the innermost reg needs reloading, in TImode instead of
475 ;; PTImode. So reload will choose a reg in TImode which has no
476 ;; requirement that the reg be even.
477 (define_predicate "quad_int_reg_operand"
482 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
486 if (r >= FIRST_PSEUDO_REGISTER)
489 return (INT_REGNO_P (r) && ((r &
1) ==
0));
492 ;; Return
1 if op is a register that is a condition register field.
493 (define_predicate "cc_reg_operand"
494 (match_operand
0 "register_operand")
496 if (GET_CODE (op) == SUBREG)
497 op = SUBREG_REG (op);
502 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
505 return CR_REGNO_P (REGNO (op));
508 ;; Return
1 if op is a register that is a condition register field not cr0.
509 (define_predicate "cc_reg_not_cr0_operand"
510 (match_operand
0 "register_operand")
512 if (GET_CODE (op) == SUBREG)
513 op = SUBREG_REG (op);
518 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
521 return CR_REGNO_NOT_CR0_P (REGNO (op));
524 ;; Return
1 if op is a constant integer valid for D field
525 ;; or non-special register register.
526 (define_predicate "reg_or_short_operand"
527 (if_then_else (match_code "const_int")
528 (match_operand
0 "short_cint_operand")
529 (match_operand
0 "gpc_reg_operand")))
531 ;; Return
1 if op is a constant integer valid for DS field
532 ;; or non-special register.
533 (define_predicate "reg_or_aligned_short_operand"
534 (if_then_else (match_code "const_int")
535 (and (match_operand
0 "short_cint_operand")
536 (match_test "!(INTVAL (op) &
3)"))
537 (match_operand
0 "gpc_reg_operand")))
539 ;; Return
1 if op is a constant integer whose high-order
16 bits are zero
540 ;; or non-special register.
541 (define_predicate "reg_or_u_short_operand"
542 (if_then_else (match_code "const_int")
543 (match_operand
0 "u_short_cint_operand")
544 (match_operand
0 "gpc_reg_operand")))
546 ;; Return
1 if op is any constant integer
547 ;; or non-special register.
548 (define_predicate "reg_or_cint_operand"
549 (ior (match_code "const_int")
550 (match_operand
0 "gpc_reg_operand")))
552 ;; Return
1 if op is a constant integer valid for addition with addis, addi.
553 (define_predicate "add_cint_operand"
554 (and (match_code "const_int")
555 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
556 + (mode == SImode ?
0x80000000 :
0x80008000))
557 < (unsigned HOST_WIDE_INT)
0x100000000ll")))
559 ;; Return
1 if op is a constant integer valid for addition
560 ;; or non-special register.
561 (define_predicate "reg_or_add_cint_operand"
562 (if_then_else (match_code "const_int")
563 (match_operand
0 "add_cint_operand")
564 (match_operand
0 "gpc_reg_operand")))
566 ;; Return
1 if op is a constant integer valid for subtraction
567 ;; or non-special register.
568 (define_predicate "reg_or_sub_cint_operand"
569 (if_then_else (match_code "const_int")
570 (match_test "(unsigned HOST_WIDE_INT)
571 (- UINTVAL (op) + (mode == SImode ?
0x80000000 :
0x80008000))
572 < (unsigned HOST_WIDE_INT)
0x100000000ll")
573 (match_operand
0 "gpc_reg_operand")))
575 ;; Return
1 if op is any
32-bit unsigned constant integer
576 ;; or non-special register.
577 (define_predicate "reg_or_logical_cint_operand"
578 (if_then_else (match_code "const_int")
579 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
581 || ((INTVAL (op) & GET_MODE_MASK (mode)
582 & (~ (unsigned HOST_WIDE_INT)
0xffffffff)) ==
0)")
583 (match_operand
0 "gpc_reg_operand")))
585 ;; Like reg_or_logical_cint_operand, but allow vsx registers
586 (define_predicate "vsx_reg_or_cint_operand"
587 (ior (match_operand
0 "vsx_register_operand")
588 (match_operand
0 "reg_or_logical_cint_operand")))
590 ;; Return
1 if operand is a CONST_DOUBLE that can be set in a register
591 ;; with no more than one instruction per word.
592 (define_predicate "easy_fp_constant"
593 (match_code "const_double")
595 if (GET_MODE (op) != mode
596 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
599 /* Consider all constants with -msoft-float to be easy. */
600 if ((TARGET_SOFT_FLOAT
601 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
605 /*
0.0D is not all zero bits. */
606 if (DECIMAL_FLOAT_MODE_P (mode))
609 /* The constant
0.0 is easy under VSX. */
610 if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode))
613 /* If we are using V
.4 style PIC, consider all constants to be hard. */
614 if (flag_pic && DEFAULT_ABI == ABI_V4)
617 /* If we have real FPRs, consider floating point constants hard (other than
618 0.0 under VSX), so that the constant gets pushed to memory during the
619 early RTL phases. This has the advantage that double precision constants
620 that can be represented in single precision without a loss of precision
621 will use single precision loads. */
633 return (num_insns_constant (op, DImode) <=
2);
643 ;; Return
1 if the operand is a constant that can loaded with a XXSPLTIB
644 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
646 (define_predicate "xxspltib_constant_split"
647 (match_code "const_vector,vec_duplicate,const_int")
652 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
655 return num_insns >
1;
659 ;; Return
1 if the operand is constant that can loaded directly with a XXSPLTIB
662 (define_predicate "xxspltib_constant_nosplit"
663 (match_code "const_vector,vec_duplicate,const_int")
668 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
671 return num_insns ==
1;
674 ;; Return
1 if the operand is a CONST_VECTOR and can be loaded into a
675 ;; vector register without using memory.
676 (define_predicate "easy_vector_constant"
677 (match_code "const_vector")
679 /* As the paired vectors are actually FPRs it seems that there is
680 no easy way to load a CONST_VECTOR without using memory. */
681 if (TARGET_PAIRED_FLOAT)
684 /* Because IEEE
128-bit floating point is considered a vector type
685 in order to pass it in VSX registers, it might use this function
686 instead of easy_fp_constant. */
687 if (FLOAT128_VECTOR_P (mode))
688 return easy_fp_constant (op, mode);
690 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
695 if (zero_constant (op, mode) || all_ones_constant (op, mode))
699 && xxspltib_constant_p (op, mode, &num_insns, &value))
702 return easy_altivec_constant (op, mode);
708 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
709 (define_predicate "easy_vector_constant_add_self"
710 (and (match_code "const_vector")
711 (and (match_test "TARGET_ALTIVEC")
712 (match_test "easy_altivec_constant (op, mode)")))
716 if (mode == V2DImode || mode == V2DFmode)
718 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
719 val = const_vector_elt_as_int (op, elt);
720 val = ((val &
0xff) ^
0x80) -
0x80;
721 return EASY_VECTOR_15_ADD_SELF (val);
724 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
725 (define_predicate "easy_vector_constant_msb"
726 (and (match_code "const_vector")
727 (and (match_test "TARGET_ALTIVEC")
728 (match_test "easy_altivec_constant (op, mode)")))
732 if (mode == V2DImode || mode == V2DFmode)
734 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
735 val = const_vector_elt_as_int (op, elt);
736 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
739 ;; Return true if this is an easy altivec constant that we form
741 (define_predicate "easy_vector_constant_vsldoi"
742 (and (match_code "const_vector")
743 (and (match_test "TARGET_ALTIVEC")
744 (and (match_test "easy_altivec_constant (op, mode)")
745 (match_test "vspltis_shifted (op) !=
0")))))
747 ;; Return
1 if operand is constant zero (scalars and vectors).
748 (define_predicate "zero_constant"
749 (and (match_code "const_int,const_double,const_wide_int,const_vector")
750 (match_test "op == CONST0_RTX (mode)")))
752 ;; Return
1 if operand is constant -
1 (scalars and vectors).
753 (define_predicate "all_ones_constant"
754 (and (match_code "const_int,const_double,const_wide_int,const_vector")
755 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
757 ;; Return
1 if operand is a vector int register or is either a vector constant
758 ;; of all
0 bits of a vector constant of all
1 bits.
759 (define_predicate "vector_int_reg_or_same_bit"
760 (match_code "reg,subreg,const_vector")
762 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
765 else if (REG_P (op) || SUBREG_P (op))
766 return vint_operand (op, mode);
769 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
772 ;; Return
1 if operand is
0.0.
773 (define_predicate "zero_fp_constant"
774 (and (match_code "const_double")
775 (match_test "SCALAR_FLOAT_MODE_P (mode)
776 && op == CONST0_RTX (mode)")))
778 ;; Return
1 if the operand is in volatile memory. Note that during the
779 ;; RTL generation phase, memory_operand does not return TRUE for volatile
780 ;; memory references. So this function allows us to recognize volatile
781 ;; references where it's safe.
782 (define_predicate "volatile_mem_operand"
783 (and (and (match_code "mem")
784 (match_test "MEM_VOLATILE_P (op)"))
785 (if_then_else (match_test "reload_completed")
786 (match_operand
0 "memory_operand")
787 (match_test "memory_address_p (mode, XEXP (op,
0))"))))
789 ;; Return
1 if the operand is an offsettable memory operand.
790 (define_predicate "offsettable_mem_operand"
791 (and (match_operand
0 "memory_operand")
792 (match_test "offsettable_nonstrict_memref_p (op)")))
794 ;; Return
1 if the operand is a simple offsettable memory operand
795 ;; that does not include pre-increment, post-increment, etc.
796 (define_predicate "simple_offsettable_mem_operand"
797 (match_operand
0 "offsettable_mem_operand")
799 rtx addr = XEXP (op,
0);
801 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
804 if (!CONSTANT_P (XEXP (addr,
1)))
807 return base_reg_operand (XEXP (addr,
0), Pmode);
810 ;; Return
1 if the operand is suitable for load/store quad memory.
811 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
812 (define_predicate "quad_memory_operand"
815 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
818 if (GET_MODE_SIZE (mode) !=
16 || !MEM_P (op) || MEM_ALIGN (op) <
128)
821 return quad_address_p (XEXP (op,
0), mode, false);
824 ;; Return
1 if the operand is suitable for load/store to vector registers with
825 ;; d-form addressing (register+offset), which was added in ISA
3.0.
826 ;; Unlike quad_memory_operand, we do not have to check for alignment.
827 (define_predicate "vsx_quad_dform_memory_operand"
830 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) !=
16)
833 return quad_address_p (XEXP (op,
0), mode, false);
836 ;; Return
1 if the operand is an indexed or indirect memory operand.
837 (define_predicate "indexed_or_indirect_operand"
841 if (VECTOR_MEM_ALTIVEC_P (mode)
842 && GET_CODE (op) == AND
843 && GET_CODE (XEXP (op,
1)) == CONST_INT
844 && INTVAL (XEXP (op,
1)) == -
16)
847 return indexed_or_indirect_address (op, mode);
850 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
851 ;; moves are supported.
852 (define_predicate "reg_or_indexed_operand"
853 (match_code "mem,reg,subreg")
856 return indexed_or_indirect_operand (op, mode);
857 else if (TARGET_DIRECT_MOVE)
858 return register_operand (op, mode);
863 ;; Return
1 if the operand is an indexed or indirect memory operand with an
864 ;; AND -
16 in it, used to recognize when we need to switch to Altivec loads
865 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
866 ;; while VSX uses the full address and traps)
867 (define_predicate "altivec_indexed_or_indirect_operand"
871 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
872 && GET_CODE (op) == AND
873 && GET_CODE (XEXP (op,
1)) == CONST_INT
874 && INTVAL (XEXP (op,
1)) == -
16)
875 return indexed_or_indirect_address (XEXP (op,
0), mode);
880 ;; Return
1 if the operand is an indexed or indirect address.
881 (define_special_predicate "indexed_or_indirect_address"
882 (and (match_test "REG_P (op)
883 || (GET_CODE (op) == PLUS
884 /* Omit testing REG_P (XEXP (op,
0)). */
885 && REG_P (XEXP (op,
1)))")
886 (match_operand
0 "address_operand")))
888 ;; Return
1 if the operand is an index-form address.
889 (define_special_predicate "indexed_address"
890 (match_test "(GET_CODE (op) == PLUS
891 && REG_P (XEXP (op,
0))
892 && REG_P (XEXP (op,
1)))"))
894 ;; Return
1 if the operand is a MEM with an update-form address. This may
895 ;; also include update-indexed form.
896 (define_special_predicate "update_address_mem"
897 (match_test "(MEM_P (op)
898 && (GET_CODE (XEXP (op,
0)) == PRE_INC
899 || GET_CODE (XEXP (op,
0)) == PRE_DEC
900 || GET_CODE (XEXP (op,
0)) == PRE_MODIFY))"))
902 ;; Return
1 if the operand is a MEM with an indexed-form address.
903 (define_special_predicate "indexed_address_mem"
904 (match_test "(MEM_P (op)
905 && (indexed_address (XEXP (op,
0), mode)
906 || (GET_CODE (XEXP (op,
0)) == PRE_MODIFY
907 && indexed_address (XEXP (XEXP (op,
0),
1), mode))))"))
909 ;; Return
1 if the operand is either a non-special register or can be used
910 ;; as the operand of a
`mode' add insn.
911 (define_predicate "add_operand"
912 (if_then_else (match_code "const_int")
913 (match_test "satisfies_constraint_I (op)
914 || satisfies_constraint_L (op)")
915 (match_operand 0 "gpc_reg_operand")))
917 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
918 (define_predicate "adde_operand"
919 (if_then_else (match_code "const_int")
920 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
921 (match_operand 0 "gpc_reg_operand")))
923 ;; Return 1 if OP is a constant but not a valid add_operand.
924 (define_predicate "non_add_cint_operand"
925 (and (match_code "const_int")
926 (match_test "!satisfies_constraint_I (op)
927 && !satisfies_constraint_L (op)")))
929 ;; Return 1 if the operand is a constant that can be used as the operand
931 (define_predicate "logical_const_operand"
932 (match_code "const_int")
936 opl = INTVAL (op) & GET_MODE_MASK (mode);
938 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
939 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
942 ;; Return 1 if the operand is a non-special register or a constant that
943 ;; can be used as the operand of an OR or XOR.
944 (define_predicate "logical_operand"
945 (ior (match_operand 0 "gpc_reg_operand")
946 (match_operand 0 "logical_const_operand")))
948 ;; Return 1 if op is a constant that is not a logical operand, but could
949 ;; be split into one.
950 (define_predicate "non_logical_cint_operand"
951 (and (match_code "const_int,const_wide_int")
952 (and (not (match_operand 0 "logical_operand"))
953 (match_operand 0 "reg_or_logical_cint_operand"))))
955 ;; Return 1 if the operand is either a non-special register or a
956 ;; constant that can be used as the operand of a logical AND.
957 (define_predicate "and_operand"
958 (ior (and (match_code "const_int")
959 (match_test "rs6000_is_valid_and_mask (op, mode)"))
960 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
961 (match_operand 0 "gpc_reg_operand")
962 (match_operand 0 "logical_operand"))))
964 ;; Return 1 if the operand is either a logical operand or a short cint operand.
965 (define_predicate "scc_eq_operand"
966 (ior (match_operand 0 "logical_operand")
967 (match_operand 0 "short_cint_operand")))
969 ;; Return 1 if the operand is a general non-special register or memory operand.
970 (define_predicate "reg_or_mem_operand"
971 (ior (match_operand 0 "memory_operand")
972 (and (match_code "mem")
973 (match_test "macho_lo_sum_memory_operand (op, mode)"))
974 (match_operand 0 "volatile_mem_operand")
975 (match_operand 0 "gpc_reg_operand")))
977 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
978 (define_predicate "zero_reg_mem_operand"
979 (ior (and (match_test "TARGET_VSX")
980 (match_operand 0 "zero_fp_constant"))
981 (match_operand 0 "reg_or_mem_operand")))
983 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
984 ;; data types inside of a vector that scalar instructions operate on
985 (define_predicate "vsx_scalar_64bit"
986 (match_code "const_int")
988 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
991 ;; Return 1 if the operand is a general register or memory operand without
992 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
994 (define_predicate "lwa_operand"
995 (match_code "reg,subreg,mem")
997 rtx inner, addr, offset;
1000 if (reload_completed && GET_CODE (inner) == SUBREG)
1001 inner = SUBREG_REG (inner);
1003 if (gpc_reg_operand (inner, mode))
1005 if (!memory_operand (inner, mode))
1008 addr = XEXP (inner, 0);
1009 if (GET_CODE (addr) == PRE_INC
1010 || GET_CODE (addr) == PRE_DEC
1011 || (GET_CODE (addr) == PRE_MODIFY
1012 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1014 if (GET_CODE (addr) == LO_SUM
1015 && GET_CODE (XEXP (addr, 0)) == REG
1016 && GET_CODE (XEXP (addr, 1)) == CONST)
1017 addr = XEXP (XEXP (addr, 1), 0);
1018 if (GET_CODE (addr) != PLUS)
1020 offset = XEXP (addr, 1);
1021 if (GET_CODE (offset) != CONST_INT)
1023 return INTVAL (offset) % 4 == 0;
1026 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1027 (define_predicate "symbol_ref_operand"
1028 (and (match_code "symbol_ref")
1029 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1030 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1032 ;; Return 1 if op is an operand that can be loaded via the GOT.
1033 ;; or non-special register register field no cr0
1034 (define_predicate "got_operand"
1035 (match_code "symbol_ref,const,label_ref"))
1037 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1038 ;; excluding labels involving addition.
1039 (define_predicate "got_no_const_operand"
1040 (match_code "symbol_ref,label_ref"))
1042 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1043 (define_predicate "rs6000_tls_symbol_ref"
1044 (and (match_code "symbol_ref")
1045 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1047 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1048 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1049 (define_predicate "call_operand"
1050 (if_then_else (match_code "reg")
1051 (match_test "REGNO (op) == LR_REGNO
1052 || REGNO (op) == CTR_REGNO
1053 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1054 (match_code "symbol_ref")))
1056 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1058 (define_predicate "current_file_function_operand"
1059 (and (match_code "symbol_ref")
1060 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1061 && (SYMBOL_REF_LOCAL_P (op)
1062 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1063 && !decl_replaceable_p (current_function_decl)))
1064 && !((DEFAULT_ABI == ABI_AIX
1065 || DEFAULT_ABI == ABI_ELFv2)
1066 && (SYMBOL_REF_EXTERNAL_P (op)
1067 || SYMBOL_REF_WEAK (op)))")))
1069 ;; Return 1 if this operand is a valid input for a move insn.
1070 (define_predicate "input_operand"
1071 (match_code "symbol_ref,const,reg,subreg,mem,
1072 const_double,const_wide_int,const_vector,const_int")
1074 /* Memory is always valid. */
1075 if (memory_operand (op, mode))
1078 /* For floating-point, easy constants are valid. */
1079 if (SCALAR_FLOAT_MODE_P (mode)
1080 && easy_fp_constant (op, mode))
1083 /* Allow any integer constant. */
1084 if (GET_MODE_CLASS (mode) == MODE_INT
1085 && CONST_SCALAR_INT_P (op))
1088 /* Allow easy vector constants. */
1089 if (GET_CODE (op) == CONST_VECTOR
1090 && easy_vector_constant (op, mode))
1093 /* For floating-point or multi-word mode, the only remaining valid type
1095 if (SCALAR_FLOAT_MODE_P (mode)
1096 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1097 return register_operand (op, mode);
1099 /* We don't allow moving the carry bit around. */
1100 if (ca_operand (op, mode))
1103 /* The only cases left are integral modes one word or smaller (we
1104 do not get called for MODE_CC values). These can be in any
1106 if (register_operand (op, mode))
1109 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1111 if (DEFAULT_ABI == ABI_V4
1112 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1113 && small_data_operand (op, Pmode))
1119 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1120 (define_predicate "splat_input_operand"
1121 (match_code "reg,subreg,mem")
1127 else if (mode == DImode)
1129 else if (mode == SImode && TARGET_P9_VECTOR)
1131 else if (mode == SFmode && TARGET_P9_VECTOR)
1138 rtx addr = XEXP (op, 0);
1140 if (! volatile_ok && MEM_VOLATILE_P (op))
1143 if (lra_in_progress || reload_completed)
1144 return indexed_or_indirect_address (addr, vmode);
1146 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1148 return gpc_reg_operand (op, mode);
1151 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1152 (define_predicate "rotate_mask_operator"
1153 (match_code "rotate,ashift,lshiftrt"))
1155 ;; Return true if operand is boolean operator.
1156 (define_predicate "boolean_operator"
1157 (match_code "and,ior,xor"))
1159 ;; Return true if operand is OR-form of boolean operator.
1160 (define_predicate "boolean_or_operator"
1161 (match_code "ior,xor"))
1163 ;; Return true if operand is an equality operator.
1164 (define_special_predicate "equality_operator"
1165 (match_code "eq,ne"))
1167 ;; Return 1 if OP is a comparison operation that is valid for a branch
1168 ;; instruction. We check the opcode against the mode of the CC value.
1169 ;; validate_condition_mode is an assertion.
1170 (define_predicate "branch_comparison_operator"
1171 (and (match_operand 0 "comparison_operator")
1172 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1173 (match_test "validate_condition_mode (GET_CODE (op),
1174 GET_MODE (XEXP (op, 0))),
1177 ;; Return 1 if OP is an unsigned comparison operator.
1178 (define_predicate "unsigned_comparison_operator"
1179 (match_code "ltu,gtu,leu,geu"))
1181 ;; Return 1 if OP is a signed comparison operator.
1182 (define_predicate "signed_comparison_operator"
1183 (match_code "lt,gt,le,ge"))
1185 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1186 ;; it must be a positive comparison.
1187 (define_predicate "scc_comparison_operator"
1188 (and (match_operand 0 "branch_comparison_operator")
1189 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1191 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1193 (define_predicate "scc_rev_comparison_operator"
1194 (and (match_operand 0 "branch_comparison_operator")
1195 (match_code "ne,le,ge,leu,geu,ordered")))
1197 ;; Return 1 if OP is a comparison operator suitable for floating point
1198 ;; vector/scalar comparisons that generate a -1/0 mask.
1199 (define_predicate "fpmask_comparison_operator"
1200 (match_code "eq,gt,ge"))
1202 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1203 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1204 ;; fpmask_comparison_operator).
1205 (define_predicate "invert_fpmask_comparison_operator"
1206 (match_code "ne,unlt,unle"))
1208 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1209 ;; comparisons that generate a -1/0 mask.
1210 (define_predicate "vecint_comparison_operator"
1211 (match_code "eq,gt,gtu"))
1213 ;; Return 1 if OP is a comparison operation that is valid for a branch
1214 ;; insn, which is true if the corresponding bit in the CC register is set.
1215 (define_predicate "branch_positive_comparison_operator"
1216 (and (match_operand 0 "branch_comparison_operator")
1217 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1219 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1220 (define_predicate "load_multiple_operation"
1221 (match_code "parallel")
1223 int count = XVECLEN (op, 0);
1224 unsigned int dest_regno;
1228 /* Perform a quick check so we don't blow up below. */
1230 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1231 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1232 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1235 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1236 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1238 for (i = 1; i < count; i++)
1240 rtx elt = XVECEXP (op, 0, i);
1242 if (GET_CODE (elt) != SET
1243 || GET_CODE (SET_DEST (elt)) != REG
1244 || GET_MODE (SET_DEST (elt)) != SImode
1245 || REGNO (SET_DEST (elt)) != dest_regno + i
1246 || GET_CODE (SET_SRC (elt)) != MEM
1247 || GET_MODE (SET_SRC (elt)) != SImode
1248 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1249 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1250 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1251 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1258 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1259 ;; The second vector element is a CLOBBER.
1260 (define_predicate "store_multiple_operation"
1261 (match_code "parallel")
1263 int count = XVECLEN (op, 0) - 1;
1264 unsigned int src_regno;
1268 /* Perform a quick check so we don't blow up below. */
1270 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1271 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1272 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1275 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1276 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1278 for (i = 1; i < count; i++)
1280 rtx elt = XVECEXP (op, 0, i + 1);
1282 if (GET_CODE (elt) != SET
1283 || GET_CODE (SET_SRC (elt)) != REG
1284 || GET_MODE (SET_SRC (elt)) != SImode
1285 || REGNO (SET_SRC (elt)) != src_regno + i
1286 || GET_CODE (SET_DEST (elt)) != MEM
1287 || GET_MODE (SET_DEST (elt)) != SImode
1288 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1289 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1290 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1291 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1298 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1300 (define_predicate "save_world_operation"
1301 (match_code "parallel")
1306 int count = XVECLEN (op, 0);
1312 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1313 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1316 for (i=1; i <= 18; i++)
1318 elt = XVECEXP (op, 0, index++);
1319 if (GET_CODE (elt) != SET
1320 || GET_CODE (SET_DEST (elt)) != MEM
1321 || ! memory_operand (SET_DEST (elt), DFmode)
1322 || GET_CODE (SET_SRC (elt)) != REG
1323 || GET_MODE (SET_SRC (elt)) != DFmode)
1327 for (i=1; i <= 12; i++)
1329 elt = XVECEXP (op, 0, index++);
1330 if (GET_CODE (elt) != SET
1331 || GET_CODE (SET_DEST (elt)) != MEM
1332 || GET_CODE (SET_SRC (elt)) != REG
1333 || GET_MODE (SET_SRC (elt)) != V4SImode)
1337 for (i=1; i <= 19; i++)
1339 elt = XVECEXP (op, 0, index++);
1340 if (GET_CODE (elt) != SET
1341 || GET_CODE (SET_DEST (elt)) != MEM
1342 || ! memory_operand (SET_DEST (elt), Pmode)
1343 || GET_CODE (SET_SRC (elt)) != REG
1344 || GET_MODE (SET_SRC (elt)) != Pmode)
1348 elt = XVECEXP (op, 0, index++);
1349 if (GET_CODE (elt) != SET
1350 || GET_CODE (SET_DEST (elt)) != MEM
1351 || ! memory_operand (SET_DEST (elt), Pmode)
1352 || GET_CODE (SET_SRC (elt)) != REG
1353 || REGNO (SET_SRC (elt)) != CR2_REGNO
1354 || GET_MODE (SET_SRC (elt)) != Pmode)
1357 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1358 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1363 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1365 (define_predicate "restore_world_operation"
1366 (match_code "parallel")
1371 int count = XVECLEN (op, 0);
1377 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1378 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1379 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1380 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1383 elt = XVECEXP (op, 0, index++);
1384 if (GET_CODE (elt) != SET
1385 || GET_CODE (SET_SRC (elt)) != MEM
1386 || ! memory_operand (SET_SRC (elt), Pmode)
1387 || GET_CODE (SET_DEST (elt)) != REG
1388 || REGNO (SET_DEST (elt)) != CR2_REGNO
1389 || GET_MODE (SET_DEST (elt)) != Pmode)
1392 for (i=1; i <= 19; i++)
1394 elt = XVECEXP (op, 0, index++);
1395 if (GET_CODE (elt) != SET
1396 || GET_CODE (SET_SRC (elt)) != MEM
1397 || ! memory_operand (SET_SRC (elt), Pmode)
1398 || GET_CODE (SET_DEST (elt)) != REG
1399 || GET_MODE (SET_DEST (elt)) != Pmode)
1403 for (i=1; i <= 12; i++)
1405 elt = XVECEXP (op, 0, index++);
1406 if (GET_CODE (elt) != SET
1407 || GET_CODE (SET_SRC (elt)) != MEM
1408 || GET_CODE (SET_DEST (elt)) != REG
1409 || GET_MODE (SET_DEST (elt)) != V4SImode)
1413 for (i=1; i <= 18; i++)
1415 elt = XVECEXP (op, 0, index++);
1416 if (GET_CODE (elt) != SET
1417 || GET_CODE (SET_SRC (elt)) != MEM
1418 || ! memory_operand (SET_SRC (elt), DFmode)
1419 || GET_CODE (SET_DEST (elt)) != REG
1420 || GET_MODE (SET_DEST (elt)) != DFmode)
1424 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1425 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1426 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1427 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1428 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1433 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1434 (define_predicate "vrsave_operation"
1435 (match_code "parallel")
1437 int count = XVECLEN (op, 0);
1438 unsigned int dest_regno, src_regno;
1442 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1443 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1444 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1445 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1448 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1449 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1451 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1454 for (i = 1; i < count; i++)
1456 rtx elt = XVECEXP (op, 0, i);
1458 if (GET_CODE (elt) != CLOBBER
1459 && GET_CODE (elt) != SET)
1466 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1467 (define_predicate "mfcr_operation"
1468 (match_code "parallel")
1470 int count = XVECLEN (op, 0);
1473 /* Perform a quick check so we don't blow up below. */
1475 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1476 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1477 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1480 for (i = 0; i < count; i++)
1482 rtx exp = XVECEXP (op, 0, i);
1487 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1489 if (GET_CODE (src_reg) != REG
1490 || GET_MODE (src_reg) != CCmode
1491 || ! CR_REGNO_P (REGNO (src_reg)))
1494 if (GET_CODE (exp) != SET
1495 || GET_CODE (SET_DEST (exp)) != REG
1496 || GET_MODE (SET_DEST (exp)) != SImode
1497 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1499 unspec = SET_SRC (exp);
1500 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1502 if (GET_CODE (unspec) != UNSPEC
1503 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1504 || XVECLEN (unspec, 0) != 2
1505 || XVECEXP (unspec, 0, 0) != src_reg
1506 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1507 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1513 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1514 (define_predicate "mtcrf_operation"
1515 (match_code "parallel")
1517 int count = XVECLEN (op, 0);
1521 /* Perform a quick check so we don't blow up below. */
1523 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1524 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1525 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1527 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1529 if (GET_CODE (src_reg) != REG
1530 || GET_MODE (src_reg) != SImode
1531 || ! INT_REGNO_P (REGNO (src_reg)))
1534 for (i = 0; i < count; i++)
1536 rtx exp = XVECEXP (op, 0, i);
1540 if (GET_CODE (exp) != SET
1541 || GET_CODE (SET_DEST (exp)) != REG
1542 || GET_MODE (SET_DEST (exp)) != CCmode
1543 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1545 unspec = SET_SRC (exp);
1546 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1548 if (GET_CODE (unspec) != UNSPEC
1549 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1550 || XVECLEN (unspec, 0) != 2
1551 || XVECEXP (unspec, 0, 0) != src_reg
1552 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1553 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1559 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1560 (define_predicate "crsave_operation"
1561 (match_code "parallel")
1563 int count = XVECLEN (op, 0);
1566 for (i = 1; i < count; i++)
1568 rtx exp = XVECEXP (op, 0, i);
1570 if (GET_CODE (exp) != USE
1571 || GET_CODE (XEXP (exp, 0)) != REG
1572 || GET_MODE (XEXP (exp, 0)) != CCmode
1573 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1579 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1580 (define_predicate "lmw_operation"
1581 (match_code "parallel")
1583 int count = XVECLEN (op, 0);
1584 unsigned int dest_regno;
1586 unsigned int base_regno;
1587 HOST_WIDE_INT offset;
1590 /* Perform a quick check so we don't blow up below. */
1592 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1593 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1594 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1597 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1598 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1601 || count != 32 - (int) dest_regno)
1604 if (legitimate_indirect_address_p (src_addr, 0))
1607 base_regno = REGNO (src_addr);
1608 if (base_regno == 0)
1611 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1613 offset = INTVAL (XEXP (src_addr, 1));
1614 base_regno = REGNO (XEXP (src_addr, 0));
1619 for (i = 0; i < count; i++)
1621 rtx elt = XVECEXP (op, 0, i);
1624 HOST_WIDE_INT newoffset;
1626 if (GET_CODE (elt) != SET
1627 || GET_CODE (SET_DEST (elt)) != REG
1628 || GET_MODE (SET_DEST (elt)) != SImode
1629 || REGNO (SET_DEST (elt)) != dest_regno + i
1630 || GET_CODE (SET_SRC (elt)) != MEM
1631 || GET_MODE (SET_SRC (elt)) != SImode)
1633 newaddr = XEXP (SET_SRC (elt), 0);
1634 if (legitimate_indirect_address_p (newaddr, 0))
1639 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1641 addr_reg = XEXP (newaddr, 0);
1642 newoffset = INTVAL (XEXP (newaddr, 1));
1646 if (REGNO (addr_reg) != base_regno
1647 || newoffset != offset + 4 * i)
1654 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1655 (define_predicate "stmw_operation"
1656 (match_code "parallel")
1658 int count = XVECLEN (op, 0);
1659 unsigned int src_regno;
1661 unsigned int base_regno;
1662 HOST_WIDE_INT offset;
1665 /* Perform a quick check so we don't blow up below. */
1667 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1668 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1669 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1672 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1673 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1676 || count != 32 - (int) src_regno)
1679 if (legitimate_indirect_address_p (dest_addr, 0))
1682 base_regno = REGNO (dest_addr);
1683 if (base_regno == 0)
1686 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1688 offset = INTVAL (XEXP (dest_addr, 1));
1689 base_regno = REGNO (XEXP (dest_addr, 0));
1694 for (i = 0; i < count; i++)
1696 rtx elt = XVECEXP (op, 0, i);
1699 HOST_WIDE_INT newoffset;
1701 if (GET_CODE (elt) != SET
1702 || GET_CODE (SET_SRC (elt)) != REG
1703 || GET_MODE (SET_SRC (elt)) != SImode
1704 || REGNO (SET_SRC (elt)) != src_regno + i
1705 || GET_CODE (SET_DEST (elt)) != MEM
1706 || GET_MODE (SET_DEST (elt)) != SImode)
1708 newaddr = XEXP (SET_DEST (elt), 0);
1709 if (legitimate_indirect_address_p (newaddr, 0))
1714 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1716 addr_reg = XEXP (newaddr, 0);
1717 newoffset = INTVAL (XEXP (newaddr, 1));
1721 if (REGNO (addr_reg) != base_regno
1722 || newoffset != offset + 4 * i)
1729 ;; Return 1 if OP is a stack tie operand.
1730 (define_predicate "tie_operand"
1731 (match_code "parallel")
1733 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1734 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1735 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1736 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1739 ;; Match a small code model toc reference (or medium and large
1740 ;; model toc references before reload).
1741 (define_predicate "small_toc_ref"
1742 (match_code "unspec,plus")
1744 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1747 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1750 ;; Match the TOC memory operand that can be fused with an addis instruction.
1751 ;; This is used in matching a potential fused address before register
1753 (define_predicate "toc_fusion_mem_raw"
1756 if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ())
1759 return small_toc_ref (XEXP (op, 0), Pmode);
1762 ;; Match the memory operand that has been fused with an addis instruction and
1763 ;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper.
1764 (define_predicate "toc_fusion_mem_wrapped"
1769 if (!TARGET_TOC_FUSION_INT)
1775 addr = XEXP (op, 0);
1776 return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS);
1779 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1780 ;; GPR registers on power8.
1781 (define_predicate "fusion_gpr_addis"
1782 (match_code "const_int,high,plus")
1784 HOST_WIDE_INT value;
1787 if (GET_CODE (op) == HIGH)
1790 if (CONST_INT_P (op))
1793 else if (GET_CODE (op) == PLUS
1794 && base_reg_operand (XEXP (op, 0), Pmode)
1795 && CONST_INT_P (XEXP (op, 1)))
1796 int_const = XEXP (op, 1);
1801 value = INTVAL (int_const);
1802 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1805 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1808 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1809 value are all 1's or 0's. Ignore this restriction if we are testing
1811 if (TARGET_P9_FUSION)
1814 return (IN_RANGE (value >> 16, -32, 31));
1817 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1818 ;; and loads to GPR registers on power8.
1819 (define_predicate "fusion_gpr_mem_load"
1820 (match_code "mem,sign_extend,zero_extend")
1822 rtx addr, base, offset;
1824 /* Handle sign/zero extend. */
1825 if (GET_CODE (op) == ZERO_EXTEND
1826 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1829 mode = GET_MODE (op);
1843 if (!TARGET_POWERPC64)
1851 addr = XEXP (op, 0);
1852 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1855 base = XEXP (addr, 0);
1856 if (!base_reg_operand (base, GET_MODE (base)))
1859 offset = XEXP (addr, 1);
1861 if (GET_CODE (addr) == PLUS)
1862 return satisfies_constraint_I (offset);
1864 else if (GET_CODE (addr) == LO_SUM)
1866 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1867 return small_toc_ref (offset, GET_MODE (offset));
1869 else if (TARGET_ELF && !TARGET_POWERPC64)
1870 return CONSTANT_P (offset);
1876 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1877 ;; memory field with both the addis and the memory offset. Sign extension
1878 ;; is not handled here, since lha and lwa are not fused.
1879 ;; With P9 fusion, also match a fpr/vector load and float_extend
1880 (define_predicate "fusion_addis_mem_combo_load"
1881 (match_code "mem,zero_extend,float_extend")
1883 rtx addr, base, offset;
1885 /* Handle zero/float extend. */
1886 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1889 mode = GET_MODE (op);
1902 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1903 separate instructions. */
1905 if (!TARGET_POWERPC64)
1909 /* ISA 2.08/power8 only had fusion of GPR loads. */
1911 if (!TARGET_P9_FUSION)
1915 /* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit
1916 DFmode in 32-bit if -msoft-float since it splits into two separate
1919 if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION)
1927 addr = XEXP (op, 0);
1928 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1931 base = XEXP (addr, 0);
1932 if (!fusion_gpr_addis (base, GET_MODE (base)))
1935 offset = XEXP (addr, 1);
1936 if (GET_CODE (addr) == PLUS)
1937 return satisfies_constraint_I (offset);
1939 else if (GET_CODE (addr) == LO_SUM)
1941 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1942 return small_toc_ref (offset, GET_MODE (offset));
1944 else if (TARGET_ELF && !TARGET_POWERPC64)
1945 return CONSTANT_P (offset);
1951 ;; Like fusion_addis_mem_combo_load, but for stores
1952 (define_predicate "fusion_addis_mem_combo_store"
1955 rtx addr, base, offset;
1957 if (!MEM_P (op) || !TARGET_P9_FUSION)
1968 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1969 separate instructions. */
1971 if (!TARGET_POWERPC64)
1975 /* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits
1976 into two separate instructions. Do allow fusion if we have hardware
1979 if (!TARGET_POWERPC64 && !TARGET_DF_FPR)
1987 addr = XEXP (op, 0);
1988 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1991 base = XEXP (addr, 0);
1992 if (!fusion_gpr_addis (base, GET_MODE (base)))
1995 offset = XEXP (addr, 1);
1996 if (GET_CODE (addr) == PLUS)
1997 return satisfies_constraint_I (offset);
1999 else if (GET_CODE (addr) == LO_SUM)
2001 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
2002 return small_toc_ref (offset, GET_MODE (offset));
2004 else if (TARGET_ELF && !TARGET_POWERPC64)
2005 return CONSTANT_P (offset);
2011 ;; Return true if the operand is a float_extend or zero extend of an
2012 ;; offsettable memory operand suitable for use in fusion
2013 (define_predicate "fusion_offsettable_mem_operand"
2014 (match_code "mem,zero_extend,float_extend")
2016 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
2019 mode = GET_MODE (op);
2022 if (!memory_operand (op, mode))
2025 return offsettable_nonstrict_memref_p (op);