1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C)
2005-
2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version
3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return
1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return
1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return
1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return
1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (match_operand
0 "register_operand")
38 if (GET_CODE (op) == SUBREG)
44 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
47 return ALTIVEC_REGNO_P (REGNO (op));
50 ;; Return
1 if op is a VSX register.
51 (define_predicate "vsx_register_operand"
52 (match_operand
0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
60 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
63 return VSX_REGNO_P (REGNO (op));
66 ;; Return
1 if op is a vector register that operates on floating point vectors
67 ;; (either altivec or VSX).
68 (define_predicate "vfloat_operand"
69 (match_operand
0 "register_operand")
71 if (GET_CODE (op) == SUBREG)
77 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
80 return VFLOAT_REGNO_P (REGNO (op));
83 ;; Return
1 if op is a vector register that operates on integer vectors
84 ;; (only altivec, VSX doesn't support integer vectors)
85 (define_predicate "vint_operand"
86 (match_operand
0 "register_operand")
88 if (GET_CODE (op) == SUBREG)
94 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
97 return VINT_REGNO_P (REGNO (op));
100 ;; Return
1 if op is a vector register to do logical operations on (and, or,
102 (define_predicate "vlogical_operand"
103 (match_operand
0 "register_operand")
105 if (GET_CODE (op) == SUBREG)
106 op = SUBREG_REG (op);
111 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
114 return VLOGICAL_REGNO_P (REGNO (op));
117 ;; Return
1 if op is the carry register.
118 (define_predicate "ca_operand"
119 (match_operand
0 "register_operand")
121 if (GET_CODE (op) == SUBREG)
122 op = SUBREG_REG (op);
127 return CA_REGNO_P (REGNO (op));
130 ;; Return
1 if op is a signed
5-bit constant integer.
131 (define_predicate "s5bit_cint_operand"
132 (and (match_code "const_int")
133 (match_test "INTVAL (op) >= -
16 && INTVAL (op) <=
15")))
135 ;; Return
1 if op is a unsigned
3-bit constant integer.
136 (define_predicate "u3bit_cint_operand"
137 (and (match_code "const_int")
138 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
7")))
140 ;; Return
1 if op is a unsigned
5-bit constant integer.
141 (define_predicate "u5bit_cint_operand"
142 (and (match_code "const_int")
143 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
31")))
145 ;; Return
1 if op is a unsigned
6-bit constant integer.
146 (define_predicate "u6bit_cint_operand"
147 (and (match_code "const_int")
148 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
63")))
150 ;; Return
1 if op is an unsigned
7-bit constant integer.
151 (define_predicate "u7bit_cint_operand"
152 (and (match_code "const_int")
153 (match_test "IN_RANGE (INTVAL (op),
0,
127)")))
155 ;; Return
1 if op is a signed
8-bit constant integer.
156 ;; Integer multiplication complete more quickly
157 (define_predicate "s8bit_cint_operand"
158 (and (match_code "const_int")
159 (match_test "INTVAL (op) >= -
128 && INTVAL (op) <=
127")))
161 ;; Return
1 if op is a unsigned
10-bit constant integer.
162 (define_predicate "u10bit_cint_operand"
163 (and (match_code "const_int")
164 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1023")))
166 ;; Return
1 if op is a constant integer that can fit in a D field.
167 (define_predicate "short_cint_operand"
168 (and (match_code "const_int")
169 (match_test "satisfies_constraint_I (op)")))
171 ;; Return
1 if op is a constant integer that can fit in an unsigned D field.
172 (define_predicate "u_short_cint_operand"
173 (and (match_code "const_int")
174 (match_test "satisfies_constraint_K (op)")))
176 ;; Return
1 if op is a constant integer that is a signed
16-bit constant
177 ;; shifted left
16 bits
178 (define_predicate "upper16_cint_operand"
179 (and (match_code "const_int")
180 (match_test "satisfies_constraint_L (op)")))
182 ;; Return
1 if op is a constant integer that cannot fit in a signed D field.
183 (define_predicate "non_short_cint_operand"
184 (and (match_code "const_int")
185 (match_test "(unsigned HOST_WIDE_INT)
186 (INTVAL (op) +
0x8000) >=
0x10000")))
188 ;; Return
1 if op is a positive constant integer that is an exact power of
2.
189 (define_predicate "exact_log2_cint_operand"
190 (and (match_code "const_int")
191 (match_test "INTVAL (op) >
0 && exact_log2 (INTVAL (op)) >=
0")))
193 ;; Match op =
0 or op =
1.
194 (define_predicate "const_0_to_1_operand"
195 (and (match_code "const_int")
196 (match_test "IN_RANGE (INTVAL (op),
0,
1)")))
199 (define_predicate "const_0_to_3_operand"
200 (and (match_code "const_int")
201 (match_test "IN_RANGE (INTVAL (op),
0,
3)")))
203 ;; Match op =
2 or op =
3.
204 (define_predicate "const_2_to_3_operand"
205 (and (match_code "const_int")
206 (match_test "IN_RANGE (INTVAL (op),
2,
3)")))
209 (define_predicate "const_0_to_7_operand"
210 (and (match_code "const_int")
211 (match_test "IN_RANGE (INTVAL (op),
0,
7)")))
214 (define_predicate "const_0_to_12_operand"
215 (and (match_code "const_int")
216 (match_test "IN_RANGE (INTVAL (op),
0,
12)")))
219 (define_predicate "const_0_to_15_operand"
220 (and (match_code "const_int")
221 (match_test "IN_RANGE (INTVAL (op),
0,
15)")))
223 ;; Return
1 if op is a register that is not special.
224 (define_predicate "gpc_reg_operand"
225 (match_operand
0 "register_operand")
227 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
230 if (GET_CODE (op) == SUBREG)
231 op = SUBREG_REG (op);
236 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
239 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
242 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
245 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
248 ;; Return
1 if op is a general purpose register. Unlike gpc_reg_operand, don't
249 ;; allow floating point or vector registers.
250 (define_predicate "int_reg_operand"
251 (match_operand
0 "register_operand")
253 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
256 if (GET_CODE (op) == SUBREG)
257 op = SUBREG_REG (op);
262 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
265 return INT_REGNO_P (REGNO (op));
268 ;; Like int_reg_operand, but don't return true for pseudo registers
269 (define_predicate "int_reg_operand_not_pseudo"
270 (match_operand
0 "register_operand")
272 if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
275 if (GET_CODE (op) == SUBREG)
276 op = SUBREG_REG (op);
281 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
284 return INT_REGNO_P (REGNO (op));
287 ;; Like int_reg_operand, but only return true for base registers
288 (define_predicate "base_reg_operand"
289 (match_operand
0 "int_reg_operand")
291 if (GET_CODE (op) == SUBREG)
292 op = SUBREG_REG (op);
297 return (REGNO (op) != FIRST_GPR_REGNO);
301 ;; Return true if this is a traditional floating point register
302 (define_predicate "fpr_reg_operand"
303 (match_code "reg,subreg")
307 if (GET_CODE (op) == SUBREG)
308 op = SUBREG_REG (op);
314 if (r >= FIRST_PSEUDO_REGISTER)
317 return FP_REGNO_P (r);
320 ;; Return true if this is a register that can has D-form addressing (GPR and
321 ;; traditional FPR registers for scalars). ISA
3.0 (power9) adds D-form
322 ;; addressing for scalars in Altivec registers.
324 ;; If this is a pseudo only allow for GPR fusion in power8. If we have the
325 ;; power9 fusion allow the floating point types.
326 (define_predicate "toc_fusion_or_p9_reg_operand"
327 (match_code "reg,subreg")
330 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode
332 || (TARGET_POWERPC64 && (mode == DImode || mode == DFmode)));
333 bool fpr_p = (TARGET_P9_FUSION
334 && (mode == DFmode || mode == SFmode
335 || (TARGET_POWERPC64 && mode == DImode)));
336 bool vmx_p = (TARGET_P9_FUSION && TARGET_P9_VECTOR
337 && (mode == DFmode || mode == SFmode));
339 if (!TARGET_P8_FUSION)
342 if (GET_CODE (op) == SUBREG)
343 op = SUBREG_REG (op);
349 if (r >= FIRST_PSEUDO_REGISTER)
350 return (gpr_p || fpr_p || vmx_p);
358 if (ALTIVEC_REGNO_P (r))
364 ;; Return
1 if op is a HTM specific SPR register.
365 (define_predicate "htm_spr_reg_operand"
366 (match_operand
0 "register_operand")
371 if (GET_CODE (op) == SUBREG)
372 op = SUBREG_REG (op);
391 ;; Return
1 if op is a general purpose register that is an even register
392 ;; which suitable for a load/store quad operation
393 ;; Subregs are not allowed here because when they are combine can
394 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
395 ;; think the innermost reg needs reloading, in TImode instead of
396 ;; PTImode. So reload will choose a reg in TImode which has no
397 ;; requirement that the reg be even.
398 (define_predicate "quad_int_reg_operand"
403 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
407 if (r >= FIRST_PSEUDO_REGISTER)
410 return (INT_REGNO_P (r) && ((r &
1) ==
0));
413 ;; Return
1 if op is a register that is a condition register field.
414 (define_predicate "cc_reg_operand"
415 (match_operand
0 "register_operand")
417 if (GET_CODE (op) == SUBREG)
418 op = SUBREG_REG (op);
423 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
426 return CR_REGNO_P (REGNO (op));
429 ;; Return
1 if op is a register that is a condition register field not cr0.
430 (define_predicate "cc_reg_not_cr0_operand"
431 (match_operand
0 "register_operand")
433 if (GET_CODE (op) == SUBREG)
434 op = SUBREG_REG (op);
439 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
442 return CR_REGNO_NOT_CR0_P (REGNO (op));
445 ;; Return
1 if op is a register that is a condition register field and if generating microcode, not cr0.
446 (define_predicate "cc_reg_not_micro_cr0_operand"
447 (match_operand
0 "register_operand")
449 if (GET_CODE (op) == SUBREG)
450 op = SUBREG_REG (op);
455 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
458 if (rs6000_gen_cell_microcode)
459 return CR_REGNO_NOT_CR0_P (REGNO (op));
461 return CR_REGNO_P (REGNO (op));
464 ;; Return
1 if op is a constant integer valid for D field
465 ;; or non-special register register.
466 (define_predicate "reg_or_short_operand"
467 (if_then_else (match_code "const_int")
468 (match_operand
0 "short_cint_operand")
469 (match_operand
0 "gpc_reg_operand")))
471 ;; Return
1 if op is a constant integer valid for DS field
472 ;; or non-special register.
473 (define_predicate "reg_or_aligned_short_operand"
474 (if_then_else (match_code "const_int")
475 (and (match_operand
0 "short_cint_operand")
476 (match_test "!(INTVAL (op) &
3)"))
477 (match_operand
0 "gpc_reg_operand")))
479 ;; Return
1 if op is a constant integer whose high-order
16 bits are zero
480 ;; or non-special register.
481 (define_predicate "reg_or_u_short_operand"
482 (if_then_else (match_code "const_int")
483 (match_operand
0 "u_short_cint_operand")
484 (match_operand
0 "gpc_reg_operand")))
486 ;; Return
1 if op is any constant integer
487 ;; or non-special register.
488 (define_predicate "reg_or_cint_operand"
489 (ior (match_code "const_int")
490 (match_operand
0 "gpc_reg_operand")))
492 ;; Return
1 if op is a constant integer valid for addition with addis, addi.
493 (define_predicate "add_cint_operand"
494 (and (match_code "const_int")
495 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
496 + (mode == SImode ?
0x80000000 :
0x80008000))
497 < (unsigned HOST_WIDE_INT)
0x100000000ll")))
499 ;; Return
1 if op is a constant integer valid for addition
500 ;; or non-special register.
501 (define_predicate "reg_or_add_cint_operand"
502 (if_then_else (match_code "const_int")
503 (match_operand
0 "add_cint_operand")
504 (match_operand
0 "gpc_reg_operand")))
506 ;; Return
1 if op is a constant integer valid for subtraction
507 ;; or non-special register.
508 (define_predicate "reg_or_sub_cint_operand"
509 (if_then_else (match_code "const_int")
510 (match_test "(unsigned HOST_WIDE_INT)
511 (- UINTVAL (op) + (mode == SImode ?
0x80000000 :
0x80008000))
512 < (unsigned HOST_WIDE_INT)
0x100000000ll")
513 (match_operand
0 "gpc_reg_operand")))
515 ;; Return
1 if op is any
32-bit unsigned constant integer
516 ;; or non-special register.
517 (define_predicate "reg_or_logical_cint_operand"
518 (if_then_else (match_code "const_int")
519 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
521 || ((INTVAL (op) & GET_MODE_MASK (mode)
522 & (~ (unsigned HOST_WIDE_INT)
0xffffffff)) ==
0)")
523 (match_operand
0 "gpc_reg_operand")))
525 ;; Like reg_or_logical_cint_operand, but allow vsx registers
526 (define_predicate "vsx_reg_or_cint_operand"
527 (ior (match_operand
0 "vsx_register_operand")
528 (match_operand
0 "reg_or_logical_cint_operand")))
530 ;; Return
1 if operand is a CONST_DOUBLE that can be set in a register
531 ;; with no more than one instruction per word.
532 (define_predicate "easy_fp_constant"
533 (match_code "const_double")
535 if (GET_MODE (op) != mode
536 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
539 /* Consider all constants with -msoft-float to be easy. */
540 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
541 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
545 /*
0.0D is not all zero bits. */
546 if (DECIMAL_FLOAT_MODE_P (mode))
549 /* The constant
0.0 is easy under VSX. */
550 if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode))
553 /* If we are using V
.4 style PIC, consider all constants to be hard. */
554 if (flag_pic && DEFAULT_ABI == ABI_V4)
557 /* If we have real FPRs, consider floating point constants hard (other than
558 0.0 under VSX), so that the constant gets pushed to memory during the
559 early RTL phases. This has the advantage that double precision constants
560 that can be represented in single precision without a loss of precision
561 will use single precision loads. */
573 return (num_insns_constant (op, DImode) <=
2);
583 ;; Return
1 if the operand is a constant that can loaded with a XXSPLTIB
584 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
586 (define_predicate "xxspltib_constant_split"
587 (match_code "const_vector,vec_duplicate,const_int")
592 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
595 return num_insns >
1;
599 ;; Return
1 if the operand is constant that can loaded directly with a XXSPLTIB
602 (define_predicate "xxspltib_constant_nosplit"
603 (match_code "const_vector,vec_duplicate,const_int")
608 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
611 return num_insns ==
1;
614 ;; Return
1 if the operand is a CONST_VECTOR and can be loaded into a
615 ;; vector register without using memory.
616 (define_predicate "easy_vector_constant"
617 (match_code "const_vector")
619 /* As the paired vectors are actually FPRs it seems that there is
620 no easy way to load a CONST_VECTOR without using memory. */
621 if (TARGET_PAIRED_FLOAT)
624 /* Because IEEE
128-bit floating point is considered a vector type
625 in order to pass it in VSX registers, it might use this function
626 instead of easy_fp_constant. */
627 if (FLOAT128_VECTOR_P (mode))
628 return easy_fp_constant (op, mode);
630 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
635 if (zero_constant (op, mode) || all_ones_constant (op, mode))
639 && xxspltib_constant_p (op, mode, &num_insns, &value))
642 return easy_altivec_constant (op, mode);
645 if (SPE_VECTOR_MODE (mode))
648 if (zero_constant (op, mode))
650 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
653 /* Limit SPE vectors to
15 bits signed. These we can generate with:
658 I don't know how efficient it would be to allow bigger constants,
659 considering we'll have an extra 'ori' for every 'li'. I doubt
5
660 instructions is better than a
64-bit memory load, but I don't
661 have the e500 timing specs. */
662 if (mode == V2SImode)
664 cst = INTVAL (CONST_VECTOR_ELT (op,
0));
665 cst2 = INTVAL (CONST_VECTOR_ELT (op,
1));
666 return cst >= -
0x7fff && cst <=
0x7fff
667 && cst2 >= -
0x7fff && cst2 <=
0x7fff;
674 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
675 (define_predicate "easy_vector_constant_add_self"
676 (and (match_code "const_vector")
677 (and (match_test "TARGET_ALTIVEC")
678 (match_test "easy_altivec_constant (op, mode)")))
682 if (mode == V2DImode || mode == V2DFmode)
684 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
685 val = const_vector_elt_as_int (op, elt);
686 val = ((val &
0xff) ^
0x80) -
0x80;
687 return EASY_VECTOR_15_ADD_SELF (val);
690 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
691 (define_predicate "easy_vector_constant_msb"
692 (and (match_code "const_vector")
693 (and (match_test "TARGET_ALTIVEC")
694 (match_test "easy_altivec_constant (op, mode)")))
698 if (mode == V2DImode || mode == V2DFmode)
700 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
701 val = const_vector_elt_as_int (op, elt);
702 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
705 ;; Return true if this is an easy altivec constant that we form
707 (define_predicate "easy_vector_constant_vsldoi"
708 (and (match_code "const_vector")
709 (and (match_test "TARGET_ALTIVEC")
710 (and (match_test "easy_altivec_constant (op, mode)")
711 (match_test "vspltis_shifted (op) !=
0")))))
713 ;; Return
1 if operand is constant zero (scalars and vectors).
714 (define_predicate "zero_constant"
715 (and (match_code "const_int,const_double,const_wide_int,const_vector")
716 (match_test "op == CONST0_RTX (mode)")))
718 ;; Return
1 if operand is constant -
1 (scalars and vectors).
719 (define_predicate "all_ones_constant"
720 (and (match_code "const_int,const_double,const_wide_int,const_vector")
721 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
723 ;; Return
1 if operand is
0.0.
724 (define_predicate "zero_fp_constant"
725 (and (match_code "const_double")
726 (match_test "SCALAR_FLOAT_MODE_P (mode)
727 && op == CONST0_RTX (mode)")))
729 ;; Return
1 if the operand is in volatile memory. Note that during the
730 ;; RTL generation phase, memory_operand does not return TRUE for volatile
731 ;; memory references. So this function allows us to recognize volatile
732 ;; references where it's safe.
733 (define_predicate "volatile_mem_operand"
734 (and (and (match_code "mem")
735 (match_test "MEM_VOLATILE_P (op)"))
736 (if_then_else (match_test "reload_completed")
737 (match_operand
0 "memory_operand")
738 (if_then_else (match_test "reload_in_progress")
739 (match_test "strict_memory_address_p (mode, XEXP (op,
0))")
740 (match_test "memory_address_p (mode, XEXP (op,
0))")))))
742 ;; Return
1 if the operand is an offsettable memory operand.
743 (define_predicate "offsettable_mem_operand"
744 (and (match_operand
0 "memory_operand")
745 (match_test "offsettable_nonstrict_memref_p (op)")))
747 ;; Return
1 if the operand is suitable for load/store quad memory.
748 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
749 (define_predicate "quad_memory_operand"
752 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
755 if (GET_MODE_SIZE (mode) !=
16 || !MEM_P (op) || MEM_ALIGN (op) <
128)
758 return quad_address_p (XEXP (op,
0), mode, false);
761 ;; Return
1 if the operand is suitable for load/store to vector registers with
762 ;; d-form addressing (register+offset), which was added in ISA
3.0.
763 ;; Unlike quad_memory_operand, we do not have to check for alignment.
764 (define_predicate "vsx_quad_dform_memory_operand"
767 if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) !=
16)
770 return quad_address_p (XEXP (op,
0), mode, false);
773 ;; Return
1 if the operand is an indexed or indirect memory operand.
774 (define_predicate "indexed_or_indirect_operand"
778 if (VECTOR_MEM_ALTIVEC_P (mode)
779 && GET_CODE (op) == AND
780 && GET_CODE (XEXP (op,
1)) == CONST_INT
781 && INTVAL (XEXP (op,
1)) == -
16)
784 return indexed_or_indirect_address (op, mode);
787 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
788 ;; moves are supported.
789 (define_predicate "reg_or_indexed_operand"
790 (match_code "mem,reg,subreg")
793 return indexed_or_indirect_operand (op, mode);
794 else if (TARGET_DIRECT_MOVE)
795 return register_operand (op, mode);
800 ;; Return
1 if the operand is an indexed or indirect memory operand with an
801 ;; AND -
16 in it, used to recognize when we need to switch to Altivec loads
802 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
803 ;; while VSX uses the full address and traps)
804 (define_predicate "altivec_indexed_or_indirect_operand"
808 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
809 && GET_CODE (op) == AND
810 && GET_CODE (XEXP (op,
1)) == CONST_INT
811 && INTVAL (XEXP (op,
1)) == -
16)
812 return indexed_or_indirect_address (XEXP (op,
0), mode);
817 ;; Return
1 if the operand is an indexed or indirect address.
818 (define_special_predicate "indexed_or_indirect_address"
819 (and (match_test "REG_P (op)
820 || (GET_CODE (op) == PLUS
821 /* Omit testing REG_P (XEXP (op,
0)). */
822 && REG_P (XEXP (op,
1)))")
823 (match_operand
0 "address_operand")))
825 ;; Return
1 if the operand is an index-form address.
826 (define_special_predicate "indexed_address"
827 (match_test "(GET_CODE (op) == PLUS
828 && REG_P (XEXP (op,
0))
829 && REG_P (XEXP (op,
1)))"))
831 ;; Return
1 if the operand is a MEM with an update-form address. This may
832 ;; also include update-indexed form.
833 (define_special_predicate "update_address_mem"
834 (match_test "(MEM_P (op)
835 && (GET_CODE (XEXP (op,
0)) == PRE_INC
836 || GET_CODE (XEXP (op,
0)) == PRE_DEC
837 || GET_CODE (XEXP (op,
0)) == PRE_MODIFY))"))
839 ;; Return
1 if the operand is a MEM with an indexed-form address.
840 (define_special_predicate "indexed_address_mem"
841 (match_test "(MEM_P (op)
842 && (indexed_address (XEXP (op,
0), mode)
843 || (GET_CODE (XEXP (op,
0)) == PRE_MODIFY
844 && indexed_address (XEXP (XEXP (op,
0),
1), mode))))"))
846 ;; Return
1 if the operand is either a non-special register or can be used
847 ;; as the operand of a
`mode' add insn.
848 (define_predicate "add_operand"
849 (if_then_else (match_code "const_int")
850 (match_test "satisfies_constraint_I (op)
851 || satisfies_constraint_L (op)")
852 (match_operand 0 "gpc_reg_operand")))
854 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
855 (define_predicate "adde_operand"
856 (if_then_else (match_code "const_int")
857 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
858 (match_operand 0 "gpc_reg_operand")))
860 ;; Return 1 if OP is a constant but not a valid add_operand.
861 (define_predicate "non_add_cint_operand"
862 (and (match_code "const_int")
863 (match_test "!satisfies_constraint_I (op)
864 && !satisfies_constraint_L (op)")))
866 ;; Return 1 if the operand is a constant that can be used as the operand
868 (define_predicate "logical_const_operand"
869 (match_code "const_int")
873 opl = INTVAL (op) & GET_MODE_MASK (mode);
875 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
876 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
879 ;; Return 1 if the operand is a non-special register or a constant that
880 ;; can be used as the operand of an OR or XOR.
881 (define_predicate "logical_operand"
882 (ior (match_operand 0 "gpc_reg_operand")
883 (match_operand 0 "logical_const_operand")))
885 ;; Return 1 if op is a constant that is not a logical operand, but could
886 ;; be split into one.
887 (define_predicate "non_logical_cint_operand"
888 (and (match_code "const_int,const_wide_int")
889 (and (not (match_operand 0 "logical_operand"))
890 (match_operand 0 "reg_or_logical_cint_operand"))))
892 ;; Return 1 if the operand is either a non-special register or a
893 ;; constant that can be used as the operand of a logical AND.
894 (define_predicate "and_operand"
895 (ior (and (match_code "const_int")
896 (match_test "rs6000_is_valid_and_mask (op, mode)"))
897 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
898 (match_operand 0 "gpc_reg_operand")
899 (match_operand 0 "logical_operand"))))
901 ;; Return 1 if the operand is either a logical operand or a short cint operand.
902 (define_predicate "scc_eq_operand"
903 (ior (match_operand 0 "logical_operand")
904 (match_operand 0 "short_cint_operand")))
906 ;; Return 1 if the operand is a general non-special register or memory operand.
907 (define_predicate "reg_or_mem_operand"
908 (ior (match_operand 0 "memory_operand")
909 (ior (and (match_code "mem")
910 (match_test "macho_lo_sum_memory_operand (op, mode)"))
911 (ior (match_operand 0 "volatile_mem_operand")
912 (match_operand 0 "gpc_reg_operand")))))
914 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
915 (define_predicate "reg_or_none500mem_operand"
916 (if_then_else (match_code "mem")
917 (and (match_test "!TARGET_E500_DOUBLE")
918 (ior (match_operand 0 "memory_operand")
919 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
920 (match_operand 0 "volatile_mem_operand"))))
921 (match_operand 0 "gpc_reg_operand")))
923 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
924 (define_predicate "zero_reg_mem_operand"
925 (ior (and (match_test "TARGET_VSX")
926 (match_operand 0 "zero_fp_constant"))
927 (match_operand 0 "reg_or_mem_operand")))
929 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
930 ;; data types inside of a vector that scalar instructions operate on
931 (define_predicate "vsx_scalar_64bit"
932 (match_code "const_int")
934 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
937 ;; Return 1 if the operand is a general register or memory operand without
938 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
940 (define_predicate "lwa_operand"
941 (match_code "reg,subreg,mem")
943 rtx inner, addr, offset;
946 if (reload_completed && GET_CODE (inner) == SUBREG)
947 inner = SUBREG_REG (inner);
949 if (gpc_reg_operand (inner, mode))
951 if (!memory_operand (inner, mode))
953 if (!rs6000_gen_cell_microcode)
956 addr = XEXP (inner, 0);
957 if (GET_CODE (addr) == PRE_INC
958 || GET_CODE (addr) == PRE_DEC
959 || (GET_CODE (addr) == PRE_MODIFY
960 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
962 if (GET_CODE (addr) == LO_SUM
963 && GET_CODE (XEXP (addr, 0)) == REG
964 && GET_CODE (XEXP (addr, 1)) == CONST)
965 addr = XEXP (XEXP (addr, 1), 0);
966 if (GET_CODE (addr) != PLUS)
968 offset = XEXP (addr, 1);
969 if (GET_CODE (offset) != CONST_INT)
971 return INTVAL (offset) % 4 == 0;
974 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
975 (define_predicate "symbol_ref_operand"
976 (and (match_code "symbol_ref")
977 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
978 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
980 ;; Return 1 if op is an operand that can be loaded via the GOT.
981 ;; or non-special register register field no cr0
982 (define_predicate "got_operand"
983 (match_code "symbol_ref,const,label_ref"))
985 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
986 ;; excluding labels involving addition.
987 (define_predicate "got_no_const_operand"
988 (match_code "symbol_ref,label_ref"))
990 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
991 (define_predicate "rs6000_tls_symbol_ref"
992 (and (match_code "symbol_ref")
993 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
995 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
996 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
997 (define_predicate "call_operand"
998 (if_then_else (match_code "reg")
999 (match_test "REGNO (op) == LR_REGNO
1000 || REGNO (op) == CTR_REGNO
1001 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1002 (match_code "symbol_ref")))
1004 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1006 (define_predicate "current_file_function_operand"
1007 (and (match_code "symbol_ref")
1008 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1009 && (SYMBOL_REF_LOCAL_P (op)
1010 || op == XEXP (DECL_RTL (current_function_decl), 0))
1011 && !((DEFAULT_ABI == ABI_AIX
1012 || DEFAULT_ABI == ABI_ELFv2)
1013 && (SYMBOL_REF_EXTERNAL_P (op)
1014 || SYMBOL_REF_WEAK (op)))")))
1016 ;; Return 1 if this operand is a valid input for a move insn.
1017 (define_predicate "input_operand"
1018 (match_code "symbol_ref,const,reg,subreg,mem,
1019 const_double,const_wide_int,const_vector,const_int")
1021 /* Memory is always valid. */
1022 if (memory_operand (op, mode))
1025 /* For floating-point, easy constants are valid. */
1026 if (SCALAR_FLOAT_MODE_P (mode)
1027 && easy_fp_constant (op, mode))
1030 /* Allow any integer constant. */
1031 if (GET_MODE_CLASS (mode) == MODE_INT
1032 && CONST_SCALAR_INT_P (op))
1035 /* Allow easy vector constants. */
1036 if (GET_CODE (op) == CONST_VECTOR
1037 && easy_vector_constant (op, mode))
1040 /* Do not allow invalid E500 subregs. */
1041 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1042 && GET_CODE (op) == SUBREG
1043 && invalid_e500_subreg (op, mode))
1046 /* For floating-point or multi-word mode, the only remaining valid type
1048 if (SCALAR_FLOAT_MODE_P (mode)
1049 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1050 return register_operand (op, mode);
1052 /* We don't allow moving the carry bit around. */
1053 if (ca_operand (op, mode))
1056 /* The only cases left are integral modes one word or smaller (we
1057 do not get called for MODE_CC values). These can be in any
1059 if (register_operand (op, mode))
1062 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1064 if (DEFAULT_ABI == ABI_V4
1065 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1066 && small_data_operand (op, Pmode))
1072 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1073 (define_predicate "splat_input_operand"
1074 (match_code "reg,subreg,mem")
1080 else if (mode == DImode)
1082 else if (mode == SImode && TARGET_P9_VECTOR)
1084 else if (mode == SFmode && TARGET_P9_VECTOR)
1091 rtx addr = XEXP (op, 0);
1093 if (! volatile_ok && MEM_VOLATILE_P (op))
1096 if (reload_in_progress || lra_in_progress || reload_completed)
1097 return indexed_or_indirect_address (addr, vmode);
1099 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1101 return gpc_reg_operand (op, mode);
1104 ;; Return true if OP is a non-immediate operand and not an invalid
1105 ;; SUBREG operation on the e500.
1106 (define_predicate "rs6000_nonimmediate_operand"
1107 (match_code "reg,subreg,mem")
1109 if ((TARGET_E500_DOUBLE || TARGET_SPE)
1110 && GET_CODE (op) == SUBREG
1111 && invalid_e500_subreg (op, mode))
1114 return nonimmediate_operand (op, mode);
1117 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1118 (define_predicate "rotate_mask_operator"
1119 (match_code "rotate,ashift,lshiftrt"))
1121 ;; Return true if operand is boolean operator.
1122 (define_predicate "boolean_operator"
1123 (match_code "and,ior,xor"))
1125 ;; Return true if operand is OR-form of boolean operator.
1126 (define_predicate "boolean_or_operator"
1127 (match_code "ior,xor"))
1129 ;; Return true if operand is an equality operator.
1130 (define_special_predicate "equality_operator"
1131 (match_code "eq,ne"))
1133 ;; Return 1 if OP is a comparison operation that is valid for a branch
1134 ;; instruction. We check the opcode against the mode of the CC value.
1135 ;; validate_condition_mode is an assertion.
1136 (define_predicate "branch_comparison_operator"
1137 (and (match_operand 0 "comparison_operator")
1138 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1139 (match_test "validate_condition_mode (GET_CODE (op),
1140 GET_MODE (XEXP (op, 0))),
1143 ;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
1144 ;; If we're assuming that FP operations cannot generate user-visible traps,
1145 ;; then on e500 we can use the ordered-signaling instructions to implement
1146 ;; the unordered-quiet FP comparison predicates modulo a reversal.
1147 (define_predicate "rs6000_cbranch_operator"
1148 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
1149 (if_then_else (match_test "flag_trapping_math")
1150 (match_operand 0 "ordered_comparison_operator")
1151 (ior (match_operand 0 "ordered_comparison_operator")
1152 (match_code ("unlt,unle,ungt,unge"))))
1153 (match_operand 0 "comparison_operator")))
1155 ;; Return 1 if OP is an unsigned comparison operator.
1156 (define_predicate "unsigned_comparison_operator"
1157 (match_code "ltu,gtu,leu,geu"))
1159 ;; Return 1 if OP is a signed comparison operator.
1160 (define_predicate "signed_comparison_operator"
1161 (match_code "lt,gt,le,ge"))
1163 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1164 ;; it must be a positive comparison.
1165 (define_predicate "scc_comparison_operator"
1166 (and (match_operand 0 "branch_comparison_operator")
1167 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1169 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1171 (define_predicate "scc_rev_comparison_operator"
1172 (and (match_operand 0 "branch_comparison_operator")
1173 (match_code "ne,le,ge,leu,geu,ordered")))
1175 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1176 ;; comparisons that generate a -1/0 mask.
1177 (define_predicate "fpmask_comparison_operator"
1178 (match_code "eq,gt,ge"))
1180 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1181 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1182 ;; fpmask_comparison_operator).
1183 (define_predicate "invert_fpmask_comparison_operator"
1184 (match_code "ne,unlt,unle"))
1186 ;; Return 1 if OP is a comparison operation that is valid for a branch
1187 ;; insn, which is true if the corresponding bit in the CC register is set.
1188 (define_predicate "branch_positive_comparison_operator"
1189 (and (match_operand 0 "branch_comparison_operator")
1190 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1192 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1193 (define_predicate "load_multiple_operation"
1194 (match_code "parallel")
1196 int count = XVECLEN (op, 0);
1197 unsigned int dest_regno;
1201 /* Perform a quick check so we don't blow up below. */
1203 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1204 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1205 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1208 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1209 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1211 for (i = 1; i < count; i++)
1213 rtx elt = XVECEXP (op, 0, i);
1215 if (GET_CODE (elt) != SET
1216 || GET_CODE (SET_DEST (elt)) != REG
1217 || GET_MODE (SET_DEST (elt)) != SImode
1218 || REGNO (SET_DEST (elt)) != dest_regno + i
1219 || GET_CODE (SET_SRC (elt)) != MEM
1220 || GET_MODE (SET_SRC (elt)) != SImode
1221 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1222 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1223 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1224 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1231 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1232 ;; The second vector element is a CLOBBER.
1233 (define_predicate "store_multiple_operation"
1234 (match_code "parallel")
1236 int count = XVECLEN (op, 0) - 1;
1237 unsigned int src_regno;
1241 /* Perform a quick check so we don't blow up below. */
1243 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1244 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1245 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1248 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1249 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1251 for (i = 1; i < count; i++)
1253 rtx elt = XVECEXP (op, 0, i + 1);
1255 if (GET_CODE (elt) != SET
1256 || GET_CODE (SET_SRC (elt)) != REG
1257 || GET_MODE (SET_SRC (elt)) != SImode
1258 || REGNO (SET_SRC (elt)) != src_regno + i
1259 || GET_CODE (SET_DEST (elt)) != MEM
1260 || GET_MODE (SET_DEST (elt)) != SImode
1261 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1262 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1263 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1264 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1271 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1273 (define_predicate "save_world_operation"
1274 (match_code "parallel")
1279 int count = XVECLEN (op, 0);
1285 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1286 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1289 for (i=1; i <= 18; i++)
1291 elt = XVECEXP (op, 0, index++);
1292 if (GET_CODE (elt) != SET
1293 || GET_CODE (SET_DEST (elt)) != MEM
1294 || ! memory_operand (SET_DEST (elt), DFmode)
1295 || GET_CODE (SET_SRC (elt)) != REG
1296 || GET_MODE (SET_SRC (elt)) != DFmode)
1300 for (i=1; i <= 12; i++)
1302 elt = XVECEXP (op, 0, index++);
1303 if (GET_CODE (elt) != SET
1304 || GET_CODE (SET_DEST (elt)) != MEM
1305 || GET_CODE (SET_SRC (elt)) != REG
1306 || GET_MODE (SET_SRC (elt)) != V4SImode)
1310 for (i=1; i <= 19; i++)
1312 elt = XVECEXP (op, 0, index++);
1313 if (GET_CODE (elt) != SET
1314 || GET_CODE (SET_DEST (elt)) != MEM
1315 || ! memory_operand (SET_DEST (elt), Pmode)
1316 || GET_CODE (SET_SRC (elt)) != REG
1317 || GET_MODE (SET_SRC (elt)) != Pmode)
1321 elt = XVECEXP (op, 0, index++);
1322 if (GET_CODE (elt) != SET
1323 || GET_CODE (SET_DEST (elt)) != MEM
1324 || ! memory_operand (SET_DEST (elt), Pmode)
1325 || GET_CODE (SET_SRC (elt)) != REG
1326 || REGNO (SET_SRC (elt)) != CR2_REGNO
1327 || GET_MODE (SET_SRC (elt)) != Pmode)
1330 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1331 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1336 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1338 (define_predicate "restore_world_operation"
1339 (match_code "parallel")
1344 int count = XVECLEN (op, 0);
1350 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1351 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1352 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1353 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1356 elt = XVECEXP (op, 0, index++);
1357 if (GET_CODE (elt) != SET
1358 || GET_CODE (SET_SRC (elt)) != MEM
1359 || ! memory_operand (SET_SRC (elt), Pmode)
1360 || GET_CODE (SET_DEST (elt)) != REG
1361 || REGNO (SET_DEST (elt)) != CR2_REGNO
1362 || GET_MODE (SET_DEST (elt)) != Pmode)
1365 for (i=1; i <= 19; i++)
1367 elt = XVECEXP (op, 0, index++);
1368 if (GET_CODE (elt) != SET
1369 || GET_CODE (SET_SRC (elt)) != MEM
1370 || ! memory_operand (SET_SRC (elt), Pmode)
1371 || GET_CODE (SET_DEST (elt)) != REG
1372 || GET_MODE (SET_DEST (elt)) != Pmode)
1376 for (i=1; i <= 12; i++)
1378 elt = XVECEXP (op, 0, index++);
1379 if (GET_CODE (elt) != SET
1380 || GET_CODE (SET_SRC (elt)) != MEM
1381 || GET_CODE (SET_DEST (elt)) != REG
1382 || GET_MODE (SET_DEST (elt)) != V4SImode)
1386 for (i=1; i <= 18; i++)
1388 elt = XVECEXP (op, 0, index++);
1389 if (GET_CODE (elt) != SET
1390 || GET_CODE (SET_SRC (elt)) != MEM
1391 || ! memory_operand (SET_SRC (elt), DFmode)
1392 || GET_CODE (SET_DEST (elt)) != REG
1393 || GET_MODE (SET_DEST (elt)) != DFmode)
1397 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1398 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1399 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1400 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1401 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1406 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1407 (define_predicate "vrsave_operation"
1408 (match_code "parallel")
1410 int count = XVECLEN (op, 0);
1411 unsigned int dest_regno, src_regno;
1415 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1416 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1417 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1418 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1421 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1422 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1424 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1427 for (i = 1; i < count; i++)
1429 rtx elt = XVECEXP (op, 0, i);
1431 if (GET_CODE (elt) != CLOBBER
1432 && GET_CODE (elt) != SET)
1439 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1440 (define_predicate "mfcr_operation"
1441 (match_code "parallel")
1443 int count = XVECLEN (op, 0);
1446 /* Perform a quick check so we don't blow up below. */
1448 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1449 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1450 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1453 for (i = 0; i < count; i++)
1455 rtx exp = XVECEXP (op, 0, i);
1460 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1462 if (GET_CODE (src_reg) != REG
1463 || GET_MODE (src_reg) != CCmode
1464 || ! CR_REGNO_P (REGNO (src_reg)))
1467 if (GET_CODE (exp) != SET
1468 || GET_CODE (SET_DEST (exp)) != REG
1469 || GET_MODE (SET_DEST (exp)) != SImode
1470 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1472 unspec = SET_SRC (exp);
1473 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1475 if (GET_CODE (unspec) != UNSPEC
1476 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1477 || XVECLEN (unspec, 0) != 2
1478 || XVECEXP (unspec, 0, 0) != src_reg
1479 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1480 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1486 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1487 (define_predicate "mtcrf_operation"
1488 (match_code "parallel")
1490 int count = XVECLEN (op, 0);
1494 /* Perform a quick check so we don't blow up below. */
1496 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1497 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1498 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1500 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1502 if (GET_CODE (src_reg) != REG
1503 || GET_MODE (src_reg) != SImode
1504 || ! INT_REGNO_P (REGNO (src_reg)))
1507 for (i = 0; i < count; i++)
1509 rtx exp = XVECEXP (op, 0, i);
1513 if (GET_CODE (exp) != SET
1514 || GET_CODE (SET_DEST (exp)) != REG
1515 || GET_MODE (SET_DEST (exp)) != CCmode
1516 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1518 unspec = SET_SRC (exp);
1519 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1521 if (GET_CODE (unspec) != UNSPEC
1522 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1523 || XVECLEN (unspec, 0) != 2
1524 || XVECEXP (unspec, 0, 0) != src_reg
1525 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1526 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1532 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1533 (define_predicate "crsave_operation"
1534 (match_code "parallel")
1536 int count = XVECLEN (op, 0);
1539 for (i = 1; i < count; i++)
1541 rtx exp = XVECEXP (op, 0, i);
1543 if (GET_CODE (exp) != USE
1544 || GET_CODE (XEXP (exp, 0)) != REG
1545 || GET_MODE (XEXP (exp, 0)) != CCmode
1546 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1552 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1553 (define_predicate "lmw_operation"
1554 (match_code "parallel")
1556 int count = XVECLEN (op, 0);
1557 unsigned int dest_regno;
1559 unsigned int base_regno;
1560 HOST_WIDE_INT offset;
1563 /* Perform a quick check so we don't blow up below. */
1565 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1566 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1567 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1570 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1571 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1574 || count != 32 - (int) dest_regno)
1577 if (legitimate_indirect_address_p (src_addr, 0))
1580 base_regno = REGNO (src_addr);
1581 if (base_regno == 0)
1584 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1586 offset = INTVAL (XEXP (src_addr, 1));
1587 base_regno = REGNO (XEXP (src_addr, 0));
1592 for (i = 0; i < count; i++)
1594 rtx elt = XVECEXP (op, 0, i);
1597 HOST_WIDE_INT newoffset;
1599 if (GET_CODE (elt) != SET
1600 || GET_CODE (SET_DEST (elt)) != REG
1601 || GET_MODE (SET_DEST (elt)) != SImode
1602 || REGNO (SET_DEST (elt)) != dest_regno + i
1603 || GET_CODE (SET_SRC (elt)) != MEM
1604 || GET_MODE (SET_SRC (elt)) != SImode)
1606 newaddr = XEXP (SET_SRC (elt), 0);
1607 if (legitimate_indirect_address_p (newaddr, 0))
1612 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1614 addr_reg = XEXP (newaddr, 0);
1615 newoffset = INTVAL (XEXP (newaddr, 1));
1619 if (REGNO (addr_reg) != base_regno
1620 || newoffset != offset + 4 * i)
1627 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1628 (define_predicate "stmw_operation"
1629 (match_code "parallel")
1631 int count = XVECLEN (op, 0);
1632 unsigned int src_regno;
1634 unsigned int base_regno;
1635 HOST_WIDE_INT offset;
1638 /* Perform a quick check so we don't blow up below. */
1640 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1641 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1642 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1645 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1646 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1649 || count != 32 - (int) src_regno)
1652 if (legitimate_indirect_address_p (dest_addr, 0))
1655 base_regno = REGNO (dest_addr);
1656 if (base_regno == 0)
1659 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1661 offset = INTVAL (XEXP (dest_addr, 1));
1662 base_regno = REGNO (XEXP (dest_addr, 0));
1667 for (i = 0; i < count; i++)
1669 rtx elt = XVECEXP (op, 0, i);
1672 HOST_WIDE_INT newoffset;
1674 if (GET_CODE (elt) != SET
1675 || GET_CODE (SET_SRC (elt)) != REG
1676 || GET_MODE (SET_SRC (elt)) != SImode
1677 || REGNO (SET_SRC (elt)) != src_regno + i
1678 || GET_CODE (SET_DEST (elt)) != MEM
1679 || GET_MODE (SET_DEST (elt)) != SImode)
1681 newaddr = XEXP (SET_DEST (elt), 0);
1682 if (legitimate_indirect_address_p (newaddr, 0))
1687 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1689 addr_reg = XEXP (newaddr, 0);
1690 newoffset = INTVAL (XEXP (newaddr, 1));
1694 if (REGNO (addr_reg) != base_regno
1695 || newoffset != offset + 4 * i)
1702 ;; Return 1 if OP is a stack tie operand.
1703 (define_predicate "tie_operand"
1704 (match_code "parallel")
1706 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1707 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1708 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1709 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1712 ;; Match a small code model toc reference (or medium and large
1713 ;; model toc references before reload).
1714 (define_predicate "small_toc_ref"
1715 (match_code "unspec,plus")
1717 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1720 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1723 ;; Match the TOC memory operand that can be fused with an addis instruction.
1724 ;; This is used in matching a potential fused address before register
1726 (define_predicate "toc_fusion_mem_raw"
1729 if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ())
1732 return small_toc_ref (XEXP (op, 0), Pmode);
1735 ;; Match the memory operand that has been fused with an addis instruction and
1736 ;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper.
1737 (define_predicate "toc_fusion_mem_wrapped"
1742 if (!TARGET_TOC_FUSION_INT)
1748 addr = XEXP (op, 0);
1749 return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS);
1752 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1753 ;; GPR registers on power8.
1754 (define_predicate "fusion_gpr_addis"
1755 (match_code "const_int,high,plus")
1757 HOST_WIDE_INT value;
1760 if (GET_CODE (op) == HIGH)
1763 if (CONST_INT_P (op))
1766 else if (GET_CODE (op) == PLUS
1767 && base_reg_operand (XEXP (op, 0), Pmode)
1768 && CONST_INT_P (XEXP (op, 1)))
1769 int_const = XEXP (op, 1);
1774 value = INTVAL (int_const);
1775 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1778 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1781 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1782 value are all 1's or 0's. Ignore this restriction if we are testing
1784 if (TARGET_P9_FUSION)
1787 return (IN_RANGE (value >> 16, -32, 31));
1790 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1791 ;; and loads to GPR registers on power8.
1792 (define_predicate "fusion_gpr_mem_load"
1793 (match_code "mem,sign_extend,zero_extend")
1795 rtx addr, base, offset;
1797 /* Handle sign/zero extend. */
1798 if (GET_CODE (op) == ZERO_EXTEND
1799 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1802 mode = GET_MODE (op);
1816 if (!TARGET_POWERPC64)
1824 addr = XEXP (op, 0);
1825 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1828 base = XEXP (addr, 0);
1829 if (!base_reg_operand (base, GET_MODE (base)))
1832 offset = XEXP (addr, 1);
1834 if (GET_CODE (addr) == PLUS)
1835 return satisfies_constraint_I (offset);
1837 else if (GET_CODE (addr) == LO_SUM)
1839 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1840 return small_toc_ref (offset, GET_MODE (offset));
1842 else if (TARGET_ELF && !TARGET_POWERPC64)
1843 return CONSTANT_P (offset);
1849 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1850 ;; memory field with both the addis and the memory offset. Sign extension
1851 ;; is not handled here, since lha and lwa are not fused.
1852 ;; With P9 fusion, also match a fpr/vector load and float_extend
1853 (define_predicate "fusion_addis_mem_combo_load"
1854 (match_code "mem,zero_extend,float_extend")
1856 rtx addr, base, offset;
1858 /* Handle zero/float extend. */
1859 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1862 mode = GET_MODE (op);
1875 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1876 separate instructions. */
1878 if (!TARGET_POWERPC64)
1882 /* ISA 2.08/power8 only had fusion of GPR loads. */
1884 if (!TARGET_P9_FUSION)
1888 /* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit
1889 DFmode in 32-bit if -msoft-float since it splits into two separate
1892 if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION)
1900 addr = XEXP (op, 0);
1901 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1904 base = XEXP (addr, 0);
1905 if (!fusion_gpr_addis (base, GET_MODE (base)))
1908 offset = XEXP (addr, 1);
1909 if (GET_CODE (addr) == PLUS)
1910 return satisfies_constraint_I (offset);
1912 else if (GET_CODE (addr) == LO_SUM)
1914 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1915 return small_toc_ref (offset, GET_MODE (offset));
1917 else if (TARGET_ELF && !TARGET_POWERPC64)
1918 return CONSTANT_P (offset);
1924 ;; Like fusion_addis_mem_combo_load, but for stores
1925 (define_predicate "fusion_addis_mem_combo_store"
1928 rtx addr, base, offset;
1930 if (!MEM_P (op) || !TARGET_P9_FUSION)
1941 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1942 separate instructions. */
1944 if (!TARGET_POWERPC64)
1948 /* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits
1949 into two separate instructions. Do allow fusion if we have hardware
1952 if (!TARGET_POWERPC64 && !TARGET_DF_FPR)
1960 addr = XEXP (op, 0);
1961 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1964 base = XEXP (addr, 0);
1965 if (!fusion_gpr_addis (base, GET_MODE (base)))
1968 offset = XEXP (addr, 1);
1969 if (GET_CODE (addr) == PLUS)
1970 return satisfies_constraint_I (offset);
1972 else if (GET_CODE (addr) == LO_SUM)
1974 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1975 return small_toc_ref (offset, GET_MODE (offset));
1977 else if (TARGET_ELF && !TARGET_POWERPC64)
1978 return CONSTANT_P (offset);
1984 ;; Return true if the operand is a float_extend or zero extend of an
1985 ;; offsettable memory operand suitable for use in fusion
1986 (define_predicate "fusion_offsettable_mem_operand"
1987 (match_code "mem,zero_extend,float_extend")
1989 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1992 mode = GET_MODE (op);
1995 if (!memory_operand (op, mode))
1998 return offsettable_nonstrict_memref_p (op);