1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C)
2005-
2021 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version
3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return
1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return
1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return
1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return
1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have
64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return
1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand
0 "register_operand")
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (!HARD_REGISTER_P (op))
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return
1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand
0 "register_operand")
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (!HARD_REGISTER_P (op))
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand
0 "register_operand")
111 op = SUBREG_REG (op);
116 if (!HARD_REGISTER_P (op))
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return
1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand
0 "register_operand")
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (!HARD_REGISTER_P (op))
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return
1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand
0 "register_operand")
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (!HARD_REGISTER_P (op))
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return
1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand
0 "register_operand")
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (!HARD_REGISTER_P (op))
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return
1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand
0 "register_operand")
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return
1 if operand is constant zero (scalars and vectors).
203 (define_predicate "zero_constant"
204 (and (match_code "const_int,const_double,const_wide_int,const_vector")
205 (match_test "op == CONST0_RTX (mode)")))
207 ;; Return
1 if operand is constant -
1 (scalars and vectors).
208 (define_predicate "all_ones_constant"
209 (and (match_code "const_int,const_double,const_wide_int,const_vector")
210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
212 ;; Return
1 if op is a signed
5-bit constant integer.
213 (define_predicate "s5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >= -
16 && INTVAL (op) <=
15")))
217 ;; Return
1 if op is an unsigned
1-bit constant integer.
218 (define_predicate "u1bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1")))
222 ;; Return
1 if op is a unsigned
3-bit constant integer.
223 (define_predicate "u3bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
7")))
227 ;; Return
1 if op is a unsigned
5-bit constant integer.
228 (define_predicate "u5bit_cint_operand"
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
31")))
232 ;; Return
1 if op is a unsigned
6-bit constant integer.
233 (define_predicate "u6bit_cint_operand"
234 (and (match_code "const_int")
235 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
63")))
237 ;; Return
1 if op is an unsigned
7-bit constant integer.
238 (define_predicate "u7bit_cint_operand"
239 (and (match_code "const_int")
240 (match_test "IN_RANGE (INTVAL (op),
0,
127)")))
242 ;; Return
1 if op is a unsigned
8-bit constant integer.
243 (define_predicate "u8bit_cint_operand"
244 (and (match_code "const_int")
245 (match_test "IN_RANGE (INTVAL (op),
0,
255)")))
247 ;; Return
1 if op is a signed
8-bit constant integer.
248 ;; Integer multiplication complete more quickly
249 (define_predicate "s8bit_cint_operand"
250 (and (match_code "const_int")
251 (match_test "INTVAL (op) >= -
128 && INTVAL (op) <=
127")))
253 ;; Return
1 if op is a unsigned
10-bit constant integer.
254 (define_predicate "u10bit_cint_operand"
255 (and (match_code "const_int")
256 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1023")))
258 ;; Return
1 if op is a constant integer that can fit in a D field.
259 (define_predicate "short_cint_operand"
260 (and (match_code "const_int")
261 (match_test "satisfies_constraint_I (op)")))
263 ;; Return
1 if op is a constant integer that can fit in an unsigned D field.
264 (define_predicate "u_short_cint_operand"
265 (and (match_code "const_int")
266 (match_test "satisfies_constraint_K (op)")))
268 ;; Return
1 if op is a constant integer that is a signed
16-bit constant
269 ;; shifted left
16 bits
270 (define_predicate "upper16_cint_operand"
271 (and (match_code "const_int")
272 (match_test "satisfies_constraint_L (op)")))
274 ;; Return
1 if op is a constant integer that cannot fit in a signed D field.
275 (define_predicate "non_short_cint_operand"
276 (and (match_code "const_int")
277 (match_test "(unsigned HOST_WIDE_INT)
278 (INTVAL (op) +
0x8000) >=
0x10000")))
280 ;; Return
1 if op is a
32-bit constant signed integer
281 (define_predicate "s32bit_cint_operand"
282 (and (match_code "const_int")
283 (match_test "(
0x80000000 + UINTVAL (op)) >>
32 ==
0")))
285 ;; Return
1 if op is a constant
32-bit unsigned
286 (define_predicate "c32bit_cint_operand"
287 (and (match_code "const_int")
288 (match_test "((UINTVAL (op) >>
32) ==
0)")))
290 ;; Return
1 if op is a positive constant integer that is an exact power of
2.
291 (define_predicate "exact_log2_cint_operand"
292 (and (match_code "const_int")
293 (match_test "INTVAL (op) >
0 && exact_log2 (INTVAL (op)) >=
0")))
295 ;; Match op =
0 or op =
1.
296 (define_predicate "const_0_to_1_operand"
297 (and (match_code "const_int")
298 (match_test "IN_RANGE (INTVAL (op),
0,
1)")))
300 ;; Match op = -
1, op =
0, or op =
1.
301 (define_predicate "const_m1_to_1_operand"
302 (and (match_code "const_int")
303 (match_test "IN_RANGE (INTVAL (op), -
1,
1)")))
306 (define_predicate "const_0_to_3_operand"
307 (and (match_code "const_int")
308 (match_test "IN_RANGE (INTVAL (op),
0,
3)")))
310 ;; Match op =
2 or op =
3.
311 (define_predicate "const_2_to_3_operand"
312 (and (match_code "const_int")
313 (match_test "IN_RANGE (INTVAL (op),
2,
3)")))
316 (define_predicate "const_0_to_7_operand"
317 (and (match_code "const_int")
318 (match_test "IN_RANGE (INTVAL (op),
0,
7)")))
321 (define_predicate "const_0_to_12_operand"
322 (and (match_code "const_int")
323 (match_test "IN_RANGE (INTVAL (op),
0,
12)")))
326 (define_predicate "const_0_to_15_operand"
327 (and (match_code "const_int")
328 (match_test "IN_RANGE (INTVAL (op),
0,
15)")))
330 ;; Return
1 if op is a
34-bit constant integer.
331 (define_predicate "cint34_operand"
332 (match_code "const_int")
334 if (!TARGET_PREFIXED)
337 return SIGNED_INTEGER_34BIT_P (INTVAL (op));
340 ;; Return
1 if op is a register that is not special.
341 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
342 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
343 ;; the fact that SFmode is represented as DFmode in the VSX registers.
344 (define_predicate "gpc_reg_operand"
345 (match_operand
0 "register_operand")
349 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
352 op = SUBREG_REG (op);
358 if (!HARD_REGISTER_P (op))
361 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
364 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
367 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
370 ;; Return
1 if op is a general purpose register. Unlike gpc_reg_operand, don't
371 ;; allow floating point or vector registers. Since vector registers are not
372 ;; allowed, we don't have to reject SFmode/SImode subregs.
373 (define_predicate "int_reg_operand"
374 (match_operand
0 "register_operand")
378 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
381 op = SUBREG_REG (op);
387 if (!HARD_REGISTER_P (op))
390 return INT_REGNO_P (REGNO (op));
393 ;; Like int_reg_operand, but don't return true for pseudo registers
394 ;; We don't have to check for SF SUBREGS because pseudo registers
395 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
396 (define_predicate "int_reg_operand_not_pseudo"
397 (match_operand
0 "register_operand")
400 op = SUBREG_REG (op);
405 if (!HARD_REGISTER_P (op))
408 return INT_REGNO_P (REGNO (op));
411 ;; Like int_reg_operand, but only return true for base registers
412 (define_predicate "base_reg_operand"
413 (match_operand
0 "int_reg_operand")
416 op = SUBREG_REG (op);
421 return (REGNO (op) != FIRST_GPR_REGNO);
425 ;; Return true if this is a traditional floating point register
426 (define_predicate "fpr_reg_operand"
427 (match_code "reg,subreg")
432 op = SUBREG_REG (op);
438 if (!HARD_REGISTER_NUM_P (r))
441 return FP_REGNO_P (r);
444 ;; Return
1 if op is a general purpose register that is an even register
445 ;; which suitable for a load/store quad operation
446 ;; Subregs are not allowed here because when they are combine can
447 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
448 ;; think the innermost reg needs reloading, in TImode instead of
449 ;; PTImode. So reload will choose a reg in TImode which has no
450 ;; requirement that the reg be even.
451 (define_predicate "quad_int_reg_operand"
456 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
460 if (!HARD_REGISTER_NUM_P (r))
463 return (INT_REGNO_P (r) && ((r &
1) ==
0));
466 ;; Return
1 if op is a register that is a condition register field.
467 (define_predicate "cc_reg_operand"
468 (match_operand
0 "register_operand")
471 op = SUBREG_REG (op);
476 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
479 return CR_REGNO_P (REGNO (op));
482 ;; Return
1 if op is a register that is a condition register field not cr0.
483 (define_predicate "cc_reg_not_cr0_operand"
484 (match_operand
0 "register_operand")
487 op = SUBREG_REG (op);
492 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
495 return CR_REGNO_NOT_CR0_P (REGNO (op));
498 ;; Return
1 if op is a constant integer valid for D field
499 ;; or non-special register register.
500 (define_predicate "reg_or_short_operand"
501 (if_then_else (match_code "const_int")
502 (match_operand
0 "short_cint_operand")
503 (match_operand
0 "gpc_reg_operand")))
505 ;; Return
1 if op is a constant integer valid for DS field
506 ;; or non-special register.
507 (define_predicate "reg_or_aligned_short_operand"
508 (if_then_else (match_code "const_int")
509 (and (match_operand
0 "short_cint_operand")
510 (match_test "!(INTVAL (op) &
3)"))
511 (match_operand
0 "gpc_reg_operand")))
513 ;; Return
1 if op is a constant integer whose high-order
16 bits are zero
514 ;; or non-special register.
515 (define_predicate "reg_or_u_short_operand"
516 (if_then_else (match_code "const_int")
517 (match_operand
0 "u_short_cint_operand")
518 (match_operand
0 "gpc_reg_operand")))
520 ;; Return
1 if op is any constant integer or a non-special register.
521 (define_predicate "reg_or_cint_operand"
522 (ior (match_code "const_int")
523 (match_operand
0 "gpc_reg_operand")))
525 ;; Return
1 if op is constant zero or a non-special register.
526 (define_predicate "reg_or_zero_operand"
527 (ior (match_operand
0 "zero_constant")
528 (match_operand
0 "gpc_reg_operand")))
530 ;; Return
1 if op is a constant integer valid for addition with addis, addi.
531 (define_predicate "add_cint_operand"
532 (and (match_code "const_int")
533 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
534 + (mode == SImode ?
0x80000000 :
0x80008000))
535 < (unsigned HOST_WIDE_INT)
0x100000000ll")))
537 ;; Return
1 if op is a constant integer valid for addition
538 ;; or non-special register.
539 (define_predicate "reg_or_add_cint_operand"
540 (if_then_else (match_code "const_int")
541 (match_operand
0 "add_cint_operand")
542 (match_operand
0 "gpc_reg_operand")))
544 ;; Return
1 if op is a constant integer valid for subtraction
545 ;; or non-special register.
546 (define_predicate "reg_or_sub_cint_operand"
547 (if_then_else (match_code "const_int")
548 (match_test "(unsigned HOST_WIDE_INT)
549 (- UINTVAL (op) + (mode == SImode ?
0x80000000 :
0x80008000))
550 < (unsigned HOST_WIDE_INT)
0x100000000ll")
551 (match_operand
0 "gpc_reg_operand")))
553 ;; Return
1 if op is any
32-bit unsigned constant integer
554 ;; or non-special register.
555 (define_predicate "reg_or_logical_cint_operand"
556 (if_then_else (match_code "const_int")
557 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
559 || ((INTVAL (op) & GET_MODE_MASK (mode)
560 & (~ (unsigned HOST_WIDE_INT)
0xffffffff)) ==
0)")
561 (match_operand
0 "gpc_reg_operand")))
563 ;; Like reg_or_logical_cint_operand, but allow vsx registers
564 (define_predicate "vsx_reg_or_cint_operand"
565 (ior (match_operand
0 "vsx_register_operand")
566 (match_operand
0 "reg_or_logical_cint_operand")))
568 ;; Return
1 if operand is a CONST_DOUBLE that can be set in a register
569 ;; with no more than one instruction per word.
570 (define_predicate "easy_fp_constant"
571 (match_code "const_double")
573 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode));
575 /* Consider all constants with -msoft-float to be easy when regs are
576 32-bit and thus can be loaded with a maximum of
2 insns. For
577 64-bit avoid long dependent insn sequences. */
578 if (TARGET_SOFT_FLOAT)
580 if (!TARGET_POWERPC64)
583 int size = GET_MODE_SIZE (mode);
587 int load_from_mem_insns =
2;
589 load_from_mem_insns++;
590 if (TARGET_CMODEL != CMODEL_SMALL)
591 load_from_mem_insns++;
592 if (num_insns_constant (op, mode) <= load_from_mem_insns)
596 /*
0.0D is not all zero bits. */
597 if (DECIMAL_FLOAT_MODE_P (mode))
600 /* The constant
0.0 is easy under VSX. */
601 if (TARGET_VSX && op == CONST0_RTX (mode))
604 /* Otherwise consider floating point constants hard, so that the
605 constant gets pushed to memory during the early RTL phases. This
606 has the advantage that double precision constants that can be
607 represented in single precision without a loss of precision will
608 use single precision loads. */
612 ;; Return
1 if the operand is a constant that can loaded with a XXSPLTIB
613 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
615 (define_predicate "xxspltib_constant_split"
616 (match_code "const_vector,vec_duplicate,const_int")
621 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
624 return num_insns >
1;
628 ;; Return
1 if the operand is constant that can loaded directly with a XXSPLTIB
631 (define_predicate "xxspltib_constant_nosplit"
632 (match_code "const_vector,vec_duplicate,const_int")
637 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
640 return num_insns ==
1;
643 ;; Return
1 if the operand is a CONST_VECTOR and can be loaded into a
644 ;; vector register without using memory.
645 (define_predicate "easy_vector_constant"
646 (match_code "const_vector")
648 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
653 if (zero_constant (op, mode) || all_ones_constant (op, mode))
657 && xxspltib_constant_p (op, mode, &num_insns, &value))
660 return easy_altivec_constant (op, mode);
666 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
667 (define_predicate "easy_vector_constant_add_self"
668 (and (match_code "const_vector")
669 (and (match_test "TARGET_ALTIVEC")
670 (match_test "easy_altivec_constant (op, mode)")))
674 if (mode == V2DImode || mode == V2DFmode)
676 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
677 val = const_vector_elt_as_int (op, elt);
678 val = ((val &
0xff) ^
0x80) -
0x80;
679 return EASY_VECTOR_15_ADD_SELF (val);
682 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
683 (define_predicate "easy_vector_constant_msb"
684 (and (match_code "const_vector")
685 (and (match_test "TARGET_ALTIVEC")
686 (match_test "easy_altivec_constant (op, mode)")))
690 if (mode == V2DImode || mode == V2DFmode)
692 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
693 val = const_vector_elt_as_int (op, elt);
694 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
697 ;; Return true if this is an easy altivec constant that we form
699 (define_predicate "easy_vector_constant_vsldoi"
700 (and (match_code "const_vector")
701 (and (match_test "TARGET_ALTIVEC")
702 (and (match_test "easy_altivec_constant (op, mode)")
703 (match_test "vspltis_shifted (op) !=
0")))))
705 ;; Return
1 if operand is a vector int register or is either a vector constant
706 ;; of all
0 bits of a vector constant of all
1 bits.
707 (define_predicate "vector_int_reg_or_same_bit"
708 (match_code "reg,subreg,const_vector")
710 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
713 else if (REG_P (op) || SUBREG_P (op))
714 return vint_operand (op, mode);
717 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
720 ;; Return
1 if operand is
0.0.
721 (define_predicate "zero_fp_constant"
722 (and (match_code "const_double")
723 (match_test "SCALAR_FLOAT_MODE_P (mode)
724 && op == CONST0_RTX (mode)")))
726 ;; Return
1 if the operand is in volatile memory. Note that during the
727 ;; RTL generation phase, memory_operand does not return TRUE for volatile
728 ;; memory references. So this function allows us to recognize volatile
729 ;; references where it's safe.
730 (define_predicate "volatile_mem_operand"
731 (and (match_code "mem")
732 (match_test "MEM_VOLATILE_P (op)")
733 (if_then_else (match_test "reload_completed")
734 (match_operand
0 "memory_operand")
735 (match_test "memory_address_p (mode, XEXP (op,
0))"))))
737 ;; Return
1 if the operand is a volatile or non-volatile memory operand.
738 (define_predicate "any_memory_operand"
739 (ior (match_operand
0 "memory_operand")
740 (match_operand
0 "volatile_mem_operand")))
742 ;; Return
1 if the operand is an offsettable memory operand.
743 (define_predicate "offsettable_mem_operand"
744 (and (match_operand
0 "any_memory_operand")
745 (match_test "offsettable_nonstrict_memref_p (op)")))
747 ;; Return
1 if the operand is a simple offsettable memory operand
748 ;; that does not include pre-increment, post-increment, etc.
749 (define_predicate "simple_offsettable_mem_operand"
750 (match_operand
0 "offsettable_mem_operand")
752 rtx addr = XEXP (op,
0);
754 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
757 if (!CONSTANT_P (XEXP (addr,
1)))
760 return base_reg_operand (XEXP (addr,
0), Pmode);
763 ;; Return
1 if the operand is suitable for load/store quad memory.
764 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
765 (define_predicate "quad_memory_operand"
768 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
771 if (GET_MODE_SIZE (mode) !=
16 || !MEM_P (op) || MEM_ALIGN (op) <
128)
774 return quad_address_p (XEXP (op,
0), mode, false);
777 ;; Return
1 if the operand is suitable for load/store to vector registers with
778 ;; d-form addressing (register+offset), which was added in ISA
3.0.
779 ;; Unlike quad_memory_operand, we do not have to check for alignment.
780 (define_predicate "vsx_quad_dform_memory_operand"
783 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) !=
16)
786 return quad_address_p (XEXP (op,
0), mode, false);
789 ;; Return
1 if the operand is an indexed or indirect memory operand.
790 (define_predicate "indexed_or_indirect_operand"
794 if (VECTOR_MEM_ALTIVEC_P (mode)
795 && GET_CODE (op) == AND
796 && CONST_INT_P (XEXP (op,
1))
797 && INTVAL (XEXP (op,
1)) == -
16)
800 return indexed_or_indirect_address (op, mode);
803 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
804 ;; moves are supported.
805 (define_predicate "reg_or_indexed_operand"
806 (match_code "mem,reg,subreg")
809 return indexed_or_indirect_operand (op, mode);
810 else if (TARGET_DIRECT_MOVE)
811 return register_operand (op, mode);
816 ;; Return
1 if the operand is an indexed or indirect memory operand with an
817 ;; AND -
16 in it, used to recognize when we need to switch to Altivec loads
818 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
819 ;; while VSX uses the full address and traps)
820 (define_predicate "altivec_indexed_or_indirect_operand"
824 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
825 && GET_CODE (op) == AND
826 && CONST_INT_P (XEXP (op,
1))
827 && INTVAL (XEXP (op,
1)) == -
16)
828 return indexed_or_indirect_address (XEXP (op,
0), mode);
833 ;; Return
1 if the operand is an indexed or indirect address.
834 (define_special_predicate "indexed_or_indirect_address"
835 (and (match_test "REG_P (op)
836 || (GET_CODE (op) == PLUS
837 /* Omit testing REG_P (XEXP (op,
0)). */
838 && REG_P (XEXP (op,
1)))")
839 (match_operand
0 "address_operand")))
841 ;; Return
1 if the operand is an index-form address.
842 (define_special_predicate "indexed_address"
843 (match_test "(GET_CODE (op) == PLUS
844 && REG_P (XEXP (op,
0))
845 && REG_P (XEXP (op,
1)))"))
847 ;; Return
1 if the operand is a MEM with an update-form address. This may
848 ;; also include update-indexed form.
849 (define_special_predicate "update_address_mem"
850 (match_test "(MEM_P (op)
851 && (GET_CODE (XEXP (op,
0)) == PRE_INC
852 || GET_CODE (XEXP (op,
0)) == PRE_DEC
853 || GET_CODE (XEXP (op,
0)) == PRE_MODIFY))"))
855 ;; Anything that matches memory_operand but does not update the address.
856 (define_predicate "non_update_memory_operand"
859 if (update_address_mem (op, mode))
861 return memory_operand (op, mode);
864 ;; Return
1 if the operand is a MEM with an indexed-form address.
865 (define_special_predicate "indexed_address_mem"
866 (match_test "(MEM_P (op)
867 && (indexed_address (XEXP (op,
0), mode)
868 || (GET_CODE (XEXP (op,
0)) == PRE_MODIFY
869 && indexed_address (XEXP (XEXP (op,
0),
1), mode))))"))
871 ;; Return
1 if the operand is either a non-special register or can be used
872 ;; as the operand of a
`mode' add insn.
873 (define_predicate "add_operand"
874 (if_then_else (match_code "const_int")
875 (match_test "satisfies_constraint_I (op)
876 || satisfies_constraint_L (op)
877 || satisfies_constraint_eI (op)")
878 (match_operand 0 "gpc_reg_operand")))
880 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
881 (define_predicate "adde_operand"
882 (if_then_else (match_code "const_int")
883 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
884 (match_operand 0 "gpc_reg_operand")))
886 ;; Return 1 if OP is a constant but not a valid add_operand.
887 (define_predicate "non_add_cint_operand"
888 (and (match_code "const_int")
889 (not (match_operand 0 "add_operand"))))
891 ;; Return 1 if the operand is a constant that can be used as the operand
892 ;; of an AND, OR or XOR.
893 (define_predicate "logical_const_operand"
894 (match_code "const_int")
898 opl = INTVAL (op) & GET_MODE_MASK (mode);
900 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
901 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
904 ;; Return 1 if the operand is a non-special register or a constant that
905 ;; can be used as the operand of an AND, OR or XOR.
906 (define_predicate "logical_operand"
907 (ior (match_operand 0 "gpc_reg_operand")
908 (match_operand 0 "logical_const_operand")))
910 ;; Return 1 if op is a constant that is not a logical operand, but could
911 ;; be split into one.
912 (define_predicate "non_logical_cint_operand"
913 (and (match_code "const_int,const_wide_int")
914 (and (not (match_operand 0 "logical_operand"))
915 (match_operand 0 "reg_or_logical_cint_operand"))))
917 ;; Return 1 if the operand is either a non-special register or a
918 ;; constant that can be used as the operand of a logical AND.
919 (define_predicate "and_operand"
920 (ior (and (match_code "const_int")
921 (match_test "rs6000_is_valid_and_mask (op, mode)"))
922 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
923 (match_operand 0 "gpc_reg_operand")
924 (match_operand 0 "logical_operand"))))
926 ;; Return 1 if the operand is either a logical operand or a short cint operand.
927 (define_predicate "scc_eq_operand"
928 (ior (match_operand 0 "logical_operand")
929 (match_operand 0 "short_cint_operand")))
931 ;; Return 1 if the operand is a general non-special register or memory operand.
932 (define_predicate "reg_or_mem_operand"
933 (ior (match_operand 0 "gpc_reg_operand")
934 (match_operand 0 "any_memory_operand")
935 (and (match_code "mem")
936 (match_test "macho_lo_sum_memory_operand (op, mode)"))))
938 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
939 (define_predicate "zero_reg_mem_operand"
940 (ior (and (match_test "TARGET_VSX")
941 (match_operand 0 "zero_fp_constant"))
942 (match_operand 0 "reg_or_mem_operand")))
944 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
945 ;; data types inside of a vector that scalar instructions operate on
946 (define_predicate "vsx_scalar_64bit"
947 (match_code "const_int")
949 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
952 ;; Return 1 if the operand is a general register or memory operand without
953 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
955 (define_predicate "lwa_operand"
956 (match_code "reg,subreg,mem")
958 rtx inner, addr, offset;
961 if (reload_completed && SUBREG_P (inner))
962 inner = SUBREG_REG (inner);
964 if (gpc_reg_operand (inner, mode))
966 if (!any_memory_operand (inner, mode))
969 addr = XEXP (inner, 0);
971 /* The LWA instruction uses the DS-form instruction format which requires
972 that the bottom two bits of the offset must be 0. The prefixed PLWA does
973 not have this restriction. While the actual load from memory is 32-bits,
974 we pass in DImode here to test for using a DS instruction. */
975 if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS))
978 if (GET_CODE (addr) == PRE_INC
979 || GET_CODE (addr) == PRE_DEC
980 || (GET_CODE (addr) == PRE_MODIFY
981 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
983 if (GET_CODE (addr) == LO_SUM
984 && REG_P (XEXP (addr, 0))
985 && GET_CODE (XEXP (addr, 1)) == CONST)
986 addr = XEXP (XEXP (addr, 1), 0);
987 if (GET_CODE (addr) != PLUS)
989 offset = XEXP (addr, 1);
990 if (!CONST_INT_P (offset))
992 return INTVAL (offset) % 4 == 0;
995 ;; Return 1 if the operand is a memory operand that has a valid address for
996 ;; a DS-form instruction. I.e. the address has to be either just a register,
997 ;; or register + const where the two low order bits of const are zero.
998 (define_predicate "ds_form_mem_operand"
999 (match_code "subreg,mem")
1001 if (!any_memory_operand (op, mode))
1004 rtx addr = XEXP (op, 0);
1006 return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS;
1009 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1010 (define_predicate "symbol_ref_operand"
1011 (and (match_code "symbol_ref")
1012 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1013 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1015 ;; Return 1 if op is an operand that can be loaded via the GOT.
1016 ;; or non-special register register field no cr0
1017 (define_predicate "got_operand"
1018 (match_code "symbol_ref,const,label_ref"))
1020 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1021 ;; excluding labels involving addition.
1022 (define_predicate "got_no_const_operand"
1023 (match_code "symbol_ref,label_ref"))
1025 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1026 (define_predicate "rs6000_tls_symbol_ref"
1027 (and (match_code "symbol_ref")
1028 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1030 ;; Return 1 for the CONST_INT or UNSPEC second CALL operand.
1031 ;; Prevents unwanted substitution of the unspec got_reg arg.
1032 (define_predicate "unspec_tls"
1033 (match_code "const_int,unspec")
1035 if (CONST_INT_P (op))
1037 if (XINT (op, 1) == UNSPEC_TLSGD)
1038 return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx;
1039 if (XINT (op, 1) == UNSPEC_TLSLD)
1040 return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx;
1044 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1045 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1046 (define_predicate "call_operand"
1047 (if_then_else (match_code "reg")
1048 (match_test "REGNO (op) == LR_REGNO
1049 || REGNO (op) == CTR_REGNO
1050 || !HARD_REGISTER_P (op)")
1051 (match_code "symbol_ref")))
1053 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1054 ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR.
1055 (define_predicate "indirect_call_operand"
1056 (match_code "reg,unspec")
1059 return (REGNO (op) == LR_REGNO
1060 || REGNO (op) == CTR_REGNO);
1061 if (GET_CODE (op) == UNSPEC)
1063 if (XINT (op, 1) != UNSPEC_PLTSEQ)
1065 op = XVECEXP (op, 0, 0);
1066 return REG_P (op) && REGNO (op) == CTR_REGNO;
1071 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1073 (define_predicate "current_file_function_operand"
1074 (and (match_code "symbol_ref")
1075 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1076 && (SYMBOL_REF_LOCAL_P (op)
1077 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1078 && !decl_replaceable_p (current_function_decl)))
1079 && !((DEFAULT_ABI == ABI_AIX
1080 || DEFAULT_ABI == ABI_ELFv2)
1081 && (SYMBOL_REF_EXTERNAL_P (op)
1082 || SYMBOL_REF_WEAK (op)))
1083 && !(DEFAULT_ABI == ABI_ELFv2
1084 && SYMBOL_REF_DECL (op) != NULL
1085 && TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL
1086 && (rs6000_fndecl_pcrel_p (SYMBOL_REF_DECL (op))
1087 != rs6000_pcrel_p ()))")))
1089 ;; Return 1 if this operand is a valid input for a move insn.
1090 (define_predicate "input_operand"
1091 (match_code "symbol_ref,const,reg,subreg,mem,
1092 const_double,const_wide_int,const_vector,const_int")
1094 /* Memory is always valid. */
1095 if (any_memory_operand (op, mode))
1098 /* For floating-point, easy constants are valid. */
1099 if (SCALAR_FLOAT_MODE_P (mode)
1100 && easy_fp_constant (op, mode))
1103 /* Allow any integer constant. */
1104 if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op))
1107 /* Allow easy vector constants. */
1108 if (GET_CODE (op) == CONST_VECTOR
1109 && easy_vector_constant (op, mode))
1112 /* For floating-point or multi-word mode, the only remaining valid type
1114 if (SCALAR_FLOAT_MODE_P (mode)
1115 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1116 return register_operand (op, mode);
1118 /* We don't allow moving the carry bit around. */
1119 if (ca_operand (op, mode))
1122 /* The only cases left are integral modes one word or smaller (we
1123 do not get called for MODE_CC values). These can be in any
1125 if (register_operand (op, mode))
1128 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1130 if (DEFAULT_ABI == ABI_V4
1131 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST)
1132 && small_data_operand (op, Pmode))
1138 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1139 (define_predicate "splat_input_operand"
1140 (match_code "reg,subreg,mem")
1146 else if (mode == DImode)
1148 else if (mode == SImode && TARGET_P9_VECTOR)
1150 else if (mode == SFmode && TARGET_P9_VECTOR)
1157 rtx addr = XEXP (op, 0);
1159 if (! volatile_ok && MEM_VOLATILE_P (op))
1162 if (lra_in_progress || reload_completed)
1163 return indexed_or_indirect_address (addr, vmode);
1165 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1167 return gpc_reg_operand (op, mode);
1170 ;; Return 1 if this operand is valid for a MMA assemble accumulator insn.
1171 (define_special_predicate "mma_assemble_input_operand"
1172 (match_test "(mode == V16QImode
1173 && (vsx_register_operand (op, mode)
1175 && quad_address_p (XEXP (op, 0), mode, false))))"))
1177 ;; Return 1 if this operand is valid for an MMA disassemble insn.
1178 (define_predicate "mma_disassemble_output_operand"
1179 (match_code "reg,subreg,mem")
1182 op = SUBREG_REG (op);
1186 return vsx_register_operand (op, mode);
1189 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1190 (define_predicate "rotate_mask_operator"
1191 (match_code "rotate,ashift,lshiftrt"))
1193 ;; Return true if operand is boolean operator.
1194 (define_predicate "boolean_operator"
1195 (match_code "and,ior,xor"))
1197 ;; Return true if operand is OR-form of boolean operator.
1198 (define_predicate "boolean_or_operator"
1199 (match_code "ior,xor"))
1201 ;; Return true if operand is an equality operator.
1202 (define_special_predicate "equality_operator"
1203 (match_code "eq,ne"))
1205 ;; Return 1 if OP is a comparison operation that is valid for a branch
1206 ;; instruction. We check the opcode against the mode of the CC value.
1207 ;; validate_condition_mode is an assertion.
1208 (define_predicate "branch_comparison_operator"
1209 (and (match_operand 0 "comparison_operator")
1210 (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1211 (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1212 (if_then_else (match_test "flag_finite_math_only")
1213 (match_code "lt,le,gt,ge,eq,ne,unordered,ordered")
1214 (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered"))
1215 (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne"))
1216 (match_test "validate_condition_mode (GET_CODE (op),
1217 GET_MODE (XEXP (op, 0))),
1220 ;; Return 1 if OP is a comparison that needs an extra instruction to do (a
1221 ;; crlogical or an extra branch).
1222 (define_predicate "extra_insn_branch_comparison_operator"
1223 (and (match_operand 0 "comparison_operator")
1224 (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1225 (match_code "ltgt,le,ge,unlt,ungt,uneq")
1226 (match_test "validate_condition_mode (GET_CODE (op),
1227 GET_MODE (XEXP (op, 0))),
1230 ;; Return 1 if OP is an unsigned comparison operator.
1231 (define_predicate "unsigned_comparison_operator"
1232 (match_code "ltu,gtu,leu,geu"))
1234 ;; Return 1 if OP is a signed comparison operator.
1235 (define_predicate "signed_comparison_operator"
1236 (match_code "lt,gt,le,ge"))
1238 ;; Return 1 if OP is a signed comparison or an equality operator.
1239 (define_predicate "signed_or_equality_comparison_operator"
1240 (ior (match_operand 0 "equality_operator")
1241 (match_operand 0 "signed_comparison_operator")))
1243 ;; Return 1 if OP is an unsigned comparison or an equality operator.
1244 (define_predicate "unsigned_or_equality_comparison_operator"
1245 (ior (match_operand 0 "equality_operator")
1246 (match_operand 0 "unsigned_comparison_operator")))
1248 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1249 ;; it must be a positive comparison.
1250 (define_predicate "scc_comparison_operator"
1251 (and (match_operand 0 "branch_comparison_operator")
1252 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1254 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1256 (define_predicate "scc_rev_comparison_operator"
1257 (and (match_operand 0 "branch_comparison_operator")
1258 (match_code "ne,le,ge,leu,geu,ordered")))
1260 ;; Return 1 if OP is a comparison operator suitable for floating point
1261 ;; vector/scalar comparisons that generate a -1/0 mask.
1262 (define_predicate "fpmask_comparison_operator"
1263 (match_code "eq,gt,ge"))
1265 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1266 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1267 ;; fpmask_comparison_operator).
1268 (define_predicate "invert_fpmask_comparison_operator"
1269 (match_code "ne,unlt,unle"))
1271 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1272 ;; comparisons that generate a -1/0 mask.
1273 (define_predicate "vecint_comparison_operator"
1274 (match_code "eq,gt,gtu"))
1276 ;; Return 1 if OP is a comparison operation that is valid for a branch
1277 ;; insn, which is true if the corresponding bit in the CC register is set.
1278 (define_predicate "branch_positive_comparison_operator"
1279 (and (match_operand 0 "branch_comparison_operator")
1280 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1282 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1284 (define_predicate "save_world_operation"
1285 (match_code "parallel")
1290 int count = XVECLEN (op, 0);
1296 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1297 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1300 for (i=1; i <= 18; i++)
1302 elt = XVECEXP (op, 0, index++);
1303 if (GET_CODE (elt) != SET
1304 || !MEM_P (SET_DEST (elt))
1305 || !memory_operand (SET_DEST (elt), DFmode)
1306 || !REG_P (SET_SRC (elt))
1307 || GET_MODE (SET_SRC (elt)) != DFmode)
1311 for (i=1; i <= 12; i++)
1313 elt = XVECEXP (op, 0, index++);
1314 if (GET_CODE (elt) != SET
1315 || !MEM_P (SET_DEST (elt))
1316 || !REG_P (SET_SRC (elt))
1317 || GET_MODE (SET_SRC (elt)) != V4SImode)
1321 for (i=1; i <= 19; i++)
1323 elt = XVECEXP (op, 0, index++);
1324 if (GET_CODE (elt) != SET
1325 || !MEM_P (SET_DEST (elt))
1326 || !memory_operand (SET_DEST (elt), Pmode)
1327 || !REG_P (SET_SRC (elt))
1328 || GET_MODE (SET_SRC (elt)) != Pmode)
1332 elt = XVECEXP (op, 0, index++);
1333 if (GET_CODE (elt) != SET
1334 || !MEM_P (SET_DEST (elt))
1335 || !memory_operand (SET_DEST (elt), Pmode)
1336 || !REG_P (SET_SRC (elt))
1337 || REGNO (SET_SRC (elt)) != CR2_REGNO
1338 || GET_MODE (SET_SRC (elt)) != Pmode)
1341 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1342 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1347 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1349 (define_predicate "restore_world_operation"
1350 (match_code "parallel")
1355 int count = XVECLEN (op, 0);
1361 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1362 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1363 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1366 elt = XVECEXP (op, 0, index++);
1367 if (GET_CODE (elt) != SET
1368 || !MEM_P (SET_SRC (elt))
1369 || !memory_operand (SET_SRC (elt), Pmode)
1370 || !REG_P (SET_DEST (elt))
1371 || REGNO (SET_DEST (elt)) != CR2_REGNO
1372 || GET_MODE (SET_DEST (elt)) != Pmode)
1375 for (i=1; i <= 19; i++)
1377 elt = XVECEXP (op, 0, index++);
1378 if (GET_CODE (elt) != SET
1379 || !MEM_P (SET_SRC (elt))
1380 || !memory_operand (SET_SRC (elt), Pmode)
1381 || !REG_P (SET_DEST (elt))
1382 || GET_MODE (SET_DEST (elt)) != Pmode)
1386 for (i=1; i <= 12; i++)
1388 elt = XVECEXP (op, 0, index++);
1389 if (GET_CODE (elt) != SET
1390 || !MEM_P (SET_SRC (elt))
1391 || !REG_P (SET_DEST (elt))
1392 || GET_MODE (SET_DEST (elt)) != V4SImode)
1396 for (i=1; i <= 18; i++)
1398 elt = XVECEXP (op, 0, index++);
1399 if (GET_CODE (elt) != SET
1400 || !MEM_P (SET_SRC (elt))
1401 || !memory_operand (SET_SRC (elt), DFmode)
1402 || !REG_P (SET_DEST (elt))
1403 || GET_MODE (SET_DEST (elt)) != DFmode)
1407 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1408 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1409 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1410 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1411 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1416 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1417 (define_predicate "vrsave_operation"
1418 (match_code "parallel")
1420 int count = XVECLEN (op, 0);
1421 unsigned int dest_regno, src_regno;
1425 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1426 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1427 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1428 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1431 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1432 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1434 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1437 for (i = 1; i < count; i++)
1439 rtx elt = XVECEXP (op, 0, i);
1441 if (GET_CODE (elt) != CLOBBER
1442 && GET_CODE (elt) != SET)
1449 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1450 (define_predicate "mfcr_operation"
1451 (match_code "parallel")
1453 int count = XVECLEN (op, 0);
1456 /* Perform a quick check so we don't blow up below. */
1458 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1459 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1460 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1463 for (i = 0; i < count; i++)
1465 rtx exp = XVECEXP (op, 0, i);
1470 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1472 if (!REG_P (src_reg)
1473 || GET_MODE (src_reg) != CCmode
1474 || ! CR_REGNO_P (REGNO (src_reg)))
1477 if (GET_CODE (exp) != SET
1478 || !REG_P (SET_DEST (exp))
1479 || GET_MODE (SET_DEST (exp)) != SImode
1480 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1482 unspec = SET_SRC (exp);
1483 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1485 if (GET_CODE (unspec) != UNSPEC
1486 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1487 || XVECLEN (unspec, 0) != 2
1488 || XVECEXP (unspec, 0, 0) != src_reg
1489 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1490 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1496 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1497 (define_predicate "mtcrf_operation"
1498 (match_code "parallel")
1500 int count = XVECLEN (op, 0);
1504 /* Perform a quick check so we don't blow up below. */
1506 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1507 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1508 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1510 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1512 if (!REG_P (src_reg)
1513 || GET_MODE (src_reg) != SImode
1514 || ! INT_REGNO_P (REGNO (src_reg)))
1517 for (i = 0; i < count; i++)
1519 rtx exp = XVECEXP (op, 0, i);
1523 if (GET_CODE (exp) != SET
1524 || !REG_P (SET_DEST (exp))
1525 || GET_MODE (SET_DEST (exp)) != CCmode
1526 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1528 unspec = SET_SRC (exp);
1529 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1531 if (GET_CODE (unspec) != UNSPEC
1532 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1533 || XVECLEN (unspec, 0) != 2
1534 || XVECEXP (unspec, 0, 0) != src_reg
1535 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1536 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1542 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1543 (define_predicate "crsave_operation"
1544 (match_code "parallel")
1546 int count = XVECLEN (op, 0);
1549 for (i = 1; i < count; i++)
1551 rtx exp = XVECEXP (op, 0, i);
1553 if (GET_CODE (exp) != USE
1554 || !REG_P (XEXP (exp, 0))
1555 || GET_MODE (XEXP (exp, 0)) != CCmode
1556 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1562 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1563 (define_predicate "lmw_operation"
1564 (match_code "parallel")
1566 int count = XVECLEN (op, 0);
1567 unsigned int dest_regno;
1569 unsigned int base_regno;
1570 HOST_WIDE_INT offset;
1573 /* Perform a quick check so we don't blow up below. */
1575 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1576 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1577 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
1580 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1581 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1584 || count != 32 - (int) dest_regno)
1587 if (legitimate_indirect_address_p (src_addr, 0))
1590 base_regno = REGNO (src_addr);
1591 if (base_regno == 0)
1594 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1596 offset = INTVAL (XEXP (src_addr, 1));
1597 base_regno = REGNO (XEXP (src_addr, 0));
1602 for (i = 0; i < count; i++)
1604 rtx elt = XVECEXP (op, 0, i);
1607 HOST_WIDE_INT newoffset;
1609 if (GET_CODE (elt) != SET
1610 || !REG_P (SET_DEST (elt))
1611 || GET_MODE (SET_DEST (elt)) != SImode
1612 || REGNO (SET_DEST (elt)) != dest_regno + i
1613 || !MEM_P (SET_SRC (elt))
1614 || GET_MODE (SET_SRC (elt)) != SImode)
1616 newaddr = XEXP (SET_SRC (elt), 0);
1617 if (legitimate_indirect_address_p (newaddr, 0))
1622 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1624 addr_reg = XEXP (newaddr, 0);
1625 newoffset = INTVAL (XEXP (newaddr, 1));
1629 if (REGNO (addr_reg) != base_regno
1630 || newoffset != offset + 4 * i)
1637 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1638 (define_predicate "stmw_operation"
1639 (match_code "parallel")
1641 int count = XVECLEN (op, 0);
1642 unsigned int src_regno;
1644 unsigned int base_regno;
1645 HOST_WIDE_INT offset;
1648 /* Perform a quick check so we don't blow up below. */
1650 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1651 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
1652 || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
1655 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1656 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1659 || count != 32 - (int) src_regno)
1662 if (legitimate_indirect_address_p (dest_addr, 0))
1665 base_regno = REGNO (dest_addr);
1666 if (base_regno == 0)
1669 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1671 offset = INTVAL (XEXP (dest_addr, 1));
1672 base_regno = REGNO (XEXP (dest_addr, 0));
1677 for (i = 0; i < count; i++)
1679 rtx elt = XVECEXP (op, 0, i);
1682 HOST_WIDE_INT newoffset;
1684 if (GET_CODE (elt) != SET
1685 || !REG_P (SET_SRC (elt))
1686 || GET_MODE (SET_SRC (elt)) != SImode
1687 || REGNO (SET_SRC (elt)) != src_regno + i
1688 || !MEM_P (SET_DEST (elt))
1689 || GET_MODE (SET_DEST (elt)) != SImode)
1691 newaddr = XEXP (SET_DEST (elt), 0);
1692 if (legitimate_indirect_address_p (newaddr, 0))
1697 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1699 addr_reg = XEXP (newaddr, 0);
1700 newoffset = INTVAL (XEXP (newaddr, 1));
1704 if (REGNO (addr_reg) != base_regno
1705 || newoffset != offset + 4 * i)
1712 ;; Return 1 if OP is a stack tie operand.
1713 (define_predicate "tie_operand"
1714 (match_code "parallel")
1716 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1717 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0))
1718 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1719 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1722 ;; Match a small code model toc reference (or medium and large
1723 ;; model toc references before reload).
1724 (define_predicate "small_toc_ref"
1725 (match_code "unspec,plus")
1727 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1730 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1734 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1735 ;; GPR registers on power8.
1736 (define_predicate "fusion_gpr_addis"
1737 (match_code "const_int,high,plus")
1739 HOST_WIDE_INT value;
1742 if (GET_CODE (op) == HIGH)
1745 if (CONST_INT_P (op))
1748 else if (GET_CODE (op) == PLUS
1749 && base_reg_operand (XEXP (op, 0), Pmode)
1750 && CONST_INT_P (XEXP (op, 1)))
1751 int_const = XEXP (op, 1);
1756 value = INTVAL (int_const);
1757 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1760 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1763 /* Power8 only does the fusion if the top 12 bits of the addis value are all
1765 return (IN_RANGE (value >> 16, -16, 15));
1768 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1769 ;; and loads to GPR registers on power8.
1770 (define_predicate "fusion_gpr_mem_load"
1771 (match_code "mem,sign_extend,zero_extend")
1773 rtx addr, base, offset;
1775 /* Handle sign/zero extend. */
1776 if (GET_CODE (op) == ZERO_EXTEND
1777 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1780 mode = GET_MODE (op);
1794 if (!TARGET_POWERPC64)
1798 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1804 addr = XEXP (op, 0);
1805 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1808 base = XEXP (addr, 0);
1809 if (!base_reg_operand (base, GET_MODE (base)))
1812 offset = XEXP (addr, 1);
1814 if (GET_CODE (addr) == PLUS)
1815 return satisfies_constraint_I (offset);
1817 else if (GET_CODE (addr) == LO_SUM)
1819 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1820 return small_toc_ref (offset, GET_MODE (offset));
1822 else if (TARGET_ELF && !TARGET_POWERPC64)
1823 return CONSTANT_P (offset);
1829 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1830 ;; memory field with both the addis and the memory offset. Sign extension
1831 ;; is not handled here, since lha and lwa are not fused.
1832 (define_predicate "fusion_addis_mem_combo_load"
1833 (match_code "mem,zero_extend")
1835 rtx addr, base, offset;
1837 /* Handle zero extend. */
1838 if (GET_CODE (op) == ZERO_EXTEND)
1841 mode = GET_MODE (op);
1854 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1855 separate instructions. */
1857 if (!TARGET_POWERPC64)
1861 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1867 addr = XEXP (op, 0);
1868 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1871 base = XEXP (addr, 0);
1872 if (!fusion_gpr_addis (base, GET_MODE (base)))
1875 offset = XEXP (addr, 1);
1876 if (GET_CODE (addr) == PLUS)
1877 return satisfies_constraint_I (offset);
1879 else if (GET_CODE (addr) == LO_SUM)
1881 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1882 return small_toc_ref (offset, GET_MODE (offset));
1884 else if (TARGET_ELF && !TARGET_POWERPC64)
1885 return CONSTANT_P (offset);
1892 ;; Return true if the operand is a PC-relative address of a local symbol or a
1893 ;; label that can be used directly in a memory operation.
1894 (define_predicate "pcrel_local_address"
1895 (match_code "label_ref,symbol_ref,const")
1897 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1898 return iform == INSN_FORM_PCREL_LOCAL;
1901 ;; Return true if the operand is a PC-relative external symbol whose address
1902 ;; can be loaded into a register.
1903 (define_predicate "pcrel_external_address"
1904 (match_code "symbol_ref,const")
1906 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1907 return iform == INSN_FORM_PCREL_EXTERNAL;
1910 ;; Return true if the address is PC-relative and the symbol is either local or
1912 (define_predicate "pcrel_local_or_external_address"
1913 (ior (match_operand 0 "pcrel_local_address")
1914 (match_operand 0 "pcrel_external_address")))
1916 ;; Return true if the operand is a memory address that uses a prefixed address.
1917 (define_predicate "prefixed_memory"
1920 return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT);
1923 ;; Return true if the operand is a valid memory operand with a D-form
1924 ;; address that could be merged with the load of a PC-relative external address
1925 ;; with the PCREL_OPT optimization. We don't check here whether or not the
1926 ;; offset needs to be used in a DS-FORM (bottom 2 bits 0) or DQ-FORM (bottom 4
1927 ;; bits 0) instruction.
1928 (define_predicate "d_form_memory"
1931 if (!memory_operand (op, mode))
1934 rtx addr = XEXP (op, 0);
1938 if (SUBREG_P (addr) && REG_P (SUBREG_REG (addr)))
1941 return !indexed_address (addr, mode);