1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C)
2005-
2017 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version
3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return
1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return
1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return
1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return
1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have
64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return
1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand
0 "register_operand")
68 if (GET_CODE (op) == SUBREG)
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return
1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand
0 "register_operand")
89 if (GET_CODE (op) == SUBREG)
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand
0 "register_operand")
110 if (GET_CODE (op) == SUBREG)
111 op = SUBREG_REG (op);
116 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return
1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand
0 "register_operand")
127 if (GET_CODE (op) == SUBREG)
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return
1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand
0 "register_operand")
149 if (GET_CODE (op) == SUBREG)
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return
1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand
0 "register_operand")
171 if (GET_CODE (op) == SUBREG)
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return
1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand
0 "register_operand")
193 if (GET_CODE (op) == SUBREG)
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return
1 if op is a signed
5-bit constant integer.
203 (define_predicate "s5bit_cint_operand"
204 (and (match_code "const_int")
205 (match_test "INTVAL (op) >= -
16 && INTVAL (op) <=
15")))
207 ;; Return
1 if op is a unsigned
3-bit constant integer.
208 (define_predicate "u3bit_cint_operand"
209 (and (match_code "const_int")
210 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
7")))
212 ;; Return
1 if op is a unsigned
5-bit constant integer.
213 (define_predicate "u5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
31")))
217 ;; Return
1 if op is a unsigned
6-bit constant integer.
218 (define_predicate "u6bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
63")))
222 ;; Return
1 if op is an unsigned
7-bit constant integer.
223 (define_predicate "u7bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "IN_RANGE (INTVAL (op),
0,
127)")))
227 ;; Return
1 if op is a signed
8-bit constant integer.
228 ;; Integer multiplication complete more quickly
229 (define_predicate "s8bit_cint_operand"
230 (and (match_code "const_int")
231 (match_test "INTVAL (op) >= -
128 && INTVAL (op) <=
127")))
233 ;; Return
1 if op is a unsigned
10-bit constant integer.
234 (define_predicate "u10bit_cint_operand"
235 (and (match_code "const_int")
236 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1023")))
238 ;; Return
1 if op is a constant integer that can fit in a D field.
239 (define_predicate "short_cint_operand"
240 (and (match_code "const_int")
241 (match_test "satisfies_constraint_I (op)")))
243 ;; Return
1 if op is a constant integer that can fit in an unsigned D field.
244 (define_predicate "u_short_cint_operand"
245 (and (match_code "const_int")
246 (match_test "satisfies_constraint_K (op)")))
248 ;; Return
1 if op is a constant integer that is a signed
16-bit constant
249 ;; shifted left
16 bits
250 (define_predicate "upper16_cint_operand"
251 (and (match_code "const_int")
252 (match_test "satisfies_constraint_L (op)")))
254 ;; Return
1 if op is a constant integer that cannot fit in a signed D field.
255 (define_predicate "non_short_cint_operand"
256 (and (match_code "const_int")
257 (match_test "(unsigned HOST_WIDE_INT)
258 (INTVAL (op) +
0x8000) >=
0x10000")))
260 ;; Return
1 if op is a positive constant integer that is an exact power of
2.
261 (define_predicate "exact_log2_cint_operand"
262 (and (match_code "const_int")
263 (match_test "INTVAL (op) >
0 && exact_log2 (INTVAL (op)) >=
0")))
265 ;; Match op =
0 or op =
1.
266 (define_predicate "const_0_to_1_operand"
267 (and (match_code "const_int")
268 (match_test "IN_RANGE (INTVAL (op),
0,
1)")))
271 (define_predicate "const_0_to_3_operand"
272 (and (match_code "const_int")
273 (match_test "IN_RANGE (INTVAL (op),
0,
3)")))
275 ;; Match op =
2 or op =
3.
276 (define_predicate "const_2_to_3_operand"
277 (and (match_code "const_int")
278 (match_test "IN_RANGE (INTVAL (op),
2,
3)")))
281 (define_predicate "const_0_to_7_operand"
282 (and (match_code "const_int")
283 (match_test "IN_RANGE (INTVAL (op),
0,
7)")))
286 (define_predicate "const_0_to_12_operand"
287 (and (match_code "const_int")
288 (match_test "IN_RANGE (INTVAL (op),
0,
12)")))
291 (define_predicate "const_0_to_15_operand"
292 (and (match_code "const_int")
293 (match_test "IN_RANGE (INTVAL (op),
0,
15)")))
295 ;; Return
1 if op is a register that is not special.
296 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
297 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
298 ;; the fact that SFmode is represented as DFmode in the VSX registers.
299 (define_predicate "gpc_reg_operand"
300 (match_operand
0 "register_operand")
302 if (GET_CODE (op) == SUBREG)
304 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
307 op = SUBREG_REG (op);
313 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
316 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
319 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
322 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
325 ;; Return
1 if op is a general purpose register. Unlike gpc_reg_operand, don't
326 ;; allow floating point or vector registers. Since vector registers are not
327 ;; allowed, we don't have to reject SFmode/SImode subregs.
328 (define_predicate "int_reg_operand"
329 (match_operand
0 "register_operand")
331 if (GET_CODE (op) == SUBREG)
333 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
336 op = SUBREG_REG (op);
342 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
345 return INT_REGNO_P (REGNO (op));
348 ;; Like int_reg_operand, but don't return true for pseudo registers
349 ;; We don't have to check for SF SUBREGS because pseudo registers
350 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
351 (define_predicate "int_reg_operand_not_pseudo"
352 (match_operand
0 "register_operand")
354 if (GET_CODE (op) == SUBREG)
355 op = SUBREG_REG (op);
360 if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
363 return INT_REGNO_P (REGNO (op));
366 ;; Like int_reg_operand, but only return true for base registers
367 (define_predicate "base_reg_operand"
368 (match_operand
0 "int_reg_operand")
370 if (GET_CODE (op) == SUBREG)
371 op = SUBREG_REG (op);
376 return (REGNO (op) != FIRST_GPR_REGNO);
380 ;; Return true if this is a traditional floating point register
381 (define_predicate "fpr_reg_operand"
382 (match_code "reg,subreg")
386 if (GET_CODE (op) == SUBREG)
387 op = SUBREG_REG (op);
393 if (r >= FIRST_PSEUDO_REGISTER)
396 return FP_REGNO_P (r);
399 ;; Return true if this is a register that can has D-form addressing (GPR and
400 ;; traditional FPR registers for scalars). ISA
3.0 (power9) adds D-form
401 ;; addressing for scalars in Altivec registers.
403 ;; If this is a pseudo only allow for GPR fusion in power8. If we have the
404 ;; power9 fusion allow the floating point types.
405 (define_predicate "toc_fusion_or_p9_reg_operand"
406 (match_code "reg,subreg")
409 bool gpr_p = (mode == QImode || mode == HImode || mode == SImode
411 || (TARGET_POWERPC64 && (mode == DImode || mode == DFmode)));
412 bool fpr_p = (TARGET_P9_FUSION
413 && (mode == DFmode || mode == SFmode
414 || (TARGET_POWERPC64 && mode == DImode)));
415 bool vmx_p = (TARGET_P9_FUSION && TARGET_P9_VECTOR
416 && (mode == DFmode || mode == SFmode));
418 if (!TARGET_P8_FUSION)
421 if (GET_CODE (op) == SUBREG)
422 op = SUBREG_REG (op);
428 if (r >= FIRST_PSEUDO_REGISTER)
429 return (gpr_p || fpr_p || vmx_p);
437 if (ALTIVEC_REGNO_P (r))
443 ;; Return
1 if op is a HTM specific SPR register.
444 (define_predicate "htm_spr_reg_operand"
445 (match_operand
0 "register_operand")
450 if (GET_CODE (op) == SUBREG)
451 op = SUBREG_REG (op);
470 ;; Return
1 if op is a general purpose register that is an even register
471 ;; which suitable for a load/store quad operation
472 ;; Subregs are not allowed here because when they are combine can
473 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
474 ;; think the innermost reg needs reloading, in TImode instead of
475 ;; PTImode. So reload will choose a reg in TImode which has no
476 ;; requirement that the reg be even.
477 (define_predicate "quad_int_reg_operand"
482 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
486 if (r >= FIRST_PSEUDO_REGISTER)
489 return (INT_REGNO_P (r) && ((r &
1) ==
0));
492 ;; Return
1 if op is a register that is a condition register field.
493 (define_predicate "cc_reg_operand"
494 (match_operand
0 "register_operand")
496 if (GET_CODE (op) == SUBREG)
497 op = SUBREG_REG (op);
502 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
505 return CR_REGNO_P (REGNO (op));
508 ;; Return
1 if op is a register that is a condition register field not cr0.
509 (define_predicate "cc_reg_not_cr0_operand"
510 (match_operand
0 "register_operand")
512 if (GET_CODE (op) == SUBREG)
513 op = SUBREG_REG (op);
518 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
521 return CR_REGNO_NOT_CR0_P (REGNO (op));
524 ;; Return
1 if op is a constant integer valid for D field
525 ;; or non-special register register.
526 (define_predicate "reg_or_short_operand"
527 (if_then_else (match_code "const_int")
528 (match_operand
0 "short_cint_operand")
529 (match_operand
0 "gpc_reg_operand")))
531 ;; Return
1 if op is a constant integer valid for DS field
532 ;; or non-special register.
533 (define_predicate "reg_or_aligned_short_operand"
534 (if_then_else (match_code "const_int")
535 (and (match_operand
0 "short_cint_operand")
536 (match_test "!(INTVAL (op) &
3)"))
537 (match_operand
0 "gpc_reg_operand")))
539 ;; Return
1 if op is a constant integer whose high-order
16 bits are zero
540 ;; or non-special register.
541 (define_predicate "reg_or_u_short_operand"
542 (if_then_else (match_code "const_int")
543 (match_operand
0 "u_short_cint_operand")
544 (match_operand
0 "gpc_reg_operand")))
546 ;; Return
1 if op is any constant integer
547 ;; or non-special register.
548 (define_predicate "reg_or_cint_operand"
549 (ior (match_code "const_int")
550 (match_operand
0 "gpc_reg_operand")))
552 ;; Return
1 if op is a constant integer valid for addition with addis, addi.
553 (define_predicate "add_cint_operand"
554 (and (match_code "const_int")
555 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
556 + (mode == SImode ?
0x80000000 :
0x80008000))
557 < (unsigned HOST_WIDE_INT)
0x100000000ll")))
559 ;; Return
1 if op is a constant integer valid for addition
560 ;; or non-special register.
561 (define_predicate "reg_or_add_cint_operand"
562 (if_then_else (match_code "const_int")
563 (match_operand
0 "add_cint_operand")
564 (match_operand
0 "gpc_reg_operand")))
566 ;; Return
1 if op is a constant integer valid for subtraction
567 ;; or non-special register.
568 (define_predicate "reg_or_sub_cint_operand"
569 (if_then_else (match_code "const_int")
570 (match_test "(unsigned HOST_WIDE_INT)
571 (- UINTVAL (op) + (mode == SImode ?
0x80000000 :
0x80008000))
572 < (unsigned HOST_WIDE_INT)
0x100000000ll")
573 (match_operand
0 "gpc_reg_operand")))
575 ;; Return
1 if op is any
32-bit unsigned constant integer
576 ;; or non-special register.
577 (define_predicate "reg_or_logical_cint_operand"
578 (if_then_else (match_code "const_int")
579 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
581 || ((INTVAL (op) & GET_MODE_MASK (mode)
582 & (~ (unsigned HOST_WIDE_INT)
0xffffffff)) ==
0)")
583 (match_operand
0 "gpc_reg_operand")))
585 ;; Like reg_or_logical_cint_operand, but allow vsx registers
586 (define_predicate "vsx_reg_or_cint_operand"
587 (ior (match_operand
0 "vsx_register_operand")
588 (match_operand
0 "reg_or_logical_cint_operand")))
590 ;; Return
1 if operand is a CONST_DOUBLE that can be set in a register
591 ;; with no more than one instruction per word.
592 (define_predicate "easy_fp_constant"
593 (match_code "const_double")
595 if (GET_MODE (op) != mode
596 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
599 /* Consider all constants with -msoft-float to be easy. */
600 if ((TARGET_SOFT_FLOAT
601 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
605 /*
0.0D is not all zero bits. */
606 if (DECIMAL_FLOAT_MODE_P (mode))
609 /* The constant
0.0 is easy under VSX. */
610 if (TARGET_VSX && SCALAR_FLOAT_MODE_P (mode) && op == CONST0_RTX (mode))
613 /* If we are using V
.4 style PIC, consider all constants to be hard. */
614 if (flag_pic && DEFAULT_ABI == ABI_V4)
617 /* If we have real FPRs, consider floating point constants hard (other than
618 0.0 under VSX), so that the constant gets pushed to memory during the
619 early RTL phases. This has the advantage that double precision constants
620 that can be represented in single precision without a loss of precision
621 will use single precision loads. */
633 return (num_insns_constant (op, DImode) <=
2);
643 ;; Return
1 if the operand is a constant that can loaded with a XXSPLTIB
644 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
646 (define_predicate "xxspltib_constant_split"
647 (match_code "const_vector,vec_duplicate,const_int")
652 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
655 return num_insns >
1;
659 ;; Return
1 if the operand is constant that can loaded directly with a XXSPLTIB
662 (define_predicate "xxspltib_constant_nosplit"
663 (match_code "const_vector,vec_duplicate,const_int")
668 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
671 return num_insns ==
1;
674 ;; Return
1 if the operand is a CONST_VECTOR and can be loaded into a
675 ;; vector register without using memory.
676 (define_predicate "easy_vector_constant"
677 (match_code "const_vector")
679 /* As the paired vectors are actually FPRs it seems that there is
680 no easy way to load a CONST_VECTOR without using memory. */
681 if (TARGET_PAIRED_FLOAT)
684 /* Because IEEE
128-bit floating point is considered a vector type
685 in order to pass it in VSX registers, it might use this function
686 instead of easy_fp_constant. */
687 if (FLOAT128_VECTOR_P (mode))
688 return easy_fp_constant (op, mode);
690 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
695 if (zero_constant (op, mode) || all_ones_constant (op, mode))
699 && xxspltib_constant_p (op, mode, &num_insns, &value))
702 return easy_altivec_constant (op, mode);
708 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
709 (define_predicate "easy_vector_constant_add_self"
710 (and (match_code "const_vector")
711 (and (match_test "TARGET_ALTIVEC")
712 (match_test "easy_altivec_constant (op, mode)")))
716 if (mode == V2DImode || mode == V2DFmode)
718 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
719 val = const_vector_elt_as_int (op, elt);
720 val = ((val &
0xff) ^
0x80) -
0x80;
721 return EASY_VECTOR_15_ADD_SELF (val);
724 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
725 (define_predicate "easy_vector_constant_msb"
726 (and (match_code "const_vector")
727 (and (match_test "TARGET_ALTIVEC")
728 (match_test "easy_altivec_constant (op, mode)")))
732 if (mode == V2DImode || mode == V2DFmode)
734 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
735 val = const_vector_elt_as_int (op, elt);
736 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
739 ;; Return true if this is an easy altivec constant that we form
741 (define_predicate "easy_vector_constant_vsldoi"
742 (and (match_code "const_vector")
743 (and (match_test "TARGET_ALTIVEC")
744 (and (match_test "easy_altivec_constant (op, mode)")
745 (match_test "vspltis_shifted (op) !=
0")))))
747 ;; Return
1 if operand is constant zero (scalars and vectors).
748 (define_predicate "zero_constant"
749 (and (match_code "const_int,const_double,const_wide_int,const_vector")
750 (match_test "op == CONST0_RTX (mode)")))
752 ;; Return
1 if operand is constant -
1 (scalars and vectors).
753 (define_predicate "all_ones_constant"
754 (and (match_code "const_int,const_double,const_wide_int,const_vector")
755 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
757 ;; Return
1 if operand is a vector int register or is either a vector constant
758 ;; of all
0 bits of a vector constant of all
1 bits.
759 (define_predicate "vector_int_reg_or_same_bit"
760 (match_code "reg,subreg,const_vector")
762 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
765 else if (REG_P (op) || SUBREG_P (op))
766 return vint_operand (op, mode);
769 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
772 ;; Return
1 if operand is
0.0.
773 (define_predicate "zero_fp_constant"
774 (and (match_code "const_double")
775 (match_test "SCALAR_FLOAT_MODE_P (mode)
776 && op == CONST0_RTX (mode)")))
778 ;; Return
1 if the operand is in volatile memory. Note that during the
779 ;; RTL generation phase, memory_operand does not return TRUE for volatile
780 ;; memory references. So this function allows us to recognize volatile
781 ;; references where it's safe.
782 (define_predicate "volatile_mem_operand"
783 (and (and (match_code "mem")
784 (match_test "MEM_VOLATILE_P (op)"))
785 (if_then_else (match_test "reload_completed")
786 (match_operand
0 "memory_operand")
787 (if_then_else (match_test "reload_in_progress")
788 (match_test "strict_memory_address_p (mode, XEXP (op,
0))")
789 (match_test "memory_address_p (mode, XEXP (op,
0))")))))
791 ;; Return
1 if the operand is an offsettable memory operand.
792 (define_predicate "offsettable_mem_operand"
793 (and (match_operand
0 "memory_operand")
794 (match_test "offsettable_nonstrict_memref_p (op)")))
796 ;; Return
1 if the operand is a simple offsettable memory operand
797 ;; that does not include pre-increment, post-increment, etc.
798 (define_predicate "simple_offsettable_mem_operand"
799 (match_operand
0 "offsettable_mem_operand")
801 rtx addr = XEXP (op,
0);
803 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
806 if (!CONSTANT_P (XEXP (addr,
1)))
809 return base_reg_operand (XEXP (addr,
0), Pmode);
812 ;; Return
1 if the operand is suitable for load/store quad memory.
813 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
814 (define_predicate "quad_memory_operand"
817 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
820 if (GET_MODE_SIZE (mode) !=
16 || !MEM_P (op) || MEM_ALIGN (op) <
128)
823 return quad_address_p (XEXP (op,
0), mode, false);
826 ;; Return
1 if the operand is suitable for load/store to vector registers with
827 ;; d-form addressing (register+offset), which was added in ISA
3.0.
828 ;; Unlike quad_memory_operand, we do not have to check for alignment.
829 (define_predicate "vsx_quad_dform_memory_operand"
832 if (!TARGET_P9_DFORM_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) !=
16)
835 return quad_address_p (XEXP (op,
0), mode, false);
838 ;; Return
1 if the operand is an indexed or indirect memory operand.
839 (define_predicate "indexed_or_indirect_operand"
843 if (VECTOR_MEM_ALTIVEC_P (mode)
844 && GET_CODE (op) == AND
845 && GET_CODE (XEXP (op,
1)) == CONST_INT
846 && INTVAL (XEXP (op,
1)) == -
16)
849 return indexed_or_indirect_address (op, mode);
852 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
853 ;; moves are supported.
854 (define_predicate "reg_or_indexed_operand"
855 (match_code "mem,reg,subreg")
858 return indexed_or_indirect_operand (op, mode);
859 else if (TARGET_DIRECT_MOVE)
860 return register_operand (op, mode);
865 ;; Return
1 if the operand is an indexed or indirect memory operand with an
866 ;; AND -
16 in it, used to recognize when we need to switch to Altivec loads
867 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
868 ;; while VSX uses the full address and traps)
869 (define_predicate "altivec_indexed_or_indirect_operand"
873 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
874 && GET_CODE (op) == AND
875 && GET_CODE (XEXP (op,
1)) == CONST_INT
876 && INTVAL (XEXP (op,
1)) == -
16)
877 return indexed_or_indirect_address (XEXP (op,
0), mode);
882 ;; Return
1 if the operand is an indexed or indirect address.
883 (define_special_predicate "indexed_or_indirect_address"
884 (and (match_test "REG_P (op)
885 || (GET_CODE (op) == PLUS
886 /* Omit testing REG_P (XEXP (op,
0)). */
887 && REG_P (XEXP (op,
1)))")
888 (match_operand
0 "address_operand")))
890 ;; Return
1 if the operand is an index-form address.
891 (define_special_predicate "indexed_address"
892 (match_test "(GET_CODE (op) == PLUS
893 && REG_P (XEXP (op,
0))
894 && REG_P (XEXP (op,
1)))"))
896 ;; Return
1 if the operand is a MEM with an update-form address. This may
897 ;; also include update-indexed form.
898 (define_special_predicate "update_address_mem"
899 (match_test "(MEM_P (op)
900 && (GET_CODE (XEXP (op,
0)) == PRE_INC
901 || GET_CODE (XEXP (op,
0)) == PRE_DEC
902 || GET_CODE (XEXP (op,
0)) == PRE_MODIFY))"))
904 ;; Return
1 if the operand is a MEM with an indexed-form address.
905 (define_special_predicate "indexed_address_mem"
906 (match_test "(MEM_P (op)
907 && (indexed_address (XEXP (op,
0), mode)
908 || (GET_CODE (XEXP (op,
0)) == PRE_MODIFY
909 && indexed_address (XEXP (XEXP (op,
0),
1), mode))))"))
911 ;; Return
1 if the operand is either a non-special register or can be used
912 ;; as the operand of a
`mode' add insn.
913 (define_predicate "add_operand"
914 (if_then_else (match_code "const_int")
915 (match_test "satisfies_constraint_I (op)
916 || satisfies_constraint_L (op)")
917 (match_operand 0 "gpc_reg_operand")))
919 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
920 (define_predicate "adde_operand"
921 (if_then_else (match_code "const_int")
922 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
923 (match_operand 0 "gpc_reg_operand")))
925 ;; Return 1 if OP is a constant but not a valid add_operand.
926 (define_predicate "non_add_cint_operand"
927 (and (match_code "const_int")
928 (match_test "!satisfies_constraint_I (op)
929 && !satisfies_constraint_L (op)")))
931 ;; Return 1 if the operand is a constant that can be used as the operand
933 (define_predicate "logical_const_operand"
934 (match_code "const_int")
938 opl = INTVAL (op) & GET_MODE_MASK (mode);
940 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
941 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
944 ;; Return 1 if the operand is a non-special register or a constant that
945 ;; can be used as the operand of an OR or XOR.
946 (define_predicate "logical_operand"
947 (ior (match_operand 0 "gpc_reg_operand")
948 (match_operand 0 "logical_const_operand")))
950 ;; Return 1 if op is a constant that is not a logical operand, but could
951 ;; be split into one.
952 (define_predicate "non_logical_cint_operand"
953 (and (match_code "const_int,const_wide_int")
954 (and (not (match_operand 0 "logical_operand"))
955 (match_operand 0 "reg_or_logical_cint_operand"))))
957 ;; Return 1 if the operand is either a non-special register or a
958 ;; constant that can be used as the operand of a logical AND.
959 (define_predicate "and_operand"
960 (ior (and (match_code "const_int")
961 (match_test "rs6000_is_valid_and_mask (op, mode)"))
962 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
963 (match_operand 0 "gpc_reg_operand")
964 (match_operand 0 "logical_operand"))))
966 ;; Return 1 if the operand is either a logical operand or a short cint operand.
967 (define_predicate "scc_eq_operand"
968 (ior (match_operand 0 "logical_operand")
969 (match_operand 0 "short_cint_operand")))
971 ;; Return 1 if the operand is a general non-special register or memory operand.
972 (define_predicate "reg_or_mem_operand"
973 (ior (match_operand 0 "memory_operand")
974 (and (match_code "mem")
975 (match_test "macho_lo_sum_memory_operand (op, mode)"))
976 (match_operand 0 "volatile_mem_operand")
977 (match_operand 0 "gpc_reg_operand")))
979 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
980 (define_predicate "zero_reg_mem_operand"
981 (ior (and (match_test "TARGET_VSX")
982 (match_operand 0 "zero_fp_constant"))
983 (match_operand 0 "reg_or_mem_operand")))
985 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
986 ;; data types inside of a vector that scalar instructions operate on
987 (define_predicate "vsx_scalar_64bit"
988 (match_code "const_int")
990 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
993 ;; Return 1 if the operand is a general register or memory operand without
994 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
996 (define_predicate "lwa_operand"
997 (match_code "reg,subreg,mem")
999 rtx inner, addr, offset;
1002 if (reload_completed && GET_CODE (inner) == SUBREG)
1003 inner = SUBREG_REG (inner);
1005 if (gpc_reg_operand (inner, mode))
1007 if (!memory_operand (inner, mode))
1010 addr = XEXP (inner, 0);
1011 if (GET_CODE (addr) == PRE_INC
1012 || GET_CODE (addr) == PRE_DEC
1013 || (GET_CODE (addr) == PRE_MODIFY
1014 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1016 if (GET_CODE (addr) == LO_SUM
1017 && GET_CODE (XEXP (addr, 0)) == REG
1018 && GET_CODE (XEXP (addr, 1)) == CONST)
1019 addr = XEXP (XEXP (addr, 1), 0);
1020 if (GET_CODE (addr) != PLUS)
1022 offset = XEXP (addr, 1);
1023 if (GET_CODE (offset) != CONST_INT)
1025 return INTVAL (offset) % 4 == 0;
1028 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1029 (define_predicate "symbol_ref_operand"
1030 (and (match_code "symbol_ref")
1031 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1032 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1034 ;; Return 1 if op is an operand that can be loaded via the GOT.
1035 ;; or non-special register register field no cr0
1036 (define_predicate "got_operand"
1037 (match_code "symbol_ref,const,label_ref"))
1039 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1040 ;; excluding labels involving addition.
1041 (define_predicate "got_no_const_operand"
1042 (match_code "symbol_ref,label_ref"))
1044 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1045 (define_predicate "rs6000_tls_symbol_ref"
1046 (and (match_code "symbol_ref")
1047 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1049 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1050 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1051 (define_predicate "call_operand"
1052 (if_then_else (match_code "reg")
1053 (match_test "REGNO (op) == LR_REGNO
1054 || REGNO (op) == CTR_REGNO
1055 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
1056 (match_code "symbol_ref")))
1058 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1060 (define_predicate "current_file_function_operand"
1061 (and (match_code "symbol_ref")
1062 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1063 && (SYMBOL_REF_LOCAL_P (op)
1064 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1065 && !decl_replaceable_p (current_function_decl)))
1066 && !((DEFAULT_ABI == ABI_AIX
1067 || DEFAULT_ABI == ABI_ELFv2)
1068 && (SYMBOL_REF_EXTERNAL_P (op)
1069 || SYMBOL_REF_WEAK (op)))")))
1071 ;; Return 1 if this operand is a valid input for a move insn.
1072 (define_predicate "input_operand"
1073 (match_code "symbol_ref,const,reg,subreg,mem,
1074 const_double,const_wide_int,const_vector,const_int")
1076 /* Memory is always valid. */
1077 if (memory_operand (op, mode))
1080 /* For floating-point, easy constants are valid. */
1081 if (SCALAR_FLOAT_MODE_P (mode)
1082 && easy_fp_constant (op, mode))
1085 /* Allow any integer constant. */
1086 if (GET_MODE_CLASS (mode) == MODE_INT
1087 && CONST_SCALAR_INT_P (op))
1090 /* Allow easy vector constants. */
1091 if (GET_CODE (op) == CONST_VECTOR
1092 && easy_vector_constant (op, mode))
1095 /* For floating-point or multi-word mode, the only remaining valid type
1097 if (SCALAR_FLOAT_MODE_P (mode)
1098 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1099 return register_operand (op, mode);
1101 /* We don't allow moving the carry bit around. */
1102 if (ca_operand (op, mode))
1105 /* The only cases left are integral modes one word or smaller (we
1106 do not get called for MODE_CC values). These can be in any
1108 if (register_operand (op, mode))
1111 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1113 if (DEFAULT_ABI == ABI_V4
1114 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
1115 && small_data_operand (op, Pmode))
1121 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1122 (define_predicate "splat_input_operand"
1123 (match_code "reg,subreg,mem")
1129 else if (mode == DImode)
1131 else if (mode == SImode && TARGET_P9_VECTOR)
1133 else if (mode == SFmode && TARGET_P9_VECTOR)
1140 rtx addr = XEXP (op, 0);
1142 if (! volatile_ok && MEM_VOLATILE_P (op))
1145 if (reload_in_progress || lra_in_progress || reload_completed)
1146 return indexed_or_indirect_address (addr, vmode);
1148 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1150 return gpc_reg_operand (op, mode);
1153 ;; Return true if OP is a non-immediate operand.
1154 (define_predicate "rs6000_nonimmediate_operand"
1155 (match_code "reg,subreg,mem")
1157 return nonimmediate_operand (op, mode);
1160 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1161 (define_predicate "rotate_mask_operator"
1162 (match_code "rotate,ashift,lshiftrt"))
1164 ;; Return true if operand is boolean operator.
1165 (define_predicate "boolean_operator"
1166 (match_code "and,ior,xor"))
1168 ;; Return true if operand is OR-form of boolean operator.
1169 (define_predicate "boolean_or_operator"
1170 (match_code "ior,xor"))
1172 ;; Return true if operand is an equality operator.
1173 (define_special_predicate "equality_operator"
1174 (match_code "eq,ne"))
1176 ;; Return 1 if OP is a comparison operation that is valid for a branch
1177 ;; instruction. We check the opcode against the mode of the CC value.
1178 ;; validate_condition_mode is an assertion.
1179 (define_predicate "branch_comparison_operator"
1180 (and (match_operand 0 "comparison_operator")
1181 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1182 (match_test "validate_condition_mode (GET_CODE (op),
1183 GET_MODE (XEXP (op, 0))),
1186 ;; Return 1 if OP is an unsigned comparison operator.
1187 (define_predicate "unsigned_comparison_operator"
1188 (match_code "ltu,gtu,leu,geu"))
1190 ;; Return 1 if OP is a signed comparison operator.
1191 (define_predicate "signed_comparison_operator"
1192 (match_code "lt,gt,le,ge"))
1194 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1195 ;; it must be a positive comparison.
1196 (define_predicate "scc_comparison_operator"
1197 (and (match_operand 0 "branch_comparison_operator")
1198 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1200 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1202 (define_predicate "scc_rev_comparison_operator"
1203 (and (match_operand 0 "branch_comparison_operator")
1204 (match_code "ne,le,ge,leu,geu,ordered")))
1206 ;; Return 1 if OP is a comparison operator suitable for floating point
1207 ;; vector/scalar comparisons that generate a -1/0 mask.
1208 (define_predicate "fpmask_comparison_operator"
1209 (match_code "eq,gt,ge"))
1211 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1212 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1213 ;; fpmask_comparison_operator).
1214 (define_predicate "invert_fpmask_comparison_operator"
1215 (match_code "ne,unlt,unle"))
1217 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1218 ;; comparisons that generate a -1/0 mask.
1219 (define_predicate "vecint_comparison_operator"
1220 (match_code "eq,gt,gtu"))
1222 ;; Return 1 if OP is a comparison operation that is valid for a branch
1223 ;; insn, which is true if the corresponding bit in the CC register is set.
1224 (define_predicate "branch_positive_comparison_operator"
1225 (and (match_operand 0 "branch_comparison_operator")
1226 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1228 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
1229 (define_predicate "load_multiple_operation"
1230 (match_code "parallel")
1232 int count = XVECLEN (op, 0);
1233 unsigned int dest_regno;
1237 /* Perform a quick check so we don't blow up below. */
1239 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1240 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1241 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1244 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1245 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1247 for (i = 1; i < count; i++)
1249 rtx elt = XVECEXP (op, 0, i);
1251 if (GET_CODE (elt) != SET
1252 || GET_CODE (SET_DEST (elt)) != REG
1253 || GET_MODE (SET_DEST (elt)) != SImode
1254 || REGNO (SET_DEST (elt)) != dest_regno + i
1255 || GET_CODE (SET_SRC (elt)) != MEM
1256 || GET_MODE (SET_SRC (elt)) != SImode
1257 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1258 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1259 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1260 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1267 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1268 ;; The second vector element is a CLOBBER.
1269 (define_predicate "store_multiple_operation"
1270 (match_code "parallel")
1272 int count = XVECLEN (op, 0) - 1;
1273 unsigned int src_regno;
1277 /* Perform a quick check so we don't blow up below. */
1279 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1280 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1281 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1284 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1285 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1287 for (i = 1; i < count; i++)
1289 rtx elt = XVECEXP (op, 0, i + 1);
1291 if (GET_CODE (elt) != SET
1292 || GET_CODE (SET_SRC (elt)) != REG
1293 || GET_MODE (SET_SRC (elt)) != SImode
1294 || REGNO (SET_SRC (elt)) != src_regno + i
1295 || GET_CODE (SET_DEST (elt)) != MEM
1296 || GET_MODE (SET_DEST (elt)) != SImode
1297 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1298 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1299 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1300 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1307 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1309 (define_predicate "save_world_operation"
1310 (match_code "parallel")
1315 int count = XVECLEN (op, 0);
1321 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1322 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1325 for (i=1; i <= 18; i++)
1327 elt = XVECEXP (op, 0, index++);
1328 if (GET_CODE (elt) != SET
1329 || GET_CODE (SET_DEST (elt)) != MEM
1330 || ! memory_operand (SET_DEST (elt), DFmode)
1331 || GET_CODE (SET_SRC (elt)) != REG
1332 || GET_MODE (SET_SRC (elt)) != DFmode)
1336 for (i=1; i <= 12; i++)
1338 elt = XVECEXP (op, 0, index++);
1339 if (GET_CODE (elt) != SET
1340 || GET_CODE (SET_DEST (elt)) != MEM
1341 || GET_CODE (SET_SRC (elt)) != REG
1342 || GET_MODE (SET_SRC (elt)) != V4SImode)
1346 for (i=1; i <= 19; i++)
1348 elt = XVECEXP (op, 0, index++);
1349 if (GET_CODE (elt) != SET
1350 || GET_CODE (SET_DEST (elt)) != MEM
1351 || ! memory_operand (SET_DEST (elt), Pmode)
1352 || GET_CODE (SET_SRC (elt)) != REG
1353 || GET_MODE (SET_SRC (elt)) != Pmode)
1357 elt = XVECEXP (op, 0, index++);
1358 if (GET_CODE (elt) != SET
1359 || GET_CODE (SET_DEST (elt)) != MEM
1360 || ! memory_operand (SET_DEST (elt), Pmode)
1361 || GET_CODE (SET_SRC (elt)) != REG
1362 || REGNO (SET_SRC (elt)) != CR2_REGNO
1363 || GET_MODE (SET_SRC (elt)) != Pmode)
1366 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1367 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1372 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1374 (define_predicate "restore_world_operation"
1375 (match_code "parallel")
1380 int count = XVECLEN (op, 0);
1386 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1387 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1388 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1389 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1392 elt = XVECEXP (op, 0, index++);
1393 if (GET_CODE (elt) != SET
1394 || GET_CODE (SET_SRC (elt)) != MEM
1395 || ! memory_operand (SET_SRC (elt), Pmode)
1396 || GET_CODE (SET_DEST (elt)) != REG
1397 || REGNO (SET_DEST (elt)) != CR2_REGNO
1398 || GET_MODE (SET_DEST (elt)) != Pmode)
1401 for (i=1; i <= 19; i++)
1403 elt = XVECEXP (op, 0, index++);
1404 if (GET_CODE (elt) != SET
1405 || GET_CODE (SET_SRC (elt)) != MEM
1406 || ! memory_operand (SET_SRC (elt), Pmode)
1407 || GET_CODE (SET_DEST (elt)) != REG
1408 || GET_MODE (SET_DEST (elt)) != Pmode)
1412 for (i=1; i <= 12; i++)
1414 elt = XVECEXP (op, 0, index++);
1415 if (GET_CODE (elt) != SET
1416 || GET_CODE (SET_SRC (elt)) != MEM
1417 || GET_CODE (SET_DEST (elt)) != REG
1418 || GET_MODE (SET_DEST (elt)) != V4SImode)
1422 for (i=1; i <= 18; i++)
1424 elt = XVECEXP (op, 0, index++);
1425 if (GET_CODE (elt) != SET
1426 || GET_CODE (SET_SRC (elt)) != MEM
1427 || ! memory_operand (SET_SRC (elt), DFmode)
1428 || GET_CODE (SET_DEST (elt)) != REG
1429 || GET_MODE (SET_DEST (elt)) != DFmode)
1433 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1434 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1435 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1436 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1437 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1442 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1443 (define_predicate "vrsave_operation"
1444 (match_code "parallel")
1446 int count = XVECLEN (op, 0);
1447 unsigned int dest_regno, src_regno;
1451 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1452 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1453 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1454 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1457 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1458 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1460 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1463 for (i = 1; i < count; i++)
1465 rtx elt = XVECEXP (op, 0, i);
1467 if (GET_CODE (elt) != CLOBBER
1468 && GET_CODE (elt) != SET)
1475 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1476 (define_predicate "mfcr_operation"
1477 (match_code "parallel")
1479 int count = XVECLEN (op, 0);
1482 /* Perform a quick check so we don't blow up below. */
1484 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1485 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1486 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1489 for (i = 0; i < count; i++)
1491 rtx exp = XVECEXP (op, 0, i);
1496 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1498 if (GET_CODE (src_reg) != REG
1499 || GET_MODE (src_reg) != CCmode
1500 || ! CR_REGNO_P (REGNO (src_reg)))
1503 if (GET_CODE (exp) != SET
1504 || GET_CODE (SET_DEST (exp)) != REG
1505 || GET_MODE (SET_DEST (exp)) != SImode
1506 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1508 unspec = SET_SRC (exp);
1509 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1511 if (GET_CODE (unspec) != UNSPEC
1512 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1513 || XVECLEN (unspec, 0) != 2
1514 || XVECEXP (unspec, 0, 0) != src_reg
1515 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1516 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1522 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1523 (define_predicate "mtcrf_operation"
1524 (match_code "parallel")
1526 int count = XVECLEN (op, 0);
1530 /* Perform a quick check so we don't blow up below. */
1532 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1533 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1534 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1536 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1538 if (GET_CODE (src_reg) != REG
1539 || GET_MODE (src_reg) != SImode
1540 || ! INT_REGNO_P (REGNO (src_reg)))
1543 for (i = 0; i < count; i++)
1545 rtx exp = XVECEXP (op, 0, i);
1549 if (GET_CODE (exp) != SET
1550 || GET_CODE (SET_DEST (exp)) != REG
1551 || GET_MODE (SET_DEST (exp)) != CCmode
1552 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1554 unspec = SET_SRC (exp);
1555 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1557 if (GET_CODE (unspec) != UNSPEC
1558 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1559 || XVECLEN (unspec, 0) != 2
1560 || XVECEXP (unspec, 0, 0) != src_reg
1561 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1562 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1568 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1569 (define_predicate "crsave_operation"
1570 (match_code "parallel")
1572 int count = XVECLEN (op, 0);
1575 for (i = 1; i < count; i++)
1577 rtx exp = XVECEXP (op, 0, i);
1579 if (GET_CODE (exp) != USE
1580 || GET_CODE (XEXP (exp, 0)) != REG
1581 || GET_MODE (XEXP (exp, 0)) != CCmode
1582 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1588 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1589 (define_predicate "lmw_operation"
1590 (match_code "parallel")
1592 int count = XVECLEN (op, 0);
1593 unsigned int dest_regno;
1595 unsigned int base_regno;
1596 HOST_WIDE_INT offset;
1599 /* Perform a quick check so we don't blow up below. */
1601 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1602 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1603 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1606 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1607 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1610 || count != 32 - (int) dest_regno)
1613 if (legitimate_indirect_address_p (src_addr, 0))
1616 base_regno = REGNO (src_addr);
1617 if (base_regno == 0)
1620 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1622 offset = INTVAL (XEXP (src_addr, 1));
1623 base_regno = REGNO (XEXP (src_addr, 0));
1628 for (i = 0; i < count; i++)
1630 rtx elt = XVECEXP (op, 0, i);
1633 HOST_WIDE_INT newoffset;
1635 if (GET_CODE (elt) != SET
1636 || GET_CODE (SET_DEST (elt)) != REG
1637 || GET_MODE (SET_DEST (elt)) != SImode
1638 || REGNO (SET_DEST (elt)) != dest_regno + i
1639 || GET_CODE (SET_SRC (elt)) != MEM
1640 || GET_MODE (SET_SRC (elt)) != SImode)
1642 newaddr = XEXP (SET_SRC (elt), 0);
1643 if (legitimate_indirect_address_p (newaddr, 0))
1648 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1650 addr_reg = XEXP (newaddr, 0);
1651 newoffset = INTVAL (XEXP (newaddr, 1));
1655 if (REGNO (addr_reg) != base_regno
1656 || newoffset != offset + 4 * i)
1663 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1664 (define_predicate "stmw_operation"
1665 (match_code "parallel")
1667 int count = XVECLEN (op, 0);
1668 unsigned int src_regno;
1670 unsigned int base_regno;
1671 HOST_WIDE_INT offset;
1674 /* Perform a quick check so we don't blow up below. */
1676 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1677 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1678 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1681 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1682 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1685 || count != 32 - (int) src_regno)
1688 if (legitimate_indirect_address_p (dest_addr, 0))
1691 base_regno = REGNO (dest_addr);
1692 if (base_regno == 0)
1695 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1697 offset = INTVAL (XEXP (dest_addr, 1));
1698 base_regno = REGNO (XEXP (dest_addr, 0));
1703 for (i = 0; i < count; i++)
1705 rtx elt = XVECEXP (op, 0, i);
1708 HOST_WIDE_INT newoffset;
1710 if (GET_CODE (elt) != SET
1711 || GET_CODE (SET_SRC (elt)) != REG
1712 || GET_MODE (SET_SRC (elt)) != SImode
1713 || REGNO (SET_SRC (elt)) != src_regno + i
1714 || GET_CODE (SET_DEST (elt)) != MEM
1715 || GET_MODE (SET_DEST (elt)) != SImode)
1717 newaddr = XEXP (SET_DEST (elt), 0);
1718 if (legitimate_indirect_address_p (newaddr, 0))
1723 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1725 addr_reg = XEXP (newaddr, 0);
1726 newoffset = INTVAL (XEXP (newaddr, 1));
1730 if (REGNO (addr_reg) != base_regno
1731 || newoffset != offset + 4 * i)
1738 ;; Return 1 if OP is a stack tie operand.
1739 (define_predicate "tie_operand"
1740 (match_code "parallel")
1742 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1743 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 0)) == MEM
1744 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1745 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1748 ;; Match a small code model toc reference (or medium and large
1749 ;; model toc references before reload).
1750 (define_predicate "small_toc_ref"
1751 (match_code "unspec,plus")
1753 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1756 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1759 ;; Match the TOC memory operand that can be fused with an addis instruction.
1760 ;; This is used in matching a potential fused address before register
1762 (define_predicate "toc_fusion_mem_raw"
1765 if (!TARGET_TOC_FUSION_INT || !can_create_pseudo_p ())
1768 return small_toc_ref (XEXP (op, 0), Pmode);
1771 ;; Match the memory operand that has been fused with an addis instruction and
1772 ;; wrapped inside of an (unspec [...] UNSPEC_FUSION_ADDIS) wrapper.
1773 (define_predicate "toc_fusion_mem_wrapped"
1778 if (!TARGET_TOC_FUSION_INT)
1784 addr = XEXP (op, 0);
1785 return (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS);
1788 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1789 ;; GPR registers on power8.
1790 (define_predicate "fusion_gpr_addis"
1791 (match_code "const_int,high,plus")
1793 HOST_WIDE_INT value;
1796 if (GET_CODE (op) == HIGH)
1799 if (CONST_INT_P (op))
1802 else if (GET_CODE (op) == PLUS
1803 && base_reg_operand (XEXP (op, 0), Pmode)
1804 && CONST_INT_P (XEXP (op, 1)))
1805 int_const = XEXP (op, 1);
1810 value = INTVAL (int_const);
1811 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1814 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1817 /* Power8 currently will only do the fusion if the top 11 bits of the addis
1818 value are all 1's or 0's. Ignore this restriction if we are testing
1820 if (TARGET_P9_FUSION)
1823 return (IN_RANGE (value >> 16, -32, 31));
1826 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1827 ;; and loads to GPR registers on power8.
1828 (define_predicate "fusion_gpr_mem_load"
1829 (match_code "mem,sign_extend,zero_extend")
1831 rtx addr, base, offset;
1833 /* Handle sign/zero extend. */
1834 if (GET_CODE (op) == ZERO_EXTEND
1835 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1838 mode = GET_MODE (op);
1852 if (!TARGET_POWERPC64)
1860 addr = XEXP (op, 0);
1861 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1864 base = XEXP (addr, 0);
1865 if (!base_reg_operand (base, GET_MODE (base)))
1868 offset = XEXP (addr, 1);
1870 if (GET_CODE (addr) == PLUS)
1871 return satisfies_constraint_I (offset);
1873 else if (GET_CODE (addr) == LO_SUM)
1875 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1876 return small_toc_ref (offset, GET_MODE (offset));
1878 else if (TARGET_ELF && !TARGET_POWERPC64)
1879 return CONSTANT_P (offset);
1885 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1886 ;; memory field with both the addis and the memory offset. Sign extension
1887 ;; is not handled here, since lha and lwa are not fused.
1888 ;; With P9 fusion, also match a fpr/vector load and float_extend
1889 (define_predicate "fusion_addis_mem_combo_load"
1890 (match_code "mem,zero_extend,float_extend")
1892 rtx addr, base, offset;
1894 /* Handle zero/float extend. */
1895 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
1898 mode = GET_MODE (op);
1911 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1912 separate instructions. */
1914 if (!TARGET_POWERPC64)
1918 /* ISA 2.08/power8 only had fusion of GPR loads. */
1920 if (!TARGET_P9_FUSION)
1924 /* ISA 2.08/power8 only had fusion of GPR loads. Do not allow 64-bit
1925 DFmode in 32-bit if -msoft-float since it splits into two separate
1928 if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION)
1936 addr = XEXP (op, 0);
1937 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1940 base = XEXP (addr, 0);
1941 if (!fusion_gpr_addis (base, GET_MODE (base)))
1944 offset = XEXP (addr, 1);
1945 if (GET_CODE (addr) == PLUS)
1946 return satisfies_constraint_I (offset);
1948 else if (GET_CODE (addr) == LO_SUM)
1950 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1951 return small_toc_ref (offset, GET_MODE (offset));
1953 else if (TARGET_ELF && !TARGET_POWERPC64)
1954 return CONSTANT_P (offset);
1960 ;; Like fusion_addis_mem_combo_load, but for stores
1961 (define_predicate "fusion_addis_mem_combo_store"
1964 rtx addr, base, offset;
1966 if (!MEM_P (op) || !TARGET_P9_FUSION)
1977 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1978 separate instructions. */
1980 if (!TARGET_POWERPC64)
1984 /* Do not allow 64-bit DFmode in 32-bit if -msoft-float since it splits
1985 into two separate instructions. Do allow fusion if we have hardware
1988 if (!TARGET_POWERPC64 && !TARGET_DF_FPR)
1996 addr = XEXP (op, 0);
1997 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
2000 base = XEXP (addr, 0);
2001 if (!fusion_gpr_addis (base, GET_MODE (base)))
2004 offset = XEXP (addr, 1);
2005 if (GET_CODE (addr) == PLUS)
2006 return satisfies_constraint_I (offset);
2008 else if (GET_CODE (addr) == LO_SUM)
2010 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
2011 return small_toc_ref (offset, GET_MODE (offset));
2013 else if (TARGET_ELF && !TARGET_POWERPC64)
2014 return CONSTANT_P (offset);
2020 ;; Return true if the operand is a float_extend or zero extend of an
2021 ;; offsettable memory operand suitable for use in fusion
2022 (define_predicate "fusion_offsettable_mem_operand"
2023 (match_code "mem,zero_extend,float_extend")
2025 if (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == FLOAT_EXTEND)
2028 mode = GET_MODE (op);
2031 if (!memory_operand (op, mode))
2034 return offsettable_nonstrict_memref_p (op);