1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C)
2005-
2019 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version
3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return
1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return
1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return
1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return
1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have
64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return
1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand
0 "register_operand")
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (!HARD_REGISTER_P (op))
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return
1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand
0 "register_operand")
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (!HARD_REGISTER_P (op))
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand
0 "register_operand")
111 op = SUBREG_REG (op);
116 if (!HARD_REGISTER_P (op))
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return
1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand
0 "register_operand")
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (!HARD_REGISTER_P (op))
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return
1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand
0 "register_operand")
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (!HARD_REGISTER_P (op))
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return
1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand
0 "register_operand")
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (!HARD_REGISTER_P (op))
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return
1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand
0 "register_operand")
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return
1 if operand is constant zero (scalars and vectors).
203 (define_predicate "zero_constant"
204 (and (match_code "const_int,const_double,const_wide_int,const_vector")
205 (match_test "op == CONST0_RTX (mode)")))
207 ;; Return
1 if operand is constant -
1 (scalars and vectors).
208 (define_predicate "all_ones_constant"
209 (and (match_code "const_int,const_double,const_wide_int,const_vector")
210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
212 ;; Return
1 if op is a signed
5-bit constant integer.
213 (define_predicate "s5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >= -
16 && INTVAL (op) <=
15")))
217 ;; Return
1 if op is a unsigned
3-bit constant integer.
218 (define_predicate "u3bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
7")))
222 ;; Return
1 if op is a unsigned
5-bit constant integer.
223 (define_predicate "u5bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
31")))
227 ;; Return
1 if op is a unsigned
6-bit constant integer.
228 (define_predicate "u6bit_cint_operand"
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
63")))
232 ;; Return
1 if op is an unsigned
7-bit constant integer.
233 (define_predicate "u7bit_cint_operand"
234 (and (match_code "const_int")
235 (match_test "IN_RANGE (INTVAL (op),
0,
127)")))
237 ;; Return
1 if op is a signed
8-bit constant integer.
238 ;; Integer multiplication complete more quickly
239 (define_predicate "s8bit_cint_operand"
240 (and (match_code "const_int")
241 (match_test "INTVAL (op) >= -
128 && INTVAL (op) <=
127")))
243 ;; Return
1 if op is a unsigned
10-bit constant integer.
244 (define_predicate "u10bit_cint_operand"
245 (and (match_code "const_int")
246 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1023")))
248 ;; Return
1 if op is a constant integer that can fit in a D field.
249 (define_predicate "short_cint_operand"
250 (and (match_code "const_int")
251 (match_test "satisfies_constraint_I (op)")))
253 ;; Return
1 if op is a constant integer that can fit in an unsigned D field.
254 (define_predicate "u_short_cint_operand"
255 (and (match_code "const_int")
256 (match_test "satisfies_constraint_K (op)")))
258 ;; Return
1 if op is a constant integer that is a signed
16-bit constant
259 ;; shifted left
16 bits
260 (define_predicate "upper16_cint_operand"
261 (and (match_code "const_int")
262 (match_test "satisfies_constraint_L (op)")))
264 ;; Return
1 if op is a constant integer that cannot fit in a signed D field.
265 (define_predicate "non_short_cint_operand"
266 (and (match_code "const_int")
267 (match_test "(unsigned HOST_WIDE_INT)
268 (INTVAL (op) +
0x8000) >=
0x10000")))
270 ;; Return
1 if op is a positive constant integer that is an exact power of
2.
271 (define_predicate "exact_log2_cint_operand"
272 (and (match_code "const_int")
273 (match_test "INTVAL (op) >
0 && exact_log2 (INTVAL (op)) >=
0")))
275 ;; Match op =
0 or op =
1.
276 (define_predicate "const_0_to_1_operand"
277 (and (match_code "const_int")
278 (match_test "IN_RANGE (INTVAL (op),
0,
1)")))
281 (define_predicate "const_0_to_3_operand"
282 (and (match_code "const_int")
283 (match_test "IN_RANGE (INTVAL (op),
0,
3)")))
285 ;; Match op =
2 or op =
3.
286 (define_predicate "const_2_to_3_operand"
287 (and (match_code "const_int")
288 (match_test "IN_RANGE (INTVAL (op),
2,
3)")))
291 (define_predicate "const_0_to_7_operand"
292 (and (match_code "const_int")
293 (match_test "IN_RANGE (INTVAL (op),
0,
7)")))
296 (define_predicate "const_0_to_12_operand"
297 (and (match_code "const_int")
298 (match_test "IN_RANGE (INTVAL (op),
0,
12)")))
301 (define_predicate "const_0_to_15_operand"
302 (and (match_code "const_int")
303 (match_test "IN_RANGE (INTVAL (op),
0,
15)")))
305 ;; Return
1 if op is a
34-bit constant integer.
306 (define_predicate "cint34_operand"
307 (match_code "const_int")
309 if (!TARGET_PREFIXED_ADDR)
312 return SIGNED_34BIT_OFFSET_P (INTVAL (op));
315 ;; Return
1 if op is a register that is not special.
316 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
317 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
318 ;; the fact that SFmode is represented as DFmode in the VSX registers.
319 (define_predicate "gpc_reg_operand"
320 (match_operand
0 "register_operand")
324 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
327 op = SUBREG_REG (op);
333 if (!HARD_REGISTER_P (op))
336 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
339 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
342 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
345 ;; Return
1 if op is a general purpose register. Unlike gpc_reg_operand, don't
346 ;; allow floating point or vector registers. Since vector registers are not
347 ;; allowed, we don't have to reject SFmode/SImode subregs.
348 (define_predicate "int_reg_operand"
349 (match_operand
0 "register_operand")
353 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
356 op = SUBREG_REG (op);
362 if (!HARD_REGISTER_P (op))
365 return INT_REGNO_P (REGNO (op));
368 ;; Like int_reg_operand, but don't return true for pseudo registers
369 ;; We don't have to check for SF SUBREGS because pseudo registers
370 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
371 (define_predicate "int_reg_operand_not_pseudo"
372 (match_operand
0 "register_operand")
375 op = SUBREG_REG (op);
380 if (!HARD_REGISTER_P (op))
383 return INT_REGNO_P (REGNO (op));
386 ;; Like int_reg_operand, but only return true for base registers
387 (define_predicate "base_reg_operand"
388 (match_operand
0 "int_reg_operand")
391 op = SUBREG_REG (op);
396 return (REGNO (op) != FIRST_GPR_REGNO);
400 ;; Return true if this is a traditional floating point register
401 (define_predicate "fpr_reg_operand"
402 (match_code "reg,subreg")
407 op = SUBREG_REG (op);
413 if (!HARD_REGISTER_NUM_P (r))
416 return FP_REGNO_P (r);
419 ;; Return
1 if op is a general purpose register that is an even register
420 ;; which suitable for a load/store quad operation
421 ;; Subregs are not allowed here because when they are combine can
422 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
423 ;; think the innermost reg needs reloading, in TImode instead of
424 ;; PTImode. So reload will choose a reg in TImode which has no
425 ;; requirement that the reg be even.
426 (define_predicate "quad_int_reg_operand"
431 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
435 if (!HARD_REGISTER_NUM_P (r))
438 return (INT_REGNO_P (r) && ((r &
1) ==
0));
441 ;; Return
1 if op is a register that is a condition register field.
442 (define_predicate "cc_reg_operand"
443 (match_operand
0 "register_operand")
446 op = SUBREG_REG (op);
451 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
454 return CR_REGNO_P (REGNO (op));
457 ;; Return
1 if op is a register that is a condition register field not cr0.
458 (define_predicate "cc_reg_not_cr0_operand"
459 (match_operand
0 "register_operand")
462 op = SUBREG_REG (op);
467 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
470 return CR_REGNO_NOT_CR0_P (REGNO (op));
473 ;; Return
1 if op is a constant integer valid for D field
474 ;; or non-special register register.
475 (define_predicate "reg_or_short_operand"
476 (if_then_else (match_code "const_int")
477 (match_operand
0 "short_cint_operand")
478 (match_operand
0 "gpc_reg_operand")))
480 ;; Return
1 if op is a constant integer valid for DS field
481 ;; or non-special register.
482 (define_predicate "reg_or_aligned_short_operand"
483 (if_then_else (match_code "const_int")
484 (and (match_operand
0 "short_cint_operand")
485 (match_test "!(INTVAL (op) &
3)"))
486 (match_operand
0 "gpc_reg_operand")))
488 ;; Return
1 if op is a constant integer whose high-order
16 bits are zero
489 ;; or non-special register.
490 (define_predicate "reg_or_u_short_operand"
491 (if_then_else (match_code "const_int")
492 (match_operand
0 "u_short_cint_operand")
493 (match_operand
0 "gpc_reg_operand")))
495 ;; Return
1 if op is any constant integer or a non-special register.
496 (define_predicate "reg_or_cint_operand"
497 (ior (match_code "const_int")
498 (match_operand
0 "gpc_reg_operand")))
500 ;; Return
1 if op is constant zero or a non-special register.
501 (define_predicate "reg_or_zero_operand"
502 (ior (match_operand
0 "zero_constant")
503 (match_operand
0 "gpc_reg_operand")))
505 ;; Return
1 if op is a constant integer valid for addition with addis, addi.
506 (define_predicate "add_cint_operand"
507 (and (match_code "const_int")
508 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
509 + (mode == SImode ?
0x80000000 :
0x80008000))
510 < (unsigned HOST_WIDE_INT)
0x100000000ll")))
512 ;; Return
1 if op is a constant integer valid for addition
513 ;; or non-special register.
514 (define_predicate "reg_or_add_cint_operand"
515 (if_then_else (match_code "const_int")
516 (match_operand
0 "add_cint_operand")
517 (match_operand
0 "gpc_reg_operand")))
519 ;; Return
1 if op is a constant integer valid for subtraction
520 ;; or non-special register.
521 (define_predicate "reg_or_sub_cint_operand"
522 (if_then_else (match_code "const_int")
523 (match_test "(unsigned HOST_WIDE_INT)
524 (- UINTVAL (op) + (mode == SImode ?
0x80000000 :
0x80008000))
525 < (unsigned HOST_WIDE_INT)
0x100000000ll")
526 (match_operand
0 "gpc_reg_operand")))
528 ;; Return
1 if op is any
32-bit unsigned constant integer
529 ;; or non-special register.
530 (define_predicate "reg_or_logical_cint_operand"
531 (if_then_else (match_code "const_int")
532 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
534 || ((INTVAL (op) & GET_MODE_MASK (mode)
535 & (~ (unsigned HOST_WIDE_INT)
0xffffffff)) ==
0)")
536 (match_operand
0 "gpc_reg_operand")))
538 ;; Like reg_or_logical_cint_operand, but allow vsx registers
539 (define_predicate "vsx_reg_or_cint_operand"
540 (ior (match_operand
0 "vsx_register_operand")
541 (match_operand
0 "reg_or_logical_cint_operand")))
543 ;; Return
1 if operand is a CONST_DOUBLE that can be set in a register
544 ;; with no more than one instruction per word.
545 (define_predicate "easy_fp_constant"
546 (match_code "const_double")
548 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode));
550 /* Consider all constants with -msoft-float to be easy when regs are
551 32-bit and thus can be loaded with a maximum of
2 insns. For
552 64-bit avoid long dependent insn sequences. */
553 if (TARGET_SOFT_FLOAT)
555 if (!TARGET_POWERPC64)
558 int size = GET_MODE_SIZE (mode);
562 int load_from_mem_insns =
2;
564 load_from_mem_insns++;
565 if (TARGET_CMODEL != CMODEL_SMALL)
566 load_from_mem_insns++;
567 if (num_insns_constant (op, mode) <= load_from_mem_insns)
571 /*
0.0D is not all zero bits. */
572 if (DECIMAL_FLOAT_MODE_P (mode))
575 /* The constant
0.0 is easy under VSX. */
576 if (TARGET_VSX && op == CONST0_RTX (mode))
579 /* Otherwise consider floating point constants hard, so that the
580 constant gets pushed to memory during the early RTL phases. This
581 has the advantage that double precision constants that can be
582 represented in single precision without a loss of precision will
583 use single precision loads. */
587 ;; Return
1 if the operand is a constant that can loaded with a XXSPLTIB
588 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
590 (define_predicate "xxspltib_constant_split"
591 (match_code "const_vector,vec_duplicate,const_int")
596 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
599 return num_insns >
1;
603 ;; Return
1 if the operand is constant that can loaded directly with a XXSPLTIB
606 (define_predicate "xxspltib_constant_nosplit"
607 (match_code "const_vector,vec_duplicate,const_int")
612 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
615 return num_insns ==
1;
618 ;; Return
1 if the operand is a CONST_VECTOR and can be loaded into a
619 ;; vector register without using memory.
620 (define_predicate "easy_vector_constant"
621 (match_code "const_vector")
623 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
628 if (zero_constant (op, mode) || all_ones_constant (op, mode))
632 && xxspltib_constant_p (op, mode, &num_insns, &value))
635 return easy_altivec_constant (op, mode);
641 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
642 (define_predicate "easy_vector_constant_add_self"
643 (and (match_code "const_vector")
644 (and (match_test "TARGET_ALTIVEC")
645 (match_test "easy_altivec_constant (op, mode)")))
649 if (mode == V2DImode || mode == V2DFmode)
651 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
652 val = const_vector_elt_as_int (op, elt);
653 val = ((val &
0xff) ^
0x80) -
0x80;
654 return EASY_VECTOR_15_ADD_SELF (val);
657 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
658 (define_predicate "easy_vector_constant_msb"
659 (and (match_code "const_vector")
660 (and (match_test "TARGET_ALTIVEC")
661 (match_test "easy_altivec_constant (op, mode)")))
665 if (mode == V2DImode || mode == V2DFmode)
667 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
668 val = const_vector_elt_as_int (op, elt);
669 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
672 ;; Return true if this is an easy altivec constant that we form
674 (define_predicate "easy_vector_constant_vsldoi"
675 (and (match_code "const_vector")
676 (and (match_test "TARGET_ALTIVEC")
677 (and (match_test "easy_altivec_constant (op, mode)")
678 (match_test "vspltis_shifted (op) !=
0")))))
680 ;; Return
1 if operand is a vector int register or is either a vector constant
681 ;; of all
0 bits of a vector constant of all
1 bits.
682 (define_predicate "vector_int_reg_or_same_bit"
683 (match_code "reg,subreg,const_vector")
685 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
688 else if (REG_P (op) || SUBREG_P (op))
689 return vint_operand (op, mode);
692 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
695 ;; Return
1 if operand is
0.0.
696 (define_predicate "zero_fp_constant"
697 (and (match_code "const_double")
698 (match_test "SCALAR_FLOAT_MODE_P (mode)
699 && op == CONST0_RTX (mode)")))
701 ;; Return
1 if the operand is in volatile memory. Note that during the
702 ;; RTL generation phase, memory_operand does not return TRUE for volatile
703 ;; memory references. So this function allows us to recognize volatile
704 ;; references where it's safe.
705 (define_predicate "volatile_mem_operand"
706 (and (match_code "mem")
707 (match_test "MEM_VOLATILE_P (op)")
708 (if_then_else (match_test "reload_completed")
709 (match_operand
0 "memory_operand")
710 (match_test "memory_address_p (mode, XEXP (op,
0))"))))
712 ;; Return
1 if the operand is a volatile or non-volatile memory operand.
713 (define_predicate "any_memory_operand"
714 (ior (match_operand
0 "memory_operand")
715 (match_operand
0 "volatile_mem_operand")))
717 ;; Return
1 if the operand is an offsettable memory operand.
718 (define_predicate "offsettable_mem_operand"
719 (and (match_operand
0 "any_memory_operand")
720 (match_test "offsettable_nonstrict_memref_p (op)")))
722 ;; Return
1 if the operand is a simple offsettable memory operand
723 ;; that does not include pre-increment, post-increment, etc.
724 (define_predicate "simple_offsettable_mem_operand"
725 (match_operand
0 "offsettable_mem_operand")
727 rtx addr = XEXP (op,
0);
729 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
732 if (!CONSTANT_P (XEXP (addr,
1)))
735 return base_reg_operand (XEXP (addr,
0), Pmode);
738 ;; Return
1 if the operand is suitable for load/store quad memory.
739 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
740 (define_predicate "quad_memory_operand"
743 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
746 if (GET_MODE_SIZE (mode) !=
16 || !MEM_P (op) || MEM_ALIGN (op) <
128)
749 return quad_address_p (XEXP (op,
0), mode, false);
752 ;; Return
1 if the operand is suitable for load/store to vector registers with
753 ;; d-form addressing (register+offset), which was added in ISA
3.0.
754 ;; Unlike quad_memory_operand, we do not have to check for alignment.
755 (define_predicate "vsx_quad_dform_memory_operand"
758 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) !=
16)
761 return quad_address_p (XEXP (op,
0), mode, false);
764 ;; Return
1 if the operand is an indexed or indirect memory operand.
765 (define_predicate "indexed_or_indirect_operand"
769 if (VECTOR_MEM_ALTIVEC_P (mode)
770 && GET_CODE (op) == AND
771 && CONST_INT_P (XEXP (op,
1))
772 && INTVAL (XEXP (op,
1)) == -
16)
775 return indexed_or_indirect_address (op, mode);
778 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
779 ;; moves are supported.
780 (define_predicate "reg_or_indexed_operand"
781 (match_code "mem,reg,subreg")
784 return indexed_or_indirect_operand (op, mode);
785 else if (TARGET_DIRECT_MOVE)
786 return register_operand (op, mode);
791 ;; Return
1 if the operand is an indexed or indirect memory operand with an
792 ;; AND -
16 in it, used to recognize when we need to switch to Altivec loads
793 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
794 ;; while VSX uses the full address and traps)
795 (define_predicate "altivec_indexed_or_indirect_operand"
799 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
800 && GET_CODE (op) == AND
801 && CONST_INT_P (XEXP (op,
1))
802 && INTVAL (XEXP (op,
1)) == -
16)
803 return indexed_or_indirect_address (XEXP (op,
0), mode);
808 ;; Return
1 if the operand is an indexed or indirect address.
809 (define_special_predicate "indexed_or_indirect_address"
810 (and (match_test "REG_P (op)
811 || (GET_CODE (op) == PLUS
812 /* Omit testing REG_P (XEXP (op,
0)). */
813 && REG_P (XEXP (op,
1)))")
814 (match_operand
0 "address_operand")))
816 ;; Return
1 if the operand is an index-form address.
817 (define_special_predicate "indexed_address"
818 (match_test "(GET_CODE (op) == PLUS
819 && REG_P (XEXP (op,
0))
820 && REG_P (XEXP (op,
1)))"))
822 ;; Return
1 if the operand is a MEM with an update-form address. This may
823 ;; also include update-indexed form.
824 (define_special_predicate "update_address_mem"
825 (match_test "(MEM_P (op)
826 && (GET_CODE (XEXP (op,
0)) == PRE_INC
827 || GET_CODE (XEXP (op,
0)) == PRE_DEC
828 || GET_CODE (XEXP (op,
0)) == PRE_MODIFY))"))
830 ;; Return
1 if the operand is a MEM with an indexed-form address.
831 (define_special_predicate "indexed_address_mem"
832 (match_test "(MEM_P (op)
833 && (indexed_address (XEXP (op,
0), mode)
834 || (GET_CODE (XEXP (op,
0)) == PRE_MODIFY
835 && indexed_address (XEXP (XEXP (op,
0),
1), mode))))"))
837 ;; Return
1 if the operand is either a non-special register or can be used
838 ;; as the operand of a
`mode' add insn.
839 (define_predicate "add_operand"
840 (if_then_else (match_code "const_int")
841 (match_test "satisfies_constraint_I (op)
842 || satisfies_constraint_L (op)")
843 (match_operand 0 "gpc_reg_operand")))
845 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
846 (define_predicate "adde_operand"
847 (if_then_else (match_code "const_int")
848 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
849 (match_operand 0 "gpc_reg_operand")))
851 ;; Return 1 if OP is a constant but not a valid add_operand.
852 (define_predicate "non_add_cint_operand"
853 (and (match_code "const_int")
854 (not (match_operand 0 "add_operand"))))
856 ;; Return 1 if the operand is a constant that can be used as the operand
857 ;; of an AND, OR or XOR.
858 (define_predicate "logical_const_operand"
859 (match_code "const_int")
863 opl = INTVAL (op) & GET_MODE_MASK (mode);
865 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
866 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
869 ;; Return 1 if the operand is a non-special register or a constant that
870 ;; can be used as the operand of an AND, OR or XOR.
871 (define_predicate "logical_operand"
872 (ior (match_operand 0 "gpc_reg_operand")
873 (match_operand 0 "logical_const_operand")))
875 ;; Return 1 if op is a constant that is not a logical operand, but could
876 ;; be split into one.
877 (define_predicate "non_logical_cint_operand"
878 (and (match_code "const_int,const_wide_int")
879 (and (not (match_operand 0 "logical_operand"))
880 (match_operand 0 "reg_or_logical_cint_operand"))))
882 ;; Return 1 if the operand is either a non-special register or a
883 ;; constant that can be used as the operand of a logical AND.
884 (define_predicate "and_operand"
885 (ior (and (match_code "const_int")
886 (match_test "rs6000_is_valid_and_mask (op, mode)"))
887 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
888 (match_operand 0 "gpc_reg_operand")
889 (match_operand 0 "logical_operand"))))
891 ;; Return 1 if the operand is either a logical operand or a short cint operand.
892 (define_predicate "scc_eq_operand"
893 (ior (match_operand 0 "logical_operand")
894 (match_operand 0 "short_cint_operand")))
896 ;; Return 1 if the operand is a general non-special register or memory operand.
897 (define_predicate "reg_or_mem_operand"
898 (ior (match_operand 0 "gpc_reg_operand")
899 (match_operand 0 "any_memory_operand")
900 (and (match_code "mem")
901 (match_test "macho_lo_sum_memory_operand (op, mode)"))))
903 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
904 (define_predicate "zero_reg_mem_operand"
905 (ior (and (match_test "TARGET_VSX")
906 (match_operand 0 "zero_fp_constant"))
907 (match_operand 0 "reg_or_mem_operand")))
909 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
910 ;; data types inside of a vector that scalar instructions operate on
911 (define_predicate "vsx_scalar_64bit"
912 (match_code "const_int")
914 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
917 ;; Return 1 if the operand is a general register or memory operand without
918 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
920 (define_predicate "lwa_operand"
921 (match_code "reg,subreg,mem")
923 rtx inner, addr, offset;
926 if (reload_completed && SUBREG_P (inner))
927 inner = SUBREG_REG (inner);
929 if (gpc_reg_operand (inner, mode))
931 if (!any_memory_operand (inner, mode))
934 addr = XEXP (inner, 0);
935 if (GET_CODE (addr) == PRE_INC
936 || GET_CODE (addr) == PRE_DEC
937 || (GET_CODE (addr) == PRE_MODIFY
938 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
940 if (GET_CODE (addr) == LO_SUM
941 && REG_P (XEXP (addr, 0))
942 && GET_CODE (XEXP (addr, 1)) == CONST)
943 addr = XEXP (XEXP (addr, 1), 0);
944 if (GET_CODE (addr) != PLUS)
946 offset = XEXP (addr, 1);
947 if (!CONST_INT_P (offset))
949 return INTVAL (offset) % 4 == 0;
952 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
953 (define_predicate "symbol_ref_operand"
954 (and (match_code "symbol_ref")
955 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
956 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
958 ;; Return 1 if op is an operand that can be loaded via the GOT.
959 ;; or non-special register register field no cr0
960 (define_predicate "got_operand"
961 (match_code "symbol_ref,const,label_ref"))
963 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
964 ;; excluding labels involving addition.
965 (define_predicate "got_no_const_operand"
966 (match_code "symbol_ref,label_ref"))
968 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
969 (define_predicate "rs6000_tls_symbol_ref"
970 (and (match_code "symbol_ref")
971 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
973 ;; Return 1 for the CONST_INT or UNSPEC second CALL operand.
974 ;; Prevents unwanted substitution of the unspec got_reg arg.
975 (define_predicate "unspec_tls"
976 (match_code "const_int,unspec")
978 if (CONST_INT_P (op))
980 if (XINT (op, 1) == UNSPEC_TLSGD)
981 return REG_P (XVECEXP (op, 0, 1));
982 if (XINT (op, 1) == UNSPEC_TLSLD)
983 return REG_P (XVECEXP (op, 0, 0));
987 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
988 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
989 (define_predicate "call_operand"
990 (if_then_else (match_code "reg")
991 (match_test "REGNO (op) == LR_REGNO
992 || REGNO (op) == CTR_REGNO
993 || !HARD_REGISTER_P (op)")
994 (match_code "symbol_ref")))
996 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
997 ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR.
998 (define_predicate "indirect_call_operand"
999 (match_code "reg,unspec")
1002 return (REGNO (op) == LR_REGNO
1003 || REGNO (op) == CTR_REGNO);
1004 if (GET_CODE (op) == UNSPEC)
1006 if (XINT (op, 1) != UNSPEC_PLTSEQ)
1008 op = XVECEXP (op, 0, 0);
1009 return REG_P (op) && REGNO (op) == CTR_REGNO;
1014 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1016 (define_predicate "current_file_function_operand"
1017 (and (match_code "symbol_ref")
1018 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1019 && (SYMBOL_REF_LOCAL_P (op)
1020 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1021 && !decl_replaceable_p (current_function_decl)))
1022 && !((DEFAULT_ABI == ABI_AIX
1023 || DEFAULT_ABI == ABI_ELFv2)
1024 && (SYMBOL_REF_EXTERNAL_P (op)
1025 || SYMBOL_REF_WEAK (op)))")))
1027 ;; Return 1 if this operand is a valid input for a move insn.
1028 (define_predicate "input_operand"
1029 (match_code "symbol_ref,const,reg,subreg,mem,
1030 const_double,const_wide_int,const_vector,const_int")
1032 /* Memory is always valid. */
1033 if (any_memory_operand (op, mode))
1036 /* For floating-point, easy constants are valid. */
1037 if (SCALAR_FLOAT_MODE_P (mode)
1038 && easy_fp_constant (op, mode))
1041 /* Allow any integer constant. */
1042 if (GET_MODE_CLASS (mode) == MODE_INT
1043 && CONST_SCALAR_INT_P (op))
1046 /* Allow easy vector constants. */
1047 if (GET_CODE (op) == CONST_VECTOR
1048 && easy_vector_constant (op, mode))
1051 /* For floating-point or multi-word mode, the only remaining valid type
1053 if (SCALAR_FLOAT_MODE_P (mode)
1054 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1055 return register_operand (op, mode);
1057 /* We don't allow moving the carry bit around. */
1058 if (ca_operand (op, mode))
1061 /* The only cases left are integral modes one word or smaller (we
1062 do not get called for MODE_CC values). These can be in any
1064 if (register_operand (op, mode))
1067 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1069 if (DEFAULT_ABI == ABI_V4
1070 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST)
1071 && small_data_operand (op, Pmode))
1077 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1078 (define_predicate "splat_input_operand"
1079 (match_code "reg,subreg,mem")
1085 else if (mode == DImode)
1087 else if (mode == SImode && TARGET_P9_VECTOR)
1089 else if (mode == SFmode && TARGET_P9_VECTOR)
1096 rtx addr = XEXP (op, 0);
1098 if (! volatile_ok && MEM_VOLATILE_P (op))
1101 if (lra_in_progress || reload_completed)
1102 return indexed_or_indirect_address (addr, vmode);
1104 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1106 return gpc_reg_operand (op, mode);
1109 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1110 (define_predicate "rotate_mask_operator"
1111 (match_code "rotate,ashift,lshiftrt"))
1113 ;; Return true if operand is boolean operator.
1114 (define_predicate "boolean_operator"
1115 (match_code "and,ior,xor"))
1117 ;; Return true if operand is OR-form of boolean operator.
1118 (define_predicate "boolean_or_operator"
1119 (match_code "ior,xor"))
1121 ;; Return true if operand is an equality operator.
1122 (define_special_predicate "equality_operator"
1123 (match_code "eq,ne"))
1125 ;; Return 1 if OP is a comparison operation that is valid for a branch
1126 ;; instruction. We check the opcode against the mode of the CC value.
1127 ;; validate_condition_mode is an assertion.
1128 (define_predicate "branch_comparison_operator"
1129 (and (match_operand 0 "comparison_operator")
1130 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1131 (match_test "validate_condition_mode (GET_CODE (op),
1132 GET_MODE (XEXP (op, 0))),
1135 ;; Return 1 if OP is an unsigned comparison operator.
1136 (define_predicate "unsigned_comparison_operator"
1137 (match_code "ltu,gtu,leu,geu"))
1139 ;; Return 1 if OP is a signed comparison operator.
1140 (define_predicate "signed_comparison_operator"
1141 (match_code "lt,gt,le,ge"))
1143 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1144 ;; it must be a positive comparison.
1145 (define_predicate "scc_comparison_operator"
1146 (and (match_operand 0 "branch_comparison_operator")
1147 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1149 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1151 (define_predicate "scc_rev_comparison_operator"
1152 (and (match_operand 0 "branch_comparison_operator")
1153 (match_code "ne,le,ge,leu,geu,ordered")))
1155 ;; Return 1 if OP is a comparison operator suitable for floating point
1156 ;; vector/scalar comparisons that generate a -1/0 mask.
1157 (define_predicate "fpmask_comparison_operator"
1158 (match_code "eq,gt,ge"))
1160 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1161 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1162 ;; fpmask_comparison_operator).
1163 (define_predicate "invert_fpmask_comparison_operator"
1164 (match_code "ne,unlt,unle"))
1166 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1167 ;; comparisons that generate a -1/0 mask.
1168 (define_predicate "vecint_comparison_operator"
1169 (match_code "eq,gt,gtu"))
1171 ;; Return 1 if OP is a comparison operation that is valid for a branch
1172 ;; insn, which is true if the corresponding bit in the CC register is set.
1173 (define_predicate "branch_positive_comparison_operator"
1174 (and (match_operand 0 "branch_comparison_operator")
1175 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1177 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1179 (define_predicate "save_world_operation"
1180 (match_code "parallel")
1185 int count = XVECLEN (op, 0);
1191 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1192 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1195 for (i=1; i <= 18; i++)
1197 elt = XVECEXP (op, 0, index++);
1198 if (GET_CODE (elt) != SET
1199 || !MEM_P (SET_DEST (elt))
1200 || !memory_operand (SET_DEST (elt), DFmode)
1201 || !REG_P (SET_SRC (elt))
1202 || GET_MODE (SET_SRC (elt)) != DFmode)
1206 for (i=1; i <= 12; i++)
1208 elt = XVECEXP (op, 0, index++);
1209 if (GET_CODE (elt) != SET
1210 || !MEM_P (SET_DEST (elt))
1211 || !REG_P (SET_SRC (elt))
1212 || GET_MODE (SET_SRC (elt)) != V4SImode)
1216 for (i=1; i <= 19; i++)
1218 elt = XVECEXP (op, 0, index++);
1219 if (GET_CODE (elt) != SET
1220 || !MEM_P (SET_DEST (elt))
1221 || !memory_operand (SET_DEST (elt), Pmode)
1222 || !REG_P (SET_SRC (elt))
1223 || GET_MODE (SET_SRC (elt)) != Pmode)
1227 elt = XVECEXP (op, 0, index++);
1228 if (GET_CODE (elt) != SET
1229 || !MEM_P (SET_DEST (elt))
1230 || !memory_operand (SET_DEST (elt), Pmode)
1231 || !REG_P (SET_SRC (elt))
1232 || REGNO (SET_SRC (elt)) != CR2_REGNO
1233 || GET_MODE (SET_SRC (elt)) != Pmode)
1236 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1237 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1242 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1244 (define_predicate "restore_world_operation"
1245 (match_code "parallel")
1250 int count = XVECLEN (op, 0);
1256 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1257 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1258 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1261 elt = XVECEXP (op, 0, index++);
1262 if (GET_CODE (elt) != SET
1263 || !MEM_P (SET_SRC (elt))
1264 || !memory_operand (SET_SRC (elt), Pmode)
1265 || !REG_P (SET_DEST (elt))
1266 || REGNO (SET_DEST (elt)) != CR2_REGNO
1267 || GET_MODE (SET_DEST (elt)) != Pmode)
1270 for (i=1; i <= 19; i++)
1272 elt = XVECEXP (op, 0, index++);
1273 if (GET_CODE (elt) != SET
1274 || !MEM_P (SET_SRC (elt))
1275 || !memory_operand (SET_SRC (elt), Pmode)
1276 || !REG_P (SET_DEST (elt))
1277 || GET_MODE (SET_DEST (elt)) != Pmode)
1281 for (i=1; i <= 12; i++)
1283 elt = XVECEXP (op, 0, index++);
1284 if (GET_CODE (elt) != SET
1285 || !MEM_P (SET_SRC (elt))
1286 || !REG_P (SET_DEST (elt))
1287 || GET_MODE (SET_DEST (elt)) != V4SImode)
1291 for (i=1; i <= 18; i++)
1293 elt = XVECEXP (op, 0, index++);
1294 if (GET_CODE (elt) != SET
1295 || !MEM_P (SET_SRC (elt))
1296 || !memory_operand (SET_SRC (elt), DFmode)
1297 || !REG_P (SET_DEST (elt))
1298 || GET_MODE (SET_DEST (elt)) != DFmode)
1302 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1303 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1304 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1305 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1306 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1311 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1312 (define_predicate "vrsave_operation"
1313 (match_code "parallel")
1315 int count = XVECLEN (op, 0);
1316 unsigned int dest_regno, src_regno;
1320 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1321 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1322 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1323 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1326 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1327 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1329 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1332 for (i = 1; i < count; i++)
1334 rtx elt = XVECEXP (op, 0, i);
1336 if (GET_CODE (elt) != CLOBBER
1337 && GET_CODE (elt) != SET)
1344 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1345 (define_predicate "mfcr_operation"
1346 (match_code "parallel")
1348 int count = XVECLEN (op, 0);
1351 /* Perform a quick check so we don't blow up below. */
1353 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1354 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1355 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1358 for (i = 0; i < count; i++)
1360 rtx exp = XVECEXP (op, 0, i);
1365 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1367 if (!REG_P (src_reg)
1368 || GET_MODE (src_reg) != CCmode
1369 || ! CR_REGNO_P (REGNO (src_reg)))
1372 if (GET_CODE (exp) != SET
1373 || !REG_P (SET_DEST (exp))
1374 || GET_MODE (SET_DEST (exp)) != SImode
1375 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1377 unspec = SET_SRC (exp);
1378 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1380 if (GET_CODE (unspec) != UNSPEC
1381 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1382 || XVECLEN (unspec, 0) != 2
1383 || XVECEXP (unspec, 0, 0) != src_reg
1384 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1385 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1391 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1392 (define_predicate "mtcrf_operation"
1393 (match_code "parallel")
1395 int count = XVECLEN (op, 0);
1399 /* Perform a quick check so we don't blow up below. */
1401 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1402 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1403 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1405 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1407 if (!REG_P (src_reg)
1408 || GET_MODE (src_reg) != SImode
1409 || ! INT_REGNO_P (REGNO (src_reg)))
1412 for (i = 0; i < count; i++)
1414 rtx exp = XVECEXP (op, 0, i);
1418 if (GET_CODE (exp) != SET
1419 || !REG_P (SET_DEST (exp))
1420 || GET_MODE (SET_DEST (exp)) != CCmode
1421 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1423 unspec = SET_SRC (exp);
1424 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1426 if (GET_CODE (unspec) != UNSPEC
1427 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1428 || XVECLEN (unspec, 0) != 2
1429 || XVECEXP (unspec, 0, 0) != src_reg
1430 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1431 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1437 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1438 (define_predicate "crsave_operation"
1439 (match_code "parallel")
1441 int count = XVECLEN (op, 0);
1444 for (i = 1; i < count; i++)
1446 rtx exp = XVECEXP (op, 0, i);
1448 if (GET_CODE (exp) != USE
1449 || !REG_P (XEXP (exp, 0))
1450 || GET_MODE (XEXP (exp, 0)) != CCmode
1451 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1457 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1458 (define_predicate "lmw_operation"
1459 (match_code "parallel")
1461 int count = XVECLEN (op, 0);
1462 unsigned int dest_regno;
1464 unsigned int base_regno;
1465 HOST_WIDE_INT offset;
1468 /* Perform a quick check so we don't blow up below. */
1470 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1471 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1472 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
1475 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1476 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1479 || count != 32 - (int) dest_regno)
1482 if (legitimate_indirect_address_p (src_addr, 0))
1485 base_regno = REGNO (src_addr);
1486 if (base_regno == 0)
1489 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1491 offset = INTVAL (XEXP (src_addr, 1));
1492 base_regno = REGNO (XEXP (src_addr, 0));
1497 for (i = 0; i < count; i++)
1499 rtx elt = XVECEXP (op, 0, i);
1502 HOST_WIDE_INT newoffset;
1504 if (GET_CODE (elt) != SET
1505 || !REG_P (SET_DEST (elt))
1506 || GET_MODE (SET_DEST (elt)) != SImode
1507 || REGNO (SET_DEST (elt)) != dest_regno + i
1508 || !MEM_P (SET_SRC (elt))
1509 || GET_MODE (SET_SRC (elt)) != SImode)
1511 newaddr = XEXP (SET_SRC (elt), 0);
1512 if (legitimate_indirect_address_p (newaddr, 0))
1517 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1519 addr_reg = XEXP (newaddr, 0);
1520 newoffset = INTVAL (XEXP (newaddr, 1));
1524 if (REGNO (addr_reg) != base_regno
1525 || newoffset != offset + 4 * i)
1532 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1533 (define_predicate "stmw_operation"
1534 (match_code "parallel")
1536 int count = XVECLEN (op, 0);
1537 unsigned int src_regno;
1539 unsigned int base_regno;
1540 HOST_WIDE_INT offset;
1543 /* Perform a quick check so we don't blow up below. */
1545 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1546 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
1547 || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
1550 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1551 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1554 || count != 32 - (int) src_regno)
1557 if (legitimate_indirect_address_p (dest_addr, 0))
1560 base_regno = REGNO (dest_addr);
1561 if (base_regno == 0)
1564 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1566 offset = INTVAL (XEXP (dest_addr, 1));
1567 base_regno = REGNO (XEXP (dest_addr, 0));
1572 for (i = 0; i < count; i++)
1574 rtx elt = XVECEXP (op, 0, i);
1577 HOST_WIDE_INT newoffset;
1579 if (GET_CODE (elt) != SET
1580 || !REG_P (SET_SRC (elt))
1581 || GET_MODE (SET_SRC (elt)) != SImode
1582 || REGNO (SET_SRC (elt)) != src_regno + i
1583 || !MEM_P (SET_DEST (elt))
1584 || GET_MODE (SET_DEST (elt)) != SImode)
1586 newaddr = XEXP (SET_DEST (elt), 0);
1587 if (legitimate_indirect_address_p (newaddr, 0))
1592 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1594 addr_reg = XEXP (newaddr, 0);
1595 newoffset = INTVAL (XEXP (newaddr, 1));
1599 if (REGNO (addr_reg) != base_regno
1600 || newoffset != offset + 4 * i)
1607 ;; Return 1 if OP is a stack tie operand.
1608 (define_predicate "tie_operand"
1609 (match_code "parallel")
1611 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1612 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0))
1613 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1614 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1617 ;; Match a small code model toc reference (or medium and large
1618 ;; model toc references before reload).
1619 (define_predicate "small_toc_ref"
1620 (match_code "unspec,plus")
1622 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1625 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1629 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1630 ;; GPR registers on power8.
1631 (define_predicate "fusion_gpr_addis"
1632 (match_code "const_int,high,plus")
1634 HOST_WIDE_INT value;
1637 if (GET_CODE (op) == HIGH)
1640 if (CONST_INT_P (op))
1643 else if (GET_CODE (op) == PLUS
1644 && base_reg_operand (XEXP (op, 0), Pmode)
1645 && CONST_INT_P (XEXP (op, 1)))
1646 int_const = XEXP (op, 1);
1651 value = INTVAL (int_const);
1652 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1655 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1658 /* Power8 only does the fusion if the top 12 bits of the addis value are all
1660 return (IN_RANGE (value >> 16, -16, 15));
1663 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1664 ;; and loads to GPR registers on power8.
1665 (define_predicate "fusion_gpr_mem_load"
1666 (match_code "mem,sign_extend,zero_extend")
1668 rtx addr, base, offset;
1670 /* Handle sign/zero extend. */
1671 if (GET_CODE (op) == ZERO_EXTEND
1672 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1675 mode = GET_MODE (op);
1689 if (!TARGET_POWERPC64)
1693 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1699 addr = XEXP (op, 0);
1700 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1703 base = XEXP (addr, 0);
1704 if (!base_reg_operand (base, GET_MODE (base)))
1707 offset = XEXP (addr, 1);
1709 if (GET_CODE (addr) == PLUS)
1710 return satisfies_constraint_I (offset);
1712 else if (GET_CODE (addr) == LO_SUM)
1714 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1715 return small_toc_ref (offset, GET_MODE (offset));
1717 else if (TARGET_ELF && !TARGET_POWERPC64)
1718 return CONSTANT_P (offset);
1724 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1725 ;; memory field with both the addis and the memory offset. Sign extension
1726 ;; is not handled here, since lha and lwa are not fused.
1727 (define_predicate "fusion_addis_mem_combo_load"
1728 (match_code "mem,zero_extend")
1730 rtx addr, base, offset;
1732 /* Handle zero extend. */
1733 if (GET_CODE (op) == ZERO_EXTEND)
1736 mode = GET_MODE (op);
1749 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1750 separate instructions. */
1752 if (!TARGET_POWERPC64)
1756 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1762 addr = XEXP (op, 0);
1763 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1766 base = XEXP (addr, 0);
1767 if (!fusion_gpr_addis (base, GET_MODE (base)))
1770 offset = XEXP (addr, 1);
1771 if (GET_CODE (addr) == PLUS)
1772 return satisfies_constraint_I (offset);
1774 else if (GET_CODE (addr) == LO_SUM)
1776 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1777 return small_toc_ref (offset, GET_MODE (offset));
1779 else if (TARGET_ELF && !TARGET_POWERPC64)
1780 return CONSTANT_P (offset);
1787 ;; Return true if the operand is a PC-relative address of a local symbol or a
1788 ;; label that can be used directly in a memory operation.
1789 (define_predicate "pcrel_local_address"
1790 (match_code "label_ref,symbol_ref,const")
1792 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1793 return iform == INSN_FORM_PCREL_LOCAL;
1796 ;; Return true if the operand is a PC-relative external symbol whose address
1797 ;; can be loaded into a register.
1798 (define_predicate "pcrel_external_address"
1799 (match_code "symbol_ref,const")
1801 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1802 return iform == INSN_FORM_PCREL_EXTERNAL;
1805 ;; Return true if the address is PC-relative and the symbol is either local or
1807 (define_predicate "pcrel_local_or_external_address"
1808 (ior (match_operand 0 "pcrel_local_address")
1809 (match_operand 0 "pcrel_external_address")))