1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C)
2005-
2021 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version
3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return
1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return
1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return
1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return
1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have
64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return
1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand
0 "register_operand")
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (!HARD_REGISTER_P (op))
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return
1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand
0 "register_operand")
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (!HARD_REGISTER_P (op))
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand
0 "register_operand")
111 op = SUBREG_REG (op);
116 if (!HARD_REGISTER_P (op))
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return
1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand
0 "register_operand")
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (!HARD_REGISTER_P (op))
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return
1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand
0 "register_operand")
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (!HARD_REGISTER_P (op))
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return
1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand
0 "register_operand")
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (!HARD_REGISTER_P (op))
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return
1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand
0 "register_operand")
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return
1 if operand is constant zero (scalars and vectors).
203 (define_predicate "zero_constant"
204 (and (match_code "const_int,const_double,const_wide_int,const_vector")
205 (match_test "op == CONST0_RTX (mode)")))
207 ;; Return
1 if operand is constant -
1 (scalars and vectors).
208 (define_predicate "all_ones_constant"
209 (and (match_code "const_int,const_double,const_wide_int,const_vector")
210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
212 ;; Return
1 if op is a signed
5-bit constant integer.
213 (define_predicate "s5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >= -
16 && INTVAL (op) <=
15")))
217 ;; Return
1 if op is an unsigned
1-bit constant integer.
218 (define_predicate "u1bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1")))
222 ;; Return
1 if op is a unsigned
3-bit constant integer.
223 (define_predicate "u3bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
7")))
227 ;; Return
1 if op is a unsigned
5-bit constant integer.
228 (define_predicate "u5bit_cint_operand"
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
31")))
232 ;; Return
1 if op is a unsigned
6-bit constant integer.
233 (define_predicate "u6bit_cint_operand"
234 (and (match_code "const_int")
235 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
63")))
237 ;; Return
1 if op is an unsigned
7-bit constant integer.
238 (define_predicate "u7bit_cint_operand"
239 (and (match_code "const_int")
240 (match_test "IN_RANGE (INTVAL (op),
0,
127)")))
242 ;; Return
1 if op is a unsigned
8-bit constant integer.
243 (define_predicate "u8bit_cint_operand"
244 (and (match_code "const_int")
245 (match_test "IN_RANGE (INTVAL (op),
0,
255)")))
247 ;; Return
1 if op is a signed
8-bit constant integer.
248 ;; Integer multiplication complete more quickly
249 (define_predicate "s8bit_cint_operand"
250 (and (match_code "const_int")
251 (match_test "INTVAL (op) >= -
128 && INTVAL (op) <=
127")))
253 ;; Return
1 if op is a unsigned
10-bit constant integer.
254 (define_predicate "u10bit_cint_operand"
255 (and (match_code "const_int")
256 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
1023")))
258 ;; Return
1 if op is a constant integer that can fit in a D field.
259 (define_predicate "short_cint_operand"
260 (and (match_code "const_int")
261 (match_test "satisfies_constraint_I (op)")))
263 ;; Return
1 if op is a constant integer that can fit in an unsigned D field.
264 (define_predicate "u_short_cint_operand"
265 (and (match_code "const_int")
266 (match_test "satisfies_constraint_K (op)")))
268 ;; Return
1 if op is a constant integer that is a signed
16-bit constant
269 ;; shifted left
16 bits
270 (define_predicate "upper16_cint_operand"
271 (and (match_code "const_int")
272 (match_test "satisfies_constraint_L (op)")))
274 ;; Return
1 if op is a constant integer that cannot fit in a signed D field.
275 (define_predicate "non_short_cint_operand"
276 (and (match_code "const_int")
277 (match_test "(unsigned HOST_WIDE_INT)
278 (INTVAL (op) +
0x8000) >=
0x10000")))
280 ;; Return
1 if op is a
32-bit constant signed integer
281 (define_predicate "s32bit_cint_operand"
282 (and (match_code "const_int")
283 (match_test "(
0x80000000 + UINTVAL (op)) >>
32 ==
0")))
285 ;; Return
1 if op is a constant
32-bit unsigned
286 (define_predicate "c32bit_cint_operand"
287 (and (match_code "const_int")
288 (match_test "((UINTVAL (op) >>
32) ==
0)")))
290 ;; Return
1 if op is a positive constant integer that is an exact power of
2.
291 (define_predicate "exact_log2_cint_operand"
292 (and (match_code "const_int")
293 (match_test "INTVAL (op) >
0 && exact_log2 (INTVAL (op)) >=
0")))
295 ;; Match op =
0 or op =
1.
296 (define_predicate "const_0_to_1_operand"
297 (and (match_code "const_int")
298 (match_test "IN_RANGE (INTVAL (op),
0,
1)")))
300 ;; Match op = -
1, op =
0, or op =
1.
301 (define_predicate "const_m1_to_1_operand"
302 (and (match_code "const_int")
303 (match_test "IN_RANGE (INTVAL (op), -
1,
1)")))
306 (define_predicate "const_0_to_3_operand"
307 (and (match_code "const_int")
308 (match_test "IN_RANGE (INTVAL (op),
0,
3)")))
310 ;; Match op =
2 or op =
3.
311 (define_predicate "const_2_to_3_operand"
312 (and (match_code "const_int")
313 (match_test "IN_RANGE (INTVAL (op),
2,
3)")))
316 (define_predicate "const_0_to_7_operand"
317 (and (match_code "const_int")
318 (match_test "IN_RANGE (INTVAL (op),
0,
7)")))
321 (define_predicate "const_0_to_12_operand"
322 (and (match_code "const_int")
323 (match_test "IN_RANGE (INTVAL (op),
0,
12)")))
326 (define_predicate "const_0_to_15_operand"
327 (and (match_code "const_int")
328 (match_test "IN_RANGE (INTVAL (op),
0,
15)")))
330 ;; Return
1 if op is a
34-bit constant integer.
331 (define_predicate "cint34_operand"
332 (match_code "const_int")
334 if (!TARGET_PREFIXED)
337 return SIGNED_INTEGER_34BIT_P (INTVAL (op));
340 ;; Return
1 if op is a register that is not special.
341 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
342 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
343 ;; the fact that SFmode is represented as DFmode in the VSX registers.
344 (define_predicate "gpc_reg_operand"
345 (match_operand
0 "register_operand")
349 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
352 op = SUBREG_REG (op);
358 if (!HARD_REGISTER_P (op))
361 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
364 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
367 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
370 ;; Return
1 if op is a general purpose register. Unlike gpc_reg_operand, don't
371 ;; allow floating point or vector registers. Since vector registers are not
372 ;; allowed, we don't have to reject SFmode/SImode subregs.
373 (define_predicate "int_reg_operand"
374 (match_operand
0 "register_operand")
378 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
381 op = SUBREG_REG (op);
387 if (!HARD_REGISTER_P (op))
390 return INT_REGNO_P (REGNO (op));
393 ;; Like int_reg_operand, but don't return true for pseudo registers
394 ;; We don't have to check for SF SUBREGS because pseudo registers
395 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
396 (define_predicate "int_reg_operand_not_pseudo"
397 (match_operand
0 "register_operand")
400 op = SUBREG_REG (op);
405 if (!HARD_REGISTER_P (op))
408 return INT_REGNO_P (REGNO (op));
411 ;; Like int_reg_operand, but only return true for base registers
412 (define_predicate "base_reg_operand"
413 (match_operand
0 "int_reg_operand")
416 op = SUBREG_REG (op);
421 return (REGNO (op) != FIRST_GPR_REGNO);
425 ;; Return true if this is a traditional floating point register
426 (define_predicate "fpr_reg_operand"
427 (match_code "reg,subreg")
432 op = SUBREG_REG (op);
438 if (!HARD_REGISTER_NUM_P (r))
441 return FP_REGNO_P (r);
444 ;; Return
1 if op is a general purpose register that is an even register
445 ;; which suitable for a load/store quad operation
446 ;; Subregs are not allowed here because when they are combine can
447 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
448 ;; think the innermost reg needs reloading, in TImode instead of
449 ;; PTImode. So reload will choose a reg in TImode which has no
450 ;; requirement that the reg be even.
451 (define_predicate "quad_int_reg_operand"
456 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
460 if (!HARD_REGISTER_NUM_P (r))
463 return (INT_REGNO_P (r) && ((r &
1) ==
0));
466 ;; Return
1 if op is a register that is a condition register field.
467 (define_predicate "cc_reg_operand"
468 (match_operand
0 "register_operand")
471 op = SUBREG_REG (op);
476 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
479 return CR_REGNO_P (REGNO (op));
482 ;; Return
1 if op is a register that is a condition register field not cr0.
483 (define_predicate "cc_reg_not_cr0_operand"
484 (match_operand
0 "register_operand")
487 op = SUBREG_REG (op);
492 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
495 return CR_REGNO_NOT_CR0_P (REGNO (op));
498 ;; Return
1 if op is a constant integer valid for D field
499 ;; or non-special register register.
500 (define_predicate "reg_or_short_operand"
501 (if_then_else (match_code "const_int")
502 (match_operand
0 "short_cint_operand")
503 (match_operand
0 "gpc_reg_operand")))
505 ;; Return
1 if op is a constant integer valid for DS field
506 ;; or non-special register.
507 (define_predicate "reg_or_aligned_short_operand"
508 (if_then_else (match_code "const_int")
509 (and (match_operand
0 "short_cint_operand")
510 (match_test "!(INTVAL (op) &
3)"))
511 (match_operand
0 "gpc_reg_operand")))
513 ;; Return
1 if op is a constant integer whose high-order
16 bits are zero
514 ;; or non-special register.
515 (define_predicate "reg_or_u_short_operand"
516 (if_then_else (match_code "const_int")
517 (match_operand
0 "u_short_cint_operand")
518 (match_operand
0 "gpc_reg_operand")))
520 ;; Return
1 if op is any constant integer or a non-special register.
521 (define_predicate "reg_or_cint_operand"
522 (ior (match_code "const_int")
523 (match_operand
0 "gpc_reg_operand")))
525 ;; Return
1 if op is constant zero or a non-special register.
526 (define_predicate "reg_or_zero_operand"
527 (ior (match_operand
0 "zero_constant")
528 (match_operand
0 "gpc_reg_operand")))
530 ;; Return
1 if op is a constant integer valid for addition with addis, addi.
531 (define_predicate "add_cint_operand"
532 (and (match_code "const_int")
533 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
534 + (mode == SImode ?
0x80000000 :
0x80008000))
535 < (unsigned HOST_WIDE_INT)
0x100000000ll")))
537 ;; Return
1 if op is a constant integer valid for addition
538 ;; or non-special register.
539 (define_predicate "reg_or_add_cint_operand"
540 (if_then_else (match_code "const_int")
541 (match_operand
0 "add_cint_operand")
542 (match_operand
0 "gpc_reg_operand")))
544 ;; Return
1 if op is a constant integer valid for subtraction
545 ;; or non-special register.
546 (define_predicate "reg_or_sub_cint_operand"
547 (if_then_else (match_code "const_int")
548 (match_test "(unsigned HOST_WIDE_INT)
549 (- UINTVAL (op) + (mode == SImode ?
0x80000000 :
0x80008000))
550 < (unsigned HOST_WIDE_INT)
0x100000000ll")
551 (match_operand
0 "gpc_reg_operand")))
553 ;; Return
1 if op is any
32-bit unsigned constant integer
554 ;; or non-special register.
555 (define_predicate "reg_or_logical_cint_operand"
556 (if_then_else (match_code "const_int")
557 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
559 || ((INTVAL (op) & GET_MODE_MASK (mode)
560 & (~ (unsigned HOST_WIDE_INT)
0xffffffff)) ==
0)")
561 (match_operand
0 "gpc_reg_operand")))
563 ;; Like reg_or_logical_cint_operand, but allow vsx registers
564 (define_predicate "vsx_reg_or_cint_operand"
565 (ior (match_operand
0 "vsx_register_operand")
566 (match_operand
0 "reg_or_logical_cint_operand")))
568 ;; Return
1 if operand is a CONST_DOUBLE that can be set in a register
569 ;; with no more than one instruction per word.
570 (define_predicate "easy_fp_constant"
571 (match_code "const_double")
573 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode));
575 /* Consider all constants with -msoft-float to be easy when regs are
576 32-bit and thus can be loaded with a maximum of
2 insns. For
577 64-bit avoid long dependent insn sequences. */
578 if (TARGET_SOFT_FLOAT)
580 if (!TARGET_POWERPC64)
583 int size = GET_MODE_SIZE (mode);
587 int load_from_mem_insns =
2;
589 load_from_mem_insns++;
590 if (TARGET_CMODEL != CMODEL_SMALL)
591 load_from_mem_insns++;
592 if (num_insns_constant (op, mode) <= load_from_mem_insns)
596 /*
0.0D is not all zero bits. */
597 if (DECIMAL_FLOAT_MODE_P (mode))
600 /* The constant
0.0 is easy under VSX. */
601 if (TARGET_VSX && op == CONST0_RTX (mode))
604 /* If we have the ISA
3.1 XXSPLTIDP instruction, see if the constant can
605 be loaded with that instruction. */
606 if (xxspltidp_operand (op, mode))
609 /* If we have the ISA
3.1 LXVKQ instruction, see if the constant can be loaded
610 with that instruction. */
611 if (lxvkq_operand (op, mode))
614 /* Otherwise consider floating point constants hard, so that the
615 constant gets pushed to memory during the early RTL phases. This
616 has the advantage that double precision constants that can be
617 represented in single precision without a loss of precision will
618 use single precision loads. */
622 ;; Return
1 if the operand is a constant that can loaded with a XXSPLTIB
623 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
625 (define_predicate "xxspltib_constant_split"
626 (match_code "const_vector,vec_duplicate,const_int")
631 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
634 return num_insns >
1;
638 ;; Return
1 if the operand is constant that can loaded directly with a XXSPLTIB
641 (define_predicate "xxspltib_constant_nosplit"
642 (match_code "const_vector,vec_duplicate,const_int")
647 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
650 return num_insns ==
1;
653 ;; Return
1 if the operand is a CONST_VECTOR that can be loaded with the
654 ;; XXSPLTIW instruction.
655 (define_predicate "xxspltiw_operand"
656 (match_code "const_vector")
658 HOST_WIDE_INT xxspltiw_value =
0;
660 return xxspltiw_constant_p (op, mode, &xxspltiw_value);
663 ;; Return
1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
664 ;; loaded via the ISA
3.1 XXSPLTIDP instruction.
665 (define_predicate "xxspltidp_operand"
666 (match_code "const_double,const_vector,vec_duplicate")
668 HOST_WIDE_INT value =
0;
669 return xxspltidp_constant_p (op, mode, &value);
672 ;; Return
1 if the operand is an IEEE
128-bit special constant that can be
673 ;; loaded with the LXVKQ instruction.
674 (define_predicate "lxvkq_operand"
675 (match_code "const_double")
678 return lxvkq_constant_p (op, mode, &immediate);
681 ;; Return
1 if the operand is a CONST_VECTOR and can be loaded into a
682 ;; vector register without using memory.
683 (define_predicate "easy_vector_constant"
684 (match_code "const_vector")
686 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
691 if (zero_constant (op, mode) || all_ones_constant (op, mode))
694 if (xxspltiw_operand (op, mode))
697 if (xxspltidp_operand (op, mode))
701 && xxspltib_constant_p (op, mode, &num_insns, &value))
704 return easy_altivec_constant (op, mode);
710 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
711 (define_predicate "easy_vector_constant_add_self"
712 (and (match_code "const_vector")
713 (and (match_test "TARGET_ALTIVEC")
714 (match_test "easy_altivec_constant (op, mode)")))
718 if (mode == V2DImode || mode == V2DFmode)
720 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
721 val = const_vector_elt_as_int (op, elt);
722 val = ((val &
0xff) ^
0x80) -
0x80;
723 return EASY_VECTOR_15_ADD_SELF (val);
726 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
727 (define_predicate "easy_vector_constant_msb"
728 (and (match_code "const_vector")
729 (and (match_test "TARGET_ALTIVEC")
730 (match_test "easy_altivec_constant (op, mode)")
731 (match_test "vspltis_shifted (op) ==
0")))
734 int elt, sz = easy_altivec_constant (op, mode);
735 machine_mode inner = GET_MODE_INNER (mode);
736 int isz = GET_MODE_SIZE (inner);
737 if (mode == V2DImode || mode == V2DFmode)
739 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) -
1 :
0;
742 if (const_vector_elt_as_int (op, elt) !=
0)
744 elt += (BYTES_BIG_ENDIAN ? -
1 :
1) * (sz - isz) / isz;
747 inner = smallest_int_mode_for_size (sz * BITS_PER_UNIT);
748 val = const_vector_elt_as_int (op, elt);
749 return EASY_VECTOR_MSB (val, inner);
752 ;; Return true if this is an easy altivec constant that we form
754 (define_predicate "easy_vector_constant_vsldoi"
755 (and (match_code "const_vector")
756 (and (match_test "TARGET_ALTIVEC")
757 (and (match_test "easy_altivec_constant (op, mode)")
758 (match_test "vspltis_shifted (op) !=
0")))))
760 ;; Return
1 if operand is a vector int register or is either a vector constant
761 ;; of all
0 bits of a vector constant of all
1 bits.
762 (define_predicate "vector_int_reg_or_same_bit"
763 (match_code "reg,subreg,const_vector")
765 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
768 else if (REG_P (op) || SUBREG_P (op))
769 return vint_operand (op, mode);
772 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
775 ;; Return
1 if operand is
0.0.
776 (define_predicate "zero_fp_constant"
777 (and (match_code "const_double")
778 (match_test "SCALAR_FLOAT_MODE_P (mode)
779 && op == CONST0_RTX (mode)")))
781 ;; Return
1 if the operand is in volatile memory. Note that during the
782 ;; RTL generation phase, memory_operand does not return TRUE for volatile
783 ;; memory references. So this function allows us to recognize volatile
784 ;; references where it's safe.
785 (define_predicate "volatile_mem_operand"
786 (and (match_code "mem")
787 (match_test "MEM_VOLATILE_P (op)")
788 (if_then_else (match_test "reload_completed")
789 (match_operand
0 "memory_operand")
790 (match_test "memory_address_p (mode, XEXP (op,
0))"))))
792 ;; Return
1 if the operand is a volatile or non-volatile memory operand.
793 (define_predicate "any_memory_operand"
794 (ior (match_operand
0 "memory_operand")
795 (match_operand
0 "volatile_mem_operand")))
797 ;; Return
1 if the operand is an offsettable memory operand.
798 (define_predicate "offsettable_mem_operand"
799 (and (match_operand
0 "any_memory_operand")
800 (match_test "offsettable_nonstrict_memref_p (op)")))
802 ;; Return
1 if the operand is a simple offsettable memory operand
803 ;; that does not include pre-increment, post-increment, etc.
804 (define_predicate "simple_offsettable_mem_operand"
805 (match_operand
0 "offsettable_mem_operand")
807 rtx addr = XEXP (op,
0);
809 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
812 if (!CONSTANT_P (XEXP (addr,
1)))
815 return base_reg_operand (XEXP (addr,
0), Pmode);
818 ;; Return
1 if the operand is suitable for load/store quad memory.
819 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
820 (define_predicate "quad_memory_operand"
823 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
826 if (GET_MODE_SIZE (mode) !=
16 || !MEM_P (op) || MEM_ALIGN (op) <
128)
829 return quad_address_p (XEXP (op,
0), mode, false);
832 ;; Return
1 if the operand is suitable for load/store to vector registers with
833 ;; d-form addressing (register+offset), which was added in ISA
3.0.
834 ;; Unlike quad_memory_operand, we do not have to check for alignment.
835 (define_predicate "vsx_quad_dform_memory_operand"
838 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) !=
16)
841 return quad_address_p (XEXP (op,
0), mode, false);
844 ;; Return
1 if the operand is an indexed or indirect memory operand.
845 (define_predicate "indexed_or_indirect_operand"
849 if (VECTOR_MEM_ALTIVEC_P (mode)
850 && GET_CODE (op) == AND
851 && CONST_INT_P (XEXP (op,
1))
852 && INTVAL (XEXP (op,
1)) == -
16)
855 return indexed_or_indirect_address (op, mode);
858 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
859 ;; moves are supported.
860 (define_predicate "reg_or_indexed_operand"
861 (match_code "mem,reg,subreg")
864 return indexed_or_indirect_operand (op, mode);
865 else if (TARGET_DIRECT_MOVE)
866 return register_operand (op, mode);
871 ;; Return
1 if the operand is an indexed or indirect memory operand with an
872 ;; AND -
16 in it, used to recognize when we need to switch to Altivec loads
873 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
874 ;; while VSX uses the full address and traps)
875 (define_predicate "altivec_indexed_or_indirect_operand"
879 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
880 && GET_CODE (op) == AND
881 && CONST_INT_P (XEXP (op,
1))
882 && INTVAL (XEXP (op,
1)) == -
16)
883 return indexed_or_indirect_address (XEXP (op,
0), mode);
888 ;; Return
1 if the operand is an indexed or indirect address.
889 (define_special_predicate "indexed_or_indirect_address"
890 (and (match_test "REG_P (op)
891 || (GET_CODE (op) == PLUS
892 /* Omit testing REG_P (XEXP (op,
0)). */
893 && REG_P (XEXP (op,
1)))")
894 (match_operand
0 "address_operand")))
896 ;; Return
1 if the operand is an index-form address.
897 (define_special_predicate "indexed_address"
898 (match_test "(GET_CODE (op) == PLUS
899 && REG_P (XEXP (op,
0))
900 && REG_P (XEXP (op,
1)))"))
902 ;; Return
1 if the operand is a MEM with an update-form address. This may
903 ;; also include update-indexed form.
904 (define_special_predicate "update_address_mem"
905 (match_test "(MEM_P (op)
906 && (GET_CODE (XEXP (op,
0)) == PRE_INC
907 || GET_CODE (XEXP (op,
0)) == PRE_DEC
908 || GET_CODE (XEXP (op,
0)) == PRE_MODIFY))"))
910 ;; Anything that matches memory_operand but does not update the address.
911 (define_predicate "non_update_memory_operand"
914 if (update_address_mem (op, mode))
916 return memory_operand (op, mode);
919 ;; Return
1 if the operand is a MEM with an indexed-form address.
920 (define_special_predicate "indexed_address_mem"
921 (match_test "(MEM_P (op)
922 && (indexed_address (XEXP (op,
0), mode)
923 || (GET_CODE (XEXP (op,
0)) == PRE_MODIFY
924 && indexed_address (XEXP (XEXP (op,
0),
1), mode))))"))
926 ;; Return
1 if the operand is either a non-special register or can be used
927 ;; as the operand of a
`mode' add insn.
928 (define_predicate "add_operand"
929 (if_then_else (match_code "const_int")
930 (match_test "satisfies_constraint_I (op)
931 || satisfies_constraint_L (op)
932 || satisfies_constraint_eI (op)")
933 (match_operand 0 "gpc_reg_operand")))
935 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
936 (define_predicate "adde_operand"
937 (if_then_else (match_code "const_int")
938 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
939 (match_operand 0 "gpc_reg_operand")))
941 ;; Return 1 if OP is a constant but not a valid add_operand.
942 (define_predicate "non_add_cint_operand"
943 (and (match_code "const_int")
944 (not (match_operand 0 "add_operand"))))
946 ;; Return 1 if the operand is a constant that can be used as the operand
947 ;; of an AND, OR or XOR.
948 (define_predicate "logical_const_operand"
949 (match_code "const_int")
953 opl = INTVAL (op) & GET_MODE_MASK (mode);
955 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
956 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
959 ;; Return 1 if the operand is a non-special register or a constant that
960 ;; can be used as the operand of an AND, OR or XOR.
961 (define_predicate "logical_operand"
962 (ior (match_operand 0 "gpc_reg_operand")
963 (match_operand 0 "logical_const_operand")))
965 ;; Return 1 if op is a constant that is not a logical operand, but could
966 ;; be split into one.
967 (define_predicate "non_logical_cint_operand"
968 (and (match_code "const_int,const_wide_int")
969 (and (not (match_operand 0 "logical_operand"))
970 (match_operand 0 "reg_or_logical_cint_operand"))))
972 ;; Return 1 if the operand is either a non-special register or a
973 ;; constant that can be used as the operand of a logical AND.
974 (define_predicate "and_operand"
975 (ior (and (match_code "const_int")
976 (match_test "rs6000_is_valid_and_mask (op, mode)"))
977 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
978 (match_operand 0 "gpc_reg_operand")
979 (match_operand 0 "logical_operand"))))
981 ;; Return 1 if the operand is either a logical operand or a short cint operand.
982 (define_predicate "scc_eq_operand"
983 (ior (match_operand 0 "logical_operand")
984 (match_operand 0 "short_cint_operand")))
986 ;; Return 1 if the operand is a general non-special register or memory operand.
987 (define_predicate "reg_or_mem_operand"
988 (ior (match_operand 0 "gpc_reg_operand")
989 (match_operand 0 "any_memory_operand")
990 (and (match_code "mem")
991 (match_test "macho_lo_sum_memory_operand (op, mode)"))))
993 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
994 (define_predicate "zero_reg_mem_operand"
995 (ior (and (match_test "TARGET_VSX")
996 (match_operand 0 "zero_fp_constant"))
997 (match_operand 0 "reg_or_mem_operand")))
999 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
1000 ;; data types inside of a vector that scalar instructions operate on
1001 (define_predicate "vsx_scalar_64bit"
1002 (match_code "const_int")
1004 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
1007 ;; Return 1 if the operand is a general register or memory operand without
1008 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
1010 (define_predicate "lwa_operand"
1011 (match_code "reg,subreg,mem")
1013 rtx inner, addr, offset;
1016 if (reload_completed && SUBREG_P (inner))
1017 inner = SUBREG_REG (inner);
1019 if (gpc_reg_operand (inner, mode))
1021 if (!any_memory_operand (inner, mode))
1024 addr = XEXP (inner, 0);
1026 /* The LWA instruction uses the DS-form instruction format which requires
1027 that the bottom two bits of the offset must be 0. The prefixed PLWA does
1028 not have this restriction. While the actual load from memory is 32-bits,
1029 we pass in DImode here to test for using a DS instruction. */
1030 if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS))
1033 if (GET_CODE (addr) == PRE_INC
1034 || GET_CODE (addr) == PRE_DEC
1035 || (GET_CODE (addr) == PRE_MODIFY
1036 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
1038 if (GET_CODE (addr) == LO_SUM
1039 && REG_P (XEXP (addr, 0))
1040 && GET_CODE (XEXP (addr, 1)) == CONST)
1041 addr = XEXP (XEXP (addr, 1), 0);
1042 if (GET_CODE (addr) != PLUS)
1044 offset = XEXP (addr, 1);
1045 if (!CONST_INT_P (offset))
1047 return INTVAL (offset) % 4 == 0;
1050 ;; Return 1 if the operand is a memory operand that has a valid address for
1051 ;; a DS-form instruction. I.e. the address has to be either just a register,
1052 ;; or register + const where the two low order bits of const are zero.
1053 (define_predicate "ds_form_mem_operand"
1054 (match_code "subreg,mem")
1056 if (!any_memory_operand (op, mode))
1059 rtx addr = XEXP (op, 0);
1061 return address_to_insn_form (addr, mode, NON_PREFIXED_DS) == INSN_FORM_DS;
1064 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
1065 (define_predicate "symbol_ref_operand"
1066 (and (match_code "symbol_ref")
1067 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
1068 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
1070 ;; Return 1 if op is an operand that can be loaded via the GOT.
1071 ;; or non-special register register field no cr0
1072 (define_predicate "got_operand"
1073 (match_code "symbol_ref,const,label_ref"))
1075 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
1076 ;; excluding labels involving addition.
1077 (define_predicate "got_no_const_operand"
1078 (match_code "symbol_ref,label_ref"))
1080 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
1081 (define_predicate "rs6000_tls_symbol_ref"
1082 (and (match_code "symbol_ref")
1083 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
1085 ;; Return 1 for the CONST_INT or UNSPEC second CALL operand.
1086 ;; Prevents unwanted substitution of the unspec got_reg arg.
1087 (define_predicate "unspec_tls"
1088 (match_code "const_int,unspec")
1090 if (CONST_INT_P (op))
1092 if (XINT (op, 1) == UNSPEC_TLSGD)
1093 return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx;
1094 if (XINT (op, 1) == UNSPEC_TLSLD)
1095 return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx;
1099 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1100 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
1101 (define_predicate "call_operand"
1102 (if_then_else (match_code "reg")
1103 (match_test "REGNO (op) == LR_REGNO
1104 || REGNO (op) == CTR_REGNO
1105 || !HARD_REGISTER_P (op)")
1106 (match_code "symbol_ref")))
1108 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1109 ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR.
1110 (define_predicate "indirect_call_operand"
1111 (match_code "reg,unspec")
1114 return (REGNO (op) == LR_REGNO
1115 || REGNO (op) == CTR_REGNO);
1116 if (GET_CODE (op) == UNSPEC)
1118 if (XINT (op, 1) != UNSPEC_PLTSEQ)
1120 op = XVECEXP (op, 0, 0);
1121 return REG_P (op) && REGNO (op) == CTR_REGNO;
1126 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1128 (define_predicate "current_file_function_operand"
1129 (and (match_code "symbol_ref")
1130 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1131 && (SYMBOL_REF_LOCAL_P (op)
1132 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1133 && !decl_replaceable_p (current_function_decl)))
1134 && !((DEFAULT_ABI == ABI_AIX
1135 || DEFAULT_ABI == ABI_ELFv2)
1136 && (SYMBOL_REF_EXTERNAL_P (op)
1137 || SYMBOL_REF_WEAK (op)))
1138 && !(DEFAULT_ABI == ABI_ELFv2
1139 && SYMBOL_REF_DECL (op) != NULL
1140 && TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL
1141 && (rs6000_fndecl_pcrel_p (SYMBOL_REF_DECL (op))
1142 != rs6000_pcrel_p ()))")))
1144 ;; Return 1 if this operand is a valid input for a move insn.
1145 (define_predicate "input_operand"
1146 (match_code "symbol_ref,const,reg,subreg,mem,
1147 const_double,const_wide_int,const_vector,const_int")
1149 /* Memory is always valid. */
1150 if (any_memory_operand (op, mode))
1153 /* For floating-point, easy constants are valid. */
1154 if (SCALAR_FLOAT_MODE_P (mode)
1155 && easy_fp_constant (op, mode))
1158 /* Allow any integer constant. */
1159 if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op))
1162 /* Allow easy vector constants. */
1163 if (GET_CODE (op) == CONST_VECTOR
1164 && easy_vector_constant (op, mode))
1167 /* For floating-point or multi-word mode, the only remaining valid type
1169 if (SCALAR_FLOAT_MODE_P (mode)
1170 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1171 return register_operand (op, mode);
1173 /* We don't allow moving the carry bit around. */
1174 if (ca_operand (op, mode))
1177 /* The only cases left are integral modes one word or smaller (we
1178 do not get called for MODE_CC values). These can be in any
1180 if (register_operand (op, mode))
1183 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1185 if (DEFAULT_ABI == ABI_V4
1186 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST)
1187 && small_data_operand (op, Pmode))
1193 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1194 (define_predicate "splat_input_operand"
1195 (match_code "reg,subreg,mem")
1201 else if (mode == DImode)
1203 else if (mode == SImode && TARGET_P9_VECTOR)
1205 else if (mode == SFmode && TARGET_P9_VECTOR)
1212 rtx addr = XEXP (op, 0);
1214 if (! volatile_ok && MEM_VOLATILE_P (op))
1217 if (lra_in_progress || reload_completed)
1218 return indexed_or_indirect_address (addr, vmode);
1220 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1222 return gpc_reg_operand (op, mode);
1225 ;; Return 1 if this operand is valid for a MMA assemble accumulator insn.
1226 (define_special_predicate "mma_assemble_input_operand"
1227 (match_test "(mode == V16QImode
1228 && (vsx_register_operand (op, mode)
1230 && (indexed_or_indirect_address (XEXP (op, 0), mode)
1231 || quad_address_p (XEXP (op, 0), mode, false)))))"))
1233 ;; Return 1 if this operand is valid for an MMA disassemble insn.
1234 (define_predicate "mma_disassemble_output_operand"
1235 (match_code "reg,subreg,mem")
1238 op = SUBREG_REG (op);
1242 return vsx_register_operand (op, mode);
1245 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1246 (define_predicate "rotate_mask_operator"
1247 (match_code "rotate,ashift,lshiftrt"))
1249 ;; Return true if operand is boolean operator.
1250 (define_predicate "boolean_operator"
1251 (match_code "and,ior,xor"))
1253 ;; Return true if operand is OR-form of boolean operator.
1254 (define_predicate "boolean_or_operator"
1255 (match_code "ior,xor"))
1257 ;; Return true if operand is an equality operator.
1258 (define_special_predicate "equality_operator"
1259 (match_code "eq,ne"))
1261 ;; Return 1 if OP is a comparison operation that is valid for a branch
1262 ;; instruction. We check the opcode against the mode of the CC value.
1263 ;; validate_condition_mode is an assertion.
1264 (define_predicate "branch_comparison_operator"
1265 (and (match_operand 0 "comparison_operator")
1266 (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1267 (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1268 (if_then_else (match_test "flag_finite_math_only")
1269 (match_code "lt,le,gt,ge,eq,ne,unordered,ordered")
1270 (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered"))
1271 (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne"))
1272 (match_test "validate_condition_mode (GET_CODE (op),
1273 GET_MODE (XEXP (op, 0))),
1276 ;; Return 1 if OP is a comparison that needs an extra instruction to do (a
1277 ;; crlogical or an extra branch).
1278 (define_predicate "extra_insn_branch_comparison_operator"
1279 (and (match_operand 0 "comparison_operator")
1280 (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1281 (match_code "ltgt,le,ge,unlt,ungt,uneq")
1282 (match_test "validate_condition_mode (GET_CODE (op),
1283 GET_MODE (XEXP (op, 0))),
1286 ;; Return 1 if OP is an unsigned comparison operator.
1287 (define_predicate "unsigned_comparison_operator"
1288 (match_code "ltu,gtu,leu,geu"))
1290 ;; Return 1 if OP is a signed comparison operator.
1291 (define_predicate "signed_comparison_operator"
1292 (match_code "lt,gt,le,ge"))
1294 ;; Return 1 if OP is a signed comparison or an equality operator.
1295 (define_predicate "signed_or_equality_comparison_operator"
1296 (ior (match_operand 0 "equality_operator")
1297 (match_operand 0 "signed_comparison_operator")))
1299 ;; Return 1 if OP is an unsigned comparison or an equality operator.
1300 (define_predicate "unsigned_or_equality_comparison_operator"
1301 (ior (match_operand 0 "equality_operator")
1302 (match_operand 0 "unsigned_comparison_operator")))
1304 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1305 ;; it must be a positive comparison.
1306 (define_predicate "scc_comparison_operator"
1307 (and (match_operand 0 "branch_comparison_operator")
1308 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1310 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1312 (define_predicate "scc_rev_comparison_operator"
1313 (and (match_operand 0 "branch_comparison_operator")
1314 (match_code "ne,le,ge,leu,geu,ordered")))
1316 ;; Return 1 if OP is a comparison operator suitable for floating point
1317 ;; vector/scalar comparisons that generate a -1/0 mask.
1318 (define_predicate "fpmask_comparison_operator"
1319 (match_code "eq,gt,ge"))
1321 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1322 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1323 ;; fpmask_comparison_operator).
1324 (define_predicate "invert_fpmask_comparison_operator"
1325 (match_code "ne,unlt,unle"))
1327 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1328 ;; comparisons that generate a -1/0 mask.
1329 (define_predicate "vecint_comparison_operator"
1330 (match_code "eq,gt,gtu"))
1332 ;; Return 1 if OP is a comparison operation that is valid for a branch
1333 ;; insn, which is true if the corresponding bit in the CC register is set.
1334 (define_predicate "branch_positive_comparison_operator"
1335 (and (match_operand 0 "branch_comparison_operator")
1336 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1338 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1340 (define_predicate "save_world_operation"
1341 (match_code "parallel")
1346 int count = XVECLEN (op, 0);
1352 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1353 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1356 for (i=1; i <= 18; i++)
1358 elt = XVECEXP (op, 0, index++);
1359 if (GET_CODE (elt) != SET
1360 || !MEM_P (SET_DEST (elt))
1361 || !memory_operand (SET_DEST (elt), DFmode)
1362 || !REG_P (SET_SRC (elt))
1363 || GET_MODE (SET_SRC (elt)) != DFmode)
1367 for (i=1; i <= 12; i++)
1369 elt = XVECEXP (op, 0, index++);
1370 if (GET_CODE (elt) != SET
1371 || !MEM_P (SET_DEST (elt))
1372 || !REG_P (SET_SRC (elt))
1373 || GET_MODE (SET_SRC (elt)) != V4SImode)
1377 for (i=1; i <= 19; i++)
1379 elt = XVECEXP (op, 0, index++);
1380 if (GET_CODE (elt) != SET
1381 || !MEM_P (SET_DEST (elt))
1382 || !memory_operand (SET_DEST (elt), Pmode)
1383 || !REG_P (SET_SRC (elt))
1384 || GET_MODE (SET_SRC (elt)) != Pmode)
1388 elt = XVECEXP (op, 0, index++);
1389 if (GET_CODE (elt) != SET
1390 || !MEM_P (SET_DEST (elt))
1391 || !memory_operand (SET_DEST (elt), Pmode)
1392 || !REG_P (SET_SRC (elt))
1393 || REGNO (SET_SRC (elt)) != CR2_REGNO
1394 || GET_MODE (SET_SRC (elt)) != Pmode)
1397 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1398 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1403 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1405 (define_predicate "restore_world_operation"
1406 (match_code "parallel")
1411 int count = XVECLEN (op, 0);
1417 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1418 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1419 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1422 elt = XVECEXP (op, 0, index++);
1423 if (GET_CODE (elt) != SET
1424 || !MEM_P (SET_SRC (elt))
1425 || !memory_operand (SET_SRC (elt), Pmode)
1426 || !REG_P (SET_DEST (elt))
1427 || REGNO (SET_DEST (elt)) != CR2_REGNO
1428 || GET_MODE (SET_DEST (elt)) != Pmode)
1431 for (i=1; i <= 19; i++)
1433 elt = XVECEXP (op, 0, index++);
1434 if (GET_CODE (elt) != SET
1435 || !MEM_P (SET_SRC (elt))
1436 || !memory_operand (SET_SRC (elt), Pmode)
1437 || !REG_P (SET_DEST (elt))
1438 || GET_MODE (SET_DEST (elt)) != Pmode)
1442 for (i=1; i <= 12; i++)
1444 elt = XVECEXP (op, 0, index++);
1445 if (GET_CODE (elt) != SET
1446 || !MEM_P (SET_SRC (elt))
1447 || !REG_P (SET_DEST (elt))
1448 || GET_MODE (SET_DEST (elt)) != V4SImode)
1452 for (i=1; i <= 18; i++)
1454 elt = XVECEXP (op, 0, index++);
1455 if (GET_CODE (elt) != SET
1456 || !MEM_P (SET_SRC (elt))
1457 || !memory_operand (SET_SRC (elt), DFmode)
1458 || !REG_P (SET_DEST (elt))
1459 || GET_MODE (SET_DEST (elt)) != DFmode)
1463 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1464 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1465 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1466 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1467 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1472 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1473 (define_predicate "vrsave_operation"
1474 (match_code "parallel")
1476 int count = XVECLEN (op, 0);
1477 unsigned int dest_regno, src_regno;
1481 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1482 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1483 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1484 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1487 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1488 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1490 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1493 for (i = 1; i < count; i++)
1495 rtx elt = XVECEXP (op, 0, i);
1497 if (GET_CODE (elt) != CLOBBER
1498 && GET_CODE (elt) != SET)
1505 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1506 (define_predicate "mfcr_operation"
1507 (match_code "parallel")
1509 int count = XVECLEN (op, 0);
1512 /* Perform a quick check so we don't blow up below. */
1514 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1515 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1516 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1519 for (i = 0; i < count; i++)
1521 rtx exp = XVECEXP (op, 0, i);
1526 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1528 if (!REG_P (src_reg)
1529 || GET_MODE (src_reg) != CCmode
1530 || ! CR_REGNO_P (REGNO (src_reg)))
1533 if (GET_CODE (exp) != SET
1534 || !REG_P (SET_DEST (exp))
1535 || GET_MODE (SET_DEST (exp)) != SImode
1536 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1538 unspec = SET_SRC (exp);
1539 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1541 if (GET_CODE (unspec) != UNSPEC
1542 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1543 || XVECLEN (unspec, 0) != 2
1544 || XVECEXP (unspec, 0, 0) != src_reg
1545 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1546 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1552 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1553 (define_predicate "mtcrf_operation"
1554 (match_code "parallel")
1556 int count = XVECLEN (op, 0);
1560 /* Perform a quick check so we don't blow up below. */
1562 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1563 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1564 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1566 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1568 if (!REG_P (src_reg)
1569 || GET_MODE (src_reg) != SImode
1570 || ! INT_REGNO_P (REGNO (src_reg)))
1573 for (i = 0; i < count; i++)
1575 rtx exp = XVECEXP (op, 0, i);
1579 if (GET_CODE (exp) != SET
1580 || !REG_P (SET_DEST (exp))
1581 || GET_MODE (SET_DEST (exp)) != CCmode
1582 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1584 unspec = SET_SRC (exp);
1585 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1587 if (GET_CODE (unspec) != UNSPEC
1588 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1589 || XVECLEN (unspec, 0) != 2
1590 || XVECEXP (unspec, 0, 0) != src_reg
1591 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1592 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1598 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1599 (define_predicate "crsave_operation"
1600 (match_code "parallel")
1602 int count = XVECLEN (op, 0);
1605 for (i = 1; i < count; i++)
1607 rtx exp = XVECEXP (op, 0, i);
1609 if (GET_CODE (exp) != USE
1610 || !REG_P (XEXP (exp, 0))
1611 || GET_MODE (XEXP (exp, 0)) != CCmode
1612 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1618 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1619 (define_predicate "lmw_operation"
1620 (match_code "parallel")
1622 int count = XVECLEN (op, 0);
1623 unsigned int dest_regno;
1625 unsigned int base_regno;
1626 HOST_WIDE_INT offset;
1629 /* Perform a quick check so we don't blow up below. */
1631 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1632 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1633 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
1636 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1637 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1640 || count != 32 - (int) dest_regno)
1643 if (legitimate_indirect_address_p (src_addr, 0))
1646 base_regno = REGNO (src_addr);
1647 if (base_regno == 0)
1650 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1652 offset = INTVAL (XEXP (src_addr, 1));
1653 base_regno = REGNO (XEXP (src_addr, 0));
1658 for (i = 0; i < count; i++)
1660 rtx elt = XVECEXP (op, 0, i);
1663 HOST_WIDE_INT newoffset;
1665 if (GET_CODE (elt) != SET
1666 || !REG_P (SET_DEST (elt))
1667 || GET_MODE (SET_DEST (elt)) != SImode
1668 || REGNO (SET_DEST (elt)) != dest_regno + i
1669 || !MEM_P (SET_SRC (elt))
1670 || GET_MODE (SET_SRC (elt)) != SImode)
1672 newaddr = XEXP (SET_SRC (elt), 0);
1673 if (legitimate_indirect_address_p (newaddr, 0))
1678 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1680 addr_reg = XEXP (newaddr, 0);
1681 newoffset = INTVAL (XEXP (newaddr, 1));
1685 if (REGNO (addr_reg) != base_regno
1686 || newoffset != offset + 4 * i)
1693 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1694 (define_predicate "stmw_operation"
1695 (match_code "parallel")
1697 int count = XVECLEN (op, 0);
1698 unsigned int src_regno;
1700 unsigned int base_regno;
1701 HOST_WIDE_INT offset;
1704 /* Perform a quick check so we don't blow up below. */
1706 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1707 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
1708 || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
1711 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1712 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1715 || count != 32 - (int) src_regno)
1718 if (legitimate_indirect_address_p (dest_addr, 0))
1721 base_regno = REGNO (dest_addr);
1722 if (base_regno == 0)
1725 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1727 offset = INTVAL (XEXP (dest_addr, 1));
1728 base_regno = REGNO (XEXP (dest_addr, 0));
1733 for (i = 0; i < count; i++)
1735 rtx elt = XVECEXP (op, 0, i);
1738 HOST_WIDE_INT newoffset;
1740 if (GET_CODE (elt) != SET
1741 || !REG_P (SET_SRC (elt))
1742 || GET_MODE (SET_SRC (elt)) != SImode
1743 || REGNO (SET_SRC (elt)) != src_regno + i
1744 || !MEM_P (SET_DEST (elt))
1745 || GET_MODE (SET_DEST (elt)) != SImode)
1747 newaddr = XEXP (SET_DEST (elt), 0);
1748 if (legitimate_indirect_address_p (newaddr, 0))
1753 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1755 addr_reg = XEXP (newaddr, 0);
1756 newoffset = INTVAL (XEXP (newaddr, 1));
1760 if (REGNO (addr_reg) != base_regno
1761 || newoffset != offset + 4 * i)
1768 ;; Return 1 if OP is a stack tie operand.
1769 (define_predicate "tie_operand"
1770 (match_code "parallel")
1772 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1773 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0))
1774 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1775 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1778 ;; Match a small code model toc reference (or medium and large
1779 ;; model toc references before reload).
1780 (define_predicate "small_toc_ref"
1781 (match_code "unspec,plus")
1783 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1786 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1790 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1791 ;; GPR registers on power8.
1792 (define_predicate "fusion_gpr_addis"
1793 (match_code "const_int,high,plus")
1795 HOST_WIDE_INT value;
1798 if (GET_CODE (op) == HIGH)
1801 if (CONST_INT_P (op))
1804 else if (GET_CODE (op) == PLUS
1805 && base_reg_operand (XEXP (op, 0), Pmode)
1806 && CONST_INT_P (XEXP (op, 1)))
1807 int_const = XEXP (op, 1);
1812 value = INTVAL (int_const);
1813 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1816 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1819 /* Power8 only does the fusion if the top 12 bits of the addis value are all
1821 return (IN_RANGE (value >> 16, -16, 15));
1824 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1825 ;; and loads to GPR registers on power8.
1826 (define_predicate "fusion_gpr_mem_load"
1827 (match_code "mem,sign_extend,zero_extend")
1829 rtx addr, base, offset;
1831 /* Handle sign/zero extend. */
1832 if (GET_CODE (op) == ZERO_EXTEND
1833 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1836 mode = GET_MODE (op);
1850 if (!TARGET_POWERPC64)
1854 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1860 addr = XEXP (op, 0);
1861 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1864 base = XEXP (addr, 0);
1865 if (!base_reg_operand (base, GET_MODE (base)))
1868 offset = XEXP (addr, 1);
1870 if (GET_CODE (addr) == PLUS)
1871 return satisfies_constraint_I (offset);
1873 else if (GET_CODE (addr) == LO_SUM)
1875 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1876 return small_toc_ref (offset, GET_MODE (offset));
1878 else if (TARGET_ELF && !TARGET_POWERPC64)
1879 return CONSTANT_P (offset);
1885 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1886 ;; memory field with both the addis and the memory offset. Sign extension
1887 ;; is not handled here, since lha and lwa are not fused.
1888 (define_predicate "fusion_addis_mem_combo_load"
1889 (match_code "mem,zero_extend")
1891 rtx addr, base, offset;
1893 /* Handle zero extend. */
1894 if (GET_CODE (op) == ZERO_EXTEND)
1897 mode = GET_MODE (op);
1910 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1911 separate instructions. */
1913 if (!TARGET_POWERPC64)
1917 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1923 addr = XEXP (op, 0);
1924 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1927 base = XEXP (addr, 0);
1928 if (!fusion_gpr_addis (base, GET_MODE (base)))
1931 offset = XEXP (addr, 1);
1932 if (GET_CODE (addr) == PLUS)
1933 return satisfies_constraint_I (offset);
1935 else if (GET_CODE (addr) == LO_SUM)
1937 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1938 return small_toc_ref (offset, GET_MODE (offset));
1940 else if (TARGET_ELF && !TARGET_POWERPC64)
1941 return CONSTANT_P (offset);
1948 ;; Return true if the operand is a PC-relative address of a local symbol or a
1949 ;; label that can be used directly in a memory operation.
1950 (define_predicate "pcrel_local_address"
1951 (match_code "label_ref,symbol_ref,const")
1953 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1954 return iform == INSN_FORM_PCREL_LOCAL;
1957 ;; Return true if the operand is a PC-relative external symbol whose address
1958 ;; can be loaded into a register.
1959 (define_predicate "pcrel_external_address"
1960 (match_code "symbol_ref,const")
1962 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1963 return iform == INSN_FORM_PCREL_EXTERNAL;
1966 ;; Return true if the address is PC-relative and the symbol is either local or
1968 (define_predicate "pcrel_local_or_external_address"
1969 (ior (match_operand 0 "pcrel_local_address")
1970 (match_operand 0 "pcrel_external_address")))
1972 ;; Return true if the operand is a memory address that uses a prefixed address.
1973 (define_predicate "prefixed_memory"
1976 return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT);
1979 ;; Return true if the operand is a valid memory operand with a D-form
1980 ;; address that could be merged with the load of a PC-relative external address
1981 ;; with the PCREL_OPT optimization. We don't check here whether or not the
1982 ;; offset needs to be used in a DS-FORM (bottom 2 bits 0) or DQ-FORM (bottom 4
1983 ;; bits 0) instruction.
1984 (define_predicate "d_form_memory"
1987 if (!memory_operand (op, mode))
1990 rtx addr = XEXP (op, 0);
1994 if (SUBREG_P (addr) && REG_P (SUBREG_REG (addr)))
1997 return !indexed_address (addr, mode);
2000 ;; Return 1 if this operand is valid as the index for vec_set.
2001 (define_predicate "vec_set_index_operand"
2002 (if_then_else (match_test "TARGET_VSX")
2003 (match_operand 0 "reg_or_cint_operand")
2004 (match_operand 0 "const_int_operand")))