1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C)
2005,
2006,
2007,
2008,
2009,
2010,
2011
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return
1 for anything except PARALLEL.
22 (define_predicate "any_operand"
23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
25 ;; Return
1 for any PARALLEL.
26 (define_predicate "any_parallel_operand"
27 (match_code "parallel"))
29 ;; Return
1 if op is COUNT register.
30 (define_predicate "count_register_operand"
31 (and (match_code "reg")
32 (match_test "REGNO (op) == CTR_REGNO
33 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
35 ;; Return
1 if op is an Altivec register.
36 (define_predicate "altivec_register_operand"
37 (and (match_operand
0 "register_operand")
38 (match_test "GET_CODE (op) != REG
39 || ALTIVEC_REGNO_P (REGNO (op))
40 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
42 ;; Return
1 if op is a VSX register.
43 (define_predicate "vsx_register_operand"
44 (and (match_operand
0 "register_operand")
45 (match_test "GET_CODE (op) != REG
46 || VSX_REGNO_P (REGNO (op))
47 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
49 ;; Return
1 if op is a vector register that operates on floating point vectors
50 ;; (either altivec or VSX).
51 (define_predicate "vfloat_operand"
52 (and (match_operand
0 "register_operand")
53 (match_test "GET_CODE (op) != REG
54 || VFLOAT_REGNO_P (REGNO (op))
55 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
57 ;; Return
1 if op is a vector register that operates on integer vectors
58 ;; (only altivec, VSX doesn't support integer vectors)
59 (define_predicate "vint_operand"
60 (and (match_operand
0 "register_operand")
61 (match_test "GET_CODE (op) != REG
62 || VINT_REGNO_P (REGNO (op))
63 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
65 ;; Return
1 if op is a vector register to do logical operations on (and, or,
67 (define_predicate "vlogical_operand"
68 (and (match_operand
0 "register_operand")
69 (match_test "GET_CODE (op) != REG
70 || VLOGICAL_REGNO_P (REGNO (op))
71 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
73 ;; Return
1 if op is the carry register.
74 (define_predicate "ca_operand"
75 (and (match_code "reg")
76 (match_test "CA_REGNO_P (REGNO (op))")))
78 ;; Return
1 if op is a signed
5-bit constant integer.
79 (define_predicate "s5bit_cint_operand"
80 (and (match_code "const_int")
81 (match_test "INTVAL (op) >= -
16 && INTVAL (op) <=
15")))
83 ;; Return
1 if op is a unsigned
5-bit constant integer.
84 (define_predicate "u5bit_cint_operand"
85 (and (match_code "const_int")
86 (match_test "INTVAL (op) >=
0 && INTVAL (op) <=
31")))
88 ;; Return
1 if op is a signed
8-bit constant integer.
89 ;; Integer multiplication complete more quickly
90 (define_predicate "s8bit_cint_operand"
91 (and (match_code "const_int")
92 (match_test "INTVAL (op) >= -
128 && INTVAL (op) <=
127")))
94 ;; Return
1 if op is a constant integer that can fit in a D field.
95 (define_predicate "short_cint_operand"
96 (and (match_code "const_int")
97 (match_test "satisfies_constraint_I (op)")))
99 ;; Return
1 if op is a constant integer that can fit in an unsigned D field.
100 (define_predicate "u_short_cint_operand"
101 (and (match_code "const_int")
102 (match_test "satisfies_constraint_K (op)")))
104 ;; Return
1 if op is a constant integer that cannot fit in a signed D field.
105 (define_predicate "non_short_cint_operand"
106 (and (match_code "const_int")
107 (match_test "(unsigned HOST_WIDE_INT)
108 (INTVAL (op) +
0x8000) >=
0x10000")))
110 ;; Return
1 if op is a positive constant integer that is an exact power of
2.
111 (define_predicate "exact_log2_cint_operand"
112 (and (match_code "const_int")
113 (match_test "INTVAL (op) >
0 && exact_log2 (INTVAL (op)) >=
0")))
115 ;; Match op =
0 or op =
1.
116 (define_predicate "const_0_to_1_operand"
117 (and (match_code "const_int")
118 (match_test "IN_RANGE (INTVAL (op),
0,
1)")))
120 ;; Match op =
2 or op =
3.
121 (define_predicate "const_2_to_3_operand"
122 (and (match_code "const_int")
123 (match_test "IN_RANGE (INTVAL (op),
2,
3)")))
125 ;; Return
1 if op is a register that is not special.
126 (define_predicate "gpc_reg_operand"
127 (and (match_operand
0 "register_operand")
128 (match_test "(GET_CODE (op) != REG
129 || (REGNO (op) >= ARG_POINTER_REGNUM
130 && !CA_REGNO_P (REGNO (op)))
131 || REGNO (op) < MQ_REGNO)
132 && !((TARGET_E500_DOUBLE || TARGET_SPE)
133 && invalid_e500_subreg (op, mode))")))
135 ;; Return
1 if op is a register that is a condition register field.
136 (define_predicate "cc_reg_operand"
137 (and (match_operand
0 "register_operand")
138 (match_test "GET_CODE (op) != REG
139 || REGNO (op) > LAST_VIRTUAL_REGISTER
140 || CR_REGNO_P (REGNO (op))")))
142 ;; Return
1 if op is a register that is a condition register field not cr0.
143 (define_predicate "cc_reg_not_cr0_operand"
144 (and (match_operand
0 "register_operand")
145 (match_test "GET_CODE (op) != REG
146 || REGNO (op) > LAST_VIRTUAL_REGISTER
147 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
149 ;; Return
1 if op is a register that is a condition register field and if generating microcode, not cr0.
150 (define_predicate "cc_reg_not_micro_cr0_operand"
151 (and (match_operand
0 "register_operand")
152 (match_test "GET_CODE (op) != REG
153 || REGNO (op) > LAST_VIRTUAL_REGISTER
154 || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
155 || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
157 ;; Return
1 if op is a constant integer valid for D field
158 ;; or non-special register register.
159 (define_predicate "reg_or_short_operand"
160 (if_then_else (match_code "const_int")
161 (match_operand
0 "short_cint_operand")
162 (match_operand
0 "gpc_reg_operand")))
164 ;; Return
1 if op is a constant integer valid whose negation is valid for
165 ;; D field or non-special register register.
166 ;; Do not allow a constant zero because all patterns that call this
167 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
168 ;; or equal to const, which does not work for zero.
169 (define_predicate "reg_or_neg_short_operand"
170 (if_then_else (match_code "const_int")
171 (match_test "satisfies_constraint_P (op)
172 && INTVAL (op) !=
0")
173 (match_operand
0 "gpc_reg_operand")))
175 ;; Return
1 if op is a constant integer valid for DS field
176 ;; or non-special register.
177 (define_predicate "reg_or_aligned_short_operand"
178 (if_then_else (match_code "const_int")
179 (and (match_operand
0 "short_cint_operand")
180 (match_test "!(INTVAL (op) &
3)"))
181 (match_operand
0 "gpc_reg_operand")))
183 ;; Return
1 if op is a constant integer whose high-order
16 bits are zero
184 ;; or non-special register.
185 (define_predicate "reg_or_u_short_operand"
186 (if_then_else (match_code "const_int")
187 (match_operand
0 "u_short_cint_operand")
188 (match_operand
0 "gpc_reg_operand")))
190 ;; Return
1 if op is any constant integer
191 ;; or non-special register.
192 (define_predicate "reg_or_cint_operand"
193 (ior (match_code "const_int")
194 (match_operand
0 "gpc_reg_operand")))
196 ;; Return
1 if op is a constant integer valid for addition
197 ;; or non-special register.
198 (define_predicate "reg_or_add_cint_operand"
199 (if_then_else (match_code "const_int")
200 (match_test "(HOST_BITS_PER_WIDE_INT ==
32
201 && (mode == SImode || INTVAL (op) <
0x7fff8000))
202 || ((unsigned HOST_WIDE_INT) (INTVAL (op) +
0x80008000)
203 < (unsigned HOST_WIDE_INT)
0x100000000ll)")
204 (match_operand
0 "gpc_reg_operand")))
206 ;; Return
1 if op is a constant integer valid for subtraction
207 ;; or non-special register.
208 (define_predicate "reg_or_sub_cint_operand"
209 (if_then_else (match_code "const_int")
210 (match_test "(HOST_BITS_PER_WIDE_INT ==
32
211 && (mode == SImode || - INTVAL (op) <
0x7fff8000))
212 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
214 ?
0x80000000 :
0x80008000))
215 < (unsigned HOST_WIDE_INT)
0x100000000ll)")
216 (match_operand
0 "gpc_reg_operand")))
218 ;; Return
1 if op is any
32-bit unsigned constant integer
219 ;; or non-special register.
220 (define_predicate "reg_or_logical_cint_operand"
221 (if_then_else (match_code "const_int")
222 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
224 || ((INTVAL (op) & GET_MODE_MASK (mode)
225 & (~ (unsigned HOST_WIDE_INT)
0xffffffff)) ==
0)")
226 (if_then_else (match_code "const_double")
227 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
229 && CONST_DOUBLE_HIGH (op) ==
0")
230 (match_operand
0 "gpc_reg_operand"))))
232 ;; Return
1 if operand is a CONST_DOUBLE that can be set in a register
233 ;; with no more than one instruction per word.
234 (define_predicate "easy_fp_constant"
235 (match_code "const_double")
240 if (GET_MODE (op) != mode
241 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
244 /* Consider all constants with -msoft-float to be easy. */
245 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
246 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
250 if (DECIMAL_FLOAT_MODE_P (mode))
253 /* If we are using V
.4 style PIC, consider all constants to be hard. */
254 if (flag_pic && DEFAULT_ABI == ABI_V4)
257 #ifdef TARGET_RELOCATABLE
258 /* Similarly if we are using -mrelocatable, consider all constants
260 if (TARGET_RELOCATABLE)
267 if (TARGET_E500_DOUBLE)
270 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
271 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
273 return (num_insns_constant_wide ((HOST_WIDE_INT) k[
0]) ==
1
274 && num_insns_constant_wide ((HOST_WIDE_INT) k[
1]) ==
1
275 && num_insns_constant_wide ((HOST_WIDE_INT) k[
2]) ==
1
276 && num_insns_constant_wide ((HOST_WIDE_INT) k[
3]) ==
1);
279 /* The constant
0.f is easy under VSX. */
280 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode))
283 /* Force constants to memory before reload to utilize
284 compress_float_constant.
285 Avoid this when flag_unsafe_math_optimizations is enabled
286 because RDIV division to reciprocal optimization is not able
287 to regenerate the division. */
288 if (TARGET_E500_DOUBLE
289 || (!reload_in_progress && !reload_completed
290 && !flag_unsafe_math_optimizations))
293 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
294 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
296 return (num_insns_constant_wide ((HOST_WIDE_INT) k[
0]) ==
1
297 && num_insns_constant_wide ((HOST_WIDE_INT) k[
1]) ==
1);
300 /* The constant
0.f is easy. */
301 if (op == CONST0_RTX (SFmode))
304 /* Force constants to memory before reload to utilize
305 compress_float_constant.
306 Avoid this when flag_unsafe_math_optimizations is enabled
307 because RDIV division to reciprocal optimization is not able
308 to regenerate the division. */
309 if (!reload_in_progress && !reload_completed
310 && !flag_unsafe_math_optimizations)
313 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
314 REAL_VALUE_TO_TARGET_SINGLE (rv, k[
0]);
316 return num_insns_constant_wide (k[
0]) ==
1;
319 return ((TARGET_POWERPC64
320 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) ==
0)
321 || (num_insns_constant (op, DImode) <=
2));
331 ;; Return
1 if the operand is a CONST_VECTOR and can be loaded into a
332 ;; vector register without using memory.
333 (define_predicate "easy_vector_constant"
334 (match_code "const_vector")
336 /* As the paired vectors are actually FPRs it seems that there is
337 no easy way to load a CONST_VECTOR without using memory. */
338 if (TARGET_PAIRED_FLOAT)
341 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
343 if (zero_constant (op, mode))
346 return easy_altivec_constant (op, mode);
349 if (SPE_VECTOR_MODE (mode))
352 if (zero_constant (op, mode))
354 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
357 /* Limit SPE vectors to
15 bits signed. These we can generate with:
362 I don't know how efficient it would be to allow bigger constants,
363 considering we'll have an extra 'ori' for every 'li'. I doubt
5
364 instructions is better than a
64-bit memory load, but I don't
365 have the e500 timing specs. */
366 if (mode == V2SImode)
368 cst = INTVAL (CONST_VECTOR_ELT (op,
0));
369 cst2 = INTVAL (CONST_VECTOR_ELT (op,
1));
370 return cst >= -
0x7fff && cst <=
0x7fff
371 && cst2 >= -
0x7fff && cst2 <=
0x7fff;
378 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
379 (define_predicate "easy_vector_constant_add_self"
380 (and (match_code "const_vector")
381 (and (match_test "TARGET_ALTIVEC")
382 (match_test "easy_altivec_constant (op, mode)")))
385 if (mode == V2DImode || mode == V2DFmode)
387 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) -
1);
388 val = ((val &
0xff) ^
0x80) -
0x80;
389 return EASY_VECTOR_15_ADD_SELF (val);
392 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
393 (define_predicate "easy_vector_constant_msb"
394 (and (match_code "const_vector")
395 (and (match_test "TARGET_ALTIVEC")
396 (match_test "easy_altivec_constant (op, mode)")))
399 if (mode == V2DImode || mode == V2DFmode)
401 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) -
1);
402 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
405 ;; Return
1 if operand is constant zero (scalars and vectors).
406 (define_predicate "zero_constant"
407 (and (match_code "const_int,const_double,const_vector")
408 (match_test "op == CONST0_RTX (mode)")))
410 ;; Return
1 if operand is
0.0.
411 ;; or non-special register register field no cr0
412 (define_predicate "zero_fp_constant"
413 (and (match_code "const_double")
414 (match_test "SCALAR_FLOAT_MODE_P (mode)
415 && op == CONST0_RTX (mode)")))
417 ;; Return
1 if the operand is in volatile memory. Note that during the
418 ;; RTL generation phase, memory_operand does not return TRUE for volatile
419 ;; memory references. So this function allows us to recognize volatile
420 ;; references where it's safe.
421 (define_predicate "volatile_mem_operand"
422 (and (and (match_code "mem")
423 (match_test "MEM_VOLATILE_P (op)"))
424 (if_then_else (match_test "reload_completed")
425 (match_operand
0 "memory_operand")
426 (if_then_else (match_test "reload_in_progress")
427 (match_test "strict_memory_address_p (mode, XEXP (op,
0))")
428 (match_test "memory_address_p (mode, XEXP (op,
0))")))))
430 ;; Return
1 if the operand is an offsettable memory operand.
431 (define_predicate "offsettable_mem_operand"
432 (and (match_operand
0 "memory_operand")
433 (match_test "offsettable_nonstrict_memref_p (op)")))
435 ;; Return
1 if the operand is a memory operand with an address divisible by
4
436 (define_predicate "word_offset_memref_operand"
437 (match_operand
0 "memory_operand")
439 /* Address inside MEM. */
442 /* Extract address from auto-inc/dec. */
443 if (GET_CODE (op) == PRE_INC
444 || GET_CODE (op) == PRE_DEC)
446 else if (GET_CODE (op) == PRE_MODIFY)
448 else if (GET_CODE (op) == LO_SUM
449 && GET_CODE (XEXP (op,
0)) == REG
450 && GET_CODE (XEXP (op,
1)) == CONST)
451 op = XEXP (XEXP (op,
1),
0);
453 return (GET_CODE (op) != PLUS
454 || GET_CODE (XEXP (op,
1)) != CONST_INT
455 || INTVAL (XEXP (op,
1)) %
4 ==
0);
458 ;; Return
1 if the operand is an indexed or indirect memory operand.
459 (define_predicate "indexed_or_indirect_operand"
463 if (VECTOR_MEM_ALTIVEC_P (mode)
464 && GET_CODE (op) == AND
465 && GET_CODE (XEXP (op,
1)) == CONST_INT
466 && INTVAL (XEXP (op,
1)) == -
16)
469 return indexed_or_indirect_address (op, mode);
472 ;; Return
1 if the operand is an indexed or indirect memory operand with an
473 ;; AND -
16 in it, used to recognize when we need to switch to Altivec loads
474 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
475 ;; while VSX uses the full address and traps)
476 (define_predicate "altivec_indexed_or_indirect_operand"
480 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
481 && GET_CODE (op) == AND
482 && GET_CODE (XEXP (op,
1)) == CONST_INT
483 && INTVAL (XEXP (op,
1)) == -
16)
484 return indexed_or_indirect_address (XEXP (op,
0), mode);
489 ;; Return
1 if the operand is an indexed or indirect address.
490 (define_special_predicate "indexed_or_indirect_address"
491 (and (match_test "REG_P (op)
492 || (GET_CODE (op) == PLUS
493 /* Omit testing REG_P (XEXP (op,
0)). */
494 && REG_P (XEXP (op,
1)))")
495 (match_operand
0 "address_operand")))
497 ;; Used for the destination of the fix_truncdfsi2 expander.
498 ;; If stfiwx will be used, the result goes to memory; otherwise,
499 ;; we're going to emit a store and a load of a subreg, so the dest is a
501 (define_predicate "fix_trunc_dest_operand"
502 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
503 (match_operand
0 "memory_operand")
504 (match_operand
0 "gpc_reg_operand")))
506 ;; Return
1 if the operand is either a non-special register or can be used
507 ;; as the operand of a
`mode' add insn.
508 (define_predicate "add_operand"
509 (if_then_else (match_code "const_int")
510 (match_test "satisfies_constraint_I (op)
511 || satisfies_constraint_L (op)")
512 (match_operand 0 "gpc_reg_operand")))
514 ;; Return 1 if OP is a constant but not a valid add_operand.
515 (define_predicate "non_add_cint_operand"
516 (and (match_code "const_int")
517 (match_test "!satisfies_constraint_I (op)
518 && !satisfies_constraint_L (op)")))
520 ;; Return 1 if the operand is a constant that can be used as the operand
522 (define_predicate "logical_const_operand"
523 (match_code "const_int,const_double")
525 HOST_WIDE_INT opl, oph;
527 if (GET_CODE (op) == CONST_INT)
529 opl = INTVAL (op) & GET_MODE_MASK (mode);
531 if (HOST_BITS_PER_WIDE_INT <= 32
532 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
535 else if (GET_CODE (op) == CONST_DOUBLE)
537 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
539 opl = CONST_DOUBLE_LOW (op);
540 oph = CONST_DOUBLE_HIGH (op);
547 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
548 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
551 ;; Return 1 if the operand is a non-special register or a constant that
552 ;; can be used as the operand of an OR or XOR.
553 (define_predicate "logical_operand"
554 (ior (match_operand 0 "gpc_reg_operand")
555 (match_operand 0 "logical_const_operand")))
557 ;; Return 1 if op is a constant that is not a logical operand, but could
558 ;; be split into one.
559 (define_predicate "non_logical_cint_operand"
560 (and (match_code "const_int,const_double")
561 (and (not (match_operand 0 "logical_operand"))
562 (match_operand 0 "reg_or_logical_cint_operand"))))
564 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
565 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
566 ;; transitions). Reject all ones and all zeros, since these should have
567 ;; been optimized away and confuse the making of MB and ME.
568 (define_predicate "mask_operand"
569 (match_code "const_int")
571 HOST_WIDE_INT c, lsb;
575 if (TARGET_POWERPC64)
577 /* Fail if the mask is not 32-bit. */
578 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
581 /* Fail if the mask wraps around because the upper 32-bits of the
582 mask will all be 1s, contrary to GCC's internal view. */
583 if ((c & 0x80000001) == 0x80000001)
587 /* We don't change the number of transitions by inverting,
588 so make sure we start with the LS bit zero. */
592 /* Reject all zeros or all ones. */
596 /* Find the first transition. */
599 /* Invert to look for a second transition. */
602 /* Erase first transition. */
605 /* Find the second transition (if any). */
608 /* Match if all the bits above are 1's (or c is zero). */
612 ;; Return 1 for the PowerPC64 rlwinm corner case.
613 (define_predicate "mask_operand_wrap"
614 (match_code "const_int")
616 HOST_WIDE_INT c, lsb;
620 if ((c & 0x80000001) != 0x80000001)
634 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
635 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
636 ;; transition). Reject all zeros, since zero should have been
637 ;; optimized away and confuses the making of MB and ME.
638 (define_predicate "mask64_operand"
639 (match_code "const_int")
641 HOST_WIDE_INT c, lsb;
645 /* Reject all zeros. */
649 /* We don't change the number of transitions by inverting,
650 so make sure we start with the LS bit zero. */
654 /* Find the first transition. */
657 /* Match if all the bits above are 1's (or c is zero). */
661 ;; Like mask64_operand, but allow up to three transitions. This
662 ;; predicate is used by insn patterns that generate two rldicl or
663 ;; rldicr machine insns.
664 (define_predicate "mask64_2_operand"
665 (match_code "const_int")
667 HOST_WIDE_INT c, lsb;
671 /* Disallow all zeros. */
675 /* We don't change the number of transitions by inverting,
676 so make sure we start with the LS bit zero. */
680 /* Find the first transition. */
683 /* Invert to look for a second transition. */
686 /* Erase first transition. */
689 /* Find the second transition. */
692 /* Invert to look for a third transition. */
695 /* Erase second transition. */
698 /* Find the third transition (if any). */
701 /* Match if all the bits above are 1's (or c is zero). */
705 ;; Like and_operand, but also match constants that can be implemented
706 ;; with two rldicl or rldicr insns.
707 (define_predicate "and64_2_operand"
708 (ior (match_operand 0 "mask64_2_operand")
709 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
710 (match_operand 0 "gpc_reg_operand")
711 (match_operand 0 "logical_operand"))))
713 ;; Return 1 if the operand is either a non-special register or a
714 ;; constant that can be used as the operand of a logical AND.
715 (define_predicate "and_operand"
716 (ior (match_operand 0 "mask_operand")
717 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
718 (match_operand 0 "mask64_operand"))
719 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
720 (match_operand 0 "gpc_reg_operand")
721 (match_operand 0 "logical_operand")))))
723 ;; Return 1 if the operand is either a logical operand or a short cint operand.
724 (define_predicate "scc_eq_operand"
725 (ior (match_operand 0 "logical_operand")
726 (match_operand 0 "short_cint_operand")))
728 ;; Return 1 if the operand is a general non-special register or memory operand.
729 (define_predicate "reg_or_mem_operand"
730 (ior (match_operand 0 "memory_operand")
731 (ior (and (match_code "mem")
732 (match_test "macho_lo_sum_memory_operand (op, mode)"))
733 (ior (match_operand 0 "volatile_mem_operand")
734 (match_operand 0 "gpc_reg_operand")))))
736 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
737 (define_predicate "reg_or_none500mem_operand"
738 (if_then_else (match_code "mem")
739 (and (match_test "!TARGET_E500_DOUBLE")
740 (ior (match_operand 0 "memory_operand")
741 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
742 (match_operand 0 "volatile_mem_operand"))))
743 (match_operand 0 "gpc_reg_operand")))
745 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
746 (define_predicate "zero_reg_mem_operand"
747 (ior (match_operand 0 "zero_fp_constant")
748 (match_operand 0 "reg_or_mem_operand")))
750 ;; Return 1 if the operand is a general register or memory operand without
751 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
753 (define_predicate "lwa_operand"
754 (match_code "reg,subreg,mem")
756 rtx inner, addr, offset;
759 if (reload_completed && GET_CODE (inner) == SUBREG)
760 inner = SUBREG_REG (inner);
762 if (gpc_reg_operand (inner, mode))
764 if (!memory_operand (inner, mode))
766 addr = XEXP (inner, 0);
767 if (GET_CODE (addr) == PRE_INC
768 || GET_CODE (addr) == PRE_DEC
769 || (GET_CODE (addr) == PRE_MODIFY
770 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
772 if (GET_CODE (addr) == LO_SUM
773 && GET_CODE (XEXP (addr, 0)) == REG
774 && GET_CODE (XEXP (addr, 1)) == CONST)
775 addr = XEXP (XEXP (addr, 1), 0);
776 if (GET_CODE (addr) != PLUS)
778 offset = XEXP (addr, 1);
779 if (GET_CODE (offset) != CONST_INT)
781 return INTVAL (offset) % 4 == 0;
784 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
785 (define_predicate "symbol_ref_operand"
786 (and (match_code "symbol_ref")
787 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
788 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
790 ;; Return 1 if op is an operand that can be loaded via the GOT.
791 ;; or non-special register register field no cr0
792 (define_predicate "got_operand"
793 (match_code "symbol_ref,const,label_ref"))
795 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
796 ;; excluding labels involving addition.
797 (define_predicate "got_no_const_operand"
798 (match_code "symbol_ref,label_ref"))
800 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
801 (define_predicate "rs6000_tls_symbol_ref"
802 (and (match_code "symbol_ref")
803 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
805 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
806 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
807 (define_predicate "call_operand"
808 (if_then_else (match_code "reg")
809 (match_test "REGNO (op) == LR_REGNO
810 || REGNO (op) == CTR_REGNO
811 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
812 (match_code "symbol_ref")))
814 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
816 (define_predicate "current_file_function_operand"
817 (and (match_code "symbol_ref")
818 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
819 && ((SYMBOL_REF_LOCAL_P (op)
820 && (DEFAULT_ABI != ABI_AIX
821 || !SYMBOL_REF_EXTERNAL_P (op)))
822 || (op == XEXP (DECL_RTL (current_function_decl),
825 ;; Return 1 if this operand is a valid input for a move insn.
826 (define_predicate "input_operand"
827 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
828 const_double,const_vector,const_int,plus")
830 /* Memory is always valid. */
831 if (memory_operand (op, mode))
834 /* For floating-point, easy constants are valid. */
835 if (SCALAR_FLOAT_MODE_P (mode)
837 && easy_fp_constant (op, mode))
840 /* Allow any integer constant. */
841 if (GET_MODE_CLASS (mode) == MODE_INT
842 && (GET_CODE (op) == CONST_INT
843 || GET_CODE (op) == CONST_DOUBLE))
846 /* Allow easy vector constants. */
847 if (GET_CODE (op) == CONST_VECTOR
848 && easy_vector_constant (op, mode))
851 /* Do not allow invalid E500 subregs. */
852 if ((TARGET_E500_DOUBLE || TARGET_SPE)
853 && GET_CODE (op) == SUBREG
854 && invalid_e500_subreg (op, mode))
857 /* For floating-point or multi-word mode, the only remaining valid type
859 if (SCALAR_FLOAT_MODE_P (mode)
860 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
861 return register_operand (op, mode);
863 /* The only cases left are integral modes one word or smaller (we
864 do not get called for MODE_CC values). These can be in any
866 if (register_operand (op, mode))
869 /* A SYMBOL_REF referring to the TOC is valid. */
870 if (legitimate_constant_pool_address_p (op, mode, false))
873 /* A constant pool expression (relative to the TOC) is valid */
874 if (toc_relative_expr_p (op))
877 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
879 if (DEFAULT_ABI == ABI_V4
880 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
881 && small_data_operand (op, Pmode))
887 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
888 (define_predicate "splat_input_operand"
889 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
890 const_double,const_vector,const_int,plus")
896 else if (mode == DImode)
901 return input_operand (op, mode);
904 ;; Return true if OP is an invalid SUBREG operation on the e500.
905 (define_predicate "rs6000_nonimmediate_operand"
906 (match_code "reg,subreg,mem")
908 if ((TARGET_E500_DOUBLE || TARGET_SPE)
909 && GET_CODE (op) == SUBREG
910 && invalid_e500_subreg (op, mode))
913 return nonimmediate_operand (op, mode);
916 ;; Return true if operand is boolean operator.
917 (define_predicate "boolean_operator"
918 (match_code "and,ior,xor"))
920 ;; Return true if operand is OR-form of boolean operator.
921 (define_predicate "boolean_or_operator"
922 (match_code "ior,xor"))
924 ;; Return true if operand is an equality operator.
925 (define_special_predicate "equality_operator"
926 (match_code "eq,ne"))
928 ;; Return true if operand is MIN or MAX operator.
929 (define_predicate "min_max_operator"
930 (match_code "smin,smax,umin,umax"))
932 ;; Return 1 if OP is a comparison operation that is valid for a branch
933 ;; instruction. We check the opcode against the mode of the CC value.
934 ;; validate_condition_mode is an assertion.
935 (define_predicate "branch_comparison_operator"
936 (and (match_operand 0 "comparison_operator")
937 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
938 (match_test "validate_condition_mode (GET_CODE (op),
939 GET_MODE (XEXP (op, 0))),
942 (define_predicate "rs6000_cbranch_operator"
943 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS")
944 (match_operand 0 "ordered_comparison_operator")
945 (match_operand 0 "comparison_operator")))
947 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
948 ;; it must be a positive comparison.
949 (define_predicate "scc_comparison_operator"
950 (and (match_operand 0 "branch_comparison_operator")
951 (match_code "eq,lt,gt,ltu,gtu,unordered")))
953 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
955 (define_predicate "scc_rev_comparison_operator"
956 (and (match_operand 0 "branch_comparison_operator")
957 (match_code "ne,le,ge,leu,geu,ordered")))
959 ;; Return 1 if OP is a comparison operation that is valid for a branch
960 ;; insn, which is true if the corresponding bit in the CC register is set.
961 (define_predicate "branch_positive_comparison_operator"
962 (and (match_operand 0 "branch_comparison_operator")
963 (match_code "eq,lt,gt,ltu,gtu,unordered")))
965 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
966 (define_predicate "load_multiple_operation"
967 (match_code "parallel")
969 int count = XVECLEN (op, 0);
970 unsigned int dest_regno;
974 /* Perform a quick check so we don't blow up below. */
976 || GET_CODE (XVECEXP (op, 0, 0)) != SET
977 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
978 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
981 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
982 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
984 for (i = 1; i < count; i++)
986 rtx elt = XVECEXP (op, 0, i);
988 if (GET_CODE (elt) != SET
989 || GET_CODE (SET_DEST (elt)) != REG
990 || GET_MODE (SET_DEST (elt)) != SImode
991 || REGNO (SET_DEST (elt)) != dest_regno + i
992 || GET_CODE (SET_SRC (elt)) != MEM
993 || GET_MODE (SET_SRC (elt)) != SImode
994 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
995 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
996 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
997 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1004 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
1005 ;; The second vector element is a CLOBBER.
1006 (define_predicate "store_multiple_operation"
1007 (match_code "parallel")
1009 int count = XVECLEN (op, 0) - 1;
1010 unsigned int src_regno;
1014 /* Perform a quick check so we don't blow up below. */
1016 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1017 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1018 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1021 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1022 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1024 for (i = 1; i < count; i++)
1026 rtx elt = XVECEXP (op, 0, i + 1);
1028 if (GET_CODE (elt) != SET
1029 || GET_CODE (SET_SRC (elt)) != REG
1030 || GET_MODE (SET_SRC (elt)) != SImode
1031 || REGNO (SET_SRC (elt)) != src_regno + i
1032 || GET_CODE (SET_DEST (elt)) != MEM
1033 || GET_MODE (SET_DEST (elt)) != SImode
1034 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1035 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1036 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1037 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1044 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1046 (define_predicate "save_world_operation"
1047 (match_code "parallel")
1052 int count = XVECLEN (op, 0);
1058 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1059 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1062 for (i=1; i <= 18; i++)
1064 elt = XVECEXP (op, 0, index++);
1065 if (GET_CODE (elt) != SET
1066 || GET_CODE (SET_DEST (elt)) != MEM
1067 || ! memory_operand (SET_DEST (elt), DFmode)
1068 || GET_CODE (SET_SRC (elt)) != REG
1069 || GET_MODE (SET_SRC (elt)) != DFmode)
1073 for (i=1; i <= 12; i++)
1075 elt = XVECEXP (op, 0, index++);
1076 if (GET_CODE (elt) != SET
1077 || GET_CODE (SET_DEST (elt)) != MEM
1078 || GET_CODE (SET_SRC (elt)) != REG
1079 || GET_MODE (SET_SRC (elt)) != V4SImode)
1083 for (i=1; i <= 19; i++)
1085 elt = XVECEXP (op, 0, index++);
1086 if (GET_CODE (elt) != SET
1087 || GET_CODE (SET_DEST (elt)) != MEM
1088 || ! memory_operand (SET_DEST (elt), Pmode)
1089 || GET_CODE (SET_SRC (elt)) != REG
1090 || GET_MODE (SET_SRC (elt)) != Pmode)
1094 elt = XVECEXP (op, 0, index++);
1095 if (GET_CODE (elt) != SET
1096 || GET_CODE (SET_DEST (elt)) != MEM
1097 || ! memory_operand (SET_DEST (elt), Pmode)
1098 || GET_CODE (SET_SRC (elt)) != REG
1099 || REGNO (SET_SRC (elt)) != CR2_REGNO
1100 || GET_MODE (SET_SRC (elt)) != Pmode)
1103 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1104 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1109 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1111 (define_predicate "restore_world_operation"
1112 (match_code "parallel")
1117 int count = XVECLEN (op, 0);
1123 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1124 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1125 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1126 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1129 elt = XVECEXP (op, 0, index++);
1130 if (GET_CODE (elt) != SET
1131 || GET_CODE (SET_SRC (elt)) != MEM
1132 || ! memory_operand (SET_SRC (elt), Pmode)
1133 || GET_CODE (SET_DEST (elt)) != REG
1134 || REGNO (SET_DEST (elt)) != CR2_REGNO
1135 || GET_MODE (SET_DEST (elt)) != Pmode)
1138 for (i=1; i <= 19; i++)
1140 elt = XVECEXP (op, 0, index++);
1141 if (GET_CODE (elt) != SET
1142 || GET_CODE (SET_SRC (elt)) != MEM
1143 || ! memory_operand (SET_SRC (elt), Pmode)
1144 || GET_CODE (SET_DEST (elt)) != REG
1145 || GET_MODE (SET_DEST (elt)) != Pmode)
1149 for (i=1; i <= 12; i++)
1151 elt = XVECEXP (op, 0, index++);
1152 if (GET_CODE (elt) != SET
1153 || GET_CODE (SET_SRC (elt)) != MEM
1154 || GET_CODE (SET_DEST (elt)) != REG
1155 || GET_MODE (SET_DEST (elt)) != V4SImode)
1159 for (i=1; i <= 18; i++)
1161 elt = XVECEXP (op, 0, index++);
1162 if (GET_CODE (elt) != SET
1163 || GET_CODE (SET_SRC (elt)) != MEM
1164 || ! memory_operand (SET_SRC (elt), DFmode)
1165 || GET_CODE (SET_DEST (elt)) != REG
1166 || GET_MODE (SET_DEST (elt)) != DFmode)
1170 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1171 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1172 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1173 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1174 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1179 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1180 (define_predicate "vrsave_operation"
1181 (match_code "parallel")
1183 int count = XVECLEN (op, 0);
1184 unsigned int dest_regno, src_regno;
1188 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1189 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1190 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1191 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1194 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1195 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1197 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1200 for (i = 1; i < count; i++)
1202 rtx elt = XVECEXP (op, 0, i);
1204 if (GET_CODE (elt) != CLOBBER
1205 && GET_CODE (elt) != SET)
1212 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1213 (define_predicate "mfcr_operation"
1214 (match_code "parallel")
1216 int count = XVECLEN (op, 0);
1219 /* Perform a quick check so we don't blow up below. */
1221 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1222 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1223 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1226 for (i = 0; i < count; i++)
1228 rtx exp = XVECEXP (op, 0, i);
1233 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1235 if (GET_CODE (src_reg) != REG
1236 || GET_MODE (src_reg) != CCmode
1237 || ! CR_REGNO_P (REGNO (src_reg)))
1240 if (GET_CODE (exp) != SET
1241 || GET_CODE (SET_DEST (exp)) != REG
1242 || GET_MODE (SET_DEST (exp)) != SImode
1243 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1245 unspec = SET_SRC (exp);
1246 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1248 if (GET_CODE (unspec) != UNSPEC
1249 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1250 || XVECLEN (unspec, 0) != 2
1251 || XVECEXP (unspec, 0, 0) != src_reg
1252 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1253 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1259 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1260 (define_predicate "mtcrf_operation"
1261 (match_code "parallel")
1263 int count = XVECLEN (op, 0);
1267 /* Perform a quick check so we don't blow up below. */
1269 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1270 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1271 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1273 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1275 if (GET_CODE (src_reg) != REG
1276 || GET_MODE (src_reg) != SImode
1277 || ! INT_REGNO_P (REGNO (src_reg)))
1280 for (i = 0; i < count; i++)
1282 rtx exp = XVECEXP (op, 0, i);
1286 if (GET_CODE (exp) != SET
1287 || GET_CODE (SET_DEST (exp)) != REG
1288 || GET_MODE (SET_DEST (exp)) != CCmode
1289 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1291 unspec = SET_SRC (exp);
1292 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1294 if (GET_CODE (unspec) != UNSPEC
1295 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1296 || XVECLEN (unspec, 0) != 2
1297 || XVECEXP (unspec, 0, 0) != src_reg
1298 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1299 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1305 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1306 (define_predicate "lmw_operation"
1307 (match_code "parallel")
1309 int count = XVECLEN (op, 0);
1310 unsigned int dest_regno;
1312 unsigned int base_regno;
1313 HOST_WIDE_INT offset;
1316 /* Perform a quick check so we don't blow up below. */
1318 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1319 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1320 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1323 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1324 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1327 || count != 32 - (int) dest_regno)
1330 if (legitimate_indirect_address_p (src_addr, 0))
1333 base_regno = REGNO (src_addr);
1334 if (base_regno == 0)
1337 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1339 offset = INTVAL (XEXP (src_addr, 1));
1340 base_regno = REGNO (XEXP (src_addr, 0));
1345 for (i = 0; i < count; i++)
1347 rtx elt = XVECEXP (op, 0, i);
1350 HOST_WIDE_INT newoffset;
1352 if (GET_CODE (elt) != SET
1353 || GET_CODE (SET_DEST (elt)) != REG
1354 || GET_MODE (SET_DEST (elt)) != SImode
1355 || REGNO (SET_DEST (elt)) != dest_regno + i
1356 || GET_CODE (SET_SRC (elt)) != MEM
1357 || GET_MODE (SET_SRC (elt)) != SImode)
1359 newaddr = XEXP (SET_SRC (elt), 0);
1360 if (legitimate_indirect_address_p (newaddr, 0))
1365 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1367 addr_reg = XEXP (newaddr, 0);
1368 newoffset = INTVAL (XEXP (newaddr, 1));
1372 if (REGNO (addr_reg) != base_regno
1373 || newoffset != offset + 4 * i)
1380 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1381 (define_predicate "stmw_operation"
1382 (match_code "parallel")
1384 int count = XVECLEN (op, 0);
1385 unsigned int src_regno;
1387 unsigned int base_regno;
1388 HOST_WIDE_INT offset;
1391 /* Perform a quick check so we don't blow up below. */
1393 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1394 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1395 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1398 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1399 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1402 || count != 32 - (int) src_regno)
1405 if (legitimate_indirect_address_p (dest_addr, 0))
1408 base_regno = REGNO (dest_addr);
1409 if (base_regno == 0)
1412 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1414 offset = INTVAL (XEXP (dest_addr, 1));
1415 base_regno = REGNO (XEXP (dest_addr, 0));
1420 for (i = 0; i < count; i++)
1422 rtx elt = XVECEXP (op, 0, i);
1425 HOST_WIDE_INT newoffset;
1427 if (GET_CODE (elt) != SET
1428 || GET_CODE (SET_SRC (elt)) != REG
1429 || GET_MODE (SET_SRC (elt)) != SImode
1430 || REGNO (SET_SRC (elt)) != src_regno + i
1431 || GET_CODE (SET_DEST (elt)) != MEM
1432 || GET_MODE (SET_DEST (elt)) != SImode)
1434 newaddr = XEXP (SET_DEST (elt), 0);
1435 if (legitimate_indirect_address_p (newaddr, 0))
1440 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1442 addr_reg = XEXP (newaddr, 0);
1443 newoffset = INTVAL (XEXP (newaddr, 1));
1447 if (REGNO (addr_reg) != base_regno
1448 || newoffset != offset + 4 * i)