1 ;;- Machine description for the pdp11 for GNU C compiler
2 ;; Copyright (C)
1994,
1995,
1997,
1998,
1999,
2000
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version
2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
21 ;; Boston, MA
02111-
1307, USA.
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
30 ;;- updates for most instructions.
32 ;;- Operand classes for the register allocator:
34 ;; Compare instructions.
36 ;; currently we only support df floats, which saves us quite some
37 ;; hassle switching the FP mode!
38 ;; we assume that CPU is always in long float mode, and
39 ;;
16 bit integer mode - currently, the prologue for main does this,
40 ;; but maybe we should just set up a NEW crt0 properly,
41 ;; -- and what about signal handling code?
42 ;; (we don't even let sf floats in the register file, so
43 ;; we only should have to worry about truncating and widening
44 ;; when going to memory)
46 ;; abort() call by g++ - must define libfunc for cmp_optab
47 ;; and ucmp_optab for mode SImode, because we don't have that!!!
48 ;; - yet since no libfunc is there, we abort ()
50 ;; The only thing that remains to be done then is output
51 ;; the floats in a way the assembler can handle it (and
52 ;; if you're really into it, use a PDP11 float emulation
53 ;; library to do floating point constant folding - but
54 ;; I guess you'll get reasonable results even when not
56 ;; the last thing to do is fix the UPDATE_CC macro to check
57 ;; for floating point condition codes, and set cc_status
58 ;; properly, also setting the CC_IN_FCCR flag.
61 ;; currently type is only fpu or arith or unknown, maybe branch later ?
63 (define_attr "type" "unknown,arith,fp" (const_string "arith"))
65 ;; length default is
1 word each
66 (define_attr "length" "" (const_int
1))
68 ;; a user's asm statement
69 (define_asm_attributes
70 [(set_attr "type" "unknown")
71 ; all bets are off how long it is - make it
256, forces long jumps
72 ; whenever jumping around it !!!
73 (set_attr "length" "
256")])
75 ;; define function units
77 ;; arithmetic - values here immediately when next insn issued
78 ;; or does it mean the number of cycles after this insn was issued?
79 ;; how do I say that fpu insns use cpu also? (pre-interaction phase)
81 ;(define_function_unit "cpu"
1 1 (eq_attr "type" "arith")
0 0)
82 ;(define_function_unit "fpu"
1 1 (eq_attr "type" "fp")
0 0)
87 (compare (match_operand:DF
0 "general_operand" "fR,Q,F")
88 (match_operand:DF
1 "register_operand" "a,a,a")))]
92 cc_status.flags = CC_IN_FPU;
93 return
\"{cmpd|cmpf} %
0, %
1\;cfcc
\";
95 [(set_attr "length" "
2,
3,
6")])
97 ;; a bit of brain damage, maybe inline later -
98 ;; problem is - gcc seems to NEED SImode because
99 ;; of the cmp weirdness - maybe change gcc to handle this?
101 (define_expand "cmpsi"
103 (match_operand:SI
0 "general_operand" "g"))
105 (match_operand:SI
1 "general_operand" "g"))
106 (parallel [(set (cc0)
109 (clobber (reg:SI
0))])]
110 "
0" ;; disable for test
113 ;; check for next insn for branch code - does this still
120 (clobber (reg:SI
0))]
124 rtx br_insn = NEXT_INSN (insn);
127 if (GET_CODE (br_insn) != JUMP_INSN)
129 br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn),
1),
0));
138 return
\"jsr pc, ___ucmpsi\;cmp $
1,r0
\";
147 return
\"jsr pc, ___cmpsi\;tst r0
\";
154 [(set_attr "length" "
4")])
159 (compare (match_operand:HI
0 "general_operand" "rR,rR,Qi,Qi")
160 (match_operand:HI
1 "general_operand" "rR,Qi,rR,Qi")))]
163 [(set_attr "length" "
1,
2,
2,
3")])
167 (compare (match_operand:QI
0 "general_operand" "rR,rR,Qi,Qi")
168 (match_operand:QI
1 "general_operand" "rR,Qi,rR,Qi")))]
171 [(set_attr "length" "
1,
2,
2,
3")])
174 ;; We have to have this because cse can optimize the previous pattern
179 (match_operand:DF
0 "general_operand" "fR,Q"))]
183 cc_status.flags = CC_IN_FPU;
184 return
\"{tstd|tstf} %
0\;cfcc
\";
186 [(set_attr "length" "
2,
3")])
189 (define_expand "tstsi"
191 (match_operand:SI
0 "general_operand" "g"))
192 (parallel [(set (cc0)
194 (clobber (reg:SI
0))])]
195 "
0" ;; disable for test
201 (clobber (reg:SI
0))]
203 "jsr pc, ___tstsi\;tst r0"
204 [(set_attr "length" "
3")])
209 (match_operand:HI
0 "general_operand" "rR,Q"))]
212 [(set_attr "length" "
1,
2")])
216 (match_operand:QI
0 "general_operand" "rR,Q"))]
219 [(set_attr "length" "
1,
2")])
221 ;; sob instruction - we need an assembler which can make this instruction
222 ;; valid under _all_ circumstances!
227 (ne (plus:HI (match_operand:HI
0 "register_operand" "+r")
230 (label_ref (match_operand
1 "" ""))
233 (plus:HI (match_dup
0)
238 static int labelcount =
0;
239 static char buf[
1000];
241 if (get_attr_length (insn) ==
1)
242 return
\"sob %
0, %l1
\";
245 output_asm_insn (
\"dec %
0\", operands);
247 sprintf (buf,
\"bge LONG_SOB%d
\", labelcount);
248 output_asm_insn (buf, NULL);
250 output_asm_insn (
\"jmp %l1
\", operands);
252 sprintf (buf,
\"LONG_SOB%d:
\", labelcount++);
253 output_asm_insn (buf, NULL);
257 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
260 (ge (minus (match_dup
0)
266 ;; These control RTL generation for conditional jump insns
267 ;; and match them for register allocation.
269 ;; problem with too short jump distance! we need an assembler which can
270 ;; make this valid for all jump distances!
273 ;; these must be changed to check for CC_IN_FCCR if float is to be
278 (if_then_else (eq (cc0)
280 (label_ref (match_operand
0 "" ""))
283 "* return output_jump(
\"beq
\",
\"bne
\", get_attr_length(insn));"
284 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
287 (ge (minus (match_dup
0)
296 (if_then_else (ne (cc0)
298 (label_ref (match_operand
0 "" ""))
301 "* return output_jump(
\"bne
\",
\"beq
\", get_attr_length(insn));"
302 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
305 (ge (minus (match_dup
0)
313 (if_then_else (gt (cc0)
315 (label_ref (match_operand
0 "" ""))
318 "* return output_jump(
\"bgt
\",
\"ble
\", get_attr_length(insn));"
319 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
322 (ge (minus (match_dup
0)
330 (if_then_else (gtu (cc0)
332 (label_ref (match_operand
0 "" ""))
335 "* return output_jump(
\"bhi
\",
\"blos
\", get_attr_length(insn));"
336 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
339 (ge (minus (match_dup
0)
347 (if_then_else (lt (cc0)
349 (label_ref (match_operand
0 "" ""))
352 "* return output_jump(
\"blt
\",
\"bge
\", get_attr_length(insn));"
353 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
356 (ge (minus (match_dup
0)
365 (if_then_else (ltu (cc0)
367 (label_ref (match_operand
0 "" ""))
370 "* return output_jump(
\"blo
\",
\"bhis
\", get_attr_length(insn));"
371 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
374 (ge (minus (match_dup
0)
382 (if_then_else (ge (cc0)
384 (label_ref (match_operand
0 "" ""))
387 "* return output_jump(
\"bge
\",
\"blt
\", get_attr_length(insn));"
388 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
391 (ge (minus (match_dup
0)
399 (if_then_else (geu (cc0)
401 (label_ref (match_operand
0 "" ""))
404 "* return output_jump(
\"bhis
\",
\"blo
\", get_attr_length(insn));"
405 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
408 (ge (minus (match_dup
0)
416 (if_then_else (le (cc0)
418 (label_ref (match_operand
0 "" ""))
421 "* return output_jump(
\"ble
\",
\"bgt
\", get_attr_length(insn));"
422 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
425 (ge (minus (match_dup
0)
433 (if_then_else (leu (cc0)
435 (label_ref (match_operand
0 "" ""))
438 "* return output_jump(
\"blos
\",
\"bhi
\", get_attr_length(insn));"
439 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
442 (ge (minus (match_dup
0)
449 ;; These match inverted jump insns for register allocation.
453 (if_then_else (eq (cc0)
456 (label_ref (match_operand
0 "" ""))))]
458 "* return output_jump(
\"bne
\",
\"beq
\", get_attr_length(insn));"
459 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
462 (ge (minus (match_dup
0)
470 (if_then_else (ne (cc0)
473 (label_ref (match_operand
0 "" ""))))]
475 "* return output_jump(
\"beq
\",
\"bne
\", get_attr_length(insn));"
476 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
479 (ge (minus (match_dup
0)
487 (if_then_else (gt (cc0)
490 (label_ref (match_operand
0 "" ""))))]
492 "* return output_jump(
\"ble
\",
\"bgt
\", get_attr_length(insn));"
493 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
496 (ge (minus (match_dup
0)
504 (if_then_else (gtu (cc0)
507 (label_ref (match_operand
0 "" ""))))]
509 "* return output_jump(
\"blos
\",
\"bhi
\", get_attr_length(insn));"
510 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
513 (ge (minus (match_dup
0)
521 (if_then_else (lt (cc0)
524 (label_ref (match_operand
0 "" ""))))]
526 "* return output_jump(
\"bge
\",
\"blt
\", get_attr_length(insn));"
527 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
530 (ge (minus (match_dup
0)
538 (if_then_else (ltu (cc0)
541 (label_ref (match_operand
0 "" ""))))]
543 "* return output_jump(
\"bhis
\",
\"blo
\", get_attr_length(insn));"
544 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
547 (ge (minus (match_dup
0)
555 (if_then_else (ge (cc0)
558 (label_ref (match_operand
0 "" ""))))]
560 "* return output_jump(
\"blt
\",
\"bge
\", get_attr_length(insn));"
561 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
564 (ge (minus (match_dup
0)
572 (if_then_else (geu (cc0)
575 (label_ref (match_operand
0 "" ""))))]
577 "* return output_jump(
\"blo
\",
\"bhis
\", get_attr_length(insn));"
578 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
581 (ge (minus (match_dup
0)
589 (if_then_else (le (cc0)
592 (label_ref (match_operand
0 "" ""))))]
594 "* return output_jump(
\"bgt
\",
\"ble
\", get_attr_length(insn));"
595 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
598 (ge (minus (match_dup
0)
606 (if_then_else (leu (cc0)
609 (label_ref (match_operand
0 "" ""))))]
611 "* return output_jump(
\"bhi
\",
\"blos
\", get_attr_length(insn));"
612 [(set (attr "length") (if_then_else (ior (le (minus (match_dup
0)
615 (ge (minus (match_dup
0)
624 [(set (match_operand:DI
0 "general_operand" "=g")
625 (match_operand:DI
1 "general_operand" "g"))]
627 "* return output_move_quad (operands);"
628 ;; what's the mose expensive code - say twice movsi =
16
629 [(set_attr "length" "
16")])
632 [(set (match_operand:SI
0 "general_operand" "=r,r,r,rm,m")
633 (match_operand:SI
1 "general_operand" "rN,IJ,K,m,r"))]
635 "* return output_move_double (operands);"
636 ;; what's the most expensive code ? - I think
8!
637 ;; we could split it up and make several sub-cases...
638 [(set_attr "length" "
2,
3,
4,
8,
8")])
641 [(set (match_operand:HI
0 "general_operand" "=rR,rR,Q,Q")
642 (match_operand:HI
1 "general_operand" "rRN,Qi,rRN,Qi"))]
646 if (operands[
1] == const0_rtx)
649 return
\"mov %
1, %
0\";
651 [(set_attr "length" "
1,
2,
2,
3")])
654 [(set (match_operand:QI
0 "general_operand" "=rR,rR,Q,Q")
655 (match_operand:QI
1 "general_operand" "rRN,Qi,rRN,Qi"))]
659 if (operands[
1] == const0_rtx)
662 return
\"movb %
1, %
0\";
664 [(set_attr "length" "
1,
2,
2,
3")])
666 ;; do we have to supply all these moves? e.g. to
667 ;; NO_LOAD_FPU_REGs ?
669 [(set (match_operand:DF
0 "general_operand" "=f,R,f,Q,f,m")
670 (match_operand:DF
1 "general_operand" "fR,f,Q,f,F,m"))]
672 "* return output_move_quad (operands);"
674 [(set_attr "length" "
1,
1,
2,
2,
5,
16")])
677 [(set (match_operand:SF
0 "general_operand" "=g,r,g")
678 (match_operand:SF
1 "general_operand" "r,rmF,g"))]
680 "* return output_move_double (operands);"
681 [(set_attr "length" "
8,
8,
8")])
683 ;; maybe fiddle a bit with move_ratio, then
684 ;; let constraints only accept a register ...
686 (define_expand "movstrhi"
687 [(parallel [(set (match_operand:BLK
0 "general_operand" "=g,g")
688 (match_operand:BLK
1 "general_operand" "g,g"))
689 (use (match_operand:HI
2 "arith_operand" "n,&mr"))
690 (use (match_operand:HI
3 "immediate_operand" "i,i"))
691 (clobber (match_scratch:HI
4 "=&r,X"))
692 (clobber (match_dup
5))
693 (clobber (match_dup
6))
694 (clobber (match_dup
2))])]
695 "(TARGET_BCOPY_BUILTIN)"
699 = change_address (operands[
0], VOIDmode,
700 copy_to_mode_reg (Pmode, XEXP (operands[
0],
0)));
702 = change_address (operands[
1], VOIDmode,
703 copy_to_mode_reg (Pmode, XEXP (operands[
1],
0)));
705 operands[
5] = XEXP (operands[
0],
0);
706 operands[
6] = XEXP (operands[
1],
0);
710 (define_insn "" ; "movstrhi"
711 [(set (mem:BLK (match_operand:HI
0 "general_operand" "=r,r"))
712 (mem:BLK (match_operand:HI
1 "general_operand" "r,r")))
713 (use (match_operand:HI
2 "arith_operand" "n,&r"))
714 (use (match_operand:HI
3 "immediate_operand" "i,i"))
715 (clobber (match_scratch:HI
4 "=&r,X"))
716 (clobber (match_dup
0))
717 (clobber (match_dup
1))
718 (clobber (match_dup
2))]
719 "(TARGET_BCOPY_BUILTIN)"
720 "* return output_block_move (operands);"
722 [(set_attr "length" "
40")])
726 ;;- truncation instructions
728 (define_insn "truncdfsf2"
729 [(set (match_operand:SF
0 "general_operand" "=r,R,Q")
730 (float_truncate:SF (match_operand:DF
1 "register_operand" "a,a,a")))]
732 "* if (which_alternative ==
0)
734 output_asm_insn(
\"{stcdf|movfo} %
1, -(sp)
\", operands);
735 output_asm_insn(
\"mov (sp)+, %
0\", operands);
736 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0])+
1);
737 output_asm_insn(
\"mov (sp)+, %
0\", operands);
740 else if (which_alternative ==
1)
741 return
\"{stcdf|movfo} %
1, %
0\";
743 return
\"{stcdf|movfo} %
1, %
0\";
745 [(set_attr "length" "
3,
1,
2")])
748 (define_expand "truncsihi2"
749 [(set (match_operand:HI
0 "general_operand" "=g")
751 (match_operand:SI
1 "general_operand" "or")
757 ;;- zero extension instructions
759 (define_insn "zero_extendqihi2"
760 [(set (match_operand:HI
0 "general_operand" "=r")
761 (zero_extend:HI (match_operand:QI
1 "general_operand" "
0")))]
764 [(set_attr "length" "
2")])
766 (define_expand "zero_extendhisi2"
770 (match_operand:HI
1 "register_operand" "r"))
772 (match_operand:SI
0 "register_operand" "=r")
776 "/* operands[
1] = make_safe_from (operands[
1], operands[
0]); */")
779 ;;- sign extension instructions
781 (define_insn "extendsfdf2"
782 [(set (match_operand:DF
0 "register_operand" "=a,a,a")
783 (float_extend:DF (match_operand:SF
1 "general_operand" "r,R,Q")))]
786 mov %
1, -(sp)\;{ldcfd|movof} (sp)+,%
0
788 {ldcfd|movof} %
1, %
0"
789 [(set_attr "length" "
2,
1,
2")])
791 ;; does movb sign extend in register-to-register move?
792 (define_insn "extendqihi2"
793 [(set (match_operand:HI
0 "register_operand" "=r,r")
794 (sign_extend:HI (match_operand:QI
1 "general_operand" "rR,Q")))]
797 [(set_attr "length" "
1,
2")])
799 (define_insn "extendqisi2"
800 [(set (match_operand:SI
0 "register_operand" "=r,r")
801 (sign_extend:SI (match_operand:QI
1 "general_operand" "rR,Q")))]
807 /* make register pair available */
808 latehalf[
0] = operands[
0];
809 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0])+
1);
811 output_asm_insn(
\"movb %
1, %
0\", operands);
812 output_asm_insn(
\"sxt %
0\", latehalf);
816 [(set_attr "length" "
2,
3")])
818 ;; maybe we have to use define_expand to say that we have the instruction,
819 ;; unconditionally, and then match dependent on CPU type:
821 (define_expand "extendhisi2"
822 [(set (match_operand:SI
0 "general_operand" "=g")
823 (sign_extend:SI (match_operand:HI
1 "general_operand" "g")))]
827 (define_insn "" ; "extendhisi2"
828 [(set (match_operand:SI
0 "general_operand" "=o,<,r")
829 (sign_extend:SI (match_operand:HI
1 "general_operand" "g,g,g")))]
835 /* we don't want to mess with auto increment */
837 switch(which_alternative)
841 latehalf[
0] = operands[
0];
842 operands[
0] = adj_offsettable_operand(operands[
0],
2);
844 output_asm_insn(
\"mov %
1, %
0\", operands);
845 output_asm_insn(
\"sxt %
0\", latehalf);
851 /* - auto-decrement - right direction ;-) */
852 output_asm_insn(
\"mov %
1, %
0\", operands);
853 output_asm_insn(
\"sxt %
0\", operands);
859 /* make register pair available */
860 latehalf[
0] = operands[
0];
861 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
863 output_asm_insn(
\"mov %
1, %
0\", operands);
864 output_asm_insn(
\"sxt %
0\", latehalf);
873 [(set_attr "length" "
5,
3,
3")])
877 [(set (match_operand:SI
0 "register_operand" "=r")
878 (sign_extend:SI (match_operand:HI
1 "general_operand" "
0")))]
882 static int count =
0;
886 lateoperands[
0] = operands[
0];
887 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
889 output_asm_insn(
\"tst %
0\", operands);
890 sprintf(buf,
\"bge extendhisi%d
\", count);
891 output_asm_insn(buf, NULL);
892 output_asm_insn(
\"mov -
1, %
0\", lateoperands);
893 sprintf(buf,
\"bne extendhisi%d
\", count+
1);
894 output_asm_insn(buf, NULL);
895 sprintf(buf,
\"\\nextendhisi%d:
\", count);
896 output_asm_insn(buf, NULL);
897 output_asm_insn(
\"clr %
0\", lateoperands);
898 sprintf(buf,
\"\\nextendhisi%d:
\", count+
1);
899 output_asm_insn(buf, NULL);
905 [(set_attr "length" "
6")])
907 ;; make float to int and vice versa
908 ;; using the cc_status.flag field we could probably cut down
910 ;; assume that we are normally in double and integer mode -
911 ;; what do pdp library routines do to fpu mode ?
913 (define_insn "floatsidf2"
914 [(set (match_operand:DF
0 "register_operand" "=a,a,a")
915 (float:DF (match_operand:SI
1 "general_operand" "r,R,Q")))]
917 "* if (which_alternative ==
0)
922 latehalf[
1] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
923 output_asm_insn(
\"mov %
1, -(sp)
\", latehalf);
924 output_asm_insn(
\"mov %
1, -(sp)
\", operands);
926 output_asm_insn(
\"setl
\", operands);
927 output_asm_insn(
\"{ldcld|movif} (sp)+, %
0\", operands);
928 output_asm_insn(
\"seti
\", operands);
931 else if (which_alternative ==
1)
932 return
\"setl\;{ldcld|movif} %
1, %
0\;seti
\";
934 return
\"setl\;{ldcld|movif} %
1, %
0\;seti
\";
936 [(set_attr "length" "
5,
3,
4")])
938 (define_insn "floathidf2"
939 [(set (match_operand:DF
0 "register_operand" "=a,a")
940 (float:DF (match_operand:HI
1 "general_operand" "rR,Qi")))]
942 "{ldcid|movif} %
1, %
0"
943 [(set_attr "length" "
1,
2")])
946 (define_insn "fix_truncdfsi2"
947 [(set (match_operand:SI
0 "general_operand" "=r,R,Q")
948 (fix:SI (fix:DF (match_operand:DF
1 "register_operand" "a,a,a"))))]
950 "* if (which_alternative ==
0)
952 output_asm_insn(
\"setl
\", operands);
953 output_asm_insn(
\"{stcdl|movfi} %
1, -(sp)
\", operands);
954 output_asm_insn(
\"seti
\", operands);
955 output_asm_insn(
\"mov (sp)+, %
0\", operands);
956 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
957 output_asm_insn(
\"mov (sp)+, %
0\", operands);
960 else if (which_alternative ==
1)
961 return
\"setl\;{stcdl|movfi} %
1, %
0\;seti
\";
963 return
\"setl\;{stcdl|movfi} %
1, %
0\;seti
\";
965 [(set_attr "length" "
5,
3,
4")])
967 (define_insn "fix_truncdfhi2"
968 [(set (match_operand:HI
0 "general_operand" "=rR,Q")
969 (fix:HI (fix:DF (match_operand:DF
1 "register_operand" "a,a"))))]
971 "{stcdi|movfi} %
1, %
0"
972 [(set_attr "length" "
1,
2")])
975 ;;- arithmetic instructions
978 (define_insn "adddf3"
979 [(set (match_operand:DF
0 "register_operand" "=a,a,a")
980 (plus:DF (match_operand:DF
1 "register_operand" "%
0,
0,
0")
981 (match_operand:DF
2 "general_operand" "fR,Q,F")))]
984 [(set_attr "length" "
1,
2,
5")])
986 (define_insn "addsi3"
987 [(set (match_operand:SI
0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
988 (plus:SI (match_operand:SI
1 "general_operand" "%
0,
0,
0,
0,
0,
0,
0,
0,
0,
0")
989 (match_operand:SI
2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
992 { /* Here we trust that operands don't overlap
994 or is lateoperands the low word?? - looks like it! */
998 lateoperands[
0] = operands[
0];
1000 if (REG_P (operands[
0]))
1001 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
1003 operands[
0] = adj_offsettable_operand (operands[
0],
2);
1005 if (! CONSTANT_P(operands[
2]))
1007 lateoperands[
2] = operands[
2];
1009 if (REG_P (operands[
2]))
1010 operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
2]) +
1);
1012 operands[
2] = adj_offsettable_operand(operands[
2],
2);
1014 output_asm_insn (
\"add %
2, %
0\", operands);
1015 output_asm_insn (
\"adc %
0\", lateoperands);
1016 output_asm_insn (
\"add %
2, %
0\", lateoperands);
1020 lateoperands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
16) &
0xffff);
1021 operands[
2] = GEN_INT (INTVAL (operands[
2]) &
0xffff);
1023 if (INTVAL(operands[
2]))
1025 output_asm_insn (
\"add %
2, %
0\", operands);
1026 output_asm_insn (
\"adc %
0\", lateoperands);
1029 if (INTVAL(lateoperands[
2]))
1030 output_asm_insn (
\"add %
2, %
0\", lateoperands);
1034 [(set_attr "length" "
3,
5,
6,
8,
3,
1,
5,
5,
3,
8")])
1036 (define_insn "addhi3"
1037 [(set (match_operand:HI
0 "general_operand" "=rR,rR,Q,Q")
1038 (plus:HI (match_operand:HI
1 "general_operand" "%
0,
0,
0,
0")
1039 (match_operand:HI
2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
1043 if (GET_CODE (operands[
2]) == CONST_INT)
1045 if (INTVAL(operands[
2]) ==
1)
1047 else if (INTVAL(operands[
2]) == -
1)
1051 return
\"add %
2, %
0\";
1053 [(set_attr "length" "
1,
2,
2,
3")])
1055 (define_insn "addqi3"
1056 [(set (match_operand:QI
0 "general_operand" "=rR,rR,Q,Q")
1057 (plus:QI (match_operand:QI
1 "general_operand" "%
0,
0,
0,
0")
1058 (match_operand:QI
2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
1062 if (GET_CODE (operands[
2]) == CONST_INT)
1064 if (INTVAL(operands[
2]) ==
1)
1066 else if (INTVAL(operands[
2]) == -
1)
1070 return
\"addb %
2, %
0\";
1072 [(set_attr "length" "
1,
2,
2,
3")])
1075 ;;- subtract instructions
1076 ;; we don't have to care for constant second
1077 ;; args, since they are canonical plus:xx now!
1078 ;; also for minus:DF ??
1080 (define_insn "subdf3"
1081 [(set (match_operand:DF
0 "register_operand" "=a,a")
1082 (minus:DF (match_operand:DF
1 "register_operand" "
0,
0")
1083 (match_operand:DF
2 "general_operand" "fR,Q")))]
1085 "{subd|subf} %
2, %
0"
1086 [(set_attr "length" "
1,
2")])
1088 (define_insn "subsi3"
1089 [(set (match_operand:SI
0 "general_operand" "=r,r,o,o")
1090 (minus:SI (match_operand:SI
1 "general_operand" "
0,
0,
0,
0")
1091 (match_operand:SI
2 "general_operand" "r,o,r,o")))]
1094 { /* Here we trust that operands don't overlap
1096 or is lateoperands the low word?? - looks like it! */
1098 rtx lateoperands[
3];
1100 lateoperands[
0] = operands[
0];
1102 if (REG_P (operands[
0]))
1103 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
1105 operands[
0] = adj_offsettable_operand (operands[
0],
2);
1107 lateoperands[
2] = operands[
2];
1109 if (REG_P (operands[
2]))
1110 operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
2]) +
1);
1112 operands[
2] = adj_offsettable_operand(operands[
2],
2);
1114 output_asm_insn (
\"sub %
2, %
0\", operands);
1115 output_asm_insn (
\"sbc %
0\", lateoperands);
1116 output_asm_insn (
\"sub %
2, %
0\", lateoperands);
1119 ;; offsettable memory addresses always are expensive!!!
1120 [(set_attr "length" "
3,
5,
6,
8")])
1122 (define_insn "subhi3"
1123 [(set (match_operand:HI
0 "general_operand" "=rR,rR,Q,Q")
1124 (minus:HI (match_operand:HI
1 "general_operand" "
0,
0,
0,
0")
1125 (match_operand:HI
2 "general_operand" "rR,Qi,rR,Qi")))]
1129 if (GET_CODE (operands[
2]) == CONST_INT)
1132 return
\"sub %
2, %
0\";
1134 [(set_attr "length" "
1,
2,
2,
3")])
1136 (define_insn "subqi3"
1137 [(set (match_operand:QI
0 "general_operand" "=rR,rR,Q,Q")
1138 (minus:QI (match_operand:QI
1 "general_operand" "
0,
0,
0,
0")
1139 (match_operand:QI
2 "general_operand" "rR,Qi,rR,Qi")))]
1143 if (GET_CODE (operands[
2]) == CONST_INT)
1146 return
\"subb %
2, %
0\";
1148 [(set_attr "length" "
1,
2,
2,
3")])
1150 ;;;;- and instructions
1151 ;; Bit-and on the pdp (like on the vax) is done with a clear-bits insn.
1152 (define_expand "andsi3"
1153 [(set (match_operand:SI
0 "general_operand" "=g")
1154 (and:SI (match_operand:SI
1 "general_operand" "
0")
1155 (not:SI (match_operand:SI
2 "general_operand" "g"))))]
1159 extern rtx expand_unop ();
1160 if (GET_CODE (operands[
2]) == CONST_INT)
1161 operands[
2] = GEN_INT (~INTVAL (operands[
2]));
1163 operands[
2] = expand_unop (SImode, one_cmpl_optab, operands[
2],
0,
1);
1166 (define_expand "andhi3"
1167 [(set (match_operand:HI
0 "general_operand" "=g")
1168 (and:HI (match_operand:HI
1 "general_operand" "
0")
1169 (not:HI (match_operand:HI
2 "general_operand" "g"))))]
1173 extern rtx expand_unop ();
1174 if (GET_CODE (operands[
2]) == CONST_INT)
1175 operands[
2] = GEN_INT (~INTVAL (operands[
2]));
1177 operands[
2] = expand_unop (HImode, one_cmpl_optab, operands[
2],
0,
1);
1180 (define_expand "andqi3"
1181 [(set (match_operand:QI
0 "general_operand" "=g")
1182 (and:QI (match_operand:QI
1 "general_operand" "
0")
1183 (not:QI (match_operand:QI
2 "general_operand" "g"))))]
1187 extern rtx expand_unop ();
1188 rtx op = operands[
2];
1189 if (GET_CODE (op) == CONST_INT)
1190 operands[
2] = GEN_INT (((
1 <<
8) -
1) & ~INTVAL (op));
1192 operands[
2] = expand_unop (QImode, one_cmpl_optab, op,
0,
1);
1195 (define_insn "andcbsi3"
1196 [(set (match_operand:SI
0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
1197 (and:SI (match_operand:SI
1 "general_operand" "%
0,
0,
0,
0,
0,
0,
0,
0,
0,
0")
1198 (not:SI (match_operand:SI
2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))]
1201 { /* Here we trust that operands don't overlap
1203 or is lateoperands the low word?? - looks like it! */
1205 rtx lateoperands[
3];
1207 lateoperands[
0] = operands[
0];
1209 if (REG_P (operands[
0]))
1210 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
1212 operands[
0] = adj_offsettable_operand (operands[
0],
2);
1214 if (! CONSTANT_P(operands[
2]))
1216 lateoperands[
2] = operands[
2];
1218 if (REG_P (operands[
2]))
1219 operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
2]) +
1);
1221 operands[
2] = adj_offsettable_operand(operands[
2],
2);
1223 output_asm_insn (
\"bic %
2, %
0\", operands);
1224 output_asm_insn (
\"bic %
2, %
0\", lateoperands);
1228 lateoperands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
16) &
0xffff);
1229 operands[
2] = GEN_INT (INTVAL (operands[
2]) &
0xffff);
1231 /* these have different lengths, so we should have
1232 different constraints! */
1233 if (INTVAL(operands[
2]))
1234 output_asm_insn (
\"bic %
2, %
0\", operands);
1236 if (INTVAL(lateoperands[
2]))
1237 output_asm_insn (
\"bic %
2, %
0\", lateoperands);
1241 [(set_attr "length" "
2,
4,
4,
6,
2,
2,
4,
3,
3,
6")])
1243 (define_insn "andcbhi3"
1244 [(set (match_operand:HI
0 "general_operand" "=rR,rR,Q,Q")
1245 (and:HI (match_operand:HI
1 "general_operand" "
0,
0,
0,
0")
1246 (not:HI (match_operand:HI
2 "general_operand" "rR,Qi,rR,Qi"))))]
1249 [(set_attr "length" "
1,
2,
2,
3")])
1251 (define_insn "andcbqi3"
1252 [(set (match_operand:QI
0 "general_operand" "=rR,rR,Q,Q")
1253 (and:QI (match_operand:QI
1 "general_operand" "
0,
0,
0,
0")
1254 (not:QI (match_operand:QI
2 "general_operand" "rR,Qi,rR,Qi"))))]
1257 [(set_attr "length" "
1,
2,
2,
3")])
1259 ;;- Bit set (inclusive or) instructions
1260 (define_insn "iorsi3"
1261 [(set (match_operand:SI
0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
1262 (ior:SI (match_operand:SI
1 "general_operand" "%
0,
0,
0,
0,
0,
0,
0,
0,
0,
0")
1263 (match_operand:SI
2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
1266 { /* Here we trust that operands don't overlap
1268 or is lateoperands the low word?? - looks like it! */
1270 rtx lateoperands[
3];
1272 lateoperands[
0] = operands[
0];
1274 if (REG_P (operands[
0]))
1275 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
1277 operands[
0] = adj_offsettable_operand (operands[
0],
2);
1279 if (! CONSTANT_P(operands[
2]))
1281 lateoperands[
2] = operands[
2];
1283 if (REG_P (operands[
2]))
1284 operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
2]) +
1);
1286 operands[
2] = adj_offsettable_operand (operands[
2],
2);
1288 output_asm_insn (
\"bis %
2, %
0\", operands);
1289 output_asm_insn (
\"bis %
2, %
0\", lateoperands);
1293 lateoperands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
16) &
0xffff);
1294 operands[
2] = GEN_INT (INTVAL (operands[
2]) &
0xffff);
1296 /* these have different lengths, so we should have
1297 different constraints! */
1298 if (INTVAL(operands[
2]))
1299 output_asm_insn (
\"bis %
2, %
0\", operands);
1301 if (INTVAL(lateoperands[
2]))
1302 output_asm_insn (
\"bis %
2, %
0\", lateoperands);
1306 [(set_attr "length" "
2,
4,
4,
6,
2,
2,
4,
3,
3,
6")])
1308 (define_insn "iorhi3"
1309 [(set (match_operand:HI
0 "general_operand" "=rR,rR,Q,Q")
1310 (ior:HI (match_operand:HI
1 "general_operand" "%
0,
0,
0,
0")
1311 (match_operand:HI
2 "general_operand" "rR,Qi,rR,Qi")))]
1314 [(set_attr "length" "
1,
2,
2,
3")])
1316 (define_insn "iorqi3"
1317 [(set (match_operand:QI
0 "general_operand" "=rR,rR,Q,Q")
1318 (ior:QI (match_operand:QI
1 "general_operand" "%
0,
0,
0,
0")
1319 (match_operand:QI
2 "general_operand" "rR,Qi,rR,Qi")))]
1323 ;;- xor instructions
1324 (define_insn "xorsi3"
1325 [(set (match_operand:SI
0 "register_operand" "=r,r,r,r")
1326 (xor:SI (match_operand:SI
1 "register_operand" "%
0,
0,
0,
0")
1327 (match_operand:SI
2 "arith_operand" "r,I,J,K")))]
1330 { /* Here we trust that operands don't overlap */
1332 rtx lateoperands[
3];
1334 lateoperands[
0] = operands[
0];
1335 operands[
0] = gen_rtx_REG (HImode, REGNO (operands[
0]) +
1);
1337 if (REG_P(operands[
2]))
1339 lateoperands[
2] = operands[
2];
1340 operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
2]) +
1);
1342 output_asm_insn (
\"xor %
2, %
0\", operands);
1343 output_asm_insn (
\"xor %
2, %
0\", lateoperands);
1348 lateoperands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
16) &
0xffff);
1349 operands[
2] = GEN_INT (INTVAL(operands[
2]) &
0xffff);
1351 if (INTVAL (operands[
2]))
1352 output_asm_insn (
\"xor %
2, %
0\", operands);
1354 if (INTVAL (lateoperands[
2]))
1355 output_asm_insn (
\"xor %
2, %
0\", lateoperands);
1359 [(set_attr "length" "
2,
1,
1,
2")])
1361 (define_insn "xorhi3"
1362 [(set (match_operand:HI
0 "general_operand" "=rR,Q")
1363 (xor:HI (match_operand:HI
1 "general_operand" "%
0,
0")
1364 (match_operand:HI
2 "register_operand" "r,r")))]
1367 [(set_attr "length" "
1,
2")])
1369 ;;- one complement instructions
1371 (define_insn "one_cmplhi2"
1372 [(set (match_operand:HI
0 "general_operand" "=rR,Q")
1373 (not:HI (match_operand:HI
1 "general_operand" "
0,
0")))]
1376 [(set_attr "length" "
1,
2")])
1378 (define_insn "one_cmplqi2"
1379 [(set (match_operand:QI
0 "general_operand" "=rR,Q")
1380 (not:QI (match_operand:QI
1 "general_operand" "
0,
0")))]
1383 [(set_attr "length" "
1,
2")])
1385 ;;- arithmetic shift instructions
1386 (define_insn "ashlsi3"
1387 [(set (match_operand:SI
0 "register_operand" "=r,r")
1388 (ashift:SI (match_operand:SI
1 "register_operand" "
0,
0")
1389 (match_operand:HI
2 "general_operand" "rR,Qi")))]
1392 [(set_attr "length" "
1,
2")])
1394 ;; Arithmetic right shift on the pdp works by negating the shift count.
1395 (define_expand "ashrsi3"
1396 [(set (match_operand:SI
0 "register_operand" "=r")
1397 (ashift:SI (match_operand:SI
1 "register_operand" "
0")
1398 (match_operand:HI
2 "general_operand" "g")))]
1402 operands[
2] = negate_rtx (HImode, operands[
2]);
1405 ;; define asl aslb asr asrb - ashc missing!
1409 [(set (match_operand:HI
0 "general_operand" "=rR,Q")
1410 (ashift:HI (match_operand:HI
1 "general_operand" "
0,
0")
1414 [(set_attr "length" "
1,
2")])
1416 ;; and another possibility for asr is << -
1
1417 ;; might cause problems since -
1 can also be encoded as
65535!
1422 [(set (match_operand:HI
0 "general_operand" "=rR,Q")
1423 (ashift:HI (match_operand:HI
1 "general_operand" "
0,
0")
1427 [(set_attr "length" "
1,
2")])
1429 ;; shift is by arbitrary count is expensive,
1430 ;; shift by one cheap - so let's do that, if
1431 ;; space doesn't matter
1433 [(set (match_operand:HI
0 "general_operand" "=r")
1434 (ashift:HI (match_operand:HI
1 "general_operand" "
0")
1435 (match_operand:HI
2 "expand_shift_operand" "O")))]
1441 for (i =
1; i <= abs(INTVAL(operands[
2])); i++)
1442 if (INTVAL(operands[
2]) <
0)
1443 output_asm_insn(
\"asr %
0\", operands);
1445 output_asm_insn(
\"asl %
0\", operands);
1450 [(set (attr "length") (const_int
4))])
1454 [(set (match_operand:QI
0 "general_operand" "=r,o")
1455 (ashift:QI (match_operand:QI
1 "general_operand" "
0,
0")
1456 (match_operand:HI
2 "const_immediate_operand" "n,n")))]
1459 { /* allowing predec or post_inc is possible, but hairy! */
1462 cnt = INTVAL(operands[
2]) &
0x0007;
1464 for (i=
0 ; i < cnt ; i++)
1465 output_asm_insn(
\"aslb %
0\", operands);
1469 ;; set attribute length ( match_dup
2 &
7 ) *(
1 or
2) !!!
1470 [(set_attr_alternative "length"
1476 ; [(set (match_operand:HI
0 "general_operand" "=rR,Q")
1477 ; (ashiftrt:HI (match_operand:HI
1 "general_operand" "
0,
0")
1481 ; [(set_attr "length" "
1,
2")])
1485 [(set (match_operand:QI
0 "general_operand" "=r,o")
1486 (ashiftrt:QI (match_operand:QI
1 "general_operand" "
0,
0")
1487 (match_operand:HI
2 "const_immediate_operand" "n,n")))]
1490 { /* allowing predec or post_inc is possible, but hairy! */
1493 cnt = INTVAL(operands[
2]) &
0x0007;
1495 for (i=
0 ; i < cnt ; i++)
1496 output_asm_insn(
\"asrb %
0\", operands);
1500 [(set_attr_alternative "length"
1504 ;; the following is invalid - too complex!!! - just say
14 !!!
1505 ; [(set (attr "length") (plus (and (match_dup
2)
1507 ; (and (match_dup
2)
1508 ; (const_int
7))))])
1512 ;; can we get +-
1 in the next pattern? should
1513 ;; have been caught by previous patterns!
1515 (define_insn "ashlhi3"
1516 [(set (match_operand:HI
0 "register_operand" "=r,r")
1517 (ashift:HI (match_operand:HI
1 "register_operand" "
0,
0")
1518 (match_operand:HI
2 "general_operand" "rR,Qi")))]
1522 if (GET_CODE(operands[
2]) == CONST_INT)
1524 if (INTVAL(operands[
2]) ==
1)
1526 else if (INTVAL(operands[
2]) == -
1)
1530 return
\"ash %
2,%
0\";
1532 [(set_attr "length" "
1,
2")])
1534 ;; Arithmetic right shift on the pdp works by negating the shift count.
1535 (define_expand "ashrhi3"
1536 [(set (match_operand:HI
0 "register_operand" "=r")
1537 (ashift:HI (match_operand:HI
1 "register_operand" "
0")
1538 (match_operand:HI
2 "general_operand" "g")))]
1542 operands[
2] = negate_rtx (HImode, operands[
2]);
1545 ;;;;- logical shift instructions
1546 ;;(define_insn "lshrsi3"
1547 ;; [(set (match_operand:HI
0 "register_operand" "=r")
1548 ;; (lshiftrt:HI (match_operand:HI
1 "register_operand" "
0")
1549 ;; (match_operand:HI
2 "arith_operand" "rI")))]
1555 (define_insn "absdf2"
1556 [(set (match_operand:DF
0 "general_operand" "=fR,Q")
1557 (abs:DF (match_operand:DF
1 "general_operand" "
0,
0")))]
1560 [(set_attr "length" "
1,
2")])
1562 (define_insn "abshi2"
1563 [(set (match_operand:HI
0 "general_operand" "=r,o")
1564 (abs:HI (match_operand:HI
1 "general_operand" "
0,
0")))]
1565 "TARGET_ABSHI_BUILTIN"
1568 static int count =
0;
1571 output_asm_insn(
\"tst %
0\", operands);
1572 sprintf(buf,
\"bge abshi%d
\", count);
1573 output_asm_insn(buf, NULL);
1574 output_asm_insn(
\"neg %
0\", operands);
1575 sprintf(buf,
\"\\nabshi%d:
\", count++);
1576 output_asm_insn(buf, NULL);
1580 [(set_attr "length" "
3,
5")])
1583 ;; define expand abshi - is much better !!! - but
1584 ;; will it be optimized into an abshi2 ?
1585 ;; it will leave better code, because the tsthi might be
1587 ; -- just a thought - don't have time to check
1589 ;(define_expand "abshi2"
1590 ; [(match_operand:HI
0 "general_operand" "")
1591 ; (match_operand:HI
1 "general_operand" "")]
1595 ; rtx label = gen_label_rtx ();
1597 ; /* do I need this? */
1598 ; do_pending_stack_adjust ();
1600 ; emit_move_insn (operands[
0], operands[
1]);
1602 ; emit_insn (gen_tsthi (operands[
0]));
1603 ; emit_insn (gen_bge (label1));
1605 ; emit_insn (gen_neghi(operands[
0], operands[
0])
1609 ; emit_label (label);
1611 ; /* allow REG_NOTES to be set on last insn (labels don't have enough
1612 ; fields, and can't be used for REG_NOTES anyway). */
1613 ; emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
1619 (define_insn "negdf2"
1620 [(set (match_operand:DF
0 "general_operand" "=fR,Q")
1621 (neg:DF (match_operand:DF
1 "register_operand" "
0,
0")))]
1624 [(set_attr "length" "
1,
2")])
1626 (define_insn "neghi2"
1627 [(set (match_operand:HI
0 "general_operand" "=rR,Q")
1628 (neg:HI (match_operand:HI
1 "general_operand" "
0,
0")))]
1631 [(set_attr "length" "
1,
2")])
1633 (define_insn "negqi2"
1634 [(set (match_operand:QI
0 "general_operand" "=rR,Q")
1635 (neg:QI (match_operand:QI
1 "general_operand" "
0,
0")))]
1638 [(set_attr "length" "
1,
2")])
1641 ;; Unconditional and other jump instructions
1644 (label_ref (match_operand
0 "" "")))]
1647 [(set_attr "length" "
2")])
1651 (label_ref (match_operand
0 "" "")))
1652 (clobber (const_int
1))]
1655 [(set_attr "length" "
2")])
1657 (define_insn "tablejump"
1658 [(set (pc) (match_operand:HI
0 "general_operand" "rR,Q"))
1659 (use (label_ref (match_operand
1 "" "")))]
1662 [(set_attr "length" "
1,
2")])
1664 ;; indirect jump - let's be conservative!
1665 ;; allow only register_operand, even though we could also
1666 ;; allow labels etc.
1668 (define_insn "indirect_jump"
1669 [(set (pc) (match_operand:HI
0 "register_operand" "r"))]
1673 ;;- jump to subroutine
1676 [(call (match_operand:HI
0 "general_operand" "R,Q")
1677 (match_operand:HI
1 "general_operand" "g,g"))
1678 ;; (use (reg:HI
0)) what was that ???
1680 ;;- Don't use operand
1 for most machines.
1683 [(set_attr "length" "
1,
2")])
1685 ;;- jump to subroutine
1686 (define_insn "call_value"
1687 [(set (match_operand
0 "" "")
1688 (call (match_operand:HI
1 "general_operand" "R,Q")
1689 (match_operand:HI
2 "general_operand" "g,g")))
1690 ;; (use (reg:HI
0)) - what was that ????
1692 ;;- Don't use operand
2 for most machines.
1695 [(set_attr "length" "
1,
2")])
1706 (define_insn "muldf3"
1707 [(set (match_operand:DF
0 "register_operand" "=a,a,a")
1708 (mult:DF (match_operand:DF
1 "register_operand" "%
0,
0,
0")
1709 (match_operand:DF
2 "general_operand" "fR,Q,F")))]
1711 "{muld|mulf} %
2, %
0"
1712 [(set_attr "length" "
1,
2,
5")])
1714 ;;
16 bit result multiply:
1715 ;; currently we multiply only into odd registers, so we don't use two
1716 ;; registers - but this is a bit inefficient at times. If we define
1717 ;; a register class for each register, then we can specify properly
1718 ;; which register need which scratch register ....
1720 (define_insn "mulhi3"
1721 [(set (match_operand:HI
0 "register_operand" "=d,d") ; multiply regs
1722 (mult:HI (match_operand:HI
1 "register_operand" "%
0,
0")
1723 (match_operand:HI
2 "general_operand" "rR,Qi")))]
1726 [(set_attr "length" "
1,
2")])
1729 (define_expand "mulhisi3"
1731 (match_operand:HI
1 "general_operand" "g,g"))
1732 (set (match_operand:SI
0 "register_operand" "=r,r") ; even numbered!
1733 (mult:SI (truncate:HI
1735 (match_operand:HI
2 "general_operand" "rR,Qi")))]
1737 "operands[
3] = gen_lowpart(HImode, operands[
1]);")
1740 [(set (match_operand:SI
0 "register_operand" "=r,r") ; even numbered!
1741 (mult:SI (truncate:HI
1742 (match_operand:SI
1 "register_operand" "%
0,
0"))
1743 (match_operand:HI
2 "general_operand" "rR,Qi")))]
1746 [(set_attr "length" "
1,
2")])
1748 ;(define_insn "mulhisi3"
1749 ; [(set (match_operand:SI
0 "register_operand" "=r,r") ; even numbered!
1750 ; (mult:SI (truncate:HI
1751 ; (match_operand:SI
1 "register_operand" "%
0,
0"))
1752 ; (match_operand:HI
2 "general_operand" "rR,Qi")))]
1755 ; [(set_attr "length" "
1,
2")])
1758 (define_insn "divdf3"
1759 [(set (match_operand:DF
0 "register_operand" "=a,a,a")
1760 (div:DF (match_operand:DF
1 "register_operand" "
0,
0,
0")
1761 (match_operand:DF
2 "general_operand" "fR,Q,F")))]
1763 "{divd|divf} %
2, %
0"
1764 [(set_attr "length" "
1,
2,
5")])
1767 (define_expand "divhi3"
1768 [(set (subreg:HI (match_dup
1)
0)
1769 (div:HI (match_operand:SI
1 "general_operand" "
0")
1770 (match_operand:HI
2 "general_operand" "g")))
1771 (set (match_operand:HI
0 "general_operand" "=r")
1772 (subreg:HI (match_dup
1)
0))]
1777 [(set (subreg:HI (match_operand:SI
0 "general_operand" "=r")
0)
1778 (div:HI (match_operand:SI
1 "general_operand" "
0")
1779 (match_operand:HI
2 "general_operand" "g")))]
1782 [(set_attr "length" "
2")])
1784 (define_expand "modhi3"
1785 [(set (subreg:HI (match_dup
1)
1)
1786 (mod:HI (match_operand:SI
1 "general_operand" "
0")
1787 (match_operand:HI
2 "general_operand" "g")))
1788 (set (match_operand:HI
0 "general_operand" "=r")
1789 (subreg:HI (match_dup
1)
1))]
1794 [(set (subreg:HI (match_operand:SI
0 "general_operand" "=r")
1)
1795 (mod:HI (match_operand:SI
1 "general_operand" "
0")
1796 (match_operand:HI
2 "general_operand" "g")))]
1799 [(set_attr "length" "
2")])
1801 ;(define_expand "divmodhi4"
1802 ; [(parallel [(set (subreg:HI (match_dup
1)
0)
1803 ; (div:HI (match_operand:SI
1 "general_operand" "
0")
1804 ; (match_operand:HI
2 "general_operand" "g")))
1805 ; (set (subreg:HI (match_dup
1)
1)
1806 ; (mod:HI (match_dup
1)
1808 ; (set (match_operand:HI
3 "general_operand" "=r")
1809 ; (subreg:HI (match_dup
1)
1))
1810 ; (set (match_operand:HI
0 "general_operand" "=r")
1811 ; (subreg:HI (match_dup
1)
0))]
1816 ; [(set (subreg:HI (match_operand:SI
0 "general_operand" "=r")
0)
1817 ; (div:HI (match_operand:SI
1 "general_operand" "
0")
1818 ; (match_operand:HI
2 "general_operand" "g")))
1819 ; (set (subreg:HI (match_dup
0)
1)
1820 ; (mod:HI (match_dup
1)
1826 ;; is rotate doing the right thing to be included here ????