1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
39 /* Save the operands last given to a compare for use when we
40 generate a scc or bcc insn. */
42 rtx hppa_compare_op0
, hppa_compare_op1
;
43 enum cmp_type hppa_branch_type
;
45 /* Which cpu we are scheduling for. */
46 enum processor_type pa_cpu
;
48 /* String to hold which cpu we are scheduling for. */
51 /* Set by the FUNCTION_PROFILER macro. */
52 int hp_profile_labelno
;
54 /* Counts for the number of callee-saved general and floating point
55 registers which were saved by the current function's prologue. */
56 static int gr_saved
, fr_saved
;
58 static rtx
find_addr_reg ();
60 /* Keep track of the number of bytes we have output in the CODE subspaces
61 during this compilation so we'll know when to emit inline long-calls. */
63 unsigned int total_code_bytes
;
65 /* Variables to handle plabels that we discover are necessary at assembly
66 output time. They are output after the current function. */
72 } *deferred_plabels
= 0;
73 int n_deferred_plabels
= 0;
78 /* Default to 700 scheduling which is reasonable for older 800 processors
79 correct for the 700s, and not too bad for the 7100s and 7100LCs. */
80 if (pa_cpu_string
== NULL
81 || ! strcmp (pa_cpu_string
, "700"))
83 pa_cpu_string
= "700";
84 pa_cpu
= PROCESSOR_700
;
86 else if (! strcmp (pa_cpu_string
, "7100"))
88 pa_cpu_string
= "7100";
89 pa_cpu
= PROCESSOR_7100
;
91 else if (! strcmp (pa_cpu_string
, "7100LC"))
93 pa_cpu_string
= "7100LC";
94 pa_cpu
= PROCESSOR_7100LC
;
98 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100 and 7100LC\n", pa_cpu_string
);
101 if (flag_pic
&& TARGET_PORTABLE_RUNTIME
)
103 warning ("PIC code generation is not supported in the portable runtime model\n");
106 if (flag_pic
&& TARGET_NO_SPACE_REGS
)
108 warning ("PIC code generation is not compatable with fast indirect calls\n");
113 /* Return non-zero only if OP is a register of mode MODE,
116 reg_or_0_operand (op
, mode
)
118 enum machine_mode mode
;
120 return (op
== CONST0_RTX (mode
) || register_operand (op
, mode
));
123 /* Return non-zero if OP is suitable for use in a call to a named
126 (???) For 2.5 try to eliminate either call_operand_address or
127 function_label_operand, they perform very similar functions. */
129 call_operand_address (op
, mode
)
131 enum machine_mode mode
;
133 return (CONSTANT_P (op
) && ! TARGET_PORTABLE_RUNTIME
);
136 /* Return 1 if X contains a symbolic expression. We know these
137 expressions will have one of a few well defined forms, so
138 we need only check those forms. */
140 symbolic_expression_p (x
)
144 /* Strip off any HIGH. */
145 if (GET_CODE (x
) == HIGH
)
148 return (symbolic_operand (x
, VOIDmode
));
152 symbolic_operand (op
, mode
)
154 enum machine_mode mode
;
156 switch (GET_CODE (op
))
163 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
164 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
165 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
171 /* Return truth value of statement that OP is a symbolic memory
172 operand of mode MODE. */
175 symbolic_memory_operand (op
, mode
)
177 enum machine_mode mode
;
179 if (GET_CODE (op
) == SUBREG
)
180 op
= SUBREG_REG (op
);
181 if (GET_CODE (op
) != MEM
)
184 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
185 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
188 /* Return 1 if the operand is either a register or a memory operand that is
192 reg_or_nonsymb_mem_operand (op
, mode
)
194 enum machine_mode mode
;
196 if (register_operand (op
, mode
))
199 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
205 /* Return 1 if the operand is either a register, zero, or a memory operand
206 that is not symbolic. */
209 reg_or_0_or_nonsymb_mem_operand (op
, mode
)
211 enum machine_mode mode
;
213 if (register_operand (op
, mode
))
216 if (op
== CONST0_RTX (mode
))
219 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
225 /* Accept any constant that can be moved in one instructions into a
228 cint_ok_for_move (intval
)
229 HOST_WIDE_INT intval
;
231 /* OK if ldo, ldil, or zdepi, can be used. */
232 return (VAL_14_BITS_P (intval
) || (intval
& 0x7ff) == 0
233 || zdepi_cint_p (intval
));
236 /* Accept anything that can be moved in one instruction into a general
239 move_operand (op
, mode
)
241 enum machine_mode mode
;
243 if (register_operand (op
, mode
))
246 if (GET_CODE (op
) == CONST_INT
)
247 return cint_ok_for_move (INTVAL (op
));
249 if (GET_MODE (op
) != mode
)
251 if (GET_CODE (op
) == SUBREG
)
252 op
= SUBREG_REG (op
);
253 if (GET_CODE (op
) != MEM
)
257 if (GET_CODE (op
) == LO_SUM
)
258 return (register_operand (XEXP (op
, 0), Pmode
)
259 && CONSTANT_P (XEXP (op
, 1)));
260 return memory_address_p (mode
, op
);
263 /* Accept REG and any CONST_INT that can be moved in one instruction into a
266 reg_or_cint_move_operand (op
, mode
)
268 enum machine_mode mode
;
270 if (register_operand (op
, mode
))
273 if (GET_CODE (op
) == CONST_INT
)
274 return cint_ok_for_move (INTVAL (op
));
280 pic_label_operand (op
, mode
)
282 enum machine_mode mode
;
287 switch (GET_CODE (op
))
293 return (GET_CODE (XEXP (op
, 0)) == LABEL_REF
294 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
301 fp_reg_operand (op
, mode
)
303 enum machine_mode mode
;
305 return reg_renumber
&& FP_REG_P (op
);
310 /* Return truth value of whether OP can be used as an operand in a
311 three operand arithmetic insn that accepts registers of mode MODE
312 or 14-bit signed integers. */
314 arith_operand (op
, mode
)
316 enum machine_mode mode
;
318 return (register_operand (op
, mode
)
319 || (GET_CODE (op
) == CONST_INT
&& INT_14_BITS (op
)));
322 /* Return truth value of whether OP can be used as an operand in a
323 three operand arithmetic insn that accepts registers of mode MODE
324 or 11-bit signed integers. */
326 arith11_operand (op
, mode
)
328 enum machine_mode mode
;
330 return (register_operand (op
, mode
)
331 || (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
)));
334 /* A constant integer suitable for use in a PRE_MODIFY memory
337 pre_cint_operand (op
, mode
)
339 enum machine_mode mode
;
341 return (GET_CODE (op
) == CONST_INT
342 && INTVAL (op
) >= -0x2000 && INTVAL (op
) < 0x10);
345 /* A constant integer suitable for use in a POST_MODIFY memory
348 post_cint_operand (op
, mode
)
350 enum machine_mode mode
;
352 return (GET_CODE (op
) == CONST_INT
353 && INTVAL (op
) < 0x2000 && INTVAL (op
) >= -0x10);
357 arith_double_operand (op
, mode
)
359 enum machine_mode mode
;
361 return (register_operand (op
, mode
)
362 || (GET_CODE (op
) == CONST_DOUBLE
363 && GET_MODE (op
) == mode
364 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op
))
365 && (CONST_DOUBLE_HIGH (op
) >= 0
366 == ((CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
369 /* Return truth value of whether OP is a integer which fits the
370 range constraining immediate operands in three-address insns. */
373 int5_operand (op
, mode
)
375 enum machine_mode mode
;
377 return (GET_CODE (op
) == CONST_INT
&& INT_5_BITS (op
));
381 uint5_operand (op
, mode
)
383 enum machine_mode mode
;
385 return (GET_CODE (op
) == CONST_INT
&& INT_U5_BITS (op
));
389 int11_operand (op
, mode
)
391 enum machine_mode mode
;
393 return (GET_CODE (op
) == CONST_INT
&& INT_11_BITS (op
));
397 uint32_operand (op
, mode
)
399 enum machine_mode mode
;
401 #if HOST_BITS_PER_WIDE_INT > 32
402 /* All allowed constants will fit a CONST_INT. */
403 return (GET_CODE (op
) == CONST_INT
404 && (INTVAL (op
) >= 0 && INTVAL (op
) < 0x100000000L
));
406 return (GET_CODE (op
) == CONST_INT
407 || (GET_CODE (op
) == CONST_DOUBLE
408 && CONST_DOUBLE_HIGH (op
) == 0));
413 arith5_operand (op
, mode
)
415 enum machine_mode mode
;
417 return register_operand (op
, mode
) || int5_operand (op
, mode
);
420 /* True iff zdepi can be used to generate this CONST_INT. */
423 unsigned HOST_WIDE_INT x
;
425 unsigned HOST_WIDE_INT lsb_mask
, t
;
427 /* This might not be obvious, but it's at least fast.
428 This function is critical; we don't have the time loops would take. */
430 t
= ((x
>> 4) + lsb_mask
) & ~(lsb_mask
- 1);
431 /* Return true iff t is a power of two. */
432 return ((t
& (t
- 1)) == 0);
435 /* True iff depi or extru can be used to compute (reg & mask).
436 Accept bit pattern like these:
442 unsigned HOST_WIDE_INT mask
;
445 mask
+= mask
& -mask
;
446 return (mask
& (mask
- 1)) == 0;
449 /* True iff depi or extru can be used to compute (reg & OP). */
451 and_operand (op
, mode
)
453 enum machine_mode mode
;
455 return (register_operand (op
, mode
)
456 || (GET_CODE (op
) == CONST_INT
&& and_mask_p (INTVAL (op
))));
459 /* True iff depi can be used to compute (reg | MASK). */
462 unsigned HOST_WIDE_INT mask
;
464 mask
+= mask
& -mask
;
465 return (mask
& (mask
- 1)) == 0;
468 /* True iff depi can be used to compute (reg | OP). */
470 ior_operand (op
, mode
)
472 enum machine_mode mode
;
474 return (GET_CODE (op
) == CONST_INT
&& ior_mask_p (INTVAL (op
)));
478 lhs_lshift_operand (op
, mode
)
480 enum machine_mode mode
;
482 return register_operand (op
, mode
) || lhs_lshift_cint_operand (op
, mode
);
485 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
486 Such values can be the left hand side x in (x << r), using the zvdepi
489 lhs_lshift_cint_operand (op
, mode
)
491 enum machine_mode mode
;
493 unsigned HOST_WIDE_INT x
;
494 if (GET_CODE (op
) != CONST_INT
)
496 x
= INTVAL (op
) >> 4;
497 return (x
& (x
+ 1)) == 0;
501 arith32_operand (op
, mode
)
503 enum machine_mode mode
;
505 return register_operand (op
, mode
) || GET_CODE (op
) == CONST_INT
;
509 pc_or_label_operand (op
, mode
)
511 enum machine_mode mode
;
513 return (GET_CODE (op
) == PC
|| GET_CODE (op
) == LABEL_REF
);
516 /* Legitimize PIC addresses. If the address is already
517 position-independent, we return ORIG. Newly generated
518 position-independent addresses go to REG. If we need more
519 than one register, we lose. */
522 legitimize_pic_address (orig
, mode
, reg
)
524 enum machine_mode mode
;
528 /* Labels need special handling. */
529 if (pic_label_operand (orig
))
531 emit_insn (gen_pic_load_label (reg
, orig
));
532 current_function_uses_pic_offset_table
= 1;
535 if (GET_CODE (orig
) == SYMBOL_REF
)
542 emit_insn (gen_pic2_highpart (reg
, pic_offset_table_rtx
, orig
));
543 pic_ref
= gen_rtx (MEM
, Pmode
,
544 gen_rtx (LO_SUM
, Pmode
, reg
,
545 gen_rtx (UNSPEC
, SImode
, gen_rtvec (1, orig
), 0)));
548 pic_ref
= gen_rtx (MEM
, Pmode
,
549 gen_rtx (PLUS
, Pmode
, pic_offset_table_rtx
, orig
));
550 current_function_uses_pic_offset_table
= 1;
551 RTX_UNCHANGING_P (pic_ref
) = 1;
552 emit_move_insn (reg
, pic_ref
);
555 else if (GET_CODE (orig
) == CONST
)
559 if (GET_CODE (XEXP (orig
, 0)) == PLUS
560 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
566 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
568 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
569 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
570 base
== reg
? 0 : reg
);
573 if (GET_CODE (orig
) == CONST_INT
)
575 if (INT_14_BITS (orig
))
576 return plus_constant_for_output (base
, INTVAL (orig
));
577 orig
= force_reg (Pmode
, orig
);
579 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
580 /* Likewise, should we set special REG_NOTEs here? */
585 /* Try machine-dependent ways of modifying an illegitimate address
586 to be legitimate. If we find one, return the new, valid address.
587 This macro is used in only one place: `memory_address' in explow.c.
589 OLDX is the address as it was before break_out_memory_refs was called.
590 In some cases it is useful to look at this to decide what needs to be done.
592 MODE and WIN are passed so that this macro can use
593 GO_IF_LEGITIMATE_ADDRESS.
595 It is always safe for this macro to do nothing. It exists to recognize
596 opportunities to optimize the output.
598 For the PA, transform:
600 memory(X + <large int>)
604 if (<large int> & mask) >= 16
605 Y = (<large int> & ~mask) + mask + 1 Round up.
607 Y = (<large int> & ~mask) Round down.
609 memory (Z + (<large int> - Y));
611 This is for CSE to find several similar references, and only use one Z.
613 X can either be a SYMBOL_REF or REG, but because combine can not
614 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
615 D will not fit in 14 bits.
617 MODE_FLOAT references allow displacements which fit in 5 bits, so use
620 MODE_INT references allow displacements which fit in 14 bits, so use
623 This relies on the fact that most mode MODE_FLOAT references will use FP
624 registers and most mode MODE_INT references will use integer registers.
625 (In the rare case of an FP register used in an integer MODE, we depend
626 on secondary reloads to clean things up.)
629 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
630 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
631 addressing modes to be used).
633 Put X and Z into registers. Then put the entire expression into
637 hppa_legitimize_address (x
, oldx
, mode
)
639 enum machine_mode mode
;
644 return legitimize_pic_address (x
, mode
, gen_reg_rtx (Pmode
));
646 /* Strip off CONST. */
647 if (GET_CODE (x
) == CONST
)
650 /* Special case. Get the SYMBOL_REF into a register and use indexing.
651 That should always be safe. */
652 if (GET_CODE (x
) == PLUS
653 && GET_CODE (XEXP (x
, 0)) == REG
654 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
)
656 rtx reg
= force_reg (SImode
, XEXP (x
, 1));
657 return force_reg (SImode
, gen_rtx (PLUS
, SImode
, reg
, XEXP (x
, 0)));
660 /* Note we must reject symbols which represent function addresses
661 since the assembler/linker can't handle arithmetic on plabels. */
662 if (GET_CODE (x
) == PLUS
663 && GET_CODE (XEXP (x
, 1)) == CONST_INT
664 && ((GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
665 && !FUNCTION_NAME_P (XSTR (XEXP (x
, 0), 0)))
666 || GET_CODE (XEXP (x
, 0)) == REG
))
668 rtx int_part
, ptr_reg
;
670 int offset
= INTVAL (XEXP (x
, 1));
671 int mask
= GET_MODE_CLASS (mode
) == MODE_FLOAT
? 0x1f : 0x3fff;
673 /* Choose which way to round the offset. Round up if we
674 are >= halfway to the next boundary. */
675 if ((offset
& mask
) >= ((mask
+ 1) / 2))
676 newoffset
= (offset
& ~ mask
) + mask
+ 1;
678 newoffset
= (offset
& ~ mask
);
680 /* If the newoffset will not fit in 14 bits (ldo), then
681 handling this would take 4 or 5 instructions (2 to load
682 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
683 add the new offset and the SYMBOL_REF.) Combine can
684 not handle 4->2 or 5->2 combinations, so do not create
686 if (! VAL_14_BITS_P (newoffset
)
687 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
689 rtx const_part
= gen_rtx (CONST
, VOIDmode
,
690 gen_rtx (PLUS
, Pmode
,
692 GEN_INT (newoffset
)));
695 gen_rtx (HIGH
, Pmode
, const_part
));
698 gen_rtx (LO_SUM
, Pmode
,
699 tmp_reg
, const_part
));
703 if (! VAL_14_BITS_P (newoffset
))
704 int_part
= force_reg (Pmode
, GEN_INT (newoffset
));
706 int_part
= GEN_INT (newoffset
);
708 ptr_reg
= force_reg (Pmode
,
709 gen_rtx (PLUS
, Pmode
,
710 force_reg (Pmode
, XEXP (x
, 0)),
713 return plus_constant (ptr_reg
, offset
- newoffset
);
716 /* Try to arrange things so that indexing modes can be used, but
717 only do so if indexing is safe.
719 Indexing is safe when the second operand for the outer PLUS
720 is a REG, SUBREG, SYMBOL_REF or the like.
722 For 2.5, indexing is also safe for (plus (symbol_ref) (const_int))
723 if the integer is > 0. */
724 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
725 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
726 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1)))
727 && (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == 'o'
728 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
729 && GET_CODE (XEXP (x
, 1)) != CONST
)
731 int val
= INTVAL (XEXP (XEXP (x
, 0), 1));
733 reg1
= force_reg (Pmode
, force_operand (XEXP (x
, 1), 0));
734 reg2
= force_reg (Pmode
,
735 force_operand (XEXP (XEXP (x
, 0), 0), 0));
736 return force_reg (Pmode
,
737 gen_rtx (PLUS
, Pmode
,
738 gen_rtx (MULT
, Pmode
, reg2
,
743 /* Uh-oh. We might have an address for x[n-100000]. This needs
746 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
747 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
748 && shadd_constant_p (INTVAL (XEXP (XEXP (x
, 0), 1))))
750 /* Ugly. We modify things here so that the address offset specified
751 by the index expression is computed first, then added to x to form
754 For 2.5, it might be profitable to set things up so that we
755 compute the raw (unscaled) index first, then use scaled indexing
756 to access memory, or better yet have the MI parts of the compiler
759 rtx regx1
, regy1
, regy2
, y
;
761 /* Strip off any CONST. */
763 if (GET_CODE (y
) == CONST
)
766 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
768 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
769 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
770 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
771 regx1
= force_reg (Pmode
, gen_rtx (GET_CODE (y
), Pmode
, regx1
, regy2
));
772 return force_reg (Pmode
, gen_rtx (PLUS
, Pmode
, regx1
, regy1
));
779 /* For the HPPA, REG and REG+CONST is cost 0
780 and addresses involving symbolic constants are cost 2.
782 PIC addresses are very expensive.
784 It is no coincidence that this has the same structure
785 as GO_IF_LEGITIMATE_ADDRESS. */
787 hppa_address_cost (X
)
790 if (GET_CODE (X
) == PLUS
)
792 else if (GET_CODE (X
) == LO_SUM
)
794 else if (GET_CODE (X
) == HIGH
)
799 /* Emit insns to move operands[1] into operands[0].
801 Return 1 if we have written out everything that needs to be done to
802 do the move. Otherwise, return 0 and the caller will emit the move
806 emit_move_sequence (operands
, mode
, scratch_reg
)
808 enum machine_mode mode
;
811 register rtx operand0
= operands
[0];
812 register rtx operand1
= operands
[1];
814 /* Handle secondary reloads for loads/stores of FP registers from
815 REG+D addresses where D does not fit in 5 bits, including
816 (subreg (mem (addr))) cases. */
817 if (fp_reg_operand (operand0
, mode
)
818 && ((GET_CODE (operand1
) == MEM
819 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
820 || ((GET_CODE (operand1
) == SUBREG
821 && GET_CODE (XEXP (operand1
, 0)) == MEM
822 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
825 if (GET_CODE (operand1
) == SUBREG
)
826 operand1
= XEXP (operand1
, 0);
828 scratch_reg
= gen_rtx (REG
, SImode
, REGNO (scratch_reg
));
830 /* D might not fit in 14 bits either; for such cases load D into
832 if (!memory_address_p (SImode
, XEXP (operand1
, 0)))
834 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
835 emit_move_insn (scratch_reg
, gen_rtx (GET_CODE (XEXP (operand1
, 0)),
837 XEXP (XEXP (operand1
, 0), 0),
841 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
842 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, gen_rtx (MEM
, mode
,
846 else if (fp_reg_operand (operand1
, mode
)
847 && ((GET_CODE (operand0
) == MEM
848 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
849 || ((GET_CODE (operand0
) == SUBREG
)
850 && GET_CODE (XEXP (operand0
, 0)) == MEM
851 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
854 if (GET_CODE (operand0
) == SUBREG
)
855 operand0
= XEXP (operand0
, 0);
857 scratch_reg
= gen_rtx (REG
, SImode
, REGNO (scratch_reg
));
858 /* D might not fit in 14 bits either; for such cases load D into
860 if (!memory_address_p (SImode
, XEXP (operand0
, 0)))
862 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
863 emit_move_insn (scratch_reg
, gen_rtx (GET_CODE (XEXP (operand0
, 0)),
865 XEXP (XEXP (operand0
, 0), 0),
869 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
870 emit_insn (gen_rtx (SET
, VOIDmode
, gen_rtx (MEM
, mode
, scratch_reg
),
874 /* Handle secondary reloads for loads of FP registers from constant
875 expressions by forcing the constant into memory.
877 use scratch_reg to hold the address of the memory location.
879 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
880 NO_REGS when presented with a const_int and an register class
881 containing only FP registers. Doing so unfortunately creates
882 more problems than it solves. Fix this for 2.5. */
883 else if (fp_reg_operand (operand0
, mode
)
884 && CONSTANT_P (operand1
)
889 /* Force the constant into memory and put the address of the
890 memory location into scratch_reg. */
891 xoperands
[0] = scratch_reg
;
892 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
893 emit_move_sequence (xoperands
, Pmode
, 0);
895 /* Now load the destination register. */
896 emit_insn (gen_rtx (SET
, mode
, operand0
,
897 gen_rtx (MEM
, mode
, scratch_reg
)));
900 /* Handle secondary reloads for SAR. These occur when trying to load
901 the SAR from memory a FP register, or with a constant. */
902 else if (GET_CODE (operand0
) == REG
903 && REGNO_REG_CLASS (REGNO (operand0
)) == SHIFT_REGS
904 && (GET_CODE (operand1
) == MEM
905 || GET_CODE (operand1
) == CONST_INT
906 || (GET_CODE (operand1
) == REG
907 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1
)))))
910 emit_move_insn (scratch_reg
, operand1
);
911 emit_move_insn (operand0
, scratch_reg
);
914 /* Handle most common case: storing into a register. */
915 else if (register_operand (operand0
, mode
))
917 if (register_operand (operand1
, mode
)
918 || (GET_CODE (operand1
) == CONST_INT
&& INT_14_BITS (operand1
))
919 || (operand1
== CONST0_RTX (mode
))
920 || (GET_CODE (operand1
) == HIGH
921 && !symbolic_operand (XEXP (operand1
, 0), VOIDmode
))
922 /* Only `general_operands' can come here, so MEM is ok. */
923 || GET_CODE (operand1
) == MEM
)
925 /* Run this case quickly. */
926 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
930 else if (GET_CODE (operand0
) == MEM
)
932 if (register_operand (operand1
, mode
) || operand1
== CONST0_RTX (mode
))
934 /* Run this case quickly. */
935 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
938 if (! (reload_in_progress
|| reload_completed
))
940 operands
[0] = validize_mem (operand0
);
941 operands
[1] = operand1
= force_reg (mode
, operand1
);
945 /* Simplify the source if we need to. */
946 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
947 || (GET_CODE (operand1
) == HIGH
948 && symbolic_operand (XEXP (operand1
, 0), mode
)))
952 if (GET_CODE (operand1
) == HIGH
)
955 operand1
= XEXP (operand1
, 0);
957 if (symbolic_operand (operand1
, mode
))
959 rtx const_part
= NULL
;
961 /* Argh. The assembler and linker can't handle arithmetic
962 involving plabels. We'll have to split up operand1 here
963 if it's a function label involved in an arithmetic
964 expression. Luckily, this only happens with addition
965 of constants to plabels, which simplifies the test.
967 We add the constant back in just before returning to
969 if (GET_CODE (operand1
) == CONST
970 && GET_CODE (XEXP (operand1
, 0)) == PLUS
971 && function_label_operand (XEXP (XEXP (operand1
, 0), 0), Pmode
))
973 /* Save away the constant part of the expression. */
974 const_part
= XEXP (XEXP (operand1
, 0), 1);
975 if (GET_CODE (const_part
) != CONST_INT
)
978 /* Set operand1 to just the SYMBOL_REF. */
979 operand1
= XEXP (XEXP (operand1
, 0), 0);
986 if (reload_in_progress
|| reload_completed
)
987 temp
= scratch_reg
? scratch_reg
: operand0
;
989 temp
= gen_reg_rtx (Pmode
);
991 /* If operand1 is a function label, then we've got to
992 force it to memory, then load op0 from memory. */
993 if (function_label_operand (operand1
, mode
))
995 operands
[1] = force_const_mem (mode
, operand1
);
996 emit_move_sequence (operands
, mode
, temp
);
998 /* Likewise for (const (plus (symbol) (const_int))) when
999 generating pic code during or after reload and const_int
1000 will not fit in 14 bits. */
1001 else if (GET_CODE (operand1
) == CONST
1002 && GET_CODE (XEXP (operand1
, 0)) == PLUS
1003 && GET_CODE (XEXP (XEXP (operand1
, 0), 1)) == CONST_INT
1004 && !INT_14_BITS (XEXP (XEXP (operand1
, 0), 1))
1005 && (reload_completed
|| reload_in_progress
)
1008 operands
[1] = force_const_mem (mode
, operand1
);
1009 operands
[1] = legitimize_pic_address (XEXP (operands
[1], 0),
1011 emit_move_sequence (operands
, mode
, temp
);
1015 operands
[1] = legitimize_pic_address (operand1
, mode
, temp
);
1016 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operands
[1]));
1019 /* On the HPPA, references to data space are supposed to use dp,
1020 register 27, but showing it in the RTL inhibits various cse
1021 and loop optimizations. */
1026 if (reload_in_progress
|| reload_completed
)
1027 temp
= scratch_reg
? scratch_reg
: operand0
;
1029 temp
= gen_reg_rtx (mode
);
1031 /* Loading a SYMBOL_REF into a register makes that register
1032 safe to be used as the base in an indexed address.
1034 Don't mark hard registers though. That loses. */
1035 if (REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
1036 REGNO_POINTER_FLAG (REGNO (operand0
)) = 1;
1037 if (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
)
1038 REGNO_POINTER_FLAG (REGNO (temp
)) = 1;
1040 set
= gen_rtx (SET
, mode
, operand0
, temp
);
1042 set
= gen_rtx (SET
, VOIDmode
,
1044 gen_rtx (LO_SUM
, mode
, temp
, operand1
));
1046 emit_insn (gen_rtx (SET
, VOIDmode
,
1048 gen_rtx (HIGH
, mode
, operand1
)));
1053 /* Add back in the constant part if needed. */
1054 if (const_part
!= NULL
)
1055 expand_inc (operand0
, const_part
);
1058 else if (GET_CODE (operand1
) != CONST_INT
1059 || ! cint_ok_for_move (INTVAL (operand1
)))
1063 if (reload_in_progress
|| reload_completed
)
1066 temp
= gen_reg_rtx (mode
);
1068 emit_insn (gen_rtx (SET
, VOIDmode
, temp
,
1069 gen_rtx (HIGH
, mode
, operand1
)));
1070 operands
[1] = gen_rtx (LO_SUM
, mode
, temp
, operand1
);
1073 /* Now have insn-emit do whatever it normally does. */
1077 /* Does operand (which is a symbolic_operand) live in text space? If
1078 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1081 read_only_operand (operand
)
1084 if (GET_CODE (operand
) == CONST
)
1085 operand
= XEXP (XEXP (operand
, 0), 0);
1088 if (GET_CODE (operand
) == SYMBOL_REF
)
1089 return SYMBOL_REF_FLAG (operand
) && !CONSTANT_POOL_ADDRESS_P (operand
);
1093 if (GET_CODE (operand
) == SYMBOL_REF
)
1094 return SYMBOL_REF_FLAG (operand
) || CONSTANT_POOL_ADDRESS_P (operand
);
1100 /* Return the best assembler insn template
1101 for moving operands[1] into operands[0] as a fullword. */
1103 singlemove_string (operands
)
1106 HOST_WIDE_INT intval
;
1108 if (GET_CODE (operands
[0]) == MEM
)
1109 return "stw %r1,%0";
1110 if (GET_CODE (operands
[1]) == MEM
)
1112 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1117 if (GET_MODE (operands
[1]) != SFmode
)
1120 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1122 REAL_VALUE_FROM_CONST_DOUBLE (d
, operands
[1]);
1123 REAL_VALUE_TO_TARGET_SINGLE (d
, i
);
1125 operands
[1] = GEN_INT (i
);
1126 /* Fall through to CONST_INT case. */
1128 if (GET_CODE (operands
[1]) == CONST_INT
)
1130 intval
= INTVAL (operands
[1]);
1132 if (VAL_14_BITS_P (intval
))
1134 else if ((intval
& 0x7ff) == 0)
1135 return "ldil L'%1,%0";
1136 else if (zdepi_cint_p (intval
))
1137 return "zdepi %Z1,%0";
1139 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1141 return "copy %1,%0";
1145 /* Compute position (in OP[1]) and width (in OP[2])
1146 useful for copying IMM to a register using the zdepi
1147 instructions. Store the immediate value to insert in OP[0]. */
1149 compute_zdepi_operands (imm
, op
)
1150 unsigned HOST_WIDE_INT imm
;
1155 /* Find the least significant set bit in IMM. */
1156 for (lsb
= 0; lsb
< 32; lsb
++)
1163 /* Choose variants based on *sign* of the 5-bit field. */
1164 if ((imm
& 0x10) == 0)
1165 len
= (lsb
<= 28) ? 4 : 32 - lsb
;
1168 /* Find the width of the bitstring in IMM. */
1169 for (len
= 5; len
< 32; len
++)
1171 if ((imm
& (1 << len
)) == 0)
1175 /* Sign extend IMM as a 5-bit value. */
1176 imm
= (imm
& 0xf) - 0x10;
1184 /* Output assembler code to perform a doubleword move insn
1185 with operands OPERANDS. */
1188 output_move_double (operands
)
1191 enum { REGOP
, OFFSOP
, MEMOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
1193 rtx addreg0
= 0, addreg1
= 0;
1195 /* First classify both operands. */
1197 if (REG_P (operands
[0]))
1199 else if (offsettable_memref_p (operands
[0]))
1201 else if (GET_CODE (operands
[0]) == MEM
)
1206 if (REG_P (operands
[1]))
1208 else if (CONSTANT_P (operands
[1]))
1210 else if (offsettable_memref_p (operands
[1]))
1212 else if (GET_CODE (operands
[1]) == MEM
)
1217 /* Check for the cases that the operand constraints are not
1218 supposed to allow to happen. Abort if we get one,
1219 because generating code for these cases is painful. */
1221 if (optype0
!= REGOP
&& optype1
!= REGOP
)
1224 /* Handle auto decrementing and incrementing loads and stores
1225 specifically, since the structure of the function doesn't work
1226 for them without major modification. Do it better when we learn
1227 this port about the general inc/dec addressing of PA.
1228 (This was written by tege. Chide him if it doesn't work.) */
1230 if (optype0
== MEMOP
)
1232 /* We have to output the address syntax ourselves, since print_operand
1233 doesn't deal with the addresses we want to use. Fix this later. */
1235 rtx addr
= XEXP (operands
[0], 0);
1236 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1238 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1240 operands
[0] = XEXP (addr
, 0);
1241 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1244 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1246 /* No overlap between high target register and address
1247 register. (We do this in a non-obvious way to
1248 save a register file writeback) */
1249 if (GET_CODE (addr
) == POST_INC
)
1250 return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
1251 return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
1256 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1258 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[1], 0);
1260 operands
[0] = XEXP (addr
, 0);
1261 if (GET_CODE (operands
[1]) != REG
|| GET_CODE (operands
[0]) != REG
)
1264 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1266 /* No overlap between high target register and address
1267 register. (We do this in a non-obvious way to
1268 save a register file writeback) */
1269 if (GET_CODE (addr
) == PRE_INC
)
1270 return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
1271 return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
1277 if (optype1
== MEMOP
)
1279 /* We have to output the address syntax ourselves, since print_operand
1280 doesn't deal with the addresses we want to use. Fix this later. */
1282 rtx addr
= XEXP (operands
[1], 0);
1283 if (GET_CODE (addr
) == POST_INC
|| GET_CODE (addr
) == POST_DEC
)
1285 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1287 operands
[1] = XEXP (addr
, 0);
1288 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1291 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1293 /* No overlap between high target register and address
1294 register. (We do this in a non-obvious way to
1295 save a register file writeback) */
1296 if (GET_CODE (addr
) == POST_INC
)
1297 return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
1298 return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
1302 /* This is an undefined situation. We should load into the
1303 address register *and* update that register. Probably
1304 we don't need to handle this at all. */
1305 if (GET_CODE (addr
) == POST_INC
)
1306 return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
1307 return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
1310 else if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
1312 rtx high_reg
= gen_rtx (SUBREG
, SImode
, operands
[0], 0);
1314 operands
[1] = XEXP (addr
, 0);
1315 if (GET_CODE (operands
[0]) != REG
|| GET_CODE (operands
[1]) != REG
)
1318 if (!reg_overlap_mentioned_p (high_reg
, addr
))
1320 /* No overlap between high target register and address
1321 register. (We do this in a non-obvious way to
1322 save a register file writeback) */
1323 if (GET_CODE (addr
) == PRE_INC
)
1324 return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
1325 return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
1329 /* This is an undefined situation. We should load into the
1330 address register *and* update that register. Probably
1331 we don't need to handle this at all. */
1332 if (GET_CODE (addr
) == PRE_INC
)
1333 return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
1334 return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
1339 /* If an operand is an unoffsettable memory ref, find a register
1340 we can increment temporarily to make it refer to the second word. */
1342 if (optype0
== MEMOP
)
1343 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1345 if (optype1
== MEMOP
)
1346 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1348 /* Ok, we can do one word at a time.
1349 Normally we do the low-numbered word first.
1351 In either case, set up in LATEHALF the operands to use
1352 for the high-numbered word and in some cases alter the
1353 operands in OPERANDS to be suitable for the low-numbered word. */
1355 if (optype0
== REGOP
)
1356 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1357 else if (optype0
== OFFSOP
)
1358 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1360 latehalf
[0] = operands
[0];
1362 if (optype1
== REGOP
)
1363 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1364 else if (optype1
== OFFSOP
)
1365 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1366 else if (optype1
== CNSTOP
)
1367 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1369 latehalf
[1] = operands
[1];
1371 /* If the first move would clobber the source of the second one,
1372 do them in the other order.
1374 RMS says "This happens only for registers;
1375 such overlap can't happen in memory unless the user explicitly
1376 sets it up, and that is an undefined circumstance."
1378 but it happens on the HP-PA when loading parameter registers,
1379 so I am going to define that circumstance, and make it work
1382 if (optype0
== REGOP
&& (optype1
== MEMOP
|| optype1
== OFFSOP
)
1383 && reg_overlap_mentioned_p (operands
[0], XEXP (operands
[1], 0)))
1385 /* XXX THIS PROBABLY DOESN'T WORK. */
1386 /* Do the late half first. */
1388 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1389 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1391 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1393 return singlemove_string (operands
);
1396 if (optype0
== REGOP
&& optype1
== REGOP
1397 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1399 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1400 return singlemove_string (operands
);
1403 /* Normal case: do the two words, low-numbered first. */
1405 output_asm_insn (singlemove_string (operands
), operands
);
1407 /* Make any unoffsettable addresses point at high-numbered word. */
1409 output_asm_insn ("ldo 4(%0),%0", &addreg0
);
1411 output_asm_insn ("ldo 4(%0),%0", &addreg1
);
1414 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1416 /* Undo the adds we just did. */
1418 output_asm_insn ("ldo -4(%0),%0", &addreg0
);
1420 output_asm_insn ("ldo -4(%0),%0", &addreg1
);
1426 output_fp_move_double (operands
)
1429 if (FP_REG_P (operands
[0]))
1431 if (FP_REG_P (operands
[1])
1432 || operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1433 output_asm_insn ("fcpy,dbl %r1,%0", operands
);
1435 output_asm_insn ("fldds%F1 %1,%0", operands
);
1437 else if (FP_REG_P (operands
[1]))
1439 output_asm_insn ("fstds%F0 %1,%0", operands
);
1441 else if (operands
[1] == CONST0_RTX (GET_MODE (operands
[0])))
1443 if (GET_CODE (operands
[0]) == REG
)
1446 xoperands
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1447 xoperands
[0] = operands
[0];
1448 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands
);
1450 /* This is a pain. You have to be prepared to deal with an
1451 arbitrary address here including pre/post increment/decrement.
1453 so avoid this in the MD. */
1461 /* Return a REG that occurs in ADDR with coefficient 1.
1462 ADDR can be effectively incremented by incrementing REG. */
1465 find_addr_reg (addr
)
1468 while (GET_CODE (addr
) == PLUS
)
1470 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1471 addr
= XEXP (addr
, 0);
1472 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
1473 addr
= XEXP (addr
, 1);
1474 else if (CONSTANT_P (XEXP (addr
, 0)))
1475 addr
= XEXP (addr
, 1);
1476 else if (CONSTANT_P (XEXP (addr
, 1)))
1477 addr
= XEXP (addr
, 0);
1481 if (GET_CODE (addr
) == REG
)
1486 /* Emit code to perform a block move.
1488 OPERANDS[0] is the destination pointer as a REG, clobbered.
1489 OPERANDS[1] is the source pointer as a REG, clobbered.
1490 OPERANDS[2] is a register for temporary storage.
1491 OPERANDS[4] is the size as a CONST_INT
1492 OPERANDS[3] is a register for temporary storage.
1493 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1494 OPERNADS[6] is another temporary register. */
1497 output_block_move (operands
, size_is_constant
)
1499 int size_is_constant
;
1501 int align
= INTVAL (operands
[5]);
1502 unsigned long n_bytes
= INTVAL (operands
[4]);
1504 /* We can't move more than four bytes at a time because the PA
1505 has no longer integer move insns. (Could use fp mem ops?) */
1509 /* Note that we know each loop below will execute at least twice
1510 (else we would have open-coded the copy). */
1514 /* Pre-adjust the loop counter. */
1515 operands
[4] = GEN_INT (n_bytes
- 8);
1516 output_asm_insn ("ldi %4,%2", operands
);
1519 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1520 output_asm_insn ("ldws,ma 4(0,%1),%6", operands
);
1521 output_asm_insn ("stws,ma %3,4(0,%0)", operands
);
1522 output_asm_insn ("addib,>= -8,%2,.-12", operands
);
1523 output_asm_insn ("stws,ma %6,4(0,%0)", operands
);
1525 /* Handle the residual. There could be up to 7 bytes of
1526 residual to copy! */
1527 if (n_bytes
% 8 != 0)
1529 operands
[4] = GEN_INT (n_bytes
% 4);
1530 if (n_bytes
% 8 >= 4)
1531 output_asm_insn ("ldws,ma 4(0,%1),%3", operands
);
1532 if (n_bytes
% 4 != 0)
1533 output_asm_insn ("ldw 0(0,%1),%6", operands
);
1534 if (n_bytes
% 8 >= 4)
1535 output_asm_insn ("stws,ma %3,4(0,%0)", operands
);
1536 if (n_bytes
% 4 != 0)
1537 output_asm_insn ("stbys,e %6,%4(0,%0)", operands
);
1542 /* Pre-adjust the loop counter. */
1543 operands
[4] = GEN_INT (n_bytes
- 4);
1544 output_asm_insn ("ldi %4,%2", operands
);
1547 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands
);
1548 output_asm_insn ("ldhs,ma 2(0,%1),%6", operands
);
1549 output_asm_insn ("sths,ma %3,2(0,%0)", operands
);
1550 output_asm_insn ("addib,>= -4,%2,.-12", operands
);
1551 output_asm_insn ("sths,ma %6,2(0,%0)", operands
);
1553 /* Handle the residual. */
1554 if (n_bytes
% 4 != 0)
1556 if (n_bytes
% 4 >= 2)
1557 output_asm_insn ("ldhs,ma 2(0,%1),%3", operands
);
1558 if (n_bytes
% 2 != 0)
1559 output_asm_insn ("ldb 0(0,%1),%6", operands
);
1560 if (n_bytes
% 4 >= 2)
1561 output_asm_insn ("sths,ma %3,2(0,%0)", operands
);
1562 if (n_bytes
% 2 != 0)
1563 output_asm_insn ("stb %6,0(0,%0)", operands
);
1568 /* Pre-adjust the loop counter. */
1569 operands
[4] = GEN_INT (n_bytes
- 2);
1570 output_asm_insn ("ldi %4,%2", operands
);
1573 output_asm_insn ("ldbs,ma 1(0,%1),%3", operands
);
1574 output_asm_insn ("ldbs,ma 1(0,%1),%6", operands
);
1575 output_asm_insn ("stbs,ma %3,1(0,%0)", operands
);
1576 output_asm_insn ("addib,>= -2,%2,.-12", operands
);
1577 output_asm_insn ("stbs,ma %6,1(0,%0)", operands
);
1579 /* Handle the residual. */
1580 if (n_bytes
% 2 != 0)
1582 output_asm_insn ("ldb 0(0,%1),%3", operands
);
1583 output_asm_insn ("stb %3,0(0,%0)", operands
);
1592 /* Count the number of insns necessary to handle this block move.
1594 Basic structure is the same as emit_block_move, except that we
1595 count insns rather than emit them. */
1598 compute_movstrsi_length (insn
)
1601 rtx pat
= PATTERN (insn
);
1602 int align
= INTVAL (XEXP (XVECEXP (pat
, 0, 6), 0));
1603 unsigned long n_bytes
= INTVAL (XEXP (XVECEXP (pat
, 0, 5), 0));
1604 unsigned int n_insns
= 0;
1606 /* We can't move more than four bytes at a time because the PA
1607 has no longer integer move insns. (Could use fp mem ops?) */
1611 /* The basic opying loop. */
1615 if (n_bytes
% (2 * align
) != 0)
1617 /* Any residual caused by unrolling the copy loop. */
1618 if (n_bytes
% (2 * align
) > align
)
1621 /* Any residual because the number of bytes was not a
1622 multiple of the alignment. */
1623 if (n_bytes
% align
!= 0)
1627 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
1633 output_and (operands
)
1636 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) != 0)
1638 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
1639 int ls0
, ls1
, ms0
, p
, len
;
1641 for (ls0
= 0; ls0
< 32; ls0
++)
1642 if ((mask
& (1 << ls0
)) == 0)
1645 for (ls1
= ls0
; ls1
< 32; ls1
++)
1646 if ((mask
& (1 << ls1
)) != 0)
1649 for (ms0
= ls1
; ms0
< 32; ms0
++)
1650 if ((mask
& (1 << ms0
)) == 0)
1663 operands
[2] = GEN_INT (len
);
1664 return "extru %1,31,%2,%0";
1668 /* We could use this `depi' for the case above as well, but `depi'
1669 requires one more register file access than an `extru'. */
1674 operands
[2] = GEN_INT (p
);
1675 operands
[3] = GEN_INT (len
);
1676 return "depi 0,%2,%3,%0";
1680 return "and %1,%2,%0";
1684 output_ior (operands
)
1687 unsigned HOST_WIDE_INT mask
= INTVAL (operands
[2]);
1688 int bs0
, bs1
, p
, len
;
1690 if (INTVAL (operands
[2]) == 0)
1691 return "copy %1,%0";
1693 for (bs0
= 0; bs0
< 32; bs0
++)
1694 if ((mask
& (1 << bs0
)) != 0)
1697 for (bs1
= bs0
; bs1
< 32; bs1
++)
1698 if ((mask
& (1 << bs1
)) == 0)
1701 if (bs1
!= 32 && ((unsigned HOST_WIDE_INT
) 1 << bs1
) <= mask
)
1707 operands
[2] = GEN_INT (p
);
1708 operands
[3] = GEN_INT (len
);
1709 return "depi -1,%2,%3,%0";
1712 /* Output an ascii string. */
1714 output_ascii (file
, p
, size
)
1721 unsigned char partial_output
[16]; /* Max space 4 chars can occupy. */
1723 /* The HP assembler can only take strings of 256 characters at one
1724 time. This is a limitation on input line length, *not* the
1725 length of the string. Sigh. Even worse, it seems that the
1726 restriction is in number of input characters (see \xnn &
1727 \whatever). So we have to do this very carefully. */
1729 fprintf (file
, "\t.STRING \"");
1732 for (i
= 0; i
< size
; i
+= 4)
1736 for (io
= 0, co
= 0; io
< MIN (4, size
- i
); io
++)
1738 register unsigned int c
= p
[i
+ io
];
1740 if (c
== '\"' || c
== '\\')
1741 partial_output
[co
++] = '\\';
1742 if (c
>= ' ' && c
< 0177)
1743 partial_output
[co
++] = c
;
1747 partial_output
[co
++] = '\\';
1748 partial_output
[co
++] = 'x';
1749 hexd
= c
/ 16 - 0 + '0';
1751 hexd
-= '9' - 'a' + 1;
1752 partial_output
[co
++] = hexd
;
1753 hexd
= c
% 16 - 0 + '0';
1755 hexd
-= '9' - 'a' + 1;
1756 partial_output
[co
++] = hexd
;
1759 if (chars_output
+ co
> 243)
1761 fprintf (file
, "\"\n\t.STRING \"");
1764 fwrite (partial_output
, 1, co
, file
);
1768 fprintf (file
, "\"\n");
1771 /* You may have trouble believing this, but this is the HP-PA stack
1776 Variable arguments (optional; any number may be allocated)
1778 SP-(4*(N+9)) arg word N
1783 Fixed arguments (must be allocated; may remain unused)
1792 SP-32 External Data Pointer (DP)
1794 SP-24 External/stub RP (RP')
1798 SP-8 Calling Stub RP (RP'')
1803 SP-0 Stack Pointer (points to next available address)
1807 /* This function saves registers as follows. Registers marked with ' are
1808 this function's registers (as opposed to the previous function's).
1809 If a frame_pointer isn't needed, r4 is saved as a general register;
1810 the space for the frame pointer is still allocated, though, to keep
1816 SP (FP') Previous FP
1817 SP + 4 Alignment filler (sigh)
1818 SP + 8 Space for locals reserved here.
1822 SP + n All call saved register used.
1826 SP + o All call saved fp registers used.
1830 SP + p (SP') points to next available address.
1834 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
1835 Handle case where DISP > 8k by using the add_high_const pattern.
1837 Note in DISP > 8k case, we will leave the high part of the address
1838 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1840 store_reg (reg
, disp
, base
)
1841 int reg
, disp
, base
;
1843 if (VAL_14_BITS_P (disp
))
1845 emit_move_insn (gen_rtx (MEM
, SImode
,
1846 gen_rtx (PLUS
, SImode
,
1847 gen_rtx (REG
, SImode
, base
),
1849 gen_rtx (REG
, SImode
, reg
));
1853 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
1854 gen_rtx (REG
, SImode
, base
),
1856 emit_move_insn (gen_rtx (MEM
, SImode
,
1857 gen_rtx (LO_SUM
, SImode
,
1858 gen_rtx (REG
, SImode
, 1),
1860 gen_rtx (REG
, SImode
, reg
));
1864 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
1865 Handle case where DISP > 8k by using the add_high_const pattern.
1867 Note in DISP > 8k case, we will leave the high part of the address
1868 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1870 load_reg (reg
, disp
, base
)
1871 int reg
, disp
, base
;
1873 if (VAL_14_BITS_P (disp
))
1875 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1876 gen_rtx (MEM
, SImode
,
1877 gen_rtx (PLUS
, SImode
,
1878 gen_rtx (REG
, SImode
, base
),
1883 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
1884 gen_rtx (REG
, SImode
, base
),
1886 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1887 gen_rtx (MEM
, SImode
,
1888 gen_rtx (LO_SUM
, SImode
,
1889 gen_rtx (REG
, SImode
, 1),
1894 /* Emit RTL to set REG to the value specified by BASE+DISP.
1895 Handle case where DISP > 8k by using the add_high_const pattern.
1897 Note in DISP > 8k case, we will leave the high part of the address
1898 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
1900 set_reg_plus_d(reg
, base
, disp
)
1901 int reg
, base
, disp
;
1903 if (VAL_14_BITS_P (disp
))
1905 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1906 gen_rtx (PLUS
, SImode
,
1907 gen_rtx (REG
, SImode
, base
),
1912 emit_insn (gen_add_high_const (gen_rtx (REG
, SImode
, 1),
1913 gen_rtx (REG
, SImode
, base
),
1915 emit_move_insn (gen_rtx (REG
, SImode
, reg
),
1916 gen_rtx (LO_SUM
, SImode
,
1917 gen_rtx (REG
, SImode
, 1),
1922 /* Global variables set by FUNCTION_PROLOGUE. */
1923 /* Size of frame. Need to know this to emit return insns from
1925 static int actual_fsize
;
1926 static int local_fsize
, save_fregs
;
1929 compute_frame_size (size
, fregs_live
)
1933 extern int current_function_outgoing_args_size
;
1936 /* 8 is space for frame pointer + filler. If any frame is allocated
1937 we need to add this in because of STARTING_FRAME_OFFSET. */
1938 fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
1940 for (i
= 18; i
>= 4; i
--)
1942 if (regs_ever_live
[i
])
1945 /* If we don't have a frame pointer, the register normally used for that
1946 purpose is saved just like other registers, not in the "frame marker". */
1947 if (! frame_pointer_needed
)
1949 if (regs_ever_live
[FRAME_POINTER_REGNUM
])
1952 fsize
= (fsize
+ 7) & ~7;
1954 for (i
= 66; i
>= 48; i
-= 2)
1955 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
1962 fsize
+= current_function_outgoing_args_size
;
1963 if (! leaf_function_p () || fsize
)
1965 return (fsize
+ 63) & ~63;
1968 rtx hp_profile_label_rtx
;
1969 static char hp_profile_label_name
[8];
1971 output_function_prologue (file
, size
)
1975 /* The function's label and associated .PROC must never be
1976 separated and must be output *after* any profiling declarations
1977 to avoid changing spaces/subspaces within a procedure. */
1978 ASM_OUTPUT_LABEL (file
, XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0));
1979 fputs ("\t.PROC\n", file
);
1981 /* hppa_expand_prologue does the dirty work now. We just need
1982 to output the assembler directives which denote the start
1984 fprintf (file
, "\t.CALLINFO FRAME=%d", actual_fsize
);
1985 if (regs_ever_live
[2] || profile_flag
)
1986 fprintf (file
, ",CALLS,SAVE_RP");
1988 fprintf (file
, ",NO_CALLS");
1990 if (frame_pointer_needed
)
1991 fprintf (file
, ",SAVE_SP");
1993 /* Pass on information about the number of callee register saves
1994 performed in the prologue.
1996 The compiler is supposed to pass the highest register number
1997 saved, the assembler then has to adjust that number before
1998 entering it into the unwind descriptor (to account for any
1999 caller saved registers with lower register numbers than the
2000 first callee saved register). */
2002 fprintf (file
, ",ENTRY_GR=%d", gr_saved
+ 2);
2005 fprintf (file
, ",ENTRY_FR=%d", fr_saved
+ 11);
2007 fprintf (file
, "\n\t.ENTRY\n");
2009 /* Horrid hack. emit_function_prologue will modify this RTL in
2010 place to get the expected results. */
2012 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name
, "LP",
2013 hp_profile_labelno
);
2015 /* If we're using GAS and not using the portable runtime model, then
2016 we don't need to accumulate the total number of code bytes. */
2017 if (TARGET_GAS
&& ! TARGET_PORTABLE_RUNTIME
)
2018 total_code_bytes
= 0;
2019 else if (insn_addresses
)
2021 unsigned int old_total
= total_code_bytes
;
2023 total_code_bytes
+= insn_addresses
[INSN_UID (get_last_insn())];
2024 total_code_bytes
+= FUNCTION_BOUNDARY
/ BITS_PER_UNIT
;
2026 /* Be prepared to handle overflows. */
2027 total_code_bytes
= old_total
> total_code_bytes
? -1 : total_code_bytes
;
2030 total_code_bytes
= -1;
2034 hppa_expand_prologue()
2036 extern char call_used_regs
[];
2037 int size
= get_frame_size ();
2038 int merge_sp_adjust_with_store
= 0;
2040 rtx tmpreg
, size_rtx
;
2045 local_fsize
= size
+ (size
|| frame_pointer_needed
? 8 : 0);
2046 actual_fsize
= compute_frame_size (size
, &save_fregs
);
2048 /* Compute a few things we will use often. */
2049 tmpreg
= gen_rtx (REG
, SImode
, 1);
2050 size_rtx
= GEN_INT (actual_fsize
);
2052 /* Save RP first. The calling conventions manual states RP will
2053 always be stored into the caller's frame at sp-20. */
2054 if (regs_ever_live
[2] || profile_flag
)
2055 store_reg (2, -20, STACK_POINTER_REGNUM
);
2057 /* Allocate the local frame and set up the frame pointer if needed. */
2059 if (frame_pointer_needed
)
2061 /* Copy the old frame pointer temporarily into %r1. Set up the
2062 new stack pointer, then store away the saved old frame pointer
2063 into the stack at sp+actual_fsize and at the same time update
2064 the stack pointer by actual_fsize bytes. Two versions, first
2065 handles small (<8k) frames. The second handles large (>8k)
2067 emit_move_insn (tmpreg
, frame_pointer_rtx
);
2068 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
2069 if (VAL_14_BITS_P (actual_fsize
))
2070 emit_insn (gen_post_stwm (stack_pointer_rtx
,
2075 /* It is incorrect to store the saved frame pointer at *sp,
2076 then increment sp (writes beyond the current stack boundary).
2078 So instead use stwm to store at *sp and post-increment the
2079 stack pointer as an atomic operation. Then increment sp to
2080 finish allocating the new frame. */
2081 emit_insn (gen_post_stwm (stack_pointer_rtx
,
2083 GEN_INT (64), tmpreg
));
2084 set_reg_plus_d (STACK_POINTER_REGNUM
,
2085 STACK_POINTER_REGNUM
,
2089 /* no frame pointer needed. */
2092 /* In some cases we can perform the first callee register save
2093 and allocating the stack frame at the same time. If so, just
2094 make a note of it and defer allocating the frame until saving
2095 the callee registers. */
2096 if (VAL_14_BITS_P (-actual_fsize
)
2100 merge_sp_adjust_with_store
= 1;
2101 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2102 else if (actual_fsize
!= 0)
2103 set_reg_plus_d (STACK_POINTER_REGNUM
,
2104 STACK_POINTER_REGNUM
,
2107 /* The hppa calling conventions say that that %r19, the pic offset
2108 register, is saved at sp - 32 (in this function's frame) when
2109 generating PIC code. FIXME: What is the correct thing to do
2110 for functions which make no calls and allocate no frame? Do
2111 we need to allocate a frame, or can we just omit the save? For
2112 now we'll just omit the save. */
2113 if (actual_fsize
!= 0 && flag_pic
)
2114 store_reg (PIC_OFFSET_TABLE_REGNUM
, -32, STACK_POINTER_REGNUM
);
2118 Instead of taking one argument, the counter label, as most normal
2119 mcounts do, _mcount appears to behave differently on the HPPA. It
2120 takes the return address of the caller, the address of this routine,
2121 and the address of the label. Also, it isn't magic, so
2122 argument registers have to be preserved. */
2125 int pc_offset
, i
, arg_offset
, basereg
, offsetadj
;
2127 pc_offset
= 4 + (frame_pointer_needed
2128 ? (VAL_14_BITS_P (actual_fsize
) ? 12 : 20)
2129 : (VAL_14_BITS_P (actual_fsize
) ? 4 : 8));
2131 /* When the function has a frame pointer, use it as the base
2132 register for saving/restore registers. Else use the stack
2133 pointer. Adjust the offset according to the frame size if
2134 this function does not have a frame pointer. */
2136 basereg
= frame_pointer_needed
? FRAME_POINTER_REGNUM
2137 : STACK_POINTER_REGNUM
;
2138 offsetadj
= frame_pointer_needed
? 0 : actual_fsize
;
2140 /* Horrid hack. emit_function_prologue will modify this RTL in
2141 place to get the expected results. sprintf here is just to
2142 put something in the name. */
2143 sprintf(hp_profile_label_name
, "LP$%04d", -1);
2144 hp_profile_label_rtx
= gen_rtx (SYMBOL_REF
, SImode
,
2145 hp_profile_label_name
);
2146 if (current_function_returns_struct
)
2147 store_reg (STRUCT_VALUE_REGNUM
, - 12 - offsetadj
, basereg
);
2149 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2150 if (regs_ever_live
[i
])
2152 store_reg (i
, arg_offset
, basereg
);
2153 /* Deal with arg_offset not fitting in 14 bits. */
2154 pc_offset
+= VAL_14_BITS_P (arg_offset
) ? 4 : 8;
2157 emit_move_insn (gen_rtx (REG
, SImode
, 26), gen_rtx (REG
, SImode
, 2));
2158 emit_move_insn (tmpreg
, gen_rtx (HIGH
, SImode
, hp_profile_label_rtx
));
2159 emit_move_insn (gen_rtx (REG
, SImode
, 24),
2160 gen_rtx (LO_SUM
, SImode
, tmpreg
, hp_profile_label_rtx
));
2161 /* %r25 is set from within the output pattern. */
2162 emit_insn (gen_call_profiler (GEN_INT (- pc_offset
- 20)));
2164 /* Restore argument registers. */
2165 for (i
= 26, arg_offset
= -36 - offsetadj
; i
>= 23; i
--, arg_offset
-= 4)
2166 if (regs_ever_live
[i
])
2167 load_reg (i
, arg_offset
, basereg
);
2169 if (current_function_returns_struct
)
2170 load_reg (STRUCT_VALUE_REGNUM
, -12 - offsetadj
, basereg
);
2174 /* Normal register save.
2176 Do not save the frame pointer in the frame_pointer_needed case. It
2177 was done earlier. */
2178 if (frame_pointer_needed
)
2180 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
2181 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2183 store_reg (i
, offset
, FRAME_POINTER_REGNUM
);
2187 /* Account for %r4 which is saved in a special place. */
2190 /* No frame pointer needed. */
2193 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
2194 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2196 /* If merge_sp_adjust_with_store is nonzero, then we can
2197 optimize the first GR save. */
2198 if (merge_sp_adjust_with_store
)
2200 merge_sp_adjust_with_store
= 0;
2201 emit_insn (gen_post_stwm (stack_pointer_rtx
,
2204 gen_rtx (REG
, SImode
, i
)));
2207 store_reg (i
, offset
, STACK_POINTER_REGNUM
);
2212 /* If we wanted to merge the SP adjustment with a GR save, but we never
2213 did any GR saves, then just emit the adjustment here. */
2214 if (merge_sp_adjust_with_store
)
2215 set_reg_plus_d (STACK_POINTER_REGNUM
,
2216 STACK_POINTER_REGNUM
,
2220 /* Align pointer properly (doubleword boundary). */
2221 offset
= (offset
+ 7) & ~7;
2223 /* Floating point register store. */
2227 /* First get the frame or stack pointer to the start of the FP register
2229 if (frame_pointer_needed
)
2230 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
2232 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
2234 /* Now actually save the FP registers. */
2235 for (i
= 66; i
>= 48; i
-= 2)
2236 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2238 emit_move_insn (gen_rtx (MEM
, DFmode
,
2239 gen_rtx (POST_INC
, DFmode
, tmpreg
)),
2240 gen_rtx (REG
, DFmode
, i
));
2245 /* When generating PIC code it is necessary to save/restore the
2246 PIC register around each function call. We used to do this
2247 in the call patterns themselves, but that implementation
2248 made incorrect assumptions about using global variables to hold
2249 per-function rtl code generated in the backend.
2251 So instead, we copy the PIC register into a reserved callee saved
2252 register in the prologue. Then after each call we reload the PIC
2253 register from the callee saved register. We also reload the PIC
2254 register from the callee saved register in the epilogue ensure the
2255 PIC register is valid at function exit.
2257 This may (depending on the exact characteristics of the function)
2258 even be more efficient.
2260 Avoid this if the callee saved register wasn't used (these are
2262 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM_SAVED
])
2263 emit_move_insn (gen_rtx (REG
, SImode
, PIC_OFFSET_TABLE_REGNUM_SAVED
),
2264 gen_rtx (REG
, SImode
, PIC_OFFSET_TABLE_REGNUM
));
2269 output_function_epilogue (file
, size
)
2273 rtx insn
= get_last_insn ();
2276 /* hppa_expand_epilogue does the dirty work now. We just need
2277 to output the assembler directives which denote the end
2280 To make debuggers happy, emit a nop if the epilogue was completely
2281 eliminated due to a volatile call as the last insn in the
2282 current function. That way the return address (in %r2) will
2283 always point to a valid instruction in the current function. */
2285 /* Get the last real insn. */
2286 if (GET_CODE (insn
) == NOTE
)
2287 insn
= prev_real_insn (insn
);
2289 /* If it is a sequence, then look inside. */
2290 if (insn
&& GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2291 insn
= XVECEXP (PATTERN (insn
), 0, 0);
2293 /* If insn is a CALL_INSN, then it must be a call to a volatile
2294 function (otherwise there would be epilogue insns). */
2295 if (insn
&& GET_CODE (insn
) == CALL_INSN
)
2296 fprintf (file
, "\tnop\n");
2298 fprintf (file
, "\t.EXIT\n\t.PROCEND\n");
2300 /* If we have deferred plabels, then we need to switch into the data
2301 section and align it to a 4 byte boundary before we output the
2302 deferred plabels. */
2303 if (n_deferred_plabels
)
2306 ASM_OUTPUT_ALIGN (file
, 2);
2309 /* Now output the deferred plabels. */
2310 for (i
= 0; i
< n_deferred_plabels
; i
++)
2312 ASM_OUTPUT_INTERNAL_LABEL (file
, "L", CODE_LABEL_NUMBER (deferred_plabels
[i
].internal_label
));
2313 ASM_OUTPUT_INT (file
, deferred_plabels
[i
].symbol
);
2315 n_deferred_plabels
= 0;
2319 hppa_expand_epilogue ()
2323 int merge_sp_adjust_with_load
= 0;
2325 /* We will use this often. */
2326 tmpreg
= gen_rtx (REG
, SImode
, 1);
2328 /* Try to restore RP early to avoid load/use interlocks when
2329 RP gets used in the return (bv) instruction. This appears to still
2330 be necessary even when we schedule the prologue and epilogue. */
2331 if (frame_pointer_needed
2332 && (regs_ever_live
[2] || profile_flag
))
2333 load_reg (2, -20, FRAME_POINTER_REGNUM
);
2335 /* No frame pointer, and stack is smaller than 8k. */
2336 else if (! frame_pointer_needed
2337 && VAL_14_BITS_P (actual_fsize
+ 20)
2338 && (regs_ever_live
[2] || profile_flag
))
2339 load_reg (2, - (actual_fsize
+ 20), STACK_POINTER_REGNUM
);
2341 /* General register restores. */
2342 if (frame_pointer_needed
)
2344 for (i
= 18, offset
= local_fsize
; i
>= 4; i
--)
2345 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2347 load_reg (i
, offset
, FRAME_POINTER_REGNUM
);
2353 for (i
= 18, offset
= local_fsize
- actual_fsize
; i
>= 3; i
--)
2354 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2356 /* Only for the first load.
2357 merge_sp_adjust_with_load holds the register load
2358 with which we will merge the sp adjustment. */
2359 if (VAL_14_BITS_P (actual_fsize
+ 20)
2361 && ! merge_sp_adjust_with_load
)
2362 merge_sp_adjust_with_load
= i
;
2364 load_reg (i
, offset
, STACK_POINTER_REGNUM
);
2369 /* Align pointer properly (doubleword boundary). */
2370 offset
= (offset
+ 7) & ~7;
2372 /* FP register restores. */
2375 /* Adjust the register to index off of. */
2376 if (frame_pointer_needed
)
2377 set_reg_plus_d (1, FRAME_POINTER_REGNUM
, offset
);
2379 set_reg_plus_d (1, STACK_POINTER_REGNUM
, offset
);
2381 /* Actually do the restores now. */
2382 for (i
= 66; i
>= 48; i
-= 2)
2383 if (regs_ever_live
[i
] || regs_ever_live
[i
+ 1])
2384 emit_move_insn (gen_rtx (REG
, DFmode
, i
),
2385 gen_rtx (MEM
, DFmode
,
2386 gen_rtx (POST_INC
, DFmode
, tmpreg
)));
2389 /* No frame pointer, but we have a stack greater than 8k. We restore
2390 %r2 very late in this case. (All other cases are restored as early
2392 if (! frame_pointer_needed
2393 && ! VAL_14_BITS_P (actual_fsize
+ 20)
2394 && (regs_ever_live
[2] || profile_flag
))
2396 set_reg_plus_d (STACK_POINTER_REGNUM
,
2397 STACK_POINTER_REGNUM
,
2400 /* This used to try and be clever by not depending on the value in
2401 %r30 and instead use the value held in %r1 (so that the 2nd insn
2402 which sets %r30 could be put in the delay slot of the return insn).
2404 That won't work since if the stack is exactly 8k set_reg_plus_d
2405 doesn't set %r1, just %r30. */
2406 load_reg (2, - 20, STACK_POINTER_REGNUM
);
2409 /* Reset stack pointer (and possibly frame pointer). The stack
2410 pointer is initially set to fp + 64 to avoid a race condition. */
2411 else if (frame_pointer_needed
)
2413 /* Emit a blockage insn here to keep these insns from being moved
2414 to the beginning of the prologue or into the main instruction
2415 stream, doing so avoids some very obscure problems. */
2416 emit_insn (gen_blockage ());
2417 set_reg_plus_d (STACK_POINTER_REGNUM
, FRAME_POINTER_REGNUM
, 64);
2418 emit_insn (gen_pre_ldwm (stack_pointer_rtx
, stack_pointer_rtx
,
2419 GEN_INT (-64), frame_pointer_rtx
));
2421 /* If we were deferring a callee register restore, do it now. */
2422 else if (! frame_pointer_needed
&& merge_sp_adjust_with_load
)
2423 emit_insn (gen_pre_ldwm (stack_pointer_rtx
,
2425 GEN_INT (- actual_fsize
),
2426 gen_rtx (REG
, SImode
,
2427 merge_sp_adjust_with_load
)));
2428 else if (actual_fsize
!= 0)
2429 set_reg_plus_d (STACK_POINTER_REGNUM
,
2430 STACK_POINTER_REGNUM
,
2434 /* This is only valid once reload has completed because it depends on
2435 knowing exactly how much (if any) frame there is and...
2437 It's only valid if there is no frame marker to de-allocate and...
2439 It's only valid if %r2 hasn't been saved into the caller's frame
2440 (we're not profiling and %r2 isn't live anywhere). */
2442 hppa_can_use_return_insn_p ()
2444 return (reload_completed
2445 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
2447 && ! regs_ever_live
[2]
2448 && ! frame_pointer_needed
);
2452 emit_bcond_fp (code
, operand0
)
2456 emit_jump_insn (gen_rtx (SET
, VOIDmode
, pc_rtx
,
2457 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2458 gen_rtx (code
, VOIDmode
,
2459 gen_rtx (REG
, CCFPmode
, 0),
2461 gen_rtx (LABEL_REF
, VOIDmode
, operand0
),
2467 gen_cmp_fp (code
, operand0
, operand1
)
2469 rtx operand0
, operand1
;
2471 return gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, CCFPmode
, 0),
2472 gen_rtx (code
, CCFPmode
, operand0
, operand1
));
2475 /* Adjust the cost of a scheduling dependency. Return the new cost of
2476 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
2479 pa_adjust_cost (insn
, link
, dep_insn
, cost
)
2485 if (! recog_memoized (insn
))
2488 if (REG_NOTE_KIND (link
) == 0)
2490 /* Data dependency; DEP_INSN writes a register that INSN reads some
2493 if (get_attr_type (insn
) == TYPE_FPSTORE
)
2495 rtx pat
= PATTERN (insn
);
2496 rtx dep_pat
= PATTERN (dep_insn
);
2497 if (GET_CODE (pat
) == PARALLEL
)
2499 /* This happens for the fstXs,mb patterns. */
2500 pat
= XVECEXP (pat
, 0, 0);
2502 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
2503 /* If this happens, we have to extend this to schedule
2504 optimally. Return 0 for now. */
2507 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
2509 if (! recog_memoized (dep_insn
))
2511 /* DEP_INSN is writing its result to the register
2512 being stored in the fpstore INSN. */
2513 switch (get_attr_type (dep_insn
))
2516 /* This cost 3 cycles, not 2 as the md says for the
2517 700 and 7100. Note scaling of cost for 7100. */
2518 return cost
+ (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
2525 case TYPE_FPSQRTSGL
:
2526 case TYPE_FPSQRTDBL
:
2527 /* In these important cases, we save one cycle compared to
2528 when flop instruction feed each other. */
2529 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
2537 /* For other data dependencies, the default cost specified in the
2541 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
2543 /* Anti dependency; DEP_INSN reads a register that INSN writes some
2546 if (get_attr_type (insn
) == TYPE_FPLOAD
)
2548 rtx pat
= PATTERN (insn
);
2549 rtx dep_pat
= PATTERN (dep_insn
);
2550 if (GET_CODE (pat
) == PARALLEL
)
2552 /* This happens for the fldXs,mb patterns. */
2553 pat
= XVECEXP (pat
, 0, 0);
2555 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
2556 /* If this happens, we have to extend this to schedule
2557 optimally. Return 0 for now. */
2560 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
2562 if (! recog_memoized (dep_insn
))
2564 switch (get_attr_type (dep_insn
))
2571 case TYPE_FPSQRTSGL
:
2572 case TYPE_FPSQRTDBL
:
2573 /* A fpload can't be issued until one cycle before a
2574 preceding arithmetic operation has finished if
2575 the target of the fpload is any of the sources
2576 (or destination) of the arithmetic operation. */
2577 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
2584 else if (get_attr_type (insn
) == TYPE_FPALU
)
2586 rtx pat
= PATTERN (insn
);
2587 rtx dep_pat
= PATTERN (dep_insn
);
2588 if (GET_CODE (pat
) == PARALLEL
)
2590 /* This happens for the fldXs,mb patterns. */
2591 pat
= XVECEXP (pat
, 0, 0);
2593 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
2594 /* If this happens, we have to extend this to schedule
2595 optimally. Return 0 for now. */
2598 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
2600 if (! recog_memoized (dep_insn
))
2602 switch (get_attr_type (dep_insn
))
2606 case TYPE_FPSQRTSGL
:
2607 case TYPE_FPSQRTDBL
:
2608 /* An ALU flop can't be issued until two cycles before a
2609 preceding divide or sqrt operation has finished if
2610 the target of the ALU flop is any of the sources
2611 (or destination) of the divide or sqrt operation. */
2612 return cost
- (pa_cpu
== PROCESSOR_700
) ? 2 : 4;
2620 /* For other anti dependencies, the cost is 0. */
2623 else if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
2625 /* Output dependency; DEP_INSN writes a register that INSN writes some
2627 if (get_attr_type (insn
) == TYPE_FPLOAD
)
2629 rtx pat
= PATTERN (insn
);
2630 rtx dep_pat
= PATTERN (dep_insn
);
2631 if (GET_CODE (pat
) == PARALLEL
)
2633 /* This happens for the fldXs,mb patterns. */
2634 pat
= XVECEXP (pat
, 0, 0);
2636 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
2637 /* If this happens, we have to extend this to schedule
2638 optimally. Return 0 for now. */
2641 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
2643 if (! recog_memoized (dep_insn
))
2645 switch (get_attr_type (dep_insn
))
2652 case TYPE_FPSQRTSGL
:
2653 case TYPE_FPSQRTDBL
:
2654 /* A fpload can't be issued until one cycle before a
2655 preceding arithmetic operation has finished if
2656 the target of the fpload is the destination of the
2657 arithmetic operation. */
2658 return cost
- (pa_cpu
== PROCESSOR_700
) ? 1 : 2;
2665 else if (get_attr_type (insn
) == TYPE_FPALU
)
2667 rtx pat
= PATTERN (insn
);
2668 rtx dep_pat
= PATTERN (dep_insn
);
2669 if (GET_CODE (pat
) == PARALLEL
)
2671 /* This happens for the fldXs,mb patterns. */
2672 pat
= XVECEXP (pat
, 0, 0);
2674 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
2675 /* If this happens, we have to extend this to schedule
2676 optimally. Return 0 for now. */
2679 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
2681 if (! recog_memoized (dep_insn
))
2683 switch (get_attr_type (dep_insn
))
2687 case TYPE_FPSQRTSGL
:
2688 case TYPE_FPSQRTDBL
:
2689 /* An ALU flop can't be issued until two cycles before a
2690 preceding divide or sqrt operation has finished if
2691 the target of the ALU flop is also the target of
2692 of the divide or sqrt operation. */
2693 return cost
- (pa_cpu
== PROCESSOR_700
) ? 2 : 4;
2701 /* For other output dependencies, the cost is 0. */
2708 /* Return any length adjustment needed by INSN which already has its length
2709 computed as LENGTH. Return zero if no adjustment is necessary.
2711 For the PA: function calls, millicode calls, and backwards short
2712 conditional branches with unfilled delay slots need an adjustment by +1
2713 (to account for the NOP which will be inserted into the instruction stream).
2715 Also compute the length of an inline block move here as it is too
2716 complicated to express as a length attribute in pa.md. */
2718 pa_adjust_insn_length (insn
, length
)
2722 rtx pat
= PATTERN (insn
);
2724 /* Call insns which are *not* indirect and have unfilled delay slots. */
2725 if (GET_CODE (insn
) == CALL_INSN
)
2728 if (GET_CODE (XVECEXP (pat
, 0, 0)) == CALL
2729 && GET_CODE (XEXP (XEXP (XVECEXP (pat
, 0, 0), 0), 0)) == SYMBOL_REF
)
2731 else if (GET_CODE (XVECEXP (pat
, 0, 0)) == SET
2732 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat
, 0, 0), 1), 0), 0))
2738 /* Jumps inside switch tables which have unfilled delay slots
2739 also need adjustment. */
2740 else if (GET_CODE (insn
) == JUMP_INSN
2741 && simplejump_p (insn
)
2742 && GET_MODE (PATTERN (insn
)) == DImode
)
2744 /* Millicode insn with an unfilled delay slot. */
2745 else if (GET_CODE (insn
) == INSN
2746 && GET_CODE (pat
) != SEQUENCE
2747 && GET_CODE (pat
) != USE
2748 && GET_CODE (pat
) != CLOBBER
2749 && get_attr_type (insn
) == TYPE_MILLI
)
2751 /* Block move pattern. */
2752 else if (GET_CODE (insn
) == INSN
2753 && GET_CODE (pat
) == PARALLEL
2754 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == MEM
2755 && GET_CODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == MEM
2756 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 0)) == BLKmode
2757 && GET_MODE (XEXP (XVECEXP (pat
, 0, 0), 1)) == BLKmode
)
2758 return compute_movstrsi_length (insn
) - 4;
2759 /* Conditional branch with an unfilled delay slot. */
2760 else if (GET_CODE (insn
) == JUMP_INSN
&& ! simplejump_p (insn
))
2762 /* Adjust a short backwards conditional with an unfilled delay slot. */
2763 if (GET_CODE (pat
) == SET
2765 && ! forward_branch_p (insn
))
2767 /* Adjust dbra insn with short backwards conditional branch with
2768 unfilled delay slot -- only for case where counter is in a
2769 general register register. */
2770 else if (GET_CODE (pat
) == PARALLEL
2771 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
2772 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == REG
2773 && ! FP_REG_P (XEXP (XVECEXP (pat
, 0, 1), 0))
2775 && ! forward_branch_p (insn
))
2784 /* Print operand X (an rtx) in assembler syntax to file FILE.
2785 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2786 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2789 print_operand (file
, x
, code
)
2797 /* Output a 'nop' if there's nothing for the delay slot. */
2798 if (dbr_sequence_length () == 0)
2799 fputs ("\n\tnop", file
);
2802 /* Output an nullification completer if there's nothing for the */
2803 /* delay slot or nullification is requested. */
2804 if (dbr_sequence_length () == 0 ||
2806 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))))
2810 /* Print out the second register name of a register pair.
2811 I.e., R (6) => 7. */
2812 fputs (reg_names
[REGNO (x
)+1], file
);
2815 /* A register or zero. */
2817 || (x
== CONST0_RTX (DFmode
))
2818 || (x
== CONST0_RTX (SFmode
)))
2825 case 'C': /* Plain (C)ondition */
2827 switch (GET_CODE (x
))
2830 fprintf (file
, "="); break;
2832 fprintf (file
, "<>"); break;
2834 fprintf (file
, ">"); break;
2836 fprintf (file
, ">="); break;
2838 fprintf (file
, ">>="); break;
2840 fprintf (file
, ">>"); break;
2842 fprintf (file
, "<"); break;
2844 fprintf (file
, "<="); break;
2846 fprintf (file
, "<<="); break;
2848 fprintf (file
, "<<"); break;
2853 case 'N': /* Condition, (N)egated */
2854 switch (GET_CODE (x
))
2857 fprintf (file
, "<>"); break;
2859 fprintf (file
, "="); break;
2861 fprintf (file
, "<="); break;
2863 fprintf (file
, "<"); break;
2865 fprintf (file
, "<<"); break;
2867 fprintf (file
, "<<="); break;
2869 fprintf (file
, ">="); break;
2871 fprintf (file
, ">"); break;
2873 fprintf (file
, ">>"); break;
2875 fprintf (file
, ">>="); break;
2880 /* For floating point comparisons. Need special conditions to deal
2881 with NaNs properly. */
2883 switch (GET_CODE (x
))
2886 fprintf (file
, "!="); break;
2888 fprintf (file
, "="); break;
2890 fprintf (file
, "!>"); break;
2892 fprintf (file
, "!>="); break;
2894 fprintf (file
, "!<"); break;
2896 fprintf (file
, "!<="); break;
2901 /* Reversed floating point comparison. Need special conditions to
2902 deal with NaNs properly. */
2904 switch (GET_CODE (x
))
2907 fprintf (file
, "?="); break;
2909 fprintf (file
, "!?="); break;
2911 fprintf (file
, "!<="); break;
2913 fprintf (file
, "!<"); break;
2915 fprintf (file
, "!>="); break;
2917 fprintf (file
, "!>"); break;
2922 case 'S': /* Condition, operands are (S)wapped. */
2923 switch (GET_CODE (x
))
2926 fprintf (file
, "="); break;
2928 fprintf (file
, "<>"); break;
2930 fprintf (file
, "<"); break;
2932 fprintf (file
, "<="); break;
2934 fprintf (file
, "<<="); break;
2936 fprintf (file
, "<<"); break;
2938 fprintf (file
, ">"); break;
2940 fprintf (file
, ">="); break;
2942 fprintf (file
, ">>="); break;
2944 fprintf (file
, ">>"); break;
2949 case 'B': /* Condition, (B)oth swapped and negate. */
2950 switch (GET_CODE (x
))
2953 fprintf (file
, "<>"); break;
2955 fprintf (file
, "="); break;
2957 fprintf (file
, ">="); break;
2959 fprintf (file
, ">"); break;
2961 fprintf (file
, ">>"); break;
2963 fprintf (file
, ">>="); break;
2965 fprintf (file
, "<="); break;
2967 fprintf (file
, "<"); break;
2969 fprintf (file
, "<<"); break;
2971 fprintf (file
, "<<="); break;
2977 if (GET_CODE (x
) == CONST_INT
)
2979 fprintf (file
, "%d", ~INTVAL (x
));
2984 if (GET_CODE (x
) == CONST_INT
)
2986 fprintf (file
, "%d", 32 - (INTVAL (x
) & 31));
2991 if (GET_CODE (x
) == CONST_INT
&& exact_log2 (INTVAL (x
)) >= 0)
2993 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
2998 if (GET_CODE (x
) == CONST_INT
)
3000 fprintf (file
, "%d", 31 - (INTVAL (x
) & 31));
3005 if (GET_CODE (x
) == CONST_INT
)
3009 switch (GET_CODE (XEXP (x
, 0)))
3013 fprintf (file
, "s,mb");
3017 fprintf (file
, "s,ma");
3024 switch (GET_CODE (XEXP (x
, 0)))
3028 fprintf (file
, ",mb");
3032 fprintf (file
, ",ma");
3039 output_global_address (file
, x
, 0);
3042 output_global_address (file
, x
, 1);
3044 case 0: /* Don't do anything special */
3049 compute_zdepi_operands (INTVAL (x
), op
);
3050 fprintf (file
, "%d,%d,%d", op
[0], op
[1], op
[2]);
3056 if (GET_CODE (x
) == REG
)
3058 if (FP_REG_P (x
) && GET_MODE_SIZE (GET_MODE (x
)) <= 4 && (REGNO (x
) & 1) == 0)
3059 fprintf (file
, "%sL", reg_names
[REGNO (x
)]);
3061 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
3063 else if (GET_CODE (x
) == MEM
)
3065 int size
= GET_MODE_SIZE (GET_MODE (x
));
3066 rtx base
= XEXP (XEXP (x
, 0), 0);
3067 switch (GET_CODE (XEXP (x
, 0)))
3071 fprintf (file
, "-%d(0,%s)", size
, reg_names
[REGNO (base
)]);
3075 fprintf (file
, "%d(0,%s)", size
, reg_names
[REGNO (base
)]);
3078 output_address (XEXP (x
, 0));
3083 output_addr_const (file
, x
);
3086 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3089 output_global_address (file
, x
, round_constant
)
3095 /* Imagine (high (const (plus ...))). */
3096 if (GET_CODE (x
) == HIGH
)
3099 if (GET_CODE (x
) == SYMBOL_REF
&& read_only_operand (x
))
3100 assemble_name (file
, XSTR (x
, 0));
3101 else if (GET_CODE (x
) == SYMBOL_REF
&& !flag_pic
)
3103 assemble_name (file
, XSTR (x
, 0));
3104 fprintf (file
, "-$global$");
3106 else if (GET_CODE (x
) == CONST
)
3109 int offset
= 0; /* assembler wants -$global$ at end */
3112 if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)
3114 base
= XEXP (XEXP (x
, 0), 0);
3115 output_addr_const (file
, base
);
3117 else if (GET_CODE (XEXP (XEXP (x
, 0), 0)) == CONST_INT
)
3118 offset
= INTVAL (XEXP (XEXP (x
, 0), 0));
3121 if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == SYMBOL_REF
)
3123 base
= XEXP (XEXP (x
, 0), 1);
3124 output_addr_const (file
, base
);
3126 else if (GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
3127 offset
= INTVAL (XEXP (XEXP (x
, 0),1));
3130 /* How bogus. The compiler is apparently responsible for
3131 rounding the constant if it uses an LR field selector.
3133 The linker and/or assembler seem a better place since
3134 they have to do this kind of thing already.
3136 If we fail to do this, HP's optimizing linker may eliminate
3137 an addil, but not update the ldw/stw/ldo instruction that
3138 uses the result of the addil. */
3140 offset
= ((offset
+ 0x1000) & ~0x1fff);
3142 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
3152 else if (GET_CODE (XEXP (x
, 0)) == MINUS
3153 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
))
3157 if (!read_only_operand (base
) && !flag_pic
)
3158 fprintf (file
, "-$global$");
3160 fprintf (file
,"%s%d", sep
, offset
);
3163 output_addr_const (file
, x
);
3166 /* HP's millicode routines mean something special to the assembler.
3167 Keep track of which ones we have used. */
3169 enum millicodes
{ remI
, remU
, divI
, divU
, mulI
, mulU
, end1000
};
3170 static char imported
[(int)end1000
];
3171 static char *milli_names
[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
3172 static char import_string
[] = ".IMPORT $$....,MILLICODE";
3173 #define MILLI_START 10
3177 enum millicodes code
;
3179 char str
[sizeof (import_string
)];
3181 if (!imported
[(int)code
])
3183 imported
[(int)code
] = 1;
3184 strcpy (str
, import_string
);
3185 strncpy (str
+ MILLI_START
, milli_names
[(int)code
], 4);
3186 output_asm_insn (str
, 0);
3190 /* The register constraints have put the operands and return value in
3191 the proper registers. */
3194 output_mul_insn (unsignedp
, insn
)
3198 import_milli (mulI
);
3199 return output_millicode_call (insn
, gen_rtx (SYMBOL_REF
, SImode
, "$$mulI"));
3202 /* Emit the rtl for doing a division by a constant. */
3204 /* Do magic division millicodes exist for this value? */
3205 static int magic_milli
[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
3208 /* We'll use an array to keep track of the magic millicodes and
3209 whether or not we've used them already. [n][0] is signed, [n][1] is
3212 static int div_milli
[16][2];
3215 div_operand (op
, mode
)
3217 enum machine_mode mode
;
3219 return (mode
== SImode
3220 && ((GET_CODE (op
) == REG
&& REGNO (op
) == 25)
3221 || (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) > 0
3222 && INTVAL (op
) < 16 && magic_milli
[INTVAL (op
)])));
3226 emit_hpdiv_const (operands
, unsignedp
)
3230 if (GET_CODE (operands
[2]) == CONST_INT
3231 && INTVAL (operands
[2]) > 0
3232 && INTVAL (operands
[2]) < 16
3233 && magic_milli
[INTVAL (operands
[2])])
3235 emit_move_insn ( gen_rtx (REG
, SImode
, 26), operands
[1]);
3238 (PARALLEL
, VOIDmode
,
3239 gen_rtvec (5, gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, SImode
, 29),
3240 gen_rtx (unsignedp
? UDIV
: DIV
, SImode
,
3241 gen_rtx (REG
, SImode
, 26),
3243 gen_rtx (CLOBBER
, VOIDmode
, operands
[3]),
3244 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 26)),
3245 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 25)),
3246 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (REG
, SImode
, 31)))));
3247 emit_move_insn (operands
[0], gen_rtx (REG
, SImode
, 29));
3254 output_div_insn (operands
, unsignedp
, insn
)
3261 /* If the divisor is a constant, try to use one of the special
3263 if (GET_CODE (operands
[0]) == CONST_INT
)
3265 static char buf
[100];
3266 divisor
= INTVAL (operands
[0]);
3267 if (!div_milli
[divisor
][unsignedp
])
3269 div_milli
[divisor
][unsignedp
] = 1;
3271 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands
);
3273 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands
);
3277 sprintf (buf
, "$$divU_%d", INTVAL (operands
[0]));
3278 return output_millicode_call (insn
,
3279 gen_rtx (SYMBOL_REF
, SImode
, buf
));
3283 sprintf (buf
, "$$divI_%d", INTVAL (operands
[0]));
3284 return output_millicode_call (insn
,
3285 gen_rtx (SYMBOL_REF
, SImode
, buf
));
3288 /* Divisor isn't a special constant. */
3293 import_milli (divU
);
3294 return output_millicode_call (insn
,
3295 gen_rtx (SYMBOL_REF
, SImode
, "$$divU"));
3299 import_milli (divI
);
3300 return output_millicode_call (insn
,
3301 gen_rtx (SYMBOL_REF
, SImode
, "$$divI"));
3306 /* Output a $$rem millicode to do mod. */
3309 output_mod_insn (unsignedp
, insn
)
3315 import_milli (remU
);
3316 return output_millicode_call (insn
,
3317 gen_rtx (SYMBOL_REF
, SImode
, "$$remU"));
3321 import_milli (remI
);
3322 return output_millicode_call (insn
,
3323 gen_rtx (SYMBOL_REF
, SImode
, "$$remI"));
3328 output_arg_descriptor (call_insn
)
3332 enum machine_mode arg_mode
;
3334 int i
, output_flag
= 0;
3337 for (i
= 0; i
< 4; i
++)
3340 /* Specify explicitly that no argument relocations should take place
3341 if using the portable runtime calling conventions. */
3342 if (TARGET_PORTABLE_RUNTIME
)
3344 fprintf (asm_out_file
,
3345 "\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n");
3349 if (GET_CODE (call_insn
) != CALL_INSN
)
3351 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); link
; link
= XEXP (link
, 1))
3353 rtx use
= XEXP (link
, 0);
3355 if (! (GET_CODE (use
) == USE
3356 && GET_CODE (XEXP (use
, 0)) == REG
3357 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
3360 arg_mode
= GET_MODE (XEXP (use
, 0));
3361 regno
= REGNO (XEXP (use
, 0));
3362 if (regno
>= 23 && regno
<= 26)
3364 arg_regs
[26 - regno
] = "GR";
3365 if (arg_mode
== DImode
)
3366 arg_regs
[25 - regno
] = "GR";
3368 else if (regno
>= 32 && regno
<= 39)
3370 if (arg_mode
== SFmode
)
3371 arg_regs
[(regno
- 32) / 2] = "FR";
3374 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
3375 arg_regs
[(regno
- 34) / 2] = "FR";
3376 arg_regs
[(regno
- 34) / 2 + 1] = "FU";
3378 arg_regs
[(regno
- 34) / 2] = "FU";
3379 arg_regs
[(regno
- 34) / 2 + 1] = "FR";
3384 fputs ("\t.CALL ", asm_out_file
);
3385 for (i
= 0; i
< 4; i
++)
3390 fputc (',', asm_out_file
);
3391 fprintf (asm_out_file
, "ARGW%d=%s", i
, arg_regs
[i
]);
3394 fputc ('\n', asm_out_file
);
3397 /* Memory loads/stores to/from the shift need to go through
3398 the general registers. */
3401 secondary_reload_class (class, mode
, in
)
3402 enum reg_class
class;
3403 enum machine_mode mode
;
3406 int regno
= true_regnum (in
);
3408 /* Trying to load a constant into a FP register during PIC code
3409 generation will require %r1 as a scratch register. */
3411 && GET_MODE_CLASS (mode
) == MODE_INT
3412 && FP_REG_CLASS_P (class)
3413 && (GET_CODE (in
) == CONST_INT
|| GET_CODE (in
) == CONST_DOUBLE
))
3416 if (((regno
>= FIRST_PSEUDO_REGISTER
|| regno
== -1)
3417 && GET_MODE_CLASS (mode
) == MODE_INT
3418 && FP_REG_CLASS_P (class))
3419 || (class == SHIFT_REGS
&& (regno
<= 0 || regno
>= 32)))
3420 return GENERAL_REGS
;
3422 if (GET_CODE (in
) == HIGH
)
3426 && symbolic_operand (in
, VOIDmode
)
3427 && read_only_operand (in
))
3430 if (class != R1_REGS
&& symbolic_operand (in
, VOIDmode
))
3433 if (GET_CODE (in
) == SUBREG
)
3434 in
= SUBREG_REG (in
);
3440 function_arg_padding (mode
, type
)
3441 enum machine_mode mode
;
3446 if (mode
== BLKmode
)
3448 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
3449 size
= int_size_in_bytes (type
) * BITS_PER_UNIT
;
3451 return upward
; /* Don't know if this is right, but */
3452 /* same as old definition. */
3455 size
= GET_MODE_BITSIZE (mode
);
3456 if (size
< PARM_BOUNDARY
)
3458 else if (size
% PARM_BOUNDARY
)
3465 /* Do what is necessary for `va_start'. The argument is ignored;
3466 We look at the current function to determine if stdargs or varargs
3467 is used and fill in an initial va_list. A pointer to this constructor
3471 hppa_builtin_saveregs (arglist
)
3475 tree fntype
= TREE_TYPE (current_function_decl
);
3476 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
3477 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
3478 != void_type_node
)))
3479 ? UNITS_PER_WORD
: 0);
3482 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
3484 offset
= current_function_arg_offset_rtx
;
3486 /* Store general registers on the stack. */
3487 move_block_from_reg (23,
3488 gen_rtx (MEM
, BLKmode
,
3490 (current_function_internal_arg_pointer
, -16)),
3491 4, 4 * UNITS_PER_WORD
);
3492 return copy_to_reg (expand_binop (Pmode
, add_optab
,
3493 current_function_internal_arg_pointer
,
3494 offset
, 0, 0, OPTAB_LIB_WIDEN
));
3497 /* This routine handles all the normal conditional branch sequences we
3498 might need to generate. It handles compare immediate vs compare
3499 register, nullification of delay slots, varying length branches,
3500 negated branches, and all combinations of the above. It returns the
3501 output appropriate to emit the branch corresponding to all given
3505 output_cbranch (operands
, nullify
, length
, negated
, insn
)
3507 int nullify
, length
, negated
;
3510 static char buf
[100];
3513 /* A conditional branch to the following instruction (eg the delay slot) is
3514 asking for a disaster. This can happen when not optimizing.
3516 In such cases it is safe to emit nothing. */
3518 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
3521 /* If this is a long branch with its delay slot unfilled, set `nullify'
3522 as it can nullify the delay slot and save a nop. */
3523 if (length
== 8 && dbr_sequence_length () == 0)
3526 /* If this is a short forward conditional branch which did not get
3527 its delay slot filled, the delay slot can still be nullified. */
3528 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3529 nullify
= forward_branch_p (insn
);
3531 /* A forward branch over a single nullified insn can be done with a
3532 comclr instruction. This avoids a single cycle penalty due to
3533 mis-predicted branch if we fall through (branch not taken). */
3535 && next_real_insn (insn
) != 0
3536 && get_attr_length (next_real_insn (insn
)) == 4
3537 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
3543 /* All short conditional branches except backwards with an unfilled
3547 strcpy (buf
, "com%I2clr,");
3549 strcpy (buf
, "com%I2b,");
3551 strcat (buf
, "%B3");
3553 strcat (buf
, "%S3");
3555 strcat (buf
, " %2,%1,0");
3557 strcat (buf
, ",n %2,%1,%0");
3559 strcat (buf
, " %2,%1,%0");
3562 /* All long conditionals. Note an short backward branch with an
3563 unfilled delay slot is treated just like a long backward branch
3564 with an unfilled delay slot. */
3566 /* Handle weird backwards branch with a filled delay slot
3567 with is nullified. */
3568 if (dbr_sequence_length () != 0
3569 && ! forward_branch_p (insn
)
3572 strcpy (buf
, "com%I2b,");
3574 strcat (buf
, "%S3");
3576 strcat (buf
, "%B3");
3577 strcat (buf
, ",n %2,%1,.+12\n\tbl %0,0");
3579 /* Handle short backwards branch with an unfilled delay slot.
3580 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
3581 taken and untaken branches. */
3582 else if (dbr_sequence_length () == 0
3583 && ! forward_branch_p (insn
)
3585 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
3586 - insn_addresses
[INSN_UID (insn
)] - 8))
3588 strcpy (buf
, "com%I2b,");
3590 strcat (buf
, "%B3 %2,%1,%0%#");
3592 strcat (buf
, "%S3 %2,%1,%0%#");
3596 strcpy (buf
, "com%I2clr,");
3598 strcat (buf
, "%S3");
3600 strcat (buf
, "%B3");
3602 strcat (buf
, " %2,%1,0\n\tbl,n %0,0");
3604 strcat (buf
, " %2,%1,0\n\tbl %0,0");
3614 /* This routine handles all the branch-on-bit conditional branch sequences we
3615 might need to generate. It handles nullification of delay slots,
3616 varying length branches, negated branches and all combinations of the
3617 above. it returns the appropriate output template to emit the branch. */
3620 output_bb (operands
, nullify
, length
, negated
, insn
, which
)
3622 int nullify
, length
, negated
;
3626 static char buf
[100];
3629 /* A conditional branch to the following instruction (eg the delay slot) is
3630 asking for a disaster. I do not think this can happen as this pattern
3631 is only used when optimizing; jump optimization should eliminate the
3632 jump. But be prepared just in case. */
3634 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
3637 /* If this is a long branch with its delay slot unfilled, set `nullify'
3638 as it can nullify the delay slot and save a nop. */
3639 if (length
== 8 && dbr_sequence_length () == 0)
3642 /* If this is a short forward conditional branch which did not get
3643 its delay slot filled, the delay slot can still be nullified. */
3644 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3645 nullify
= forward_branch_p (insn
);
3647 /* A forward branch over a single nullified insn can be done with a
3648 extrs instruction. This avoids a single cycle penalty due to
3649 mis-predicted branch if we fall through (branch not taken). */
3652 && next_real_insn (insn
) != 0
3653 && get_attr_length (next_real_insn (insn
)) == 4
3654 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
3661 /* All short conditional branches except backwards with an unfilled
3665 strcpy (buf
, "extrs,");
3667 strcpy (buf
, "bb,");
3668 if ((which
== 0 && negated
)
3669 || (which
== 1 && ! negated
))
3674 strcat (buf
, " %0,%1,1,0");
3675 else if (nullify
&& negated
)
3676 strcat (buf
, ",n %0,%1,%3");
3677 else if (nullify
&& ! negated
)
3678 strcat (buf
, ",n %0,%1,%2");
3679 else if (! nullify
&& negated
)
3680 strcat (buf
, "%0,%1,%3");
3681 else if (! nullify
&& ! negated
)
3682 strcat (buf
, " %0,%1,%2");
3685 /* All long conditionals. Note an short backward branch with an
3686 unfilled delay slot is treated just like a long backward branch
3687 with an unfilled delay slot. */
3689 /* Handle weird backwards branch with a filled delay slot
3690 with is nullified. */
3691 if (dbr_sequence_length () != 0
3692 && ! forward_branch_p (insn
)
3695 strcpy (buf
, "bb,");
3696 if ((which
== 0 && negated
)
3697 || (which
== 1 && ! negated
))
3702 strcat (buf
, ",n %0,%1,.+12\n\tbl %3,0");
3704 strcat (buf
, ",n %0,%1,.+12\n\tbl %2,0");
3706 /* Handle short backwards branch with an unfilled delay slot.
3707 Using a bb;nop rather than extrs;bl saves 1 cycle for both
3708 taken and untaken branches. */
3709 else if (dbr_sequence_length () == 0
3710 && ! forward_branch_p (insn
)
3712 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
3713 - insn_addresses
[INSN_UID (insn
)] - 8))
3715 strcpy (buf
, "bb,");
3716 if ((which
== 0 && negated
)
3717 || (which
== 1 && ! negated
))
3722 strcat (buf
, " %0,%1,%3%#");
3724 strcat (buf
, " %0,%1,%2%#");
3728 strcpy (buf
, "extrs,");
3729 if ((which
== 0 && negated
)
3730 || (which
== 1 && ! negated
))
3734 if (nullify
&& negated
)
3735 strcat (buf
, " %0,%1,1,0\n\tbl,n %3,0");
3736 else if (nullify
&& ! negated
)
3737 strcat (buf
, " %0,%1,1,0\n\tbl,n %2,0");
3739 strcat (buf
, " %0,%1,1,0\n\tbl %3,0");
3741 strcat (buf
, " %0,%1,1,0\n\tbl %2,0");
3751 /* This routine handles all the branch-on-variable-bit conditional branch
3752 sequences we might need to generate. It handles nullification of delay
3753 slots, varying length branches, negated branches and all combinations
3754 of the above. it returns the appropriate output template to emit the
3758 output_bvb (operands
, nullify
, length
, negated
, insn
, which
)
3760 int nullify
, length
, negated
;
3764 static char buf
[100];
3767 /* A conditional branch to the following instruction (eg the delay slot) is
3768 asking for a disaster. I do not think this can happen as this pattern
3769 is only used when optimizing; jump optimization should eliminate the
3770 jump. But be prepared just in case. */
3772 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
3775 /* If this is a long branch with its delay slot unfilled, set `nullify'
3776 as it can nullify the delay slot and save a nop. */
3777 if (length
== 8 && dbr_sequence_length () == 0)
3780 /* If this is a short forward conditional branch which did not get
3781 its delay slot filled, the delay slot can still be nullified. */
3782 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3783 nullify
= forward_branch_p (insn
);
3785 /* A forward branch over a single nullified insn can be done with a
3786 extrs instruction. This avoids a single cycle penalty due to
3787 mis-predicted branch if we fall through (branch not taken). */
3790 && next_real_insn (insn
) != 0
3791 && get_attr_length (next_real_insn (insn
)) == 4
3792 && JUMP_LABEL (insn
) == next_nonnote_insn (next_real_insn (insn
))
3799 /* All short conditional branches except backwards with an unfilled
3803 strcpy (buf
, "vextrs,");
3805 strcpy (buf
, "bvb,");
3806 if ((which
== 0 && negated
)
3807 || (which
== 1 && ! negated
))
3812 strcat (buf
, " %0,1,0");
3813 else if (nullify
&& negated
)
3814 strcat (buf
, ",n %0,%3");
3815 else if (nullify
&& ! negated
)
3816 strcat (buf
, ",n %0,%2");
3817 else if (! nullify
&& negated
)
3818 strcat (buf
, "%0,%3");
3819 else if (! nullify
&& ! negated
)
3820 strcat (buf
, " %0,%2");
3823 /* All long conditionals. Note an short backward branch with an
3824 unfilled delay slot is treated just like a long backward branch
3825 with an unfilled delay slot. */
3827 /* Handle weird backwards branch with a filled delay slot
3828 with is nullified. */
3829 if (dbr_sequence_length () != 0
3830 && ! forward_branch_p (insn
)
3833 strcpy (buf
, "bvb,");
3834 if ((which
== 0 && negated
)
3835 || (which
== 1 && ! negated
))
3840 strcat (buf
, ",n %0,.+12\n\tbl %3,0");
3842 strcat (buf
, ",n %0,.+12\n\tbl %2,0");
3844 /* Handle short backwards branch with an unfilled delay slot.
3845 Using a bb;nop rather than extrs;bl saves 1 cycle for both
3846 taken and untaken branches. */
3847 else if (dbr_sequence_length () == 0
3848 && ! forward_branch_p (insn
)
3850 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
3851 - insn_addresses
[INSN_UID (insn
)] - 8))
3853 strcpy (buf
, "bvb,");
3854 if ((which
== 0 && negated
)
3855 || (which
== 1 && ! negated
))
3860 strcat (buf
, " %0,%3%#");
3862 strcat (buf
, " %0,%2%#");
3866 strcpy (buf
, "vextrs,");
3867 if ((which
== 0 && negated
)
3868 || (which
== 1 && ! negated
))
3872 if (nullify
&& negated
)
3873 strcat (buf
, " %0,1,0\n\tbl,n %3,0");
3874 else if (nullify
&& ! negated
)
3875 strcat (buf
, " %0,1,0\n\tbl,n %2,0");
3877 strcat (buf
, " %0,1,0\n\tbl %3,0");
3879 strcat (buf
, " %0,1,0\n\tbl %2,0");
3889 /* Return the output template for emitting a dbra type insn.
3891 Note it may perform some output operations on its own before
3892 returning the final output string. */
3894 output_dbra (operands
, insn
, which_alternative
)
3897 int which_alternative
;
3900 /* A conditional branch to the following instruction (eg the delay slot) is
3901 asking for a disaster. Be prepared! */
3903 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
3905 if (which_alternative
== 0)
3906 return "ldo %1(%0),%0";
3907 else if (which_alternative
== 1)
3909 output_asm_insn ("fstws %0,-16(0,%%r30)",operands
);
3910 output_asm_insn ("ldw -16(0,%%r30),%4",operands
);
3911 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
3912 return "fldws -16(0,%%r30),%0";
3916 output_asm_insn ("ldw %0,%4", operands
);
3917 return "ldo %1(%4),%4\n\tstw %4,%0";
3921 if (which_alternative
== 0)
3923 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
3924 int length
= get_attr_length (insn
);
3926 /* If this is a long branch with its delay slot unfilled, set `nullify'
3927 as it can nullify the delay slot and save a nop. */
3928 if (length
== 8 && dbr_sequence_length () == 0)
3931 /* If this is a short forward conditional branch which did not get
3932 its delay slot filled, the delay slot can still be nullified. */
3933 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
3934 nullify
= forward_branch_p (insn
);
3936 /* Handle short versions first. */
3937 if (length
== 4 && nullify
)
3938 return "addib,%C2,n %1,%0,%3";
3939 else if (length
== 4 && ! nullify
)
3940 return "addib,%C2 %1,%0,%3";
3941 else if (length
== 8)
3943 /* Handle weird backwards branch with a fulled delay slot
3944 which is nullified. */
3945 if (dbr_sequence_length () != 0
3946 && ! forward_branch_p (insn
)
3948 return "addib,%N2,n %1,%0,.+12\n\tbl %3,0";
3949 /* Handle short backwards branch with an unfilled delay slot.
3950 Using a addb;nop rather than addi;bl saves 1 cycle for both
3951 taken and untaken branches. */
3952 else if (dbr_sequence_length () == 0
3953 && ! forward_branch_p (insn
)
3955 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
3956 - insn_addresses
[INSN_UID (insn
)] - 8))
3957 return "addib,%C2 %1,%0,%3%#";
3959 /* Handle normal cases. */
3961 return "addi,%N2 %1,%0,%0\n\tbl,n %3,0";
3963 return "addi,%N2 %1,%0,%0\n\tbl %3,0";
3968 /* Deal with gross reload from FP register case. */
3969 else if (which_alternative
== 1)
3971 /* Move loop counter from FP register to MEM then into a GR,
3972 increment the GR, store the GR into MEM, and finally reload
3973 the FP register from MEM from within the branch's delay slot. */
3974 output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands
);
3975 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands
);
3976 if (get_attr_length (insn
) == 24)
3977 return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
3979 return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
3981 /* Deal with gross reload from memory case. */
3984 /* Reload loop counter from memory, the store back to memory
3985 happens in the branch's delay slot. */
3986 output_asm_insn ("ldw %0,%4", operands
);
3987 if (get_attr_length (insn
) == 12)
3988 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
3990 return "addi,%N2 %1,%4,%4\n\tbl %3,0\n\tstw %4,%0";
3994 /* Return the output template for emitting a dbra type insn.
3996 Note it may perform some output operations on its own before
3997 returning the final output string. */
3999 output_movb (operands
, insn
, which_alternative
, reverse_comparison
)
4002 int which_alternative
;
4003 int reverse_comparison
;
4006 /* A conditional branch to the following instruction (eg the delay slot) is
4007 asking for a disaster. Be prepared! */
4009 if (next_active_insn (JUMP_LABEL (insn
)) == next_active_insn (insn
))
4011 if (which_alternative
== 0)
4012 return "copy %1,%0";
4013 else if (which_alternative
== 1)
4015 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
4016 return "fldws -16(0,%%r30),%0";
4022 /* Support the second variant. */
4023 if (reverse_comparison
)
4024 PUT_CODE (operands
[2], reverse_condition (GET_CODE (operands
[2])));
4026 if (which_alternative
== 0)
4028 int nullify
= INSN_ANNULLED_BRANCH_P (insn
);
4029 int length
= get_attr_length (insn
);
4031 /* If this is a long branch with its delay slot unfilled, set `nullify'
4032 as it can nullify the delay slot and save a nop. */
4033 if (length
== 8 && dbr_sequence_length () == 0)
4036 /* If this is a short forward conditional branch which did not get
4037 its delay slot filled, the delay slot can still be nullified. */
4038 if (! nullify
&& length
== 4 && dbr_sequence_length () == 0)
4039 nullify
= forward_branch_p (insn
);
4041 /* Handle short versions first. */
4042 if (length
== 4 && nullify
)
4043 return "movb,%C2,n %1,%0,%3";
4044 else if (length
== 4 && ! nullify
)
4045 return "movb,%C2 %1,%0,%3";
4046 else if (length
== 8)
4048 /* Handle weird backwards branch with a filled delay slot
4049 which is nullified. */
4050 if (dbr_sequence_length () != 0
4051 && ! forward_branch_p (insn
)
4053 return "movb,%N2,n %1,%0,.+12\n\tbl %3,0";
4055 /* Handle short backwards branch with an unfilled delay slot.
4056 Using a movb;nop rather than or;bl saves 1 cycle for both
4057 taken and untaken branches. */
4058 else if (dbr_sequence_length () == 0
4059 && ! forward_branch_p (insn
)
4061 && VAL_14_BITS_P (insn_addresses
[INSN_UID (JUMP_LABEL (insn
))]
4062 - insn_addresses
[INSN_UID (insn
)] - 8))
4063 return "movb,%C2 %1,%0,%3%#";
4064 /* Handle normal cases. */
4066 return "or,%N2 %1,%%r0,%0\n\tbl,n %3,0";
4068 return "or,%N2 %1,%%r0,%0\n\tbl %3,0";
4073 /* Deal with gross reload from FP register case. */
4074 else if (which_alternative
== 1)
4076 /* Move loop counter from FP register to MEM then into a GR,
4077 increment the GR, store the GR into MEM, and finally reload
4078 the FP register from MEM from within the branch's delay slot. */
4079 output_asm_insn ("stw %1,-16(0,%%r30)",operands
);
4080 if (get_attr_length (insn
) == 12)
4081 return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
4083 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
4085 /* Deal with gross reload from memory case. */
4088 /* Reload loop counter from memory, the store back to memory
4089 happens in the branch's delay slot. */
4090 if (get_attr_length (insn
) == 8)
4091 return "comb,%S2 0,%1,%3\n\tstw %1,%0";
4093 return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tstw %1,%0";
4098 /* INSN is a millicode call. It may have an unconditional jump in its delay
4101 CALL_DEST is the routine we are calling. */
4104 output_millicode_call (insn
, call_dest
)
4112 /* Handle common case -- empty delay slot or no jump in the delay slot,
4113 and we're sure that the branch will reach the beginning of the $CODE$
4115 if ((dbr_sequence_length () == 0
4116 /* CYGNUS LOCAL mentor6480hack/law */
4117 && (get_attr_length (insn
) == 8 || get_attr_length (insn
) == 28))
4118 /* END CYGNUS LOCAL */
4119 || (dbr_sequence_length () != 0
4120 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
4121 && get_attr_length (insn
) == 4))
4123 xoperands
[0] = call_dest
;
4124 output_asm_insn ("bl %0,%%r31%#", xoperands
);
4128 /* This call may not reach the beginning of the $CODE$ subspace. */
4129 if (get_attr_length (insn
) > 4)
4131 int delay_insn_deleted
= 0;
4135 /* We need to emit an inline long-call branch. */
4136 if (dbr_sequence_length () != 0
4137 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
4139 /* A non-jump insn in the delay slot. By definition we can
4140 emit this insn before the call. */
4141 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
4143 /* Now delete the delay insn. */
4144 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4145 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4146 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4147 delay_insn_deleted
= 1;
4150 /* If we're allowed to use be/ble instructions, then this is the
4151 best sequence to use for a long millicode call. */
4152 if (TARGET_NO_SPACE_REGS
4153 || ! (flag_pic
|| TARGET_PORTABLE_RUNTIME
))
4155 xoperands
[0] = call_dest
;
4156 output_asm_insn ("ldil L%%%0,%%r31", xoperands
);
4157 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands
);
4158 output_asm_insn ("nop", xoperands
);
4160 /* Pure portable runtime doesn't allow be/ble; we also don't have
4161 PIC support int he assembler/linker, so this sequence is needed. */
4162 else if (TARGET_PORTABLE_RUNTIME
)
4164 xoperands
[0] = call_dest
;
4165 /* Get the address of our target into %r29. */
4166 output_asm_insn ("ldil L%%%0,%%r29", xoperands
);
4167 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands
);
4169 /* Get our return address into %r31. */
4170 output_asm_insn ("blr 0,%%r31", xoperands
);
4172 /* Jump to our target address in %r29. */
4173 output_asm_insn ("bv,n 0(%%r29)", xoperands
);
4175 /* Empty delay slot. Note this insn gets fetched twice and
4176 executed once. To be safe we use a nop. */
4177 output_asm_insn ("nop", xoperands
);
4180 /* PIC long millicode call sequence. */
4183 xoperands
[0] = call_dest
;
4184 xoperands
[1] = gen_label_rtx ();
4185 /* Get our address + 8 into %r1. */
4186 output_asm_insn ("bl .+8,%%r1", xoperands
);
4188 /* Add %r1 to the offset of our target from the next insn. */
4189 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands
);
4190 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4191 CODE_LABEL_NUMBER (xoperands
[1]));
4192 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands
);
4194 /* Get the return address into %r31. */
4195 output_asm_insn ("blr 0,%%r31", xoperands
);
4197 /* Branch to our target which is in %r1. */
4198 output_asm_insn ("bv,n 0(%%r1)", xoperands
);
4200 /* Empty delay slot. Note this insn gets fetched twice and
4201 executed once. To be safe we use a nop. */
4202 output_asm_insn ("nop", xoperands
);
4205 /* If we had a jump in the call's delay slot, output it now. */
4206 if (dbr_sequence_length () != 0
4207 && !delay_insn_deleted
)
4209 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
4210 output_asm_insn ("b,n %0", xoperands
);
4212 /* Now delete the delay insn. */
4213 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4214 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4215 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4220 /* This call has an unconditional jump in its delay slot and the
4221 call is known to reach its target or the beginning of the current
4224 /* Use the containing sequence insn's address. */
4225 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
4227 distance
= insn_addresses
[INSN_UID (JUMP_LABEL (NEXT_INSN (insn
)))]
4228 - insn_addresses
[INSN_UID (seq_insn
)] - 8;
4230 /* If the branch was too far away, emit a normal call followed
4231 by a nop, followed by the unconditional branch.
4233 If the branch is close, then adjust %r2 from within the
4234 call's delay slot. */
4236 xoperands
[0] = call_dest
;
4237 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
4238 if (! VAL_14_BITS_P (distance
))
4239 output_asm_insn ("bl %0,%%r31\n\tnop\n\tbl,n %1,%%r0", xoperands
);
4242 xoperands
[3] = gen_label_rtx ();
4243 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands
);
4244 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4245 CODE_LABEL_NUMBER (xoperands
[3]));
4248 /* Delete the jump. */
4249 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4250 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4251 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4255 /* INSN is either a function call. It may have an unconditional jump
4258 CALL_DEST is the routine we are calling. */
4261 output_call (insn
, call_dest
)
4269 /* Handle common case -- empty delay slot or no jump in the delay slot,
4270 and we're sure that the branch will reach the beginning of the $CODE$
4272 if ((dbr_sequence_length () == 0
4273 && get_attr_length (insn
) == 8)
4274 || (dbr_sequence_length () != 0
4275 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
4276 && get_attr_length (insn
) == 4))
4278 xoperands
[0] = call_dest
;
4279 output_asm_insn ("bl %0,%%r2%#", xoperands
);
4283 /* This call may not reach the beginning of the $CODE$ subspace. */
4284 if (get_attr_length (insn
) > 8)
4286 int delay_insn_deleted
= 0;
4290 /* We need to emit an inline long-call branch. Furthermore,
4291 because we're changing a named function call into an indirect
4292 function call well after the parameters have been set up, we
4293 need to make sure any FP args appear in both the integer
4294 and FP registers. Also, we need move any delay slot insn
4295 out of the delay slot. And finally, we can't rely on the linker
4296 being able to fix the call to $$dyncall! -- Yuk!. */
4297 if (dbr_sequence_length () != 0
4298 && GET_CODE (NEXT_INSN (insn
)) != JUMP_INSN
)
4300 /* A non-jump insn in the delay slot. By definition we can
4301 emit this insn before the call (and in fact before argument
4303 final_scan_insn (NEXT_INSN (insn
), asm_out_file
, optimize
, 0, 0);
4305 /* Now delete the delay insn. */
4306 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4307 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4308 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4309 delay_insn_deleted
= 1;
4312 /* Now copy any FP arguments into integer registers. */
4313 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
; link
= XEXP (link
, 1))
4315 int arg_mode
, regno
;
4316 rtx use
= XEXP (link
, 0);
4317 if (! (GET_CODE (use
) == USE
4318 && GET_CODE (XEXP (use
, 0)) == REG
4319 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use
, 0)))))
4322 arg_mode
= GET_MODE (XEXP (use
, 0));
4323 regno
= REGNO (XEXP (use
, 0));
4324 /* Is it a floating point register? */
4325 if (regno
>= 32 && regno
<= 39)
4327 /* Copy from the FP register into an integer register
4329 if (arg_mode
== SFmode
)
4331 xoperands
[0] = XEXP (use
, 0);
4332 xoperands
[1] = gen_rtx (REG
, SImode
, 26 - (regno
- 32) / 2);
4333 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands
);
4334 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
4338 xoperands
[0] = XEXP (use
, 0);
4339 xoperands
[1] = gen_rtx (REG
, DImode
, 25 - (regno
- 34) / 2);
4340 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands
);
4341 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands
);
4342 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands
);
4348 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
4349 we don't have any direct calls in that case. */
4352 /* We have to load the address of the function using a procedure
4353 label (plabel). The LP and RP relocs don't work reliably for PIC,
4354 so we make a plain 32 bit plabel in the data segment instead. We
4355 have to defer outputting it of course... Not pretty. */
4357 xoperands
[0] = gen_label_rtx ();
4358 xoperands
[1] = gen_label_rtx ();
4359 output_asm_insn ("addil LT%%%0,%%r19", xoperands
);
4360 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands
);
4361 output_asm_insn ("ldw 0(0,%%r22),%%r22", xoperands
);
4363 if (deferred_plabels
== 0)
4364 deferred_plabels
= (struct defer_plab
*)
4365 xmalloc (1 * sizeof (struct defer_plab
));
4367 deferred_plabels
= (struct defer_plab
*)
4368 xrealloc (deferred_plabels
,
4369 (n_deferred_plabels
+ 1) * sizeof (struct defer_plab
));
4370 deferred_plabels
[n_deferred_plabels
].internal_label
= xoperands
[0];
4371 deferred_plabels
[n_deferred_plabels
].symbol
= call_dest
;
4372 n_deferred_plabels
++;
4374 /* Get our address + 8 into %r1. */
4375 output_asm_insn ("bl .+8,%%r1", xoperands
);
4377 /* Add %r1 to the offset of dyncall from the next insn. */
4378 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands
);
4379 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4380 CODE_LABEL_NUMBER (xoperands
[1]));
4381 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands
);
4383 /* Get the return address into %r31. */
4384 output_asm_insn ("blr 0,%%r31", xoperands
);
4386 /* Branch to our target which is in %r1. */
4387 output_asm_insn ("bv 0(%%r1)", xoperands
);
4389 /* Copy the return address into %r2 also. */
4390 output_asm_insn ("copy %%r31,%%r2", xoperands
);
4394 /* No PIC stuff to worry about. We can use ldil;ble. */
4395 xoperands
[0] = call_dest
;
4397 /* Get the address of our target into %r22. */
4398 output_asm_insn ("ldil LP%%%0,%%r22", xoperands
);
4399 output_asm_insn ("ldo RP%%%0(%%r22),%%r22", xoperands
);
4401 /* Get the high part of the address of $dyncall into %r2, then
4402 add in the low part in the branch instruction. */
4403 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands
);
4404 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands
);
4406 /* Copy the return pointer into both %r31 and %r2. */
4407 output_asm_insn ("copy %%r31,%%r2", xoperands
);
4410 /* If we had a jump in the call's delay slot, output it now. */
4411 if (dbr_sequence_length () != 0
4412 && !delay_insn_deleted
)
4414 xoperands
[0] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
4415 output_asm_insn ("b,n %0", xoperands
);
4417 /* Now delete the delay insn. */
4418 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4419 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4420 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4425 /* This call has an unconditional jump in its delay slot and the
4426 call is known to reach its target or the beginning of the current
4429 /* Use the containing sequence insn's address. */
4430 seq_insn
= NEXT_INSN (PREV_INSN (XVECEXP (final_sequence
, 0, 0)));
4432 distance
= insn_addresses
[INSN_UID (JUMP_LABEL (NEXT_INSN (insn
)))]
4433 - insn_addresses
[INSN_UID (seq_insn
)] - 8;
4435 /* If the branch was too far away, emit a normal call followed
4436 by a nop, followed by the unconditional branch.
4438 If the branch is close, then adjust %r2 from within the
4439 call's delay slot. */
4441 xoperands
[0] = call_dest
;
4442 xoperands
[1] = XEXP (PATTERN (NEXT_INSN (insn
)), 1);
4443 if (! VAL_14_BITS_P (distance
))
4444 output_asm_insn ("bl %0,%%r2\n\tnop\n\tbl,n %1,%%r0", xoperands
);
4447 xoperands
[3] = gen_label_rtx ();
4448 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands
);
4449 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4450 CODE_LABEL_NUMBER (xoperands
[3]));
4453 /* Delete the jump. */
4454 PUT_CODE (NEXT_INSN (insn
), NOTE
);
4455 NOTE_LINE_NUMBER (NEXT_INSN (insn
)) = NOTE_INSN_DELETED
;
4456 NOTE_SOURCE_FILE (NEXT_INSN (insn
)) = 0;
4460 extern struct obstack permanent_obstack
;
4461 extern struct obstack
*saveable_obstack
;
4463 /* In HPUX 8.0's shared library scheme, special relocations are needed
4464 for function labels if they might be passed to a function
4465 in a shared library (because shared libraries don't live in code
4466 space), and special magic is needed to construct their address.
4468 For reasons too disgusting to describe storage for the new name
4469 is allocated either on the saveable_obstack (released at function
4470 exit) or on the permanent_obstack for things that can never change
4471 (libcall names for example). */
4474 hppa_encode_label (sym
, permanent
)
4478 char *str
= XSTR (sym
, 0);
4479 int len
= strlen (str
);
4482 newstr
= obstack_alloc ((permanent
? &permanent_obstack
: saveable_obstack
),
4487 strcpy (newstr
+ 1, str
);
4489 XSTR (sym
,0) = newstr
;
4493 function_label_operand (op
, mode
)
4495 enum machine_mode mode
;
4497 return GET_CODE (op
) == SYMBOL_REF
&& FUNCTION_NAME_P (XSTR (op
, 0));
4500 /* Returns 1 if OP is a function label involved in a simple addition
4501 with a constant. Used to keep certain patterns from matching
4502 during instruction combination. */
4504 is_function_label_plus_const (op
)
4507 /* Strip off any CONST. */
4508 if (GET_CODE (op
) == CONST
)
4511 return (GET_CODE (op
) == PLUS
4512 && function_label_operand (XEXP (op
, 0), Pmode
)
4513 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
4516 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
4517 use in fmpyadd instructions. */
4519 fmpyaddoperands (operands
)
4522 enum machine_mode mode
= GET_MODE (operands
[0]);
4524 /* All modes must be the same. */
4525 if (! (mode
== GET_MODE (operands
[1])
4526 && mode
== GET_MODE (operands
[2])
4527 && mode
== GET_MODE (operands
[3])
4528 && mode
== GET_MODE (operands
[4])
4529 && mode
== GET_MODE (operands
[5])))
4532 /* Both DFmode and SFmode should work. But using SFmode makes the
4533 assembler complain. Just turn it off for now. */
4537 /* Only 2 real operands to the addition. One of the input operands must
4538 be the same as the output operand. */
4539 if (! rtx_equal_p (operands
[3], operands
[4])
4540 && ! rtx_equal_p (operands
[3], operands
[5]))
4543 /* Inout operand of add can not conflict with any operands from multiply. */
4544 if (rtx_equal_p (operands
[3], operands
[0])
4545 || rtx_equal_p (operands
[3], operands
[1])
4546 || rtx_equal_p (operands
[3], operands
[2]))
4549 /* multiply can not feed into addition operands. */
4550 if (rtx_equal_p (operands
[4], operands
[0])
4551 || rtx_equal_p (operands
[5], operands
[0]))
4554 /* Passed. Operands are suitable for fmpyadd. */
4558 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
4559 use in fmpysub instructions. */
4561 fmpysuboperands (operands
)
4564 enum machine_mode mode
= GET_MODE (operands
[0]);
4566 /* All modes must be the same. */
4567 if (! (mode
== GET_MODE (operands
[1])
4568 && mode
== GET_MODE (operands
[2])
4569 && mode
== GET_MODE (operands
[3])
4570 && mode
== GET_MODE (operands
[4])
4571 && mode
== GET_MODE (operands
[5])))
4574 /* Both DFmode and SFmode should work. But using SFmode makes the
4575 assembler complain. Just turn it off for now. */
4579 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
4580 operation, so operands[4] must be the same as operand[3]. */
4581 if (! rtx_equal_p (operands
[3], operands
[4]))
4584 /* multiply can not feed into subtraction. */
4585 if (rtx_equal_p (operands
[5], operands
[0]))
4588 /* Inout operand of sub can not conflict with any operands from multiply. */
4589 if (rtx_equal_p (operands
[3], operands
[0])
4590 || rtx_equal_p (operands
[3], operands
[1])
4591 || rtx_equal_p (operands
[3], operands
[2]))
4594 /* Passed. Operands are suitable for fmpysub. */
4599 plus_xor_ior_operator (op
, mode
)
4601 enum machine_mode mode
;
4603 return (GET_CODE (op
) == PLUS
|| GET_CODE (op
) == XOR
4604 || GET_CODE (op
) == IOR
);
4607 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
4608 constants for shadd instructions. */
4610 shadd_constant_p (val
)
4613 if (val
== 2 || val
== 4 || val
== 8)
4619 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
4620 the valid constant for shadd instructions. */
4622 shadd_operand (op
, mode
)
4624 enum machine_mode mode
;
4626 return (GET_CODE (op
) == CONST_INT
&& shadd_constant_p (INTVAL (op
)));
4629 /* Return 1 if OP is valid as a base register in a reg + reg address. */
4632 basereg_operand (op
, mode
)
4634 enum machine_mode mode
;
4636 /* Once reload has started everything is considered valid. Reload should
4637 only create indexed addresses using the stack/frame pointer, and any
4638 others were checked for validity when created by the combine pass.
4640 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
4641 we don't have to worry about the braindamaged implicit space register
4642 selection using the basereg only (rather than effective address)
4643 screwing us over. */
4644 if (TARGET_NO_SPACE_REGS
|| reload_in_progress
|| reload_completed
)
4645 return (GET_CODE (op
) == REG
|| GET_CODE (op
) == CONST_INT
);
4647 /* Stack and frame pointers are always OK for indexing. */
4648 if (op
== stack_pointer_rtx
|| op
== frame_pointer_rtx
)
4651 /* The only other valid OPs are pseudo registers with
4652 REGNO_POINTER_FLAG set. */
4653 if (GET_CODE (op
) != REG
4654 || REGNO (op
) < FIRST_PSEUDO_REGISTER
4655 || ! register_operand (op
, mode
))
4658 return REGNO_POINTER_FLAG (REGNO (op
));
4661 /* Return 1 if this operand is anything other than a hard register. */
4664 non_hard_reg_operand (op
, mode
)
4666 enum machine_mode mode
;
4668 return ! (GET_CODE (op
) == REG
&& REGNO (op
) < FIRST_PSEUDO_REGISTER
);
4671 /* Return 1 if INSN branches forward. Should be using insn_addresses
4672 to avoid walking through all the insns... */
4674 forward_branch_p (insn
)
4677 rtx label
= JUMP_LABEL (insn
);
4684 insn
= NEXT_INSN (insn
);
4687 return (insn
== label
);
4690 /* Return 1 if OP is an equality comparison, else return 0. */
4692 eq_neq_comparison_operator (op
, mode
)
4694 enum machine_mode mode
;
4696 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
4699 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
4701 movb_comparison_operator (op
, mode
)
4703 enum machine_mode mode
;
4705 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
4706 || GET_CODE (op
) == LT
|| GET_CODE (op
) == GE
);
4709 /* Return 1 if INSN is in the delay slot of a call instruction. */
4711 jump_in_call_delay (insn
)
4715 if (GET_CODE (insn
) != JUMP_INSN
)
4718 if (PREV_INSN (insn
)
4719 && PREV_INSN (PREV_INSN (insn
))
4720 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn
)))) == INSN
)
4722 rtx test_insn
= next_active_insn (PREV_INSN (PREV_INSN (insn
)));
4724 return (GET_CODE (PATTERN (test_insn
)) == SEQUENCE
4725 && XVECEXP (PATTERN (test_insn
), 0, 1) == insn
);
4733 /* We use this hook to perform a PA specific optimization which is difficult
4734 to do in earlier passes.
4736 We want the delay slots of branches within jump tables to be filled.
4737 None of the compiler passes at the moment even has the notion that a
4738 PA jump table doesn't contain addresses, but instead contains actual
4741 Because we actually jump into the table, the addresses of each entry
4742 must stay constant in relation to the beginning of the table (which
4743 itself must stay constant relative to the instruction to jump into
4744 it). I don't believe we can guarantee earlier passes of the compiler
4745 will adhere to those rules.
4747 So, late in the compilation process we find all the jump tables, and
4748 expand them into real code -- eg each entry in the jump table vector
4749 will get an appropriate label followed by a jump to the final target.
4751 Reorg and the final jump pass can then optimize these branches and
4752 fill their delay slots. We end up with smaller, more efficient code.
4754 The jump instructions within the table are special; we must be able
4755 to identify them during assembly output (if the jumps don't get filled
4756 we need to emit a nop rather than nullifying the delay slot)). We
4757 identify jumps in switch tables by marking the SET with DImode. */
4764 /* This is fairly cheap, so always run it if optimizing. */
4767 /* Find and explode all ADDR_VEC insns. */
4768 insns
= get_insns ();
4769 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
4771 rtx pattern
, tmp
, location
;
4772 unsigned int length
, i
;
4774 /* Find an ADDR_VEC insn to explode. */
4775 if (GET_CODE (insn
) != JUMP_INSN
4776 || GET_CODE (PATTERN (insn
)) != ADDR_VEC
)
4779 /* If needed, emit marker for the beginning of the branch table. */
4781 emit_insn_before (gen_begin_brtab (), insn
);
4783 pattern
= PATTERN (insn
);
4784 location
= PREV_INSN (insn
);
4785 length
= XVECLEN (pattern
, 0);
4787 for (i
= 0; i
< length
; i
++)
4789 /* Emit the jump itself. */
4790 tmp
= gen_switch_jump (XEXP (XVECEXP (pattern
, 0, i
), 0));
4791 tmp
= emit_jump_insn_after (tmp
, location
);
4792 JUMP_LABEL (tmp
) = XEXP (XVECEXP (pattern
, 0, i
), 0);
4793 LABEL_NUSES (JUMP_LABEL (tmp
))++;
4795 /* Emit a BARRIER after the jump. */
4796 location
= NEXT_INSN (location
);
4797 emit_barrier_after (location
);
4799 /* Put a CODE_LABEL before each so jump.c does not optimize
4801 location
= NEXT_INSN (location
);
4802 tmp
= gen_label_rtx ();
4803 LABEL_NUSES (tmp
) = 1;
4804 emit_label_after (tmp
, location
);
4805 location
= NEXT_INSN (location
);
4808 /* If needed, emit marker for the end of the branch table. */
4810 emit_insn_before (gen_end_brtab (), location
);
4811 /* Delete the ADDR_VEC. */
4815 else if (TARGET_GAS
)
4817 /* Sill need an end_brtab insn. */
4818 insns
= get_insns ();
4819 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
4821 /* Find an ADDR_VEC insn. */
4822 if (GET_CODE (insn
) != JUMP_INSN
4823 || GET_CODE (PATTERN (insn
)) != ADDR_VEC
)
4826 /* Now generate markers for the beginning and end of the
4828 emit_insn_before (gen_begin_brtab (), insn
);
4829 emit_insn_after (gen_end_brtab (), insn
);