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1 /* Subroutines used for calculate rtx costs of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2015 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 /* ------------------------------------------------------------------------ */
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "tree.h"
28 #include "stor-layout.h"
29 #include "varasm.h"
30 #include "calls.h"
31 #include "rtl.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h" /* Required by recog.h. */
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h" /* For DFA state_t. */
38 #include "insn-codes.h" /* For CODE_FOR_xxx. */
39 #include "reload.h" /* For push_reload(). */
40 #include "flags.h"
41 #include "hashtab.h"
42 #include "hash-set.h"
43 #include "vec.h"
44 #include "machmode.h"
45 #include "input.h"
46 #include "function.h"
47 #include "expr.h"
48 #include "recog.h"
49 #include "diagnostic-core.h"
50 #include "dominance.h"
51 #include "cfg.h"
52 #include "cfgrtl.h"
53 #include "cfganal.h"
54 #include "lcm.h"
55 #include "cfgbuild.h"
56 #include "cfgcleanup.h"
57 #include "predict.h"
58 #include "basic-block.h"
59 #include "df.h"
60 #include "tm_p.h"
61 #include "tm-constrs.h"
62 #include "optabs.h" /* For GEN_FCN. */
63 #include "target.h"
64 #include "target-def.h"
65 #include "langhooks.h" /* For add_builtin_function(). */
66 #include "ggc.h"
67 #include "builtins.h"
68
69 /* ------------------------------------------------------------------------ */
70
71 bool
72 nds32_rtx_costs_impl (rtx x,
73 int code,
74 int outer_code,
75 int opno ATTRIBUTE_UNUSED,
76 int *total,
77 bool speed)
78 {
79 /* According to 'speed', goto suitable cost model section. */
80 if (speed)
81 goto performance_cost;
82 else
83 goto size_cost;
84
85
86 performance_cost:
87 /* This is section for performance cost model. */
88
89 /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
90 We treat it as 4-cycle cost for each instruction
91 under performance consideration. */
92 switch (code)
93 {
94 case SET:
95 /* For 'SET' rtx, we need to return false
96 so that it can recursively calculate costs. */
97 return false;
98
99 case USE:
100 /* Used in combine.c as a marker. */
101 *total = 0;
102 break;
103
104 case MULT:
105 *total = COSTS_N_INSNS (1);
106 break;
107
108 case DIV:
109 case UDIV:
110 case MOD:
111 case UMOD:
112 *total = COSTS_N_INSNS (7);
113 break;
114
115 default:
116 *total = COSTS_N_INSNS (1);
117 break;
118 }
119
120 return true;
121
122
123 size_cost:
124 /* This is section for size cost model. */
125
126 /* In gcc/rtl.h, the default value of COSTS_N_INSNS(N) is N*4.
127 We treat it as 4-byte cost for each instruction
128 under code size consideration. */
129 switch (code)
130 {
131 case SET:
132 /* For 'SET' rtx, we need to return false
133 so that it can recursively calculate costs. */
134 return false;
135
136 case USE:
137 /* Used in combine.c as a marker. */
138 *total = 0;
139 break;
140
141 case CONST_INT:
142 /* All instructions involving constant operation
143 need to be considered for cost evaluation. */
144 if (outer_code == SET)
145 {
146 /* (set X imm5s), use movi55, 2-byte cost.
147 (set X imm20s), use movi, 4-byte cost.
148 (set X BIG_INT), use sethi/ori, 8-byte cost. */
149 if (satisfies_constraint_Is05 (x))
150 *total = COSTS_N_INSNS (1) - 2;
151 else if (satisfies_constraint_Is20 (x))
152 *total = COSTS_N_INSNS (1);
153 else
154 *total = COSTS_N_INSNS (2);
155 }
156 else if (outer_code == PLUS || outer_code == MINUS)
157 {
158 /* Possible addi333/subi333 or subi45/addi45, 2-byte cost.
159 General case, cost 1 instruction with 4-byte. */
160 if (satisfies_constraint_Iu05 (x))
161 *total = COSTS_N_INSNS (1) - 2;
162 else
163 *total = COSTS_N_INSNS (1);
164 }
165 else if (outer_code == ASHIFT)
166 {
167 /* Possible slli333, 2-byte cost.
168 General case, cost 1 instruction with 4-byte. */
169 if (satisfies_constraint_Iu03 (x))
170 *total = COSTS_N_INSNS (1) - 2;
171 else
172 *total = COSTS_N_INSNS (1);
173 }
174 else if (outer_code == ASHIFTRT || outer_code == LSHIFTRT)
175 {
176 /* Possible srai45 or srli45, 2-byte cost.
177 General case, cost 1 instruction with 4-byte. */
178 if (satisfies_constraint_Iu05 (x))
179 *total = COSTS_N_INSNS (1) - 2;
180 else
181 *total = COSTS_N_INSNS (1);
182 }
183 else
184 {
185 /* For other cases, simply set it 4-byte cost. */
186 *total = COSTS_N_INSNS (1);
187 }
188 break;
189
190 case CONST_DOUBLE:
191 /* It requires high part and low part processing, set it 8-byte cost. */
192 *total = COSTS_N_INSNS (2);
193 break;
194
195 default:
196 /* For other cases, generally we set it 4-byte cost
197 and stop resurively traversing. */
198 *total = COSTS_N_INSNS (1);
199 break;
200 }
201
202 return true;
203 }
204
205 int
206 nds32_address_cost_impl (rtx address,
207 machine_mode mode ATTRIBUTE_UNUSED,
208 addr_space_t as ATTRIBUTE_UNUSED,
209 bool speed)
210 {
211 rtx plus0, plus1;
212 enum rtx_code code;
213
214 code = GET_CODE (address);
215
216 /* According to 'speed', goto suitable cost model section. */
217 if (speed)
218 goto performance_cost;
219 else
220 goto size_cost;
221
222 performance_cost:
223 /* This is section for performance cost model. */
224
225 /* FALLTHRU, currently we use same cost model as size_cost. */
226
227 size_cost:
228 /* This is section for size cost model. */
229
230 switch (code)
231 {
232 case POST_MODIFY:
233 case POST_INC:
234 case POST_DEC:
235 /* We encourage that rtx contains
236 POST_MODIFY/POST_INC/POST_DEC behavior. */
237 return 0;
238
239 case SYMBOL_REF:
240 /* We can have gp-relative load/store for symbol_ref.
241 Have it 4-byte cost. */
242 return COSTS_N_INSNS (1);
243
244 case CONST:
245 /* It is supposed to be the pattern (const (plus symbol_ref const_int)).
246 Have it 4-byte cost. */
247 return COSTS_N_INSNS (1);
248
249 case REG:
250 /* Simply return 4-byte costs. */
251 return COSTS_N_INSNS (1);
252
253 case PLUS:
254 /* We do not need to check if the address is a legitimate address,
255 because this hook is never called with an invalid address.
256 But we better check the range of
257 const_int value for cost, if it exists. */
258 plus0 = XEXP (address, 0);
259 plus1 = XEXP (address, 1);
260
261 if (REG_P (plus0) && CONST_INT_P (plus1))
262 {
263 /* If it is possible to be lwi333/swi333 form,
264 make it 2-byte cost. */
265 if (satisfies_constraint_Iu05 (plus1))
266 return (COSTS_N_INSNS (1) - 2);
267 else
268 return COSTS_N_INSNS (1);
269 }
270
271 /* For other 'plus' situation, make it cost 4-byte. */
272 return COSTS_N_INSNS (1);
273
274 default:
275 break;
276 }
277
278 return COSTS_N_INSNS (4);
279 }
280
281 /* ------------------------------------------------------------------------ */
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