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1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
34
35 /* MIPS external variables defined in mips.c. */
36
37 /* comparison type */
38 enum cmp_type {
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
44 };
45
46 /* types of delay slot */
47 enum delay_type {
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
52 };
53
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
58
59 enum processor_type {
60 PROCESSOR_DEFAULT,
61 PROCESSOR_R3000,
62 PROCESSOR_R3900,
63 PROCESSOR_R6000,
64 PROCESSOR_R4000,
65 PROCESSOR_R4100,
66 PROCESSOR_R4300,
67 PROCESSOR_R4600,
68 PROCESSOR_R4650,
69 PROCESSOR_R5000,
70 PROCESSOR_R8000,
71 PROCESSOR_R4KC,
72 PROCESSOR_R5KC,
73 PROCESSOR_R20KC
74 };
75
76 /* Recast the cpu class to be the cpu attribute. */
77 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
78
79 /* Which ABI to use. These are constants because abi64.h must check their
80 value at preprocessing time.
81
82 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
83 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
84
85 #define ABI_32 0
86 #define ABI_N32 1
87 #define ABI_64 2
88 #define ABI_EABI 3
89 #define ABI_O64 4
90 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
91 which is not the same as the above EABI (defined by Cygnus,
92 Greenhills, and Toshiba?). MEABI is not yet complete or published,
93 but at this point it looks like N32 as far as calling conventions go,
94 but allows for either 32 or 64 bit registers.
95
96 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
97 EABI the legacy EABI. In the end we may end up calling both ABI's
98 EABI but give them different version numbers, but for now I'm going
99 with different names. */
100 #define ABI_MEABI 5
101
102 /* Whether to emit abicalls code sequences or not. */
103
104 enum mips_abicalls_type {
105 MIPS_ABICALLS_NO,
106 MIPS_ABICALLS_YES
107 };
108
109 /* Recast the abicalls class to be the abicalls attribute. */
110 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
111
112 /* Which type of block move to do (whether or not the last store is
113 split out so it can fill a branch delay slot). */
114
115 enum block_move_type {
116 BLOCK_MOVE_NORMAL, /* generate complete block move */
117 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
118 BLOCK_MOVE_LAST /* generate just the last store */
119 };
120
121 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
122 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
123 extern const char *current_function_file; /* filename current function is in */
124 extern int num_source_filenames; /* current .file # */
125 extern int inside_function; /* != 0 if inside of a function */
126 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
127 extern int file_in_function_warning; /* warning given about .file in func */
128 extern int sdb_label_count; /* block start/end next label # */
129 extern int sdb_begin_function_line; /* Starting Line of current function */
130 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
131 extern int g_switch_value; /* value of the -G xx switch */
132 extern int g_switch_set; /* whether -G xx was passed. */
133 extern int sym_lineno; /* sgi next label # for each stmt */
134 extern int set_noreorder; /* # of nested .set noreorder's */
135 extern int set_nomacro; /* # of nested .set nomacro's */
136 extern int set_noat; /* # of nested .set noat's */
137 extern int set_volatile; /* # of nested .set volatile's */
138 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
139 extern int mips_dbx_regno[]; /* Map register # to debug register # */
140 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
141 extern enum cmp_type branch_type; /* what type of branch to use */
142 extern enum processor_type mips_arch; /* which cpu to codegen for */
143 extern enum processor_type mips_tune; /* which cpu to schedule for */
144 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
145 extern int mips_isa; /* architectural level */
146 extern int mips16; /* whether generating mips16 code */
147 extern int mips16_hard_float; /* mips16 without -msoft-float */
148 extern int mips_entry; /* generate entry/exit for mips16 */
149 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
150 extern const char *mips_arch_string; /* for -march=<xxx> */
151 extern const char *mips_tune_string; /* for -mtune=<xxx> */
152 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
153 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
154 extern const char *mips_entry_string; /* for -mentry */
155 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
156 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
157 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
158 extern int mips_split_addresses; /* perform high/lo_sum support */
159 extern int dslots_load_total; /* total # load related delay slots */
160 extern int dslots_load_filled; /* # filled load delay slots */
161 extern int dslots_jump_total; /* total # jump related delay slots */
162 extern int dslots_jump_filled; /* # filled jump delay slots */
163 extern int dslots_number_nops; /* # of nops needed by previous insn */
164 extern int num_refs[3]; /* # 1/2/3 word references */
165 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
166 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
167 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
168 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
169 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
170 extern int mips_string_length; /* length of strings for mips16 */
171 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
172
173 /* Functions to change what output section we are using. */
174 extern void rdata_section PARAMS ((void));
175 extern void sdata_section PARAMS ((void));
176 extern void sbss_section PARAMS ((void));
177
178 /* Stubs for half-pic support if not OSF/1 reference platform. */
179
180 #ifndef HALF_PIC_P
181 #define HALF_PIC_P() 0
182 #define HALF_PIC_NUMBER_PTRS 0
183 #define HALF_PIC_NUMBER_REFS 0
184 #define HALF_PIC_ENCODE(DECL)
185 #define HALF_PIC_DECLARE(NAME)
186 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
187 #define HALF_PIC_ADDRESS_P(X) 0
188 #define HALF_PIC_PTR(X) X
189 #define HALF_PIC_FINISH(STREAM)
190 #endif
191
192 /* Macros to silence warnings about numbers being signed in traditional
193 C and unsigned in ISO C when compiled on 32-bit hosts. */
194
195 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
196 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
197 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
198
199 \f
200 /* Run-time compilation parameters selecting different hardware subsets. */
201
202 /* Macros used in the machine description to test the flags. */
203
204 /* Bits for real switches */
205 #define MASK_INT64 0x00000001 /* ints are 64 bits */
206 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
207 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
208 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
209 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
210 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
211 #define MASK_STATS 0x00000040 /* print statistics to stderr */
212 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
213 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
214 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
215 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
216 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
217 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
218 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
219 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
220 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
221 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
222 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
223 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
224 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
225 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
226 #define MASK_NO_CHECK_ZERO_DIV \
227 0x00200000 /* divide by zero checking */
228 #define MASK_CHECK_RANGE_DIV \
229 0x00400000 /* divide result range checking */
230 #define MASK_UNINIT_CONST_IN_RODATA \
231 0x00800000 /* Store uninitialized
232 consts in rodata */
233 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
234 multiply-add operations. */
235
236 /* Debug switches, not documented */
237 #define MASK_DEBUG 0 /* unused */
238 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
239 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
240 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
241 #define MASK_DEBUG_D 0 /* don't do define_split's */
242 #define MASK_DEBUG_E 0 /* function_arg debug */
243 #define MASK_DEBUG_F 0 /* ??? */
244 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
245 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
246 #define MASK_DEBUG_I 0 /* unused */
247
248 /* Dummy switches used only in specs */
249 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
250
251 /* r4000 64 bit sizes */
252 #define TARGET_INT64 (target_flags & MASK_INT64)
253 #define TARGET_LONG64 (target_flags & MASK_LONG64)
254 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
255 #define TARGET_64BIT (target_flags & MASK_64BIT)
256
257 /* Mips vs. GNU linker */
258 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
259
260 /* Mips vs. GNU assembler */
261 #define TARGET_GAS (target_flags & MASK_GAS)
262 #define TARGET_MIPS_AS (!TARGET_GAS)
263
264 /* Debug Modes */
265 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
266 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
267 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
268 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
269 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
270 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
271 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
272 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
273 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
274 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
275
276 /* Reg. Naming in .s ($21 vs. $a0) */
277 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
278
279 /* Optimize for Sdata/Sbss */
280 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
281
282 /* print program statistics */
283 #define TARGET_STATS (target_flags & MASK_STATS)
284
285 /* call memcpy instead of inline code */
286 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
287
288 /* .abicalls, etc from Pyramid V.4 */
289 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
290
291 /* OSF pic references to externs */
292 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
293
294 /* software floating point */
295 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
296 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
297
298 /* always call through a register */
299 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
300
301 /* generate embedded PIC code;
302 requires gas. */
303 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
304
305 /* for embedded systems, optimize for
306 reduced RAM space instead of for
307 fastest code. */
308 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
309
310 /* always store uninitialized const
311 variables in rodata, requires
312 TARGET_EMBEDDED_DATA. */
313 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
314
315 /* generate big endian code. */
316 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
317
318 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
319 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
320
321 #define TARGET_MAD (target_flags & MASK_MAD)
322
323 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
324
325 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
326
327 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
328 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
329
330 /* This is true if we must enable the assembly language file switching
331 code. */
332
333 #define TARGET_FILE_SWITCHING \
334 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
335
336 /* We must disable the function end stabs when doing the file switching trick,
337 because the Lscope stabs end up in the wrong place, making it impossible
338 to debug the resulting code. */
339 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
340
341 /* Generate mips16 code */
342 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
343
344 /* Architecture target defines. */
345 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
346 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
347 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
348 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
349 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
350 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
351
352 /* Scheduling target defines. */
353 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
354 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
355 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
356 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
357 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
358
359 /* Macro to define tables used to set the flags.
360 This is a list in braces of pairs in braces,
361 each pair being { "NAME", VALUE }
362 where VALUE is the bits to set or minus the bits to clear.
363 An empty string NAME is used to identify the default VALUE. */
364
365 #define TARGET_SWITCHES \
366 { \
367 {"no-crt0", 0, \
368 N_("No default crt0.o") }, \
369 {"int64", MASK_INT64 | MASK_LONG64, \
370 N_("Use 64-bit int type")}, \
371 {"long64", MASK_LONG64, \
372 N_("Use 64-bit long type")}, \
373 {"long32", -(MASK_LONG64 | MASK_INT64), \
374 N_("Use 32-bit long type")}, \
375 {"split-addresses", MASK_SPLIT_ADDR, \
376 N_("Optimize lui/addiu address loads")}, \
377 {"no-split-addresses", -MASK_SPLIT_ADDR, \
378 N_("Don't optimize lui/addiu address loads")}, \
379 {"mips-as", -MASK_GAS, \
380 N_("Use MIPS as")}, \
381 {"gas", MASK_GAS, \
382 N_("Use GNU as")}, \
383 {"rnames", MASK_NAME_REGS, \
384 N_("Use symbolic register names")}, \
385 {"no-rnames", -MASK_NAME_REGS, \
386 N_("Don't use symbolic register names")}, \
387 {"gpOPT", MASK_GPOPT, \
388 N_("Use GP relative sdata/sbss sections")}, \
389 {"gpopt", MASK_GPOPT, \
390 N_("Use GP relative sdata/sbss sections")}, \
391 {"no-gpOPT", -MASK_GPOPT, \
392 N_("Don't use GP relative sdata/sbss sections")}, \
393 {"no-gpopt", -MASK_GPOPT, \
394 N_("Don't use GP relative sdata/sbss sections")}, \
395 {"stats", MASK_STATS, \
396 N_("Output compiler statistics")}, \
397 {"no-stats", -MASK_STATS, \
398 N_("Don't output compiler statistics")}, \
399 {"memcpy", MASK_MEMCPY, \
400 N_("Don't optimize block moves")}, \
401 {"no-memcpy", -MASK_MEMCPY, \
402 N_("Optimize block moves")}, \
403 {"mips-tfile", MASK_MIPS_TFILE, \
404 N_("Use mips-tfile asm postpass")}, \
405 {"no-mips-tfile", -MASK_MIPS_TFILE, \
406 N_("Don't use mips-tfile asm postpass")}, \
407 {"soft-float", MASK_SOFT_FLOAT, \
408 N_("Use software floating point")}, \
409 {"hard-float", -MASK_SOFT_FLOAT, \
410 N_("Use hardware floating point")}, \
411 {"fp64", MASK_FLOAT64, \
412 N_("Use 64-bit FP registers")}, \
413 {"fp32", -MASK_FLOAT64, \
414 N_("Use 32-bit FP registers")}, \
415 {"gp64", MASK_64BIT, \
416 N_("Use 64-bit general registers")}, \
417 {"gp32", -MASK_64BIT, \
418 N_("Use 32-bit general registers")}, \
419 {"abicalls", MASK_ABICALLS, \
420 N_("Use Irix PIC")}, \
421 {"no-abicalls", -MASK_ABICALLS, \
422 N_("Don't use Irix PIC")}, \
423 {"half-pic", MASK_HALF_PIC, \
424 N_("Use OSF PIC")}, \
425 {"no-half-pic", -MASK_HALF_PIC, \
426 N_("Don't use OSF PIC")}, \
427 {"long-calls", MASK_LONG_CALLS, \
428 N_("Use indirect calls")}, \
429 {"no-long-calls", -MASK_LONG_CALLS, \
430 N_("Don't use indirect calls")}, \
431 {"embedded-pic", MASK_EMBEDDED_PIC, \
432 N_("Use embedded PIC")}, \
433 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
434 N_("Don't use embedded PIC")}, \
435 {"embedded-data", MASK_EMBEDDED_DATA, \
436 N_("Use ROM instead of RAM")}, \
437 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
438 N_("Don't use ROM instead of RAM")}, \
439 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
440 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
441 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
442 N_("Don't put uninitialized constants in ROM")}, \
443 {"eb", MASK_BIG_ENDIAN, \
444 N_("Use big-endian byte order")}, \
445 {"el", -MASK_BIG_ENDIAN, \
446 N_("Use little-endian byte order")}, \
447 {"single-float", MASK_SINGLE_FLOAT, \
448 N_("Use single (32-bit) FP only")}, \
449 {"double-float", -MASK_SINGLE_FLOAT, \
450 N_("Don't use single (32-bit) FP only")}, \
451 {"mad", MASK_MAD, \
452 N_("Use multiply accumulate")}, \
453 {"no-mad", -MASK_MAD, \
454 N_("Don't use multiply accumulate")}, \
455 {"no-fused-madd", MASK_NO_FUSED_MADD, \
456 N_("Don't generate fused multiply/add instructions")}, \
457 {"fused-madd", -MASK_NO_FUSED_MADD, \
458 N_("Generate fused multiply/add instructions")}, \
459 {"fix4300", MASK_4300_MUL_FIX, \
460 N_("Work around early 4300 hardware bug")}, \
461 {"no-fix4300", -MASK_4300_MUL_FIX, \
462 N_("Don't work around early 4300 hardware bug")}, \
463 {"3900", 0, \
464 N_("Optimize for 3900")}, \
465 {"4650", 0, \
466 N_("Optimize for 4650")}, \
467 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
468 N_("Trap on integer divide by zero")}, \
469 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
470 N_("Don't trap on integer divide by zero")}, \
471 {"check-range-division",MASK_CHECK_RANGE_DIV, \
472 N_("Trap on integer divide overflow")}, \
473 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
474 N_("Don't trap on integer divide overflow")}, \
475 {"debug", MASK_DEBUG, \
476 NULL}, \
477 {"debuga", MASK_DEBUG_A, \
478 NULL}, \
479 {"debugb", MASK_DEBUG_B, \
480 NULL}, \
481 {"debugc", MASK_DEBUG_C, \
482 NULL}, \
483 {"debugd", MASK_DEBUG_D, \
484 NULL}, \
485 {"debuge", MASK_DEBUG_E, \
486 NULL}, \
487 {"debugf", MASK_DEBUG_F, \
488 NULL}, \
489 {"debugg", MASK_DEBUG_G, \
490 NULL}, \
491 {"debugh", MASK_DEBUG_H, \
492 NULL}, \
493 {"debugi", MASK_DEBUG_I, \
494 NULL}, \
495 {"", (TARGET_DEFAULT \
496 | TARGET_CPU_DEFAULT \
497 | TARGET_ENDIAN_DEFAULT), \
498 NULL}, \
499 }
500
501 /* Default target_flags if no switches are specified */
502
503 #ifndef TARGET_DEFAULT
504 #define TARGET_DEFAULT 0
505 #endif
506
507 #ifndef TARGET_CPU_DEFAULT
508 #define TARGET_CPU_DEFAULT 0
509 #endif
510
511 #ifndef TARGET_ENDIAN_DEFAULT
512 #ifndef DECSTATION
513 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
514 #else
515 #define TARGET_ENDIAN_DEFAULT 0
516 #endif
517 #endif
518
519 #ifndef MIPS_ISA_DEFAULT
520 #define MIPS_ISA_DEFAULT 1
521 #endif
522
523 #ifdef IN_LIBGCC2
524 #undef TARGET_64BIT
525 /* Make this compile time constant for libgcc2 */
526 #ifdef __mips64
527 #define TARGET_64BIT 1
528 #else
529 #define TARGET_64BIT 0
530 #endif
531 #endif /* IN_LIBGCC2 */
532
533 #ifndef MULTILIB_ENDIAN_DEFAULT
534 #if TARGET_ENDIAN_DEFAULT == 0
535 #define MULTILIB_ENDIAN_DEFAULT "EL"
536 #else
537 #define MULTILIB_ENDIAN_DEFAULT "EB"
538 #endif
539 #endif
540
541 #ifndef MULTILIB_ISA_DEFAULT
542 # if MIPS_ISA_DEFAULT == 1
543 # define MULTILIB_ISA_DEFAULT "mips1"
544 # else
545 # if MIPS_ISA_DEFAULT == 2
546 # define MULTILIB_ISA_DEFAULT "mips2"
547 # else
548 # if MIPS_ISA_DEFAULT == 3
549 # define MULTILIB_ISA_DEFAULT "mips3"
550 # else
551 # if MIPS_ISA_DEFAULT == 4
552 # define MULTILIB_ISA_DEFAULT "mips4"
553 # else
554 # if MIPS_ISA_DEFAULT == 32
555 # define MULTILIB_ISA_DEFAULT "mips32"
556 # else
557 # if MIPS_ISA_DEFAULT == 64
558 # define MULTILIB_ISA_DEFAULT "mips64"
559 # else
560 # define MULTILIB_ISA_DEFAULT "mips1"
561 # endif
562 # endif
563 # endif
564 # endif
565 # endif
566 # endif
567 #endif
568
569 #ifndef MULTILIB_DEFAULTS
570 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
571 #endif
572
573 /* We must pass -EL to the linker by default for little endian embedded
574 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
575 linker will default to using big-endian output files. The OUTPUT_FORMAT
576 line must be in the linker script, otherwise -EB/-EL will not work. */
577
578 #ifndef ENDIAN_SPEC
579 #if TARGET_ENDIAN_DEFAULT == 0
580 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
581 #else
582 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
583 #endif
584 #endif
585
586 /* This macro is similar to `TARGET_SWITCHES' but defines names of
587 command options that have values. Its definition is an
588 initializer with a subgrouping for each command option.
589
590 Each subgrouping contains a string constant, that defines the
591 fixed part of the option name, and the address of a variable.
592 The variable, type `char *', is set to the variable part of the
593 given option if the fixed part matches. The actual option name
594 is made by appending `-m' to the specified name.
595
596 Here is an example which defines `-mshort-data-NUMBER'. If the
597 given option is `-mshort-data-512', the variable `m88k_short_data'
598 will be set to the string `"512"'.
599
600 extern char *m88k_short_data;
601 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
602
603 #define TARGET_OPTIONS \
604 { \
605 SUBTARGET_TARGET_OPTIONS \
606 { "cpu=", &mips_cpu_string, \
607 N_("Specify CPU for scheduling purposes")}, \
608 { "tune=", &mips_tune_string, \
609 N_("Specify CPU for scheduling purposes")}, \
610 { "arch=", &mips_arch_string, \
611 N_("Specify CPU for code generation purposes")}, \
612 { "ips", &mips_isa_string, \
613 N_("Specify a Standard MIPS ISA")}, \
614 { "entry", &mips_entry_string, \
615 N_("Use mips16 entry/exit psuedo ops")}, \
616 { "no-mips16", &mips_no_mips16_string, \
617 N_("Don't use MIPS16 instructions")}, \
618 { "explicit-type-size", &mips_explicit_type_size_string, \
619 NULL}, \
620 { "no-flush-func", &mips_cache_flush_func, \
621 N_("Don't call any cache flush functions")}, \
622 { "flush-func=", &mips_cache_flush_func, \
623 N_("Specify cache flush function")}, \
624 }
625
626 /* This is meant to be redefined in the host dependent files. */
627 #define SUBTARGET_TARGET_OPTIONS
628
629 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
630
631 /* Generate three-operand multiply instructions for SImode. */
632 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
633 || mips_isa == 32 \
634 || mips_isa == 64) \
635 && !TARGET_MIPS16)
636
637 /* Generate three-operand multiply instructions for DImode. */
638 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
639 && !TARGET_MIPS16)
640
641 /* Macros to decide whether certain features are available or not,
642 depending on the instruction set architecture level. */
643
644 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
645 #define HAVE_SQRT_P() (mips_isa != 1)
646
647 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
648 #define ISA_HAS_64BIT_REGS (mips_isa == 3 \
649 || mips_isa == 4 \
650 || mips_isa == 64)
651
652 /* ISA has branch likely instructions (eg. mips2). */
653 /* Disable branchlikely for tx39 until compare rewrite. They haven't
654 been generated up to this point. */
655 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
656 /* || TARGET_MIPS3900 */)
657
658 /* ISA has the conditional move instructions introduced in mips4. */
659 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
660 || mips_isa == 32 \
661 || mips_isa == 64)
662
663 /* ISA has just the integer condition move instructions (movn,movz) */
664 #define ISA_HAS_INT_CONDMOVE 0
665
666
667
668 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
669 branch on CC, and move (both FP and non-FP) on CC. */
670 #define ISA_HAS_8CC (mips_isa == 4 \
671 || mips_isa == 32 \
672 || mips_isa == 64)
673
674
675 /* This is a catch all for the other new mips4 instructions: indexed load and
676 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
677 and the FP recip and recip sqrt instructions */
678 #define ISA_HAS_FP4 (mips_isa == 4 \
679 )
680
681 /* ISA has conditional trap instructions. */
682 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
683
684 /* ISA has multiply-accumulate instructions, madd and msub. */
685 #define ISA_HAS_MADD_MSUB (mips_isa == 32 \
686 || mips_isa == 64 \
687 )
688
689 /* ISA has nmadd and nmsub instructions. */
690 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
691 )
692
693 /* ISA has count leading zeroes/ones instruction (not implemented). */
694 #define ISA_HAS_CLZ_CLO (mips_isa == 32 \
695 || mips_isa == 64 \
696 )
697
698 /* ISA has double-word count leading zeroes/ones instruction (not
699 implemented). */
700 #define ISA_HAS_DCLZ_DCLO (mips_isa == 64)
701
702
703 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
704 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
705 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
706 target_flags, and -mgp64 sets MASK_64BIT.
707
708 Setting MASK_64BIT in target_flags will cause gcc to assume that
709 registers are 64 bits wide. int, long and void * will be 32 bit;
710 this may be changed with -mint64 or -mlong64.
711
712 The gen* programs link code that refers to MASK_64BIT. They don't
713 actually use the information in target_flags; they just refer to
714 it. */
715 \f
716 /* Switch Recognition by gcc.c. Add -G xx support */
717
718 #undef SWITCH_TAKES_ARG
719 #define SWITCH_TAKES_ARG(CHAR) \
720 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
721
722 /* Sometimes certain combinations of command options do not make sense
723 on a particular target machine. You can define a macro
724 `OVERRIDE_OPTIONS' to take account of this. This macro, if
725 defined, is executed once just after all the command options have
726 been parsed.
727
728 On the MIPS, it is used to handle -G. We also use it to set up all
729 of the tables referenced in the other macros. */
730
731 #define OVERRIDE_OPTIONS override_options ()
732
733 /* Zero or more C statements that may conditionally modify two
734 variables `fixed_regs' and `call_used_regs' (both of type `char
735 []') after they have been initialized from the two preceding
736 macros.
737
738 This is necessary in case the fixed or call-clobbered registers
739 depend on target flags.
740
741 You need not define this macro if it has no work to do.
742
743 If the usage of an entire class of registers depends on the target
744 flags, you may indicate this to GCC by using this macro to modify
745 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
746 the classes which should not be used by GCC. Also define the macro
747 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
748 letter for a class that shouldn't be used.
749
750 (However, if this class is not included in `GENERAL_REGS' and all
751 of the insn patterns whose constraints permit this class are
752 controlled by target switches, then GCC will automatically avoid
753 using these registers when the target switches are opposed to
754 them.) */
755
756 #define CONDITIONAL_REGISTER_USAGE \
757 do \
758 { \
759 if (!TARGET_HARD_FLOAT) \
760 { \
761 int regno; \
762 \
763 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
764 fixed_regs[regno] = call_used_regs[regno] = 1; \
765 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
766 fixed_regs[regno] = call_used_regs[regno] = 1; \
767 } \
768 else if (! ISA_HAS_8CC) \
769 { \
770 int regno; \
771 \
772 /* We only have a single condition code register. We \
773 implement this by hiding all the condition code registers, \
774 and generating RTL that refers directly to ST_REG_FIRST. */ \
775 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
776 fixed_regs[regno] = call_used_regs[regno] = 1; \
777 } \
778 /* In mips16 mode, we permit the $t temporary registers to be used \
779 for reload. We prohibit the unused $s registers, since they \
780 are caller saved, and saving them via a mips16 register would \
781 probably waste more time than just reloading the value. */ \
782 if (TARGET_MIPS16) \
783 { \
784 fixed_regs[18] = call_used_regs[18] = 1; \
785 fixed_regs[19] = call_used_regs[19] = 1; \
786 fixed_regs[20] = call_used_regs[20] = 1; \
787 fixed_regs[21] = call_used_regs[21] = 1; \
788 fixed_regs[22] = call_used_regs[22] = 1; \
789 fixed_regs[23] = call_used_regs[23] = 1; \
790 fixed_regs[26] = call_used_regs[26] = 1; \
791 fixed_regs[27] = call_used_regs[27] = 1; \
792 fixed_regs[30] = call_used_regs[30] = 1; \
793 } \
794 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
795 } \
796 while (0)
797
798 /* This is meant to be redefined in the host dependent files. */
799 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
800
801 /* Show we can debug even without a frame pointer. */
802 #define CAN_DEBUG_WITHOUT_FP
803 \f
804 /* Complain about missing specs and predefines that should be defined in each
805 of the target tm files to override the defaults. This is mostly a place-
806 holder until I can get each of the files updated [mm]. */
807
808 #if defined(OSF_OS) \
809 || defined(DECSTATION) \
810 || defined(SGI_TARGET) \
811 || defined(MIPS_NEWS) \
812 || defined(MIPS_SYSV) \
813 || defined(MIPS_SVR4) \
814 || defined(MIPS_BSD43)
815
816 #ifndef CPP_PREDEFINES
817 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
818 #endif
819
820 #ifndef LIB_SPEC
821 #error "Define LIB_SPEC in the appropriate tm.h file"
822 #endif
823
824 #ifndef STARTFILE_SPEC
825 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
826 #endif
827
828 #ifndef MACHINE_TYPE
829 #error "Define MACHINE_TYPE in the appropriate tm.h file"
830 #endif
831 #endif
832
833 /* Tell collect what flags to pass to nm. */
834 #ifndef NM_FLAGS
835 #define NM_FLAGS "-Bn"
836 #endif
837
838 \f
839 /* Names to predefine in the preprocessor for this target machine. */
840
841 #ifndef CPP_PREDEFINES
842 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
843 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
844 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
845 #endif
846
847 /* Assembler specs. */
848
849 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
850 than gas. */
851
852 #define MIPS_AS_ASM_SPEC "\
853 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
854 %{pipe: %e-pipe is not supported} \
855 %{K} %(subtarget_mips_as_asm_spec)"
856
857 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
858 rather than gas. It may be overridden by subtargets. */
859
860 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
861 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
862 #endif
863
864 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
865 assembler. */
866
867 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
868
869
870 extern int mips_abi;
871
872 #ifndef MIPS_ABI_DEFAULT
873 #define MIPS_ABI_DEFAULT ABI_32
874 #endif
875
876 #ifndef ABI_GAS_ASM_SPEC
877 #define ABI_GAS_ASM_SPEC ""
878 #endif
879
880 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
881 GAS_ASM_SPEC as the default, depending upon the value of
882 TARGET_DEFAULT. */
883
884 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
885 /* GAS */
886
887 #define TARGET_ASM_SPEC "\
888 %{mmips-as: %(mips_as_asm_spec)} \
889 %{!mmips-as: %(gas_asm_spec)}"
890
891 #else /* not GAS */
892
893 #define TARGET_ASM_SPEC "\
894 %{!mgas: %(mips_as_asm_spec)} \
895 %{mgas: %(gas_asm_spec)}"
896
897 #endif /* not GAS */
898
899 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
900 to the assembler. It may be overridden by subtargets. */
901 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
902 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
903 %{noasmopt:-O0} \
904 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
905 #endif
906
907 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
908 the assembler. It may be overridden by subtargets. */
909 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
910 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
911 %{g} %{g0} %{g1} %{g2} %{g3} \
912 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
913 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
914 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
915 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
916 #endif
917
918 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
919 overridden by subtargets. */
920
921 #ifndef SUBTARGET_ASM_SPEC
922 #define SUBTARGET_ASM_SPEC ""
923 #endif
924
925 /* ASM_SPEC is the set of arguments to pass to the assembler. */
926
927 #undef ASM_SPEC
928 #define ASM_SPEC "\
929 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
930 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
931 %(subtarget_asm_optimizing_spec) \
932 %(subtarget_asm_debugging_spec) \
933 %{membedded-pic} \
934 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
935 %(target_asm_spec) \
936 %(subtarget_asm_spec)"
937
938 /* Specify to run a post-processor, mips-tfile after the assembler
939 has run to stuff the mips debug information into the object file.
940 This is needed because the $#!%^ MIPS assembler provides no way
941 of specifying such information in the assembly file. If we are
942 cross compiling, disable mips-tfile unless the user specifies
943 -mmips-tfile. */
944
945 #ifndef ASM_FINAL_SPEC
946 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
947 /* GAS */
948 #define ASM_FINAL_SPEC "\
949 %{mmips-as: %{!mno-mips-tfile: \
950 \n mips-tfile %{v*: -v} \
951 %{K: -I %b.o~} \
952 %{!K: %{save-temps: -I %b.o~}} \
953 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
954 %{.s:%i} %{!.s:%g.s}}}"
955
956 #else
957 /* not GAS */
958 #define ASM_FINAL_SPEC "\
959 %{!mgas: %{!mno-mips-tfile: \
960 \n mips-tfile %{v*: -v} \
961 %{K: -I %b.o~} \
962 %{!K: %{save-temps: -I %b.o~}} \
963 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
964 %{.s:%i} %{!.s:%g.s}}}"
965
966 #endif
967 #endif /* ASM_FINAL_SPEC */
968
969 /* Redefinition of libraries used. Mips doesn't support normal
970 UNIX style profiling via calling _mcount. It does offer
971 profiling that samples the PC, so do what we can... */
972
973 #ifndef LIB_SPEC
974 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
975 #endif
976
977 /* Extra switches sometimes passed to the linker. */
978 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
979 will interpret it as a -b option. */
980
981 #ifndef LINK_SPEC
982 #define LINK_SPEC "\
983 %(endian_spec) \
984 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
985 %{bestGnum} %{shared} %{non_shared}"
986 #endif /* LINK_SPEC defined */
987
988
989 /* Specs for the compiler proper */
990
991 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
992 overridden by subtargets. */
993 #ifndef SUBTARGET_CC1_SPEC
994 #define SUBTARGET_CC1_SPEC ""
995 #endif
996
997 /* Deal with historic options. */
998 #ifndef CC1_CPU_SPEC
999 #define CC1_CPU_SPEC "\
1000 %{!mcpu*: \
1001 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
1002 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
1003 %{m4650:-march=r4650 -mmad -msingle-float \
1004 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
1005 #endif
1006
1007 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1008 /* Note, we will need to adjust the following if we ever find a MIPS variant
1009 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1010 that show up in this case. */
1011
1012 #ifndef CC1_SPEC
1013 #define CC1_SPEC "\
1014 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1015 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
1016 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1017 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1018 %{mips32:-mfp32 -mgp32} \
1019 %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1020 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1021 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
1022 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
1023 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
1024 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1025 %{pic-none: -mno-half-pic} \
1026 %{pic-lib: -mhalf-pic} \
1027 %{pic-extern: -mhalf-pic} \
1028 %{pic-calls: -mhalf-pic} \
1029 %{save-temps: } \
1030 %(subtarget_cc1_spec) \
1031 %(cc1_cpu_spec)"
1032 #endif
1033
1034 /* Preprocessor specs. */
1035
1036 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
1037 be overridden by subtargets. */
1038
1039 #ifndef SUBTARGET_CPP_SIZE_SPEC
1040
1041 #if MIPS_ISA_DEFAULT != 3 && MIPS_ISA_DEFAULT != 4 && MIPS_ISA_DEFAULT != 5 && MIPS_ISA_DEFAULT != 64
1042
1043 /* 32-bit cases first. */
1044
1045 #if MIPS_ABI_DEFAULT == ABI_EABI
1046 #define SUBTARGET_CPP_SIZE_SPEC "\
1047 %{mabi=eabi|!mabi=*:\
1048 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1049 %{mlong64:\
1050 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1051 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1052 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1053 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1054 %{mabi=o64:\
1055 %{mlong64:\
1056 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1057 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1058 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1059 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1060 "
1061 #endif
1062
1063 #if MIPS_ABI_DEFAULT == ABI_O64
1064 #define SUBTARGET_CPP_SIZE_SPEC "\
1065 %{mabi=eabi:\
1066 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1067 %{mlong64:\
1068 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1069 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1070 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1071 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1072 %{mabi=o64|!mabi=*:\
1073 %{mlong64:\
1074 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1075 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1076 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1077 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1078 "
1079 #endif
1080
1081 #if MIPS_ABI_DEFAULT == ABI_32
1082 #define SUBTARGET_CPP_SIZE_SPEC "\
1083 %{mabi=eabi:\
1084 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1085 %{mlong64:\
1086 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1087 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1088 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1089 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1090 %{mabi=o64:\
1091 %{mlong64:\
1092 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1093 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1094 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1095 %{mabi=32|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1096 "
1097 #endif
1098
1099 #if MIPS_ABI_DEFAULT == ABI_MEABI
1100 #define SUBTARGET_CPP_SIZE_SPEC "\
1101 %{mabi=eabi:\
1102 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1103 %{mlong64:\
1104 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1105 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1106 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1107 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1108 %{mabi=o64:\
1109 %{mlong64:\
1110 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1111 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1112 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1113 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1114 %{mabi=meabi|!mabi=*:\
1115 %{mips3|mips4|mips5|mips64|mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1116 %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}} \
1117 "
1118 #endif
1119
1120 #else
1121
1122 /* 64-bit default ISA. */
1123
1124 #if MIPS_ABI_DEFAULT == ABI_EABI
1125 #define SUBTARGET_CPP_SIZE_SPEC "\
1126 %{mabi=eabi|!mabi=*: \
1127 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1128 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1129 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1130 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1131 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1132 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1133 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1134 %{mabi=o64:\
1135 %{mlong64:\
1136 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1137 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1138 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1139 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1140 "
1141 #endif
1142
1143 #if MIPS_ABI_DEFAULT == ABI_O64
1144 #define SUBTARGET_CPP_SIZE_SPEC "\
1145 %{mabi=eabi: \
1146 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1147 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1148 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1149 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1150 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1151 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1152 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1153 %{mabi=o64|!mabi=*:\
1154 %{mlong64:\
1155 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1156 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1157 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1158 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1159 "
1160 #endif
1161
1162 #if MIPS_ABI_DEFAULT == ABI_32
1163 #define SUBTARGET_CPP_SIZE_SPEC "\
1164 %{mabi=eabi:\
1165 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1166 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1167 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1168 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1169 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1170 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1171 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1172 %{mabi=o64:\
1173 %{mlong64:\
1174 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1175 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1176 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1177 %{mabi=32|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1178 "
1179 #endif
1180
1181 #if MIPS_ABI_DEFAULT == ABI_MEABI
1182 #define SUBTARGET_CPP_SIZE_SPEC "\
1183 %{mabi=eabi:\
1184 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1185 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1186 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1187 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1188 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1189 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1190 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1191 %{mabi=o64:\
1192 %{mlong64:\
1193 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1194 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1195 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1196 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1197 %{mabi=meabi|!mabi=*:\
1198 %{mips1|mips2|mips32|mlong32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1199 %{!mips1:%{!mips2:%{!mips32:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}} \
1200 "
1201 #endif
1202
1203 #endif
1204
1205 #endif
1206
1207 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1208 overridden by subtargets. */
1209 #ifndef SUBTARGET_CPP_SPEC
1210 #define SUBTARGET_CPP_SPEC ""
1211 #endif
1212
1213 /* If we're using 64bit longs, then we have to define __LONG_MAX__
1214 correctly. Similarly for 64bit ints and __INT_MAX__. */
1215 #ifndef LONG_MAX_SPEC
1216 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
1217 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
1218 #else
1219 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
1220 #endif
1221 #endif
1222
1223 /* Define appropriate macros for fpr register size. */
1224 #ifndef CPP_FPR_SPEC
1225 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
1226 #define CPP_FPR_SPEC "-D__mips_fpr=64"
1227 #else
1228 #define CPP_FPR_SPEC "-D__mips_fpr=32"
1229 #endif
1230 #endif
1231
1232 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1233 of the source file extension. */
1234 #undef CPLUSPLUS_CPP_SPEC
1235 #define CPLUSPLUS_CPP_SPEC "\
1236 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1237 %(cpp) \
1238 "
1239 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1240
1241 #ifndef CPP_SPEC
1242 #define CPP_SPEC "\
1243 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1244 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1245 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1246 %(subtarget_cpp_size_spec) \
1247 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1248 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1249 %{mips32:-U__mips -D__mips=32} \
1250 %{mips64:-U__mips -D__mips=64 -D__mips64} \
1251 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1252 %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
1253 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1254 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1255 %{msoft-float:-D__mips_soft_float} \
1256 %{mabi=eabi:-D__mips_eabi} \
1257 %{mips16:%{!mno-mips16:-D__mips16}} \
1258 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1259 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1260 %(long_max_spec) \
1261 %(subtarget_cpp_spec) "
1262 #endif
1263
1264 /* This macro defines names of additional specifications to put in the specs
1265 that can be used in various specifications like CC1_SPEC. Its definition
1266 is an initializer with a subgrouping for each command option.
1267
1268 Each subgrouping contains a string constant, that defines the
1269 specification name, and a string constant that used by the GNU CC driver
1270 program.
1271
1272 Do not define this macro if it does not need to do anything. */
1273
1274 #define EXTRA_SPECS \
1275 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1276 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1277 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1278 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1279 { "long_max_spec", LONG_MAX_SPEC }, \
1280 { "cpp_fpr_spec", CPP_FPR_SPEC }, \
1281 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1282 { "gas_asm_spec", GAS_ASM_SPEC }, \
1283 { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
1284 { "target_asm_spec", TARGET_ASM_SPEC }, \
1285 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1286 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1287 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1288 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1289 { "endian_spec", ENDIAN_SPEC }, \
1290 SUBTARGET_EXTRA_SPECS
1291
1292 #ifndef SUBTARGET_EXTRA_SPECS
1293 #define SUBTARGET_EXTRA_SPECS
1294 #endif
1295
1296 /* If defined, this macro is an additional prefix to try after
1297 `STANDARD_EXEC_PREFIX'. */
1298
1299 #ifndef MD_EXEC_PREFIX
1300 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1301 #endif
1302
1303 #ifndef MD_STARTFILE_PREFIX
1304 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1305 #endif
1306
1307 \f
1308 /* Print subsidiary information on the compiler version in use. */
1309
1310 #define MIPS_VERSION "[AL 1.1, MM 40]"
1311
1312 #ifndef MACHINE_TYPE
1313 #define MACHINE_TYPE "BSD Mips"
1314 #endif
1315
1316 #ifndef TARGET_VERSION_INTERNAL
1317 #define TARGET_VERSION_INTERNAL(STREAM) \
1318 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1319 #endif
1320
1321 #ifndef TARGET_VERSION
1322 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1323 #endif
1324
1325 \f
1326 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1327 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1328 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1329
1330 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1331 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1332 #endif
1333
1334 /* By default, turn on GDB extensions. */
1335 #define DEFAULT_GDB_EXTENSIONS 1
1336
1337 /* If we are passing smuggling stabs through the MIPS ECOFF object
1338 format, put a comment in front of the .stab<x> operation so
1339 that the MIPS assembler does not choke. The mips-tfile program
1340 will correctly put the stab into the object file. */
1341
1342 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1343 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1344 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1345
1346 /* Local compiler-generated symbols must have a prefix that the assembler
1347 understands. By default, this is $, although some targets (e.g.,
1348 NetBSD-ELF) need to override this. */
1349
1350 #ifndef LOCAL_LABEL_PREFIX
1351 #define LOCAL_LABEL_PREFIX "$"
1352 #endif
1353
1354 /* By default on the mips, external symbols do not have an underscore
1355 prepended, but some targets (e.g., NetBSD) require this. */
1356
1357 #ifndef USER_LABEL_PREFIX
1358 #define USER_LABEL_PREFIX ""
1359 #endif
1360
1361 /* Forward references to tags are allowed. */
1362 #define SDB_ALLOW_FORWARD_REFERENCES
1363
1364 /* Unknown tags are also allowed. */
1365 #define SDB_ALLOW_UNKNOWN_REFERENCES
1366
1367 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1368 since the length can run past this up to a continuation point. */
1369 #undef DBX_CONTIN_LENGTH
1370 #define DBX_CONTIN_LENGTH 1500
1371
1372 /* How to renumber registers for dbx and gdb. */
1373 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1374
1375 /* The mapping from gcc register number to DWARF 2 CFA column number.
1376 This mapping does not allow for tracking register 0, since SGI's broken
1377 dwarf reader thinks column 0 is used for the frame address, but since
1378 register 0 is fixed this is not a problem. */
1379 #define DWARF_FRAME_REGNUM(REG) \
1380 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1381
1382 /* The DWARF 2 CFA column which tracks the return address. */
1383 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1384
1385 /* Before the prologue, RA lives in r31. */
1386 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1387
1388 /* Describe how we implement __builtin_eh_return. */
1389 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1390 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1391
1392 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1393 The default for this in 64-bit mode is 8, which causes problems with
1394 SFmode register saves. */
1395 #define DWARF_CIE_DATA_ALIGNMENT 4
1396
1397 /* Overrides for the COFF debug format. */
1398 #define PUT_SDB_SCL(a) \
1399 do { \
1400 extern FILE *asm_out_text_file; \
1401 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1402 } while (0)
1403
1404 #define PUT_SDB_INT_VAL(a) \
1405 do { \
1406 extern FILE *asm_out_text_file; \
1407 fprintf (asm_out_text_file, "\t.val\t"); \
1408 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1409 fprintf (asm_out_text_file, ";"); \
1410 } while (0)
1411
1412 #define PUT_SDB_VAL(a) \
1413 do { \
1414 extern FILE *asm_out_text_file; \
1415 fputs ("\t.val\t", asm_out_text_file); \
1416 output_addr_const (asm_out_text_file, (a)); \
1417 fputc (';', asm_out_text_file); \
1418 } while (0)
1419
1420 #define PUT_SDB_DEF(a) \
1421 do { \
1422 extern FILE *asm_out_text_file; \
1423 fprintf (asm_out_text_file, "\t%s.def\t", \
1424 (TARGET_GAS) ? "" : "#"); \
1425 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1426 fputc (';', asm_out_text_file); \
1427 } while (0)
1428
1429 #define PUT_SDB_PLAIN_DEF(a) \
1430 do { \
1431 extern FILE *asm_out_text_file; \
1432 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1433 (TARGET_GAS) ? "" : "#", (a)); \
1434 } while (0)
1435
1436 #define PUT_SDB_ENDEF \
1437 do { \
1438 extern FILE *asm_out_text_file; \
1439 fprintf (asm_out_text_file, "\t.endef\n"); \
1440 } while (0)
1441
1442 #define PUT_SDB_TYPE(a) \
1443 do { \
1444 extern FILE *asm_out_text_file; \
1445 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1446 } while (0)
1447
1448 #define PUT_SDB_SIZE(a) \
1449 do { \
1450 extern FILE *asm_out_text_file; \
1451 fprintf (asm_out_text_file, "\t.size\t"); \
1452 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1453 fprintf (asm_out_text_file, ";"); \
1454 } while (0)
1455
1456 #define PUT_SDB_DIM(a) \
1457 do { \
1458 extern FILE *asm_out_text_file; \
1459 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1460 } while (0)
1461
1462 #ifndef PUT_SDB_START_DIM
1463 #define PUT_SDB_START_DIM \
1464 do { \
1465 extern FILE *asm_out_text_file; \
1466 fprintf (asm_out_text_file, "\t.dim\t"); \
1467 } while (0)
1468 #endif
1469
1470 #ifndef PUT_SDB_NEXT_DIM
1471 #define PUT_SDB_NEXT_DIM(a) \
1472 do { \
1473 extern FILE *asm_out_text_file; \
1474 fprintf (asm_out_text_file, "%d,", a); \
1475 } while (0)
1476 #endif
1477
1478 #ifndef PUT_SDB_LAST_DIM
1479 #define PUT_SDB_LAST_DIM(a) \
1480 do { \
1481 extern FILE *asm_out_text_file; \
1482 fprintf (asm_out_text_file, "%d;", a); \
1483 } while (0)
1484 #endif
1485
1486 #define PUT_SDB_TAG(a) \
1487 do { \
1488 extern FILE *asm_out_text_file; \
1489 fprintf (asm_out_text_file, "\t.tag\t"); \
1490 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1491 fputc (';', asm_out_text_file); \
1492 } while (0)
1493
1494 /* For block start and end, we create labels, so that
1495 later we can figure out where the correct offset is.
1496 The normal .ent/.end serve well enough for functions,
1497 so those are just commented out. */
1498
1499 #define PUT_SDB_BLOCK_START(LINE) \
1500 do { \
1501 extern FILE *asm_out_text_file; \
1502 fprintf (asm_out_text_file, \
1503 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1504 LOCAL_LABEL_PREFIX, \
1505 sdb_label_count, \
1506 (TARGET_GAS) ? "" : "#", \
1507 LOCAL_LABEL_PREFIX, \
1508 sdb_label_count, \
1509 (LINE)); \
1510 sdb_label_count++; \
1511 } while (0)
1512
1513 #define PUT_SDB_BLOCK_END(LINE) \
1514 do { \
1515 extern FILE *asm_out_text_file; \
1516 fprintf (asm_out_text_file, \
1517 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1518 LOCAL_LABEL_PREFIX, \
1519 sdb_label_count, \
1520 (TARGET_GAS) ? "" : "#", \
1521 LOCAL_LABEL_PREFIX, \
1522 sdb_label_count, \
1523 (LINE)); \
1524 sdb_label_count++; \
1525 } while (0)
1526
1527 #define PUT_SDB_FUNCTION_START(LINE)
1528
1529 #define PUT_SDB_FUNCTION_END(LINE) \
1530 do { \
1531 extern FILE *asm_out_text_file; \
1532 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1533 } while (0)
1534
1535 #define PUT_SDB_EPILOGUE_END(NAME)
1536
1537 #define PUT_SDB_SRC_FILE(FILENAME) \
1538 do { \
1539 extern FILE *asm_out_text_file; \
1540 output_file_directive (asm_out_text_file, (FILENAME)); \
1541 } while (0)
1542
1543 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1544 sprintf ((BUFFER), ".%dfake", (NUMBER));
1545
1546 /* Correct the offset of automatic variables and arguments. Note that
1547 the MIPS debug format wants all automatic variables and arguments
1548 to be in terms of the virtual frame pointer (stack pointer before
1549 any adjustment in the function), while the MIPS 3.0 linker wants
1550 the frame pointer to be the stack pointer after the initial
1551 adjustment. */
1552
1553 #define DEBUGGER_AUTO_OFFSET(X) \
1554 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1555 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1556 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1557
1558 /* Tell collect that the object format is ECOFF */
1559 #ifndef OBJECT_FORMAT_ROSE
1560 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1561 #define EXTENDED_COFF /* ECOFF, not normal coff */
1562 #endif
1563 \f
1564 /* Target machine storage layout */
1565
1566 /* Define in order to support both big and little endian float formats
1567 in the same gcc binary. */
1568 #define REAL_ARITHMETIC
1569
1570 /* Define this if most significant bit is lowest numbered
1571 in instructions that operate on numbered bit-fields.
1572 */
1573 #define BITS_BIG_ENDIAN 0
1574
1575 /* Define this if most significant byte of a word is the lowest numbered. */
1576 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1577
1578 /* Define this if most significant word of a multiword number is the lowest. */
1579 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1580
1581 /* Define this to set the endianness to use in libgcc2.c, which can
1582 not depend on target_flags. */
1583 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1584 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1585 #else
1586 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1587 #endif
1588
1589 /* Number of bits in an addressable storage unit */
1590 #define BITS_PER_UNIT 8
1591
1592 /* Width in bits of a "word", which is the contents of a machine register.
1593 Note that this is not necessarily the width of data type `int';
1594 if using 16-bit ints on a 68000, this would still be 32.
1595 But on a machine with 16-bit registers, this would be 16. */
1596 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1597 #define MAX_BITS_PER_WORD 64
1598
1599 /* Width of a word, in units (bytes). */
1600 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1601 #define MIN_UNITS_PER_WORD 4
1602
1603 /* For MIPS, width of a floating point register. */
1604 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1605
1606 /* A C expression for the size in bits of the type `int' on the
1607 target machine. If you don't define this, the default is one
1608 word. */
1609 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1610
1611 /* Tell the preprocessor the maximum size of wchar_t. */
1612 #ifndef MAX_WCHAR_TYPE_SIZE
1613 #ifndef WCHAR_TYPE_SIZE
1614 #define MAX_WCHAR_TYPE_SIZE 64
1615 #endif
1616 #endif
1617
1618 /* A C expression for the size in bits of the type `short' on the
1619 target machine. If you don't define this, the default is half a
1620 word. (If this would be less than one storage unit, it is
1621 rounded up to one unit.) */
1622 #define SHORT_TYPE_SIZE 16
1623
1624 /* A C expression for the size in bits of the type `long' on the
1625 target machine. If you don't define this, the default is one
1626 word. */
1627 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1628 #define MAX_LONG_TYPE_SIZE 64
1629
1630 /* A C expression for the size in bits of the type `long long' on the
1631 target machine. If you don't define this, the default is two
1632 words. */
1633 #define LONG_LONG_TYPE_SIZE 64
1634
1635 /* A C expression for the size in bits of the type `char' on the
1636 target machine. If you don't define this, the default is one
1637 quarter of a word. (If this would be less than one storage unit,
1638 it is rounded up to one unit.) */
1639 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1640
1641 /* A C expression for the size in bits of the type `float' on the
1642 target machine. If you don't define this, the default is one
1643 word. */
1644 #define FLOAT_TYPE_SIZE 32
1645
1646 /* A C expression for the size in bits of the type `double' on the
1647 target machine. If you don't define this, the default is two
1648 words. */
1649 #define DOUBLE_TYPE_SIZE 64
1650
1651 /* A C expression for the size in bits of the type `long double' on
1652 the target machine. If you don't define this, the default is two
1653 words. */
1654 #define LONG_DOUBLE_TYPE_SIZE 64
1655
1656 /* Width in bits of a pointer.
1657 See also the macro `Pmode' defined below. */
1658 #ifndef POINTER_SIZE
1659 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1660 #endif
1661
1662 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1663 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1664
1665 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1666 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1667
1668 /* Allocation boundary (in *bits*) for the code of a function. */
1669 #define FUNCTION_BOUNDARY 32
1670
1671 /* Alignment of field after `int : 0' in a structure. */
1672 #define EMPTY_FIELD_BOUNDARY 32
1673
1674 /* Every structure's size must be a multiple of this. */
1675 /* 8 is observed right on a DECstation and on riscos 4.02. */
1676 #define STRUCTURE_SIZE_BOUNDARY 8
1677
1678 /* There is no point aligning anything to a rounder boundary than this. */
1679 #define BIGGEST_ALIGNMENT 64
1680
1681 /* Set this nonzero if move instructions will actually fail to work
1682 when given unaligned data. */
1683 #define STRICT_ALIGNMENT 1
1684
1685 /* Define this if you wish to imitate the way many other C compilers
1686 handle alignment of bitfields and the structures that contain
1687 them.
1688
1689 The behavior is that the type written for a bitfield (`int',
1690 `short', or other integer type) imposes an alignment for the
1691 entire structure, as if the structure really did contain an
1692 ordinary field of that type. In addition, the bitfield is placed
1693 within the structure so that it would fit within such a field,
1694 not crossing a boundary for it.
1695
1696 Thus, on most machines, a bitfield whose type is written as `int'
1697 would not cross a four-byte boundary, and would force four-byte
1698 alignment for the whole structure. (The alignment used may not
1699 be four bytes; it is controlled by the other alignment
1700 parameters.)
1701
1702 If the macro is defined, its definition should be a C expression;
1703 a nonzero value for the expression enables this behavior. */
1704
1705 #define PCC_BITFIELD_TYPE_MATTERS 1
1706
1707 /* If defined, a C expression to compute the alignment given to a
1708 constant that is being placed in memory. CONSTANT is the constant
1709 and ALIGN is the alignment that the object would ordinarily have.
1710 The value of this macro is used instead of that alignment to align
1711 the object.
1712
1713 If this macro is not defined, then ALIGN is used.
1714
1715 The typical use of this macro is to increase alignment for string
1716 constants to be word aligned so that `strcpy' calls that copy
1717 constants can be done inline. */
1718
1719 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1720 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1721 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1722
1723 /* If defined, a C expression to compute the alignment for a static
1724 variable. TYPE is the data type, and ALIGN is the alignment that
1725 the object would ordinarily have. The value of this macro is used
1726 instead of that alignment to align the object.
1727
1728 If this macro is not defined, then ALIGN is used.
1729
1730 One use of this macro is to increase alignment of medium-size
1731 data to make it all fit in fewer cache lines. Another is to
1732 cause character arrays to be word-aligned so that `strcpy' calls
1733 that copy constants to character arrays can be done inline. */
1734
1735 #undef DATA_ALIGNMENT
1736 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1737 ((((ALIGN) < BITS_PER_WORD) \
1738 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1739 || TREE_CODE (TYPE) == UNION_TYPE \
1740 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1741
1742
1743 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1744
1745 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1746 || mips_abi == ABI_MEABI \
1747 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1748
1749 /* Define this macro if an argument declared as `char' or `short' in a
1750 prototype should actually be passed as an `int'. In addition to
1751 avoiding errors in certain cases of mismatch, it also makes for
1752 better code on certain machines. */
1753
1754 #define PROMOTE_PROTOTYPES 1
1755
1756 /* Define if operations between registers always perform the operation
1757 on the full register even if a narrower mode is specified. */
1758 #define WORD_REGISTER_OPERATIONS
1759
1760 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1761 will either zero-extend or sign-extend. The value of this macro should
1762 be the code that says which one of the two operations is implicitly
1763 done, NIL if none.
1764
1765 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1766 moves. All other referces are zero extended. */
1767 #define LOAD_EXTEND_OP(MODE) \
1768 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1769 ? SIGN_EXTEND : ZERO_EXTEND)
1770
1771 /* Define this macro if it is advisable to hold scalars in registers
1772 in a wider mode than that declared by the program. In such cases,
1773 the value is constrained to be within the bounds of the declared
1774 type, but kept valid in the wider mode. The signedness of the
1775 extension may differ from that of the type.
1776
1777 We promote any value smaller than SImode up to SImode. We don't
1778 want to promote to DImode when in 64 bit mode, because that would
1779 prevent us from using the faster SImode multiply and divide
1780 instructions. */
1781
1782 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1783 if (GET_MODE_CLASS (MODE) == MODE_INT \
1784 && GET_MODE_SIZE (MODE) < 4) \
1785 (MODE) = SImode;
1786
1787 /* Define this if function arguments should also be promoted using the above
1788 procedure. */
1789
1790 #define PROMOTE_FUNCTION_ARGS
1791
1792 /* Likewise, if the function return value is promoted. */
1793
1794 #define PROMOTE_FUNCTION_RETURN
1795 \f
1796 /* Standard register usage. */
1797
1798 /* Number of actual hardware registers.
1799 The hardware registers are assigned numbers for the compiler
1800 from 0 to just below FIRST_PSEUDO_REGISTER.
1801 All registers that the compiler knows about must be given numbers,
1802 even those that are not normally considered general registers.
1803
1804 On the Mips, we have 32 integer registers, 32 floating point
1805 registers, 8 condition code registers, and the special registers
1806 hi, lo, hilo, and rap. The 8 condition code registers are only
1807 used if mips_isa >= 4. The hilo register is only used in 64 bit
1808 mode. It represents a 64 bit value stored as two 32 bit values in
1809 the hi and lo registers; this is the result of the mult
1810 instruction. rap is a pointer to the stack where the return
1811 address reg ($31) was stored. This is needed for C++ exception
1812 handling. */
1813
1814 #define FIRST_PSEUDO_REGISTER 76
1815
1816 /* 1 for registers that have pervasive standard uses
1817 and are not available for the register allocator.
1818
1819 On the MIPS, see conventions, page D-2 */
1820
1821 #define FIXED_REGISTERS \
1822 { \
1823 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1824 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1825 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1826 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1827 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1828 }
1829
1830
1831 /* 1 for registers not available across function calls.
1832 These must include the FIXED_REGISTERS and also any
1833 registers that can be used without being saved.
1834 The latter must include the registers where values are returned
1835 and the register where structure-value addresses are passed.
1836 Aside from that, you can include as many other registers as you like. */
1837
1838 #define CALL_USED_REGISTERS \
1839 { \
1840 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1841 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1842 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1843 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1844 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1845 }
1846
1847 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1848 problem which makes CALL_USED_REGISTERS *always* include
1849 all the FIXED_REGISTERS. Until this problem has been
1850 resolved this macro can be used to overcome this situation.
1851 In particular, block_propagate() requires this list
1852 be acurate, or we can remove registers which should be live.
1853 This macro is used in regs_invalidated_by_call. */
1854
1855
1856 #define CALL_REALLY_USED_REGISTERS \
1857 { /* General registers. */ \
1858 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1859 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1860 /* Floating-point registers. */ \
1861 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1862 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1863 /* Others. */ \
1864 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1865 }
1866
1867 /* Internal macros to classify a register number as to whether it's a
1868 general purpose register, a floating point register, a
1869 multiply/divide register, or a status register. */
1870
1871 #define GP_REG_FIRST 0
1872 #define GP_REG_LAST 31
1873 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1874 #define GP_DBX_FIRST 0
1875
1876 #define FP_REG_FIRST 32
1877 #define FP_REG_LAST 63
1878 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1879 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1880
1881 #define MD_REG_FIRST 64
1882 #define MD_REG_LAST 66
1883 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1884
1885 #define ST_REG_FIRST 67
1886 #define ST_REG_LAST 74
1887 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1888
1889 #define RAP_REG_NUM 75
1890
1891 #define AT_REGNUM (GP_REG_FIRST + 1)
1892 #define HI_REGNUM (MD_REG_FIRST + 0)
1893 #define LO_REGNUM (MD_REG_FIRST + 1)
1894 #define HILO_REGNUM (MD_REG_FIRST + 2)
1895
1896 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1897 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1898 should be used instead. */
1899 #define FPSW_REGNUM ST_REG_FIRST
1900
1901 #define GP_REG_P(REGNO) \
1902 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1903 #define M16_REG_P(REGNO) \
1904 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1905 #define FP_REG_P(REGNO) \
1906 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1907 #define MD_REG_P(REGNO) \
1908 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1909 #define ST_REG_P(REGNO) \
1910 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1911
1912 /* Return number of consecutive hard regs needed starting at reg REGNO
1913 to hold something of mode MODE.
1914 This is ordinarily the length in words of a value of mode MODE
1915 but can be less for certain modes in special long registers.
1916
1917 On the MIPS, all general registers are one word long. Except on
1918 the R4000 with the FR bit set, the floating point uses register
1919 pairs, with the second register not being allocable. */
1920
1921 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1922
1923 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1924 MODE. In 32 bit mode, require that DImode and DFmode be in even
1925 registers. For DImode, this makes some of the insns easier to
1926 write, since you don't have to worry about a DImode value in
1927 registers 3 & 4, producing a result in 4 & 5.
1928
1929 To make the code simpler HARD_REGNO_MODE_OK now just references an
1930 array built in override_options. Because machmodes.h is not yet
1931 included before this file is processed, the MODE bound can't be
1932 expressed here. */
1933
1934 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1935
1936 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1937 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1938
1939 /* Value is 1 if it is a good idea to tie two pseudo registers
1940 when one has mode MODE1 and one has mode MODE2.
1941 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1942 for any hard reg, then this must be 0 for correct output. */
1943 #define MODES_TIEABLE_P(MODE1, MODE2) \
1944 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1945 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1946 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1947 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1948
1949 /* MIPS pc is not overloaded on a register. */
1950 /* #define PC_REGNUM xx */
1951
1952 /* Register to use for pushing function arguments. */
1953 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1954
1955 /* Offset from the stack pointer to the first available location. Use
1956 the default value zero. */
1957 /* #define STACK_POINTER_OFFSET 0 */
1958
1959 /* Base register for access to local variables of the function. We
1960 pretend that the frame pointer is $1, and then eliminate it to
1961 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1962 a fixed register, and will not be used for anything else. */
1963 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1964
1965 /* Temporary scratch register for use by the assembler. */
1966 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1967
1968 /* $30 is not available on the mips16, so we use $17 as the frame
1969 pointer. */
1970 #define HARD_FRAME_POINTER_REGNUM \
1971 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1972
1973 /* Value should be nonzero if functions must have frame pointers.
1974 Zero means the frame pointer need not be set up (and parms
1975 may be accessed via the stack pointer) in functions that seem suitable.
1976 This is computed in `reload', in reload1.c. */
1977 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1978
1979 /* Base register for access to arguments of the function. */
1980 #define ARG_POINTER_REGNUM GP_REG_FIRST
1981
1982 /* Fake register that holds the address on the stack of the
1983 current function's return address. */
1984 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1985
1986 /* Register in which static-chain is passed to a function. */
1987 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1988
1989 /* If the structure value address is passed in a register, then
1990 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1991 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1992
1993 /* If the structure value address is not passed in a register, define
1994 `STRUCT_VALUE' as an expression returning an RTX for the place
1995 where the address is passed. If it returns 0, the address is
1996 passed as an "invisible" first argument. */
1997 #define STRUCT_VALUE 0
1998
1999 /* Mips registers used in prologue/epilogue code when the stack frame
2000 is larger than 32K bytes. These registers must come from the
2001 scratch register set, and not used for passing and returning
2002 arguments and any other information used in the calling sequence
2003 (such as pic). Must start at 12, since t0/t3 are parameter passing
2004 registers in the 64 bit ABI. */
2005
2006 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
2007 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
2008
2009 /* Define this macro if it is as good or better to call a constant
2010 function address than to call an address kept in a register. */
2011 #define NO_FUNCTION_CSE 1
2012
2013 /* Define this macro if it is as good or better for a function to
2014 call itself with an explicit address than to call an address
2015 kept in a register. */
2016 #define NO_RECURSIVE_FUNCTION_CSE 1
2017
2018 /* The register number of the register used to address a table of
2019 static data addresses in memory. In some cases this register is
2020 defined by a processor's "application binary interface" (ABI).
2021 When this macro is defined, RTL is generated for this register
2022 once, as with the stack pointer and frame pointer registers. If
2023 this macro is not defined, it is up to the machine-dependent
2024 files to allocate such a register (if necessary). */
2025 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
2026
2027 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
2028
2029 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
2030 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
2031 isn't always called for static inline functions. */
2032 #define INIT_EXPANDERS \
2033 do { \
2034 embedded_pic_fnaddr_rtx = NULL; \
2035 mips16_gp_pseudo_rtx = NULL; \
2036 } while (0)
2037 \f
2038 /* Define the classes of registers for register constraints in the
2039 machine description. Also define ranges of constants.
2040
2041 One of the classes must always be named ALL_REGS and include all hard regs.
2042 If there is more than one class, another class must be named NO_REGS
2043 and contain no registers.
2044
2045 The name GENERAL_REGS must be the name of a class (or an alias for
2046 another name such as ALL_REGS). This is the class of registers
2047 that is allowed by "g" or "r" in a register constraint.
2048 Also, registers outside this class are allocated only when
2049 instructions express preferences for them.
2050
2051 The classes must be numbered in nondecreasing order; that is,
2052 a larger-numbered class must never be contained completely
2053 in a smaller-numbered class.
2054
2055 For any two classes, it is very desirable that there be another
2056 class that represents their union. */
2057
2058 enum reg_class
2059 {
2060 NO_REGS, /* no registers in set */
2061 M16_NA_REGS, /* mips16 regs not used to pass args */
2062 M16_REGS, /* mips16 directly accessible registers */
2063 T_REG, /* mips16 T register ($24) */
2064 M16_T_REGS, /* mips16 registers plus T register */
2065 GR_REGS, /* integer registers */
2066 FP_REGS, /* floating point registers */
2067 HI_REG, /* hi register */
2068 LO_REG, /* lo register */
2069 HILO_REG, /* hilo register pair for 64 bit mode mult */
2070 MD_REGS, /* multiply/divide registers (hi/lo) */
2071 HI_AND_GR_REGS, /* union classes */
2072 LO_AND_GR_REGS,
2073 HILO_AND_GR_REGS,
2074 HI_AND_FP_REGS,
2075 ST_REGS, /* status registers (fp status) */
2076 ALL_REGS, /* all registers */
2077 LIM_REG_CLASSES /* max value + 1 */
2078 };
2079
2080 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2081
2082 #define GENERAL_REGS GR_REGS
2083
2084 /* An initializer containing the names of the register classes as C
2085 string constants. These names are used in writing some of the
2086 debugging dumps. */
2087
2088 #define REG_CLASS_NAMES \
2089 { \
2090 "NO_REGS", \
2091 "M16_NA_REGS", \
2092 "M16_REGS", \
2093 "T_REG", \
2094 "M16_T_REGS", \
2095 "GR_REGS", \
2096 "FP_REGS", \
2097 "HI_REG", \
2098 "LO_REG", \
2099 "HILO_REG", \
2100 "MD_REGS", \
2101 "HI_AND_GR_REGS", \
2102 "LO_AND_GR_REGS", \
2103 "HILO_AND_GR_REGS", \
2104 "HI_AND_FP_REGS", \
2105 "ST_REGS", \
2106 "ALL_REGS" \
2107 }
2108
2109 /* An initializer containing the contents of the register classes,
2110 as integers which are bit masks. The Nth integer specifies the
2111 contents of class N. The way the integer MASK is interpreted is
2112 that register R is in the class if `MASK & (1 << R)' is 1.
2113
2114 When the machine has more than 32 registers, an integer does not
2115 suffice. Then the integers are replaced by sub-initializers,
2116 braced groupings containing several integers. Each
2117 sub-initializer must be suitable as an initializer for the type
2118 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2119
2120 #define REG_CLASS_CONTENTS \
2121 { \
2122 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2123 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2124 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2125 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2126 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2127 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
2128 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
2129 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
2130 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
2131 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
2132 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
2133 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
2134 { 0xffffffff, 0x00000000, 0x00000002 }, \
2135 { 0xffffffff, 0x00000000, 0x00000004 }, \
2136 { 0x00000000, 0xffffffff, 0x00000001 }, \
2137 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
2138 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
2139 }
2140
2141
2142 /* A C expression whose value is a register class containing hard
2143 register REGNO. In general there is more that one such class;
2144 choose a class which is "minimal", meaning that no smaller class
2145 also contains the register. */
2146
2147 extern const enum reg_class mips_regno_to_class[];
2148
2149 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2150
2151 /* A macro whose definition is the name of the class to which a
2152 valid base register must belong. A base register is one used in
2153 an address which is the register value plus a displacement. */
2154
2155 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2156
2157 /* A macro whose definition is the name of the class to which a
2158 valid index register must belong. An index register is one used
2159 in an address where its value is either multiplied by a scale
2160 factor or added to another register (as well as added to a
2161 displacement). */
2162
2163 #define INDEX_REG_CLASS NO_REGS
2164
2165 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2166 registers explicitly used in the rtl to be used as spill registers
2167 but prevents the compiler from extending the lifetime of these
2168 registers. */
2169
2170 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2171
2172 /* This macro is used later on in the file. */
2173 #define GR_REG_CLASS_P(CLASS) \
2174 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2175 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2176
2177 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2178 is the default value (allocate the registers in numeric order). We
2179 define it just so that we can override it for the mips16 target in
2180 ORDER_REGS_FOR_LOCAL_ALLOC. */
2181
2182 #define REG_ALLOC_ORDER \
2183 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2184 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2185 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2186 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2187 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
2188 }
2189
2190 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2191 to be rearranged based on a particular function. On the mips16, we
2192 want to allocate $24 (T_REG) before other registers for
2193 instructions for which it is possible. */
2194
2195 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2196
2197 /* REGISTER AND CONSTANT CLASSES */
2198
2199 /* Get reg_class from a letter such as appears in the machine
2200 description.
2201
2202 DEFINED REGISTER CLASSES:
2203
2204 'd' General (aka integer) registers
2205 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2206 'y' General registers (in both mips16 and non mips16 mode)
2207 'e' mips16 non argument registers (M16_NA_REGS)
2208 't' mips16 temporary register ($24)
2209 'f' Floating point registers
2210 'h' Hi register
2211 'l' Lo register
2212 'x' Multiply/divide registers
2213 'a' HILO_REG
2214 'z' FP Status register
2215 'b' All registers */
2216
2217 extern enum reg_class mips_char_to_class[256];
2218
2219 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2220
2221 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2222 string can be used to stand for particular ranges of immediate
2223 operands. This macro defines what the ranges are. C is the
2224 letter, and VALUE is a constant value. Return 1 if VALUE is
2225 in the range specified by C. */
2226
2227 /* For MIPS:
2228
2229 `I' is used for the range of constants an arithmetic insn can
2230 actually contain (16 bits signed integers).
2231
2232 `J' is used for the range which is just zero (ie, $r0).
2233
2234 `K' is used for the range of constants a logical insn can actually
2235 contain (16 bit zero-extended integers).
2236
2237 `L' is used for the range of constants that be loaded with lui
2238 (ie, the bottom 16 bits are zero).
2239
2240 `M' is used for the range of constants that take two words to load
2241 (ie, not matched by `I', `K', and `L').
2242
2243 `N' is used for negative 16 bit constants other than -65536.
2244
2245 `O' is a 15 bit signed integer.
2246
2247 `P' is used for positive 16 bit constants. */
2248
2249 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2250 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2251
2252 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2253 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2254 : (C) == 'J' ? ((VALUE) == 0) \
2255 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2256 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2257 && (((VALUE) & ~2147483647) == 0 \
2258 || ((VALUE) & ~2147483647) == ~2147483647)) \
2259 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2260 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2261 && (((VALUE) & 0x0000ffff) != 0 \
2262 || (((VALUE) & ~2147483647) != 0 \
2263 && ((VALUE) & ~2147483647) != ~2147483647))) \
2264 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2265 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2266 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2267 : 0)
2268
2269 /* Similar, but for floating constants, and defining letters G and H.
2270 Here VALUE is the CONST_DOUBLE rtx itself. */
2271
2272 /* For Mips
2273
2274 'G' : Floating point 0 */
2275
2276 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2277 ((C) == 'G' \
2278 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2279
2280 /* Letters in the range `Q' through `U' may be defined in a
2281 machine-dependent fashion to stand for arbitrary operand types.
2282 The machine description macro `EXTRA_CONSTRAINT' is passed the
2283 operand as its first argument and the constraint letter as its
2284 second operand.
2285
2286 `Q' is for mips16 GP relative constants
2287 `R' is for memory references which take 1 word for the instruction.
2288 `S' is for references to extern items which are PIC for OSF/rose.
2289 `T' is for memory addresses that can be used to load two words. */
2290
2291 #define EXTRA_CONSTRAINT(OP,CODE) \
2292 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2293 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2294 && mips16_gp_offset_p (OP)) \
2295 : (GET_CODE (OP) != MEM) ? FALSE \
2296 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2297 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2298 && HALF_PIC_ADDRESS_P (OP)) \
2299 : FALSE)
2300
2301 /* Given an rtx X being reloaded into a reg required to be
2302 in class CLASS, return the class of reg to actually use.
2303 In general this is just CLASS; but on some machines
2304 in some cases it is preferable to use a more restrictive class. */
2305
2306 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2307 ((CLASS) != ALL_REGS \
2308 ? (! TARGET_MIPS16 \
2309 ? (CLASS) \
2310 : ((CLASS) != GR_REGS \
2311 ? (CLASS) \
2312 : M16_REGS)) \
2313 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2314 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2315 ? (TARGET_SOFT_FLOAT \
2316 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2317 : FP_REGS) \
2318 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2319 || GET_MODE (X) == VOIDmode) \
2320 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2321 : (CLASS))))
2322
2323 /* Certain machines have the property that some registers cannot be
2324 copied to some other registers without using memory. Define this
2325 macro on those machines to be a C expression that is non-zero if
2326 objects of mode MODE in registers of CLASS1 can only be copied to
2327 registers of class CLASS2 by storing a register of CLASS1 into
2328 memory and loading that memory location into a register of CLASS2.
2329
2330 Do not define this macro if its value would always be zero. */
2331
2332 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2333 ((!TARGET_DEBUG_H_MODE \
2334 && GET_MODE_CLASS (MODE) == MODE_INT \
2335 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2336 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2337 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2338 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2339 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2340
2341 /* The HI and LO registers can only be reloaded via the general
2342 registers. Condition code registers can only be loaded to the
2343 general registers, and from the floating point registers. */
2344
2345 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2346 mips_secondary_reload_class (CLASS, MODE, X, 1)
2347 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2348 mips_secondary_reload_class (CLASS, MODE, X, 0)
2349
2350 /* Return the maximum number of consecutive registers
2351 needed to represent mode MODE in a register of class CLASS. */
2352
2353 #define CLASS_UNITS(mode, size) \
2354 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2355
2356 #define CLASS_MAX_NREGS(CLASS, MODE) \
2357 ((CLASS) == FP_REGS \
2358 ? (TARGET_FLOAT64 \
2359 ? CLASS_UNITS (MODE, 8) \
2360 : 2 * CLASS_UNITS (MODE, 8)) \
2361 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2362
2363 /* If defined, gives a class of registers that cannot be used as the
2364 operand of a SUBREG that changes the mode of the object illegally.
2365 When FP regs are larger than integer regs... Er, anyone remember what
2366 goes wrong?
2367
2368 In little-endian mode, the hi-lo registers are numbered backwards,
2369 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2370 word as intended. */
2371
2372 #define CLASS_CANNOT_CHANGE_MODE \
2373 (TARGET_BIG_ENDIAN \
2374 ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \
2375 : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG))
2376
2377 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2378
2379 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2380 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2381 \f
2382 /* Stack layout; function entry, exit and calling. */
2383
2384 /* Define this if pushing a word on the stack
2385 makes the stack pointer a smaller address. */
2386 #define STACK_GROWS_DOWNWARD
2387
2388 /* Define this if the nominal address of the stack frame
2389 is at the high-address end of the local variables;
2390 that is, each additional local variable allocated
2391 goes at a more negative offset in the frame. */
2392 /* #define FRAME_GROWS_DOWNWARD */
2393
2394 /* Offset within stack frame to start allocating local variables at.
2395 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2396 first local allocated. Otherwise, it is the offset to the BEGINNING
2397 of the first local allocated. */
2398 #define STARTING_FRAME_OFFSET \
2399 (current_function_outgoing_args_size \
2400 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2401
2402 /* Offset from the stack pointer register to an item dynamically
2403 allocated on the stack, e.g., by `alloca'.
2404
2405 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2406 length of the outgoing arguments. The default is correct for most
2407 machines. See `function.c' for details.
2408
2409 The MIPS ABI states that functions which dynamically allocate the
2410 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2411 we are trying to create a second frame pointer to the function, so
2412 allocate some stack space to make it happy.
2413
2414 However, the linker currently complains about linking any code that
2415 dynamically allocates stack space, and there seems to be a bug in
2416 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2417
2418 #if 0
2419 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2420 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2421 ? 4*UNITS_PER_WORD \
2422 : current_function_outgoing_args_size)
2423 #endif
2424
2425 /* The return address for the current frame is in r31 is this is a leaf
2426 function. Otherwise, it is on the stack. It is at a variable offset
2427 from sp/fp/ap, so we define a fake hard register rap which is a
2428 poiner to the return address on the stack. This always gets eliminated
2429 during reload to be either the frame pointer or the stack pointer plus
2430 an offset. */
2431
2432 /* ??? This definition fails for leaf functions. There is currently no
2433 general solution for this problem. */
2434
2435 /* ??? There appears to be no way to get the return address of any previous
2436 frame except by disassembling instructions in the prologue/epilogue.
2437 So currently we support only the current frame. */
2438
2439 #define RETURN_ADDR_RTX(count, frame) \
2440 ((count == 0) \
2441 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2442 : (rtx) 0)
2443
2444 /* Structure to be filled in by compute_frame_size with register
2445 save masks, and offsets for the current function. */
2446
2447 struct mips_frame_info
2448 {
2449 long total_size; /* # bytes that the entire frame takes up */
2450 long var_size; /* # bytes that variables take up */
2451 long args_size; /* # bytes that outgoing arguments take up */
2452 long extra_size; /* # bytes of extra gunk */
2453 int gp_reg_size; /* # bytes needed to store gp regs */
2454 int fp_reg_size; /* # bytes needed to store fp regs */
2455 long mask; /* mask of saved gp registers */
2456 long fmask; /* mask of saved fp registers */
2457 long gp_save_offset; /* offset from vfp to store gp registers */
2458 long fp_save_offset; /* offset from vfp to store fp registers */
2459 long gp_sp_offset; /* offset from new sp to store gp registers */
2460 long fp_sp_offset; /* offset from new sp to store fp registers */
2461 int initialized; /* != 0 if frame size already calculated */
2462 int num_gp; /* number of gp registers saved */
2463 int num_fp; /* number of fp registers saved */
2464 long insns_len; /* length of insns; mips16 only */
2465 };
2466
2467 extern struct mips_frame_info current_frame_info;
2468
2469 /* If defined, this macro specifies a table of register pairs used to
2470 eliminate unneeded registers that point into the stack frame. If
2471 it is not defined, the only elimination attempted by the compiler
2472 is to replace references to the frame pointer with references to
2473 the stack pointer.
2474
2475 The definition of this macro is a list of structure
2476 initializations, each of which specifies an original and
2477 replacement register.
2478
2479 On some machines, the position of the argument pointer is not
2480 known until the compilation is completed. In such a case, a
2481 separate hard register must be used for the argument pointer.
2482 This register can be eliminated by replacing it with either the
2483 frame pointer or the argument pointer, depending on whether or not
2484 the frame pointer has been eliminated.
2485
2486 In this case, you might specify:
2487 #define ELIMINABLE_REGS \
2488 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2489 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2490 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2491
2492 Note that the elimination of the argument pointer with the stack
2493 pointer is specified first since that is the preferred elimination.
2494
2495 The eliminations to $17 are only used on the mips16. See the
2496 definition of HARD_FRAME_POINTER_REGNUM. */
2497
2498 #define ELIMINABLE_REGS \
2499 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2500 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2501 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2502 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2503 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2504 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2505 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2506 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2507 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2508 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2509
2510 /* A C expression that returns non-zero if the compiler is allowed to
2511 try to replace register number FROM-REG with register number
2512 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2513 defined, and will usually be the constant 1, since most of the
2514 cases preventing register elimination are things that the compiler
2515 already knows about.
2516
2517 When not in mips16 and mips64, we can always eliminate to the
2518 frame pointer. We can eliminate to the stack pointer unless
2519 a frame pointer is needed. In mips16 mode, we need a frame
2520 pointer for a large frame; otherwise, reload may be unable
2521 to compute the address of a local variable, since there is
2522 no way to add a large constant to the stack pointer
2523 without using a temporary register.
2524
2525 In mips16, for some instructions (eg lwu), we can't eliminate the
2526 frame pointer for the stack pointer. These instructions are
2527 only generated in TARGET_64BIT mode.
2528 */
2529
2530 #define CAN_ELIMINATE(FROM, TO) \
2531 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2532 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2533 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2534 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2535 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2536 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2537 && (! TARGET_MIPS16 \
2538 || compute_frame_size (get_frame_size ()) < 32768)))))
2539
2540 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2541 specifies the initial difference between the specified pair of
2542 registers. This macro must be defined if `ELIMINABLE_REGS' is
2543 defined. */
2544
2545 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2546 { compute_frame_size (get_frame_size ()); \
2547 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2548 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2549 (OFFSET) = - current_function_outgoing_args_size; \
2550 else if ((FROM) == FRAME_POINTER_REGNUM) \
2551 (OFFSET) = 0; \
2552 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2553 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2554 (OFFSET) = (current_frame_info.total_size \
2555 - current_function_outgoing_args_size \
2556 - ((mips_abi != ABI_32 \
2557 && mips_abi != ABI_O64 \
2558 && mips_abi != ABI_EABI) \
2559 ? current_function_pretend_args_size \
2560 : 0)); \
2561 else if ((FROM) == ARG_POINTER_REGNUM) \
2562 (OFFSET) = (current_frame_info.total_size \
2563 - ((mips_abi != ABI_32 \
2564 && mips_abi != ABI_O64 \
2565 && mips_abi != ABI_EABI) \
2566 ? current_function_pretend_args_size \
2567 : 0)); \
2568 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2569 so we must add 4 bytes to the offset to get the right value. */ \
2570 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2571 { \
2572 if (leaf_function_p ()) \
2573 (OFFSET) = 0; \
2574 else (OFFSET) = current_frame_info.gp_sp_offset \
2575 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2576 * (BYTES_BIG_ENDIAN != 0)); \
2577 } \
2578 else \
2579 abort(); \
2580 }
2581
2582 /* If we generate an insn to push BYTES bytes,
2583 this says how many the stack pointer really advances by.
2584 On the VAX, sp@- in a byte insn really pushes a word. */
2585
2586 /* #define PUSH_ROUNDING(BYTES) 0 */
2587
2588 /* If defined, the maximum amount of space required for outgoing
2589 arguments will be computed and placed into the variable
2590 `current_function_outgoing_args_size'. No space will be pushed
2591 onto the stack for each call; instead, the function prologue
2592 should increase the stack frame size by this amount.
2593
2594 It is not proper to define both `PUSH_ROUNDING' and
2595 `ACCUMULATE_OUTGOING_ARGS'. */
2596 #define ACCUMULATE_OUTGOING_ARGS 1
2597
2598 /* Offset from the argument pointer register to the first argument's
2599 address. On some machines it may depend on the data type of the
2600 function.
2601
2602 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2603 the first argument's address.
2604
2605 On the MIPS, we must skip the first argument position if we are
2606 returning a structure or a union, to account for its address being
2607 passed in $4. However, at the current time, this produces a compiler
2608 that can't bootstrap, so comment it out for now. */
2609
2610 #if 0
2611 #define FIRST_PARM_OFFSET(FNDECL) \
2612 (FNDECL != 0 \
2613 && TREE_TYPE (FNDECL) != 0 \
2614 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2615 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2616 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2617 ? UNITS_PER_WORD \
2618 : 0)
2619 #else
2620 #define FIRST_PARM_OFFSET(FNDECL) 0
2621 #endif
2622
2623 /* When a parameter is passed in a register, stack space is still
2624 allocated for it. For the MIPS, stack space must be allocated, cf
2625 Asm Lang Prog Guide page 7-8.
2626
2627 BEWARE that some space is also allocated for non existing arguments
2628 in register. In case an argument list is of form GF used registers
2629 are a0 (a2,a3), but we should push over a1... */
2630
2631 #define REG_PARM_STACK_SPACE(FNDECL) \
2632 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2633
2634 /* Define this if it is the responsibility of the caller to
2635 allocate the area reserved for arguments passed in registers.
2636 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2637 of this macro is to determine whether the space is included in
2638 `current_function_outgoing_args_size'. */
2639 #define OUTGOING_REG_PARM_STACK_SPACE
2640
2641 /* Align stack frames on 64 bits (Double Word ). */
2642 #ifndef STACK_BOUNDARY
2643 #define STACK_BOUNDARY 64
2644 #endif
2645
2646 /* Make sure 4 words are always allocated on the stack. */
2647
2648 #ifndef STACK_ARGS_ADJUST
2649 #define STACK_ARGS_ADJUST(SIZE) \
2650 { \
2651 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2652 SIZE.constant = 4 * UNITS_PER_WORD; \
2653 }
2654 #endif
2655
2656 \f
2657 /* A C expression that should indicate the number of bytes of its
2658 own arguments that a function pops on returning, or 0
2659 if the function pops no arguments and the caller must therefore
2660 pop them all after the function returns.
2661
2662 FUNDECL is the declaration node of the function (as a tree).
2663
2664 FUNTYPE is a C variable whose value is a tree node that
2665 describes the function in question. Normally it is a node of
2666 type `FUNCTION_TYPE' that describes the data type of the function.
2667 From this it is possible to obtain the data types of the value
2668 and arguments (if known).
2669
2670 When a call to a library function is being considered, FUNTYPE
2671 will contain an identifier node for the library function. Thus,
2672 if you need to distinguish among various library functions, you
2673 can do so by their names. Note that "library function" in this
2674 context means a function used to perform arithmetic, whose name
2675 is known specially in the compiler and was not mentioned in the
2676 C code being compiled.
2677
2678 STACK-SIZE is the number of bytes of arguments passed on the
2679 stack. If a variable number of bytes is passed, it is zero, and
2680 argument popping will always be the responsibility of the
2681 calling function. */
2682
2683 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2684
2685
2686 /* Symbolic macros for the registers used to return integer and floating
2687 point values. */
2688
2689 #define GP_RETURN (GP_REG_FIRST + 2)
2690 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2691
2692 /* Symbolic macros for the first/last argument registers. */
2693
2694 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2695 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2696 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2697 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2698
2699 #define MAX_ARGS_IN_REGISTERS 4
2700
2701 /* Define how to find the value returned by a library function
2702 assuming the value has mode MODE. Because we define
2703 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2704 PROMOTE_MODE does. */
2705
2706 #define LIBCALL_VALUE(MODE) \
2707 gen_rtx (REG, \
2708 ((GET_MODE_CLASS (MODE) != MODE_INT \
2709 || GET_MODE_SIZE (MODE) >= 4) \
2710 ? (MODE) \
2711 : SImode), \
2712 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2713 && (! TARGET_SINGLE_FLOAT \
2714 || GET_MODE_SIZE (MODE) <= 4)) \
2715 ? FP_RETURN \
2716 : GP_RETURN))
2717
2718 /* Define how to find the value returned by a function.
2719 VALTYPE is the data type of the value (as a tree).
2720 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2721 otherwise, FUNC is 0. */
2722
2723 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2724
2725
2726 /* 1 if N is a possible register number for a function value.
2727 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2728 Currently, R2 and F0 are only implemented here (C has no complex type) */
2729
2730 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2731
2732 /* 1 if N is a possible register number for function argument passing.
2733 We have no FP argument registers when soft-float. When FP registers
2734 are 32 bits, we can't directly reference the odd numbered ones. */
2735
2736 #define FUNCTION_ARG_REGNO_P(N) \
2737 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2738 || ((! TARGET_SOFT_FLOAT \
2739 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2740 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2741 && ! fixed_regs[N]))
2742
2743 /* A C expression which can inhibit the returning of certain function
2744 values in registers, based on the type of value. A nonzero value says
2745 to return the function value in memory, just as large structures are
2746 always returned. Here TYPE will be a C expression of type
2747 `tree', representing the data type of the value.
2748
2749 Note that values of mode `BLKmode' must be explicitly
2750 handled by this macro. Also, the option `-fpcc-struct-return'
2751 takes effect regardless of this macro. On most systems, it is
2752 possible to leave the macro undefined; this causes a default
2753 definition to be used, whose value is the constant 1 for BLKmode
2754 values, and 0 otherwise.
2755
2756 GCC normally converts 1 byte structures into chars, 2 byte
2757 structs into shorts, and 4 byte structs into ints, and returns
2758 them this way. Defining the following macro overrides this,
2759 to give us MIPS cc compatibility. */
2760
2761 #define RETURN_IN_MEMORY(TYPE) \
2762 (TYPE_MODE (TYPE) == BLKmode)
2763 \f
2764 /* A code distinguishing the floating point format of the target
2765 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2766 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2767
2768 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2769
2770 \f
2771 /* Define a data type for recording info about an argument list
2772 during the scan of that argument list. This data type should
2773 hold all necessary information about the function itself
2774 and about the args processed so far, enough to enable macros
2775 such as FUNCTION_ARG to determine where the next arg should go.
2776
2777 On the mips16, we need to keep track of which floating point
2778 arguments were passed in general registers, but would have been
2779 passed in the FP regs if this were a 32 bit function, so that we
2780 can move them to the FP regs if we wind up calling a 32 bit
2781 function. We record this information in fp_code, encoded in base
2782 four. A zero digit means no floating point argument, a one digit
2783 means an SFmode argument, and a two digit means a DFmode argument,
2784 and a three digit is not used. The low order digit is the first
2785 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2786 an SFmode argument. ??? A more sophisticated approach will be
2787 needed if MIPS_ABI != ABI_32. */
2788
2789 typedef struct mips_args {
2790 int gp_reg_found; /* whether a gp register was found yet */
2791 unsigned int arg_number; /* argument number */
2792 unsigned int arg_words; /* # total words the arguments take */
2793 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2794 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2795 int fp_code; /* Mode of FP arguments (mips16) */
2796 unsigned int num_adjusts; /* number of adjustments made */
2797 /* Adjustments made to args pass in regs. */
2798 /* ??? The size is doubled to work around a
2799 bug in the code that sets the adjustments
2800 in function_arg. */
2801 int prototype; /* True if the function has a prototype. */
2802 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2803 } CUMULATIVE_ARGS;
2804
2805 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2806 for a call to a function whose data type is FNTYPE.
2807 For a library call, FNTYPE is 0.
2808
2809 */
2810
2811 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2812 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2813
2814 /* Update the data in CUM to advance over an argument
2815 of mode MODE and data type TYPE.
2816 (TYPE is null for libcalls where that information may not be available.) */
2817
2818 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2819 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2820
2821 /* Determine where to put an argument to a function.
2822 Value is zero to push the argument on the stack,
2823 or a hard register in which to store the argument.
2824
2825 MODE is the argument's machine mode.
2826 TYPE is the data type of the argument (as a tree).
2827 This is null for libcalls where that information may
2828 not be available.
2829 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2830 the preceding args and about the function being called.
2831 NAMED is nonzero if this argument is a named parameter
2832 (otherwise it is an extra parameter matching an ellipsis). */
2833
2834 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2835 function_arg( &CUM, MODE, TYPE, NAMED)
2836
2837 /* For an arg passed partly in registers and partly in memory,
2838 this is the number of registers used.
2839 For args passed entirely in registers or entirely in memory, zero. */
2840
2841 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2842 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2843
2844 /* If defined, a C expression that gives the alignment boundary, in
2845 bits, of an argument with the specified mode and type. If it is
2846 not defined, `PARM_BOUNDARY' is used for all arguments. */
2847
2848 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2849 (((TYPE) != 0) \
2850 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2851 ? PARM_BOUNDARY \
2852 : TYPE_ALIGN(TYPE)) \
2853 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2854 ? PARM_BOUNDARY \
2855 : GET_MODE_ALIGNMENT(MODE)))
2856
2857 \f
2858 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2859
2860 #define MUST_SAVE_REGISTER(regno) \
2861 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2862 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2863 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2864
2865 /* ALIGN FRAMES on double word boundaries */
2866 #ifndef MIPS_STACK_ALIGN
2867 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2868 #endif
2869
2870 \f
2871 /* Define the `__builtin_va_list' type for the ABI. */
2872 #define BUILD_VA_LIST_TYPE(VALIST) \
2873 (VALIST) = mips_build_va_list ()
2874
2875 /* Implement `va_start' for varargs and stdarg. */
2876 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2877 mips_va_start (stdarg, valist, nextarg)
2878
2879 /* Implement `va_arg'. */
2880 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2881 mips_va_arg (valist, type)
2882 \f
2883 /* Output assembler code to FILE to increment profiler label # LABELNO
2884 for profiling a function entry. */
2885
2886 #define FUNCTION_PROFILER(FILE, LABELNO) \
2887 { \
2888 if (TARGET_MIPS16) \
2889 sorry ("mips16 function profiling"); \
2890 fprintf (FILE, "\t.set\tnoreorder\n"); \
2891 fprintf (FILE, "\t.set\tnoat\n"); \
2892 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2893 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2894 fprintf (FILE, "\tjal\t_mcount\n"); \
2895 fprintf (FILE, \
2896 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2897 TARGET_64BIT ? "dsubu" : "subu", \
2898 reg_names[STACK_POINTER_REGNUM], \
2899 reg_names[STACK_POINTER_REGNUM], \
2900 Pmode == DImode ? 16 : 8); \
2901 fprintf (FILE, "\t.set\treorder\n"); \
2902 fprintf (FILE, "\t.set\tat\n"); \
2903 }
2904
2905 /* Define this macro if the code for function profiling should come
2906 before the function prologue. Normally, the profiling code comes
2907 after. */
2908
2909 /* #define PROFILE_BEFORE_PROLOGUE */
2910
2911 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2912 the stack pointer does not matter. The value is tested only in
2913 functions that have frame pointers.
2914 No definition is equivalent to always zero. */
2915
2916 #define EXIT_IGNORE_STACK 1
2917
2918 \f
2919 /* A C statement to output, on the stream FILE, assembler code for a
2920 block of data that contains the constant parts of a trampoline.
2921 This code should not include a label--the label is taken care of
2922 automatically. */
2923
2924 #define TRAMPOLINE_TEMPLATE(STREAM) \
2925 { \
2926 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2927 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2928 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2929 if (Pmode == DImode) \
2930 { \
2931 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2932 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2933 } \
2934 else \
2935 { \
2936 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2937 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2938 } \
2939 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2940 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2941 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2942 if (Pmode == DImode) \
2943 { \
2944 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2945 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2946 } \
2947 else \
2948 { \
2949 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2950 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2951 } \
2952 }
2953
2954 /* A C expression for the size in bytes of the trampoline, as an
2955 integer. */
2956
2957 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2958
2959 /* Alignment required for trampolines, in bits. */
2960
2961 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2962
2963 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2964 program and data caches. */
2965
2966 #ifndef CACHE_FLUSH_FUNC
2967 #define CACHE_FLUSH_FUNC "_flush_cache"
2968 #endif
2969
2970 /* A C statement to initialize the variable parts of a trampoline.
2971 ADDR is an RTX for the address of the trampoline; FNADDR is an
2972 RTX for the address of the nested function; STATIC_CHAIN is an
2973 RTX for the static chain value that should be passed to the
2974 function when it is called. */
2975
2976 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2977 { \
2978 rtx addr = ADDR; \
2979 if (Pmode == DImode) \
2980 { \
2981 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2982 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2983 } \
2984 else \
2985 { \
2986 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2987 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2988 } \
2989 \
2990 /* Flush both caches. We need to flush the data cache in case \
2991 the system has a write-back cache. */ \
2992 /* ??? Should check the return value for errors. */ \
2993 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2994 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2995 0, VOIDmode, 3, addr, Pmode, \
2996 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2997 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2998 }
2999 \f
3000 /* Addressing modes, and classification of registers for them. */
3001
3002 /* #define HAVE_POST_INCREMENT 0 */
3003 /* #define HAVE_POST_DECREMENT 0 */
3004
3005 /* #define HAVE_PRE_DECREMENT 0 */
3006 /* #define HAVE_PRE_INCREMENT 0 */
3007
3008 /* These assume that REGNO is a hard or pseudo reg number.
3009 They give nonzero only if REGNO is a hard reg of the suitable class
3010 or a pseudo reg currently allocated to a suitable hard reg.
3011 These definitions are NOT overridden anywhere. */
3012
3013 #define BASE_REG_P(regno, mode) \
3014 (TARGET_MIPS16 \
3015 ? (M16_REG_P (regno) \
3016 || (regno) == FRAME_POINTER_REGNUM \
3017 || (regno) == ARG_POINTER_REGNUM \
3018 || ((regno) == STACK_POINTER_REGNUM \
3019 && (GET_MODE_SIZE (mode) == 4 \
3020 || GET_MODE_SIZE (mode) == 8))) \
3021 : GP_REG_P (regno))
3022
3023 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3024 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3025 (mode))
3026
3027 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3028 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3029
3030 #define REGNO_OK_FOR_INDEX_P(regno) 0
3031 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3032 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3033
3034 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3035 and check its validity for a certain class.
3036 We have two alternate definitions for each of them.
3037 The usual definition accepts all pseudo regs; the other rejects them all.
3038 The symbol REG_OK_STRICT causes the latter definition to be used.
3039
3040 Most source files want to accept pseudo regs in the hope that
3041 they will get allocated to the class that the insn wants them to be in.
3042 Some source files that are used after register allocation
3043 need to be strict. */
3044
3045 #ifndef REG_OK_STRICT
3046 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3047 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3048 #else
3049 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3050 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3051 #endif
3052
3053 #define REG_OK_FOR_INDEX_P(X) 0
3054
3055 \f
3056 /* Maximum number of registers that can appear in a valid memory address. */
3057
3058 #define MAX_REGS_PER_ADDRESS 1
3059
3060 /* A C compound statement with a conditional `goto LABEL;' executed
3061 if X (an RTX) is a legitimate memory address on the target
3062 machine for a memory operand of mode MODE.
3063
3064 It usually pays to define several simpler macros to serve as
3065 subroutines for this one. Otherwise it may be too complicated
3066 to understand.
3067
3068 This macro must exist in two variants: a strict variant and a
3069 non-strict one. The strict variant is used in the reload pass.
3070 It must be defined so that any pseudo-register that has not been
3071 allocated a hard register is considered a memory reference. In
3072 contexts where some kind of register is required, a
3073 pseudo-register with no hard register must be rejected.
3074
3075 The non-strict variant is used in other passes. It must be
3076 defined to accept all pseudo-registers in every context where
3077 some kind of register is required.
3078
3079 Compiler source files that want to use the strict variant of
3080 this macro define the macro `REG_OK_STRICT'. You should use an
3081 `#ifdef REG_OK_STRICT' conditional to define the strict variant
3082 in that case and the non-strict variant otherwise.
3083
3084 Typically among the subroutines used to define
3085 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
3086 acceptable registers for various purposes (one for base
3087 registers, one for index registers, and so on). Then only these
3088 subroutine macros need have two variants; the higher levels of
3089 macros may be the same whether strict or not.
3090
3091 Normally, constant addresses which are the sum of a `symbol_ref'
3092 and an integer are stored inside a `const' RTX to mark them as
3093 constant. Therefore, there is no need to recognize such sums
3094 specifically as legitimate addresses. Normally you would simply
3095 recognize any `const' as legitimate.
3096
3097 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
3098 constant sums that are not marked with `const'. It assumes
3099 that a naked `plus' indicates indexing. If so, then you *must*
3100 reject such naked constant sums as illegitimate addresses, so
3101 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
3102
3103 On some machines, whether a symbolic address is legitimate
3104 depends on the section that the address refers to. On these
3105 machines, define the macro `ENCODE_SECTION_INFO' to store the
3106 information into the `symbol_ref', and then check for it here.
3107 When you see a `const', you will have to look inside it to find
3108 the `symbol_ref' in order to determine the section. */
3109
3110 #if 1
3111 #define GO_PRINTF(x) fprintf(stderr, (x))
3112 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3113 #define GO_DEBUG_RTX(x) debug_rtx(x)
3114
3115 #else
3116 #define GO_PRINTF(x)
3117 #define GO_PRINTF2(x,y)
3118 #define GO_DEBUG_RTX(x)
3119 #endif
3120
3121 #ifdef REG_OK_STRICT
3122 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3123 { \
3124 if (mips_legitimate_address_p (MODE, X, 1)) \
3125 goto ADDR; \
3126 }
3127 #else
3128 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3129 { \
3130 if (mips_legitimate_address_p (MODE, X, 0)) \
3131 goto ADDR; \
3132 }
3133 #endif
3134
3135 /* A C expression that is 1 if the RTX X is a constant which is a
3136 valid address. This is defined to be the same as `CONSTANT_P (X)',
3137 but rejecting CONST_DOUBLE. */
3138 /* When pic, we must reject addresses of the form symbol+large int.
3139 This is because an instruction `sw $4,s+70000' needs to be converted
3140 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3141 assembler would use $at as a temp to load in the large offset. In this
3142 case $at is already in use. We convert such problem addresses to
3143 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3144 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
3145 #define CONSTANT_ADDRESS_P(X) \
3146 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3147 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3148 || (GET_CODE (X) == CONST \
3149 && ! (flag_pic && pic_address_needs_scratch (X)) \
3150 && (mips_abi == ABI_32 \
3151 || mips_abi == ABI_O64 \
3152 || mips_abi == ABI_EABI))) \
3153 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
3154
3155 /* Define this, so that when PIC, reload won't try to reload invalid
3156 addresses which require two reload registers. */
3157
3158 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3159
3160 /* Nonzero if the constant value X is a legitimate general operand.
3161 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3162
3163 At present, GAS doesn't understand li.[sd], so don't allow it
3164 to be generated at present. Also, the MIPS assembler does not
3165 grok li.d Infinity. */
3166
3167 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3168 Note that the Irix 6 assembler problem may already be fixed.
3169 Note also that the GET_CODE (X) == CONST test catches the mips16
3170 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3171 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3172 ABI_64 to work together, we'll need to fix this. */
3173 #define LEGITIMATE_CONSTANT_P(X) \
3174 ((GET_CODE (X) != CONST_DOUBLE \
3175 || mips_const_double_ok (X, GET_MODE (X))) \
3176 && ! (GET_CODE (X) == CONST \
3177 && ! TARGET_GAS \
3178 && (mips_abi == ABI_N32 \
3179 || mips_abi == ABI_64)) \
3180 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3181
3182 /* A C compound statement that attempts to replace X with a valid
3183 memory address for an operand of mode MODE. WIN will be a C
3184 statement label elsewhere in the code; the macro definition may
3185 use
3186
3187 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3188
3189 to avoid further processing if the address has become legitimate.
3190
3191 X will always be the result of a call to `break_out_memory_refs',
3192 and OLDX will be the operand that was given to that function to
3193 produce X.
3194
3195 The code generated by this macro should not alter the
3196 substructure of X. If it transforms X into a more legitimate
3197 form, it should assign X (which will always be a C variable) a
3198 new value.
3199
3200 It is not necessary for this macro to come up with a legitimate
3201 address. The compiler has standard ways of doing so in all
3202 cases. In fact, it is safe for this macro to do nothing. But
3203 often a machine-dependent strategy can generate better code.
3204
3205 For the MIPS, transform:
3206
3207 memory(X + <large int>)
3208
3209 into:
3210
3211 Y = <large int> & ~0x7fff;
3212 Z = X + Y
3213 memory (Z + (<large int> & 0x7fff));
3214
3215 This is for CSE to find several similar references, and only use one Z.
3216
3217 When PIC, convert addresses of the form memory (symbol+large int) to
3218 memory (reg+large int). */
3219
3220
3221 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3222 { \
3223 register rtx xinsn = (X); \
3224 \
3225 if (TARGET_DEBUG_B_MODE) \
3226 { \
3227 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3228 GO_DEBUG_RTX (xinsn); \
3229 } \
3230 \
3231 if (mips_split_addresses && mips_check_split (X, MODE)) \
3232 { \
3233 /* ??? Is this ever executed? */ \
3234 X = gen_rtx_LO_SUM (Pmode, \
3235 copy_to_mode_reg (Pmode, \
3236 gen_rtx (HIGH, Pmode, X)), \
3237 X); \
3238 goto WIN; \
3239 } \
3240 \
3241 if (GET_CODE (xinsn) == CONST \
3242 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3243 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3244 || (mips_abi != ABI_32 \
3245 && mips_abi != ABI_O64 \
3246 && mips_abi != ABI_EABI))) \
3247 { \
3248 rtx ptr_reg = gen_reg_rtx (Pmode); \
3249 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3250 \
3251 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3252 \
3253 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3254 if (SMALL_INT (constant)) \
3255 goto WIN; \
3256 /* Otherwise we fall through so the code below will fix the \
3257 constant. */ \
3258 xinsn = X; \
3259 } \
3260 \
3261 if (GET_CODE (xinsn) == PLUS) \
3262 { \
3263 register rtx xplus0 = XEXP (xinsn, 0); \
3264 register rtx xplus1 = XEXP (xinsn, 1); \
3265 register enum rtx_code code0 = GET_CODE (xplus0); \
3266 register enum rtx_code code1 = GET_CODE (xplus1); \
3267 \
3268 if (code0 != REG && code1 == REG) \
3269 { \
3270 xplus0 = XEXP (xinsn, 1); \
3271 xplus1 = XEXP (xinsn, 0); \
3272 code0 = GET_CODE (xplus0); \
3273 code1 = GET_CODE (xplus1); \
3274 } \
3275 \
3276 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3277 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3278 { \
3279 rtx int_reg = gen_reg_rtx (Pmode); \
3280 rtx ptr_reg = gen_reg_rtx (Pmode); \
3281 \
3282 emit_move_insn (int_reg, \
3283 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3284 \
3285 emit_insn (gen_rtx_SET (VOIDmode, \
3286 ptr_reg, \
3287 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3288 \
3289 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3290 goto WIN; \
3291 } \
3292 } \
3293 \
3294 if (TARGET_DEBUG_B_MODE) \
3295 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3296 }
3297
3298
3299 /* A C statement or compound statement with a conditional `goto
3300 LABEL;' executed if memory address X (an RTX) can have different
3301 meanings depending on the machine mode of the memory reference it
3302 is used for.
3303
3304 Autoincrement and autodecrement addresses typically have
3305 mode-dependent effects because the amount of the increment or
3306 decrement is the size of the operand being addressed. Some
3307 machines have other mode-dependent addresses. Many RISC machines
3308 have no mode-dependent addresses.
3309
3310 You may assume that ADDR is a valid address for the machine. */
3311
3312 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3313
3314
3315 /* Define this macro if references to a symbol must be treated
3316 differently depending on something about the variable or
3317 function named by the symbol (such as what section it is in).
3318
3319 The macro definition, if any, is executed immediately after the
3320 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3321 The value of the rtl will be a `mem' whose address is a
3322 `symbol_ref'.
3323
3324 The usual thing for this macro to do is to a flag in the
3325 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3326 name string in the `symbol_ref' (if one bit is not enough
3327 information).
3328
3329 The best way to modify the name string is by adding text to the
3330 beginning, with suitable punctuation to prevent any ambiguity.
3331 Allocate the new name in `saveable_obstack'. You will have to
3332 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3333 and output the name accordingly.
3334
3335 You can also check the information stored in the `symbol_ref' in
3336 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3337 `PRINT_OPERAND_ADDRESS'.
3338
3339 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3340 small objects.
3341
3342 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3343 symbols which are not in the .text section.
3344
3345 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3346 constants which are put in the .text section. We also record the
3347 total length of all such strings; this total is used to decide
3348 whether we need to split the constant table, and need not be
3349 precisely correct.
3350
3351 When not mips16 code nor embedded PIC, if a symbol is in a
3352 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3353 splitting the reference so that gas can generate a gp relative
3354 reference.
3355
3356 When TARGET_EMBEDDED_DATA is set, we assume that all const
3357 variables will be stored in ROM, which is too far from %gp to use
3358 %gprel addressing. Note that (1) we include "extern const"
3359 variables in this, which mips_select_section doesn't, and (2) we
3360 can't always tell if they're really const (they might be const C++
3361 objects with non-const constructors), so we err on the side of
3362 caution and won't use %gprel anyway (otherwise we'd have to defer
3363 this decision to the linker/loader). The handling of extern consts
3364 is why the DECL_INITIAL macros differ from mips_select_section.
3365
3366 If you are changing this macro, you should look at
3367 mips_select_section and see if it needs a similar change. */
3368
3369 #define ENCODE_SECTION_INFO(DECL) \
3370 do \
3371 { \
3372 if (TARGET_MIPS16) \
3373 { \
3374 if (TREE_CODE (DECL) == STRING_CST \
3375 && ! flag_writable_strings \
3376 /* If this string is from a function, and the function will \
3377 go in a gnu linkonce section, then we can't directly \
3378 access the string. This gets an assembler error \
3379 "unsupported PC relative reference to different section".\
3380 If we modify SELECT_SECTION to put it in function_section\
3381 instead of text_section, it still fails because \
3382 DECL_SECTION_NAME isn't set until assemble_start_function.\
3383 If we fix that, it still fails because strings are shared\
3384 among multiple functions, and we have cross section \
3385 references again. We force it to work by putting string \
3386 addresses in the constant pool and indirecting. */ \
3387 && (! current_function_decl \
3388 || ! DECL_ONE_ONLY (current_function_decl))) \
3389 { \
3390 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3391 mips_string_length += TREE_STRING_LENGTH (DECL); \
3392 } \
3393 } \
3394 \
3395 if (TARGET_EMBEDDED_DATA \
3396 && (TREE_CODE (DECL) == VAR_DECL \
3397 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3398 && (!DECL_INITIAL (DECL) \
3399 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3400 { \
3401 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3402 } \
3403 \
3404 else if (TARGET_EMBEDDED_PIC) \
3405 { \
3406 if (TREE_CODE (DECL) == VAR_DECL) \
3407 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3408 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3409 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3410 else if (TREE_CODE (DECL) == STRING_CST \
3411 && ! flag_writable_strings) \
3412 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3413 else \
3414 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3415 } \
3416 \
3417 else if (TREE_CODE (DECL) == VAR_DECL \
3418 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3419 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3420 ".sdata") \
3421 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3422 ".sbss"))) \
3423 { \
3424 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3425 } \
3426 \
3427 /* We can not perform GP optimizations on variables which are in \
3428 specific sections, except for .sdata and .sbss which are \
3429 handled above. */ \
3430 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3431 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3432 { \
3433 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3434 \
3435 if (size > 0 && size <= mips_section_threshold) \
3436 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3437 } \
3438 \
3439 else if (HALF_PIC_P ()) \
3440 { \
3441 HALF_PIC_ENCODE (DECL); \
3442 } \
3443 } \
3444 while (0)
3445
3446 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3447 'the start of the function that this code is output in'. */
3448
3449 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3450 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3451 asm_fprintf ((FILE), "%U%s", \
3452 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3453 else \
3454 asm_fprintf ((FILE), "%U%s", (NAME))
3455
3456 /* The mips16 wants the constant pool to be after the function,
3457 because the PC relative load instructions use unsigned offsets. */
3458
3459 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3460
3461 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3462 mips_string_length = 0;
3463
3464 #if 0
3465 /* In mips16 mode, put most string constants after the function. */
3466 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3467 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3468 #endif
3469 \f
3470 /* Specify the machine mode that this machine uses
3471 for the index in the tablejump instruction.
3472 ??? Using HImode in mips16 mode can cause overflow. However, the
3473 overflow is no more likely than the overflow in a branch
3474 instruction. Large functions can currently break in both ways. */
3475 #define CASE_VECTOR_MODE \
3476 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3477
3478 /* Define as C expression which evaluates to nonzero if the tablejump
3479 instruction expects the table to contain offsets from the address of the
3480 table.
3481 Do not define this if the table should contain absolute addresses. */
3482 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3483
3484 /* Define this as 1 if `char' should by default be signed; else as 0. */
3485 #ifndef DEFAULT_SIGNED_CHAR
3486 #define DEFAULT_SIGNED_CHAR 1
3487 #endif
3488
3489 /* Max number of bytes we can move from memory to memory
3490 in one reasonably fast instruction. */
3491 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3492 #define MAX_MOVE_MAX 8
3493
3494 /* Define this macro as a C expression which is nonzero if
3495 accessing less than a word of memory (i.e. a `char' or a
3496 `short') is no faster than accessing a word of memory, i.e., if
3497 such access require more than one instruction or if there is no
3498 difference in cost between byte and (aligned) word loads.
3499
3500 On RISC machines, it tends to generate better code to define
3501 this as 1, since it avoids making a QI or HI mode register. */
3502 #define SLOW_BYTE_ACCESS 1
3503
3504 /* We assume that the store-condition-codes instructions store 0 for false
3505 and some other value for true. This is the value stored for true. */
3506
3507 #define STORE_FLAG_VALUE 1
3508
3509 /* Define this to be nonzero if shift instructions ignore all but the low-order
3510 few bits. */
3511 #define SHIFT_COUNT_TRUNCATED 1
3512
3513 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3514 is done just by pretending it is already truncated. */
3515 /* In 64 bit mode, 32 bit instructions require that register values be properly
3516 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3517 converts a value >32 bits to a value <32 bits. */
3518 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3519 Something needs to be done about this. Perhaps not use any 32 bit
3520 instructions? Perhaps use PROMOTE_MODE? */
3521 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3522 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3523
3524 /* Specify the machine mode that pointers have.
3525 After generation of rtl, the compiler makes no further distinction
3526 between pointers and any other objects of this machine mode.
3527
3528 For MIPS we make pointers are the smaller of longs and gp-registers. */
3529
3530 #ifndef Pmode
3531 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3532 #endif
3533
3534 /* A function address in a call instruction
3535 is a word address (for indexing purposes)
3536 so give the MEM rtx a words's mode. */
3537
3538 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3539
3540 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3541 memset, instead of the BSD functions bcopy and bzero. */
3542
3543 #if defined(MIPS_SYSV) || defined(OSF_OS)
3544 #define TARGET_MEM_FUNCTIONS
3545 #endif
3546
3547 \f
3548 /* A part of a C `switch' statement that describes the relative
3549 costs of constant RTL expressions. It must contain `case'
3550 labels for expression codes `const_int', `const', `symbol_ref',
3551 `label_ref' and `const_double'. Each case must ultimately reach
3552 a `return' statement to return the relative cost of the use of
3553 that kind of constant value in an expression. The cost may
3554 depend on the precise value of the constant, which is available
3555 for examination in X.
3556
3557 CODE is the expression code--redundant, since it can be obtained
3558 with `GET_CODE (X)'. */
3559
3560 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3561 case CONST_INT: \
3562 if (! TARGET_MIPS16) \
3563 { \
3564 /* Always return 0, since we don't have different sized \
3565 instructions, hence different costs according to Richard \
3566 Kenner */ \
3567 return 0; \
3568 } \
3569 if ((OUTER_CODE) == SET) \
3570 { \
3571 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3572 return 0; \
3573 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3574 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3575 return COSTS_N_INSNS (1); \
3576 else \
3577 return COSTS_N_INSNS (2); \
3578 } \
3579 /* A PLUS could be an address. We don't want to force an address \
3580 to use a register, so accept any signed 16 bit value without \
3581 complaint. */ \
3582 if ((OUTER_CODE) == PLUS \
3583 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3584 return 0; \
3585 /* A number between 1 and 8 inclusive is efficient for a shift. \
3586 Otherwise, we will need an extended instruction. */ \
3587 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3588 || (OUTER_CODE) == LSHIFTRT) \
3589 { \
3590 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3591 return 0; \
3592 return COSTS_N_INSNS (1); \
3593 } \
3594 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3595 if ((OUTER_CODE) == XOR \
3596 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3597 return 0; \
3598 /* We may be able to use slt or sltu for a comparison with a \
3599 signed 16 bit value. (The boundary conditions aren't quite \
3600 right, but this is just a heuristic anyhow.) */ \
3601 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3602 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3603 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3604 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3605 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3606 return 0; \
3607 /* Equality comparisons with 0 are cheap. */ \
3608 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3609 && INTVAL (X) == 0) \
3610 return 0; \
3611 \
3612 /* Otherwise, work out the cost to load the value into a \
3613 register. */ \
3614 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3615 return COSTS_N_INSNS (1); \
3616 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3617 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3618 return COSTS_N_INSNS (2); \
3619 else \
3620 return COSTS_N_INSNS (3); \
3621 \
3622 case LABEL_REF: \
3623 return COSTS_N_INSNS (2); \
3624 \
3625 case CONST: \
3626 { \
3627 rtx offset = const0_rtx; \
3628 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3629 \
3630 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3631 { \
3632 /* Treat this like a signed 16 bit CONST_INT. */ \
3633 if ((OUTER_CODE) == PLUS) \
3634 return 0; \
3635 else if ((OUTER_CODE) == SET) \
3636 return COSTS_N_INSNS (1); \
3637 else \
3638 return COSTS_N_INSNS (2); \
3639 } \
3640 \
3641 if (GET_CODE (symref) == LABEL_REF) \
3642 return COSTS_N_INSNS (2); \
3643 \
3644 if (GET_CODE (symref) != SYMBOL_REF) \
3645 return COSTS_N_INSNS (4); \
3646 \
3647 /* let's be paranoid.... */ \
3648 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3649 return COSTS_N_INSNS (2); \
3650 \
3651 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3652 } \
3653 \
3654 case SYMBOL_REF: \
3655 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3656 \
3657 case CONST_DOUBLE: \
3658 { \
3659 rtx high, low; \
3660 if (TARGET_MIPS16) \
3661 return COSTS_N_INSNS (4); \
3662 split_double (X, &high, &low); \
3663 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3664 || low == CONST0_RTX (GET_MODE (low))) \
3665 ? 2 : 4); \
3666 }
3667
3668 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3669 This can be used, for example, to indicate how costly a multiply
3670 instruction is. In writing this macro, you can use the construct
3671 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3672
3673 This macro is optional; do not define it if the default cost
3674 assumptions are adequate for the target machine.
3675
3676 If -mdebugd is used, change the multiply cost to 2, so multiply by
3677 a constant isn't converted to a series of shifts. This helps
3678 strength reduction, and also makes it easier to identify what the
3679 compiler is doing. */
3680
3681 /* ??? Fix this to be right for the R8000. */
3682 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3683 case MEM: \
3684 { \
3685 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3686 if (simple_memory_operand (X, GET_MODE (X))) \
3687 return COSTS_N_INSNS (num_words); \
3688 \
3689 return COSTS_N_INSNS (2*num_words); \
3690 } \
3691 \
3692 case FFS: \
3693 return COSTS_N_INSNS (6); \
3694 \
3695 case NOT: \
3696 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3697 \
3698 case AND: \
3699 case IOR: \
3700 case XOR: \
3701 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3702 return COSTS_N_INSNS (2); \
3703 \
3704 break; \
3705 \
3706 case ASHIFT: \
3707 case ASHIFTRT: \
3708 case LSHIFTRT: \
3709 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3710 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3711 \
3712 break; \
3713 \
3714 case ABS: \
3715 { \
3716 enum machine_mode xmode = GET_MODE (X); \
3717 if (xmode == SFmode || xmode == DFmode) \
3718 return COSTS_N_INSNS (1); \
3719 \
3720 return COSTS_N_INSNS (4); \
3721 } \
3722 \
3723 case PLUS: \
3724 case MINUS: \
3725 { \
3726 enum machine_mode xmode = GET_MODE (X); \
3727 if (xmode == SFmode || xmode == DFmode) \
3728 { \
3729 if (TUNE_MIPS3000 \
3730 || TUNE_MIPS3900) \
3731 return COSTS_N_INSNS (2); \
3732 else if (TUNE_MIPS6000) \
3733 return COSTS_N_INSNS (3); \
3734 else \
3735 return COSTS_N_INSNS (6); \
3736 } \
3737 \
3738 if (xmode == DImode && !TARGET_64BIT) \
3739 return COSTS_N_INSNS (4); \
3740 \
3741 break; \
3742 } \
3743 \
3744 case NEG: \
3745 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3746 return 4; \
3747 \
3748 break; \
3749 \
3750 case MULT: \
3751 { \
3752 enum machine_mode xmode = GET_MODE (X); \
3753 if (xmode == SFmode) \
3754 { \
3755 if (TUNE_MIPS3000 \
3756 || TUNE_MIPS3900 \
3757 || TUNE_MIPS5000) \
3758 return COSTS_N_INSNS (4); \
3759 else if (TUNE_MIPS6000) \
3760 return COSTS_N_INSNS (5); \
3761 else \
3762 return COSTS_N_INSNS (7); \
3763 } \
3764 \
3765 if (xmode == DFmode) \
3766 { \
3767 if (TUNE_MIPS3000 \
3768 || TUNE_MIPS3900 \
3769 || TUNE_MIPS5000) \
3770 return COSTS_N_INSNS (5); \
3771 else if (TUNE_MIPS6000) \
3772 return COSTS_N_INSNS (6); \
3773 else \
3774 return COSTS_N_INSNS (8); \
3775 } \
3776 \
3777 if (TUNE_MIPS3000) \
3778 return COSTS_N_INSNS (12); \
3779 else if (TUNE_MIPS3900) \
3780 return COSTS_N_INSNS (2); \
3781 else if (TUNE_MIPS6000) \
3782 return COSTS_N_INSNS (17); \
3783 else if (TUNE_MIPS5000) \
3784 return COSTS_N_INSNS (5); \
3785 else \
3786 return COSTS_N_INSNS (10); \
3787 } \
3788 \
3789 case DIV: \
3790 case MOD: \
3791 { \
3792 enum machine_mode xmode = GET_MODE (X); \
3793 if (xmode == SFmode) \
3794 { \
3795 if (TUNE_MIPS3000 \
3796 || TUNE_MIPS3900) \
3797 return COSTS_N_INSNS (12); \
3798 else if (TUNE_MIPS6000) \
3799 return COSTS_N_INSNS (15); \
3800 else \
3801 return COSTS_N_INSNS (23); \
3802 } \
3803 \
3804 if (xmode == DFmode) \
3805 { \
3806 if (TUNE_MIPS3000 \
3807 || TUNE_MIPS3900) \
3808 return COSTS_N_INSNS (19); \
3809 else if (TUNE_MIPS6000) \
3810 return COSTS_N_INSNS (16); \
3811 else \
3812 return COSTS_N_INSNS (36); \
3813 } \
3814 } \
3815 /* fall through */ \
3816 \
3817 case UDIV: \
3818 case UMOD: \
3819 if (TUNE_MIPS3000 \
3820 || TUNE_MIPS3900) \
3821 return COSTS_N_INSNS (35); \
3822 else if (TUNE_MIPS6000) \
3823 return COSTS_N_INSNS (38); \
3824 else if (TUNE_MIPS5000) \
3825 return COSTS_N_INSNS (36); \
3826 else \
3827 return COSTS_N_INSNS (69); \
3828 \
3829 case SIGN_EXTEND: \
3830 /* A sign extend from SImode to DImode in 64 bit mode is often \
3831 zero instructions, because the result can often be used \
3832 directly by another instruction; we'll call it one. */ \
3833 if (TARGET_64BIT && GET_MODE (X) == DImode \
3834 && GET_MODE (XEXP (X, 0)) == SImode) \
3835 return COSTS_N_INSNS (1); \
3836 else \
3837 return COSTS_N_INSNS (2); \
3838 \
3839 case ZERO_EXTEND: \
3840 if (TARGET_64BIT && GET_MODE (X) == DImode \
3841 && GET_MODE (XEXP (X, 0)) == SImode) \
3842 return COSTS_N_INSNS (2); \
3843 else \
3844 return COSTS_N_INSNS (1);
3845
3846 /* An expression giving the cost of an addressing mode that
3847 contains ADDRESS. If not defined, the cost is computed from the
3848 form of the ADDRESS expression and the `CONST_COSTS' values.
3849
3850 For most CISC machines, the default cost is a good approximation
3851 of the true cost of the addressing mode. However, on RISC
3852 machines, all instructions normally have the same length and
3853 execution time. Hence all addresses will have equal costs.
3854
3855 In cases where more than one form of an address is known, the
3856 form with the lowest cost will be used. If multiple forms have
3857 the same, lowest, cost, the one that is the most complex will be
3858 used.
3859
3860 For example, suppose an address that is equal to the sum of a
3861 register and a constant is used twice in the same basic block.
3862 When this macro is not defined, the address will be computed in
3863 a register and memory references will be indirect through that
3864 register. On machines where the cost of the addressing mode
3865 containing the sum is no higher than that of a simple indirect
3866 reference, this will produce an additional instruction and
3867 possibly require an additional register. Proper specification
3868 of this macro eliminates this overhead for such machines.
3869
3870 Similar use of this macro is made in strength reduction of loops.
3871
3872 ADDRESS need not be valid as an address. In such a case, the
3873 cost is not relevant and can be any value; invalid addresses
3874 need not be assigned a different cost.
3875
3876 On machines where an address involving more than one register is
3877 as cheap as an address computation involving only one register,
3878 defining `ADDRESS_COST' to reflect this can cause two registers
3879 to be live over a region of code where only one would have been
3880 if `ADDRESS_COST' were not defined in that manner. This effect
3881 should be considered in the definition of this macro.
3882 Equivalent costs should probably only be given to addresses with
3883 different numbers of registers on machines with lots of registers.
3884
3885 This macro will normally either not be defined or be defined as
3886 a constant. */
3887
3888 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3889
3890 /* A C expression for the cost of moving data from a register in
3891 class FROM to one in class TO. The classes are expressed using
3892 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3893 the default; other values are interpreted relative to that.
3894
3895 It is not required that the cost always equal 2 when FROM is the
3896 same as TO; on some machines it is expensive to move between
3897 registers if they are not general registers.
3898
3899 If reload sees an insn consisting of a single `set' between two
3900 hard registers, and if `REGISTER_MOVE_COST' applied to their
3901 classes returns a value of 2, reload does not check to ensure
3902 that the constraints of the insn are met. Setting a cost of
3903 other than 2 will allow reload to verify that the constraints are
3904 met. You should do this if the `movM' pattern's constraints do
3905 not allow such copying.
3906
3907 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3908 registers the same as for one of moving general registers to
3909 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3910 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3911 isn't clear if it is wise. And it might not work in all cases. We
3912 could solve the DImode LO reg problem by using a multiply, just like
3913 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3914 by using divide instructions. divu puts the remainder in the HI
3915 reg, so doing a divide by -1 will move the value in the HI reg for
3916 all values except -1. We could handle that case by using a signed
3917 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3918 compare/branch to test the input value to see which instruction we
3919 need to use. This gets pretty messy, but it is feasible. */
3920
3921 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3922 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3923 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3924 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3925 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3926 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3927 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3928 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3929 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3930 : (((FROM) == HI_REG || (FROM) == LO_REG \
3931 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3932 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3933 : (((TO) == HI_REG || (TO) == LO_REG \
3934 || (TO) == MD_REGS || (TO) == HILO_REG) \
3935 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3936 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3937 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3938 : 12)
3939
3940 /* ??? Fix this to be right for the R8000. */
3941 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3942 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3943 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3944
3945 /* Define if copies to/from condition code registers should be avoided.
3946
3947 This is needed for the MIPS because reload_outcc is not complete;
3948 it needs to handle cases where the source is a general or another
3949 condition code register. */
3950 #define AVOID_CCMODE_COPIES
3951
3952 /* A C expression for the cost of a branch instruction. A value of
3953 1 is the default; other values are interpreted relative to that. */
3954
3955 /* ??? Fix this to be right for the R8000. */
3956 #define BRANCH_COST \
3957 ((! TARGET_MIPS16 \
3958 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3959 ? 2 : 1)
3960
3961 /* If defined, modifies the length assigned to instruction INSN as a
3962 function of the context in which it is used. LENGTH is an lvalue
3963 that contains the initially computed length of the insn and should
3964 be updated with the correct length of the insn. */
3965 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3966 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3967
3968 \f
3969 /* Optionally define this if you have added predicates to
3970 `MACHINE.c'. This macro is called within an initializer of an
3971 array of structures. The first field in the structure is the
3972 name of a predicate and the second field is an array of rtl
3973 codes. For each predicate, list all rtl codes that can be in
3974 expressions matched by the predicate. The list should have a
3975 trailing comma. Here is an example of two entries in the list
3976 for a typical RISC machine:
3977
3978 #define PREDICATE_CODES \
3979 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3980 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3981
3982 Defining this macro does not affect the generated code (however,
3983 incorrect definitions that omit an rtl code that may be matched
3984 by the predicate can cause the compiler to malfunction).
3985 Instead, it allows the table built by `genrecog' to be more
3986 compact and efficient, thus speeding up the compiler. The most
3987 important predicates to include in the list specified by this
3988 macro are thoses used in the most insn patterns. */
3989
3990 #define PREDICATE_CODES \
3991 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3992 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3993 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3994 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3995 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3996 {"small_int", { CONST_INT }}, \
3997 {"large_int", { CONST_INT }}, \
3998 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3999 {"const_float_1_operand", { CONST_DOUBLE }}, \
4000 {"simple_memory_operand", { MEM, SUBREG }}, \
4001 {"equality_op", { EQ, NE }}, \
4002 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
4003 LTU, LEU }}, \
4004 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
4005 {"pc_or_label_operand", { PC, LABEL_REF }}, \
4006 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
4007 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
4008 SYMBOL_REF, LABEL_REF, SUBREG, \
4009 REG, MEM}}, \
4010 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
4011 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
4012 MEM, SIGN_EXTEND }}, \
4013 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
4014 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
4015 SIGN_EXTEND }}, \
4016 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
4017 SIGN_EXTEND }}, \
4018 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
4019 SIGN_EXTEND }}, \
4020 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
4021 SYMBOL_REF, LABEL_REF, SUBREG, \
4022 REG, SIGN_EXTEND }}, \
4023 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
4024 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
4025 CONST_DOUBLE, CONST }}, \
4026 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
4027 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
4028
4029 /* A list of predicates that do special things with modes, and so
4030 should not elicit warnings for VOIDmode match_operand. */
4031
4032 #define SPECIAL_MODE_PREDICATES \
4033 "pc_or_label_operand",
4034
4035 \f
4036 /* If defined, a C statement to be executed just prior to the
4037 output of assembler code for INSN, to modify the extracted
4038 operands so they will be output differently.
4039
4040 Here the argument OPVEC is the vector containing the operands
4041 extracted from INSN, and NOPERANDS is the number of elements of
4042 the vector which contain meaningful data for this insn. The
4043 contents of this vector are what will be used to convert the
4044 insn template into assembler code, so you can change the
4045 assembler output by changing the contents of the vector.
4046
4047 We use it to check if the current insn needs a nop in front of it
4048 because of load delays, and also to update the delay slot
4049 statistics. */
4050
4051 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
4052 final_prescan_insn (INSN, OPVEC, NOPERANDS)
4053
4054 \f
4055 /* Control the assembler format that we output. */
4056
4057 /* Output at beginning of assembler file.
4058 If we are optimizing to use the global pointer, create a temporary
4059 file to hold all of the text stuff, and write it out to the end.
4060 This is needed because the MIPS assembler is evidently one pass,
4061 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4062 declaration when the code is processed, it generates a two
4063 instruction sequence. */
4064
4065 #undef ASM_FILE_START
4066 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
4067
4068 /* Output to assembler file text saying following lines
4069 may contain character constants, extra white space, comments, etc. */
4070
4071 #ifndef ASM_APP_ON
4072 #define ASM_APP_ON " #APP\n"
4073 #endif
4074
4075 /* Output to assembler file text saying following lines
4076 no longer contain unusual constructs. */
4077
4078 #ifndef ASM_APP_OFF
4079 #define ASM_APP_OFF " #NO_APP\n"
4080 #endif
4081
4082 /* How to refer to registers in assembler output.
4083 This sequence is indexed by compiler's hard-register-number (see above).
4084
4085 In order to support the two different conventions for register names,
4086 we use the name of a table set up in mips.c, which is overwritten
4087 if -mrnames is used. */
4088
4089 #define REGISTER_NAMES \
4090 { \
4091 &mips_reg_names[ 0][0], \
4092 &mips_reg_names[ 1][0], \
4093 &mips_reg_names[ 2][0], \
4094 &mips_reg_names[ 3][0], \
4095 &mips_reg_names[ 4][0], \
4096 &mips_reg_names[ 5][0], \
4097 &mips_reg_names[ 6][0], \
4098 &mips_reg_names[ 7][0], \
4099 &mips_reg_names[ 8][0], \
4100 &mips_reg_names[ 9][0], \
4101 &mips_reg_names[10][0], \
4102 &mips_reg_names[11][0], \
4103 &mips_reg_names[12][0], \
4104 &mips_reg_names[13][0], \
4105 &mips_reg_names[14][0], \
4106 &mips_reg_names[15][0], \
4107 &mips_reg_names[16][0], \
4108 &mips_reg_names[17][0], \
4109 &mips_reg_names[18][0], \
4110 &mips_reg_names[19][0], \
4111 &mips_reg_names[20][0], \
4112 &mips_reg_names[21][0], \
4113 &mips_reg_names[22][0], \
4114 &mips_reg_names[23][0], \
4115 &mips_reg_names[24][0], \
4116 &mips_reg_names[25][0], \
4117 &mips_reg_names[26][0], \
4118 &mips_reg_names[27][0], \
4119 &mips_reg_names[28][0], \
4120 &mips_reg_names[29][0], \
4121 &mips_reg_names[30][0], \
4122 &mips_reg_names[31][0], \
4123 &mips_reg_names[32][0], \
4124 &mips_reg_names[33][0], \
4125 &mips_reg_names[34][0], \
4126 &mips_reg_names[35][0], \
4127 &mips_reg_names[36][0], \
4128 &mips_reg_names[37][0], \
4129 &mips_reg_names[38][0], \
4130 &mips_reg_names[39][0], \
4131 &mips_reg_names[40][0], \
4132 &mips_reg_names[41][0], \
4133 &mips_reg_names[42][0], \
4134 &mips_reg_names[43][0], \
4135 &mips_reg_names[44][0], \
4136 &mips_reg_names[45][0], \
4137 &mips_reg_names[46][0], \
4138 &mips_reg_names[47][0], \
4139 &mips_reg_names[48][0], \
4140 &mips_reg_names[49][0], \
4141 &mips_reg_names[50][0], \
4142 &mips_reg_names[51][0], \
4143 &mips_reg_names[52][0], \
4144 &mips_reg_names[53][0], \
4145 &mips_reg_names[54][0], \
4146 &mips_reg_names[55][0], \
4147 &mips_reg_names[56][0], \
4148 &mips_reg_names[57][0], \
4149 &mips_reg_names[58][0], \
4150 &mips_reg_names[59][0], \
4151 &mips_reg_names[60][0], \
4152 &mips_reg_names[61][0], \
4153 &mips_reg_names[62][0], \
4154 &mips_reg_names[63][0], \
4155 &mips_reg_names[64][0], \
4156 &mips_reg_names[65][0], \
4157 &mips_reg_names[66][0], \
4158 &mips_reg_names[67][0], \
4159 &mips_reg_names[68][0], \
4160 &mips_reg_names[69][0], \
4161 &mips_reg_names[70][0], \
4162 &mips_reg_names[71][0], \
4163 &mips_reg_names[72][0], \
4164 &mips_reg_names[73][0], \
4165 &mips_reg_names[74][0], \
4166 &mips_reg_names[75][0], \
4167 }
4168
4169 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4170 So define this for it. */
4171 #define DEBUG_REGISTER_NAMES \
4172 { \
4173 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4174 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4175 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4176 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4177 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4178 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4179 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4180 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4181 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4182 "$fcc5","$fcc6","$fcc7","$rap" \
4183 }
4184
4185 /* If defined, a C initializer for an array of structures
4186 containing a name and a register number. This macro defines
4187 additional names for hard registers, thus allowing the `asm'
4188 option in declarations to refer to registers using alternate
4189 names.
4190
4191 We define both names for the integer registers here. */
4192
4193 #define ADDITIONAL_REGISTER_NAMES \
4194 { \
4195 { "$0", 0 + GP_REG_FIRST }, \
4196 { "$1", 1 + GP_REG_FIRST }, \
4197 { "$2", 2 + GP_REG_FIRST }, \
4198 { "$3", 3 + GP_REG_FIRST }, \
4199 { "$4", 4 + GP_REG_FIRST }, \
4200 { "$5", 5 + GP_REG_FIRST }, \
4201 { "$6", 6 + GP_REG_FIRST }, \
4202 { "$7", 7 + GP_REG_FIRST }, \
4203 { "$8", 8 + GP_REG_FIRST }, \
4204 { "$9", 9 + GP_REG_FIRST }, \
4205 { "$10", 10 + GP_REG_FIRST }, \
4206 { "$11", 11 + GP_REG_FIRST }, \
4207 { "$12", 12 + GP_REG_FIRST }, \
4208 { "$13", 13 + GP_REG_FIRST }, \
4209 { "$14", 14 + GP_REG_FIRST }, \
4210 { "$15", 15 + GP_REG_FIRST }, \
4211 { "$16", 16 + GP_REG_FIRST }, \
4212 { "$17", 17 + GP_REG_FIRST }, \
4213 { "$18", 18 + GP_REG_FIRST }, \
4214 { "$19", 19 + GP_REG_FIRST }, \
4215 { "$20", 20 + GP_REG_FIRST }, \
4216 { "$21", 21 + GP_REG_FIRST }, \
4217 { "$22", 22 + GP_REG_FIRST }, \
4218 { "$23", 23 + GP_REG_FIRST }, \
4219 { "$24", 24 + GP_REG_FIRST }, \
4220 { "$25", 25 + GP_REG_FIRST }, \
4221 { "$26", 26 + GP_REG_FIRST }, \
4222 { "$27", 27 + GP_REG_FIRST }, \
4223 { "$28", 28 + GP_REG_FIRST }, \
4224 { "$29", 29 + GP_REG_FIRST }, \
4225 { "$30", 30 + GP_REG_FIRST }, \
4226 { "$31", 31 + GP_REG_FIRST }, \
4227 { "$sp", 29 + GP_REG_FIRST }, \
4228 { "$fp", 30 + GP_REG_FIRST }, \
4229 { "at", 1 + GP_REG_FIRST }, \
4230 { "v0", 2 + GP_REG_FIRST }, \
4231 { "v1", 3 + GP_REG_FIRST }, \
4232 { "a0", 4 + GP_REG_FIRST }, \
4233 { "a1", 5 + GP_REG_FIRST }, \
4234 { "a2", 6 + GP_REG_FIRST }, \
4235 { "a3", 7 + GP_REG_FIRST }, \
4236 { "t0", 8 + GP_REG_FIRST }, \
4237 { "t1", 9 + GP_REG_FIRST }, \
4238 { "t2", 10 + GP_REG_FIRST }, \
4239 { "t3", 11 + GP_REG_FIRST }, \
4240 { "t4", 12 + GP_REG_FIRST }, \
4241 { "t5", 13 + GP_REG_FIRST }, \
4242 { "t6", 14 + GP_REG_FIRST }, \
4243 { "t7", 15 + GP_REG_FIRST }, \
4244 { "s0", 16 + GP_REG_FIRST }, \
4245 { "s1", 17 + GP_REG_FIRST }, \
4246 { "s2", 18 + GP_REG_FIRST }, \
4247 { "s3", 19 + GP_REG_FIRST }, \
4248 { "s4", 20 + GP_REG_FIRST }, \
4249 { "s5", 21 + GP_REG_FIRST }, \
4250 { "s6", 22 + GP_REG_FIRST }, \
4251 { "s7", 23 + GP_REG_FIRST }, \
4252 { "t8", 24 + GP_REG_FIRST }, \
4253 { "t9", 25 + GP_REG_FIRST }, \
4254 { "k0", 26 + GP_REG_FIRST }, \
4255 { "k1", 27 + GP_REG_FIRST }, \
4256 { "gp", 28 + GP_REG_FIRST }, \
4257 { "sp", 29 + GP_REG_FIRST }, \
4258 { "fp", 30 + GP_REG_FIRST }, \
4259 { "ra", 31 + GP_REG_FIRST }, \
4260 { "$sp", 29 + GP_REG_FIRST }, \
4261 { "$fp", 30 + GP_REG_FIRST } \
4262 }
4263
4264 /* A C compound statement to output to stdio stream STREAM the
4265 assembler syntax for an instruction operand X. X is an RTL
4266 expression.
4267
4268 CODE is a value that can be used to specify one of several ways
4269 of printing the operand. It is used when identical operands
4270 must be printed differently depending on the context. CODE
4271 comes from the `%' specification that was used to request
4272 printing of the operand. If the specification was just `%DIGIT'
4273 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4274 is the ASCII code for LTR.
4275
4276 If X is a register, this macro should print the register's name.
4277 The names can be found in an array `reg_names' whose type is
4278 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4279
4280 When the machine description has a specification `%PUNCT' (a `%'
4281 followed by a punctuation character), this macro is called with
4282 a null pointer for X and the punctuation character for CODE.
4283
4284 See mips.c for the MIPS specific codes. */
4285
4286 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4287
4288 /* A C expression which evaluates to true if CODE is a valid
4289 punctuation character for use in the `PRINT_OPERAND' macro. If
4290 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4291 punctuation characters (except for the standard one, `%') are
4292 used in this way. */
4293
4294 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4295
4296 /* A C compound statement to output to stdio stream STREAM the
4297 assembler syntax for an instruction operand that is a memory
4298 reference whose address is ADDR. ADDR is an RTL expression.
4299
4300 On some machines, the syntax for a symbolic address depends on
4301 the section that the address refers to. On these machines,
4302 define the macro `ENCODE_SECTION_INFO' to store the information
4303 into the `symbol_ref', and then check for it here. */
4304
4305 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4306
4307
4308 /* A C statement, to be executed after all slot-filler instructions
4309 have been output. If necessary, call `dbr_sequence_length' to
4310 determine the number of slots filled in a sequence (zero if not
4311 currently outputting a sequence), to decide how many no-ops to
4312 output, or whatever.
4313
4314 Don't define this macro if it has nothing to do, but it is
4315 helpful in reading assembly output if the extent of the delay
4316 sequence is made explicit (e.g. with white space).
4317
4318 Note that output routines for instructions with delay slots must
4319 be prepared to deal with not being output as part of a sequence
4320 (i.e. when the scheduling pass is not run, or when no slot
4321 fillers could be found.) The variable `final_sequence' is null
4322 when not processing a sequence, otherwise it contains the
4323 `sequence' rtx being output. */
4324
4325 #define DBR_OUTPUT_SEQEND(STREAM) \
4326 do \
4327 { \
4328 if (set_nomacro > 0 && --set_nomacro == 0) \
4329 fputs ("\t.set\tmacro\n", STREAM); \
4330 \
4331 if (set_noreorder > 0 && --set_noreorder == 0) \
4332 fputs ("\t.set\treorder\n", STREAM); \
4333 \
4334 dslots_jump_filled++; \
4335 fputs ("\n", STREAM); \
4336 } \
4337 while (0)
4338
4339
4340 /* How to tell the debugger about changes of source files. Note, the
4341 mips ECOFF format cannot deal with changes of files inside of
4342 functions, which means the output of parser generators like bison
4343 is generally not debuggable without using the -l switch. Lose,
4344 lose, lose. Silicon graphics seems to want all .file's hardwired
4345 to 1. */
4346
4347 #ifndef SET_FILE_NUMBER
4348 #define SET_FILE_NUMBER() ++num_source_filenames
4349 #endif
4350
4351 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4352 mips_output_filename (STREAM, NAME)
4353
4354 /* This is defined so that it can be overridden in iris6.h. */
4355 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4356 do \
4357 { \
4358 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4359 output_quoted_string (STREAM, NAME); \
4360 fputs ("\n", STREAM); \
4361 } \
4362 while (0)
4363
4364 /* This is how to output a note the debugger telling it the line number
4365 to which the following sequence of instructions corresponds.
4366 Silicon graphics puts a label after each .loc. */
4367
4368 #ifndef LABEL_AFTER_LOC
4369 #define LABEL_AFTER_LOC(STREAM)
4370 #endif
4371
4372 #ifndef ASM_OUTPUT_SOURCE_LINE
4373 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4374 mips_output_lineno (STREAM, LINE)
4375 #endif
4376
4377 /* The MIPS implementation uses some labels for its own purpose. The
4378 following lists what labels are created, and are all formed by the
4379 pattern $L[a-z].*. The machine independent portion of GCC creates
4380 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4381
4382 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4383 $Lb[0-9]+ Begin blocks for MIPS debug support
4384 $Lc[0-9]+ Label for use in s<xx> operation.
4385 $Le[0-9]+ End blocks for MIPS debug support
4386 $Lp\..+ Half-pic labels. */
4387
4388 /* This is how to output the definition of a user-level label named NAME,
4389 such as the label on a static function or variable NAME.
4390
4391 If we are optimizing the gp, remember that this label has been put
4392 out, so we know not to emit an .extern for it in mips_asm_file_end.
4393 We use one of the common bits in the IDENTIFIER tree node for this,
4394 since those bits seem to be unused, and we don't have any method
4395 of getting the decl nodes from the name. */
4396
4397 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4398 do { \
4399 assemble_name (STREAM, NAME); \
4400 fputs (":\n", STREAM); \
4401 } while (0)
4402
4403
4404 /* A C statement (sans semicolon) to output to the stdio stream
4405 STREAM any text necessary for declaring the name NAME of an
4406 initialized variable which is being defined. This macro must
4407 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4408 The argument DECL is the `VAR_DECL' tree node representing the
4409 variable.
4410
4411 If this macro is not defined, then the variable name is defined
4412 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4413
4414 #undef ASM_DECLARE_OBJECT_NAME
4415 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4416 do \
4417 { \
4418 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4419 HALF_PIC_DECLARE (NAME); \
4420 } \
4421 while (0)
4422
4423
4424 /* This is how to output a command to make the user-level label named NAME
4425 defined for reference from other files. */
4426
4427 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4428 do { \
4429 fputs ("\t.globl\t", STREAM); \
4430 assemble_name (STREAM, NAME); \
4431 fputs ("\n", STREAM); \
4432 } while (0)
4433
4434 /* This says how to define a global common symbol. */
4435
4436 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4437 do { \
4438 /* If the target wants uninitialized const declarations in \
4439 .rdata then don't put them in .comm */ \
4440 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4441 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4442 && (DECL_INITIAL (DECL) == 0 \
4443 || DECL_INITIAL (DECL) == error_mark_node)) \
4444 { \
4445 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4446 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4447 \
4448 READONLY_DATA_SECTION (); \
4449 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4450 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4451 (SIZE)); \
4452 } \
4453 else \
4454 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4455 (SIZE)); \
4456 } while (0)
4457
4458
4459 /* This says how to define a local common symbol (ie, not visible to
4460 linker). */
4461
4462 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4463 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4464
4465
4466 /* This says how to output an external. It would be possible not to
4467 output anything and let undefined symbol become external. However
4468 the assembler uses length information on externals to allocate in
4469 data/sdata bss/sbss, thereby saving exec time. */
4470
4471 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4472 mips_output_external(STREAM,DECL,NAME)
4473
4474 /* This says what to print at the end of the assembly file */
4475 #undef ASM_FILE_END
4476 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4477
4478
4479 /* Play switch file games if we're optimizing the global pointer. */
4480
4481 #undef TEXT_SECTION
4482 #define TEXT_SECTION() \
4483 do { \
4484 extern FILE *asm_out_text_file; \
4485 if (TARGET_FILE_SWITCHING) \
4486 asm_out_file = asm_out_text_file; \
4487 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4488 fputc ('\n', asm_out_file); \
4489 } while (0)
4490
4491
4492 /* This is how to declare a function name. The actual work of
4493 emitting the label is moved to function_prologue, so that we can
4494 get the line number correctly emitted before the .ent directive,
4495 and after any .file directives. */
4496
4497 #undef ASM_DECLARE_FUNCTION_NAME
4498 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4499 HALF_PIC_DECLARE (NAME)
4500
4501 /* This is how to output an internal numbered label where
4502 PREFIX is the class of label and NUM is the number within the class. */
4503
4504 #undef ASM_OUTPUT_INTERNAL_LABEL
4505 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4506 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4507
4508 /* This is how to store into the string LABEL
4509 the symbol_ref name of an internal numbered label where
4510 PREFIX is the class of label and NUM is the number within the class.
4511 This is suitable for output with `assemble_name'. */
4512
4513 #undef ASM_GENERATE_INTERNAL_LABEL
4514 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4515 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4516
4517 /* This is how to output an element of a case-vector that is absolute. */
4518
4519 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4520 fprintf (STREAM, "\t%s\t%sL%d\n", \
4521 Pmode == DImode ? ".dword" : ".word", \
4522 LOCAL_LABEL_PREFIX, \
4523 VALUE)
4524
4525 /* This is how to output an element of a case-vector that is relative.
4526 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4527 TARGET_EMBEDDED_PIC). */
4528
4529 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4530 do { \
4531 if (TARGET_MIPS16) \
4532 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4533 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4534 else if (TARGET_EMBEDDED_PIC) \
4535 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4536 Pmode == DImode ? ".dword" : ".word", \
4537 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4538 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4539 fprintf (STREAM, "\t%s\t%sL%d\n", \
4540 Pmode == DImode ? ".gpdword" : ".gpword", \
4541 LOCAL_LABEL_PREFIX, VALUE); \
4542 else \
4543 fprintf (STREAM, "\t%s\t%sL%d\n", \
4544 Pmode == DImode ? ".dword" : ".word", \
4545 LOCAL_LABEL_PREFIX, VALUE); \
4546 } while (0)
4547
4548 /* When generating embedded PIC or mips16 code we want to put the jump
4549 table in the .text section. In all other cases, we want to put the
4550 jump table in the .rdata section. Unfortunately, we can't use
4551 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4552 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4553 section if appropriate. */
4554 #undef ASM_OUTPUT_CASE_LABEL
4555 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4556 do { \
4557 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4558 function_section (current_function_decl); \
4559 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4560 } while (0)
4561
4562 /* This is how to output an assembler line
4563 that says to advance the location counter
4564 to a multiple of 2**LOG bytes. */
4565
4566 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4567 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4568
4569 /* This is how to output an assembler line to advance the location
4570 counter by SIZE bytes. */
4571
4572 #undef ASM_OUTPUT_SKIP
4573 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4574 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4575
4576 /* This is how to output a string. */
4577 #undef ASM_OUTPUT_ASCII
4578 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4579 mips_output_ascii (STREAM, STRING, LEN)
4580
4581 /* Handle certain cpp directives used in header files on sysV. */
4582 #define SCCS_DIRECTIVE
4583
4584 /* Output #ident as a in the read-only data section. */
4585 #undef ASM_OUTPUT_IDENT
4586 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4587 { \
4588 const char *p = STRING; \
4589 int size = strlen (p) + 1; \
4590 rdata_section (); \
4591 assemble_string (p, size); \
4592 }
4593 \f
4594 /* Default to -G 8 */
4595 #ifndef MIPS_DEFAULT_GVALUE
4596 #define MIPS_DEFAULT_GVALUE 8
4597 #endif
4598
4599 /* Define the strings to put out for each section in the object file. */
4600 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4601 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4602 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4603 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4604 #undef READONLY_DATA_SECTION
4605 #define READONLY_DATA_SECTION rdata_section
4606 #define SMALL_DATA_SECTION sdata_section
4607
4608 /* What other sections we support other than the normal .data/.text. */
4609
4610 #undef EXTRA_SECTIONS
4611 #define EXTRA_SECTIONS in_sdata, in_rdata
4612
4613 /* Define the additional functions to select our additional sections. */
4614
4615 /* on the MIPS it is not a good idea to put constants in the text
4616 section, since this defeats the sdata/data mechanism. This is
4617 especially true when -O is used. In this case an effort is made to
4618 address with faster (gp) register relative addressing, which can
4619 only get at sdata and sbss items (there is no stext !!) However,
4620 if the constant is too large for sdata, and it's readonly, it
4621 will go into the .rdata section. */
4622
4623 #undef EXTRA_SECTION_FUNCTIONS
4624 #define EXTRA_SECTION_FUNCTIONS \
4625 void \
4626 sdata_section () \
4627 { \
4628 if (in_section != in_sdata) \
4629 { \
4630 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4631 in_section = in_sdata; \
4632 } \
4633 } \
4634 \
4635 void \
4636 rdata_section () \
4637 { \
4638 if (in_section != in_rdata) \
4639 { \
4640 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4641 in_section = in_rdata; \
4642 } \
4643 }
4644
4645 /* Given a decl node or constant node, choose the section to output it in
4646 and select that section. */
4647
4648 #undef SELECT_RTX_SECTION
4649 #define SELECT_RTX_SECTION(MODE, RTX, ALIGN) \
4650 mips_select_rtx_section (MODE, RTX)
4651
4652 #undef SELECT_SECTION
4653 #define SELECT_SECTION(DECL, RELOC, ALIGN) \
4654 mips_select_section (DECL, RELOC)
4655
4656 \f
4657 /* Store in OUTPUT a string (made with alloca) containing
4658 an assembler-name for a local static variable named NAME.
4659 LABELNO is an integer which is different for each call. */
4660
4661 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4662 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4663 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4664
4665 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4666 do \
4667 { \
4668 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4669 TARGET_64BIT ? "dsubu" : "subu", \
4670 reg_names[STACK_POINTER_REGNUM], \
4671 reg_names[STACK_POINTER_REGNUM], \
4672 TARGET_64BIT ? "sd" : "sw", \
4673 reg_names[REGNO], \
4674 reg_names[STACK_POINTER_REGNUM]); \
4675 } \
4676 while (0)
4677
4678 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4679 do \
4680 { \
4681 if (! set_noreorder) \
4682 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4683 \
4684 dslots_load_total++; \
4685 dslots_load_filled++; \
4686 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4687 TARGET_64BIT ? "ld" : "lw", \
4688 reg_names[REGNO], \
4689 reg_names[STACK_POINTER_REGNUM], \
4690 TARGET_64BIT ? "daddu" : "addu", \
4691 reg_names[STACK_POINTER_REGNUM], \
4692 reg_names[STACK_POINTER_REGNUM]); \
4693 \
4694 if (! set_noreorder) \
4695 fprintf (STREAM, "\t.set\treorder\n"); \
4696 } \
4697 while (0)
4698
4699 /* How to start an assembler comment.
4700 The leading space is important (the mips native assembler requires it). */
4701 #ifndef ASM_COMMENT_START
4702 #define ASM_COMMENT_START " #"
4703 #endif
4704 \f
4705
4706 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4707 and mips-tdump.c to print them out.
4708
4709 These must match the corresponding definitions in gdb/mipsread.c.
4710 Unfortunately, gcc and gdb do not currently share any directories. */
4711
4712 #define CODE_MASK 0x8F300
4713 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4714 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4715 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4716
4717 \f
4718 /* Default definitions for size_t and ptrdiff_t. */
4719
4720 #ifndef SIZE_TYPE
4721 #define NO_BUILTIN_SIZE_TYPE
4722 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4723 #endif
4724
4725 #ifndef PTRDIFF_TYPE
4726 #define NO_BUILTIN_PTRDIFF_TYPE
4727 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4728 #endif
4729
4730 /* See mips_expand_prologue's use of loadgp for when this should be
4731 true. */
4732
4733 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4734 && mips_abi != ABI_32 \
4735 && mips_abi != ABI_O64)
4736 \f
4737 /* In mips16 mode, we need to look through the function to check for
4738 PC relative loads that are out of range. */
4739 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4740
4741 /* We need to use a special set of functions to handle hard floating
4742 point code in mips16 mode. */
4743
4744 #ifndef INIT_SUBTARGET_OPTABS
4745 #define INIT_SUBTARGET_OPTABS
4746 #endif
4747
4748 #define INIT_TARGET_OPTABS \
4749 do \
4750 { \
4751 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4752 INIT_SUBTARGET_OPTABS; \
4753 else \
4754 { \
4755 add_optab->handlers[(int) SFmode].libfunc = \
4756 init_one_libfunc ("__mips16_addsf3"); \
4757 sub_optab->handlers[(int) SFmode].libfunc = \
4758 init_one_libfunc ("__mips16_subsf3"); \
4759 smul_optab->handlers[(int) SFmode].libfunc = \
4760 init_one_libfunc ("__mips16_mulsf3"); \
4761 sdiv_optab->handlers[(int) SFmode].libfunc = \
4762 init_one_libfunc ("__mips16_divsf3"); \
4763 \
4764 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4765 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4766 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4767 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4768 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4769 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4770 \
4771 floatsisf_libfunc = \
4772 init_one_libfunc ("__mips16_floatsisf"); \
4773 fixsfsi_libfunc = \
4774 init_one_libfunc ("__mips16_fixsfsi"); \
4775 \
4776 if (TARGET_DOUBLE_FLOAT) \
4777 { \
4778 add_optab->handlers[(int) DFmode].libfunc = \
4779 init_one_libfunc ("__mips16_adddf3"); \
4780 sub_optab->handlers[(int) DFmode].libfunc = \
4781 init_one_libfunc ("__mips16_subdf3"); \
4782 smul_optab->handlers[(int) DFmode].libfunc = \
4783 init_one_libfunc ("__mips16_muldf3"); \
4784 sdiv_optab->handlers[(int) DFmode].libfunc = \
4785 init_one_libfunc ("__mips16_divdf3"); \
4786 \
4787 extendsfdf2_libfunc = \
4788 init_one_libfunc ("__mips16_extendsfdf2"); \
4789 truncdfsf2_libfunc = \
4790 init_one_libfunc ("__mips16_truncdfsf2"); \
4791 \
4792 eqdf2_libfunc = \
4793 init_one_libfunc ("__mips16_eqdf2"); \
4794 nedf2_libfunc = \
4795 init_one_libfunc ("__mips16_nedf2"); \
4796 gtdf2_libfunc = \
4797 init_one_libfunc ("__mips16_gtdf2"); \
4798 gedf2_libfunc = \
4799 init_one_libfunc ("__mips16_gedf2"); \
4800 ltdf2_libfunc = \
4801 init_one_libfunc ("__mips16_ltdf2"); \
4802 ledf2_libfunc = \
4803 init_one_libfunc ("__mips16_ledf2"); \
4804 \
4805 floatsidf_libfunc = \
4806 init_one_libfunc ("__mips16_floatsidf"); \
4807 fixdfsi_libfunc = \
4808 init_one_libfunc ("__mips16_fixdfsi"); \
4809 } \
4810 } \
4811 } \
4812 while (0)
GNU Compiler Collection
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