1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-95, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
37 #include "insn-attr.h"
38 #include "insn-codes.h"
42 #undef MAX /* sys/param.h may also define these */
47 #include <sys/types.h>
60 #if defined(USG) || defined(NO_STAB_H)
61 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
63 #include <stab.h> /* On BSD, use the system's stab.h. */
67 #define STAB_CODE_TYPE enum __stab_debug_code
69 #define STAB_CODE_TYPE int
74 extern char *getenv ();
75 extern char *mktemp ();
77 extern rtx
adj_offsettable_operand ();
78 extern rtx
copy_to_reg ();
81 extern tree
lookup_name ();
82 extern void pfatal_with_name ();
83 extern void warning ();
85 extern FILE *asm_out_file
;
87 /* Enumeration for all of the relational tests, so that we can build
88 arrays indexed by the test type, and not worry about the order
105 /* Global variables for machine-dependent things. */
107 /* Threshold for data being put into the small data/bss area, instead
108 of the normal data area (references to the small data/bss area take
109 1 instruction, and use the global pointer, references to the normal
110 data area takes 2 instructions). */
111 int mips_section_threshold
= -1;
113 /* Count the number of .file directives, so that .loc is up to date. */
114 int num_source_filenames
= 0;
116 /* Count the number of sdb related labels are generated (to find block
117 start and end boundaries). */
118 int sdb_label_count
= 0;
120 /* Next label # for each statement for Silicon Graphics IRIS systems. */
123 /* Non-zero if inside of a function, because the stupid MIPS asm can't
124 handle .files inside of functions. */
125 int inside_function
= 0;
127 /* Files to separate the text and the data output, so that all of the data
128 can be emitted before the text, which will mean that the assembler will
129 generate smaller code, based on the global pointer. */
130 FILE *asm_out_data_file
;
131 FILE *asm_out_text_file
;
133 /* Linked list of all externals that are to be emitted when optimizing
134 for the global pointer if they haven't been declared by the end of
135 the program with an appropriate .comm or initialization. */
138 struct extern_list
*next
; /* next external */
139 char *name
; /* name of the external */
140 int size
; /* size in bytes */
143 /* Name of the file containing the current function. */
144 char *current_function_file
= "";
146 /* Warning given that Mips ECOFF can't support changing files
147 within a function. */
148 int file_in_function_warning
= FALSE
;
150 /* Whether to suppress issuing .loc's because the user attempted
151 to change the filename within a function. */
152 int ignore_line_number
= FALSE
;
154 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
160 /* The next branch instruction is a branch likely, not branch normal. */
161 int mips_branch_likely
;
163 /* Count of delay slots and how many are filled. */
164 int dslots_load_total
;
165 int dslots_load_filled
;
166 int dslots_jump_total
;
167 int dslots_jump_filled
;
169 /* # of nops needed by previous insn */
170 int dslots_number_nops
;
172 /* Number of 1/2/3 word references to data items (ie, not jal's). */
175 /* registers to check for load delay */
176 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
178 /* Cached operands, and operator to compare for use in set/branch on
182 /* what type of branch to use */
183 enum cmp_type branch_type
;
185 /* Number of previously seen half-pic pointers and references. */
186 static int prev_half_pic_ptrs
= 0;
187 static int prev_half_pic_refs
= 0;
189 /* which cpu are we scheduling for */
190 enum processor_type mips_cpu
;
192 /* which instruction set architecture to use. */
195 #ifdef MIPS_ABI_DEFAULT
196 /* which ABI to use. This is defined to a constant in mips.h if the target
197 doesn't support multiple ABIs. */
198 enum mips_abi_type mips_abi
;
201 /* Strings to hold which cpu and instruction set architecture to use. */
202 char *mips_cpu_string
; /* for -mcpu=<xxx> */
203 char *mips_isa_string
; /* for -mips{1,2,3,4} */
204 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64,eabi} */
206 /* If TRUE, we split addresses into their high and low parts in the RTL. */
207 int mips_split_addresses
;
209 /* Generating calls to position independent functions? */
210 enum mips_abicalls_type mips_abicalls
;
212 /* High and low marks for floating point values which we will accept
213 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
214 initialized in override_options. */
215 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
217 /* Array giving truth value on whether or not a given hard register
218 can support a given mode. */
219 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
221 /* Current frame information calculated by compute_frame_size. */
222 struct mips_frame_info current_frame_info
;
224 /* Zero structure to initialize current_frame_info. */
225 struct mips_frame_info zero_frame_info
;
227 /* Temporary filename used to buffer .text until end of program
229 static char *temp_filename
;
231 /* Pseudo-reg holding the address of the current function when
232 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
233 by mips_finalize_pic if it was created. */
234 rtx embedded_pic_fnaddr_rtx
;
236 /* List of all MIPS punctuation characters used by print_operand. */
237 char mips_print_operand_punct
[256];
239 /* Map GCC register number to debugger register number. */
240 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
242 /* Buffer to use to enclose a load/store operation with %{ %} to
243 turn on .set volatile. */
244 static char volatile_buffer
[60];
246 /* Hardware names for the registers. If -mrnames is used, this
247 will be overwritten with mips_sw_reg_names. */
249 char mips_reg_names
[][8] =
251 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
252 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
253 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
254 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
255 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
256 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
257 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
258 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
259 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
260 "$fcc5","$fcc6","$fcc7","$rap"
263 /* Mips software names for the registers, used to overwrite the
264 mips_reg_names array. */
266 char mips_sw_reg_names
[][8] =
268 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
269 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
270 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
271 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
272 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
273 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
274 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
275 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
276 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
277 "$fcc5","$fcc6","$fcc7","$rap"
280 /* Map hard register number to register class */
281 enum reg_class mips_regno_to_class
[] =
283 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
284 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
290 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
291 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
292 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
298 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
299 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
300 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
301 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
304 /* Map register constraint character to register class. */
305 enum reg_class mips_char_to_class
[256] =
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
368 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
369 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
370 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
374 /* Return truth value of whether OP can be used as an operands
375 where a register or 16 bit unsigned integer is needed. */
378 uns_arith_operand (op
, mode
)
380 enum machine_mode mode
;
382 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
385 return register_operand (op
, mode
);
388 /* Return truth value of whether OP can be used as an operands
389 where a 16 bit integer is needed */
392 arith_operand (op
, mode
)
394 enum machine_mode mode
;
396 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
399 return register_operand (op
, mode
);
402 /* Return truth value of whether OP can be used as an operand in a two
403 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
406 arith32_operand (op
, mode
)
408 enum machine_mode mode
;
410 if (GET_CODE (op
) == CONST_INT
)
413 return register_operand (op
, mode
);
416 /* Return truth value of whether OP is a integer which fits in 16 bits */
421 enum machine_mode mode
;
423 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
426 /* Return truth value of whether OP is a 32 bit integer which is too big to
427 be loaded with one instruction. */
432 enum machine_mode mode
;
436 if (GET_CODE (op
) != CONST_INT
)
440 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
443 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
446 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
452 /* Return truth value of whether OP is a register or the constant 0. */
455 reg_or_0_operand (op
, mode
)
457 enum machine_mode mode
;
459 switch (GET_CODE (op
))
465 return (INTVAL (op
) == 0);
468 if (op
!= CONST0_RTX (mode
))
475 return register_operand (op
, mode
);
481 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
484 mips_const_double_ok (op
, mode
)
486 enum machine_mode mode
;
490 if (GET_CODE (op
) != CONST_DOUBLE
)
493 if (mode
== VOIDmode
)
496 if (mode
!= SFmode
&& mode
!= DFmode
)
499 if (op
== CONST0_RTX (mode
))
502 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
503 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
506 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
508 if (REAL_VALUE_ISNAN (d
))
511 if (REAL_VALUE_NEGATIVE (d
))
512 d
= REAL_VALUE_NEGATE (d
);
516 if (REAL_VALUES_LESS (d
, dfhigh
)
517 && REAL_VALUES_LESS (dflow
, d
))
522 if (REAL_VALUES_LESS (d
, sfhigh
)
523 && REAL_VALUES_LESS (sflow
, d
))
530 /* Accept the floating point constant 1 in the appropriate mode. */
533 const_float_1_operand (op
, mode
)
535 enum machine_mode mode
;
538 static REAL_VALUE_TYPE onedf
;
539 static REAL_VALUE_TYPE onesf
;
540 static int one_initialized
;
542 if (GET_CODE (op
) != CONST_DOUBLE
543 || mode
!= GET_MODE (op
)
544 || (mode
!= DFmode
&& mode
!= SFmode
))
547 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
549 /* We only initialize these values if we need them, since we will
550 never get called unless mips_isa >= 4. */
551 if (! one_initialized
)
553 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
554 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
555 one_initialized
= TRUE
;
559 return REAL_VALUES_EQUAL (d
, onedf
);
561 return REAL_VALUES_EQUAL (d
, onesf
);
564 /* Return truth value if a memory operand fits in a single instruction
565 (ie, register + small offset). */
568 simple_memory_operand (op
, mode
)
570 enum machine_mode mode
;
572 rtx addr
, plus0
, plus1
;
574 /* Eliminate non-memory operations */
575 if (GET_CODE (op
) != MEM
)
578 /* dword operations really put out 2 instructions, so eliminate them. */
579 /* ??? This isn't strictly correct. It is OK to accept multiword modes
580 here, since the length attributes are being set correctly, but only
581 if the address is offsettable. LO_SUM is not offsettable. */
582 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
585 /* Decode the address now. */
587 switch (GET_CODE (addr
))
597 return SMALL_INT (op
);
600 plus0
= XEXP (addr
, 0);
601 plus1
= XEXP (addr
, 1);
602 if (GET_CODE (plus0
) == REG
603 && GET_CODE (plus1
) == CONST_INT
604 && SMALL_INT (plus1
))
607 else if (GET_CODE (plus1
) == REG
608 && GET_CODE (plus0
) == CONST_INT
609 && SMALL_INT (plus0
))
616 /* We used to allow small symbol refs here (ie, stuff in .sdata
617 or .sbss), but this causes some bugs in G++. Also, it won't
618 interfere if the MIPS linker rewrites the store instruction
619 because the function is PIC. */
621 case LABEL_REF
: /* never gp relative */
625 /* If -G 0, we can never have a GP relative memory operation.
626 Also, save some time if not optimizing. */
631 rtx offset
= const0_rtx
;
632 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
633 if (GET_CODE (op
) != SYMBOL_REF
)
636 /* let's be paranoid.... */
637 if (! SMALL_INT (offset
))
643 return SYMBOL_REF_FLAG (addr
);
650 /* Return true if the code of this rtx pattern is EQ or NE. */
653 equality_op (op
, mode
)
655 enum machine_mode mode
;
657 if (mode
!= GET_MODE (op
))
660 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
663 /* Return true if the code is a relational operations (EQ, LE, etc.) */
668 enum machine_mode mode
;
670 if (mode
!= GET_MODE (op
))
673 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
676 /* Return true if the operand is either the PC or a label_ref. */
679 pc_or_label_operand (op
, mode
)
681 enum machine_mode mode
;
686 if (GET_CODE (op
) == LABEL_REF
)
692 /* Test for a valid operand for a call instruction.
693 Don't allow the arg pointer register or virtual regs
694 since they may change into reg + const, which the patterns
698 call_insn_operand (op
, mode
)
700 enum machine_mode mode
;
702 if (CONSTANT_ADDRESS_P (op
)
703 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
704 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
705 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
710 /* Return true if OPERAND is valid as a source operand for a move
714 move_operand (op
, mode
)
716 enum machine_mode mode
;
718 /* Accept any general operand after reload has started; doing so
719 avoids losing if reload does an in-place replacement of a register
720 with a SYMBOL_REF or CONST. */
721 return (general_operand (op
, mode
)
722 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
723 || reload_in_progress
724 || reload_completed
));
729 /* Return true if OPERAND is valid as a source operand for movdi.
730 This accepts not only general_operand, but also sign extended
731 constants and registers. We need to accept sign extended constants
732 in case a sign extended register which is used in an expression,
733 and is equivalent to a constant, is spilled. */
736 movdi_operand (op
, mode
)
738 enum machine_mode mode
;
742 && GET_CODE (op
) == SIGN_EXTEND
743 && GET_MODE (op
) == DImode
744 && (GET_MODE (XEXP (op
, 0)) == SImode
745 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
746 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
747 && (register_operand (XEXP (op
, 0), SImode
)
748 || immediate_operand (XEXP (op
, 0), SImode
)))
751 return general_operand (op
, mode
);
754 /* Like register_operand, but when in 64 bit mode also accept a sign
755 extend of a 32 bit register, since the value is known to be already
759 se_register_operand (op
, mode
)
761 enum machine_mode mode
;
765 && GET_CODE (op
) == SIGN_EXTEND
766 && GET_MODE (op
) == DImode
767 && GET_MODE (XEXP (op
, 0)) == SImode
768 && register_operand (XEXP (op
, 0), SImode
))
771 return register_operand (op
, mode
);
774 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
775 extend of a 32 bit register, since the value is known to be already
779 se_reg_or_0_operand (op
, mode
)
781 enum machine_mode mode
;
785 && GET_CODE (op
) == SIGN_EXTEND
786 && GET_MODE (op
) == DImode
787 && GET_MODE (XEXP (op
, 0)) == SImode
788 && register_operand (XEXP (op
, 0), SImode
))
791 return reg_or_0_operand (op
, mode
);
794 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
795 extend of a 32 bit register, since the value is known to be already
799 se_uns_arith_operand (op
, mode
)
801 enum machine_mode mode
;
805 && GET_CODE (op
) == SIGN_EXTEND
806 && GET_MODE (op
) == DImode
807 && GET_MODE (XEXP (op
, 0)) == SImode
808 && register_operand (XEXP (op
, 0), SImode
))
811 return uns_arith_operand (op
, mode
);
814 /* Like arith_operand, but when in 64 bit mode also accept a sign
815 extend of a 32 bit register, since the value is known to be already
819 se_arith_operand (op
, mode
)
821 enum machine_mode mode
;
825 && GET_CODE (op
) == SIGN_EXTEND
826 && GET_MODE (op
) == DImode
827 && GET_MODE (XEXP (op
, 0)) == SImode
828 && register_operand (XEXP (op
, 0), SImode
))
831 return arith_operand (op
, mode
);
834 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
835 extend of a 32 bit register, since the value is known to be already
839 se_nonmemory_operand (op
, mode
)
841 enum machine_mode mode
;
845 && GET_CODE (op
) == SIGN_EXTEND
846 && GET_MODE (op
) == DImode
847 && GET_MODE (XEXP (op
, 0)) == SImode
848 && register_operand (XEXP (op
, 0), SImode
))
851 return nonmemory_operand (op
, mode
);
854 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
855 sign extend of a 32 bit register, since the value is known to be
856 already sign extended. */
859 se_nonimmediate_operand (op
, mode
)
861 enum machine_mode mode
;
865 && GET_CODE (op
) == SIGN_EXTEND
866 && GET_MODE (op
) == DImode
867 && GET_MODE (XEXP (op
, 0)) == SImode
868 && register_operand (XEXP (op
, 0), SImode
))
871 return nonimmediate_operand (op
, mode
);
874 /* Return true if we split the address into high and low parts. */
876 /* ??? We should also handle reg+array somewhere. We get four
877 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
878 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
879 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
880 out of the address, then we have 4 instructions to combine. Perhaps
881 add a 3->2 define_split for combine. */
883 /* ??? We could also split a CONST_INT here if it is a large_int().
884 However, it doesn't seem to be very useful to have %hi(constant).
885 We would be better off by doing the masking ourselves and then putting
886 the explicit high part of the constant in the RTL. This will give better
887 optimization. Also, %hi(constant) needs assembler changes to work.
888 There is already a define_split that does this. */
891 mips_check_split (address
, mode
)
893 enum machine_mode mode
;
895 /* ??? This is the same check used in simple_memory_operand.
896 We use it here because LO_SUM is not offsettable. */
897 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
900 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
901 || (GET_CODE (address
) == CONST
902 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
903 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
904 || GET_CODE (address
) == LABEL_REF
)
910 /* Returns an operand string for the given instruction's delay slot,
911 after updating filled delay slot statistics.
913 We assume that operands[0] is the target register that is set.
915 In order to check the next insn, most of this functionality is moved
916 to FINAL_PRESCAN_INSN, and we just set the global variables that
919 /* ??? This function no longer does anything useful, because final_prescan_insn
920 now will never emit a nop. */
923 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
924 char *ret
; /* normal string to return */
925 enum delay_type type
; /* type of delay */
926 rtx operands
[]; /* operands to use */
927 rtx cur_insn
; /* current insn */
929 register rtx set_reg
;
930 register enum machine_mode mode
;
931 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
932 register int num_nops
;
934 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
937 else if (type
== DELAY_HILO
)
943 /* Make sure that we don't put nop's after labels. */
944 next_insn
= NEXT_INSN (cur_insn
);
945 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
946 next_insn
= NEXT_INSN (next_insn
);
948 dslots_load_total
+= num_nops
;
949 if (TARGET_DEBUG_F_MODE
951 || type
== DELAY_NONE
952 || operands
== (rtx
*)0
953 || cur_insn
== (rtx
)0
954 || next_insn
== (rtx
)0
955 || GET_CODE (next_insn
) == CODE_LABEL
956 || (set_reg
= operands
[0]) == (rtx
)0)
958 dslots_number_nops
= 0;
959 mips_load_reg
= (rtx
)0;
960 mips_load_reg2
= (rtx
)0;
961 mips_load_reg3
= (rtx
)0;
962 mips_load_reg4
= (rtx
)0;
966 set_reg
= operands
[0];
967 if (set_reg
== (rtx
)0)
970 while (GET_CODE (set_reg
) == SUBREG
)
971 set_reg
= SUBREG_REG (set_reg
);
973 mode
= GET_MODE (set_reg
);
974 dslots_number_nops
= num_nops
;
975 mips_load_reg
= set_reg
;
976 if (GET_MODE_SIZE (mode
)
977 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
978 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
982 if (type
== DELAY_HILO
)
984 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
985 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
997 /* Determine whether a memory reference takes one (based off of the GP pointer),
998 two (normal), or three (label + reg) instructions, and bump the appropriate
999 counter for -mstats. */
1002 mips_count_memory_refs (op
, num
)
1008 rtx addr
, plus0
, plus1
;
1009 enum rtx_code code0
, code1
;
1012 if (TARGET_DEBUG_B_MODE
)
1014 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1018 /* Skip MEM if passed, otherwise handle movsi of address. */
1019 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1021 /* Loop, going through the address RTL */
1025 switch (GET_CODE (addr
))
1036 plus0
= XEXP (addr
, 0);
1037 plus1
= XEXP (addr
, 1);
1038 code0
= GET_CODE (plus0
);
1039 code1
= GET_CODE (plus1
);
1049 if (code0
== CONST_INT
)
1064 if (code1
== CONST_INT
)
1071 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1078 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1088 n_words
= 2; /* always 2 words */
1092 addr
= XEXP (addr
, 0);
1097 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1106 n_words
+= additional
;
1110 num_refs
[n_words
-1] += num
;
1114 /* Return RTL for the offset from the current function to the
1118 embedded_pic_offset (x
)
1121 if (embedded_pic_fnaddr_rtx
== NULL
)
1125 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1127 /* Output code at function start to initialize the pseudo-reg. */
1128 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1129 inline functions, because it is called after RTL for the function
1130 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1131 does not get copied, and ends up not matching the rest of the RTL.
1132 This solution works, but means that we get unnecessary code to
1133 initialize this value every time a function is inlined into another
1136 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1137 XEXP (DECL_RTL (current_function_decl
), 0)));
1138 seq
= gen_sequence ();
1140 push_topmost_sequence ();
1141 emit_insn_after (seq
, get_insns ());
1142 pop_topmost_sequence ();
1145 return gen_rtx (CONST
, Pmode
,
1146 gen_rtx (MINUS
, Pmode
, x
,
1147 XEXP (DECL_RTL (current_function_decl
), 0)));
1150 /* Return the appropriate instructions to move one operand to another. */
1153 mips_move_1word (operands
, insn
, unsignedp
)
1159 rtx op0
= operands
[0];
1160 rtx op1
= operands
[1];
1161 enum rtx_code code0
= GET_CODE (op0
);
1162 enum rtx_code code1
= GET_CODE (op1
);
1163 enum machine_mode mode
= GET_MODE (op0
);
1164 int subreg_word0
= 0;
1165 int subreg_word1
= 0;
1166 enum delay_type delay
= DELAY_NONE
;
1168 while (code0
== SUBREG
)
1170 subreg_word0
+= SUBREG_WORD (op0
);
1171 op0
= SUBREG_REG (op0
);
1172 code0
= GET_CODE (op0
);
1175 while (code1
== SUBREG
)
1177 subreg_word1
+= SUBREG_WORD (op1
);
1178 op1
= SUBREG_REG (op1
);
1179 code1
= GET_CODE (op1
);
1182 /* For our purposes, a condition code mode is the same as SImode. */
1188 int regno0
= REGNO (op0
) + subreg_word0
;
1192 int regno1
= REGNO (op1
) + subreg_word1
;
1194 /* Just in case, don't do anything for assigning a register
1195 to itself, unless we are filling a delay slot. */
1196 if (regno0
== regno1
&& set_nomacro
== 0)
1199 else if (GP_REG_P (regno0
))
1201 if (GP_REG_P (regno1
))
1202 ret
= "move\t%0,%1";
1204 else if (MD_REG_P (regno1
))
1207 if (regno1
!= HILO_REGNUM
)
1213 else if (ST_REG_P (regno1
) && mips_isa
>= 4)
1214 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1219 if (FP_REG_P (regno1
))
1220 ret
= "mfc1\t%0,%1";
1222 else if (regno1
== FPSW_REGNUM
&& mips_isa
< 4)
1223 ret
= "cfc1\t%0,$31";
1227 else if (FP_REG_P (regno0
))
1229 if (GP_REG_P (regno1
))
1232 ret
= "mtc1\t%1,%0";
1235 if (FP_REG_P (regno1
))
1236 ret
= "mov.s\t%0,%1";
1239 else if (MD_REG_P (regno0
))
1241 if (GP_REG_P (regno1
))
1244 if (regno0
!= HILO_REGNUM
)
1249 else if (regno0
== FPSW_REGNUM
&& mips_isa
< 4)
1251 if (GP_REG_P (regno1
))
1254 ret
= "ctc1\t%0,$31";
1259 else if (code1
== MEM
)
1264 mips_count_memory_refs (op1
, 1);
1266 if (GP_REG_P (regno0
))
1268 /* For loads, use the mode of the memory item, instead of the
1269 target, so zero/sign extend can use this code as well. */
1270 switch (GET_MODE (op1
))
1279 ret
= ((unsignedp
&& TARGET_64BIT
)
1284 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1287 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1292 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1295 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1297 int i
= strlen (ret
);
1298 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1301 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1302 ret
= volatile_buffer
;
1306 else if (code1
== CONST_INT
1307 || (code1
== CONST_DOUBLE
1308 && GET_MODE (op1
) == VOIDmode
))
1310 if (code1
== CONST_DOUBLE
)
1312 /* This can happen when storing constants into long long
1313 bitfields. Just store the least significant word of
1315 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1318 if (INTVAL (op1
) == 0)
1320 if (GP_REG_P (regno0
))
1321 ret
= "move\t%0,%z1";
1323 else if (FP_REG_P (regno0
))
1326 ret
= "mtc1\t%z1,%0";
1329 else if (MD_REG_P (regno0
))
1336 else if (GP_REG_P (regno0
))
1337 /* Don't use X format, because that will give out of range
1338 numbers for 64 bit host and 32 bit target. */
1339 ret
= "li\t%0,%1\t\t\t# %X1";
1342 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1344 if (op1
== CONST0_RTX (SFmode
))
1346 if (GP_REG_P (regno0
))
1347 ret
= "move\t%0,%.";
1349 else if (FP_REG_P (regno0
))
1352 ret
= "mtc1\t%.,%0";
1359 ret
= "li.s\t%0,%1";
1363 else if (code1
== LABEL_REF
)
1366 mips_count_memory_refs (op1
, 1);
1371 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1373 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1375 rtx offset
= const0_rtx
;
1377 if (GET_CODE (op1
) == CONST
)
1378 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1380 if (GET_CODE (op1
) == SYMBOL_REF
)
1382 operands
[2] = HALF_PIC_PTR (op1
);
1385 mips_count_memory_refs (operands
[2], 1);
1387 if (INTVAL (offset
) == 0)
1390 ret
= (unsignedp
&& TARGET_64BIT
1396 dslots_load_total
++;
1397 operands
[3] = offset
;
1398 if (unsignedp
&& TARGET_64BIT
)
1399 ret
= (SMALL_INT (offset
))
1400 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1401 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1403 ret
= (SMALL_INT (offset
))
1404 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1405 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1412 mips_count_memory_refs (op1
, 1);
1418 else if (code1
== PLUS
)
1420 rtx add_op0
= XEXP (op1
, 0);
1421 rtx add_op1
= XEXP (op1
, 1);
1423 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1425 add_op0
= XEXP (op1
, 1); /* reverse operands */
1426 add_op1
= XEXP (op1
, 0);
1429 operands
[2] = add_op0
;
1430 operands
[3] = add_op1
;
1431 ret
= "add%:\t%0,%2,%3";
1434 else if (code1
== HIGH
)
1436 operands
[1] = XEXP (op1
, 0);
1437 ret
= "lui\t%0,%%hi(%1)";
1441 else if (code0
== MEM
)
1444 mips_count_memory_refs (op0
, 1);
1448 int regno1
= REGNO (op1
) + subreg_word1
;
1450 if (GP_REG_P (regno1
))
1455 case SFmode
: ret
= "sw\t%1,%0"; break;
1456 case SImode
: ret
= "sw\t%1,%0"; break;
1457 case HImode
: ret
= "sh\t%1,%0"; break;
1458 case QImode
: ret
= "sb\t%1,%0"; break;
1462 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1466 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1471 case SFmode
: ret
= "sw\t%z1,%0"; break;
1472 case SImode
: ret
= "sw\t%z1,%0"; break;
1473 case HImode
: ret
= "sh\t%z1,%0"; break;
1474 case QImode
: ret
= "sb\t%z1,%0"; break;
1478 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1483 case SFmode
: ret
= "sw\t%.,%0"; break;
1484 case SImode
: ret
= "sw\t%.,%0"; break;
1485 case HImode
: ret
= "sh\t%.,%0"; break;
1486 case QImode
: ret
= "sb\t%.,%0"; break;
1490 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1492 int i
= strlen (ret
);
1493 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1496 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1497 ret
= volatile_buffer
;
1501 if (ret
== (char *)0)
1503 abort_with_insn (insn
, "Bad move");
1507 if (delay
!= DELAY_NONE
)
1508 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1514 /* Return the appropriate instructions to move 2 words */
1517 mips_move_2words (operands
, insn
)
1522 rtx op0
= operands
[0];
1523 rtx op1
= operands
[1];
1524 enum rtx_code code0
= GET_CODE (operands
[0]);
1525 enum rtx_code code1
= GET_CODE (operands
[1]);
1526 int subreg_word0
= 0;
1527 int subreg_word1
= 0;
1528 enum delay_type delay
= DELAY_NONE
;
1530 while (code0
== SUBREG
)
1532 subreg_word0
+= SUBREG_WORD (op0
);
1533 op0
= SUBREG_REG (op0
);
1534 code0
= GET_CODE (op0
);
1537 if (code1
== SIGN_EXTEND
)
1539 op1
= XEXP (op1
, 0);
1540 code1
= GET_CODE (op1
);
1543 while (code1
== SUBREG
)
1545 subreg_word1
+= SUBREG_WORD (op1
);
1546 op1
= SUBREG_REG (op1
);
1547 code1
= GET_CODE (op1
);
1551 if (GET_CODE (operands
[1]) == SIGN_EXTEND
1553 && code1
!= CONST_INT
1554 /* The following three can happen as the result of a questionable
1556 && code1
!= LABEL_REF
1557 && code1
!= SYMBOL_REF
1563 int regno0
= REGNO (op0
) + subreg_word0
;
1567 int regno1
= REGNO (op1
) + subreg_word1
;
1569 /* Just in case, don't do anything for assigning a register
1570 to itself, unless we are filling a delay slot. */
1571 if (regno0
== regno1
&& set_nomacro
== 0)
1574 else if (FP_REG_P (regno0
))
1576 if (FP_REG_P (regno1
))
1577 ret
= "mov.d\t%0,%1";
1585 abort_with_insn (insn
, "Bad move");
1586 #ifdef TARGET_FP_CALL_32
1587 if (FP_CALL_GP_REG_P (regno1
))
1588 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1591 ret
= "dmtc1\t%1,%0";
1594 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1598 else if (FP_REG_P (regno1
))
1604 abort_with_insn (insn
, "Bad move");
1605 #ifdef TARGET_FP_CALL_32
1606 if (FP_CALL_GP_REG_P (regno0
))
1607 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1610 ret
= "dmfc1\t%0,%1";
1613 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1616 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1621 if (regno0
!= HILO_REGNUM
)
1623 else if (regno1
== 0)
1624 ret
= "mtlo\t%.\n\tmthi\t%.";
1627 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1630 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1635 if (regno1
!= HILO_REGNUM
)
1639 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1642 else if (TARGET_64BIT
)
1643 ret
= "move\t%0,%1";
1645 else if (regno0
!= (regno1
+1))
1646 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1649 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1652 else if (code1
== CONST_DOUBLE
)
1654 /* Move zero from $0 unless !TARGET_64BIT and recipient
1655 is 64-bit fp reg, in which case generate a constant. */
1656 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1657 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1659 if (GET_MODE (op1
) == DFmode
)
1662 #ifdef TARGET_FP_CALL_32
1663 if (FP_CALL_GP_REG_P (regno0
))
1665 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1667 split_double (op1
, operands
+ 2, operands
+ 3);
1668 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1671 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1675 ret
= "li.d\t%0,%1";
1678 else if (TARGET_64BIT
)
1683 split_double (op1
, operands
+ 2, operands
+ 3);
1684 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1690 if (GP_REG_P (regno0
))
1692 #ifdef TARGET_FP_CALL_32
1693 && ! FP_CALL_GP_REG_P (regno0
)
1697 : "move\t%0,%.\n\tmove\t%D0,%.";
1699 else if (FP_REG_P (regno0
))
1702 ret
= (TARGET_64BIT
)
1704 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1709 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1711 if (GP_REG_P (regno0
))
1712 ret
= (TARGET_64BIT
)
1714 : "move\t%0,%.\n\tmove\t%D0,%.";
1716 else if (FP_REG_P (regno0
))
1719 ret
= (TARGET_64BIT
)
1723 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1725 else if (MD_REG_P (regno0
))
1728 if (regno0
!= HILO_REGNUM
)
1731 ret
= "mtlo\t%.\n\tmthi\t%.";
1735 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1739 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1740 ret
= "li\t%0,%1\t\t# %X1";
1741 else if (HOST_BITS_PER_WIDE_INT
< 64)
1742 /* We can't use 'X' for negative numbers, because then we won't
1743 get the right value for the upper 32 bits. */
1744 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1745 : "dli\t%0,%X1\t\t# %1");
1747 /* We must use 'X', because otherwise LONG_MIN will print as
1748 a number that the assembler won't accept. */
1749 ret
= "dli\t%0,%X1\t\t# %1";
1751 else if (HOST_BITS_PER_WIDE_INT
< 64)
1753 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1754 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1758 /* We use multiple shifts here, to avoid warnings about out
1759 of range shifts on 32 bit hosts. */
1760 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1761 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1762 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1766 else if (code1
== MEM
)
1771 mips_count_memory_refs (op1
, 2);
1773 if (FP_REG_P (regno0
))
1776 else if (TARGET_64BIT
)
1778 #ifdef TARGET_FP_CALL_32
1779 if (FP_CALL_GP_REG_P (regno0
))
1781 if (offsettable_address_p (FALSE
, SImode
, op1
))
1782 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1784 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1791 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1793 operands
[2] = adj_offsettable_operand (op1
, 4);
1794 if (reg_mentioned_p (op0
, op1
))
1795 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1797 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1800 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1802 int i
= strlen (ret
);
1803 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1806 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1807 ret
= volatile_buffer
;
1811 else if (code1
== LABEL_REF
1812 || code1
== SYMBOL_REF
1816 mips_count_memory_refs (op1
, 2);
1818 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1819 /* We deliberately remove the 'a' from '%1', so that we don't
1820 have to add SIGN_EXTEND support to print_operand_address.
1821 print_operand will just call print_operand_address in this
1822 case, so there is no problem. */
1825 ret
= "dla\t%0,%a1";
1829 else if (code0
== MEM
)
1833 int regno1
= REGNO (op1
) + subreg_word1
;
1835 if (FP_REG_P (regno1
))
1838 else if (TARGET_64BIT
)
1840 #ifdef TARGET_FP_CALL_32
1841 if (FP_CALL_GP_REG_P (regno1
))
1842 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1848 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1850 operands
[2] = adj_offsettable_operand (op0
, 4);
1851 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1855 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1856 || (code1
== CONST_DOUBLE
1857 && op1
== CONST0_RTX (GET_MODE (op1
))))
1859 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1865 operands
[2] = adj_offsettable_operand (op0
, 4);
1866 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1871 mips_count_memory_refs (op0
, 2);
1873 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1875 int i
= strlen (ret
);
1876 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1879 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1880 ret
= volatile_buffer
;
1884 if (ret
== (char *)0)
1886 abort_with_insn (insn
, "Bad move");
1890 if (delay
!= DELAY_NONE
)
1891 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1897 /* Provide the costs of an addressing mode that contains ADDR.
1898 If ADDR is not a valid address, its cost is irrelevant. */
1901 mips_address_cost (addr
)
1904 switch (GET_CODE (addr
))
1917 rtx offset
= const0_rtx
;
1918 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1919 if (GET_CODE (addr
) == LABEL_REF
)
1922 if (GET_CODE (addr
) != SYMBOL_REF
)
1925 if (! SMALL_INT (offset
))
1931 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1935 register rtx plus0
= XEXP (addr
, 0);
1936 register rtx plus1
= XEXP (addr
, 1);
1938 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1940 plus0
= XEXP (addr
, 1);
1941 plus1
= XEXP (addr
, 0);
1944 if (GET_CODE (plus0
) != REG
)
1947 switch (GET_CODE (plus1
))
1953 return (SMALL_INT (plus1
) ? 1 : 2);
1960 return mips_address_cost (plus1
) + 1;
1968 /* Return true if X is an address which needs a temporary register when
1969 reloaded while generating PIC code. */
1972 pic_address_needs_scratch (x
)
1975 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1976 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1977 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1978 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1979 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1985 /* Make normal rtx_code into something we can index from an array */
1987 static enum internal_test
1988 map_test_to_internal_test (test_code
)
1989 enum rtx_code test_code
;
1991 enum internal_test test
= ITEST_MAX
;
1996 case EQ
: test
= ITEST_EQ
; break;
1997 case NE
: test
= ITEST_NE
; break;
1998 case GT
: test
= ITEST_GT
; break;
1999 case GE
: test
= ITEST_GE
; break;
2000 case LT
: test
= ITEST_LT
; break;
2001 case LE
: test
= ITEST_LE
; break;
2002 case GTU
: test
= ITEST_GTU
; break;
2003 case GEU
: test
= ITEST_GEU
; break;
2004 case LTU
: test
= ITEST_LTU
; break;
2005 case LEU
: test
= ITEST_LEU
; break;
2012 /* Generate the code to compare two integer values. The return value is:
2013 (reg:SI xx) The pseudo register the comparison is in
2014 (rtx)0 No register, generate a simple branch.
2016 ??? This is called with result nonzero by the Scond patterns in
2017 mips.md. These patterns are called with a target in the mode of
2018 the Scond instruction pattern. Since this must be a constant, we
2019 must use SImode. This means that if RESULT is non-zero, it will
2020 always be an SImode register, even if TARGET_64BIT is true. We
2021 cope with this by calling convert_move rather than emit_move_insn.
2022 This will sometimes lead to an unnecessary extension of the result;
2034 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2035 enum rtx_code test_code
; /* relational test (EQ, etc) */
2036 rtx result
; /* result to store comp. or 0 if branch */
2037 rtx cmp0
; /* first operand to compare */
2038 rtx cmp1
; /* second operand to compare */
2039 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2040 /* to reverse its test */
2043 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2044 int const_low
; /* low bound of constant we can accept */
2045 int const_high
; /* high bound of constant we can accept */
2046 int const_add
; /* constant to add (convert LE -> LT) */
2047 int reverse_regs
; /* reverse registers in test */
2048 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2049 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2050 int unsignedp
; /* != 0 for unsigned comparisons. */
2053 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2055 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2056 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2057 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2058 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2059 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2060 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2061 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2062 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2063 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2064 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2067 enum internal_test test
;
2068 enum machine_mode mode
;
2069 struct cmp_info
*p_info
;
2076 test
= map_test_to_internal_test (test_code
);
2077 if (test
== ITEST_MAX
)
2080 p_info
= &info
[ (int)test
];
2081 eqne_p
= (p_info
->test_code
== XOR
);
2083 mode
= GET_MODE (cmp0
);
2084 if (mode
== VOIDmode
)
2085 mode
= GET_MODE (cmp1
);
2087 /* Eliminate simple branches */
2088 branch_p
= (result
== (rtx
)0);
2091 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2093 /* Comparisons against zero are simple branches */
2094 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2097 /* Test for beq/bne. */
2102 /* allocate a pseudo to calculate the value in. */
2103 result
= gen_reg_rtx (mode
);
2106 /* Make sure we can handle any constants given to us. */
2107 if (GET_CODE (cmp0
) == CONST_INT
)
2108 cmp0
= force_reg (mode
, cmp0
);
2110 if (GET_CODE (cmp1
) == CONST_INT
)
2112 HOST_WIDE_INT value
= INTVAL (cmp1
);
2113 if (value
< p_info
->const_low
2114 || value
> p_info
->const_high
2115 /* ??? Why? And why wasn't the similar code below modified too? */
2117 && HOST_BITS_PER_WIDE_INT
< 64
2118 && p_info
->const_add
!= 0
2119 && ((p_info
->unsignedp
2120 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2122 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2123 != (p_info
->const_add
> 0))))
2124 cmp1
= force_reg (mode
, cmp1
);
2127 /* See if we need to invert the result. */
2128 invert
= (GET_CODE (cmp1
) == CONST_INT
)
2129 ? p_info
->invert_const
2130 : p_info
->invert_reg
;
2132 if (p_invert
!= (int *)0)
2138 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2139 Comparison between two registers, may involve switching operands. */
2140 if (GET_CODE (cmp1
) == CONST_INT
)
2142 if (p_info
->const_add
!= 0)
2144 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2145 /* If modification of cmp1 caused overflow,
2146 we would get the wrong answer if we follow the usual path;
2147 thus, x > 0xffffffffU would turn into x > 0U. */
2148 if ((p_info
->unsignedp
2149 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
2150 : new > INTVAL (cmp1
))
2151 != (p_info
->const_add
> 0))
2153 /* This test is always true, but if INVERT is true then
2154 the result of the test needs to be inverted so 0 should
2155 be returned instead. */
2156 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2160 cmp1
= GEN_INT (new);
2163 else if (p_info
->reverse_regs
)
2170 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2174 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
2175 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2178 if (test
== ITEST_NE
)
2180 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
2184 else if (test
== ITEST_EQ
)
2186 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
2187 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
2192 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
2198 /* Emit the common code for doing conditional branches.
2199 operand[0] is the label to jump to.
2200 The comparison operands are saved away by cmp{si,di,sf,df}. */
2203 gen_conditional_branch (operands
, test_code
)
2205 enum rtx_code test_code
;
2207 enum cmp_type type
= branch_type
;
2208 rtx cmp0
= branch_cmp
[0];
2209 rtx cmp1
= branch_cmp
[1];
2210 enum machine_mode mode
;
2218 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2222 mode
= type
== CMP_SI
? SImode
: DImode
;
2224 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2231 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2233 /* We don't want to build a comparison against a non-zero
2235 cmp1
= force_reg (mode
, cmp1
);
2242 reg
= gen_rtx (REG
, CCmode
, FPSW_REGNUM
);
2244 reg
= gen_reg_rtx (CCmode
);
2246 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2247 0 in the instruction built below. The MIPS FPU handles
2248 inequality testing by testing for equality and looking for a
2250 emit_insn (gen_rtx (SET
, VOIDmode
,
2252 gen_rtx (test_code
== NE
? EQ
: test_code
,
2253 CCmode
, cmp0
, cmp1
)));
2255 test_code
= test_code
== NE
? EQ
: NE
;
2263 /* Generate the branch. */
2265 label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2274 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2276 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2277 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2282 /* Emit the common code for conditional moves. OPERANDS is the array
2283 of operands passed to the conditional move defined_expand. */
2286 gen_conditional_move (operands
)
2289 rtx op0
= branch_cmp
[0];
2290 rtx op1
= branch_cmp
[1];
2291 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2292 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2293 enum rtx_code move_code
= NE
;
2294 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2295 enum machine_mode cmp_mode
;
2298 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2317 op0
= force_reg (mode
, branch_cmp
[1]);
2318 op1
= branch_cmp
[0];
2322 op0
= force_reg (mode
, branch_cmp
[1]);
2323 op1
= branch_cmp
[0];
2334 op0
= force_reg (mode
, branch_cmp
[1]);
2335 op1
= branch_cmp
[0];
2339 op0
= force_reg (mode
, branch_cmp
[1]);
2340 op1
= branch_cmp
[0];
2356 if (mode
== SImode
|| mode
== DImode
)
2358 else if (mode
== SFmode
|| mode
== DFmode
)
2363 cmp_reg
= gen_reg_rtx (cmp_mode
);
2364 emit_insn (gen_rtx (SET
, cmp_mode
,
2366 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2367 emit_insn (gen_rtx (SET
, op_mode
,
2369 gen_rtx (IF_THEN_ELSE
, op_mode
,
2370 gen_rtx (move_code
, VOIDmode
,
2372 CONST0_RTX (SImode
)),
2377 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2383 temp<last> = src[MAX_MOVE_REGS-1];
2387 dest[MAX_MOVE_REGS-1] = temp<last>;
2388 src += MAX_MOVE_REGS;
2389 dest += MAX_MOVE_REGS;
2390 } while (src != final);
2392 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2393 registers are needed.
2395 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2396 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2397 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2399 #define MAX_MOVE_REGS 4
2400 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2403 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
2404 rtx dest_reg
; /* register holding destination address */
2405 rtx src_reg
; /* register holding source address */
2406 int bytes
; /* # bytes to move */
2407 int align
; /* alignment */
2408 rtx orig_dest
; /* original dest for change_address */
2409 rtx orig_src
; /* original source for making a reg note */
2411 rtx dest_mem
= change_address (orig_dest
, BLKmode
, dest_reg
);
2412 rtx src_mem
= change_address (orig_src
, BLKmode
, src_reg
);
2413 rtx align_rtx
= GEN_INT (align
);
2419 if (bytes
< 2*MAX_MOVE_BYTES
)
2422 leftover
= bytes
% MAX_MOVE_BYTES
;
2425 label
= gen_label_rtx ();
2426 final_src
= gen_reg_rtx (Pmode
);
2427 bytes_rtx
= GEN_INT (bytes
);
2433 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2434 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2438 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2439 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2445 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2447 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2452 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2453 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2456 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2457 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2458 emit_insn (gen_cmpdi (src_reg
, final_src
));
2462 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2463 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2464 emit_insn (gen_cmpsi (src_reg
, final_src
));
2466 emit_jump_insn (gen_bne (label
));
2469 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2474 /* Use a library function to move some bytes. */
2477 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2482 /* We want to pass the size as Pmode, which will normally be SImode
2483 but will be DImode if we are using 64 bit longs and pointers. */
2484 if (GET_MODE (bytes_rtx
) != VOIDmode
2485 && GET_MODE (bytes_rtx
) != Pmode
)
2486 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2488 #ifdef TARGET_MEM_FUNCTIONS
2489 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2493 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2494 TREE_UNSIGNED (sizetype
)),
2495 TYPE_MODE (sizetype
));
2497 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2501 convert_to_mode (TYPE_MODE (integer_type_node
),
2503 TREE_UNSIGNED (integer_type_node
)),
2504 TYPE_MODE (integer_type_node
));
2509 /* Expand string/block move operations.
2511 operands[0] is the pointer to the destination.
2512 operands[1] is the pointer to the source.
2513 operands[2] is the number of bytes to move.
2514 operands[3] is the alignment. */
2517 expand_block_move (operands
)
2520 rtx bytes_rtx
= operands
[2];
2521 rtx align_rtx
= operands
[3];
2522 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2523 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2524 int align
= INTVAL (align_rtx
);
2525 rtx orig_src
= operands
[1];
2526 rtx orig_dest
= operands
[0];
2530 if (constp
&& bytes
<= 0)
2533 if (align
> UNITS_PER_WORD
)
2534 align
= UNITS_PER_WORD
;
2536 /* Move the address into scratch registers. */
2537 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2538 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2541 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2543 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2544 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2546 change_address (orig_src
, BLKmode
,
2548 bytes_rtx
, align_rtx
));
2550 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2551 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
2553 else if (constp
&& optimize
)
2555 /* If the alignment is not word aligned, generate a test at
2556 runtime, to see whether things wound up aligned, and we
2557 can use the faster lw/sw instead ulw/usw. */
2559 rtx temp
= gen_reg_rtx (Pmode
);
2560 rtx aligned_label
= gen_label_rtx ();
2561 rtx join_label
= gen_label_rtx ();
2562 int leftover
= bytes
% MAX_MOVE_BYTES
;
2568 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2569 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2570 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2574 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2575 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2576 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2578 emit_jump_insn (gen_beq (aligned_label
));
2580 /* Unaligned loop. */
2581 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
2582 emit_jump_insn (gen_jump (join_label
));
2586 emit_label (aligned_label
);
2587 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
2589 emit_label (join_label
);
2591 /* Bytes at the end of the loop. */
2593 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2595 change_address (orig_src
, BLKmode
,
2602 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2606 /* Emit load/stores for a small constant block_move.
2608 operands[0] is the memory address of the destination.
2609 operands[1] is the memory address of the source.
2610 operands[2] is the number of bytes to move.
2611 operands[3] is the alignment.
2612 operands[4] is a temp register.
2613 operands[5] is a temp register.
2615 operands[3+num_regs] is the last temp register.
2617 The block move type can be one of the following:
2618 BLOCK_MOVE_NORMAL Do all of the block move.
2619 BLOCK_MOVE_NOT_LAST Do all but the last store.
2620 BLOCK_MOVE_LAST Do just the last store. */
2623 output_block_move (insn
, operands
, num_regs
, move_type
)
2627 enum block_move_type move_type
;
2629 rtx dest_reg
= XEXP (operands
[0], 0);
2630 rtx src_reg
= XEXP (operands
[1], 0);
2631 int bytes
= INTVAL (operands
[2]);
2632 int align
= INTVAL (operands
[3]);
2635 int use_lwl_lwr
= FALSE
;
2636 int last_operand
= num_regs
+4;
2642 char *load
; /* load insn without nop */
2643 char *load_nop
; /* load insn with trailing nop */
2644 char *store
; /* store insn */
2645 char *final
; /* if last_store used: NULL or swr */
2646 char *last_store
; /* last store instruction */
2647 int offset
; /* current offset */
2648 enum machine_mode mode
; /* mode to use on (MEM) */
2651 /* Detect a bug in GCC, where it can give us a register
2652 the same as one of the addressing registers and reduce
2653 the number of registers available. */
2655 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2658 if (!reg_mentioned_p (operands
[i
], operands
[0])
2659 && !reg_mentioned_p (operands
[i
], operands
[1]))
2661 xoperands
[safe_regs
++] = operands
[i
];
2664 if (safe_regs
< last_operand
)
2666 xoperands
[0] = operands
[0];
2667 xoperands
[1] = operands
[1];
2668 xoperands
[2] = operands
[2];
2669 xoperands
[3] = operands
[3];
2670 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2673 /* If we are given global or static addresses, and we would be
2674 emitting a few instructions, try to save time by using a
2675 temporary register for the pointer. */
2676 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
2677 an ldl/ldr instruction pair. We play it safe, and always move
2678 constant addresses into registers when generating N32/N64 code, just
2679 in case we might emit an unaligned load instruction. */
2680 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
2681 || mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
2683 if (CONSTANT_P (src_reg
))
2686 mips_count_memory_refs (operands
[1], 1);
2688 src_reg
= operands
[ 3 + num_regs
-- ];
2689 if (move_type
!= BLOCK_MOVE_LAST
)
2691 xoperands
[1] = operands
[1];
2692 xoperands
[0] = src_reg
;
2693 if (Pmode
== DImode
)
2694 output_asm_insn ("dla\t%0,%1", xoperands
);
2696 output_asm_insn ("la\t%0,%1", xoperands
);
2700 if (CONSTANT_P (dest_reg
))
2703 mips_count_memory_refs (operands
[0], 1);
2705 dest_reg
= operands
[ 3 + num_regs
-- ];
2706 if (move_type
!= BLOCK_MOVE_LAST
)
2708 xoperands
[1] = operands
[0];
2709 xoperands
[0] = dest_reg
;
2710 if (Pmode
== DImode
)
2711 output_asm_insn ("dla\t%0,%1", xoperands
);
2713 output_asm_insn ("la\t%0,%1", xoperands
);
2718 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2719 are not offsettable, however, offsettable_address_p says they are
2720 offsettable. I think this is a bug in offsettable_address_p.
2721 For expediency, we fix this by just loading the address into a register
2722 if we happen to get one. */
2724 if (GET_CODE (src_reg
) == LO_SUM
)
2726 src_reg
= operands
[ 3 + num_regs
-- ];
2727 if (move_type
!= BLOCK_MOVE_LAST
)
2729 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2730 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2731 xoperands
[0] = src_reg
;
2732 if (Pmode
== DImode
)
2733 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2735 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2739 if (GET_CODE (dest_reg
) == LO_SUM
)
2741 dest_reg
= operands
[ 3 + num_regs
-- ];
2742 if (move_type
!= BLOCK_MOVE_LAST
)
2744 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2745 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2746 xoperands
[0] = dest_reg
;
2747 if (Pmode
== DImode
)
2748 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2750 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2754 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2755 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2757 else if (num_regs
< 1)
2758 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2762 load_store
[num
].offset
= offset
;
2764 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2766 load_store
[num
].load
= "ld\t%0,%1";
2767 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2768 load_store
[num
].store
= "sd\t%0,%1";
2769 load_store
[num
].last_store
= "sd\t%0,%1";
2770 load_store
[num
].final
= (char *)0;
2771 load_store
[num
].mode
= DImode
;
2776 else if (TARGET_64BIT
&& bytes
>= 8)
2778 if (BYTES_BIG_ENDIAN
)
2780 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2781 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2782 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2783 load_store
[num
].last_store
= "sdr\t%0,%2";
2784 load_store
[num
].final
= "sdl\t%0,%1";
2788 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2789 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2790 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2791 load_store
[num
].last_store
= "sdr\t%0,%1";
2792 load_store
[num
].final
= "sdl\t%0,%2";
2794 load_store
[num
].mode
= DImode
;
2800 else if (bytes
>= 4 && align
>= 4)
2802 load_store
[num
].load
= "lw\t%0,%1";
2803 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2804 load_store
[num
].store
= "sw\t%0,%1";
2805 load_store
[num
].last_store
= "sw\t%0,%1";
2806 load_store
[num
].final
= (char *)0;
2807 load_store
[num
].mode
= SImode
;
2812 else if (bytes
>= 4)
2814 if (BYTES_BIG_ENDIAN
)
2816 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2817 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2818 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2819 load_store
[num
].last_store
= "swr\t%0,%2";
2820 load_store
[num
].final
= "swl\t%0,%1";
2824 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2825 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2826 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2827 load_store
[num
].last_store
= "swr\t%0,%1";
2828 load_store
[num
].final
= "swl\t%0,%2";
2830 load_store
[num
].mode
= SImode
;
2836 else if (bytes
>= 2 && align
>= 2)
2838 load_store
[num
].load
= "lh\t%0,%1";
2839 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2840 load_store
[num
].store
= "sh\t%0,%1";
2841 load_store
[num
].last_store
= "sh\t%0,%1";
2842 load_store
[num
].final
= (char *)0;
2843 load_store
[num
].mode
= HImode
;
2850 load_store
[num
].load
= "lb\t%0,%1";
2851 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2852 load_store
[num
].store
= "sb\t%0,%1";
2853 load_store
[num
].last_store
= "sb\t%0,%1";
2854 load_store
[num
].final
= (char *)0;
2855 load_store
[num
].mode
= QImode
;
2860 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2862 dslots_load_total
++;
2863 dslots_load_filled
++;
2865 if (CONSTANT_P (src_reg
))
2866 mips_count_memory_refs (src_reg
, 1);
2868 if (CONSTANT_P (dest_reg
))
2869 mips_count_memory_refs (dest_reg
, 1);
2872 /* Emit load/stores now if we have run out of registers or are
2873 at the end of the move. */
2875 if (++num
== num_regs
|| bytes
== 0)
2877 /* If only load/store, we need a NOP after the load. */
2880 load_store
[0].load
= load_store
[0].load_nop
;
2881 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2882 dslots_load_filled
--;
2885 if (move_type
!= BLOCK_MOVE_LAST
)
2887 for (i
= 0; i
< num
; i
++)
2894 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2895 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2897 offset
= load_store
[i
].offset
;
2898 xoperands
[0] = operands
[i
+4];
2899 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2900 plus_constant (src_reg
, offset
));
2905 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2906 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2907 plus_constant (src_reg
,
2912 output_asm_insn (load_store
[i
].load
, xoperands
);
2916 for (i
= 0; i
< num
; i
++)
2918 int last_p
= (i
== num
-1 && bytes
== 0);
2919 int offset
= load_store
[i
].offset
;
2921 xoperands
[0] = operands
[i
+4];
2922 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2923 plus_constant (dest_reg
, offset
));
2929 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2930 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2931 plus_constant (dest_reg
,
2936 if (move_type
== BLOCK_MOVE_NORMAL
)
2937 output_asm_insn (load_store
[i
].store
, xoperands
);
2939 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2942 output_asm_insn (load_store
[i
].store
, xoperands
);
2944 else if (load_store
[i
].final
!= (char *)0)
2945 output_asm_insn (load_store
[i
].final
, xoperands
);
2949 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2952 num
= 0; /* reset load_store */
2953 use_lwl_lwr
= FALSE
;
2961 /* Argument support functions. */
2963 /* Initialize CUMULATIVE_ARGS for a function. */
2966 init_cumulative_args (cum
, fntype
, libname
)
2967 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2968 tree fntype
; /* tree ptr for function decl */
2969 rtx libname
; /* SYMBOL_REF of library name or 0 */
2971 static CUMULATIVE_ARGS zero_cum
;
2972 tree param
, next_param
;
2974 if (TARGET_DEBUG_E_MODE
)
2976 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2978 fputc ('\n', stderr
);
2982 tree ret_type
= TREE_TYPE (fntype
);
2983 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2984 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2985 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2991 /* Determine if this function has variable arguments. This is
2992 indicated by the last argument being 'void_type_mode' if there
2993 are no variable arguments. The standard MIPS calling sequence
2994 passes all arguments in the general purpose registers in this
2997 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
3001 next_param
= TREE_CHAIN (param
);
3002 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
3003 cum
->gp_reg_found
= 1;
3007 /* Advance the argument to the next argument position. */
3010 function_arg_advance (cum
, mode
, type
, named
)
3011 CUMULATIVE_ARGS
*cum
; /* current arg information */
3012 enum machine_mode mode
; /* current arg mode */
3013 tree type
; /* type of the argument or 0 if lib support */
3014 int named
; /* whether or not the argument was named */
3016 if (TARGET_DEBUG_E_MODE
)
3018 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
3019 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3029 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3030 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3032 cum
->gp_reg_found
= 1;
3033 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3038 cum
->gp_reg_found
= 1;
3039 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3044 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3045 cum
->fp_arg_words
++;
3051 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3052 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3054 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3058 cum
->gp_reg_found
= 1;
3059 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3065 cum
->gp_reg_found
= 1;
3071 /* Return an RTL expression containing the register for the given mode,
3072 or 0 if the argument is to be passed on the stack. */
3075 function_arg (cum
, mode
, type
, named
)
3076 CUMULATIVE_ARGS
*cum
; /* current arg information */
3077 enum machine_mode mode
; /* current arg mode */
3078 tree type
; /* type of the argument or 0 if lib support */
3079 int named
; /* != 0 for normal args, == 0 for ... args */
3084 int *arg_words
= &cum
->arg_words
;
3085 int struct_p
= ((type
!= (tree
)0)
3086 && (TREE_CODE (type
) == RECORD_TYPE
3087 || TREE_CODE (type
) == UNION_TYPE
));
3089 if (TARGET_DEBUG_E_MODE
)
3091 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3092 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3095 cum
->last_arg_fp
= 0;
3099 if (mips_abi
== ABI_32
)
3101 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3102 regbase
= GP_ARG_FIRST
;
3105 regbase
= FP_ARG_FIRST
;
3106 /* If the first arg was a float in a floating point register,
3107 then set bias to align this float arg properly. */
3108 if (cum
->arg_words
== 1)
3112 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3115 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3116 cum
->last_arg_fp
= 1;
3117 arg_words
= &cum
->fp_arg_words
;
3118 regbase
= FP_ARG_FIRST
;
3121 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3127 if (mips_abi
== ABI_EABI
3128 && ! TARGET_SOFT_FLOAT
3129 && ! TARGET_SINGLE_FLOAT
)
3130 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3132 cum
->arg_words
+= cum
->arg_words
& 1;
3134 if (mips_abi
== ABI_32
)
3135 regbase
= ((cum
->gp_reg_found
3136 || TARGET_SOFT_FLOAT
3137 || TARGET_SINGLE_FLOAT
3138 || cum
->arg_number
>= 2)
3141 else if (mips_abi
== ABI_EABI
3142 && ! TARGET_SOFT_FLOAT
3143 && ! TARGET_SINGLE_FLOAT
)
3145 cum
->last_arg_fp
= 1;
3146 arg_words
= &cum
->fp_arg_words
;
3147 regbase
= FP_ARG_FIRST
;
3150 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3151 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3155 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3156 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3159 /* Drops through. */
3161 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3162 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3163 cum
->arg_words
+= (cum
->arg_words
& 1);
3164 regbase
= GP_ARG_FIRST
;
3171 regbase
= GP_ARG_FIRST
;
3176 cum
->arg_words
+= (cum
->arg_words
& 1);
3177 regbase
= GP_ARG_FIRST
;
3180 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3182 if (TARGET_DEBUG_E_MODE
)
3183 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3192 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3193 || mips_abi
== ABI_EABI
|| ! named
)
3194 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3197 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3198 structure contains a double in its entirety, then that 64 bit
3199 chunk is passed in a floating point register. */
3202 /* First check to see if there is any such field. */
3203 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3204 if (TREE_CODE (field
) == FIELD_DECL
3205 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3206 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3207 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3208 % BITS_PER_WORD
== 0))
3212 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3215 /* Now handle the special case by returning a PARALLEL
3216 indicating where each 64 bit chunk goes. */
3222 /* ??? If this is a packed structure, then the last hunk won't
3225 /* ??? If this is a structure with a single double field,
3226 it would be more convenient to return (REG:DI %fX) than
3227 a parallel. However, we would have to modify the mips
3228 backend to allow DImode values in fp registers. */
3230 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3231 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3232 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3234 /* assign_parms checks the mode of ENTRY_PARM, so we must
3235 use the actual mode here. */
3236 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3239 regno
= regbase
+ *arg_words
+ bias
;
3240 field
= TYPE_FIELDS (type
);
3241 for (i
= 0; i
< chunks
; i
++)
3245 for (; field
; field
= TREE_CHAIN (field
))
3246 if (TREE_CODE (field
) == FIELD_DECL
3247 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3252 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3253 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3254 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3255 reg
= gen_rtx (REG
, DFmode
,
3256 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3258 reg
= gen_rtx (REG
, word_mode
, regno
);
3260 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3261 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3269 if (TARGET_DEBUG_E_MODE
)
3270 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3271 struct_p
? ", [struct]" : "");
3273 /* The following is a hack in order to pass 1 byte structures
3274 the same way that the MIPS compiler does (namely by passing
3275 the structure in the high byte or half word of the register).
3276 This also makes varargs work. If we have such a structure,
3277 we save the adjustment RTL, and the call define expands will
3278 emit them. For the VOIDmode argument (argument after the
3279 last real argument), pass back a parallel vector holding each
3280 of the adjustments. */
3282 /* ??? function_arg can be called more than once for each argument.
3283 As a result, we compute more adjustments than we need here.
3284 See the CUMULATIVE_ARGS definition in mips.h. */
3286 /* ??? This scheme requires everything smaller than the word size to
3287 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3288 that would mean every int needs to be shifted left, which is very
3289 inefficient. Let's not carry this compatibility to the 64 bit
3290 calling convention for now. */
3292 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3293 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3295 rtx amount
= GEN_INT (BITS_PER_WORD
3296 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3297 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ *arg_words
+ bias
);
3299 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3301 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3305 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3306 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3313 function_arg_partial_nregs (cum
, mode
, type
, named
)
3314 CUMULATIVE_ARGS
*cum
; /* current arg information */
3315 enum machine_mode mode
; /* current arg mode */
3316 tree type
; /* type of the argument or 0 if lib support */
3317 int named
; /* != 0 for normal args, == 0 for ... args */
3319 if ((mode
== BLKmode
3320 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3321 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3322 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3323 && mips_abi
!= ABI_EABI
)
3326 if (mode
== BLKmode
)
3327 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3330 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3332 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3333 return 0; /* structure fits in registers */
3335 if (TARGET_DEBUG_E_MODE
)
3336 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3337 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3339 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3342 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3344 && mips_abi
!= ABI_EABI
)
3346 if (TARGET_DEBUG_E_MODE
)
3347 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3355 /* Abort after printing out a specific insn. */
3358 abort_with_insn (insn
, reason
)
3367 /* Write a message to stderr (for use in macros expanded in files that do not
3368 include stdio.h). */
3374 fprintf (stderr
, s
, s1
, s2
);
3384 fprintf (stderr
, "compiling '%s' in '%s'\n",
3385 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3386 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3389 #endif /* SIGINFO */
3392 /* Set up the threshold for data to go into the small data area, instead
3393 of the normal data area, and detect any conflicts in the switches. */
3398 register int i
, start
;
3400 register enum machine_mode mode
;
3402 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3404 if (mips_section_threshold
<= 0)
3405 target_flags
&= ~MASK_GPOPT
;
3407 target_flags
|= MASK_GPOPT
;
3409 /* Get the architectural level. */
3410 if (mips_isa_string
== (char *)0)
3412 #ifdef MIPS_ISA_DEFAULT
3413 mips_isa
= MIPS_ISA_DEFAULT
;
3419 else if (isdigit (*mips_isa_string
))
3421 mips_isa
= atoi (mips_isa_string
);
3422 if (mips_isa
< 1 || mips_isa
> 4)
3424 error ("-mips%d not supported", mips_isa
);
3431 error ("bad value (%s) for -mips switch", mips_isa_string
);
3435 #ifdef MIPS_ABI_DEFAULT
3436 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3437 if (mips_abi_string
== (char *) 0)
3438 mips_abi
= MIPS_ABI_DEFAULT
;
3439 else if (! strcmp (mips_abi_string
, "32")
3440 || ! strcmp (mips_abi_string
, "o32"))
3442 else if (! strcmp (mips_abi_string
, "n32"))
3444 else if (! strcmp (mips_abi_string
, "64")
3445 || ! strcmp (mips_abi_string
, "n64"))
3447 else if (! strcmp (mips_abi_string
, "eabi"))
3448 mips_abi
= ABI_EABI
;
3450 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3452 /* A specified ISA defaults the ABI if it was not specified. */
3453 if (mips_abi_string
== 0 && mips_isa_string
&& mips_abi
!= ABI_EABI
)
3460 /* A specified ABI defaults the ISA if it was not specified. */
3461 else if (mips_isa_string
== 0 && mips_abi_string
&& mips_abi
!= ABI_EABI
)
3463 if (mips_abi
== ABI_32
)
3465 else if (mips_abi
== ABI_N32
)
3470 /* If both ABI and ISA were specified, check for conflicts. */
3471 else if (mips_isa_string
&& mips_abi_string
)
3473 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3474 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3475 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3478 /* Override TARGET_DEFAULT if necessary. */
3479 if (mips_abi
== ABI_32
)
3480 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3482 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. */
3483 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
3484 target_flags
|= MASK_LONG64
;
3486 /* ??? This doesn't work yet, so don't let people try to use it. */
3487 if (mips_abi
== ABI_32
)
3488 error ("The -mabi=32 support does not work yet.");
3490 if (mips_abi_string
)
3491 error ("This target does not support the -mabi switch.");
3494 #ifdef MIPS_CPU_STRING_DEFAULT
3495 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3496 greater than that supported by the default processor, then the user gets
3497 an error. Normally, the compiler will just default to the base level cpu
3498 for the indicated isa. */
3499 if (mips_cpu_string
== (char *)0)
3500 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3503 /* Identify the processor type */
3504 if (mips_cpu_string
== (char *)0
3505 || !strcmp (mips_cpu_string
, "default")
3506 || !strcmp (mips_cpu_string
, "DEFAULT"))
3511 mips_cpu_string
= "3000";
3512 mips_cpu
= PROCESSOR_R3000
;
3515 mips_cpu_string
= "6000";
3516 mips_cpu
= PROCESSOR_R6000
;
3519 mips_cpu_string
= "4000";
3520 mips_cpu
= PROCESSOR_R4000
;
3523 mips_cpu_string
= "8000";
3524 mips_cpu
= PROCESSOR_R8000
;
3531 char *p
= mips_cpu_string
;
3534 /* We need to cope with the various "vr" prefixes for the NEC 4300
3535 and 4100 processors. */
3536 if (*p
== 'v' || *p
== 'V')
3541 if (*p
== 'r' || *p
== 'R')
3544 /* Since there is no difference between a R2000 and R3000 in
3545 terms of the scheduler, we collapse them into just an R3000. */
3547 mips_cpu
= PROCESSOR_DEFAULT
;
3551 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3552 mips_cpu
= PROCESSOR_R3000
;
3556 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3557 mips_cpu
= PROCESSOR_R3000
;
3561 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3562 mips_cpu
= PROCESSOR_R4000
;
3563 /* The vr4100 is a non-FP ISA III processor with some extra
3565 else if (!strcmp (p
, "4100")) {
3566 mips_cpu
= PROCESSOR_R4100
;
3567 target_flags
|= MASK_SOFT_FLOAT
;
3569 /* The vr4300 is a standard ISA III processor, but with a different
3571 else if (!strcmp (p
, "4300"))
3572 mips_cpu
= PROCESSOR_R4300
;
3573 /* The r4400 is exactly the same as the r4000 from the compiler's
3575 else if (!strcmp (p
, "4400"))
3576 mips_cpu
= PROCESSOR_R4000
;
3577 else if (!strcmp (p
, "4600"))
3578 mips_cpu
= PROCESSOR_R4600
;
3579 else if (!strcmp (p
, "4650"))
3580 mips_cpu
= PROCESSOR_R4650
;
3584 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
3585 mips_cpu
= PROCESSOR_R5000
;
3589 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3590 mips_cpu
= PROCESSOR_R6000
;
3594 if (!strcmp (p
, "8000"))
3595 mips_cpu
= PROCESSOR_R8000
;
3599 if (!strcmp (p
, "orion"))
3600 mips_cpu
= PROCESSOR_R4600
;
3605 && mips_cpu
!= PROCESSOR_R4300
3606 && mips_cpu
!= PROCESSOR_R4100
3607 && mips_cpu
!= PROCESSOR_R5000
)
3608 mips_cpu
= PROCESSOR_DEFAULT
;
3610 if (mips_cpu
== PROCESSOR_DEFAULT
)
3612 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3613 mips_cpu_string
= "default";
3617 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3618 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3619 || ((mips_cpu
== PROCESSOR_R4000
3620 || mips_cpu
== PROCESSOR_R4100
3621 || mips_cpu
== PROCESSOR_R4300
3622 || mips_cpu
== PROCESSOR_R4600
3623 || mips_cpu
== PROCESSOR_R4650
)
3625 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3627 /* make sure sizes of ints/longs/etc. are ok */
3631 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3633 else if (TARGET_LONG64
)
3634 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3636 else if (TARGET_FLOAT64
)
3637 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3639 else if (TARGET_64BIT
)
3640 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3643 if (mips_abi
!= ABI_32
)
3644 flag_pcc_struct_return
= 0;
3646 /* Tell halfpic.c that we have half-pic code if we do. */
3647 if (TARGET_HALF_PIC
)
3650 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3651 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3652 /* ??? -non_shared turns off pic code generation, but this is not
3654 if (TARGET_ABICALLS
)
3656 mips_abicalls
= MIPS_ABICALLS_YES
;
3658 if (mips_section_threshold
> 0)
3659 warning ("-G is incompatible with PIC code which is the default");
3662 mips_abicalls
= MIPS_ABICALLS_NO
;
3664 /* -membedded-pic is a form of PIC code suitable for embedded
3665 systems. All calls are made using PC relative addressing, and
3666 all data is addressed using the $gp register. This requires gas,
3667 which does most of the work, and GNU ld, which automatically
3668 expands PC relative calls which are out of range into a longer
3669 instruction sequence. All gcc really does differently is
3670 generate a different sequence for a switch. */
3671 if (TARGET_EMBEDDED_PIC
)
3674 if (TARGET_ABICALLS
)
3675 warning ("-membedded-pic and -mabicalls are incompatible");
3677 warning ("-G and -membedded-pic are incompatible");
3678 /* Setting mips_section_threshold is not required, because gas
3679 will force everything to be GP addressable anyhow, but
3680 setting it will cause gcc to make better estimates of the
3681 number of instructions required to access a particular data
3683 mips_section_threshold
= 0x7fffffff;
3686 /* This optimization requires a linker that can support a R_MIPS_LO16
3687 relocation which is not immediately preceeded by a R_MIPS_HI16 relocation.
3688 GNU ld has this support, but not all other MIPS linkers do, so we enable
3689 this optimization only if the user requests it, or if GNU ld is the
3690 standard linker for this configuration. */
3691 /* ??? This does not work when target addresses are DImode.
3692 This is because we are missing DImode high/lo_sum patterns. */
3693 if (TARGET_GAS
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
3695 mips_split_addresses
= 1;
3697 mips_split_addresses
= 0;
3699 /* -mrnames says to use the MIPS software convention for register
3700 names instead of the hardware names (ie, $a0 instead of $4).
3701 We do this by switching the names in mips_reg_names, which the
3702 reg_names points into via the REGISTER_NAMES macro. */
3704 if (TARGET_NAME_REGS
)
3705 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3707 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3708 is currently being compiled. */
3710 if (getenv ("GCC_SIGINFO") != (char *)0)
3712 struct sigaction action
;
3713 action
.sa_handler
= siginfo
;
3715 action
.sa_flags
= SA_RESTART
;
3716 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3721 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3722 /* If -mstats and -quiet, make stderr line buffered. */
3723 if (quiet_flag
&& TARGET_STATS
)
3724 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3728 /* Initialize the high and low values for legitimate floating point
3729 constants. Rather than trying to get the accuracy down to the
3730 last bit, just use approximate ranges. */
3731 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3732 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3733 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3734 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3736 mips_print_operand_punct
['?'] = TRUE
;
3737 mips_print_operand_punct
['#'] = TRUE
;
3738 mips_print_operand_punct
['&'] = TRUE
;
3739 mips_print_operand_punct
['!'] = TRUE
;
3740 mips_print_operand_punct
['*'] = TRUE
;
3741 mips_print_operand_punct
['@'] = TRUE
;
3742 mips_print_operand_punct
['.'] = TRUE
;
3743 mips_print_operand_punct
['('] = TRUE
;
3744 mips_print_operand_punct
[')'] = TRUE
;
3745 mips_print_operand_punct
['['] = TRUE
;
3746 mips_print_operand_punct
[']'] = TRUE
;
3747 mips_print_operand_punct
['<'] = TRUE
;
3748 mips_print_operand_punct
['>'] = TRUE
;
3749 mips_print_operand_punct
['{'] = TRUE
;
3750 mips_print_operand_punct
['}'] = TRUE
;
3751 mips_print_operand_punct
['^'] = TRUE
;
3753 mips_char_to_class
['d'] = GR_REGS
;
3754 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3755 mips_char_to_class
['h'] = HI_REG
;
3756 mips_char_to_class
['l'] = LO_REG
;
3757 mips_char_to_class
['a'] = HILO_REG
;
3758 mips_char_to_class
['x'] = MD_REGS
;
3759 mips_char_to_class
['b'] = ALL_REGS
;
3760 mips_char_to_class
['y'] = GR_REGS
;
3761 mips_char_to_class
['z'] = ST_REGS
;
3763 /* Set up array to map GCC register number to debug register number.
3764 Ignore the special purpose register numbers. */
3766 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3767 mips_dbx_regno
[i
] = -1;
3769 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3770 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3771 mips_dbx_regno
[i
] = i
+ start
;
3773 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3774 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3775 mips_dbx_regno
[i
] = i
+ start
;
3777 /* Set up array giving whether a given register can hold a given mode.
3778 At present, restrict ints from being in FP registers, because reload
3779 is a little enthusiastic about storing extra values in FP registers,
3780 and this is not good for things like OS kernels. Also, due to the
3781 mandatory delay, it is as fast to load from cached memory as to move
3782 from the FP register. */
3784 for (mode
= VOIDmode
;
3785 mode
!= MAX_MACHINE_MODE
;
3786 mode
= (enum machine_mode
)((int)mode
+ 1))
3788 register int size
= GET_MODE_SIZE (mode
);
3789 register enum mode_class
class = GET_MODE_CLASS (mode
);
3791 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3798 temp
= (regno
== FPSW_REGNUM
);
3800 temp
= (ST_REG_P (regno
)
3802 || FP_REG_P (regno
));
3805 else if (GP_REG_P (regno
))
3806 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3808 else if (FP_REG_P (regno
))
3809 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3810 && (class == MODE_FLOAT
3811 || class == MODE_COMPLEX_FLOAT
3812 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3813 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3815 else if (MD_REG_P (regno
))
3816 temp
= (class == MODE_INT
3817 && (size
<= UNITS_PER_WORD
3818 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3823 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3830 * The MIPS debug format wants all automatic variables and arguments
3831 * to be in terms of the virtual frame pointer (stack pointer before
3832 * any adjustment in the function), while the MIPS 3.0 linker wants
3833 * the frame pointer to be the stack pointer after the initial
3834 * adjustment. So, we do the adjustment here. The arg pointer (which
3835 * is eliminated) points to the virtual frame pointer, while the frame
3836 * pointer (which may be eliminated) points to the stack pointer after
3837 * the initial adjustments.
3841 mips_debugger_offset (addr
, offset
)
3845 rtx offset2
= const0_rtx
;
3846 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3849 offset
= INTVAL (offset2
);
3851 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3853 int frame_size
= (!current_frame_info
.initialized
)
3854 ? compute_frame_size (get_frame_size ())
3855 : current_frame_info
.total_size
;
3857 offset
= offset
- frame_size
;
3859 /* sdbout_parms does not want this to crash for unrecognized cases. */
3861 else if (reg
!= arg_pointer_rtx
)
3862 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3869 /* A C compound statement to output to stdio stream STREAM the
3870 assembler syntax for an instruction operand X. X is an RTL
3873 CODE is a value that can be used to specify one of several ways
3874 of printing the operand. It is used when identical operands
3875 must be printed differently depending on the context. CODE
3876 comes from the `%' specification that was used to request
3877 printing of the operand. If the specification was just `%DIGIT'
3878 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3879 is the ASCII code for LTR.
3881 If X is a register, this macro should print the register's name.
3882 The names can be found in an array `reg_names' whose type is
3883 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3885 When the machine description has a specification `%PUNCT' (a `%'
3886 followed by a punctuation character), this macro is called with
3887 a null pointer for X and the punctuation character for CODE.
3889 The MIPS specific codes are:
3891 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3892 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3893 'd' output integer constant in decimal,
3894 'z' if the operand is 0, use $0 instead of normal operand.
3895 'D' print second register of double-word register operand.
3896 'L' print low-order register of double-word register operand.
3897 'M' print high-order register of double-word register operand.
3898 'C' print part of opcode for a branch condition.
3899 'N' print part of opcode for a branch condition, inverted.
3900 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3901 'B' print 'z' for EQ, 'n' for NE
3902 'b' print 'n' for EQ, 'z' for NE
3903 'T' print 'f' for EQ, 't' for NE
3904 't' print 't' for EQ, 'f' for NE
3905 'Z' print register and a comma, but print nothing for $fcc0
3906 '(' Turn on .set noreorder
3907 ')' Turn on .set reorder
3908 '[' Turn on .set noat
3910 '<' Turn on .set nomacro
3911 '>' Turn on .set macro
3912 '{' Turn on .set volatile (not GAS)
3913 '}' Turn on .set novolatile (not GAS)
3914 '&' Turn on .set noreorder if filling delay slots
3915 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3916 '!' Turn on .set nomacro if filling delay slots
3917 '#' Print nop if in a .set noreorder section.
3918 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3919 '@' Print the name of the assembler temporary register (at or $1).
3920 '.' Print the name of the register with a hard-wired zero (zero or $0).
3921 '^' Print the name of the pic call-through register (t9 or $25). */
3924 print_operand (file
, op
, letter
)
3925 FILE *file
; /* file to write to */
3926 rtx op
; /* operand to print */
3927 int letter
; /* %<letter> or 0 */
3929 register enum rtx_code code
;
3931 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3936 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3940 if (mips_branch_likely
)
3945 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3949 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3953 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3957 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3958 fputs (".set\tnoreorder\n\t", file
);
3962 if (final_sequence
!= 0)
3964 if (set_noreorder
++ == 0)
3965 fputs (".set\tnoreorder\n\t", file
);
3967 if (set_nomacro
++ == 0)
3968 fputs (".set\tnomacro\n\t", file
);
3973 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3974 fputs ("\n\t.set\tnomacro", file
);
3978 if (set_noreorder
!= 0)
3979 fputs ("\n\tnop", file
);
3981 else if (TARGET_STATS
)
3982 fputs ("\n\t#nop", file
);
3987 if (set_noreorder
++ == 0)
3988 fputs (".set\tnoreorder\n\t", file
);
3992 if (set_noreorder
== 0)
3993 error ("internal error: %%) found without a %%( in assembler pattern");
3995 else if (--set_noreorder
== 0)
3996 fputs ("\n\t.set\treorder", file
);
4001 if (set_noat
++ == 0)
4002 fputs (".set\tnoat\n\t", file
);
4007 error ("internal error: %%] found without a %%[ in assembler pattern");
4009 else if (--set_noat
== 0)
4010 fputs ("\n\t.set\tat", file
);
4015 if (set_nomacro
++ == 0)
4016 fputs (".set\tnomacro\n\t", file
);
4020 if (set_nomacro
== 0)
4021 error ("internal error: %%> found without a %%< in assembler pattern");
4023 else if (--set_nomacro
== 0)
4024 fputs ("\n\t.set\tmacro", file
);
4029 if (set_volatile
++ == 0)
4030 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
4034 if (set_volatile
== 0)
4035 error ("internal error: %%} found without a %%{ in assembler pattern");
4037 else if (--set_volatile
== 0)
4038 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
4047 error ("PRINT_OPERAND null pointer");
4051 code
= GET_CODE (op
);
4053 if (code
== SIGN_EXTEND
)
4056 code
= GET_CODE (op
);
4062 case EQ
: fputs ("eq", file
); break;
4063 case NE
: fputs ("ne", file
); break;
4064 case GT
: fputs ("gt", file
); break;
4065 case GE
: fputs ("ge", file
); break;
4066 case LT
: fputs ("lt", file
); break;
4067 case LE
: fputs ("le", file
); break;
4068 case GTU
: fputs ("gtu", file
); break;
4069 case GEU
: fputs ("geu", file
); break;
4070 case LTU
: fputs ("ltu", file
); break;
4071 case LEU
: fputs ("leu", file
); break;
4074 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
4077 else if (letter
== 'N')
4080 case EQ
: fputs ("ne", file
); break;
4081 case NE
: fputs ("eq", file
); break;
4082 case GT
: fputs ("le", file
); break;
4083 case GE
: fputs ("lt", file
); break;
4084 case LT
: fputs ("ge", file
); break;
4085 case LE
: fputs ("gt", file
); break;
4086 case GTU
: fputs ("leu", file
); break;
4087 case GEU
: fputs ("ltu", file
); break;
4088 case LTU
: fputs ("geu", file
); break;
4089 case LEU
: fputs ("gtu", file
); break;
4092 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
4095 else if (letter
== 'S')
4099 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
4100 assemble_name (file
, buffer
);
4103 else if (letter
== 'Z')
4105 register int regnum
;
4109 regnum
= REGNO (op
);
4110 if (! ST_REG_P (regnum
))
4112 if (regnum
!= ST_REG_FIRST
)
4113 fprintf (file
, "%s,", reg_names
[regnum
]);
4116 else if (code
== REG
|| code
== SUBREG
)
4118 register int regnum
;
4121 regnum
= REGNO (op
);
4123 regnum
= true_regnum (op
);
4125 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4126 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4130 fprintf (file
, "%s", reg_names
[regnum
]);
4133 else if (code
== MEM
)
4134 output_address (XEXP (op
, 0));
4136 else if (code
== CONST_DOUBLE
4137 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
4142 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
4143 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
4147 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
4148 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
4150 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4151 && HOST_BITS_PER_WIDE_INT
== 32)
4152 fprintf (file
, "0x%08x", INTVAL(op
));
4154 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4155 && HOST_BITS_PER_WIDE_INT
== 64)
4156 fprintf (file
, "0x%016lx", INTVAL(op
));
4158 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
4159 fprintf (file
, "%d", (INTVAL(op
)));
4161 else if (letter
== 'z'
4162 && (GET_CODE (op
) == CONST_INT
)
4163 && INTVAL (op
) == 0)
4164 fputs (reg_names
[GP_REG_FIRST
], file
);
4166 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4167 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
4169 else if (letter
== 'B')
4170 fputs (code
== EQ
? "z" : "n", file
);
4171 else if (letter
== 'b')
4172 fputs (code
== EQ
? "n" : "z", file
);
4173 else if (letter
== 'T')
4174 fputs (code
== EQ
? "f" : "t", file
);
4175 else if (letter
== 't')
4176 fputs (code
== EQ
? "t" : "f", file
);
4179 output_addr_const (file
, op
);
4183 /* A C compound statement to output to stdio stream STREAM the
4184 assembler syntax for an instruction operand that is a memory
4185 reference whose address is ADDR. ADDR is an RTL expression.
4187 On some machines, the syntax for a symbolic address depends on
4188 the section that the address refers to. On these machines,
4189 define the macro `ENCODE_SECTION_INFO' to store the information
4190 into the `symbol_ref', and then check for it here. */
4193 print_operand_address (file
, addr
)
4198 error ("PRINT_OPERAND_ADDRESS, null pointer");
4201 switch (GET_CODE (addr
))
4204 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4208 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4209 abort_with_insn (addr
, "Arg pointer not eliminated.");
4211 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4216 register rtx arg0
= XEXP (addr
, 0);
4217 register rtx arg1
= XEXP (addr
, 1);
4219 if (! mips_split_addresses
)
4220 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4222 if (GET_CODE (arg0
) != REG
)
4223 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4225 fprintf (file
, "%%lo(");
4226 print_operand_address (file
, arg1
);
4227 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4233 register rtx reg
= (rtx
)0;
4234 register rtx offset
= (rtx
)0;
4235 register rtx arg0
= XEXP (addr
, 0);
4236 register rtx arg1
= XEXP (addr
, 1);
4238 if (GET_CODE (arg0
) == REG
)
4242 if (GET_CODE (offset
) == REG
)
4243 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4245 else if (GET_CODE (arg1
) == REG
)
4250 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4252 output_addr_const (file
, addr
);
4256 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4258 if (!CONSTANT_P (offset
))
4259 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4261 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4262 abort_with_insn (addr
, "Arg pointer not eliminated.");
4264 output_addr_const (file
, offset
);
4265 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4273 output_addr_const (file
, addr
);
4279 /* If optimizing for the global pointer, keep track of all of
4280 the externs, so that at the end of the file, we can emit
4281 the appropriate .extern declaration for them, before writing
4282 out the text section. We assume that all names passed to
4283 us are in the permanent obstack, so that they will be valid
4284 at the end of the compilation.
4286 If we have -G 0, or the extern size is unknown, don't bother
4287 emitting the .externs. */
4290 mips_output_external (file
, decl
, name
)
4295 register struct extern_list
*p
;
4299 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4300 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0))
4302 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4303 p
->next
= extern_head
;
4309 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4310 if (TREE_CODE (decl
) == FUNCTION_DECL
4311 /* ??? Don't include alloca, since gcc will always expand it
4312 inline. If we don't do this, libg++ fails to build. */
4313 && strcmp (name
, "alloca")
4314 /* ??? Don't include __builtin_next_arg, because then gcc will not
4315 bootstrap under Irix 5.1. */
4316 && strcmp (name
, "__builtin_next_arg"))
4318 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4319 p
->next
= extern_head
;
4329 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4331 mips_output_external_libcall (file
, name
)
4335 register struct extern_list
*p
;
4337 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4338 p
->next
= extern_head
;
4348 /* Compute a string to use as a temporary file name. */
4350 /* On MSDOS, write temp files in current dir
4351 because there's no place else we can expect to use. */
4354 #define P_tmpdir "./"
4362 char *base
= getenv ("TMPDIR");
4365 if (base
== (char *)0)
4368 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4372 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4378 len
= strlen (base
);
4379 /* temp_filename is global, so we must use malloc, not alloca. */
4380 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4381 strcpy (temp_filename
, base
);
4382 if (len
> 0 && temp_filename
[len
-1] != '/')
4383 temp_filename
[len
++] = '/';
4385 strcpy (temp_filename
+ len
, "ctXXXXXX");
4386 mktemp (temp_filename
);
4388 stream
= fopen (temp_filename
, "w+");
4390 pfatal_with_name (temp_filename
);
4393 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4394 it. Otherwise, we delete it now, so that it will be gone even if the
4395 compiler happens to crash. */
4396 unlink (temp_filename
);
4402 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4403 for .file's that start within a function. If we are smuggling stabs, try to
4404 put out a MIPS ECOFF file and a stab. */
4407 mips_output_filename (stream
, name
)
4411 static int first_time
= TRUE
;
4412 char ltext_label_name
[100];
4418 current_function_file
= name
;
4419 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4420 /* This tells mips-tfile that stabs will follow. */
4421 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4422 fprintf (stream
, "\t#@stabs\n");
4425 else if (write_symbols
== DBX_DEBUG
)
4427 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4428 fprintf (stream
, "%s ", ASM_STABS_OP
);
4429 output_quoted_string (stream
, name
);
4430 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4433 else if (name
!= current_function_file
4434 && strcmp (name
, current_function_file
) != 0)
4436 if (inside_function
&& !TARGET_GAS
)
4438 if (!file_in_function_warning
)
4440 file_in_function_warning
= TRUE
;
4441 ignore_line_number
= TRUE
;
4442 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4448 current_function_file
= name
;
4449 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4455 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4456 as well as a .loc, since it is possible that MIPS ECOFF might not be
4457 able to represent the location for inlines that come from a different
4461 mips_output_lineno (stream
, line
)
4465 if (write_symbols
== DBX_DEBUG
)
4468 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4469 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4470 LOCAL_LABEL_PREFIX
, sym_lineno
);
4475 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4476 (ignore_line_number
) ? "#" : "",
4477 num_source_filenames
, line
);
4479 LABEL_AFTER_LOC (stream
);
4484 /* If defined, a C statement to be executed just prior to the
4485 output of assembler code for INSN, to modify the extracted
4486 operands so they will be output differently.
4488 Here the argument OPVEC is the vector containing the operands
4489 extracted from INSN, and NOPERANDS is the number of elements of
4490 the vector which contain meaningful data for this insn. The
4491 contents of this vector are what will be used to convert the
4492 insn template into assembler code, so you can change the
4493 assembler output by changing the contents of the vector.
4495 We use it to check if the current insn needs a nop in front of it
4496 because of load delays, and also to update the delay slot
4499 /* ??? There is no real need for this function, because it never actually
4500 emits a NOP anymore. */
4503 final_prescan_insn (insn
, opvec
, noperands
)
4508 if (dslots_number_nops
> 0)
4510 rtx pattern
= PATTERN (insn
);
4511 int length
= get_attr_length (insn
);
4513 /* Do we need to emit a NOP? */
4515 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4516 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4517 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4518 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4519 fputs ("\t#nop\n", asm_out_file
);
4522 dslots_load_filled
++;
4524 while (--dslots_number_nops
> 0)
4525 fputs ("\t#nop\n", asm_out_file
);
4527 mips_load_reg
= (rtx
)0;
4528 mips_load_reg2
= (rtx
)0;
4529 mips_load_reg3
= (rtx
)0;
4530 mips_load_reg4
= (rtx
)0;
4535 enum rtx_code code
= GET_CODE (insn
);
4536 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4537 dslots_jump_total
++;
4542 /* Output at beginning of assembler file.
4543 If we are optimizing to use the global pointer, create a temporary
4544 file to hold all of the text stuff, and write it out to the end.
4545 This is needed because the MIPS assembler is evidently one pass,
4546 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4547 declaration when the code is processed, it generates a two
4548 instruction sequence. */
4551 mips_asm_file_start (stream
)
4554 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4556 /* Versions of the MIPS assembler before 2.20 generate errors
4557 if a branch inside of a .set noreorder section jumps to a
4558 label outside of the .set noreorder section. Revision 2.20
4559 just set nobopt silently rather than fixing the bug. */
4561 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4562 fprintf (stream
, "\t.set\tnobopt\n");
4564 /* Generate the pseudo ops that System V.4 wants. */
4565 #ifndef ABICALLS_ASM_OP
4566 #define ABICALLS_ASM_OP ".abicalls"
4568 if (TARGET_ABICALLS
)
4569 /* ??? but do not want this (or want pic0) if -non-shared? */
4570 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4572 /* Start a section, so that the first .popsection directive is guaranteed
4573 to have a previously defined section to pop back to. */
4574 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
4575 fprintf (stream
, "\t.section\t.text\n");
4577 /* This code exists so that we can put all externs before all symbol
4578 references. This is necessary for the MIPS assembler's global pointer
4579 optimizations to work. */
4580 if (TARGET_FILE_SWITCHING
)
4582 asm_out_data_file
= stream
;
4583 asm_out_text_file
= make_temp_file ();
4586 asm_out_data_file
= asm_out_text_file
= stream
;
4588 if (flag_verbose_asm
)
4589 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4591 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4595 /* If we are optimizing the global pointer, emit the text section now
4596 and any small externs which did not have .comm, etc that are
4597 needed. Also, give a warning if the data area is more than 32K and
4598 -pic because 3 instructions are needed to reference the data
4602 mips_asm_file_end (file
)
4607 struct extern_list
*p
;
4611 HALF_PIC_FINISH (file
);
4617 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4619 name_tree
= get_identifier (p
->name
);
4621 /* Positively ensure only one .extern for any given symbol. */
4622 if (! TREE_ASM_WRITTEN (name_tree
))
4624 TREE_ASM_WRITTEN (name_tree
) = 1;
4625 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4627 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4631 fputs ("\t.extern\t", file
);
4632 assemble_name (file
, p
->name
);
4633 fprintf (file
, ", %d\n", p
->size
);
4639 if (TARGET_FILE_SWITCHING
)
4641 fprintf (file
, "\n\t.text\n");
4642 rewind (asm_out_text_file
);
4643 if (ferror (asm_out_text_file
))
4644 fatal_io_error (temp_filename
);
4646 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4647 if (fwrite (buffer
, 1, len
, file
) != len
)
4648 pfatal_with_name (asm_file_name
);
4651 pfatal_with_name (temp_filename
);
4653 if (fclose (asm_out_text_file
) != 0)
4654 pfatal_with_name (temp_filename
);
4657 unlink (temp_filename
);
4663 /* Emit either a label, .comm, or .lcomm directive, and mark
4664 that the symbol is used, so that we don't emit an .extern
4665 for it in mips_asm_file_end. */
4668 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4675 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4676 assemble_name (stream
, name
);
4677 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4681 tree name_tree
= get_identifier (name
);
4682 TREE_ASM_WRITTEN (name_tree
) = 1;
4687 /* Output a double precision value to the assembler. If both the
4688 host and target are IEEE, emit the values in hex. */
4691 mips_output_double (stream
, value
)
4693 REAL_VALUE_TYPE value
;
4695 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4697 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4699 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4700 value_long
[0], value
, value_long
[1]);
4702 fprintf (stream
, "\t.double\t%.20g\n", value
);
4707 /* Output a single precision value to the assembler. If both the
4708 host and target are IEEE, emit the values in hex. */
4711 mips_output_float (stream
, value
)
4713 REAL_VALUE_TYPE value
;
4715 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4717 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4719 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4721 fprintf (stream
, "\t.float\t%.12g\n", value
);
4726 /* Return TRUE if any register used in the epilogue is used. This to insure
4727 any insn put into the epilogue delay slots is safe. */
4730 epilogue_reg_mentioned_p (insn
)
4735 register enum rtx_code code
;
4741 if (GET_CODE (insn
) == LABEL_REF
)
4744 code
= GET_CODE (insn
);
4748 regno
= REGNO (insn
);
4749 if (regno
== STACK_POINTER_REGNUM
)
4752 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4755 if (!call_used_regs
[regno
])
4758 if (regno
!= MIPS_TEMP1_REGNUM
&& regno
!= MIPS_TEMP2_REGNUM
)
4761 if (!current_frame_info
.initialized
)
4762 compute_frame_size (get_frame_size ());
4764 return (current_frame_info
.total_size
>= 32768);
4774 fmt
= GET_RTX_FORMAT (code
);
4775 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4780 for (j
= XVECLEN (insn
, i
) - 1; j
>= 0; j
--)
4781 if (epilogue_reg_mentioned_p (XVECEXP (insn
, i
, j
)))
4784 else if (fmt
[i
] == 'e' && epilogue_reg_mentioned_p (XEXP (insn
, i
)))
4791 /* Return the bytes needed to compute the frame pointer from the current
4794 Mips stack frames look like:
4796 Before call After call
4797 +-----------------------+ +-----------------------+
4800 | caller's temps. | | caller's temps. |
4802 +-----------------------+ +-----------------------+
4804 | arguments on stack. | | arguments on stack. |
4806 +-----------------------+ +-----------------------+
4807 | 4 words to save | | 4 words to save |
4808 | arguments passed | | arguments passed |
4809 | in registers, even | | in registers, even |
4810 SP->| if not passed. | VFP->| if not passed. |
4811 +-----------------------+ +-----------------------+
4813 | fp register save |
4815 +-----------------------+
4817 | gp register save |
4819 +-----------------------+
4823 +-----------------------+
4825 | alloca allocations |
4827 +-----------------------+
4829 | GP save for V.4 abi |
4831 +-----------------------+
4833 | arguments on stack |
4835 +-----------------------+
4837 | arguments passed |
4838 | in registers, even |
4839 low SP->| if not passed. |
4840 memory +-----------------------+
4845 compute_frame_size (size
)
4846 int size
; /* # of var. bytes allocated */
4849 long total_size
; /* # bytes that the entire frame takes up */
4850 long var_size
; /* # bytes that variables take up */
4851 long args_size
; /* # bytes that outgoing arguments take up */
4852 long extra_size
; /* # extra bytes */
4853 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4854 long gp_reg_size
; /* # bytes needed to store gp regs */
4855 long fp_reg_size
; /* # bytes needed to store fp regs */
4856 long mask
; /* mask of saved gp registers */
4857 long fmask
; /* mask of saved fp registers */
4858 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4859 long fp_bits
; /* bitmask to use for each fp register */
4865 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4866 var_size
= MIPS_STACK_ALIGN (size
);
4867 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4869 /* The MIPS 3.0 linker does not like functions that dynamically
4870 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4871 looks like we are trying to create a second frame pointer to the
4872 function, so allocate some stack space to make it happy. */
4874 if (args_size
== 0 && current_function_calls_alloca
)
4875 args_size
= 4*UNITS_PER_WORD
;
4877 total_size
= var_size
+ args_size
+ extra_size
;
4879 /* Calculate space needed for gp registers. */
4880 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4882 if (MUST_SAVE_REGISTER (regno
))
4884 gp_reg_size
+= UNITS_PER_WORD
;
4885 mask
|= 1L << (regno
- GP_REG_FIRST
);
4889 /* Calculate space needed for fp registers. */
4890 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4901 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4903 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4905 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4906 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4910 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4911 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4913 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4914 for leaf routines (total_size == extra_size) to save the gp reg.
4915 The gp reg is callee saved in the 64 bit ABI, so all routines must
4917 if (total_size
== extra_size
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
))
4918 total_size
= extra_size
= 0;
4919 else if (TARGET_ABICALLS
)
4921 /* Add the context-pointer to the saved registers. */
4922 gp_reg_size
+= UNITS_PER_WORD
;
4923 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4924 total_size
-= gp_reg_rounded
;
4925 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4926 total_size
+= gp_reg_rounded
;
4929 /* Add in space reserved on the stack by the callee for storing arguments
4930 passed in registers. */
4931 if (mips_abi
!= ABI_32
)
4932 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4934 /* Save other computed information. */
4935 current_frame_info
.total_size
= total_size
;
4936 current_frame_info
.var_size
= var_size
;
4937 current_frame_info
.args_size
= args_size
;
4938 current_frame_info
.extra_size
= extra_size
;
4939 current_frame_info
.gp_reg_size
= gp_reg_size
;
4940 current_frame_info
.fp_reg_size
= fp_reg_size
;
4941 current_frame_info
.mask
= mask
;
4942 current_frame_info
.fmask
= fmask
;
4943 current_frame_info
.initialized
= reload_completed
;
4944 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4945 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4949 unsigned long offset
= (args_size
+ extra_size
+ var_size
4950 + gp_reg_size
- UNITS_PER_WORD
);
4951 current_frame_info
.gp_sp_offset
= offset
;
4952 current_frame_info
.gp_save_offset
= offset
- total_size
;
4956 current_frame_info
.gp_sp_offset
= 0;
4957 current_frame_info
.gp_save_offset
= 0;
4963 unsigned long offset
= (args_size
+ extra_size
+ var_size
4964 + gp_reg_rounded
+ fp_reg_size
4965 - fp_inc
* UNITS_PER_FPREG
);
4966 current_frame_info
.fp_sp_offset
= offset
;
4967 current_frame_info
.fp_save_offset
= offset
- total_size
;
4971 current_frame_info
.fp_sp_offset
= 0;
4972 current_frame_info
.fp_save_offset
= 0;
4975 /* Ok, we're done. */
4980 /* Common code to emit the insns (or to write the instructions to a file)
4981 to save/restore registers.
4983 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4984 is not modified within save_restore_insns. */
4986 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4989 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4990 int store_p
; /* true if this is prologue */
4991 rtx large_reg
; /* register holding large offset constant or NULL */
4992 long large_offset
; /* large constant offset value */
4993 FILE *file
; /* file to write instructions to instead of making RTL */
4995 long mask
= current_frame_info
.mask
;
4996 long fmask
= current_frame_info
.fmask
;
5005 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
5008 if (mask
== 0 && fmask
== 0)
5011 /* Save registers starting from high to low. The debuggers prefer
5012 at least the return register be stored at func+4, and also it
5013 allows us not to need a nop in the epilog if at least one
5014 register is reloaded in addition to return address. */
5016 /* Save GP registers if needed. */
5019 /* Pick which pointer to use as a base register. For small
5020 frames, just use the stack pointer. Otherwise, use a
5021 temporary register. Save 2 cycles if the save area is near
5022 the end of a large frame, by reusing the constant created in
5023 the prologue/epilogue to adjust the stack frame. */
5025 gp_offset
= current_frame_info
.gp_sp_offset
;
5026 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
5028 if (gp_offset
< 0 || end_offset
< 0)
5029 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5030 gp_offset
, end_offset
);
5032 else if (gp_offset
< 32768)
5034 base_reg_rtx
= stack_pointer_rtx
;
5038 else if (large_reg
!= (rtx
)0
5039 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
5040 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5042 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5043 base_offset
= large_offset
;
5044 if (file
== (FILE *)0)
5047 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5049 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5050 RTX_FRAME_RELATED_P (insn
) = 1;
5053 fprintf (file
, "\t%s\t%s,%s,%s\n",
5054 TARGET_LONG64
? "daddu" : "addu",
5055 reg_names
[MIPS_TEMP2_REGNUM
],
5056 reg_names
[REGNO (large_reg
)],
5057 reg_names
[STACK_POINTER_REGNUM
]);
5062 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5063 base_offset
= gp_offset
;
5064 if (file
== (FILE *)0)
5066 insn
= emit_move_insn (base_reg_rtx
, GEN_INT (gp_offset
));
5067 RTX_FRAME_RELATED_P (insn
) = 1;
5069 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5071 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5072 RTX_FRAME_RELATED_P (insn
) = 1;
5075 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5076 reg_names
[MIPS_TEMP2_REGNUM
],
5079 TARGET_LONG64
? "daddu" : "addu",
5080 reg_names
[MIPS_TEMP2_REGNUM
],
5081 reg_names
[MIPS_TEMP2_REGNUM
],
5082 reg_names
[STACK_POINTER_REGNUM
]);
5085 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
5087 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
5089 if (file
== (FILE *)0)
5091 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
5092 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
5093 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5094 GEN_INT (gp_offset
- base_offset
)));
5098 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5099 RTX_FRAME_RELATED_P (insn
) = 1;
5101 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
5102 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5103 emit_move_insn (reg_rtx
, mem_rtx
);
5107 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
5108 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5109 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5111 ? (store_p
) ? "sd" : "ld"
5112 : (store_p
) ? "sw" : "lw"),
5114 gp_offset
- base_offset
,
5115 reg_names
[REGNO(base_reg_rtx
)]);
5118 gp_offset
-= UNITS_PER_WORD
;
5124 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
5128 /* Save floating point registers if needed. */
5131 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
5132 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
5134 /* Pick which pointer to use as a base register. */
5135 fp_offset
= current_frame_info
.fp_sp_offset
;
5136 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
5138 if (fp_offset
< 0 || end_offset
< 0)
5139 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5140 fp_offset
, end_offset
);
5142 else if (fp_offset
< 32768)
5144 base_reg_rtx
= stack_pointer_rtx
;
5148 else if (base_reg_rtx
!= (rtx
)0
5149 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
5150 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
5152 ; /* already set up for gp registers above */
5155 else if (large_reg
!= (rtx
)0
5156 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
5157 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5159 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5160 base_offset
= large_offset
;
5161 if (file
== (FILE *)0)
5164 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5166 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5167 RTX_FRAME_RELATED_P (insn
) = 1;
5170 fprintf (file
, "\t%s\t%s,%s,%s\n",
5171 TARGET_LONG64
? "daddu" : "addu",
5172 reg_names
[MIPS_TEMP2_REGNUM
],
5173 reg_names
[REGNO (large_reg
)],
5174 reg_names
[STACK_POINTER_REGNUM
]);
5179 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5180 base_offset
= fp_offset
;
5181 if (file
== (FILE *)0)
5183 insn
= emit_move_insn (base_reg_rtx
, GEN_INT (fp_offset
));
5184 RTX_FRAME_RELATED_P (insn
) = 1;
5186 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5188 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5189 RTX_FRAME_RELATED_P (insn
) = 1;
5192 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5193 reg_names
[MIPS_TEMP2_REGNUM
],
5196 TARGET_LONG64
? "daddu" : "addu",
5197 reg_names
[MIPS_TEMP2_REGNUM
],
5198 reg_names
[MIPS_TEMP2_REGNUM
],
5199 reg_names
[STACK_POINTER_REGNUM
]);
5202 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5204 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5206 if (file
== (FILE *)0)
5208 enum machine_mode sz
=
5209 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5210 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5211 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5212 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5213 GEN_INT (fp_offset
- base_offset
)));
5217 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5218 RTX_FRAME_RELATED_P (insn
) = 1;
5221 emit_move_insn (reg_rtx
, mem_rtx
);
5224 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5225 (TARGET_SINGLE_FLOAT
5226 ? ((store_p
) ? "s.s" : "l.s")
5227 : ((store_p
) ? "s.d" : "l.d")),
5229 fp_offset
- base_offset
,
5230 reg_names
[REGNO(base_reg_rtx
)]);
5233 fp_offset
-= fp_size
;
5240 /* Set up the stack and frame (if desired) for the function. */
5243 function_prologue (file
, size
)
5248 long tsize
= current_frame_info
.total_size
;
5250 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5252 #ifdef SDB_DEBUGGING_INFO
5253 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5254 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5257 inside_function
= 1;
5259 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5260 /* Get the function name the same way that toplev.c does before calling
5261 assemble_start_function. This is needed so that the name used here
5262 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5263 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5265 fputs ("\t.ent\t", file
);
5266 assemble_name (file
, fnname
);
5269 assemble_name (file
, fnname
);
5270 fputs (":\n", file
);
5273 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5274 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5276 reg_names
[31 + GP_REG_FIRST
],
5277 current_frame_info
.var_size
,
5278 current_frame_info
.num_gp
,
5279 current_frame_info
.num_fp
,
5280 current_function_outgoing_args_size
,
5281 current_frame_info
.extra_size
);
5283 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5284 current_frame_info
.mask
,
5285 current_frame_info
.gp_save_offset
,
5286 current_frame_info
.fmask
,
5287 current_frame_info
.fp_save_offset
);
5289 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5291 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5293 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5294 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5297 fprintf (file
, "\t%s\t%s,%s,%d\n",
5298 (TARGET_LONG64
? "dsubu" : "subu"),
5299 sp_str
, sp_str
, tsize
);
5300 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5306 /* Expand the prologue into a bunch of separate insns. */
5309 mips_expand_prologue ()
5313 rtx tmp_rtx
= (rtx
)0;
5314 char *arg_name
= (char *)0;
5315 tree fndecl
= current_function_decl
;
5316 tree fntype
= TREE_TYPE (fndecl
);
5317 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5322 CUMULATIVE_ARGS args_so_far
;
5324 /* If struct value address is treated as the first argument, make it so. */
5325 if (aggregate_value_p (DECL_RESULT (fndecl
))
5326 && ! current_function_returns_pcc_struct
5327 && struct_value_incoming_rtx
== 0)
5329 tree type
= build_pointer_type (fntype
);
5330 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5331 DECL_ARG_TYPE (function_result_decl
) = type
;
5332 TREE_CHAIN (function_result_decl
) = fnargs
;
5333 fnargs
= function_result_decl
;
5336 /* Determine the last argument, and get its name. */
5338 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5339 regno
= GP_ARG_FIRST
;
5341 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5343 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5344 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5347 if (TREE_ADDRESSABLE (passed_type
))
5349 passed_type
= build_pointer_type (passed_type
);
5350 passed_mode
= Pmode
;
5353 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5359 /* passed in a register, so will get homed automatically */
5360 if (GET_MODE (entry_parm
) == BLKmode
)
5361 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5363 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5365 regno
= REGNO (entry_parm
) + words
- 1;
5369 regno
= GP_ARG_LAST
+1;
5373 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5375 next_arg
= TREE_CHAIN (cur_arg
);
5376 if (next_arg
== (tree
)0)
5378 if (DECL_NAME (cur_arg
))
5379 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5385 /* In order to pass small structures by value in registers
5386 compatibly with the MIPS compiler, we need to shift the value
5387 into the high part of the register. Function_arg has encoded a
5388 PARALLEL rtx, holding a vector of adjustments to be made as the
5389 next_arg_reg variable, so we split up the insns, and emit them
5392 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5393 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5395 rtvec adjust
= XVEC (next_arg_reg
, 0);
5396 int num
= GET_NUM_ELEM (adjust
);
5398 for (i
= 0; i
< num
; i
++)
5400 rtx pattern
= RTVEC_ELT (adjust
, i
);
5401 if (GET_CODE (pattern
) != SET
5402 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5403 abort_with_insn (pattern
, "Insn is not a shift");
5405 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5406 emit_insn (pattern
);
5410 tsize
= compute_frame_size (get_frame_size ());
5412 /* If this function is a varargs function, store any registers that
5413 would normally hold arguments ($4 - $7) on the stack. */
5414 if (mips_abi
== ABI_32
5415 && ((TYPE_ARG_TYPES (fntype
) != 0
5416 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5417 || (arg_name
!= (char *)0
5418 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5419 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5421 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5422 rtx ptr
= stack_pointer_rtx
;
5424 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5425 if (TARGET_ABICALLS
)
5428 for (; regno
<= GP_ARG_LAST
; regno
++)
5431 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5432 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5433 gen_rtx (REG
, word_mode
, regno
));
5434 offset
+= UNITS_PER_WORD
;
5440 rtx tsize_rtx
= GEN_INT (tsize
);
5442 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5443 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5449 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5451 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5452 bit, so make sure that we don't emit anything that can be
5454 /* ??? There is no DImode ori immediate pattern, so we can only
5455 do this for 32 bit code. */
5456 if (large_int (tsize_rtx
) && GET_MODE (tmp_rtx
) == SImode
)
5458 insn
= emit_move_insn (tmp_rtx
,
5459 GEN_INT (tsize
& 0xffff0000));
5460 RTX_FRAME_RELATED_P (insn
) = 1;
5461 insn
= emit_insn (gen_iorsi3 (tmp_rtx
, tmp_rtx
,
5462 GEN_INT (tsize
& 0x0000ffff)));
5463 RTX_FRAME_RELATED_P (insn
) = 1;
5467 insn
= emit_move_insn (tmp_rtx
, tsize_rtx
);
5468 RTX_FRAME_RELATED_P (insn
) = 1;
5471 tsize_rtx
= tmp_rtx
;
5475 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5478 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5481 RTX_FRAME_RELATED_P (insn
) = 1;
5484 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5486 if (frame_pointer_needed
)
5491 insn
= emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5493 insn
= emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5495 RTX_FRAME_RELATED_P (insn
) = 1;
5498 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5499 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5502 /* If we are profiling, make sure no instructions are scheduled before
5503 the call to mcount. */
5505 if (profile_flag
|| profile_block_flag
)
5506 emit_insn (gen_blockage ());
5510 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5512 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5513 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5516 function_epilogue (file
, size
)
5522 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5523 char *t1_str
= reg_names
[MIPS_TEMP1_REGNUM
];
5524 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5525 int noreorder
= (epilogue_delay
!= 0);
5526 int noepilogue
= FALSE
;
5527 int load_nop
= FALSE
;
5529 rtx tmp_rtx
= (rtx
)0;
5533 /* The epilogue does not depend on any registers, but the stack
5534 registers, so we assume that if we have 1 pending nop, it can be
5535 ignored, and 2 it must be filled (2 nops occur for integer
5536 multiply and divide). */
5538 if (dslots_number_nops
> 0)
5540 if (dslots_number_nops
== 1)
5542 dslots_number_nops
= 0;
5543 dslots_load_filled
++;
5547 while (--dslots_number_nops
> 0)
5548 fputs ("\t#nop\n", asm_out_file
);
5555 fputs ("\t.set\tat\n", file
);
5556 error ("internal gcc error: .set noat left on in epilogue");
5559 if (set_nomacro
!= 0)
5562 fputs ("\t.set\tmacro\n", file
);
5563 error ("internal gcc error: .set nomacro left on in epilogue");
5566 if (set_noreorder
!= 0)
5569 fputs ("\t.set\treorder\n", file
);
5570 error ("internal gcc error: .set noreorder left on in epilogue");
5573 if (set_volatile
!= 0)
5576 fprintf (file
, "\t%s.set\tnovolatile\n", (TARGET_MIPS_AS
) ? "" : "#");
5577 error ("internal gcc error: .set volatile left on in epilogue");
5580 size
= MIPS_STACK_ALIGN (size
);
5581 tsize
= (!current_frame_info
.initialized
)
5582 ? compute_frame_size (size
)
5583 : current_frame_info
.total_size
;
5585 if (tsize
== 0 && epilogue_delay
== 0)
5587 rtx insn
= get_last_insn ();
5589 /* If the last insn was a BARRIER, we don't have to write any code
5590 because a jump (aka return) was put there. */
5591 if (GET_CODE (insn
) == NOTE
)
5592 insn
= prev_nonnote_insn (insn
);
5593 if (insn
&& GET_CODE (insn
) == BARRIER
)
5601 /* In the reload sequence, we don't need to fill the load delay
5602 slots for most of the loads, also see if we can fill the final
5603 delay slot if not otherwise filled by the reload sequence. */
5606 fprintf (file
, "\t.set\tnoreorder\n");
5610 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n", t1_str
, (long)tsize
, (long)tsize
);
5611 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5614 if (frame_pointer_needed
)
5615 fprintf (file
, "\tmove\t%s,%s\t\t\t# sp not trusted here\n",
5616 sp_str
, reg_names
[FRAME_POINTER_REGNUM
]);
5618 save_restore_insns (FALSE
, tmp_rtx
, tsize
, file
);
5620 load_only_r31
= (((current_frame_info
.mask
5621 & ~ (TARGET_ABICALLS
&& mips_abi
== ABI_32
5622 ? PIC_OFFSET_TABLE_MASK
: 0))
5624 && current_frame_info
.fmask
== 0);
5628 /* If the only register saved is the return address, we need a
5629 nop, unless we have an instruction to put into it. Otherwise
5630 we don't since reloading multiple registers doesn't reference
5631 the register being loaded. */
5636 final_scan_insn (XEXP (epilogue_delay
, 0),
5640 1); /* nopeepholes */
5643 fprintf (file
, "\tnop\n");
5648 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5651 fprintf (file
, "\t%s\t%s,%s,%s\n",
5652 TARGET_LONG64
? "daddu" : "addu",
5653 sp_str
, sp_str
, t1_str
);
5656 fprintf (file
, "\t%s\t%s,%s,%d\n",
5657 TARGET_LONG64
? "daddu" : "addu",
5658 sp_str
, sp_str
, tsize
);
5660 else if (!load_only_r31
&& epilogue_delay
!= 0)
5661 final_scan_insn (XEXP (epilogue_delay
, 0),
5665 1); /* nopeepholes */
5667 fprintf (file
, "\t.set\treorder\n");
5673 fprintf (file
, "\t%s\t%s,%s,%s\n",
5674 TARGET_LONG64
? "daddu" : "addu",
5675 sp_str
, sp_str
, t1_str
);
5678 fprintf (file
, "\t%s\t%s,%s,%d\n",
5679 TARGET_LONG64
? "daddu" : "addu",
5680 sp_str
, sp_str
, tsize
);
5682 fprintf (file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 31]);
5686 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5687 /* Get the function name the same way that toplev.c does before calling
5688 assemble_start_function. This is needed so that the name used here
5689 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5690 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5692 fputs ("\t.end\t", file
);
5693 assemble_name (file
, fnname
);
5699 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5700 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5701 int num_regs
= num_gp_regs
+ num_fp_regs
;
5702 char *name
= fnname
;
5707 dslots_load_total
+= num_regs
;
5710 dslots_jump_total
++;
5714 dslots_load_filled
+= num_regs
;
5716 /* If the only register saved is the return register, we
5717 can't fill this register's delay slot. */
5719 if (load_only_r31
&& epilogue_delay
== 0)
5720 dslots_load_filled
--;
5722 if (tsize
> 0 || (!load_only_r31
&& epilogue_delay
!= 0))
5723 dslots_jump_filled
++;
5727 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5729 (frame_pointer_needed
) ? 'y' : 'n',
5730 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5731 (current_function_calls_alloca
) ? 'y' : 'n',
5732 (current_function_calls_setjmp
) ? 'y' : 'n',
5733 (long)current_frame_info
.total_size
,
5734 (long)current_function_outgoing_args_size
,
5735 num_gp_regs
, num_fp_regs
,
5736 dslots_load_total
, dslots_load_filled
,
5737 dslots_jump_total
, dslots_jump_filled
,
5738 num_refs
[0], num_refs
[1], num_refs
[2]);
5740 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5742 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5743 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5746 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5748 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5749 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5752 fputc ('\n', stderr
);
5755 /* Reset state info for each function. */
5756 inside_function
= FALSE
;
5757 ignore_line_number
= FALSE
;
5758 dslots_load_total
= 0;
5759 dslots_jump_total
= 0;
5760 dslots_load_filled
= 0;
5761 dslots_jump_filled
= 0;
5765 mips_load_reg
= (rtx
)0;
5766 mips_load_reg2
= (rtx
)0;
5767 current_frame_info
= zero_frame_info
;
5769 /* Restore the output file if optimizing the GP (optimizing the GP causes
5770 the text to be diverted to a tempfile, so that data decls come before
5771 references to the data). */
5774 asm_out_file
= asm_out_data_file
;
5778 /* Expand the epilogue into a bunch of separate insns. */
5781 mips_expand_epilogue ()
5783 long tsize
= current_frame_info
.total_size
;
5784 rtx tsize_rtx
= GEN_INT (tsize
);
5785 rtx tmp_rtx
= (rtx
)0;
5789 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5790 emit_move_insn (tmp_rtx
, tsize_rtx
);
5791 tsize_rtx
= tmp_rtx
;
5796 if (frame_pointer_needed
)
5799 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5801 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5804 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5807 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5810 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5814 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
, GP_REG_FIRST
+31)));
5818 /* Define the number of delay slots needed for the function epilogue.
5820 On the mips, we need a slot if either no stack has been allocated,
5821 or the only register saved is the return register. */
5824 mips_epilogue_delay_slots ()
5826 if (!current_frame_info
.initialized
)
5827 (void) compute_frame_size (get_frame_size ());
5829 if (current_frame_info
.total_size
== 0)
5832 if (current_frame_info
.mask
== RA_MASK
&& current_frame_info
.fmask
== 0)
5839 /* Return true if this function is known to have a null epilogue.
5840 This allows the optimizer to omit jumps to jumps if no stack
5844 simple_epilogue_p ()
5846 if (!reload_completed
)
5849 if (current_frame_info
.initialized
)
5850 return current_frame_info
.total_size
== 0;
5852 return (compute_frame_size (get_frame_size ())) == 0;
5855 /* Choose the section to use for the constant rtx expression X that has
5858 mips_select_rtx_section (mode
, x
)
5859 enum machine_mode mode
;
5862 if (TARGET_EMBEDDED_DATA
)
5864 /* For embedded applications, always put constants in read-only data,
5865 in order to reduce RAM usage. */
5866 READONLY_DATA_SECTION ();
5870 /* For hosted applications, always put constants in small data if
5871 possible, as this gives the best performance. */
5873 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5874 && mips_section_threshold
> 0)
5875 SMALL_DATA_SECTION ();
5877 READONLY_DATA_SECTION ();
5881 /* Choose the section to use for DECL. RELOC is true if its value contains
5882 any relocatable expression. */
5884 mips_select_section (decl
, reloc
)
5888 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5890 if (TARGET_EMBEDDED_PIC
5891 && TREE_CODE (decl
) == STRING_CST
5892 && !flag_writable_strings
)
5894 /* For embedded position independent code, put constant strings
5895 in the text section, because the data section is limited to
5900 else if (TARGET_EMBEDDED_DATA
)
5902 /* For embedded applications, always put an object in read-only data
5903 if possible, in order to reduce RAM usage. */
5905 if (((TREE_CODE (decl
) == VAR_DECL
5906 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5907 && DECL_INITIAL (decl
)
5908 && (DECL_INITIAL (decl
) == error_mark_node
5909 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5910 /* Deal with calls from output_constant_def_contents. */
5911 || (TREE_CODE (decl
) != VAR_DECL
5912 && (TREE_CODE (decl
) != STRING_CST
5913 || !flag_writable_strings
)))
5914 && ! (flag_pic
&& reloc
))
5915 READONLY_DATA_SECTION ();
5916 else if (size
> 0 && size
<= mips_section_threshold
)
5917 SMALL_DATA_SECTION ();
5923 /* For hosted applications, always put an object in small data if
5924 possible, as this gives the best performance. */
5926 if (size
> 0 && size
<= mips_section_threshold
)
5927 SMALL_DATA_SECTION ();
5928 else if (((TREE_CODE (decl
) == VAR_DECL
5929 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5930 && DECL_INITIAL (decl
)
5931 && (DECL_INITIAL (decl
) == error_mark_node
5932 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5933 /* Deal with calls from output_constant_def_contents. */
5934 || (TREE_CODE (decl
) != VAR_DECL
5935 && (TREE_CODE (decl
) != STRING_CST
5936 || !flag_writable_strings
)))
5937 && ! (flag_pic
&& reloc
))
5938 READONLY_DATA_SECTION ();
5944 #ifdef MIPS_ABI_DEFAULT
5945 /* Support functions for the 64 bit ABI. */
5947 /* Return register to use for a function return value with VALTYPE for function
5951 mips_function_value (valtype
, func
)
5955 int reg
= GP_RETURN
;
5956 enum machine_mode mode
= TYPE_MODE (valtype
);
5957 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5959 /* ??? How should we return complex float? */
5960 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5962 if (TARGET_SINGLE_FLOAT
5963 && (mclass
== MODE_FLOAT
5964 ? GET_MODE_SIZE (mode
) > 4
5965 : GET_MODE_SIZE (mode
) / 2 > 4))
5970 else if (TREE_CODE (valtype
) == RECORD_TYPE
5971 && mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
5973 /* A struct with only one or two floating point fields is returned in
5974 the floating point registers. */
5975 tree field
, fields
[2];
5978 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5979 field
= TREE_CHAIN (field
))
5981 if (TREE_CODE (field
) != FIELD_DECL
)
5983 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5986 fields
[i
++] = field
;
5989 /* Must check i, so that we reject structures with no elements. */
5994 /* The structure has DImode, but we don't allow DImode values
5995 in FP registers, so we use a PARALLEL even though it isn't
5996 strictly necessary. */
5997 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5999 return gen_rtx (PARALLEL
, mode
,
6001 gen_rtx (EXPR_LIST
, VOIDmode
,
6002 gen_rtx (REG
, field_mode
, FP_RETURN
),
6007 enum machine_mode first_mode
6008 = TYPE_MODE (TREE_TYPE (fields
[0]));
6009 enum machine_mode second_mode
6010 = TYPE_MODE (TREE_TYPE (fields
[1]));
6012 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
6014 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
6016 return gen_rtx (PARALLEL
, mode
,
6018 gen_rtx (EXPR_LIST
, VOIDmode
,
6019 gen_rtx (REG
, first_mode
, FP_RETURN
),
6020 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
6021 gen_rtx (EXPR_LIST
, VOIDmode
,
6022 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
6023 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
6028 return gen_rtx (REG
, mode
, reg
);
6031 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
6032 nonzero when an argument must be passed by reference. */
6035 function_arg_pass_by_reference (cum
, mode
, type
, named
)
6036 CUMULATIVE_ARGS
*cum
;
6037 enum machine_mode mode
;
6043 if (mips_abi
!= ABI_EABI
)
6046 /* ??? How should SCmode be handled? */
6047 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
6050 size
= int_size_in_bytes (type
);
6051 return size
== -1 || size
> UNITS_PER_WORD
;
6056 /* This function returns the register class required for a secondary
6057 register when copying between one of the registers in CLASS, and X,
6058 using MODE. If IN_P is nonzero, the copy is going from X to the
6059 register, otherwise the register is the source. A return value of
6060 NO_REGS means that no secondary register is required. */
6063 mips_secondary_reload_class (class, mode
, x
, in_p
)
6064 enum reg_class
class;
6065 enum machine_mode mode
;
6071 if (GET_CODE (x
) == SIGN_EXTEND
)
6077 /* We may be called with reg_renumber NULL from regclass.
6078 ??? This is probably a bug. */
6080 regno
= true_regnum (x
);
6083 while (GET_CODE (x
) == SUBREG
)
6085 off
+= SUBREG_WORD (x
);
6088 if (GET_CODE (x
) == REG
)
6089 regno
= REGNO (x
) + off
;
6092 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
6093 regno
= true_regnum (x
);
6095 /* We always require a general register when copying anything to
6096 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
6097 to a general register, or when copying from register 0. */
6098 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
6102 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6106 if (regno
== HILO_REGNUM
)
6110 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
6115 /* Copying from HI or LO to anywhere other than a general register
6116 requires a general register. */
6117 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
6119 if (GP_REG_P (regno
))
6123 if (MD_REG_P (regno
))
6125 if (class == GR_REGS
)
6130 /* We can only copy a value to a condition code register from a
6131 floating point register, and even then we require a scratch
6132 floating point register. We can only copy a value out of a
6133 condition code register into a general register. */
6134 if (class == ST_REGS
)
6138 if (GP_REG_P (regno
))
6142 if (ST_REG_P (regno
))
6146 if (class == GR_REGS
)