1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-96, 1997 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-flags.h"
40 #include "insn-attr.h"
41 #include "insn-codes.h"
45 #undef MAX /* sys/param.h may also define these */
49 #include <sys/types.h>
62 #if defined(USG) || defined(NO_STAB_H)
63 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
65 #include <stab.h> /* On BSD, use the system's stab.h. */
69 #define STAB_CODE_TYPE enum __stab_debug_code
71 #define STAB_CODE_TYPE int
76 extern char *getenv ();
77 extern char *mktemp ();
79 extern rtx
adj_offsettable_operand ();
80 extern rtx
copy_to_reg ();
82 extern tree
lookup_name ();
83 extern void pfatal_with_name ();
84 extern void warning ();
86 extern FILE *asm_out_file
;
88 /* Enumeration for all of the relational tests, so that we can build
89 arrays indexed by the test type, and not worry about the order
106 /* Global variables for machine-dependent things. */
108 /* Threshold for data being put into the small data/bss area, instead
109 of the normal data area (references to the small data/bss area take
110 1 instruction, and use the global pointer, references to the normal
111 data area takes 2 instructions). */
112 int mips_section_threshold
= -1;
114 /* Count the number of .file directives, so that .loc is up to date. */
115 int num_source_filenames
= 0;
117 /* Count the number of sdb related labels are generated (to find block
118 start and end boundaries). */
119 int sdb_label_count
= 0;
121 /* Next label # for each statement for Silicon Graphics IRIS systems. */
124 /* Non-zero if inside of a function, because the stupid MIPS asm can't
125 handle .files inside of functions. */
126 int inside_function
= 0;
128 /* Files to separate the text and the data output, so that all of the data
129 can be emitted before the text, which will mean that the assembler will
130 generate smaller code, based on the global pointer. */
131 FILE *asm_out_data_file
;
132 FILE *asm_out_text_file
;
134 /* Linked list of all externals that are to be emitted when optimizing
135 for the global pointer if they haven't been declared by the end of
136 the program with an appropriate .comm or initialization. */
139 struct extern_list
*next
; /* next external */
140 char *name
; /* name of the external */
141 int size
; /* size in bytes */
144 /* Name of the file containing the current function. */
145 char *current_function_file
= "";
147 /* Warning given that Mips ECOFF can't support changing files
148 within a function. */
149 int file_in_function_warning
= FALSE
;
151 /* Whether to suppress issuing .loc's because the user attempted
152 to change the filename within a function. */
153 int ignore_line_number
= FALSE
;
155 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
161 /* The next branch instruction is a branch likely, not branch normal. */
162 int mips_branch_likely
;
164 /* Count of delay slots and how many are filled. */
165 int dslots_load_total
;
166 int dslots_load_filled
;
167 int dslots_jump_total
;
168 int dslots_jump_filled
;
170 /* # of nops needed by previous insn */
171 int dslots_number_nops
;
173 /* Number of 1/2/3 word references to data items (ie, not jal's). */
176 /* registers to check for load delay */
177 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
179 /* Cached operands, and operator to compare for use in set/branch on
183 /* what type of branch to use */
184 enum cmp_type branch_type
;
186 /* Number of previously seen half-pic pointers and references. */
187 static int prev_half_pic_ptrs
= 0;
188 static int prev_half_pic_refs
= 0;
190 /* which cpu are we scheduling for */
191 enum processor_type mips_cpu
;
193 /* which instruction set architecture to use. */
196 #ifdef MIPS_ABI_DEFAULT
197 /* Which ABI to use. This is defined to a constant in mips.h if the target
198 doesn't support multiple ABIs. */
202 /* Strings to hold which cpu and instruction set architecture to use. */
203 char *mips_cpu_string
; /* for -mcpu=<xxx> */
204 char *mips_isa_string
; /* for -mips{1,2,3,4} */
205 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64,eabi} */
207 /* If TRUE, we split addresses into their high and low parts in the RTL. */
208 int mips_split_addresses
;
210 /* Generating calls to position independent functions? */
211 enum mips_abicalls_type mips_abicalls
;
213 /* High and low marks for floating point values which we will accept
214 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
215 initialized in override_options. */
216 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
218 /* Array giving truth value on whether or not a given hard register
219 can support a given mode. */
220 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
222 /* Current frame information calculated by compute_frame_size. */
223 struct mips_frame_info current_frame_info
;
225 /* Zero structure to initialize current_frame_info. */
226 struct mips_frame_info zero_frame_info
;
228 /* Temporary filename used to buffer .text until end of program
230 static char *temp_filename
;
232 /* Pseudo-reg holding the address of the current function when
233 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
234 by mips_finalize_pic if it was created. */
235 rtx embedded_pic_fnaddr_rtx
;
237 /* List of all MIPS punctuation characters used by print_operand. */
238 char mips_print_operand_punct
[256];
240 /* Map GCC register number to debugger register number. */
241 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
243 /* Buffer to use to enclose a load/store operation with %{ %} to
244 turn on .set volatile. */
245 static char volatile_buffer
[60];
247 /* Hardware names for the registers. If -mrnames is used, this
248 will be overwritten with mips_sw_reg_names. */
250 char mips_reg_names
[][8] =
252 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
253 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
254 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
255 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
256 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
257 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
258 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
259 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
260 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
261 "$fcc5","$fcc6","$fcc7","$rap"
264 /* Mips software names for the registers, used to overwrite the
265 mips_reg_names array. */
267 char mips_sw_reg_names
[][8] =
269 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
270 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
271 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
272 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
273 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
274 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
275 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
276 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
277 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
278 "$fcc5","$fcc6","$fcc7","$rap"
281 /* Map hard register number to register class */
282 enum reg_class mips_regno_to_class
[] =
284 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
285 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
286 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
287 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
288 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
289 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
290 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
291 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
292 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
293 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
294 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
295 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
296 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
297 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
298 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
299 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
300 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
301 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
302 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
305 /* Map register constraint character to register class. */
306 enum reg_class mips_char_to_class
[256] =
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
360 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
361 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
362 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
364 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
365 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
366 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
367 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
368 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
369 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
370 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
371 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
375 /* Return truth value of whether OP can be used as an operands
376 where a register or 16 bit unsigned integer is needed. */
379 uns_arith_operand (op
, mode
)
381 enum machine_mode mode
;
383 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
386 return register_operand (op
, mode
);
389 /* Return truth value of whether OP can be used as an operands
390 where a 16 bit integer is needed */
393 arith_operand (op
, mode
)
395 enum machine_mode mode
;
397 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
400 return register_operand (op
, mode
);
403 /* Return truth value of whether OP can be used as an operand in a two
404 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
407 arith32_operand (op
, mode
)
409 enum machine_mode mode
;
411 if (GET_CODE (op
) == CONST_INT
)
414 return register_operand (op
, mode
);
417 /* Return truth value of whether OP is a integer which fits in 16 bits */
422 enum machine_mode mode
;
424 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
427 /* Return truth value of whether OP is a 32 bit integer which is too big to
428 be loaded with one instruction. */
433 enum machine_mode mode
;
437 if (GET_CODE (op
) != CONST_INT
)
441 if ((value
& ~0x0000ffff) == 0) /* ior reg,$r0,value */
444 if (((unsigned long)(value
+ 32768)) <= 32767) /* subu reg,$r0,value */
447 if ((value
& 0x0000ffff) == 0) /* lui reg,value>>16 */
453 /* Return truth value of whether OP is a register or the constant 0. */
456 reg_or_0_operand (op
, mode
)
458 enum machine_mode mode
;
460 switch (GET_CODE (op
))
466 return (INTVAL (op
) == 0);
469 if (op
!= CONST0_RTX (mode
))
476 return register_operand (op
, mode
);
482 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
485 mips_const_double_ok (op
, mode
)
487 enum machine_mode mode
;
491 if (GET_CODE (op
) != CONST_DOUBLE
)
494 if (mode
== VOIDmode
)
497 if (mode
!= SFmode
&& mode
!= DFmode
)
500 if (op
== CONST0_RTX (mode
))
503 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
504 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
507 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
509 if (REAL_VALUE_ISNAN (d
))
512 if (REAL_VALUE_NEGATIVE (d
))
513 d
= REAL_VALUE_NEGATE (d
);
517 if (REAL_VALUES_LESS (d
, dfhigh
)
518 && REAL_VALUES_LESS (dflow
, d
))
523 if (REAL_VALUES_LESS (d
, sfhigh
)
524 && REAL_VALUES_LESS (sflow
, d
))
531 /* Accept the floating point constant 1 in the appropriate mode. */
534 const_float_1_operand (op
, mode
)
536 enum machine_mode mode
;
539 static REAL_VALUE_TYPE onedf
;
540 static REAL_VALUE_TYPE onesf
;
541 static int one_initialized
;
543 if (GET_CODE (op
) != CONST_DOUBLE
544 || mode
!= GET_MODE (op
)
545 || (mode
!= DFmode
&& mode
!= SFmode
))
548 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
550 /* We only initialize these values if we need them, since we will
551 never get called unless mips_isa >= 4. */
552 if (! one_initialized
)
554 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
555 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
556 one_initialized
= TRUE
;
560 return REAL_VALUES_EQUAL (d
, onedf
);
562 return REAL_VALUES_EQUAL (d
, onesf
);
565 /* Return truth value if a memory operand fits in a single instruction
566 (ie, register + small offset). */
569 simple_memory_operand (op
, mode
)
571 enum machine_mode mode
;
573 rtx addr
, plus0
, plus1
;
575 /* Eliminate non-memory operations */
576 if (GET_CODE (op
) != MEM
)
579 /* dword operations really put out 2 instructions, so eliminate them. */
580 /* ??? This isn't strictly correct. It is OK to accept multiword modes
581 here, since the length attributes are being set correctly, but only
582 if the address is offsettable. LO_SUM is not offsettable. */
583 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
586 /* Decode the address now. */
588 switch (GET_CODE (addr
))
598 return SMALL_INT (op
);
601 plus0
= XEXP (addr
, 0);
602 plus1
= XEXP (addr
, 1);
603 if (GET_CODE (plus0
) == REG
604 && GET_CODE (plus1
) == CONST_INT
605 && SMALL_INT (plus1
))
608 else if (GET_CODE (plus1
) == REG
609 && GET_CODE (plus0
) == CONST_INT
610 && SMALL_INT (plus0
))
617 /* We used to allow small symbol refs here (ie, stuff in .sdata
618 or .sbss), but this causes some bugs in G++. Also, it won't
619 interfere if the MIPS linker rewrites the store instruction
620 because the function is PIC. */
622 case LABEL_REF
: /* never gp relative */
626 /* If -G 0, we can never have a GP relative memory operation.
627 Also, save some time if not optimizing. */
632 rtx offset
= const0_rtx
;
633 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
634 if (GET_CODE (op
) != SYMBOL_REF
)
637 /* let's be paranoid.... */
638 if (! SMALL_INT (offset
))
644 return SYMBOL_REF_FLAG (addr
);
651 /* Return true if the code of this rtx pattern is EQ or NE. */
654 equality_op (op
, mode
)
656 enum machine_mode mode
;
658 if (mode
!= GET_MODE (op
))
661 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
664 /* Return true if the code is a relational operations (EQ, LE, etc.) */
669 enum machine_mode mode
;
671 if (mode
!= GET_MODE (op
))
674 return (GET_RTX_CLASS (GET_CODE (op
)) == '<');
677 /* Return true if the operand is either the PC or a label_ref. */
680 pc_or_label_operand (op
, mode
)
682 enum machine_mode mode
;
687 if (GET_CODE (op
) == LABEL_REF
)
693 /* Test for a valid operand for a call instruction.
694 Don't allow the arg pointer register or virtual regs
695 since they may change into reg + const, which the patterns
699 call_insn_operand (op
, mode
)
701 enum machine_mode mode
;
703 if (CONSTANT_ADDRESS_P (op
)
704 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
705 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
706 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
711 /* Return true if OPERAND is valid as a source operand for a move
715 move_operand (op
, mode
)
717 enum machine_mode mode
;
719 /* Accept any general operand after reload has started; doing so
720 avoids losing if reload does an in-place replacement of a register
721 with a SYMBOL_REF or CONST. */
722 return (general_operand (op
, mode
)
723 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
724 || reload_in_progress
725 || reload_completed
));
730 /* Return true if OPERAND is valid as a source operand for movdi.
731 This accepts not only general_operand, but also sign extended
732 constants and registers. We need to accept sign extended constants
733 in case a sign extended register which is used in an expression,
734 and is equivalent to a constant, is spilled. */
737 movdi_operand (op
, mode
)
739 enum machine_mode mode
;
743 && GET_CODE (op
) == SIGN_EXTEND
744 && GET_MODE (op
) == DImode
745 && (GET_MODE (XEXP (op
, 0)) == SImode
746 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
747 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
748 && (register_operand (XEXP (op
, 0), SImode
)
749 || immediate_operand (XEXP (op
, 0), SImode
)))
752 return general_operand (op
, mode
);
755 /* Like register_operand, but when in 64 bit mode also accept a sign
756 extend of a 32 bit register, since the value is known to be already
760 se_register_operand (op
, mode
)
762 enum machine_mode mode
;
766 && GET_CODE (op
) == SIGN_EXTEND
767 && GET_MODE (op
) == DImode
768 && GET_MODE (XEXP (op
, 0)) == SImode
769 && register_operand (XEXP (op
, 0), SImode
))
772 return register_operand (op
, mode
);
775 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
776 extend of a 32 bit register, since the value is known to be already
780 se_reg_or_0_operand (op
, mode
)
782 enum machine_mode mode
;
786 && GET_CODE (op
) == SIGN_EXTEND
787 && GET_MODE (op
) == DImode
788 && GET_MODE (XEXP (op
, 0)) == SImode
789 && register_operand (XEXP (op
, 0), SImode
))
792 return reg_or_0_operand (op
, mode
);
795 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
796 extend of a 32 bit register, since the value is known to be already
800 se_uns_arith_operand (op
, mode
)
802 enum machine_mode mode
;
806 && GET_CODE (op
) == SIGN_EXTEND
807 && GET_MODE (op
) == DImode
808 && GET_MODE (XEXP (op
, 0)) == SImode
809 && register_operand (XEXP (op
, 0), SImode
))
812 return uns_arith_operand (op
, mode
);
815 /* Like arith_operand, but when in 64 bit mode also accept a sign
816 extend of a 32 bit register, since the value is known to be already
820 se_arith_operand (op
, mode
)
822 enum machine_mode mode
;
826 && GET_CODE (op
) == SIGN_EXTEND
827 && GET_MODE (op
) == DImode
828 && GET_MODE (XEXP (op
, 0)) == SImode
829 && register_operand (XEXP (op
, 0), SImode
))
832 return arith_operand (op
, mode
);
835 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
836 extend of a 32 bit register, since the value is known to be already
840 se_nonmemory_operand (op
, mode
)
842 enum machine_mode mode
;
846 && GET_CODE (op
) == SIGN_EXTEND
847 && GET_MODE (op
) == DImode
848 && GET_MODE (XEXP (op
, 0)) == SImode
849 && register_operand (XEXP (op
, 0), SImode
))
852 return nonmemory_operand (op
, mode
);
855 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
856 sign extend of a 32 bit register, since the value is known to be
857 already sign extended. */
860 se_nonimmediate_operand (op
, mode
)
862 enum machine_mode mode
;
866 && GET_CODE (op
) == SIGN_EXTEND
867 && GET_MODE (op
) == DImode
868 && GET_MODE (XEXP (op
, 0)) == SImode
869 && register_operand (XEXP (op
, 0), SImode
))
872 return nonimmediate_operand (op
, mode
);
875 /* Return true if we split the address into high and low parts. */
877 /* ??? We should also handle reg+array somewhere. We get four
878 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
879 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
880 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
881 out of the address, then we have 4 instructions to combine. Perhaps
882 add a 3->2 define_split for combine. */
884 /* ??? We could also split a CONST_INT here if it is a large_int().
885 However, it doesn't seem to be very useful to have %hi(constant).
886 We would be better off by doing the masking ourselves and then putting
887 the explicit high part of the constant in the RTL. This will give better
888 optimization. Also, %hi(constant) needs assembler changes to work.
889 There is already a define_split that does this. */
892 mips_check_split (address
, mode
)
894 enum machine_mode mode
;
896 /* ??? This is the same check used in simple_memory_operand.
897 We use it here because LO_SUM is not offsettable. */
898 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
901 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
902 || (GET_CODE (address
) == CONST
903 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
904 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
905 || GET_CODE (address
) == LABEL_REF
)
911 /* Returns an operand string for the given instruction's delay slot,
912 after updating filled delay slot statistics.
914 We assume that operands[0] is the target register that is set.
916 In order to check the next insn, most of this functionality is moved
917 to FINAL_PRESCAN_INSN, and we just set the global variables that
920 /* ??? This function no longer does anything useful, because final_prescan_insn
921 now will never emit a nop. */
924 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
925 char *ret
; /* normal string to return */
926 enum delay_type type
; /* type of delay */
927 rtx operands
[]; /* operands to use */
928 rtx cur_insn
; /* current insn */
930 register rtx set_reg
;
931 register enum machine_mode mode
;
932 register rtx next_insn
= (cur_insn
) ? NEXT_INSN (cur_insn
) : (rtx
)0;
933 register int num_nops
;
935 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
938 else if (type
== DELAY_HILO
)
944 /* Make sure that we don't put nop's after labels. */
945 next_insn
= NEXT_INSN (cur_insn
);
946 while (next_insn
!= (rtx
)0 && GET_CODE (next_insn
) == NOTE
)
947 next_insn
= NEXT_INSN (next_insn
);
949 dslots_load_total
+= num_nops
;
950 if (TARGET_DEBUG_F_MODE
952 || type
== DELAY_NONE
953 || operands
== (rtx
*)0
954 || cur_insn
== (rtx
)0
955 || next_insn
== (rtx
)0
956 || GET_CODE (next_insn
) == CODE_LABEL
957 || (set_reg
= operands
[0]) == (rtx
)0)
959 dslots_number_nops
= 0;
960 mips_load_reg
= (rtx
)0;
961 mips_load_reg2
= (rtx
)0;
962 mips_load_reg3
= (rtx
)0;
963 mips_load_reg4
= (rtx
)0;
967 set_reg
= operands
[0];
968 if (set_reg
== (rtx
)0)
971 while (GET_CODE (set_reg
) == SUBREG
)
972 set_reg
= SUBREG_REG (set_reg
);
974 mode
= GET_MODE (set_reg
);
975 dslots_number_nops
= num_nops
;
976 mips_load_reg
= set_reg
;
977 if (GET_MODE_SIZE (mode
)
978 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
979 mips_load_reg2
= gen_rtx (REG
, SImode
, REGNO (set_reg
) + 1);
983 if (type
== DELAY_HILO
)
985 mips_load_reg3
= gen_rtx (REG
, SImode
, MD_REG_FIRST
);
986 mips_load_reg4
= gen_rtx (REG
, SImode
, MD_REG_FIRST
+1);
998 /* Determine whether a memory reference takes one (based off of the GP pointer),
999 two (normal), or three (label + reg) instructions, and bump the appropriate
1000 counter for -mstats. */
1003 mips_count_memory_refs (op
, num
)
1009 rtx addr
, plus0
, plus1
;
1010 enum rtx_code code0
, code1
;
1013 if (TARGET_DEBUG_B_MODE
)
1015 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1019 /* Skip MEM if passed, otherwise handle movsi of address. */
1020 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1022 /* Loop, going through the address RTL */
1026 switch (GET_CODE (addr
))
1037 plus0
= XEXP (addr
, 0);
1038 plus1
= XEXP (addr
, 1);
1039 code0
= GET_CODE (plus0
);
1040 code1
= GET_CODE (plus1
);
1050 if (code0
== CONST_INT
)
1065 if (code1
== CONST_INT
)
1072 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1079 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1089 n_words
= 2; /* always 2 words */
1093 addr
= XEXP (addr
, 0);
1098 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1107 n_words
+= additional
;
1111 num_refs
[n_words
-1] += num
;
1115 /* Return RTL for the offset from the current function to the
1119 embedded_pic_offset (x
)
1122 if (embedded_pic_fnaddr_rtx
== NULL
)
1126 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1128 /* Output code at function start to initialize the pseudo-reg. */
1129 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1130 inline functions, because it is called after RTL for the function
1131 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1132 does not get copied, and ends up not matching the rest of the RTL.
1133 This solution works, but means that we get unnecessary code to
1134 initialize this value every time a function is inlined into another
1137 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1138 XEXP (DECL_RTL (current_function_decl
), 0)));
1139 seq
= gen_sequence ();
1141 push_topmost_sequence ();
1142 emit_insn_after (seq
, get_insns ());
1143 pop_topmost_sequence ();
1146 return gen_rtx (CONST
, Pmode
,
1147 gen_rtx (MINUS
, Pmode
, x
,
1148 XEXP (DECL_RTL (current_function_decl
), 0)));
1151 /* Return the appropriate instructions to move one operand to another. */
1154 mips_move_1word (operands
, insn
, unsignedp
)
1160 rtx op0
= operands
[0];
1161 rtx op1
= operands
[1];
1162 enum rtx_code code0
= GET_CODE (op0
);
1163 enum rtx_code code1
= GET_CODE (op1
);
1164 enum machine_mode mode
= GET_MODE (op0
);
1165 int subreg_word0
= 0;
1166 int subreg_word1
= 0;
1167 enum delay_type delay
= DELAY_NONE
;
1169 while (code0
== SUBREG
)
1171 subreg_word0
+= SUBREG_WORD (op0
);
1172 op0
= SUBREG_REG (op0
);
1173 code0
= GET_CODE (op0
);
1176 while (code1
== SUBREG
)
1178 subreg_word1
+= SUBREG_WORD (op1
);
1179 op1
= SUBREG_REG (op1
);
1180 code1
= GET_CODE (op1
);
1183 /* For our purposes, a condition code mode is the same as SImode. */
1189 int regno0
= REGNO (op0
) + subreg_word0
;
1193 int regno1
= REGNO (op1
) + subreg_word1
;
1195 /* Just in case, don't do anything for assigning a register
1196 to itself, unless we are filling a delay slot. */
1197 if (regno0
== regno1
&& set_nomacro
== 0)
1200 else if (GP_REG_P (regno0
))
1202 if (GP_REG_P (regno1
))
1203 ret
= "move\t%0,%1";
1205 else if (MD_REG_P (regno1
))
1208 if (regno1
!= HILO_REGNUM
)
1214 else if (ST_REG_P (regno1
) && mips_isa
>= 4)
1215 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1220 if (FP_REG_P (regno1
))
1221 ret
= "mfc1\t%0,%1";
1223 else if (regno1
== FPSW_REGNUM
&& mips_isa
< 4)
1224 ret
= "cfc1\t%0,$31";
1228 else if (FP_REG_P (regno0
))
1230 if (GP_REG_P (regno1
))
1233 ret
= "mtc1\t%1,%0";
1236 if (FP_REG_P (regno1
))
1237 ret
= "mov.s\t%0,%1";
1240 else if (MD_REG_P (regno0
))
1242 if (GP_REG_P (regno1
))
1245 if (regno0
!= HILO_REGNUM
)
1250 else if (regno0
== FPSW_REGNUM
&& mips_isa
< 4)
1252 if (GP_REG_P (regno1
))
1255 ret
= "ctc1\t%0,$31";
1260 else if (code1
== MEM
)
1265 mips_count_memory_refs (op1
, 1);
1267 if (GP_REG_P (regno0
))
1269 /* For loads, use the mode of the memory item, instead of the
1270 target, so zero/sign extend can use this code as well. */
1271 switch (GET_MODE (op1
))
1280 ret
= ((unsignedp
&& TARGET_64BIT
)
1285 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1288 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1293 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1296 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1298 int i
= strlen (ret
);
1299 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1302 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1303 ret
= volatile_buffer
;
1307 else if (code1
== CONST_INT
1308 || (code1
== CONST_DOUBLE
1309 && GET_MODE (op1
) == VOIDmode
))
1311 if (code1
== CONST_DOUBLE
)
1313 /* This can happen when storing constants into long long
1314 bitfields. Just store the least significant word of
1316 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1319 if (INTVAL (op1
) == 0)
1321 if (GP_REG_P (regno0
))
1322 ret
= "move\t%0,%z1";
1324 else if (FP_REG_P (regno0
))
1327 ret
= "mtc1\t%z1,%0";
1330 else if (MD_REG_P (regno0
))
1337 else if (GP_REG_P (regno0
))
1338 /* Don't use X format, because that will give out of range
1339 numbers for 64 bit host and 32 bit target. */
1340 ret
= "li\t%0,%1\t\t\t# %X1";
1343 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1345 if (op1
== CONST0_RTX (SFmode
))
1347 if (GP_REG_P (regno0
))
1348 ret
= "move\t%0,%.";
1350 else if (FP_REG_P (regno0
))
1353 ret
= "mtc1\t%.,%0";
1360 ret
= "li.s\t%0,%1";
1364 else if (code1
== LABEL_REF
)
1367 mips_count_memory_refs (op1
, 1);
1372 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1374 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1376 rtx offset
= const0_rtx
;
1378 if (GET_CODE (op1
) == CONST
)
1379 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1381 if (GET_CODE (op1
) == SYMBOL_REF
)
1383 operands
[2] = HALF_PIC_PTR (op1
);
1386 mips_count_memory_refs (operands
[2], 1);
1388 if (INTVAL (offset
) == 0)
1391 ret
= (unsignedp
&& TARGET_64BIT
1397 dslots_load_total
++;
1398 operands
[3] = offset
;
1399 if (unsignedp
&& TARGET_64BIT
)
1400 ret
= (SMALL_INT (offset
))
1401 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1402 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1404 ret
= (SMALL_INT (offset
))
1405 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1406 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1413 mips_count_memory_refs (op1
, 1);
1419 else if (code1
== PLUS
)
1421 rtx add_op0
= XEXP (op1
, 0);
1422 rtx add_op1
= XEXP (op1
, 1);
1424 if (GET_CODE (XEXP (op1
, 1)) == REG
&& GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1426 add_op0
= XEXP (op1
, 1); /* reverse operands */
1427 add_op1
= XEXP (op1
, 0);
1430 operands
[2] = add_op0
;
1431 operands
[3] = add_op1
;
1432 ret
= "add%:\t%0,%2,%3";
1435 else if (code1
== HIGH
)
1437 operands
[1] = XEXP (op1
, 0);
1438 ret
= "lui\t%0,%%hi(%1)";
1442 else if (code0
== MEM
)
1445 mips_count_memory_refs (op0
, 1);
1449 int regno1
= REGNO (op1
) + subreg_word1
;
1451 if (GP_REG_P (regno1
))
1456 case SFmode
: ret
= "sw\t%1,%0"; break;
1457 case SImode
: ret
= "sw\t%1,%0"; break;
1458 case HImode
: ret
= "sh\t%1,%0"; break;
1459 case QImode
: ret
= "sb\t%1,%0"; break;
1463 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1467 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1472 case SFmode
: ret
= "sw\t%z1,%0"; break;
1473 case SImode
: ret
= "sw\t%z1,%0"; break;
1474 case HImode
: ret
= "sh\t%z1,%0"; break;
1475 case QImode
: ret
= "sb\t%z1,%0"; break;
1479 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1484 case SFmode
: ret
= "sw\t%.,%0"; break;
1485 case SImode
: ret
= "sw\t%.,%0"; break;
1486 case HImode
: ret
= "sh\t%.,%0"; break;
1487 case QImode
: ret
= "sb\t%.,%0"; break;
1491 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1493 int i
= strlen (ret
);
1494 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1497 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1498 ret
= volatile_buffer
;
1502 if (ret
== (char *)0)
1504 abort_with_insn (insn
, "Bad move");
1508 if (delay
!= DELAY_NONE
)
1509 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1515 /* Return the appropriate instructions to move 2 words */
1518 mips_move_2words (operands
, insn
)
1523 rtx op0
= operands
[0];
1524 rtx op1
= operands
[1];
1525 enum rtx_code code0
= GET_CODE (operands
[0]);
1526 enum rtx_code code1
= GET_CODE (operands
[1]);
1527 int subreg_word0
= 0;
1528 int subreg_word1
= 0;
1529 enum delay_type delay
= DELAY_NONE
;
1531 while (code0
== SUBREG
)
1533 subreg_word0
+= SUBREG_WORD (op0
);
1534 op0
= SUBREG_REG (op0
);
1535 code0
= GET_CODE (op0
);
1538 if (code1
== SIGN_EXTEND
)
1540 op1
= XEXP (op1
, 0);
1541 code1
= GET_CODE (op1
);
1544 while (code1
== SUBREG
)
1546 subreg_word1
+= SUBREG_WORD (op1
);
1547 op1
= SUBREG_REG (op1
);
1548 code1
= GET_CODE (op1
);
1552 if (GET_CODE (operands
[1]) == SIGN_EXTEND
1554 && code1
!= CONST_INT
1555 /* The following three can happen as the result of a questionable
1557 && code1
!= LABEL_REF
1558 && code1
!= SYMBOL_REF
1564 int regno0
= REGNO (op0
) + subreg_word0
;
1568 int regno1
= REGNO (op1
) + subreg_word1
;
1570 /* Just in case, don't do anything for assigning a register
1571 to itself, unless we are filling a delay slot. */
1572 if (regno0
== regno1
&& set_nomacro
== 0)
1575 else if (FP_REG_P (regno0
))
1577 if (FP_REG_P (regno1
))
1578 ret
= "mov.d\t%0,%1";
1586 abort_with_insn (insn
, "Bad move");
1587 #ifdef TARGET_FP_CALL_32
1588 if (FP_CALL_GP_REG_P (regno1
))
1589 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1592 ret
= "dmtc1\t%1,%0";
1595 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1599 else if (FP_REG_P (regno1
))
1605 abort_with_insn (insn
, "Bad move");
1606 #ifdef TARGET_FP_CALL_32
1607 if (FP_CALL_GP_REG_P (regno0
))
1608 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1611 ret
= "dmfc1\t%0,%1";
1614 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1617 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1622 if (regno0
!= HILO_REGNUM
)
1624 else if (regno1
== 0)
1625 ret
= "mtlo\t%.\n\tmthi\t%.";
1628 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1631 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1636 if (regno1
!= HILO_REGNUM
)
1640 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1643 else if (TARGET_64BIT
)
1644 ret
= "move\t%0,%1";
1646 else if (regno0
!= (regno1
+1))
1647 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1650 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1653 else if (code1
== CONST_DOUBLE
)
1655 /* Move zero from $0 unless !TARGET_64BIT and recipient
1656 is 64-bit fp reg, in which case generate a constant. */
1657 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1658 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1660 if (GET_MODE (op1
) == DFmode
)
1663 #ifdef TARGET_FP_CALL_32
1664 if (FP_CALL_GP_REG_P (regno0
))
1666 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1668 split_double (op1
, operands
+ 2, operands
+ 3);
1669 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1672 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1676 ret
= "li.d\t%0,%1";
1679 else if (TARGET_64BIT
)
1684 split_double (op1
, operands
+ 2, operands
+ 3);
1685 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1691 if (GP_REG_P (regno0
))
1693 #ifdef TARGET_FP_CALL_32
1694 && ! FP_CALL_GP_REG_P (regno0
)
1698 : "move\t%0,%.\n\tmove\t%D0,%.";
1700 else if (FP_REG_P (regno0
))
1703 ret
= (TARGET_64BIT
)
1705 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
1710 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1712 if (GP_REG_P (regno0
))
1713 ret
= (TARGET_64BIT
)
1715 : "move\t%0,%.\n\tmove\t%D0,%.";
1717 else if (FP_REG_P (regno0
))
1720 ret
= (TARGET_64BIT
)
1724 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1726 else if (MD_REG_P (regno0
))
1729 if (regno0
!= HILO_REGNUM
)
1732 ret
= "mtlo\t%.\n\tmthi\t%.";
1736 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
&& GP_REG_P (regno0
))
1740 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1741 ret
= "li\t%0,%1\t\t# %X1";
1742 else if (HOST_BITS_PER_WIDE_INT
< 64)
1743 /* We can't use 'X' for negative numbers, because then we won't
1744 get the right value for the upper 32 bits. */
1745 ret
= ((INTVAL (op1
) < 0) ? "dli\t%0,%1\t\t\t# %X1"
1746 : "dli\t%0,%X1\t\t# %1");
1748 /* We must use 'X', because otherwise LONG_MIN will print as
1749 a number that the assembler won't accept. */
1750 ret
= "dli\t%0,%X1\t\t# %1";
1752 else if (HOST_BITS_PER_WIDE_INT
< 64)
1754 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1755 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1759 /* We use multiple shifts here, to avoid warnings about out
1760 of range shifts on 32 bit hosts. */
1761 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1762 operands
[1] = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1763 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1767 else if (code1
== MEM
)
1772 mips_count_memory_refs (op1
, 2);
1774 if (FP_REG_P (regno0
))
1777 else if (TARGET_64BIT
)
1779 #ifdef TARGET_FP_CALL_32
1780 if (FP_CALL_GP_REG_P (regno0
))
1782 if (offsettable_address_p (FALSE
, SImode
, op1
))
1783 ret
= "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
1785 ret
= "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1792 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1794 operands
[2] = adj_offsettable_operand (op1
, 4);
1795 if (reg_mentioned_p (op0
, op1
))
1796 ret
= "lw\t%D0,%2\n\tlw\t%0,%1";
1798 ret
= "lw\t%0,%1\n\tlw\t%D0,%2";
1801 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1803 int i
= strlen (ret
);
1804 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1807 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1808 ret
= volatile_buffer
;
1812 else if (code1
== LABEL_REF
1813 || code1
== SYMBOL_REF
1817 mips_count_memory_refs (op1
, 2);
1819 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1820 /* We deliberately remove the 'a' from '%1', so that we don't
1821 have to add SIGN_EXTEND support to print_operand_address.
1822 print_operand will just call print_operand_address in this
1823 case, so there is no problem. */
1826 ret
= "dla\t%0,%a1";
1830 else if (code0
== MEM
)
1834 int regno1
= REGNO (op1
) + subreg_word1
;
1836 if (FP_REG_P (regno1
))
1839 else if (TARGET_64BIT
)
1841 #ifdef TARGET_FP_CALL_32
1842 if (FP_CALL_GP_REG_P (regno1
))
1843 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1849 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1851 operands
[2] = adj_offsettable_operand (op0
, 4);
1852 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1856 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1857 || (code1
== CONST_DOUBLE
1858 && op1
== CONST0_RTX (GET_MODE (op1
))))
1860 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1866 operands
[2] = adj_offsettable_operand (op0
, 4);
1867 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1872 mips_count_memory_refs (op0
, 2);
1874 if (ret
!= (char *)0 && MEM_VOLATILE_P (op0
))
1876 int i
= strlen (ret
);
1877 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1880 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1881 ret
= volatile_buffer
;
1885 if (ret
== (char *)0)
1887 abort_with_insn (insn
, "Bad move");
1891 if (delay
!= DELAY_NONE
)
1892 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1898 /* Provide the costs of an addressing mode that contains ADDR.
1899 If ADDR is not a valid address, its cost is irrelevant. */
1902 mips_address_cost (addr
)
1905 switch (GET_CODE (addr
))
1918 rtx offset
= const0_rtx
;
1919 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1920 if (GET_CODE (addr
) == LABEL_REF
)
1923 if (GET_CODE (addr
) != SYMBOL_REF
)
1926 if (! SMALL_INT (offset
))
1932 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1936 register rtx plus0
= XEXP (addr
, 0);
1937 register rtx plus1
= XEXP (addr
, 1);
1939 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1941 plus0
= XEXP (addr
, 1);
1942 plus1
= XEXP (addr
, 0);
1945 if (GET_CODE (plus0
) != REG
)
1948 switch (GET_CODE (plus1
))
1954 return (SMALL_INT (plus1
) ? 1 : 2);
1961 return mips_address_cost (plus1
) + 1;
1969 /* Return true if X is an address which needs a temporary register when
1970 reloaded while generating PIC code. */
1973 pic_address_needs_scratch (x
)
1976 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1977 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1978 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1979 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1980 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1986 /* Make normal rtx_code into something we can index from an array */
1988 static enum internal_test
1989 map_test_to_internal_test (test_code
)
1990 enum rtx_code test_code
;
1992 enum internal_test test
= ITEST_MAX
;
1997 case EQ
: test
= ITEST_EQ
; break;
1998 case NE
: test
= ITEST_NE
; break;
1999 case GT
: test
= ITEST_GT
; break;
2000 case GE
: test
= ITEST_GE
; break;
2001 case LT
: test
= ITEST_LT
; break;
2002 case LE
: test
= ITEST_LE
; break;
2003 case GTU
: test
= ITEST_GTU
; break;
2004 case GEU
: test
= ITEST_GEU
; break;
2005 case LTU
: test
= ITEST_LTU
; break;
2006 case LEU
: test
= ITEST_LEU
; break;
2013 /* Generate the code to compare two integer values. The return value is:
2014 (reg:SI xx) The pseudo register the comparison is in
2015 (rtx)0 No register, generate a simple branch.
2017 ??? This is called with result nonzero by the Scond patterns in
2018 mips.md. These patterns are called with a target in the mode of
2019 the Scond instruction pattern. Since this must be a constant, we
2020 must use SImode. This means that if RESULT is non-zero, it will
2021 always be an SImode register, even if TARGET_64BIT is true. We
2022 cope with this by calling convert_move rather than emit_move_insn.
2023 This will sometimes lead to an unnecessary extension of the result;
2035 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2036 enum rtx_code test_code
; /* relational test (EQ, etc) */
2037 rtx result
; /* result to store comp. or 0 if branch */
2038 rtx cmp0
; /* first operand to compare */
2039 rtx cmp1
; /* second operand to compare */
2040 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2041 /* to reverse its test */
2044 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2045 int const_low
; /* low bound of constant we can accept */
2046 int const_high
; /* high bound of constant we can accept */
2047 int const_add
; /* constant to add (convert LE -> LT) */
2048 int reverse_regs
; /* reverse registers in test */
2049 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2050 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2051 int unsignedp
; /* != 0 for unsigned comparisons. */
2054 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2056 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2057 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2058 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2059 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2060 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2061 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2062 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2063 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2064 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2065 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2068 enum internal_test test
;
2069 enum machine_mode mode
;
2070 struct cmp_info
*p_info
;
2077 test
= map_test_to_internal_test (test_code
);
2078 if (test
== ITEST_MAX
)
2081 p_info
= &info
[ (int)test
];
2082 eqne_p
= (p_info
->test_code
== XOR
);
2084 mode
= GET_MODE (cmp0
);
2085 if (mode
== VOIDmode
)
2086 mode
= GET_MODE (cmp1
);
2088 /* Eliminate simple branches */
2089 branch_p
= (result
== (rtx
)0);
2092 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2094 /* Comparisons against zero are simple branches */
2095 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2098 /* Test for beq/bne. */
2103 /* allocate a pseudo to calculate the value in. */
2104 result
= gen_reg_rtx (mode
);
2107 /* Make sure we can handle any constants given to us. */
2108 if (GET_CODE (cmp0
) == CONST_INT
)
2109 cmp0
= force_reg (mode
, cmp0
);
2111 if (GET_CODE (cmp1
) == CONST_INT
)
2113 HOST_WIDE_INT value
= INTVAL (cmp1
);
2114 if (value
< p_info
->const_low
2115 || value
> p_info
->const_high
2116 /* ??? Why? And why wasn't the similar code below modified too? */
2118 && HOST_BITS_PER_WIDE_INT
< 64
2119 && p_info
->const_add
!= 0
2120 && ((p_info
->unsignedp
2121 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2123 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2124 != (p_info
->const_add
> 0))))
2125 cmp1
= force_reg (mode
, cmp1
);
2128 /* See if we need to invert the result. */
2129 invert
= (GET_CODE (cmp1
) == CONST_INT
)
2130 ? p_info
->invert_const
2131 : p_info
->invert_reg
;
2133 if (p_invert
!= (int *)0)
2139 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2140 Comparison between two registers, may involve switching operands. */
2141 if (GET_CODE (cmp1
) == CONST_INT
)
2143 if (p_info
->const_add
!= 0)
2145 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2146 /* If modification of cmp1 caused overflow,
2147 we would get the wrong answer if we follow the usual path;
2148 thus, x > 0xffffffffU would turn into x > 0U. */
2149 if ((p_info
->unsignedp
2150 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
2151 : new > INTVAL (cmp1
))
2152 != (p_info
->const_add
> 0))
2154 /* This test is always true, but if INVERT is true then
2155 the result of the test needs to be inverted so 0 should
2156 be returned instead. */
2157 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2161 cmp1
= GEN_INT (new);
2164 else if (p_info
->reverse_regs
)
2171 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2175 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
2176 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2179 if (test
== ITEST_NE
)
2181 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
2185 else if (test
== ITEST_EQ
)
2187 reg2
= (invert
) ? gen_reg_rtx (mode
) : result
;
2188 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
2193 convert_move (result
, gen_rtx (XOR
, mode
, reg
, const1_rtx
), 0);
2199 /* Emit the common code for doing conditional branches.
2200 operand[0] is the label to jump to.
2201 The comparison operands are saved away by cmp{si,di,sf,df}. */
2204 gen_conditional_branch (operands
, test_code
)
2206 enum rtx_code test_code
;
2208 enum cmp_type type
= branch_type
;
2209 rtx cmp0
= branch_cmp
[0];
2210 rtx cmp1
= branch_cmp
[1];
2211 enum machine_mode mode
;
2219 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2223 mode
= type
== CMP_SI
? SImode
: DImode
;
2225 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2232 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2234 /* We don't want to build a comparison against a non-zero
2236 cmp1
= force_reg (mode
, cmp1
);
2243 reg
= gen_rtx (REG
, CCmode
, FPSW_REGNUM
);
2245 reg
= gen_reg_rtx (CCmode
);
2247 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2248 0 in the instruction built below. The MIPS FPU handles
2249 inequality testing by testing for equality and looking for a
2251 emit_insn (gen_rtx (SET
, VOIDmode
,
2253 gen_rtx (test_code
== NE
? EQ
: test_code
,
2254 CCmode
, cmp0
, cmp1
)));
2256 test_code
= test_code
== NE
? EQ
: NE
;
2264 /* Generate the branch. */
2266 label1
= gen_rtx (LABEL_REF
, VOIDmode
, operands
[0]);
2275 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
2277 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
2278 gen_rtx (test_code
, mode
, cmp0
, cmp1
),
2283 /* Emit the common code for conditional moves. OPERANDS is the array
2284 of operands passed to the conditional move defined_expand. */
2287 gen_conditional_move (operands
)
2290 rtx op0
= branch_cmp
[0];
2291 rtx op1
= branch_cmp
[1];
2292 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2293 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2294 enum rtx_code move_code
= NE
;
2295 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2296 enum machine_mode cmp_mode
;
2299 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2318 op0
= force_reg (mode
, branch_cmp
[1]);
2319 op1
= branch_cmp
[0];
2323 op0
= force_reg (mode
, branch_cmp
[1]);
2324 op1
= branch_cmp
[0];
2335 op0
= force_reg (mode
, branch_cmp
[1]);
2336 op1
= branch_cmp
[0];
2340 op0
= force_reg (mode
, branch_cmp
[1]);
2341 op1
= branch_cmp
[0];
2357 if (mode
== SImode
|| mode
== DImode
)
2359 else if (mode
== SFmode
|| mode
== DFmode
)
2364 cmp_reg
= gen_reg_rtx (cmp_mode
);
2365 emit_insn (gen_rtx (SET
, cmp_mode
,
2367 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2368 emit_insn (gen_rtx (SET
, op_mode
,
2370 gen_rtx (IF_THEN_ELSE
, op_mode
,
2371 gen_rtx (move_code
, VOIDmode
,
2373 CONST0_RTX (SImode
)),
2378 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2384 temp<last> = src[MAX_MOVE_REGS-1];
2388 dest[MAX_MOVE_REGS-1] = temp<last>;
2389 src += MAX_MOVE_REGS;
2390 dest += MAX_MOVE_REGS;
2391 } while (src != final);
2393 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2394 registers are needed.
2396 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2397 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2398 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2400 #define MAX_MOVE_REGS 4
2401 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2404 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
2405 rtx dest_reg
; /* register holding destination address */
2406 rtx src_reg
; /* register holding source address */
2407 int bytes
; /* # bytes to move */
2408 int align
; /* alignment */
2409 rtx orig_dest
; /* original dest for change_address */
2410 rtx orig_src
; /* original source for making a reg note */
2412 rtx dest_mem
= change_address (orig_dest
, BLKmode
, dest_reg
);
2413 rtx src_mem
= change_address (orig_src
, BLKmode
, src_reg
);
2414 rtx align_rtx
= GEN_INT (align
);
2420 if (bytes
< 2*MAX_MOVE_BYTES
)
2423 leftover
= bytes
% MAX_MOVE_BYTES
;
2426 label
= gen_label_rtx ();
2427 final_src
= gen_reg_rtx (Pmode
);
2428 bytes_rtx
= GEN_INT (bytes
);
2434 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2435 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2439 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2440 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2446 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2448 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2453 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2454 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2457 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2458 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2459 emit_insn (gen_cmpdi (src_reg
, final_src
));
2463 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2464 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2465 emit_insn (gen_cmpsi (src_reg
, final_src
));
2467 emit_jump_insn (gen_bne (label
));
2470 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
,
2475 /* Use a library function to move some bytes. */
2478 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2483 /* We want to pass the size as Pmode, which will normally be SImode
2484 but will be DImode if we are using 64 bit longs and pointers. */
2485 if (GET_MODE (bytes_rtx
) != VOIDmode
2486 && GET_MODE (bytes_rtx
) != Pmode
)
2487 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, TRUE
);
2489 #ifdef TARGET_MEM_FUNCTIONS
2490 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "memcpy"), 0,
2494 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2495 TREE_UNSIGNED (sizetype
)),
2496 TYPE_MODE (sizetype
));
2498 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "bcopy"), 0,
2502 convert_to_mode (TYPE_MODE (integer_type_node
),
2504 TREE_UNSIGNED (integer_type_node
)),
2505 TYPE_MODE (integer_type_node
));
2510 /* Expand string/block move operations.
2512 operands[0] is the pointer to the destination.
2513 operands[1] is the pointer to the source.
2514 operands[2] is the number of bytes to move.
2515 operands[3] is the alignment. */
2518 expand_block_move (operands
)
2521 rtx bytes_rtx
= operands
[2];
2522 rtx align_rtx
= operands
[3];
2523 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2524 int bytes
= (constp
? INTVAL (bytes_rtx
) : 0);
2525 int align
= INTVAL (align_rtx
);
2526 rtx orig_src
= operands
[1];
2527 rtx orig_dest
= operands
[0];
2531 if (constp
&& bytes
<= 0)
2534 if (align
> UNITS_PER_WORD
)
2535 align
= UNITS_PER_WORD
;
2537 /* Move the address into scratch registers. */
2538 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2539 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2542 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2544 else if (constp
&& bytes
<= 2*MAX_MOVE_BYTES
)
2545 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2547 change_address (orig_src
, BLKmode
,
2549 bytes_rtx
, align_rtx
));
2551 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2552 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
2554 else if (constp
&& optimize
)
2556 /* If the alignment is not word aligned, generate a test at
2557 runtime, to see whether things wound up aligned, and we
2558 can use the faster lw/sw instead ulw/usw. */
2560 rtx temp
= gen_reg_rtx (Pmode
);
2561 rtx aligned_label
= gen_label_rtx ();
2562 rtx join_label
= gen_label_rtx ();
2563 int leftover
= bytes
% MAX_MOVE_BYTES
;
2569 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2570 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2571 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2575 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2576 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
-1)));
2577 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2579 emit_jump_insn (gen_beq (aligned_label
));
2581 /* Unaligned loop. */
2582 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
2583 emit_jump_insn (gen_jump (join_label
));
2587 emit_label (aligned_label
);
2588 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
2590 emit_label (join_label
);
2592 /* Bytes at the end of the loop. */
2594 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2596 change_address (orig_src
, BLKmode
,
2603 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2607 /* Emit load/stores for a small constant block_move.
2609 operands[0] is the memory address of the destination.
2610 operands[1] is the memory address of the source.
2611 operands[2] is the number of bytes to move.
2612 operands[3] is the alignment.
2613 operands[4] is a temp register.
2614 operands[5] is a temp register.
2616 operands[3+num_regs] is the last temp register.
2618 The block move type can be one of the following:
2619 BLOCK_MOVE_NORMAL Do all of the block move.
2620 BLOCK_MOVE_NOT_LAST Do all but the last store.
2621 BLOCK_MOVE_LAST Do just the last store. */
2624 output_block_move (insn
, operands
, num_regs
, move_type
)
2628 enum block_move_type move_type
;
2630 rtx dest_reg
= XEXP (operands
[0], 0);
2631 rtx src_reg
= XEXP (operands
[1], 0);
2632 int bytes
= INTVAL (operands
[2]);
2633 int align
= INTVAL (operands
[3]);
2636 int use_lwl_lwr
= FALSE
;
2637 int last_operand
= num_regs
+4;
2643 char *load
; /* load insn without nop */
2644 char *load_nop
; /* load insn with trailing nop */
2645 char *store
; /* store insn */
2646 char *final
; /* if last_store used: NULL or swr */
2647 char *last_store
; /* last store instruction */
2648 int offset
; /* current offset */
2649 enum machine_mode mode
; /* mode to use on (MEM) */
2652 /* Detect a bug in GCC, where it can give us a register
2653 the same as one of the addressing registers and reduce
2654 the number of registers available. */
2656 i
< last_operand
&& safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2659 if (!reg_mentioned_p (operands
[i
], operands
[0])
2660 && !reg_mentioned_p (operands
[i
], operands
[1]))
2662 xoperands
[safe_regs
++] = operands
[i
];
2665 if (safe_regs
< last_operand
)
2667 xoperands
[0] = operands
[0];
2668 xoperands
[1] = operands
[1];
2669 xoperands
[2] = operands
[2];
2670 xoperands
[3] = operands
[3];
2671 return output_block_move (insn
, xoperands
, safe_regs
-4, move_type
);
2674 /* If we are given global or static addresses, and we would be
2675 emitting a few instructions, try to save time by using a
2676 temporary register for the pointer. */
2677 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
2678 an ldl/ldr instruction pair. We play it safe, and always move
2679 constant addresses into registers when generating N32/N64 code, just
2680 in case we might emit an unaligned load instruction. */
2681 if (num_regs
> 2 && (bytes
> 2*align
|| move_type
!= BLOCK_MOVE_NORMAL
2682 || mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
2684 if (CONSTANT_P (src_reg
))
2687 mips_count_memory_refs (operands
[1], 1);
2689 src_reg
= operands
[ 3 + num_regs
-- ];
2690 if (move_type
!= BLOCK_MOVE_LAST
)
2692 xoperands
[1] = operands
[1];
2693 xoperands
[0] = src_reg
;
2694 if (Pmode
== DImode
)
2695 output_asm_insn ("dla\t%0,%1", xoperands
);
2697 output_asm_insn ("la\t%0,%1", xoperands
);
2701 if (CONSTANT_P (dest_reg
))
2704 mips_count_memory_refs (operands
[0], 1);
2706 dest_reg
= operands
[ 3 + num_regs
-- ];
2707 if (move_type
!= BLOCK_MOVE_LAST
)
2709 xoperands
[1] = operands
[0];
2710 xoperands
[0] = dest_reg
;
2711 if (Pmode
== DImode
)
2712 output_asm_insn ("dla\t%0,%1", xoperands
);
2714 output_asm_insn ("la\t%0,%1", xoperands
);
2719 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2720 are not offsettable, however, offsettable_address_p says they are
2721 offsettable. I think this is a bug in offsettable_address_p.
2722 For expediency, we fix this by just loading the address into a register
2723 if we happen to get one. */
2725 if (GET_CODE (src_reg
) == LO_SUM
)
2727 src_reg
= operands
[ 3 + num_regs
-- ];
2728 if (move_type
!= BLOCK_MOVE_LAST
)
2730 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2731 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2732 xoperands
[0] = src_reg
;
2733 if (Pmode
== DImode
)
2734 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2736 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2740 if (GET_CODE (dest_reg
) == LO_SUM
)
2742 dest_reg
= operands
[ 3 + num_regs
-- ];
2743 if (move_type
!= BLOCK_MOVE_LAST
)
2745 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2746 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2747 xoperands
[0] = dest_reg
;
2748 if (Pmode
== DImode
)
2749 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2751 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2755 if (num_regs
> (sizeof (load_store
) / sizeof (load_store
[0])))
2756 num_regs
= (sizeof (load_store
) / sizeof (load_store
[0]));
2758 else if (num_regs
< 1)
2759 abort_with_insn (insn
, "Cannot do block move, not enough scratch registers");
2763 load_store
[num
].offset
= offset
;
2765 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2767 load_store
[num
].load
= "ld\t%0,%1";
2768 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2769 load_store
[num
].store
= "sd\t%0,%1";
2770 load_store
[num
].last_store
= "sd\t%0,%1";
2771 load_store
[num
].final
= (char *)0;
2772 load_store
[num
].mode
= DImode
;
2777 else if (TARGET_64BIT
&& bytes
>= 8)
2779 if (BYTES_BIG_ENDIAN
)
2781 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2782 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2783 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2784 load_store
[num
].last_store
= "sdr\t%0,%2";
2785 load_store
[num
].final
= "sdl\t%0,%1";
2789 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2790 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2791 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2792 load_store
[num
].last_store
= "sdr\t%0,%1";
2793 load_store
[num
].final
= "sdl\t%0,%2";
2795 load_store
[num
].mode
= DImode
;
2801 else if (bytes
>= 4 && align
>= 4)
2803 load_store
[num
].load
= "lw\t%0,%1";
2804 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2805 load_store
[num
].store
= "sw\t%0,%1";
2806 load_store
[num
].last_store
= "sw\t%0,%1";
2807 load_store
[num
].final
= (char *)0;
2808 load_store
[num
].mode
= SImode
;
2813 else if (bytes
>= 4)
2815 if (BYTES_BIG_ENDIAN
)
2817 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2818 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2819 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2820 load_store
[num
].last_store
= "swr\t%0,%2";
2821 load_store
[num
].final
= "swl\t%0,%1";
2825 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2826 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2827 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2828 load_store
[num
].last_store
= "swr\t%0,%1";
2829 load_store
[num
].final
= "swl\t%0,%2";
2831 load_store
[num
].mode
= SImode
;
2837 else if (bytes
>= 2 && align
>= 2)
2839 load_store
[num
].load
= "lh\t%0,%1";
2840 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2841 load_store
[num
].store
= "sh\t%0,%1";
2842 load_store
[num
].last_store
= "sh\t%0,%1";
2843 load_store
[num
].final
= (char *)0;
2844 load_store
[num
].mode
= HImode
;
2851 load_store
[num
].load
= "lb\t%0,%1";
2852 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2853 load_store
[num
].store
= "sb\t%0,%1";
2854 load_store
[num
].last_store
= "sb\t%0,%1";
2855 load_store
[num
].final
= (char *)0;
2856 load_store
[num
].mode
= QImode
;
2861 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2863 dslots_load_total
++;
2864 dslots_load_filled
++;
2866 if (CONSTANT_P (src_reg
))
2867 mips_count_memory_refs (src_reg
, 1);
2869 if (CONSTANT_P (dest_reg
))
2870 mips_count_memory_refs (dest_reg
, 1);
2873 /* Emit load/stores now if we have run out of registers or are
2874 at the end of the move. */
2876 if (++num
== num_regs
|| bytes
== 0)
2878 /* If only load/store, we need a NOP after the load. */
2881 load_store
[0].load
= load_store
[0].load_nop
;
2882 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2883 dslots_load_filled
--;
2886 if (move_type
!= BLOCK_MOVE_LAST
)
2888 for (i
= 0; i
< num
; i
++)
2895 if (GET_MODE (operands
[i
+4]) != load_store
[i
].mode
)
2896 operands
[i
+4] = gen_rtx (REG
, load_store
[i
].mode
, REGNO (operands
[i
+4]));
2898 offset
= load_store
[i
].offset
;
2899 xoperands
[0] = operands
[i
+4];
2900 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2901 plus_constant (src_reg
, offset
));
2906 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2907 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2908 plus_constant (src_reg
,
2913 output_asm_insn (load_store
[i
].load
, xoperands
);
2917 for (i
= 0; i
< num
; i
++)
2919 int last_p
= (i
== num
-1 && bytes
== 0);
2920 int offset
= load_store
[i
].offset
;
2922 xoperands
[0] = operands
[i
+4];
2923 xoperands
[1] = gen_rtx (MEM
, load_store
[i
].mode
,
2924 plus_constant (dest_reg
, offset
));
2930 extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2931 xoperands
[2] = gen_rtx (MEM
, load_store
[i
].mode
,
2932 plus_constant (dest_reg
,
2937 if (move_type
== BLOCK_MOVE_NORMAL
)
2938 output_asm_insn (load_store
[i
].store
, xoperands
);
2940 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2943 output_asm_insn (load_store
[i
].store
, xoperands
);
2945 else if (load_store
[i
].final
!= (char *)0)
2946 output_asm_insn (load_store
[i
].final
, xoperands
);
2950 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2953 num
= 0; /* reset load_store */
2954 use_lwl_lwr
= FALSE
;
2962 /* Argument support functions. */
2964 /* Initialize CUMULATIVE_ARGS for a function. */
2967 init_cumulative_args (cum
, fntype
, libname
)
2968 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2969 tree fntype
; /* tree ptr for function decl */
2970 rtx libname
; /* SYMBOL_REF of library name or 0 */
2972 static CUMULATIVE_ARGS zero_cum
;
2973 tree param
, next_param
;
2975 if (TARGET_DEBUG_E_MODE
)
2977 fprintf (stderr
, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2979 fputc ('\n', stderr
);
2983 tree ret_type
= TREE_TYPE (fntype
);
2984 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2985 tree_code_name
[ (int)TREE_CODE (fntype
) ],
2986 tree_code_name
[ (int)TREE_CODE (ret_type
) ]);
2992 /* Determine if this function has variable arguments. This is
2993 indicated by the last argument being 'void_type_mode' if there
2994 are no variable arguments. The standard MIPS calling sequence
2995 passes all arguments in the general purpose registers in this
2998 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
3002 next_param
= TREE_CHAIN (param
);
3003 if (next_param
== (tree
)0 && TREE_VALUE (param
) != void_type_node
)
3004 cum
->gp_reg_found
= 1;
3008 /* Advance the argument to the next argument position. */
3011 function_arg_advance (cum
, mode
, type
, named
)
3012 CUMULATIVE_ARGS
*cum
; /* current arg information */
3013 enum machine_mode mode
; /* current arg mode */
3014 tree type
; /* type of the argument or 0 if lib support */
3015 int named
; /* whether or not the argument was named */
3017 if (TARGET_DEBUG_E_MODE
)
3019 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
3020 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3030 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3031 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3033 cum
->gp_reg_found
= 1;
3034 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3039 cum
->gp_reg_found
= 1;
3040 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3045 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3046 cum
->fp_arg_words
++;
3052 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3053 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3055 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3059 cum
->gp_reg_found
= 1;
3060 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3066 cum
->gp_reg_found
= 1;
3072 /* Return an RTL expression containing the register for the given mode,
3073 or 0 if the argument is to be passed on the stack. */
3076 function_arg (cum
, mode
, type
, named
)
3077 CUMULATIVE_ARGS
*cum
; /* current arg information */
3078 enum machine_mode mode
; /* current arg mode */
3079 tree type
; /* type of the argument or 0 if lib support */
3080 int named
; /* != 0 for normal args, == 0 for ... args */
3085 int *arg_words
= &cum
->arg_words
;
3086 int struct_p
= ((type
!= (tree
)0)
3087 && (TREE_CODE (type
) == RECORD_TYPE
3088 || TREE_CODE (type
) == UNION_TYPE
));
3090 if (TARGET_DEBUG_E_MODE
)
3092 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3093 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
, GET_MODE_NAME (mode
),
3096 cum
->last_arg_fp
= 0;
3100 if (mips_abi
== ABI_32
)
3102 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3103 regbase
= GP_ARG_FIRST
;
3106 regbase
= FP_ARG_FIRST
;
3107 /* If the first arg was a float in a floating point register,
3108 then set bias to align this float arg properly. */
3109 if (cum
->arg_words
== 1)
3113 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3116 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3117 cum
->last_arg_fp
= 1;
3118 arg_words
= &cum
->fp_arg_words
;
3119 regbase
= FP_ARG_FIRST
;
3122 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3128 if (mips_abi
== ABI_EABI
3129 && ! TARGET_SOFT_FLOAT
3130 && ! TARGET_SINGLE_FLOAT
)
3131 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3133 cum
->arg_words
+= cum
->arg_words
& 1;
3135 if (mips_abi
== ABI_32
)
3136 regbase
= ((cum
->gp_reg_found
3137 || TARGET_SOFT_FLOAT
3138 || TARGET_SINGLE_FLOAT
3139 || cum
->arg_number
>= 2)
3142 else if (mips_abi
== ABI_EABI
3143 && ! TARGET_SOFT_FLOAT
3144 && ! TARGET_SINGLE_FLOAT
)
3146 cum
->last_arg_fp
= 1;
3147 arg_words
= &cum
->fp_arg_words
;
3148 regbase
= FP_ARG_FIRST
;
3151 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3152 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3156 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3157 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3160 /* Drops through. */
3162 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3163 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3164 cum
->arg_words
+= (cum
->arg_words
& 1);
3165 regbase
= GP_ARG_FIRST
;
3172 regbase
= GP_ARG_FIRST
;
3177 cum
->arg_words
+= (cum
->arg_words
& 1);
3178 regbase
= GP_ARG_FIRST
;
3181 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3183 if (TARGET_DEBUG_E_MODE
)
3184 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3193 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3194 || mips_abi
== ABI_EABI
|| ! named
)
3195 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3198 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3199 structure contains a double in its entirety, then that 64 bit
3200 chunk is passed in a floating point register. */
3203 /* First check to see if there is any such field. */
3204 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3205 if (TREE_CODE (field
) == FIELD_DECL
3206 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3207 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3208 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3209 % BITS_PER_WORD
== 0))
3212 /* If the whole struct fits a DFmode register,
3213 we don't need the PARALLEL. */
3214 if (! field
|| mode
== DFmode
)
3215 ret
= gen_rtx (REG
, mode
, regbase
+ *arg_words
+ bias
);
3218 /* Now handle the special case by returning a PARALLEL
3219 indicating where each 64 bit chunk goes. */
3225 /* ??? If this is a packed structure, then the last hunk won't
3228 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3229 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3230 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3232 /* assign_parms checks the mode of ENTRY_PARM, so we must
3233 use the actual mode here. */
3234 ret
= gen_rtx (PARALLEL
, mode
, rtvec_alloc (chunks
));
3237 regno
= regbase
+ *arg_words
+ bias
;
3238 field
= TYPE_FIELDS (type
);
3239 for (i
= 0; i
< chunks
; i
++)
3243 for (; field
; field
= TREE_CHAIN (field
))
3244 if (TREE_CODE (field
) == FIELD_DECL
3245 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3250 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3251 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3252 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3253 reg
= gen_rtx (REG
, DFmode
,
3254 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3256 reg
= gen_rtx (REG
, word_mode
, regno
);
3258 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
3259 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3267 if (TARGET_DEBUG_E_MODE
)
3268 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3269 struct_p
? ", [struct]" : "");
3271 /* The following is a hack in order to pass 1 byte structures
3272 the same way that the MIPS compiler does (namely by passing
3273 the structure in the high byte or half word of the register).
3274 This also makes varargs work. If we have such a structure,
3275 we save the adjustment RTL, and the call define expands will
3276 emit them. For the VOIDmode argument (argument after the
3277 last real argument), pass back a parallel vector holding each
3278 of the adjustments. */
3280 /* ??? function_arg can be called more than once for each argument.
3281 As a result, we compute more adjustments than we need here.
3282 See the CUMULATIVE_ARGS definition in mips.h. */
3284 /* ??? This scheme requires everything smaller than the word size to
3285 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3286 that would mean every int needs to be shifted left, which is very
3287 inefficient. Let's not carry this compatibility to the 64 bit
3288 calling convention for now. */
3290 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3291 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3293 rtx amount
= GEN_INT (BITS_PER_WORD
3294 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3295 rtx reg
= gen_rtx (REG
, word_mode
, regbase
+ *arg_words
+ bias
);
3297 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashldi3 (reg
, reg
, amount
);
3299 cum
->adjust
[ cum
->num_adjusts
++ ] = gen_ashlsi3 (reg
, reg
, amount
);
3303 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3304 ret
= gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3311 function_arg_partial_nregs (cum
, mode
, type
, named
)
3312 CUMULATIVE_ARGS
*cum
; /* current arg information */
3313 enum machine_mode mode
; /* current arg mode */
3314 tree type
; /* type of the argument or 0 if lib support */
3315 int named
; /* != 0 for normal args, == 0 for ... args */
3317 if ((mode
== BLKmode
3318 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3319 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3320 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3321 && mips_abi
!= ABI_EABI
)
3324 if (mode
== BLKmode
)
3325 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3328 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3330 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3331 return 0; /* structure fits in registers */
3333 if (TARGET_DEBUG_E_MODE
)
3334 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3335 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3337 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3340 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3342 && mips_abi
!= ABI_EABI
)
3344 if (TARGET_DEBUG_E_MODE
)
3345 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3353 /* Abort after printing out a specific insn. */
3356 abort_with_insn (insn
, reason
)
3365 /* Write a message to stderr (for use in macros expanded in files that do not
3366 include stdio.h). */
3372 fprintf (stderr
, s
, s1
, s2
);
3382 fprintf (stderr
, "compiling '%s' in '%s'\n",
3383 (current_function_name
!= (char *)0) ? current_function_name
: "<toplevel>",
3384 (current_function_file
!= (char *)0) ? current_function_file
: "<no file>");
3387 #endif /* SIGINFO */
3390 /* Set up the threshold for data to go into the small data area, instead
3391 of the normal data area, and detect any conflicts in the switches. */
3396 register int i
, start
;
3398 register enum machine_mode mode
;
3400 mips_section_threshold
= (g_switch_set
) ? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3402 if (mips_section_threshold
<= 0)
3403 target_flags
&= ~MASK_GPOPT
;
3405 target_flags
|= MASK_GPOPT
;
3407 /* Get the architectural level. */
3408 if (mips_isa_string
== (char *)0)
3410 #ifdef MIPS_ISA_DEFAULT
3411 mips_isa
= MIPS_ISA_DEFAULT
;
3417 else if (isdigit (*mips_isa_string
))
3419 mips_isa
= atoi (mips_isa_string
);
3420 if (mips_isa
< 1 || mips_isa
> 4)
3422 error ("-mips%d not supported", mips_isa
);
3429 error ("bad value (%s) for -mips switch", mips_isa_string
);
3433 #ifdef MIPS_ABI_DEFAULT
3434 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3435 if (mips_abi_string
== (char *) 0)
3436 mips_abi
= MIPS_ABI_DEFAULT
;
3437 else if (! strcmp (mips_abi_string
, "32")
3438 || ! strcmp (mips_abi_string
, "o32"))
3440 else if (! strcmp (mips_abi_string
, "n32"))
3442 else if (! strcmp (mips_abi_string
, "64")
3443 || ! strcmp (mips_abi_string
, "n64"))
3445 else if (! strcmp (mips_abi_string
, "eabi"))
3446 mips_abi
= ABI_EABI
;
3448 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3450 /* A specified ISA defaults the ABI if it was not specified. */
3451 if (mips_abi_string
== 0 && mips_isa_string
&& mips_abi
!= ABI_EABI
)
3458 /* A specified ABI defaults the ISA if it was not specified. */
3459 else if (mips_isa_string
== 0 && mips_abi_string
&& mips_abi
!= ABI_EABI
)
3461 if (mips_abi
== ABI_32
)
3463 else if (mips_abi
== ABI_N32
)
3468 /* If both ABI and ISA were specified, check for conflicts. */
3469 else if (mips_isa_string
&& mips_abi_string
)
3471 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3472 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3473 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3476 /* Override TARGET_DEFAULT if necessary. */
3477 if (mips_abi
== ABI_32
)
3478 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3480 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. Likewise
3481 for the SGI Irix6 N64 ABI. */
3482 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
)
3483 || mips_abi
== ABI_64
)
3484 target_flags
|= MASK_LONG64
;
3486 /* ??? This doesn't work yet, so don't let people try to use it. */
3487 if (mips_abi
== ABI_32
)
3488 error ("The -mabi=32 support does not work yet.");
3490 if (mips_abi_string
)
3491 error ("This target does not support the -mabi switch.");
3494 #ifdef MIPS_CPU_STRING_DEFAULT
3495 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3496 greater than that supported by the default processor, then the user gets
3497 an error. Normally, the compiler will just default to the base level cpu
3498 for the indicated isa. */
3499 if (mips_cpu_string
== (char *)0)
3500 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3503 /* Identify the processor type */
3504 if (mips_cpu_string
== (char *)0
3505 || !strcmp (mips_cpu_string
, "default")
3506 || !strcmp (mips_cpu_string
, "DEFAULT"))
3511 mips_cpu_string
= "3000";
3512 mips_cpu
= PROCESSOR_R3000
;
3515 mips_cpu_string
= "6000";
3516 mips_cpu
= PROCESSOR_R6000
;
3519 mips_cpu_string
= "4000";
3520 mips_cpu
= PROCESSOR_R4000
;
3523 mips_cpu_string
= "8000";
3524 mips_cpu
= PROCESSOR_R8000
;
3531 char *p
= mips_cpu_string
;
3534 /* We need to cope with the various "vr" prefixes for the NEC 4300
3535 and 4100 processors. */
3536 if (*p
== 'v' || *p
== 'V')
3541 if (*p
== 'r' || *p
== 'R')
3544 /* Since there is no difference between a R2000 and R3000 in
3545 terms of the scheduler, we collapse them into just an R3000. */
3547 mips_cpu
= PROCESSOR_DEFAULT
;
3551 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3552 mips_cpu
= PROCESSOR_R3000
;
3556 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3557 mips_cpu
= PROCESSOR_R3000
;
3558 else if (!strcmp (p
, "3900"))
3559 mips_cpu
= PROCESSOR_R3900
;
3563 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3564 mips_cpu
= PROCESSOR_R4000
;
3565 /* The vr4100 is a non-FP ISA III processor with some extra
3567 else if (!strcmp (p
, "4100")) {
3568 mips_cpu
= PROCESSOR_R4100
;
3569 target_flags
|= MASK_SOFT_FLOAT
;
3571 /* The vr4300 is a standard ISA III processor, but with a different
3573 else if (!strcmp (p
, "4300"))
3574 mips_cpu
= PROCESSOR_R4300
;
3575 /* The r4400 is exactly the same as the r4000 from the compiler's
3577 else if (!strcmp (p
, "4400"))
3578 mips_cpu
= PROCESSOR_R4000
;
3579 else if (!strcmp (p
, "4600"))
3580 mips_cpu
= PROCESSOR_R4600
;
3581 else if (!strcmp (p
, "4650"))
3582 mips_cpu
= PROCESSOR_R4650
;
3586 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
3587 mips_cpu
= PROCESSOR_R5000
;
3591 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3592 mips_cpu
= PROCESSOR_R6000
;
3596 if (!strcmp (p
, "8000"))
3597 mips_cpu
= PROCESSOR_R8000
;
3601 if (!strcmp (p
, "orion"))
3602 mips_cpu
= PROCESSOR_R4600
;
3607 && mips_cpu
!= PROCESSOR_R4300
3608 && mips_cpu
!= PROCESSOR_R4100
3609 && mips_cpu
!= PROCESSOR_R5000
)
3610 mips_cpu
= PROCESSOR_DEFAULT
;
3612 if (mips_cpu
== PROCESSOR_DEFAULT
)
3614 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3615 mips_cpu_string
= "default";
3619 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3620 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3621 || ((mips_cpu
== PROCESSOR_R4000
3622 || mips_cpu
== PROCESSOR_R4100
3623 || mips_cpu
== PROCESSOR_R4300
3624 || mips_cpu
== PROCESSOR_R4600
3625 || mips_cpu
== PROCESSOR_R4650
)
3627 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3629 /* make sure sizes of ints/longs/etc. are ok */
3633 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3635 else if (TARGET_LONG64
)
3636 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3638 else if (TARGET_FLOAT64
)
3639 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3641 else if (TARGET_64BIT
)
3642 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3645 if (mips_abi
!= ABI_32
)
3646 flag_pcc_struct_return
= 0;
3648 /* Tell halfpic.c that we have half-pic code if we do. */
3649 if (TARGET_HALF_PIC
)
3652 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3653 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3654 /* ??? -non_shared turns off pic code generation, but this is not
3656 if (TARGET_ABICALLS
)
3658 mips_abicalls
= MIPS_ABICALLS_YES
;
3660 if (mips_section_threshold
> 0)
3661 warning ("-G is incompatible with PIC code which is the default");
3664 mips_abicalls
= MIPS_ABICALLS_NO
;
3666 /* -membedded-pic is a form of PIC code suitable for embedded
3667 systems. All calls are made using PC relative addressing, and
3668 all data is addressed using the $gp register. This requires gas,
3669 which does most of the work, and GNU ld, which automatically
3670 expands PC relative calls which are out of range into a longer
3671 instruction sequence. All gcc really does differently is
3672 generate a different sequence for a switch. */
3673 if (TARGET_EMBEDDED_PIC
)
3676 if (TARGET_ABICALLS
)
3677 warning ("-membedded-pic and -mabicalls are incompatible");
3679 warning ("-G and -membedded-pic are incompatible");
3680 /* Setting mips_section_threshold is not required, because gas
3681 will force everything to be GP addressable anyhow, but
3682 setting it will cause gcc to make better estimates of the
3683 number of instructions required to access a particular data
3685 mips_section_threshold
= 0x7fffffff;
3688 /* This optimization requires a linker that can support a R_MIPS_LO16
3689 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
3690 GNU ld has this support, but not all other MIPS linkers do, so we enable
3691 this optimization only if the user requests it, or if GNU ld is the
3692 standard linker for this configuration. */
3693 /* ??? This does not work when target addresses are DImode.
3694 This is because we are missing DImode high/lo_sum patterns. */
3695 if (TARGET_GAS
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
3697 mips_split_addresses
= 1;
3699 mips_split_addresses
= 0;
3701 /* -mrnames says to use the MIPS software convention for register
3702 names instead of the hardware names (ie, $a0 instead of $4).
3703 We do this by switching the names in mips_reg_names, which the
3704 reg_names points into via the REGISTER_NAMES macro. */
3706 if (TARGET_NAME_REGS
)
3707 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
, sizeof (mips_reg_names
));
3709 /* If this is OSF/1, set up a SIGINFO handler so we can see what function
3710 is currently being compiled. */
3712 if (getenv ("GCC_SIGINFO") != (char *)0)
3714 struct sigaction action
;
3715 action
.sa_handler
= siginfo
;
3717 action
.sa_flags
= SA_RESTART
;
3718 sigaction (SIGINFO
, &action
, (struct sigaction
*)0);
3723 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
3724 /* If -mstats and -quiet, make stderr line buffered. */
3725 if (quiet_flag
&& TARGET_STATS
)
3726 setvbuf (stderr
, (char *)0, _IOLBF
, BUFSIZ
);
3730 /* Initialize the high and low values for legitimate floating point
3731 constants. Rather than trying to get the accuracy down to the
3732 last bit, just use approximate ranges. */
3733 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3734 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3735 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3736 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3738 mips_print_operand_punct
['?'] = TRUE
;
3739 mips_print_operand_punct
['#'] = TRUE
;
3740 mips_print_operand_punct
['&'] = TRUE
;
3741 mips_print_operand_punct
['!'] = TRUE
;
3742 mips_print_operand_punct
['*'] = TRUE
;
3743 mips_print_operand_punct
['@'] = TRUE
;
3744 mips_print_operand_punct
['.'] = TRUE
;
3745 mips_print_operand_punct
['('] = TRUE
;
3746 mips_print_operand_punct
[')'] = TRUE
;
3747 mips_print_operand_punct
['['] = TRUE
;
3748 mips_print_operand_punct
[']'] = TRUE
;
3749 mips_print_operand_punct
['<'] = TRUE
;
3750 mips_print_operand_punct
['>'] = TRUE
;
3751 mips_print_operand_punct
['{'] = TRUE
;
3752 mips_print_operand_punct
['}'] = TRUE
;
3753 mips_print_operand_punct
['^'] = TRUE
;
3755 mips_char_to_class
['d'] = GR_REGS
;
3756 mips_char_to_class
['f'] = ((TARGET_HARD_FLOAT
) ? FP_REGS
: NO_REGS
);
3757 mips_char_to_class
['h'] = HI_REG
;
3758 mips_char_to_class
['l'] = LO_REG
;
3759 mips_char_to_class
['a'] = HILO_REG
;
3760 mips_char_to_class
['x'] = MD_REGS
;
3761 mips_char_to_class
['b'] = ALL_REGS
;
3762 mips_char_to_class
['y'] = GR_REGS
;
3763 mips_char_to_class
['z'] = ST_REGS
;
3765 /* Set up array to map GCC register number to debug register number.
3766 Ignore the special purpose register numbers. */
3768 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3769 mips_dbx_regno
[i
] = -1;
3771 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3772 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3773 mips_dbx_regno
[i
] = i
+ start
;
3775 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3776 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3777 mips_dbx_regno
[i
] = i
+ start
;
3779 /* Set up array giving whether a given register can hold a given mode.
3780 At present, restrict ints from being in FP registers, because reload
3781 is a little enthusiastic about storing extra values in FP registers,
3782 and this is not good for things like OS kernels. Also, due to the
3783 mandatory delay, it is as fast to load from cached memory as to move
3784 from the FP register. */
3786 for (mode
= VOIDmode
;
3787 mode
!= MAX_MACHINE_MODE
;
3788 mode
= (enum machine_mode
)((int)mode
+ 1))
3790 register int size
= GET_MODE_SIZE (mode
);
3791 register enum mode_class
class = GET_MODE_CLASS (mode
);
3793 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3800 temp
= (regno
== FPSW_REGNUM
);
3802 temp
= (ST_REG_P (regno
)
3804 || FP_REG_P (regno
));
3807 else if (GP_REG_P (regno
))
3808 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
3810 else if (FP_REG_P (regno
))
3811 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3812 && (class == MODE_FLOAT
3813 || class == MODE_COMPLEX_FLOAT
3814 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3815 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3817 else if (MD_REG_P (regno
))
3818 temp
= (class == MODE_INT
3819 && (size
<= UNITS_PER_WORD
3820 || (regno
== MD_REG_FIRST
&& size
== 2 * UNITS_PER_WORD
)));
3825 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3832 * The MIPS debug format wants all automatic variables and arguments
3833 * to be in terms of the virtual frame pointer (stack pointer before
3834 * any adjustment in the function), while the MIPS 3.0 linker wants
3835 * the frame pointer to be the stack pointer after the initial
3836 * adjustment. So, we do the adjustment here. The arg pointer (which
3837 * is eliminated) points to the virtual frame pointer, while the frame
3838 * pointer (which may be eliminated) points to the stack pointer after
3839 * the initial adjustments.
3843 mips_debugger_offset (addr
, offset
)
3847 rtx offset2
= const0_rtx
;
3848 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3851 offset
= INTVAL (offset2
);
3853 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3855 int frame_size
= (!current_frame_info
.initialized
)
3856 ? compute_frame_size (get_frame_size ())
3857 : current_frame_info
.total_size
;
3859 offset
= offset
- frame_size
;
3861 /* sdbout_parms does not want this to crash for unrecognized cases. */
3863 else if (reg
!= arg_pointer_rtx
)
3864 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3871 /* A C compound statement to output to stdio stream STREAM the
3872 assembler syntax for an instruction operand X. X is an RTL
3875 CODE is a value that can be used to specify one of several ways
3876 of printing the operand. It is used when identical operands
3877 must be printed differently depending on the context. CODE
3878 comes from the `%' specification that was used to request
3879 printing of the operand. If the specification was just `%DIGIT'
3880 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3881 is the ASCII code for LTR.
3883 If X is a register, this macro should print the register's name.
3884 The names can be found in an array `reg_names' whose type is
3885 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3887 When the machine description has a specification `%PUNCT' (a `%'
3888 followed by a punctuation character), this macro is called with
3889 a null pointer for X and the punctuation character for CODE.
3891 The MIPS specific codes are:
3893 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3894 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3895 'd' output integer constant in decimal,
3896 'z' if the operand is 0, use $0 instead of normal operand.
3897 'D' print second register of double-word register operand.
3898 'L' print low-order register of double-word register operand.
3899 'M' print high-order register of double-word register operand.
3900 'C' print part of opcode for a branch condition.
3901 'N' print part of opcode for a branch condition, inverted.
3902 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3903 'B' print 'z' for EQ, 'n' for NE
3904 'b' print 'n' for EQ, 'z' for NE
3905 'T' print 'f' for EQ, 't' for NE
3906 't' print 't' for EQ, 'f' for NE
3907 'Z' print register and a comma, but print nothing for $fcc0
3908 '(' Turn on .set noreorder
3909 ')' Turn on .set reorder
3910 '[' Turn on .set noat
3912 '<' Turn on .set nomacro
3913 '>' Turn on .set macro
3914 '{' Turn on .set volatile (not GAS)
3915 '}' Turn on .set novolatile (not GAS)
3916 '&' Turn on .set noreorder if filling delay slots
3917 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3918 '!' Turn on .set nomacro if filling delay slots
3919 '#' Print nop if in a .set noreorder section.
3920 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3921 '@' Print the name of the assembler temporary register (at or $1).
3922 '.' Print the name of the register with a hard-wired zero (zero or $0).
3923 '^' Print the name of the pic call-through register (t9 or $25). */
3926 print_operand (file
, op
, letter
)
3927 FILE *file
; /* file to write to */
3928 rtx op
; /* operand to print */
3929 int letter
; /* %<letter> or 0 */
3931 register enum rtx_code code
;
3933 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3938 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3942 if (mips_branch_likely
)
3947 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3951 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3955 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3959 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3960 fputs (".set\tnoreorder\n\t", file
);
3964 if (final_sequence
!= 0)
3966 if (set_noreorder
++ == 0)
3967 fputs (".set\tnoreorder\n\t", file
);
3969 if (set_nomacro
++ == 0)
3970 fputs (".set\tnomacro\n\t", file
);
3975 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3976 fputs ("\n\t.set\tnomacro", file
);
3980 if (set_noreorder
!= 0)
3981 fputs ("\n\tnop", file
);
3983 else if (TARGET_STATS
)
3984 fputs ("\n\t#nop", file
);
3989 if (set_noreorder
++ == 0)
3990 fputs (".set\tnoreorder\n\t", file
);
3994 if (set_noreorder
== 0)
3995 error ("internal error: %%) found without a %%( in assembler pattern");
3997 else if (--set_noreorder
== 0)
3998 fputs ("\n\t.set\treorder", file
);
4003 if (set_noat
++ == 0)
4004 fputs (".set\tnoat\n\t", file
);
4009 error ("internal error: %%] found without a %%[ in assembler pattern");
4011 else if (--set_noat
== 0)
4012 fputs ("\n\t.set\tat", file
);
4017 if (set_nomacro
++ == 0)
4018 fputs (".set\tnomacro\n\t", file
);
4022 if (set_nomacro
== 0)
4023 error ("internal error: %%> found without a %%< in assembler pattern");
4025 else if (--set_nomacro
== 0)
4026 fputs ("\n\t.set\tmacro", file
);
4031 if (set_volatile
++ == 0)
4032 fprintf (file
, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS
) ? "" : "#");
4036 if (set_volatile
== 0)
4037 error ("internal error: %%} found without a %%{ in assembler pattern");
4039 else if (--set_volatile
== 0)
4040 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
4049 error ("PRINT_OPERAND null pointer");
4053 code
= GET_CODE (op
);
4055 if (code
== SIGN_EXTEND
)
4058 code
= GET_CODE (op
);
4064 case EQ
: fputs ("eq", file
); break;
4065 case NE
: fputs ("ne", file
); break;
4066 case GT
: fputs ("gt", file
); break;
4067 case GE
: fputs ("ge", file
); break;
4068 case LT
: fputs ("lt", file
); break;
4069 case LE
: fputs ("le", file
); break;
4070 case GTU
: fputs ("gtu", file
); break;
4071 case GEU
: fputs ("geu", file
); break;
4072 case LTU
: fputs ("ltu", file
); break;
4073 case LEU
: fputs ("leu", file
); break;
4076 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
4079 else if (letter
== 'N')
4082 case EQ
: fputs ("ne", file
); break;
4083 case NE
: fputs ("eq", file
); break;
4084 case GT
: fputs ("le", file
); break;
4085 case GE
: fputs ("lt", file
); break;
4086 case LT
: fputs ("ge", file
); break;
4087 case LE
: fputs ("gt", file
); break;
4088 case GTU
: fputs ("leu", file
); break;
4089 case GEU
: fputs ("ltu", file
); break;
4090 case LTU
: fputs ("geu", file
); break;
4091 case LEU
: fputs ("gtu", file
); break;
4094 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
4097 else if (letter
== 'S')
4101 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
4102 assemble_name (file
, buffer
);
4105 else if (letter
== 'Z')
4107 register int regnum
;
4111 regnum
= REGNO (op
);
4112 if (! ST_REG_P (regnum
))
4114 if (regnum
!= ST_REG_FIRST
)
4115 fprintf (file
, "%s,", reg_names
[regnum
]);
4118 else if (code
== REG
|| code
== SUBREG
)
4120 register int regnum
;
4123 regnum
= REGNO (op
);
4125 regnum
= true_regnum (op
);
4127 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4128 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4132 fprintf (file
, "%s", reg_names
[regnum
]);
4135 else if (code
== MEM
)
4136 output_address (XEXP (op
, 0));
4138 else if (code
== CONST_DOUBLE
4139 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
4144 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
4145 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
4149 else if ((letter
== 'x') && (GET_CODE(op
) == CONST_INT
))
4150 fprintf (file
, "0x%04x", 0xffff & (INTVAL(op
)));
4152 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4153 && HOST_BITS_PER_WIDE_INT
== 32)
4154 fprintf (file
, "0x%08x", INTVAL(op
));
4156 else if ((letter
== 'X') && (GET_CODE(op
) == CONST_INT
)
4157 && HOST_BITS_PER_WIDE_INT
== 64)
4158 fprintf (file
, "0x%016lx", INTVAL(op
));
4160 else if ((letter
== 'd') && (GET_CODE(op
) == CONST_INT
))
4161 fprintf (file
, "%d", (INTVAL(op
)));
4163 else if (letter
== 'z'
4164 && (GET_CODE (op
) == CONST_INT
)
4165 && INTVAL (op
) == 0)
4166 fputs (reg_names
[GP_REG_FIRST
], file
);
4168 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4169 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter
);
4171 else if (letter
== 'B')
4172 fputs (code
== EQ
? "z" : "n", file
);
4173 else if (letter
== 'b')
4174 fputs (code
== EQ
? "n" : "z", file
);
4175 else if (letter
== 'T')
4176 fputs (code
== EQ
? "f" : "t", file
);
4177 else if (letter
== 't')
4178 fputs (code
== EQ
? "t" : "f", file
);
4181 output_addr_const (file
, op
);
4185 /* A C compound statement to output to stdio stream STREAM the
4186 assembler syntax for an instruction operand that is a memory
4187 reference whose address is ADDR. ADDR is an RTL expression.
4189 On some machines, the syntax for a symbolic address depends on
4190 the section that the address refers to. On these machines,
4191 define the macro `ENCODE_SECTION_INFO' to store the information
4192 into the `symbol_ref', and then check for it here. */
4195 print_operand_address (file
, addr
)
4200 error ("PRINT_OPERAND_ADDRESS, null pointer");
4203 switch (GET_CODE (addr
))
4206 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4210 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4211 abort_with_insn (addr
, "Arg pointer not eliminated.");
4213 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4218 register rtx arg0
= XEXP (addr
, 0);
4219 register rtx arg1
= XEXP (addr
, 1);
4221 if (! mips_split_addresses
)
4222 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4224 if (GET_CODE (arg0
) != REG
)
4225 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4227 fprintf (file
, "%%lo(");
4228 print_operand_address (file
, arg1
);
4229 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4235 register rtx reg
= (rtx
)0;
4236 register rtx offset
= (rtx
)0;
4237 register rtx arg0
= XEXP (addr
, 0);
4238 register rtx arg1
= XEXP (addr
, 1);
4240 if (GET_CODE (arg0
) == REG
)
4244 if (GET_CODE (offset
) == REG
)
4245 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4247 else if (GET_CODE (arg1
) == REG
)
4252 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4254 output_addr_const (file
, addr
);
4258 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4260 if (!CONSTANT_P (offset
))
4261 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4263 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4264 abort_with_insn (addr
, "Arg pointer not eliminated.");
4266 output_addr_const (file
, offset
);
4267 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4275 output_addr_const (file
, addr
);
4281 /* If optimizing for the global pointer, keep track of all of
4282 the externs, so that at the end of the file, we can emit
4283 the appropriate .extern declaration for them, before writing
4284 out the text section. We assume that all names passed to
4285 us are in the permanent obstack, so that they will be valid
4286 at the end of the compilation.
4288 If we have -G 0, or the extern size is unknown, or the object is in
4289 a user specified section that is not .sbss/.sdata, don't bother
4290 emitting the .externs. In the case of user specified sections this
4291 behaviour is required as otherwise GAS will think the object lives in
4295 mips_output_external (file
, decl
, name
)
4300 register struct extern_list
*p
;
4305 && ((TREE_CODE (decl
)) != FUNCTION_DECL
)
4306 && ((len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0)
4307 && (((section_name
= DECL_SECTION_NAME (decl
)) == NULL
)
4308 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
4309 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
4311 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4312 p
->next
= extern_head
;
4318 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4319 if (TREE_CODE (decl
) == FUNCTION_DECL
4320 /* ??? Don't include alloca, since gcc will always expand it
4321 inline. If we don't do this, libg++ fails to build. */
4322 && strcmp (name
, "alloca")
4323 /* ??? Don't include __builtin_next_arg, because then gcc will not
4324 bootstrap under Irix 5.1. */
4325 && strcmp (name
, "__builtin_next_arg"))
4327 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4328 p
->next
= extern_head
;
4338 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4340 mips_output_external_libcall (file
, name
)
4344 register struct extern_list
*p
;
4346 p
= (struct extern_list
*)permalloc ((long) sizeof (struct extern_list
));
4347 p
->next
= extern_head
;
4357 /* Compute a string to use as a temporary file name. */
4359 /* On MSDOS, write temp files in current dir
4360 because there's no place else we can expect to use. */
4363 #define P_tmpdir "./"
4371 char *base
= getenv ("TMPDIR");
4374 if (base
== (char *)0)
4377 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4381 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4387 len
= strlen (base
);
4388 /* temp_filename is global, so we must use malloc, not alloca. */
4389 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4390 strcpy (temp_filename
, base
);
4391 if (len
> 0 && temp_filename
[len
-1] != '/')
4392 temp_filename
[len
++] = '/';
4394 strcpy (temp_filename
+ len
, "ctXXXXXX");
4395 mktemp (temp_filename
);
4397 stream
= fopen (temp_filename
, "w+");
4399 pfatal_with_name (temp_filename
);
4402 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4403 it. Otherwise, we delete it now, so that it will be gone even if the
4404 compiler happens to crash. */
4405 unlink (temp_filename
);
4411 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4412 for .file's that start within a function. If we are smuggling stabs, try to
4413 put out a MIPS ECOFF file and a stab. */
4416 mips_output_filename (stream
, name
)
4420 static int first_time
= TRUE
;
4421 char ltext_label_name
[100];
4427 current_function_file
= name
;
4428 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4429 /* This tells mips-tfile that stabs will follow. */
4430 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4431 fprintf (stream
, "\t#@stabs\n");
4434 else if (write_symbols
== DBX_DEBUG
)
4436 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4437 fprintf (stream
, "%s ", ASM_STABS_OP
);
4438 output_quoted_string (stream
, name
);
4439 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4442 else if (name
!= current_function_file
4443 && strcmp (name
, current_function_file
) != 0)
4445 if (inside_function
&& !TARGET_GAS
)
4447 if (!file_in_function_warning
)
4449 file_in_function_warning
= TRUE
;
4450 ignore_line_number
= TRUE
;
4451 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4457 current_function_file
= name
;
4458 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4464 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4465 as well as a .loc, since it is possible that MIPS ECOFF might not be
4466 able to represent the location for inlines that come from a different
4470 mips_output_lineno (stream
, line
)
4474 if (write_symbols
== DBX_DEBUG
)
4477 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4478 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4479 LOCAL_LABEL_PREFIX
, sym_lineno
);
4484 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4485 (ignore_line_number
) ? "#" : "",
4486 num_source_filenames
, line
);
4488 LABEL_AFTER_LOC (stream
);
4493 /* If defined, a C statement to be executed just prior to the
4494 output of assembler code for INSN, to modify the extracted
4495 operands so they will be output differently.
4497 Here the argument OPVEC is the vector containing the operands
4498 extracted from INSN, and NOPERANDS is the number of elements of
4499 the vector which contain meaningful data for this insn. The
4500 contents of this vector are what will be used to convert the
4501 insn template into assembler code, so you can change the
4502 assembler output by changing the contents of the vector.
4504 We use it to check if the current insn needs a nop in front of it
4505 because of load delays, and also to update the delay slot
4508 /* ??? There is no real need for this function, because it never actually
4509 emits a NOP anymore. */
4512 final_prescan_insn (insn
, opvec
, noperands
)
4517 if (dslots_number_nops
> 0)
4519 rtx pattern
= PATTERN (insn
);
4520 int length
= get_attr_length (insn
);
4522 /* Do we need to emit a NOP? */
4524 || (mips_load_reg
!= (rtx
)0 && reg_mentioned_p (mips_load_reg
, pattern
))
4525 || (mips_load_reg2
!= (rtx
)0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4526 || (mips_load_reg3
!= (rtx
)0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4527 || (mips_load_reg4
!= (rtx
)0 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4528 fputs ("\t#nop\n", asm_out_file
);
4531 dslots_load_filled
++;
4533 while (--dslots_number_nops
> 0)
4534 fputs ("\t#nop\n", asm_out_file
);
4536 mips_load_reg
= (rtx
)0;
4537 mips_load_reg2
= (rtx
)0;
4538 mips_load_reg3
= (rtx
)0;
4539 mips_load_reg4
= (rtx
)0;
4544 enum rtx_code code
= GET_CODE (insn
);
4545 if (code
== JUMP_INSN
|| code
== CALL_INSN
)
4546 dslots_jump_total
++;
4551 /* Output at beginning of assembler file.
4552 If we are optimizing to use the global pointer, create a temporary
4553 file to hold all of the text stuff, and write it out to the end.
4554 This is needed because the MIPS assembler is evidently one pass,
4555 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4556 declaration when the code is processed, it generates a two
4557 instruction sequence. */
4560 mips_asm_file_start (stream
)
4563 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4565 /* Versions of the MIPS assembler before 2.20 generate errors
4566 if a branch inside of a .set noreorder section jumps to a
4567 label outside of the .set noreorder section. Revision 2.20
4568 just set nobopt silently rather than fixing the bug. */
4570 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4571 fprintf (stream
, "\t.set\tnobopt\n");
4573 /* Generate the pseudo ops that System V.4 wants. */
4574 #ifndef ABICALLS_ASM_OP
4575 #define ABICALLS_ASM_OP ".abicalls"
4577 if (TARGET_ABICALLS
)
4578 /* ??? but do not want this (or want pic0) if -non-shared? */
4579 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4581 /* Start a section, so that the first .popsection directive is guaranteed
4582 to have a previously defined section to pop back to. */
4583 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
4584 fprintf (stream
, "\t.section\t.text\n");
4586 /* This code exists so that we can put all externs before all symbol
4587 references. This is necessary for the MIPS assembler's global pointer
4588 optimizations to work. */
4589 if (TARGET_FILE_SWITCHING
)
4591 asm_out_data_file
= stream
;
4592 asm_out_text_file
= make_temp_file ();
4595 asm_out_data_file
= asm_out_text_file
= stream
;
4597 if (flag_verbose_asm
)
4598 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4600 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4604 /* If we are optimizing the global pointer, emit the text section now
4605 and any small externs which did not have .comm, etc that are
4606 needed. Also, give a warning if the data area is more than 32K and
4607 -pic because 3 instructions are needed to reference the data
4611 mips_asm_file_end (file
)
4616 struct extern_list
*p
;
4620 HALF_PIC_FINISH (file
);
4626 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4628 name_tree
= get_identifier (p
->name
);
4630 /* Positively ensure only one .extern for any given symbol. */
4631 if (! TREE_ASM_WRITTEN (name_tree
))
4633 TREE_ASM_WRITTEN (name_tree
) = 1;
4634 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4636 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4640 fputs ("\t.extern\t", file
);
4641 assemble_name (file
, p
->name
);
4642 fprintf (file
, ", %d\n", p
->size
);
4648 if (TARGET_FILE_SWITCHING
)
4650 fprintf (file
, "\n\t.text\n");
4651 rewind (asm_out_text_file
);
4652 if (ferror (asm_out_text_file
))
4653 fatal_io_error (temp_filename
);
4655 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4656 if (fwrite (buffer
, 1, len
, file
) != len
)
4657 pfatal_with_name (asm_file_name
);
4660 pfatal_with_name (temp_filename
);
4662 if (fclose (asm_out_text_file
) != 0)
4663 pfatal_with_name (temp_filename
);
4666 unlink (temp_filename
);
4672 /* Emit either a label, .comm, or .lcomm directive, and mark
4673 that the symbol is used, so that we don't emit an .extern
4674 for it in mips_asm_file_end. */
4677 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4684 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4685 assemble_name (stream
, name
);
4686 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4690 tree name_tree
= get_identifier (name
);
4691 TREE_ASM_WRITTEN (name_tree
) = 1;
4696 /* Output a double precision value to the assembler. If both the
4697 host and target are IEEE, emit the values in hex. */
4700 mips_output_double (stream
, value
)
4702 REAL_VALUE_TYPE value
;
4704 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4706 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4708 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4709 value_long
[0], value
, value_long
[1]);
4711 fprintf (stream
, "\t.double\t%.20g\n", value
);
4716 /* Output a single precision value to the assembler. If both the
4717 host and target are IEEE, emit the values in hex. */
4720 mips_output_float (stream
, value
)
4722 REAL_VALUE_TYPE value
;
4724 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4726 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4728 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4730 fprintf (stream
, "\t.float\t%.12g\n", value
);
4735 /* Return the bytes needed to compute the frame pointer from the current
4738 Mips stack frames look like:
4740 Before call After call
4741 +-----------------------+ +-----------------------+
4744 | caller's temps. | | caller's temps. |
4746 +-----------------------+ +-----------------------+
4748 | arguments on stack. | | arguments on stack. |
4750 +-----------------------+ +-----------------------+
4751 | 4 words to save | | 4 words to save |
4752 | arguments passed | | arguments passed |
4753 | in registers, even | | in registers, even |
4754 SP->| if not passed. | VFP->| if not passed. |
4755 +-----------------------+ +-----------------------+
4757 | fp register save |
4759 +-----------------------+
4761 | gp register save |
4763 +-----------------------+
4767 +-----------------------+
4769 | alloca allocations |
4771 +-----------------------+
4773 | GP save for V.4 abi |
4775 +-----------------------+
4777 | arguments on stack |
4779 +-----------------------+
4781 | arguments passed |
4782 | in registers, even |
4783 low SP->| if not passed. |
4784 memory +-----------------------+
4789 compute_frame_size (size
)
4790 int size
; /* # of var. bytes allocated */
4793 long total_size
; /* # bytes that the entire frame takes up */
4794 long var_size
; /* # bytes that variables take up */
4795 long args_size
; /* # bytes that outgoing arguments take up */
4796 long extra_size
; /* # extra bytes */
4797 long gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4798 long gp_reg_size
; /* # bytes needed to store gp regs */
4799 long fp_reg_size
; /* # bytes needed to store fp regs */
4800 long mask
; /* mask of saved gp registers */
4801 long fmask
; /* mask of saved fp registers */
4802 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4803 long fp_bits
; /* bitmask to use for each fp register */
4809 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4810 var_size
= MIPS_STACK_ALIGN (size
);
4811 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4813 /* The MIPS 3.0 linker does not like functions that dynamically
4814 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
4815 looks like we are trying to create a second frame pointer to the
4816 function, so allocate some stack space to make it happy. */
4818 if (args_size
== 0 && current_function_calls_alloca
)
4819 args_size
= 4*UNITS_PER_WORD
;
4821 total_size
= var_size
+ args_size
+ extra_size
;
4823 /* Calculate space needed for gp registers. */
4824 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4826 if (MUST_SAVE_REGISTER (regno
))
4828 gp_reg_size
+= UNITS_PER_WORD
;
4829 mask
|= 1L << (regno
- GP_REG_FIRST
);
4833 /* Calculate space needed for fp registers. */
4834 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4845 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4847 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4849 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4850 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4854 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4855 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4857 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4858 for leaf routines (total_size == extra_size) to save the gp reg.
4859 The gp reg is callee saved in the 64 bit ABI, so all routines must
4860 save the gp reg. This is not a leaf routine if -p, because of the
4862 if (total_size
== extra_size
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
)
4864 total_size
= extra_size
= 0;
4865 else if (TARGET_ABICALLS
)
4867 /* Add the context-pointer to the saved registers. */
4868 gp_reg_size
+= UNITS_PER_WORD
;
4869 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4870 total_size
-= gp_reg_rounded
;
4871 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4872 total_size
+= gp_reg_rounded
;
4875 /* Add in space reserved on the stack by the callee for storing arguments
4876 passed in registers. */
4877 if (mips_abi
!= ABI_32
)
4878 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4880 /* Save other computed information. */
4881 current_frame_info
.total_size
= total_size
;
4882 current_frame_info
.var_size
= var_size
;
4883 current_frame_info
.args_size
= args_size
;
4884 current_frame_info
.extra_size
= extra_size
;
4885 current_frame_info
.gp_reg_size
= gp_reg_size
;
4886 current_frame_info
.fp_reg_size
= fp_reg_size
;
4887 current_frame_info
.mask
= mask
;
4888 current_frame_info
.fmask
= fmask
;
4889 current_frame_info
.initialized
= reload_completed
;
4890 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4891 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4895 unsigned long offset
= (args_size
+ extra_size
+ var_size
4896 + gp_reg_size
- UNITS_PER_WORD
);
4897 current_frame_info
.gp_sp_offset
= offset
;
4898 current_frame_info
.gp_save_offset
= offset
- total_size
;
4902 current_frame_info
.gp_sp_offset
= 0;
4903 current_frame_info
.gp_save_offset
= 0;
4909 unsigned long offset
= (args_size
+ extra_size
+ var_size
4910 + gp_reg_rounded
+ fp_reg_size
4911 - fp_inc
* UNITS_PER_FPREG
);
4912 current_frame_info
.fp_sp_offset
= offset
;
4913 current_frame_info
.fp_save_offset
= offset
- total_size
;
4917 current_frame_info
.fp_sp_offset
= 0;
4918 current_frame_info
.fp_save_offset
= 0;
4921 /* Ok, we're done. */
4926 /* Common code to emit the insns (or to write the instructions to a file)
4927 to save/restore registers.
4929 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4930 is not modified within save_restore_insns. */
4932 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
4935 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4936 int store_p
; /* true if this is prologue */
4937 rtx large_reg
; /* register holding large offset constant or NULL */
4938 long large_offset
; /* large constant offset value */
4939 FILE *file
; /* file to write instructions to instead of making RTL */
4941 long mask
= current_frame_info
.mask
;
4942 long fmask
= current_frame_info
.fmask
;
4951 if (frame_pointer_needed
&& !BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4954 if (mask
== 0 && fmask
== 0)
4957 /* Save registers starting from high to low. The debuggers prefer
4958 at least the return register be stored at func+4, and also it
4959 allows us not to need a nop in the epilog if at least one
4960 register is reloaded in addition to return address. */
4962 /* Save GP registers if needed. */
4965 /* Pick which pointer to use as a base register. For small
4966 frames, just use the stack pointer. Otherwise, use a
4967 temporary register. Save 2 cycles if the save area is near
4968 the end of a large frame, by reusing the constant created in
4969 the prologue/epilogue to adjust the stack frame. */
4971 gp_offset
= current_frame_info
.gp_sp_offset
;
4972 end_offset
= gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
4974 if (gp_offset
< 0 || end_offset
< 0)
4975 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4976 gp_offset
, end_offset
);
4978 else if (gp_offset
< 32768)
4980 base_reg_rtx
= stack_pointer_rtx
;
4984 else if (large_reg
!= (rtx
)0
4985 && (((unsigned long)(large_offset
- gp_offset
)) < 32768)
4986 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
4988 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
4989 base_offset
= large_offset
;
4990 if (file
== (FILE *)0)
4993 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4995 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
4997 RTX_FRAME_RELATED_P (insn
) = 1;
5000 fprintf (file
, "\t%s\t%s,%s,%s\n",
5001 TARGET_LONG64
? "daddu" : "addu",
5002 reg_names
[MIPS_TEMP2_REGNUM
],
5003 reg_names
[REGNO (large_reg
)],
5004 reg_names
[STACK_POINTER_REGNUM
]);
5009 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5010 base_offset
= gp_offset
;
5011 if (file
== (FILE *)0)
5013 rtx gp_offset_rtx
= GEN_INT (gp_offset
);
5015 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5016 bit, so make sure that we don't emit anything that can be
5018 /* ??? There is no DImode ori immediate pattern, so we can only
5019 do this for 32 bit code. */
5020 if (large_int (gp_offset_rtx
)
5021 && GET_MODE (base_reg_rtx
) == SImode
)
5023 insn
= emit_move_insn (base_reg_rtx
,
5024 GEN_INT (gp_offset
& 0xffff0000));
5026 RTX_FRAME_RELATED_P (insn
) = 1;
5027 insn
= emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
5028 GEN_INT (gp_offset
& 0x0000ffff)));
5030 RTX_FRAME_RELATED_P (insn
) = 1;
5034 insn
= emit_move_insn (base_reg_rtx
, gp_offset_rtx
);
5036 RTX_FRAME_RELATED_P (insn
) = 1;
5040 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5042 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5044 RTX_FRAME_RELATED_P (insn
) = 1;
5047 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5048 reg_names
[MIPS_TEMP2_REGNUM
],
5051 TARGET_LONG64
? "daddu" : "addu",
5052 reg_names
[MIPS_TEMP2_REGNUM
],
5053 reg_names
[MIPS_TEMP2_REGNUM
],
5054 reg_names
[STACK_POINTER_REGNUM
]);
5057 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
5059 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
5061 if (file
== (FILE *)0)
5063 rtx reg_rtx
= gen_rtx (REG
, word_mode
, regno
);
5064 rtx mem_rtx
= gen_rtx (MEM
, word_mode
,
5065 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5066 GEN_INT (gp_offset
- base_offset
)));
5070 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5071 RTX_FRAME_RELATED_P (insn
) = 1;
5073 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
5074 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5075 emit_move_insn (reg_rtx
, mem_rtx
);
5079 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
5080 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
5081 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5083 ? (store_p
) ? "sd" : "ld"
5084 : (store_p
) ? "sw" : "lw"),
5086 gp_offset
- base_offset
,
5087 reg_names
[REGNO(base_reg_rtx
)]);
5090 gp_offset
-= UNITS_PER_WORD
;
5096 base_reg_rtx
= (rtx
)0; /* Make sure these are initialized */
5100 /* Save floating point registers if needed. */
5103 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
5104 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
5106 /* Pick which pointer to use as a base register. */
5107 fp_offset
= current_frame_info
.fp_sp_offset
;
5108 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
5110 if (fp_offset
< 0 || end_offset
< 0)
5111 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5112 fp_offset
, end_offset
);
5114 else if (fp_offset
< 32768)
5116 base_reg_rtx
= stack_pointer_rtx
;
5120 else if (base_reg_rtx
!= (rtx
)0
5121 && (((unsigned long)(base_offset
- fp_offset
)) < 32768)
5122 && (((unsigned long)(base_offset
- end_offset
)) < 32768))
5124 ; /* already set up for gp registers above */
5127 else if (large_reg
!= (rtx
)0
5128 && (((unsigned long)(large_offset
- fp_offset
)) < 32768)
5129 && (((unsigned long)(large_offset
- end_offset
)) < 32768))
5131 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5132 base_offset
= large_offset
;
5133 if (file
== (FILE *)0)
5136 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5138 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
, stack_pointer_rtx
));
5140 RTX_FRAME_RELATED_P (insn
) = 1;
5143 fprintf (file
, "\t%s\t%s,%s,%s\n",
5144 TARGET_LONG64
? "daddu" : "addu",
5145 reg_names
[MIPS_TEMP2_REGNUM
],
5146 reg_names
[REGNO (large_reg
)],
5147 reg_names
[STACK_POINTER_REGNUM
]);
5152 base_reg_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP2_REGNUM
);
5153 base_offset
= fp_offset
;
5154 if (file
== (FILE *)0)
5156 rtx fp_offset_rtx
= GEN_INT (fp_offset
);
5158 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5159 bit, so make sure that we don't emit anything that can be
5161 /* ??? There is no DImode ori immediate pattern, so we can only
5162 do this for 32 bit code. */
5163 if (large_int (fp_offset_rtx
)
5164 && GET_MODE (base_reg_rtx
) == SImode
)
5166 insn
= emit_move_insn (base_reg_rtx
,
5167 GEN_INT (fp_offset
& 0xffff0000));
5169 RTX_FRAME_RELATED_P (insn
) = 1;
5170 insn
= emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
5171 GEN_INT (fp_offset
& 0x0000ffff)));
5173 RTX_FRAME_RELATED_P (insn
) = 1;
5177 insn
= emit_move_insn (base_reg_rtx
, fp_offset_rtx
);
5179 RTX_FRAME_RELATED_P (insn
) = 1;
5183 RTX_FRAME_RELATED_P (insn
) = 1;
5185 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5187 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
, stack_pointer_rtx
));
5189 RTX_FRAME_RELATED_P (insn
) = 1;
5192 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5193 reg_names
[MIPS_TEMP2_REGNUM
],
5196 TARGET_LONG64
? "daddu" : "addu",
5197 reg_names
[MIPS_TEMP2_REGNUM
],
5198 reg_names
[MIPS_TEMP2_REGNUM
],
5199 reg_names
[STACK_POINTER_REGNUM
]);
5202 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5204 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5206 if (file
== (FILE *)0)
5208 enum machine_mode sz
=
5209 TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5210 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
5211 rtx mem_rtx
= gen_rtx (MEM
, sz
,
5212 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
5213 GEN_INT (fp_offset
- base_offset
)));
5217 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5218 RTX_FRAME_RELATED_P (insn
) = 1;
5221 emit_move_insn (reg_rtx
, mem_rtx
);
5224 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5225 (TARGET_SINGLE_FLOAT
5226 ? ((store_p
) ? "s.s" : "l.s")
5227 : ((store_p
) ? "s.d" : "l.d")),
5229 fp_offset
- base_offset
,
5230 reg_names
[REGNO(base_reg_rtx
)]);
5233 fp_offset
-= fp_size
;
5240 /* Set up the stack and frame (if desired) for the function. */
5243 function_prologue (file
, size
)
5248 long tsize
= current_frame_info
.total_size
;
5250 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5252 #ifdef SDB_DEBUGGING_INFO
5253 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5254 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5257 inside_function
= 1;
5259 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5260 /* Get the function name the same way that toplev.c does before calling
5261 assemble_start_function. This is needed so that the name used here
5262 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5263 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5265 if (!flag_inhibit_size_directive
)
5267 fputs ("\t.ent\t", file
);
5268 assemble_name (file
, fnname
);
5272 assemble_name (file
, fnname
);
5273 fputs (":\n", file
);
5276 if (!flag_inhibit_size_directive
)
5278 fprintf (file
, "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5279 reg_names
[ (frame_pointer_needed
) ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
],
5281 reg_names
[31 + GP_REG_FIRST
],
5282 current_frame_info
.var_size
,
5283 current_frame_info
.num_gp
,
5284 current_frame_info
.num_fp
,
5285 current_function_outgoing_args_size
,
5286 current_frame_info
.extra_size
);
5288 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5289 current_frame_info
.mask
,
5290 current_frame_info
.gp_save_offset
,
5291 current_frame_info
.fmask
,
5292 current_frame_info
.fp_save_offset
);
5295 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5297 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5299 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5300 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5303 fprintf (file
, "\t%s\t%s,%s,%d\n",
5304 (TARGET_LONG64
? "dsubu" : "subu"),
5305 sp_str
, sp_str
, tsize
);
5306 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5309 if (dwarf2out_do_frame ())
5310 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
5315 /* Expand the prologue into a bunch of separate insns. */
5318 mips_expand_prologue ()
5322 rtx tmp_rtx
= (rtx
)0;
5323 char *arg_name
= (char *)0;
5324 tree fndecl
= current_function_decl
;
5325 tree fntype
= TREE_TYPE (fndecl
);
5326 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5331 CUMULATIVE_ARGS args_so_far
;
5333 /* If struct value address is treated as the first argument, make it so. */
5334 if (aggregate_value_p (DECL_RESULT (fndecl
))
5335 && ! current_function_returns_pcc_struct
5336 && struct_value_incoming_rtx
== 0)
5338 tree type
= build_pointer_type (fntype
);
5339 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5340 DECL_ARG_TYPE (function_result_decl
) = type
;
5341 TREE_CHAIN (function_result_decl
) = fnargs
;
5342 fnargs
= function_result_decl
;
5345 /* Determine the last argument, and get its name. */
5347 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, (rtx
)0, 0);
5348 regno
= GP_ARG_FIRST
;
5350 for (cur_arg
= fnargs
; cur_arg
!= (tree
)0; cur_arg
= next_arg
)
5352 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5353 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5356 if (TREE_ADDRESSABLE (passed_type
))
5358 passed_type
= build_pointer_type (passed_type
);
5359 passed_mode
= Pmode
;
5362 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5368 /* passed in a register, so will get homed automatically */
5369 if (GET_MODE (entry_parm
) == BLKmode
)
5370 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5372 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5374 regno
= REGNO (entry_parm
) + words
- 1;
5378 regno
= GP_ARG_LAST
+1;
5382 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5384 next_arg
= TREE_CHAIN (cur_arg
);
5385 if (next_arg
== (tree
)0)
5387 if (DECL_NAME (cur_arg
))
5388 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5394 /* In order to pass small structures by value in registers
5395 compatibly with the MIPS compiler, we need to shift the value
5396 into the high part of the register. Function_arg has encoded a
5397 PARALLEL rtx, holding a vector of adjustments to be made as the
5398 next_arg_reg variable, so we split up the insns, and emit them
5401 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5402 if (next_arg_reg
!= (rtx
)0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5404 rtvec adjust
= XVEC (next_arg_reg
, 0);
5405 int num
= GET_NUM_ELEM (adjust
);
5407 for (i
= 0; i
< num
; i
++)
5409 rtx pattern
= RTVEC_ELT (adjust
, i
);
5410 if (GET_CODE (pattern
) != SET
5411 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5412 abort_with_insn (pattern
, "Insn is not a shift");
5414 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5415 emit_insn (pattern
);
5419 tsize
= compute_frame_size (get_frame_size ());
5421 /* If this function is a varargs function, store any registers that
5422 would normally hold arguments ($4 - $7) on the stack. */
5423 if (mips_abi
== ABI_32
5424 && ((TYPE_ARG_TYPES (fntype
) != 0
5425 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
))) != void_type_node
))
5426 || (arg_name
!= (char *)0
5427 && ((arg_name
[0] == '_' && strcmp (arg_name
, "__builtin_va_alist") == 0)
5428 || (arg_name
[0] == 'v' && strcmp (arg_name
, "va_alist") == 0)))))
5430 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5431 rtx ptr
= stack_pointer_rtx
;
5433 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5434 if (TARGET_ABICALLS
)
5437 for (; regno
<= GP_ARG_LAST
; regno
++)
5440 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
5441 emit_move_insn (gen_rtx (MEM
, word_mode
, ptr
),
5442 gen_rtx (REG
, word_mode
, regno
));
5443 offset
+= UNITS_PER_WORD
;
5449 rtx tsize_rtx
= GEN_INT (tsize
);
5451 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5452 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5458 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5460 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5461 bit, so make sure that we don't emit anything that can be
5463 /* ??? There is no DImode ori immediate pattern, so we can only
5464 do this for 32 bit code. */
5465 if (large_int (tsize_rtx
) && GET_MODE (tmp_rtx
) == SImode
)
5467 insn
= emit_move_insn (tmp_rtx
,
5468 GEN_INT (tsize
& 0xffff0000));
5469 RTX_FRAME_RELATED_P (insn
) = 1;
5470 insn
= emit_insn (gen_iorsi3 (tmp_rtx
, tmp_rtx
,
5471 GEN_INT (tsize
& 0x0000ffff)));
5472 RTX_FRAME_RELATED_P (insn
) = 1;
5476 insn
= emit_move_insn (tmp_rtx
, tsize_rtx
);
5477 RTX_FRAME_RELATED_P (insn
) = 1;
5480 tsize_rtx
= tmp_rtx
;
5484 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5487 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5490 RTX_FRAME_RELATED_P (insn
) = 1;
5493 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5495 if (frame_pointer_needed
)
5500 insn
= emit_insn (gen_movdi (frame_pointer_rtx
, stack_pointer_rtx
));
5502 insn
= emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
5504 RTX_FRAME_RELATED_P (insn
) = 1;
5507 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5508 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0)));
5511 /* If we are profiling, make sure no instructions are scheduled before
5512 the call to mcount. */
5514 if (profile_flag
|| profile_block_flag
)
5515 emit_insn (gen_blockage ());
5519 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
5521 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5522 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5525 function_epilogue (file
, size
)
5531 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5532 /* Get the function name the same way that toplev.c does before calling
5533 assemble_start_function. This is needed so that the name used here
5534 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5535 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5537 if (!flag_inhibit_size_directive
)
5539 fputs ("\t.end\t", file
);
5540 assemble_name (file
, fnname
);
5547 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5548 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5549 int num_regs
= num_gp_regs
+ num_fp_regs
;
5550 char *name
= fnname
;
5555 dslots_load_total
+= num_regs
;
5558 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5560 (frame_pointer_needed
) ? 'y' : 'n',
5561 ((current_frame_info
.mask
& RA_MASK
) != 0) ? 'n' : 'y',
5562 (current_function_calls_alloca
) ? 'y' : 'n',
5563 (current_function_calls_setjmp
) ? 'y' : 'n',
5564 (long)current_frame_info
.total_size
,
5565 (long)current_function_outgoing_args_size
,
5566 num_gp_regs
, num_fp_regs
,
5567 dslots_load_total
, dslots_load_filled
,
5568 dslots_jump_total
, dslots_jump_filled
,
5569 num_refs
[0], num_refs
[1], num_refs
[2]);
5571 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5573 fprintf (stderr
, " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5574 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5577 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5579 fprintf (stderr
, " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5580 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5583 fputc ('\n', stderr
);
5586 /* Reset state info for each function. */
5587 inside_function
= FALSE
;
5588 ignore_line_number
= FALSE
;
5589 dslots_load_total
= 0;
5590 dslots_jump_total
= 0;
5591 dslots_load_filled
= 0;
5592 dslots_jump_filled
= 0;
5596 mips_load_reg
= (rtx
)0;
5597 mips_load_reg2
= (rtx
)0;
5598 current_frame_info
= zero_frame_info
;
5600 /* Restore the output file if optimizing the GP (optimizing the GP causes
5601 the text to be diverted to a tempfile, so that data decls come before
5602 references to the data). */
5605 asm_out_file
= asm_out_data_file
;
5609 /* Expand the epilogue into a bunch of separate insns. */
5612 mips_expand_epilogue ()
5614 long tsize
= current_frame_info
.total_size
;
5615 rtx tsize_rtx
= GEN_INT (tsize
);
5616 rtx tmp_rtx
= (rtx
)0;
5618 if (mips_can_use_return_insn ())
5620 emit_insn (gen_return ());
5626 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
5627 emit_move_insn (tmp_rtx
, tsize_rtx
);
5628 tsize_rtx
= tmp_rtx
;
5633 if (frame_pointer_needed
)
5635 emit_insn (gen_blockage ());
5637 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5639 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5641 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
5642 are going to restore it, then we must emit a blockage insn to
5643 prevent the scheduler from moving the restore out of the epilogue. */
5644 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
5645 && (current_frame_info
.mask
5646 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
5647 emit_insn (gen_blockage ());
5649 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5651 emit_insn (gen_blockage ());
5653 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5656 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5660 emit_jump_insn (gen_return_internal ());
5664 /* Return true if this function is known to have a null epilogue.
5665 This allows the optimizer to omit jumps to jumps if no stack
5669 mips_can_use_return_insn ()
5671 if (!reload_completed
)
5674 if (regs_ever_live
[31] || profile_flag
)
5677 if (current_frame_info
.initialized
)
5678 return current_frame_info
.total_size
== 0;
5680 return (compute_frame_size (get_frame_size ())) == 0;
5683 /* Choose the section to use for the constant rtx expression X that has
5686 mips_select_rtx_section (mode
, x
)
5687 enum machine_mode mode
;
5690 if (TARGET_EMBEDDED_DATA
)
5692 /* For embedded applications, always put constants in read-only data,
5693 in order to reduce RAM usage. */
5694 READONLY_DATA_SECTION ();
5698 /* For hosted applications, always put constants in small data if
5699 possible, as this gives the best performance. */
5701 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5702 && mips_section_threshold
> 0)
5703 SMALL_DATA_SECTION ();
5705 READONLY_DATA_SECTION ();
5709 /* Choose the section to use for DECL. RELOC is true if its value contains
5710 any relocatable expression. */
5712 mips_select_section (decl
, reloc
)
5716 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5718 if (TARGET_EMBEDDED_PIC
5719 && TREE_CODE (decl
) == STRING_CST
5720 && !flag_writable_strings
)
5722 /* For embedded position independent code, put constant strings
5723 in the text section, because the data section is limited to
5728 else if (TARGET_EMBEDDED_DATA
)
5730 /* For embedded applications, always put an object in read-only data
5731 if possible, in order to reduce RAM usage. */
5733 if (((TREE_CODE (decl
) == VAR_DECL
5734 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5735 && DECL_INITIAL (decl
)
5736 && (DECL_INITIAL (decl
) == error_mark_node
5737 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5738 /* Deal with calls from output_constant_def_contents. */
5739 || (TREE_CODE (decl
) != VAR_DECL
5740 && (TREE_CODE (decl
) != STRING_CST
5741 || !flag_writable_strings
)))
5742 && ! (flag_pic
&& reloc
))
5743 READONLY_DATA_SECTION ();
5744 else if (size
> 0 && size
<= mips_section_threshold
)
5745 SMALL_DATA_SECTION ();
5751 /* For hosted applications, always put an object in small data if
5752 possible, as this gives the best performance. */
5754 if (size
> 0 && size
<= mips_section_threshold
)
5755 SMALL_DATA_SECTION ();
5756 else if (((TREE_CODE (decl
) == VAR_DECL
5757 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5758 && DECL_INITIAL (decl
)
5759 && (DECL_INITIAL (decl
) == error_mark_node
5760 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5761 /* Deal with calls from output_constant_def_contents. */
5762 || (TREE_CODE (decl
) != VAR_DECL
5763 && (TREE_CODE (decl
) != STRING_CST
5764 || !flag_writable_strings
)))
5765 && ! (flag_pic
&& reloc
))
5766 READONLY_DATA_SECTION ();
5772 #ifdef MIPS_ABI_DEFAULT
5773 /* Support functions for the 64 bit ABI. */
5775 /* Return register to use for a function return value with VALTYPE for function
5779 mips_function_value (valtype
, func
)
5783 int reg
= GP_RETURN
;
5784 enum machine_mode mode
= TYPE_MODE (valtype
);
5785 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5787 /* ??? How should we return complex float? */
5788 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5790 if (TARGET_SINGLE_FLOAT
5791 && (mclass
== MODE_FLOAT
5792 ? GET_MODE_SIZE (mode
) > 4
5793 : GET_MODE_SIZE (mode
) / 2 > 4))
5798 else if (TREE_CODE (valtype
) == RECORD_TYPE
5799 && mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
5801 /* A struct with only one or two floating point fields is returned in
5802 the floating point registers. */
5803 tree field
, fields
[2];
5806 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5807 field
= TREE_CHAIN (field
))
5809 if (TREE_CODE (field
) != FIELD_DECL
)
5811 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5814 fields
[i
++] = field
;
5817 /* Must check i, so that we reject structures with no elements. */
5822 /* The structure has DImode, but we don't allow DImode values
5823 in FP registers, so we use a PARALLEL even though it isn't
5824 strictly necessary. */
5825 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5827 return gen_rtx (PARALLEL
, mode
,
5829 gen_rtx (EXPR_LIST
, VOIDmode
,
5830 gen_rtx (REG
, field_mode
, FP_RETURN
),
5835 enum machine_mode first_mode
5836 = TYPE_MODE (TREE_TYPE (fields
[0]));
5837 enum machine_mode second_mode
5838 = TYPE_MODE (TREE_TYPE (fields
[1]));
5840 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5842 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5844 return gen_rtx (PARALLEL
, mode
,
5846 gen_rtx (EXPR_LIST
, VOIDmode
,
5847 gen_rtx (REG
, first_mode
, FP_RETURN
),
5848 GEN_INT (first_offset
/ BITS_PER_UNIT
)),
5849 gen_rtx (EXPR_LIST
, VOIDmode
,
5850 gen_rtx (REG
, second_mode
, FP_RETURN
+ 2),
5851 GEN_INT (second_offset
/ BITS_PER_UNIT
))));
5856 return gen_rtx (REG
, mode
, reg
);
5859 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
5860 nonzero when an argument must be passed by reference. */
5863 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5864 CUMULATIVE_ARGS
*cum
;
5865 enum machine_mode mode
;
5871 if (mips_abi
!= ABI_EABI
)
5874 /* ??? How should SCmode be handled? */
5875 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
5878 size
= int_size_in_bytes (type
);
5879 return size
== -1 || size
> UNITS_PER_WORD
;
5884 /* This function returns the register class required for a secondary
5885 register when copying between one of the registers in CLASS, and X,
5886 using MODE. If IN_P is nonzero, the copy is going from X to the
5887 register, otherwise the register is the source. A return value of
5888 NO_REGS means that no secondary register is required. */
5891 mips_secondary_reload_class (class, mode
, x
, in_p
)
5892 enum reg_class
class;
5893 enum machine_mode mode
;
5899 if (GET_CODE (x
) == SIGN_EXTEND
)
5905 /* We may be called with reg_renumber NULL from regclass.
5906 ??? This is probably a bug. */
5908 regno
= true_regnum (x
);
5911 while (GET_CODE (x
) == SUBREG
)
5913 off
+= SUBREG_WORD (x
);
5916 if (GET_CODE (x
) == REG
)
5917 regno
= REGNO (x
) + off
;
5920 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5921 regno
= true_regnum (x
);
5923 /* We always require a general register when copying anything to
5924 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5925 to a general register, or when copying from register 0. */
5926 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
5930 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5934 if (regno
== HILO_REGNUM
)
5938 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5943 /* Copying from HI or LO to anywhere other than a general register
5944 requires a general register. */
5945 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
5947 if (GP_REG_P (regno
))
5951 if (MD_REG_P (regno
))
5953 if (class == GR_REGS
)
5958 /* We can only copy a value to a condition code register from a
5959 floating point register, and even then we require a scratch
5960 floating point register. We can only copy a value out of a
5961 condition code register into a general register. */
5962 if (class == ST_REGS
)
5966 if (GP_REG_P (regno
))
5970 if (ST_REG_P (regno
))
5974 if (class == GR_REGS
)