1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
34 #include "hard-reg-set.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "insn-flags.h"
39 #include "insn-attr.h"
40 #include "insn-codes.h"
54 #if defined(USG) || !defined(HAVE_STAB_H)
55 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
57 #include <stab.h> /* On BSD, use the system's stab.h. */
61 #define STAB_CODE_TYPE enum __stab_debug_code
63 #define STAB_CODE_TYPE int
66 extern char *mktemp
PARAMS ((char *));
67 extern tree lookup_name
PARAMS ((tree
));
69 /* Enumeration for all of the relational tests, so that we can build
70 arrays indexed by the test type, and not worry about the order
89 static enum internal_test map_test_to_internal_test
PARAMS ((enum rtx_code
));
90 static int mips16_simple_memory_operand
PARAMS ((rtx
, rtx
,
92 static int m16_check_op
PARAMS ((rtx
, int, int, int));
93 static void block_move_loop
PARAMS ((rtx
, rtx
, int, int,
95 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
96 static FILE *mips_make_temp_file
PARAMS ((void));
97 static void save_restore_insns
PARAMS ((int, rtx
,
99 static void mips16_output_gp_offset
PARAMS ((FILE *, rtx
));
100 static void mips16_fp_args
PARAMS ((FILE *, int, int));
101 static void build_mips16_function_stub
PARAMS ((FILE *));
102 static void mips16_optimize_gp
PARAMS ((rtx
));
103 static rtx add_constant
PARAMS ((struct constant
**,
106 static void dump_constants
PARAMS ((struct constant
*,
108 static rtx mips_find_symbol
PARAMS ((rtx
));
109 static void abort_with_insn
PARAMS ((rtx
, const char *))
111 static int symbolic_expression_p
PARAMS ((rtx
));
112 static void mips_add_gc_roots
PARAMS ((void));
114 /* Global variables for machine-dependent things. */
116 /* Threshold for data being put into the small data/bss area, instead
117 of the normal data area (references to the small data/bss area take
118 1 instruction, and use the global pointer, references to the normal
119 data area takes 2 instructions). */
120 int mips_section_threshold
= -1;
122 /* Count the number of .file directives, so that .loc is up to date. */
123 int num_source_filenames
= 0;
125 /* Count the number of sdb related labels are generated (to find block
126 start and end boundaries). */
127 int sdb_label_count
= 0;
129 /* Next label # for each statement for Silicon Graphics IRIS systems. */
132 /* Non-zero if inside of a function, because the stupid MIPS asm can't
133 handle .files inside of functions. */
134 int inside_function
= 0;
136 /* Files to separate the text and the data output, so that all of the data
137 can be emitted before the text, which will mean that the assembler will
138 generate smaller code, based on the global pointer. */
139 FILE *asm_out_data_file
;
140 FILE *asm_out_text_file
;
142 /* Linked list of all externals that are to be emitted when optimizing
143 for the global pointer if they haven't been declared by the end of
144 the program with an appropriate .comm or initialization. */
148 struct extern_list
*next
; /* next external */
149 const char *name
; /* name of the external */
150 int size
; /* size in bytes */
153 /* Name of the file containing the current function. */
154 const char *current_function_file
= "";
156 /* Warning given that Mips ECOFF can't support changing files
157 within a function. */
158 int file_in_function_warning
= FALSE
;
160 /* Whether to suppress issuing .loc's because the user attempted
161 to change the filename within a function. */
162 int ignore_line_number
= FALSE
;
164 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
170 /* The next branch instruction is a branch likely, not branch normal. */
171 int mips_branch_likely
;
173 /* Count of delay slots and how many are filled. */
174 int dslots_load_total
;
175 int dslots_load_filled
;
176 int dslots_jump_total
;
177 int dslots_jump_filled
;
179 /* # of nops needed by previous insn */
180 int dslots_number_nops
;
182 /* Number of 1/2/3 word references to data items (ie, not jal's). */
185 /* registers to check for load delay */
186 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
188 /* Cached operands, and operator to compare for use in set/branch on
192 /* what type of branch to use */
193 enum cmp_type branch_type
;
195 /* Number of previously seen half-pic pointers and references. */
196 static int prev_half_pic_ptrs
= 0;
197 static int prev_half_pic_refs
= 0;
199 /* which cpu are we scheduling for */
200 enum processor_type mips_cpu
;
202 /* which instruction set architecture to use. */
205 #ifdef MIPS_ABI_DEFAULT
206 /* Which ABI to use. This is defined to a constant in mips.h if the target
207 doesn't support multiple ABIs. */
211 /* Strings to hold which cpu and instruction set architecture to use. */
212 const char *mips_cpu_string
; /* for -mcpu=<xxx> */
213 const char *mips_isa_string
; /* for -mips{1,2,3,4} */
214 const char *mips_abi_string
; /* for -mabi={32,n32,64,eabi} */
216 /* Whether we are generating mips16 code. This is a synonym for
217 TARGET_MIPS16, and exists for use as an attribute. */
220 /* This variable is set by -mno-mips16. We only care whether
221 -mno-mips16 appears or not, and using a string in this fashion is
222 just a way to avoid using up another bit in target_flags. */
223 const char *mips_no_mips16_string
;
225 /* This is only used to determine if an type size setting option was
226 explicitly specified (-mlong64, -mint64, -mlong32). The specs
227 set this option if such an option is used. */
228 const char *mips_explicit_type_size_string
;
230 /* Whether we are generating mips16 hard float code. In mips16 mode
231 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
232 -msoft-float was not specified by the user, which means that we
233 should arrange to call mips32 hard floating point code. */
234 int mips16_hard_float
;
236 /* This variable is set by -mentry. We only care whether -mentry
237 appears or not, and using a string in this fashion is just a way to
238 avoid using up another bit in target_flags. */
239 const char *mips_entry_string
;
241 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
244 /* If TRUE, we split addresses into their high and low parts in the RTL. */
245 int mips_split_addresses
;
247 /* Generating calls to position independent functions? */
248 enum mips_abicalls_type mips_abicalls
;
250 /* High and low marks for floating point values which we will accept
251 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
252 initialized in override_options. */
253 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
255 /* Mode used for saving/restoring general purpose registers. */
256 static enum machine_mode gpr_mode
;
258 /* Array giving truth value on whether or not a given hard register
259 can support a given mode. */
260 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
262 /* Current frame information calculated by compute_frame_size. */
263 struct mips_frame_info current_frame_info
;
265 /* Zero structure to initialize current_frame_info. */
266 struct mips_frame_info zero_frame_info
;
268 /* Temporary filename used to buffer .text until end of program
270 static char *temp_filename
;
272 /* Pseudo-reg holding the address of the current function when
273 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
274 by mips_finalize_pic if it was created. */
275 rtx embedded_pic_fnaddr_rtx
;
277 /* The length of all strings seen when compiling for the mips16. This
278 is used to tell how many strings are in the constant pool, so that
279 we can see if we may have an overflow. This is reset each time the
280 constant pool is output. */
281 int mips_string_length
;
283 /* Pseudo-reg holding the value of $28 in a mips16 function which
284 refers to GP relative global variables. */
285 rtx mips16_gp_pseudo_rtx
;
287 /* In mips16 mode, we build a list of all the string constants we see
288 in a particular function. */
290 struct string_constant
292 struct string_constant
*next
;
296 static struct string_constant
*string_constants
;
298 /* List of all MIPS punctuation characters used by print_operand. */
299 char mips_print_operand_punct
[256];
301 /* Map GCC register number to debugger register number. */
302 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
304 /* Buffer to use to enclose a load/store operation with %{ %} to
305 turn on .set volatile. */
306 static char volatile_buffer
[60];
308 /* Hardware names for the registers. If -mrnames is used, this
309 will be overwritten with mips_sw_reg_names. */
311 char mips_reg_names
[][8] =
313 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
314 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
315 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
316 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
317 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
318 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
319 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
320 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
321 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
322 "$fcc5","$fcc6","$fcc7","$rap"
325 /* Mips software names for the registers, used to overwrite the
326 mips_reg_names array. */
328 char mips_sw_reg_names
[][8] =
330 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
331 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
332 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
333 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
334 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
335 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
336 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
337 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
338 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
339 "$fcc5","$fcc6","$fcc7","$rap"
342 /* Map hard register number to register class */
343 enum reg_class mips_regno_to_class
[] =
345 GR_REGS
, GR_REGS
, M16_NA_REGS
, M16_NA_REGS
,
346 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
347 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
348 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
349 M16_NA_REGS
, M16_NA_REGS
, GR_REGS
, GR_REGS
,
350 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
351 T_REG
, GR_REGS
, GR_REGS
, GR_REGS
,
352 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
353 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
354 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
355 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
356 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
357 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
358 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
359 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
360 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
361 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
362 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
363 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
366 /* Map register constraint character to register class. */
367 enum reg_class mips_char_to_class
[256] =
369 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
370 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
371 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
372 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
373 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
374 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
375 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
376 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
377 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
378 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
379 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
380 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
381 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
382 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
383 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
384 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
385 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
386 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
387 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
388 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
389 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
390 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
391 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
392 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
393 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
394 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
395 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
396 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
397 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
398 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
399 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
400 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
401 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
402 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
403 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
404 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
405 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
406 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
407 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
408 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
409 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
410 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
411 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
412 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
413 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
414 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
415 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
416 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
417 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
418 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
419 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
420 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
421 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
422 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
423 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
424 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
425 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
426 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
427 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
428 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
429 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
430 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
431 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
432 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
436 /* Return truth value of whether OP can be used as an operands
437 where a register or 16 bit unsigned integer is needed. */
440 uns_arith_operand (op
, mode
)
442 enum machine_mode mode
;
444 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
447 return register_operand (op
, mode
);
450 /* Return truth value of whether OP can be used as an operands
451 where a 16 bit integer is needed */
454 arith_operand (op
, mode
)
456 enum machine_mode mode
;
458 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
461 /* On the mips16, a GP relative value is a signed 16 bit offset. */
462 if (TARGET_MIPS16
&& GET_CODE (op
) == CONST
&& mips16_gp_offset_p (op
))
465 return register_operand (op
, mode
);
468 /* Return truth value of whether OP can be used as an operand in a two
469 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
472 arith32_operand (op
, mode
)
474 enum machine_mode mode
;
476 if (GET_CODE (op
) == CONST_INT
)
479 return register_operand (op
, mode
);
482 /* Return truth value of whether OP is a integer which fits in 16 bits */
487 enum machine_mode mode ATTRIBUTE_UNUSED
;
489 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
492 /* Return truth value of whether OP is a 32 bit integer which is too big to
493 be loaded with one instruction. */
498 enum machine_mode mode ATTRIBUTE_UNUSED
;
502 if (GET_CODE (op
) != CONST_INT
)
507 /* ior reg,$r0,value */
508 if ((value
& ~ ((HOST_WIDE_INT
) 0x0000ffff)) == 0)
511 /* subu reg,$r0,value */
512 if (((unsigned HOST_WIDE_INT
) (value
+ 32768)) <= 32767)
515 /* lui reg,value>>16 */
516 if ((value
& 0x0000ffff) == 0)
522 /* Return truth value of whether OP is a register or the constant 0.
523 In mips16 mode, we only accept a register, since the mips16 does
527 reg_or_0_operand (op
, mode
)
529 enum machine_mode mode
;
531 switch (GET_CODE (op
))
536 return INTVAL (op
) == 0;
541 return op
== CONST0_RTX (mode
);
545 return register_operand (op
, mode
);
554 /* Return truth value of whether OP is a register or the constant 0,
555 even in mips16 mode. */
558 true_reg_or_0_operand (op
, mode
)
560 enum machine_mode mode
;
562 switch (GET_CODE (op
))
565 return INTVAL (op
) == 0;
568 return op
== CONST0_RTX (mode
);
572 return register_operand (op
, mode
);
581 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
584 mips_const_double_ok (op
, mode
)
586 enum machine_mode mode
;
590 if (GET_CODE (op
) != CONST_DOUBLE
)
593 if (mode
== VOIDmode
)
596 if (mode
!= SFmode
&& mode
!= DFmode
)
599 if (op
== CONST0_RTX (mode
))
602 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
603 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
&& mips_abi
!= ABI_EABI
)
606 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
608 if (REAL_VALUE_ISNAN (d
))
611 if (REAL_VALUE_NEGATIVE (d
))
612 d
= REAL_VALUE_NEGATE (d
);
616 if (REAL_VALUES_LESS (d
, dfhigh
)
617 && REAL_VALUES_LESS (dflow
, d
))
622 if (REAL_VALUES_LESS (d
, sfhigh
)
623 && REAL_VALUES_LESS (sflow
, d
))
630 /* Accept the floating point constant 1 in the appropriate mode. */
633 const_float_1_operand (op
, mode
)
635 enum machine_mode mode
;
638 static REAL_VALUE_TYPE onedf
;
639 static REAL_VALUE_TYPE onesf
;
640 static int one_initialized
;
642 if (GET_CODE (op
) != CONST_DOUBLE
643 || mode
!= GET_MODE (op
)
644 || (mode
!= DFmode
&& mode
!= SFmode
))
647 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
649 /* We only initialize these values if we need them, since we will
650 never get called unless mips_isa >= 4. */
651 if (! one_initialized
)
653 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
654 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
659 return REAL_VALUES_EQUAL (d
, onedf
);
661 return REAL_VALUES_EQUAL (d
, onesf
);
664 /* Return true if a memory load or store of REG plus OFFSET in MODE
665 can be represented in a single word on the mips16. */
668 mips16_simple_memory_operand (reg
, offset
, mode
)
671 enum machine_mode mode
;
677 /* We can't tell, because we don't know how the value will
678 eventually be accessed. Returning 0 here does no great
679 harm; it just prevents some possible instruction scheduling. */
683 size
= GET_MODE_SIZE (mode
);
685 if (INTVAL (offset
) % size
!= 0)
687 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode
) == 4)
691 if (INTVAL (offset
) >= 0 && INTVAL (offset
) < off
* size
)
696 /* Return truth value if a memory operand fits in a single instruction
697 (ie, register + small offset). */
700 simple_memory_operand (op
, mode
)
702 enum machine_mode mode
;
704 rtx addr
, plus0
, plus1
;
706 /* Eliminate non-memory operations */
707 if (GET_CODE (op
) != MEM
)
710 /* dword operations really put out 2 instructions, so eliminate them. */
711 /* ??? This isn't strictly correct. It is OK to accept multiword modes
712 here, since the length attributes are being set correctly, but only
713 if the address is offsettable. LO_SUM is not offsettable. */
714 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
717 /* Decode the address now. */
719 switch (GET_CODE (addr
))
728 return SMALL_INT (op
);
731 plus0
= XEXP (addr
, 0);
732 plus1
= XEXP (addr
, 1);
733 if (GET_CODE (plus0
) == REG
734 && GET_CODE (plus1
) == CONST_INT
&& SMALL_INT (plus1
)
736 || mips16_simple_memory_operand (plus0
, plus1
, mode
)))
739 else if (GET_CODE (plus1
) == REG
740 && GET_CODE (plus0
) == CONST_INT
&& SMALL_INT (plus0
)
742 || mips16_simple_memory_operand (plus1
, plus0
, mode
)))
749 /* We used to allow small symbol refs here (ie, stuff in .sdata
750 or .sbss), but this causes some bugs in G++. Also, it won't
751 interfere if the MIPS linker rewrites the store instruction
752 because the function is PIC. */
754 case LABEL_REF
: /* never gp relative */
758 /* If -G 0, we can never have a GP relative memory operation.
759 Also, save some time if not optimizing. */
764 rtx offset
= const0_rtx
;
765 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
766 if (GET_CODE (op
) != SYMBOL_REF
)
769 /* let's be paranoid.... */
770 if (! SMALL_INT (offset
))
777 return SYMBOL_REF_FLAG (addr
);
780 /* This SYMBOL_REF case is for the mips16. If the above case is
781 reenabled, this one should be merged in. */
783 /* References to the constant pool on the mips16 use a small
784 offset if the function is small. The only time we care about
785 getting this right is during delayed branch scheduling, so
786 don't need to check until then. The machine_dependent_reorg
787 function will set the total length of the instructions used
788 in the function in current_frame_info. If that is small
789 enough, we know for sure that this is a small offset. It
790 would be better if we could take into account the location of
791 the instruction within the function, but we can't, because we
792 don't know where we are. */
794 && CONSTANT_POOL_ADDRESS_P (addr
)
795 && current_frame_info
.insns_len
> 0)
799 size
= current_frame_info
.insns_len
+ get_pool_size ();
800 if (GET_MODE_SIZE (mode
) == 4)
801 return size
< 4 * 0x100;
802 else if (GET_MODE_SIZE (mode
) == 8)
803 return size
< 8 * 0x20;
817 /* Return nonzero for a memory address that can be used to load or store
821 double_memory_operand (op
, mode
)
823 enum machine_mode mode
;
827 if (GET_CODE (op
) != MEM
828 || ! memory_operand (op
, mode
))
830 /* During reload, we accept a pseudo register if it has an
831 appropriate memory address. If we don't do this, we will
832 wind up reloading into a register, and then reloading that
833 register from memory, when we could just reload directly from
835 if (reload_in_progress
836 && GET_CODE (op
) == REG
837 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
838 && reg_renumber
[REGNO (op
)] < 0
839 && reg_equiv_mem
[REGNO (op
)] != 0
840 && double_memory_operand (reg_equiv_mem
[REGNO (op
)], mode
))
843 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
844 the same test performed for 'm' in find_reloads. */
846 if (reload_in_progress
848 && (GET_CODE (op
) == MEM
849 || (GET_CODE (op
) == REG
850 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
851 && reg_renumber
[REGNO (op
)] < 0)))
854 if (reload_in_progress
856 && GET_CODE (op
) == MEM
)
862 /* During reload on the mips16, we accept a large offset
863 from the frame pointer or the stack pointer. This large
864 address will get reloaded anyhow. */
865 if (GET_CODE (addr
) == PLUS
866 && GET_CODE (XEXP (addr
, 0)) == REG
867 && (REGNO (XEXP (addr
, 0)) == HARD_FRAME_POINTER_REGNUM
868 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
869 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
870 && ! SMALL_INT (XEXP (addr
, 1)))
871 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
872 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
875 /* Similarly, we accept a case where the memory address is
876 itself on the stack, and will be reloaded. */
877 if (GET_CODE (addr
) == MEM
)
881 maddr
= XEXP (addr
, 0);
882 if (GET_CODE (maddr
) == PLUS
883 && GET_CODE (XEXP (maddr
, 0)) == REG
884 && (REGNO (XEXP (maddr
, 0)) == HARD_FRAME_POINTER_REGNUM
885 || REGNO (XEXP (maddr
, 0)) == STACK_POINTER_REGNUM
)
886 && ((GET_CODE (XEXP (maddr
, 1)) == CONST_INT
887 && ! SMALL_INT (XEXP (maddr
, 1)))
888 || (GET_CODE (XEXP (maddr
, 1)) == SYMBOL_REF
889 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr
, 1)))))
893 /* We also accept the same case when we have a 16 bit signed
894 offset mixed in as well. The large address will get
895 reloaded, and the 16 bit offset will be OK. */
896 if (GET_CODE (addr
) == PLUS
897 && GET_CODE (XEXP (addr
, 0)) == MEM
898 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
899 && SMALL_INT (XEXP (addr
, 1)))
901 addr
= XEXP (XEXP (addr
, 0), 0);
902 if (GET_CODE (addr
) == PLUS
903 && GET_CODE (XEXP (addr
, 0)) == REG
904 && (REGNO (XEXP (addr
, 0)) == HARD_FRAME_POINTER_REGNUM
905 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
906 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
907 && ! SMALL_INT (XEXP (addr
, 1)))
908 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
909 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
919 /* In this case we can use an instruction like sd. */
923 /* Make sure that 4 added to the address is a valid memory address.
924 This essentially just checks for overflow in an added constant. */
928 if (CONSTANT_ADDRESS_P (addr
))
931 return memory_address_p ((GET_MODE_CLASS (mode
) == MODE_INT
934 plus_constant_for_output (addr
, 4));
937 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
940 equality_op (op
, mode
)
942 enum machine_mode mode
;
944 if (mode
!= GET_MODE (op
))
947 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
950 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
955 enum machine_mode mode
;
957 if (mode
!= GET_MODE (op
))
960 return GET_RTX_CLASS (GET_CODE (op
)) == '<';
963 /* Return nonzero if the operand is either the PC or a label_ref. */
966 pc_or_label_operand (op
, mode
)
968 enum machine_mode mode ATTRIBUTE_UNUSED
;
973 if (GET_CODE (op
) == LABEL_REF
)
979 /* Test for a valid operand for a call instruction.
980 Don't allow the arg pointer register or virtual regs
981 since they may change into reg + const, which the patterns
985 call_insn_operand (op
, mode
)
987 enum machine_mode mode ATTRIBUTE_UNUSED
;
989 return (CONSTANT_ADDRESS_P (op
)
990 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
991 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
992 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
995 /* Return nonzero if OPERAND is valid as a source operand for a move
999 move_operand (op
, mode
)
1001 enum machine_mode mode
;
1003 /* Accept any general operand after reload has started; doing so
1004 avoids losing if reload does an in-place replacement of a register
1005 with a SYMBOL_REF or CONST. */
1006 return (general_operand (op
, mode
)
1007 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
1008 || reload_in_progress
|| reload_completed
)
1010 && GET_CODE (op
) == SYMBOL_REF
1011 && ! mips16_constant (op
, mode
, 1, 0)));
1014 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1015 This accepts not only general_operand, but also sign extended
1016 constants and registers. We need to accept sign extended constants
1017 in case a sign extended register which is used in an expression,
1018 and is equivalent to a constant, is spilled. */
1021 movdi_operand (op
, mode
)
1023 enum machine_mode mode
;
1027 && GET_CODE (op
) == SIGN_EXTEND
1028 && GET_MODE (op
) == DImode
1029 && (GET_MODE (XEXP (op
, 0)) == SImode
1030 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
1031 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
1032 && (register_operand (XEXP (op
, 0), SImode
)
1033 || immediate_operand (XEXP (op
, 0), SImode
)))
1036 return (general_operand (op
, mode
)
1038 && GET_CODE (op
) == SYMBOL_REF
1039 && ! mips16_constant (op
, mode
, 1, 0)));
1042 /* Like register_operand, but when in 64 bit mode also accept a sign
1043 extend of a 32 bit register, since the value is known to be already
1047 se_register_operand (op
, mode
)
1049 enum machine_mode mode
;
1053 && GET_CODE (op
) == SIGN_EXTEND
1054 && GET_MODE (op
) == DImode
1055 && GET_MODE (XEXP (op
, 0)) == SImode
1056 && register_operand (XEXP (op
, 0), SImode
))
1059 return register_operand (op
, mode
);
1062 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1063 extend of a 32 bit register, since the value is known to be already
1067 se_reg_or_0_operand (op
, mode
)
1069 enum machine_mode mode
;
1073 && GET_CODE (op
) == SIGN_EXTEND
1074 && GET_MODE (op
) == DImode
1075 && GET_MODE (XEXP (op
, 0)) == SImode
1076 && register_operand (XEXP (op
, 0), SImode
))
1079 return reg_or_0_operand (op
, mode
);
1082 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1083 extend of a 32 bit register, since the value is known to be already
1087 se_uns_arith_operand (op
, mode
)
1089 enum machine_mode mode
;
1093 && GET_CODE (op
) == SIGN_EXTEND
1094 && GET_MODE (op
) == DImode
1095 && GET_MODE (XEXP (op
, 0)) == SImode
1096 && register_operand (XEXP (op
, 0), SImode
))
1099 return uns_arith_operand (op
, mode
);
1102 /* Like arith_operand, but when in 64 bit mode also accept a sign
1103 extend of a 32 bit register, since the value is known to be already
1107 se_arith_operand (op
, mode
)
1109 enum machine_mode mode
;
1113 && GET_CODE (op
) == SIGN_EXTEND
1114 && GET_MODE (op
) == DImode
1115 && GET_MODE (XEXP (op
, 0)) == SImode
1116 && register_operand (XEXP (op
, 0), SImode
))
1119 return arith_operand (op
, mode
);
1122 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1123 extend of a 32 bit register, since the value is known to be already
1127 se_nonmemory_operand (op
, mode
)
1129 enum machine_mode mode
;
1133 && GET_CODE (op
) == SIGN_EXTEND
1134 && GET_MODE (op
) == DImode
1135 && GET_MODE (XEXP (op
, 0)) == SImode
1136 && register_operand (XEXP (op
, 0), SImode
))
1139 return nonmemory_operand (op
, mode
);
1142 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1143 sign extend of a 32 bit register, since the value is known to be
1144 already sign extended. */
1147 se_nonimmediate_operand (op
, mode
)
1149 enum machine_mode mode
;
1153 && GET_CODE (op
) == SIGN_EXTEND
1154 && GET_MODE (op
) == DImode
1155 && GET_MODE (XEXP (op
, 0)) == SImode
1156 && register_operand (XEXP (op
, 0), SImode
))
1159 return nonimmediate_operand (op
, mode
);
1162 /* Accept any operand that can appear in a mips16 constant table
1163 instruction. We can't use any of the standard operand functions
1164 because for these instructions we accept values that are not
1165 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1168 consttable_operand (op
, mode
)
1170 enum machine_mode mode ATTRIBUTE_UNUSED
;
1172 return CONSTANT_P (op
);
1175 /* Return nonzero if we split the address into high and low parts. */
1177 /* ??? We should also handle reg+array somewhere. We get four
1178 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1179 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1180 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1181 out of the address, then we have 4 instructions to combine. Perhaps
1182 add a 3->2 define_split for combine. */
1184 /* ??? We could also split a CONST_INT here if it is a large_int().
1185 However, it doesn't seem to be very useful to have %hi(constant).
1186 We would be better off by doing the masking ourselves and then putting
1187 the explicit high part of the constant in the RTL. This will give better
1188 optimization. Also, %hi(constant) needs assembler changes to work.
1189 There is already a define_split that does this. */
1192 mips_check_split (address
, mode
)
1194 enum machine_mode mode
;
1196 /* ??? This is the same check used in simple_memory_operand.
1197 We use it here because LO_SUM is not offsettable. */
1198 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
1201 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
1202 || (GET_CODE (address
) == CONST
1203 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
1204 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
1205 || GET_CODE (address
) == LABEL_REF
)
1211 /* We need a lot of little routines to check constant values on the
1212 mips16. These are used to figure out how long the instruction will
1213 be. It would be much better to do this using constraints, but
1214 there aren't nearly enough letters available. */
1217 m16_check_op (op
, low
, high
, mask
)
1223 return (GET_CODE (op
) == CONST_INT
1224 && INTVAL (op
) >= low
1225 && INTVAL (op
) <= high
1226 && (INTVAL (op
) & mask
) == 0);
1230 m16_uimm3_b (op
, mode
)
1232 enum machine_mode mode ATTRIBUTE_UNUSED
;
1234 return m16_check_op (op
, 0x1, 0x8, 0);
1238 m16_simm4_1 (op
, mode
)
1240 enum machine_mode mode ATTRIBUTE_UNUSED
;
1242 return m16_check_op (op
, - 0x8, 0x7, 0);
1246 m16_nsimm4_1 (op
, mode
)
1248 enum machine_mode mode ATTRIBUTE_UNUSED
;
1250 return m16_check_op (op
, - 0x7, 0x8, 0);
1254 m16_simm5_1 (op
, mode
)
1256 enum machine_mode mode ATTRIBUTE_UNUSED
;
1258 return m16_check_op (op
, - 0x10, 0xf, 0);
1262 m16_nsimm5_1 (op
, mode
)
1264 enum machine_mode mode ATTRIBUTE_UNUSED
;
1266 return m16_check_op (op
, - 0xf, 0x10, 0);
1270 m16_uimm5_4 (op
, mode
)
1272 enum machine_mode mode ATTRIBUTE_UNUSED
;
1274 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
1278 m16_nuimm5_4 (op
, mode
)
1280 enum machine_mode mode ATTRIBUTE_UNUSED
;
1282 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
1286 m16_simm8_1 (op
, mode
)
1288 enum machine_mode mode ATTRIBUTE_UNUSED
;
1290 return m16_check_op (op
, - 0x80, 0x7f, 0);
1294 m16_nsimm8_1 (op
, mode
)
1296 enum machine_mode mode ATTRIBUTE_UNUSED
;
1298 return m16_check_op (op
, - 0x7f, 0x80, 0);
1302 m16_uimm8_1 (op
, mode
)
1304 enum machine_mode mode ATTRIBUTE_UNUSED
;
1306 return m16_check_op (op
, 0x0, 0xff, 0);
1310 m16_nuimm8_1 (op
, mode
)
1312 enum machine_mode mode ATTRIBUTE_UNUSED
;
1314 return m16_check_op (op
, - 0xff, 0x0, 0);
1318 m16_uimm8_m1_1 (op
, mode
)
1320 enum machine_mode mode ATTRIBUTE_UNUSED
;
1322 return m16_check_op (op
, - 0x1, 0xfe, 0);
1326 m16_uimm8_4 (op
, mode
)
1328 enum machine_mode mode ATTRIBUTE_UNUSED
;
1330 return m16_check_op (op
, 0x0, 0xff << 2, 3);
1334 m16_nuimm8_4 (op
, mode
)
1336 enum machine_mode mode ATTRIBUTE_UNUSED
;
1338 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
1342 m16_simm8_8 (op
, mode
)
1344 enum machine_mode mode ATTRIBUTE_UNUSED
;
1346 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
1350 m16_nsimm8_8 (op
, mode
)
1352 enum machine_mode mode ATTRIBUTE_UNUSED
;
1354 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
1357 /* References to the string table on the mips16 only use a small
1358 offset if the function is small. See the comment in the SYMBOL_REF
1359 case in simple_memory_operand. We can't check for LABEL_REF here,
1360 because the offset is always large if the label is before the
1361 referencing instruction. */
1364 m16_usym8_4 (op
, mode
)
1366 enum machine_mode mode ATTRIBUTE_UNUSED
;
1368 if (GET_CODE (op
) == SYMBOL_REF
1369 && SYMBOL_REF_FLAG (op
)
1370 && current_frame_info
.insns_len
> 0
1371 && XSTR (op
, 0)[0] == '*'
1372 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1373 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1374 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1377 struct string_constant
*l
;
1379 /* Make sure this symbol is on thelist of string constants to be
1380 output for this function. It is possible that it has already
1381 been output, in which case this requires a large offset. */
1382 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1383 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1391 m16_usym5_4 (op
, mode
)
1393 enum machine_mode mode ATTRIBUTE_UNUSED
;
1395 if (GET_CODE (op
) == SYMBOL_REF
1396 && SYMBOL_REF_FLAG (op
)
1397 && current_frame_info
.insns_len
> 0
1398 && XSTR (op
, 0)[0] == '*'
1399 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1400 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1401 && (current_frame_info
.insns_len
+ get_pool_size () + mips_string_length
1404 struct string_constant
*l
;
1406 /* Make sure this symbol is on thelist of string constants to be
1407 output for this function. It is possible that it has already
1408 been output, in which case this requires a large offset. */
1409 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1410 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1417 /* Returns an operand string for the given instruction's delay slot,
1418 after updating filled delay slot statistics.
1420 We assume that operands[0] is the target register that is set.
1422 In order to check the next insn, most of this functionality is moved
1423 to FINAL_PRESCAN_INSN, and we just set the global variables that
1426 /* ??? This function no longer does anything useful, because final_prescan_insn
1427 now will never emit a nop. */
1430 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
1431 const char *ret
; /* normal string to return */
1432 enum delay_type type
; /* type of delay */
1433 rtx operands
[]; /* operands to use */
1434 rtx cur_insn
; /* current insn */
1436 register rtx set_reg
;
1437 register enum machine_mode mode
;
1438 register rtx next_insn
= cur_insn
? NEXT_INSN (cur_insn
) : NULL_RTX
;
1439 register int num_nops
;
1441 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
1444 else if (type
== DELAY_HILO
)
1450 /* Make sure that we don't put nop's after labels. */
1451 next_insn
= NEXT_INSN (cur_insn
);
1452 while (next_insn
!= 0 && GET_CODE (next_insn
) == NOTE
)
1453 next_insn
= NEXT_INSN (next_insn
);
1455 dslots_load_total
+= num_nops
;
1456 if (TARGET_DEBUG_F_MODE
1458 || type
== DELAY_NONE
1462 || GET_CODE (next_insn
) == CODE_LABEL
1463 || (set_reg
= operands
[0]) == 0)
1465 dslots_number_nops
= 0;
1473 set_reg
= operands
[0];
1477 while (GET_CODE (set_reg
) == SUBREG
)
1478 set_reg
= SUBREG_REG (set_reg
);
1480 mode
= GET_MODE (set_reg
);
1481 dslots_number_nops
= num_nops
;
1482 mips_load_reg
= set_reg
;
1483 if (GET_MODE_SIZE (mode
)
1484 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
1485 mips_load_reg2
= gen_rtx_REG (SImode
, REGNO (set_reg
) + 1);
1489 if (type
== DELAY_HILO
)
1491 mips_load_reg3
= gen_rtx_REG (SImode
, MD_REG_FIRST
);
1492 mips_load_reg4
= gen_rtx_REG (SImode
, MD_REG_FIRST
+1);
1504 /* Determine whether a memory reference takes one (based off of the GP
1505 pointer), two (normal), or three (label + reg) instructions, and bump the
1506 appropriate counter for -mstats. */
1509 mips_count_memory_refs (op
, num
)
1515 rtx addr
, plus0
, plus1
;
1516 enum rtx_code code0
, code1
;
1519 if (TARGET_DEBUG_B_MODE
)
1521 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1525 /* Skip MEM if passed, otherwise handle movsi of address. */
1526 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1528 /* Loop, going through the address RTL. */
1532 switch (GET_CODE (addr
))
1540 plus0
= XEXP (addr
, 0);
1541 plus1
= XEXP (addr
, 1);
1542 code0
= GET_CODE (plus0
);
1543 code1
= GET_CODE (plus1
);
1553 if (code0
== CONST_INT
)
1568 if (code1
== CONST_INT
)
1575 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1582 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1592 n_words
= 2; /* always 2 words */
1596 addr
= XEXP (addr
, 0);
1601 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1613 n_words
+= additional
;
1617 num_refs
[n_words
-1] += num
;
1621 /* Return RTL for the offset from the current function to the argument.
1623 ??? Which argument is this? */
1626 embedded_pic_offset (x
)
1629 if (embedded_pic_fnaddr_rtx
== NULL
)
1633 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1635 /* Output code at function start to initialize the pseudo-reg. */
1636 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1637 inline functions, because it is called after RTL for the function
1638 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1639 does not get copied, and ends up not matching the rest of the RTL.
1640 This solution works, but means that we get unnecessary code to
1641 initialize this value every time a function is inlined into another
1644 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1645 XEXP (DECL_RTL (current_function_decl
), 0)));
1646 seq
= gen_sequence ();
1648 push_topmost_sequence ();
1649 emit_insn_after (seq
, get_insns ());
1650 pop_topmost_sequence ();
1654 gen_rtx_CONST (Pmode
,
1655 gen_rtx_MINUS (Pmode
, x
,
1656 XEXP (DECL_RTL (current_function_decl
), 0)));
1659 /* Return the appropriate instructions to move one operand to another. */
1662 mips_move_1word (operands
, insn
, unsignedp
)
1667 const char *ret
= 0;
1668 rtx op0
= operands
[0];
1669 rtx op1
= operands
[1];
1670 enum rtx_code code0
= GET_CODE (op0
);
1671 enum rtx_code code1
= GET_CODE (op1
);
1672 enum machine_mode mode
= GET_MODE (op0
);
1673 int subreg_word0
= 0;
1674 int subreg_word1
= 0;
1675 enum delay_type delay
= DELAY_NONE
;
1677 while (code0
== SUBREG
)
1679 subreg_word0
+= SUBREG_WORD (op0
);
1680 op0
= SUBREG_REG (op0
);
1681 code0
= GET_CODE (op0
);
1684 while (code1
== SUBREG
)
1686 subreg_word1
+= SUBREG_WORD (op1
);
1687 op1
= SUBREG_REG (op1
);
1688 code1
= GET_CODE (op1
);
1691 /* For our purposes, a condition code mode is the same as SImode. */
1697 int regno0
= REGNO (op0
) + subreg_word0
;
1701 int regno1
= REGNO (op1
) + subreg_word1
;
1703 /* Just in case, don't do anything for assigning a register
1704 to itself, unless we are filling a delay slot. */
1705 if (regno0
== regno1
&& set_nomacro
== 0)
1708 else if (GP_REG_P (regno0
))
1710 if (GP_REG_P (regno1
))
1711 ret
= "move\t%0,%1";
1713 else if (MD_REG_P (regno1
))
1716 if (regno1
!= HILO_REGNUM
)
1722 else if (ST_REG_P (regno1
) && ISA_HAS_8CC
)
1723 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1728 if (FP_REG_P (regno1
))
1729 ret
= "mfc1\t%0,%1";
1731 else if (regno1
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
1732 ret
= "cfc1\t%0,$31";
1736 else if (FP_REG_P (regno0
))
1738 if (GP_REG_P (regno1
))
1741 ret
= "mtc1\t%1,%0";
1744 if (FP_REG_P (regno1
))
1745 ret
= "mov.s\t%0,%1";
1748 else if (MD_REG_P (regno0
))
1750 if (GP_REG_P (regno1
))
1753 if (regno0
!= HILO_REGNUM
&& ! TARGET_MIPS16
)
1758 else if (regno0
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
1760 if (GP_REG_P (regno1
))
1763 ret
= "ctc1\t%0,$31";
1768 else if (code1
== MEM
)
1773 mips_count_memory_refs (op1
, 1);
1775 if (GP_REG_P (regno0
))
1777 /* For loads, use the mode of the memory item, instead of the
1778 target, so zero/sign extend can use this code as well. */
1779 switch (GET_MODE (op1
))
1788 ret
= ((unsignedp
&& TARGET_64BIT
)
1793 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1796 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1801 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1804 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1806 size_t i
= strlen (ret
);
1807 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1810 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1811 ret
= volatile_buffer
;
1815 else if (code1
== CONST_INT
1816 || (code1
== CONST_DOUBLE
1817 && GET_MODE (op1
) == VOIDmode
))
1819 if (code1
== CONST_DOUBLE
)
1821 /* This can happen when storing constants into long long
1822 bitfields. Just store the least significant word of
1824 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1827 if (INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
1829 if (GP_REG_P (regno0
))
1830 ret
= "move\t%0,%z1";
1832 else if (FP_REG_P (regno0
))
1835 ret
= "mtc1\t%z1,%0";
1838 else if (MD_REG_P (regno0
))
1845 else if (GP_REG_P (regno0
))
1847 /* Don't use X format, because that will give out of
1848 range numbers for 64 bit host and 32 bit target. */
1849 if (! TARGET_MIPS16
)
1850 ret
= "li\t%0,%1\t\t\t# %X1";
1853 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
1855 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
1856 ret
= "li\t%0,%n1\n\tneg\t%0";
1861 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1863 if (op1
== CONST0_RTX (SFmode
))
1865 if (GP_REG_P (regno0
))
1866 ret
= "move\t%0,%.";
1868 else if (FP_REG_P (regno0
))
1871 ret
= "mtc1\t%.,%0";
1878 ret
= "li.s\t%0,%1";
1882 else if (code1
== LABEL_REF
)
1885 mips_count_memory_refs (op1
, 1);
1890 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1892 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1894 rtx offset
= const0_rtx
;
1896 if (GET_CODE (op1
) == CONST
)
1897 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1899 if (GET_CODE (op1
) == SYMBOL_REF
)
1901 operands
[2] = HALF_PIC_PTR (op1
);
1904 mips_count_memory_refs (operands
[2], 1);
1906 if (INTVAL (offset
) == 0)
1909 ret
= (unsignedp
&& TARGET_64BIT
1915 dslots_load_total
++;
1916 operands
[3] = offset
;
1917 if (unsignedp
&& TARGET_64BIT
)
1918 ret
= (SMALL_INT (offset
)
1919 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1920 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1922 ret
= (SMALL_INT (offset
)
1923 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1924 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1928 else if (TARGET_MIPS16
1930 && GET_CODE (XEXP (op1
, 0)) == REG
1931 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
1933 /* This case arises on the mips16; see
1934 mips16_gp_pseudo_reg. */
1935 ret
= "move\t%0,%+";
1937 else if (TARGET_MIPS16
1938 && code1
== SYMBOL_REF
1939 && SYMBOL_REF_FLAG (op1
)
1940 && (XSTR (op1
, 0)[0] != '*'
1941 || strncmp (XSTR (op1
, 0) + 1,
1943 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
1945 /* This can occur when reloading the address of a GP
1946 relative symbol on the mips16. */
1947 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
1952 mips_count_memory_refs (op1
, 1);
1958 else if (code1
== PLUS
)
1960 rtx add_op0
= XEXP (op1
, 0);
1961 rtx add_op1
= XEXP (op1
, 1);
1963 if (GET_CODE (XEXP (op1
, 1)) == REG
1964 && GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1965 add_op0
= XEXP (op1
, 1), add_op1
= XEXP (op1
, 0);
1967 operands
[2] = add_op0
;
1968 operands
[3] = add_op1
;
1969 ret
= "add%:\t%0,%2,%3";
1972 else if (code1
== HIGH
)
1974 operands
[1] = XEXP (op1
, 0);
1975 ret
= "lui\t%0,%%hi(%1)";
1979 else if (code0
== MEM
)
1982 mips_count_memory_refs (op0
, 1);
1986 int regno1
= REGNO (op1
) + subreg_word1
;
1988 if (GP_REG_P (regno1
))
1992 case SFmode
: ret
= "sw\t%1,%0"; break;
1993 case SImode
: ret
= "sw\t%1,%0"; break;
1994 case HImode
: ret
= "sh\t%1,%0"; break;
1995 case QImode
: ret
= "sb\t%1,%0"; break;
2000 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
2004 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
2008 case SFmode
: ret
= "sw\t%z1,%0"; break;
2009 case SImode
: ret
= "sw\t%z1,%0"; break;
2010 case HImode
: ret
= "sh\t%z1,%0"; break;
2011 case QImode
: ret
= "sb\t%z1,%0"; break;
2016 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
2020 case SFmode
: ret
= "sw\t%.,%0"; break;
2021 case SImode
: ret
= "sw\t%.,%0"; break;
2022 case HImode
: ret
= "sh\t%.,%0"; break;
2023 case QImode
: ret
= "sb\t%.,%0"; break;
2028 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2030 size_t i
= strlen (ret
);
2032 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2035 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2036 ret
= volatile_buffer
;
2042 abort_with_insn (insn
, "Bad move");
2046 if (delay
!= DELAY_NONE
)
2047 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2053 /* Return the appropriate instructions to move 2 words */
2056 mips_move_2words (operands
, insn
)
2060 const char *ret
= 0;
2061 rtx op0
= operands
[0];
2062 rtx op1
= operands
[1];
2063 enum rtx_code code0
= GET_CODE (operands
[0]);
2064 enum rtx_code code1
= GET_CODE (operands
[1]);
2065 int subreg_word0
= 0;
2066 int subreg_word1
= 0;
2067 enum delay_type delay
= DELAY_NONE
;
2069 while (code0
== SUBREG
)
2071 subreg_word0
+= SUBREG_WORD (op0
);
2072 op0
= SUBREG_REG (op0
);
2073 code0
= GET_CODE (op0
);
2076 if (code1
== SIGN_EXTEND
)
2078 op1
= XEXP (op1
, 0);
2079 code1
= GET_CODE (op1
);
2082 while (code1
== SUBREG
)
2084 subreg_word1
+= SUBREG_WORD (op1
);
2085 op1
= SUBREG_REG (op1
);
2086 code1
= GET_CODE (op1
);
2090 if (GET_CODE (operands
[1]) == SIGN_EXTEND
2092 && code1
!= CONST_INT
2093 /* The following three can happen as the result of a questionable
2095 && code1
!= LABEL_REF
2096 && code1
!= SYMBOL_REF
2102 int regno0
= REGNO (op0
) + subreg_word0
;
2106 int regno1
= REGNO (op1
) + subreg_word1
;
2108 /* Just in case, don't do anything for assigning a register
2109 to itself, unless we are filling a delay slot. */
2110 if (regno0
== regno1
&& set_nomacro
== 0)
2113 else if (FP_REG_P (regno0
))
2115 if (FP_REG_P (regno1
))
2116 ret
= "mov.d\t%0,%1";
2124 abort_with_insn (insn
, "Bad move");
2126 #ifdef TARGET_FP_CALL_32
2127 if (FP_CALL_GP_REG_P (regno1
))
2128 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2131 ret
= "dmtc1\t%1,%0";
2134 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2138 else if (FP_REG_P (regno1
))
2144 abort_with_insn (insn
, "Bad move");
2146 #ifdef TARGET_FP_CALL_32
2147 if (FP_CALL_GP_REG_P (regno0
))
2148 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2151 ret
= "dmfc1\t%0,%1";
2154 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2157 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
) && !TARGET_MIPS16
)
2162 if (regno0
!= HILO_REGNUM
)
2164 else if (regno1
== 0)
2165 ret
= "mtlo\t%.\n\tmthi\t%.";
2168 ret
= "mthi\t%M1\n\tmtlo\t%L1";
2171 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
2176 if (regno1
!= HILO_REGNUM
)
2180 ret
= "mfhi\t%M0\n\tmflo\t%L0";
2183 else if (TARGET_64BIT
)
2184 ret
= "move\t%0,%1";
2186 else if (regno0
!= (regno1
+1))
2187 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
2190 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
2193 else if (code1
== CONST_DOUBLE
)
2195 /* Move zero from $0 unless !TARGET_64BIT and recipient
2196 is 64-bit fp reg, in which case generate a constant. */
2197 if (op1
!= CONST0_RTX (GET_MODE (op1
))
2198 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
2200 if (GET_MODE (op1
) == DFmode
)
2204 #ifdef TARGET_FP_CALL_32
2205 if (FP_CALL_GP_REG_P (regno0
))
2207 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
2209 split_double (op1
, operands
+ 2, operands
+ 3);
2210 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2213 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2217 /* GNU as emits 64-bit code for li.d if the ISA is 3
2218 or higher. For !TARGET_64BIT && gp registers we
2219 need to avoid this by using two li instructions
2221 if (ISA_HAS_64BIT_REGS
2223 && ! FP_REG_P (regno0
))
2225 split_double (op1
, operands
+ 2, operands
+ 3);
2226 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2229 ret
= "li.d\t%0,%1";
2232 else if (TARGET_64BIT
)
2234 if (! TARGET_MIPS16
)
2240 split_double (op1
, operands
+ 2, operands
+ 3);
2241 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2247 if (GP_REG_P (regno0
))
2249 #ifdef TARGET_FP_CALL_32
2250 && ! FP_CALL_GP_REG_P (regno0
)
2253 : "move\t%0,%.\n\tmove\t%D0,%.");
2255 else if (FP_REG_P (regno0
))
2260 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2265 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2267 if (GP_REG_P (regno0
))
2270 : "move\t%0,%.\n\tmove\t%D0,%.");
2272 else if (FP_REG_P (regno0
))
2279 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2281 else if (MD_REG_P (regno0
))
2284 ret
= (regno0
== HILO_REGNUM
2285 ? "mtlo\t%.\n\tmthi\t%."
2290 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
2291 && GP_REG_P (regno0
))
2297 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2299 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2300 ret
= "li\t%0,%n1\n\tneg\t%0";
2302 else if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2303 ret
= "li\t%0,%1\t\t# %X1";
2304 else if (HOST_BITS_PER_WIDE_INT
< 64)
2305 /* We can't use 'X' for negative numbers, because then we won't
2306 get the right value for the upper 32 bits. */
2307 ret
= (INTVAL (op1
) < 0
2308 ? "dli\t%0,%1\t\t\t# %X1"
2309 : "dli\t%0,%X1\t\t# %1");
2311 /* We must use 'X', because otherwise LONG_MIN will print as
2312 a number that the assembler won't accept. */
2313 ret
= "dli\t%0,%X1\t\t# %1";
2315 else if (HOST_BITS_PER_WIDE_INT
< 64)
2317 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
2320 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2321 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2322 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2324 operands
[2] = GEN_INT (1);
2325 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2329 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2333 /* We use multiple shifts here, to avoid warnings about out
2334 of range shifts on 32 bit hosts. */
2335 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
2337 = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
2338 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2342 else if (code1
== MEM
)
2347 mips_count_memory_refs (op1
, 2);
2349 if (FP_REG_P (regno0
))
2352 else if (TARGET_64BIT
)
2355 #ifdef TARGET_FP_CALL_32
2356 if (FP_CALL_GP_REG_P (regno0
))
2357 ret
= (double_memory_operand (op1
, GET_MODE (op1
))
2358 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2359 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2365 else if (double_memory_operand (op1
, GET_MODE (op1
)))
2367 operands
[2] = adj_offsettable_operand (op1
, 4);
2368 ret
= (reg_mentioned_p (op0
, op1
)
2369 ? "lw\t%D0,%2\n\tlw\t%0,%1"
2370 : "lw\t%0,%1\n\tlw\t%D0,%2");
2373 if (ret
!= 0 && MEM_VOLATILE_P (op1
))
2375 size_t i
= strlen (ret
);
2377 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2380 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2381 ret
= volatile_buffer
;
2385 else if (code1
== LABEL_REF
)
2388 mips_count_memory_refs (op1
, 2);
2390 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2391 /* We deliberately remove the 'a' from '%1', so that we don't
2392 have to add SIGN_EXTEND support to print_operand_address.
2393 print_operand will just call print_operand_address in this
2394 case, so there is no problem. */
2397 ret
= "dla\t%0,%a1";
2399 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2403 && GET_CODE (XEXP (op1
, 0)) == REG
2404 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2406 /* This case arises on the mips16; see
2407 mips16_gp_pseudo_reg. */
2408 ret
= "move\t%0,%+";
2410 else if (TARGET_MIPS16
2411 && code1
== SYMBOL_REF
2412 && SYMBOL_REF_FLAG (op1
)
2413 && (XSTR (op1
, 0)[0] != '*'
2414 || strncmp (XSTR (op1
, 0) + 1,
2416 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2418 /* This can occur when reloading the address of a GP
2419 relative symbol on the mips16. */
2420 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2425 mips_count_memory_refs (op1
, 2);
2427 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2428 /* We deliberately remove the 'a' from '%1', so that we don't
2429 have to add SIGN_EXTEND support to print_operand_address.
2430 print_operand will just call print_operand_address in this
2431 case, so there is no problem. */
2434 ret
= "dla\t%0,%a1";
2439 else if (code0
== MEM
)
2443 int regno1
= REGNO (op1
) + subreg_word1
;
2445 if (FP_REG_P (regno1
))
2448 else if (TARGET_64BIT
)
2451 #ifdef TARGET_FP_CALL_32
2452 if (FP_CALL_GP_REG_P (regno1
))
2453 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2459 else if (double_memory_operand (op0
, GET_MODE (op0
)))
2461 operands
[2] = adj_offsettable_operand (op0
, 4);
2462 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
2466 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
2467 || (code1
== CONST_DOUBLE
2468 && op1
== CONST0_RTX (GET_MODE (op1
))))
2470 || double_memory_operand (op0
, GET_MODE (op0
))))
2476 operands
[2] = adj_offsettable_operand (op0
, 4);
2477 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
2482 mips_count_memory_refs (op0
, 2);
2484 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2486 size_t i
= strlen (ret
);
2488 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2491 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2492 ret
= volatile_buffer
;
2498 abort_with_insn (insn
, "Bad move");
2502 if (delay
!= DELAY_NONE
)
2503 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2508 /* Provide the costs of an addressing mode that contains ADDR.
2509 If ADDR is not a valid address, its cost is irrelevant. */
2512 mips_address_cost (addr
)
2515 switch (GET_CODE (addr
))
2525 rtx offset
= const0_rtx
;
2526 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
2527 if (GET_CODE (addr
) == LABEL_REF
)
2530 if (GET_CODE (addr
) != SYMBOL_REF
)
2533 if (! SMALL_INT (offset
))
2537 /* ... fall through ... */
2540 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
2544 register rtx plus0
= XEXP (addr
, 0);
2545 register rtx plus1
= XEXP (addr
, 1);
2547 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
2548 plus0
= XEXP (addr
, 1), plus1
= XEXP (addr
, 0);
2550 if (GET_CODE (plus0
) != REG
)
2553 switch (GET_CODE (plus1
))
2556 return SMALL_INT (plus1
) ? 1 : 2;
2563 return mips_address_cost (plus1
) + 1;
2577 /* Return nonzero if X is an address which needs a temporary register when
2578 reloaded while generating PIC code. */
2581 pic_address_needs_scratch (x
)
2584 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2585 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
2586 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2587 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2588 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
2594 /* Make normal rtx_code into something we can index from an array */
2596 static enum internal_test
2597 map_test_to_internal_test (test_code
)
2598 enum rtx_code test_code
;
2600 enum internal_test test
= ITEST_MAX
;
2604 case EQ
: test
= ITEST_EQ
; break;
2605 case NE
: test
= ITEST_NE
; break;
2606 case GT
: test
= ITEST_GT
; break;
2607 case GE
: test
= ITEST_GE
; break;
2608 case LT
: test
= ITEST_LT
; break;
2609 case LE
: test
= ITEST_LE
; break;
2610 case GTU
: test
= ITEST_GTU
; break;
2611 case GEU
: test
= ITEST_GEU
; break;
2612 case LTU
: test
= ITEST_LTU
; break;
2613 case LEU
: test
= ITEST_LEU
; break;
2621 /* Generate the code to compare two integer values. The return value is:
2622 (reg:SI xx) The pseudo register the comparison is in
2623 0 No register, generate a simple branch.
2625 ??? This is called with result nonzero by the Scond patterns in
2626 mips.md. These patterns are called with a target in the mode of
2627 the Scond instruction pattern. Since this must be a constant, we
2628 must use SImode. This means that if RESULT is non-zero, it will
2629 always be an SImode register, even if TARGET_64BIT is true. We
2630 cope with this by calling convert_move rather than emit_move_insn.
2631 This will sometimes lead to an unnecessary extension of the result;
2643 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2644 enum rtx_code test_code
; /* relational test (EQ, etc) */
2645 rtx result
; /* result to store comp. or 0 if branch */
2646 rtx cmp0
; /* first operand to compare */
2647 rtx cmp1
; /* second operand to compare */
2648 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2649 /* to reverse its test */
2653 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2654 int const_low
; /* low bound of constant we can accept */
2655 int const_high
; /* high bound of constant we can accept */
2656 int const_add
; /* constant to add (convert LE -> LT) */
2657 int reverse_regs
; /* reverse registers in test */
2658 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2659 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2660 int unsignedp
; /* != 0 for unsigned comparisons. */
2663 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2665 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2666 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2667 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2668 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2669 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2670 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2671 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2672 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2673 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2674 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2677 enum internal_test test
;
2678 enum machine_mode mode
;
2679 struct cmp_info
*p_info
;
2686 test
= map_test_to_internal_test (test_code
);
2687 if (test
== ITEST_MAX
)
2690 p_info
= &info
[(int) test
];
2691 eqne_p
= (p_info
->test_code
== XOR
);
2693 mode
= GET_MODE (cmp0
);
2694 if (mode
== VOIDmode
)
2695 mode
= GET_MODE (cmp1
);
2697 /* Eliminate simple branches */
2698 branch_p
= (result
== 0);
2701 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2703 /* Comparisons against zero are simple branches */
2704 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0
2705 && (! TARGET_MIPS16
|| eqne_p
))
2708 /* Test for beq/bne. */
2709 if (eqne_p
&& ! TARGET_MIPS16
)
2713 /* allocate a pseudo to calculate the value in. */
2714 result
= gen_reg_rtx (mode
);
2717 /* Make sure we can handle any constants given to us. */
2718 if (GET_CODE (cmp0
) == CONST_INT
)
2719 cmp0
= force_reg (mode
, cmp0
);
2721 if (GET_CODE (cmp1
) == CONST_INT
)
2723 HOST_WIDE_INT value
= INTVAL (cmp1
);
2725 if (value
< p_info
->const_low
2726 || value
> p_info
->const_high
2727 /* ??? Why? And why wasn't the similar code below modified too? */
2729 && HOST_BITS_PER_WIDE_INT
< 64
2730 && p_info
->const_add
!= 0
2731 && ((p_info
->unsignedp
2732 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2733 > (unsigned HOST_WIDE_INT
) INTVAL (cmp1
))
2734 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2735 != (p_info
->const_add
> 0))))
2736 cmp1
= force_reg (mode
, cmp1
);
2739 /* See if we need to invert the result. */
2740 invert
= (GET_CODE (cmp1
) == CONST_INT
2741 ? p_info
->invert_const
: p_info
->invert_reg
);
2743 if (p_invert
!= (int *)0)
2749 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2750 Comparison between two registers, may involve switching operands. */
2751 if (GET_CODE (cmp1
) == CONST_INT
)
2753 if (p_info
->const_add
!= 0)
2755 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2757 /* If modification of cmp1 caused overflow,
2758 we would get the wrong answer if we follow the usual path;
2759 thus, x > 0xffffffffU would turn into x > 0U. */
2760 if ((p_info
->unsignedp
2761 ? (unsigned HOST_WIDE_INT
) new >
2762 (unsigned HOST_WIDE_INT
) INTVAL (cmp1
)
2763 : new > INTVAL (cmp1
))
2764 != (p_info
->const_add
> 0))
2766 /* This test is always true, but if INVERT is true then
2767 the result of the test needs to be inverted so 0 should
2768 be returned instead. */
2769 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2773 cmp1
= GEN_INT (new);
2777 else if (p_info
->reverse_regs
)
2784 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2788 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
2789 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2792 if (test
== ITEST_NE
)
2794 if (! TARGET_MIPS16
)
2796 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
2801 reg2
= invert
? gen_reg_rtx (mode
) : result
;
2802 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
2807 else if (test
== ITEST_EQ
)
2809 reg2
= invert
? gen_reg_rtx (mode
) : result
;
2810 convert_move (reg2
, gen_rtx_LTU (mode
, reg
, const1_rtx
), 0);
2818 if (! TARGET_MIPS16
)
2822 /* The value is in $24. Copy it to another register, so
2823 that reload doesn't think it needs to store the $24 and
2824 the input to the XOR in the same location. */
2825 reg2
= gen_reg_rtx (mode
);
2826 emit_move_insn (reg2
, reg
);
2828 one
= force_reg (mode
, const1_rtx
);
2830 convert_move (result
, gen_rtx (XOR
, mode
, reg
, one
), 0);
2836 /* Emit the common code for doing conditional branches.
2837 operand[0] is the label to jump to.
2838 The comparison operands are saved away by cmp{si,di,sf,df}. */
2841 gen_conditional_branch (operands
, test_code
)
2843 enum rtx_code test_code
;
2845 enum cmp_type type
= branch_type
;
2846 rtx cmp0
= branch_cmp
[0];
2847 rtx cmp1
= branch_cmp
[1];
2848 enum machine_mode mode
;
2857 mode
= type
== CMP_SI
? SImode
: DImode
;
2859 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2867 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2868 /* We don't want to build a comparison against a non-zero
2870 cmp1
= force_reg (mode
, cmp1
);
2877 reg
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
2879 reg
= gen_reg_rtx (CCmode
);
2881 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2882 0 in the instruction built below. The MIPS FPU handles
2883 inequality testing by testing for equality and looking for a
2885 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
2886 gen_rtx (test_code
== NE
? EQ
: test_code
,
2887 CCmode
, cmp0
, cmp1
)));
2889 test_code
= test_code
== NE
? EQ
: NE
;
2897 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2900 /* Generate the branch. */
2902 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
2911 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
2912 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2913 gen_rtx (test_code
, mode
,
2918 /* Emit the common code for conditional moves. OPERANDS is the array
2919 of operands passed to the conditional move defined_expand. */
2922 gen_conditional_move (operands
)
2925 rtx op0
= branch_cmp
[0];
2926 rtx op1
= branch_cmp
[1];
2927 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2928 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2929 enum rtx_code move_code
= NE
;
2930 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2931 enum machine_mode cmp_mode
;
2934 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2953 op0
= force_reg (mode
, branch_cmp
[1]);
2954 op1
= branch_cmp
[0];
2958 op0
= force_reg (mode
, branch_cmp
[1]);
2959 op1
= branch_cmp
[0];
2970 op0
= force_reg (mode
, branch_cmp
[1]);
2971 op1
= branch_cmp
[0];
2975 op0
= force_reg (mode
, branch_cmp
[1]);
2976 op1
= branch_cmp
[0];
2983 else if (cmp_code
== NE
)
2984 cmp_code
= EQ
, move_code
= EQ
;
2986 if (mode
== SImode
|| mode
== DImode
)
2988 else if (mode
== SFmode
|| mode
== DFmode
)
2993 cmp_reg
= gen_reg_rtx (cmp_mode
);
2994 emit_insn (gen_rtx_SET (cmp_mode
, cmp_reg
,
2995 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2997 emit_insn (gen_rtx_SET (op_mode
, operands
[0],
2998 gen_rtx_IF_THEN_ELSE (op_mode
,
2999 gen_rtx (move_code
, VOIDmode
,
3001 CONST0_RTX (SImode
)),
3002 operands
[2], operands
[3])));
3005 /* Write a loop to move a constant number of bytes.
3006 Generate load/stores as follows:
3012 temp<last> = src[MAX_MOVE_REGS-1];
3016 dest[MAX_MOVE_REGS-1] = temp<last>;
3017 src += MAX_MOVE_REGS;
3018 dest += MAX_MOVE_REGS;
3019 } while (src != final);
3021 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3022 registers are needed.
3024 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3025 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3026 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3028 #define MAX_MOVE_REGS 4
3029 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3032 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
3033 rtx dest_reg
; /* register holding destination address */
3034 rtx src_reg
; /* register holding source address */
3035 int bytes
; /* # bytes to move */
3036 int align
; /* alignment */
3037 rtx orig_dest
; /* original dest for change_address */
3038 rtx orig_src
; /* original source for making a reg note */
3040 rtx dest_mem
= change_address (orig_dest
, BLKmode
, dest_reg
);
3041 rtx src_mem
= change_address (orig_src
, BLKmode
, src_reg
);
3042 rtx align_rtx
= GEN_INT (align
);
3048 if (bytes
< 2 * MAX_MOVE_BYTES
)
3051 leftover
= bytes
% MAX_MOVE_BYTES
;
3054 label
= gen_label_rtx ();
3055 final_src
= gen_reg_rtx (Pmode
);
3056 bytes_rtx
= GEN_INT (bytes
);
3060 if (Pmode
== DImode
)
3062 emit_insn (gen_movdi (final_src
, bytes_rtx
));
3063 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
3067 emit_insn (gen_movsi (final_src
, bytes_rtx
));
3068 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
3073 if (Pmode
== DImode
)
3074 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
3076 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
3081 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
3082 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
3084 if (Pmode
== DImode
)
3086 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
3087 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
3088 emit_insn (gen_cmpdi (src_reg
, final_src
));
3092 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
3093 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
3094 emit_insn (gen_cmpsi (src_reg
, final_src
));
3097 emit_jump_insn (gen_bne (label
));
3100 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, GEN_INT (leftover
),
3104 /* Use a library function to move some bytes. */
3107 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
3112 /* We want to pass the size as Pmode, which will normally be SImode
3113 but will be DImode if we are using 64 bit longs and pointers. */
3114 if (GET_MODE (bytes_rtx
) != VOIDmode
3115 && GET_MODE (bytes_rtx
) != Pmode
)
3116 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
3118 #ifdef TARGET_MEM_FUNCTIONS
3119 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0,
3120 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
3121 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
3122 TREE_UNSIGNED (sizetype
)),
3123 TYPE_MODE (sizetype
));
3125 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "bcopy"), 0,
3126 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
3127 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
3128 TREE_UNSIGNED (integer_type_node
)),
3129 TYPE_MODE (integer_type_node
));
3133 /* Expand string/block move operations.
3135 operands[0] is the pointer to the destination.
3136 operands[1] is the pointer to the source.
3137 operands[2] is the number of bytes to move.
3138 operands[3] is the alignment. */
3141 expand_block_move (operands
)
3144 rtx bytes_rtx
= operands
[2];
3145 rtx align_rtx
= operands
[3];
3146 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
3147 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
3148 int align
= INTVAL (align_rtx
);
3149 rtx orig_src
= operands
[1];
3150 rtx orig_dest
= operands
[0];
3154 if (constp
&& bytes
<= 0)
3157 if (align
> UNITS_PER_WORD
)
3158 align
= UNITS_PER_WORD
;
3160 /* Move the address into scratch registers. */
3161 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
3162 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
3165 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3167 else if (constp
&& bytes
<= 2 * MAX_MOVE_BYTES
3168 && align
== UNITS_PER_WORD
)
3169 move_by_pieces (orig_dest
, orig_src
, bytes
, align
);
3171 else if (constp
&& bytes
<= 2 * MAX_MOVE_BYTES
)
3172 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
3174 change_address (orig_src
, BLKmode
,
3176 bytes_rtx
, align_rtx
));
3178 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
3179 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
3181 else if (constp
&& optimize
)
3183 /* If the alignment is not word aligned, generate a test at
3184 runtime, to see whether things wound up aligned, and we
3185 can use the faster lw/sw instead ulw/usw. */
3187 rtx temp
= gen_reg_rtx (Pmode
);
3188 rtx aligned_label
= gen_label_rtx ();
3189 rtx join_label
= gen_label_rtx ();
3190 int leftover
= bytes
% MAX_MOVE_BYTES
;
3194 if (Pmode
== DImode
)
3196 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
3197 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3198 emit_insn (gen_cmpdi (temp
, const0_rtx
));
3202 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
3203 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3204 emit_insn (gen_cmpsi (temp
, const0_rtx
));
3207 emit_jump_insn (gen_beq (aligned_label
));
3209 /* Unaligned loop. */
3210 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
3211 emit_jump_insn (gen_jump (join_label
));
3215 emit_label (aligned_label
);
3216 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
3218 emit_label (join_label
);
3220 /* Bytes at the end of the loop. */
3222 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
3224 change_address (orig_src
, BLKmode
,
3231 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3234 /* Emit load/stores for a small constant block_move.
3236 operands[0] is the memory address of the destination.
3237 operands[1] is the memory address of the source.
3238 operands[2] is the number of bytes to move.
3239 operands[3] is the alignment.
3240 operands[4] is a temp register.
3241 operands[5] is a temp register.
3243 operands[3+num_regs] is the last temp register.
3245 The block move type can be one of the following:
3246 BLOCK_MOVE_NORMAL Do all of the block move.
3247 BLOCK_MOVE_NOT_LAST Do all but the last store.
3248 BLOCK_MOVE_LAST Do just the last store. */
3251 output_block_move (insn
, operands
, num_regs
, move_type
)
3255 enum block_move_type move_type
;
3257 rtx dest_reg
= XEXP (operands
[0], 0);
3258 rtx src_reg
= XEXP (operands
[1], 0);
3259 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
3260 int align
= INTVAL (operands
[3]);
3263 int use_lwl_lwr
= 0;
3264 int last_operand
= num_regs
+ 4;
3270 const char *load
; /* load insn without nop */
3271 const char *load_nop
; /* load insn with trailing nop */
3272 const char *store
; /* store insn */
3273 const char *final
; /* if last_store used: NULL or swr */
3274 const char *last_store
; /* last store instruction */
3275 int offset
; /* current offset */
3276 enum machine_mode mode
; /* mode to use on (MEM) */
3279 /* ??? Detect a bug in GCC, where it can give us a register
3280 the same as one of the addressing registers and reduce
3281 the number of registers available. */
3284 && safe_regs
< (int)(sizeof(xoperands
) / sizeof(xoperands
[0]));
3286 if (! reg_mentioned_p (operands
[i
], operands
[0])
3287 && ! reg_mentioned_p (operands
[i
], operands
[1]))
3288 xoperands
[safe_regs
++] = operands
[i
];
3290 if (safe_regs
< last_operand
)
3292 xoperands
[0] = operands
[0];
3293 xoperands
[1] = operands
[1];
3294 xoperands
[2] = operands
[2];
3295 xoperands
[3] = operands
[3];
3296 return output_block_move (insn
, xoperands
, safe_regs
- 4, move_type
);
3299 /* If we are given global or static addresses, and we would be
3300 emitting a few instructions, try to save time by using a
3301 temporary register for the pointer. */
3302 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3303 an ldl/ldr instruction pair. We play it safe, and always move
3304 constant addresses into registers when generating N32/N64 code, just
3305 in case we might emit an unaligned load instruction. */
3306 if (num_regs
> 2 && (bytes
> 2 * align
|| move_type
!= BLOCK_MOVE_NORMAL
3307 || mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3309 if (CONSTANT_P (src_reg
))
3312 mips_count_memory_refs (operands
[1], 1);
3314 src_reg
= operands
[3 + num_regs
--];
3315 if (move_type
!= BLOCK_MOVE_LAST
)
3317 xoperands
[1] = operands
[1];
3318 xoperands
[0] = src_reg
;
3319 if (Pmode
== DImode
)
3320 output_asm_insn ("dla\t%0,%1", xoperands
);
3322 output_asm_insn ("la\t%0,%1", xoperands
);
3326 if (CONSTANT_P (dest_reg
))
3329 mips_count_memory_refs (operands
[0], 1);
3331 dest_reg
= operands
[3 + num_regs
--];
3332 if (move_type
!= BLOCK_MOVE_LAST
)
3334 xoperands
[1] = operands
[0];
3335 xoperands
[0] = dest_reg
;
3336 if (Pmode
== DImode
)
3337 output_asm_insn ("dla\t%0,%1", xoperands
);
3339 output_asm_insn ("la\t%0,%1", xoperands
);
3344 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3345 are not offsettable, however, offsettable_address_p says they are
3346 offsettable. I think this is a bug in offsettable_address_p.
3347 For expediency, we fix this by just loading the address into a register
3348 if we happen to get one. */
3350 if (GET_CODE (src_reg
) == LO_SUM
)
3352 src_reg
= operands
[3 + num_regs
--];
3353 if (move_type
!= BLOCK_MOVE_LAST
)
3355 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
3356 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3357 xoperands
[0] = src_reg
;
3358 if (Pmode
== DImode
)
3359 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3361 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3365 if (GET_CODE (dest_reg
) == LO_SUM
)
3367 dest_reg
= operands
[3 + num_regs
--];
3368 if (move_type
!= BLOCK_MOVE_LAST
)
3370 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
3371 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
3372 xoperands
[0] = dest_reg
;
3373 if (Pmode
== DImode
)
3374 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3376 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3380 if (num_regs
> (int)(sizeof (load_store
) / sizeof (load_store
[0])))
3381 num_regs
= sizeof (load_store
) / sizeof (load_store
[0]);
3383 else if (num_regs
< 1)
3384 abort_with_insn (insn
,
3385 "Cannot do block move, not enough scratch registers");
3389 load_store
[num
].offset
= offset
;
3391 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
3393 load_store
[num
].load
= "ld\t%0,%1";
3394 load_store
[num
].load_nop
= "ld\t%0,%1%#";
3395 load_store
[num
].store
= "sd\t%0,%1";
3396 load_store
[num
].last_store
= "sd\t%0,%1";
3397 load_store
[num
].final
= 0;
3398 load_store
[num
].mode
= DImode
;
3403 /* ??? Fails because of a MIPS assembler bug? */
3404 else if (TARGET_64BIT
&& bytes
>= 8 && ! TARGET_MIPS16
)
3406 if (BYTES_BIG_ENDIAN
)
3408 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
3409 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
3410 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
3411 load_store
[num
].last_store
= "sdr\t%0,%2";
3412 load_store
[num
].final
= "sdl\t%0,%1";
3416 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
3417 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
3418 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
3419 load_store
[num
].last_store
= "sdr\t%0,%1";
3420 load_store
[num
].final
= "sdl\t%0,%2";
3423 load_store
[num
].mode
= DImode
;
3429 else if (bytes
>= 4 && align
>= 4)
3431 load_store
[num
].load
= "lw\t%0,%1";
3432 load_store
[num
].load_nop
= "lw\t%0,%1%#";
3433 load_store
[num
].store
= "sw\t%0,%1";
3434 load_store
[num
].last_store
= "sw\t%0,%1";
3435 load_store
[num
].final
= 0;
3436 load_store
[num
].mode
= SImode
;
3441 else if (bytes
>= 4 && ! TARGET_MIPS16
)
3443 if (BYTES_BIG_ENDIAN
)
3445 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
3446 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3447 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
3448 load_store
[num
].last_store
= "swr\t%0,%2";
3449 load_store
[num
].final
= "swl\t%0,%1";
3453 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
3454 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3455 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
3456 load_store
[num
].last_store
= "swr\t%0,%1";
3457 load_store
[num
].final
= "swl\t%0,%2";
3460 load_store
[num
].mode
= SImode
;
3466 else if (bytes
>= 2 && align
>= 2)
3468 load_store
[num
].load
= "lh\t%0,%1";
3469 load_store
[num
].load_nop
= "lh\t%0,%1%#";
3470 load_store
[num
].store
= "sh\t%0,%1";
3471 load_store
[num
].last_store
= "sh\t%0,%1";
3472 load_store
[num
].final
= 0;
3473 load_store
[num
].mode
= HImode
;
3479 load_store
[num
].load
= "lb\t%0,%1";
3480 load_store
[num
].load_nop
= "lb\t%0,%1%#";
3481 load_store
[num
].store
= "sb\t%0,%1";
3482 load_store
[num
].last_store
= "sb\t%0,%1";
3483 load_store
[num
].final
= 0;
3484 load_store
[num
].mode
= QImode
;
3489 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3491 dslots_load_total
++;
3492 dslots_load_filled
++;
3494 if (CONSTANT_P (src_reg
))
3495 mips_count_memory_refs (src_reg
, 1);
3497 if (CONSTANT_P (dest_reg
))
3498 mips_count_memory_refs (dest_reg
, 1);
3501 /* Emit load/stores now if we have run out of registers or are
3502 at the end of the move. */
3504 if (++num
== num_regs
|| bytes
== 0)
3506 /* If only load/store, we need a NOP after the load. */
3509 load_store
[0].load
= load_store
[0].load_nop
;
3510 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
3511 dslots_load_filled
--;
3514 if (move_type
!= BLOCK_MOVE_LAST
)
3516 for (i
= 0; i
< num
; i
++)
3520 if (!operands
[i
+ 4])
3523 if (GET_MODE (operands
[i
+ 4]) != load_store
[i
].mode
)
3524 operands
[i
+ 4] = gen_rtx_REG (load_store
[i
].mode
,
3525 REGNO (operands
[i
+ 4]));
3527 offset
= load_store
[i
].offset
;
3528 xoperands
[0] = operands
[i
+ 4];
3529 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
3530 plus_constant (src_reg
, offset
));
3535 = GET_MODE_SIZE (load_store
[i
].mode
) - 1;
3537 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
3538 plus_constant (src_reg
,
3543 output_asm_insn (load_store
[i
].load
, xoperands
);
3547 for (i
= 0; i
< num
; i
++)
3549 int last_p
= (i
== num
-1 && bytes
== 0);
3550 int offset
= load_store
[i
].offset
;
3552 xoperands
[0] = operands
[i
+ 4];
3553 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
3554 plus_constant (dest_reg
, offset
));
3559 int extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
3560 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
3561 plus_constant (dest_reg
,
3566 if (move_type
== BLOCK_MOVE_NORMAL
)
3567 output_asm_insn (load_store
[i
].store
, xoperands
);
3569 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
3572 output_asm_insn (load_store
[i
].store
, xoperands
);
3574 else if (load_store
[i
].final
!= 0)
3575 output_asm_insn (load_store
[i
].final
, xoperands
);
3579 output_asm_insn (load_store
[i
].last_store
, xoperands
);
3582 num
= 0; /* reset load_store */
3590 /* Argument support functions. */
3592 /* Initialize CUMULATIVE_ARGS for a function. */
3595 init_cumulative_args (cum
, fntype
, libname
)
3596 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
3597 tree fntype
; /* tree ptr for function decl */
3598 rtx libname ATTRIBUTE_UNUSED
; /* SYMBOL_REF of library name or 0 */
3600 static CUMULATIVE_ARGS zero_cum
;
3601 tree param
, next_param
;
3603 if (TARGET_DEBUG_E_MODE
)
3606 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
3609 fputc ('\n', stderr
);
3613 tree ret_type
= TREE_TYPE (fntype
);
3614 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
3615 tree_code_name
[(int)TREE_CODE (fntype
)],
3616 tree_code_name
[(int)TREE_CODE (ret_type
)]);
3622 /* Determine if this function has variable arguments. This is
3623 indicated by the last argument being 'void_type_mode' if there
3624 are no variable arguments. The standard MIPS calling sequence
3625 passes all arguments in the general purpose registers in this case. */
3627 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
3628 param
!= 0; param
= next_param
)
3630 next_param
= TREE_CHAIN (param
);
3631 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
3632 cum
->gp_reg_found
= 1;
3636 /* Advance the argument to the next argument position. */
3639 function_arg_advance (cum
, mode
, type
, named
)
3640 CUMULATIVE_ARGS
*cum
; /* current arg information */
3641 enum machine_mode mode
; /* current arg mode */
3642 tree type
; /* type of the argument or 0 if lib support */
3643 int named
; /* whether or not the argument was named */
3645 if (TARGET_DEBUG_E_MODE
)
3648 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3649 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
,
3650 GET_MODE_NAME (mode
));
3651 fprintf (stderr
, HOST_PTR_PRINTF
, type
);
3652 fprintf (stderr
, ", %d )\n\n", named
);
3662 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3663 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3666 cum
->gp_reg_found
= 1;
3667 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3672 cum
->gp_reg_found
= 1;
3673 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3678 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3679 cum
->fp_arg_words
++;
3682 if (! cum
->gp_reg_found
&& cum
->arg_number
<= 2)
3683 cum
->fp_code
+= 1 << ((cum
->arg_number
- 1) * 2);
3687 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3688 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3690 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3691 if (! cum
->gp_reg_found
&& ! TARGET_SINGLE_FLOAT
&& cum
->arg_number
<= 2)
3692 cum
->fp_code
+= 2 << ((cum
->arg_number
- 1) * 2);
3696 cum
->gp_reg_found
= 1;
3697 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3703 cum
->gp_reg_found
= 1;
3709 /* Return an RTL expression containing the register for the given mode,
3710 or 0 if the argument is to be passed on the stack. */
3713 function_arg (cum
, mode
, type
, named
)
3714 CUMULATIVE_ARGS
*cum
; /* current arg information */
3715 enum machine_mode mode
; /* current arg mode */
3716 tree type
; /* type of the argument or 0 if lib support */
3717 int named
; /* != 0 for normal args, == 0 for ... args */
3722 int *arg_words
= &cum
->arg_words
;
3723 int struct_p
= (type
!= 0
3724 && (TREE_CODE (type
) == RECORD_TYPE
3725 || TREE_CODE (type
) == UNION_TYPE
3726 || TREE_CODE (type
) == QUAL_UNION_TYPE
));
3728 if (TARGET_DEBUG_E_MODE
)
3731 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3732 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
,
3733 GET_MODE_NAME (mode
));
3734 fprintf (stderr
, HOST_PTR_PRINTF
, type
);
3735 fprintf (stderr
, ", %d ) = ", named
);
3739 cum
->last_arg_fp
= 0;
3743 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
3745 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3746 regbase
= GP_ARG_FIRST
;
3749 regbase
= FP_ARG_FIRST
;
3751 /* If the first arg was a float in a floating point register,
3752 then set bias to align this float arg properly. */
3753 if (cum
->arg_words
== 1)
3757 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3760 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3761 cum
->last_arg_fp
= 1;
3762 arg_words
= &cum
->fp_arg_words
;
3763 regbase
= FP_ARG_FIRST
;
3766 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3772 if (mips_abi
== ABI_EABI
3773 && ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3774 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3776 cum
->arg_words
+= cum
->arg_words
& 1;
3779 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
3780 regbase
= ((cum
->gp_reg_found
3781 || TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
3782 || cum
->arg_number
>= 2)
3783 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3784 else if (mips_abi
== ABI_EABI
3785 && ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3787 cum
->last_arg_fp
= 1;
3788 arg_words
= &cum
->fp_arg_words
;
3789 regbase
= FP_ARG_FIRST
;
3792 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3793 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3797 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3798 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3801 /* Drops through. */
3803 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
3804 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3805 cum
->arg_words
+= (cum
->arg_words
& 1);
3806 regbase
= GP_ARG_FIRST
;
3813 regbase
= GP_ARG_FIRST
;
3818 cum
->arg_words
+= (cum
->arg_words
& 1);
3819 regbase
= GP_ARG_FIRST
;
3822 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3824 if (TARGET_DEBUG_E_MODE
)
3825 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3834 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3835 || mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
|| ! named
)
3836 ret
= gen_rtx_REG (mode
, regbase
+ *arg_words
+ bias
);
3839 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3840 structure contains a double in its entirety, then that 64 bit
3841 chunk is passed in a floating point register. */
3844 /* First check to see if there is any such field. */
3845 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3846 if (TREE_CODE (field
) == FIELD_DECL
3847 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3848 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3849 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3850 % BITS_PER_WORD
== 0))
3853 /* If the whole struct fits a DFmode register,
3854 we don't need the PARALLEL. */
3855 if (! field
|| mode
== DFmode
)
3856 ret
= gen_rtx_REG (mode
, regbase
+ *arg_words
+ bias
);
3859 /* Now handle the special case by returning a PARALLEL
3860 indicating where each 64 bit chunk goes. */
3866 /* ??? If this is a packed structure, then the last hunk won't
3869 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3870 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3871 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3873 /* assign_parms checks the mode of ENTRY_PARM, so we must
3874 use the actual mode here. */
3875 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (chunks
));
3878 regno
= regbase
+ *arg_words
+ bias
;
3879 field
= TYPE_FIELDS (type
);
3880 for (i
= 0; i
< chunks
; i
++)
3884 for (; field
; field
= TREE_CHAIN (field
))
3885 if (TREE_CODE (field
) == FIELD_DECL
3886 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3891 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3892 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3893 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3894 reg
= gen_rtx_REG (DFmode
,
3895 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3897 reg
= gen_rtx_REG (word_mode
, regno
);
3900 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
3901 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3909 if (TARGET_DEBUG_E_MODE
)
3910 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3911 struct_p
? ", [struct]" : "");
3913 /* The following is a hack in order to pass 1 byte structures
3914 the same way that the MIPS compiler does (namely by passing
3915 the structure in the high byte or half word of the register).
3916 This also makes varargs work. If we have such a structure,
3917 we save the adjustment RTL, and the call define expands will
3918 emit them. For the VOIDmode argument (argument after the
3919 last real argument), pass back a parallel vector holding each
3920 of the adjustments. */
3922 /* ??? function_arg can be called more than once for each argument.
3923 As a result, we compute more adjustments than we need here.
3924 See the CUMULATIVE_ARGS definition in mips.h. */
3926 /* ??? This scheme requires everything smaller than the word size to
3927 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3928 that would mean every int needs to be shifted left, which is very
3929 inefficient. Let's not carry this compatibility to the 64 bit
3930 calling convention for now. */
3932 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3933 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3935 rtx amount
= GEN_INT (BITS_PER_WORD
3936 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3937 rtx reg
= gen_rtx_REG (word_mode
, regbase
+ *arg_words
+ bias
);
3940 cum
->adjust
[cum
->num_adjusts
++] = gen_ashldi3 (reg
, reg
, amount
);
3942 cum
->adjust
[cum
->num_adjusts
++] = gen_ashlsi3 (reg
, reg
, amount
);
3946 /* We will be called with a mode of VOIDmode after the last argument
3947 has been seen. Whatever we return will be passed to the call
3948 insn. If we need any shifts for small structures, return them in
3949 a PARALLEL; in that case, stuff the mips16 fp_code in as the
3950 mode. Otherwise, if we have need a mips16 fp_code, return a REG
3951 with the code stored as the mode. */
3952 if (mode
== VOIDmode
)
3954 if (cum
->num_adjusts
> 0)
3955 ret
= gen_rtx (PARALLEL
, (enum machine_mode
) cum
->fp_code
,
3956 gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3957 else if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
3958 ret
= gen_rtx (REG
, (enum machine_mode
) cum
->fp_code
, 0);
3965 function_arg_partial_nregs (cum
, mode
, type
, named
)
3966 CUMULATIVE_ARGS
*cum
; /* current arg information */
3967 enum machine_mode mode
; /* current arg mode */
3968 tree type
; /* type of the argument or 0 if lib support */
3969 int named ATTRIBUTE_UNUSED
;/* != 0 for normal args, == 0 for ... args */
3971 if ((mode
== BLKmode
3972 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3973 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3974 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3975 && mips_abi
!= ABI_EABI
)
3978 if (mode
== BLKmode
)
3979 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3982 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3984 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3985 return 0; /* structure fits in registers */
3987 if (TARGET_DEBUG_E_MODE
)
3988 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3989 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3991 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3994 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3995 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3997 if (TARGET_DEBUG_E_MODE
)
3998 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
4006 /* Create the va_list data type. */
4009 mips_build_va_list ()
4011 if (mips_abi
== ABI_EABI
&& !TARGET_SOFT_FLOAT
&& !TARGET_SINGLE_FLOAT
)
4013 tree f_fpr
, f_rem
, f_gpr
, record
;
4015 record
= make_node (RECORD_TYPE
);
4017 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("__fp_regs"),
4019 f_rem
= build_decl (FIELD_DECL
, get_identifier ("__fp_left"),
4021 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("__gp_regs"),
4024 DECL_FIELD_CONTEXT (f_fpr
) = record
;
4025 DECL_FIELD_CONTEXT (f_rem
) = record
;
4026 DECL_FIELD_CONTEXT (f_gpr
) = record
;
4028 TYPE_FIELDS (record
) = f_fpr
;
4029 TREE_CHAIN (f_fpr
) = f_rem
;
4030 TREE_CHAIN (f_rem
) = f_gpr
;
4032 layout_type (record
);
4037 return ptr_type_node
;
4040 /* Implement va_start. */
4043 mips_va_start (stdarg_p
, valist
, nextarg
)
4051 arg_words
= current_function_args_info
.arg_words
;
4053 if (mips_abi
== ABI_EABI
)
4055 if (!TARGET_SOFT_FLOAT
&& !TARGET_SINGLE_FLOAT
)
4057 tree f_fpr
, f_rem
, f_gpr
, fpr
, rem
, gpr
;
4061 fpro
= (8 - current_function_args_info
.fp_arg_words
);
4066 f_fpr
= TYPE_FIELDS (va_list_type_node
);
4067 f_rem
= TREE_CHAIN (f_fpr
);
4068 f_gpr
= TREE_CHAIN (f_rem
);
4070 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
);
4071 rem
= build (COMPONENT_REF
, TREE_TYPE (f_rem
), valist
, f_rem
);
4072 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
);
4075 gpro
= (8 - arg_words
) * UNITS_PER_WORD
;
4077 gpro
= (stdarg_p
? 0 : UNITS_PER_WORD
);
4079 gprv
= make_tree (ptr_type_node
, nextarg
);
4082 gprv
= build (PLUS_EXPR
, ptr_type_node
, gprv
,
4083 build_int_2 (-gpro
, -1));
4086 t
= build (MODIFY_EXPR
, ptr_type_node
, gpr
, gprv
);
4087 TREE_SIDE_EFFECTS (t
) = 1;
4088 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4090 t
= build (MODIFY_EXPR
, integer_type_node
, rem
,
4091 build_int_2 (fpro
, 0));
4092 TREE_SIDE_EFFECTS (t
) = 1;
4093 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4098 fprv
= fold (build (PLUS_EXPR
, ptr_type_node
, gprv
,
4099 build_int_2 (-(fpro
*8), -1)));
4102 fprv
= fold (build (BIT_AND_EXPR
, ptr_type_node
, fprv
,
4103 build_int_2 (-8, -1)));
4105 t
= build (MODIFY_EXPR
, ptr_type_node
, fpr
, fprv
);
4106 TREE_SIDE_EFFECTS (t
) = 1;
4107 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4114 ofs
= (stdarg_p
? 0 : UNITS_PER_WORD
);
4116 ofs
= (8 - arg_words
) * UNITS_PER_WORD
;
4118 nextarg
= plus_constant (nextarg
, -ofs
);
4119 std_expand_builtin_va_start (1, valist
, nextarg
);
4130 /* ??? This had been conditional on
4131 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4132 and both iris5.h and iris6.h define _MIPS_SIM. */
4133 if (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
)
4134 ofs
= (arg_words
>= 8 ? -UNITS_PER_WORD
: 0);
4136 ofs
= -UNITS_PER_WORD
;
4139 nextarg
= plus_constant (nextarg
, ofs
);
4140 std_expand_builtin_va_start (1, valist
, nextarg
);
4144 /* Implement va_arg. */
4147 mips_va_arg (valist
, type
)
4150 HOST_WIDE_INT size
, rsize
;
4154 size
= int_size_in_bytes (type
);
4155 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4157 if (mips_abi
== ABI_EABI
)
4161 rtx lab_over
= NULL_RTX
, lab_false
, r
;
4164 = function_arg_pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4166 size
= rsize
= POINTER_SIZE
/ BITS_PER_UNIT
;
4168 addr_rtx
= gen_reg_rtx (Pmode
);
4170 if (!TARGET_SOFT_FLOAT
&& !TARGET_SINGLE_FLOAT
)
4172 tree f_fpr
, f_rem
, f_gpr
, fpr
, rem
;
4174 f_fpr
= TYPE_FIELDS (va_list_type_node
);
4175 f_rem
= TREE_CHAIN (f_fpr
);
4176 f_gpr
= TREE_CHAIN (f_rem
);
4178 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
);
4179 rem
= build (COMPONENT_REF
, TREE_TYPE (f_rem
), valist
, f_rem
);
4180 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
);
4182 if (TREE_CODE (type
) == REAL_TYPE
)
4184 lab_false
= gen_label_rtx ();
4185 lab_over
= gen_label_rtx ();
4187 r
= expand_expr (rem
, NULL_RTX
, TYPE_MODE (TREE_TYPE (rem
)),
4189 emit_cmp_and_jump_insns (r
, const0_rtx
, LE
, const1_rtx
,
4190 GET_MODE (r
), 1, 1, lab_false
);
4192 t
= build (PLUS_EXPR
, TREE_TYPE (rem
), rem
,
4193 build_int_2 (-1, -1));
4194 t
= build (MODIFY_EXPR
, TREE_TYPE (rem
), rem
, t
);
4195 TREE_SIDE_EFFECTS (t
) = 1;
4196 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4198 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (fpr
), fpr
,
4199 build_int_2 (8, 0));
4200 TREE_SIDE_EFFECTS (t
) = 1;
4201 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4203 emit_move_insn (addr_rtx
, r
);
4205 /* Ensure that the POSTINCREMENT is emitted before lab_over */
4208 emit_jump (lab_over
);
4210 emit_label (lab_false
);
4218 && TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
)
4220 t
= build (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
4221 build_int_2 (2*UNITS_PER_WORD
- 1, 0));
4222 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4223 build_int_2 (-2*UNITS_PER_WORD
, -1));
4224 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
4225 TREE_SIDE_EFFECTS (t
) = 1;
4226 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4229 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (gpr
), gpr
, size_int (rsize
));
4230 TREE_SIDE_EFFECTS (t
) = 1;
4231 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4233 emit_move_insn (addr_rtx
, r
);
4235 /* Ensure that the above POSTINCREMENT is emitted before lab_over */
4239 emit_label (lab_over
);
4243 r
= gen_rtx_MEM (Pmode
, addr_rtx
);
4244 MEM_ALIAS_SET (r
) = get_varargs_alias_set ();
4245 emit_move_insn (addr_rtx
, r
);
4249 if (BYTES_BIG_ENDIAN
&& rsize
!= size
)
4250 addr_rtx
= plus_constant (addr_rtx
, rsize
- size
);
4259 /* ??? The original va-mips.h did always align, despite the fact
4260 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4261 increment mechanism. */
4265 else if (TYPE_ALIGN (type
) > 32)
4270 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4271 build_int_2 (align
- 1, 0));
4272 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, build_int_2 (-align
, -1));
4273 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4274 TREE_SIDE_EFFECTS (t
) = 1;
4275 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4277 /* Everything past the alignment is standard. */
4278 return std_expand_builtin_va_arg (valist
, type
);
4282 /* Abort after printing out a specific insn. */
4285 abort_with_insn (insn
, reason
)
4294 /* Set up the threshold for data to go into the small data area, instead
4295 of the normal data area, and detect any conflicts in the switches. */
4300 register int i
, start
;
4302 register enum machine_mode mode
;
4304 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
4306 if (mips_section_threshold
<= 0)
4307 target_flags
&= ~MASK_GPOPT
;
4309 target_flags
|= MASK_GPOPT
;
4311 /* If both single-float and soft-float are set, then clear the one that
4312 was set by TARGET_DEFAULT, leaving the one that was set by the
4313 user. We assume here that the specs prevent both being set by the
4315 #ifdef TARGET_DEFAULT
4316 if (TARGET_SINGLE_FLOAT
&& TARGET_SOFT_FLOAT
)
4317 target_flags
&= ~(TARGET_DEFAULT
&(MASK_SOFT_FLOAT
|MASK_SINGLE_FLOAT
));
4320 /* Get the architectural level. */
4321 if (mips_isa_string
== 0)
4322 mips_isa
= MIPS_ISA_DEFAULT
;
4324 else if (ISDIGIT (*mips_isa_string
))
4326 mips_isa
= atoi (mips_isa_string
);
4329 /* -mno-mips16 overrides -mips16. */
4330 if (mips_no_mips16_string
== NULL
)
4332 target_flags
|= MASK_MIPS16
;
4336 mips_isa
= MIPS_ISA_DEFAULT
;
4340 mips_isa
= MIPS_ISA_DEFAULT
;
4343 else if (mips_isa
< 1 || mips_isa
> 4)
4345 error ("-mips%d not supported", mips_isa
);
4352 error ("bad value (%s) for -mips switch", mips_isa_string
);
4356 #ifdef MIPS_ABI_DEFAULT
4357 /* Get the ABI to use. */
4358 if (mips_abi_string
== (char *) 0)
4359 mips_abi
= MIPS_ABI_DEFAULT
;
4360 else if (! strcmp (mips_abi_string
, "32"))
4362 else if (! strcmp (mips_abi_string
, "o64"))
4364 else if (! strcmp (mips_abi_string
, "n32"))
4366 else if (! strcmp (mips_abi_string
, "64"))
4368 else if (! strcmp (mips_abi_string
, "eabi"))
4369 mips_abi
= ABI_EABI
;
4371 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
4373 /* A specified ISA defaults the ABI if it was not specified. */
4374 if (mips_abi_string
== 0 && mips_isa_string
4375 && mips_abi
!= ABI_EABI
&& mips_abi
!= ABI_O64
)
4377 if (! ISA_HAS_64BIT_REGS
)
4383 /* A specified ABI defaults the ISA if it was not specified. */
4384 else if (mips_isa_string
== 0 && mips_abi_string
4385 && mips_abi
!= ABI_EABI
&& mips_abi
!= ABI_O64
)
4387 if (mips_abi
== ABI_32
)
4389 else if (mips_abi
== ABI_N32
)
4395 /* If both ABI and ISA were specified, check for conflicts. */
4396 else if (mips_isa_string
&& mips_abi_string
)
4398 if ((! ISA_HAS_64BIT_REGS
&& (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
4399 || mips_abi
== ABI_O64
))
4400 || (ISA_HAS_64BIT_REGS
&& mips_abi
== ABI_32
))
4401 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
4404 /* Override TARGET_DEFAULT if necessary. */
4405 if (mips_abi
== ABI_32
)
4406 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
4408 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4409 then set the type sizes. In the EABI in 64 bit mode, longs and
4410 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4411 if (mips_explicit_type_size_string
== NULL
4412 && ((mips_abi
== ABI_EABI
&& TARGET_64BIT
)
4413 || mips_abi
== ABI_64
))
4414 target_flags
|= MASK_LONG64
;
4416 /* ??? This doesn't work yet, so don't let people try to use it. */
4417 if (mips_abi
== ABI_32
)
4418 error ("The -mabi=32 support does not work yet.");
4421 if (mips_abi_string
)
4422 error ("This target does not support the -mabi switch.");
4425 #ifdef MIPS_CPU_STRING_DEFAULT
4426 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4427 greater than that supported by the default processor, then the user gets
4428 an error. Normally, the compiler will just default to the base level cpu
4429 for the indicated isa. */
4430 if (mips_cpu_string
== 0)
4431 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
4434 /* Identify the processor type */
4435 if (mips_cpu_string
== 0
4436 || !strcmp (mips_cpu_string
, "default")
4437 || !strcmp (mips_cpu_string
, "DEFAULT"))
4442 mips_cpu_string
= "3000";
4443 mips_cpu
= PROCESSOR_R3000
;
4446 mips_cpu_string
= "6000";
4447 mips_cpu
= PROCESSOR_R6000
;
4450 mips_cpu_string
= "4000";
4451 mips_cpu
= PROCESSOR_R4000
;
4454 mips_cpu_string
= "8000";
4455 mips_cpu
= PROCESSOR_R8000
;
4462 const char *p
= mips_cpu_string
;
4465 /* We need to cope with the various "vr" prefixes for the NEC 4300
4466 and 4100 processors. */
4467 if (*p
== 'v' || *p
== 'V')
4470 if (*p
== 'r' || *p
== 'R')
4473 /* Since there is no difference between a R2000 and R3000 in
4474 terms of the scheduler, we collapse them into just an R3000. */
4476 mips_cpu
= PROCESSOR_DEFAULT
;
4480 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
4481 mips_cpu
= PROCESSOR_R3000
;
4485 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
4486 mips_cpu
= PROCESSOR_R3000
;
4487 else if (!strcmp (p
, "3900"))
4488 mips_cpu
= PROCESSOR_R3900
;
4492 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
4493 mips_cpu
= PROCESSOR_R4000
;
4494 /* The vr4100 is a non-FP ISA III processor with some extra
4496 else if (!strcmp (p
, "4100"))
4498 mips_cpu
= PROCESSOR_R4100
;
4499 target_flags
|= MASK_SOFT_FLOAT
;
4501 /* The vr4300 is a standard ISA III processor, but with a different
4503 else if (!strcmp (p
, "4300"))
4504 mips_cpu
= PROCESSOR_R4300
;
4505 /* The r4400 is exactly the same as the r4000 from the compiler's
4507 else if (!strcmp (p
, "4400"))
4508 mips_cpu
= PROCESSOR_R4000
;
4509 else if (!strcmp (p
, "4600"))
4510 mips_cpu
= PROCESSOR_R4600
;
4511 else if (!strcmp (p
, "4650"))
4512 mips_cpu
= PROCESSOR_R4650
;
4516 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
4517 mips_cpu
= PROCESSOR_R5000
;
4521 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
4522 mips_cpu
= PROCESSOR_R6000
;
4526 if (!strcmp (p
, "8000"))
4527 mips_cpu
= PROCESSOR_R8000
;
4531 if (!strcmp (p
, "orion"))
4532 mips_cpu
= PROCESSOR_R4600
;
4537 && mips_cpu
!= PROCESSOR_R4300
4538 && mips_cpu
!= PROCESSOR_R4100
4539 && mips_cpu
!= PROCESSOR_R5000
)
4540 mips_cpu
= PROCESSOR_DEFAULT
;
4542 if (mips_cpu
== PROCESSOR_DEFAULT
)
4544 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
4545 mips_cpu_string
= "default";
4549 if ((mips_cpu
== PROCESSOR_R3000
&& (mips_isa
!= 1))
4550 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
!= 1 && mips_isa
!= 2)
4551 || ((mips_cpu
== PROCESSOR_R4000
4552 || mips_cpu
== PROCESSOR_R4100
4553 || mips_cpu
== PROCESSOR_R4300
4554 || mips_cpu
== PROCESSOR_R4600
4555 || mips_cpu
== PROCESSOR_R4650
)
4556 && mips_isa
!= 1 && mips_isa
!= 2 && mips_isa
!= 3))
4557 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
4559 /* make sure sizes of ints/longs/etc. are ok */
4560 if (! ISA_HAS_64BIT_REGS
)
4563 fatal ("-mips%d does not support 64 bit fp registers", mips_isa
);
4565 else if (TARGET_64BIT
)
4566 fatal ("-mips%d does not support 64 bit gp registers", mips_isa
);
4569 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
4570 flag_pcc_struct_return
= 0;
4572 /* Tell halfpic.c that we have half-pic code if we do. */
4573 if (TARGET_HALF_PIC
)
4576 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4577 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4578 /* ??? -non_shared turns off pic code generation, but this is not
4580 if (TARGET_ABICALLS
)
4582 mips_abicalls
= MIPS_ABICALLS_YES
;
4584 if (mips_section_threshold
> 0)
4585 warning ("-G is incompatible with PIC code which is the default");
4588 mips_abicalls
= MIPS_ABICALLS_NO
;
4590 /* -membedded-pic is a form of PIC code suitable for embedded
4591 systems. All calls are made using PC relative addressing, and
4592 all data is addressed using the $gp register. This requires gas,
4593 which does most of the work, and GNU ld, which automatically
4594 expands PC relative calls which are out of range into a longer
4595 instruction sequence. All gcc really does differently is
4596 generate a different sequence for a switch. */
4597 if (TARGET_EMBEDDED_PIC
)
4600 if (TARGET_ABICALLS
)
4601 warning ("-membedded-pic and -mabicalls are incompatible");
4604 warning ("-G and -membedded-pic are incompatible");
4606 /* Setting mips_section_threshold is not required, because gas
4607 will force everything to be GP addressable anyhow, but
4608 setting it will cause gcc to make better estimates of the
4609 number of instructions required to access a particular data
4611 mips_section_threshold
= 0x7fffffff;
4614 /* This optimization requires a linker that can support a R_MIPS_LO16
4615 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
4616 GNU ld has this support, but not all other MIPS linkers do, so we enable
4617 this optimization only if the user requests it, or if GNU ld is the
4618 standard linker for this configuration. */
4619 /* ??? This does not work when target addresses are DImode.
4620 This is because we are missing DImode high/lo_sum patterns. */
4621 if (TARGET_GAS
&& ! TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
4623 mips_split_addresses
= 1;
4625 mips_split_addresses
= 0;
4627 /* -mrnames says to use the MIPS software convention for register
4628 names instead of the hardware names (ie, $a0 instead of $4).
4629 We do this by switching the names in mips_reg_names, which the
4630 reg_names points into via the REGISTER_NAMES macro. */
4632 if (TARGET_NAME_REGS
)
4633 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
,
4634 sizeof (mips_reg_names
));
4636 /* When compiling for the mips16, we can not use floating point. We
4637 record the original hard float value in mips16_hard_float. */
4640 if (TARGET_SOFT_FLOAT
)
4641 mips16_hard_float
= 0;
4643 mips16_hard_float
= 1;
4644 target_flags
|= MASK_SOFT_FLOAT
;
4646 /* Don't run the scheduler before reload, since it tends to
4647 increase register pressure. */
4648 flag_schedule_insns
= 0;
4651 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
4652 to avoid using up another bit in target_flags. */
4653 if (mips_entry_string
!= NULL
)
4655 if (*mips_entry_string
!= '\0')
4656 error ("Invalid option `entry%s'", mips_entry_string
);
4658 if (! TARGET_MIPS16
)
4659 warning ("-mentry is only meaningful with -mips-16");
4664 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
4665 attributes can access it. */
4671 /* Initialize the high and low values for legitimate floating point
4672 constants. Rather than trying to get the accuracy down to the
4673 last bit, just use approximate ranges. */
4674 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
4675 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
4676 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
4677 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
4679 mips_print_operand_punct
['?'] = 1;
4680 mips_print_operand_punct
['#'] = 1;
4681 mips_print_operand_punct
['&'] = 1;
4682 mips_print_operand_punct
['!'] = 1;
4683 mips_print_operand_punct
['*'] = 1;
4684 mips_print_operand_punct
['@'] = 1;
4685 mips_print_operand_punct
['.'] = 1;
4686 mips_print_operand_punct
['('] = 1;
4687 mips_print_operand_punct
[')'] = 1;
4688 mips_print_operand_punct
['['] = 1;
4689 mips_print_operand_punct
[']'] = 1;
4690 mips_print_operand_punct
['<'] = 1;
4691 mips_print_operand_punct
['>'] = 1;
4692 mips_print_operand_punct
['{'] = 1;
4693 mips_print_operand_punct
['}'] = 1;
4694 mips_print_operand_punct
['^'] = 1;
4695 mips_print_operand_punct
['$'] = 1;
4696 mips_print_operand_punct
['+'] = 1;
4697 mips_print_operand_punct
['~'] = 1;
4699 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
4700 mips_char_to_class
['e'] = M16_NA_REGS
;
4701 mips_char_to_class
['t'] = T_REG
;
4702 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
4703 mips_char_to_class
['h'] = HI_REG
;
4704 mips_char_to_class
['l'] = LO_REG
;
4705 mips_char_to_class
['a'] = HILO_REG
;
4706 mips_char_to_class
['x'] = MD_REGS
;
4707 mips_char_to_class
['b'] = ALL_REGS
;
4708 mips_char_to_class
['y'] = GR_REGS
;
4709 mips_char_to_class
['z'] = ST_REGS
;
4711 /* Set up array to map GCC register number to debug register number.
4712 Ignore the special purpose register numbers. */
4714 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4715 mips_dbx_regno
[i
] = -1;
4717 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
4718 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
4719 mips_dbx_regno
[i
] = i
+ start
;
4721 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
4722 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
4723 mips_dbx_regno
[i
] = i
+ start
;
4725 /* Set up array giving whether a given register can hold a given mode.
4726 At present, restrict ints from being in FP registers, because reload
4727 is a little enthusiastic about storing extra values in FP registers,
4728 and this is not good for things like OS kernels. Also, due to the
4729 mandatory delay, it is as fast to load from cached memory as to move
4730 from the FP register. */
4732 for (mode
= VOIDmode
;
4733 mode
!= MAX_MACHINE_MODE
;
4734 mode
= (enum machine_mode
) ((int)mode
+ 1))
4736 register int size
= GET_MODE_SIZE (mode
);
4737 register enum mode_class
class = GET_MODE_CLASS (mode
);
4739 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4746 temp
= (regno
== FPSW_REGNUM
);
4748 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
4749 || FP_REG_P (regno
));
4752 else if (GP_REG_P (regno
))
4753 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
4755 else if (FP_REG_P (regno
))
4756 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
4757 && (class == MODE_FLOAT
4758 || class == MODE_COMPLEX_FLOAT
4759 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
4760 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
4762 else if (MD_REG_P (regno
))
4763 temp
= (class == MODE_INT
4764 && (size
<= UNITS_PER_WORD
4765 || (regno
== MD_REG_FIRST
4766 && size
== 2 * UNITS_PER_WORD
)));
4771 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
4775 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4776 initialized yet, so we can't use that here. */
4777 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
4779 /* Provide default values for align_* for 64-bit targets. */
4780 if (TARGET_64BIT
&& !TARGET_MIPS16
)
4782 if (align_loops
== 0)
4784 if (align_jumps
== 0)
4786 if (align_functions
== 0)
4787 align_functions
= 8;
4790 /* Register global variables with the garbage collector. */
4791 mips_add_gc_roots ();
4794 /* On the mips16, we want to allocate $24 (T_REG) before other
4795 registers for instructions for which it is possible. This helps
4796 avoid shuffling registers around in order to set up for an xor,
4797 encouraging the compiler to use a cmp instead. */
4800 mips_order_regs_for_local_alloc ()
4804 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4805 reg_alloc_order
[i
] = i
;
4809 /* It really doesn't matter where we put register 0, since it is
4810 a fixed register anyhow. */
4811 reg_alloc_order
[0] = 24;
4812 reg_alloc_order
[24] = 0;
4817 /* The MIPS debug format wants all automatic variables and arguments
4818 to be in terms of the virtual frame pointer (stack pointer before
4819 any adjustment in the function), while the MIPS 3.0 linker wants
4820 the frame pointer to be the stack pointer after the initial
4821 adjustment. So, we do the adjustment here. The arg pointer (which
4822 is eliminated) points to the virtual frame pointer, while the frame
4823 pointer (which may be eliminated) points to the stack pointer after
4824 the initial adjustments. */
4827 mips_debugger_offset (addr
, offset
)
4829 HOST_WIDE_INT offset
;
4831 rtx offset2
= const0_rtx
;
4832 rtx reg
= eliminate_constant_term (addr
, &offset2
);
4835 offset
= INTVAL (offset2
);
4837 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
4838 || reg
== hard_frame_pointer_rtx
)
4840 HOST_WIDE_INT frame_size
= (!current_frame_info
.initialized
)
4841 ? compute_frame_size (get_frame_size ())
4842 : current_frame_info
.total_size
;
4844 /* MIPS16 frame is smaller */
4845 if (frame_pointer_needed
&& TARGET_MIPS16
)
4846 frame_size
-= current_function_outgoing_args_size
;
4848 offset
= offset
- frame_size
;
4851 /* sdbout_parms does not want this to crash for unrecognized cases. */
4853 else if (reg
!= arg_pointer_rtx
)
4854 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
4860 /* A C compound statement to output to stdio stream STREAM the
4861 assembler syntax for an instruction operand X. X is an RTL
4864 CODE is a value that can be used to specify one of several ways
4865 of printing the operand. It is used when identical operands
4866 must be printed differently depending on the context. CODE
4867 comes from the `%' specification that was used to request
4868 printing of the operand. If the specification was just `%DIGIT'
4869 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4870 is the ASCII code for LTR.
4872 If X is a register, this macro should print the register's name.
4873 The names can be found in an array `reg_names' whose type is
4874 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4876 When the machine description has a specification `%PUNCT' (a `%'
4877 followed by a punctuation character), this macro is called with
4878 a null pointer for X and the punctuation character for CODE.
4880 The MIPS specific codes are:
4882 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4883 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4884 'd' output integer constant in decimal,
4885 'z' if the operand is 0, use $0 instead of normal operand.
4886 'D' print second register of double-word register operand.
4887 'L' print low-order register of double-word register operand.
4888 'M' print high-order register of double-word register operand.
4889 'C' print part of opcode for a branch condition.
4890 'F' print part of opcode for a floating-point branch condition.
4891 'N' print part of opcode for a branch condition, inverted.
4892 'W' print part of opcode for a floating-point branch condition, inverted.
4893 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
4894 'B' print 'z' for EQ, 'n' for NE
4895 'b' print 'n' for EQ, 'z' for NE
4896 'T' print 'f' for EQ, 't' for NE
4897 't' print 't' for EQ, 'f' for NE
4898 'Z' print register and a comma, but print nothing for $fcc0
4899 '(' Turn on .set noreorder
4900 ')' Turn on .set reorder
4901 '[' Turn on .set noat
4903 '<' Turn on .set nomacro
4904 '>' Turn on .set macro
4905 '{' Turn on .set volatile (not GAS)
4906 '}' Turn on .set novolatile (not GAS)
4907 '&' Turn on .set noreorder if filling delay slots
4908 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4909 '!' Turn on .set nomacro if filling delay slots
4910 '#' Print nop if in a .set noreorder section.
4911 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4912 '@' Print the name of the assembler temporary register (at or $1).
4913 '.' Print the name of the register with a hard-wired zero (zero or $0).
4914 '^' Print the name of the pic call-through register (t9 or $25).
4915 '$' Print the name of the stack pointer register (sp or $29).
4916 '+' Print the name of the gp register (gp or $28).
4917 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
4920 print_operand (file
, op
, letter
)
4921 FILE *file
; /* file to write to */
4922 rtx op
; /* operand to print */
4923 int letter
; /* %<letter> or 0 */
4925 register enum rtx_code code
;
4927 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
4932 if (mips_branch_likely
)
4937 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
4941 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
4945 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
4949 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
4953 fputs (reg_names
[GP_REG_FIRST
+ 28], file
);
4957 if (final_sequence
!= 0 && set_noreorder
++ == 0)
4958 fputs (".set\tnoreorder\n\t", file
);
4962 if (final_sequence
!= 0)
4964 if (set_noreorder
++ == 0)
4965 fputs (".set\tnoreorder\n\t", file
);
4967 if (set_nomacro
++ == 0)
4968 fputs (".set\tnomacro\n\t", file
);
4973 if (final_sequence
!= 0 && set_nomacro
++ == 0)
4974 fputs ("\n\t.set\tnomacro", file
);
4978 if (set_noreorder
!= 0)
4979 fputs ("\n\tnop", file
);
4980 else if (TARGET_STATS
)
4981 fputs ("\n\t#nop", file
);
4986 if (set_noreorder
++ == 0)
4987 fputs (".set\tnoreorder\n\t", file
);
4991 if (set_noreorder
== 0)
4992 error ("internal error: %%) found without a %%( in assembler pattern");
4994 else if (--set_noreorder
== 0)
4995 fputs ("\n\t.set\treorder", file
);
5000 if (set_noat
++ == 0)
5001 fputs (".set\tnoat\n\t", file
);
5006 error ("internal error: %%] found without a %%[ in assembler pattern");
5007 else if (--set_noat
== 0)
5008 fputs ("\n\t.set\tat", file
);
5013 if (set_nomacro
++ == 0)
5014 fputs (".set\tnomacro\n\t", file
);
5018 if (set_nomacro
== 0)
5019 error ("internal error: %%> found without a %%< in assembler pattern");
5020 else if (--set_nomacro
== 0)
5021 fputs ("\n\t.set\tmacro", file
);
5026 if (set_volatile
++ == 0)
5027 fprintf (file
, "%s.set\tvolatile\n\t", TARGET_MIPS_AS
? "" : "#");
5031 if (set_volatile
== 0)
5032 error ("internal error: %%} found without a %%{ in assembler pattern");
5033 else if (--set_volatile
== 0)
5034 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
5040 if (align_labels_log
> 0)
5041 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
5046 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
5055 error ("PRINT_OPERAND null pointer");
5059 code
= GET_CODE (op
);
5061 if (code
== SIGN_EXTEND
)
5062 op
= XEXP (op
, 0), code
= GET_CODE (op
);
5067 case EQ
: fputs ("eq", file
); break;
5068 case NE
: fputs ("ne", file
); break;
5069 case GT
: fputs ("gt", file
); break;
5070 case GE
: fputs ("ge", file
); break;
5071 case LT
: fputs ("lt", file
); break;
5072 case LE
: fputs ("le", file
); break;
5073 case GTU
: fputs ("gtu", file
); break;
5074 case GEU
: fputs ("geu", file
); break;
5075 case LTU
: fputs ("ltu", file
); break;
5076 case LEU
: fputs ("leu", file
); break;
5078 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
5081 else if (letter
== 'N')
5084 case EQ
: fputs ("ne", file
); break;
5085 case NE
: fputs ("eq", file
); break;
5086 case GT
: fputs ("le", file
); break;
5087 case GE
: fputs ("lt", file
); break;
5088 case LT
: fputs ("ge", file
); break;
5089 case LE
: fputs ("gt", file
); break;
5090 case GTU
: fputs ("leu", file
); break;
5091 case GEU
: fputs ("ltu", file
); break;
5092 case LTU
: fputs ("geu", file
); break;
5093 case LEU
: fputs ("gtu", file
); break;
5095 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
5098 else if (letter
== 'F')
5101 case EQ
: fputs ("c1f", file
); break;
5102 case NE
: fputs ("c1t", file
); break;
5104 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%F");
5107 else if (letter
== 'W')
5110 case EQ
: fputs ("c1t", file
); break;
5111 case NE
: fputs ("c1f", file
); break;
5113 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%W");
5116 else if (letter
== 'S')
5120 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
5121 assemble_name (file
, buffer
);
5124 else if (letter
== 'Z')
5126 register int regnum
;
5131 regnum
= REGNO (op
);
5132 if (! ST_REG_P (regnum
))
5135 if (regnum
!= ST_REG_FIRST
)
5136 fprintf (file
, "%s,", reg_names
[regnum
]);
5139 else if (code
== REG
|| code
== SUBREG
)
5141 register int regnum
;
5144 regnum
= REGNO (op
);
5146 regnum
= true_regnum (op
);
5148 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
5149 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
5153 fprintf (file
, "%s", reg_names
[regnum
]);
5156 else if (code
== MEM
)
5157 output_address (XEXP (op
, 0));
5159 else if (code
== CONST_DOUBLE
5160 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
5165 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
5166 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
5170 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
5171 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
5173 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
5174 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
5176 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
5177 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
5179 else if (letter
== 'z' && GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
5180 fputs (reg_names
[GP_REG_FIRST
], file
);
5182 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
5183 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
5186 else if (letter
== 'B')
5187 fputs (code
== EQ
? "z" : "n", file
);
5188 else if (letter
== 'b')
5189 fputs (code
== EQ
? "n" : "z", file
);
5190 else if (letter
== 'T')
5191 fputs (code
== EQ
? "f" : "t", file
);
5192 else if (letter
== 't')
5193 fputs (code
== EQ
? "t" : "f", file
);
5195 else if (code
== CONST
&& GET_CODE (XEXP (op
, 0)) == REG
)
5197 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5198 print_operand (file
, XEXP (op
, 0), letter
);
5201 else if (TARGET_MIPS16
&& code
== CONST
&& mips16_gp_offset_p (op
))
5203 fputs ("%gprel(", file
);
5204 mips16_output_gp_offset (file
, op
);
5209 output_addr_const (file
, op
);
5212 /* A C compound statement to output to stdio stream STREAM the
5213 assembler syntax for an instruction operand that is a memory
5214 reference whose address is ADDR. ADDR is an RTL expression.
5216 On some machines, the syntax for a symbolic address depends on
5217 the section that the address refers to. On these machines,
5218 define the macro `ENCODE_SECTION_INFO' to store the information
5219 into the `symbol_ref', and then check for it here. */
5222 print_operand_address (file
, addr
)
5227 error ("PRINT_OPERAND_ADDRESS, null pointer");
5230 switch (GET_CODE (addr
))
5233 if (! TARGET_MIPS16
&& REGNO (addr
) == ARG_POINTER_REGNUM
)
5234 abort_with_insn (addr
, "Arg pointer not eliminated.");
5236 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
5241 register rtx arg0
= XEXP (addr
, 0);
5242 register rtx arg1
= XEXP (addr
, 1);
5244 if (! mips_split_addresses
)
5245 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5247 if (GET_CODE (arg0
) != REG
)
5248 abort_with_insn (addr
,
5249 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5251 fprintf (file
, "%%lo(");
5252 print_operand_address (file
, arg1
);
5253 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
5259 register rtx reg
= 0;
5260 register rtx offset
= 0;
5261 register rtx arg0
= XEXP (addr
, 0);
5262 register rtx arg1
= XEXP (addr
, 1);
5264 if (GET_CODE (arg0
) == REG
)
5268 if (GET_CODE (offset
) == REG
)
5269 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
5272 else if (GET_CODE (arg1
) == REG
)
5273 reg
= arg1
, offset
= arg0
;
5274 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
5276 output_addr_const (file
, addr
);
5280 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
5282 if (! CONSTANT_P (offset
))
5283 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5285 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
5286 abort_with_insn (addr
, "Arg pointer not eliminated.");
5289 && GET_CODE (offset
) == CONST
5290 && mips16_gp_offset_p (offset
))
5292 fputs ("%gprel(", file
);
5293 mips16_output_gp_offset (file
, offset
);
5297 output_addr_const (file
, offset
);
5298 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
5306 output_addr_const (file
, addr
);
5310 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5316 /* If optimizing for the global pointer, keep track of all of the externs, so
5317 that at the end of the file, we can emit the appropriate .extern
5318 declaration for them, before writing out the text section. We assume all
5319 names passed to us are in the permanent obstack, so they will be valid at
5320 the end of the compilation.
5322 If we have -G 0, or the extern size is unknown, or the object is in a user
5323 specified section that is not .sbss/.sdata, don't bother emitting the
5324 .externs. In the case of user specified sections this behaviour is
5325 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5328 mips_output_external (file
, decl
, name
)
5329 FILE *file ATTRIBUTE_UNUSED
;
5333 register struct extern_list
*p
;
5338 && TREE_CODE (decl
) != FUNCTION_DECL
5339 && (len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
5340 && ((section_name
= DECL_SECTION_NAME (decl
)) == NULL
5341 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
5342 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
5344 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
5345 p
->next
= extern_head
;
5351 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5352 if (TREE_CODE (decl
) == FUNCTION_DECL
5353 /* ??? Don't include alloca, since gcc will always expand it
5354 inline. If we don't do this, the C++ library fails to build. */
5355 && strcmp (name
, "alloca")
5356 /* ??? Don't include __builtin_next_arg, because then gcc will not
5357 bootstrap under Irix 5.1. */
5358 && strcmp (name
, "__builtin_next_arg"))
5360 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
5361 p
->next
= extern_head
;
5371 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5373 mips_output_external_libcall (file
, name
)
5377 register struct extern_list
*p
;
5379 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
5380 p
->next
= extern_head
;
5389 /* Compute a string to use as a temporary file name. */
5391 /* On MSDOS, write temp files in current dir
5392 because there's no place else we can expect to use. */
5395 #define P_tmpdir "./"
5400 mips_make_temp_file ()
5403 const char *base
= getenv ("TMPDIR");
5409 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
5413 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
5419 len
= strlen (base
);
5420 /* temp_filename is global, so we must use malloc, not alloca. */
5421 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
5422 strcpy (temp_filename
, base
);
5423 if (len
> 0 && temp_filename
[len
-1] != '/')
5424 temp_filename
[len
++] = '/';
5426 strcpy (temp_filename
+ len
, "ctXXXXXX");
5427 mktemp (temp_filename
);
5429 stream
= fopen (temp_filename
, "w+");
5431 pfatal_with_name (temp_filename
);
5434 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5435 it. Otherwise, we delete it now, so that it will be gone even if the
5436 compiler happens to crash. */
5437 unlink (temp_filename
);
5442 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5443 for .file's that start within a function. If we are smuggling stabs, try to
5444 put out a MIPS ECOFF file and a stab. */
5447 mips_output_filename (stream
, name
)
5451 static int first_time
= 1;
5452 char ltext_label_name
[100];
5458 current_function_file
= name
;
5459 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
5460 /* This tells mips-tfile that stabs will follow. */
5461 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
5462 fprintf (stream
, "\t#@stabs\n");
5465 else if (write_symbols
== DBX_DEBUG
)
5467 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
5468 fprintf (stream
, "%s ", ASM_STABS_OP
);
5469 output_quoted_string (stream
, name
);
5470 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
5473 else if (name
!= current_function_file
5474 && strcmp (name
, current_function_file
) != 0)
5476 if (inside_function
&& !TARGET_GAS
)
5478 if (!file_in_function_warning
)
5480 file_in_function_warning
= 1;
5481 ignore_line_number
= 1;
5482 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5488 current_function_file
= name
;
5489 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
5494 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5495 as well as a .loc, since it is possible that MIPS ECOFF might not be
5496 able to represent the location for inlines that come from a different
5500 mips_output_lineno (stream
, line
)
5504 if (write_symbols
== DBX_DEBUG
)
5507 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5508 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
5509 LOCAL_LABEL_PREFIX
, sym_lineno
);
5514 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
5515 (ignore_line_number
) ? "#" : "",
5516 num_source_filenames
, line
);
5518 LABEL_AFTER_LOC (stream
);
5522 /* If defined, a C statement to be executed just prior to the output of
5523 assembler code for INSN, to modify the extracted operands so they will be
5526 Here the argument OPVEC is the vector containing the operands extracted
5527 from INSN, and NOPERANDS is the number of elements of the vector which
5528 contain meaningful data for this insn. The contents of this vector are
5529 what will be used to convert the insn template into assembler code, so you
5530 can change the assembler output by changing the contents of the vector.
5532 We use it to check if the current insn needs a nop in front of it because
5533 of load delays, and also to update the delay slot statistics. */
5535 /* ??? There is no real need for this function, because it never actually
5536 emits a NOP anymore. */
5539 final_prescan_insn (insn
, opvec
, noperands
)
5541 rtx opvec
[] ATTRIBUTE_UNUSED
;
5542 int noperands ATTRIBUTE_UNUSED
;
5544 if (dslots_number_nops
> 0)
5546 rtx pattern
= PATTERN (insn
);
5547 int length
= get_attr_length (insn
);
5549 /* Do we need to emit a NOP? */
5551 || (mips_load_reg
!= 0 && reg_mentioned_p (mips_load_reg
, pattern
))
5552 || (mips_load_reg2
!= 0 && reg_mentioned_p (mips_load_reg2
, pattern
))
5553 || (mips_load_reg3
!= 0 && reg_mentioned_p (mips_load_reg3
, pattern
))
5554 || (mips_load_reg4
!= 0
5555 && reg_mentioned_p (mips_load_reg4
, pattern
)))
5556 fputs ("\t#nop\n", asm_out_file
);
5559 dslots_load_filled
++;
5561 while (--dslots_number_nops
> 0)
5562 fputs ("\t#nop\n", asm_out_file
);
5571 && (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CALL_INSN
))
5572 dslots_jump_total
++;
5575 /* Output at beginning of assembler file.
5577 If we are optimizing to use the global pointer, create a temporary file to
5578 hold all of the text stuff, and write it out to the end. This is needed
5579 because the MIPS assembler is evidently one pass, and if it hasn't seen the
5580 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
5581 processed, it generates a two instruction sequence. */
5584 mips_asm_file_start (stream
)
5587 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
5589 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5590 inside of a .set noreorder section jumps to a label outside of the .set
5591 noreorder section. Revision 2.20 just set nobopt silently rather than
5594 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
5595 fprintf (stream
, "\t.set\tnobopt\n");
5597 /* Generate the pseudo ops that System V.4 wants. */
5598 #ifndef ABICALLS_ASM_OP
5599 #define ABICALLS_ASM_OP ".abicalls"
5601 if (TARGET_ABICALLS
)
5602 /* ??? but do not want this (or want pic0) if -non-shared? */
5603 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
5606 fprintf (stream
, "\t.set\tmips16\n");
5608 /* Start a section, so that the first .popsection directive is guaranteed
5609 to have a previously defined section to pop back to. */
5610 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
&& mips_abi
!= ABI_EABI
)
5611 fprintf (stream
, "\t.section\t.text\n");
5613 /* This code exists so that we can put all externs before all symbol
5614 references. This is necessary for the MIPS assembler's global pointer
5615 optimizations to work. */
5616 if (TARGET_FILE_SWITCHING
&& ! TARGET_MIPS16
)
5618 asm_out_data_file
= stream
;
5619 asm_out_text_file
= mips_make_temp_file ();
5623 asm_out_data_file
= asm_out_text_file
= stream
;
5625 if (flag_verbose_asm
)
5626 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5628 mips_section_threshold
, mips_cpu_string
, mips_isa
);
5631 /* If we are optimizing the global pointer, emit the text section now and any
5632 small externs which did not have .comm, etc that are needed. Also, give a
5633 warning if the data area is more than 32K and -pic because 3 instructions
5634 are needed to reference the data pointers. */
5637 mips_asm_file_end (file
)
5642 struct extern_list
*p
;
5647 HALF_PIC_FINISH (file
);
5654 for (p
= extern_head
; p
!= 0; p
= p
->next
)
5656 name_tree
= get_identifier (p
->name
);
5658 /* Positively ensure only one .extern for any given symbol. */
5659 if (! TREE_ASM_WRITTEN (name_tree
))
5661 TREE_ASM_WRITTEN (name_tree
) = 1;
5662 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5664 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
5668 fputs ("\t.extern\t", file
);
5669 assemble_name (file
, p
->name
);
5670 fprintf (file
, ", %d\n", p
->size
);
5676 if (TARGET_FILE_SWITCHING
&& ! TARGET_MIPS16
)
5678 fprintf (file
, "\n\t.text\n");
5679 rewind (asm_out_text_file
);
5680 if (ferror (asm_out_text_file
))
5681 fatal_io_error (temp_filename
);
5683 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
5684 if ((int) fwrite (buffer
, 1, len
, file
) != len
)
5685 pfatal_with_name (asm_file_name
);
5688 pfatal_with_name (temp_filename
);
5690 if (fclose (asm_out_text_file
) != 0)
5691 pfatal_with_name (temp_filename
);
5694 unlink (temp_filename
);
5699 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
5700 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
5703 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
5706 const char *init_string
;
5707 const char *final_string
;
5710 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
5711 assemble_name (stream
, name
);
5712 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
5716 tree name_tree
= get_identifier (name
);
5717 TREE_ASM_WRITTEN (name_tree
) = 1;
5721 /* Output a double precision value to the assembler. If both the
5722 host and target are IEEE, emit the values in hex. */
5725 mips_output_double (stream
, value
)
5727 REAL_VALUE_TYPE value
;
5729 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
5731 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
5733 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
5734 value_long
[0], value
, value_long
[1]);
5736 fprintf (stream
, "\t.double\t%.20g\n", value
);
5740 /* Output a single precision value to the assembler. If both the
5741 host and target are IEEE, emit the values in hex. */
5744 mips_output_float (stream
, value
)
5746 REAL_VALUE_TYPE value
;
5748 #ifdef REAL_VALUE_TO_TARGET_SINGLE
5750 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
5752 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
5754 fprintf (stream
, "\t.float\t%.12g\n", value
);
5758 /* Return the bytes needed to compute the frame pointer from the current
5761 Mips stack frames look like:
5763 Before call After call
5764 +-----------------------+ +-----------------------+
5767 | caller's temps. | | caller's temps. |
5769 +-----------------------+ +-----------------------+
5771 | arguments on stack. | | arguments on stack. |
5773 +-----------------------+ +-----------------------+
5774 | 4 words to save | | 4 words to save |
5775 | arguments passed | | arguments passed |
5776 | in registers, even | | in registers, even |
5777 SP->| if not passed. | VFP->| if not passed. |
5778 +-----------------------+ +-----------------------+
5780 | fp register save |
5782 +-----------------------+
5784 | gp register save |
5786 +-----------------------+
5790 +-----------------------+
5792 | alloca allocations |
5794 +-----------------------+
5796 | GP save for V.4 abi |
5798 +-----------------------+
5800 | arguments on stack |
5802 +-----------------------+
5804 | arguments passed |
5805 | in registers, even |
5806 low SP->| if not passed. |
5807 memory +-----------------------+
5812 compute_frame_size (size
)
5813 HOST_WIDE_INT size
; /* # of var. bytes allocated */
5816 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
5817 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
5818 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
5819 HOST_WIDE_INT extra_size
; /* # extra bytes */
5820 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
5821 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
5822 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
5823 long mask
; /* mask of saved gp registers */
5824 long fmask
; /* mask of saved fp registers */
5825 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
5826 long fp_bits
; /* bitmask to use for each fp register */
5832 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
5833 var_size
= MIPS_STACK_ALIGN (size
);
5834 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
5836 /* The MIPS 3.0 linker does not like functions that dynamically
5837 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5838 looks like we are trying to create a second frame pointer to the
5839 function, so allocate some stack space to make it happy. */
5841 if (args_size
== 0 && current_function_calls_alloca
)
5842 args_size
= 4 * UNITS_PER_WORD
;
5844 total_size
= var_size
+ args_size
+ extra_size
;
5846 /* Calculate space needed for gp registers. */
5847 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
5849 /* $18 is a special case on the mips16. It may be used to call
5850 a function which returns a floating point value, but it is
5851 marked in call_used_regs. $31 is also a special case. When
5852 not using -mentry, it will be used to copy a return value
5853 into the floating point registers if the return value is
5855 if (MUST_SAVE_REGISTER (regno
)
5857 && regno
== GP_REG_FIRST
+ 18
5858 && regs_ever_live
[regno
])
5860 && regno
== GP_REG_FIRST
+ 31
5861 && mips16_hard_float
5863 && ! aggregate_value_p (DECL_RESULT (current_function_decl
))
5864 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl
)))
5866 && (! TARGET_SINGLE_FLOAT
5867 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl
)))
5870 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
5871 mask
|= 1L << (regno
- GP_REG_FIRST
);
5873 /* The entry and exit pseudo instructions can not save $17
5874 without also saving $16. */
5876 && regno
== GP_REG_FIRST
+ 17
5877 && ! MUST_SAVE_REGISTER (GP_REG_FIRST
+ 16))
5879 gp_reg_size
+= UNITS_PER_WORD
;
5885 /* Calculate space needed for fp registers. */
5886 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
5897 /* This loop must iterate over the same space as its companion in
5898 save_restore_regs. */
5899 for (regno
= (FP_REG_LAST
- fp_inc
+ 1);
5900 regno
>= FP_REG_FIRST
;
5903 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
5905 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
5906 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
5910 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
5911 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
5913 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
5914 for leaf routines (total_size == extra_size) to save the gp reg.
5915 The gp reg is callee saved in the 64 bit ABI, so all routines must
5916 save the gp reg. This is not a leaf routine if -p, because of the
5918 if (total_size
== extra_size
5919 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
|| mips_abi
== ABI_EABI
)
5921 total_size
= extra_size
= 0;
5922 else if (TARGET_ABICALLS
)
5924 /* Add the context-pointer to the saved registers. */
5925 gp_reg_size
+= UNITS_PER_WORD
;
5926 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
5927 total_size
-= gp_reg_rounded
;
5928 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
5929 total_size
+= gp_reg_rounded
;
5932 /* Add in space reserved on the stack by the callee for storing arguments
5933 passed in registers. */
5934 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
5935 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
5937 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
5938 if (mips_entry
&& total_size
> 0 && total_size
< 32)
5941 /* Save other computed information. */
5942 current_frame_info
.total_size
= total_size
;
5943 current_frame_info
.var_size
= var_size
;
5944 current_frame_info
.args_size
= args_size
;
5945 current_frame_info
.extra_size
= extra_size
;
5946 current_frame_info
.gp_reg_size
= gp_reg_size
;
5947 current_frame_info
.fp_reg_size
= fp_reg_size
;
5948 current_frame_info
.mask
= mask
;
5949 current_frame_info
.fmask
= fmask
;
5950 current_frame_info
.initialized
= reload_completed
;
5951 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
5952 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
5956 unsigned long offset
;
5958 /* When using mips_entry, the registers are always saved at the
5959 top of the stack. */
5961 offset
= (args_size
+ extra_size
+ var_size
5962 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
5964 offset
= total_size
- GET_MODE_SIZE (gpr_mode
);
5966 current_frame_info
.gp_sp_offset
= offset
;
5967 current_frame_info
.gp_save_offset
= offset
- total_size
;
5971 current_frame_info
.gp_sp_offset
= 0;
5972 current_frame_info
.gp_save_offset
= 0;
5977 unsigned long offset
= (args_size
+ extra_size
+ var_size
5978 + gp_reg_rounded
+ fp_reg_size
5979 - fp_inc
* UNITS_PER_FPREG
);
5980 current_frame_info
.fp_sp_offset
= offset
;
5981 current_frame_info
.fp_save_offset
= offset
- total_size
;
5985 current_frame_info
.fp_sp_offset
= 0;
5986 current_frame_info
.fp_save_offset
= 0;
5989 /* Ok, we're done. */
5993 /* Common code to emit the insns (or to write the instructions to a file)
5994 to save/restore registers.
5996 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
5997 is not modified within save_restore_insns. */
5999 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6002 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
6003 int store_p
; /* true if this is prologue */
6004 rtx large_reg
; /* register holding large offset constant or NULL */
6005 long large_offset
; /* large constant offset value */
6006 FILE *file
; /* file to write instructions instead of making RTL */
6008 long mask
= current_frame_info
.mask
;
6009 long fmask
= current_frame_info
.fmask
;
6012 HOST_WIDE_INT base_offset
;
6013 HOST_WIDE_INT gp_offset
;
6014 HOST_WIDE_INT fp_offset
;
6015 HOST_WIDE_INT end_offset
;
6018 if (frame_pointer_needed
6019 && ! BITSET_P (mask
, HARD_FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
6022 if (mask
== 0 && fmask
== 0)
6025 /* Save registers starting from high to low. The debuggers prefer at least
6026 the return register be stored at func+4, and also it allows us not to
6027 need a nop in the epilog if at least one register is reloaded in
6028 addition to return address. */
6030 /* Save GP registers if needed. */
6033 /* Pick which pointer to use as a base register. For small frames, just
6034 use the stack pointer. Otherwise, use a temporary register. Save 2
6035 cycles if the save area is near the end of a large frame, by reusing
6036 the constant created in the prologue/epilogue to adjust the stack
6039 gp_offset
= current_frame_info
.gp_sp_offset
;
6041 = gp_offset
- (current_frame_info
.gp_reg_size
6042 - GET_MODE_SIZE (gpr_mode
));
6044 if (gp_offset
< 0 || end_offset
< 0)
6045 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6046 (long) gp_offset
, (long) end_offset
);
6048 /* If we see a large frame in mips16 mode, we save the registers
6049 before adjusting the stack pointer, and load them afterward. */
6050 else if (TARGET_MIPS16
&& large_offset
> 32767)
6051 base_reg_rtx
= stack_pointer_rtx
, base_offset
= large_offset
;
6053 else if (gp_offset
< 32768)
6054 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6056 else if (large_reg
!= 0
6057 && (unsigned HOST_WIDE_INT
) (large_offset
- gp_offset
) < 32768
6058 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6060 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6061 base_offset
= large_offset
;
6064 if (Pmode
== DImode
)
6065 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6066 stack_pointer_rtx
));
6068 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6069 stack_pointer_rtx
));
6071 RTX_FRAME_RELATED_P (insn
) = 1;
6074 fprintf (file
, "\t%s\t%s,%s,%s\n",
6075 Pmode
== DImode
? "daddu" : "addu",
6076 reg_names
[MIPS_TEMP2_REGNUM
],
6077 reg_names
[REGNO (large_reg
)],
6078 reg_names
[STACK_POINTER_REGNUM
]);
6083 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6084 base_offset
= gp_offset
;
6087 rtx gp_offset_rtx
= GEN_INT (gp_offset
);
6089 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6090 bit, so make sure that we don't emit anything that can be
6092 /* ??? There is no DImode ori immediate pattern, so we can only
6093 do this for 32 bit code. */
6094 if (large_int (gp_offset_rtx
, GET_MODE (gp_offset_rtx
))
6095 && GET_MODE (base_reg_rtx
) == SImode
)
6097 insn
= emit_move_insn (base_reg_rtx
,
6098 GEN_INT (gp_offset
& 0xffff0000));
6100 RTX_FRAME_RELATED_P (insn
) = 1;
6102 = emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
6103 GEN_INT (gp_offset
& 0x0000ffff)));
6105 RTX_FRAME_RELATED_P (insn
) = 1;
6109 insn
= emit_move_insn (base_reg_rtx
, gp_offset_rtx
);
6111 RTX_FRAME_RELATED_P (insn
) = 1;
6114 if (Pmode
== DImode
)
6115 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
,
6116 stack_pointer_rtx
));
6118 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
,
6119 stack_pointer_rtx
));
6121 RTX_FRAME_RELATED_P (insn
) = 1;
6125 fprintf (file
, "\tli\t%s,0x%.08lx\t# ",
6126 reg_names
[MIPS_TEMP2_REGNUM
], (long) base_offset
);
6127 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, base_offset
);
6128 fprintf (file
, "\n\t%s\t%s,%s,%s\n",
6129 Pmode
== DImode
? "daddu" : "addu",
6130 reg_names
[MIPS_TEMP2_REGNUM
],
6131 reg_names
[MIPS_TEMP2_REGNUM
],
6132 reg_names
[STACK_POINTER_REGNUM
]);
6136 /* When we restore the registers in MIPS16 mode, then if we are
6137 using a frame pointer, and this is not a large frame, the
6138 current stack pointer will be offset by
6139 current_function_outgoing_args_size. Doing it this way lets
6140 us avoid offsetting the frame pointer before copying it into
6141 the stack pointer; there is no instruction to set the stack
6142 pointer to the sum of a register and a constant. */
6145 && frame_pointer_needed
6146 && large_offset
<= 32767)
6147 base_offset
+= current_function_outgoing_args_size
;
6149 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
6150 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
6156 = gen_rtx (MEM
, gpr_mode
,
6157 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
6158 GEN_INT (gp_offset
- base_offset
)));
6160 RTX_UNCHANGING_P (mem_rtx
) = 1;
6162 /* The mips16 does not have an instruction to load
6163 $31, so we load $7 instead, and work things out
6165 if (TARGET_MIPS16
&& ! store_p
&& regno
== GP_REG_FIRST
+ 31)
6166 reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 7);
6167 /* The mips16 sometimes needs to save $18. */
6168 else if (TARGET_MIPS16
6169 && regno
!= GP_REG_FIRST
+ 31
6170 && ! M16_REG_P (regno
))
6173 reg_rtx
= gen_rtx (REG
, gpr_mode
, 6);
6176 reg_rtx
= gen_rtx (REG
, gpr_mode
, 3);
6177 emit_move_insn (reg_rtx
,
6178 gen_rtx (REG
, gpr_mode
, regno
));
6182 reg_rtx
= gen_rtx (REG
, gpr_mode
, regno
);
6186 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
6187 RTX_FRAME_RELATED_P (insn
) = 1;
6189 else if (!TARGET_ABICALLS
6190 || (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
6191 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
6193 emit_move_insn (reg_rtx
, mem_rtx
);
6195 && regno
!= GP_REG_FIRST
+ 31
6196 && ! M16_REG_P (regno
))
6197 emit_move_insn (gen_rtx (REG
, gpr_mode
, regno
),
6203 if (store_p
|| !TARGET_ABICALLS
6204 || (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
6205 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
6209 /* The mips16 does not have an instruction to
6210 load $31, so we load $7 instead, and work
6211 things out in the caller. */
6212 if (TARGET_MIPS16
&& ! store_p
&& r
== GP_REG_FIRST
+ 31)
6213 r
= GP_REG_FIRST
+ 7;
6214 /* The mips16 sometimes needs to save $18. */
6216 && regno
!= GP_REG_FIRST
+ 31
6217 && ! M16_REG_P (regno
))
6220 r
= GP_REG_FIRST
+ 6;
6223 r
= GP_REG_FIRST
+ 3;
6224 fprintf (file
, "\tmove\t%s,%s\n",
6225 reg_names
[r
], reg_names
[regno
]);
6228 fprintf (file
, "\t%s\t%s,",
6230 ? (store_p
) ? "sd" : "ld"
6231 : (store_p
) ? "sw" : "lw"),
6233 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6234 gp_offset
- base_offset
);
6235 fprintf (file
, "(%s)\n", reg_names
[REGNO(base_reg_rtx
)]);
6238 && regno
!= GP_REG_FIRST
+ 31
6239 && ! M16_REG_P (regno
))
6240 fprintf (file
, "\tmove\t%s,%s\n",
6241 reg_names
[regno
], reg_names
[r
]);
6245 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
6249 base_reg_rtx
= 0, base_offset
= 0;
6251 /* Save floating point registers if needed. */
6254 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
6255 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
6257 /* Pick which pointer to use as a base register. */
6258 fp_offset
= current_frame_info
.fp_sp_offset
;
6259 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
6261 if (fp_offset
< 0 || end_offset
< 0)
6262 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6263 (long) fp_offset
, (long) end_offset
);
6265 else if (fp_offset
< 32768)
6266 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6268 else if (base_reg_rtx
!= 0
6269 && (unsigned HOST_WIDE_INT
) (base_offset
- fp_offset
) < 32768
6270 && (unsigned HOST_WIDE_INT
) (base_offset
- end_offset
) < 32768)
6271 ; /* already set up for gp registers above */
6273 else if (large_reg
!= 0
6274 && (unsigned HOST_WIDE_INT
) (large_offset
- fp_offset
) < 32768
6275 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6277 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6278 base_offset
= large_offset
;
6281 if (Pmode
== DImode
)
6282 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6283 stack_pointer_rtx
));
6285 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6286 stack_pointer_rtx
));
6288 RTX_FRAME_RELATED_P (insn
) = 1;
6292 fprintf (file
, "\t%s\t%s,%s,%s\n",
6293 Pmode
== DImode
? "daddu" : "addu",
6294 reg_names
[MIPS_TEMP2_REGNUM
],
6295 reg_names
[REGNO (large_reg
)],
6296 reg_names
[STACK_POINTER_REGNUM
]);
6301 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6302 base_offset
= fp_offset
;
6305 rtx fp_offset_rtx
= GEN_INT (fp_offset
);
6307 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6308 bit, so make sure that we don't emit anything that can be
6310 /* ??? There is no DImode ori immediate pattern, so we can only
6311 do this for 32 bit code. */
6312 if (large_int (fp_offset_rtx
, GET_MODE (fp_offset_rtx
))
6313 && GET_MODE (base_reg_rtx
) == SImode
)
6315 insn
= emit_move_insn (base_reg_rtx
,
6316 GEN_INT (fp_offset
& 0xffff0000));
6318 RTX_FRAME_RELATED_P (insn
) = 1;
6319 insn
= emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
6320 GEN_INT (fp_offset
& 0x0000ffff)));
6322 RTX_FRAME_RELATED_P (insn
) = 1;
6326 insn
= emit_move_insn (base_reg_rtx
, fp_offset_rtx
);
6328 RTX_FRAME_RELATED_P (insn
) = 1;
6332 RTX_FRAME_RELATED_P (insn
) = 1;
6333 if (Pmode
== DImode
)
6334 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
,
6335 stack_pointer_rtx
));
6337 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
,
6338 stack_pointer_rtx
));
6340 RTX_FRAME_RELATED_P (insn
) = 1;
6344 fprintf (file
, "\tli\t%s,0x%.08lx\t# ",
6345 reg_names
[MIPS_TEMP2_REGNUM
], (long) base_offset
);
6346 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, base_offset
);
6347 fprintf (file
, "\n\t%s\t%s,%s,%s\n",
6348 Pmode
== DImode
? "daddu" : "addu",
6349 reg_names
[MIPS_TEMP2_REGNUM
],
6350 reg_names
[MIPS_TEMP2_REGNUM
],
6351 reg_names
[STACK_POINTER_REGNUM
]);
6355 /* This loop must iterate over the same space as its companion in
6356 compute_frame_size. */
6357 for (regno
= (FP_REG_LAST
- fp_inc
+ 1);
6358 regno
>= FP_REG_FIRST
;
6360 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
6364 enum machine_mode sz
6365 = TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6366 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
6367 rtx mem_rtx
= gen_rtx (MEM
, sz
,
6368 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
6371 RTX_UNCHANGING_P (mem_rtx
) = 1;
6375 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
6376 RTX_FRAME_RELATED_P (insn
) = 1;
6379 emit_move_insn (reg_rtx
, mem_rtx
);
6383 fprintf (file
, "\t%s\t%s,",
6384 (TARGET_SINGLE_FLOAT
6385 ? (store_p
? "s.s" : "l.s")
6386 : (store_p
? "s.d" : "l.d")),
6388 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
6389 fp_offset
- base_offset
);
6390 fprintf (file
, "(%s)\n", reg_names
[REGNO(base_reg_rtx
)]);
6393 fp_offset
-= fp_size
;
6398 /* Set up the stack and frame (if desired) for the function. */
6401 function_prologue (file
, size
)
6403 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
6405 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6408 long tsize
= current_frame_info
.total_size
;
6410 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
6412 #ifdef SDB_DEBUGGING_INFO
6413 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
6414 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
6417 /* In mips16 mode, we may need to generate a 32 bit to handle
6418 floating point arguments. The linker will arrange for any 32 bit
6419 functions to call this stub, which will then jump to the 16 bit
6421 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
6422 && current_function_args_info
.fp_code
!= 0)
6423 build_mips16_function_stub (file
);
6425 inside_function
= 1;
6427 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6428 /* Get the function name the same way that toplev.c does before calling
6429 assemble_start_function. This is needed so that the name used here
6430 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6431 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6433 if (!flag_inhibit_size_directive
)
6435 fputs ("\t.ent\t", file
);
6436 assemble_name (file
, fnname
);
6440 assemble_name (file
, fnname
);
6441 fputs (":\n", file
);
6444 if (!flag_inhibit_size_directive
)
6446 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6448 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6449 (reg_names
[(frame_pointer_needed
)
6450 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
6451 ((frame_pointer_needed
&& TARGET_MIPS16
)
6452 ? (tsize
- current_function_outgoing_args_size
)
6454 reg_names
[31 + GP_REG_FIRST
],
6455 current_frame_info
.var_size
,
6456 current_frame_info
.num_gp
,
6457 current_frame_info
.num_fp
,
6458 current_function_outgoing_args_size
,
6459 current_frame_info
.extra_size
);
6461 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6462 fprintf (file
, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6463 current_frame_info
.mask
,
6464 current_frame_info
.gp_save_offset
,
6465 current_frame_info
.fmask
,
6466 current_frame_info
.fp_save_offset
);
6469 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6470 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6473 if (mips_entry
&& ! mips_can_use_return_insn ())
6475 int save16
= BITSET_P (current_frame_info
.mask
, 16);
6476 int save17
= BITSET_P (current_frame_info
.mask
, 17);
6477 int save31
= BITSET_P (current_frame_info
.mask
, 31);
6481 /* Look through the initial insns to see if any of them store
6482 the function parameters into the incoming parameter storage
6483 area. If they do, we delete the insn, and save the register
6484 using the entry pseudo-instruction instead. We don't try to
6485 look past a label, jump, or call. */
6486 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6488 rtx note
, set
, src
, dest
, base
, offset
;
6491 if (GET_CODE (insn
) == CODE_LABEL
6492 || GET_CODE (insn
) == JUMP_INSN
6493 || GET_CODE (insn
) == CALL_INSN
)
6495 if (GET_CODE (insn
) != INSN
)
6497 set
= PATTERN (insn
);
6498 if (GET_CODE (set
) != SET
)
6501 /* An insn storing a function parameter will still have a
6502 REG_EQUIV note on it mentioning the argument pointer. */
6503 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
6504 if (note
== NULL_RTX
)
6506 if (! reg_mentioned_p (arg_pointer_rtx
, XEXP (note
, 0)))
6509 src
= SET_SRC (set
);
6510 if (GET_CODE (src
) != REG
6511 || REGNO (src
) < GP_REG_FIRST
+ 4
6512 || REGNO (src
) > GP_REG_FIRST
+ 7)
6515 dest
= SET_DEST (set
);
6516 if (GET_CODE (dest
) != MEM
)
6518 if (GET_MODE_SIZE (GET_MODE (dest
)) == UNITS_PER_WORD
)
6520 else if (GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
6521 && REGNO (src
) < GP_REG_FIRST
+ 7)
6525 offset
= const0_rtx
;
6526 base
= eliminate_constant_term (XEXP (dest
, 0), &offset
);
6527 if (GET_CODE (base
) != REG
6528 || GET_CODE (offset
) != CONST_INT
)
6530 if (REGNO (base
) == STACK_POINTER_REGNUM
6531 && INTVAL (offset
) == tsize
+ (REGNO (src
) - 4) * UNITS_PER_WORD
)
6533 else if (REGNO (base
) == HARD_FRAME_POINTER_REGNUM
6536 + (REGNO (src
) - 4) * UNITS_PER_WORD
6537 - current_function_outgoing_args_size
)))
6542 /* This insn stores a parameter onto the stack, in the same
6543 location where the entry pseudo-instruction will put it.
6544 Delete the insn, and arrange to tell the entry
6545 instruction to save the register. */
6546 PUT_CODE (insn
, NOTE
);
6547 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
6548 NOTE_SOURCE_FILE (insn
) = 0;
6550 hireg
= (REGNO (src
)
6551 + HARD_REGNO_NREGS (REGNO (src
), GET_MODE (dest
))
6553 if (hireg
> savearg
)
6557 /* If this is a varargs function, we need to save all the
6558 registers onto the stack anyhow. */
6559 if (current_function_stdarg
|| current_function_varargs
)
6560 savearg
= GP_REG_FIRST
+ 7;
6562 fprintf (file
, "\tentry\t");
6565 if (savearg
== GP_REG_FIRST
+ 4)
6566 fprintf (file
, "%s", reg_names
[savearg
]);
6568 fprintf (file
, "%s-%s", reg_names
[GP_REG_FIRST
+ 4],
6569 reg_names
[savearg
]);
6571 if (save16
|| save17
)
6574 fprintf (file
, ",");
6575 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 16]);
6577 fprintf (file
, "-%s", reg_names
[GP_REG_FIRST
+ 17]);
6581 if (savearg
> 0 || save16
|| save17
)
6582 fprintf (file
, ",");
6583 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 31]);
6585 fprintf (file
, "\n");
6588 if (TARGET_ABICALLS
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
6590 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
6592 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6593 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
6596 fprintf (file
, "\t%s\t%s,%s,%ld\n",
6597 (Pmode
== DImode
? "dsubu" : "subu"),
6598 sp_str
, sp_str
, tsize
);
6599 fprintf (file
, "\t.cprestore %ld\n", current_frame_info
.args_size
);
6602 if (dwarf2out_do_frame ())
6603 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
6607 /* Expand the prologue into a bunch of separate insns. */
6610 mips_expand_prologue ()
6613 HOST_WIDE_INT tsize
;
6615 const char *arg_name
= 0;
6616 tree fndecl
= current_function_decl
;
6617 tree fntype
= TREE_TYPE (fndecl
);
6618 tree fnargs
= DECL_ARGUMENTS (fndecl
);
6623 CUMULATIVE_ARGS args_so_far
;
6624 rtx reg_18_save
= NULL_RTX
;
6626 /* If struct value address is treated as the first argument, make it so. */
6627 if (aggregate_value_p (DECL_RESULT (fndecl
))
6628 && ! current_function_returns_pcc_struct
6629 && struct_value_incoming_rtx
== 0)
6631 tree type
= build_pointer_type (fntype
);
6632 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
6634 DECL_ARG_TYPE (function_result_decl
) = type
;
6635 TREE_CHAIN (function_result_decl
) = fnargs
;
6636 fnargs
= function_result_decl
;
6639 /* Determine the last argument, and get its name. */
6641 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, NULL_RTX
, 0);
6642 regno
= GP_ARG_FIRST
;
6644 for (cur_arg
= fnargs
; cur_arg
!= 0; cur_arg
= next_arg
)
6646 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
6647 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
6650 if (TREE_ADDRESSABLE (passed_type
))
6652 passed_type
= build_pointer_type (passed_type
);
6653 passed_mode
= Pmode
;
6656 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
6662 /* passed in a register, so will get homed automatically */
6663 if (GET_MODE (entry_parm
) == BLKmode
)
6664 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
6666 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
6668 regno
= REGNO (entry_parm
) + words
- 1;
6672 regno
= GP_ARG_LAST
+1;
6676 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
6678 next_arg
= TREE_CHAIN (cur_arg
);
6681 if (DECL_NAME (cur_arg
))
6682 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
6688 /* In order to pass small structures by value in registers compatibly with
6689 the MIPS compiler, we need to shift the value into the high part of the
6690 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
6691 adjustments to be made as the next_arg_reg variable, so we split up the
6692 insns, and emit them separately. */
6694 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
6695 if (next_arg_reg
!= 0 && GET_CODE (next_arg_reg
) == PARALLEL
)
6697 rtvec adjust
= XVEC (next_arg_reg
, 0);
6698 int num
= GET_NUM_ELEM (adjust
);
6700 for (i
= 0; i
< num
; i
++)
6702 rtx pattern
= RTVEC_ELT (adjust
, i
);
6703 if (GET_CODE (pattern
) != SET
6704 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
6705 abort_with_insn (pattern
, "Insn is not a shift");
6707 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
6708 emit_insn (pattern
);
6712 tsize
= compute_frame_size (get_frame_size ());
6714 /* If this function is a varargs function, store any registers that
6715 would normally hold arguments ($4 - $7) on the stack. */
6716 if ((mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
6717 && (! mips_entry
|| mips_can_use_return_insn ())
6718 && ((TYPE_ARG_TYPES (fntype
) != 0
6719 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
6722 && ((arg_name
[0] == '_'
6723 && strcmp (arg_name
, "__builtin_va_alist") == 0)
6724 || (arg_name
[0] == 'v'
6725 && strcmp (arg_name
, "va_alist") == 0)))))
6727 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
6728 rtx ptr
= stack_pointer_rtx
;
6730 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
6731 if (TARGET_ABICALLS
)
6734 for (; regno
<= GP_ARG_LAST
; regno
++)
6737 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
6738 emit_move_insn (gen_rtx (MEM
, gpr_mode
, ptr
),
6739 gen_rtx (REG
, gpr_mode
, regno
));
6741 offset
+= GET_MODE_SIZE (gpr_mode
);
6745 /* If we are using the entry pseudo instruction, it will
6746 automatically subtract 32 from the stack pointer, so we don't
6747 need to. The entry pseudo instruction is emitted by
6748 function_prologue. */
6749 if (mips_entry
&& ! mips_can_use_return_insn ())
6751 if (tsize
> 0 && tsize
<= 32 && frame_pointer_needed
)
6755 /* If we are using a frame pointer with a small stack frame,
6756 we need to initialize it here since it won't be done
6758 if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
6760 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
6761 if (Pmode
== DImode
)
6762 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
6766 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
6770 else if (Pmode
== DImode
)
6771 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
6772 stack_pointer_rtx
));
6774 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
6775 stack_pointer_rtx
));
6777 RTX_FRAME_RELATED_P (insn
) = 1;
6780 /* We may need to save $18, if it is used to call a function
6781 which may return a floating point value. Set up a sequence
6782 of instructions to do so. Later on we emit them at the right
6784 if (TARGET_MIPS16
&& BITSET_P (current_frame_info
.mask
, 18))
6786 rtx reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 3);
6787 long gp_offset
, base_offset
;
6789 gp_offset
= current_frame_info
.gp_sp_offset
;
6790 if (BITSET_P (current_frame_info
.mask
, 16))
6791 gp_offset
-= UNITS_PER_WORD
;
6792 if (BITSET_P (current_frame_info
.mask
, 17))
6793 gp_offset
-= UNITS_PER_WORD
;
6794 if (BITSET_P (current_frame_info
.mask
, 31))
6795 gp_offset
-= UNITS_PER_WORD
;
6797 base_offset
= tsize
;
6801 emit_move_insn (reg_rtx
,
6802 gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 18));
6803 emit_move_insn (gen_rtx (MEM
, gpr_mode
,
6804 gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
,
6808 reg_18_save
= gen_sequence ();
6817 if (reg_18_save
!= NULL_RTX
)
6818 emit_insn (reg_18_save
);
6824 rtx tsize_rtx
= GEN_INT (tsize
);
6826 /* If we are doing svr4-abi, sp move is done by
6827 function_prologue. In mips16 mode with a large frame, we
6828 save the registers before adjusting the stack. */
6829 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
6830 && (!TARGET_MIPS16
|| tsize
<= 32767))
6836 tmp_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
6838 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6839 bit, so make sure that we don't emit anything that can be
6841 /* ??? There is no DImode ori immediate pattern, so we can only
6842 do this for 32 bit code. */
6843 if (large_int (tsize_rtx
, GET_MODE (tsize_rtx
))
6844 && GET_MODE (tmp_rtx
) == SImode
)
6846 insn
= emit_move_insn (tmp_rtx
,
6847 GEN_INT (tsize
& 0xffff0000));
6848 RTX_FRAME_RELATED_P (insn
) = 1;
6849 insn
= emit_insn (gen_iorsi3 (tmp_rtx
, tmp_rtx
,
6850 GEN_INT (tsize
& 0x0000ffff)));
6851 RTX_FRAME_RELATED_P (insn
) = 1;
6855 insn
= emit_move_insn (tmp_rtx
, tsize_rtx
);
6856 RTX_FRAME_RELATED_P (insn
) = 1;
6859 tsize_rtx
= tmp_rtx
;
6862 if (Pmode
== DImode
)
6863 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6866 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6869 RTX_FRAME_RELATED_P (insn
) = 1;
6873 save_restore_insns (1, tmp_rtx
, tsize
, (FILE *)0);
6874 else if (reg_18_save
!= NULL_RTX
)
6875 emit_insn (reg_18_save
);
6877 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
6883 if (!frame_pointer_needed
)
6886 reg_rtx
= gen_rtx (REG
, Pmode
, 3);
6887 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
6888 emit_move_insn (reg_rtx
, tsize_rtx
);
6889 if (Pmode
== DImode
)
6890 emit_insn (gen_subdi3 (hard_frame_pointer_rtx
,
6891 hard_frame_pointer_rtx
,
6894 emit_insn (gen_subsi3 (hard_frame_pointer_rtx
,
6895 hard_frame_pointer_rtx
,
6897 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
6900 if (frame_pointer_needed
)
6904 /* On the mips16, we encourage the use of unextended
6905 instructions when using the frame pointer by pointing the
6906 frame pointer ahead of the argument space allocated on
6908 if ((! TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
6912 /* In this case, we have already copied the stack
6913 pointer into the frame pointer, above. We need only
6914 adjust for the outgoing argument size. */
6915 if (current_function_outgoing_args_size
!= 0)
6917 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
6918 if (Pmode
== DImode
)
6919 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
6920 hard_frame_pointer_rtx
,
6923 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
6924 hard_frame_pointer_rtx
,
6928 else if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
6930 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
6931 if (Pmode
== DImode
)
6932 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
6936 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
6940 else if (Pmode
== DImode
)
6941 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
6942 stack_pointer_rtx
));
6944 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
6945 stack_pointer_rtx
));
6948 RTX_FRAME_RELATED_P (insn
) = 1;
6951 if (TARGET_ABICALLS
&& (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
6952 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
6953 gen_rtx_REG (DImode
, 25)));
6956 /* If we are profiling, make sure no instructions are scheduled before
6957 the call to mcount. */
6959 if (profile_flag
|| profile_block_flag
)
6960 emit_insn (gen_blockage ());
6963 /* Do any necessary cleanup after a function to restore stack, frame,
6966 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
6967 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6970 function_epilogue (file
, size
)
6971 FILE *file ATTRIBUTE_UNUSED
;
6972 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
6976 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6977 /* Get the function name the same way that toplev.c does before calling
6978 assemble_start_function. This is needed so that the name used here
6979 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6980 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
6982 if (!flag_inhibit_size_directive
)
6984 fputs ("\t.end\t", file
);
6985 assemble_name (file
, fnname
);
6992 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
6993 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
6994 int num_regs
= num_gp_regs
+ num_fp_regs
;
6995 const char *name
= fnname
;
7000 dslots_load_total
+= num_regs
;
7003 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7004 name
, frame_pointer_needed
? 'y' : 'n',
7005 (current_frame_info
.mask
& RA_MASK
) != 0 ? 'n' : 'y',
7006 current_function_calls_alloca
? 'y' : 'n',
7007 current_function_calls_setjmp
? 'y' : 'n',
7008 current_frame_info
.total_size
,
7009 current_function_outgoing_args_size
, num_gp_regs
, num_fp_regs
,
7010 dslots_load_total
, dslots_load_filled
,
7011 dslots_jump_total
, dslots_jump_filled
,
7012 num_refs
[0], num_refs
[1], num_refs
[2]);
7014 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
7017 " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
7018 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
7021 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
7024 " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
7025 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
7028 fputc ('\n', stderr
);
7031 /* Reset state info for each function. */
7032 inside_function
= 0;
7033 ignore_line_number
= 0;
7034 dslots_load_total
= 0;
7035 dslots_jump_total
= 0;
7036 dslots_load_filled
= 0;
7037 dslots_jump_filled
= 0;
7043 current_frame_info
= zero_frame_info
;
7045 while (string_constants
!= NULL
)
7047 struct string_constant
*next
;
7049 next
= string_constants
->next
;
7050 free (string_constants
);
7051 string_constants
= next
;
7054 /* Restore the output file if optimizing the GP (optimizing the GP causes
7055 the text to be diverted to a tempfile, so that data decls come before
7056 references to the data). */
7058 if (TARGET_GP_OPT
&& ! TARGET_MIPS16
&& ! TARGET_GAS
)
7059 asm_out_file
= asm_out_data_file
;
7062 /* Expand the epilogue into a bunch of separate insns. */
7065 mips_expand_epilogue ()
7067 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
7068 rtx tsize_rtx
= GEN_INT (tsize
);
7069 rtx tmp_rtx
= (rtx
)0;
7071 if (mips_can_use_return_insn ())
7073 emit_insn (gen_return ());
7077 if (mips_entry
&& ! mips_can_use_return_insn ())
7080 if (tsize
> 32767 && ! TARGET_MIPS16
)
7082 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
7083 emit_move_insn (tmp_rtx
, tsize_rtx
);
7084 tsize_rtx
= tmp_rtx
;
7089 long orig_tsize
= tsize
;
7091 if (frame_pointer_needed
)
7093 emit_insn (gen_blockage ());
7095 /* On the mips16, the frame pointer is offset from the stack
7096 pointer by current_function_outgoing_args_size. We
7097 account for that by changing tsize. Note that this can
7098 actually make tsize negative. */
7101 tsize
-= current_function_outgoing_args_size
;
7103 /* If we have a large frame, it's easier to add to $17
7104 than to $sp, since the mips16 has no instruction to
7105 add a register to $sp. */
7106 if (orig_tsize
> 32767)
7108 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7110 emit_move_insn (g6_rtx
, GEN_INT (tsize
));
7111 if (Pmode
== DImode
)
7112 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7113 hard_frame_pointer_rtx
,
7116 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7117 hard_frame_pointer_rtx
,
7122 if (tsize
&& tsize
!= orig_tsize
)
7123 tsize_rtx
= GEN_INT (tsize
);
7126 if (Pmode
== DImode
)
7127 emit_insn (gen_movdi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7129 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7132 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7133 are going to restore it, then we must emit a blockage insn to
7134 prevent the scheduler from moving the restore out of the epilogue. */
7135 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
7136 && (current_frame_info
.mask
7137 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
7138 emit_insn (gen_blockage ());
7140 save_restore_insns (0, tmp_rtx
, orig_tsize
, (FILE *)0);
7142 /* In mips16 mode with a large frame, we adjust the stack
7143 pointer before restoring the registers. In this case, we
7144 should always be using a frame pointer, so everything should
7145 have been handled above. */
7146 if (tsize
> 32767 && TARGET_MIPS16
)
7149 emit_insn (gen_blockage ());
7150 if (Pmode
== DImode
&& tsize
!= 0)
7151 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7153 else if (tsize
!= 0)
7154 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7158 /* The mips16 loads the return address into $7, not $31. */
7159 if (TARGET_MIPS16
&& (current_frame_info
.mask
& RA_MASK
) != 0)
7160 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7161 GP_REG_FIRST
+ 7)));
7163 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7164 GP_REG_FIRST
+ 31)));
7167 /* Return nonzero if this function is known to have a null epilogue.
7168 This allows the optimizer to omit jumps to jumps if no stack
7172 mips_can_use_return_insn ()
7174 if (! reload_completed
)
7177 if (regs_ever_live
[31] || profile_flag
)
7180 /* In mips16 mode, a function which returns a floating point value
7181 needs to arrange to copy the return value into the floating point
7184 && mips16_hard_float
7185 && ! aggregate_value_p (DECL_RESULT (current_function_decl
))
7186 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl
)))
7188 && (! TARGET_SINGLE_FLOAT
7189 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl
)))
7193 if (current_frame_info
.initialized
)
7194 return current_frame_info
.total_size
== 0;
7196 return compute_frame_size (get_frame_size ()) == 0;
7199 /* Returns non-zero if X contains a SYMBOL_REF. */
7202 symbolic_expression_p (x
)
7205 if (GET_CODE (x
) == SYMBOL_REF
)
7208 if (GET_CODE (x
) == CONST
)
7209 return symbolic_expression_p (XEXP (x
, 0));
7211 if (GET_RTX_CLASS (GET_CODE (x
)) == '1')
7212 return symbolic_expression_p (XEXP (x
, 0));
7214 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
7215 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
7216 return (symbolic_expression_p (XEXP (x
, 0))
7217 || symbolic_expression_p (XEXP (x
, 1)));
7222 /* Choose the section to use for the constant rtx expression X that has
7226 mips_select_rtx_section (mode
, x
)
7227 enum machine_mode mode
;
7228 rtx x ATTRIBUTE_UNUSED
;
7232 /* In mips16 mode, the constant table always goes in the same section
7233 as the function, so that constants can be loaded using PC relative
7235 function_section (current_function_decl
);
7237 else if (TARGET_EMBEDDED_DATA
)
7239 /* For embedded applications, always put constants in read-only data,
7240 in order to reduce RAM usage. */
7241 READONLY_DATA_SECTION ();
7245 /* For hosted applications, always put constants in small data if
7246 possible, as this gives the best performance. */
7248 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
7249 && mips_section_threshold
> 0)
7250 SMALL_DATA_SECTION ();
7251 else if (flag_pic
&& symbolic_expression_p (x
))
7252 /* Any expression involving a SYMBOL_REF might need a run-time
7253 relocation. (The symbol might be defined in a shared
7254 library loaded at an unexpected base address.) So, we must
7255 put such expressions in the data segment (which is
7256 writable), rather than the text segment (which is
7260 READONLY_DATA_SECTION ();
7264 /* Choose the section to use for DECL. RELOC is true if its value contains
7265 any relocatable expression.
7267 Some of the logic used here needs to be replicated in
7268 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7269 are done correctly. Specifically, at least all symbols assigned
7270 here to rom (.text and/or .rodata) must not be referenced via
7271 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7273 If you need to make a change here, you probably should check
7274 ENCODE_SECTION_INFO to see if it needs a similar change. */
7277 mips_select_section (decl
, reloc
)
7281 int size
= int_size_in_bytes (TREE_TYPE (decl
));
7283 if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
7284 && TREE_CODE (decl
) == STRING_CST
7285 && !flag_writable_strings
)
7286 /* For embedded position independent code, put constant strings in the
7287 text section, because the data section is limited to 64K in size.
7288 For mips16 code, put strings in the text section so that a PC
7289 relative load instruction can be used to get their address. */
7291 else if (TARGET_EMBEDDED_DATA
)
7293 /* For embedded applications, always put an object in read-only data
7294 if possible, in order to reduce RAM usage. */
7296 if (((TREE_CODE (decl
) == VAR_DECL
7297 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
7298 && DECL_INITIAL (decl
)
7299 && (DECL_INITIAL (decl
) == error_mark_node
7300 || TREE_CONSTANT (DECL_INITIAL (decl
))))
7301 /* Deal with calls from output_constant_def_contents. */
7302 || (TREE_CODE (decl
) != VAR_DECL
7303 && (TREE_CODE (decl
) != STRING_CST
7304 || !flag_writable_strings
)))
7305 && ! (flag_pic
&& reloc
))
7306 READONLY_DATA_SECTION ();
7307 else if (size
> 0 && size
<= mips_section_threshold
)
7308 SMALL_DATA_SECTION ();
7314 /* For hosted applications, always put an object in small data if
7315 possible, as this gives the best performance. */
7317 if (size
> 0 && size
<= mips_section_threshold
)
7318 SMALL_DATA_SECTION ();
7319 else if (((TREE_CODE (decl
) == VAR_DECL
7320 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
7321 && DECL_INITIAL (decl
)
7322 && (DECL_INITIAL (decl
) == error_mark_node
7323 || TREE_CONSTANT (DECL_INITIAL (decl
))))
7324 /* Deal with calls from output_constant_def_contents. */
7325 || (TREE_CODE (decl
) != VAR_DECL
7326 && (TREE_CODE (decl
) != STRING_CST
7327 || !flag_writable_strings
)))
7328 && ! (flag_pic
&& reloc
))
7329 READONLY_DATA_SECTION ();
7335 #ifdef MIPS_ABI_DEFAULT
7337 /* Support functions for the 64 bit ABI. */
7339 /* Return register to use for a function return value with VALTYPE for function
7343 mips_function_value (valtype
, func
)
7345 tree func ATTRIBUTE_UNUSED
;
7347 int reg
= GP_RETURN
;
7348 enum machine_mode mode
= TYPE_MODE (valtype
);
7349 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7350 int unsignedp
= TREE_UNSIGNED (valtype
);
7352 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7353 just as PROMOTE_MODE does. */
7354 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
7356 /* ??? How should we return complex float? */
7357 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7359 if (TARGET_SINGLE_FLOAT
7360 && (mclass
== MODE_FLOAT
7361 ? GET_MODE_SIZE (mode
) > 4 : GET_MODE_SIZE (mode
) / 2 > 4))
7367 else if (TREE_CODE (valtype
) == RECORD_TYPE
7368 && mips_abi
!= ABI_32
7369 && mips_abi
!= ABI_O64
7370 && mips_abi
!= ABI_EABI
)
7372 /* A struct with only one or two floating point fields is returned in
7373 the floating point registers. */
7374 tree field
, fields
[2];
7377 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
7378 field
= TREE_CHAIN (field
))
7380 if (TREE_CODE (field
) != FIELD_DECL
)
7383 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
7386 fields
[i
++] = field
;
7389 /* Must check i, so that we reject structures with no elements. */
7394 /* The structure has DImode, but we don't allow DImode values
7395 in FP registers, so we use a PARALLEL even though it isn't
7396 strictly necessary. */
7397 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
7399 return gen_rtx_PARALLEL
7402 gen_rtx_EXPR_LIST (VOIDmode
,
7403 gen_rtx_REG (field_mode
,
7410 enum machine_mode first_mode
7411 = TYPE_MODE (TREE_TYPE (fields
[0]));
7412 enum machine_mode second_mode
7413 = TYPE_MODE (TREE_TYPE (fields
[1]));
7415 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
7417 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
7419 return gen_rtx_PARALLEL
7422 gen_rtx_EXPR_LIST (VOIDmode
,
7423 gen_rtx_REG (first_mode
,
7425 GEN_INT (first_offset
7427 gen_rtx_EXPR_LIST (VOIDmode
,
7428 gen_rtx_REG (second_mode
,
7430 GEN_INT (second_offset
7431 / BITS_PER_UNIT
))));
7436 return gen_rtx_REG (mode
, reg
);
7440 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7441 nonzero when an argument must be passed by reference. */
7444 function_arg_pass_by_reference (cum
, mode
, type
, named
)
7445 CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
7446 enum machine_mode mode
;
7448 int named ATTRIBUTE_UNUSED
;
7452 /* We must pass by reference if we would be both passing in registers
7453 and the stack. This is because any subsequent partial arg would be
7454 handled incorrectly in this case.
7456 ??? This is really a kludge. We should either fix GCC so that such
7457 a situation causes an abort and then do something in the MIPS port
7458 to prevent it, or add code to function.c to properly handle the case. */
7459 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
7460 here hopefully is not relevant to mips_va_arg. */
7461 if (cum
&& MUST_PASS_IN_STACK (mode
, type
))
7463 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
7464 get double copies of any offsets generated for small structs
7465 passed in registers. */
7466 CUMULATIVE_ARGS temp
= *cum
;
7467 if (FUNCTION_ARG (temp
, mode
, type
, named
) != 0)
7472 /* Otherwise, we only do this if EABI is selected. */
7473 if (mips_abi
!= ABI_EABI
)
7476 /* ??? How should SCmode be handled? */
7477 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
7480 size
= int_size_in_bytes (type
);
7481 return size
== -1 || size
> UNITS_PER_WORD
;
7484 /* This function returns the register class required for a secondary
7485 register when copying between one of the registers in CLASS, and X,
7486 using MODE. If IN_P is nonzero, the copy is going from X to the
7487 register, otherwise the register is the source. A return value of
7488 NO_REGS means that no secondary register is required. */
7491 mips_secondary_reload_class (class, mode
, x
, in_p
)
7492 enum reg_class
class;
7493 enum machine_mode mode
;
7497 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
7501 if (GET_CODE (x
) == SIGN_EXTEND
)
7507 /* We may be called with reg_renumber NULL from regclass.
7508 ??? This is probably a bug. */
7510 regno
= true_regnum (x
);
7513 while (GET_CODE (x
) == SUBREG
)
7515 off
+= SUBREG_WORD (x
);
7519 if (GET_CODE (x
) == REG
)
7520 regno
= REGNO (x
) + off
;
7524 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
7525 regno
= true_regnum (x
);
7527 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
7529 /* We always require a general register when copying anything to
7530 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7531 to a general register, or when copying from register 0. */
7532 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
7535 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
7536 ? NO_REGS
: gr_regs
);
7537 else if (regno
== HILO_REGNUM
)
7540 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
7541 ? NO_REGS
: gr_regs
);
7543 /* Copying from HI or LO to anywhere other than a general register
7544 requires a general register. */
7545 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
7547 if (TARGET_MIPS16
&& in_p
)
7549 /* We can't really copy to HI or LO at all in mips16 mode. */
7552 return gp_reg_p
? NO_REGS
: gr_regs
;
7554 if (MD_REG_P (regno
))
7556 if (TARGET_MIPS16
&& ! in_p
)
7558 /* We can't really copy to HI or LO at all in mips16 mode. */
7561 return class == gr_regs
? NO_REGS
: gr_regs
;
7564 /* We can only copy a value to a condition code register from a
7565 floating point register, and even then we require a scratch
7566 floating point register. We can only copy a value out of a
7567 condition code register into a general register. */
7568 if (class == ST_REGS
)
7572 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
7574 if (ST_REG_P (regno
))
7578 return class == GR_REGS
? NO_REGS
: GR_REGS
;
7581 /* In mips16 mode, going between memory and anything but M16_REGS
7582 requires an M16_REG. */
7585 if (class != M16_REGS
&& class != M16_NA_REGS
)
7593 /* The stack pointer isn't a valid operand to an add instruction,
7594 so we need to load it into M16_REGS first. This can happen as
7595 a result of register elimination and form_sum converting
7596 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
7597 need an extra register if the dest is the same as the other
7598 register. In that case, we can't fix the problem by loading SP
7599 into the dest first. */
7600 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == REG
7601 && GET_CODE (XEXP (x
, 1)) == REG
7602 && (XEXP (x
, 0) == stack_pointer_rtx
7603 || XEXP (x
, 1) == stack_pointer_rtx
))
7604 return (class == M16_REGS
? M16_NA_REGS
: M16_REGS
);
7606 if (class == M16_REGS
|| class == M16_NA_REGS
)
7615 /* For each mips16 function which refers to GP relative symbols, we
7616 use a pseudo register, initialized at the start of the function, to
7617 hold the $gp value. */
7620 mips16_gp_pseudo_reg ()
7622 if (mips16_gp_pseudo_rtx
== NULL_RTX
)
7627 mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
7628 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx
) = 1;
7630 /* We want to initialize this to a value which gcc will believe
7632 const_gp
= gen_rtx (CONST
, Pmode
,
7633 gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 28));
7636 emit_move_insn (mips16_gp_pseudo_rtx
, const_gp
);
7637 insn
= gen_sequence ();
7640 push_topmost_sequence ();
7641 /* We need to emit the initialization after the FUNCTION_BEG
7642 note, so that it will be integrated. */
7643 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
7644 if (GET_CODE (scan
) == NOTE
7645 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
7647 if (scan
== NULL_RTX
)
7648 scan
= get_insns ();
7649 insn
= emit_insn_after (insn
, scan
);
7650 pop_topmost_sequence ();
7653 return mips16_gp_pseudo_rtx
;
7656 /* Return an RTX which represents the signed 16 bit offset from the
7657 $gp register for the given symbol. This is only used on the
7661 mips16_gp_offset (sym
)
7666 if (GET_CODE (sym
) != SYMBOL_REF
7667 || ! SYMBOL_REF_FLAG (sym
))
7670 /* We use a special identifier to represent the value of the gp
7672 gp
= get_identifier ("__mips16_gp_value");
7674 return gen_rtx (CONST
, Pmode
,
7675 gen_rtx (MINUS
, Pmode
, sym
,
7676 gen_rtx (SYMBOL_REF
, Pmode
,
7677 IDENTIFIER_POINTER (gp
))));
7680 /* Return nonzero if the given RTX represents a signed 16 bit offset
7681 from the $gp register. */
7684 mips16_gp_offset_p (x
)
7687 if (GET_CODE (x
) == CONST
)
7690 /* It's OK to add a small integer value to a gp offset. */
7691 if (GET_CODE (x
) == PLUS
)
7693 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7694 && SMALL_INT (XEXP (x
, 1)))
7695 return mips16_gp_offset_p (XEXP (x
, 0));
7696 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
7697 && SMALL_INT (XEXP (x
, 0)))
7698 return mips16_gp_offset_p (XEXP (x
, 1));
7702 /* Make sure it is in the form SYM - __mips16_gp_value. */
7703 return (GET_CODE (x
) == MINUS
7704 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
7705 && SYMBOL_REF_FLAG (XEXP (x
, 0))
7706 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
7707 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0);
7710 /* Output a GP offset. We don't want to print the subtraction of
7711 __mips16_gp_value; it is implicitly represented by the %gprel which
7712 should have been printed by the caller. */
7715 mips16_output_gp_offset (file
, x
)
7719 if (GET_CODE (x
) == CONST
)
7722 if (GET_CODE (x
) == PLUS
)
7724 mips16_output_gp_offset (file
, XEXP (x
, 0));
7726 mips16_output_gp_offset (file
, XEXP (x
, 1));
7730 if (GET_CODE (x
) == MINUS
7731 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
7732 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0)
7734 mips16_output_gp_offset (file
, XEXP (x
, 0));
7738 output_addr_const (file
, x
);
7741 /* Return nonzero if a constant should not be output until after the
7742 function. This is true of most string constants, so that we can
7743 use a more efficient PC relative reference. However, a static
7744 inline function may never call assemble_function_end to write out
7745 the constant pool, so don't try to postpone the constant in that
7748 ??? It's really a bug that a static inline function can put stuff
7749 in the constant pool even if the function itself is not output.
7751 We record which string constants we've seen, so that we know which
7752 ones might use the more efficient reference. */
7755 mips16_constant_after_function_p (x
)
7758 if (TREE_CODE (x
) == STRING_CST
7759 && ! flag_writable_strings
7760 && current_function_decl
!= 0
7761 && ! DECL_DEFER_OUTPUT (current_function_decl
)
7762 && ! (DECL_INLINE (current_function_decl
)
7763 && ((! TREE_PUBLIC (current_function_decl
)
7764 && ! TREE_ADDRESSABLE (current_function_decl
)
7765 && ! flag_keep_inline_functions
)
7766 || DECL_EXTERNAL (current_function_decl
))))
7768 struct string_constant
*n
;
7770 n
= (struct string_constant
*) xmalloc (sizeof *n
);
7771 n
->label
= XSTR (XEXP (TREE_CST_RTL (x
), 0), 0);
7772 n
->next
= string_constants
;
7773 string_constants
= n
;
7781 /* Validate a constant for the mips16. This rejects general symbolic
7782 addresses, which must be loaded from memory. If ADDR is nonzero,
7783 this should reject anything which is not a legal address. If
7784 ADDEND is nonzero, this is being added to something else. */
7787 mips16_constant (x
, mode
, addr
, addend
)
7789 enum machine_mode mode
;
7793 while (GET_CODE (x
) == CONST
)
7796 switch (GET_CODE (x
))
7802 return (mips16_constant (XEXP (x
, 0), mode
, addr
, 1)
7803 && mips16_constant (XEXP (x
, 1), mode
, addr
, 1));
7806 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
7808 if (CONSTANT_POOL_ADDRESS_P (x
))
7811 /* If we aren't looking for a memory address, we can accept a GP
7812 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
7813 knows how to handle this. We can always accept a string
7814 constant, which is the other case in which SYMBOL_REF_FLAG
7816 if (! addr
&& ! addend
&& SYMBOL_REF_FLAG (x
) && mode
== Pmode
)
7819 /* We can accept a string constant, which will have
7820 SYMBOL_REF_FLAG set but must be recognized by name to
7821 distinguish from a GP accessible symbol. The name of a
7822 string constant will have been generated by
7823 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
7824 if (SYMBOL_REF_FLAG (x
))
7826 const char *name
= XSTR (x
, 0);
7828 return (name
[0] == '*'
7829 && strncmp (name
+ 1, LOCAL_LABEL_PREFIX
,
7830 sizeof LOCAL_LABEL_PREFIX
- 1) == 0);
7836 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
7841 if (addr
&& ! addend
)
7843 return INTVAL (x
) > - 0x10000 && INTVAL (x
) <= 0xffff;
7846 /* We need to treat $gp as a legitimate constant, because
7847 mips16_gp_pseudo_reg assumes that. */
7848 return REGNO (x
) == GP_REG_FIRST
+ 28;
7852 /* Write out code to move floating point arguments in or out of
7853 general registers. Output the instructions to FILE. FP_CODE is
7854 the code describing which arguments are present (see the comment at
7855 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
7856 we are copying from the floating point registers. */
7859 mips16_fp_args (file
, fp_code
, from_fp_p
)
7868 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7869 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
7876 gparg
= GP_ARG_FIRST
;
7877 fparg
= FP_ARG_FIRST
;
7878 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7882 if ((fparg
& 1) != 0)
7884 fprintf (file
, "\t%s\t%s,%s\n", s
,
7885 reg_names
[gparg
], reg_names
[fparg
]);
7887 else if ((f
& 3) == 2)
7890 fprintf (file
, "\td%s\t%s,%s\n", s
,
7891 reg_names
[gparg
], reg_names
[fparg
]);
7894 if ((fparg
& 1) != 0)
7896 if (TARGET_BIG_ENDIAN
)
7897 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7898 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
7899 reg_names
[gparg
+ 1], reg_names
[fparg
]);
7901 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
7902 reg_names
[gparg
], reg_names
[fparg
], s
,
7903 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
7916 /* Build a mips16 function stub. This is used for functions which
7917 take aruments in the floating point registers. It is 32 bit code
7918 that moves the floating point args into the general registers, and
7919 then jumps to the 16 bit code. */
7922 build_mips16_function_stub (file
)
7926 char *secname
, *stubname
;
7927 tree stubid
, stubdecl
;
7931 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7932 secname
= (char *) alloca (strlen (fnname
) + 20);
7933 sprintf (secname
, ".mips16.fn.%s", fnname
);
7934 stubname
= (char *) alloca (strlen (fnname
) + 20);
7935 sprintf (stubname
, "__fn_stub_%s", fnname
);
7936 stubid
= get_identifier (stubname
);
7937 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
7938 build_function_type (void_type_node
, NULL_TREE
));
7939 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
7941 fprintf (file
, "\t# Stub function for %s (", current_function_name
);
7943 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
7945 fprintf (file
, "%s%s",
7946 need_comma
? ", " : "",
7947 (f
& 3) == 1 ? "float" : "double");
7950 fprintf (file
, ")\n");
7952 fprintf (file
, "\t.set\tnomips16\n");
7953 function_section (stubdecl
);
7954 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
7956 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7957 within a .ent, and we can not emit another .ent. */
7958 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7959 fputs ("\t.ent\t", file
);
7960 assemble_name (file
, stubname
);
7964 assemble_name (file
, stubname
);
7965 fputs (":\n", file
);
7967 /* We don't want the assembler to insert any nops here. */
7968 fprintf (file
, "\t.set\tnoreorder\n");
7970 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
7972 fprintf (asm_out_file
, "\t.set\tnoat\n");
7973 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
7974 assemble_name (file
, fnname
);
7975 fprintf (file
, "\n");
7976 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
7977 fprintf (asm_out_file
, "\t.set\tat\n");
7979 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7980 with one of the mfc1 instructions, because the result is not
7981 available for one instruction, so if the very first instruction
7982 in the function refers to the register, it will see the wrong
7984 fprintf (file
, "\tnop\n");
7986 fprintf (file
, "\t.set\treorder\n");
7988 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7989 fputs ("\t.end\t", file
);
7990 assemble_name (file
, stubname
);
7994 fprintf (file
, "\t.set\tmips16\n");
7996 function_section (current_function_decl
);
7999 /* We keep a list of functions for which we have already built stubs
8000 in build_mips16_call_stub. */
8004 struct mips16_stub
*next
;
8009 static struct mips16_stub
*mips16_stubs
;
8011 /* Build a call stub for a mips16 call. A stub is needed if we are
8012 passing any floating point values which should go into the floating
8013 point registers. If we are, and the call turns out to be to a 32
8014 bit function, the stub will be used to move the values into the
8015 floating point registers before calling the 32 bit function. The
8016 linker will magically adjust the function call to either the 16 bit
8017 function or the 32 bit stub, depending upon where the function call
8018 is actually defined.
8020 Similarly, we need a stub if the return value might come back in a
8021 floating point register.
8023 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8024 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8025 is the code built by function_arg. This function returns a nonzero
8026 value if it builds the call instruction itself. */
8029 build_mips16_call_stub (retval
, fnmem
, arg_size
, fp_code
)
8038 char *secname
, *stubname
;
8039 struct mips16_stub
*l
;
8040 tree stubid
, stubdecl
;
8044 /* We don't need to do anything if we aren't in mips16 mode, or if
8045 we were invoked with the -msoft-float option. */
8046 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
8049 /* Figure out whether the value might come back in a floating point
8051 fpret
= (retval
!= 0
8052 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
8053 && (! TARGET_SINGLE_FLOAT
8054 || GET_MODE_SIZE (GET_MODE (retval
)) <= 4));
8056 /* We don't need to do anything if there were no floating point
8057 arguments and the value will not be returned in a floating point
8059 if (fp_code
== 0 && ! fpret
)
8062 if (GET_CODE (fnmem
) != MEM
)
8064 fn
= XEXP (fnmem
, 0);
8066 /* We don't need to do anything if this is a call to a special
8067 mips16 support function. */
8068 if (GET_CODE (fn
) == SYMBOL_REF
8069 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
8072 /* This code will only work for o32 and o64 abis. The other ABI's
8073 require more sophisticated support. */
8074 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8077 /* We can only handle SFmode and DFmode floating point return
8079 if (fpret
&& GET_MODE (retval
) != SFmode
&& GET_MODE (retval
) != DFmode
)
8082 /* If we're calling via a function pointer, then we must always call
8083 via a stub. There are magic stubs provided in libgcc.a for each
8084 of the required cases. Each of them expects the function address
8085 to arrive in register $2. */
8087 if (GET_CODE (fn
) != SYMBOL_REF
)
8091 rtx stub_fn
, stub_mem
, insn
;
8093 /* ??? If this code is modified to support other ABI's, we need
8094 to handle PARALLEL return values here. */
8096 sprintf (buf
, "__mips16_call_stub_%s%d",
8098 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
8101 id
= get_identifier (buf
);
8102 stub_fn
= gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (id
));
8103 stub_mem
= gen_rtx (MEM
, Pmode
, stub_fn
);
8105 emit_move_insn (gen_rtx (REG
, Pmode
, 2), fn
);
8107 if (retval
== NULL_RTX
)
8108 insn
= gen_call_internal0 (stub_mem
, arg_size
,
8109 gen_rtx (REG
, SImode
,
8110 GP_REG_FIRST
+ 31));
8112 insn
= gen_call_value_internal0 (retval
, stub_mem
, arg_size
,
8113 gen_rtx (REG
, SImode
,
8114 GP_REG_FIRST
+ 31));
8115 insn
= emit_call_insn (insn
);
8117 /* Put the register usage information on the CALL. */
8118 if (GET_CODE (insn
) != CALL_INSN
)
8120 CALL_INSN_FUNCTION_USAGE (insn
) =
8121 gen_rtx (EXPR_LIST
, VOIDmode
,
8122 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, Pmode
, 2)),
8123 CALL_INSN_FUNCTION_USAGE (insn
));
8125 /* If we are handling a floating point return value, we need to
8126 save $18 in the function prologue. Putting a note on the
8127 call will mean that regs_ever_live[$18] will be true if the
8128 call is not eliminated, and we can check that in the prologue
8131 CALL_INSN_FUNCTION_USAGE (insn
) =
8132 gen_rtx (EXPR_LIST
, VOIDmode
,
8133 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
8134 CALL_INSN_FUNCTION_USAGE (insn
));
8136 /* Return 1 to tell the caller that we've generated the call
8141 /* We know the function we are going to call. If we have already
8142 built a stub, we don't need to do anything further. */
8144 fnname
= XSTR (fn
, 0);
8145 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
8146 if (strcmp (l
->name
, fnname
) == 0)
8151 /* Build a special purpose stub. When the linker sees a
8152 function call in mips16 code, it will check where the target
8153 is defined. If the target is a 32 bit call, the linker will
8154 search for the section defined here. It can tell which
8155 symbol this section is associated with by looking at the
8156 relocation information (the name is unreliable, since this
8157 might be a static function). If such a section is found, the
8158 linker will redirect the call to the start of the magic
8161 If the function does not return a floating point value, the
8162 special stub section is named
8165 If the function does return a floating point value, the stub
8167 .mips16.call.fp.FNNAME
8170 secname
= (char *) alloca (strlen (fnname
) + 40);
8171 sprintf (secname
, ".mips16.call.%s%s",
8174 stubname
= (char *) alloca (strlen (fnname
) + 20);
8175 sprintf (stubname
, "__call_stub_%s%s",
8178 stubid
= get_identifier (stubname
);
8179 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8180 build_function_type (void_type_node
, NULL_TREE
));
8181 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8183 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
8185 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
8189 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8191 fprintf (asm_out_file
, "%s%s",
8192 need_comma
? ", " : "",
8193 (f
& 3) == 1 ? "float" : "double");
8196 fprintf (asm_out_file
, ")\n");
8198 fprintf (asm_out_file
, "\t.set\tnomips16\n");
8199 assemble_start_function (stubdecl
, stubname
);
8201 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8202 fputs ("\t.ent\t", asm_out_file
);
8203 assemble_name (asm_out_file
, stubname
);
8204 fputs ("\n", asm_out_file
);
8206 assemble_name (asm_out_file
, stubname
);
8207 fputs (":\n", asm_out_file
);
8210 /* We build the stub code by hand. That's the only way we can
8211 do it, since we can't generate 32 bit code during a 16 bit
8214 /* We don't want the assembler to insert any nops here. */
8215 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
8217 mips16_fp_args (asm_out_file
, fp_code
, 0);
8221 fprintf (asm_out_file
, "\t.set\tnoat\n");
8222 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
8224 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8225 fprintf (asm_out_file
, "\t.set\tat\n");
8226 /* Unfortunately, we can't fill the jump delay slot. We
8227 can't fill with one of the mtc1 instructions, because the
8228 result is not available for one instruction, so if the
8229 very first instruction in the function refers to the
8230 register, it will see the wrong value. */
8231 fprintf (asm_out_file
, "\tnop\n");
8235 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
8236 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
8237 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
8238 /* As above, we can't fill the delay slot. */
8239 fprintf (asm_out_file
, "\tnop\n");
8240 if (GET_MODE (retval
) == SFmode
)
8241 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8242 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
8245 if (TARGET_BIG_ENDIAN
)
8247 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8248 reg_names
[GP_REG_FIRST
+ 2],
8249 reg_names
[FP_REG_FIRST
+ 1]);
8250 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8251 reg_names
[GP_REG_FIRST
+ 3],
8252 reg_names
[FP_REG_FIRST
+ 0]);
8256 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8257 reg_names
[GP_REG_FIRST
+ 2],
8258 reg_names
[FP_REG_FIRST
+ 0]);
8259 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
8260 reg_names
[GP_REG_FIRST
+ 3],
8261 reg_names
[FP_REG_FIRST
+ 1]);
8264 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
8265 /* As above, we can't fill the delay slot. */
8266 fprintf (asm_out_file
, "\tnop\n");
8269 fprintf (asm_out_file
, "\t.set\treorder\n");
8271 #ifdef ASM_DECLARE_FUNCTION_SIZE
8272 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
8275 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8276 fputs ("\t.end\t", asm_out_file
);
8277 assemble_name (asm_out_file
, stubname
);
8278 fputs ("\n", asm_out_file
);
8281 fprintf (asm_out_file
, "\t.set\tmips16\n");
8283 /* Record this stub. */
8284 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
8285 l
->name
= xstrdup (fnname
);
8287 l
->next
= mips16_stubs
;
8291 /* If we expect a floating point return value, but we've built a
8292 stub which does not expect one, then we're in trouble. We can't
8293 use the existing stub, because it won't handle the floating point
8294 value. We can't build a new stub, because the linker won't know
8295 which stub to use for the various calls in this object file.
8296 Fortunately, this case is illegal, since it means that a function
8297 was declared in two different ways in a single compilation. */
8298 if (fpret
&& ! l
->fpret
)
8299 error ("can not handle inconsistent calls to `%s'", fnname
);
8301 /* If we are calling a stub which handles a floating point return
8302 value, we need to arrange to save $18 in the prologue. We do
8303 this by marking the function call as using the register. The
8304 prologue will later see that it is used, and emit code to save
8311 if (retval
== NULL_RTX
)
8312 insn
= gen_call_internal0 (fnmem
, arg_size
,
8313 gen_rtx (REG
, SImode
,
8314 GP_REG_FIRST
+ 31));
8316 insn
= gen_call_value_internal0 (retval
, fnmem
, arg_size
,
8317 gen_rtx (REG
, SImode
,
8318 GP_REG_FIRST
+ 31));
8319 insn
= emit_call_insn (insn
);
8321 if (GET_CODE (insn
) != CALL_INSN
)
8324 CALL_INSN_FUNCTION_USAGE (insn
) =
8325 gen_rtx (EXPR_LIST
, VOIDmode
,
8326 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
8327 CALL_INSN_FUNCTION_USAGE (insn
));
8329 /* Return 1 to tell the caller that we've generated the call
8334 /* Return 0 to let the caller generate the call insn. */
8338 /* This function looks through the code for a function, and tries to
8339 optimize the usage of the $gp register. We arrange to copy $gp
8340 into a pseudo-register, and then let gcc's normal reload handling
8341 deal with the pseudo-register. Unfortunately, if reload choose to
8342 put the pseudo-register into a call-clobbered register, it will
8343 emit saves and restores for that register around any function
8344 calls. We don't need the saves, and it's faster to copy $gp than
8345 to do an actual restore. ??? This still means that we waste a
8348 This is an optimization, and the code which gcc has actually
8349 generated is correct, so we do not need to catch all cases. */
8352 mips16_optimize_gp (first
)
8355 rtx gpcopy
, slot
, insn
;
8357 /* Look through the instructions. Set GPCOPY to the register which
8358 holds a copy of $gp. Set SLOT to the stack slot where it is
8359 saved. If we find an instruction which sets GPCOPY to anything
8360 other than $gp or SLOT, then we can't use it. If we find an
8361 instruction which sets SLOT to anything other than GPCOPY, we
8366 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
8370 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8373 set
= PATTERN (insn
);
8375 /* We know that all references to memory will be inside a SET,
8376 because there is no other way to access memory on the mips16.
8377 We don't have to worry about a PARALLEL here, because the
8378 mips.md file will never generate them for memory references. */
8379 if (GET_CODE (set
) != SET
)
8382 if (gpcopy
== NULL_RTX
8383 && GET_CODE (SET_SRC (set
)) == CONST
8384 && GET_CODE (XEXP (SET_SRC (set
), 0)) == REG
8385 && REGNO (XEXP (SET_SRC (set
), 0)) == GP_REG_FIRST
+ 28
8386 && GET_CODE (SET_DEST (set
)) == REG
8387 && GET_MODE (SET_DEST (set
)) == Pmode
)
8388 gpcopy
= SET_DEST (set
);
8389 else if (slot
== NULL_RTX
8390 && gpcopy
!= NULL_RTX
8391 && GET_CODE (SET_DEST (set
)) == MEM
8392 && GET_CODE (SET_SRC (set
)) == REG
8393 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
)
8394 && GET_MODE (SET_DEST (set
)) == Pmode
)
8398 offset
= const0_rtx
;
8399 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
8400 if (GET_CODE (base
) == REG
8401 && (REGNO (base
) == STACK_POINTER_REGNUM
8402 || REGNO (base
) == FRAME_POINTER_REGNUM
))
8403 slot
= SET_DEST (set
);
8405 else if (gpcopy
!= NULL_RTX
8406 && (GET_CODE (SET_DEST (set
)) == REG
8407 || GET_CODE (SET_DEST (set
)) == SUBREG
)
8408 && reg_overlap_mentioned_p (SET_DEST (set
), gpcopy
)
8409 && (GET_CODE (SET_DEST (set
)) != REG
8410 || REGNO (SET_DEST (set
)) != REGNO (gpcopy
)
8411 || GET_MODE (SET_DEST (set
)) != Pmode
8412 || ((GET_CODE (SET_SRC (set
)) != CONST
8413 || GET_CODE (XEXP (SET_SRC (set
), 0)) != REG
8414 || (REGNO (XEXP (SET_SRC (set
), 0))
8415 != GP_REG_FIRST
+ 28))
8416 && ! rtx_equal_p (SET_SRC (set
), slot
))))
8418 else if (slot
!= NULL_RTX
8419 && GET_CODE (SET_DEST (set
)) == MEM
8420 && rtx_equal_p (SET_DEST (set
), slot
)
8421 && (GET_CODE (SET_SRC (set
)) != REG
8422 || REGNO (SET_SRC (set
)) != REGNO (gpcopy
)))
8426 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8427 different optimization. Any time we find a copy of $28 into a
8428 register, followed by an add of a symbol_ref to that register, we
8429 convert it to load the value from the constant table instead.
8430 The copy and add will take six bytes, just as the load and
8431 constant table entry will take six bytes. However, it is
8432 possible that the constant table entry will be shared.
8434 This could be a peephole optimization, but I don't know if the
8435 peephole code can call force_const_mem.
8437 Using the same register for the copy of $28 and the add of the
8438 symbol_ref is actually pretty likely, since the add instruction
8439 requires the destination and the first addend to be the same
8442 if (insn
!= NULL_RTX
|| gpcopy
== NULL_RTX
|| slot
== NULL_RTX
)
8446 /* This optimization is only reasonable if the constant table
8447 entries are only 4 bytes. */
8448 if (Pmode
!= SImode
)
8451 for (insn
= first
; insn
!= NULL_RTX
; insn
= next
)
8458 next
= NEXT_INSN (next
);
8460 while (next
!= NULL_RTX
8461 && (GET_CODE (next
) == NOTE
8462 || (GET_CODE (next
) == INSN
8463 && (GET_CODE (PATTERN (next
)) == USE
8464 || GET_CODE (PATTERN (next
)) == CLOBBER
))));
8466 if (next
== NULL_RTX
)
8469 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8472 if (GET_RTX_CLASS (GET_CODE (next
)) != 'i')
8475 set1
= PATTERN (insn
);
8476 if (GET_CODE (set1
) != SET
)
8478 set2
= PATTERN (next
);
8479 if (GET_CODE (set2
) != SET
)
8482 if (GET_CODE (SET_DEST (set1
)) == REG
8483 && GET_CODE (SET_SRC (set1
)) == CONST
8484 && GET_CODE (XEXP (SET_SRC (set1
), 0)) == REG
8485 && REGNO (XEXP (SET_SRC (set1
), 0)) == GP_REG_FIRST
+ 28
8486 && rtx_equal_p (SET_DEST (set1
), SET_DEST (set2
))
8487 && GET_CODE (SET_SRC (set2
)) == PLUS
8488 && rtx_equal_p (SET_DEST (set1
), XEXP (SET_SRC (set2
), 0))
8489 && mips16_gp_offset_p (XEXP (SET_SRC (set2
), 1))
8490 && GET_CODE (XEXP (XEXP (SET_SRC (set2
), 1), 0)) == MINUS
)
8494 /* We've found a case we can change to load from the
8497 sym
= XEXP (XEXP (XEXP (SET_SRC (set2
), 1), 0), 0);
8498 if (GET_CODE (sym
) != SYMBOL_REF
)
8500 emit_insn_after (gen_rtx (SET
, VOIDmode
, SET_DEST (set1
),
8501 force_const_mem (Pmode
, sym
)),
8504 PUT_CODE (insn
, NOTE
);
8505 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8506 NOTE_SOURCE_FILE (insn
) = 0;
8508 PUT_CODE (next
, NOTE
);
8509 NOTE_LINE_NUMBER (next
) = NOTE_INSN_DELETED
;
8510 NOTE_SOURCE_FILE (next
) = 0;
8517 /* We can safely remove all assignments to SLOT from GPCOPY, and
8518 replace all assignments from SLOT to GPCOPY with assignments from
8521 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
8525 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8528 set
= PATTERN (insn
);
8529 if (GET_CODE (set
) != SET
8530 || GET_MODE (SET_DEST (set
)) != Pmode
)
8533 if (GET_CODE (SET_DEST (set
)) == MEM
8534 && rtx_equal_p (SET_DEST (set
), slot
)
8535 && GET_CODE (SET_SRC (set
)) == REG
8536 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
))
8538 PUT_CODE (insn
, NOTE
);
8539 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8540 NOTE_SOURCE_FILE (insn
) = 0;
8542 else if (GET_CODE (SET_DEST (set
)) == REG
8543 && REGNO (SET_DEST (set
)) == REGNO (gpcopy
)
8544 && GET_CODE (SET_SRC (set
)) == MEM
8545 && rtx_equal_p (SET_SRC (set
), slot
))
8547 emit_insn_after (gen_rtx (SET
, Pmode
, SET_DEST (set
),
8548 gen_rtx (CONST
, Pmode
,
8549 gen_rtx (REG
, Pmode
,
8550 GP_REG_FIRST
+ 28))),
8552 PUT_CODE (insn
, NOTE
);
8553 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8554 NOTE_SOURCE_FILE (insn
) = 0;
8559 /* We keep a list of constants we which we have to add to internal
8560 constant tables in the middle of large functions. */
8564 struct constant
*next
;
8567 enum machine_mode mode
;
8570 /* Add a constant to the list in *PCONSTANTS. */
8573 add_constant (pconstants
, val
, mode
)
8574 struct constant
**pconstants
;
8576 enum machine_mode mode
;
8580 for (c
= *pconstants
; c
!= NULL
; c
= c
->next
)
8581 if (mode
== c
->mode
&& rtx_equal_p (val
, c
->value
))
8584 c
= (struct constant
*) xmalloc (sizeof *c
);
8587 c
->label
= gen_label_rtx ();
8588 c
->next
= *pconstants
;
8593 /* Dump out the constants in CONSTANTS after INSN. */
8596 dump_constants (constants
, insn
)
8597 struct constant
*constants
;
8608 struct constant
*next
;
8610 switch (GET_MODE_SIZE (c
->mode
))
8617 insn
= emit_insn_after (gen_align_2 (), insn
);
8622 insn
= emit_insn_after (gen_align_4 (), insn
);
8627 insn
= emit_insn_after (gen_align_8 (), insn
);
8632 insn
= emit_label_after (c
->label
, insn
);
8637 r
= gen_consttable_qi (c
->value
);
8640 r
= gen_consttable_hi (c
->value
);
8643 r
= gen_consttable_si (c
->value
);
8646 r
= gen_consttable_sf (c
->value
);
8649 r
= gen_consttable_di (c
->value
);
8652 r
= gen_consttable_df (c
->value
);
8658 insn
= emit_insn_after (r
, insn
);
8665 emit_barrier_after (insn
);
8668 /* Find the symbol in an address expression. */
8671 mips_find_symbol (addr
)
8674 if (GET_CODE (addr
) == MEM
)
8675 addr
= XEXP (addr
, 0);
8676 while (GET_CODE (addr
) == CONST
)
8677 addr
= XEXP (addr
, 0);
8678 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
8680 if (GET_CODE (addr
) == PLUS
)
8684 l1
= mips_find_symbol (XEXP (addr
, 0));
8685 l2
= mips_find_symbol (XEXP (addr
, 1));
8686 if (l1
!= NULL_RTX
&& l2
== NULL_RTX
)
8688 else if (l1
== NULL_RTX
&& l2
!= NULL_RTX
)
8694 /* Exported to toplev.c.
8696 Do a final pass over the function, just before delayed branch
8700 machine_dependent_reorg (first
)
8703 int insns_len
, max_internal_pool_size
, pool_size
, addr
, first_constant_ref
;
8705 struct constant
*constants
;
8707 if (! TARGET_MIPS16
)
8710 /* If $gp is used, try to remove stores, and replace loads with
8713 mips16_optimize_gp (first
);
8715 /* Scan the function looking for PC relative loads which may be out
8716 of range. All such loads will either be from the constant table,
8717 or be getting the address of a constant string. If the size of
8718 the function plus the size of the constant table is less than
8719 0x8000, then all loads are in range. */
8722 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8724 insns_len
+= get_attr_length (insn
);
8726 /* ??? We put switch tables in .text, but we don't define
8727 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8728 compute their lengths correctly. */
8729 if (GET_CODE (insn
) == JUMP_INSN
)
8733 body
= PATTERN (insn
);
8734 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
8735 insns_len
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
8736 * GET_MODE_SIZE (GET_MODE (body
)));
8737 insns_len
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
8741 /* Store the original value of insns_len in current_frame_info, so
8742 that simple_memory_operand can look at it. */
8743 current_frame_info
.insns_len
= insns_len
;
8745 pool_size
= get_pool_size ();
8746 if (insns_len
+ pool_size
+ mips_string_length
< 0x8000)
8749 /* Loop over the insns and figure out what the maximum internal pool
8751 max_internal_pool_size
= 0;
8752 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8754 if (GET_CODE (insn
) == INSN
8755 && GET_CODE (PATTERN (insn
)) == SET
)
8759 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
8760 if (src
== NULL_RTX
)
8762 if (CONSTANT_POOL_ADDRESS_P (src
))
8763 max_internal_pool_size
+= GET_MODE_SIZE (get_pool_mode (src
));
8764 else if (SYMBOL_REF_FLAG (src
))
8765 max_internal_pool_size
+= GET_MODE_SIZE (Pmode
);
8771 first_constant_ref
= -1;
8773 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8775 if (GET_CODE (insn
) == INSN
8776 && GET_CODE (PATTERN (insn
)) == SET
)
8779 enum machine_mode mode
;
8782 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
8783 if (src
!= NULL_RTX
&& CONSTANT_POOL_ADDRESS_P (src
))
8785 /* ??? This is very conservative, which means that we
8786 will generate too many copies of the constant table.
8787 The only solution would seem to be some form of
8789 if (((insns_len
- addr
)
8790 + max_internal_pool_size
8791 + get_pool_offset (src
))
8794 val
= get_pool_constant (src
);
8795 mode
= get_pool_mode (src
);
8797 max_internal_pool_size
-= GET_MODE_SIZE (get_pool_mode (src
));
8799 else if (src
!= NULL_RTX
&& SYMBOL_REF_FLAG (src
))
8801 /* Including all of mips_string_length is conservative,
8802 and so is including all of max_internal_pool_size. */
8803 if (((insns_len
- addr
)
8804 + max_internal_pool_size
8806 + mips_string_length
)
8810 max_internal_pool_size
-= Pmode
;
8813 if (val
!= NULL_RTX
)
8817 /* This PC relative load is out of range. ??? In the
8818 case of a string constant, we are only guessing that
8819 it is range, since we don't know the offset of a
8820 particular string constant. */
8822 lab
= add_constant (&constants
, val
, mode
);
8823 newsrc
= gen_rtx (MEM
, mode
,
8824 gen_rtx (LABEL_REF
, VOIDmode
, lab
));
8825 RTX_UNCHANGING_P (newsrc
) = 1;
8826 PATTERN (insn
) = gen_rtx (SET
, VOIDmode
,
8827 SET_DEST (PATTERN (insn
)),
8829 INSN_CODE (insn
) = -1;
8831 if (first_constant_ref
< 0)
8832 first_constant_ref
= addr
;
8836 addr
+= get_attr_length (insn
);
8838 /* ??? We put switch tables in .text, but we don't define
8839 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8840 compute their lengths correctly. */
8841 if (GET_CODE (insn
) == JUMP_INSN
)
8845 body
= PATTERN (insn
);
8846 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
8847 addr
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
8848 * GET_MODE_SIZE (GET_MODE (body
)));
8849 addr
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
8852 if (GET_CODE (insn
) == BARRIER
)
8854 /* Output any constants we have accumulated. Note that we
8855 don't need to change ADDR, since its only use is
8856 subtraction from INSNS_LEN, and both would be changed by
8858 ??? If the instructions up to the next barrier reuse a
8859 constant, it would often be better to continue
8861 if (constants
!= NULL
)
8862 dump_constants (constants
, insn
);
8864 first_constant_ref
= -1;
8867 if (constants
!= NULL
8868 && (NEXT_INSN (insn
) == NULL
8869 || (first_constant_ref
>= 0
8870 && (((addr
- first_constant_ref
)
8871 + 2 /* for alignment */
8872 + 2 /* for a short jump insn */
8876 /* If we haven't had a barrier within 0x8000 bytes of a
8877 constant reference or we are at the end of the function,
8878 emit a barrier now. */
8880 rtx label
, jump
, barrier
;
8882 label
= gen_label_rtx ();
8883 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
8884 JUMP_LABEL (jump
) = label
;
8885 LABEL_NUSES (label
) = 1;
8886 barrier
= emit_barrier_after (jump
);
8887 emit_label_after (label
, barrier
);
8888 first_constant_ref
= -1;
8892 /* ??? If we output all references to a constant in internal
8893 constants table, we don't need to output the constant in the real
8894 constant table, but we have no way to prevent that. */
8897 /* Return nonzero if X is a SIGN or ZERO extend operator. */
8899 extend_operator (x
, mode
)
8901 enum machine_mode mode ATTRIBUTE_UNUSED
;
8903 enum rtx_code code
= GET_CODE (x
);
8904 return code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
;
8907 /* Accept any operator that can be used to shift the high half of the
8908 input value to the lower half, suitable for truncation. The
8909 remainder (the lower half of the input, and the upper half of the
8910 output) will be discarded. */
8912 highpart_shift_operator (x
, mode
)
8914 enum machine_mode mode ATTRIBUTE_UNUSED
;
8916 enum rtx_code code
= GET_CODE (x
);
8917 return (code
== LSHIFTRT
8923 /* Return the length of INSN. LENGTH is the initial length computed by
8924 attributes in the machine-description file. */
8927 mips_adjust_insn_length (insn
, length
)
8931 /* A unconditional jump has an unfilled delay slot if it is not part
8932 of a sequence. A conditional jump normally has a delay slot, but
8933 does not on MIPS16. */
8934 if (simplejump_p (insn
)
8935 || (!TARGET_MIPS16
&& (GET_CODE (insn
) == JUMP_INSN
8936 || GET_CODE (insn
) == CALL_INSN
)))
8939 /* All MIPS16 instructions are a measly two bytes. */
8946 /* Output assembly instructions to peform a conditional branch.
8948 INSN is the branch instruction. OPERANDS[0] is the condition.
8949 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8950 of the first operand to the condition. If TWO_OPERANDS_P is
8951 non-zero the comparison takes two operands; OPERANDS[3] will be the
8954 If INVERTED_P is non-zero we are to branch if the condition does
8955 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
8957 LENGTH is the length (in bytes) of the sequence we are to generate.
8958 That tells us whether to generate a simple conditional branch, or a
8959 reversed conditional branch around a `jr' instruction. */
8961 mips_output_conditional_branch (insn
,
8974 static char buffer
[200];
8975 /* The kind of comparison we are doing. */
8976 enum rtx_code code
= GET_CODE (operands
[0]);
8977 /* Non-zero if the opcode for the comparison needs a `z' indicating
8978 that it is a comparision against zero. */
8980 /* A string to use in the assembly output to represent the first
8982 const char *op1
= "%z2";
8983 /* A string to use in the assembly output to represent the second
8984 operand. Use the hard-wired zero register if there's no second
8986 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
8987 /* The operand-printing string for the comparison. */
8988 const char *comp
= (float_p
? "%F0" : "%C0");
8989 /* The operand-printing string for the inverted comparison. */
8990 const char *inverted_comp
= (float_p
? "%W0" : "%N0");
8992 /* The MIPS processors (for levels of the ISA at least two), have
8993 "likely" variants of each branch instruction. These instructions
8994 annul the instruction in the delay slot if the branch is not
8996 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
8998 if (!two_operands_p
)
9000 /* To compute whether than A > B, for example, we normally
9001 subtract B from A and then look at the sign bit. But, if we
9002 are doing an unsigned comparison, and B is zero, we don't
9003 have to do the subtraction. Instead, we can just check to
9004 see if A is non-zero. Thus, we change the CODE here to
9005 reflect the simpler comparison operation. */
9017 /* A condition which will always be true. */
9023 /* A condition which will always be false. */
9029 /* Not a special case. */
9034 /* Relative comparisons are always done against zero. But
9035 equality comparisons are done between two operands, and therefore
9036 do not require a `z' in the assembly language output. */
9037 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
9038 /* For comparisons against zero, the zero is not provided
9043 /* Begin by terminating the buffer. That way we can always use
9044 strcat to add to it. */
9051 /* Just a simple conditional branch. */
9053 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1",
9054 inverted_p
? inverted_comp
: comp
);
9056 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1",
9057 inverted_p
? inverted_comp
: comp
,
9058 need_z_p
? "z" : "",
9066 /* Generate a reversed conditional branch around ` j'
9078 Because we have to jump four bytes *past* the following
9079 instruction if this branch was annulled, we can't just use
9080 a label, as in the picture above; there's no way to put the
9081 label after the next instruction, as the assembler does not
9082 accept `.L+4' as the target of a branch. (We can't just
9083 wait until the next instruction is output; it might be a
9084 macro and take up more than four bytes. Once again, we see
9085 why we want to eliminate macros.)
9087 If the branch is annulled, we jump four more bytes that we
9088 would otherwise; that way we skip the annulled instruction
9089 in the delay slot. */
9092 = ((mips_branch_likely
|| length
== 16) ? ".+16" : ".+12");
9095 strcpy (buffer
, "%(%<");
9096 c
= strchr (buffer
, '\0');
9097 /* Generate the reversed comparision. This takes four
9100 sprintf (c
, "%%*b%s\t%%Z2%s",
9101 inverted_p
? comp
: inverted_comp
,
9104 sprintf (c
, "%%*b%s%s\t%s%s,%s",
9105 inverted_p
? comp
: inverted_comp
,
9106 need_z_p
? "z" : "",
9110 strcat (c
, "\n\tnop\n\tj\t%1");
9112 /* The delay slot was unfilled. Since we're inside
9113 .noreorder, the assembler will not fill in the NOP for
9114 us, so we must do it ourselves. */
9115 strcat (buffer
, "\n\tnop");
9116 strcat (buffer
, "%>%)");
9120 /* We do not currently use this code. It handles jumps to
9121 arbitrary locations, using `jr', even across a 256MB boundary.
9122 We could add a -mhuge switch, and then use this code instead of
9123 the `j' alternative above when -mhuge was used. */
9128 /* Generate a reversed conditional branch around a `jr'
9142 Not pretty, but allows a conditional branch anywhere in the
9143 32-bit address space. If the original branch is annulled,
9144 then the instruction in the delay slot should be executed
9145 only if the branch is taken. The la instruction is really
9146 a macro which will usually take eight bytes, but sometimes
9147 takes only four, if the instruction to which we're jumping
9148 gets its own entry in the global pointer table, which will
9149 happen if its a case label. The assembler will then
9150 generate only a four-byte sequence, rather than eight, and
9151 there seems to be no way to tell it not to. Thus, we can't
9152 just use a `.+x' addressing form; we don't know what value
9155 So, we resort to using the explicit relocation syntax
9156 available in the assembler and do:
9158 lw $at,%got_page(target)($gp)
9159 daddiu $at,$at,%got_ofst(target)
9161 That way, this always takes up eight bytes, and we can use
9162 the `.+x' form. Of course, these explicit machinations
9163 with relocation will not work with old assemblers. Then
9164 again, neither do out-of-range branches, so we haven't lost
9167 /* The target of the reversed branch. */
9169 = ((mips_branch_likely
|| length
== 20) ? ".+20" : ".+16");
9170 const char *at_register
= mips_reg_names
[ASSEMBLER_SCRATCH_REGNUM
];
9171 const char *gp_register
= mips_reg_names
[PIC_OFFSET_TABLE_REGNUM
];
9174 strcpy (buffer
, "%(%<%[");
9175 c
= strchr (buffer
, '\0');
9176 /* Generate the reversed comparision. This takes four
9179 sprintf (c
, "%%*b%s\t%%Z2%s",
9180 inverted_p
? comp
: inverted_comp
,
9183 sprintf (c
, "%%*b%s%s\t%s%s,%s",
9184 inverted_p
? comp
: inverted_comp
,
9185 need_z_p
? "z" : "",
9189 c
= strchr (buffer
, '\0');
9190 /* Generate the load-address, and jump. This takes twelve
9191 bytes, for a total of 16. */
9193 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9200 /* The delay slot was unfilled. Since we're inside
9201 .noreorder, the assembler will not fill in the NOP for
9202 us, so we must do it ourselves. */
9203 strcat (buffer
, "\n\tnop");
9204 strcat (buffer
, "%]%>%)");
9217 /* Called to register all of our global variables with the garbage
9221 mips_add_gc_roots ()
9223 ggc_add_rtx_root (&mips_load_reg
, 1);
9224 ggc_add_rtx_root (&mips_load_reg2
, 1);
9225 ggc_add_rtx_root (&mips_load_reg3
, 1);
9226 ggc_add_rtx_root (&mips_load_reg4
, 1);
9227 ggc_add_rtx_root (branch_cmp
, sizeof (branch_cmp
) / sizeof (rtx
));
9228 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx
, 1);
9229 ggc_add_rtx_root (&mips16_gp_pseudo_rtx
, 1);