1 /* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
2 Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Note that some other tm.h files include this one and then override
23 many of the definitions that relate to assembler syntax. */
26 /* Names to predefine in the preprocessor for this target machine. */
28 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
30 /* Print subsidiary information on the compiler version in use. */
32 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
34 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
37 /* Define SUPPORT_SUN_FPA to include support for generating code for
38 the Sun Floating Point Accelerator, an optional product for Sun 3
39 machines. By default, it is not defined. Avoid defining it unless
40 you need to output code for the Sun3+FPA architecture, as it has the
41 effect of slowing down the register set operations in hard-reg-set.h
42 (total number of registers will exceed number of bits in a long,
43 if defined, causing the set operations to expand to loops).
44 SUPPORT_SUN_FPA is typically defined in sun3.h. */
46 /* Run-time compilation parameters selecting different hardware subsets. */
48 extern int target_flags
;
50 /* Macros used in the machine description to test the flags. */
52 /* Compile for a 68020 (not a 68000 or 68010). */
54 #define TARGET_68020 (target_flags & MASK_68020)
56 /* Compile 68881 insns for floating point (not library calls). */
58 #define TARGET_68881 (target_flags & MASK_68881)
60 /* Compile using 68020 bitfield insns. */
61 #define MASK_BITFIELD 4
62 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
64 /* Compile using rtd insn calling sequence.
65 This will not work unless you use prototypes at least
66 for all functions that can take varying numbers of args. */
68 #define TARGET_RTD (target_flags & MASK_RTD)
70 /* Compile passing first two args in regs 0 and 1.
71 This exists only to test compiler features that will
72 be needed for RISC chips. It is not usable
73 and is not intended to be usable on this cpu. */
74 #define MASK_REGPARM 16
75 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
77 /* Compile with 16-bit `int'. */
79 #define TARGET_SHORT (target_flags & MASK_SHORT)
81 /* Compile with special insns for Sun FPA. */
83 #define TARGET_FPA (target_flags & MASK_FPA)
85 /* Compile (actually, link) for Sun SKY board. */
87 #define TARGET_SKY (target_flags & MASK_SKY)
89 /* Optimize for 68040, but still allow execution on 68020
90 (-m68020-40 or -m68040).
91 The 68040 will execute all 68030 and 68881/2 instructions, but some
92 of them must be emulated in software by the OS. When TARGET_68040 is
93 turned on, these instructions won't be used. This code will still
94 run on a 68030 and 68881/2. */
95 #define MASK_68040 256
96 #define TARGET_68040 (target_flags & MASK_68040)
98 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
99 #define MASK_68040_ONLY 512
100 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
102 /* Optimize for 68060, but still allow execution on 68020
103 (-m68020-60 or -m68060).
104 The 68060 will execute all 68030 and 68881/2 instructions, but some
105 of them must be emulated in software by the OS. When TARGET_68060 is
106 turned on, these instructions won't be used. This code will still
107 run on a 68030 and 68881/2. */
108 #define MASK_68060 1024
109 #define TARGET_68060 (target_flags & MASK_68060)
111 /* Compile for mcf5200 */
112 #define MASK_5200 2048
113 #define TARGET_5200 (target_flags & MASK_5200)
115 /* Align ints to a word boundary. This breaks compatibility with the
116 published ABI's for structures containing ints, but produces faster
117 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
118 It's required for coldfire cpus without a misalignment module. */
119 #define MASK_ALIGN_INT 4096
120 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
122 /* Compile for a CPU32 */
123 /* A 68020 without bitfields is a good heuristic for a CPU32 */
124 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
126 /* Macro to define tables used to set the flags.
127 This is a list in braces of pairs in braces,
128 each pair being { "NAME", VALUE }
129 where VALUE is the bits to set or minus the bits to clear.
130 An empty string NAME is used to identify the default VALUE. */
132 #define TARGET_SWITCHES \
133 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
134 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
135 { "68020", (MASK_68020|MASK_BITFIELD)}, \
136 { "c68020", (MASK_68020|MASK_BITFIELD)}, \
137 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
138 |MASK_68020|MASK_BITFIELD)}, \
139 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
140 |MASK_68020|MASK_BITFIELD)}, \
141 { "bitfield", MASK_BITFIELD}, \
142 { "nobitfield", - MASK_BITFIELD}, \
143 { "rtd", MASK_RTD}, \
144 { "nortd", - MASK_RTD}, \
145 { "short", MASK_SHORT}, \
146 { "noshort", - MASK_SHORT}, \
147 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
148 { "fpa", MASK_FPA}, \
149 { "nofpa", - MASK_FPA}, \
150 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881)}, \
151 { "sky", MASK_SKY}, \
152 { "nosky", - MASK_SKY}, \
153 { "68881" - (MASK_FPA|MASK_SKY)}, \
154 { "68881", MASK_68881}, \
155 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
156 { "68020-40", -(MASK_5200|MASK_68060)}, \
157 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040)}, \
158 { "68020-60", -(MASK_5200|MASK_68040)}, \
159 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68060)}, \
160 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
161 { "68030", (MASK_68020|MASK_BITFIELD)}, \
162 { "68040", - (MASK_5200|MASK_68060)}, \
163 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
164 |MASK_68040_ONLY|MASK_68040)}, \
165 { "68060", - (MASK_5200|MASK_68040)}, \
166 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
167 |MASK_68040_ONLY|MASK_68060)}, \
168 { "5200", - (MASK_68060|MASK_68040|MASK_68020|MASK_BITFIELD|MASK_68881)}, \
169 { "5200", (MASK_5200)}, \
172 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68020|MASK_BITFIELD)}, \
173 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_BITFIELD)}, \
174 { "68332", MASK_68020}, \
175 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_BITFIELD)}, \
176 { "cpu32", MASK_68020}, \
177 { "align-int", MASK_ALIGN_INT }, \
178 { "no-align-int", -MASK_ALIGN_INT }, \
180 { "", TARGET_DEFAULT}}
181 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
183 /* This macro is similar to `TARGET_SWITCHES' but defines names of
184 command options that have values. Its definition is an
185 initializer with a subgrouping for each command option.
187 Each subgrouping contains a string constant, that defines the
188 fixed part of the option name, and the address of a variable. The
189 variable, type `char *', is set to the variable part of the given
190 option if the fixed part matches. The actual option name is made
191 by appending `-m' to the specified name. */
192 #define TARGET_OPTIONS \
193 { { "align-loops=", &m68k_align_loops_string }, \
194 { "align-jumps=", &m68k_align_jumps_string }, \
195 { "align-functions=", &m68k_align_funcs_string }, \
199 /* Sometimes certain combinations of command options do not make
200 sense on a particular target machine. You can define a macro
201 `OVERRIDE_OPTIONS' to take account of this. This macro, if
202 defined, is executed once just after all the command options have
205 Don't use this macro to turn on various extra optimizations for
206 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
208 #define OVERRIDE_OPTIONS \
210 override_options(); \
211 if (! TARGET_68020 && flag_pic == 2) \
212 error("-fPIC is not currently supported on the 68000 or 68010\n"); \
213 SUBTARGET_OVERRIDE_OPTIONS; \
216 /* These are meant to be redefined in the host dependent files */
217 #define SUBTARGET_SWITCHES
218 #define SUBTARGET_OPTIONS
219 #define SUBTARGET_OVERRIDE_OPTIONS
221 /* target machine storage layout */
223 /* Define for XFmode extended real floating point support.
224 This will automatically cause REAL_ARITHMETIC to be defined. */
225 #define LONG_DOUBLE_TYPE_SIZE 96
227 /* Define if you don't want extended real, but do want to use the
228 software floating point emulator for REAL_ARITHMETIC and
229 decimal <-> binary conversion. */
230 /* #define REAL_ARITHMETIC */
232 /* Define this if most significant bit is lowest numbered
233 in instructions that operate on numbered bit-fields.
234 This is true for 68020 insns such as bfins and bfexts.
235 We make it true always by avoiding using the single-bit insns
236 except in special cases with constant bit numbers. */
237 #define BITS_BIG_ENDIAN 1
239 /* Define this if most significant byte of a word is the lowest numbered. */
240 /* That is true on the 68000. */
241 #define BYTES_BIG_ENDIAN 1
243 /* Define this if most significant word of a multiword number is the lowest
245 /* For 68000 we can decide arbitrarily
246 since there are no machine instructions for them.
247 So let's be consistent. */
248 #define WORDS_BIG_ENDIAN 1
250 /* number of bits in an addressable storage unit */
251 #define BITS_PER_UNIT 8
253 /* Width in bits of a "word", which is the contents of a machine register.
254 Note that this is not necessarily the width of data type `int';
255 if using 16-bit ints on a 68000, this would still be 32.
256 But on a machine with 16-bit registers, this would be 16. */
257 #define BITS_PER_WORD 32
259 /* Width of a word, in units (bytes). */
260 #define UNITS_PER_WORD 4
262 /* Width in bits of a pointer.
263 See also the macro `Pmode' defined below. */
264 #define POINTER_SIZE 32
266 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
267 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
269 /* Boundary (in *bits*) on which stack pointer should be aligned. */
270 #define STACK_BOUNDARY 16
272 /* Allocation boundary (in *bits*) for the code of a function. */
273 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
275 /* Alignment of field after `int : 0' in a structure. */
276 #define EMPTY_FIELD_BOUNDARY 16
278 /* No data type wants to be aligned rounder than this.
279 Most published ABIs say that ints should be aligned on 16 bit
280 boundries, but cpus with 32 bit busses get better performance
281 aligned on 32 bit boundries. Coldfires without a misalignment
282 module require 32 bit alignment. */
283 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
285 /* Set this nonzero if move instructions will actually fail to work
286 when given unaligned data. */
287 #define STRICT_ALIGNMENT 1
289 /* Maximum power of 2 that code can be aligned to. */
290 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
292 /* Align loop starts for optimal branching. */
293 #define ASM_OUTPUT_LOOP_ALIGN(FILE) ASM_OUTPUT_ALIGN ((FILE), m68k_align_loops)
295 /* This is how to align an instruction for optimal branching. */
296 #define ASM_OUTPUT_ALIGN_CODE(FILE) ASM_OUTPUT_ALIGN ((FILE), m68k_align_jumps)
298 #define SELECT_RTX_SECTION(MODE, X) \
301 readonly_data_section(); \
302 else if (LEGITIMATE_PIC_OPERAND_P (X)) \
303 readonly_data_section(); \
308 /* Define number of bits in most basic integer type.
309 (If undefined, default is BITS_PER_WORD). */
311 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
313 /* Define these to avoid dependence on meaning of `int'.
314 Note that WCHAR_TYPE_SIZE is used in cexp.y,
315 where TARGET_SHORT is not available. */
317 #define WCHAR_TYPE "long int"
318 #define WCHAR_TYPE_SIZE 32
320 /* Standard register usage. */
322 /* Number of actual hardware registers.
323 The hardware registers are assigned numbers for the compiler
324 from 0 to just below FIRST_PSEUDO_REGISTER.
325 All registers that the compiler knows about must be given numbers,
326 even those that are not normally considered general registers.
327 For the 68000, we give the data registers numbers 0-7,
328 the address registers numbers 010-017,
329 and the 68881 floating point registers numbers 020-027. */
330 #ifndef SUPPORT_SUN_FPA
331 #define FIRST_PSEUDO_REGISTER 24
333 #define FIRST_PSEUDO_REGISTER 56
336 /* This defines the register which is used to hold the offset table for PIC. */
337 #define PIC_OFFSET_TABLE_REGNUM 13
339 /* Used to output a (use pic_offset_table_rtx) so that we
340 always save/restore a5 in functions that use PIC relocation
341 at *any* time during the compilation process. */
342 #define FINALIZE_PIC finalize_pic()
344 #ifndef SUPPORT_SUN_FPA
346 /* 1 for registers that have pervasive standard uses
347 and are not available for the register allocator.
348 On the 68000, only the stack pointer is such. */
350 #define FIXED_REGISTERS \
351 {/* Data registers. */ \
352 0, 0, 0, 0, 0, 0, 0, 0, \
354 /* Address registers. */ \
355 0, 0, 0, 0, 0, 0, 0, 1, \
357 /* Floating point registers \
359 0, 0, 0, 0, 0, 0, 0, 0 }
361 /* 1 for registers not available across function calls.
362 These must include the FIXED_REGISTERS and also any
363 registers that can be used without being saved.
364 The latter must include the registers where values are returned
365 and the register where structure-value addresses are passed.
366 Aside from that, you can include as many other registers as you like. */
367 #define CALL_USED_REGISTERS \
368 {1, 1, 0, 0, 0, 0, 0, 0, \
369 1, 1, 0, 0, 0, 0, 0, 1, \
370 1, 1, 0, 0, 0, 0, 0, 0 }
372 #else /* SUPPORT_SUN_FPA */
374 /* 1 for registers that have pervasive standard uses
375 and are not available for the register allocator.
376 On the 68000, only the stack pointer is such. */
378 /* fpa0 is also reserved so that it can be used to move shit back and
379 forth between high fpa regs and everything else. */
381 #define FIXED_REGISTERS \
382 {/* Data registers. */ \
383 0, 0, 0, 0, 0, 0, 0, 0, \
385 /* Address registers. */ \
386 0, 0, 0, 0, 0, 0, 0, 1, \
388 /* Floating point registers \
390 0, 0, 0, 0, 0, 0, 0, 0, \
392 /* Sun3 FPA registers. */ \
393 1, 0, 0, 0, 0, 0, 0, 0, \
394 0, 0, 0, 0, 0, 0, 0, 0, \
395 0, 0, 0, 0, 0, 0, 0, 0, \
396 0, 0, 0, 0, 0, 0, 0, 0 }
398 /* 1 for registers not available across function calls.
399 These must include the FIXED_REGISTERS and also any
400 registers that can be used without being saved.
401 The latter must include the registers where values are returned
402 and the register where structure-value addresses are passed.
403 Aside from that, you can include as many other registers as you like. */
404 #define CALL_USED_REGISTERS \
405 {1, 1, 0, 0, 0, 0, 0, 0, \
406 1, 1, 0, 0, 0, 0, 0, 1, \
407 1, 1, 0, 0, 0, 0, 0, 0, \
408 /* FPA registers. */ \
409 1, 1, 1, 1, 0, 0, 0, 0, \
410 0, 0, 0, 0, 0, 0, 0, 0, \
411 0, 0, 0, 0, 0, 0, 0, 0, \
412 0, 0, 0, 0, 0, 0, 0, 0 }
414 #endif /* defined SUPPORT_SUN_FPA */
417 /* Make sure everything's fine if we *don't* have a given processor.
418 This assumes that putting a register in fixed_regs will keep the
419 compiler's mitts completely off it. We don't bother to zero it out
420 of register classes. If neither TARGET_FPA or TARGET_68881 is set,
421 the compiler won't touch since no instructions that use these
422 registers will be valid. */
424 #ifdef SUPPORT_SUN_FPA
426 #define CONDITIONAL_REGISTER_USAGE \
432 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
433 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
434 if (TEST_HARD_REG_BIT (x, i)) \
435 fixed_regs[i] = call_used_regs[i] = 1; \
439 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
440 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
441 if (TEST_HARD_REG_BIT (x, i)) \
442 fixed_regs[i] = call_used_regs[i] = 1; \
446 #endif /* defined SUPPORT_SUN_FPA */
448 /* Return number of consecutive hard regs needed starting at reg REGNO
449 to hold something of mode MODE.
450 This is ordinarily the length in words of a value of mode MODE
451 but can be less for certain modes in special long registers.
453 On the 68000, ordinary registers hold 32 bits worth;
454 for the 68881 registers, a single register is always enough for
455 anything that can be stored in them at all. */
456 #define HARD_REGNO_NREGS(REGNO, MODE) \
457 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
458 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
460 #ifndef SUPPORT_SUN_FPA
462 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
463 On the 68000, the cpu registers can hold any mode but the 68881 registers
464 can hold only SFmode or DFmode. The 68881 registers can't hold anything
465 if 68881 use is disabled. */
467 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
469 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8)) \
472 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
473 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)))
475 #else /* defined SUPPORT_SUN_FPA */
477 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
478 On the 68000, the cpu registers can hold any mode but the 68881 registers
479 can hold only SFmode or DFmode. And the 68881 registers can't hold anything
480 if 68881 use is disabled. However, the Sun FPA register can
481 (apparently) hold whatever you feel like putting in them.
482 If using the fpa, don't put a double in d7/a0. */
484 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
487 && GET_MODE_CLASS ((MODE)) != MODE_INT \
488 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
489 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
490 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
492 ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
493 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
494 : ((REGNO) < 56 ? TARGET_FPA : 0)))
496 #endif /* defined SUPPORT_SUN_FPA */
498 /* Value is 1 if it is a good idea to tie two pseudo registers
499 when one has mode MODE1 and one has mode MODE2.
500 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
501 for any hard reg, then this must be 0 for correct output. */
502 #define MODES_TIEABLE_P(MODE1, MODE2) \
504 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
505 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
506 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
507 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
509 /* Specify the registers used for certain standard purposes.
510 The values of these macros are register numbers. */
512 /* m68000 pc isn't overloaded on a register. */
513 /* #define PC_REGNUM */
515 /* Register to use for pushing function arguments. */
516 #define STACK_POINTER_REGNUM 15
518 /* Base register for access to local variables of the function. */
519 #define FRAME_POINTER_REGNUM 14
521 /* Value should be nonzero if functions must have frame pointers.
522 Zero means the frame pointer need not be set up (and parms
523 may be accessed via the stack pointer) in functions that seem suitable.
524 This is computed in `reload', in reload1.c. */
525 #define FRAME_POINTER_REQUIRED 0
527 /* Base register for access to arguments of the function. */
528 #define ARG_POINTER_REGNUM 14
530 /* Register in which static-chain is passed to a function. */
531 #define STATIC_CHAIN_REGNUM 8
533 /* Register in which address to store a structure value
534 is passed to a function. */
535 #define STRUCT_VALUE_REGNUM 9
537 /* Define the classes of registers for register constraints in the
538 machine description. Also define ranges of constants.
540 One of the classes must always be named ALL_REGS and include all hard regs.
541 If there is more than one class, another class must be named NO_REGS
542 and contain no registers.
544 The name GENERAL_REGS must be the name of a class (or an alias for
545 another name such as ALL_REGS). This is the class of registers
546 that is allowed by "g" or "r" in a register constraint.
547 Also, registers outside this class are allocated only when
548 instructions express preferences for them.
550 The classes must be numbered in nondecreasing order; that is,
551 a larger-numbered class must never be contained completely
552 in a smaller-numbered class.
554 For any two classes, it is very desirable that there be another
555 class that represents their union. */
557 /* The 68000 has three kinds of registers, so eight classes would be
558 a complete set. One of them is not needed. */
560 #ifndef SUPPORT_SUN_FPA
565 GENERAL_REGS
, DATA_OR_FP_REGS
,
566 ADDR_OR_FP_REGS
, ALL_REGS
,
569 #define N_REG_CLASSES (int) LIM_REG_CLASSES
571 /* Give names of register classes as strings for dump file. */
573 #define REG_CLASS_NAMES \
574 { "NO_REGS", "DATA_REGS", \
575 "ADDR_REGS", "FP_REGS", \
576 "GENERAL_REGS", "DATA_OR_FP_REGS", \
577 "ADDR_OR_FP_REGS", "ALL_REGS" }
579 /* Define which registers fit in which classes.
580 This is an initializer for a vector of HARD_REG_SET
581 of length N_REG_CLASSES. */
583 #define REG_CLASS_CONTENTS \
585 0x00000000, /* NO_REGS */ \
586 0x000000ff, /* DATA_REGS */ \
587 0x0000ff00, /* ADDR_REGS */ \
588 0x00ff0000, /* FP_REGS */ \
589 0x0000ffff, /* GENERAL_REGS */ \
590 0x00ff00ff, /* DATA_OR_FP_REGS */ \
591 0x00ffff00, /* ADDR_OR_FP_REGS */ \
592 0x00ffffff, /* ALL_REGS */ \
595 /* The same information, inverted:
596 Return the class number of the smallest class containing
597 reg number REGNO. This could be a conditional expression
598 or could index an array. */
600 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
602 #else /* defined SUPPORT_SUN_FPA */
605 * Notes on final choices:
607 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
609 * 2) Removed all unions that involve address registers with
610 * floating point registers (left in unions of address and data with
612 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
613 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
614 * 4) Left in everything else.
616 enum reg_class
{ NO_REGS
, LO_FPA_REGS
, FPA_REGS
, FP_REGS
,
617 FP_OR_FPA_REGS
, DATA_REGS
, DATA_OR_FPA_REGS
, DATA_OR_FP_REGS
,
618 DATA_OR_FP_OR_FPA_REGS
, ADDR_REGS
, GENERAL_REGS
,
619 GENERAL_OR_FPA_REGS
, GENERAL_OR_FP_REGS
, ALL_REGS
,
622 #define N_REG_CLASSES (int) LIM_REG_CLASSES
624 /* Give names of register classes as strings for dump file. */
626 #define REG_CLASS_NAMES \
627 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
628 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
629 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
630 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
632 /* Define which registers fit in which classes.
633 This is an initializer for a vector of HARD_REG_SET
634 of length N_REG_CLASSES. */
636 #define REG_CLASS_CONTENTS \
638 {0, 0}, /* NO_REGS */ \
639 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
640 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
641 {0x00ff0000, 0x00000000}, /* FP_REGS */ \
642 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
643 {0x000000ff, 0x00000000}, /* DATA_REGS */ \
644 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
645 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
646 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
647 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
648 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
649 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
650 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
651 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
654 /* The same information, inverted:
655 Return the class number of the smallest class containing
656 reg number REGNO. This could be a conditional expression
657 or could index an array. */
659 extern enum reg_class regno_reg_class
[];
660 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
662 #endif /* SUPPORT_SUN_FPA */
664 /* The class value for index registers, and the one for base regs. */
666 #define INDEX_REG_CLASS GENERAL_REGS
667 #define BASE_REG_CLASS ADDR_REGS
669 /* Get reg_class from a letter such as appears in the machine description.
670 We do a trick here to modify the effective constraints on the
671 machine description; we zorch the constraint letters that aren't
672 appropriate for a specific target. This allows us to guarantee
673 that a specific kind of register will not be used for a given target
674 without fiddling with the register classes above. */
676 #ifndef SUPPORT_SUN_FPA
678 #define REG_CLASS_FROM_LETTER(C) \
679 ((C) == 'a' ? ADDR_REGS : \
680 ((C) == 'd' ? DATA_REGS : \
681 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
685 #else /* defined SUPPORT_SUN_FPA */
687 #define REG_CLASS_FROM_LETTER(C) \
688 ((C) == 'a' ? ADDR_REGS : \
689 ((C) == 'd' ? DATA_REGS : \
690 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
692 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
694 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
698 #endif /* defined SUPPORT_SUN_FPA */
700 /* The letters I, J, K, L and M in a register constraint string
701 can be used to stand for particular ranges of immediate operands.
702 This macro defines what the ranges are.
703 C is the letter, and VALUE is a constant value.
704 Return 1 if VALUE is in the range specified by C.
706 For the 68000, `I' is used for the range 1 to 8
707 allowed as immediate shift counts and in addq.
708 `J' is used for the range of signed numbers that fit in 16 bits.
709 `K' is for numbers that moveq can't handle.
710 `L' is for range -8 to -1, range of values that can be added with subq.
711 `M' is for numbers that moveq+notb can't handle.
712 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
713 'O' is for 16 (for rotate using swap).
714 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
716 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
717 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
718 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
719 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
720 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
721 (C) == 'M' ? (VALUE) < -0x100 && (VALUE) >= 0x100 : \
722 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
723 (C) == 'O' ? (VALUE) == 16 : \
724 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
727 * A small bit of explanation:
728 * "G" defines all of the floating constants that are *NOT* 68881
729 * constants. this is so 68881 constants get reloaded and the
730 * fpmovecr is used. "H" defines *only* the class of constants that
731 * the fpa can use, because these can be gotten at in any fpa
732 * instruction and there is no need to force reloads.
734 #ifndef SUPPORT_SUN_FPA
735 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
736 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
737 #else /* defined SUPPORT_SUN_FPA */
738 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
739 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
740 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
741 #endif /* defined SUPPORT_SUN_FPA */
743 /* A C expression that defines the optional machine-dependent constraint
744 letters that can be used to segregate specific types of operands,
745 usually memory references, for the target machine. It should return 1 if
746 VALUE corresponds to the operand type represented by the constraint letter
747 C. If C is not defined as an extra constraint, the value returned should
748 be 0 regardless of VALUE. */
750 /* For the m68k, `Q' means address register indirect addressing mode. */
752 #define EXTRA_CONSTRAINT(OP, C) \
753 ((C) == 'Q' ? (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) : \
756 /* Given an rtx X being reloaded into a reg required to be
757 in class CLASS, return the class of reg to actually use.
758 In general this is just CLASS; but on some machines
759 in some cases it is preferable to use a more restrictive class.
760 On the 68000 series, use a data reg if possible when the
761 value is a constant in the range where moveq could be used
762 and we ensure that QImodes are reloaded into data regs.
763 Also, if a floating constant needs reloading, put it in memory.
764 Don't do this for !G constants, since all patterns in the md file
765 expect them to be loaded into a register via fpmovecr. See above. */
767 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
768 ((GET_CODE (X) == CONST_INT \
769 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
770 && (CLASS) != ADDR_REGS) \
772 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
774 : (GET_CODE (X) == CONST_DOUBLE \
775 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
776 ? (! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G') \
777 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
778 ? FP_REGS : NO_REGS) \
781 /* Return the maximum number of consecutive registers
782 needed to represent mode MODE in a register of class CLASS. */
783 /* On the 68000, this is the size of MODE in words,
784 except in the FP regs, where a single reg is always enough. */
785 #ifndef SUPPORT_SUN_FPA
787 #define CLASS_MAX_NREGS(CLASS, MODE) \
788 ((CLASS) == FP_REGS ? 1 \
789 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
791 /* Moves between fp regs and other regs are two insns. */
792 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
793 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
794 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
797 #else /* defined SUPPORT_SUN_FPA */
799 #define CLASS_MAX_NREGS(CLASS, MODE) \
800 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
801 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
803 /* Moves between fp regs and other regs are two insns. */
804 /* Likewise for high fpa regs and other regs. */
805 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
806 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
807 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
808 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
809 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
812 #endif /* define SUPPORT_SUN_FPA */
814 /* Stack layout; function entry, exit and calling. */
816 /* Define this if pushing a word on the stack
817 makes the stack pointer a smaller address. */
818 #define STACK_GROWS_DOWNWARD
820 /* Nonzero if we need to generate stack-probe insns.
821 On most systems they are not needed.
822 When they are needed, define this as the stack offset to probe at. */
825 /* Define this if the nominal address of the stack frame
826 is at the high-address end of the local variables;
827 that is, each additional local variable allocated
828 goes at a more negative offset in the frame. */
829 #define FRAME_GROWS_DOWNWARD
831 /* Offset within stack frame to start allocating local variables at.
832 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
833 first local allocated. Otherwise, it is the offset to the BEGINNING
834 of the first local allocated. */
835 #define STARTING_FRAME_OFFSET 0
837 /* If we generate an insn to push BYTES bytes,
838 this says how many the stack pointer really advances by.
839 On the 68000, sp@- in a byte insn really pushes a word.
840 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
841 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
843 /* Offset of first parameter from the argument pointer register value. */
844 #define FIRST_PARM_OFFSET(FNDECL) 8
846 /* Value is the number of byte of arguments automatically
847 popped when returning from a subroutine call.
848 FUNDECL is the declaration node of the function (as a tree),
849 FUNTYPE is the data type of the function (as a tree),
850 or for a library call it is an identifier node for the subroutine name.
851 SIZE is the number of bytes of arguments passed on the stack.
853 On the 68000, the RTS insn cannot pop anything.
854 On the 68010, the RTD insn may be used to pop them if the number
855 of args is fixed, but if the number is variable then the caller
856 must pop them all. RTD can't be used for library calls now
857 because the library is compiled with the Unix compiler.
858 Use of RTD is a selectable option, since it is incompatible with
859 standard Unix calling sequences. If the option is not selected,
860 the caller must always pop the args. */
862 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
863 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
864 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
865 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
866 == void_type_node))) \
869 /* Define how to find the value returned by a function.
870 VALTYPE is the data type of the value (as a tree).
871 If the precise function being called is known, FUNC is its FUNCTION_DECL;
872 otherwise, FUNC is 0. */
874 /* On the 68000 the return value is in D0 regardless. */
876 #define FUNCTION_VALUE(VALTYPE, FUNC) \
877 gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
879 /* Define how to find the value returned by a library function
880 assuming the value has mode MODE. */
882 /* On the 68000 the return value is in D0 regardless. */
884 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
886 /* 1 if N is a possible register number for a function value.
887 On the 68000, d0 is the only register thus used. */
889 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
891 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
892 more than one register. */
894 #define NEEDS_UNTYPED_CALL 0
896 /* Define this if PCC uses the nonreentrant convention for returning
897 structure and union values. */
899 #define PCC_STATIC_STRUCT_RETURN
901 /* 1 if N is a possible register number for function argument passing.
902 On the 68000, no registers are used in this way. */
904 #define FUNCTION_ARG_REGNO_P(N) 0
906 /* Define a data type for recording info about an argument list
907 during the scan of that argument list. This data type should
908 hold all necessary information about the function itself
909 and about the args processed so far, enough to enable macros
910 such as FUNCTION_ARG to determine where the next arg should go.
912 On the m68k, this is a single integer, which is a number of bytes
913 of arguments scanned so far. */
915 #define CUMULATIVE_ARGS int
917 /* Initialize a variable CUM of type CUMULATIVE_ARGS
918 for a call to a function whose data type is FNTYPE.
919 For a library call, FNTYPE is 0.
921 On the m68k, the offset starts at 0. */
923 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
926 /* Update the data in CUM to advance over an argument
927 of mode MODE and data type TYPE.
928 (TYPE is null for libcalls where that information may not be available.) */
930 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
931 ((CUM) += ((MODE) != BLKmode \
932 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
933 : (int_size_in_bytes (TYPE) + 3) & ~3))
935 /* Define where to put the arguments to a function.
936 Value is zero to push the argument on the stack,
937 or a hard register in which to store the argument.
939 MODE is the argument's machine mode.
940 TYPE is the data type of the argument (as a tree).
941 This is null for libcalls where that information may
943 CUM is a variable of type CUMULATIVE_ARGS which gives info about
944 the preceding args and about the function being called.
945 NAMED is nonzero if this argument is a named parameter
946 (otherwise it is an extra parameter matching an ellipsis). */
948 /* On the 68000 all args are pushed, except if -mregparm is specified
949 then the first two words of arguments are passed in d0, d1.
950 *NOTE* -mregparm does not work.
951 It exists only to test register calling conventions. */
953 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
954 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
956 /* For an arg passed partly in registers and partly in memory,
957 this is the number of registers used.
958 For args passed entirely in registers or entirely in memory, zero. */
960 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
961 ((TARGET_REGPARM && (CUM) < 8 \
962 && 8 < ((CUM) + ((MODE) == BLKmode \
963 ? int_size_in_bytes (TYPE) \
964 : GET_MODE_SIZE (MODE)))) \
967 /* Generate the assembly code for function entry. */
968 #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE)
970 /* Output assembler code to FILE to increment profiler label # LABELNO
971 for profiling a function entry. */
973 #define FUNCTION_PROFILER(FILE, LABELNO) \
974 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
976 /* Output assembler code to FILE to initialize this source file's
977 basic block profiling info, if that has not already been done. */
979 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
982 switch (profile_block_flag) \
985 asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \
990 asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
991 (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \
997 /* Output assembler code to FILE to increment the counter for
998 the BLOCKNO'th basic block in this source file. */
1000 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1003 switch (profile_block_flag) \
1006 asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \
1011 asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \
1017 /* Output assembler code to FILE to indicate return from
1018 a function during basic block profiling. */
1020 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1021 asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n");
1023 /* Save all registers which may be clobbered by a function call. */
1026 #define MACHINE_STATE_SAVE(id) \
1029 asm ("sub.l 20,%sp"); \
1030 asm ("movm.l &0x0303,4(%sp)"); \
1031 asm ("move.w %ccr,%d0"); \
1032 asm ("movm.l &0x0001,(%sp)"); \
1036 asm ("move.w %ccr,-(%sp)"); \
1037 asm ("movm.l &0xc0c0,-(%sp)"); \
1040 #define MACHINE_STATE_SAVE(id) \
1043 asm ("subl 20,sp"); \
1044 asm ("movml d0/d1/a0/a1,sp@(4)"); \
1045 asm ("movew cc,d0"); \
1046 asm ("movml d0,sp@"); \
1050 asm ("movew cc,sp@-"); \
1051 asm ("moveml d0/d1/a0/a1,sp@-"); \
1055 /* Restore all registers saved by MACHINE_STATE_SAVE. */
1058 #define MACHINE_STATE_RESTORE(id) \
1061 asm ("movm.l (%sp),&0x0001"); \
1062 asm ("move.w %d0,%ccr"); \
1063 asm ("movm.l 4(%sp),&0x0303"); \
1064 asm ("add.l 20,%sp"); \
1068 asm ("movm.l (%sp)+,&0x0303"); \
1069 asm ("move.w (%sp)+,%ccr"); \
1072 #define MACHINE_STATE_RESTORE(id) \
1075 asm ("movml sp@,d0"); \
1076 asm ("movew d0,cc"); \
1077 asm ("movml sp@(4),d0/d1/a0/a1"); \
1078 asm ("addl 20,sp"); \
1082 asm ("moveml sp@+,d0/d1/a0/a1"); \
1083 asm ("movew sp@+,cc"); \
1087 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1088 the stack pointer does not matter. The value is tested only in
1089 functions that have frame pointers.
1090 No definition is equivalent to always zero. */
1092 #define EXIT_IGNORE_STACK 1
1094 /* Generate the assembly code for function exit. */
1095 #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE)
1097 /* This is a hook for other tm files to change. */
1098 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1100 /* Determine if the epilogue should be output as RTL.
1101 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1102 #define USE_RETURN_INSN use_return_insn ()
1104 /* Store in the variable DEPTH the initial difference between the
1105 frame pointer reg contents and the stack pointer reg contents,
1106 as of the start of the function body. This depends on the layout
1107 of the fixed parts of the stack frame and on how registers are saved.
1109 On the 68k, if we have a frame, we must add one word to its length
1110 to allow for the place that a6 is stored when we do have a frame pointer.
1111 Otherwise, we would need to compute the offset from the frame pointer
1112 of a local variable as a function of frame_pointer_needed, which
1115 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1118 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1119 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1121 for (regno = 0; regno < 16; regno++) \
1122 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1124 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1125 + (get_frame_size () == 0 ? 0 : 4)); \
1128 /* Output assembler code for a block containing the constant parts
1129 of a trampoline, leaving space for the variable parts. */
1131 /* On the 68k, the trampoline looks like this:
1135 WARNING: Targets that may run on 68040+ cpus must arrange for
1136 the instruction cache to be flushed. Previous incarnations of
1137 the m68k trampoline code attempted to get around this by either
1138 using an out-of-line transfer function or pc-relative data, but
1139 the fact remains that the code to jump to the transfer function
1140 or the code to load the pc-relative data needs to be flushed
1141 just as much as the "variable" portion of the trampoline.
1142 Recognizing that a cache flush is going to be required anyway,
1143 dispense with such notions and build a smaller trampoline. */
1145 /* Since more instructions are required to move a template into
1146 place than to create it on the spot, don't use a template. */
1148 /* Length in units of the trampoline for entering a nested function. */
1150 #define TRAMPOLINE_SIZE 12
1152 /* Alignment required for a trampoline in bits. */
1154 #define TRAMPOLINE_ALIGNMENT 16
1156 /* Targets redefine this to invoke code to either flush the cache,
1157 or enable stack execution (or both). */
1159 #ifndef FINALIZE_TRAMPOLINE
1160 #define FINALIZE_TRAMPOLINE(TRAMP)
1163 /* Emit RTL insns to initialize the variable parts of a trampoline.
1164 FNADDR is an RTX for the address of the function's pure code.
1165 CXT is an RTX for the static chain value for the function. */
1167 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1169 emit_move_insn (gen_rtx (MEM, HImode, TRAMP), GEN_INT(0x207C)); \
1170 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \
1171 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), \
1173 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), FNADDR); \
1174 FINALIZE_TRAMPOLINE(TRAMP); \
1177 /* This is the library routine that is used
1178 to transfer control from the trampoline
1179 to the actual nested function.
1180 It is defined for backward compatibility,
1181 for linking with object code that used the old
1182 trampoline definition. */
1184 /* A colon is used with no explicit operands
1185 to cause the template string to be scanned for %-constructs. */
1186 /* The function name __transfer_from_trampoline is not actually used.
1187 The function definition just permits use of "asm with operands"
1188 (though the operand list is empty). */
1189 #define TRANSFER_FROM_TRAMPOLINE \
1191 __transfer_from_trampoline () \
1193 register char *a0 asm ("%a0"); \
1194 asm (GLOBAL_ASM_OP " ___trampoline"); \
1195 asm ("___trampoline:"); \
1196 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1197 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1201 /* Addressing modes, and classification of registers for them. */
1203 #define HAVE_POST_INCREMENT
1204 /* #define HAVE_POST_DECREMENT */
1206 #define HAVE_PRE_DECREMENT
1207 /* #define HAVE_PRE_INCREMENT */
1209 /* Macros to check register numbers against specific register classes. */
1211 /* These assume that REGNO is a hard or pseudo reg number.
1212 They give nonzero only if REGNO is a hard reg of the suitable class
1213 or a pseudo reg currently allocated to a suitable hard reg.
1214 Since they use reg_renumber, they are safe only once reg_renumber
1215 has been allocated, which happens in local-alloc.c. */
1217 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1218 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1219 #define REGNO_OK_FOR_BASE_P(REGNO) \
1220 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1221 #define REGNO_OK_FOR_DATA_P(REGNO) \
1222 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1223 #define REGNO_OK_FOR_FP_P(REGNO) \
1224 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1225 #ifdef SUPPORT_SUN_FPA
1226 #define REGNO_OK_FOR_FPA_P(REGNO) \
1227 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1230 /* Now macros that check whether X is a register and also,
1231 strictly, whether it is in a specified class.
1233 These macros are specific to the 68000, and may be used only
1234 in code for printing assembler insns and in conditions for
1235 define_optimization. */
1237 /* 1 if X is a data register. */
1239 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1241 /* 1 if X is an fp register. */
1243 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1245 /* 1 if X is an address register */
1247 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1249 #ifdef SUPPORT_SUN_FPA
1250 /* 1 if X is a register in the Sun FPA. */
1251 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1253 /* Answer must be no if we don't have an FPA. */
1254 #define FPA_REG_P(X) 0
1257 /* Maximum number of registers that can appear in a valid memory address. */
1259 #define MAX_REGS_PER_ADDRESS 2
1261 /* Recognize any constant value that is a valid address. */
1263 #define CONSTANT_ADDRESS_P(X) \
1264 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1265 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1266 || GET_CODE (X) == HIGH)
1268 /* Nonzero if the constant value X is a legitimate general operand.
1269 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1271 #define LEGITIMATE_CONSTANT_P(X) 1
1273 /* Nonzero if the constant value X is a legitimate general operand
1274 when generating PIC code. It is given that flag_pic is on and
1275 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1277 #define LEGITIMATE_PIC_OPERAND_P(X) \
1278 ((! symbolic_operand (X, VOIDmode) \
1279 && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \
1280 && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \
1281 && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \
1283 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
1285 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1286 and check its validity for a certain class.
1287 We have two alternate definitions for each of them.
1288 The usual definition accepts all pseudo regs; the other rejects
1289 them unless they have been allocated suitable hard regs.
1290 The symbol REG_OK_STRICT causes the latter definition to be used.
1292 Most source files want to accept pseudo regs in the hope that
1293 they will get allocated to the class that the insn wants them to be in.
1294 Source files for reload pass need to be strict.
1295 After reload, it makes no difference, since pseudo regs have
1296 been eliminated by then. */
1298 #ifndef REG_OK_STRICT
1300 /* Nonzero if X is a hard reg that can be used as an index
1301 or if it is a pseudo reg. */
1302 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1303 /* Nonzero if X is a hard reg that can be used as a base reg
1304 or if it is a pseudo reg. */
1305 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1309 /* Nonzero if X is a hard reg that can be used as an index. */
1310 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1311 /* Nonzero if X is a hard reg that can be used as a base reg. */
1312 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1316 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1317 that is a valid memory address for an instruction.
1318 The MODE argument is the machine mode for the MEM expression
1319 that wants to use this address.
1321 When generating PIC, an address involving a SYMBOL_REF is legitimate
1322 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1323 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1324 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1326 Likewise for a LABEL_REF when generating PIC.
1328 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1330 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1331 also makes function inlining work when inline functions are called with
1332 arguments that are SUBREGs. */
1334 #define LEGITIMATE_BASE_REG_P(X) \
1335 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1336 || (GET_CODE (X) == SUBREG \
1337 && GET_CODE (SUBREG_REG (X)) == REG \
1338 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1340 #define INDIRECTABLE_1_ADDRESS_P(X) \
1341 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1342 || LEGITIMATE_BASE_REG_P (X) \
1343 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1344 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1345 || (GET_CODE (X) == PLUS \
1346 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1347 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1348 && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \
1349 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1350 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1351 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1352 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \
1355 /* This should replace the last two (non-pic) lines
1356 except that Sun's assembler does not seem to handle such operands. */
1357 && (TARGET_68020
? CONSTANT_ADDRESS_P (XEXP (X
, 1)) \
1358 : (GET_CODE (XEXP (X
, 1)) == CONST_INT \
1359 && ((unsigned) INTVAL (XEXP (X
, 1)) + 0x8000) < 0x10000))))
1363 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1364 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1366 /* Only labels on dispatch tables are valid for indexing from. */
1367 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1369 if (GET_CODE (X) == LABEL_REF \
1370 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1371 && GET_CODE (temp) == JUMP_INSN \
1372 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1373 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1375 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1377 #define GO_IF_INDEXING(X, ADDR) \
1378 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1379 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1380 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1381 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1383 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1384 { GO_IF_INDEXING (X, ADDR); \
1385 if (GET_CODE (X) == PLUS) \
1386 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1387 && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \
1388 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1389 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1390 && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \
1391 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1393 #define LEGITIMATE_INDEX_REG_P(X) \
1394 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1395 || (GET_CODE (X) == SIGN_EXTEND \
1396 && GET_CODE (XEXP (X, 0)) == REG \
1397 && GET_MODE (XEXP (X, 0)) == HImode \
1398 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1399 || (GET_CODE (X) == SUBREG \
1400 && GET_CODE (SUBREG_REG (X)) == REG \
1401 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1403 #define LEGITIMATE_INDEX_P(X) \
1404 (LEGITIMATE_INDEX_REG_P (X) \
1405 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1406 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1407 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1408 && (INTVAL (XEXP (X, 1)) == 2 \
1409 || INTVAL (XEXP (X, 1)) == 4 \
1410 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1412 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1413 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1414 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1415 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1416 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1417 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1418 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1421 /* Don't call memory_address_noforce for the address to fetch
1422 the switch offset. This address is ok as it stands (see above),
1423 but memory_address_noforce would alter it. */
1424 #define PIC_CASE_VECTOR_ADDRESS(index) index
1426 /* Try machine-dependent ways of modifying an illegitimate address
1427 to be legitimate. If we find one, return the new, valid address.
1428 This macro is used in only one place: `memory_address' in explow.c.
1430 OLDX is the address as it was before break_out_memory_refs was called.
1431 In some cases it is useful to look at this to decide what needs to be done.
1433 MODE and WIN are passed so that this macro can use
1434 GO_IF_LEGITIMATE_ADDRESS.
1436 It is always safe for this macro to do nothing. It exists to recognize
1437 opportunities to optimize the output.
1439 For the 68000, we handle X+REG by loading X into a register R and
1440 using R+REG. R will go in an address reg and indexing will be used.
1441 However, if REG is a broken-out memory address or multiplication,
1442 nothing needs to be done because REG can certainly go in an address reg. */
1444 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1445 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1446 { register int ch = (X) != (OLDX); \
1447 if (GET_CODE (X) == PLUS) \
1449 if (GET_CODE (XEXP (X, 0)) == MULT) \
1450 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1451 if (GET_CODE (XEXP (X, 1)) == MULT) \
1452 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1453 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1454 && GET_CODE (XEXP (X, 0)) == REG) \
1456 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1457 if (GET_CODE (XEXP (X, 0)) == REG \
1458 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1459 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1460 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1461 { register rtx temp = gen_reg_rtx (Pmode); \
1462 register rtx val = force_operand (XEXP (X, 1), 0); \
1463 emit_move_insn (temp, val); \
1465 XEXP (X, 1) = temp; \
1467 else if (GET_CODE (XEXP (X, 1)) == REG \
1468 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1469 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1470 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1471 { register rtx temp = gen_reg_rtx (Pmode); \
1472 register rtx val = force_operand (XEXP (X, 0), 0); \
1473 emit_move_insn (temp, val); \
1475 XEXP (X, 0) = temp; \
1478 /* Go to LABEL if ADDR (a legitimate address expression)
1479 has an effect that depends on the machine mode it is used for.
1480 On the 68000, only predecrement and postincrement address depend thus
1481 (the amount of decrement or increment being the length of the operand). */
1483 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1484 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1486 /* Specify the machine mode that this machine uses
1487 for the index in the tablejump instruction. */
1488 #define CASE_VECTOR_MODE HImode
1490 /* Define this if the tablejump instruction expects the table
1491 to contain offsets from the address of the table.
1492 Do not define this if the table should contain absolute addresses. */
1493 #define CASE_VECTOR_PC_RELATIVE
1495 /* Specify the tree operation to be used to convert reals to integers. */
1496 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1498 /* This is the kind of divide that is easiest to do in the general case. */
1499 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1501 /* Define this as 1 if `char' should by default be signed; else as 0. */
1502 #define DEFAULT_SIGNED_CHAR 1
1504 /* Don't cse the address of the function being compiled. */
1505 #define NO_RECURSIVE_FUNCTION_CSE
1507 /* Max number of bytes we can move from memory to memory
1508 in one reasonably fast instruction. */
1511 /* Define this if zero-extension is slow (more than one real instruction). */
1512 #define SLOW_ZERO_EXTEND
1514 /* Nonzero if access to memory by bytes is slow and undesirable. */
1515 #define SLOW_BYTE_ACCESS 0
1517 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1518 is done just by pretending it is already truncated. */
1519 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1521 /* We assume that the store-condition-codes instructions store 0 for false
1522 and some other value for true. This is the value stored for true. */
1524 #define STORE_FLAG_VALUE -1
1526 /* When a prototype says `char' or `short', really pass an `int'. */
1527 #define PROMOTE_PROTOTYPES
1529 /* Specify the machine mode that pointers have.
1530 After generation of rtl, the compiler makes no further distinction
1531 between pointers and any other objects of this machine mode. */
1532 #define Pmode SImode
1534 /* A function address in a call instruction
1535 is a byte address (for indexing purposes)
1536 so give the MEM rtx a byte's mode. */
1537 #define FUNCTION_MODE QImode
1539 /* Compute the cost of computing a constant rtl expression RTX
1540 whose rtx-code is CODE. The body of this macro is a portion
1541 of a switch statement. If the code is computed here,
1542 return it with a return statement. Otherwise, break from the switch. */
1544 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1546 /* Constant zero is super cheap due to clr instruction. */ \
1547 if (RTX == const0_rtx) return 0; \
1548 /* if ((OUTER_CODE) == SET) */ \
1549 return const_int_cost(RTX); \
1554 case CONST_DOUBLE: \
1557 /* Compute the cost of various arithmetic operations.
1558 These are vaguely right for a 68020. */
1559 /* The costs for long multiply have been adjusted to
1560 work properly in synth_mult on the 68020,
1561 relative to an average of the time for add and the time for shift,
1562 taking away a little more because sometimes move insns are needed. */
1563 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1564 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1565 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1566 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1568 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1570 /* An lea costs about three times as much as a simple add. */ \
1571 if (GET_MODE (X) == SImode \
1572 && GET_CODE (XEXP (X, 1)) == REG \
1573 && GET_CODE (XEXP (X, 0)) == MULT \
1574 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1575 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1576 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1577 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1578 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1579 return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1585 return COSTS_N_INSNS(1); \
1586 if (! TARGET_68020) \
1588 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1590 if (INTVAL (XEXP (X, 1)) < 16) \
1591 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \
1593 /* We're using clrw + swap for these cases. */ \
1594 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
1596 return COSTS_N_INSNS (10); /* worst case */ \
1598 /* A shift by a big integer takes an extra instruction. */ \
1599 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1600 && (INTVAL (XEXP (X, 1)) == 16)) \
1601 return COSTS_N_INSNS (2); /* clrw;swap */ \
1602 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1603 && !(INTVAL (XEXP (X, 1)) > 0 \
1604 && INTVAL (XEXP (X, 1)) <= 8)) \
1605 return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1608 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1609 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \
1610 && GET_MODE (X) == SImode) \
1611 return COSTS_N_INSNS (MULW_COST); \
1612 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1613 return COSTS_N_INSNS (MULW_COST); \
1615 return COSTS_N_INSNS (MULL_COST); \
1620 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1621 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \
1622 return COSTS_N_INSNS (43); /* div.l */
1624 /* Tell final.c how to eliminate redundant test instructions. */
1626 /* Here we define machine-dependent flags and fields in cc_status
1627 (see `conditions.h'). */
1629 /* Set if the cc value is actually in the 68881, so a floating point
1630 conditional branch must be output. */
1631 #define CC_IN_68881 04000
1633 /* Store in cc_status the expressions that the condition codes will
1634 describe after execution of an instruction whose pattern is EXP.
1635 Do not alter them if the instruction would not alter the cc's. */
1637 /* On the 68000, all the insns to store in an address register fail to
1638 set the cc's. However, in some cases these instructions can make it
1639 possibly invalid to use the saved cc's. In those cases we clear out
1640 some or all of the saved cc's so they won't be used. */
1642 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1644 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1645 { if (cc_prev_status.flags & CC_IN_68881) \
1647 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1651 /* Control the assembler format that we output. */
1653 /* Output at beginning of assembler file. */
1655 #define ASM_FILE_START(FILE) \
1656 fprintf (FILE, "#NO_APP\n");
1658 /* Output to assembler file text saying following lines
1659 may contain character constants, extra white space, comments, etc. */
1661 #define ASM_APP_ON "#APP\n"
1663 /* Output to assembler file text saying following lines
1664 no longer contain unusual constructs. */
1666 #define ASM_APP_OFF "#NO_APP\n"
1668 /* Output before read-only data. */
1670 #define TEXT_SECTION_ASM_OP ".text"
1672 /* Output before writable data. */
1674 #define DATA_SECTION_ASM_OP ".data"
1676 /* Here are four prefixes that are used by asm_fprintf to
1677 facilitate customization for alternate assembler syntaxes.
1678 Machines with no likelihood of an alternate syntax need not
1679 define these and need not use asm_fprintf. */
1681 /* The prefix for register names. Note that REGISTER_NAMES
1682 is supposed to include this prefix. */
1684 #define REGISTER_PREFIX ""
1686 /* The prefix for local labels. You should be able to define this as
1687 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1688 without having to make any other changes to account for the specific
1689 definition. Note it is a string literal, not interpreted by printf
1692 #define LOCAL_LABEL_PREFIX ""
1694 /* The prefix to add to user-visible assembler symbols. */
1696 #define USER_LABEL_PREFIX "_"
1698 /* The prefix for immediate operands. */
1700 #define IMMEDIATE_PREFIX "#"
1702 /* How to refer to registers in assembler output.
1703 This sequence is indexed by compiler's hard-register-number (see above). */
1705 #ifndef SUPPORT_SUN_FPA
1707 #define REGISTER_NAMES \
1708 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1709 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1710 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1712 #else /* SUPPORTED_SUN_FPA */
1714 #define REGISTER_NAMES \
1715 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1716 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1717 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1718 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1719 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1720 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1721 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1723 #endif /* defined SUPPORT_SUN_FPA */
1725 /* How to renumber registers for dbx and gdb.
1726 On the Sun-3, the floating point registers have numbers
1727 18 to 25, not 16 to 23 as they do in the compiler. */
1729 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1731 /* This is how to output the definition of a user-level label named NAME,
1732 such as the label on a static function or variable NAME. */
1734 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1735 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1737 /* This is how to output a command to make the user-level label named NAME
1738 defined for reference from other files. */
1740 #define GLOBAL_ASM_OP ".globl"
1741 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1742 do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \
1743 assemble_name (FILE, NAME); \
1744 fputs ("\n", FILE);} while (0)
1746 /* This is how to output a reference to a user-level label named NAME.
1747 `assemble_name' uses this. */
1749 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1750 asm_fprintf (FILE, "%0U%s", NAME)
1752 /* This is how to output an internal numbered label where
1753 PREFIX is the class of label and NUM is the number within the class. */
1755 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1756 asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
1758 /* This is how to store into the string LABEL
1759 the symbol_ref name of an internal numbered label where
1760 PREFIX is the class of label and NUM is the number within the class.
1761 This is suitable for output with `assemble_name'. */
1763 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1764 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
1766 /* This is how to output a `long double' extended real constant. */
1768 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1770 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1771 if (sizeof (int) == sizeof (long)) \
1772 fprintf (FILE, "\t.long 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \
1774 fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \
1777 /* This is how to output an assembler line defining a `double' constant. */
1779 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1780 do { char dstr[30]; \
1781 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1782 fprintf (FILE, "\t.double 0r%s\n", dstr); \
1785 /* This is how to output an assembler line defining a `float' constant. */
1787 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1789 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1790 if (sizeof (int) == sizeof (long)) \
1791 fprintf (FILE, "\t.long 0x%x\n", l); \
1793 fprintf (FILE, "\t.long 0x%lx\n", l); \
1796 /* This is how to output an assembler line defining an `int' constant. */
1798 #define ASM_OUTPUT_INT(FILE,VALUE) \
1799 ( fprintf (FILE, "\t.long "), \
1800 output_addr_const (FILE, (VALUE)), \
1801 fprintf (FILE, "\n"))
1803 /* Likewise for `char' and `short' constants. */
1805 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1806 ( fprintf (FILE, "\t.word "), \
1807 output_addr_const (FILE, (VALUE)), \
1808 fprintf (FILE, "\n"))
1810 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1811 ( fprintf (FILE, "\t.byte "), \
1812 output_addr_const (FILE, (VALUE)), \
1813 fprintf (FILE, "\n"))
1815 /* This is how to output an assembler line for a numeric constant byte. */
1817 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1818 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1820 /* This is how to output an insn to push a register on the stack.
1821 It need not be very fast code. */
1823 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1824 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1826 /* This is how to output an insn to pop a register from the stack.
1827 It need not be very fast code. */
1829 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1830 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1832 /* This is how to output an element of a case-vector that is absolute.
1833 (The 68000 does not use such vectors,
1834 but we must define this macro anyway.) */
1836 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1837 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1839 /* This is how to output an element of a case-vector that is relative. */
1841 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1842 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1844 /* This is how to output an assembler line
1845 that says to advance the location counter
1846 to a multiple of 2**LOG bytes. */
1848 /* We don't have a way to align to more than a two-byte boundary, so do the
1849 best we can and don't complain. */
1850 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1852 fprintf (FILE, "\t.even\n");
1854 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1855 fprintf (FILE, "\t.skip %u\n", (SIZE))
1857 /* This says how to output an assembler line
1858 to define a global common symbol. */
1860 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1861 ( fputs (".comm ", (FILE)), \
1862 assemble_name ((FILE), (NAME)), \
1863 fprintf ((FILE), ",%u\n", (ROUNDED)))
1865 /* This says how to output an assembler line
1866 to define a local common symbol. */
1868 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1869 ( fputs (".lcomm ", (FILE)), \
1870 assemble_name ((FILE), (NAME)), \
1871 fprintf ((FILE), ",%u\n", (ROUNDED)))
1873 /* Store in OUTPUT a string (made with alloca) containing
1874 an assembler-name for a local static variable named NAME.
1875 LABELNO is an integer which is different for each call. */
1877 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1878 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1879 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1881 /* Define the parentheses used to group arithmetic operations
1882 in assembler code. */
1884 #define ASM_OPEN_PAREN "("
1885 #define ASM_CLOSE_PAREN ")"
1887 /* Define results of standard character escape sequences. */
1888 #define TARGET_BELL 007
1889 #define TARGET_BS 010
1890 #define TARGET_TAB 011
1891 #define TARGET_NEWLINE 012
1892 #define TARGET_VT 013
1893 #define TARGET_FF 014
1894 #define TARGET_CR 015
1896 /* Output a float value (represented as a C double) as an immediate operand.
1897 This macro is a 68k-specific macro. */
1899 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1904 REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
1905 asm_fprintf ((FILE), "%I0r%s", dstr); \
1910 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1911 if (sizeof (int) == sizeof (long)) \
1912 asm_fprintf ((FILE), "%I0x%x", l); \
1914 asm_fprintf ((FILE), "%I0x%lx", l); \
1918 /* Output a double value (represented as a C double) as an immediate operand.
1919 This macro is a 68k-specific macro. */
1920 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1921 do { char dstr[30]; \
1922 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1923 asm_fprintf (FILE, "%I0r%s", dstr); \
1926 /* Note, long double immediate operands are not actually
1927 generated by m68k.md. */
1928 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1929 do { char dstr[30]; \
1930 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1931 asm_fprintf (FILE, "%I0r%s", dstr); \
1934 /* Print operand X (an rtx) in assembler syntax to file FILE.
1935 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1936 For `%' followed by punctuation, CODE is the punctuation and X is null.
1938 On the 68000, we use several CODE characters:
1939 '.' for dot needed in Motorola-style opcode names.
1940 '-' for an operand pushing on the stack:
1941 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1942 '+' for an operand pushing on the stack:
1943 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1944 '@' for a reference to the top word on the stack:
1945 sp@, (sp) or (%sp) depending on the style of syntax.
1946 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1947 but & in SGS syntax).
1948 '!' for the fpcr register (used in some float-to-fixed conversions).
1949 '$' for the letter `s' in an op code, but only on the 68040.
1950 '&' for the letter `d' in an op code, but only on the 68040.
1951 '/' for register prefix needed by longlong.h.
1953 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1954 'd' to force memory addressing to be absolute, not relative.
1955 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1956 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
1957 than directly). Second part of 'y' below.
1958 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1959 or print pair of registers as rx:ry.
1960 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
1961 CONST_DOUBLE's as SunFPA constant RAM registers if
1962 possible, so it should not be used except for the SunFPA. */
1964 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1965 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1966 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1967 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1969 /* A C compound statement to output to stdio stream STREAM the
1970 assembler syntax for an instruction operand X. X is an RTL
1973 CODE is a value that can be used to specify one of several ways
1974 of printing the operand. It is used when identical operands
1975 must be printed differently depending on the context. CODE
1976 comes from the `%' specification that was used to request
1977 printing of the operand. If the specification was just `%DIGIT'
1978 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1979 is the ASCII code for LTR.
1981 If X is a register, this macro should print the register's name.
1982 The names can be found in an array `reg_names' whose type is
1983 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1985 When the machine description has a specification `%PUNCT' (a `%'
1986 followed by a punctuation character), this macro is called with
1987 a null pointer for X and the punctuation character for CODE.
1989 See m68k.c for the m68k specific codes. */
1991 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1993 /* A C compound statement to output to stdio stream STREAM the
1994 assembler syntax for an instruction operand that is a memory
1995 reference whose address is ADDR. ADDR is an RTL expression.
1997 On some machines, the syntax for a symbolic address depends on
1998 the section that the address refers to. On these machines,
1999 define the macro `ENCODE_SECTION_INFO' to store the information
2000 into the `symbol_ref', and then check for it here. */
2002 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2005 /* Definitions for generating bytecode */
2007 /* Just so it's known this target is supported by the bytecode generator.
2008 If this define isn't found anywhere in the target config files, then
2009 dummy stubs are supplied by bytecode.h, and any attempt to use
2010 -fbytecode will result in an error message. */
2012 #define TARGET_SUPPORTS_BYTECODE
2014 /* Minimal segment alignment within sections is 8 units. */
2015 #define MACHINE_SEG_ALIGN 3
2017 /* Integer alignment is two units. */
2020 /* Pointer alignment is eight units. */
2023 /* Global symbols begin with `_' */
2024 #define NAMES_HAVE_UNDERSCORES
2026 /* BC_xxx below are similar to their ASM_xxx counterparts above. */
2027 #define BC_GLOBALIZE_LABEL(FP, NAME) bc_globalize_label(NAME)
2029 #define BC_OUTPUT_COMMON(FP, NAME, SIZE, ROUNDED) \
2030 do { bc_emit_common(NAME, ROUNDED); bc_globalize_label(NAME); } while (0)
2032 #define BC_OUTPUT_BSS(FP, NAME, SIZE, ROUNDED) \
2033 do { bc_data (); bc_emit_labeldef(NAME); bc_emit_skip (SIZE); } while (0)
2035 #define BC_OUTPUT_LOCAL(FP, NAME, SIZE, ROUNDED) \
2036 bc_emit_common(NAME, ROUNDED)
2038 #define BC_OUTPUT_ALIGN(FP, ALIGN) bc_align(ALIGN)
2040 #define BC_OUTPUT_LABEL(FP, NAME) bc_emit_labeldef(NAME)
2042 #define BC_OUTPUT_SKIP(FP, SIZE) bc_emit_skip(SIZE)
2044 #define BC_OUTPUT_LABELREF(FP, NAME) \
2046 char *foo = (char *) xmalloc(strlen(NAME) + 2); \
2048 strcat(foo, NAME); \
2049 bc_emit_labelref (foo); \
2053 #define BC_OUTPUT_FLOAT(FP, VAL) \
2056 bc_emit ((char *) &F, sizeof F); \
2059 #define BC_OUTPUT_DOUBLE(FP, VAL) \
2062 bc_emit ((char *) &D, sizeof D); \
2065 #define BC_OUTPUT_BYTE(FP, VAL) \
2072 #define BC_OUTPUT_FILE ASM_OUTPUT_FILE
2073 #define BC_OUTPUT_ASCII ASM_OUTPUT_ASCII
2074 #define BC_OUTPUT_IDENT ASM_OUTPUT_IDENT
2076 /* Same as XSTR, but for bytecode */
2077 #define BCXSTR(RTX) ((RTX)->bc_label)
2080 /* Flush bytecode buffer onto file */
2081 #define BC_WRITE_FILE(FP) \
2083 fprintf (FP, ".text\n"); \
2084 bc_seg_write (bc_text_seg, FP); \
2085 fprintf(FP, "\n.data\n"); \
2086 bc_seg_write (bc_data_seg, FP); \
2087 bc_sym_write (FP); /* do .globl, .bss, etc. */ \
2090 /* Write one symbol */
2091 #define BC_WRITE_SEGSYM(SEGSYM, FP) \
2093 prsym (FP, (SEGSYM)->sym->name); \
2094 fprintf (FP, ":\n"); \
2098 /* Write one reloc entry */
2099 #define BC_WRITE_RELOC_ENTRY(SEGRELOC, FP, OFFSET) \
2101 fprintf (FP, "\t.long "); \
2102 prsym (FP, (SEGRELOC)->sym->name); \
2103 fprintf (FP, " + %d\n", OFFSET); \
2106 /* Start new line of bytecodes */
2107 #define BC_START_BYTECODE_LINE(FP) \
2109 fprintf (FP, "\t.byte"); \
2112 /* Write one bytecode */
2113 #define BC_WRITE_BYTECODE(SEP, VAL, FP) \
2115 fprintf (FP, "%c0x%02X", (SEP), (VAL) & 0xff); \
2118 /* Write one bytecode RTL entry */
2119 #define BC_WRITE_RTL(R, FP) \
2121 fprintf (FP, "%s+%d/0x%08X\n", (R)->label, (R)->offset, (R)->bc_label); \
2125 /* Emit function entry trampoline */
2126 #define BC_EMIT_TRAMPOLINE(TRAMPSEG, CALLINFO) \
2130 /* Push a reference to the callinfo structure. */ \
2131 insn = 0x4879; /* pea xxx.L */ \
2132 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2133 seg_refsym (TRAMPSEG, CALLINFO, 0); \
2135 /* Call __interp, pop arguments, and return. */ \
2136 insn = 0x4eb9; /* jsr xxx.L */ \
2137 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2138 seg_refsym (TRAMPSEG, "__callint", 0); \
2139 insn = 0x588f; /* addql #4, sp */ \
2140 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2141 insn = 0x4e75; /* rts */ \
2142 seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \
2148 #define VALIDATE_STACK() if (stack_depth < 0) abort ();
2151 #define VALIDATE_STACK() \
2152 fprintf (stderr, " %%%d%%", stack_depth);
2156 /* Define functions defined in aux-output.c and used in templates. */
2158 extern char *output_move_const_into_data_reg ();
2159 extern char *output_move_simode_const ();
2160 extern char *output_move_simode ();
2161 extern char *output_move_himode ();
2162 extern char *output_move_qimode ();
2163 extern char *output_move_stricthi ();
2164 extern char *output_move_strictqi ();
2165 extern char *output_move_double ();
2166 extern char *output_move_const_single ();
2167 extern char *output_move_const_double ();
2168 extern char *output_btst ();
2169 extern char *output_scc_di ();
2170 extern char *output_addsi3 ();
2172 /* Variables in m68k.c */
2173 extern char *m68k_align_loops_string
;
2174 extern char *m68k_align_jumps_string
;
2175 extern char *m68k_align_funcs_string
;
2176 extern int m68k_align_loops
;
2177 extern int m68k_align_jumps
;
2178 extern int m68k_align_funcs
;
2179 extern int m68k_last_compare_had_fp_operands
;