1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
45 /* Needed for use_return_insn. */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag
;
52 static rtx find_addr_reg
PARAMS ((rtx
));
53 static const char *singlemove_string
PARAMS ((rtx
*));
54 static void m68k_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
55 static void m68k_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
56 static void m68k_coff_asm_named_section
PARAMS ((const char *, unsigned int));
57 #ifdef CTOR_LIST_BEGIN
58 static void m68k_svr3_asm_out_constructor
PARAMS ((rtx
, int));
61 static void m68k_hp320_internal_label
PARAMS ((FILE *, const char *, unsigned long));
62 static void m68k_hp320_file_start
PARAMS ((void));
64 static void m68k_output_mi_thunk
PARAMS ((FILE *, tree
, HOST_WIDE_INT
,
65 HOST_WIDE_INT
, tree
));
66 static int m68k_save_reg
PARAMS ((unsigned int));
67 static int const_int_cost
PARAMS ((rtx
));
68 static bool m68k_rtx_costs
PARAMS ((rtx
, int, int, int *));
71 /* Alignment to use for loops and jumps */
72 /* Specify power of two alignment used for loops. */
73 const char *m68k_align_loops_string
;
74 /* Specify power of two alignment used for non-loop jumps. */
75 const char *m68k_align_jumps_string
;
76 /* Specify power of two alignment used for functions. */
77 const char *m68k_align_funcs_string
;
79 /* Specify power of two alignment used for loops. */
81 /* Specify power of two alignment used for non-loop jumps. */
83 /* Specify power of two alignment used for functions. */
86 /* Nonzero if the last compare/test insn had FP operands. The
87 sCC expanders peek at this to determine what to do for the
88 68060, which has no fsCC instructions. */
89 int m68k_last_compare_had_fp_operands
;
91 /* Initialize the GCC target structure. */
93 #if INT_OP_GROUP == INT_OP_DOT_WORD
94 #undef TARGET_ASM_ALIGNED_HI_OP
95 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
98 #if INT_OP_GROUP == INT_OP_NO_DOT
99 #undef TARGET_ASM_BYTE_OP
100 #define TARGET_ASM_BYTE_OP "\tbyte\t"
101 #undef TARGET_ASM_ALIGNED_HI_OP
102 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
103 #undef TARGET_ASM_ALIGNED_SI_OP
104 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
107 #if INT_OP_GROUP == INT_OP_DC
108 #undef TARGET_ASM_BYTE_OP
109 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
112 #undef TARGET_ASM_ALIGNED_SI_OP
113 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
116 #undef TARGET_ASM_UNALIGNED_HI_OP
117 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
118 #undef TARGET_ASM_UNALIGNED_SI_OP
119 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
121 #undef TARGET_ASM_FUNCTION_PROLOGUE
122 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
123 #undef TARGET_ASM_FUNCTION_EPILOGUE
124 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
126 #undef TARGET_ASM_INTERNAL_LABEL
127 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
130 #undef TARGET_ASM_OUTPUT_MI_THUNK
131 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
132 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
133 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
135 #undef TARGET_ASM_FILE_START_APP_OFF
136 #define TARGET_ASM_FILE_START_APP_OFF true
138 #undef TARGET_RTX_COSTS
139 #define TARGET_RTX_COSTS m68k_rtx_costs
141 struct gcc_target targetm
= TARGET_INITIALIZER
;
143 /* Sometimes certain combinations of command options do not make
144 sense on a particular target machine. You can define a macro
145 `OVERRIDE_OPTIONS' to take account of this. This macro, if
146 defined, is executed once just after all the command options have
149 Don't use this macro to turn on various extra optimizations for
150 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
160 /* Validate -malign-loops= value, or provide default */
161 m68k_align_loops
= def_align
;
162 if (m68k_align_loops_string
)
164 i
= atoi (m68k_align_loops_string
);
165 if (i
< 1 || i
> MAX_CODE_ALIGN
)
166 error ("-malign-loops=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
168 m68k_align_loops
= i
;
171 /* Validate -malign-jumps= value, or provide default */
172 m68k_align_jumps
= def_align
;
173 if (m68k_align_jumps_string
)
175 i
= atoi (m68k_align_jumps_string
);
176 if (i
< 1 || i
> MAX_CODE_ALIGN
)
177 error ("-malign-jumps=%d is not between 1 and %d", i
, MAX_CODE_ALIGN
);
179 m68k_align_jumps
= i
;
182 /* Validate -malign-functions= value, or provide default */
183 m68k_align_funcs
= def_align
;
184 if (m68k_align_funcs_string
)
186 i
= atoi (m68k_align_funcs_string
);
187 if (i
< 1 || i
> MAX_CODE_ALIGN
)
188 error ("-malign-functions=%d is not between 1 and %d",
191 m68k_align_funcs
= i
;
194 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
196 if (! TARGET_68020
&& flag_pic
== 2)
197 error("-fPIC is not currently supported on the 68000 or 68010\n");
199 /* ??? A historic way of turning on pic, or is this intended to
200 be an embedded thing that doesn't have the same name binding
201 significance that it does on hosted ELF systems? */
202 if (TARGET_PCREL
&& flag_pic
== 0)
205 /* Turn off function cse if we are doing PIC. We always want function call
206 to be done as `bsr foo@PLTPC', so it will force the assembler to create
207 the PLT entry for `foo'. Doing function cse will cause the address of
208 `foo' to be loaded into a register, which is exactly what we want to
209 avoid when we are doing PIC on svr4 m68k. */
211 flag_no_function_cse
= 1;
213 SUBTARGET_OVERRIDE_OPTIONS
;
215 /* Tell the compiler which flavor of XFmode we're using. */
216 real_format_for_mode
[XFmode
- QFmode
] = &ieee_extended_motorola_format
;
219 /* Return 1 if we need to save REGNO. */
221 m68k_save_reg (regno
)
224 if (flag_pic
&& current_function_uses_pic_offset_table
225 && regno
== PIC_OFFSET_TABLE_REGNUM
)
228 if (current_function_calls_eh_return
)
233 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
234 if (test
== INVALID_REGNUM
)
241 return (regs_ever_live
[regno
]
242 && !call_used_regs
[regno
]
243 && !fixed_regs
[regno
]
244 && !(regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
));
247 /* This function generates the assembly code for function entry.
248 STREAM is a stdio stream to output the code to.
249 SIZE is an int: how many units of temporary storage to allocate.
250 Refer to the array `regs_ever_live' to determine which registers
251 to save; `regs_ever_live[I]' is nonzero if register number I
252 is ever used in the function. This function is responsible for
253 knowing which registers should not be saved even if used. */
256 /* Note that the order of the bit mask for fmovem is the opposite
257 of the order for movem! */
262 m68k_output_function_prologue (stream
, size
)
267 register int mask
= 0;
268 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
270 /* unos stack probe */
273 fprintf (stream
, "\tmovel sp,a0\n");
274 fprintf (stream
, "\taddl $-" HOST_WIDE_INT_PRINT_DEC
",a0\n",
276 fprintf (stream
, "\ttstb (a0)\n");
279 fprintf (stream
, "\ttstb -" HOST_WIDE_INT_PRINT_DEC
"(sp)\n",
282 if (frame_pointer_needed
)
284 if (TARGET_68020
|| fsize
< 0x8000)
285 fprintf (stream
, "\tlink a6,$" HOST_WIDE_INT_PRINT_DEC
"\n", -fsize
);
288 "\tlink a6,$0\n\tsubl $" HOST_WIDE_INT_PRINT_DEC
",sp\n",
293 /* Adding negative number is faster on the 68040. */
294 if (fsize
+ 4 < 0x8000)
295 fprintf (stream
, "\tadd.w $" HOST_WIDE_INT_PRINT_DEC
",sp\n",
298 fprintf (stream
, "\tadd.l $" HOST_WIDE_INT_PRINT_DEC
",sp\n",
302 for (regno
= 16; regno
< 24; regno
++)
303 if (m68k_save_reg (regno
))
304 mask
|= 1 << (regno
- 16);
306 if ((mask
& 0xff) != 0)
307 fprintf (stream
, "\tfmovem $0x%x,-(sp)\n", mask
& 0xff);
310 for (regno
= 0; regno
< 16; regno
++)
311 if (m68k_save_reg (regno
))
312 mask
|= 1 << (15 - regno
);
314 if (exact_log2 (mask
) >= 0)
315 fprintf (stream
, "\tmovel %s,-(sp)\n", reg_names
[15 - exact_log2 (mask
)]);
317 fprintf (stream
, "\tmovem $0x%x,-(sp)\n", mask
);
323 m68k_output_function_prologue (stream
, size
)
328 register int mask
= 0;
329 int num_saved_regs
= 0;
330 HOST_WIDE_INT fsize
= (size
+ 3) & -4;
331 HOST_WIDE_INT cfa_offset
= INCOMING_FRAME_SP_OFFSET
;
332 HOST_WIDE_INT cfa_store_offset
= cfa_offset
;
334 /* If the stack limit is a symbol, we can check it here,
335 before actually allocating the space. */
336 if (current_function_limit_stack
337 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
339 #if defined (MOTOROLA)
340 asm_fprintf (stream
, "\tcmp.l %I%s+%wd,%Rsp\n\ttrapcs\n",
341 XSTR (stack_limit_rtx
, 0), fsize
+ 4);
343 asm_fprintf (stream
, "\tcmpl %I%s+%wd,%Rsp\n\ttrapcs\n",
344 XSTR (stack_limit_rtx
, 0), fsize
+ 4);
348 if (frame_pointer_needed
)
350 if (fsize
== 0 && TARGET_68040
)
352 /* on the 68040, pea + move is faster than link.w 0 */
354 fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
355 reg_names
[FRAME_POINTER_REGNUM
],
356 reg_names
[STACK_POINTER_REGNUM
],
357 reg_names
[FRAME_POINTER_REGNUM
]);
359 fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
360 reg_names
[FRAME_POINTER_REGNUM
],
361 reg_names
[STACK_POINTER_REGNUM
],
362 reg_names
[FRAME_POINTER_REGNUM
]);
365 else if (fsize
< 0x8000)
368 asm_fprintf (stream
, "\tlink.w %s,%I%wd\n",
369 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
371 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
372 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
375 else if (TARGET_68020
)
378 asm_fprintf (stream
, "\tlink.l %s,%I%wd\n",
379 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
381 asm_fprintf (stream
, "\tlink %s,%I%wd\n",
382 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
387 /* Adding negative number is faster on the 68040. */
389 asm_fprintf (stream
, "\tlink.w %s,%I0\n\tadd.l %I%wd,%Rsp\n",
390 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
392 asm_fprintf (stream
, "\tlink %s,%I0\n\taddl %I%wd,%Rsp\n",
393 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
396 if (dwarf2out_do_frame ())
399 l
= (char *) dwarf2out_cfi_label ();
400 cfa_store_offset
+= 4;
401 cfa_offset
= cfa_store_offset
;
402 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
403 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
404 cfa_store_offset
+= fsize
;
409 if (fsize
+ 4 < 0x8000)
416 /* asm_fprintf() cannot handle %. */
418 asm_fprintf (stream
, "\tsubq.w %I%wd,%Rsp\n", fsize
+ 4);
420 asm_fprintf (stream
, "\tsubqw %I%wd,%Rsp\n", fsize
+ 4);
425 /* asm_fprintf() cannot handle %. */
427 asm_fprintf (stream
, "\tsubq.l %I%wd,%Rsp\n", fsize
+ 4);
429 asm_fprintf (stream
, "\tsubql %I%wd,%Rsp\n", fsize
+ 4);
433 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
435 /* On the CPU32 it is faster to use two subqw instructions to
436 subtract a small integer (8 < N <= 16) to a register. */
437 /* asm_fprintf() cannot handle %. */
440 "\tsubq.w %I8,%Rsp\n\tsubq.w %I%wd,%Rsp\n",
443 asm_fprintf (stream
, "\tsubqw %I8,%Rsp\n\tsubqw %I%wd,%Rsp\n",
448 #endif /* not NO_ADDSUB_Q */
451 /* Adding negative number is faster on the 68040. */
452 /* asm_fprintf() cannot handle %. */
454 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", - (fsize
+ 4));
456 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", - (fsize
+ 4));
462 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", - (fsize
+ 4));
464 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", - (fsize
+ 4));
470 /* asm_fprintf() cannot handle %. */
472 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", - (fsize
+ 4));
474 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", - (fsize
+ 4));
477 if (dwarf2out_do_frame ())
479 cfa_store_offset
+= fsize
+ 4;
480 cfa_offset
= cfa_store_offset
;
481 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
486 for (regno
= 16; regno
< 24; regno
++)
487 if (m68k_save_reg (regno
))
489 mask
|= 1 << (regno
- 16);
492 if ((mask
& 0xff) != 0)
495 asm_fprintf (stream
, "\tfmovm %I0x%x,-(%Rsp)\n", mask
& 0xff);
497 asm_fprintf (stream
, "\tfmovem %I0x%x,%Rsp@-\n", mask
& 0xff);
499 if (dwarf2out_do_frame ())
501 char *l
= (char *) dwarf2out_cfi_label ();
504 cfa_store_offset
+= num_saved_regs
* 12;
505 if (! frame_pointer_needed
)
507 cfa_offset
= cfa_store_offset
;
508 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
510 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
511 if (mask
& (1 << (regno
- 16)))
512 dwarf2out_reg_save (l
, regno
,
513 -cfa_store_offset
+ n_regs
++ * 12);
519 for (regno
= 0; regno
< 16; regno
++)
520 if (m68k_save_reg (regno
))
522 mask
|= 1 << (15 - regno
);
526 /* If the stack limit is not a symbol, check it here.
527 This has the disadvantage that it may be too late... */
528 if (current_function_limit_stack
)
530 if (REG_P (stack_limit_rtx
))
532 #if defined (MOTOROLA)
533 asm_fprintf (stream
, "\tcmp.l %s,%Rsp\n\ttrapcs\n",
534 reg_names
[REGNO (stack_limit_rtx
)]);
536 asm_fprintf (stream
, "\tcmpl %s,%Rsp\n\ttrapcs\n",
537 reg_names
[REGNO (stack_limit_rtx
)]);
540 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
541 warning ("stack limit expression is not supported");
544 if (num_saved_regs
<= 2)
546 /* Store each separately in the same order moveml uses.
547 Using two movel instructions instead of a single moveml
548 is about 15% faster for the 68020 and 68030 at no expense
553 /* Undo the work from above. */
554 for (i
= 0; i
< 16; i
++)
559 "\t%Omove.l %s,-(%Rsp)\n",
561 "\tmovel %s,%Rsp@-\n",
564 if (dwarf2out_do_frame ())
566 char *l
= (char *) dwarf2out_cfi_label ();
568 cfa_store_offset
+= 4;
569 if (! frame_pointer_needed
)
571 cfa_offset
= cfa_store_offset
;
572 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
574 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
582 /* The coldfire does not support the predecrement form of the
583 movml instruction, so we must adjust the stack pointer and
584 then use the plain address register indirect mode. We also
585 have to invert the register save mask to use the new mode.
587 FIXME: if num_saved_regs was calculated earlier, we could
588 combine the stack pointer adjustment with any adjustment
589 done when the initial stack frame is created. This would
590 save an instruction */
595 for (i
= 0; i
< 16; i
++)
597 newmask
|= (1 << (15-i
));
600 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
601 asm_fprintf (stream
, "\tmovm.l %I0x%x,(%Rsp)\n", newmask
);
603 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
604 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@\n", newmask
);
610 asm_fprintf (stream
, "\tmovm.l %I0x%x,-(%Rsp)\n", mask
);
612 asm_fprintf (stream
, "\tmoveml %I0x%x,%Rsp@-\n", mask
);
615 if (dwarf2out_do_frame ())
617 char *l
= (char *) dwarf2out_cfi_label ();
620 cfa_store_offset
+= num_saved_regs
* 4;
621 if (! frame_pointer_needed
)
623 cfa_offset
= cfa_store_offset
;
624 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
626 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
627 if (mask
& (1 << (15 - regno
)))
628 dwarf2out_reg_save (l
, regno
,
629 -cfa_store_offset
+ n_regs
++ * 4);
632 if (flag_pic
&& current_function_uses_pic_offset_table
)
635 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
636 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
638 asm_fprintf (stream
, "\tmovel %I__GLOBAL_OFFSET_TABLE_, %s\n",
639 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
640 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
641 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
642 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
648 /* Return true if this function's epilogue can be output as RTL. */
655 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
658 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
659 if (m68k_save_reg (regno
))
665 /* This function generates the assembly code for function exit,
666 on machines that need it.
668 The function epilogue should not depend on the current stack pointer!
669 It should use the frame pointer only, if there is a frame pointer.
670 This is mandatory because of alloca; we also take advantage of it to
671 omit stack adjustments before returning. */
676 m68k_output_function_epilogue (stream
, size
)
681 register int mask
, fmask
;
683 HOST_WIDE_INT offset
, foffset
;
684 HOST_WIDE_INT fsize
= ((size
) + 3) & -4;
687 nregs
= 0; fmask
= 0;
688 for (regno
= 16; regno
< 24; regno
++)
689 if (m68k_save_reg (regno
))
692 fmask
|= 1 << (23 - regno
);
695 foffset
= nregs
* 12;
698 for (regno
= 0; regno
< 16; regno
++)
699 if (m68k_save_reg (regno
))
705 offset
= foffset
+ nregs
* 4;
706 if (offset
+ fsize
>= 0x8000
707 && frame_pointer_needed
710 fprintf (stream
, "\tmovel $" HOST_WIDE_INT_PRINT_DEC
",a0\n", -fsize
);
714 if (exact_log2 (mask
) >= 0)
717 fprintf (stream
, "\tmovel -" HOST_WIDE_INT_PRINT_DEC
"(a6,a0.l),%s\n",
718 offset
+ fsize
, reg_names
[exact_log2 (mask
)]);
719 else if (! frame_pointer_needed
)
720 fprintf (stream
, "\tmovel (sp)+,%s\n",
721 reg_names
[exact_log2 (mask
)]);
723 fprintf (stream
, "\tmovel -" HOST_WIDE_INT_PRINT_DEC
"(a6),%s\n",
724 offset
+ fsize
, reg_names
[exact_log2 (mask
)]);
730 "\tmovem -" HOST_WIDE_INT_PRINT_DEC
"(a6,a0.l),$0x%x\n",
731 offset
+ fsize
, mask
);
732 else if (! frame_pointer_needed
)
733 fprintf (stream
, "\tmovem (sp)+,$0x%x\n", mask
);
735 fprintf (stream
, "\tmovem -" HOST_WIDE_INT_PRINT_DEC
"(a6),$0x%x\n",
736 offset
+ fsize
, mask
);
743 "\tfmovem -" HOST_WIDE_INT_PRINT_DEC
"(a6,a0.l),$0x%x\n",
744 foffset
+ fsize
, fmask
);
745 else if (! frame_pointer_needed
)
746 fprintf (stream
, "\tfmovem (sp)+,$0x%x\n", fmask
);
748 fprintf (stream
, "\tfmovem -" HOST_WIDE_INT_PRINT_DEC
"(a6),$0x%x\n",
749 foffset
+ fsize
, fmask
);
752 if (frame_pointer_needed
)
753 fprintf (stream
, "\tunlk a6\n");
756 if (fsize
+ 4 < 0x8000)
757 fprintf (stream
, "\tadd.w $" HOST_WIDE_INT_PRINT_DEC
",sp\n",
760 fprintf (stream
, "\tadd.l $" HOST_WIDE_INT_PRINT_DEC
",sp\n",
764 if (current_function_calls_eh_return
)
765 fprintf (stream
, "\tadd.l a0,sp\n");
767 if (current_function_pops_args
)
768 fprintf (stream
, "\trtd $%d\n", current_function_pops_args
);
770 fprintf (stream
, "\trts\n");
776 m68k_output_function_epilogue (stream
, size
)
781 register int mask
, fmask
;
783 HOST_WIDE_INT offset
, foffset
;
784 HOST_WIDE_INT fsize
= (size
+ 3) & -4;
786 rtx insn
= get_last_insn ();
787 int restore_from_sp
= 0;
789 /* If the last insn was a BARRIER, we don't have to write any code. */
790 if (GET_CODE (insn
) == NOTE
)
791 insn
= prev_nonnote_insn (insn
);
792 if (insn
&& GET_CODE (insn
) == BARRIER
)
794 /* Output just a no-op so that debuggers don't get confused
795 about which function the pc is in at this address. */
796 fprintf (stream
, "\tnop\n");
800 #ifdef FUNCTION_EXTRA_EPILOGUE
801 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
803 nregs
= 0; fmask
= 0;
806 for (regno
= 16; regno
< 24; regno
++)
807 if (m68k_save_reg (regno
))
810 fmask
|= 1 << (23 - regno
);
813 foffset
= nregs
* 12;
815 for (regno
= 0; regno
< 16; regno
++)
816 if (m68k_save_reg (regno
))
821 offset
= foffset
+ nregs
* 4;
822 /* FIXME : leaf_function_p below is too strong.
823 What we really need to know there is if there could be pending
824 stack adjustment needed at that point. */
825 restore_from_sp
= ! frame_pointer_needed
826 || (! current_function_calls_alloca
&& leaf_function_p ());
827 if (offset
+ fsize
>= 0x8000
832 asm_fprintf (stream
, "\t%Omove.l %I%wd,%Ra1\n", -fsize
);
834 asm_fprintf (stream
, "\tmovel %I%wd,%Ra1\n", -fsize
);
838 if (TARGET_5200
|| nregs
<= 2)
840 /* Restore each separately in the same order moveml does.
841 Using two movel instructions instead of a single moveml
842 is about 15% faster for the 68020 and 68030 at no expense
847 /* Undo the work from above. */
848 for (i
= 0; i
< 16; i
++)
854 asm_fprintf (stream
, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
856 reg_names
[FRAME_POINTER_REGNUM
],
859 asm_fprintf (stream
, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
860 reg_names
[FRAME_POINTER_REGNUM
],
861 offset
+ fsize
, reg_names
[i
]);
864 else if (restore_from_sp
)
867 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
870 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
877 asm_fprintf (stream
, "\t%Omove.l -%wd(%s),%s\n",
879 reg_names
[FRAME_POINTER_REGNUM
],
883 "\tmovel %s@(-" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
884 reg_names
[FRAME_POINTER_REGNUM
],
885 offset
+ fsize
, reg_names
[i
]);
896 asm_fprintf (stream
, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
898 reg_names
[FRAME_POINTER_REGNUM
],
901 asm_fprintf (stream
, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
902 reg_names
[FRAME_POINTER_REGNUM
],
903 offset
+ fsize
, mask
);
906 else if (restore_from_sp
)
909 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%I0x%x\n", mask
);
911 asm_fprintf (stream
, "\tmoveml %Rsp@+,%I0x%x\n", mask
);
917 asm_fprintf (stream
, "\tmovm.l -%wd(%s),%I0x%x\n",
919 reg_names
[FRAME_POINTER_REGNUM
],
922 asm_fprintf (stream
, "\tmoveml %s@(-%wd),%I0x%x\n",
923 reg_names
[FRAME_POINTER_REGNUM
],
924 offset
+ fsize
, mask
);
933 asm_fprintf (stream
, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
935 reg_names
[FRAME_POINTER_REGNUM
],
938 asm_fprintf (stream
, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
939 reg_names
[FRAME_POINTER_REGNUM
],
940 foffset
+ fsize
, fmask
);
943 else if (restore_from_sp
)
946 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%I0x%x\n", fmask
);
948 asm_fprintf (stream
, "\tfmovem %Rsp@+,%I0x%x\n", fmask
);
954 asm_fprintf (stream
, "\tfmovm -%wd(%s),%I0x%x\n",
956 reg_names
[FRAME_POINTER_REGNUM
],
959 asm_fprintf (stream
, "\tfmovem %s@(-%wd),%I0x%x\n",
960 reg_names
[FRAME_POINTER_REGNUM
],
961 foffset
+ fsize
, fmask
);
965 if (frame_pointer_needed
)
966 fprintf (stream
, "\tunlk %s\n",
967 reg_names
[FRAME_POINTER_REGNUM
]);
976 asm_fprintf (stream
, "\taddq.w %I%wd,%Rsp\n", fsize
+ 4);
978 asm_fprintf (stream
, "\taddqw %I%wd,%Rsp\n", fsize
+ 4);
984 asm_fprintf (stream
, "\taddq.l %I%wd,%Rsp\n", fsize
+ 4);
986 asm_fprintf (stream
, "\taddql %I%wd,%Rsp\n", fsize
+ 4);
990 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
992 /* On the CPU32 it is faster to use two addqw instructions to
993 add a small integer (8 < N <= 16) to a register. */
994 /* asm_fprintf() cannot handle %. */
996 asm_fprintf (stream
, "\taddq.w %I8,%Rsp\n\taddq.w %I%wd,%Rsp\n",
999 asm_fprintf (stream
, "\taddqw %I8,%Rsp\n\taddqw %I%wd,%Rsp\n",
1004 #endif /* not NO_ADDSUB_Q */
1005 if (fsize
+ 4 < 0x8000)
1009 /* asm_fprintf() cannot handle %. */
1011 asm_fprintf (stream
, "\tadd.w %I%wd,%Rsp\n", fsize
+ 4);
1013 asm_fprintf (stream
, "\taddw %I%wd,%Rsp\n", fsize
+ 4);
1019 asm_fprintf (stream
, "\tlea (%wd,%Rsp),%Rsp\n", fsize
+ 4);
1021 asm_fprintf (stream
, "\tlea %Rsp@(%wd),%Rsp\n", fsize
+ 4);
1027 /* asm_fprintf() cannot handle %. */
1029 asm_fprintf (stream
, "\tadd.l %I%wd,%Rsp\n", fsize
+ 4);
1031 asm_fprintf (stream
, "\taddl %I%wd,%Rsp\n", fsize
+ 4);
1035 if (current_function_calls_eh_return
)
1038 asm_fprintf (stream
, "\tadd.l %Ra0,%Rsp\n");
1040 asm_fprintf (stream
, "\taddl %Ra0,%Rsp\n");
1043 if (current_function_pops_args
)
1044 asm_fprintf (stream
, "\trtd %I%d\n", current_function_pops_args
);
1046 fprintf (stream
, "\trts\n");
1050 /* Similar to general_operand, but exclude stack_pointer_rtx. */
1053 not_sp_operand (op
, mode
)
1055 enum machine_mode mode
;
1057 return op
!= stack_pointer_rtx
&& nonimmediate_operand (op
, mode
);
1060 /* Return TRUE if X is a valid comparison operator for the dbcc
1063 Note it rejects floating point comparison operators.
1064 (In the future we could use Fdbcc).
1066 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1069 valid_dbcc_comparison_p (x
, mode
)
1071 enum machine_mode mode ATTRIBUTE_UNUSED
;
1073 switch (GET_CODE (x
))
1075 case EQ
: case NE
: case GTU
: case LTU
:
1079 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1081 case GT
: case LT
: case GE
: case LE
:
1082 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1088 /* Return nonzero if flags are currently in the 68881 flag register. */
1092 /* We could add support for these in the future */
1093 return cc_status
.flags
& CC_IN_68881
;
1096 /* Output a dbCC; jCC sequence. Note we do not handle the
1097 floating point version of this sequence (Fdbcc). We also
1098 do not handle alternative conditions when CC_NO_OVERFLOW is
1099 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1100 kick those out before we get here. */
1103 output_dbcc_and_branch (operands
)
1106 switch (GET_CODE (operands
[3]))
1110 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
1112 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1118 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
1120 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1126 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
1128 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1134 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
1136 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1142 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
1144 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1150 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
1152 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1158 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
1160 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1166 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
1168 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1174 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
1176 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1182 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
1184 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1192 /* If the decrement is to be done in SImode, then we have
1193 to compensate for the fact that dbcc decrements in HImode. */
1194 switch (GET_MODE (operands
[0]))
1198 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
1200 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1213 output_scc_di(op
, operand1
, operand2
, dest
)
1220 enum rtx_code op_code
= GET_CODE (op
);
1222 /* This does not produce a useful cc. */
1225 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1226 below. Swap the operands and change the op if these requirements
1227 are not fulfilled. */
1228 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1232 operand1
= operand2
;
1234 op_code
= swap_condition (op_code
);
1236 loperands
[0] = operand1
;
1237 if (GET_CODE (operand1
) == REG
)
1238 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1240 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1241 if (operand2
!= const0_rtx
)
1243 loperands
[2] = operand2
;
1244 if (GET_CODE (operand2
) == REG
)
1245 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1247 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1249 loperands
[4] = gen_label_rtx();
1250 if (operand2
!= const0_rtx
)
1253 #ifdef SGS_CMP_ORDER
1254 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1256 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1259 #ifdef SGS_CMP_ORDER
1260 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1262 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1268 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[0]))
1269 output_asm_insn ("tst%.l %0", loperands
);
1272 #ifdef SGS_CMP_ORDER
1273 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1275 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1280 output_asm_insn ("jbne %l4", loperands
);
1282 output_asm_insn ("jne %l4", loperands
);
1285 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[1]))
1286 output_asm_insn ("tst%.l %1", loperands
);
1289 #ifdef SGS_CMP_ORDER
1290 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1292 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1297 loperands
[5] = dest
;
1302 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1303 CODE_LABEL_NUMBER (loperands
[4]));
1304 output_asm_insn ("seq %5", loperands
);
1308 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1309 CODE_LABEL_NUMBER (loperands
[4]));
1310 output_asm_insn ("sne %5", loperands
);
1314 loperands
[6] = gen_label_rtx();
1316 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1318 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1320 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1321 CODE_LABEL_NUMBER (loperands
[4]));
1322 output_asm_insn ("sgt %5", loperands
);
1323 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1324 CODE_LABEL_NUMBER (loperands
[6]));
1328 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1329 CODE_LABEL_NUMBER (loperands
[4]));
1330 output_asm_insn ("shi %5", loperands
);
1334 loperands
[6] = gen_label_rtx();
1336 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1338 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1340 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1341 CODE_LABEL_NUMBER (loperands
[4]));
1342 output_asm_insn ("slt %5", loperands
);
1343 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1344 CODE_LABEL_NUMBER (loperands
[6]));
1348 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1349 CODE_LABEL_NUMBER (loperands
[4]));
1350 output_asm_insn ("scs %5", loperands
);
1354 loperands
[6] = gen_label_rtx();
1356 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1358 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1360 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1361 CODE_LABEL_NUMBER (loperands
[4]));
1362 output_asm_insn ("sge %5", loperands
);
1363 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1364 CODE_LABEL_NUMBER (loperands
[6]));
1368 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1369 CODE_LABEL_NUMBER (loperands
[4]));
1370 output_asm_insn ("scc %5", loperands
);
1374 loperands
[6] = gen_label_rtx();
1376 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1378 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1380 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1381 CODE_LABEL_NUMBER (loperands
[4]));
1382 output_asm_insn ("sle %5", loperands
);
1383 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1384 CODE_LABEL_NUMBER (loperands
[6]));
1388 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1389 CODE_LABEL_NUMBER (loperands
[4]));
1390 output_asm_insn ("sls %5", loperands
);
1400 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1402 rtx countop
, dataop
;
1406 operands
[0] = countop
;
1407 operands
[1] = dataop
;
1409 if (GET_CODE (countop
) == CONST_INT
)
1411 register int count
= INTVAL (countop
);
1412 /* If COUNT is bigger than size of storage unit in use,
1413 advance to the containing unit of same size. */
1414 if (count
> signpos
)
1416 int offset
= (count
& ~signpos
) / 8;
1417 count
= count
& signpos
;
1418 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1420 if (count
== signpos
)
1421 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1423 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1425 /* These three statements used to use next_insns_test_no...
1426 but it appears that this should do the same job. */
1428 && next_insn_tests_no_inequality (insn
))
1431 && next_insn_tests_no_inequality (insn
))
1434 && next_insn_tests_no_inequality (insn
))
1437 cc_status
.flags
= CC_NOT_NEGATIVE
;
1439 return "btst %0,%1";
1442 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1443 reference and a constant. */
1446 symbolic_operand (op
, mode
)
1448 enum machine_mode mode ATTRIBUTE_UNUSED
;
1450 switch (GET_CODE (op
))
1458 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1459 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1460 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1462 #if 0 /* Deleted, with corresponding change in m68k.h,
1463 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1465 return GET_MODE (op
) == mode
;
1473 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1476 extend_operator(x
, mode
)
1478 enum machine_mode mode
;
1480 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1482 switch (GET_CODE(x
))
1493 /* Legitimize PIC addresses. If the address is already
1494 position-independent, we return ORIG. Newly generated
1495 position-independent addresses go to REG. If we need more
1496 than one register, we lose.
1498 An address is legitimized by making an indirect reference
1499 through the Global Offset Table with the name of the symbol
1502 The assembler and linker are responsible for placing the
1503 address of the symbol in the GOT. The function prologue
1504 is responsible for initializing a5 to the starting address
1507 The assembler is also responsible for translating a symbol name
1508 into a constant displacement from the start of the GOT.
1510 A quick example may make things a little clearer:
1512 When not generating PIC code to store the value 12345 into _foo
1513 we would generate the following code:
1517 When generating PIC two transformations are made. First, the compiler
1518 loads the address of foo into a register. So the first transformation makes:
1523 The code in movsi will intercept the lea instruction and call this
1524 routine which will transform the instructions into:
1526 movel a5@(_foo:w), a0
1530 That (in a nutshell) is how *all* symbol and label references are
1534 legitimize_pic_address (orig
, mode
, reg
)
1536 enum machine_mode mode ATTRIBUTE_UNUSED
;
1540 /* First handle a simple SYMBOL_REF or LABEL_REF */
1541 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1546 pic_ref
= gen_rtx_MEM (Pmode
,
1547 gen_rtx_PLUS (Pmode
,
1548 pic_offset_table_rtx
, orig
));
1549 current_function_uses_pic_offset_table
= 1;
1550 RTX_UNCHANGING_P (pic_ref
) = 1;
1551 emit_move_insn (reg
, pic_ref
);
1554 else if (GET_CODE (orig
) == CONST
)
1558 /* Make sure this is CONST has not already been legitimized */
1559 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1560 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1566 /* legitimize both operands of the PLUS */
1567 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1569 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1570 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1571 base
== reg
? 0 : reg
);
1575 if (GET_CODE (orig
) == CONST_INT
)
1576 return plus_constant (base
, INTVAL (orig
));
1577 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1578 /* Likewise, should we set special REG_NOTEs here? */
1584 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1586 static CONST_METHOD const_method
PARAMS ((rtx
));
1588 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1591 const_method (constant
)
1597 i
= INTVAL (constant
);
1601 /* The Coldfire doesn't have byte or word operations. */
1602 /* FIXME: This may not be useful for the m68060 either */
1605 /* if -256 < N < 256 but N is not in range for a moveq
1606 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1607 if (USE_MOVQ (i
^ 0xff))
1609 /* Likewise, try with not.w */
1610 if (USE_MOVQ (i
^ 0xffff))
1612 /* This is the only value where neg.w is useful */
1615 /* Try also with swap */
1617 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1620 /* Otherwise, use move.l */
1625 const_int_cost (constant
)
1628 switch (const_method (constant
))
1631 /* Constants between -128 and 127 are cheap due to moveq */
1637 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1647 m68k_rtx_costs (x
, code
, outer_code
, total
)
1649 int code
, outer_code
;
1655 /* Constant zero is super cheap due to clr instruction. */
1656 if (x
== const0_rtx
)
1659 *total
= const_int_cost (x
);
1669 /* Make 0.0 cheaper than other floating constants to
1670 encourage creating tstsf and tstdf insns. */
1671 if (outer_code
== COMPARE
1672 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
1678 /* These are vaguely right for a 68020. */
1679 /* The costs for long multiply have been adjusted to work properly
1680 in synth_mult on the 68020, relative to an average of the time
1681 for add and the time for shift, taking away a little more because
1682 sometimes move insns are needed. */
1683 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1684 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1685 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1686 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1689 /* An lea costs about three times as much as a simple add. */
1690 if (GET_MODE (x
) == SImode
1691 && GET_CODE (XEXP (x
, 1)) == REG
1692 && GET_CODE (XEXP (x
, 0)) == MULT
1693 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1694 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1695 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
1696 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
1697 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
1698 *total
= COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */
1706 *total
= COSTS_N_INSNS(1);
1711 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1713 if (INTVAL (XEXP (x
, 1)) < 16)
1714 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
1716 /* We're using clrw + swap for these cases. */
1717 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
1720 *total
= COSTS_N_INSNS (10); /* worst case */
1723 /* A shift by a big integer takes an extra instruction. */
1724 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1725 && (INTVAL (XEXP (x
, 1)) == 16))
1727 *total
= COSTS_N_INSNS (2); /* clrw;swap */
1730 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1731 && !(INTVAL (XEXP (x
, 1)) > 0
1732 && INTVAL (XEXP (x
, 1)) <= 8))
1734 *total
= COSTS_N_INSNS (3); /* lsr #i,dn */
1740 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
1741 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
1742 && GET_MODE (x
) == SImode
)
1743 *total
= COSTS_N_INSNS (MULW_COST
);
1744 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1745 *total
= COSTS_N_INSNS (MULW_COST
);
1747 *total
= COSTS_N_INSNS (MULL_COST
);
1754 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
1755 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
1757 *total
= COSTS_N_INSNS (43); /* div.l */
1766 output_move_const_into_data_reg (operands
)
1771 i
= INTVAL (operands
[1]);
1772 switch (const_method (operands
[1]))
1775 #if defined (MOTOROLA) && !defined (CRDS)
1776 return "moveq%.l %1,%0";
1778 return "moveq %1,%0";
1781 operands
[1] = GEN_INT (i
^ 0xff);
1782 #if defined (MOTOROLA) && !defined (CRDS)
1783 return "moveq%.l %1,%0\n\tnot%.b %0";
1785 return "moveq %1,%0\n\tnot%.b %0";
1788 operands
[1] = GEN_INT (i
^ 0xffff);
1789 #if defined (MOTOROLA) && !defined (CRDS)
1790 return "moveq%.l %1,%0\n\tnot%.w %0";
1792 return "moveq %1,%0\n\tnot%.w %0";
1795 #if defined (MOTOROLA) && !defined (CRDS)
1796 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1798 return "moveq %#-128,%0\n\tneg%.w %0";
1804 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1805 #if defined (MOTOROLA) && !defined (CRDS)
1806 return "moveq%.l %1,%0\n\tswap %0";
1808 return "moveq %1,%0\n\tswap %0";
1812 return "move%.l %1,%0";
1819 output_move_simode_const (operands
)
1822 if (operands
[1] == const0_rtx
1823 && (DATA_REG_P (operands
[0])
1824 || GET_CODE (operands
[0]) == MEM
)
1825 /* clr insns on 68000 read before writing.
1826 This isn't so on the 68010, but we have no TARGET_68010. */
1827 && ((TARGET_68020
|| TARGET_5200
)
1828 || !(GET_CODE (operands
[0]) == MEM
1829 && MEM_VOLATILE_P (operands
[0]))))
1831 else if (operands
[1] == const0_rtx
1832 && ADDRESS_REG_P (operands
[0]))
1833 return "sub%.l %0,%0";
1834 else if (DATA_REG_P (operands
[0]))
1835 return output_move_const_into_data_reg (operands
);
1836 else if (ADDRESS_REG_P (operands
[0])
1837 && INTVAL (operands
[1]) < 0x8000
1838 && INTVAL (operands
[1]) >= -0x8000)
1839 return "move%.w %1,%0";
1840 else if (GET_CODE (operands
[0]) == MEM
1841 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1842 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1843 && INTVAL (operands
[1]) < 0x8000
1844 && INTVAL (operands
[1]) >= -0x8000)
1846 return "move%.l %1,%0";
1850 output_move_simode (operands
)
1853 if (GET_CODE (operands
[1]) == CONST_INT
)
1854 return output_move_simode_const (operands
);
1855 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1856 || GET_CODE (operands
[1]) == CONST
)
1857 && push_operand (operands
[0], SImode
))
1859 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1860 || GET_CODE (operands
[1]) == CONST
)
1861 && ADDRESS_REG_P (operands
[0]))
1862 return "lea %a1,%0";
1863 return "move%.l %1,%0";
1867 output_move_himode (operands
)
1870 if (GET_CODE (operands
[1]) == CONST_INT
)
1872 if (operands
[1] == const0_rtx
1873 && (DATA_REG_P (operands
[0])
1874 || GET_CODE (operands
[0]) == MEM
)
1875 /* clr insns on 68000 read before writing.
1876 This isn't so on the 68010, but we have no TARGET_68010. */
1877 && ((TARGET_68020
|| TARGET_5200
)
1878 || !(GET_CODE (operands
[0]) == MEM
1879 && MEM_VOLATILE_P (operands
[0]))))
1881 else if (operands
[1] == const0_rtx
1882 && ADDRESS_REG_P (operands
[0]))
1883 return "sub%.l %0,%0";
1884 else if (DATA_REG_P (operands
[0])
1885 && INTVAL (operands
[1]) < 128
1886 && INTVAL (operands
[1]) >= -128)
1888 #if defined(MOTOROLA) && !defined(CRDS)
1889 return "moveq%.l %1,%0";
1891 return "moveq %1,%0";
1894 else if (INTVAL (operands
[1]) < 0x8000
1895 && INTVAL (operands
[1]) >= -0x8000)
1896 return "move%.w %1,%0";
1898 else if (CONSTANT_P (operands
[1]))
1899 return "move%.l %1,%0";
1901 /* Recognize the insn before a tablejump, one that refers
1902 to a table of offsets. Such an insn will need to refer
1903 to a label on the insn. So output one. Use the label-number
1904 of the table of offsets to generate this label. This code,
1905 and similar code below, assumes that there will be at most one
1906 reference to each table. */
1907 if (GET_CODE (operands
[1]) == MEM
1908 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1909 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1910 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1912 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1913 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1915 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1916 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1918 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1919 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1920 #endif /* not SGS */
1921 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1922 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LI",
1923 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1924 #ifdef SGS_SWITCH_TABLES
1925 /* Set flag saying we need to define the symbol
1926 LD%n (with value L%n-LI%n) at the end of the switch table. */
1927 switch_table_difference_label_flag
= 1;
1928 #endif /* SGS_SWITCH_TABLES */
1929 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1931 #endif /* SGS_NO_LI */
1932 return "move%.w %1,%0";
1936 output_move_qimode (operands
)
1941 /* This is probably useless, since it loses for pushing a struct
1942 of several bytes a byte at a time. */
1943 /* 68k family always modifies the stack pointer by at least 2, even for
1944 byte pushes. The 5200 (coldfire) does not do this. */
1945 if (GET_CODE (operands
[0]) == MEM
1946 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1947 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1948 && ! ADDRESS_REG_P (operands
[1])
1951 xoperands
[1] = operands
[1];
1953 = gen_rtx_MEM (QImode
,
1954 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1955 /* Just pushing a byte puts it in the high byte of the halfword. */
1956 /* We must put it in the low-order, high-numbered byte. */
1957 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1959 xoperands
[3] = stack_pointer_rtx
;
1961 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1963 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1967 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1971 /* clr and st insns on 68000 read before writing.
1972 This isn't so on the 68010, but we have no TARGET_68010. */
1973 if (!ADDRESS_REG_P (operands
[0])
1974 && ((TARGET_68020
|| TARGET_5200
)
1975 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1977 if (operands
[1] == const0_rtx
)
1979 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1980 && GET_CODE (operands
[1]) == CONST_INT
1981 && (INTVAL (operands
[1]) & 255) == 255)
1987 if (GET_CODE (operands
[1]) == CONST_INT
1988 && DATA_REG_P (operands
[0])
1989 && INTVAL (operands
[1]) < 128
1990 && INTVAL (operands
[1]) >= -128)
1992 #if defined(MOTOROLA) && !defined(CRDS)
1993 return "moveq%.l %1,%0";
1995 return "moveq %1,%0";
1998 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1999 return "sub%.l %0,%0";
2000 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
2001 return "move%.l %1,%0";
2002 /* 68k family (including the 5200 coldfire) does not support byte moves to
2003 from address registers. */
2004 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
2005 return "move%.w %1,%0";
2006 return "move%.b %1,%0";
2010 output_move_stricthi (operands
)
2013 if (operands
[1] == const0_rtx
2014 /* clr insns on 68000 read before writing.
2015 This isn't so on the 68010, but we have no TARGET_68010. */
2016 && ((TARGET_68020
|| TARGET_5200
)
2017 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2019 return "move%.w %1,%0";
2023 output_move_strictqi (operands
)
2026 if (operands
[1] == const0_rtx
2027 /* clr insns on 68000 read before writing.
2028 This isn't so on the 68010, but we have no TARGET_68010. */
2029 && ((TARGET_68020
|| TARGET_5200
)
2030 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
2032 return "move%.b %1,%0";
2035 /* Return the best assembler insn template
2036 for moving operands[1] into operands[0] as a fullword. */
2039 singlemove_string (operands
)
2042 if (GET_CODE (operands
[1]) == CONST_INT
)
2043 return output_move_simode_const (operands
);
2044 return "move%.l %1,%0";
2048 /* Output assembler code to perform a doubleword move insn
2049 with operands OPERANDS. */
2052 output_move_double (operands
)
2057 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
2062 rtx addreg0
= 0, addreg1
= 0;
2063 int dest_overlapped_low
= 0;
2064 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
2069 /* First classify both operands. */
2071 if (REG_P (operands
[0]))
2073 else if (offsettable_memref_p (operands
[0]))
2075 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
2077 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
2079 else if (GET_CODE (operands
[0]) == MEM
)
2084 if (REG_P (operands
[1]))
2086 else if (CONSTANT_P (operands
[1]))
2088 else if (offsettable_memref_p (operands
[1]))
2090 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
2092 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
2094 else if (GET_CODE (operands
[1]) == MEM
)
2099 /* Check for the cases that the operand constraints are not
2100 supposed to allow to happen. Abort if we get one,
2101 because generating code for these cases is painful. */
2103 if (optype0
== RNDOP
|| optype1
== RNDOP
)
2106 /* If one operand is decrementing and one is incrementing
2107 decrement the former register explicitly
2108 and change that operand into ordinary indexing. */
2110 if (optype0
== PUSHOP
&& optype1
== POPOP
)
2112 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
2114 output_asm_insn ("sub%.l %#12,%0", operands
);
2116 output_asm_insn ("subq%.l %#8,%0", operands
);
2117 if (GET_MODE (operands
[1]) == XFmode
)
2118 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
2119 else if (GET_MODE (operands
[0]) == DFmode
)
2120 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
2122 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
2125 if (optype0
== POPOP
&& optype1
== PUSHOP
)
2127 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2129 output_asm_insn ("sub%.l %#12,%1", operands
);
2131 output_asm_insn ("subq%.l %#8,%1", operands
);
2132 if (GET_MODE (operands
[1]) == XFmode
)
2133 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
2134 else if (GET_MODE (operands
[1]) == DFmode
)
2135 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
2137 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
2141 /* If an operand is an unoffsettable memory ref, find a register
2142 we can increment temporarily to make it refer to the second word. */
2144 if (optype0
== MEMOP
)
2145 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
2147 if (optype1
== MEMOP
)
2148 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
2150 /* Ok, we can do one word at a time.
2151 Normally we do the low-numbered word first,
2152 but if either operand is autodecrementing then we
2153 do the high-numbered word first.
2155 In either case, set up in LATEHALF the operands to use
2156 for the high-numbered word and in some cases alter the
2157 operands in OPERANDS to be suitable for the low-numbered word. */
2161 if (optype0
== REGOP
)
2163 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
2164 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2166 else if (optype0
== OFFSOP
)
2168 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
2169 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2173 middlehalf
[0] = operands
[0];
2174 latehalf
[0] = operands
[0];
2177 if (optype1
== REGOP
)
2179 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
2180 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2182 else if (optype1
== OFFSOP
)
2184 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
2185 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2187 else if (optype1
== CNSTOP
)
2189 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
2194 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
2195 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2196 operands
[1] = GEN_INT (l
[0]);
2197 middlehalf
[1] = GEN_INT (l
[1]);
2198 latehalf
[1] = GEN_INT (l
[2]);
2200 else if (CONSTANT_P (operands
[1]))
2202 /* actually, no non-CONST_DOUBLE constant should ever
2205 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
2206 latehalf
[1] = constm1_rtx
;
2208 latehalf
[1] = const0_rtx
;
2213 middlehalf
[1] = operands
[1];
2214 latehalf
[1] = operands
[1];
2218 /* size is not 12: */
2220 if (optype0
== REGOP
)
2221 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
2222 else if (optype0
== OFFSOP
)
2223 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
2225 latehalf
[0] = operands
[0];
2227 if (optype1
== REGOP
)
2228 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
2229 else if (optype1
== OFFSOP
)
2230 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
2231 else if (optype1
== CNSTOP
)
2232 split_double (operands
[1], &operands
[1], &latehalf
[1]);
2234 latehalf
[1] = operands
[1];
2237 /* If insn is effectively movd N(sp),-(sp) then we will do the
2238 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2239 for the low word as well, to compensate for the first decrement of sp. */
2240 if (optype0
== PUSHOP
2241 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
2242 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
2243 operands
[1] = middlehalf
[1] = latehalf
[1];
2245 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2246 if the upper part of reg N does not appear in the MEM, arrange to
2247 emit the move late-half first. Otherwise, compute the MEM address
2248 into the upper part of N and use that as a pointer to the memory
2250 if (optype0
== REGOP
2251 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
2253 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
2255 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2256 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2258 /* If both halves of dest are used in the src memory address,
2259 compute the address into latehalf of dest.
2260 Note that this can't happen if the dest is two data regs. */
2262 xops
[0] = latehalf
[0];
2263 xops
[1] = XEXP (operands
[1], 0);
2264 output_asm_insn ("lea %a1,%0", xops
);
2265 if (GET_MODE (operands
[1]) == XFmode
)
2267 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
2268 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
2269 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2273 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
2274 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
2278 && reg_overlap_mentioned_p (middlehalf
[0],
2279 XEXP (operands
[1], 0)))
2281 /* Check for two regs used by both source and dest.
2282 Note that this can't happen if the dest is all data regs.
2283 It can happen if the dest is d6, d7, a0.
2284 But in that case, latehalf is an addr reg, so
2285 the code at compadr does ok. */
2287 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
2288 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
2291 /* JRV says this can't happen: */
2292 if (addreg0
|| addreg1
)
2295 /* Only the middle reg conflicts; simply put it last. */
2296 output_asm_insn (singlemove_string (operands
), operands
);
2297 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2298 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2301 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
2302 /* If the low half of dest is mentioned in the source memory
2303 address, the arrange to emit the move late half first. */
2304 dest_overlapped_low
= 1;
2307 /* If one or both operands autodecrementing,
2308 do the two words, high-numbered first. */
2310 /* Likewise, the first move would clobber the source of the second one,
2311 do them in the other order. This happens only for registers;
2312 such overlap can't happen in memory unless the user explicitly
2313 sets it up, and that is an undefined circumstance. */
2315 if (optype0
== PUSHOP
|| optype1
== PUSHOP
2316 || (optype0
== REGOP
&& optype1
== REGOP
2317 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
2318 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
2319 || dest_overlapped_low
)
2321 /* Make any unoffsettable addresses point at high-numbered word. */
2325 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2327 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2332 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2334 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2338 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2340 /* Undo the adds we just did. */
2342 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2344 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2348 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2350 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2352 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2355 /* Do low-numbered word. */
2356 return singlemove_string (operands
);
2359 /* Normal case: do the two words, low-numbered first. */
2361 output_asm_insn (singlemove_string (operands
), operands
);
2363 /* Do the middle one of the three words for long double */
2367 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2369 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2371 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2374 /* Make any unoffsettable addresses point at high-numbered word. */
2376 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2378 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2381 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2383 /* Undo the adds we just did. */
2387 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2389 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2394 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2396 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2402 /* Return a REG that occurs in ADDR with coefficient 1.
2403 ADDR can be effectively incremented by incrementing REG. */
2406 find_addr_reg (addr
)
2409 while (GET_CODE (addr
) == PLUS
)
2411 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2412 addr
= XEXP (addr
, 0);
2413 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2414 addr
= XEXP (addr
, 1);
2415 else if (CONSTANT_P (XEXP (addr
, 0)))
2416 addr
= XEXP (addr
, 1);
2417 else if (CONSTANT_P (XEXP (addr
, 1)))
2418 addr
= XEXP (addr
, 0);
2422 if (GET_CODE (addr
) == REG
)
2427 /* Output assembler code to perform a 32 bit 3 operand add. */
2430 output_addsi3 (operands
)
2433 if (! operands_match_p (operands
[0], operands
[1]))
2435 if (!ADDRESS_REG_P (operands
[1]))
2437 rtx tmp
= operands
[1];
2439 operands
[1] = operands
[2];
2443 /* These insns can result from reloads to access
2444 stack slots over 64k from the frame pointer. */
2445 if (GET_CODE (operands
[2]) == CONST_INT
2446 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2447 return "move%.l %2,%0\n\tadd%.l %1,%0";
2449 if (GET_CODE (operands
[2]) == REG
)
2450 return "lea 0(%1,%2.l),%0";
2452 return "lea %c2(%1),%0";
2455 if (GET_CODE (operands
[2]) == REG
)
2456 return "lea (%1,%2.l),%0";
2458 return "lea (%c2,%1),%0";
2459 #else /* not MOTOROLA (MIT syntax) */
2460 if (GET_CODE (operands
[2]) == REG
)
2461 return "lea %1@(0,%2:l),%0";
2463 return "lea %1@(%c2),%0";
2464 #endif /* not MOTOROLA */
2465 #endif /* not SGS */
2467 if (GET_CODE (operands
[2]) == CONST_INT
)
2470 if (INTVAL (operands
[2]) > 0
2471 && INTVAL (operands
[2]) <= 8)
2472 return "addq%.l %2,%0";
2473 if (INTVAL (operands
[2]) < 0
2474 && INTVAL (operands
[2]) >= -8)
2476 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
2477 return "subq%.l %2,%0";
2479 /* On the CPU32 it is faster to use two addql instructions to
2480 add a small integer (8 < N <= 16) to a register.
2481 Likewise for subql. */
2482 if (TARGET_CPU32
&& REG_P (operands
[0]))
2484 if (INTVAL (operands
[2]) > 8
2485 && INTVAL (operands
[2]) <= 16)
2487 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2488 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2490 if (INTVAL (operands
[2]) < -8
2491 && INTVAL (operands
[2]) >= -16)
2493 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
2494 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2498 if (ADDRESS_REG_P (operands
[0])
2499 && INTVAL (operands
[2]) >= -0x8000
2500 && INTVAL (operands
[2]) < 0x8000)
2503 return "add%.w %2,%0";
2506 return "lea (%c2,%0),%0";
2508 return "lea %0@(%c2),%0";
2512 return "add%.l %2,%0";
2515 /* Store in cc_status the expressions that the condition codes will
2516 describe after execution of an instruction whose pattern is EXP.
2517 Do not alter them if the instruction would not alter the cc's. */
2519 /* On the 68000, all the insns to store in an address register fail to
2520 set the cc's. However, in some cases these instructions can make it
2521 possibly invalid to use the saved cc's. In those cases we clear out
2522 some or all of the saved cc's so they won't be used. */
2525 notice_update_cc (exp
, insn
)
2529 if (GET_CODE (exp
) == SET
)
2531 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2535 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2537 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2538 cc_status
.value1
= 0;
2539 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2540 cc_status
.value2
= 0;
2542 else if (!FP_REG_P (SET_DEST (exp
))
2543 && SET_DEST (exp
) != cc0_rtx
2544 && (FP_REG_P (SET_SRC (exp
))
2545 || GET_CODE (SET_SRC (exp
)) == FIX
2546 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2547 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2551 /* A pair of move insns doesn't produce a useful overall cc. */
2552 else if (!FP_REG_P (SET_DEST (exp
))
2553 && !FP_REG_P (SET_SRC (exp
))
2554 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2555 && (GET_CODE (SET_SRC (exp
)) == REG
2556 || GET_CODE (SET_SRC (exp
)) == MEM
2557 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2561 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2565 else if (XEXP (exp
, 0) != pc_rtx
)
2567 cc_status
.flags
= 0;
2568 cc_status
.value1
= XEXP (exp
, 0);
2569 cc_status
.value2
= XEXP (exp
, 1);
2572 else if (GET_CODE (exp
) == PARALLEL
2573 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2575 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2577 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2579 cc_status
.flags
= 0;
2580 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2581 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2586 if (cc_status
.value2
!= 0
2587 && ADDRESS_REG_P (cc_status
.value2
)
2588 && GET_MODE (cc_status
.value2
) == QImode
)
2590 if (cc_status
.value2
!= 0)
2591 switch (GET_CODE (cc_status
.value2
))
2593 case PLUS
: case MINUS
: case MULT
:
2594 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2595 #if 0 /* These instructions always clear the overflow bit */
2596 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2597 case ROTATE
: case ROTATERT
:
2599 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2600 cc_status
.flags
|= CC_NO_OVERFLOW
;
2603 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2604 ends with a move insn moving r2 in r2's mode.
2605 Thus, the cc's are set for r2.
2606 This can set N bit spuriously. */
2607 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2612 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2614 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2615 cc_status
.value2
= 0;
2616 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2617 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
2618 cc_status
.flags
= CC_IN_68881
;
2622 output_move_const_double (operands
)
2625 int code
= standard_68881_constant_p (operands
[1]);
2629 static char buf
[40];
2631 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2634 return "fmove%.d %1,%0";
2638 output_move_const_single (operands
)
2641 int code
= standard_68881_constant_p (operands
[1]);
2645 static char buf
[40];
2647 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2650 return "fmove%.s %f1,%0";
2653 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2654 from the "fmovecr" instruction.
2655 The value, anded with 0xff, gives the code to use in fmovecr
2656 to get the desired constant. */
2658 /* This code has been fixed for cross-compilation. */
2660 static int inited_68881_table
= 0;
2662 static const char *const strings_68881
[7] = {
2672 static const int codes_68881
[7] = {
2682 REAL_VALUE_TYPE values_68881
[7];
2684 /* Set up values_68881 array by converting the decimal values
2685 strings_68881 to binary. */
2692 enum machine_mode mode
;
2695 for (i
= 0; i
< 7; i
++)
2699 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2700 values_68881
[i
] = r
;
2702 inited_68881_table
= 1;
2706 standard_68881_constant_p (x
)
2712 #ifdef NO_ASM_FMOVECR
2716 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2717 used at all on those chips. */
2718 if (TARGET_68040
|| TARGET_68060
)
2721 if (! inited_68881_table
)
2722 init_68881_table ();
2724 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2726 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2728 for (i
= 0; i
< 6; i
++)
2730 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2731 return (codes_68881
[i
]);
2734 if (GET_MODE (x
) == SFmode
)
2737 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2738 return (codes_68881
[6]);
2740 /* larger powers of ten in the constants ram are not used
2741 because they are not equal to a `double' C constant. */
2745 /* If X is a floating-point constant, return the logarithm of X base 2,
2746 or 0 if X is not a power of 2. */
2749 floating_exact_log2 (x
)
2752 REAL_VALUE_TYPE r
, r1
;
2755 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2757 if (REAL_VALUES_LESS (r
, dconst1
))
2760 exp
= real_exponent (&r
);
2761 real_2expN (&r1
, exp
);
2762 if (REAL_VALUES_EQUAL (r1
, r
))
2768 /* A C compound statement to output to stdio stream STREAM the
2769 assembler syntax for an instruction operand X. X is an RTL
2772 CODE is a value that can be used to specify one of several ways
2773 of printing the operand. It is used when identical operands
2774 must be printed differently depending on the context. CODE
2775 comes from the `%' specification that was used to request
2776 printing of the operand. If the specification was just `%DIGIT'
2777 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2778 is the ASCII code for LTR.
2780 If X is a register, this macro should print the register's name.
2781 The names can be found in an array `reg_names' whose type is
2782 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2784 When the machine description has a specification `%PUNCT' (a `%'
2785 followed by a punctuation character), this macro is called with
2786 a null pointer for X and the punctuation character for CODE.
2788 The m68k specific codes are:
2790 '.' for dot needed in Motorola-style opcode names.
2791 '-' for an operand pushing on the stack:
2792 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2793 '+' for an operand pushing on the stack:
2794 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2795 '@' for a reference to the top word on the stack:
2796 sp@, (sp) or (%sp) depending on the style of syntax.
2797 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2798 but & in SGS syntax, $ in CRDS/UNOS syntax).
2799 '!' for the cc register (used in an `and to cc' insn).
2800 '$' for the letter `s' in an op code, but only on the 68040.
2801 '&' for the letter `d' in an op code, but only on the 68040.
2802 '/' for register prefix needed by longlong.h.
2804 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2805 'd' to force memory addressing to be absolute, not relative.
2806 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2807 'o' for operands to go directly to output_operand_address (bypassing
2808 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2809 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2810 or print pair of registers as rx:ry.
2815 print_operand (file
, op
, letter
)
2816 FILE *file
; /* file to write to */
2817 rtx op
; /* operand to print */
2818 int letter
; /* %<letter> or 0 */
2822 #if defined (MOTOROLA) && !defined (CRDS)
2823 fprintf (file
, ".");
2826 else if (letter
== '#')
2828 asm_fprintf (file
, "%I");
2830 else if (letter
== '-')
2833 asm_fprintf (file
, "-(%Rsp)");
2835 asm_fprintf (file
, "%Rsp@-");
2838 else if (letter
== '+')
2841 asm_fprintf (file
, "(%Rsp)+");
2843 asm_fprintf (file
, "%Rsp@+");
2846 else if (letter
== '@')
2849 asm_fprintf (file
, "(%Rsp)");
2851 asm_fprintf (file
, "%Rsp@");
2854 else if (letter
== '!')
2856 asm_fprintf (file
, "%Rfpcr");
2858 else if (letter
== '$')
2860 if (TARGET_68040_ONLY
)
2862 fprintf (file
, "s");
2865 else if (letter
== '&')
2867 if (TARGET_68040_ONLY
)
2869 fprintf (file
, "d");
2872 else if (letter
== '/')
2874 asm_fprintf (file
, "%R");
2876 else if (letter
== 'o')
2878 /* This is only for direct addresses with TARGET_PCREL */
2879 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2882 output_addr_const (file
, XEXP (op
, 0));
2884 else if (GET_CODE (op
) == REG
)
2887 /* Print out the second register name of a register pair.
2888 I.e., R (6) => 7. */
2889 fputs (reg_names
[REGNO (op
) + 1], file
);
2891 fputs (reg_names
[REGNO (op
)], file
);
2893 else if (GET_CODE (op
) == MEM
)
2895 output_address (XEXP (op
, 0));
2896 if (letter
== 'd' && ! TARGET_68020
2897 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2898 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2899 && INTVAL (XEXP (op
, 0)) < 0x8000
2900 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2903 fprintf (file
, ".l");
2905 fprintf (file
, ":l");
2909 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2912 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2913 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2915 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2918 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2919 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2921 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2924 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2925 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2929 /* Use `print_operand_address' instead of `output_addr_const'
2930 to ensure that we print relevant PIC stuff. */
2931 asm_fprintf (file
, "%I");
2933 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2934 print_operand_address (file
, op
);
2936 output_addr_const (file
, op
);
2941 /* A C compound statement to output to stdio stream STREAM the
2942 assembler syntax for an instruction operand that is a memory
2943 reference whose address is ADDR. ADDR is an RTL expression.
2945 Note that this contains a kludge that knows that the only reason
2946 we have an address (plus (label_ref...) (reg...)) when not generating
2947 PIC code is in the insn before a tablejump, and we know that m68k.md
2948 generates a label LInnn: on such an insn.
2950 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2951 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2953 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2954 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2955 we want. This difference can be accommodated by using an assembler
2956 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2957 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2958 macro. See m68k/sgs.h for an example; for versions without the bug.
2959 Some assemblers refuse all the above solutions. The workaround is to
2960 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2963 They also do not like things like "pea 1.w", so we simple leave off
2964 the .w on small constants.
2966 This routine is responsible for distinguishing between -fpic and -fPIC
2967 style relocations in an address. When generating -fpic code the
2968 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2969 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2971 #ifndef ASM_OUTPUT_CASE_FETCH
2974 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2975 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2977 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2978 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2981 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2982 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2984 #endif /* ASM_OUTPUT_CASE_FETCH */
2987 print_operand_address (file
, addr
)
2991 register rtx reg1
, reg2
, breg
, ireg
;
2994 switch (GET_CODE (addr
))
2998 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
3000 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
3005 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
3007 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
3012 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
3014 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
3018 reg1
= reg2
= ireg
= breg
= offset
= 0;
3019 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
3021 offset
= XEXP (addr
, 0);
3022 addr
= XEXP (addr
, 1);
3024 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
3026 offset
= XEXP (addr
, 1);
3027 addr
= XEXP (addr
, 0);
3029 if (GET_CODE (addr
) != PLUS
)
3033 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
3035 reg1
= XEXP (addr
, 0);
3036 addr
= XEXP (addr
, 1);
3038 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
3040 reg1
= XEXP (addr
, 1);
3041 addr
= XEXP (addr
, 0);
3043 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
3045 reg1
= XEXP (addr
, 0);
3046 addr
= XEXP (addr
, 1);
3048 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
3050 reg1
= XEXP (addr
, 1);
3051 addr
= XEXP (addr
, 0);
3053 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
3055 reg1
= XEXP (addr
, 0);
3056 addr
= XEXP (addr
, 1);
3058 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3060 reg1
= XEXP (addr
, 1);
3061 addr
= XEXP (addr
, 0);
3063 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3064 || GET_CODE (addr
) == SIGN_EXTEND
)
3076 #if 0 /* for OLD_INDEXING */
3077 else if (GET_CODE (addr
) == PLUS
)
3079 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3081 reg2
= XEXP (addr
, 0);
3082 addr
= XEXP (addr
, 1);
3084 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3086 reg2
= XEXP (addr
, 1);
3087 addr
= XEXP (addr
, 0);
3099 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3100 || GET_CODE (reg1
) == MULT
))
3101 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3106 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3111 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3112 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3115 if (GET_CODE (ireg
) == MULT
)
3117 scale
= INTVAL (XEXP (ireg
, 1));
3118 ireg
= XEXP (ireg
, 0);
3120 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3122 ASM_OUTPUT_CASE_FETCH (file
,
3123 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3124 reg_names
[REGNO (XEXP (ireg
, 0))]);
3125 fprintf (file
, "w");
3129 ASM_OUTPUT_CASE_FETCH (file
,
3130 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3131 reg_names
[REGNO (ireg
)]);
3132 fprintf (file
, "l");
3137 fprintf (file
, "*%d", scale
);
3139 fprintf (file
, ":%d", scale
);
3145 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3146 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3148 ASM_OUTPUT_CASE_FETCH (file
,
3149 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3150 reg_names
[REGNO (breg
)]);
3151 fprintf (file
, "l)");
3154 if (ireg
!= 0 || breg
!= 0)
3161 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3168 output_addr_const (file
, addr
);
3169 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3171 fprintf (file
, "@GOT");
3173 fprintf (file
, ".w");
3176 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3182 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3185 output_addr_const (file
, addr
);
3186 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3187 fprintf (file
, ":w");
3188 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3189 fprintf (file
, ":l");
3191 if (addr
!= 0 && ireg
!= 0)
3196 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3198 scale
= INTVAL (XEXP (ireg
, 1));
3199 ireg
= XEXP (ireg
, 0);
3201 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3204 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3206 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3212 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3214 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3220 fprintf (file
, "*%d", scale
);
3222 fprintf (file
, ":%d", scale
);
3228 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3229 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3231 ASM_OUTPUT_CASE_FETCH (file
,
3232 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3233 reg_names
[REGNO (reg1
)]);
3234 fprintf (file
, "l)");
3237 /* FALL-THROUGH (is this really what we want?) */
3239 if (GET_CODE (addr
) == CONST_INT
3240 && INTVAL (addr
) < 0x8000
3241 && INTVAL (addr
) >= -0x8000)
3245 /* Many SGS assemblers croak on size specifiers for constants. */
3246 fprintf (file
, "%d", (int) INTVAL (addr
));
3248 fprintf (file
, "%d.w", (int) INTVAL (addr
));
3251 fprintf (file
, "%d:w", (int) INTVAL (addr
));
3254 else if (GET_CODE (addr
) == CONST_INT
)
3256 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3258 else if (TARGET_PCREL
)
3261 output_addr_const (file
, addr
);
3263 asm_fprintf (file
, ":w,%Rpc)");
3265 asm_fprintf (file
, ":l,%Rpc)");
3269 /* Special case for SYMBOL_REF if the symbol name ends in
3270 `.<letter>', this can be mistaken as a size suffix. Put
3271 the name in parentheses. */
3272 if (GET_CODE (addr
) == SYMBOL_REF
3273 && strlen (XSTR (addr
, 0)) > 2
3274 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3277 output_addr_const (file
, addr
);
3281 output_addr_const (file
, addr
);
3287 /* Check for cases where a clr insns can be omitted from code using
3288 strict_low_part sets. For example, the second clrl here is not needed:
3289 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3291 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3292 insn we are checking for redundancy. TARGET is the register set by the
3296 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3297 enum machine_mode mode
;
3303 p
= prev_nonnote_insn (first_insn
);
3307 /* If it isn't an insn, then give up. */
3308 if (GET_CODE (p
) != INSN
)
3311 if (reg_set_p (target
, p
))
3313 rtx set
= single_set (p
);
3316 /* If it isn't an easy to recognize insn, then give up. */
3320 dest
= SET_DEST (set
);
3322 /* If this sets the entire target register to zero, then our
3323 first_insn is redundant. */
3324 if (rtx_equal_p (dest
, target
)
3325 && SET_SRC (set
) == const0_rtx
)
3327 else if (GET_CODE (dest
) == STRICT_LOW_PART
3328 && GET_CODE (XEXP (dest
, 0)) == REG
3329 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3330 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3331 <= GET_MODE_SIZE (mode
)))
3332 /* This is a strict low part set which modifies less than
3333 we are using, so it is safe. */
3339 p
= prev_nonnote_insn (p
);
3346 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3347 range carefully since this predicate is used in DImode contexts. Also, we
3348 need some extra crud to make it work when hosted on 64-bit machines. */
3351 const_uint32_operand (op
, mode
)
3353 enum machine_mode mode
;
3355 /* It doesn't make sense to ask this question with a mode that is
3356 not larger than 32 bits. */
3357 if (GET_MODE_BITSIZE (mode
) <= 32)
3360 #if HOST_BITS_PER_WIDE_INT > 32
3361 /* All allowed constants will fit a CONST_INT. */
3362 return (GET_CODE (op
) == CONST_INT
3363 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3365 return (GET_CODE (op
) == CONST_INT
3366 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3370 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3371 to check the range carefully since this predicate is used in DImode
3375 const_sint32_operand (op
, mode
)
3377 enum machine_mode mode
;
3379 /* It doesn't make sense to ask this question with a mode that is
3380 not larger than 32 bits. */
3381 if (GET_MODE_BITSIZE (mode
) <= 32)
3384 /* All allowed constants will fit a CONST_INT. */
3385 return (GET_CODE (op
) == CONST_INT
3386 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3389 /* Operand predicates for implementing asymmetric pc-relative addressing
3390 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3391 when used as a source operand, but not as a destintation operand.
3393 We model this by restricting the meaning of the basic predicates
3394 (general_operand, memory_operand, etc) to forbid the use of this
3395 addressing mode, and then define the following predicates that permit
3396 this addressing mode. These predicates can then be used for the
3397 source operands of the appropriate instructions.
3399 n.b. While it is theoretically possible to change all machine patterns
3400 to use this addressing more where permitted by the architecture,
3401 it has only been implemented for "common" cases: SImode, HImode, and
3402 QImode operands, and only for the principle operations that would
3403 require this addressing mode: data movement and simple integer operations.
3405 In parallel with these new predicates, two new constraint letters
3406 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3407 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3408 In the pcrel case 's' is only valid in combination with 'a' registers.
3409 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3410 of how these constraints are used.
3412 The use of these predicates is strictly optional, though patterns that
3413 don't will cause an extra reload register to be allocated where one
3416 lea (abc:w,%pc),%a0 ; need to reload address
3417 moveq &1,%d1 ; since write to pc-relative space
3418 movel %d1,%a0@ ; is not allowed
3420 lea (abc:w,%pc),%a1 ; no need to reload address here
3421 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3423 For more info, consult tiemann@cygnus.com.
3426 All of the ugliness with predicates and constraints is due to the
3427 simple fact that the m68k does not allow a pc-relative addressing
3428 mode as a destination. gcc does not distinguish between source and
3429 destination addresses. Hence, if we claim that pc-relative address
3430 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3431 end up with invalid code. To get around this problem, we left
3432 pc-relative modes as invalid addresses, and then added special
3433 predicates and constraints to accept them.
3435 A cleaner way to handle this is to modify gcc to distinguish
3436 between source and destination addresses. We can then say that
3437 pc-relative is a valid source address but not a valid destination
3438 address, and hopefully avoid a lot of the predicate and constraint
3439 hackery. Unfortunately, this would be a pretty big change. It would
3440 be a useful change for a number of ports, but there aren't any current
3441 plans to undertake this.
3443 ***************************************************************************/
3446 /* Special case of a general operand that's used as a source operand.
3447 Use this to permit reads from PC-relative memory when -mpcrel
3451 general_src_operand (op
, mode
)
3453 enum machine_mode mode
;
3456 && GET_CODE (op
) == MEM
3457 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3458 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3459 || GET_CODE (XEXP (op
, 0)) == CONST
))
3461 return general_operand (op
, mode
);
3464 /* Special case of a nonimmediate operand that's used as a source.
3465 Use this to permit reads from PC-relative memory when -mpcrel
3469 nonimmediate_src_operand (op
, mode
)
3471 enum machine_mode mode
;
3473 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3474 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3475 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3476 || GET_CODE (XEXP (op
, 0)) == CONST
))
3478 return nonimmediate_operand (op
, mode
);
3481 /* Special case of a memory operand that's used as a source.
3482 Use this to permit reads from PC-relative memory when -mpcrel
3486 memory_src_operand (op
, mode
)
3488 enum machine_mode mode
;
3490 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3491 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3492 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3493 || GET_CODE (XEXP (op
, 0)) == CONST
))
3495 return memory_operand (op
, mode
);
3498 /* Predicate that accepts only a pc-relative address. This is needed
3499 because pc-relative addresses don't satisfy the predicate
3500 "general_src_operand". */
3503 pcrel_address (op
, mode
)
3505 enum machine_mode mode ATTRIBUTE_UNUSED
;
3507 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3508 || GET_CODE (op
) == CONST
);
3512 output_andsi3 (operands
)
3516 if (GET_CODE (operands
[2]) == CONST_INT
3517 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3518 && (DATA_REG_P (operands
[0])
3519 || offsettable_memref_p (operands
[0]))
3522 if (GET_CODE (operands
[0]) != REG
)
3523 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3524 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3525 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3527 if (operands
[2] == const0_rtx
)
3529 return "and%.w %2,%0";
3531 if (GET_CODE (operands
[2]) == CONST_INT
3532 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3533 && (DATA_REG_P (operands
[0])
3534 || offsettable_memref_p (operands
[0])))
3536 if (DATA_REG_P (operands
[0]))
3538 operands
[1] = GEN_INT (logval
);
3542 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3543 operands
[1] = GEN_INT (logval
% 8);
3545 /* This does not set condition codes in a standard way. */
3547 return "bclr %1,%0";
3549 return "and%.l %2,%0";
3553 output_iorsi3 (operands
)
3556 register int logval
;
3557 if (GET_CODE (operands
[2]) == CONST_INT
3558 && INTVAL (operands
[2]) >> 16 == 0
3559 && (DATA_REG_P (operands
[0])
3560 || offsettable_memref_p (operands
[0]))
3563 if (GET_CODE (operands
[0]) != REG
)
3564 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3565 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3567 if (INTVAL (operands
[2]) == 0xffff)
3568 return "mov%.w %2,%0";
3569 return "or%.w %2,%0";
3571 if (GET_CODE (operands
[2]) == CONST_INT
3572 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3573 && (DATA_REG_P (operands
[0])
3574 || offsettable_memref_p (operands
[0])))
3576 if (DATA_REG_P (operands
[0]))
3577 operands
[1] = GEN_INT (logval
);
3580 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3581 operands
[1] = GEN_INT (logval
% 8);
3584 return "bset %1,%0";
3586 return "or%.l %2,%0";
3590 output_xorsi3 (operands
)
3593 register int logval
;
3594 if (GET_CODE (operands
[2]) == CONST_INT
3595 && INTVAL (operands
[2]) >> 16 == 0
3596 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3599 if (! DATA_REG_P (operands
[0]))
3600 operands
[0] = adjust_address (operands
[0], HImode
, 2);
3601 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3603 if (INTVAL (operands
[2]) == 0xffff)
3605 return "eor%.w %2,%0";
3607 if (GET_CODE (operands
[2]) == CONST_INT
3608 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3609 && (DATA_REG_P (operands
[0])
3610 || offsettable_memref_p (operands
[0])))
3612 if (DATA_REG_P (operands
[0]))
3613 operands
[1] = GEN_INT (logval
);
3616 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
3617 operands
[1] = GEN_INT (logval
% 8);
3620 return "bchg %1,%0";
3622 return "eor%.l %2,%0";
3625 /* Output assembly to switch to section NAME with attribute FLAGS. */
3628 m68k_coff_asm_named_section (name
, flags
)
3634 if (flags
& SECTION_WRITE
)
3639 fprintf (asm_out_file
, "\t.section\t%s,\"%c\"\n", name
, flagchar
);
3642 #ifdef CTOR_LIST_BEGIN
3644 m68k_svr3_asm_out_constructor (symbol
, priority
)
3646 int priority ATTRIBUTE_UNUSED
;
3651 xop
[0] = gen_rtx_MEM (SImode
, gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
));
3654 output_asm_insn (output_move_simode (xop
), xop
);
3660 m68k_hp320_internal_label (stream
, prefix
, labelno
)
3663 unsigned long labelno
;
3665 if (prefix
[0] == 'L' && prefix
[1] == 'I')
3666 fprintf(stream
, "\tset %s%ld,.+2\n", prefix
, labelno
);
3668 fprintf (stream
, "%s%ld:\n", prefix
, labelno
);
3672 m68k_hp320_file_start ()
3674 /* version 1: 68010.
3675 2: 68020 without FPU.
3676 3: 68020 with FPU. */
3677 fprintf (asm_out_file
, "\tversion %d\n",
3678 TARGET_68020
? (TARGET_68881
? 3 : 2) : 1);
3683 m68k_output_mi_thunk (file
, thunk
, delta
, vcall_offset
, function
)
3685 tree thunk ATTRIBUTE_UNUSED
;
3686 HOST_WIDE_INT delta
;
3687 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
;
3693 if (delta
> 0 && delta
<= 8)
3694 asm_fprintf (file
, "\taddq.l %I%d,4(%Rsp)\n", (int) delta
);
3695 else if (delta
< 0 && delta
>= -8)
3696 asm_fprintf (file
, "\tsubq.l %I%d,4(%Rsp)\n", (int) -delta
);
3698 asm_fprintf (file
, "\tadd.l %I%wd,4(%Rsp)\n", delta
);
3700 xops
[0] = DECL_RTL (function
);
3702 /* Logic taken from call patterns in m68k.md. */
3714 fmt
= "bra.l %0@PLTPC";
3716 fmt
= "bra %0@PLTPC";
3730 #if defined (MOTOROLA) && !defined (USE_GAS)
3741 output_asm_insn (fmt
, xops
);