1 /* Target Code for R8C/M16C/M32C
2 Copyright (C) 2005-2019 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
30 #include "stringpool.h"
39 #include "diagnostic-core.h"
41 #include "insn-attr.h"
44 #include "stor-layout.h"
49 #include "tm-constrs.h"
52 /* This file should be included last. */
53 #include "target-def.h"
57 /* Used by m32c_pushm_popm. */
65 static bool m32c_function_needs_enter (void);
66 static tree
interrupt_handler (tree
*, tree
, tree
, int, bool *);
67 static tree
function_vector_handler (tree
*, tree
, tree
, int, bool *);
68 static int interrupt_p (tree node
);
69 static int bank_switch_p (tree node
);
70 static int fast_interrupt_p (tree node
);
71 static int interrupt_p (tree node
);
72 static bool m32c_asm_integer (rtx
, unsigned int, int);
73 static int m32c_comp_type_attributes (const_tree
, const_tree
);
74 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
75 static struct machine_function
*m32c_init_machine_status (void);
76 static void m32c_insert_attributes (tree
, tree
*);
77 static bool m32c_legitimate_address_p (machine_mode
, rtx
, bool);
78 static bool m32c_addr_space_legitimate_address_p (machine_mode
, rtx
, bool, addr_space_t
);
79 static rtx
m32c_function_arg (cumulative_args_t
, const function_arg_info
&);
80 static bool m32c_pass_by_reference (cumulative_args_t
,
81 const function_arg_info
&);
82 static void m32c_function_arg_advance (cumulative_args_t
,
83 const function_arg_info
&);
84 static unsigned int m32c_function_arg_boundary (machine_mode
, const_tree
);
85 static int m32c_pushm_popm (Push_Pop_Type
);
86 static bool m32c_strict_argument_naming (cumulative_args_t
);
87 static rtx
m32c_struct_value_rtx (tree
, int);
88 static rtx
m32c_subreg (machine_mode
, rtx
, machine_mode
, int);
89 static int need_to_save (int);
90 static rtx
m32c_function_value (const_tree
, const_tree
, bool);
91 static rtx
m32c_libcall_value (machine_mode
, const_rtx
);
93 /* Returns true if an address is specified, else false. */
94 static bool m32c_get_pragma_address (const char *varname
, unsigned *addr
);
96 static bool m32c_hard_regno_mode_ok (unsigned int, machine_mode
);
98 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
100 #define streq(a,b) (strcmp ((a), (b)) == 0)
102 /* Internal support routines */
104 /* Debugging statements are tagged with DEBUG0 only so that they can
105 be easily enabled individually, by replacing the '0' with '1' as
111 #include "print-tree.h"
112 /* This is needed by some of the commented-out debug statements
114 static char const *class_names
[LIM_REG_CLASSES
] = REG_CLASS_NAMES
;
116 static int class_contents
[LIM_REG_CLASSES
][1] = REG_CLASS_CONTENTS
;
118 /* These are all to support encode_pattern(). */
119 static char pattern
[30], *patternp
;
120 static GTY(()) rtx patternr
[30];
121 #define RTX_IS(x) (streq (pattern, x))
123 /* Some macros to simplify the logic throughout this file. */
124 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
125 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
127 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
128 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
131 far_addr_space_p (rtx x
)
133 if (GET_CODE (x
) != MEM
)
136 fprintf(stderr
, "\033[35mfar_addr_space: "); debug_rtx(x
);
137 fprintf(stderr
, " = %d\033[0m\n", MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
);
139 return MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
;
142 /* We do most RTX matching by converting the RTX into a string, and
143 using string compares. This vastly simplifies the logic in many of
144 the functions in this file.
146 On exit, pattern[] has the encoded string (use RTX_IS("...") to
147 compare it) and patternr[] has pointers to the nodes in the RTX
148 corresponding to each character in the encoded string. The latter
149 is mostly used by print_operand().
151 Unrecognized patterns have '?' in them; this shows up when the
152 assembler complains about syntax errors.
156 encode_pattern_1 (rtx x
)
160 if (patternp
== pattern
+ sizeof (pattern
) - 2)
166 patternr
[patternp
- pattern
] = x
;
168 switch (GET_CODE (x
))
174 if (GET_MODE_SIZE (GET_MODE (x
)) !=
175 GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))))
177 if (GET_MODE (x
) == PSImode
178 && GET_CODE (XEXP (x
, 0)) == REG
)
180 encode_pattern_1 (XEXP (x
, 0));
186 encode_pattern_1 (XEXP (x
, 0));
191 encode_pattern_1 (XEXP (x
, 0));
196 encode_pattern_1 (XEXP (x
, 0));
200 encode_pattern_1 (XEXP (x
, 0));
201 encode_pattern_1 (XEXP (x
, 1));
205 encode_pattern_1 (XEXP (x
, 0));
209 encode_pattern_1 (XEXP (x
, 0));
213 encode_pattern_1 (XEXP (x
, 0));
214 encode_pattern_1 (XEXP (x
, 1));
218 encode_pattern_1 (XEXP (x
, 0));
235 *patternp
++ = '0' + XCINT (x
, 1, UNSPEC
);
236 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
237 encode_pattern_1 (XVECEXP (x
, 0, i
));
244 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
245 encode_pattern_1 (XVECEXP (x
, 0, i
));
249 encode_pattern_1 (XEXP (x
, 0));
251 encode_pattern_1 (XEXP (x
, 1));
256 fprintf (stderr
, "can't encode pattern %s\n",
257 GET_RTX_NAME (GET_CODE (x
)));
265 encode_pattern (rtx x
)
268 encode_pattern_1 (x
);
272 /* Since register names indicate the mode they're used in, we need a
273 way to determine which name to refer to the register with. Called
274 by print_operand(). */
277 reg_name_with_mode (int regno
, machine_mode mode
)
279 int mlen
= GET_MODE_SIZE (mode
);
280 if (regno
== R0_REGNO
&& mlen
== 1)
282 if (regno
== R0_REGNO
&& (mlen
== 3 || mlen
== 4))
284 if (regno
== R0_REGNO
&& mlen
== 6)
286 if (regno
== R0_REGNO
&& mlen
== 8)
288 if (regno
== R1_REGNO
&& mlen
== 1)
290 if (regno
== R1_REGNO
&& (mlen
== 3 || mlen
== 4))
292 if (regno
== A0_REGNO
&& TARGET_A16
&& (mlen
== 3 || mlen
== 4))
294 return reg_names
[regno
];
297 /* How many bytes a register uses on stack when it's pushed. We need
298 to know this because the push opcode needs to explicitly indicate
299 the size of the register, even though the name of the register
300 already tells it that. Used by m32c_output_reg_{push,pop}, which
301 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
304 reg_push_size (int regno
)
329 /* Given two register classes, find the largest intersection between
330 them. If there is no intersection, return RETURNED_IF_EMPTY
333 reduce_class (reg_class_t original_class
, reg_class_t limiting_class
,
334 reg_class_t returned_if_empty
)
338 reg_class_t best
= NO_REGS
;
339 unsigned int best_size
= 0;
341 if (original_class
== limiting_class
)
342 return original_class
;
344 cc
= reg_class_contents
[original_class
];
345 AND_HARD_REG_SET (cc
, reg_class_contents
[limiting_class
]);
347 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
349 if (hard_reg_set_subset_p (reg_class_contents
[i
], cc
))
350 if (best_size
< reg_class_size
[i
])
352 best
= (reg_class_t
) i
;
353 best_size
= reg_class_size
[i
];
358 return returned_if_empty
;
362 /* Used by m32c_register_move_cost to determine if a move is
363 impossibly expensive. */
365 class_can_hold_mode (reg_class_t rclass
, machine_mode mode
)
367 /* Cache the results: 0=untested 1=no 2=yes */
368 static char results
[LIM_REG_CLASSES
][MAX_MACHINE_MODE
];
370 if (results
[(int) rclass
][mode
] == 0)
373 results
[rclass
][mode
] = 1;
374 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
375 if (in_hard_reg_set_p (reg_class_contents
[(int) rclass
], mode
, r
)
376 && m32c_hard_regno_mode_ok (r
, mode
))
378 results
[rclass
][mode
] = 2;
384 fprintf (stderr
, "class %s can hold %s? %s\n",
385 class_names
[(int) rclass
], mode_name
[mode
],
386 (results
[rclass
][mode
] == 2) ? "yes" : "no");
388 return results
[(int) rclass
][mode
] == 2;
391 /* Run-time Target Specification. */
393 /* Memregs are memory locations that gcc treats like general
394 registers, as there are a limited number of true registers and the
395 m32c families can use memory in most places that registers can be
398 However, since memory accesses are more expensive than registers,
399 we allow the user to limit the number of memregs available, in
400 order to try to persuade gcc to try harder to use real registers.
402 Memregs are provided by lib1funcs.S.
405 int ok_to_change_target_memregs
= TRUE
;
407 /* Implements TARGET_OPTION_OVERRIDE. */
409 #undef TARGET_OPTION_OVERRIDE
410 #define TARGET_OPTION_OVERRIDE m32c_option_override
413 m32c_option_override (void)
415 /* We limit memregs to 0..16, and provide a default. */
416 if (global_options_set
.x_target_memregs
)
418 if (target_memregs
< 0 || target_memregs
> 16)
419 error ("invalid target memregs value %<%d%>", target_memregs
);
427 /* This target defaults to strict volatile bitfields. */
428 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
429 flag_strict_volatile_bitfields
= 1;
431 /* r8c/m16c have no 16-bit indirect call, so thunks are involved.
432 This is always worse than an absolute call. */
434 flag_no_function_cse
= 1;
436 /* This wants to put insns between compares and their jumps. */
437 /* FIXME: The right solution is to properly trace the flags register
438 values, but that is too much work for stage 4. */
439 flag_combine_stack_adjustments
= 0;
442 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
443 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change
446 m32c_override_options_after_change (void)
449 flag_no_function_cse
= 1;
452 /* Defining data structures for per-function information */
454 /* The usual; we set up our machine_function data. */
455 static struct machine_function
*
456 m32c_init_machine_status (void)
458 return ggc_cleared_alloc
<machine_function
> ();
461 /* Implements INIT_EXPANDERS. We just set up to call the above
464 m32c_init_expanders (void)
466 init_machine_status
= m32c_init_machine_status
;
471 /* Register Basics */
473 /* Basic Characteristics of Registers */
475 /* Whether a mode fits in a register is complex enough to warrant a
484 } nregs_table
[FIRST_PSEUDO_REGISTER
] =
486 { 1, 1, 2, 2, 4 }, /* r0 */
487 { 0, 1, 0, 0, 0 }, /* r2 */
488 { 1, 1, 2, 2, 0 }, /* r1 */
489 { 0, 1, 0, 0, 0 }, /* r3 */
490 { 0, 1, 1, 0, 0 }, /* a0 */
491 { 0, 1, 1, 0, 0 }, /* a1 */
492 { 0, 1, 1, 0, 0 }, /* sb */
493 { 0, 1, 1, 0, 0 }, /* fb */
494 { 0, 1, 1, 0, 0 }, /* sp */
495 { 1, 1, 1, 0, 0 }, /* pc */
496 { 0, 0, 0, 0, 0 }, /* fl */
497 { 1, 1, 1, 0, 0 }, /* ap */
498 { 1, 1, 2, 2, 4 }, /* mem0 */
499 { 1, 1, 2, 2, 4 }, /* mem1 */
500 { 1, 1, 2, 2, 4 }, /* mem2 */
501 { 1, 1, 2, 2, 4 }, /* mem3 */
502 { 1, 1, 2, 2, 4 }, /* mem4 */
503 { 1, 1, 2, 2, 0 }, /* mem5 */
504 { 1, 1, 2, 2, 0 }, /* mem6 */
505 { 1, 1, 0, 0, 0 }, /* mem7 */
508 /* Implements TARGET_CONDITIONAL_REGISTER_USAGE. We adjust the number
509 of available memregs, and select which registers need to be preserved
510 across calls based on the chip family. */
512 #undef TARGET_CONDITIONAL_REGISTER_USAGE
513 #define TARGET_CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage
515 m32c_conditional_register_usage (void)
519 if (target_memregs
>= 0 && target_memregs
<= 16)
521 /* The command line option is bytes, but our "registers" are
523 for (i
= (target_memregs
+1)/2; i
< 8; i
++)
525 fixed_regs
[MEM0_REGNO
+ i
] = 1;
526 CLEAR_HARD_REG_BIT (reg_class_contents
[MEM_REGS
], MEM0_REGNO
+ i
);
530 /* M32CM and M32C preserve more registers across function calls. */
533 call_used_regs
[R1_REGNO
] = 0;
534 call_used_regs
[R2_REGNO
] = 0;
535 call_used_regs
[R3_REGNO
] = 0;
536 call_used_regs
[A0_REGNO
] = 0;
537 call_used_regs
[A1_REGNO
] = 0;
541 /* How Values Fit in Registers */
543 /* Implements TARGET_HARD_REGNO_NREGS. This is complicated by the fact that
544 different registers are different sizes from each other, *and* may
545 be different sizes in different chip families. */
547 m32c_hard_regno_nregs_1 (unsigned int regno
, machine_mode mode
)
549 if (regno
== FLG_REGNO
&& mode
== CCmode
)
551 if (regno
>= FIRST_PSEUDO_REGISTER
)
552 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
554 if (regno
>= MEM0_REGNO
&& regno
<= MEM7_REGNO
)
555 return (GET_MODE_SIZE (mode
) + 1) / 2;
557 if (GET_MODE_SIZE (mode
) <= 1)
558 return nregs_table
[regno
].qi_regs
;
559 if (GET_MODE_SIZE (mode
) <= 2)
560 return nregs_table
[regno
].hi_regs
;
561 if (regno
== A0_REGNO
&& mode
== SImode
&& TARGET_A16
)
563 if ((GET_MODE_SIZE (mode
) <= 3 || mode
== PSImode
) && TARGET_A24
)
564 return nregs_table
[regno
].pi_regs
;
565 if (GET_MODE_SIZE (mode
) <= 4)
566 return nregs_table
[regno
].si_regs
;
567 if (GET_MODE_SIZE (mode
) <= 8)
568 return nregs_table
[regno
].di_regs
;
573 m32c_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
575 unsigned int rv
= m32c_hard_regno_nregs_1 (regno
, mode
);
579 /* Implement TARGET_HARD_REGNO_MODE_OK. The above function does the work
580 already; just test its return value. */
582 m32c_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
584 return m32c_hard_regno_nregs_1 (regno
, mode
) != 0;
587 /* Implement TARGET_MODES_TIEABLE_P. In general, modes aren't tieable since
588 registers are all different sizes. However, since most modes are
589 bigger than our registers anyway, it's easier to implement this
590 function that way, leaving QImode as the only unique case. */
592 m32c_modes_tieable_p (machine_mode m1
, machine_mode m2
)
594 if (GET_MODE_SIZE (m1
) == GET_MODE_SIZE (m2
))
598 if (m1
== QImode
|| m2
== QImode
)
605 /* Register Classes */
607 /* Implements REGNO_REG_CLASS. */
609 m32c_regno_reg_class (int regno
)
634 if (IS_MEM_REGNO (regno
))
640 /* Implements REGNO_OK_FOR_BASE_P. */
642 m32c_regno_ok_for_base_p (int regno
)
644 if (regno
== A0_REGNO
645 || regno
== A1_REGNO
|| regno
>= FIRST_PSEUDO_REGISTER
)
650 /* Implements TARGET_PREFERRED_RELOAD_CLASS. In general, prefer general
651 registers of the appropriate size. */
653 #undef TARGET_PREFERRED_RELOAD_CLASS
654 #define TARGET_PREFERRED_RELOAD_CLASS m32c_preferred_reload_class
657 m32c_preferred_reload_class (rtx x
, reg_class_t rclass
)
659 reg_class_t newclass
= rclass
;
662 fprintf (stderr
, "\npreferred_reload_class for %s is ",
663 class_names
[rclass
]);
665 if (rclass
== NO_REGS
)
666 rclass
= GET_MODE (x
) == QImode
? HL_REGS
: R03_REGS
;
668 if (reg_classes_intersect_p (rclass
, CR_REGS
))
670 switch (GET_MODE (x
))
676 /* newclass = HI_REGS; */
681 else if (newclass
== QI_REGS
&& GET_MODE_SIZE (GET_MODE (x
)) > 2)
683 else if (GET_MODE_SIZE (GET_MODE (x
)) > 4
684 && ! reg_class_subset_p (R03_REGS
, rclass
))
687 rclass
= reduce_class (rclass
, newclass
, rclass
);
689 if (GET_MODE (x
) == QImode
)
690 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
693 fprintf (stderr
, "%s\n", class_names
[rclass
]);
696 if (GET_CODE (x
) == MEM
697 && GET_CODE (XEXP (x
, 0)) == PLUS
698 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
699 fprintf (stderr
, "Glorm!\n");
704 /* Implements TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
706 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
707 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS m32c_preferred_output_reload_class
710 m32c_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
712 return m32c_preferred_reload_class (x
, rclass
);
715 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
716 address registers for reloads since they're needed for address
719 m32c_limit_reload_class (machine_mode mode
, int rclass
)
722 fprintf (stderr
, "limit_reload_class for %s: %s ->",
723 mode_name
[mode
], class_names
[rclass
]);
727 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
728 else if (mode
== HImode
)
729 rclass
= reduce_class (rclass
, HI_REGS
, rclass
);
730 else if (mode
== SImode
)
731 rclass
= reduce_class (rclass
, SI_REGS
, rclass
);
733 if (rclass
!= A_REGS
)
734 rclass
= reduce_class (rclass
, DI_REGS
, rclass
);
737 fprintf (stderr
, " %s\n", class_names
[rclass
]);
742 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
743 r0 or r1, as those are the only real QImode registers. CR regs get
744 reloaded through appropriately sized general or address
747 m32c_secondary_reload_class (int rclass
, machine_mode mode
, rtx x
)
749 int cc
= class_contents
[rclass
][0];
751 fprintf (stderr
, "\nsecondary reload class %s %s\n",
752 class_names
[rclass
], mode_name
[mode
]);
756 && GET_CODE (x
) == MEM
&& (cc
& ~class_contents
[R23_REGS
][0]) == 0)
758 if (reg_classes_intersect_p (rclass
, CR_REGS
)
759 && GET_CODE (x
) == REG
760 && REGNO (x
) >= SB_REGNO
&& REGNO (x
) <= SP_REGNO
)
761 return (TARGET_A16
|| mode
== HImode
) ? HI_REGS
: A_REGS
;
765 /* Implements TARGET_CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
768 #undef TARGET_CLASS_LIKELY_SPILLED_P
769 #define TARGET_CLASS_LIKELY_SPILLED_P m32c_class_likely_spilled_p
772 m32c_class_likely_spilled_p (reg_class_t regclass
)
774 if (regclass
== A_REGS
)
777 return (reg_class_size
[(int) regclass
] == 1);
780 /* Implements TARGET_CLASS_MAX_NREGS. We calculate this according to its
781 documented meaning, to avoid potential inconsistencies with actual
782 class definitions. */
784 #undef TARGET_CLASS_MAX_NREGS
785 #define TARGET_CLASS_MAX_NREGS m32c_class_max_nregs
788 m32c_class_max_nregs (reg_class_t regclass
, machine_mode mode
)
791 unsigned char max
= 0;
793 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
794 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) regclass
], rn
))
796 unsigned char n
= m32c_hard_regno_nregs (rn
, mode
);
803 /* Implements TARGET_CAN_CHANGE_MODE_CLASS. Only r0 and r1 can change to
804 QI (r0l, r1l) because the chip doesn't support QI ops on other
805 registers (well, it does on a0/a1 but if we let gcc do that, reload
806 suffers). Otherwise, we allow changes to larger modes. */
808 m32c_can_change_mode_class (machine_mode from
,
809 machine_mode to
, reg_class_t rclass
)
813 fprintf (stderr
, "can change from %s to %s in %s\n",
814 mode_name
[from
], mode_name
[to
], class_names
[rclass
]);
817 /* If the larger mode isn't allowed in any of these registers, we
818 can't allow the change. */
819 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
820 if (class_contents
[rclass
][0] & (1 << rn
))
821 if (! m32c_hard_regno_mode_ok (rn
, to
))
825 return (class_contents
[rclass
][0] & 0x1ffa) == 0;
827 if (class_contents
[rclass
][0] & 0x0005 /* r0, r1 */
828 && GET_MODE_SIZE (from
) > 1)
830 if (GET_MODE_SIZE (from
) > 2) /* all other regs */
836 /* Helpers for the rest of the file. */
837 /* TRUE if the rtx is a REG rtx for the given register. */
838 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
839 && REGNO (rtx) == regno)
840 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
841 base register in address calculations (hence the "strict"
843 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
844 && (REGNO (rtx) == AP_REGNO \
845 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
847 #define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)
849 /* Implements matching for constraints (see next function too). 'S' is
850 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
851 call return values. */
853 m32c_matches_constraint_p (rtx value
, int constraint
)
855 encode_pattern (value
);
857 switch (constraint
) {
859 return (far_addr_space_p (value
)
861 && A0_OR_PSEUDO (patternr
[1])
862 && GET_MODE (patternr
[1]) == SImode
)
863 || (RTX_IS ("m+^Sri")
864 && A0_OR_PSEUDO (patternr
[4])
865 && GET_MODE (patternr
[4]) == HImode
)
866 || (RTX_IS ("m+^Srs")
867 && A0_OR_PSEUDO (patternr
[4])
868 && GET_MODE (patternr
[4]) == HImode
)
869 || (RTX_IS ("m+^S+ris")
870 && A0_OR_PSEUDO (patternr
[5])
871 && GET_MODE (patternr
[5]) == HImode
)
875 /* This is the common "src/dest" address */
877 if (GET_CODE (value
) == MEM
&& CONSTANT_P (XEXP (value
, 0)))
879 if (RTX_IS ("ms") || RTX_IS ("m+si"))
881 if (RTX_IS ("m++rii"))
883 if (REGNO (patternr
[3]) == FB_REGNO
884 && INTVAL (patternr
[4]) == 0)
889 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
893 if (REGNO (r
) == SP_REGNO
)
895 return m32c_legitimate_address_p (GET_MODE (value
), XEXP (value
, 0), 1);
902 else if (RTX_IS ("m+ri"))
906 return (IS_REG (r
, A0_REGNO
) || IS_REG (r
, A1_REGNO
));
909 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
911 return ((RTX_IS ("mr")
912 && (IS_REG (patternr
[1], SP_REGNO
)))
913 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SP_REGNO
))));
915 return ((RTX_IS ("mr")
916 && (IS_REG (patternr
[1], FB_REGNO
)))
917 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], FB_REGNO
))));
919 return ((RTX_IS ("mr")
920 && (IS_REG (patternr
[1], SB_REGNO
)))
921 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SB_REGNO
))));
923 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
924 return (RTX_IS ("mi")
925 && !(INTVAL (patternr
[1]) & ~0x1fff));
927 return r1h_operand (value
, QImode
);
929 return GET_CODE (value
) == PARALLEL
;
935 /* STACK AND CALLING */
939 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
940 (yes, THREE bytes) onto the stack for the return address, but we
941 don't support pointers bigger than 16 bits on those chips. This
942 will likely wreak havoc with exception unwinding. FIXME. */
944 m32c_return_addr_rtx (int count
)
956 /* It's four bytes */
962 /* FIXME: it's really 3 bytes */
968 gen_rtx_MEM (mode
, plus_constant (Pmode
, gen_rtx_REG (Pmode
, FP_REGNO
),
970 return copy_to_mode_reg (mode
, ra_mem
);
973 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
975 m32c_incoming_return_addr_rtx (void)
978 return gen_rtx_MEM (PSImode
, gen_rtx_REG (PSImode
, SP_REGNO
));
981 /* Exception Handling Support */
983 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
986 m32c_eh_return_data_regno (int n
)
995 return INVALID_REGNUM
;
999 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1000 m32c_emit_eh_epilogue. */
1002 m32c_eh_return_stackadj_rtx (void)
1004 if (!cfun
->machine
->eh_stack_adjust
)
1008 sa
= gen_rtx_REG (Pmode
, R0_REGNO
);
1009 cfun
->machine
->eh_stack_adjust
= sa
;
1011 return cfun
->machine
->eh_stack_adjust
;
1014 /* Registers That Address the Stack Frame */
1016 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1017 the original spec called for dwarf numbers to vary with register
1018 width as well, for example, r0l, r0, and r2r0 would each have
1019 different dwarf numbers. GCC doesn't support this, and we don't do
1020 it, and gdb seems to like it this way anyway. */
1022 m32c_dwarf_frame_regnum (int n
)
1048 return DWARF_FRAME_REGISTERS
+ 1;
1052 /* The frame looks like this:
1054 ap -> +------------------------------
1055 | Return address (3 or 4 bytes)
1056 | Saved FB (2 or 4 bytes)
1057 fb -> +------------------------------
1060 | through r0 as needed
1061 sp -> +------------------------------
1064 /* We use this to wrap all emitted insns in the prologue. */
1068 RTX_FRAME_RELATED_P (x
) = 1;
1072 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1073 how much the stack pointer moves for each, for each cpu family. */
1082 /* These are in reverse push (nearest-to-sp) order. */
1083 { R0_REGNO
, 0x80, 2, 2 },
1084 { R1_REGNO
, 0x40, 2, 2 },
1085 { R2_REGNO
, 0x20, 2, 2 },
1086 { R3_REGNO
, 0x10, 2, 2 },
1087 { A0_REGNO
, 0x08, 2, 4 },
1088 { A1_REGNO
, 0x04, 2, 4 },
1089 { SB_REGNO
, 0x02, 2, 4 },
1090 { FB_REGNO
, 0x01, 2, 4 }
1093 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1095 /* Returns TRUE if we need to save/restore the given register. We
1096 save everything for exception handlers, so that any register can be
1097 unwound. For interrupt handlers, we save everything if the handler
1098 calls something else (because we don't know what *that* function
1099 might do), but try to be a bit smarter if the handler is a leaf
1100 function. We always save $a0, though, because we use that in the
1101 epilogue to copy $fb to $sp. */
1103 need_to_save (int regno
)
1105 if (fixed_regs
[regno
])
1107 if (crtl
->calls_eh_return
)
1109 if (regno
== FP_REGNO
)
1111 if (cfun
->machine
->is_interrupt
1112 && (!cfun
->machine
->is_leaf
1113 || (regno
== A0_REGNO
1114 && m32c_function_needs_enter ())
1117 if (df_regs_ever_live_p (regno
)
1118 && (!call_used_regs
[regno
] || cfun
->machine
->is_interrupt
))
1123 /* This function contains all the intelligence about saving and
1124 restoring registers. It always figures out the register save set.
1125 When called with PP_justcount, it merely returns the size of the
1126 save set (for eliminating the frame pointer, for example). When
1127 called with PP_pushm or PP_popm, it emits the appropriate
1128 instructions for saving (pushm) or restoring (popm) the
1131 m32c_pushm_popm (Push_Pop_Type ppt
)
1134 int byte_count
= 0, bytes
;
1136 rtx dwarf_set
[PUSHM_N
];
1138 int nosave_mask
= 0;
1140 if (crtl
->return_rtx
1141 && GET_CODE (crtl
->return_rtx
) == PARALLEL
1142 && !(crtl
->calls_eh_return
|| cfun
->machine
->is_interrupt
))
1144 rtx exp
= XVECEXP (crtl
->return_rtx
, 0, 0);
1145 rtx rv
= XEXP (exp
, 0);
1146 int rv_bytes
= GET_MODE_SIZE (GET_MODE (rv
));
1149 nosave_mask
|= 0x20; /* PSI, SI */
1151 nosave_mask
|= 0xf0; /* DF */
1153 nosave_mask
|= 0x50; /* DI */
1156 for (i
= 0; i
< (int) PUSHM_N
; i
++)
1158 /* Skip if neither register needs saving. */
1159 if (!need_to_save (pushm_info
[i
].reg1
))
1162 if (pushm_info
[i
].bit
& nosave_mask
)
1165 reg_mask
|= pushm_info
[i
].bit
;
1166 bytes
= TARGET_A16
? pushm_info
[i
].a16_bytes
: pushm_info
[i
].a24_bytes
;
1168 if (ppt
== PP_pushm
)
1170 machine_mode mode
= (bytes
== 2) ? HImode
: SImode
;
1173 /* Always use stack_pointer_rtx instead of calling
1174 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1175 that there is a single rtx representing the stack pointer,
1176 namely stack_pointer_rtx, and uses == to recognize it. */
1177 addr
= stack_pointer_rtx
;
1179 if (byte_count
!= 0)
1180 addr
= gen_rtx_PLUS (GET_MODE (addr
), addr
, GEN_INT (byte_count
));
1182 dwarf_set
[n_dwarfs
++] =
1183 gen_rtx_SET (gen_rtx_MEM (mode
, addr
),
1184 gen_rtx_REG (mode
, pushm_info
[i
].reg1
));
1185 F (dwarf_set
[n_dwarfs
- 1]);
1188 byte_count
+= bytes
;
1191 if (cfun
->machine
->is_interrupt
)
1193 cfun
->machine
->intr_pushm
= reg_mask
& 0xfe;
1198 if (cfun
->machine
->is_interrupt
)
1199 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1200 if (need_to_save (i
))
1203 cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
] = 1;
1206 if (ppt
== PP_pushm
&& byte_count
)
1208 rtx note
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (n_dwarfs
+ 1));
1213 XVECEXP (note
, 0, 0)
1214 = gen_rtx_SET (stack_pointer_rtx
,
1215 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx
),
1217 GEN_INT (-byte_count
)));
1218 F (XVECEXP (note
, 0, 0));
1220 for (i
= 0; i
< n_dwarfs
; i
++)
1221 XVECEXP (note
, 0, i
+ 1) = dwarf_set
[i
];
1223 pushm
= F (emit_insn (gen_pushm (GEN_INT (reg_mask
))));
1225 add_reg_note (pushm
, REG_FRAME_RELATED_EXPR
, note
);
1228 if (cfun
->machine
->is_interrupt
)
1229 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1230 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1233 pushm
= emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode
, i
)));
1235 pushm
= emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode
, i
)));
1239 if (ppt
== PP_popm
&& byte_count
)
1241 if (cfun
->machine
->is_interrupt
)
1242 for (i
= MEM7_REGNO
; i
>= MEM0_REGNO
; i
--)
1243 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1246 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, i
)));
1248 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode
, i
)));
1251 emit_insn (gen_popm (GEN_INT (reg_mask
)));
1257 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1258 diagrams our call frame. */
1260 m32c_initial_elimination_offset (int from
, int to
)
1264 if (from
== AP_REGNO
)
1274 ofs
+= m32c_pushm_popm (PP_justcount
);
1275 ofs
+= get_frame_size ();
1278 /* Account for push rounding. */
1280 ofs
= (ofs
+ 1) & ~1;
1282 fprintf (stderr
, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from
,
1288 /* Passing Function Arguments on the Stack */
1290 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1291 M32C has word stacks. */
1293 m32c_push_rounding (poly_int64 n
)
1295 if (TARGET_R8C
|| TARGET_M16C
)
1297 return (n
+ 1) & ~1;
1300 /* Passing Arguments in Registers */
1302 /* Implements TARGET_FUNCTION_ARG. Arguments are passed partly in
1303 registers, partly on stack. If our function returns a struct, a
1304 pointer to a buffer for it is at the top of the stack (last thing
1305 pushed). The first few real arguments may be in registers as
1308 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1309 arg2 in r2 if it's HI (else pushed on stack)
1311 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1314 Structs are not passed in registers, even if they fit. Only
1315 integer and pointer types are passed in registers.
1317 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1319 #undef TARGET_FUNCTION_ARG
1320 #define TARGET_FUNCTION_ARG m32c_function_arg
1322 m32c_function_arg (cumulative_args_t ca_v
, const function_arg_info
&arg
)
1324 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
1326 /* Can return a reg, parallel, or 0 for stack */
1329 fprintf (stderr
, "func_arg %d (%s, %d)\n",
1330 ca
->parm_num
, mode_name
[arg
.mode
], arg
.named
);
1331 debug_tree (arg
.type
);
1334 if (arg
.end_marker_p ())
1337 if (ca
->force_mem
|| !arg
.named
)
1340 fprintf (stderr
, "func arg: force %d named %d, mem\n", ca
->force_mem
,
1346 if (arg
.type
&& INTEGRAL_TYPE_P (arg
.type
) && POINTER_TYPE_P (arg
.type
))
1349 if (arg
.aggregate_type_p ())
1352 switch (ca
->parm_num
)
1355 if (GET_MODE_SIZE (arg
.mode
) == 1 || GET_MODE_SIZE (arg
.mode
) == 2)
1356 rv
= gen_rtx_REG (arg
.mode
, TARGET_A16
? R1_REGNO
: R0_REGNO
);
1360 if (TARGET_A16
&& GET_MODE_SIZE (arg
.mode
) == 2)
1361 rv
= gen_rtx_REG (arg
.mode
, R2_REGNO
);
1371 #undef TARGET_PASS_BY_REFERENCE
1372 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1374 m32c_pass_by_reference (cumulative_args_t
, const function_arg_info
&)
1379 /* Implements INIT_CUMULATIVE_ARGS. */
1381 m32c_init_cumulative_args (CUMULATIVE_ARGS
* ca
,
1383 rtx libname ATTRIBUTE_UNUSED
,
1385 int n_named_args ATTRIBUTE_UNUSED
)
1387 if (fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fndecl
))
1394 /* Implements TARGET_FUNCTION_ARG_ADVANCE. force_mem is set for
1395 functions returning structures, so we always reset that. Otherwise,
1396 we only need to know the sequence number of the argument to know what
1398 #undef TARGET_FUNCTION_ARG_ADVANCE
1399 #define TARGET_FUNCTION_ARG_ADVANCE m32c_function_arg_advance
1401 m32c_function_arg_advance (cumulative_args_t ca_v
,
1402 const function_arg_info
&)
1404 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
1412 /* Implements TARGET_FUNCTION_ARG_BOUNDARY. */
1413 #undef TARGET_FUNCTION_ARG_BOUNDARY
1414 #define TARGET_FUNCTION_ARG_BOUNDARY m32c_function_arg_boundary
1416 m32c_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
1417 const_tree type ATTRIBUTE_UNUSED
)
1419 return (TARGET_A16
? 8 : 16);
1422 /* Implements FUNCTION_ARG_REGNO_P. */
1424 m32c_function_arg_regno_p (int r
)
1427 return (r
== R0_REGNO
);
1428 return (r
== R1_REGNO
|| r
== R2_REGNO
);
1431 /* HImode and PSImode are the two "native" modes as far as GCC is
1432 concerned, but the chips also support a 32-bit mode which is used
1433 for some opcodes in R8C/M16C and for reset vectors and such. */
1434 #undef TARGET_VALID_POINTER_MODE
1435 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1437 m32c_valid_pointer_mode (scalar_int_mode mode
)
1447 /* How Scalar Function Values Are Returned */
1449 /* Implements TARGET_LIBCALL_VALUE. Most values are returned in $r0, or some
1450 combination of registers starting there (r2r0 for longs, r3r1r2r0
1451 for long long, r3r2r1r0 for doubles), except that that ABI
1452 currently doesn't work because it ends up using all available
1453 general registers and gcc often can't compile it. So, instead, we
1454 return anything bigger than 16 bits in "mem0" (effectively, a
1455 memory location). */
1457 #undef TARGET_LIBCALL_VALUE
1458 #define TARGET_LIBCALL_VALUE m32c_libcall_value
1461 m32c_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
1463 /* return reg or parallel */
1465 /* FIXME: GCC has difficulty returning large values in registers,
1466 because that ties up most of the general registers and gives the
1467 register allocator little to work with. Until we can resolve
1468 this, large values are returned in memory. */
1473 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (4));
1474 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1475 gen_rtx_REG (HImode
,
1478 XVECEXP (rv
, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode
,
1479 gen_rtx_REG (HImode
,
1482 XVECEXP (rv
, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode
,
1483 gen_rtx_REG (HImode
,
1486 XVECEXP (rv
, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode
,
1487 gen_rtx_REG (HImode
,
1493 if (TARGET_A24
&& GET_MODE_SIZE (mode
) > 2)
1497 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (1));
1498 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1506 if (GET_MODE_SIZE (mode
) > 2)
1507 return gen_rtx_REG (mode
, MEM0_REGNO
);
1508 return gen_rtx_REG (mode
, R0_REGNO
);
1511 /* Implements TARGET_FUNCTION_VALUE. Functions and libcalls have the same
1514 #undef TARGET_FUNCTION_VALUE
1515 #define TARGET_FUNCTION_VALUE m32c_function_value
1518 m32c_function_value (const_tree valtype
,
1519 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1520 bool outgoing ATTRIBUTE_UNUSED
)
1522 /* return reg or parallel */
1523 const machine_mode mode
= TYPE_MODE (valtype
);
1524 return m32c_libcall_value (mode
, NULL_RTX
);
1527 /* Implements TARGET_FUNCTION_VALUE_REGNO_P. */
1529 #undef TARGET_FUNCTION_VALUE_REGNO_P
1530 #define TARGET_FUNCTION_VALUE_REGNO_P m32c_function_value_regno_p
1533 m32c_function_value_regno_p (const unsigned int regno
)
1535 return (regno
== R0_REGNO
|| regno
== MEM0_REGNO
);
1538 /* How Large Values Are Returned */
1540 /* We return structures by pushing the address on the stack, even if
1541 we use registers for the first few "real" arguments. */
1542 #undef TARGET_STRUCT_VALUE_RTX
1543 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1545 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
,
1546 int incoming ATTRIBUTE_UNUSED
)
1551 /* Function Entry and Exit */
1553 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1555 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
1557 if (cfun
->machine
->is_interrupt
)
1562 /* Implementing the Varargs Macros */
1564 #undef TARGET_STRICT_ARGUMENT_NAMING
1565 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1567 m32c_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
1572 /* Trampolines for Nested Functions */
1576 1 0000 75C43412 mov.w #0x1234,a0
1577 2 0004 FC000000 jmp.a label
1580 1 0000 BC563412 mov.l:s #0x123456,a0
1581 2 0004 CC000000 jmp.a label
1584 /* Implements TRAMPOLINE_SIZE. */
1586 m32c_trampoline_size (void)
1588 /* Allocate extra space so we can avoid the messy shifts when we
1589 initialize the trampoline; we just write past the end of the
1591 return TARGET_A16
? 8 : 10;
1594 /* Implements TRAMPOLINE_ALIGNMENT. */
1596 m32c_trampoline_alignment (void)
1601 /* Implements TARGET_TRAMPOLINE_INIT. */
1603 #undef TARGET_TRAMPOLINE_INIT
1604 #define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
1606 m32c_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chainval
)
1608 rtx function
= XEXP (DECL_RTL (fndecl
), 0);
1610 #define A0(m,i) adjust_address (m_tramp, m, i)
1613 /* Note: we subtract a "word" because the moves want signed
1614 constants, not unsigned constants. */
1615 emit_move_insn (A0 (HImode
, 0), GEN_INT (0xc475 - 0x10000));
1616 emit_move_insn (A0 (HImode
, 2), chainval
);
1617 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xfc - 0x100));
1618 /* We use 16-bit addresses here, but store the zero to turn it
1619 into a 24-bit offset. */
1620 emit_move_insn (A0 (HImode
, 5), function
);
1621 emit_move_insn (A0 (QImode
, 7), GEN_INT (0x00));
1625 /* Note that the PSI moves actually write 4 bytes. Make sure we
1626 write stuff out in the right order, and leave room for the
1627 extra byte at the end. */
1628 emit_move_insn (A0 (QImode
, 0), GEN_INT (0xbc - 0x100));
1629 emit_move_insn (A0 (PSImode
, 1), chainval
);
1630 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xcc - 0x100));
1631 emit_move_insn (A0 (PSImode
, 5), function
);
1637 #define TARGET_LRA_P hook_bool_void_false
1639 /* Addressing Modes */
1641 /* The r8c/m32c family supports a wide range of non-orthogonal
1642 addressing modes, including the ability to double-indirect on *some*
1643 of them. Not all insns support all modes, either, but we rely on
1644 predicates and constraints to deal with that. */
1645 #undef TARGET_LEGITIMATE_ADDRESS_P
1646 #define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
1648 m32c_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1654 if (TARGET_A16
&& GET_MODE (x
) != HImode
&& GET_MODE (x
) != SImode
)
1656 if (TARGET_A24
&& GET_MODE (x
) != PSImode
)
1659 /* Wide references to memory will be split after reload, so we must
1660 ensure that all parts of such splits remain legitimate
1662 mode_adjust
= GET_MODE_SIZE (mode
) - 1;
1664 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1665 if (GET_CODE (x
) == PRE_DEC
1666 || GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_MODIFY
)
1668 return (GET_CODE (XEXP (x
, 0)) == REG
1669 && REGNO (XEXP (x
, 0)) == SP_REGNO
);
1673 /* This is the double indirection detection, but it currently
1674 doesn't work as cleanly as this code implies, so until we've had
1675 a chance to debug it, leave it disabled. */
1676 if (TARGET_A24
&& GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) != PLUS
)
1679 fprintf (stderr
, "double indirect\n");
1688 /* Most indexable registers can be used without displacements,
1689 although some of them will be emitted with an explicit zero
1690 to please the assembler. */
1691 switch (REGNO (patternr
[0]))
1697 if (TARGET_A16
&& GET_MODE (x
) == SImode
)
1704 if (IS_PSEUDO (patternr
[0], strict
))
1710 if (TARGET_A16
&& GET_MODE (x
) == SImode
)
1715 /* This is more interesting, because different base registers
1716 allow for different displacements - both range and signedness
1717 - and it differs from chip series to chip series too. */
1718 int rn
= REGNO (patternr
[1]);
1719 HOST_WIDE_INT offs
= INTVAL (patternr
[2]);
1725 /* The syntax only allows positive offsets, but when the
1726 offsets span the entire memory range, we can simulate
1727 negative offsets by wrapping. */
1729 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1731 return (offs
>= 0 && offs
<= 65535 - mode_adjust
);
1733 return (offs
>= -16777216 && offs
<= 16777215);
1737 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1738 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1741 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1744 if (IS_PSEUDO (patternr
[1], strict
))
1749 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1751 rtx reg
= patternr
[1];
1753 /* We don't know where the symbol is, so only allow base
1754 registers which support displacements spanning the whole
1756 switch (REGNO (reg
))
1760 /* $sb needs a secondary reload, but since it's involved in
1761 memory address reloads too, we don't deal with it very
1763 /* case SB_REGNO: */
1766 if (GET_CODE (reg
) == SUBREG
)
1768 if (IS_PSEUDO (reg
, strict
))
1776 /* Implements REG_OK_FOR_BASE_P. */
1778 m32c_reg_ok_for_base_p (rtx x
, int strict
)
1780 if (GET_CODE (x
) != REG
)
1791 if (IS_PSEUDO (x
, strict
))
1797 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1798 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1800 EB 4B FF mova -128[$fb],$a0
1801 D8 0C FF FF mov.w:Q #0,-1[$a0]
1803 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1806 77 54 00 01 sub #256,$a0
1807 D8 08 01 mov.w:Q #0,1[$a0]
1809 If we don't offset (i.e. offset by zero), we end up with:
1811 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1813 We have to subtract *something* so that we have a PLUS rtx to mark
1814 that we've done this reload. The -128 offset will never result in
1815 an 8-bit aN offset, and the payoff for the second case is five
1816 loads *if* those loads are within 256 bytes of the other end of the
1817 frame, so the third case seems best. Note that we subtract the
1818 zero, but detect that in the addhi3 pattern. */
1820 #define BIG_FB_ADJ 0
1822 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1823 worry about is frame base offsets, as $fb has a limited
1824 displacement range. We deal with this by attempting to reload $fb
1825 itself into an address register; that seems to result in the best
1827 #undef TARGET_LEGITIMIZE_ADDRESS
1828 #define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
1830 m32c_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1834 fprintf (stderr
, "m32c_legitimize_address for mode %s\n", mode_name
[mode
]);
1836 fprintf (stderr
, "\n");
1839 if (GET_CODE (x
) == PLUS
1840 && GET_CODE (XEXP (x
, 0)) == REG
1841 && REGNO (XEXP (x
, 0)) == FB_REGNO
1842 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1843 && (INTVAL (XEXP (x
, 1)) < -128
1844 || INTVAL (XEXP (x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1846 /* reload FB to A_REGS */
1847 rtx temp
= gen_reg_rtx (Pmode
);
1849 emit_insn (gen_rtx_SET (temp
, XEXP (x
, 0)));
1856 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1858 m32c_legitimize_reload_address (rtx
* x
,
1861 int type
, int ind_levels ATTRIBUTE_UNUSED
)
1864 fprintf (stderr
, "\nm32c_legitimize_reload_address for mode %s\n",
1869 /* At one point, this function tried to get $fb copied to an address
1870 register, which in theory would maximize sharing, but gcc was
1871 *also* still trying to reload the whole address, and we'd run out
1872 of address registers. So we let gcc do the naive (but safe)
1873 reload instead, when the above function doesn't handle it for
1876 The code below is a second attempt at the above. */
1878 if (GET_CODE (*x
) == PLUS
1879 && GET_CODE (XEXP (*x
, 0)) == REG
1880 && REGNO (XEXP (*x
, 0)) == FB_REGNO
1881 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1882 && (INTVAL (XEXP (*x
, 1)) < -128
1883 || INTVAL (XEXP (*x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1886 int offset
= INTVAL (XEXP (*x
, 1));
1887 int adjustment
= -BIG_FB_ADJ
;
1889 sum
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0),
1890 GEN_INT (adjustment
));
1891 *x
= gen_rtx_PLUS (Pmode
, sum
, GEN_INT (offset
- adjustment
));
1892 if (type
== RELOAD_OTHER
)
1893 type
= RELOAD_FOR_OTHER_ADDRESS
;
1894 push_reload (sum
, NULL_RTX
, &XEXP (*x
, 0), NULL
,
1895 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
1896 (enum reload_type
) type
);
1900 if (GET_CODE (*x
) == PLUS
1901 && GET_CODE (XEXP (*x
, 0)) == PLUS
1902 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1903 && REGNO (XEXP (XEXP (*x
, 0), 0)) == FB_REGNO
1904 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1905 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1908 if (type
== RELOAD_OTHER
)
1909 type
= RELOAD_FOR_OTHER_ADDRESS
;
1910 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1911 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
1912 (enum reload_type
) type
);
1916 if (TARGET_A24
&& GET_MODE (*x
) == PSImode
)
1918 push_reload (*x
, NULL_RTX
, x
, NULL
,
1919 A_REGS
, PSImode
, VOIDmode
, 0, 0, opnum
,
1920 (enum reload_type
) type
);
1927 /* Return the appropriate mode for a named address pointer. */
1928 #undef TARGET_ADDR_SPACE_POINTER_MODE
1929 #define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode
1930 static scalar_int_mode
1931 m32c_addr_space_pointer_mode (addr_space_t addrspace
)
1935 case ADDR_SPACE_GENERIC
:
1936 return TARGET_A24
? PSImode
: HImode
;
1937 case ADDR_SPACE_FAR
:
1944 /* Return the appropriate mode for a named address address. */
1945 #undef TARGET_ADDR_SPACE_ADDRESS_MODE
1946 #define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode
1947 static scalar_int_mode
1948 m32c_addr_space_address_mode (addr_space_t addrspace
)
1952 case ADDR_SPACE_GENERIC
:
1953 return TARGET_A24
? PSImode
: HImode
;
1954 case ADDR_SPACE_FAR
:
1961 /* Like m32c_legitimate_address_p, except with named addresses. */
1962 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
1963 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
1964 m32c_addr_space_legitimate_address_p
1966 m32c_addr_space_legitimate_address_p (machine_mode mode
, rtx x
,
1967 bool strict
, addr_space_t as
)
1969 if (as
== ADDR_SPACE_FAR
)
1976 if (GET_MODE (x
) != SImode
)
1978 switch (REGNO (patternr
[0]))
1984 if (IS_PSEUDO (patternr
[0], strict
))
1989 if (RTX_IS ("+^Sri"))
1991 int rn
= REGNO (patternr
[3]);
1992 HOST_WIDE_INT offs
= INTVAL (patternr
[4]);
1993 if (GET_MODE (patternr
[3]) != HImode
)
1998 return (offs
>= 0 && offs
<= 0xfffff);
2001 if (IS_PSEUDO (patternr
[3], strict
))
2006 if (RTX_IS ("+^Srs"))
2008 int rn
= REGNO (patternr
[3]);
2009 if (GET_MODE (patternr
[3]) != HImode
)
2017 if (IS_PSEUDO (patternr
[3], strict
))
2022 if (RTX_IS ("+^S+ris"))
2024 int rn
= REGNO (patternr
[4]);
2025 if (GET_MODE (patternr
[4]) != HImode
)
2033 if (IS_PSEUDO (patternr
[4], strict
))
2045 else if (as
!= ADDR_SPACE_GENERIC
)
2048 return m32c_legitimate_address_p (mode
, x
, strict
);
2051 /* Like m32c_legitimate_address, except with named address support. */
2052 #undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
2053 #define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address
2055 m32c_addr_space_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
,
2058 if (as
!= ADDR_SPACE_GENERIC
)
2061 fprintf (stderr
, "\033[36mm32c_addr_space_legitimize_address for mode %s\033[0m\n", mode_name
[mode
]);
2063 fprintf (stderr
, "\n");
2066 if (GET_CODE (x
) != REG
)
2068 x
= force_reg (SImode
, x
);
2073 return m32c_legitimize_address (x
, oldx
, mode
);
2076 /* Determine if one named address space is a subset of another. */
2077 #undef TARGET_ADDR_SPACE_SUBSET_P
2078 #define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p
2080 m32c_addr_space_subset_p (addr_space_t subset
, addr_space_t superset
)
2082 gcc_assert (subset
== ADDR_SPACE_GENERIC
|| subset
== ADDR_SPACE_FAR
);
2083 gcc_assert (superset
== ADDR_SPACE_GENERIC
|| superset
== ADDR_SPACE_FAR
);
2085 if (subset
== superset
)
2089 return (subset
== ADDR_SPACE_GENERIC
&& superset
== ADDR_SPACE_FAR
);
2092 #undef TARGET_ADDR_SPACE_CONVERT
2093 #define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert
2094 /* Convert from one address space to another. */
2096 m32c_addr_space_convert (rtx op
, tree from_type
, tree to_type
)
2098 addr_space_t from_as
= TYPE_ADDR_SPACE (TREE_TYPE (from_type
));
2099 addr_space_t to_as
= TYPE_ADDR_SPACE (TREE_TYPE (to_type
));
2102 gcc_assert (from_as
== ADDR_SPACE_GENERIC
|| from_as
== ADDR_SPACE_FAR
);
2103 gcc_assert (to_as
== ADDR_SPACE_GENERIC
|| to_as
== ADDR_SPACE_FAR
);
2105 if (to_as
== ADDR_SPACE_GENERIC
&& from_as
== ADDR_SPACE_FAR
)
2107 /* This is unpredictable, as we're truncating off usable address
2110 result
= gen_reg_rtx (HImode
);
2111 emit_move_insn (result
, simplify_subreg (HImode
, op
, SImode
, 0));
2114 else if (to_as
== ADDR_SPACE_FAR
&& from_as
== ADDR_SPACE_GENERIC
)
2116 /* This always works. */
2117 result
= gen_reg_rtx (SImode
);
2118 emit_insn (gen_zero_extendhisi2 (result
, op
));
2125 /* Condition Code Status */
2127 #undef TARGET_FIXED_CONDITION_CODE_REGS
2128 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2130 m32c_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
2133 *p2
= INVALID_REGNUM
;
2137 /* Describing Relative Costs of Operations */
2139 /* Implements TARGET_REGISTER_MOVE_COST. We make impossible moves
2140 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2141 no opcodes to do that). We also discourage use of mem* registers
2142 since they're really memory. */
2144 #undef TARGET_REGISTER_MOVE_COST
2145 #define TARGET_REGISTER_MOVE_COST m32c_register_move_cost
2148 m32c_register_move_cost (machine_mode mode
, reg_class_t from
,
2151 int cost
= COSTS_N_INSNS (3);
2154 /* FIXME: pick real values, but not 2 for now. */
2155 cc
= reg_class_contents
[from
];
2156 IOR_HARD_REG_SET (cc
, reg_class_contents
[(int) to
]);
2159 && hard_reg_set_intersect_p (cc
, reg_class_contents
[R23_REGS
]))
2161 if (hard_reg_set_subset_p (cc
, reg_class_contents
[R23_REGS
]))
2162 cost
= COSTS_N_INSNS (1000);
2164 cost
= COSTS_N_INSNS (80);
2167 if (!class_can_hold_mode (from
, mode
) || !class_can_hold_mode (to
, mode
))
2168 cost
= COSTS_N_INSNS (1000);
2170 if (reg_classes_intersect_p (from
, CR_REGS
))
2171 cost
+= COSTS_N_INSNS (5);
2173 if (reg_classes_intersect_p (to
, CR_REGS
))
2174 cost
+= COSTS_N_INSNS (5);
2176 if (from
== MEM_REGS
|| to
== MEM_REGS
)
2177 cost
+= COSTS_N_INSNS (50);
2178 else if (reg_classes_intersect_p (from
, MEM_REGS
)
2179 || reg_classes_intersect_p (to
, MEM_REGS
))
2180 cost
+= COSTS_N_INSNS (10);
2183 fprintf (stderr
, "register_move_cost %s from %s to %s = %d\n",
2184 mode_name
[mode
], class_names
[(int) from
], class_names
[(int) to
],
2190 /* Implements TARGET_MEMORY_MOVE_COST. */
2192 #undef TARGET_MEMORY_MOVE_COST
2193 #define TARGET_MEMORY_MOVE_COST m32c_memory_move_cost
2196 m32c_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2197 reg_class_t rclass ATTRIBUTE_UNUSED
,
2198 bool in ATTRIBUTE_UNUSED
)
2200 /* FIXME: pick real values. */
2201 return COSTS_N_INSNS (10);
2204 /* Here we try to describe when we use multiple opcodes for one RTX so
2205 that gcc knows when to use them. */
2206 #undef TARGET_RTX_COSTS
2207 #define TARGET_RTX_COSTS m32c_rtx_costs
2209 m32c_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2210 int opno ATTRIBUTE_UNUSED
,
2211 int *total
, bool speed ATTRIBUTE_UNUSED
)
2213 int code
= GET_CODE (x
);
2217 if (REGNO (x
) >= MEM0_REGNO
&& REGNO (x
) <= MEM7_REGNO
)
2218 *total
+= COSTS_N_INSNS (500);
2220 *total
+= COSTS_N_INSNS (1);
2226 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2228 /* mov.b r1l, r1h */
2229 *total
+= COSTS_N_INSNS (1);
2232 if (INTVAL (XEXP (x
, 1)) > 8
2233 || INTVAL (XEXP (x
, 1)) < -8)
2236 /* mov.b r1l, r1h */
2237 *total
+= COSTS_N_INSNS (2);
2252 if (outer_code
== SET
)
2254 *total
+= COSTS_N_INSNS (2);
2261 rtx dest
= XEXP (x
, 0);
2262 rtx addr
= XEXP (dest
, 0);
2263 switch (GET_CODE (addr
))
2266 *total
+= COSTS_N_INSNS (1);
2269 *total
+= COSTS_N_INSNS (3);
2272 *total
+= COSTS_N_INSNS (2);
2280 /* Reasonable default. */
2281 if (TARGET_A16
&& mode
== SImode
)
2282 *total
+= COSTS_N_INSNS (2);
2288 #undef TARGET_ADDRESS_COST
2289 #define TARGET_ADDRESS_COST m32c_address_cost
2291 m32c_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
2292 addr_space_t as ATTRIBUTE_UNUSED
,
2293 bool speed ATTRIBUTE_UNUSED
)
2296 /* fprintf(stderr, "\naddress_cost\n");
2298 switch (GET_CODE (addr
))
2303 return COSTS_N_INSNS(1);
2304 if (i
> 0 && i
<= 255)
2305 return COSTS_N_INSNS(2);
2306 if (i
> 0 && i
<= 65535)
2307 return COSTS_N_INSNS(3);
2308 return COSTS_N_INSNS(4);
2310 return COSTS_N_INSNS(4);
2312 return COSTS_N_INSNS(1);
2314 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2316 i
= INTVAL (XEXP (addr
, 1));
2318 return COSTS_N_INSNS(1);
2319 if (i
> 0 && i
<= 255)
2320 return COSTS_N_INSNS(2);
2321 if (i
> 0 && i
<= 65535)
2322 return COSTS_N_INSNS(3);
2324 return COSTS_N_INSNS(4);
2330 /* Defining the Output Assembler Language */
2332 /* Output of Data */
2334 /* We may have 24 bit sizes, which is the native address size.
2335 Currently unused, but provided for completeness. */
2336 #undef TARGET_ASM_INTEGER
2337 #define TARGET_ASM_INTEGER m32c_asm_integer
2339 m32c_asm_integer (rtx x
, unsigned int size
, int aligned_p
)
2344 fprintf (asm_out_file
, "\t.3byte\t");
2345 output_addr_const (asm_out_file
, x
);
2346 fputc ('\n', asm_out_file
);
2349 if (GET_CODE (x
) == SYMBOL_REF
)
2351 fprintf (asm_out_file
, "\t.long\t");
2352 output_addr_const (asm_out_file
, x
);
2353 fputc ('\n', asm_out_file
);
2358 return default_assemble_integer (x
, size
, aligned_p
);
2361 /* Output of Assembler Instructions */
2363 /* We use a lookup table because the addressing modes are non-orthogonal. */
2368 char const *pattern
;
2371 const conversions
[] = {
2374 { 0, "mr", "z[1]" },
2375 { 0, "m+ri", "3[2]" },
2376 { 0, "m+rs", "3[2]" },
2377 { 0, "m+^Zrs", "5[4]" },
2378 { 0, "m+^Zri", "5[4]" },
2379 { 0, "m+^Z+ris", "7+6[5]" },
2380 { 0, "m+^Srs", "5[4]" },
2381 { 0, "m+^Sri", "5[4]" },
2382 { 0, "m+^S+ris", "7+6[5]" },
2383 { 0, "m+r+si", "4+5[2]" },
2386 { 0, "m+si", "2+3" },
2388 { 0, "mmr", "[z[2]]" },
2389 { 0, "mm+ri", "[4[3]]" },
2390 { 0, "mm+rs", "[4[3]]" },
2391 { 0, "mm+r+si", "[5+6[3]]" },
2392 { 0, "mms", "[[2]]" },
2393 { 0, "mmi", "[[2]]" },
2394 { 0, "mm+si", "[4[3]]" },
2398 { 0, "+si", "#1+2" },
2404 { 'd', "+si", "1+2" },
2407 { 'D', "+si", "1+2" },
2418 /* This is in order according to the bitfield that pushm/popm use. */
2419 static char const *pushm_regs
[] = {
2420 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2423 /* Implements TARGET_PRINT_OPERAND. */
2425 #undef TARGET_PRINT_OPERAND
2426 #define TARGET_PRINT_OPERAND m32c_print_operand
2429 m32c_print_operand (FILE * file
, rtx x
, int code
)
2434 int unsigned_const
= 0;
2437 /* Multiplies; constants are converted to sign-extended format but
2438 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2450 /* This one is only for debugging; you can put it in a pattern to
2451 force this error. */
2454 fprintf (stderr
, "dj: unreviewed pattern:");
2455 if (current_output_insn
)
2456 debug_rtx (current_output_insn
);
2459 /* PSImode operations are either .w or .l depending on the target. */
2463 fprintf (file
, "w");
2465 fprintf (file
, "l");
2468 /* Inverted conditionals. */
2471 switch (GET_CODE (x
))
2477 fputs ("gtu", file
);
2483 fputs ("geu", file
);
2489 fputs ("leu", file
);
2495 fputs ("ltu", file
);
2508 /* Regular conditionals. */
2511 switch (GET_CODE (x
))
2517 fputs ("leu", file
);
2523 fputs ("ltu", file
);
2529 fputs ("gtu", file
);
2535 fputs ("geu", file
);
2548 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2550 if (code
== 'h' && GET_MODE (x
) == SImode
)
2552 x
= m32c_subreg (HImode
, x
, SImode
, 0);
2555 if (code
== 'H' && GET_MODE (x
) == SImode
)
2557 x
= m32c_subreg (HImode
, x
, SImode
, 2);
2560 if (code
== 'h' && GET_MODE (x
) == HImode
)
2562 x
= m32c_subreg (QImode
, x
, HImode
, 0);
2565 if (code
== 'H' && GET_MODE (x
) == HImode
)
2567 /* We can't actually represent this as an rtx. Do it here. */
2568 if (GET_CODE (x
) == REG
)
2573 fputs ("r0h", file
);
2576 fputs ("r1h", file
);
2582 /* This should be a MEM. */
2583 x
= m32c_subreg (QImode
, x
, HImode
, 1);
2586 /* This is for BMcond, which always wants word register names. */
2587 if (code
== 'h' && GET_MODE (x
) == QImode
)
2589 if (GET_CODE (x
) == REG
)
2590 x
= gen_rtx_REG (HImode
, REGNO (x
));
2593 /* 'x' and 'X' need to be ignored for non-immediates. */
2594 if ((code
== 'x' || code
== 'X') && GET_CODE (x
) != CONST_INT
)
2599 for (i
= 0; conversions
[i
].pattern
; i
++)
2600 if (conversions
[i
].code
== code
2601 && streq (conversions
[i
].pattern
, pattern
))
2603 for (j
= 0; conversions
[i
].format
[j
]; j
++)
2604 /* backslash quotes the next character in the output pattern. */
2605 if (conversions
[i
].format
[j
] == '\\')
2607 fputc (conversions
[i
].format
[j
+ 1], file
);
2610 /* Digits in the output pattern indicate that the
2611 corresponding RTX is to be output at that point. */
2612 else if (ISDIGIT (conversions
[i
].format
[j
]))
2614 rtx r
= patternr
[conversions
[i
].format
[j
] - '0'];
2615 switch (GET_CODE (r
))
2618 fprintf (file
, "%s",
2619 reg_name_with_mode (REGNO (r
), GET_MODE (r
)));
2628 int i
= (int) exact_log2 (v
);
2630 i
= (int) exact_log2 ((v
^ 0xffff) & 0xffff);
2632 i
= (int) exact_log2 ((v
^ 0xff) & 0xff);
2634 fprintf (file
, "%d", i
);
2638 /* Unsigned byte. */
2639 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2643 /* Unsigned word. */
2644 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2645 INTVAL (r
) & 0xffff);
2648 /* pushm and popm encode a register set into a single byte. */
2650 for (b
= 7; b
>= 0; b
--)
2651 if (INTVAL (r
) & (1 << b
))
2653 fprintf (file
, "%s%s", comma
, pushm_regs
[b
]);
2658 /* "Minus". Output -X */
2659 ival
= (-INTVAL (r
) & 0xffff);
2661 ival
= ival
- 0x10000;
2662 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2666 if (conversions
[i
].format
[j
+ 1] == '[' && ival
< 0)
2668 /* We can simulate negative displacements by
2669 taking advantage of address space
2670 wrapping when the offset can span the
2671 entire address range. */
2673 patternr
[conversions
[i
].format
[j
+ 2] - '0'];
2674 if (GET_CODE (base
) == REG
)
2675 switch (REGNO (base
))
2680 ival
= 0x1000000 + ival
;
2682 ival
= 0x10000 + ival
;
2686 ival
= 0x10000 + ival
;
2690 else if (code
== 'd' && ival
< 0 && j
== 0)
2691 /* The "mova" opcode is used to do addition by
2692 computing displacements, but again, we need
2693 displacements to be unsigned *if* they're
2694 the only component of the displacement
2695 (i.e. no "symbol-4" type displacement). */
2696 ival
= (TARGET_A24
? 0x1000000 : 0x10000) + ival
;
2698 if (conversions
[i
].format
[j
] == '0')
2700 /* More conversions to unsigned. */
2701 if (unsigned_const
== 2)
2703 if (unsigned_const
== 1)
2706 if (streq (conversions
[i
].pattern
, "mi")
2707 || streq (conversions
[i
].pattern
, "mmi"))
2709 /* Integers used as addresses are unsigned. */
2710 ival
&= (TARGET_A24
? 0xffffff : 0xffff);
2712 if (force_sign
&& ival
>= 0)
2714 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2719 /* We don't have const_double constants. If it
2720 happens, make it obvious. */
2721 fprintf (file
, "[const_double 0x%lx]",
2722 (unsigned long) CONST_DOUBLE_HIGH (r
));
2725 assemble_name (file
, XSTR (r
, 0));
2728 output_asm_label (r
);
2731 fprintf (stderr
, "don't know how to print this operand:");
2738 if (conversions
[i
].format
[j
] == 'z')
2740 /* Some addressing modes *must* have a displacement,
2741 so insert a zero here if needed. */
2743 for (k
= j
+ 1; conversions
[i
].format
[k
]; k
++)
2744 if (ISDIGIT (conversions
[i
].format
[k
]))
2746 rtx reg
= patternr
[conversions
[i
].format
[k
] - '0'];
2747 if (GET_CODE (reg
) == REG
2748 && (REGNO (reg
) == SB_REGNO
2749 || REGNO (reg
) == FB_REGNO
2750 || REGNO (reg
) == SP_REGNO
))
2755 /* Signed displacements off symbols need to have signs
2757 if (conversions
[i
].format
[j
] == '+'
2758 && (!code
|| code
== 'D' || code
== 'd')
2759 && ISDIGIT (conversions
[i
].format
[j
+ 1])
2760 && (GET_CODE (patternr
[conversions
[i
].format
[j
+ 1] - '0'])
2766 fputc (conversions
[i
].format
[j
], file
);
2770 if (!conversions
[i
].pattern
)
2772 fprintf (stderr
, "unconvertible operand %c `%s'", code
? code
: '-',
2775 fprintf (file
, "[%c.%s]", code
? code
: '-', pattern
);
2781 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P.
2783 See m32c_print_operand above for descriptions of what these do. */
2785 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
2786 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32c_print_operand_punct_valid_p
2789 m32c_print_operand_punct_valid_p (unsigned char c
)
2791 if (c
== '&' || c
== '!')
2797 /* Implements TARGET_PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2799 #undef TARGET_PRINT_OPERAND_ADDRESS
2800 #define TARGET_PRINT_OPERAND_ADDRESS m32c_print_operand_address
2803 m32c_print_operand_address (FILE * stream
, machine_mode
/*mode*/, rtx address
)
2805 if (GET_CODE (address
) == MEM
)
2806 address
= XEXP (address
, 0);
2808 /* cf: gcc.dg/asm-4.c. */
2809 gcc_assert (GET_CODE (address
) == REG
);
2811 m32c_print_operand (stream
, address
, 0);
2814 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2815 differently than general registers. */
2817 m32c_output_reg_push (FILE * s
, int regno
)
2819 if (regno
== FLG_REGNO
)
2820 fprintf (s
, "\tpushc\tflg\n");
2822 fprintf (s
, "\tpush.%c\t%s\n",
2823 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2826 /* Likewise for ASM_OUTPUT_REG_POP. */
2828 m32c_output_reg_pop (FILE * s
, int regno
)
2830 if (regno
== FLG_REGNO
)
2831 fprintf (s
, "\tpopc\tflg\n");
2833 fprintf (s
, "\tpop.%c\t%s\n",
2834 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2837 /* Defining target-specific uses of `__attribute__' */
2839 /* Used to simplify the logic below. Find the attributes wherever
2841 #define M32C_ATTRIBUTES(decl) \
2842 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2843 : DECL_ATTRIBUTES (decl) \
2844 ? (DECL_ATTRIBUTES (decl)) \
2845 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2847 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2849 interrupt_p (tree node ATTRIBUTE_UNUSED
)
2851 tree list
= M32C_ATTRIBUTES (node
);
2854 if (is_attribute_p ("interrupt", TREE_PURPOSE (list
)))
2856 list
= TREE_CHAIN (list
);
2858 return fast_interrupt_p (node
);
2861 /* Returns TRUE if the given tree has the "bank_switch" attribute. */
2863 bank_switch_p (tree node ATTRIBUTE_UNUSED
)
2865 tree list
= M32C_ATTRIBUTES (node
);
2868 if (is_attribute_p ("bank_switch", TREE_PURPOSE (list
)))
2870 list
= TREE_CHAIN (list
);
2875 /* Returns TRUE if the given tree has the "fast_interrupt" attribute. */
2877 fast_interrupt_p (tree node ATTRIBUTE_UNUSED
)
2879 tree list
= M32C_ATTRIBUTES (node
);
2882 if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list
)))
2884 list
= TREE_CHAIN (list
);
2890 interrupt_handler (tree
* node ATTRIBUTE_UNUSED
,
2891 tree name ATTRIBUTE_UNUSED
,
2892 tree args ATTRIBUTE_UNUSED
,
2893 int flags ATTRIBUTE_UNUSED
,
2894 bool * no_add_attrs ATTRIBUTE_UNUSED
)
2899 /* Returns TRUE if given tree has the "function_vector" attribute. */
2901 m32c_special_page_vector_p (tree func
)
2905 if (TREE_CODE (func
) != FUNCTION_DECL
)
2908 list
= M32C_ATTRIBUTES (func
);
2911 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
2913 list
= TREE_CHAIN (list
);
2919 function_vector_handler (tree
* node ATTRIBUTE_UNUSED
,
2920 tree name ATTRIBUTE_UNUSED
,
2921 tree args ATTRIBUTE_UNUSED
,
2922 int flags ATTRIBUTE_UNUSED
,
2923 bool * no_add_attrs ATTRIBUTE_UNUSED
)
2927 /* The attribute is not supported for R8C target. */
2928 warning (OPT_Wattributes
,
2929 "%qE attribute is not supported for R8C target",
2931 *no_add_attrs
= true;
2933 else if (TREE_CODE (*node
) != FUNCTION_DECL
)
2935 /* The attribute must be applied to functions only. */
2936 warning (OPT_Wattributes
,
2937 "%qE attribute applies only to functions",
2939 *no_add_attrs
= true;
2941 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
2943 /* The argument must be a constant integer. */
2944 warning (OPT_Wattributes
,
2945 "%qE attribute argument not an integer constant",
2947 *no_add_attrs
= true;
2949 else if (TREE_INT_CST_LOW (TREE_VALUE (args
)) < 18
2950 || TREE_INT_CST_LOW (TREE_VALUE (args
)) > 255)
2952 /* The argument value must be between 18 to 255. */
2953 warning (OPT_Wattributes
,
2954 "%qE attribute argument should be between 18 to 255",
2956 *no_add_attrs
= true;
2961 /* If the function is assigned the attribute 'function_vector', it
2962 returns the function vector number, otherwise returns zero. */
2964 current_function_special_page_vector (rtx x
)
2968 if ((GET_CODE(x
) == SYMBOL_REF
)
2969 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
2972 tree t
= SYMBOL_REF_DECL (x
);
2974 if (TREE_CODE (t
) != FUNCTION_DECL
)
2977 list
= M32C_ATTRIBUTES (t
);
2980 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
2982 num
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list
)));
2986 list
= TREE_CHAIN (list
);
2995 #undef TARGET_ATTRIBUTE_TABLE
2996 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2997 static const struct attribute_spec m32c_attribute_table
[] = {
2998 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
2999 affects_type_identity, handler, exclude } */
3000 { "interrupt", 0, 0, false, false, false, false, interrupt_handler
, NULL
},
3001 { "bank_switch", 0, 0, false, false, false, false, interrupt_handler
, NULL
},
3002 { "fast_interrupt", 0, 0, false, false, false, false,
3003 interrupt_handler
, NULL
},
3004 { "function_vector", 1, 1, true, false, false, false,
3005 function_vector_handler
, NULL
},
3006 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
3009 #undef TARGET_COMP_TYPE_ATTRIBUTES
3010 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
3012 m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED
,
3013 const_tree type2 ATTRIBUTE_UNUSED
)
3015 /* 0=incompatible 1=compatible 2=warning */
3019 #undef TARGET_INSERT_ATTRIBUTES
3020 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
3022 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED
,
3023 tree
* attr_ptr ATTRIBUTE_UNUSED
)
3026 /* See if we need to make #pragma address variables volatile. */
3028 if (TREE_CODE (node
) == VAR_DECL
)
3030 const char *name
= IDENTIFIER_POINTER (DECL_NAME (node
));
3031 if (m32c_get_pragma_address (name
, &addr
))
3033 TREE_THIS_VOLATILE (node
) = true;
3038 /* Hash table of pragma info. */
3039 static GTY(()) hash_map
<nofree_string_hash
, unsigned> *pragma_htab
;
3042 m32c_note_pragma_address (const char *varname
, unsigned address
)
3045 pragma_htab
= hash_map
<nofree_string_hash
, unsigned>::create_ggc (31);
3047 const char *name
= ggc_strdup (varname
);
3048 unsigned int *slot
= &pragma_htab
->get_or_insert (name
);
3053 m32c_get_pragma_address (const char *varname
, unsigned *address
)
3058 unsigned int *slot
= pragma_htab
->get (varname
);
3068 m32c_output_aligned_common (FILE *stream
, tree decl ATTRIBUTE_UNUSED
,
3070 int size
, int align
, int global
)
3074 if (m32c_get_pragma_address (name
, &address
))
3076 /* We never output these as global. */
3077 assemble_name (stream
, name
);
3078 fprintf (stream
, " = 0x%04x\n", address
);
3083 fprintf (stream
, "\t.local\t");
3084 assemble_name (stream
, name
);
3085 fprintf (stream
, "\n");
3087 fprintf (stream
, "\t.comm\t");
3088 assemble_name (stream
, name
);
3089 fprintf (stream
, ",%u,%u\n", size
, align
/ BITS_PER_UNIT
);
3094 /* This is a list of legal subregs of hard regs. */
3095 static const struct {
3096 unsigned char outer_mode_size
;
3097 unsigned char inner_mode_size
;
3098 unsigned char byte_mask
;
3099 unsigned char legal_when
;
3101 } legal_subregs
[] = {
3102 {1, 2, 0x03, 1, R0_REGNO
}, /* r0h r0l */
3103 {1, 2, 0x03, 1, R1_REGNO
}, /* r1h r1l */
3104 {1, 2, 0x01, 1, A0_REGNO
},
3105 {1, 2, 0x01, 1, A1_REGNO
},
3107 {1, 4, 0x01, 1, A0_REGNO
},
3108 {1, 4, 0x01, 1, A1_REGNO
},
3110 {2, 4, 0x05, 1, R0_REGNO
}, /* r2 r0 */
3111 {2, 4, 0x05, 1, R1_REGNO
}, /* r3 r1 */
3112 {2, 4, 0x05, 16, A0_REGNO
}, /* a1 a0 */
3113 {2, 4, 0x01, 24, A0_REGNO
}, /* a1 a0 */
3114 {2, 4, 0x01, 24, A1_REGNO
}, /* a1 a0 */
3116 {4, 8, 0x55, 1, R0_REGNO
}, /* r3 r1 r2 r0 */
3119 /* Returns TRUE if OP is a subreg of a hard reg which we don't
3120 support. We also bail on MEMs with illegal addresses. */
3122 m32c_illegal_subreg_p (rtx op
)
3126 machine_mode src_mode
, dest_mode
;
3128 if (GET_CODE (op
) == MEM
3129 && ! m32c_legitimate_address_p (Pmode
, XEXP (op
, 0), false))
3134 if (GET_CODE (op
) != SUBREG
)
3137 dest_mode
= GET_MODE (op
);
3138 offset
= SUBREG_BYTE (op
);
3139 op
= SUBREG_REG (op
);
3140 src_mode
= GET_MODE (op
);
3142 if (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (src_mode
))
3144 if (GET_CODE (op
) != REG
)
3146 if (REGNO (op
) >= MEM0_REGNO
)
3149 offset
= (1 << offset
);
3151 for (i
= 0; i
< ARRAY_SIZE (legal_subregs
); i
++)
3152 if (legal_subregs
[i
].outer_mode_size
== GET_MODE_SIZE (dest_mode
)
3153 && legal_subregs
[i
].regno
== REGNO (op
)
3154 && legal_subregs
[i
].inner_mode_size
== GET_MODE_SIZE (src_mode
)
3155 && legal_subregs
[i
].byte_mask
& offset
)
3157 switch (legal_subregs
[i
].legal_when
)
3174 /* Returns TRUE if we support a move between the first two operands.
3175 At the moment, we just want to discourage mem to mem moves until
3176 after reload, because reload has a hard time with our limited
3177 number of address registers, and we can get into a situation where
3178 we need three of them when we only have two. */
3180 m32c_mov_ok (rtx
* operands
, machine_mode mode ATTRIBUTE_UNUSED
)
3182 rtx op0
= operands
[0];
3183 rtx op1
= operands
[1];
3188 #define DEBUG_MOV_OK 0
3190 fprintf (stderr
, "m32c_mov_ok %s\n", mode_name
[mode
]);
3195 if (GET_CODE (op0
) == SUBREG
)
3196 op0
= XEXP (op0
, 0);
3197 if (GET_CODE (op1
) == SUBREG
)
3198 op1
= XEXP (op1
, 0);
3200 if (GET_CODE (op0
) == MEM
3201 && GET_CODE (op1
) == MEM
3202 && ! reload_completed
)
3205 fprintf (stderr
, " - no, mem to mem\n");
3211 fprintf (stderr
, " - ok\n");
3216 /* Returns TRUE if two consecutive HImode mov instructions, generated
3217 for moving an immediate double data to a double data type variable
3218 location, can be combined into single SImode mov instruction. */
3220 m32c_immd_dbl_mov (rtx
* operands ATTRIBUTE_UNUSED
,
3221 machine_mode mode ATTRIBUTE_UNUSED
)
3223 /* ??? This relied on the now-defunct MEM_SCALAR and MEM_IN_STRUCT_P
3230 /* Subregs are non-orthogonal for us, because our registers are all
3233 m32c_subreg (machine_mode outer
,
3234 rtx x
, machine_mode inner
, int byte
)
3238 /* Converting MEMs to different types that are the same size, we
3239 just rewrite them. */
3240 if (GET_CODE (x
) == SUBREG
3241 && SUBREG_BYTE (x
) == 0
3242 && GET_CODE (SUBREG_REG (x
)) == MEM
3243 && (GET_MODE_SIZE (GET_MODE (x
))
3244 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3247 x
= gen_rtx_MEM (GET_MODE (x
), XEXP (SUBREG_REG (x
), 0));
3248 MEM_COPY_ATTRIBUTES (x
, SUBREG_REG (oldx
));
3251 /* Push/pop get done as smaller push/pops. */
3252 if (GET_CODE (x
) == MEM
3253 && (GET_CODE (XEXP (x
, 0)) == PRE_DEC
3254 || GET_CODE (XEXP (x
, 0)) == POST_INC
))
3255 return gen_rtx_MEM (outer
, XEXP (x
, 0));
3256 if (GET_CODE (x
) == SUBREG
3257 && GET_CODE (XEXP (x
, 0)) == MEM
3258 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PRE_DEC
3259 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == POST_INC
))
3260 return gen_rtx_MEM (outer
, XEXP (XEXP (x
, 0), 0));
3262 if (GET_CODE (x
) != REG
)
3264 rtx r
= simplify_gen_subreg (outer
, x
, inner
, byte
);
3265 if (GET_CODE (r
) == SUBREG
3266 && GET_CODE (x
) == MEM
3267 && MEM_VOLATILE_P (x
))
3269 /* Volatile MEMs don't get simplified, but we need them to
3270 be. We are little endian, so the subreg byte is the
3272 r
= adjust_address_nv (x
, outer
, byte
);
3278 if (r
>= FIRST_PSEUDO_REGISTER
|| r
== AP_REGNO
)
3279 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3281 if (IS_MEM_REGNO (r
))
3282 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3284 /* This is where the complexities of our register layout are
3288 else if (outer
== HImode
)
3290 if (r
== R0_REGNO
&& byte
== 2)
3292 else if (r
== R0_REGNO
&& byte
== 4)
3294 else if (r
== R0_REGNO
&& byte
== 6)
3296 else if (r
== R1_REGNO
&& byte
== 2)
3298 else if (r
== A0_REGNO
&& byte
== 2)
3301 else if (outer
== SImode
)
3303 if (r
== R0_REGNO
&& byte
== 0)
3305 else if (r
== R0_REGNO
&& byte
== 4)
3310 fprintf (stderr
, "m32c_subreg %s %s %d\n",
3311 mode_name
[outer
], mode_name
[inner
], byte
);
3315 return gen_rtx_REG (outer
, nr
);
3318 /* Used to emit move instructions. We split some moves,
3319 and avoid mem-mem moves. */
3321 m32c_prepare_move (rtx
* operands
, machine_mode mode
)
3323 if (far_addr_space_p (operands
[0])
3324 && CONSTANT_P (operands
[1]))
3326 operands
[1] = force_reg (GET_MODE (operands
[0]), operands
[1]);
3328 if (TARGET_A16
&& mode
== PSImode
)
3329 return m32c_split_move (operands
, mode
, 1);
3330 if ((GET_CODE (operands
[0]) == MEM
)
3331 && (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
))
3333 rtx pmv
= XEXP (operands
[0], 0);
3334 rtx dest_reg
= XEXP (pmv
, 0);
3335 rtx dest_mod
= XEXP (pmv
, 1);
3337 emit_insn (gen_rtx_SET (dest_reg
, dest_mod
));
3338 operands
[0] = gen_rtx_MEM (mode
, dest_reg
);
3340 if (can_create_pseudo_p () && MEM_P (operands
[0]) && MEM_P (operands
[1]))
3341 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
3345 #define DEBUG_SPLIT 0
3347 /* Returns TRUE if the given PSImode move should be split. We split
3348 for all r8c/m16c moves, since it doesn't support them, and for
3349 POP.L as we can only *push* SImode. */
3351 m32c_split_psi_p (rtx
* operands
)
3354 fprintf (stderr
, "\nm32c_split_psi_p\n");
3355 debug_rtx (operands
[0]);
3356 debug_rtx (operands
[1]);
3361 fprintf (stderr
, "yes, A16\n");
3365 if (GET_CODE (operands
[1]) == MEM
3366 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3369 fprintf (stderr
, "yes, pop.l\n");
3374 fprintf (stderr
, "no, default\n");
3379 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3380 (define_expand), 1 if it is not optional (define_insn_and_split),
3381 and 3 for define_split (alternate api). */
3383 m32c_split_move (rtx
* operands
, machine_mode mode
, int split_all
)
3386 int parts
, si
, di
, rev
= 0;
3387 int rv
= 0, opi
= 2;
3388 machine_mode submode
= HImode
;
3389 rtx
*ops
, local_ops
[10];
3391 /* define_split modifies the existing operands, but the other two
3392 emit new insns. OPS is where we store the operand pairs, which
3403 /* Before splitting mem-mem moves, force one operand into a
3405 if (can_create_pseudo_p () && MEM_P (operands
[0]) && MEM_P (operands
[1]))
3408 fprintf (stderr
, "force_reg...\n");
3409 debug_rtx (operands
[1]);
3411 operands
[1] = force_reg (mode
, operands
[1]);
3413 debug_rtx (operands
[1]);
3420 fprintf (stderr
, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3422 debug_rtx (operands
[0]);
3423 debug_rtx (operands
[1]);
3426 /* Note that split_all is not used to select the api after this
3427 point, so it's safe to set it to 3 even with define_insn. */
3428 /* None of the chips can move SI operands to sp-relative addresses,
3429 so we always split those. */
3430 if (satisfies_constraint_Ss (operands
[0]))
3434 && (far_addr_space_p (operands
[0])
3435 || far_addr_space_p (operands
[1])))
3438 /* We don't need to split these. */
3441 && (mode
== SImode
|| mode
== PSImode
)
3442 && !(GET_CODE (operands
[1]) == MEM
3443 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
))
3446 /* First, enumerate the subregs we'll be dealing with. */
3447 for (si
= 0; si
< parts
; si
++)
3450 m32c_subreg (submode
, operands
[0], mode
,
3451 si
* GET_MODE_SIZE (submode
));
3453 m32c_subreg (submode
, operands
[1], mode
,
3454 si
* GET_MODE_SIZE (submode
));
3457 /* Split pushes by emitting a sequence of smaller pushes. */
3458 if (GET_CODE (d
[0]) == MEM
&& GET_CODE (XEXP (d
[0], 0)) == PRE_DEC
)
3460 for (si
= parts
- 1; si
>= 0; si
--)
3462 ops
[opi
++] = gen_rtx_MEM (submode
,
3463 gen_rtx_PRE_DEC (Pmode
,
3471 /* Likewise for pops. */
3472 else if (GET_CODE (s
[0]) == MEM
&& GET_CODE (XEXP (s
[0], 0)) == POST_INC
)
3474 for (di
= 0; di
< parts
; di
++)
3477 ops
[opi
++] = gen_rtx_MEM (submode
,
3478 gen_rtx_POST_INC (Pmode
,
3486 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3487 for (di
= 0; di
< parts
- 1; di
++)
3488 for (si
= di
+ 1; si
< parts
; si
++)
3489 if (reg_mentioned_p (d
[di
], s
[si
]))
3493 for (si
= 0; si
< parts
; si
++)
3499 for (si
= parts
- 1; si
>= 0; si
--)
3506 /* Now emit any moves we may have accumulated. */
3507 if (rv
&& split_all
!= 3)
3510 for (i
= 2; i
< opi
; i
+= 2)
3511 emit_move_insn (ops
[i
], ops
[i
+ 1]);
3516 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3517 the like. For the R8C they expect one of the addresses to be in
3518 R1L:An so we need to arrange for that. Otherwise, it's just a
3519 matter of picking out the operands we want and emitting the right
3520 pattern for them. All these expanders, which correspond to
3521 patterns in blkmov.md, must return nonzero if they expand the insn,
3522 or zero if they should FAIL. */
3524 /* This is a memset() opcode. All operands are implied, so we need to
3525 arrange for them to be in the right registers. The opcode wants
3526 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3527 the count (HI), and $2 the value (QI). */
3529 m32c_expand_setmemhi(rtx
*operands
)
3531 rtx desta
, count
, val
;
3534 desta
= XEXP (operands
[0], 0);
3535 count
= operands
[1];
3538 desto
= gen_reg_rtx (Pmode
);
3539 counto
= gen_reg_rtx (HImode
);
3541 if (GET_CODE (desta
) != REG
3542 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3543 desta
= copy_to_mode_reg (Pmode
, desta
);
3545 /* This looks like an arbitrary restriction, but this is by far the
3546 most common case. For counts 8..14 this actually results in
3547 smaller code with no speed penalty because the half-sized
3548 constant can be loaded with a shorter opcode. */
3549 if (GET_CODE (count
) == CONST_INT
3550 && GET_CODE (val
) == CONST_INT
3551 && ! (INTVAL (count
) & 1)
3552 && (INTVAL (count
) > 1)
3553 && (INTVAL (val
) <= 7 && INTVAL (val
) >= -8))
3555 unsigned v
= INTVAL (val
) & 0xff;
3557 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3558 val
= copy_to_mode_reg (HImode
, GEN_INT (v
));
3560 emit_insn (gen_setmemhi_whi_op (desto
, counto
, val
, desta
, count
));
3562 emit_insn (gen_setmemhi_wpsi_op (desto
, counto
, val
, desta
, count
));
3566 /* This is the generalized memset() case. */
3567 if (GET_CODE (val
) != REG
3568 || REGNO (val
) < FIRST_PSEUDO_REGISTER
)
3569 val
= copy_to_mode_reg (QImode
, val
);
3571 if (GET_CODE (count
) != REG
3572 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3573 count
= copy_to_mode_reg (HImode
, count
);
3576 emit_insn (gen_setmemhi_bhi_op (desto
, counto
, val
, desta
, count
));
3578 emit_insn (gen_setmemhi_bpsi_op (desto
, counto
, val
, desta
, count
));
3583 /* This is a memcpy() opcode. All operands are implied, so we need to
3584 arrange for them to be in the right registers. The opcode wants
3585 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3586 is the source (MEM:BLK), and $2 the count (HI). */
3588 m32c_expand_cpymemhi(rtx
*operands
)
3590 rtx desta
, srca
, count
;
3591 rtx desto
, srco
, counto
;
3593 desta
= XEXP (operands
[0], 0);
3594 srca
= XEXP (operands
[1], 0);
3595 count
= operands
[2];
3597 desto
= gen_reg_rtx (Pmode
);
3598 srco
= gen_reg_rtx (Pmode
);
3599 counto
= gen_reg_rtx (HImode
);
3601 if (GET_CODE (desta
) != REG
3602 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3603 desta
= copy_to_mode_reg (Pmode
, desta
);
3605 if (GET_CODE (srca
) != REG
3606 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3607 srca
= copy_to_mode_reg (Pmode
, srca
);
3609 /* Similar to setmem, but we don't need to check the value. */
3610 if (GET_CODE (count
) == CONST_INT
3611 && ! (INTVAL (count
) & 1)
3612 && (INTVAL (count
) > 1))
3614 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3616 emit_insn (gen_cpymemhi_whi_op (desto
, srco
, counto
, desta
, srca
, count
));
3618 emit_insn (gen_cpymemhi_wpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3622 /* This is the generalized memset() case. */
3623 if (GET_CODE (count
) != REG
3624 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3625 count
= copy_to_mode_reg (HImode
, count
);
3628 emit_insn (gen_cpymemhi_bhi_op (desto
, srco
, counto
, desta
, srca
, count
));
3630 emit_insn (gen_cpymemhi_bpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3635 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3636 the copy, which should point to the NUL at the end of the string,
3637 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3638 Since our opcode leaves the destination pointing *after* the NUL,
3639 we must emit an adjustment. */
3641 m32c_expand_movstr(rtx
*operands
)
3646 desta
= XEXP (operands
[1], 0);
3647 srca
= XEXP (operands
[2], 0);
3649 desto
= gen_reg_rtx (Pmode
);
3650 srco
= gen_reg_rtx (Pmode
);
3652 if (GET_CODE (desta
) != REG
3653 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3654 desta
= copy_to_mode_reg (Pmode
, desta
);
3656 if (GET_CODE (srca
) != REG
3657 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3658 srca
= copy_to_mode_reg (Pmode
, srca
);
3660 emit_insn (gen_movstr_op (desto
, srco
, desta
, srca
));
3661 /* desto ends up being a1, which allows this type of add through MOVA. */
3662 emit_insn (gen_addpsi3 (operands
[0], desto
, GEN_INT (-1)));
3667 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3668 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3669 $2 is the other (MEM:BLK). We must do the comparison, and then
3670 convert the flags to a signed integer result. */
3672 m32c_expand_cmpstr(rtx
*operands
)
3676 src1a
= XEXP (operands
[1], 0);
3677 src2a
= XEXP (operands
[2], 0);
3679 if (GET_CODE (src1a
) != REG
3680 || REGNO (src1a
) < FIRST_PSEUDO_REGISTER
)
3681 src1a
= copy_to_mode_reg (Pmode
, src1a
);
3683 if (GET_CODE (src2a
) != REG
3684 || REGNO (src2a
) < FIRST_PSEUDO_REGISTER
)
3685 src2a
= copy_to_mode_reg (Pmode
, src2a
);
3687 emit_insn (gen_cmpstrhi_op (src1a
, src2a
, src1a
, src2a
));
3688 emit_insn (gen_cond_to_int (operands
[0]));
3694 typedef rtx (*shift_gen_func
)(rtx
, rtx
, rtx
);
3696 static shift_gen_func
3697 shift_gen_func_for (int mode
, int code
)
3699 #define GFF(m,c,f) if (mode == m && code == c) return f
3700 GFF(QImode
, ASHIFT
, gen_ashlqi3_i
);
3701 GFF(QImode
, ASHIFTRT
, gen_ashrqi3_i
);
3702 GFF(QImode
, LSHIFTRT
, gen_lshrqi3_i
);
3703 GFF(HImode
, ASHIFT
, gen_ashlhi3_i
);
3704 GFF(HImode
, ASHIFTRT
, gen_ashrhi3_i
);
3705 GFF(HImode
, LSHIFTRT
, gen_lshrhi3_i
);
3706 GFF(PSImode
, ASHIFT
, gen_ashlpsi3_i
);
3707 GFF(PSImode
, ASHIFTRT
, gen_ashrpsi3_i
);
3708 GFF(PSImode
, LSHIFTRT
, gen_lshrpsi3_i
);
3709 GFF(SImode
, ASHIFT
, TARGET_A16
? gen_ashlsi3_16
: gen_ashlsi3_24
);
3710 GFF(SImode
, ASHIFTRT
, TARGET_A16
? gen_ashrsi3_16
: gen_ashrsi3_24
);
3711 GFF(SImode
, LSHIFTRT
, TARGET_A16
? gen_lshrsi3_16
: gen_lshrsi3_24
);
3716 /* The m32c only has one shift, but it takes a signed count. GCC
3717 doesn't want this, so we fake it by negating any shift count when
3718 we're pretending to shift the other way. Also, the shift count is
3719 limited to -8..8. It's slightly better to use two shifts for 9..15
3720 than to load the count into r1h, so we do that too. */
3722 m32c_prepare_shift (rtx
* operands
, int scale
, int shift_code
)
3724 machine_mode mode
= GET_MODE (operands
[0]);
3725 shift_gen_func func
= shift_gen_func_for (mode
, shift_code
);
3728 if (GET_CODE (operands
[2]) == CONST_INT
)
3730 int maxc
= TARGET_A24
&& (mode
== PSImode
|| mode
== SImode
) ? 32 : 8;
3731 int count
= INTVAL (operands
[2]) * scale
;
3733 while (count
> maxc
)
3735 temp
= gen_reg_rtx (mode
);
3736 emit_insn (func (temp
, operands
[1], GEN_INT (maxc
)));
3740 while (count
< -maxc
)
3742 temp
= gen_reg_rtx (mode
);
3743 emit_insn (func (temp
, operands
[1], GEN_INT (-maxc
)));
3747 emit_insn (func (operands
[0], operands
[1], GEN_INT (count
)));
3751 temp
= gen_reg_rtx (QImode
);
3753 /* The pattern has a NEG that corresponds to this. */
3754 emit_move_insn (temp
, gen_rtx_NEG (QImode
, operands
[2]));
3755 else if (TARGET_A16
&& mode
== SImode
)
3756 /* We do this because the code below may modify this, we don't
3757 want to modify the origin of this value. */
3758 emit_move_insn (temp
, operands
[2]);
3760 /* We'll only use it for the shift, no point emitting a move. */
3763 if (TARGET_A16
&& GET_MODE_SIZE (mode
) == 4)
3765 /* The m16c has a limit of -16..16 for SI shifts, even when the
3766 shift count is in a register. Since there are so many targets
3767 of these shifts, it's better to expand the RTL here than to
3768 call a helper function.
3770 The resulting code looks something like this:
3782 We take advantage of the fact that "negative" shifts are
3783 undefined to skip one of the comparisons. */
3789 emit_move_insn (operands
[0], operands
[1]);
3792 rtx_code_label
*label
= gen_label_rtx ();
3793 LABEL_NUSES (label
) ++;
3795 tempvar
= gen_reg_rtx (mode
);
3797 if (shift_code
== ASHIFT
)
3799 /* This is a left shift. We only need check positive counts. */
3800 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode
, 0, 0),
3801 count
, GEN_INT (16), label
));
3802 emit_insn (func (tempvar
, operands
[0], GEN_INT (8)));
3803 emit_insn (func (operands
[0], tempvar
, GEN_INT (8)));
3804 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (-16)));
3805 emit_label_after (label
, insn
);
3809 /* This is a right shift. We only need check negative counts. */
3810 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode
, 0, 0),
3811 count
, GEN_INT (-16), label
));
3812 emit_insn (func (tempvar
, operands
[0], GEN_INT (-8)));
3813 emit_insn (func (operands
[0], tempvar
, GEN_INT (-8)));
3814 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (16)));
3815 emit_label_after (label
, insn
);
3817 operands
[1] = operands
[0];
3818 emit_insn (func (operands
[0], operands
[0], count
));
3826 /* The m32c has a limited range of operations that work on PSImode
3827 values; we have to expand to SI, do the math, and truncate back to
3828 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3831 m32c_expand_neg_mulpsi3 (rtx
* operands
)
3833 /* operands: a = b * i */
3834 rtx temp1
; /* b as SI */
3835 rtx scale
/* i as SI */;
3836 rtx temp2
; /* a*b as SI */
3838 temp1
= gen_reg_rtx (SImode
);
3839 temp2
= gen_reg_rtx (SImode
);
3840 if (GET_CODE (operands
[2]) != CONST_INT
)
3842 scale
= gen_reg_rtx (SImode
);
3843 emit_insn (gen_zero_extendpsisi2 (scale
, operands
[2]));
3846 scale
= copy_to_mode_reg (SImode
, operands
[2]);
3848 emit_insn (gen_zero_extendpsisi2 (temp1
, operands
[1]));
3849 temp2
= expand_simple_binop (SImode
, MULT
, temp1
, scale
, temp2
, 1, OPTAB_LIB
);
3850 emit_insn (gen_truncsipsi2 (operands
[0], temp2
));
3853 /* Pattern Output Functions */
3856 m32c_expand_movcc (rtx
*operands
)
3858 rtx rel
= operands
[1];
3860 if (GET_CODE (rel
) != EQ
&& GET_CODE (rel
) != NE
)
3862 if (GET_CODE (operands
[2]) != CONST_INT
3863 || GET_CODE (operands
[3]) != CONST_INT
)
3865 if (GET_CODE (rel
) == NE
)
3867 rtx tmp
= operands
[2];
3868 operands
[2] = operands
[3];
3870 rel
= gen_rtx_EQ (GET_MODE (rel
), XEXP (rel
, 0), XEXP (rel
, 1));
3873 emit_move_insn (operands
[0],
3874 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
3881 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3883 m32c_expand_insv (rtx
*operands
)
3888 if (INTVAL (operands
[1]) != 1)
3891 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3892 if (GET_CODE (operands
[3]) != CONST_INT
)
3894 if (INTVAL (operands
[3]) != 0
3895 && INTVAL (operands
[3]) != 1
3896 && INTVAL (operands
[3]) != -1)
3899 mask
= 1 << INTVAL (operands
[2]);
3902 if (GET_CODE (op0
) == SUBREG
3903 && SUBREG_BYTE (op0
) == 0)
3905 rtx sub
= SUBREG_REG (op0
);
3906 if (GET_MODE (sub
) == HImode
|| GET_MODE (sub
) == QImode
)
3910 if (!can_create_pseudo_p ()
3911 || (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
)))
3915 src0
= gen_reg_rtx (GET_MODE (op0
));
3916 emit_move_insn (src0
, op0
);
3919 if (GET_MODE (op0
) == HImode
3920 && INTVAL (operands
[2]) >= 8
3921 && GET_CODE (op0
) == MEM
)
3923 /* We are little endian. */
3924 rtx new_mem
= gen_rtx_MEM (QImode
, plus_constant (Pmode
,
3926 MEM_COPY_ATTRIBUTES (new_mem
, op0
);
3930 /* First, we generate a mask with the correct polarity. If we are
3931 storing a zero, we want an AND mask, so invert it. */
3932 if (INTVAL (operands
[3]) == 0)
3934 /* Storing a zero, use an AND mask */
3935 if (GET_MODE (op0
) == HImode
)
3940 /* Now we need to properly sign-extend the mask in case we need to
3941 fall back to an AND or OR opcode. */
3942 if (GET_MODE (op0
) == HImode
)
3953 switch ( (INTVAL (operands
[3]) ? 4 : 0)
3954 + ((GET_MODE (op0
) == HImode
) ? 2 : 0)
3955 + (TARGET_A24
? 1 : 0))
3957 case 0: p
= gen_andqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3958 case 1: p
= gen_andqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3959 case 2: p
= gen_andhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3960 case 3: p
= gen_andhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3961 case 4: p
= gen_iorqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3962 case 5: p
= gen_iorqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3963 case 6: p
= gen_iorhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3964 case 7: p
= gen_iorhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3965 default: p
= NULL_RTX
; break; /* Not reached, but silences a warning. */
3973 m32c_scc_pattern(rtx
*operands
, RTX_CODE code
)
3975 static char buf
[30];
3976 if (GET_CODE (operands
[0]) == REG
3977 && REGNO (operands
[0]) == R0_REGNO
)
3980 return "stzx\t#1,#0,r0l";
3982 return "stzx\t#0,#1,r0l";
3984 sprintf(buf
, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code
));
3988 /* Encode symbol attributes of a SYMBOL_REF into its
3989 SYMBOL_REF_FLAGS. */
3991 m32c_encode_section_info (tree decl
, rtx rtl
, int first
)
3993 int extra_flags
= 0;
3995 default_encode_section_info (decl
, rtl
, first
);
3996 if (TREE_CODE (decl
) == FUNCTION_DECL
3997 && m32c_special_page_vector_p (decl
))
3999 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
4002 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
4005 /* Returns TRUE if the current function is a leaf, and thus we can
4006 determine which registers an interrupt function really needs to
4007 save. The logic below is mostly about finding the insn sequence
4008 that's the function, versus any sequence that might be open for the
4011 m32c_leaf_function_p (void)
4015 push_topmost_sequence ();
4016 rv
= leaf_function_p ();
4017 pop_topmost_sequence ();
4021 /* Returns TRUE if the current function needs to use the ENTER/EXIT
4022 opcodes. If the function doesn't need the frame base or stack
4023 pointer, it can use the simpler RTS opcode. */
4025 m32c_function_needs_enter (void)
4028 rtx sp
= gen_rtx_REG (Pmode
, SP_REGNO
);
4029 rtx fb
= gen_rtx_REG (Pmode
, FB_REGNO
);
4031 for (insn
= get_topmost_sequence ()->first
; insn
; insn
= NEXT_INSN (insn
))
4032 if (NONDEBUG_INSN_P (insn
))
4034 if (reg_mentioned_p (sp
, insn
))
4036 if (reg_mentioned_p (fb
, insn
))
4042 /* Mark all the subexpressions of the PARALLEL rtx PAR as
4043 frame-related. Return PAR.
4045 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
4046 PARALLEL rtx other than the first if they do not have the
4047 FRAME_RELATED flag set on them. So this function is handy for
4048 marking up 'enter' instructions. */
4050 m32c_all_frame_related (rtx par
)
4052 int len
= XVECLEN (par
, 0);
4055 for (i
= 0; i
< len
; i
++)
4056 F (XVECEXP (par
, 0, i
));
4061 /* Emits the prologue. See the frame layout comment earlier in this
4062 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
4063 that we manually update sp. */
4065 m32c_emit_prologue (void)
4067 int frame_size
, extra_frame_size
= 0, reg_save_size
;
4068 int complex_prologue
= 0;
4070 cfun
->machine
->is_leaf
= m32c_leaf_function_p ();
4071 if (interrupt_p (cfun
->decl
))
4073 cfun
->machine
->is_interrupt
= 1;
4074 complex_prologue
= 1;
4076 else if (bank_switch_p (cfun
->decl
))
4077 warning (OPT_Wattributes
,
4078 "%<bank_switch%> has no effect on non-interrupt functions");
4080 reg_save_size
= m32c_pushm_popm (PP_justcount
);
4082 if (interrupt_p (cfun
->decl
))
4084 if (bank_switch_p (cfun
->decl
))
4085 emit_insn (gen_fset_b ());
4086 else if (cfun
->machine
->intr_pushm
)
4087 emit_insn (gen_pushm (GEN_INT (cfun
->machine
->intr_pushm
)));
4091 m32c_initial_elimination_offset (FB_REGNO
, SP_REGNO
) - reg_save_size
;
4093 && !m32c_function_needs_enter ())
4094 cfun
->machine
->use_rts
= 1;
4096 if (flag_stack_usage_info
)
4097 current_function_static_stack_size
= frame_size
;
4099 if (frame_size
> 254)
4101 extra_frame_size
= frame_size
- 254;
4104 if (cfun
->machine
->use_rts
== 0)
4105 F (emit_insn (m32c_all_frame_related
4107 ? gen_prologue_enter_16 (GEN_INT (frame_size
+ 2))
4108 : gen_prologue_enter_24 (GEN_INT (frame_size
+ 4)))));
4110 if (extra_frame_size
)
4112 complex_prologue
= 1;
4114 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode
, SP_REGNO
),
4115 gen_rtx_REG (HImode
, SP_REGNO
),
4116 GEN_INT (-extra_frame_size
))));
4118 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode
, SP_REGNO
),
4119 gen_rtx_REG (PSImode
, SP_REGNO
),
4120 GEN_INT (-extra_frame_size
))));
4123 complex_prologue
+= m32c_pushm_popm (PP_pushm
);
4125 /* This just emits a comment into the .s file for debugging. */
4126 if (complex_prologue
)
4127 emit_insn (gen_prologue_end ());
4130 /* Likewise, for the epilogue. The only exception is that, for
4131 interrupts, we must manually unwind the frame as the REIT opcode
4134 m32c_emit_epilogue (void)
4136 int popm_count
= m32c_pushm_popm (PP_justcount
);
4138 /* This just emits a comment into the .s file for debugging. */
4139 if (popm_count
> 0 || cfun
->machine
->is_interrupt
)
4140 emit_insn (gen_epilogue_start ());
4143 m32c_pushm_popm (PP_popm
);
4145 if (cfun
->machine
->is_interrupt
)
4147 machine_mode spmode
= TARGET_A16
? HImode
: PSImode
;
4149 /* REIT clears B flag and restores $fp for us, but we still
4150 have to fix up the stack. USE_RTS just means we didn't
4152 if (!cfun
->machine
->use_rts
)
4154 emit_move_insn (gen_rtx_REG (spmode
, A0_REGNO
),
4155 gen_rtx_REG (spmode
, FP_REGNO
));
4156 emit_move_insn (gen_rtx_REG (spmode
, SP_REGNO
),
4157 gen_rtx_REG (spmode
, A0_REGNO
));
4158 /* We can't just add this to the POPM because it would be in
4159 the wrong order, and wouldn't fix the stack if we're bank
4162 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, FP_REGNO
)));
4164 emit_insn (gen_poppsi (gen_rtx_REG (PSImode
, FP_REGNO
)));
4166 if (!bank_switch_p (cfun
->decl
) && cfun
->machine
->intr_pushm
)
4167 emit_insn (gen_popm (GEN_INT (cfun
->machine
->intr_pushm
)));
4169 /* The FREIT (Fast REturn from InTerrupt) instruction should be
4170 generated only for M32C/M32CM targets (generate the REIT
4171 instruction otherwise). */
4172 if (fast_interrupt_p (cfun
->decl
))
4174 /* Check if fast_attribute is set for M32C or M32CM. */
4177 emit_jump_insn (gen_epilogue_freit ());
4179 /* If fast_interrupt attribute is set for an R8C or M16C
4180 target ignore this attribute and generated REIT
4184 warning (OPT_Wattributes
,
4185 "%<fast_interrupt%> attribute directive ignored");
4186 emit_jump_insn (gen_epilogue_reit_16 ());
4189 else if (TARGET_A16
)
4190 emit_jump_insn (gen_epilogue_reit_16 ());
4192 emit_jump_insn (gen_epilogue_reit_24 ());
4194 else if (cfun
->machine
->use_rts
)
4195 emit_jump_insn (gen_epilogue_rts ());
4196 else if (TARGET_A16
)
4197 emit_jump_insn (gen_epilogue_exitd_16 ());
4199 emit_jump_insn (gen_epilogue_exitd_24 ());
4203 m32c_emit_eh_epilogue (rtx ret_addr
)
4205 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4206 return to. We have to fudge the stack, pop everything, pop SP
4207 (fudged), and return (fudged). This is actually easier to do in
4208 assembler, so punt to libgcc. */
4209 emit_jump_insn (gen_eh_epilogue (ret_addr
, cfun
->machine
->eh_stack_adjust
));
4210 /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
4213 /* Indicate which flags must be properly set for a given conditional. */
4215 flags_needed_for_conditional (rtx cond
)
4217 switch (GET_CODE (cond
))
4241 /* Returns true if a compare insn is redundant because it would only
4242 set flags that are already set correctly. */
4244 m32c_compare_redundant (rtx_insn
*cmp
, rtx
*operands
)
4259 fprintf(stderr
, "\n\033[32mm32c_compare_redundant\033[0m\n");
4263 fprintf(stderr
, "operands[%d] = ", i
);
4264 debug_rtx(operands
[i
]);
4268 next
= next_nonnote_insn (cmp
);
4269 if (!next
|| !INSN_P (next
))
4272 fprintf(stderr
, "compare not followed by insn\n");
4277 if (GET_CODE (PATTERN (next
)) == SET
4278 && GET_CODE (XEXP ( PATTERN (next
), 1)) == IF_THEN_ELSE
)
4280 next
= XEXP (XEXP (PATTERN (next
), 1), 0);
4282 else if (GET_CODE (PATTERN (next
)) == SET
)
4284 /* If this is a conditional, flags_needed will be something
4285 other than FLAGS_N, which we test below. */
4286 next
= XEXP (PATTERN (next
), 1);
4291 fprintf(stderr
, "compare not followed by conditional\n");
4297 fprintf(stderr
, "conditional is: ");
4301 flags_needed
= flags_needed_for_conditional (next
);
4302 if (flags_needed
== FLAGS_N
)
4305 fprintf(stderr
, "compare not followed by conditional\n");
4311 /* Compare doesn't set overflow and carry the same way that
4312 arithmetic instructions do, so we can't replace those. */
4313 if (flags_needed
& FLAGS_OC
)
4318 prev
= prev_nonnote_insn (prev
);
4322 fprintf(stderr
, "No previous insn.\n");
4329 fprintf(stderr
, "Previous insn is a non-insn.\n");
4333 pp
= PATTERN (prev
);
4334 if (GET_CODE (pp
) != SET
)
4337 fprintf(stderr
, "Previous insn is not a SET.\n");
4341 pflags
= get_attr_flags (prev
);
4343 /* Looking up attributes of previous insns corrupted the recog
4345 INSN_UID (cmp
) = -1;
4346 recog (PATTERN (cmp
), cmp
, 0);
4348 if (pflags
== FLAGS_N
4349 && reg_mentioned_p (op0
, pp
))
4352 fprintf(stderr
, "intermediate non-flags insn uses op:\n");
4358 /* Check for comparisons against memory - between volatiles and
4359 aliases, we just can't risk this one. */
4360 if (GET_CODE (operands
[0]) == MEM
4361 || GET_CODE (operands
[0]) == MEM
)
4364 fprintf(stderr
, "comparisons with memory:\n");
4370 /* Check for PREV changing a register that's used to compute a
4371 value in CMP, even if it doesn't otherwise change flags. */
4372 if (GET_CODE (operands
[0]) == REG
4373 && rtx_referenced_p (SET_DEST (PATTERN (prev
)), operands
[0]))
4376 fprintf(stderr
, "sub-value affected, op0:\n");
4381 if (GET_CODE (operands
[1]) == REG
4382 && rtx_referenced_p (SET_DEST (PATTERN (prev
)), operands
[1]))
4385 fprintf(stderr
, "sub-value affected, op1:\n");
4391 } while (pflags
== FLAGS_N
);
4393 fprintf(stderr
, "previous flag-setting insn:\n");
4398 if (GET_CODE (pp
) == SET
4399 && GET_CODE (XEXP (pp
, 0)) == REG
4400 && REGNO (XEXP (pp
, 0)) == FLG_REGNO
4401 && GET_CODE (XEXP (pp
, 1)) == COMPARE
)
4403 /* Adjacent cbranches must have the same operands to be
4405 rtx pop0
= XEXP (XEXP (pp
, 1), 0);
4406 rtx pop1
= XEXP (XEXP (pp
, 1), 1);
4408 fprintf(stderr
, "adjacent cbranches\n");
4412 if (rtx_equal_p (op0
, pop0
)
4413 && rtx_equal_p (op1
, pop1
))
4416 fprintf(stderr
, "prev cmp not same\n");
4421 /* Else the previous insn must be a SET, with either the source or
4422 dest equal to operands[0], and operands[1] must be zero. */
4424 if (!rtx_equal_p (op1
, const0_rtx
))
4427 fprintf(stderr
, "operands[1] not const0_rtx\n");
4431 if (GET_CODE (pp
) != SET
)
4434 fprintf (stderr
, "pp not set\n");
4438 if (!rtx_equal_p (op0
, SET_SRC (pp
))
4439 && !rtx_equal_p (op0
, SET_DEST (pp
)))
4442 fprintf(stderr
, "operands[0] not found in set\n");
4448 fprintf(stderr
, "cmp flags %x prev flags %x\n", flags_needed
, pflags
);
4450 if ((pflags
& flags_needed
) == flags_needed
)
4456 /* Return the pattern for a compare. This will be commented out if
4457 the compare is redundant, else a normal pattern is returned. Thus,
4458 the assembler output says where the compare would have been. */
4460 m32c_output_compare (rtx_insn
*insn
, rtx
*operands
)
4462 static char templ
[] = ";cmp.b\t%1,%0";
4465 templ
[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands
[0]))];
4466 if (m32c_compare_redundant (insn
, operands
))
4469 fprintf(stderr
, "cbranch: cmp not needed\n");
4475 fprintf(stderr
, "cbranch: cmp needed: `%s'\n", templ
+ 1);
4480 #undef TARGET_ENCODE_SECTION_INFO
4481 #define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4483 /* If the frame pointer isn't used, we detect it manually. But the
4484 stack pointer doesn't have as flexible addressing as the frame
4485 pointer, so we always assume we have it. */
4487 #undef TARGET_FRAME_POINTER_REQUIRED
4488 #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
4490 #undef TARGET_HARD_REGNO_NREGS
4491 #define TARGET_HARD_REGNO_NREGS m32c_hard_regno_nregs
4492 #undef TARGET_HARD_REGNO_MODE_OK
4493 #define TARGET_HARD_REGNO_MODE_OK m32c_hard_regno_mode_ok
4494 #undef TARGET_MODES_TIEABLE_P
4495 #define TARGET_MODES_TIEABLE_P m32c_modes_tieable_p
4497 #undef TARGET_CAN_CHANGE_MODE_CLASS
4498 #define TARGET_CAN_CHANGE_MODE_CLASS m32c_can_change_mode_class
4500 /* The Global `targetm' Variable. */
4502 struct gcc_target targetm
= TARGET_INITIALIZER
;
4504 #include "gt-m32c.h"