1 /* Target Code for R8C/M16C/M32C
2 Copyright (C) 2005-2015 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
36 #include "diagnostic-core.h"
39 #include "stor-layout.h"
43 #include "insn-codes.h"
54 #include "target-def.h"
56 #include "langhooks.h"
57 #include "hash-table.h"
59 #include "dominance.h"
65 #include "cfgcleanup.h"
66 #include "basic-block.h"
67 #include "tree-ssa-alias.h"
68 #include "internal-fn.h"
69 #include "gimple-fold.h"
71 #include "gimple-expr.h"
75 #include "tm-constrs.h"
80 /* Used by m32c_pushm_popm. */
88 static bool m32c_function_needs_enter (void);
89 static tree
interrupt_handler (tree
*, tree
, tree
, int, bool *);
90 static tree
function_vector_handler (tree
*, tree
, tree
, int, bool *);
91 static int interrupt_p (tree node
);
92 static int bank_switch_p (tree node
);
93 static int fast_interrupt_p (tree node
);
94 static int interrupt_p (tree node
);
95 static bool m32c_asm_integer (rtx
, unsigned int, int);
96 static int m32c_comp_type_attributes (const_tree
, const_tree
);
97 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
98 static struct machine_function
*m32c_init_machine_status (void);
99 static void m32c_insert_attributes (tree
, tree
*);
100 static bool m32c_legitimate_address_p (machine_mode
, rtx
, bool);
101 static bool m32c_addr_space_legitimate_address_p (machine_mode
, rtx
, bool, addr_space_t
);
102 static rtx
m32c_function_arg (cumulative_args_t
, machine_mode
,
104 static bool m32c_pass_by_reference (cumulative_args_t
, machine_mode
,
106 static void m32c_function_arg_advance (cumulative_args_t
, machine_mode
,
108 static unsigned int m32c_function_arg_boundary (machine_mode
, const_tree
);
109 static int m32c_pushm_popm (Push_Pop_Type
);
110 static bool m32c_strict_argument_naming (cumulative_args_t
);
111 static rtx
m32c_struct_value_rtx (tree
, int);
112 static rtx
m32c_subreg (machine_mode
, rtx
, machine_mode
, int);
113 static int need_to_save (int);
114 static rtx
m32c_function_value (const_tree
, const_tree
, bool);
115 static rtx
m32c_libcall_value (machine_mode
, const_rtx
);
117 /* Returns true if an address is specified, else false. */
118 static bool m32c_get_pragma_address (const char *varname
, unsigned *addr
);
120 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
122 #define streq(a,b) (strcmp ((a), (b)) == 0)
124 /* Internal support routines */
126 /* Debugging statements are tagged with DEBUG0 only so that they can
127 be easily enabled individually, by replacing the '0' with '1' as
133 /* This is needed by some of the commented-out debug statements
135 static char const *class_names
[LIM_REG_CLASSES
] = REG_CLASS_NAMES
;
137 static int class_contents
[LIM_REG_CLASSES
][1] = REG_CLASS_CONTENTS
;
139 /* These are all to support encode_pattern(). */
140 static char pattern
[30], *patternp
;
141 static GTY(()) rtx patternr
[30];
142 #define RTX_IS(x) (streq (pattern, x))
144 /* Some macros to simplify the logic throughout this file. */
145 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
146 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
148 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
149 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
152 far_addr_space_p (rtx x
)
154 if (GET_CODE (x
) != MEM
)
157 fprintf(stderr
, "\033[35mfar_addr_space: "); debug_rtx(x
);
158 fprintf(stderr
, " = %d\033[0m\n", MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
);
160 return MEM_ADDR_SPACE (x
) == ADDR_SPACE_FAR
;
163 /* We do most RTX matching by converting the RTX into a string, and
164 using string compares. This vastly simplifies the logic in many of
165 the functions in this file.
167 On exit, pattern[] has the encoded string (use RTX_IS("...") to
168 compare it) and patternr[] has pointers to the nodes in the RTX
169 corresponding to each character in the encoded string. The latter
170 is mostly used by print_operand().
172 Unrecognized patterns have '?' in them; this shows up when the
173 assembler complains about syntax errors.
177 encode_pattern_1 (rtx x
)
181 if (patternp
== pattern
+ sizeof (pattern
) - 2)
187 patternr
[patternp
- pattern
] = x
;
189 switch (GET_CODE (x
))
195 if (GET_MODE_SIZE (GET_MODE (x
)) !=
196 GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))))
198 if (GET_MODE (x
) == PSImode
199 && GET_CODE (XEXP (x
, 0)) == REG
)
201 encode_pattern_1 (XEXP (x
, 0));
206 encode_pattern_1 (XEXP (x
, 0));
211 encode_pattern_1 (XEXP (x
, 0));
216 encode_pattern_1 (XEXP (x
, 0));
220 encode_pattern_1 (XEXP (x
, 0));
221 encode_pattern_1 (XEXP (x
, 1));
225 encode_pattern_1 (XEXP (x
, 0));
229 encode_pattern_1 (XEXP (x
, 0));
233 encode_pattern_1 (XEXP (x
, 0));
234 encode_pattern_1 (XEXP (x
, 1));
238 encode_pattern_1 (XEXP (x
, 0));
255 *patternp
++ = '0' + XCINT (x
, 1, UNSPEC
);
256 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
257 encode_pattern_1 (XVECEXP (x
, 0, i
));
264 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
265 encode_pattern_1 (XVECEXP (x
, 0, i
));
269 encode_pattern_1 (XEXP (x
, 0));
271 encode_pattern_1 (XEXP (x
, 1));
276 fprintf (stderr
, "can't encode pattern %s\n",
277 GET_RTX_NAME (GET_CODE (x
)));
286 encode_pattern (rtx x
)
289 encode_pattern_1 (x
);
293 /* Since register names indicate the mode they're used in, we need a
294 way to determine which name to refer to the register with. Called
295 by print_operand(). */
298 reg_name_with_mode (int regno
, machine_mode mode
)
300 int mlen
= GET_MODE_SIZE (mode
);
301 if (regno
== R0_REGNO
&& mlen
== 1)
303 if (regno
== R0_REGNO
&& (mlen
== 3 || mlen
== 4))
305 if (regno
== R0_REGNO
&& mlen
== 6)
307 if (regno
== R0_REGNO
&& mlen
== 8)
309 if (regno
== R1_REGNO
&& mlen
== 1)
311 if (regno
== R1_REGNO
&& (mlen
== 3 || mlen
== 4))
313 if (regno
== A0_REGNO
&& TARGET_A16
&& (mlen
== 3 || mlen
== 4))
315 return reg_names
[regno
];
318 /* How many bytes a register uses on stack when it's pushed. We need
319 to know this because the push opcode needs to explicitly indicate
320 the size of the register, even though the name of the register
321 already tells it that. Used by m32c_output_reg_{push,pop}, which
322 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
325 reg_push_size (int regno
)
350 /* Given two register classes, find the largest intersection between
351 them. If there is no intersection, return RETURNED_IF_EMPTY
354 reduce_class (reg_class_t original_class
, reg_class_t limiting_class
,
355 reg_class_t returned_if_empty
)
359 reg_class_t best
= NO_REGS
;
360 unsigned int best_size
= 0;
362 if (original_class
== limiting_class
)
363 return original_class
;
365 cc
= reg_class_contents
[original_class
];
366 AND_HARD_REG_SET (cc
, reg_class_contents
[limiting_class
]);
368 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
370 if (hard_reg_set_subset_p (reg_class_contents
[i
], cc
))
371 if (best_size
< reg_class_size
[i
])
373 best
= (reg_class_t
) i
;
374 best_size
= reg_class_size
[i
];
379 return returned_if_empty
;
383 /* Used by m32c_register_move_cost to determine if a move is
384 impossibly expensive. */
386 class_can_hold_mode (reg_class_t rclass
, machine_mode mode
)
388 /* Cache the results: 0=untested 1=no 2=yes */
389 static char results
[LIM_REG_CLASSES
][MAX_MACHINE_MODE
];
391 if (results
[(int) rclass
][mode
] == 0)
394 results
[rclass
][mode
] = 1;
395 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
396 if (in_hard_reg_set_p (reg_class_contents
[(int) rclass
], mode
, r
)
397 && HARD_REGNO_MODE_OK (r
, mode
))
399 results
[rclass
][mode
] = 2;
405 fprintf (stderr
, "class %s can hold %s? %s\n",
406 class_names
[(int) rclass
], mode_name
[mode
],
407 (results
[rclass
][mode
] == 2) ? "yes" : "no");
409 return results
[(int) rclass
][mode
] == 2;
412 /* Run-time Target Specification. */
414 /* Memregs are memory locations that gcc treats like general
415 registers, as there are a limited number of true registers and the
416 m32c families can use memory in most places that registers can be
419 However, since memory accesses are more expensive than registers,
420 we allow the user to limit the number of memregs available, in
421 order to try to persuade gcc to try harder to use real registers.
423 Memregs are provided by lib1funcs.S.
426 int ok_to_change_target_memregs
= TRUE
;
428 /* Implements TARGET_OPTION_OVERRIDE. */
430 #undef TARGET_OPTION_OVERRIDE
431 #define TARGET_OPTION_OVERRIDE m32c_option_override
434 m32c_option_override (void)
436 /* We limit memregs to 0..16, and provide a default. */
437 if (global_options_set
.x_target_memregs
)
439 if (target_memregs
< 0 || target_memregs
> 16)
440 error ("invalid target memregs value '%d'", target_memregs
);
448 /* This target defaults to strict volatile bitfields. */
449 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
450 flag_strict_volatile_bitfields
= 1;
452 /* r8c/m16c have no 16-bit indirect call, so thunks are involved.
453 This is always worse than an absolute call. */
455 flag_no_function_cse
= 1;
457 /* This wants to put insns between compares and their jumps. */
458 /* FIXME: The right solution is to properly trace the flags register
459 values, but that is too much work for stage 4. */
460 flag_combine_stack_adjustments
= 0;
463 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
464 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change
467 m32c_override_options_after_change (void)
470 flag_no_function_cse
= 1;
473 /* Defining data structures for per-function information */
475 /* The usual; we set up our machine_function data. */
476 static struct machine_function
*
477 m32c_init_machine_status (void)
479 return ggc_cleared_alloc
<machine_function
> ();
482 /* Implements INIT_EXPANDERS. We just set up to call the above
485 m32c_init_expanders (void)
487 init_machine_status
= m32c_init_machine_status
;
492 /* Register Basics */
494 /* Basic Characteristics of Registers */
496 /* Whether a mode fits in a register is complex enough to warrant a
505 } nregs_table
[FIRST_PSEUDO_REGISTER
] =
507 { 1, 1, 2, 2, 4 }, /* r0 */
508 { 0, 1, 0, 0, 0 }, /* r2 */
509 { 1, 1, 2, 2, 0 }, /* r1 */
510 { 0, 1, 0, 0, 0 }, /* r3 */
511 { 0, 1, 1, 0, 0 }, /* a0 */
512 { 0, 1, 1, 0, 0 }, /* a1 */
513 { 0, 1, 1, 0, 0 }, /* sb */
514 { 0, 1, 1, 0, 0 }, /* fb */
515 { 0, 1, 1, 0, 0 }, /* sp */
516 { 1, 1, 1, 0, 0 }, /* pc */
517 { 0, 0, 0, 0, 0 }, /* fl */
518 { 1, 1, 1, 0, 0 }, /* ap */
519 { 1, 1, 2, 2, 4 }, /* mem0 */
520 { 1, 1, 2, 2, 4 }, /* mem1 */
521 { 1, 1, 2, 2, 4 }, /* mem2 */
522 { 1, 1, 2, 2, 4 }, /* mem3 */
523 { 1, 1, 2, 2, 4 }, /* mem4 */
524 { 1, 1, 2, 2, 0 }, /* mem5 */
525 { 1, 1, 2, 2, 0 }, /* mem6 */
526 { 1, 1, 0, 0, 0 }, /* mem7 */
529 /* Implements TARGET_CONDITIONAL_REGISTER_USAGE. We adjust the number
530 of available memregs, and select which registers need to be preserved
531 across calls based on the chip family. */
533 #undef TARGET_CONDITIONAL_REGISTER_USAGE
534 #define TARGET_CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage
536 m32c_conditional_register_usage (void)
540 if (0 <= target_memregs
&& target_memregs
<= 16)
542 /* The command line option is bytes, but our "registers" are
544 for (i
= (target_memregs
+1)/2; i
< 8; i
++)
546 fixed_regs
[MEM0_REGNO
+ i
] = 1;
547 CLEAR_HARD_REG_BIT (reg_class_contents
[MEM_REGS
], MEM0_REGNO
+ i
);
551 /* M32CM and M32C preserve more registers across function calls. */
554 call_used_regs
[R1_REGNO
] = 0;
555 call_used_regs
[R2_REGNO
] = 0;
556 call_used_regs
[R3_REGNO
] = 0;
557 call_used_regs
[A0_REGNO
] = 0;
558 call_used_regs
[A1_REGNO
] = 0;
562 /* How Values Fit in Registers */
564 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
565 different registers are different sizes from each other, *and* may
566 be different sizes in different chip families. */
568 m32c_hard_regno_nregs_1 (int regno
, machine_mode mode
)
570 if (regno
== FLG_REGNO
&& mode
== CCmode
)
572 if (regno
>= FIRST_PSEUDO_REGISTER
)
573 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
575 if (regno
>= MEM0_REGNO
&& regno
<= MEM7_REGNO
)
576 return (GET_MODE_SIZE (mode
) + 1) / 2;
578 if (GET_MODE_SIZE (mode
) <= 1)
579 return nregs_table
[regno
].qi_regs
;
580 if (GET_MODE_SIZE (mode
) <= 2)
581 return nregs_table
[regno
].hi_regs
;
582 if (regno
== A0_REGNO
&& mode
== SImode
&& TARGET_A16
)
584 if ((GET_MODE_SIZE (mode
) <= 3 || mode
== PSImode
) && TARGET_A24
)
585 return nregs_table
[regno
].pi_regs
;
586 if (GET_MODE_SIZE (mode
) <= 4)
587 return nregs_table
[regno
].si_regs
;
588 if (GET_MODE_SIZE (mode
) <= 8)
589 return nregs_table
[regno
].di_regs
;
594 m32c_hard_regno_nregs (int regno
, machine_mode mode
)
596 int rv
= m32c_hard_regno_nregs_1 (regno
, mode
);
600 /* Implements HARD_REGNO_MODE_OK. The above function does the work
601 already; just test its return value. */
603 m32c_hard_regno_ok (int regno
, machine_mode mode
)
605 return m32c_hard_regno_nregs_1 (regno
, mode
) != 0;
608 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
609 registers are all different sizes. However, since most modes are
610 bigger than our registers anyway, it's easier to implement this
611 function that way, leaving QImode as the only unique case. */
613 m32c_modes_tieable_p (machine_mode m1
, machine_mode m2
)
615 if (GET_MODE_SIZE (m1
) == GET_MODE_SIZE (m2
))
619 if (m1
== QImode
|| m2
== QImode
)
626 /* Register Classes */
628 /* Implements REGNO_REG_CLASS. */
630 m32c_regno_reg_class (int regno
)
655 if (IS_MEM_REGNO (regno
))
661 /* Implements REGNO_OK_FOR_BASE_P. */
663 m32c_regno_ok_for_base_p (int regno
)
665 if (regno
== A0_REGNO
666 || regno
== A1_REGNO
|| regno
>= FIRST_PSEUDO_REGISTER
)
671 #define DEBUG_RELOAD 0
673 /* Implements TARGET_PREFERRED_RELOAD_CLASS. In general, prefer general
674 registers of the appropriate size. */
676 #undef TARGET_PREFERRED_RELOAD_CLASS
677 #define TARGET_PREFERRED_RELOAD_CLASS m32c_preferred_reload_class
680 m32c_preferred_reload_class (rtx x
, reg_class_t rclass
)
682 reg_class_t newclass
= rclass
;
685 fprintf (stderr
, "\npreferred_reload_class for %s is ",
686 class_names
[rclass
]);
688 if (rclass
== NO_REGS
)
689 rclass
= GET_MODE (x
) == QImode
? HL_REGS
: R03_REGS
;
691 if (reg_classes_intersect_p (rclass
, CR_REGS
))
693 switch (GET_MODE (x
))
699 /* newclass = HI_REGS; */
704 else if (newclass
== QI_REGS
&& GET_MODE_SIZE (GET_MODE (x
)) > 2)
706 else if (GET_MODE_SIZE (GET_MODE (x
)) > 4
707 && ! reg_class_subset_p (R03_REGS
, rclass
))
710 rclass
= reduce_class (rclass
, newclass
, rclass
);
712 if (GET_MODE (x
) == QImode
)
713 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
716 fprintf (stderr
, "%s\n", class_names
[rclass
]);
719 if (GET_CODE (x
) == MEM
720 && GET_CODE (XEXP (x
, 0)) == PLUS
721 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
722 fprintf (stderr
, "Glorm!\n");
727 /* Implements TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
729 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
730 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS m32c_preferred_output_reload_class
733 m32c_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
735 return m32c_preferred_reload_class (x
, rclass
);
738 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
739 address registers for reloads since they're needed for address
742 m32c_limit_reload_class (machine_mode mode
, int rclass
)
745 fprintf (stderr
, "limit_reload_class for %s: %s ->",
746 mode_name
[mode
], class_names
[rclass
]);
750 rclass
= reduce_class (rclass
, HL_REGS
, rclass
);
751 else if (mode
== HImode
)
752 rclass
= reduce_class (rclass
, HI_REGS
, rclass
);
753 else if (mode
== SImode
)
754 rclass
= reduce_class (rclass
, SI_REGS
, rclass
);
756 if (rclass
!= A_REGS
)
757 rclass
= reduce_class (rclass
, DI_REGS
, rclass
);
760 fprintf (stderr
, " %s\n", class_names
[rclass
]);
765 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
766 r0 or r1, as those are the only real QImode registers. CR regs get
767 reloaded through appropriately sized general or address
770 m32c_secondary_reload_class (int rclass
, machine_mode mode
, rtx x
)
772 int cc
= class_contents
[rclass
][0];
774 fprintf (stderr
, "\nsecondary reload class %s %s\n",
775 class_names
[rclass
], mode_name
[mode
]);
779 && GET_CODE (x
) == MEM
&& (cc
& ~class_contents
[R23_REGS
][0]) == 0)
781 if (reg_classes_intersect_p (rclass
, CR_REGS
)
782 && GET_CODE (x
) == REG
783 && REGNO (x
) >= SB_REGNO
&& REGNO (x
) <= SP_REGNO
)
784 return (TARGET_A16
|| mode
== HImode
) ? HI_REGS
: A_REGS
;
788 /* Implements TARGET_CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
791 #undef TARGET_CLASS_LIKELY_SPILLED_P
792 #define TARGET_CLASS_LIKELY_SPILLED_P m32c_class_likely_spilled_p
795 m32c_class_likely_spilled_p (reg_class_t regclass
)
797 if (regclass
== A_REGS
)
800 return (reg_class_size
[(int) regclass
] == 1);
803 /* Implements TARGET_CLASS_MAX_NREGS. We calculate this according to its
804 documented meaning, to avoid potential inconsistencies with actual
805 class definitions. */
807 #undef TARGET_CLASS_MAX_NREGS
808 #define TARGET_CLASS_MAX_NREGS m32c_class_max_nregs
811 m32c_class_max_nregs (reg_class_t regclass
, machine_mode mode
)
814 unsigned char max
= 0;
816 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
817 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) regclass
], rn
))
819 unsigned char n
= m32c_hard_regno_nregs (rn
, mode
);
826 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
827 QI (r0l, r1l) because the chip doesn't support QI ops on other
828 registers (well, it does on a0/a1 but if we let gcc do that, reload
829 suffers). Otherwise, we allow changes to larger modes. */
831 m32c_cannot_change_mode_class (machine_mode from
,
832 machine_mode to
, int rclass
)
836 fprintf (stderr
, "cannot change from %s to %s in %s\n",
837 mode_name
[from
], mode_name
[to
], class_names
[rclass
]);
840 /* If the larger mode isn't allowed in any of these registers, we
841 can't allow the change. */
842 for (rn
= 0; rn
< FIRST_PSEUDO_REGISTER
; rn
++)
843 if (class_contents
[rclass
][0] & (1 << rn
))
844 if (! m32c_hard_regno_ok (rn
, to
))
848 return (class_contents
[rclass
][0] & 0x1ffa);
850 if (class_contents
[rclass
][0] & 0x0005 /* r0, r1 */
851 && GET_MODE_SIZE (from
) > 1)
853 if (GET_MODE_SIZE (from
) > 2) /* all other regs */
859 /* Helpers for the rest of the file. */
860 /* TRUE if the rtx is a REG rtx for the given register. */
861 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
862 && REGNO (rtx) == regno)
863 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
864 base register in address calculations (hence the "strict"
866 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
867 && (REGNO (rtx) == AP_REGNO \
868 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
870 #define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)
872 /* Implements matching for constraints (see next function too). 'S' is
873 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
874 call return values. */
876 m32c_matches_constraint_p (rtx value
, int constraint
)
878 encode_pattern (value
);
880 switch (constraint
) {
882 return (far_addr_space_p (value
)
884 && A0_OR_PSEUDO (patternr
[1])
885 && GET_MODE (patternr
[1]) == SImode
)
886 || (RTX_IS ("m+^Sri")
887 && A0_OR_PSEUDO (patternr
[4])
888 && GET_MODE (patternr
[4]) == HImode
)
889 || (RTX_IS ("m+^Srs")
890 && A0_OR_PSEUDO (patternr
[4])
891 && GET_MODE (patternr
[4]) == HImode
)
892 || (RTX_IS ("m+^S+ris")
893 && A0_OR_PSEUDO (patternr
[5])
894 && GET_MODE (patternr
[5]) == HImode
)
898 /* This is the common "src/dest" address */
900 if (GET_CODE (value
) == MEM
&& CONSTANT_P (XEXP (value
, 0)))
902 if (RTX_IS ("ms") || RTX_IS ("m+si"))
904 if (RTX_IS ("m++rii"))
906 if (REGNO (patternr
[3]) == FB_REGNO
907 && INTVAL (patternr
[4]) == 0)
912 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
916 if (REGNO (r
) == SP_REGNO
)
918 return m32c_legitimate_address_p (GET_MODE (value
), XEXP (value
, 0), 1);
925 else if (RTX_IS ("m+ri"))
929 return (IS_REG (r
, A0_REGNO
) || IS_REG (r
, A1_REGNO
));
932 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
934 return ((RTX_IS ("mr")
935 && (IS_REG (patternr
[1], SP_REGNO
)))
936 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SP_REGNO
))));
938 return ((RTX_IS ("mr")
939 && (IS_REG (patternr
[1], FB_REGNO
)))
940 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], FB_REGNO
))));
942 return ((RTX_IS ("mr")
943 && (IS_REG (patternr
[1], SB_REGNO
)))
944 || (RTX_IS ("m+ri") && (IS_REG (patternr
[2], SB_REGNO
))));
946 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
947 return (RTX_IS ("mi")
948 && !(INTVAL (patternr
[1]) & ~0x1fff));
950 return r1h_operand (value
, QImode
);
952 return GET_CODE (value
) == PARALLEL
;
958 /* STACK AND CALLING */
962 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
963 (yes, THREE bytes) onto the stack for the return address, but we
964 don't support pointers bigger than 16 bits on those chips. This
965 will likely wreak havoc with exception unwinding. FIXME. */
967 m32c_return_addr_rtx (int count
)
979 /* It's four bytes */
985 /* FIXME: it's really 3 bytes */
991 gen_rtx_MEM (mode
, plus_constant (Pmode
, gen_rtx_REG (Pmode
, FP_REGNO
),
993 return copy_to_mode_reg (mode
, ra_mem
);
996 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
998 m32c_incoming_return_addr_rtx (void)
1001 return gen_rtx_MEM (PSImode
, gen_rtx_REG (PSImode
, SP_REGNO
));
1004 /* Exception Handling Support */
1006 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1009 m32c_eh_return_data_regno (int n
)
1016 return MEM0_REGNO
+4;
1018 return INVALID_REGNUM
;
1022 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1023 m32c_emit_eh_epilogue. */
1025 m32c_eh_return_stackadj_rtx (void)
1027 if (!cfun
->machine
->eh_stack_adjust
)
1031 sa
= gen_rtx_REG (Pmode
, R0_REGNO
);
1032 cfun
->machine
->eh_stack_adjust
= sa
;
1034 return cfun
->machine
->eh_stack_adjust
;
1037 /* Registers That Address the Stack Frame */
1039 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1040 the original spec called for dwarf numbers to vary with register
1041 width as well, for example, r0l, r0, and r2r0 would each have
1042 different dwarf numbers. GCC doesn't support this, and we don't do
1043 it, and gdb seems to like it this way anyway. */
1045 m32c_dwarf_frame_regnum (int n
)
1071 return DWARF_FRAME_REGISTERS
+ 1;
1075 /* The frame looks like this:
1077 ap -> +------------------------------
1078 | Return address (3 or 4 bytes)
1079 | Saved FB (2 or 4 bytes)
1080 fb -> +------------------------------
1083 | through r0 as needed
1084 sp -> +------------------------------
1087 /* We use this to wrap all emitted insns in the prologue. */
1091 RTX_FRAME_RELATED_P (x
) = 1;
1095 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1096 how much the stack pointer moves for each, for each cpu family. */
1105 /* These are in reverse push (nearest-to-sp) order. */
1106 { R0_REGNO
, 0x80, 2, 2 },
1107 { R1_REGNO
, 0x40, 2, 2 },
1108 { R2_REGNO
, 0x20, 2, 2 },
1109 { R3_REGNO
, 0x10, 2, 2 },
1110 { A0_REGNO
, 0x08, 2, 4 },
1111 { A1_REGNO
, 0x04, 2, 4 },
1112 { SB_REGNO
, 0x02, 2, 4 },
1113 { FB_REGNO
, 0x01, 2, 4 }
1116 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1118 /* Returns TRUE if we need to save/restore the given register. We
1119 save everything for exception handlers, so that any register can be
1120 unwound. For interrupt handlers, we save everything if the handler
1121 calls something else (because we don't know what *that* function
1122 might do), but try to be a bit smarter if the handler is a leaf
1123 function. We always save $a0, though, because we use that in the
1124 epilogue to copy $fb to $sp. */
1126 need_to_save (int regno
)
1128 if (fixed_regs
[regno
])
1130 if (crtl
->calls_eh_return
)
1132 if (regno
== FP_REGNO
)
1134 if (cfun
->machine
->is_interrupt
1135 && (!cfun
->machine
->is_leaf
1136 || (regno
== A0_REGNO
1137 && m32c_function_needs_enter ())
1140 if (df_regs_ever_live_p (regno
)
1141 && (!call_used_regs
[regno
] || cfun
->machine
->is_interrupt
))
1146 /* This function contains all the intelligence about saving and
1147 restoring registers. It always figures out the register save set.
1148 When called with PP_justcount, it merely returns the size of the
1149 save set (for eliminating the frame pointer, for example). When
1150 called with PP_pushm or PP_popm, it emits the appropriate
1151 instructions for saving (pushm) or restoring (popm) the
1154 m32c_pushm_popm (Push_Pop_Type ppt
)
1157 int byte_count
= 0, bytes
;
1159 rtx dwarf_set
[PUSHM_N
];
1161 int nosave_mask
= 0;
1163 if (crtl
->return_rtx
1164 && GET_CODE (crtl
->return_rtx
) == PARALLEL
1165 && !(crtl
->calls_eh_return
|| cfun
->machine
->is_interrupt
))
1167 rtx exp
= XVECEXP (crtl
->return_rtx
, 0, 0);
1168 rtx rv
= XEXP (exp
, 0);
1169 int rv_bytes
= GET_MODE_SIZE (GET_MODE (rv
));
1172 nosave_mask
|= 0x20; /* PSI, SI */
1174 nosave_mask
|= 0xf0; /* DF */
1176 nosave_mask
|= 0x50; /* DI */
1179 for (i
= 0; i
< (int) PUSHM_N
; i
++)
1181 /* Skip if neither register needs saving. */
1182 if (!need_to_save (pushm_info
[i
].reg1
))
1185 if (pushm_info
[i
].bit
& nosave_mask
)
1188 reg_mask
|= pushm_info
[i
].bit
;
1189 bytes
= TARGET_A16
? pushm_info
[i
].a16_bytes
: pushm_info
[i
].a24_bytes
;
1191 if (ppt
== PP_pushm
)
1193 machine_mode mode
= (bytes
== 2) ? HImode
: SImode
;
1196 /* Always use stack_pointer_rtx instead of calling
1197 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1198 that there is a single rtx representing the stack pointer,
1199 namely stack_pointer_rtx, and uses == to recognize it. */
1200 addr
= stack_pointer_rtx
;
1202 if (byte_count
!= 0)
1203 addr
= gen_rtx_PLUS (GET_MODE (addr
), addr
, GEN_INT (byte_count
));
1205 dwarf_set
[n_dwarfs
++] =
1206 gen_rtx_SET (VOIDmode
,
1207 gen_rtx_MEM (mode
, addr
),
1208 gen_rtx_REG (mode
, pushm_info
[i
].reg1
));
1209 F (dwarf_set
[n_dwarfs
- 1]);
1212 byte_count
+= bytes
;
1215 if (cfun
->machine
->is_interrupt
)
1217 cfun
->machine
->intr_pushm
= reg_mask
& 0xfe;
1222 if (cfun
->machine
->is_interrupt
)
1223 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1224 if (need_to_save (i
))
1227 cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
] = 1;
1230 if (ppt
== PP_pushm
&& byte_count
)
1232 rtx note
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (n_dwarfs
+ 1));
1237 XVECEXP (note
, 0, 0)
1238 = gen_rtx_SET (VOIDmode
,
1240 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx
),
1242 GEN_INT (-byte_count
)));
1243 F (XVECEXP (note
, 0, 0));
1245 for (i
= 0; i
< n_dwarfs
; i
++)
1246 XVECEXP (note
, 0, i
+ 1) = dwarf_set
[i
];
1248 pushm
= F (emit_insn (gen_pushm (GEN_INT (reg_mask
))));
1250 add_reg_note (pushm
, REG_FRAME_RELATED_EXPR
, note
);
1253 if (cfun
->machine
->is_interrupt
)
1254 for (i
= MEM0_REGNO
; i
<= MEM7_REGNO
; i
++)
1255 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1258 pushm
= emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode
, i
)));
1260 pushm
= emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode
, i
)));
1264 if (ppt
== PP_popm
&& byte_count
)
1266 if (cfun
->machine
->is_interrupt
)
1267 for (i
= MEM7_REGNO
; i
>= MEM0_REGNO
; i
--)
1268 if (cfun
->machine
->intr_pushmem
[i
- MEM0_REGNO
])
1271 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, i
)));
1273 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode
, i
)));
1276 emit_insn (gen_popm (GEN_INT (reg_mask
)));
1282 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1283 diagrams our call frame. */
1285 m32c_initial_elimination_offset (int from
, int to
)
1289 if (from
== AP_REGNO
)
1299 ofs
+= m32c_pushm_popm (PP_justcount
);
1300 ofs
+= get_frame_size ();
1303 /* Account for push rounding. */
1305 ofs
= (ofs
+ 1) & ~1;
1307 fprintf (stderr
, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from
,
1313 /* Passing Function Arguments on the Stack */
1315 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1316 M32C has word stacks. */
1318 m32c_push_rounding (int n
)
1320 if (TARGET_R8C
|| TARGET_M16C
)
1322 return (n
+ 1) & ~1;
1325 /* Passing Arguments in Registers */
1327 /* Implements TARGET_FUNCTION_ARG. Arguments are passed partly in
1328 registers, partly on stack. If our function returns a struct, a
1329 pointer to a buffer for it is at the top of the stack (last thing
1330 pushed). The first few real arguments may be in registers as
1333 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1334 arg2 in r2 if it's HI (else pushed on stack)
1336 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1339 Structs are not passed in registers, even if they fit. Only
1340 integer and pointer types are passed in registers.
1342 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1344 #undef TARGET_FUNCTION_ARG
1345 #define TARGET_FUNCTION_ARG m32c_function_arg
1347 m32c_function_arg (cumulative_args_t ca_v
,
1348 machine_mode mode
, const_tree type
, bool named
)
1350 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
1352 /* Can return a reg, parallel, or 0 for stack */
1355 fprintf (stderr
, "func_arg %d (%s, %d)\n",
1356 ca
->parm_num
, mode_name
[mode
], named
);
1360 if (mode
== VOIDmode
)
1363 if (ca
->force_mem
|| !named
)
1366 fprintf (stderr
, "func arg: force %d named %d, mem\n", ca
->force_mem
,
1372 if (type
&& INTEGRAL_TYPE_P (type
) && POINTER_TYPE_P (type
))
1375 if (type
&& AGGREGATE_TYPE_P (type
))
1378 switch (ca
->parm_num
)
1381 if (GET_MODE_SIZE (mode
) == 1 || GET_MODE_SIZE (mode
) == 2)
1382 rv
= gen_rtx_REG (mode
, TARGET_A16
? R1_REGNO
: R0_REGNO
);
1386 if (TARGET_A16
&& GET_MODE_SIZE (mode
) == 2)
1387 rv
= gen_rtx_REG (mode
, R2_REGNO
);
1397 #undef TARGET_PASS_BY_REFERENCE
1398 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1400 m32c_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
1401 machine_mode mode ATTRIBUTE_UNUSED
,
1402 const_tree type ATTRIBUTE_UNUSED
,
1403 bool named ATTRIBUTE_UNUSED
)
1408 /* Implements INIT_CUMULATIVE_ARGS. */
1410 m32c_init_cumulative_args (CUMULATIVE_ARGS
* ca
,
1412 rtx libname ATTRIBUTE_UNUSED
,
1414 int n_named_args ATTRIBUTE_UNUSED
)
1416 if (fntype
&& aggregate_value_p (TREE_TYPE (fntype
), fndecl
))
1423 /* Implements TARGET_FUNCTION_ARG_ADVANCE. force_mem is set for
1424 functions returning structures, so we always reset that. Otherwise,
1425 we only need to know the sequence number of the argument to know what
1427 #undef TARGET_FUNCTION_ARG_ADVANCE
1428 #define TARGET_FUNCTION_ARG_ADVANCE m32c_function_arg_advance
1430 m32c_function_arg_advance (cumulative_args_t ca_v
,
1431 machine_mode mode ATTRIBUTE_UNUSED
,
1432 const_tree type ATTRIBUTE_UNUSED
,
1433 bool named ATTRIBUTE_UNUSED
)
1435 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
1443 /* Implements TARGET_FUNCTION_ARG_BOUNDARY. */
1444 #undef TARGET_FUNCTION_ARG_BOUNDARY
1445 #define TARGET_FUNCTION_ARG_BOUNDARY m32c_function_arg_boundary
1447 m32c_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
1448 const_tree type ATTRIBUTE_UNUSED
)
1450 return (TARGET_A16
? 8 : 16);
1453 /* Implements FUNCTION_ARG_REGNO_P. */
1455 m32c_function_arg_regno_p (int r
)
1458 return (r
== R0_REGNO
);
1459 return (r
== R1_REGNO
|| r
== R2_REGNO
);
1462 /* HImode and PSImode are the two "native" modes as far as GCC is
1463 concerned, but the chips also support a 32-bit mode which is used
1464 for some opcodes in R8C/M16C and for reset vectors and such. */
1465 #undef TARGET_VALID_POINTER_MODE
1466 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1468 m32c_valid_pointer_mode (machine_mode mode
)
1478 /* How Scalar Function Values Are Returned */
1480 /* Implements TARGET_LIBCALL_VALUE. Most values are returned in $r0, or some
1481 combination of registers starting there (r2r0 for longs, r3r1r2r0
1482 for long long, r3r2r1r0 for doubles), except that that ABI
1483 currently doesn't work because it ends up using all available
1484 general registers and gcc often can't compile it. So, instead, we
1485 return anything bigger than 16 bits in "mem0" (effectively, a
1486 memory location). */
1488 #undef TARGET_LIBCALL_VALUE
1489 #define TARGET_LIBCALL_VALUE m32c_libcall_value
1492 m32c_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
1494 /* return reg or parallel */
1496 /* FIXME: GCC has difficulty returning large values in registers,
1497 because that ties up most of the general registers and gives the
1498 register allocator little to work with. Until we can resolve
1499 this, large values are returned in memory. */
1504 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (4));
1505 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1506 gen_rtx_REG (HImode
,
1509 XVECEXP (rv
, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode
,
1510 gen_rtx_REG (HImode
,
1513 XVECEXP (rv
, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode
,
1514 gen_rtx_REG (HImode
,
1517 XVECEXP (rv
, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode
,
1518 gen_rtx_REG (HImode
,
1524 if (TARGET_A24
&& GET_MODE_SIZE (mode
) > 2)
1528 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (1));
1529 XVECEXP (rv
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
,
1537 if (GET_MODE_SIZE (mode
) > 2)
1538 return gen_rtx_REG (mode
, MEM0_REGNO
);
1539 return gen_rtx_REG (mode
, R0_REGNO
);
1542 /* Implements TARGET_FUNCTION_VALUE. Functions and libcalls have the same
1545 #undef TARGET_FUNCTION_VALUE
1546 #define TARGET_FUNCTION_VALUE m32c_function_value
1549 m32c_function_value (const_tree valtype
,
1550 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1551 bool outgoing ATTRIBUTE_UNUSED
)
1553 /* return reg or parallel */
1554 const machine_mode mode
= TYPE_MODE (valtype
);
1555 return m32c_libcall_value (mode
, NULL_RTX
);
1558 /* Implements TARGET_FUNCTION_VALUE_REGNO_P. */
1560 #undef TARGET_FUNCTION_VALUE_REGNO_P
1561 #define TARGET_FUNCTION_VALUE_REGNO_P m32c_function_value_regno_p
1564 m32c_function_value_regno_p (const unsigned int regno
)
1566 return (regno
== R0_REGNO
|| regno
== MEM0_REGNO
);
1569 /* How Large Values Are Returned */
1571 /* We return structures by pushing the address on the stack, even if
1572 we use registers for the first few "real" arguments. */
1573 #undef TARGET_STRUCT_VALUE_RTX
1574 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1576 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
,
1577 int incoming ATTRIBUTE_UNUSED
)
1582 /* Function Entry and Exit */
1584 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1586 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
1588 if (cfun
->machine
->is_interrupt
)
1593 /* Implementing the Varargs Macros */
1595 #undef TARGET_STRICT_ARGUMENT_NAMING
1596 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1598 m32c_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
1603 /* Trampolines for Nested Functions */
1607 1 0000 75C43412 mov.w #0x1234,a0
1608 2 0004 FC000000 jmp.a label
1611 1 0000 BC563412 mov.l:s #0x123456,a0
1612 2 0004 CC000000 jmp.a label
1615 /* Implements TRAMPOLINE_SIZE. */
1617 m32c_trampoline_size (void)
1619 /* Allocate extra space so we can avoid the messy shifts when we
1620 initialize the trampoline; we just write past the end of the
1622 return TARGET_A16
? 8 : 10;
1625 /* Implements TRAMPOLINE_ALIGNMENT. */
1627 m32c_trampoline_alignment (void)
1632 /* Implements TARGET_TRAMPOLINE_INIT. */
1634 #undef TARGET_TRAMPOLINE_INIT
1635 #define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
1637 m32c_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chainval
)
1639 rtx function
= XEXP (DECL_RTL (fndecl
), 0);
1641 #define A0(m,i) adjust_address (m_tramp, m, i)
1644 /* Note: we subtract a "word" because the moves want signed
1645 constants, not unsigned constants. */
1646 emit_move_insn (A0 (HImode
, 0), GEN_INT (0xc475 - 0x10000));
1647 emit_move_insn (A0 (HImode
, 2), chainval
);
1648 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xfc - 0x100));
1649 /* We use 16-bit addresses here, but store the zero to turn it
1650 into a 24-bit offset. */
1651 emit_move_insn (A0 (HImode
, 5), function
);
1652 emit_move_insn (A0 (QImode
, 7), GEN_INT (0x00));
1656 /* Note that the PSI moves actually write 4 bytes. Make sure we
1657 write stuff out in the right order, and leave room for the
1658 extra byte at the end. */
1659 emit_move_insn (A0 (QImode
, 0), GEN_INT (0xbc - 0x100));
1660 emit_move_insn (A0 (PSImode
, 1), chainval
);
1661 emit_move_insn (A0 (QImode
, 4), GEN_INT (0xcc - 0x100));
1662 emit_move_insn (A0 (PSImode
, 5), function
);
1667 /* Addressing Modes */
1669 /* The r8c/m32c family supports a wide range of non-orthogonal
1670 addressing modes, including the ability to double-indirect on *some*
1671 of them. Not all insns support all modes, either, but we rely on
1672 predicates and constraints to deal with that. */
1673 #undef TARGET_LEGITIMATE_ADDRESS_P
1674 #define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
1676 m32c_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1682 if (TARGET_A16
&& GET_MODE (x
) != HImode
&& GET_MODE (x
) != SImode
)
1684 if (TARGET_A24
&& GET_MODE (x
) != PSImode
)
1687 /* Wide references to memory will be split after reload, so we must
1688 ensure that all parts of such splits remain legitimate
1690 mode_adjust
= GET_MODE_SIZE (mode
) - 1;
1692 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1693 if (GET_CODE (x
) == PRE_DEC
1694 || GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_MODIFY
)
1696 return (GET_CODE (XEXP (x
, 0)) == REG
1697 && REGNO (XEXP (x
, 0)) == SP_REGNO
);
1701 /* This is the double indirection detection, but it currently
1702 doesn't work as cleanly as this code implies, so until we've had
1703 a chance to debug it, leave it disabled. */
1704 if (TARGET_A24
&& GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) != PLUS
)
1707 fprintf (stderr
, "double indirect\n");
1716 /* Most indexable registers can be used without displacements,
1717 although some of them will be emitted with an explicit zero
1718 to please the assembler. */
1719 switch (REGNO (patternr
[0]))
1725 if (TARGET_A16
&& GET_MODE (x
) == SImode
)
1731 if (IS_PSEUDO (patternr
[0], strict
))
1737 if (TARGET_A16
&& GET_MODE (x
) == SImode
)
1742 /* This is more interesting, because different base registers
1743 allow for different displacements - both range and signedness
1744 - and it differs from chip series to chip series too. */
1745 int rn
= REGNO (patternr
[1]);
1746 HOST_WIDE_INT offs
= INTVAL (patternr
[2]);
1752 /* The syntax only allows positive offsets, but when the
1753 offsets span the entire memory range, we can simulate
1754 negative offsets by wrapping. */
1756 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1758 return (offs
>= 0 && offs
<= 65535 - mode_adjust
);
1760 return (offs
>= -16777216 && offs
<= 16777215);
1764 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1765 return (offs
>= -65536 && offs
<= 65535 - mode_adjust
);
1768 return (offs
>= -128 && offs
<= 127 - mode_adjust
);
1771 if (IS_PSEUDO (patternr
[1], strict
))
1776 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1778 rtx reg
= patternr
[1];
1780 /* We don't know where the symbol is, so only allow base
1781 registers which support displacements spanning the whole
1783 switch (REGNO (reg
))
1787 /* $sb needs a secondary reload, but since it's involved in
1788 memory address reloads too, we don't deal with it very
1790 /* case SB_REGNO: */
1793 if (GET_CODE (reg
) == SUBREG
)
1795 if (IS_PSEUDO (reg
, strict
))
1803 /* Implements REG_OK_FOR_BASE_P. */
1805 m32c_reg_ok_for_base_p (rtx x
, int strict
)
1807 if (GET_CODE (x
) != REG
)
1818 if (IS_PSEUDO (x
, strict
))
1824 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1825 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1827 EB 4B FF mova -128[$fb],$a0
1828 D8 0C FF FF mov.w:Q #0,-1[$a0]
1830 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1833 77 54 00 01 sub #256,$a0
1834 D8 08 01 mov.w:Q #0,1[$a0]
1836 If we don't offset (i.e. offset by zero), we end up with:
1838 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1840 We have to subtract *something* so that we have a PLUS rtx to mark
1841 that we've done this reload. The -128 offset will never result in
1842 an 8-bit aN offset, and the payoff for the second case is five
1843 loads *if* those loads are within 256 bytes of the other end of the
1844 frame, so the third case seems best. Note that we subtract the
1845 zero, but detect that in the addhi3 pattern. */
1847 #define BIG_FB_ADJ 0
1849 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1850 worry about is frame base offsets, as $fb has a limited
1851 displacement range. We deal with this by attempting to reload $fb
1852 itself into an address register; that seems to result in the best
1854 #undef TARGET_LEGITIMIZE_ADDRESS
1855 #define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
1857 m32c_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1861 fprintf (stderr
, "m32c_legitimize_address for mode %s\n", mode_name
[mode
]);
1863 fprintf (stderr
, "\n");
1866 if (GET_CODE (x
) == PLUS
1867 && GET_CODE (XEXP (x
, 0)) == REG
1868 && REGNO (XEXP (x
, 0)) == FB_REGNO
1869 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1870 && (INTVAL (XEXP (x
, 1)) < -128
1871 || INTVAL (XEXP (x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1873 /* reload FB to A_REGS */
1874 rtx temp
= gen_reg_rtx (Pmode
);
1876 emit_insn (gen_rtx_SET (VOIDmode
, temp
, XEXP (x
, 0)));
1883 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1885 m32c_legitimize_reload_address (rtx
* x
,
1888 int type
, int ind_levels ATTRIBUTE_UNUSED
)
1891 fprintf (stderr
, "\nm32c_legitimize_reload_address for mode %s\n",
1896 /* At one point, this function tried to get $fb copied to an address
1897 register, which in theory would maximize sharing, but gcc was
1898 *also* still trying to reload the whole address, and we'd run out
1899 of address registers. So we let gcc do the naive (but safe)
1900 reload instead, when the above function doesn't handle it for
1903 The code below is a second attempt at the above. */
1905 if (GET_CODE (*x
) == PLUS
1906 && GET_CODE (XEXP (*x
, 0)) == REG
1907 && REGNO (XEXP (*x
, 0)) == FB_REGNO
1908 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1909 && (INTVAL (XEXP (*x
, 1)) < -128
1910 || INTVAL (XEXP (*x
, 1)) > (128 - GET_MODE_SIZE (mode
))))
1913 int offset
= INTVAL (XEXP (*x
, 1));
1914 int adjustment
= -BIG_FB_ADJ
;
1916 sum
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0),
1917 GEN_INT (adjustment
));
1918 *x
= gen_rtx_PLUS (Pmode
, sum
, GEN_INT (offset
- adjustment
));
1919 if (type
== RELOAD_OTHER
)
1920 type
= RELOAD_FOR_OTHER_ADDRESS
;
1921 push_reload (sum
, NULL_RTX
, &XEXP (*x
, 0), NULL
,
1922 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
1923 (enum reload_type
) type
);
1927 if (GET_CODE (*x
) == PLUS
1928 && GET_CODE (XEXP (*x
, 0)) == PLUS
1929 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1930 && REGNO (XEXP (XEXP (*x
, 0), 0)) == FB_REGNO
1931 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1932 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
1935 if (type
== RELOAD_OTHER
)
1936 type
= RELOAD_FOR_OTHER_ADDRESS
;
1937 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1938 A_REGS
, Pmode
, VOIDmode
, 0, 0, opnum
,
1939 (enum reload_type
) type
);
1946 /* Return the appropriate mode for a named address pointer. */
1947 #undef TARGET_ADDR_SPACE_POINTER_MODE
1948 #define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode
1950 m32c_addr_space_pointer_mode (addr_space_t addrspace
)
1954 case ADDR_SPACE_GENERIC
:
1955 return TARGET_A24
? PSImode
: HImode
;
1956 case ADDR_SPACE_FAR
:
1963 /* Return the appropriate mode for a named address address. */
1964 #undef TARGET_ADDR_SPACE_ADDRESS_MODE
1965 #define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode
1967 m32c_addr_space_address_mode (addr_space_t addrspace
)
1971 case ADDR_SPACE_GENERIC
:
1972 return TARGET_A24
? PSImode
: HImode
;
1973 case ADDR_SPACE_FAR
:
1980 /* Like m32c_legitimate_address_p, except with named addresses. */
1981 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
1982 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
1983 m32c_addr_space_legitimate_address_p
1985 m32c_addr_space_legitimate_address_p (machine_mode mode
, rtx x
,
1986 bool strict
, addr_space_t as
)
1988 if (as
== ADDR_SPACE_FAR
)
1995 if (GET_MODE (x
) != SImode
)
1997 switch (REGNO (patternr
[0]))
2003 if (IS_PSEUDO (patternr
[0], strict
))
2008 if (RTX_IS ("+^Sri"))
2010 int rn
= REGNO (patternr
[3]);
2011 HOST_WIDE_INT offs
= INTVAL (patternr
[4]);
2012 if (GET_MODE (patternr
[3]) != HImode
)
2017 return (offs
>= 0 && offs
<= 0xfffff);
2020 if (IS_PSEUDO (patternr
[3], strict
))
2025 if (RTX_IS ("+^Srs"))
2027 int rn
= REGNO (patternr
[3]);
2028 if (GET_MODE (patternr
[3]) != HImode
)
2036 if (IS_PSEUDO (patternr
[3], strict
))
2041 if (RTX_IS ("+^S+ris"))
2043 int rn
= REGNO (patternr
[4]);
2044 if (GET_MODE (patternr
[4]) != HImode
)
2052 if (IS_PSEUDO (patternr
[4], strict
))
2064 else if (as
!= ADDR_SPACE_GENERIC
)
2067 return m32c_legitimate_address_p (mode
, x
, strict
);
2070 /* Like m32c_legitimate_address, except with named address support. */
2071 #undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
2072 #define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address
2074 m32c_addr_space_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
,
2077 if (as
!= ADDR_SPACE_GENERIC
)
2080 fprintf (stderr
, "\033[36mm32c_addr_space_legitimize_address for mode %s\033[0m\n", mode_name
[mode
]);
2082 fprintf (stderr
, "\n");
2085 if (GET_CODE (x
) != REG
)
2087 x
= force_reg (SImode
, x
);
2092 return m32c_legitimize_address (x
, oldx
, mode
);
2095 /* Determine if one named address space is a subset of another. */
2096 #undef TARGET_ADDR_SPACE_SUBSET_P
2097 #define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p
2099 m32c_addr_space_subset_p (addr_space_t subset
, addr_space_t superset
)
2101 gcc_assert (subset
== ADDR_SPACE_GENERIC
|| subset
== ADDR_SPACE_FAR
);
2102 gcc_assert (superset
== ADDR_SPACE_GENERIC
|| superset
== ADDR_SPACE_FAR
);
2104 if (subset
== superset
)
2108 return (subset
== ADDR_SPACE_GENERIC
&& superset
== ADDR_SPACE_FAR
);
2111 #undef TARGET_ADDR_SPACE_CONVERT
2112 #define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert
2113 /* Convert from one address space to another. */
2115 m32c_addr_space_convert (rtx op
, tree from_type
, tree to_type
)
2117 addr_space_t from_as
= TYPE_ADDR_SPACE (TREE_TYPE (from_type
));
2118 addr_space_t to_as
= TYPE_ADDR_SPACE (TREE_TYPE (to_type
));
2121 gcc_assert (from_as
== ADDR_SPACE_GENERIC
|| from_as
== ADDR_SPACE_FAR
);
2122 gcc_assert (to_as
== ADDR_SPACE_GENERIC
|| to_as
== ADDR_SPACE_FAR
);
2124 if (to_as
== ADDR_SPACE_GENERIC
&& from_as
== ADDR_SPACE_FAR
)
2126 /* This is unpredictable, as we're truncating off usable address
2129 result
= gen_reg_rtx (HImode
);
2130 emit_move_insn (result
, simplify_subreg (HImode
, op
, SImode
, 0));
2133 else if (to_as
== ADDR_SPACE_FAR
&& from_as
== ADDR_SPACE_GENERIC
)
2135 /* This always works. */
2136 result
= gen_reg_rtx (SImode
);
2137 emit_insn (gen_zero_extendhisi2 (result
, op
));
2144 /* Condition Code Status */
2146 #undef TARGET_FIXED_CONDITION_CODE_REGS
2147 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2149 m32c_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
2152 *p2
= INVALID_REGNUM
;
2156 /* Describing Relative Costs of Operations */
2158 /* Implements TARGET_REGISTER_MOVE_COST. We make impossible moves
2159 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2160 no opcodes to do that). We also discourage use of mem* registers
2161 since they're really memory. */
2163 #undef TARGET_REGISTER_MOVE_COST
2164 #define TARGET_REGISTER_MOVE_COST m32c_register_move_cost
2167 m32c_register_move_cost (machine_mode mode
, reg_class_t from
,
2170 int cost
= COSTS_N_INSNS (3);
2173 /* FIXME: pick real values, but not 2 for now. */
2174 COPY_HARD_REG_SET (cc
, reg_class_contents
[(int) from
]);
2175 IOR_HARD_REG_SET (cc
, reg_class_contents
[(int) to
]);
2178 && hard_reg_set_intersect_p (cc
, reg_class_contents
[R23_REGS
]))
2180 if (hard_reg_set_subset_p (cc
, reg_class_contents
[R23_REGS
]))
2181 cost
= COSTS_N_INSNS (1000);
2183 cost
= COSTS_N_INSNS (80);
2186 if (!class_can_hold_mode (from
, mode
) || !class_can_hold_mode (to
, mode
))
2187 cost
= COSTS_N_INSNS (1000);
2189 if (reg_classes_intersect_p (from
, CR_REGS
))
2190 cost
+= COSTS_N_INSNS (5);
2192 if (reg_classes_intersect_p (to
, CR_REGS
))
2193 cost
+= COSTS_N_INSNS (5);
2195 if (from
== MEM_REGS
|| to
== MEM_REGS
)
2196 cost
+= COSTS_N_INSNS (50);
2197 else if (reg_classes_intersect_p (from
, MEM_REGS
)
2198 || reg_classes_intersect_p (to
, MEM_REGS
))
2199 cost
+= COSTS_N_INSNS (10);
2202 fprintf (stderr
, "register_move_cost %s from %s to %s = %d\n",
2203 mode_name
[mode
], class_names
[(int) from
], class_names
[(int) to
],
2209 /* Implements TARGET_MEMORY_MOVE_COST. */
2211 #undef TARGET_MEMORY_MOVE_COST
2212 #define TARGET_MEMORY_MOVE_COST m32c_memory_move_cost
2215 m32c_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2216 reg_class_t rclass ATTRIBUTE_UNUSED
,
2217 bool in ATTRIBUTE_UNUSED
)
2219 /* FIXME: pick real values. */
2220 return COSTS_N_INSNS (10);
2223 /* Here we try to describe when we use multiple opcodes for one RTX so
2224 that gcc knows when to use them. */
2225 #undef TARGET_RTX_COSTS
2226 #define TARGET_RTX_COSTS m32c_rtx_costs
2228 m32c_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2229 int *total
, bool speed ATTRIBUTE_UNUSED
)
2234 if (REGNO (x
) >= MEM0_REGNO
&& REGNO (x
) <= MEM7_REGNO
)
2235 *total
+= COSTS_N_INSNS (500);
2237 *total
+= COSTS_N_INSNS (1);
2243 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2245 /* mov.b r1l, r1h */
2246 *total
+= COSTS_N_INSNS (1);
2249 if (INTVAL (XEXP (x
, 1)) > 8
2250 || INTVAL (XEXP (x
, 1)) < -8)
2253 /* mov.b r1l, r1h */
2254 *total
+= COSTS_N_INSNS (2);
2269 if (outer_code
== SET
)
2271 *total
+= COSTS_N_INSNS (2);
2278 rtx dest
= XEXP (x
, 0);
2279 rtx addr
= XEXP (dest
, 0);
2280 switch (GET_CODE (addr
))
2283 *total
+= COSTS_N_INSNS (1);
2286 *total
+= COSTS_N_INSNS (3);
2289 *total
+= COSTS_N_INSNS (2);
2297 /* Reasonable default. */
2298 if (TARGET_A16
&& GET_MODE(x
) == SImode
)
2299 *total
+= COSTS_N_INSNS (2);
2305 #undef TARGET_ADDRESS_COST
2306 #define TARGET_ADDRESS_COST m32c_address_cost
2308 m32c_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
2309 addr_space_t as ATTRIBUTE_UNUSED
,
2310 bool speed ATTRIBUTE_UNUSED
)
2313 /* fprintf(stderr, "\naddress_cost\n");
2315 switch (GET_CODE (addr
))
2320 return COSTS_N_INSNS(1);
2321 if (0 < i
&& i
<= 255)
2322 return COSTS_N_INSNS(2);
2323 if (0 < i
&& i
<= 65535)
2324 return COSTS_N_INSNS(3);
2325 return COSTS_N_INSNS(4);
2327 return COSTS_N_INSNS(4);
2329 return COSTS_N_INSNS(1);
2331 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
2333 i
= INTVAL (XEXP (addr
, 1));
2335 return COSTS_N_INSNS(1);
2336 if (0 < i
&& i
<= 255)
2337 return COSTS_N_INSNS(2);
2338 if (0 < i
&& i
<= 65535)
2339 return COSTS_N_INSNS(3);
2341 return COSTS_N_INSNS(4);
2347 /* Defining the Output Assembler Language */
2349 /* Output of Data */
2351 /* We may have 24 bit sizes, which is the native address size.
2352 Currently unused, but provided for completeness. */
2353 #undef TARGET_ASM_INTEGER
2354 #define TARGET_ASM_INTEGER m32c_asm_integer
2356 m32c_asm_integer (rtx x
, unsigned int size
, int aligned_p
)
2361 fprintf (asm_out_file
, "\t.3byte\t");
2362 output_addr_const (asm_out_file
, x
);
2363 fputc ('\n', asm_out_file
);
2366 if (GET_CODE (x
) == SYMBOL_REF
)
2368 fprintf (asm_out_file
, "\t.long\t");
2369 output_addr_const (asm_out_file
, x
);
2370 fputc ('\n', asm_out_file
);
2375 return default_assemble_integer (x
, size
, aligned_p
);
2378 /* Output of Assembler Instructions */
2380 /* We use a lookup table because the addressing modes are non-orthogonal. */
2385 char const *pattern
;
2388 const conversions
[] = {
2391 { 0, "mr", "z[1]" },
2392 { 0, "m+ri", "3[2]" },
2393 { 0, "m+rs", "3[2]" },
2394 { 0, "m+^Zrs", "5[4]" },
2395 { 0, "m+^Zri", "5[4]" },
2396 { 0, "m+^Z+ris", "7+6[5]" },
2397 { 0, "m+^Srs", "5[4]" },
2398 { 0, "m+^Sri", "5[4]" },
2399 { 0, "m+^S+ris", "7+6[5]" },
2400 { 0, "m+r+si", "4+5[2]" },
2403 { 0, "m+si", "2+3" },
2405 { 0, "mmr", "[z[2]]" },
2406 { 0, "mm+ri", "[4[3]]" },
2407 { 0, "mm+rs", "[4[3]]" },
2408 { 0, "mm+r+si", "[5+6[3]]" },
2409 { 0, "mms", "[[2]]" },
2410 { 0, "mmi", "[[2]]" },
2411 { 0, "mm+si", "[4[3]]" },
2415 { 0, "+si", "#1+2" },
2421 { 'd', "+si", "1+2" },
2424 { 'D', "+si", "1+2" },
2435 /* This is in order according to the bitfield that pushm/popm use. */
2436 static char const *pushm_regs
[] = {
2437 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2440 /* Implements TARGET_PRINT_OPERAND. */
2442 #undef TARGET_PRINT_OPERAND
2443 #define TARGET_PRINT_OPERAND m32c_print_operand
2446 m32c_print_operand (FILE * file
, rtx x
, int code
)
2451 int unsigned_const
= 0;
2454 /* Multiplies; constants are converted to sign-extended format but
2455 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2467 /* This one is only for debugging; you can put it in a pattern to
2468 force this error. */
2471 fprintf (stderr
, "dj: unreviewed pattern:");
2472 if (current_output_insn
)
2473 debug_rtx (current_output_insn
);
2476 /* PSImode operations are either .w or .l depending on the target. */
2480 fprintf (file
, "w");
2482 fprintf (file
, "l");
2485 /* Inverted conditionals. */
2488 switch (GET_CODE (x
))
2494 fputs ("gtu", file
);
2500 fputs ("geu", file
);
2506 fputs ("leu", file
);
2512 fputs ("ltu", file
);
2525 /* Regular conditionals. */
2528 switch (GET_CODE (x
))
2534 fputs ("leu", file
);
2540 fputs ("ltu", file
);
2546 fputs ("gtu", file
);
2552 fputs ("geu", file
);
2565 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2567 if (code
== 'h' && GET_MODE (x
) == SImode
)
2569 x
= m32c_subreg (HImode
, x
, SImode
, 0);
2572 if (code
== 'H' && GET_MODE (x
) == SImode
)
2574 x
= m32c_subreg (HImode
, x
, SImode
, 2);
2577 if (code
== 'h' && GET_MODE (x
) == HImode
)
2579 x
= m32c_subreg (QImode
, x
, HImode
, 0);
2582 if (code
== 'H' && GET_MODE (x
) == HImode
)
2584 /* We can't actually represent this as an rtx. Do it here. */
2585 if (GET_CODE (x
) == REG
)
2590 fputs ("r0h", file
);
2593 fputs ("r1h", file
);
2599 /* This should be a MEM. */
2600 x
= m32c_subreg (QImode
, x
, HImode
, 1);
2603 /* This is for BMcond, which always wants word register names. */
2604 if (code
== 'h' && GET_MODE (x
) == QImode
)
2606 if (GET_CODE (x
) == REG
)
2607 x
= gen_rtx_REG (HImode
, REGNO (x
));
2610 /* 'x' and 'X' need to be ignored for non-immediates. */
2611 if ((code
== 'x' || code
== 'X') && GET_CODE (x
) != CONST_INT
)
2616 for (i
= 0; conversions
[i
].pattern
; i
++)
2617 if (conversions
[i
].code
== code
2618 && streq (conversions
[i
].pattern
, pattern
))
2620 for (j
= 0; conversions
[i
].format
[j
]; j
++)
2621 /* backslash quotes the next character in the output pattern. */
2622 if (conversions
[i
].format
[j
] == '\\')
2624 fputc (conversions
[i
].format
[j
+ 1], file
);
2627 /* Digits in the output pattern indicate that the
2628 corresponding RTX is to be output at that point. */
2629 else if (ISDIGIT (conversions
[i
].format
[j
]))
2631 rtx r
= patternr
[conversions
[i
].format
[j
] - '0'];
2632 switch (GET_CODE (r
))
2635 fprintf (file
, "%s",
2636 reg_name_with_mode (REGNO (r
), GET_MODE (r
)));
2645 int i
= (int) exact_log2 (v
);
2647 i
= (int) exact_log2 ((v
^ 0xffff) & 0xffff);
2649 i
= (int) exact_log2 ((v
^ 0xff) & 0xff);
2651 fprintf (file
, "%d", i
);
2655 /* Unsigned byte. */
2656 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2660 /* Unsigned word. */
2661 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2662 INTVAL (r
) & 0xffff);
2665 /* pushm and popm encode a register set into a single byte. */
2667 for (b
= 7; b
>= 0; b
--)
2668 if (INTVAL (r
) & (1 << b
))
2670 fprintf (file
, "%s%s", comma
, pushm_regs
[b
]);
2675 /* "Minus". Output -X */
2676 ival
= (-INTVAL (r
) & 0xffff);
2678 ival
= ival
- 0x10000;
2679 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2683 if (conversions
[i
].format
[j
+ 1] == '[' && ival
< 0)
2685 /* We can simulate negative displacements by
2686 taking advantage of address space
2687 wrapping when the offset can span the
2688 entire address range. */
2690 patternr
[conversions
[i
].format
[j
+ 2] - '0'];
2691 if (GET_CODE (base
) == REG
)
2692 switch (REGNO (base
))
2697 ival
= 0x1000000 + ival
;
2699 ival
= 0x10000 + ival
;
2703 ival
= 0x10000 + ival
;
2707 else if (code
== 'd' && ival
< 0 && j
== 0)
2708 /* The "mova" opcode is used to do addition by
2709 computing displacements, but again, we need
2710 displacements to be unsigned *if* they're
2711 the only component of the displacement
2712 (i.e. no "symbol-4" type displacement). */
2713 ival
= (TARGET_A24
? 0x1000000 : 0x10000) + ival
;
2715 if (conversions
[i
].format
[j
] == '0')
2717 /* More conversions to unsigned. */
2718 if (unsigned_const
== 2)
2720 if (unsigned_const
== 1)
2723 if (streq (conversions
[i
].pattern
, "mi")
2724 || streq (conversions
[i
].pattern
, "mmi"))
2726 /* Integers used as addresses are unsigned. */
2727 ival
&= (TARGET_A24
? 0xffffff : 0xffff);
2729 if (force_sign
&& ival
>= 0)
2731 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
2736 /* We don't have const_double constants. If it
2737 happens, make it obvious. */
2738 fprintf (file
, "[const_double 0x%lx]",
2739 (unsigned long) CONST_DOUBLE_HIGH (r
));
2742 assemble_name (file
, XSTR (r
, 0));
2745 output_asm_label (r
);
2748 fprintf (stderr
, "don't know how to print this operand:");
2755 if (conversions
[i
].format
[j
] == 'z')
2757 /* Some addressing modes *must* have a displacement,
2758 so insert a zero here if needed. */
2760 for (k
= j
+ 1; conversions
[i
].format
[k
]; k
++)
2761 if (ISDIGIT (conversions
[i
].format
[k
]))
2763 rtx reg
= patternr
[conversions
[i
].format
[k
] - '0'];
2764 if (GET_CODE (reg
) == REG
2765 && (REGNO (reg
) == SB_REGNO
2766 || REGNO (reg
) == FB_REGNO
2767 || REGNO (reg
) == SP_REGNO
))
2772 /* Signed displacements off symbols need to have signs
2774 if (conversions
[i
].format
[j
] == '+'
2775 && (!code
|| code
== 'D' || code
== 'd')
2776 && ISDIGIT (conversions
[i
].format
[j
+ 1])
2777 && (GET_CODE (patternr
[conversions
[i
].format
[j
+ 1] - '0'])
2783 fputc (conversions
[i
].format
[j
], file
);
2787 if (!conversions
[i
].pattern
)
2789 fprintf (stderr
, "unconvertible operand %c `%s'", code
? code
: '-',
2792 fprintf (file
, "[%c.%s]", code
? code
: '-', pattern
);
2798 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P.
2800 See m32c_print_operand above for descriptions of what these do. */
2802 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
2803 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32c_print_operand_punct_valid_p
2806 m32c_print_operand_punct_valid_p (unsigned char c
)
2808 if (c
== '&' || c
== '!')
2814 /* Implements TARGET_PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2816 #undef TARGET_PRINT_OPERAND_ADDRESS
2817 #define TARGET_PRINT_OPERAND_ADDRESS m32c_print_operand_address
2820 m32c_print_operand_address (FILE * stream
, rtx address
)
2822 if (GET_CODE (address
) == MEM
)
2823 address
= XEXP (address
, 0);
2825 /* cf: gcc.dg/asm-4.c. */
2826 gcc_assert (GET_CODE (address
) == REG
);
2828 m32c_print_operand (stream
, address
, 0);
2831 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2832 differently than general registers. */
2834 m32c_output_reg_push (FILE * s
, int regno
)
2836 if (regno
== FLG_REGNO
)
2837 fprintf (s
, "\tpushc\tflg\n");
2839 fprintf (s
, "\tpush.%c\t%s\n",
2840 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2843 /* Likewise for ASM_OUTPUT_REG_POP. */
2845 m32c_output_reg_pop (FILE * s
, int regno
)
2847 if (regno
== FLG_REGNO
)
2848 fprintf (s
, "\tpopc\tflg\n");
2850 fprintf (s
, "\tpop.%c\t%s\n",
2851 " bwll"[reg_push_size (regno
)], reg_names
[regno
]);
2854 /* Defining target-specific uses of `__attribute__' */
2856 /* Used to simplify the logic below. Find the attributes wherever
2858 #define M32C_ATTRIBUTES(decl) \
2859 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2860 : DECL_ATTRIBUTES (decl) \
2861 ? (DECL_ATTRIBUTES (decl)) \
2862 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2864 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2866 interrupt_p (tree node ATTRIBUTE_UNUSED
)
2868 tree list
= M32C_ATTRIBUTES (node
);
2871 if (is_attribute_p ("interrupt", TREE_PURPOSE (list
)))
2873 list
= TREE_CHAIN (list
);
2875 return fast_interrupt_p (node
);
2878 /* Returns TRUE if the given tree has the "bank_switch" attribute. */
2880 bank_switch_p (tree node ATTRIBUTE_UNUSED
)
2882 tree list
= M32C_ATTRIBUTES (node
);
2885 if (is_attribute_p ("bank_switch", TREE_PURPOSE (list
)))
2887 list
= TREE_CHAIN (list
);
2892 /* Returns TRUE if the given tree has the "fast_interrupt" attribute. */
2894 fast_interrupt_p (tree node ATTRIBUTE_UNUSED
)
2896 tree list
= M32C_ATTRIBUTES (node
);
2899 if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list
)))
2901 list
= TREE_CHAIN (list
);
2907 interrupt_handler (tree
* node ATTRIBUTE_UNUSED
,
2908 tree name ATTRIBUTE_UNUSED
,
2909 tree args ATTRIBUTE_UNUSED
,
2910 int flags ATTRIBUTE_UNUSED
,
2911 bool * no_add_attrs ATTRIBUTE_UNUSED
)
2916 /* Returns TRUE if given tree has the "function_vector" attribute. */
2918 m32c_special_page_vector_p (tree func
)
2922 if (TREE_CODE (func
) != FUNCTION_DECL
)
2925 list
= M32C_ATTRIBUTES (func
);
2928 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
2930 list
= TREE_CHAIN (list
);
2936 function_vector_handler (tree
* node ATTRIBUTE_UNUSED
,
2937 tree name ATTRIBUTE_UNUSED
,
2938 tree args ATTRIBUTE_UNUSED
,
2939 int flags ATTRIBUTE_UNUSED
,
2940 bool * no_add_attrs ATTRIBUTE_UNUSED
)
2944 /* The attribute is not supported for R8C target. */
2945 warning (OPT_Wattributes
,
2946 "%qE attribute is not supported for R8C target",
2948 *no_add_attrs
= true;
2950 else if (TREE_CODE (*node
) != FUNCTION_DECL
)
2952 /* The attribute must be applied to functions only. */
2953 warning (OPT_Wattributes
,
2954 "%qE attribute applies only to functions",
2956 *no_add_attrs
= true;
2958 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
2960 /* The argument must be a constant integer. */
2961 warning (OPT_Wattributes
,
2962 "%qE attribute argument not an integer constant",
2964 *no_add_attrs
= true;
2966 else if (TREE_INT_CST_LOW (TREE_VALUE (args
)) < 18
2967 || TREE_INT_CST_LOW (TREE_VALUE (args
)) > 255)
2969 /* The argument value must be between 18 to 255. */
2970 warning (OPT_Wattributes
,
2971 "%qE attribute argument should be between 18 to 255",
2973 *no_add_attrs
= true;
2978 /* If the function is assigned the attribute 'function_vector', it
2979 returns the function vector number, otherwise returns zero. */
2981 current_function_special_page_vector (rtx x
)
2985 if ((GET_CODE(x
) == SYMBOL_REF
)
2986 && (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
2989 tree t
= SYMBOL_REF_DECL (x
);
2991 if (TREE_CODE (t
) != FUNCTION_DECL
)
2994 list
= M32C_ATTRIBUTES (t
);
2997 if (is_attribute_p ("function_vector", TREE_PURPOSE (list
)))
2999 num
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list
)));
3003 list
= TREE_CHAIN (list
);
3012 #undef TARGET_ATTRIBUTE_TABLE
3013 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
3014 static const struct attribute_spec m32c_attribute_table
[] = {
3015 {"interrupt", 0, 0, false, false, false, interrupt_handler
, false},
3016 {"bank_switch", 0, 0, false, false, false, interrupt_handler
, false},
3017 {"fast_interrupt", 0, 0, false, false, false, interrupt_handler
, false},
3018 {"function_vector", 1, 1, true, false, false, function_vector_handler
,
3020 {0, 0, 0, 0, 0, 0, 0, false}
3023 #undef TARGET_COMP_TYPE_ATTRIBUTES
3024 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
3026 m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED
,
3027 const_tree type2 ATTRIBUTE_UNUSED
)
3029 /* 0=incompatible 1=compatible 2=warning */
3033 #undef TARGET_INSERT_ATTRIBUTES
3034 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
3036 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED
,
3037 tree
* attr_ptr ATTRIBUTE_UNUSED
)
3040 /* See if we need to make #pragma address variables volatile. */
3042 if (TREE_CODE (node
) == VAR_DECL
)
3044 const char *name
= IDENTIFIER_POINTER (DECL_NAME (node
));
3045 if (m32c_get_pragma_address (name
, &addr
))
3047 TREE_THIS_VOLATILE (node
) = true;
3053 struct pragma_traits
: default_hashmap_traits
3055 static hashval_t
hash (const char *str
) { return htab_hash_string (str
); }
3057 equal_keys (const char *a
, const char *b
)
3059 return !strcmp (a
, b
);
3063 /* Hash table of pragma info. */
3064 static GTY(()) hash_map
<const char *, unsigned, pragma_traits
> *pragma_htab
;
3067 m32c_note_pragma_address (const char *varname
, unsigned address
)
3071 = hash_map
<const char *, unsigned, pragma_traits
>::create_ggc (31);
3073 const char *name
= ggc_strdup (varname
);
3074 unsigned int *slot
= &pragma_htab
->get_or_insert (name
);
3079 m32c_get_pragma_address (const char *varname
, unsigned *address
)
3084 unsigned int *slot
= pragma_htab
->get (varname
);
3094 m32c_output_aligned_common (FILE *stream
, tree decl ATTRIBUTE_UNUSED
,
3096 int size
, int align
, int global
)
3100 if (m32c_get_pragma_address (name
, &address
))
3102 /* We never output these as global. */
3103 assemble_name (stream
, name
);
3104 fprintf (stream
, " = 0x%04x\n", address
);
3109 fprintf (stream
, "\t.local\t");
3110 assemble_name (stream
, name
);
3111 fprintf (stream
, "\n");
3113 fprintf (stream
, "\t.comm\t");
3114 assemble_name (stream
, name
);
3115 fprintf (stream
, ",%u,%u\n", size
, align
/ BITS_PER_UNIT
);
3120 /* This is a list of legal subregs of hard regs. */
3121 static const struct {
3122 unsigned char outer_mode_size
;
3123 unsigned char inner_mode_size
;
3124 unsigned char byte_mask
;
3125 unsigned char legal_when
;
3127 } legal_subregs
[] = {
3128 {1, 2, 0x03, 1, R0_REGNO
}, /* r0h r0l */
3129 {1, 2, 0x03, 1, R1_REGNO
}, /* r1h r1l */
3130 {1, 2, 0x01, 1, A0_REGNO
},
3131 {1, 2, 0x01, 1, A1_REGNO
},
3133 {1, 4, 0x01, 1, A0_REGNO
},
3134 {1, 4, 0x01, 1, A1_REGNO
},
3136 {2, 4, 0x05, 1, R0_REGNO
}, /* r2 r0 */
3137 {2, 4, 0x05, 1, R1_REGNO
}, /* r3 r1 */
3138 {2, 4, 0x05, 16, A0_REGNO
}, /* a1 a0 */
3139 {2, 4, 0x01, 24, A0_REGNO
}, /* a1 a0 */
3140 {2, 4, 0x01, 24, A1_REGNO
}, /* a1 a0 */
3142 {4, 8, 0x55, 1, R0_REGNO
}, /* r3 r1 r2 r0 */
3145 /* Returns TRUE if OP is a subreg of a hard reg which we don't
3146 support. We also bail on MEMs with illegal addresses. */
3148 m32c_illegal_subreg_p (rtx op
)
3152 machine_mode src_mode
, dest_mode
;
3154 if (GET_CODE (op
) == MEM
3155 && ! m32c_legitimate_address_p (Pmode
, XEXP (op
, 0), false))
3160 if (GET_CODE (op
) != SUBREG
)
3163 dest_mode
= GET_MODE (op
);
3164 offset
= SUBREG_BYTE (op
);
3165 op
= SUBREG_REG (op
);
3166 src_mode
= GET_MODE (op
);
3168 if (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (src_mode
))
3170 if (GET_CODE (op
) != REG
)
3172 if (REGNO (op
) >= MEM0_REGNO
)
3175 offset
= (1 << offset
);
3177 for (i
= 0; i
< ARRAY_SIZE (legal_subregs
); i
++)
3178 if (legal_subregs
[i
].outer_mode_size
== GET_MODE_SIZE (dest_mode
)
3179 && legal_subregs
[i
].regno
== REGNO (op
)
3180 && legal_subregs
[i
].inner_mode_size
== GET_MODE_SIZE (src_mode
)
3181 && legal_subregs
[i
].byte_mask
& offset
)
3183 switch (legal_subregs
[i
].legal_when
)
3200 /* Returns TRUE if we support a move between the first two operands.
3201 At the moment, we just want to discourage mem to mem moves until
3202 after reload, because reload has a hard time with our limited
3203 number of address registers, and we can get into a situation where
3204 we need three of them when we only have two. */
3206 m32c_mov_ok (rtx
* operands
, machine_mode mode ATTRIBUTE_UNUSED
)
3208 rtx op0
= operands
[0];
3209 rtx op1
= operands
[1];
3214 #define DEBUG_MOV_OK 0
3216 fprintf (stderr
, "m32c_mov_ok %s\n", mode_name
[mode
]);
3221 if (GET_CODE (op0
) == SUBREG
)
3222 op0
= XEXP (op0
, 0);
3223 if (GET_CODE (op1
) == SUBREG
)
3224 op1
= XEXP (op1
, 0);
3226 if (GET_CODE (op0
) == MEM
3227 && GET_CODE (op1
) == MEM
3228 && ! reload_completed
)
3231 fprintf (stderr
, " - no, mem to mem\n");
3237 fprintf (stderr
, " - ok\n");
3242 /* Returns TRUE if two consecutive HImode mov instructions, generated
3243 for moving an immediate double data to a double data type variable
3244 location, can be combined into single SImode mov instruction. */
3246 m32c_immd_dbl_mov (rtx
* operands ATTRIBUTE_UNUSED
,
3247 machine_mode mode ATTRIBUTE_UNUSED
)
3249 /* ??? This relied on the now-defunct MEM_SCALAR and MEM_IN_STRUCT_P
3256 /* Subregs are non-orthogonal for us, because our registers are all
3259 m32c_subreg (machine_mode outer
,
3260 rtx x
, machine_mode inner
, int byte
)
3264 /* Converting MEMs to different types that are the same size, we
3265 just rewrite them. */
3266 if (GET_CODE (x
) == SUBREG
3267 && SUBREG_BYTE (x
) == 0
3268 && GET_CODE (SUBREG_REG (x
)) == MEM
3269 && (GET_MODE_SIZE (GET_MODE (x
))
3270 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3273 x
= gen_rtx_MEM (GET_MODE (x
), XEXP (SUBREG_REG (x
), 0));
3274 MEM_COPY_ATTRIBUTES (x
, SUBREG_REG (oldx
));
3277 /* Push/pop get done as smaller push/pops. */
3278 if (GET_CODE (x
) == MEM
3279 && (GET_CODE (XEXP (x
, 0)) == PRE_DEC
3280 || GET_CODE (XEXP (x
, 0)) == POST_INC
))
3281 return gen_rtx_MEM (outer
, XEXP (x
, 0));
3282 if (GET_CODE (x
) == SUBREG
3283 && GET_CODE (XEXP (x
, 0)) == MEM
3284 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == PRE_DEC
3285 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == POST_INC
))
3286 return gen_rtx_MEM (outer
, XEXP (XEXP (x
, 0), 0));
3288 if (GET_CODE (x
) != REG
)
3290 rtx r
= simplify_gen_subreg (outer
, x
, inner
, byte
);
3291 if (GET_CODE (r
) == SUBREG
3292 && GET_CODE (x
) == MEM
3293 && MEM_VOLATILE_P (x
))
3295 /* Volatile MEMs don't get simplified, but we need them to
3296 be. We are little endian, so the subreg byte is the
3298 r
= adjust_address_nv (x
, outer
, byte
);
3304 if (r
>= FIRST_PSEUDO_REGISTER
|| r
== AP_REGNO
)
3305 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3307 if (IS_MEM_REGNO (r
))
3308 return simplify_gen_subreg (outer
, x
, inner
, byte
);
3310 /* This is where the complexities of our register layout are
3314 else if (outer
== HImode
)
3316 if (r
== R0_REGNO
&& byte
== 2)
3318 else if (r
== R0_REGNO
&& byte
== 4)
3320 else if (r
== R0_REGNO
&& byte
== 6)
3322 else if (r
== R1_REGNO
&& byte
== 2)
3324 else if (r
== A0_REGNO
&& byte
== 2)
3327 else if (outer
== SImode
)
3329 if (r
== R0_REGNO
&& byte
== 0)
3331 else if (r
== R0_REGNO
&& byte
== 4)
3336 fprintf (stderr
, "m32c_subreg %s %s %d\n",
3337 mode_name
[outer
], mode_name
[inner
], byte
);
3341 return gen_rtx_REG (outer
, nr
);
3344 /* Used to emit move instructions. We split some moves,
3345 and avoid mem-mem moves. */
3347 m32c_prepare_move (rtx
* operands
, machine_mode mode
)
3349 if (far_addr_space_p (operands
[0])
3350 && CONSTANT_P (operands
[1]))
3352 operands
[1] = force_reg (GET_MODE (operands
[0]), operands
[1]);
3354 if (TARGET_A16
&& mode
== PSImode
)
3355 return m32c_split_move (operands
, mode
, 1);
3356 if ((GET_CODE (operands
[0]) == MEM
)
3357 && (GET_CODE (XEXP (operands
[0], 0)) == PRE_MODIFY
))
3359 rtx pmv
= XEXP (operands
[0], 0);
3360 rtx dest_reg
= XEXP (pmv
, 0);
3361 rtx dest_mod
= XEXP (pmv
, 1);
3363 emit_insn (gen_rtx_SET (Pmode
, dest_reg
, dest_mod
));
3364 operands
[0] = gen_rtx_MEM (mode
, dest_reg
);
3366 if (can_create_pseudo_p () && MEM_P (operands
[0]) && MEM_P (operands
[1]))
3367 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
3371 #define DEBUG_SPLIT 0
3373 /* Returns TRUE if the given PSImode move should be split. We split
3374 for all r8c/m16c moves, since it doesn't support them, and for
3375 POP.L as we can only *push* SImode. */
3377 m32c_split_psi_p (rtx
* operands
)
3380 fprintf (stderr
, "\nm32c_split_psi_p\n");
3381 debug_rtx (operands
[0]);
3382 debug_rtx (operands
[1]);
3387 fprintf (stderr
, "yes, A16\n");
3391 if (GET_CODE (operands
[1]) == MEM
3392 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3395 fprintf (stderr
, "yes, pop.l\n");
3400 fprintf (stderr
, "no, default\n");
3405 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3406 (define_expand), 1 if it is not optional (define_insn_and_split),
3407 and 3 for define_split (alternate api). */
3409 m32c_split_move (rtx
* operands
, machine_mode mode
, int split_all
)
3412 int parts
, si
, di
, rev
= 0;
3413 int rv
= 0, opi
= 2;
3414 machine_mode submode
= HImode
;
3415 rtx
*ops
, local_ops
[10];
3417 /* define_split modifies the existing operands, but the other two
3418 emit new insns. OPS is where we store the operand pairs, which
3429 /* Before splitting mem-mem moves, force one operand into a
3431 if (can_create_pseudo_p () && MEM_P (operands
[0]) && MEM_P (operands
[1]))
3434 fprintf (stderr
, "force_reg...\n");
3435 debug_rtx (operands
[1]);
3437 operands
[1] = force_reg (mode
, operands
[1]);
3439 debug_rtx (operands
[1]);
3446 fprintf (stderr
, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3448 debug_rtx (operands
[0]);
3449 debug_rtx (operands
[1]);
3452 /* Note that split_all is not used to select the api after this
3453 point, so it's safe to set it to 3 even with define_insn. */
3454 /* None of the chips can move SI operands to sp-relative addresses,
3455 so we always split those. */
3456 if (satisfies_constraint_Ss (operands
[0]))
3460 && (far_addr_space_p (operands
[0])
3461 || far_addr_space_p (operands
[1])))
3464 /* We don't need to split these. */
3467 && (mode
== SImode
|| mode
== PSImode
)
3468 && !(GET_CODE (operands
[1]) == MEM
3469 && GET_CODE (XEXP (operands
[1], 0)) == POST_INC
))
3472 /* First, enumerate the subregs we'll be dealing with. */
3473 for (si
= 0; si
< parts
; si
++)
3476 m32c_subreg (submode
, operands
[0], mode
,
3477 si
* GET_MODE_SIZE (submode
));
3479 m32c_subreg (submode
, operands
[1], mode
,
3480 si
* GET_MODE_SIZE (submode
));
3483 /* Split pushes by emitting a sequence of smaller pushes. */
3484 if (GET_CODE (d
[0]) == MEM
&& GET_CODE (XEXP (d
[0], 0)) == PRE_DEC
)
3486 for (si
= parts
- 1; si
>= 0; si
--)
3488 ops
[opi
++] = gen_rtx_MEM (submode
,
3489 gen_rtx_PRE_DEC (Pmode
,
3497 /* Likewise for pops. */
3498 else if (GET_CODE (s
[0]) == MEM
&& GET_CODE (XEXP (s
[0], 0)) == POST_INC
)
3500 for (di
= 0; di
< parts
; di
++)
3503 ops
[opi
++] = gen_rtx_MEM (submode
,
3504 gen_rtx_POST_INC (Pmode
,
3512 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3513 for (di
= 0; di
< parts
- 1; di
++)
3514 for (si
= di
+ 1; si
< parts
; si
++)
3515 if (reg_mentioned_p (d
[di
], s
[si
]))
3519 for (si
= 0; si
< parts
; si
++)
3525 for (si
= parts
- 1; si
>= 0; si
--)
3532 /* Now emit any moves we may have accumulated. */
3533 if (rv
&& split_all
!= 3)
3536 for (i
= 2; i
< opi
; i
+= 2)
3537 emit_move_insn (ops
[i
], ops
[i
+ 1]);
3542 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3543 the like. For the R8C they expect one of the addresses to be in
3544 R1L:An so we need to arrange for that. Otherwise, it's just a
3545 matter of picking out the operands we want and emitting the right
3546 pattern for them. All these expanders, which correspond to
3547 patterns in blkmov.md, must return nonzero if they expand the insn,
3548 or zero if they should FAIL. */
3550 /* This is a memset() opcode. All operands are implied, so we need to
3551 arrange for them to be in the right registers. The opcode wants
3552 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3553 the count (HI), and $2 the value (QI). */
3555 m32c_expand_setmemhi(rtx
*operands
)
3557 rtx desta
, count
, val
;
3560 desta
= XEXP (operands
[0], 0);
3561 count
= operands
[1];
3564 desto
= gen_reg_rtx (Pmode
);
3565 counto
= gen_reg_rtx (HImode
);
3567 if (GET_CODE (desta
) != REG
3568 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3569 desta
= copy_to_mode_reg (Pmode
, desta
);
3571 /* This looks like an arbitrary restriction, but this is by far the
3572 most common case. For counts 8..14 this actually results in
3573 smaller code with no speed penalty because the half-sized
3574 constant can be loaded with a shorter opcode. */
3575 if (GET_CODE (count
) == CONST_INT
3576 && GET_CODE (val
) == CONST_INT
3577 && ! (INTVAL (count
) & 1)
3578 && (INTVAL (count
) > 1)
3579 && (INTVAL (val
) <= 7 && INTVAL (val
) >= -8))
3581 unsigned v
= INTVAL (val
) & 0xff;
3583 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3584 val
= copy_to_mode_reg (HImode
, GEN_INT (v
));
3586 emit_insn (gen_setmemhi_whi_op (desto
, counto
, val
, desta
, count
));
3588 emit_insn (gen_setmemhi_wpsi_op (desto
, counto
, val
, desta
, count
));
3592 /* This is the generalized memset() case. */
3593 if (GET_CODE (val
) != REG
3594 || REGNO (val
) < FIRST_PSEUDO_REGISTER
)
3595 val
= copy_to_mode_reg (QImode
, val
);
3597 if (GET_CODE (count
) != REG
3598 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3599 count
= copy_to_mode_reg (HImode
, count
);
3602 emit_insn (gen_setmemhi_bhi_op (desto
, counto
, val
, desta
, count
));
3604 emit_insn (gen_setmemhi_bpsi_op (desto
, counto
, val
, desta
, count
));
3609 /* This is a memcpy() opcode. All operands are implied, so we need to
3610 arrange for them to be in the right registers. The opcode wants
3611 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3612 is the source (MEM:BLK), and $2 the count (HI). */
3614 m32c_expand_movmemhi(rtx
*operands
)
3616 rtx desta
, srca
, count
;
3617 rtx desto
, srco
, counto
;
3619 desta
= XEXP (operands
[0], 0);
3620 srca
= XEXP (operands
[1], 0);
3621 count
= operands
[2];
3623 desto
= gen_reg_rtx (Pmode
);
3624 srco
= gen_reg_rtx (Pmode
);
3625 counto
= gen_reg_rtx (HImode
);
3627 if (GET_CODE (desta
) != REG
3628 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3629 desta
= copy_to_mode_reg (Pmode
, desta
);
3631 if (GET_CODE (srca
) != REG
3632 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3633 srca
= copy_to_mode_reg (Pmode
, srca
);
3635 /* Similar to setmem, but we don't need to check the value. */
3636 if (GET_CODE (count
) == CONST_INT
3637 && ! (INTVAL (count
) & 1)
3638 && (INTVAL (count
) > 1))
3640 count
= copy_to_mode_reg (HImode
, GEN_INT (INTVAL (count
) / 2));
3642 emit_insn (gen_movmemhi_whi_op (desto
, srco
, counto
, desta
, srca
, count
));
3644 emit_insn (gen_movmemhi_wpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3648 /* This is the generalized memset() case. */
3649 if (GET_CODE (count
) != REG
3650 || REGNO (count
) < FIRST_PSEUDO_REGISTER
)
3651 count
= copy_to_mode_reg (HImode
, count
);
3654 emit_insn (gen_movmemhi_bhi_op (desto
, srco
, counto
, desta
, srca
, count
));
3656 emit_insn (gen_movmemhi_bpsi_op (desto
, srco
, counto
, desta
, srca
, count
));
3661 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3662 the copy, which should point to the NUL at the end of the string,
3663 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3664 Since our opcode leaves the destination pointing *after* the NUL,
3665 we must emit an adjustment. */
3667 m32c_expand_movstr(rtx
*operands
)
3672 desta
= XEXP (operands
[1], 0);
3673 srca
= XEXP (operands
[2], 0);
3675 desto
= gen_reg_rtx (Pmode
);
3676 srco
= gen_reg_rtx (Pmode
);
3678 if (GET_CODE (desta
) != REG
3679 || REGNO (desta
) < FIRST_PSEUDO_REGISTER
)
3680 desta
= copy_to_mode_reg (Pmode
, desta
);
3682 if (GET_CODE (srca
) != REG
3683 || REGNO (srca
) < FIRST_PSEUDO_REGISTER
)
3684 srca
= copy_to_mode_reg (Pmode
, srca
);
3686 emit_insn (gen_movstr_op (desto
, srco
, desta
, srca
));
3687 /* desto ends up being a1, which allows this type of add through MOVA. */
3688 emit_insn (gen_addpsi3 (operands
[0], desto
, GEN_INT (-1)));
3693 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3694 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3695 $2 is the other (MEM:BLK). We must do the comparison, and then
3696 convert the flags to a signed integer result. */
3698 m32c_expand_cmpstr(rtx
*operands
)
3702 src1a
= XEXP (operands
[1], 0);
3703 src2a
= XEXP (operands
[2], 0);
3705 if (GET_CODE (src1a
) != REG
3706 || REGNO (src1a
) < FIRST_PSEUDO_REGISTER
)
3707 src1a
= copy_to_mode_reg (Pmode
, src1a
);
3709 if (GET_CODE (src2a
) != REG
3710 || REGNO (src2a
) < FIRST_PSEUDO_REGISTER
)
3711 src2a
= copy_to_mode_reg (Pmode
, src2a
);
3713 emit_insn (gen_cmpstrhi_op (src1a
, src2a
, src1a
, src2a
));
3714 emit_insn (gen_cond_to_int (operands
[0]));
3720 typedef rtx (*shift_gen_func
)(rtx
, rtx
, rtx
);
3722 static shift_gen_func
3723 shift_gen_func_for (int mode
, int code
)
3725 #define GFF(m,c,f) if (mode == m && code == c) return f
3726 GFF(QImode
, ASHIFT
, gen_ashlqi3_i
);
3727 GFF(QImode
, ASHIFTRT
, gen_ashrqi3_i
);
3728 GFF(QImode
, LSHIFTRT
, gen_lshrqi3_i
);
3729 GFF(HImode
, ASHIFT
, gen_ashlhi3_i
);
3730 GFF(HImode
, ASHIFTRT
, gen_ashrhi3_i
);
3731 GFF(HImode
, LSHIFTRT
, gen_lshrhi3_i
);
3732 GFF(PSImode
, ASHIFT
, gen_ashlpsi3_i
);
3733 GFF(PSImode
, ASHIFTRT
, gen_ashrpsi3_i
);
3734 GFF(PSImode
, LSHIFTRT
, gen_lshrpsi3_i
);
3735 GFF(SImode
, ASHIFT
, TARGET_A16
? gen_ashlsi3_16
: gen_ashlsi3_24
);
3736 GFF(SImode
, ASHIFTRT
, TARGET_A16
? gen_ashrsi3_16
: gen_ashrsi3_24
);
3737 GFF(SImode
, LSHIFTRT
, TARGET_A16
? gen_lshrsi3_16
: gen_lshrsi3_24
);
3742 /* The m32c only has one shift, but it takes a signed count. GCC
3743 doesn't want this, so we fake it by negating any shift count when
3744 we're pretending to shift the other way. Also, the shift count is
3745 limited to -8..8. It's slightly better to use two shifts for 9..15
3746 than to load the count into r1h, so we do that too. */
3748 m32c_prepare_shift (rtx
* operands
, int scale
, int shift_code
)
3750 machine_mode mode
= GET_MODE (operands
[0]);
3751 shift_gen_func func
= shift_gen_func_for (mode
, shift_code
);
3754 if (GET_CODE (operands
[2]) == CONST_INT
)
3756 int maxc
= TARGET_A24
&& (mode
== PSImode
|| mode
== SImode
) ? 32 : 8;
3757 int count
= INTVAL (operands
[2]) * scale
;
3759 while (count
> maxc
)
3761 temp
= gen_reg_rtx (mode
);
3762 emit_insn (func (temp
, operands
[1], GEN_INT (maxc
)));
3766 while (count
< -maxc
)
3768 temp
= gen_reg_rtx (mode
);
3769 emit_insn (func (temp
, operands
[1], GEN_INT (-maxc
)));
3773 emit_insn (func (operands
[0], operands
[1], GEN_INT (count
)));
3777 temp
= gen_reg_rtx (QImode
);
3779 /* The pattern has a NEG that corresponds to this. */
3780 emit_move_insn (temp
, gen_rtx_NEG (QImode
, operands
[2]));
3781 else if (TARGET_A16
&& mode
== SImode
)
3782 /* We do this because the code below may modify this, we don't
3783 want to modify the origin of this value. */
3784 emit_move_insn (temp
, operands
[2]);
3786 /* We'll only use it for the shift, no point emitting a move. */
3789 if (TARGET_A16
&& GET_MODE_SIZE (mode
) == 4)
3791 /* The m16c has a limit of -16..16 for SI shifts, even when the
3792 shift count is in a register. Since there are so many targets
3793 of these shifts, it's better to expand the RTL here than to
3794 call a helper function.
3796 The resulting code looks something like this:
3808 We take advantage of the fact that "negative" shifts are
3809 undefined to skip one of the comparisons. */
3815 emit_move_insn (operands
[0], operands
[1]);
3818 label
= gen_label_rtx ();
3819 LABEL_NUSES (label
) ++;
3821 tempvar
= gen_reg_rtx (mode
);
3823 if (shift_code
== ASHIFT
)
3825 /* This is a left shift. We only need check positive counts. */
3826 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode
, 0, 0),
3827 count
, GEN_INT (16), label
));
3828 emit_insn (func (tempvar
, operands
[0], GEN_INT (8)));
3829 emit_insn (func (operands
[0], tempvar
, GEN_INT (8)));
3830 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (-16)));
3831 emit_label_after (label
, insn
);
3835 /* This is a right shift. We only need check negative counts. */
3836 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode
, 0, 0),
3837 count
, GEN_INT (-16), label
));
3838 emit_insn (func (tempvar
, operands
[0], GEN_INT (-8)));
3839 emit_insn (func (operands
[0], tempvar
, GEN_INT (-8)));
3840 insn
= emit_insn (gen_addqi3 (count
, count
, GEN_INT (16)));
3841 emit_label_after (label
, insn
);
3843 operands
[1] = operands
[0];
3844 emit_insn (func (operands
[0], operands
[0], count
));
3852 /* The m32c has a limited range of operations that work on PSImode
3853 values; we have to expand to SI, do the math, and truncate back to
3854 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3857 m32c_expand_neg_mulpsi3 (rtx
* operands
)
3859 /* operands: a = b * i */
3860 rtx temp1
; /* b as SI */
3861 rtx scale
/* i as SI */;
3862 rtx temp2
; /* a*b as SI */
3864 temp1
= gen_reg_rtx (SImode
);
3865 temp2
= gen_reg_rtx (SImode
);
3866 if (GET_CODE (operands
[2]) != CONST_INT
)
3868 scale
= gen_reg_rtx (SImode
);
3869 emit_insn (gen_zero_extendpsisi2 (scale
, operands
[2]));
3872 scale
= copy_to_mode_reg (SImode
, operands
[2]);
3874 emit_insn (gen_zero_extendpsisi2 (temp1
, operands
[1]));
3875 temp2
= expand_simple_binop (SImode
, MULT
, temp1
, scale
, temp2
, 1, OPTAB_LIB
);
3876 emit_insn (gen_truncsipsi2 (operands
[0], temp2
));
3879 /* Pattern Output Functions */
3882 m32c_expand_movcc (rtx
*operands
)
3884 rtx rel
= operands
[1];
3886 if (GET_CODE (rel
) != EQ
&& GET_CODE (rel
) != NE
)
3888 if (GET_CODE (operands
[2]) != CONST_INT
3889 || GET_CODE (operands
[3]) != CONST_INT
)
3891 if (GET_CODE (rel
) == NE
)
3893 rtx tmp
= operands
[2];
3894 operands
[2] = operands
[3];
3896 rel
= gen_rtx_EQ (GET_MODE (rel
), XEXP (rel
, 0), XEXP (rel
, 1));
3899 emit_move_insn (operands
[0],
3900 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
3907 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3909 m32c_expand_insv (rtx
*operands
)
3914 if (INTVAL (operands
[1]) != 1)
3917 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3918 if (GET_CODE (operands
[3]) != CONST_INT
)
3920 if (INTVAL (operands
[3]) != 0
3921 && INTVAL (operands
[3]) != 1
3922 && INTVAL (operands
[3]) != -1)
3925 mask
= 1 << INTVAL (operands
[2]);
3928 if (GET_CODE (op0
) == SUBREG
3929 && SUBREG_BYTE (op0
) == 0)
3931 rtx sub
= SUBREG_REG (op0
);
3932 if (GET_MODE (sub
) == HImode
|| GET_MODE (sub
) == QImode
)
3936 if (!can_create_pseudo_p ()
3937 || (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
)))
3941 src0
= gen_reg_rtx (GET_MODE (op0
));
3942 emit_move_insn (src0
, op0
);
3945 if (GET_MODE (op0
) == HImode
3946 && INTVAL (operands
[2]) >= 8
3947 && GET_CODE (op0
) == MEM
)
3949 /* We are little endian. */
3950 rtx new_mem
= gen_rtx_MEM (QImode
, plus_constant (Pmode
,
3952 MEM_COPY_ATTRIBUTES (new_mem
, op0
);
3956 /* First, we generate a mask with the correct polarity. If we are
3957 storing a zero, we want an AND mask, so invert it. */
3958 if (INTVAL (operands
[3]) == 0)
3960 /* Storing a zero, use an AND mask */
3961 if (GET_MODE (op0
) == HImode
)
3966 /* Now we need to properly sign-extend the mask in case we need to
3967 fall back to an AND or OR opcode. */
3968 if (GET_MODE (op0
) == HImode
)
3979 switch ( (INTVAL (operands
[3]) ? 4 : 0)
3980 + ((GET_MODE (op0
) == HImode
) ? 2 : 0)
3981 + (TARGET_A24
? 1 : 0))
3983 case 0: p
= gen_andqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3984 case 1: p
= gen_andqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3985 case 2: p
= gen_andhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3986 case 3: p
= gen_andhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3987 case 4: p
= gen_iorqi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3988 case 5: p
= gen_iorqi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3989 case 6: p
= gen_iorhi3_16 (op0
, src0
, GEN_INT (mask
)); break;
3990 case 7: p
= gen_iorhi3_24 (op0
, src0
, GEN_INT (mask
)); break;
3991 default: p
= NULL_RTX
; break; /* Not reached, but silences a warning. */
3999 m32c_scc_pattern(rtx
*operands
, RTX_CODE code
)
4001 static char buf
[30];
4002 if (GET_CODE (operands
[0]) == REG
4003 && REGNO (operands
[0]) == R0_REGNO
)
4006 return "stzx\t#1,#0,r0l";
4008 return "stzx\t#0,#1,r0l";
4010 sprintf(buf
, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code
));
4014 /* Encode symbol attributes of a SYMBOL_REF into its
4015 SYMBOL_REF_FLAGS. */
4017 m32c_encode_section_info (tree decl
, rtx rtl
, int first
)
4019 int extra_flags
= 0;
4021 default_encode_section_info (decl
, rtl
, first
);
4022 if (TREE_CODE (decl
) == FUNCTION_DECL
4023 && m32c_special_page_vector_p (decl
))
4025 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
4028 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
4031 /* Returns TRUE if the current function is a leaf, and thus we can
4032 determine which registers an interrupt function really needs to
4033 save. The logic below is mostly about finding the insn sequence
4034 that's the function, versus any sequence that might be open for the
4037 m32c_leaf_function_p (void)
4039 rtx_insn
*saved_first
, *saved_last
;
4040 struct sequence_stack
*seq
;
4043 saved_first
= crtl
->emit
.x_first_insn
;
4044 saved_last
= crtl
->emit
.x_last_insn
;
4045 for (seq
= crtl
->emit
.sequence_stack
; seq
&& seq
->next
; seq
= seq
->next
)
4049 crtl
->emit
.x_first_insn
= seq
->first
;
4050 crtl
->emit
.x_last_insn
= seq
->last
;
4053 rv
= leaf_function_p ();
4055 crtl
->emit
.x_first_insn
= saved_first
;
4056 crtl
->emit
.x_last_insn
= saved_last
;
4060 /* Returns TRUE if the current function needs to use the ENTER/EXIT
4061 opcodes. If the function doesn't need the frame base or stack
4062 pointer, it can use the simpler RTS opcode. */
4064 m32c_function_needs_enter (void)
4067 struct sequence_stack
*seq
;
4068 rtx sp
= gen_rtx_REG (Pmode
, SP_REGNO
);
4069 rtx fb
= gen_rtx_REG (Pmode
, FB_REGNO
);
4071 insn
= get_insns ();
4072 for (seq
= crtl
->emit
.sequence_stack
;
4074 insn
= seq
->first
, seq
= seq
->next
);
4078 if (reg_mentioned_p (sp
, insn
))
4080 if (reg_mentioned_p (fb
, insn
))
4082 insn
= NEXT_INSN (insn
);
4087 /* Mark all the subexpressions of the PARALLEL rtx PAR as
4088 frame-related. Return PAR.
4090 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
4091 PARALLEL rtx other than the first if they do not have the
4092 FRAME_RELATED flag set on them. So this function is handy for
4093 marking up 'enter' instructions. */
4095 m32c_all_frame_related (rtx par
)
4097 int len
= XVECLEN (par
, 0);
4100 for (i
= 0; i
< len
; i
++)
4101 F (XVECEXP (par
, 0, i
));
4106 /* Emits the prologue. See the frame layout comment earlier in this
4107 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
4108 that we manually update sp. */
4110 m32c_emit_prologue (void)
4112 int frame_size
, extra_frame_size
= 0, reg_save_size
;
4113 int complex_prologue
= 0;
4115 cfun
->machine
->is_leaf
= m32c_leaf_function_p ();
4116 if (interrupt_p (cfun
->decl
))
4118 cfun
->machine
->is_interrupt
= 1;
4119 complex_prologue
= 1;
4121 else if (bank_switch_p (cfun
->decl
))
4122 warning (OPT_Wattributes
,
4123 "%<bank_switch%> has no effect on non-interrupt functions");
4125 reg_save_size
= m32c_pushm_popm (PP_justcount
);
4127 if (interrupt_p (cfun
->decl
))
4129 if (bank_switch_p (cfun
->decl
))
4130 emit_insn (gen_fset_b ());
4131 else if (cfun
->machine
->intr_pushm
)
4132 emit_insn (gen_pushm (GEN_INT (cfun
->machine
->intr_pushm
)));
4136 m32c_initial_elimination_offset (FB_REGNO
, SP_REGNO
) - reg_save_size
;
4138 && !m32c_function_needs_enter ())
4139 cfun
->machine
->use_rts
= 1;
4141 if (frame_size
> 254)
4143 extra_frame_size
= frame_size
- 254;
4146 if (cfun
->machine
->use_rts
== 0)
4147 F (emit_insn (m32c_all_frame_related
4149 ? gen_prologue_enter_16 (GEN_INT (frame_size
+ 2))
4150 : gen_prologue_enter_24 (GEN_INT (frame_size
+ 4)))));
4152 if (extra_frame_size
)
4154 complex_prologue
= 1;
4156 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode
, SP_REGNO
),
4157 gen_rtx_REG (HImode
, SP_REGNO
),
4158 GEN_INT (-extra_frame_size
))));
4160 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode
, SP_REGNO
),
4161 gen_rtx_REG (PSImode
, SP_REGNO
),
4162 GEN_INT (-extra_frame_size
))));
4165 complex_prologue
+= m32c_pushm_popm (PP_pushm
);
4167 /* This just emits a comment into the .s file for debugging. */
4168 if (complex_prologue
)
4169 emit_insn (gen_prologue_end ());
4172 /* Likewise, for the epilogue. The only exception is that, for
4173 interrupts, we must manually unwind the frame as the REIT opcode
4176 m32c_emit_epilogue (void)
4178 int popm_count
= m32c_pushm_popm (PP_justcount
);
4180 /* This just emits a comment into the .s file for debugging. */
4181 if (popm_count
> 0 || cfun
->machine
->is_interrupt
)
4182 emit_insn (gen_epilogue_start ());
4185 m32c_pushm_popm (PP_popm
);
4187 if (cfun
->machine
->is_interrupt
)
4189 machine_mode spmode
= TARGET_A16
? HImode
: PSImode
;
4191 /* REIT clears B flag and restores $fp for us, but we still
4192 have to fix up the stack. USE_RTS just means we didn't
4194 if (!cfun
->machine
->use_rts
)
4196 emit_move_insn (gen_rtx_REG (spmode
, A0_REGNO
),
4197 gen_rtx_REG (spmode
, FP_REGNO
));
4198 emit_move_insn (gen_rtx_REG (spmode
, SP_REGNO
),
4199 gen_rtx_REG (spmode
, A0_REGNO
));
4200 /* We can't just add this to the POPM because it would be in
4201 the wrong order, and wouldn't fix the stack if we're bank
4204 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode
, FP_REGNO
)));
4206 emit_insn (gen_poppsi (gen_rtx_REG (PSImode
, FP_REGNO
)));
4208 if (!bank_switch_p (cfun
->decl
) && cfun
->machine
->intr_pushm
)
4209 emit_insn (gen_popm (GEN_INT (cfun
->machine
->intr_pushm
)));
4211 /* The FREIT (Fast REturn from InTerrupt) instruction should be
4212 generated only for M32C/M32CM targets (generate the REIT
4213 instruction otherwise). */
4214 if (fast_interrupt_p (cfun
->decl
))
4216 /* Check if fast_attribute is set for M32C or M32CM. */
4219 emit_jump_insn (gen_epilogue_freit ());
4221 /* If fast_interrupt attribute is set for an R8C or M16C
4222 target ignore this attribute and generated REIT
4226 warning (OPT_Wattributes
,
4227 "%<fast_interrupt%> attribute directive ignored");
4228 emit_jump_insn (gen_epilogue_reit_16 ());
4231 else if (TARGET_A16
)
4232 emit_jump_insn (gen_epilogue_reit_16 ());
4234 emit_jump_insn (gen_epilogue_reit_24 ());
4236 else if (cfun
->machine
->use_rts
)
4237 emit_jump_insn (gen_epilogue_rts ());
4238 else if (TARGET_A16
)
4239 emit_jump_insn (gen_epilogue_exitd_16 ());
4241 emit_jump_insn (gen_epilogue_exitd_24 ());
4245 m32c_emit_eh_epilogue (rtx ret_addr
)
4247 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4248 return to. We have to fudge the stack, pop everything, pop SP
4249 (fudged), and return (fudged). This is actually easier to do in
4250 assembler, so punt to libgcc. */
4251 emit_jump_insn (gen_eh_epilogue (ret_addr
, cfun
->machine
->eh_stack_adjust
));
4252 /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
4255 /* Indicate which flags must be properly set for a given conditional. */
4257 flags_needed_for_conditional (rtx cond
)
4259 switch (GET_CODE (cond
))
4283 /* Returns true if a compare insn is redundant because it would only
4284 set flags that are already set correctly. */
4286 m32c_compare_redundant (rtx_insn
*cmp
, rtx
*operands
)
4301 fprintf(stderr
, "\n\033[32mm32c_compare_redundant\033[0m\n");
4305 fprintf(stderr
, "operands[%d] = ", i
);
4306 debug_rtx(operands
[i
]);
4310 next
= next_nonnote_insn (cmp
);
4311 if (!next
|| !INSN_P (next
))
4314 fprintf(stderr
, "compare not followed by insn\n");
4319 if (GET_CODE (PATTERN (next
)) == SET
4320 && GET_CODE (XEXP ( PATTERN (next
), 1)) == IF_THEN_ELSE
)
4322 next
= XEXP (XEXP (PATTERN (next
), 1), 0);
4324 else if (GET_CODE (PATTERN (next
)) == SET
)
4326 /* If this is a conditional, flags_needed will be something
4327 other than FLAGS_N, which we test below. */
4328 next
= XEXP (PATTERN (next
), 1);
4333 fprintf(stderr
, "compare not followed by conditional\n");
4339 fprintf(stderr
, "conditional is: ");
4343 flags_needed
= flags_needed_for_conditional (next
);
4344 if (flags_needed
== FLAGS_N
)
4347 fprintf(stderr
, "compare not followed by conditional\n");
4353 /* Compare doesn't set overflow and carry the same way that
4354 arithmetic instructions do, so we can't replace those. */
4355 if (flags_needed
& FLAGS_OC
)
4360 prev
= prev_nonnote_insn (prev
);
4364 fprintf(stderr
, "No previous insn.\n");
4371 fprintf(stderr
, "Previous insn is a non-insn.\n");
4375 pp
= PATTERN (prev
);
4376 if (GET_CODE (pp
) != SET
)
4379 fprintf(stderr
, "Previous insn is not a SET.\n");
4383 pflags
= get_attr_flags (prev
);
4385 /* Looking up attributes of previous insns corrupted the recog
4387 INSN_UID (cmp
) = -1;
4388 recog (PATTERN (cmp
), cmp
, 0);
4390 if (pflags
== FLAGS_N
4391 && reg_mentioned_p (op0
, pp
))
4394 fprintf(stderr
, "intermediate non-flags insn uses op:\n");
4400 /* Check for comparisons against memory - between volatiles and
4401 aliases, we just can't risk this one. */
4402 if (GET_CODE (operands
[0]) == MEM
4403 || GET_CODE (operands
[0]) == MEM
)
4406 fprintf(stderr
, "comparisons with memory:\n");
4412 /* Check for PREV changing a register that's used to compute a
4413 value in CMP, even if it doesn't otherwise change flags. */
4414 if (GET_CODE (operands
[0]) == REG
4415 && rtx_referenced_p (SET_DEST (PATTERN (prev
)), operands
[0]))
4418 fprintf(stderr
, "sub-value affected, op0:\n");
4423 if (GET_CODE (operands
[1]) == REG
4424 && rtx_referenced_p (SET_DEST (PATTERN (prev
)), operands
[1]))
4427 fprintf(stderr
, "sub-value affected, op1:\n");
4433 } while (pflags
== FLAGS_N
);
4435 fprintf(stderr
, "previous flag-setting insn:\n");
4440 if (GET_CODE (pp
) == SET
4441 && GET_CODE (XEXP (pp
, 0)) == REG
4442 && REGNO (XEXP (pp
, 0)) == FLG_REGNO
4443 && GET_CODE (XEXP (pp
, 1)) == COMPARE
)
4445 /* Adjacent cbranches must have the same operands to be
4447 rtx pop0
= XEXP (XEXP (pp
, 1), 0);
4448 rtx pop1
= XEXP (XEXP (pp
, 1), 1);
4450 fprintf(stderr
, "adjacent cbranches\n");
4454 if (rtx_equal_p (op0
, pop0
)
4455 && rtx_equal_p (op1
, pop1
))
4458 fprintf(stderr
, "prev cmp not same\n");
4463 /* Else the previous insn must be a SET, with either the source or
4464 dest equal to operands[0], and operands[1] must be zero. */
4466 if (!rtx_equal_p (op1
, const0_rtx
))
4469 fprintf(stderr
, "operands[1] not const0_rtx\n");
4473 if (GET_CODE (pp
) != SET
)
4476 fprintf (stderr
, "pp not set\n");
4480 if (!rtx_equal_p (op0
, SET_SRC (pp
))
4481 && !rtx_equal_p (op0
, SET_DEST (pp
)))
4484 fprintf(stderr
, "operands[0] not found in set\n");
4490 fprintf(stderr
, "cmp flags %x prev flags %x\n", flags_needed
, pflags
);
4492 if ((pflags
& flags_needed
) == flags_needed
)
4498 /* Return the pattern for a compare. This will be commented out if
4499 the compare is redundant, else a normal pattern is returned. Thus,
4500 the assembler output says where the compare would have been. */
4502 m32c_output_compare (rtx_insn
*insn
, rtx
*operands
)
4504 static char templ
[] = ";cmp.b\t%1,%0";
4507 templ
[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands
[0]))];
4508 if (m32c_compare_redundant (insn
, operands
))
4511 fprintf(stderr
, "cbranch: cmp not needed\n");
4517 fprintf(stderr
, "cbranch: cmp needed: `%s'\n", templ
+ 1);
4522 #undef TARGET_ENCODE_SECTION_INFO
4523 #define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4525 /* If the frame pointer isn't used, we detect it manually. But the
4526 stack pointer doesn't have as flexible addressing as the frame
4527 pointer, so we always assume we have it. */
4529 #undef TARGET_FRAME_POINTER_REQUIRED
4530 #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
4532 /* The Global `targetm' Variable. */
4534 struct gcc_target targetm
= TARGET_INITIALIZER
;
4536 #include "gt-m32c.h"