gcc/config/m32c/bitops.md

   1 ;; Machine Descriptions for R8C/M16C/M32C
   2 ;; Copyright (C) 2005, 2007, 2008, 2010
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Red Hat.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published
  10 ;; by the Free Software Foundation; either version 3, or (at your
  11 ;; option) any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; Bit-wise operations (and, ior, xor, shift)
  23
  24 ; On the R8C and M16C, "address" for bit instructions is usually (but
  25 ; not always!) the *bit* address, not the *byte* address.  This
  26 ; confuses gcc, so we avoid cases where gcc would produce the wrong
  27 ; code.  We're left with absolute addresses and registers, and the odd
  28 ; case of shifting a bit by a variable.
  29
  30 ; On the M32C, "address" for bit instructions is a regular address,
  31 ; and the bit number is stored in a separate field.  Thus, we can let
  32 ; gcc do more interesting things.  However, the M32C cannot set all
  33 ; the bits in a 16-bit register, which the R8C/M16C can do.
  34
  35 ; However, it all means that we end up with two sets of patterns, one
  36 ; for each chip.
  37
  38 ;;----------------------------------------------------------------------
  39
  40 ;; First off, all the ways we can set one bit, other than plain IOR.
  41
  42 (define_insn "bset_qi"
  43   [(set (match_operand:QI 0 "memsym_operand" "+Si")
  44         (ior:QI (subreg:QI (ashift:HI (const_int 1)
  45                                       (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
  46                 (match_operand:QI 2 "memsym_operand" "0")))]
  47   "TARGET_A16"
  48   "bset\t%0[%1]"
  49   [(set_attr "flags" "n")]
  50   )
  51
  52 (define_insn "bset_hi"
  53   [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
  54                          (const_int 1)
  55                          (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
  56         (const_int 1))]
  57   "TARGET_A16"
  58   "bset\t%0[%1]"
  59   [(set_attr "flags" "n")]
  60   )
  61
  62 ;;----------------------------------------------------------------------
  63
  64 ;; Now all the ways we can clear one bit, other than plain AND.
  65
  66 ; This is odd because the shift patterns use QI counts, but we can't
  67 ; easily put QI in $aN without causing problems elsewhere.
  68 (define_insn "bclr_qi"
  69   [(set (zero_extract:HI (match_operand:QI 0 "memsym_operand" "+Si")
  70                          (const_int 1)
  71                          (zero_extend:HI (subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)))
  72         (const_int 0))]
  73   "TARGET_A16"
  74   "bclr\t%0[%1]"
  75   [(set_attr "flags" "n")]
  76   )
  77
  78
  79 ;;----------------------------------------------------------------------
  80
  81 ;; Now the generic patterns.
  82
  83 (define_insn "andqi3_16"
  84   [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
  85         (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
  86                 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
  87   "TARGET_A16"
  88   "@
  89    bclr\t%B2,%0
  90    bclr\t%B2,%h0
  91    and.b\t%x2,%0
  92    and.b\t%x2,%0
  93    and.b\t%x2,%0
  94    and.b\t%x2,%0"
  95   [(set_attr "flags" "n,n,sz,sz,sz,sz")]
  96   )
  97
  98 (define_insn "andhi3_16"
  99   [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,??Rmm,RhiSd,??Rmm")
 100         (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
 101                 (match_operand:HI 2 "mrai_operand" "ImB,Imw,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
 102   "TARGET_A16"
 103   "@
 104
 105    bclr\t%B2,%0
 106    bclr\t%B2-8,1+%0
 107    bclr\t%B2,%0
 108    and.w\t%X2,%0
 109    and.w\t%X2,%0
 110    and.w\t%X2,%0
 111    and.w\t%X2,%0"
 112   [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
 113   )
 114
 115 (define_insn "andsi3"
 116   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
 117         (and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
 118                 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
 119   ""
 120   "*
 121   switch (which_alternative)
 122     {
 123     case 0:
 124       output_asm_insn (\"and.w %X2,%h0\",operands);
 125       operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
 126       return \"and.w %X2,%H0\";
 127     case 1:
 128       return \"and.w %h2,%h0\;and.w %H2,%H0\";
 129     case 2:
 130       output_asm_insn (\"and.w %X2,%h0\",operands);
 131       operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
 132       return \"and.w %X2,%H0\";
 133     case 3:
 134       return \"and.w %h2,%h0\;and.w %H2,%H0\";
 135     case 4:
 136       return \"and.w %h2,%h0\;and.w %H2,%H0\";
 137     case 5:
 138       return \"and.w %h2,%h0\;and.w %H2,%H0\";
 139     default:
 140       gcc_unreachable ();
 141     }"
 142   [(set_attr "flags" "x,x,x,x,x,x")]
 143 )
 144
 145
 146 (define_insn "iorqi3_16"
 147   [(set (match_operand:QI 0 "mra_operand" "=Sp,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
 148         (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
 149                 (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
 150   "TARGET_A16"
 151   "@
 152    bset\t%B2,%0
 153    bset\t%B2,%h0
 154    or.b\t%x2,%0
 155    or.b\t%x2,%0
 156    or.b\t%x2,%0
 157    or.b\t%x2,%0"
 158   [(set_attr "flags" "n,n,sz,sz,sz,sz")]
 159   )
 160
 161 (define_insn "iorhi3_16"
 162   [(set (match_operand:HI 0 "mra_operand" "=Sp,Sp,Rhi,RhiSd,RhiSd,??Rmm,??Rmm")
 163         (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0")
 164                 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
 165   "TARGET_A16"
 166   "@
 167    bset %B2,%0
 168    bset\t%B2-8,1+%0
 169    bset\t%B2,%0
 170    or.w\t%X2,%0
 171    or.w\t%X2,%0
 172    or.w\t%X2,%0
 173    or.w\t%X2,%0"
 174   [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
 175   )
 176
 177 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 178
 179 (define_insn "andqi3_24"
 180   [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RhlSd,RhlSd,??Rmm,??Rmm")
 181         (and:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
 182                 (match_operand 2 "mrai_operand" "Imb,Imb,iRhlSd,?Rmm,iRhlSd,?Rmm")))]
 183   "TARGET_A24"
 184   "@
 185    bclr\t%B2,%0
 186    bclr\t%B2,%0
 187    and.b\t%x2,%0
 188    and.b\t%x2,%0
 189    and.b\t%x2,%0
 190    and.b\t%x2,%0"
 191   [(set_attr "flags" "n,n,sz,sz,sz,sz")]
 192   )
 193
 194 (define_insn "andhi3_24"
 195   [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm")
 196         (and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
 197                 (match_operand:HI 2 "mrai_operand" "ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
 198   "TARGET_A24"
 199   "@
 200    bclr\t%B2,%0
 201    bclr\t%B2-8,1+%0
 202    bclr\t%B2,%h0
 203    bclr\t%B2-8,%H0
 204    and.w\t%X2,%0
 205    and.w\t%X2,%0
 206    and.w\t%X2,%0
 207    and.w\t%X2,%0"
 208   [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
 209   )
 210
 211
 212
 213 (define_insn "iorqi3_24"
 214   [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
 215         (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
 216                 (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
 217   "TARGET_A24"
 218   "@
 219    bset\t%B2,%0
 220    or.b\t%x2,%0
 221    or.b\t%x2,%0
 222    or.b\t%x2,%0
 223    or.b\t%x2,%0"
 224   [(set_attr "flags" "n,sz,sz,sz,sz")]
 225   )
 226
 227 (define_insn "iorhi3_24"
 228   [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm")
 229         (ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
 230                 (match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
 231   "TARGET_A24"
 232   "@
 233    bset\t%B2,%0
 234    bset\t%B2-8,1+%0
 235    bset\t%B2,%h0
 236    bset\t%B2-8,%H0
 237    or.w\t%X2,%0
 238    or.w\t%X2,%0
 239    or.w\t%X2,%0
 240    or.w\t%X2,%0"
 241   [(set_attr "flags" "n,n,n,n,sz,sz,sz,sz")]
 242   )
 243
 244
 245 ; ----------------------------------------------------------------------
 246
 247 (define_expand "andqi3"
 248   [(set (match_operand:QI 0 "mra_operand" "")
 249         (and:QI (match_operand:QI 1 "mra_operand" "")
 250                 (match_operand:QI 2 "mrai_operand" "")))]
 251   ""
 252   "if (TARGET_A16)
 253      emit_insn (gen_andqi3_16 (operands[0], operands[1], operands[2]));
 254    else
 255      emit_insn (gen_andqi3_24 (operands[0], operands[1], operands[2]));
 256    DONE;"
 257   )
 258
 259 (define_expand "andhi3"
 260   [(set (match_operand:HI 0 "mra_operand" "")
 261         (and:HI (match_operand:HI 1 "mra_operand" "")
 262                 (match_operand:HI 2 "mrai_operand" "")))]
 263   ""
 264   "if (TARGET_A16)
 265      emit_insn (gen_andhi3_16 (operands[0], operands[1], operands[2]));
 266    else
 267      emit_insn (gen_andhi3_24 (operands[0], operands[1], operands[2]));
 268    DONE;"
 269   )
 270
 271 (define_expand "iorqi3"
 272   [(set (match_operand:QI 0 "mra_operand" "")
 273         (ior:QI (match_operand:QI 1 "mra_operand" "")
 274                 (match_operand:QI 2 "mrai_operand" "")))]
 275   ""
 276   "if (TARGET_A16)
 277      emit_insn (gen_iorqi3_16 (operands[0], operands[1], operands[2]));
 278    else
 279      emit_insn (gen_iorqi3_24 (operands[0], operands[1], operands[2]));
 280    DONE;"
 281   )
 282
 283 (define_expand "iorhi3"
 284   [(set (match_operand:HI 0 "mra_operand" "")
 285         (ior:HI (match_operand:HI 1 "mra_operand" "")
 286                 (match_operand:HI 2 "mrai_operand" "")))]
 287   ""
 288   "if (TARGET_A16)
 289      emit_insn (gen_iorhi3_16 (operands[0], operands[1], operands[2]));
 290    else
 291      emit_insn (gen_iorhi3_24 (operands[0], operands[1], operands[2]));
 292    DONE;"
 293   )
 294
 295 (define_insn "iorsi3"
 296   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
 297         (ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
 298                 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
 299   ""
 300   "*
 301   switch (which_alternative)
 302     {
 303     case 0:
 304       output_asm_insn (\"or.w %X2,%h0\",operands);
 305       operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
 306       return \"or.w %X2,%H0\";
 307     case 1:
 308       return \"or.w %h2,%h0\;or.w %H2,%H0\";
 309     case 2:
 310       output_asm_insn (\"or.w %X2,%h0\",operands);
 311       operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
 312       return \"or.w %X2,%H0\";
 313     case 3:
 314       return \"or.w %h2,%h0\;or.w %H2,%H0\";
 315     case 4:
 316       return \"or.w %h2,%h0\;or.w %H2,%H0\";
 317     case 5:
 318       return \"or.w %h2,%h0\;or.w %H2,%H0\";
 319     default:
 320       gcc_unreachable ();
 321     }"
 322   [(set_attr "flags" "x,x,x,x,x,x")]
 323 )
 324
 325 (define_insn "xorqi3"
 326   [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
 327         (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
 328                 (match_operand:QI 2 "mrai_operand" "iRhlSd,?Rmm,iRhlSd,?Rmm")))]
 329   ""
 330   "xor.b\t%x2,%0"
 331   [(set_attr "flags" "sz,sz,sz,sz")]
 332   )
 333
 334 (define_insn "xorhi3"
 335   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm")
 336         (xor:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0")
 337                 (match_operand:HI 2 "mrai_operand" "iRhiSd,?Rmm,iRhiSd,?Rmm")))]
 338   ""
 339   "xor.w\t%X2,%0"
 340   [(set_attr "flags" "sz,sz,sz,sz")]
 341   )
 342
 343 (define_insn "xorsi3"
 344   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
 345         (xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
 346                 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
 347   ""
 348   "*
 349   switch (which_alternative)
 350     {
 351     case 0:
 352       output_asm_insn (\"xor.w %X2,%h0\",operands);
 353       operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
 354       return \"xor.w %X2,%H0\";
 355     case 1:
 356       return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
 357     case 2:
 358       output_asm_insn (\"xor.w %X2,%h0\",operands);
 359       operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
 360       return \"xor.w %X2,%H0\";
 361     case 3:
 362       return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
 363     case 4:
 364       return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
 365     case 5:
 366       return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
 367     default:
 368       gcc_unreachable ();
 369     }"
 370   [(set_attr "flags" "x,x,x,x,x,x")]
 371 )
 372
 373 (define_insn "one_cmplqi2"
 374   [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
 375         (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]
 376   ""
 377   "not.b\t%0"
 378   [(set_attr "flags" "sz,sz")]
 379   )
 380
 381 (define_insn "one_cmplhi2"
 382   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
 383         (not:HI (match_operand:HI 1 "mra_operand" "0,0")))]
 384   ""
 385   "not.w\t%0"
 386   [(set_attr "flags" "sz,sz")]
 387   )
 388
 389 ; Optimizations using bit opcodes
 390
 391 ; We need this because combine only looks at three insns at a time,
 392 ; and the bclr_qi pattern uses four - mov, shift, not, and.  GCC
 393 ; should never expand this pattern, because it only shifts a constant
 394 ; by a constant, so gcc should do that itself.
 395 (define_insn "shift1_qi"
 396   [(set (match_operand:QI 0 "mra_operand" "=Rqi")
 397         (ashift:QI (const_int 1)
 398                    (match_operand 1 "const_int_operand" "In4")))]
 399   ""
 400   "mov.b\t#1,%0\n\tshl.b\t%1,%0"
 401   )
 402 (define_insn "shift1_hi"
 403   [(set (match_operand:HI 0 "mra_operand" "=Rhi")
 404         (ashift:HI (const_int 1)
 405                    (match_operand 1 "const_int_operand" "In4")))]
 406   ""
 407   "mov.w\t#1,%0\n\tshl.w\t%1,%0"
 408   )
 409
 410 ; Generic insert-bit expander, needed so that we can use the bit
 411 ; opcodes for volatile bitfields.
 412
 413 (define_expand "insv"
 414   [(set (zero_extract:HI (match_operand:HI 0 "mra_operand" "")
 415                          (match_operand 1 "const_int_operand" "")
 416                          (match_operand 2 "const_int_operand" ""))
 417         (match_operand:HI 3 "const_int_operand" ""))]
 418   ""
 419   "if (m32c_expand_insv (operands))
 420      FAIL;
 421    DONE;"
 422   )