gcc/config/loongarch/constraints.md

   1 ;; Constraint definitions for LoongArch.
   2 ;; Copyright (C) 2021-2023 Free Software Foundation, Inc.
   3 ;; Contributed by Loongson Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Register constraints
  22
  23 ;; "a" <-----unused
  24 ;; "b" "A constant call not local address."
  25 ;; "c" "A constant call local address."
  26 ;; "d" <-----unused
  27 ;; "e" JIRL_REGS
  28 ;; "f" FP_REGS
  29 ;; "g" <-----unused
  30 ;; "h" <-----unused
  31 ;; "i" "Matches a general integer constant." (Global non-architectural)
  32 ;; "j" SIBCALL_REGS
  33 ;; "k" "A memory operand whose address is formed by a base register and
  34 ;;      (optionally scaled) index register."
  35 ;; "l" "A signed 16-bit constant."
  36 ;; "m" "A memory operand whose address is formed by a base register and offset
  37 ;;      that is suitable for use in instructions with the same addressing mode
  38 ;;      as @code{st.w} and @code{ld.w}."
  39 ;; "n" "Matches a non-symbolic integer constant." (Global non-architectural)
  40 ;; "o" "Matches an offsettable memory reference." (Global non-architectural)
  41 ;; "p" "Matches a general address." (Global non-architectural)
  42 ;; "q" CSR_REGS
  43 ;; "r" GENERAL_REGS (Global non-architectural)
  44 ;; "s" "Matches a symbolic integer constant." (Global non-architectural)
  45 ;; "t" <-----unused
  46 ;; "u" "A signed 52bit constant and low 32-bit is zero (for logic instructions)"
  47 ;; "v" "A signed 64-bit constant and low 44-bit is zero (for logic instructions)."
  48 ;; "w" "Matches any valid memory."
  49 ;; "x" <-----unused
  50 ;; "y" <-----unused
  51 ;; "z" FCC_REGS
  52 ;; "A" <-----unused
  53 ;; "B" <-----unused
  54 ;; "C" <-----unused
  55 ;; "D" <-----unused
  56 ;; "E" "Matches a floating-point constant." (Global non-architectural)
  57 ;; "F" "Matches a floating-point constant." (Global non-architectural)
  58 ;; "G" "Floating-point zero."
  59 ;; "H" <-----unused
  60 ;; "I" "A signed 12-bit constant (for arithmetic instructions)."
  61 ;; "J" "Integer zero."
  62 ;; "K" "An unsigned 12-bit constant (for logic instructions)."
  63 ;; "L" -
  64 ;;     "La"
  65 ;;       "A signed constant in [-4096, 2048) or (2047, 4094]."
  66 ;;     "Lb"
  67 ;;       "A signed 32-bit constant and low 16-bit is zero, which can be
  68 ;;        added onto a register with addu16i.d.  It matches nothing if
  69 ;;        the addu16i.d instruction is not available."
  70 ;;     "Lc"
  71 ;;       "A signed 64-bit constant can be expressed as Lb + I, but not a
  72 ;;        single Lb or I."
  73 ;;     "Ld"
  74 ;;       "A signed 64-bit constant can be expressed as Lb + Lb, but not a
  75 ;;        single Lb."
  76 ;;     "Le"
  77 ;;       "A signed 32-bit constant can be expressed as Lb + I, but not a
  78 ;;        single Lb or I."
  79 ;; "M" "A constant that cannot be loaded using @code{lui}, @code{addiu}
  80 ;;      or @code{ori}."
  81 ;; "N" "A constant in the range -65535 to -1 (inclusive)."
  82 ;; "O" "A signed 15-bit constant."
  83 ;; "P" "A constant in the range 1 to 65535 (inclusive)."
  84 ;; "Q" <-----unused
  85 ;; "R" "An address that can be used in a non-macro load or store."
  86 ;; "S" <-----unused
  87 ;; "T" <-----unused
  88 ;; "U" <-----unused
  89 ;; "V" "Matches a non-offsettable memory reference." (Global non-architectural)
  90 ;; "W" <-----unused
  91 ;; "X" "Matches anything." (Global non-architectural)
  92 ;; "Y" -
  93 ;;    "Yd"
  94 ;;       "A constant @code{move_operand} that can be safely loaded using
  95 ;;        @code{la}."
  96 ;;    "Yx"
  97 ;; "Z" -
  98 ;;    "ZC"
  99 ;;      "A memory operand whose address is formed by a base register and offset
 100 ;;       that is suitable for use in instructions with the same addressing mode
 101 ;;       as @code{ll.w} and @code{sc.w}."
 102 ;;    "ZB"
 103 ;;      "An address that is held in a general-purpose register.
 104 ;;      The offset is zero"
 105 ;;    "ZD"
 106 ;;      "An address operand whose address is formed by a base register
 107 ;;       and offset that is suitable for use in instructions with the same
 108 ;;       addressing mode as @code{preld}."
 109 ;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural)
 110 ;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural)
 111
 112 (define_constraint "b"
 113   "@internal
 114    A constant call no local address."
 115   (match_operand 0 "is_const_call_no_local_symbol"))
 116
 117 (define_constraint "c"
 118   "@internal
 119    A constant call local address."
 120   (match_operand 0 "is_const_call_local_symbol"))
 121
 122 (define_register_constraint "e" "JIRL_REGS"
 123   "@internal")
 124
 125 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
 126   "A floating-point register (if available).")
 127
 128 (define_register_constraint "j" "SIBCALL_REGS"
 129   "@internal")
 130
 131 (define_memory_constraint "k"
 132   "A memory operand whose address is formed by a base register and (optionally scaled)
 133    index register."
 134   (and (match_code "mem")
 135        (match_test "loongarch_base_index_address_p (XEXP (op, 0), mode)")))
 136
 137 (define_constraint "l"
 138 "A signed 16-bit constant."
 139 (and (match_code "const_int")
 140      (match_test "IMM16_OPERAND (ival)")))
 141
 142 (define_memory_constraint "m"
 143   "A memory operand whose address is formed by a base register and offset
 144    that is suitable for use in instructions with the same addressing mode
 145    as @code{st.w} and @code{ld.w}."
 146   (and (match_code "mem")
 147        (match_test "loongarch_12bit_offset_address_p (XEXP (op, 0), mode)")))
 148
 149 (define_register_constraint "q" "CSR_REGS"
 150   "A general-purpose register except for $r0 and $r1 for lcsr.")
 151
 152 (define_constraint "u"
 153   "A signed 52bit constant and low 32-bit is zero (for logic instructions)."
 154   (and (match_code "const_int")
 155        (match_test "LU32I_OPERAND (ival)")))
 156
 157 (define_constraint "v"
 158   "A signed 64-bit constant and low 44-bit is zero (for logic instructions)."
 159   (and (match_code "const_int")
 160        (match_test "LU52I_OPERAND (ival)")))
 161
 162 (define_register_constraint "z" "FCC_REGS"
 163   "A floating-point condition code register.")
 164
 165 ;; Floating-point constraints
 166
 167 (define_constraint "G"
 168   "Floating-point zero."
 169   (and (match_code "const_double")
 170        (match_test "op == CONST0_RTX (mode)")))
 171
 172 ;; Integer constraints
 173
 174 (define_constraint "I"
 175   "A signed 12-bit constant (for arithmetic instructions)."
 176   (and (match_code "const_int")
 177        (match_test "IMM12_OPERAND (ival)")))
 178
 179 (define_constraint "J"
 180   "Integer zero."
 181   (and (match_code "const_int")
 182        (match_test "ival == 0")))
 183
 184 (define_constraint "K"
 185   "An unsigned 12-bit constant (for logic instructions)."
 186   (and (match_code "const_int")
 187        (match_test "IMM12_OPERAND_UNSIGNED (ival)")))
 188
 189 (define_constraint "La"
 190   "A signed constant in [-4096, 2048) or (2047, 4094]."
 191   (and (match_code "const_int")
 192        (match_test "DUAL_IMM12_OPERAND (ival)")))
 193
 194 (define_constraint "Lb"
 195   "A signed 32-bit constant and low 16-bit is zero, which can be added
 196    onto a register with addu16i.d."
 197   (and (match_code "const_int")
 198        (match_test "ADDU16I_OPERAND (ival)")))
 199
 200 (define_constraint "Lc"
 201   "A signed 64-bit constant can be expressed as Lb + I, but not a single Lb
 202    or I."
 203   (and (match_code "const_int")
 204        (match_test "loongarch_addu16i_imm12_operand_p (ival, DImode)")))
 205
 206 (define_constraint "Ld"
 207   "A signed 64-bit constant can be expressed as Lb + Lb, but not a single
 208    Lb."
 209   (and (match_code "const_int")
 210        (match_test "DUAL_ADDU16I_OPERAND (ival)")))
 211
 212 (define_constraint "Le"
 213   "A signed 32-bit constant can be expressed as Lb + I, but not a single Lb
 214    or I."
 215   (and (match_code "const_int")
 216        (match_test "loongarch_addu16i_imm12_operand_p (ival, SImode)")))
 217
 218 (define_constraint "M"
 219   "A constant that cannot be loaded using @code{lui}, @code{addiu}
 220    or @code{ori}."
 221   (and (match_code "const_int")
 222        (not (match_test "IMM12_OPERAND (ival)"))
 223        (not (match_test "IMM12_OPERAND_UNSIGNED (ival)"))
 224        (not (match_test "LU12I_OPERAND (ival)"))))
 225
 226 (define_constraint "N"
 227   "A constant in the range -65535 to -1 (inclusive)."
 228   (and (match_code "const_int")
 229        (match_test "ival >= -0xffff && ival < 0")))
 230
 231 (define_constraint "O"
 232   "A signed 15-bit constant."
 233   (and (match_code "const_int")
 234        (match_test "ival >= -0x4000 && ival < 0x4000")))
 235
 236 (define_constraint "P"
 237   "A constant in the range 1 to 65535 (inclusive)."
 238   (and (match_code "const_int")
 239        (match_test "ival > 0 && ival < 0x10000")))
 240
 241 ;; General constraints
 242
 243 (define_memory_constraint "R"
 244   "An address that can be used in a non-macro load or store."
 245   (and (match_code "mem")
 246        (match_test "loongarch_address_insns (XEXP (op, 0), mode, false) == 1")))
 247 (define_constraint "S"
 248   "@internal
 249    A constant call address."
 250   (and (match_operand 0 "call_insn_operand")
 251        (match_test "CONSTANT_P (op)")))
 252
 253 (define_constraint "YG"
 254   "@internal
 255    A vector zero."
 256   (and (match_code "const_vector")
 257        (match_test "op == CONST0_RTX (mode)")))
 258
 259 (define_constraint "YA"
 260   "@internal
 261    An unsigned 6-bit constant."
 262   (and (match_code "const_int")
 263        (match_test "UIMM6_OPERAND (ival)")))
 264
 265 (define_constraint "YB"
 266   "@internal
 267    A signed 10-bit constant."
 268   (and (match_code "const_int")
 269        (match_test "IMM10_OPERAND (ival)")))
 270
 271 (define_constraint "Yb"
 272    "@internal"
 273    (match_operand 0 "qi_mask_operand"))
 274
 275 (define_constraint "Yd"
 276   "@internal
 277    A constant @code{move_operand} that can be safely loaded using
 278    @code{la}."
 279   (and (match_operand 0 "move_operand")
 280        (match_test "CONSTANT_P (op)")))
 281
 282 (define_constraint "Yh"
 283    "@internal"
 284     (match_operand 0 "hi_mask_operand"))
 285
 286 (define_constraint "Yw"
 287    "@internal"
 288     (match_operand 0 "si_mask_operand"))
 289
 290 (define_constraint "Yx"
 291    "@internal"
 292    (match_operand 0 "low_bitmask_operand"))
 293
 294 (define_constraint "YI"
 295   "@internal
 296    A replicated vector const in which the replicated value is in the range
 297    [-512,511]."
 298   (and (match_code "const_vector")
 299        (match_test "loongarch_const_vector_same_int_p (op, mode, -512, 511)")))
 300
 301 (define_constraint "YC"
 302   "@internal
 303    A replicated vector const in which the replicated value has a single
 304    bit set."
 305   (and (match_code "const_vector")
 306        (match_test "loongarch_const_vector_bitimm_set_p (op, mode)")))
 307
 308 (define_constraint "YZ"
 309   "@internal
 310    A replicated vector const in which the replicated value has a single
 311    bit clear."
 312   (and (match_code "const_vector")
 313        (match_test "loongarch_const_vector_bitimm_clr_p (op, mode)")))
 314
 315 (define_constraint "Unv5"
 316   "@internal
 317    A replicated vector const in which the replicated value is in the range
 318    [-31,0]."
 319   (and (match_code "const_vector")
 320        (match_test "loongarch_const_vector_same_int_p (op, mode, -31, 0)")))
 321
 322 (define_constraint "Uuv5"
 323   "@internal
 324    A replicated vector const in which the replicated value is in the range
 325    [0,31]."
 326   (and (match_code "const_vector")
 327        (match_test "loongarch_const_vector_same_int_p (op, mode, 0, 31)")))
 328
 329 (define_constraint "Usv5"
 330   "@internal
 331    A replicated vector const in which the replicated value is in the range
 332    [-16,15]."
 333   (and (match_code "const_vector")
 334        (match_test "loongarch_const_vector_same_int_p (op, mode, -16, 15)")))
 335
 336 (define_constraint "Uuv6"
 337   "@internal
 338    A replicated vector const in which the replicated value is in the range
 339    [0,63]."
 340   (and (match_code "const_vector")
 341        (match_test "loongarch_const_vector_same_int_p (op, mode, 0, 63)")))
 342
 343 (define_constraint "Urv8"
 344   "@internal
 345    A replicated vector const with replicated byte values as well as elements"
 346   (and (match_code "const_vector")
 347        (match_test "loongarch_const_vector_same_bytes_p (op, mode)")))
 348
 349 (define_memory_constraint "ZC"
 350   "A memory operand whose address is formed by a base register and offset
 351    that is suitable for use in instructions with the same addressing mode
 352    as @code{ll.w} and @code{sc.w}."
 353   (and (match_code "mem")
 354        (match_test "loongarch_14bit_shifted_offset_address_p (XEXP (op, 0), mode)")))
 355
 356 (define_memory_constraint "ZB"
 357   "@internal
 358   An address that is held in a general-purpose register.
 359   The offset is zero"
 360   (and (match_code "mem")
 361        (match_test "REG_P (XEXP (op, 0))")))
 362
 363 (define_address_constraint "ZD"
 364   "An address operand whose address is formed by a base register
 365    and offset that is suitable for use in instructions with the same
 366    addressing mode as @code{preld}."
 367    (match_test "loongarch_12bit_offset_address_p (op, mode)"))