1 ;; IA-
64 Machine description template
2 ;; Copyright (C)
1999,
2000 Free Software Foundation, Inc.
3 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
4 ;; David Mosberger <davidm@hpl.hp.com>.
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version
2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
21 ;; Boston, MA
02111-
1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26 ;; reload. This will be fixed once scheduling support is turned on.
28 ;; ??? Optimize for post-increment addressing modes.
30 ;; ??? fselect is not supported, because there is no integer register
33 ;; ??? fp abs/min/max instructions may also work for integer values.
35 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36 ;; it assumes the operand is a register and takes REGNO of it without checking.
38 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39 ;; it assumes the operand is a register and takes REGNO of it without checking.
41 ;; ??? Go through list of documented named patterns and look for more to
44 ;; ??? Go through instruction manual and look for more instructions that
47 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
49 ;; ??? The explicit stop in the flushrs pattern is not ideal. It
50 ;; would be better if rtx_needs_barrier took care of this, but this is
51 ;; something that can be fixed later.
53 ;; ??? Need a better way to describe alternate fp status registers.
74 ;;
2 insn_group_barrier
76 ;;
8 pred.safe_across_calls all
77 ;;
9 pred.safe_across_calls normal
79 ;; ::::::::::::::::::::
83 ;; ::::::::::::::::::::
85 ;; Instruction type. This primarily determines how instructions can be
86 ;; packed in bundles, and secondarily affects scheduling to function units.
88 ;; A alu, can go in I or M syllable of a bundle
93 ;; L long immediate, takes two syllables
96 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
97 ;; check this in md_reorg? Currently use unknown for patterns which emit
98 ;; multiple instructions, patterns which emit
0 instructions, and patterns
99 ;; which emit instruction that can go in any slot (e.g. nop).
101 (define_attr "type" "unknown,A,I,M,F,B,L,S" (const_string "unknown"))
103 ;; Predication. True iff this instruction can be predicated.
105 (define_attr "predicable" "no,yes" (const_string "yes"))
108 ;; ::::::::::::::::::::
112 ;; ::::::::::::::::::::
114 ;; Each usage of a function units by a class of insns is specified with a
115 ;;
`define_function_unit' expression, which looks like this:
116 ;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY TEST READY-DELAY
117 ;; ISSUE-DELAY [CONFLICT-LIST])
119 ;; This default scheduling info seeks to pack instructions into bundles
120 ;; efficiently to reduce code size, so we just list how many of each
121 ;; instruction type can go in a bundle. ISSUE_RATE is set to 3.
123 ;; ??? Add scheduler ready-list hook (MD_SCHED_REORDER) that orders
124 ;; instructions, so that the next instruction can fill the next bundle slot.
125 ;; This really needs to know where the stop bits are though.
127 ;; ??? Use MD_SCHED_REORDER to put alloc first instead of using an unspec
128 ;; volatile. Use ADJUST_PRIORITY to set the priority of alloc very high to
129 ;; make it schedule first.
131 ;; ??? Modify the md_reorg code that emits stop bits so that instead of putting
132 ;; them in the last possible place, we put them in places where bundles allow
133 ;; them. This should reduce code size, but may decrease performance if we end
134 ;; up with more stop bits than the minimum we need.
136 ;; Alu instructions can execute on either the integer or memory function
137 ;; unit. We indicate this by defining an alu function unit, and then marking
138 ;; it as busy everytime we issue a integer or memory type instruction.
140 (define_function_unit "alu" 3 1 (eq_attr "type" "A,I,M") 1 0)
142 (define_function_unit "integer" 2 1 (eq_attr "type" "I") 1 0)
144 (define_function_unit "memory" 3 1 (eq_attr "type" "M") 1 0)
146 (define_function_unit "floating_point" 1 1 (eq_attr "type" "F") 1 0)
148 (define_function_unit "branch" 3 1 (eq_attr "type" "B") 1 0)
150 ;; ??? This isn't quite right, because we can only fit two insns in a bundle
151 ;; when using an L type instruction. That isn't modeled currently.
153 (define_function_unit "long_immediate" 1 1 (eq_attr "type" "L") 1 0)
156 ;; ::::::::::::::::::::
160 ;; ::::::::::::::::::::
162 ;; Set of a single predicate register. This is only used to implement
163 ;; pr-to-pr move and complement.
165 (define_insn "*movcci"
166 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
167 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
170 cmp.ne %0, p0 = r0, r0
171 cmp.eq %0, p0 = r0, r0
172 (%1) cmp.eq.unc %0, p0 = r0, r0"
173 [(set_attr "type" "A")
174 (set_attr "predicable" "no")])
177 [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m")
178 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r"))]
181 cmp.ne %0, %I0 = r0, r0
182 cmp.eq %0, %I0 = r0, r0
185 tbit.nz %0, %I0 = %1, 0
189 [(set_attr "type" "A,A,unknown,unknown,I,A,M,M")])
192 [(set (match_operand:BI 0 "register_operand" "")
193 (match_operand:BI 1 "register_operand" ""))]
195 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
196 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
197 [(cond_exec (ne (match_dup 1) (const_int 0))
198 (set (match_dup 0) (const_int 1)))
199 (cond_exec (eq (match_dup 1) (const_int 0))
200 (set (match_dup 0) (const_int 0)))]
204 [(set (match_operand:BI 0 "register_operand" "")
205 (match_operand:BI 1 "register_operand" ""))]
207 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
208 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
209 [(set (match_dup 2) (match_dup 4))
210 (set (match_dup 3) (match_dup 5))
211 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
212 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
213 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
214 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
215 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
217 (define_expand "movqi"
218 [(set (match_operand:QI 0 "general_operand" "")
219 (match_operand:QI 1 "general_operand" ""))]
223 if (! reload_in_progress && ! reload_completed
224 && ! ia64_move_ok (operands[0], operands[1]))
225 operands[1] = force_reg (QImode, operands[1]);
228 ;; Errata 72 implies that we cannot use predicated loads and stores
229 ;; on affected systems. Reuse TARGET_A_STEP for convenience.
231 ;; ??? It would be convenient at this point if the cond_exec pattern
232 ;; expander understood non-constant conditions on attributes. Failing
233 ;; that we have to replicate patterns.
235 (define_insn "*movqicc_astep"
237 (match_operator 2 "predicate_operator"
238 [(match_operand:BI 3 "register_operand" "c,c,c,c,c")
240 (set (match_operand:QI 0 "register_operand" "=r,r, r,*f,*f")
241 (match_operand:QI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
242 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
245 (%J2) addl %0 = %1, r0
246 (%J2) getf.sig %0 = %1
247 (%J2) setf.sig %0 = %r1
249 [(set_attr "type" "A,A,M,M,F")
250 (set_attr "predicable" "no")])
252 (define_insn "*movqi_internal_astep"
253 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
254 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
255 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
264 [(set_attr "type" "A,A,M,M,M,M,F")
265 (set_attr "predicable" "no")])
267 (define_insn "*movqi_internal"
268 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
269 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
270 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
279 [(set_attr "type" "A,A,M,M,M,M,F")])
281 (define_expand "movhi"
282 [(set (match_operand:HI 0 "general_operand" "")
283 (match_operand:HI 1 "general_operand" ""))]
287 if (! reload_in_progress && ! reload_completed
288 && ! ia64_move_ok (operands[0], operands[1]))
289 operands[1] = force_reg (HImode, operands[1]);
292 ;; Errata 72 workaround.
293 (define_insn "*movhicc_astep"
295 (match_operator 2 "predicate_operator"
296 [(match_operand:BI 3 "register_operand" "c,c,c,c,c")
298 (set (match_operand:HI 0 "register_operand" "=r,r, r,*f,*f")
299 (match_operand:HI 1 "nonmemory_operand" "rO,J,*f,rO,*f")))]
300 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
303 (%J2) addl %0 = %1, r0
304 (%J2) getf.sig %0 = %1
305 (%J2) setf.sig %0 = %r1
307 [(set_attr "type" "A,A,M,M,F")
308 (set_attr "predicable" "no")])
310 (define_insn "*movhi_internal_astep"
311 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
312 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
313 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
322 [(set_attr "type" "A,A,M,M,M,M,F")
323 (set_attr "predicable" "no")])
325 (define_insn "*movhi_internal"
326 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
327 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
328 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
337 [(set_attr "type" "A,A,M,M,M,M,F")])
339 (define_expand "movsi"
340 [(set (match_operand:SI 0 "general_operand" "")
341 (match_operand:SI 1 "general_operand" ""))]
345 if (! reload_in_progress && ! reload_completed
346 && ! ia64_move_ok (operands[0], operands[1]))
347 operands[1] = force_reg (SImode, operands[1]);
350 ;; Errata 72 workaround.
351 (define_insn "*movsicc_astep"
353 (match_operator 2 "predicate_operator"
354 [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c")
356 (set (match_operand:SI 0 "register_operand" "=r,r,r, r,*f,*f, r,*d")
357 (match_operand:SI 1 "nonmemory_operand" "rO,J,i,*f,rO,*f,*d,rK")))]
358 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
361 (%J2) addl %0 = %1, r0
363 (%J2) getf.sig %0 = %1
364 (%J2) setf.sig %0 = %r1
368 [(set_attr "type" "A,A,L,M,M,F,M,M")
369 (set_attr "predicable" "no")])
371 (define_insn "*movsi_internal_astep"
372 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
373 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
374 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
386 [(set_attr "type" "A,A,L,M,M,M,M,F,M,M")
387 (set_attr "predicable" "no")])
389 (define_insn "*movsi_internal"
390 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
391 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
392 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
404 [(set_attr "type" "A,A,L,M,M,M,M,F,M,M")])
406 (define_expand "movdi"
407 [(set (match_operand:DI 0 "general_operand" "")
408 (match_operand:DI 1 "general_operand" ""))]
412 if (! reload_in_progress && ! reload_completed
413 && ! ia64_move_ok (operands[0], operands[1]))
414 operands[1] = force_reg (DImode, operands[1]);
415 if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode))
417 /* Before optimization starts, delay committing to any particular
418 type of PIC address load. If this function gets deferred, we
419 may acquire information that changes the value of the
420 sdata_symbolic_operand predicate. */
421 /* But don't delay for function pointers. Loading a function address
422 actually loads the address of the descriptor not the function.
423 If we represent these as SYMBOL_REFs, then they get cse'd with
424 calls, and we end up with calls to the descriptor address instead of
425 calls to the function address. Functions are not candidates for
427 if (rtx_equal_function_value_matters
428 && ! (GET_CODE (operands[1]) == SYMBOL_REF
429 && SYMBOL_REF_FLAG (operands[1])))
430 emit_insn (gen_movdi_symbolic (operands[0], operands[1]));
432 ia64_expand_load_address (operands[0], operands[1]);
437 ;; Errata 72 workaround.
440 (match_operator 2 "predicate_operator"
441 [(match_operand:BI 3 "register_operand" "c,c,c,c,c,c,c,c,c,c,c")
443 (set (match_operand:DI 0 "register_operand"
444 "=r,r,r, r,*f,*f, r,*b,*e, r,*d")
445 (match_operand:DI 1 "nonmemory_operand"
446 "rO,J,i,*f,rO,*f,*b*e,rO,rK,*d,rK")))]
447 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
450 static const char * const alt[] = {
451 \"(%J2) mov %0 = %r1\",
452 \"(%J2) addl %0 = %1, r0\",
453 \"(%J2) movl %0 = %1\",
454 \"(%J2) getf.sig %0 = %1\",
455 \"(%J2) setf.sig %0 = %r1\",
456 \"(%J2) mov %0 = %1\",
457 \"(%J2) mov %0 = %1\",
458 \"(%J2) mov %0 = %r1\",
459 \"(%J2) mov %0 = %1\",
460 \"(%J2) mov %0 = %1\",
461 \"(%J2) mov %0 = %1\"
464 /* We use 'i' for alternative 2 despite possible PIC problems.
466 If we define LEGITIMATE_CONSTANT_P such that symbols are not
467 allowed, then the compiler dumps the data into constant memory
468 instead of letting us read the values from the GOT. Similarly
469 if we use 'n' instead of 'i'.
471 Instead, we allow such insns through reload and then split them
472 afterward (even without optimization). Therefore, we should
473 never get so far with a symbolic operand. */
475 if (which_alternative == 2 && ! TARGET_NO_PIC
476 && symbolic_operand (operands[1], VOIDmode))
479 return alt[which_alternative];
481 [(set_attr "type" "A,A,L,M,M,F,I,I,I,M,M")
482 (set_attr "predicable" "no")])
484 ;; This is used during early compilation to delay the decision on
485 ;; how to refer to a variable as long as possible. This is especially
486 ;; important between initial rtl generation and optimization for
487 ;; deferred functions, since we may acquire additional information
488 ;; on the variables used in the meantime.
490 (define_insn_and_split "movdi_symbolic"
491 [(set (match_operand:DI 0 "register_operand" "=r")
492 (match_operand:DI 1 "symbolic_operand" "s"))
498 "ia64_expand_load_address (operands[0], operands[1]); DONE;")
500 (define_insn "*movdi_internal_astep"
501 [(set (match_operand:DI 0 "destination_operand"
502 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b,*e, r,*d, r,*c")
503 (match_operand:DI 1 "move_operand"
504 "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,rO,rK,*d,rK,*c,rO"))]
505 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
508 static const char * const alt[] = {
510 \"addl %0 = %1, r0\",
512 \"ld8%O1 %0 = %1%P1\",
513 \"st8%Q0 %0 = %r1%P0\",
514 \"getf.sig %0 = %1\",
515 \"setf.sig %0 = %r1\",
528 if (which_alternative == 2 && ! TARGET_NO_PIC
529 && symbolic_operand (operands[1], VOIDmode))
532 return alt[which_alternative];
534 [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,I,M,M,I,I")
535 (set_attr "predicable" "no")])
537 (define_insn "*movdi_internal"
538 [(set (match_operand:DI 0 "destination_operand"
539 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b,*e, r,*d, r,*c")
540 (match_operand:DI 1 "move_operand"
541 "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b*e,rO,rK,*d,rK,*c,rO"))]
542 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
545 static const char * const alt[] = {
547 \"%,addl %0 = %1, r0\",
549 \"%,ld8%O1 %0 = %1%P1\",
550 \"%,st8%Q0 %0 = %r1%P0\",
551 \"%,getf.sig %0 = %1\",
552 \"%,setf.sig %0 = %r1\",
554 \"%,ldf8 %0 = %1%P1\",
555 \"%,stf8 %0 = %1%P0\",
565 if (which_alternative == 2 && ! TARGET_NO_PIC
566 && symbolic_operand (operands[1], VOIDmode))
569 return alt[which_alternative];
571 [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I,I,M,M,I,I")])
574 [(set (match_operand:DI 0 "register_operand" "")
575 (match_operand:DI 1 "symbolic_operand" ""))]
576 "reload_completed && ! TARGET_NO_PIC"
580 ia64_expand_load_address (operands[0], operands[1]);
584 (define_expand "load_fptr"
586 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "")))
587 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
591 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
592 operands[3] = gen_rtx_MEM (DImode, operands[2]);
593 RTX_UNCHANGING_P (operands[3]) = 1;
596 (define_insn "*load_fptr_internal1"
597 [(set (match_operand:DI 0 "register_operand" "=r")
598 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))]
600 "addl %0 = @ltoff(@fptr(%1)), gp"
601 [(set_attr "type" "A")])
603 (define_insn "load_gprel"
604 [(set (match_operand:DI 0 "register_operand" "=r")
605 (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))]
607 "addl %0 = @gprel(%1), gp"
608 [(set_attr "type" "A")])
610 (define_insn "gprel64_offset"
611 [(set (match_operand:DI 0 "register_operand" "=r")
612 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
614 "movl %0 = @gprel(%1)"
615 [(set_attr "type" "L")])
617 (define_expand "load_gprel64"
619 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))
620 (set (match_operand:DI 0 "register_operand" "")
621 (plus:DI (reg:DI 1) (match_dup 2)))]
625 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
628 (define_expand "load_symptr"
630 (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "")))
631 (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
635 operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
636 operands[3] = gen_rtx_MEM (DImode, operands[2]);
637 RTX_UNCHANGING_P (operands[3]) = 1;
640 (define_insn "*load_symptr_internal1"
641 [(set (match_operand:DI 0 "register_operand" "=r")
642 (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))]
644 "addl %0 = @ltoff(%1), gp"
645 [(set_attr "type" "A")])
647 ;; With no offsettable memory references, we've got to have a scratch
648 ;; around to play with the second word.
649 (define_expand "movti"
650 [(parallel [(set (match_operand:TI 0 "general_operand" "")
651 (match_operand:TI 1 "general_operand" ""))
652 (clobber (match_scratch:DI 2 ""))])]
656 if (! reload_in_progress && ! reload_completed
657 && ! ia64_move_ok (operands[0], operands[1]))
658 operands[1] = force_reg (TImode, operands[1]);
661 (define_insn_and_split "*movti_internal"
662 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
663 (match_operand:TI 1 "general_operand" "ri,m,r"))
664 (clobber (match_scratch:DI 2 "=X,&r,&r"))]
665 "ia64_move_ok (operands[0], operands[1])"
671 rtx adj1, adj2, in[2], out[2];
674 adj1 = ia64_split_timode (in, operands[1], operands[2]);
675 adj2 = ia64_split_timode (out, operands[0], operands[2]);
678 if (reg_overlap_mentioned_p (out[0], in[1]))
680 if (reg_overlap_mentioned_p (out[1], in[0]))
691 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
692 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
695 [(set_attr "type" "unknown")
696 (set_attr "predicable" "no")])
698 ;; ??? SSA creates these. Can't allow memories since we don't have
699 ;; the scratch register. Fortunately combine will know how to add
700 ;; the clobber and scratch.
701 (define_insn_and_split "*movti_internal_reg"
702 [(set (match_operand:TI 0 "register_operand" "=r")
703 (match_operand:TI 1 "nonmemory_operand" "ri"))]
713 ia64_split_timode (in, operands[1], NULL_RTX);
714 ia64_split_timode (out, operands[0], NULL_RTX);
717 if (reg_overlap_mentioned_p (out[0], in[1]))
719 if (reg_overlap_mentioned_p (out[1], in[0]))
724 emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
725 emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
728 [(set_attr "type" "unknown")
729 (set_attr "predicable" "no")])
731 (define_expand "reload_inti"
732 [(parallel [(set (match_operand:TI 0 "register_operand" "=r")
733 (match_operand:TI 1 "" "m"))
734 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
738 unsigned int s_regno = REGNO (operands[2]);
739 if (s_regno == REGNO (operands[0]))
741 operands[2] = gen_rtx_REG (DImode, s_regno);
744 (define_expand "reload_outti"
745 [(parallel [(set (match_operand:TI 0 "" "=m")
746 (match_operand:TI 1 "register_operand" "r"))
747 (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
751 unsigned int s_regno = REGNO (operands[2]);
752 if (s_regno == REGNO (operands[1]))
754 operands[2] = gen_rtx_REG (DImode, s_regno);
757 ;; Floating Point Moves
759 ;; Note - Patterns for SF mode moves are compulsory, but
760 ;; patterns for DF are optional, as GCC can synthesise them.
762 (define_expand "movsf"
763 [(set (match_operand:SF 0 "general_operand" "")
764 (match_operand:SF 1 "general_operand" ""))]
768 if (! reload_in_progress && ! reload_completed
769 && ! ia64_move_ok (operands[0], operands[1]))
770 operands[1] = force_reg (SFmode, operands[1]);
773 ;; Errata 72 workaround.
774 (define_insn "*movsfcc_astep"
776 (match_operator 2 "predicate_operator"
777 [(match_operand:BI 3 "register_operand" "c,c,c,c")
779 (set (match_operand:SF 0 "register_operand" "=f,*r, f,*r")
780 (match_operand:SF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
781 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
784 (%J2) getf.s %0 = %F1
787 [(set_attr "type" "F,M,M,A")
788 (set_attr "predicable" "no")])
790 (define_insn "*movsf_internal_astep"
791 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
792 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
793 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
803 [(set_attr "type" "F,M,M,M,M,A,M,M")
804 (set_attr "predicable" "no")])
806 (define_insn "*movsf_internal"
807 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
808 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
809 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
819 [(set_attr "type" "F,M,M,M,M,A,M,M")])
821 (define_expand "movdf"
822 [(set (match_operand:DF 0 "general_operand" "")
823 (match_operand:DF 1 "general_operand" ""))]
827 if (! reload_in_progress && ! reload_completed
828 && ! ia64_move_ok (operands[0], operands[1]))
829 operands[1] = force_reg (DFmode, operands[1]);
832 ;; Errata 72 workaround.
833 (define_insn "*movdfcc_astep"
835 (match_operator 2 "predicate_operator"
836 [(match_operand:BI 3 "register_operand" "c,c,c,c")
838 (set (match_operand:DF 0 "register_operand" "=f,*r, f,*r")
839 (match_operand:DF 1 "nonmemory_operand" "fG,fG,*r,*r")))]
840 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
843 (%J2) getf.d %0 = %F1
846 [(set_attr "type" "F,M,M,A")
847 (set_attr "predicable" "no")])
849 (define_insn "*movdf_internal_astep"
850 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
851 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
852 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
862 [(set_attr "type" "F,M,M,M,M,A,M,M")
863 (set_attr "predicable" "no")])
865 (define_insn "*movdf_internal"
866 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
867 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
868 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
878 [(set_attr "type" "F,M,M,M,M,A,M,M")])
880 ;; With no offsettable memory references, we've got to have a scratch
881 ;; around to play with the second word if the variable winds up in GRs.
882 (define_expand "movtf"
883 [(set (match_operand:TF 0 "general_operand" "")
884 (match_operand:TF 1 "general_operand" ""))]
888 /* We must support TFmode loads into general registers for stdarg/vararg
889 and unprototyped calls. We split them into DImode loads for convenience.
890 We don't need TFmode stores from general regs, because a stdarg/vararg
891 routine does a block store to memory of unnamed arguments. */
892 if (GET_CODE (operands[0]) == REG
893 && GR_REGNO_P (REGNO (operands[0])))
895 /* We're hoping to transform everything that deals with TFmode
896 quantities and GR registers early in the compiler. */
900 /* Struct to register can just use TImode instead. */
901 if ((GET_CODE (operands[1]) == SUBREG
902 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
903 || (GET_CODE (operands[1]) == REG
904 && GR_REGNO_P (REGNO (operands[1]))))
906 emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])),
907 SUBREG_REG (operands[1]));
911 if (GET_CODE (operands[1]) == CONST_DOUBLE)
913 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])),
914 operand_subword (operands[1], 0, 0, DImode));
915 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1),
916 operand_subword (operands[1], 1, 0, DImode));
920 /* If the quantity is in a register not known to be GR, spill it. */
921 if (register_operand (operands[1], TFmode))
922 operands[1] = spill_tfmode_operand (operands[1], 1);
924 if (GET_CODE (operands[1]) == MEM)
928 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0]));
929 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1);
931 emit_move_insn (out[0], change_address (operands[1], DImode, NULL));
932 emit_move_insn (out[1],
933 change_address (operands[1], DImode,
934 plus_constant (XEXP (operands[1], 0),
942 if (! reload_in_progress && ! reload_completed)
944 operands[0] = spill_tfmode_operand (operands[0], 0);
945 operands[1] = spill_tfmode_operand (operands[1], 0);
947 if (! ia64_move_ok (operands[0], operands[1]))
948 operands[1] = force_reg (TFmode, operands[1]);
952 ;; ??? There's no easy way to mind volatile acquire/release semantics.
954 ;; Errata 72 workaround.
955 (define_insn "*movtfcc_astep"
957 (match_operator 2 "predicate_operator"
958 [(match_operand:BI 3 "register_operand" "c")
960 (set (match_operand:TF 0 "register_operand" "=f")
961 (match_operand:TF 1 "nonmemory_operand" "fG")))]
962 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
964 [(set_attr "type" "F")
965 (set_attr "predicable" "no")])
967 (define_insn "*movtf_internal_astep"
968 [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
969 (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
970 "TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
975 [(set_attr "type" "F,M,M")
976 (set_attr "predicable" "no")])
978 (define_insn "*movtf_internal"
979 [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m")
980 (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))]
981 "! TARGET_A_STEP && ia64_move_ok (operands[0], operands[1])"
986 [(set_attr "type" "F,M,M")])
988 ;; ::::::::::::::::::::
992 ;; ::::::::::::::::::::
994 ;; Signed conversions from a smaller integer to a larger integer
996 (define_insn "extendqidi2"
997 [(set (match_operand:DI 0 "gr_register_operand" "=r")
998 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
1001 [(set_attr "type" "I")])
1003 (define_insn "extendhidi2"
1004 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1005 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
1008 [(set_attr "type" "I")])
1010 (define_insn "extendsidi2"
1011 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
1012 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
1016 fsxt.r %0 = %1, %1%B0"
1017 [(set_attr "type" "I,F")])
1019 ;; Unsigned conversions from a smaller integer to a larger integer
1021 (define_insn "zero_extendqidi2"
1022 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1023 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
1028 [(set_attr "type" "I,M")])
1030 (define_insn "zero_extendhidi2"
1031 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1032 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
1037 [(set_attr "type" "I,M")])
1039 (define_insn "zero_extendsidi2"
1040 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
1042 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
1047 fmix.r %0 = f0, %1%B0"
1048 [(set_attr "type" "I,M,F")])
1050 ;; Convert between floating point types of different sizes.
1052 ;; ??? Optimization opportunity here. Get rid of the insn altogether
1053 ;; when we can. Should probably use a scheme like has been proposed
1054 ;; for ia32 in dealing with operands that match unary operators. This
1055 ;; would let combine merge the thing into adjacent insns.
1057 (define_insn_and_split "extendsfdf2"
1058 [(set (match_operand:DF 0 "grfr_nonimmediate_operand" "=f,f,f,f,m,*r")
1060 (match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,m,*r,f,f")))]
1070 [(set (match_dup 0) (float_extend:DF (match_dup 1)))]
1071 "if (true_regnum (operands[0]) == true_regnum (operands[1])) DONE;"
1072 [(set_attr "type" "F,F,M,M,M,M")])
1074 (define_insn_and_split "extendsftf2"
1075 [(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
1077 (match_operand:SF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
1086 [(set (match_dup 0) (float_extend:TF (match_dup 1)))]
1087 "if (true_regnum (operands[0]) == true_regnum (operands[1])) DONE;"
1088 [(set_attr "type" "F,F,M,M,M")])
1090 (define_insn_and_split "extenddftf2"
1091 [(set (match_operand:TF 0 "fr_nonimmediate_operand" "=f,f,f,f,Q")
1093 (match_operand:DF 1 "grfr_nonimmediate_operand" "0,f,Q,*r,f")))]
1102 [(set (match_dup 0) (float_extend:TF (match_dup 1)))]
1103 "if (true_regnum (operands[0]) == true_regnum (operands[1])) DONE;"
1104 [(set_attr "type" "F,F,M,M,M")])
1106 (define_insn "truncdfsf2"
1107 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1108 (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
1110 "fnorm.s %0 = %1%B0"
1111 [(set_attr "type" "F")])
1113 (define_insn "trunctfsf2"
1114 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1115 (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))]
1117 "fnorm.s %0 = %1%B0"
1118 [(set_attr "type" "F")])
1120 (define_insn "trunctfdf2"
1121 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1122 (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))]
1124 "fnorm.d %0 = %1%B0"
1125 [(set_attr "type" "F")])
1127 ;; Convert between signed integer types and floating point.
1129 (define_insn "floatditf2"
1130 [(set (match_operand:TF 0 "fr_register_operand" "=f")
1131 (float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
1134 [(set_attr "type" "F")])
1136 (define_insn "fix_truncsfdi2"
1137 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1138 (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1140 "fcvt.fx.trunc %0 = %1%B0"
1141 [(set_attr "type" "F")])
1143 (define_insn "fix_truncdfdi2"
1144 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1145 (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1147 "fcvt.fx.trunc %0 = %1%B0"
1148 [(set_attr "type" "F")])
1150 (define_insn "fix_trunctfdi2"
1151 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1152 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
1154 "fcvt.fx.trunc %0 = %1%B0"
1155 [(set_attr "type" "F")])
1157 (define_insn "fix_trunctfdi2_alts"
1158 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1159 (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1160 (use (match_operand:SI 2 "const_int_operand" ""))]
1162 "fcvt.fx.trunc.s%2 %0 = %1%B0"
1163 [(set_attr "type" "F")])
1165 ;; Convert between unsigned integer types and floating point.
1167 (define_insn "floatunsdisf2"
1168 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1169 (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
1171 "fcvt.xuf.s %0 = %1%B0"
1172 [(set_attr "type" "F")])
1174 (define_insn "floatunsdidf2"
1175 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1176 (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
1178 "fcvt.xuf.d %0 = %1%B0"
1179 [(set_attr "type" "F")])
1181 (define_insn "floatunsditf2"
1182 [(set (match_operand:TF 0 "fr_register_operand" "=f")
1183 (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))]
1185 "fcvt.xuf %0 = %1%B0"
1186 [(set_attr "type" "F")])
1188 (define_insn "fixuns_truncsfdi2"
1189 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1190 (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
1192 "fcvt.fxu.trunc %0 = %1%B0"
1193 [(set_attr "type" "F")])
1195 (define_insn "fixuns_truncdfdi2"
1196 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1197 (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
1199 "fcvt.fxu.trunc %0 = %1%B0"
1200 [(set_attr "type" "F")])
1202 (define_insn "fixuns_trunctfdi2"
1203 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1204 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))]
1206 "fcvt.fxu.trunc %0 = %1%B0"
1207 [(set_attr "type" "F")])
1209 (define_insn "fixuns_trunctfdi2_alts"
1210 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1211 (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))
1212 (use (match_operand:SI 2 "const_int_operand" ""))]
1214 "fcvt.fxu.trunc.s%2 %0 = %1%B0"
1215 [(set_attr "type" "F")])
1217 ;; ::::::::::::::::::::
1219 ;; :: Bit field extraction
1221 ;; ::::::::::::::::::::
1224 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1225 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1226 (match_operand:DI 2 "const_int_operand" "n")
1227 (match_operand:DI 3 "const_int_operand" "n")))]
1229 "extr %0 = %1, %3, %2"
1230 [(set_attr "type" "I")])
1232 (define_insn "extzv"
1233 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1234 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1235 (match_operand:DI 2 "const_int_operand" "n")
1236 (match_operand:DI 3 "const_int_operand" "n")))]
1238 "extr.u %0 = %1, %3, %2"
1239 [(set_attr "type" "I")])
1241 ;; Insert a bit field.
1242 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1243 ;; Source1 can be 0 or -1.
1244 ;; Source2 can be 0.
1246 ;; ??? Actual dep instruction is more powerful than what these insv
1247 ;; patterns support. Unfortunately, combine is unable to create patterns
1248 ;; where source2 != dest.
1250 (define_expand "insv"
1251 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1252 (match_operand:DI 1 "const_int_operand" "")
1253 (match_operand:DI 2 "const_int_operand" ""))
1254 (match_operand:DI 3 "nonmemory_operand" ""))]
1258 int width = INTVAL (operands[1]);
1259 int shift = INTVAL (operands[2]);
1261 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1263 if (! register_operand (operands[3], DImode)
1264 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1265 operands[3] = force_reg (DImode, operands[3]);
1267 /* If this is a single dep instruction, we have nothing to do. */
1268 if (! ((register_operand (operands[3], DImode) && width <= 16)
1269 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1271 /* Check for cases that can be implemented with a mix instruction. */
1272 if (width == 32 && shift == 0)
1274 /* Directly generating the mix4left instruction confuses
1275 optimize_bit_field in function.c. Since this is performing
1276 a useful optimization, we defer generation of the complicated
1277 mix4left RTL to the first splitting phase. */
1278 rtx tmp = gen_reg_rtx (DImode);
1279 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1282 else if (width == 32 && shift == 32)
1284 emit_insn (gen_mix4right (operands[0], operands[3]));
1288 /* We could handle remaining cases by emitting multiple dep
1291 If we need more than two dep instructions then we lose. A 6
1292 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1293 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1294 the latter is 6 cycles on an Itanium (TM) processor, because there is
1295 only one function unit that can execute dep and shr immed.
1297 If we only need two dep instruction, then we still lose.
1298 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1299 the unnecessary mov, this is still undesirable because it will be
1300 hard to optimize, and it creates unnecessary pressure on the I0
1306 /* This code may be useful for other IA-64 processors, so we leave it in
1312 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1316 tmp = gen_reg_rtx (DImode);
1317 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1320 operands[1] = GEN_INT (width);
1321 operands[2] = GEN_INT (shift);
1326 (define_insn "*insv_internal"
1327 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1328 (match_operand:DI 1 "const_int_operand" "n")
1329 (match_operand:DI 2 "const_int_operand" "n"))
1330 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1331 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1332 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1333 "dep %0 = %3, %0, %2, %1"
1334 [(set_attr "type" "I")])
1336 ;; Combine doesn't like to create bitfield insertions into zero.
1337 (define_insn "*depz_internal"
1338 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1339 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1340 (match_operand:DI 2 "const_int_operand" "n"))
1341 (match_operand:DI 3 "const_int_operand" "n")))]
1342 "CONST_OK_FOR_M (INTVAL (operands[2]))
1343 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1346 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1347 return \"%,dep.z %0 = %1, %2, %3\";
1349 [(set_attr "type" "I")])
1351 (define_insn "shift_mix4left"
1352 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1353 (const_int 32) (const_int 0))
1354 (match_operand:DI 1 "gr_register_operand" "r"))
1355 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1358 [(set_attr "type" "unknown")])
1361 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1362 (const_int 32) (const_int 0))
1363 (match_operand:DI 1 "register_operand" ""))
1364 (clobber (match_operand:DI 2 "register_operand" ""))]
1366 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1367 (unspec_volatile [(const_int 0)] 2)
1368 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1369 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1370 "operands[3] = operands[2];")
1373 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1374 (const_int 32) (const_int 0))
1375 (match_operand:DI 1 "register_operand" ""))
1376 (clobber (match_operand:DI 2 "register_operand" ""))]
1377 "! reload_completed"
1378 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1379 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1380 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1381 "operands[3] = operands[2];")
1383 (define_insn "*mix4left"
1384 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1385 (const_int 32) (const_int 0))
1386 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1389 "mix4.l %0 = %0, %r1"
1390 [(set_attr "type" "I")])
1392 (define_insn "mix4right"
1393 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1394 (const_int 32) (const_int 32))
1395 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1397 "mix4.r %0 = %r1, %0"
1398 [(set_attr "type" "I")])
1400 ;; This is used by the rotrsi3 pattern.
1402 (define_insn "*mix4right_3op"
1403 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1404 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1405 (ashift:DI (zero_extend:DI
1406 (match_operand:SI 2 "gr_register_operand" "r"))
1409 "mix4.r %0 = %2, %1"
1410 [(set_attr "type" "I")])
1413 ;; ::::::::::::::::::::
1415 ;; :: 1 bit Integer arithmetic
1417 ;; ::::::::::::::::::::
1419 (define_insn_and_split "andbi3"
1420 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1421 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1422 (match_operand:BI 2 "register_operand" "c,r,r")))]
1426 tbit.nz.and.orcm %0, %I0 = %2, 0
1429 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1430 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1431 [(cond_exec (eq (match_dup 2) (const_int 0))
1432 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1435 [(set_attr "type" "unknown,I,A")])
1437 (define_insn_and_split "*andcmbi3"
1438 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1439 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1440 (match_operand:BI 2 "register_operand" "0,0,r")))]
1444 tbit.z.and.orcm %0, %I0 = %2, 0
1447 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1448 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1449 [(cond_exec (ne (match_dup 1) (const_int 0))
1450 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1453 [(set_attr "type" "unknown,I,A")])
1455 (define_insn_and_split "iorbi3"
1456 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1457 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1458 (match_operand:BI 2 "register_operand" "c,r,r")))]
1462 tbit.nz.or.andcm %0, %I0 = %2, 0
1465 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1466 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1467 [(cond_exec (ne (match_dup 2) (const_int 0))
1468 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1471 [(set_attr "type" "unknown,I,A")])
1473 (define_insn_and_split "*iorcmbi3"
1474 [(set (match_operand:BI 0 "register_operand" "=c,c")
1475 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1476 (match_operand:BI 2 "register_operand" "0,0")))]
1480 tbit.z.or.andcm %0, %I0 = %2, 0"
1482 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1483 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1484 [(cond_exec (eq (match_dup 1) (const_int 0))
1485 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1488 [(set_attr "type" "unknown,I")])
1490 (define_insn "one_cmplbi2"
1491 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1492 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1493 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1496 tbit.z %0, %I0 = %1, 0
1500 [(set_attr "type" "I,A,unknown,unknown")])
1503 [(set (match_operand:BI 0 "register_operand" "")
1504 (not:BI (match_operand:BI 1 "register_operand" "")))
1505 (clobber (match_scratch:BI 2 ""))]
1507 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1508 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1509 && rtx_equal_p (operands[0], operands[1])"
1510 [(set (match_dup 4) (match_dup 3))
1511 (set (match_dup 0) (const_int 1))
1512 (cond_exec (ne (match_dup 2) (const_int 0))
1513 (set (match_dup 0) (const_int 0)))
1514 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
1515 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1516 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1519 [(set (match_operand:BI 0 "register_operand" "")
1520 (not:BI (match_operand:BI 1 "register_operand" "")))
1521 (clobber (match_scratch:BI 2 ""))]
1523 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1524 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1525 && ! rtx_equal_p (operands[0], operands[1])"
1526 [(cond_exec (ne (match_dup 1) (const_int 0))
1527 (set (match_dup 0) (const_int 0)))
1528 (cond_exec (eq (match_dup 1) (const_int 0))
1529 (set (match_dup 0) (const_int 1)))
1530 (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
1533 (define_insn "*cmpsi_and_0"
1534 [(set (match_operand:BI 0 "register_operand" "=c")
1535 (and:BI (match_operator:BI 4 "predicate_operator"
1536 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1537 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1538 (match_operand:BI 1 "register_operand" "0")))]
1540 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1541 [(set_attr "type" "A")])
1543 (define_insn "*cmpsi_and_1"
1544 [(set (match_operand:BI 0 "register_operand" "=c")
1545 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1546 [(match_operand:SI 2 "gr_register_operand" "r")
1548 (match_operand:BI 1 "register_operand" "0")))]
1550 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1551 [(set_attr "type" "A")])
1553 (define_insn "*cmpsi_andnot_0"
1554 [(set (match_operand:BI 0 "register_operand" "=c")
1555 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1556 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1557 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1558 (match_operand:BI 1 "register_operand" "0")))]
1560 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1561 [(set_attr "type" "A")])
1563 (define_insn "*cmpsi_andnot_1"
1564 [(set (match_operand:BI 0 "register_operand" "=c")
1565 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1566 [(match_operand:SI 2 "gr_register_operand" "r")
1568 (match_operand:BI 1 "register_operand" "0")))]
1570 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1571 [(set_attr "type" "A")])
1573 (define_insn "*cmpdi_and_0"
1574 [(set (match_operand:BI 0 "register_operand" "=c")
1575 (and:BI (match_operator:BI 4 "predicate_operator"
1576 [(match_operand:DI 2 "gr_register_operand" "r")
1577 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1578 (match_operand:BI 1 "register_operand" "0")))]
1580 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1581 [(set_attr "type" "A")])
1583 (define_insn "*cmpdi_and_1"
1584 [(set (match_operand:BI 0 "register_operand" "=c")
1585 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1586 [(match_operand:DI 2 "gr_register_operand" "r")
1588 (match_operand:BI 1 "register_operand" "0")))]
1590 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1591 [(set_attr "type" "A")])
1593 (define_insn "*cmpdi_andnot_0"
1594 [(set (match_operand:BI 0 "register_operand" "=c")
1595 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1596 [(match_operand:DI 2 "gr_register_operand" "r")
1597 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1598 (match_operand:BI 1 "register_operand" "0")))]
1600 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1601 [(set_attr "type" "A")])
1603 (define_insn "*cmpdi_andnot_1"
1604 [(set (match_operand:BI 0 "register_operand" "=c")
1605 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1606 [(match_operand:DI 2 "gr_register_operand" "r")
1608 (match_operand:BI 1 "register_operand" "0")))]
1610 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1611 [(set_attr "type" "A")])
1613 (define_insn "*tbit_and_0"
1614 [(set (match_operand:BI 0 "register_operand" "=c")
1615 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1618 (match_operand:BI 3 "register_operand" "0")))]
1620 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1621 [(set_attr "type" "I")])
1623 (define_insn "*tbit_and_1"
1624 [(set (match_operand:BI 0 "register_operand" "=c")
1625 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1628 (match_operand:BI 3 "register_operand" "0")))]
1630 "tbit.z.and.orcm %0, %I0 = %1, 0"
1631 [(set_attr "type" "I")])
1633 (define_insn "*tbit_and_2"
1634 [(set (match_operand:BI 0 "register_operand" "=c")
1635 (and:BI (ne:BI (zero_extract:DI
1636 (match_operand:DI 1 "gr_register_operand" "r")
1638 (match_operand:DI 2 "const_int_operand" "n"))
1640 (match_operand:BI 3 "register_operand" "0")))]
1642 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1643 [(set_attr "type" "I")])
1645 (define_insn "*tbit_and_3"
1646 [(set (match_operand:BI 0 "register_operand" "=c")
1647 (and:BI (eq:BI (zero_extract:DI
1648 (match_operand:DI 1 "gr_register_operand" "r")
1650 (match_operand:DI 2 "const_int_operand" "n"))
1652 (match_operand:BI 3 "register_operand" "0")))]
1654 "tbit.z.and.orcm %0, %I0 = %1, %2"
1655 [(set_attr "type" "I")])
1657 (define_insn "*cmpsi_or_0"
1658 [(set (match_operand:BI 0 "register_operand" "=c")
1659 (ior:BI (match_operator:BI 4 "predicate_operator"
1660 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1661 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1662 (match_operand:BI 1 "register_operand" "0")))]
1664 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1665 [(set_attr "type" "A")])
1667 (define_insn "*cmpsi_or_1"
1668 [(set (match_operand:BI 0 "register_operand" "=c")
1669 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1670 [(match_operand:SI 2 "gr_register_operand" "r")
1672 (match_operand:BI 1 "register_operand" "0")))]
1674 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1675 [(set_attr "type" "A")])
1677 (define_insn "*cmpsi_orcm_0"
1678 [(set (match_operand:BI 0 "register_operand" "=c")
1679 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1680 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1681 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1682 (match_operand:BI 1 "register_operand" "0")))]
1684 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1685 [(set_attr "type" "A")])
1687 (define_insn "*cmpsi_orcm_1"
1688 [(set (match_operand:BI 0 "register_operand" "=c")
1689 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1690 [(match_operand:SI 2 "gr_register_operand" "r")
1692 (match_operand:BI 1 "register_operand" "0")))]
1694 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1695 [(set_attr "type" "A")])
1697 (define_insn "*cmpdi_or_0"
1698 [(set (match_operand:BI 0 "register_operand" "=c")
1699 (ior:BI (match_operator:BI 4 "predicate_operator"
1700 [(match_operand:DI 2 "gr_register_operand" "r")
1701 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1702 (match_operand:BI 1 "register_operand" "0")))]
1704 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1705 [(set_attr "type" "A")])
1707 (define_insn "*cmpdi_or_1"
1708 [(set (match_operand:BI 0 "register_operand" "=c")
1709 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1710 [(match_operand:DI 2 "gr_register_operand" "r")
1712 (match_operand:BI 1 "register_operand" "0")))]
1714 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1715 [(set_attr "type" "A")])
1717 (define_insn "*cmpdi_orcm_0"
1718 [(set (match_operand:BI 0 "register_operand" "=c")
1719 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1720 [(match_operand:DI 2 "gr_register_operand" "r")
1721 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1722 (match_operand:BI 1 "register_operand" "0")))]
1724 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1725 [(set_attr "type" "A")])
1727 (define_insn "*cmpdi_orcm_1"
1728 [(set (match_operand:BI 0 "register_operand" "=c")
1729 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1730 [(match_operand:DI 2 "gr_register_operand" "r")
1732 (match_operand:BI 1 "register_operand" "0")))]
1734 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1735 [(set_attr "type" "A")])
1737 (define_insn "*tbit_or_0"
1738 [(set (match_operand:BI 0 "register_operand" "=c")
1739 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1742 (match_operand:BI 3 "register_operand" "0")))]
1744 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1745 [(set_attr "type" "I")])
1747 (define_insn "*tbit_or_1"
1748 [(set (match_operand:BI 0 "register_operand" "=c")
1749 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1752 (match_operand:BI 3 "register_operand" "0")))]
1754 "tbit.z.or.andcm %0, %I0 = %1, 0"
1755 [(set_attr "type" "I")])
1757 (define_insn "*tbit_or_2"
1758 [(set (match_operand:BI 0 "register_operand" "=c")
1759 (ior:BI (ne:BI (zero_extract:DI
1760 (match_operand:DI 1 "gr_register_operand" "r")
1762 (match_operand:DI 2 "const_int_operand" "n"))
1764 (match_operand:BI 3 "register_operand" "0")))]
1766 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1767 [(set_attr "type" "I")])
1769 (define_insn "*tbit_or_3"
1770 [(set (match_operand:BI 0 "register_operand" "=c")
1771 (ior:BI (eq:BI (zero_extract:DI
1772 (match_operand:DI 1 "gr_register_operand" "r")
1774 (match_operand:DI 2 "const_int_operand" "n"))
1776 (match_operand:BI 3 "register_operand" "0")))]
1778 "tbit.z.or.andcm %0, %I0 = %1, %2"
1779 [(set_attr "type" "I")])
1781 ;; Transform test of and/or of setcc into parallel comparisons.
1784 [(set (match_operand:BI 0 "register_operand" "")
1785 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1787 (match_operand:DI 3 "register_operand" ""))
1791 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1796 [(set (match_operand:BI 0 "register_operand" "")
1797 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1799 (match_operand:DI 3 "register_operand" ""))
1803 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1805 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1806 (clobber (scratch))])]
1810 [(set (match_operand:BI 0 "register_operand" "")
1811 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1813 (match_operand:DI 3 "register_operand" ""))
1817 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1822 [(set (match_operand:BI 0 "register_operand" "")
1823 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1825 (match_operand:DI 3 "register_operand" ""))
1829 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1831 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1832 (clobber (scratch))])]
1835 ;; ??? Incredibly hackish. Either need four proper patterns with all
1836 ;; the alternatives, or rely on sched1 to split the insn and hope that
1837 ;; nothing bad happens to the comparisons in the meantime.
1839 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1840 ;; that we're doing height reduction.
1842 ;(define_insn_and_split ""
1843 ; [(set (match_operand:BI 0 "register_operand" "=c")
1844 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1845 ; [(match_operand 2 "" "")
1846 ; (match_operand 3 "" "")])
1847 ; (match_operator:BI 4 "comparison_operator"
1848 ; [(match_operand 5 "" "")
1849 ; (match_operand 6 "" "")]))
1851 ; "flag_schedule_insns"
1854 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1855 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1858 ;(define_insn_and_split ""
1859 ; [(set (match_operand:BI 0 "register_operand" "=c")
1860 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1861 ; [(match_operand 2 "" "")
1862 ; (match_operand 3 "" "")])
1863 ; (match_operator:BI 4 "comparison_operator"
1864 ; [(match_operand 5 "" "")
1865 ; (match_operand 6 "" "")]))
1867 ; "flag_schedule_insns"
1870 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1871 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1875 ; [(set (match_operand:BI 0 "register_operand" "")
1876 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1877 ; [(match_operand 2 "" "")
1878 ; (match_operand 3 "" "")])
1879 ; (match_operand:BI 7 "register_operand" ""))
1880 ; (and:BI (match_operator:BI 4 "comparison_operator"
1881 ; [(match_operand 5 "" "")
1882 ; (match_operand 6 "" "")])
1883 ; (match_operand:BI 8 "register_operand" ""))))]
1885 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
1886 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
1891 ; [(set (match_operand:BI 0 "register_operand" "")
1892 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1893 ; [(match_operand 2 "" "")
1894 ; (match_operand 3 "" "")])
1895 ; (match_operand:BI 7 "register_operand" ""))
1896 ; (ior:BI (match_operator:BI 4 "comparison_operator"
1897 ; [(match_operand 5 "" "")
1898 ; (match_operand 6 "" "")])
1899 ; (match_operand:BI 8 "register_operand" ""))))]
1901 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
1902 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
1906 ;; Try harder to avoid predicate copies by duplicating compares.
1907 ;; Note that we'll have already split the predicate copy, which
1908 ;; is kind of a pain, but oh well.
1911 [(set (match_operand:BI 0 "register_operand" "")
1912 (match_operand:BI 1 "comparison_operator" ""))
1913 (set (match_operand:CCI 2 "register_operand" "")
1914 (match_operand:CCI 3 "register_operand" ""))
1915 (set (match_operand:CCI 4 "register_operand" "")
1916 (match_operand:CCI 5 "register_operand" ""))
1917 (set (match_operand:BI 6 "register_operand" "")
1918 (unspec:BI [(match_dup 6)] 7))]
1919 "REGNO (operands[3]) == REGNO (operands[0])
1920 && REGNO (operands[4]) == REGNO (operands[0]) + 1
1921 && REGNO (operands[4]) == REGNO (operands[2]) + 1
1922 && REGNO (operands[6]) == REGNO (operands[2])"
1923 [(set (match_dup 0) (match_dup 1))
1924 (set (match_dup 6) (match_dup 7))]
1925 "operands[7] = copy_rtx (operands[1]);")
1927 ;; ::::::::::::::::::::
1929 ;; :: 16 bit Integer arithmetic
1931 ;; ::::::::::::::::::::
1933 (define_insn "mulhi3"
1934 [(set (match_operand:HI 0 "gr_register_operand" "=r")
1935 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
1936 (match_operand:HI 2 "gr_register_operand" "r")))]
1938 "pmpy2.r %0 = %1, %2"
1939 [(set_attr "type" "I")])
1942 ;; ::::::::::::::::::::
1944 ;; :: 32 bit Integer arithmetic
1946 ;; ::::::::::::::::::::
1948 (define_insn "addsi3"
1949 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
1950 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
1951 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
1957 [(set_attr "type" "A")])
1959 (define_insn "*addsi3_plus1"
1960 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1961 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
1962 (match_operand:SI 2 "gr_register_operand" "r"))
1965 "add %0 = %1, %2, 1"
1966 [(set_attr "type" "A")])
1968 (define_insn "*addsi3_plus1_alt"
1969 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1970 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1974 "add %0 = %1, %1, 1"
1975 [(set_attr "type" "A")])
1977 (define_insn "*addsi3_shladd"
1978 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1979 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
1980 (match_operand:SI 2 "shladd_operand" "n"))
1981 (match_operand:SI 3 "gr_register_operand" "r")))]
1983 "shladd %0 = %1, %S2, %3"
1984 [(set_attr "type" "A")])
1986 (define_insn "subsi3"
1987 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1988 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
1989 (match_operand:SI 2 "gr_register_operand" "r")))]
1992 [(set_attr "type" "A")])
1994 (define_insn "*subsi3_minus1"
1995 [(set (match_operand:SI 0 "gr_register_operand" "=r")
1996 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
1997 (match_operand:SI 2 "gr_register_operand" "r")))]
1999 "sub %0 = %2, %1, 1"
2000 [(set_attr "type" "A")])
2002 (define_insn "mulsi3"
2003 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2004 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2005 (match_operand:SI 2 "grfr_register_operand" "f")))]
2007 "xmpy.l %0 = %1, %2%B0"
2008 [(set_attr "type" "F")])
2010 (define_insn "maddsi4"
2011 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2012 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2013 (match_operand:SI 2 "grfr_register_operand" "f"))
2014 (match_operand:SI 3 "grfr_register_operand" "f")))]
2016 "xma.l %0 = %1, %2, %3%B0"
2017 [(set_attr "type" "F")])
2019 (define_insn "negsi2"
2020 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2021 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
2024 [(set_attr "type" "A")])
2026 (define_expand "abssi2"
2028 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
2029 (set (match_operand:SI 0 "gr_register_operand" "")
2030 (if_then_else:SI (eq (match_dup 2) (const_int 0))
2031 (neg:SI (match_dup 1))
2036 operands[2] = gen_reg_rtx (BImode);
2039 (define_expand "sminsi3"
2041 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2042 (match_operand:SI 2 "gr_register_operand" "")))
2043 (set (match_operand:SI 0 "gr_register_operand" "")
2044 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2045 (match_dup 2) (match_dup 1)))]
2049 operands[3] = gen_reg_rtx (BImode);
2052 (define_expand "smaxsi3"
2054 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2055 (match_operand:SI 2 "gr_register_operand" "")))
2056 (set (match_operand:SI 0 "gr_register_operand" "")
2057 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2058 (match_dup 1) (match_dup 2)))]
2062 operands[3] = gen_reg_rtx (BImode);
2065 (define_expand "uminsi3"
2067 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2068 (match_operand:SI 2 "gr_register_operand" "")))
2069 (set (match_operand:SI 0 "gr_register_operand" "")
2070 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2071 (match_dup 2) (match_dup 1)))]
2075 operands[3] = gen_reg_rtx (BImode);
2078 (define_expand "umaxsi3"
2080 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2081 (match_operand:SI 2 "gr_register_operand" "")))
2082 (set (match_operand:SI 0 "gr_register_operand" "")
2083 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2084 (match_dup 1) (match_dup 2)))]
2088 operands[3] = gen_reg_rtx (BImode);
2091 (define_expand "divsi3"
2092 [(set (match_operand:SI 0 "register_operand" "")
2093 (div:SI (match_operand:SI 1 "general_operand" "")
2094 (match_operand:SI 2 "general_operand" "")))]
2098 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
2100 op0_tf = gen_reg_rtx (TFmode);
2101 op0_di = gen_reg_rtx (DImode);
2103 if (CONSTANT_P (operands[1]))
2104 operands[1] = force_reg (SImode, operands[1]);
2105 op1_tf = gen_reg_rtx (TFmode);
2106 expand_float (op1_tf, operands[1], 0);
2108 if (CONSTANT_P (operands[2]))
2109 operands[2] = force_reg (SImode, operands[2]);
2110 op2_tf = gen_reg_rtx (TFmode);
2111 expand_float (op2_tf, operands[2], 0);
2115 twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
2116 (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
2117 twon34 = force_reg (TFmode, twon34);
2119 twon34 = gen_reg_rtx (TFmode);
2120 convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
2123 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
2125 emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
2126 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2130 (define_expand "modsi3"
2131 [(set (match_operand:SI 0 "register_operand" "")
2132 (mod:SI (match_operand:SI 1 "general_operand" "")
2133 (match_operand:SI 2 "general_operand" "")))]
2137 rtx op2_neg, op1_di, div;
2139 div = gen_reg_rtx (SImode);
2140 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
2142 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2144 /* This is a trick to get us to reuse the value that we're sure to
2145 have already copied to the FP regs. */
2146 op1_di = gen_reg_rtx (DImode);
2147 convert_move (op1_di, operands[1], 0);
2149 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2150 gen_lowpart (SImode, op1_di)));
2154 (define_expand "udivsi3"
2155 [(set (match_operand:SI 0 "register_operand" "")
2156 (udiv:SI (match_operand:SI 1 "general_operand" "")
2157 (match_operand:SI 2 "general_operand" "")))]
2161 rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
2163 op0_tf = gen_reg_rtx (TFmode);
2164 op0_di = gen_reg_rtx (DImode);
2166 if (CONSTANT_P (operands[1]))
2167 operands[1] = force_reg (SImode, operands[1]);
2168 op1_tf = gen_reg_rtx (TFmode);
2169 expand_float (op1_tf, operands[1], 1);
2171 if (CONSTANT_P (operands[2]))
2172 operands[2] = force_reg (SImode, operands[2]);
2173 op2_tf = gen_reg_rtx (TFmode);
2174 expand_float (op2_tf, operands[2], 1);
2178 twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
2179 (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
2180 twon34 = force_reg (TFmode, twon34);
2182 twon34 = gen_reg_rtx (TFmode);
2183 convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
2186 emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
2188 emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
2189 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
2193 (define_expand "umodsi3"
2194 [(set (match_operand:SI 0 "register_operand" "")
2195 (umod:SI (match_operand:SI 1 "general_operand" "")
2196 (match_operand:SI 2 "general_operand" "")))]
2200 rtx op2_neg, op1_di, div;
2202 div = gen_reg_rtx (SImode);
2203 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
2205 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
2207 /* This is a trick to get us to reuse the value that we're sure to
2208 have already copied to the FP regs. */
2209 op1_di = gen_reg_rtx (DImode);
2210 convert_move (op1_di, operands[1], 1);
2212 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
2213 gen_lowpart (SImode, op1_di)));
2217 (define_insn_and_split "divsi3_internal"
2218 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2219 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2220 (match_operand:TF 2 "fr_register_operand" "f"))))
2221 (clobber (match_scratch:TF 4 "=&f"))
2222 (clobber (match_scratch:TF 5 "=&f"))
2223 (clobber (match_scratch:BI 6 "=c"))
2224 (use (match_operand:TF 3 "fr_register_operand" "f"))]
2227 "&& reload_completed"
2228 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2229 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
2230 (use (const_int 1))])
2231 (cond_exec (ne (match_dup 6) (const_int 0))
2232 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2233 (use (const_int 1))]))
2234 (cond_exec (ne (match_dup 6) (const_int 0))
2235 (parallel [(set (match_dup 5)
2236 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2238 (use (const_int 1))]))
2239 (cond_exec (ne (match_dup 6) (const_int 0))
2240 (parallel [(set (match_dup 4)
2241 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2243 (use (const_int 1))]))
2244 (cond_exec (ne (match_dup 6) (const_int 0))
2245 (parallel [(set (match_dup 5)
2246 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
2248 (use (const_int 1))]))
2249 (cond_exec (ne (match_dup 6) (const_int 0))
2250 (parallel [(set (match_dup 0)
2251 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2253 (use (const_int 1))]))
2255 "operands[7] = CONST1_RTX (TFmode);"
2256 [(set_attr "predicable" "no")])
2258 ;; ::::::::::::::::::::
2260 ;; :: 64 bit Integer arithmetic
2262 ;; ::::::::::::::::::::
2264 (define_insn "adddi3"
2265 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2266 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2267 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2273 [(set_attr "type" "A")])
2275 (define_insn "*adddi3_plus1"
2276 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2277 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2278 (match_operand:DI 2 "gr_register_operand" "r"))
2281 "add %0 = %1, %2, 1"
2282 [(set_attr "type" "A")])
2284 ;; This has some of the same problems as shladd. We let the shladd
2285 ;; eliminator hack handle it, which results in the 1 being forced into
2286 ;; a register, but not more ugliness here.
2287 (define_insn "*adddi3_plus1_alt"
2288 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2289 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2293 "add %0 = %1, %1, 1"
2294 [(set_attr "type" "A")])
2296 (define_insn "subdi3"
2297 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2298 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2299 (match_operand:DI 2 "gr_register_operand" "r")))]
2302 [(set_attr "type" "A")])
2304 (define_insn "*subdi3_minus1"
2305 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2306 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2307 (match_operand:DI 2 "gr_register_operand" "r")))]
2309 "sub %0 = %2, %1, 1"
2310 [(set_attr "type" "A")])
2312 ;; ??? Use grfr instead of fr because of virtual register elimination
2313 ;; and silly test cases multiplying by the frame pointer.
2314 (define_insn "muldi3"
2315 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2316 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2317 (match_operand:DI 2 "grfr_register_operand" "f")))]
2319 "xmpy.l %0 = %1, %2%B0"
2320 [(set_attr "type" "F")])
2322 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2323 ;; same problem that we have with shladd below. Unfortunately, this case is
2324 ;; much harder to fix because the multiply puts the result in an FP register,
2325 ;; but the add needs inputs from a general register. We add a spurious clobber
2326 ;; here so that it will be present just in case register elimination gives us
2327 ;; the funny result.
2329 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2331 ;; ??? Maybe we should change how adds are canonicalized.
2333 (define_insn "madddi4"
2334 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2335 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2336 (match_operand:DI 2 "grfr_register_operand" "f"))
2337 (match_operand:DI 3 "grfr_register_operand" "f")))
2338 (clobber (match_scratch:DI 4 "=X"))]
2340 "xma.l %0 = %1, %2, %3%B0"
2341 [(set_attr "type" "F")])
2343 ;; This can be created by register elimination if operand3 of shladd is an
2344 ;; eliminable register or has reg_equiv_constant set.
2346 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2347 ;; validate_changes call inside eliminate_regs will always succeed. If it
2348 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2351 (define_insn "*madddi4_elim"
2352 [(set (match_operand:DI 0 "register_operand" "=&r")
2353 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2354 (match_operand:DI 2 "register_operand" "f"))
2355 (match_operand:DI 3 "register_operand" "f"))
2356 (match_operand:DI 4 "nonmemory_operand" "rI")))
2357 (clobber (match_scratch:DI 5 "=f"))]
2358 "reload_in_progress"
2360 [(set_attr "type" "unknown")])
2362 ;; ??? Need to emit an instruction group barrier here because this gets split
2366 [(set (match_operand:DI 0 "register_operand" "")
2367 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2368 (match_operand:DI 2 "register_operand" ""))
2369 (match_operand:DI 3 "register_operand" ""))
2370 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2371 (clobber (match_scratch:DI 5 ""))]
2373 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2375 (clobber (match_dup 0))])
2376 (unspec_volatile [(const_int 0)] 2)
2377 (set (match_dup 0) (match_dup 5))
2378 (unspec_volatile [(const_int 0)] 2)
2379 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2382 ;; ??? There are highpart multiply and add instructions, but we have no way
2383 ;; to generate them.
2385 (define_insn "smuldi3_highpart"
2386 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2389 (mult:TI (sign_extend:TI
2390 (match_operand:DI 1 "fr_register_operand" "f"))
2392 (match_operand:DI 2 "fr_register_operand" "f")))
2395 "xmpy.h %0 = %1, %2%B0"
2396 [(set_attr "type" "F")])
2398 (define_insn "umuldi3_highpart"
2399 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2402 (mult:TI (zero_extend:TI
2403 (match_operand:DI 1 "fr_register_operand" "f"))
2405 (match_operand:DI 2 "fr_register_operand" "f")))
2408 "xmpy.hu %0 = %1, %2%B0"
2409 [(set_attr "type" "F")])
2411 (define_insn "negdi2"
2412 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2413 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2416 [(set_attr "type" "A")])
2418 (define_expand "absdi2"
2420 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2421 (set (match_operand:DI 0 "gr_register_operand" "")
2422 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2423 (neg:DI (match_dup 1))
2428 operands[2] = gen_reg_rtx (BImode);
2431 (define_expand "smindi3"
2433 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2434 (match_operand:DI 2 "gr_register_operand" "")))
2435 (set (match_operand:DI 0 "gr_register_operand" "")
2436 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2437 (match_dup 2) (match_dup 1)))]
2441 operands[3] = gen_reg_rtx (BImode);
2444 (define_expand "smaxdi3"
2446 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2447 (match_operand:DI 2 "gr_register_operand" "")))
2448 (set (match_operand:DI 0 "gr_register_operand" "")
2449 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2450 (match_dup 1) (match_dup 2)))]
2454 operands[3] = gen_reg_rtx (BImode);
2457 (define_expand "umindi3"
2459 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2460 (match_operand:DI 2 "gr_register_operand" "")))
2461 (set (match_operand:DI 0 "gr_register_operand" "")
2462 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2463 (match_dup 2) (match_dup 1)))]
2467 operands[3] = gen_reg_rtx (BImode);
2470 (define_expand "umaxdi3"
2472 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2473 (match_operand:DI 2 "gr_register_operand" "")))
2474 (set (match_operand:DI 0 "gr_register_operand" "")
2475 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2476 (match_dup 1) (match_dup 2)))]
2480 operands[3] = gen_reg_rtx (BImode);
2483 (define_expand "ffsdi2"
2485 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2486 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2487 (set (match_dup 5) (const_int 0))
2488 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2489 (set (match_dup 4) (unspec:DI [(match_dup 3)] 8))
2490 (set (match_operand:DI 0 "gr_register_operand" "")
2491 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2492 (match_dup 5) (match_dup 4)))]
2496 operands[2] = gen_reg_rtx (DImode);
2497 operands[3] = gen_reg_rtx (DImode);
2498 operands[4] = gen_reg_rtx (DImode);
2499 operands[5] = gen_reg_rtx (DImode);
2500 operands[6] = gen_reg_rtx (BImode);
2503 (define_insn "*popcnt"
2504 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2505 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))]
2508 [(set_attr "type" "I")])
2510 (define_expand "divdi3"
2511 [(set (match_operand:DI 0 "register_operand" "")
2512 (div:DI (match_operand:DI 1 "general_operand" "")
2513 (match_operand:DI 2 "general_operand" "")))]
2517 rtx op1_tf, op2_tf, op0_tf;
2519 op0_tf = gen_reg_rtx (TFmode);
2521 if (CONSTANT_P (operands[1]))
2522 operands[1] = force_reg (DImode, operands[1]);
2523 op1_tf = gen_reg_rtx (TFmode);
2524 expand_float (op1_tf, operands[1], 0);
2526 if (CONSTANT_P (operands[2]))
2527 operands[2] = force_reg (DImode, operands[2]);
2528 op2_tf = gen_reg_rtx (TFmode);
2529 expand_float (op2_tf, operands[2], 0);
2531 if (TARGET_INLINE_DIV_LAT)
2532 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2534 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2536 emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2540 (define_expand "moddi3"
2541 [(set (match_operand:DI 0 "register_operand" "")
2542 (mod:SI (match_operand:DI 1 "general_operand" "")
2543 (match_operand:DI 2 "general_operand" "")))]
2549 div = gen_reg_rtx (DImode);
2550 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
2552 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2554 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2558 (define_expand "udivdi3"
2559 [(set (match_operand:DI 0 "register_operand" "")
2560 (udiv:DI (match_operand:DI 1 "general_operand" "")
2561 (match_operand:DI 2 "general_operand" "")))]
2565 rtx op1_tf, op2_tf, op0_tf;
2567 op0_tf = gen_reg_rtx (TFmode);
2569 if (CONSTANT_P (operands[1]))
2570 operands[1] = force_reg (DImode, operands[1]);
2571 op1_tf = gen_reg_rtx (TFmode);
2572 expand_float (op1_tf, operands[1], 1);
2574 if (CONSTANT_P (operands[2]))
2575 operands[2] = force_reg (DImode, operands[2]);
2576 op2_tf = gen_reg_rtx (TFmode);
2577 expand_float (op2_tf, operands[2], 1);
2579 if (TARGET_INLINE_DIV_LAT)
2580 emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
2582 emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
2584 emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
2588 (define_expand "umoddi3"
2589 [(set (match_operand:DI 0 "register_operand" "")
2590 (umod:DI (match_operand:DI 1 "general_operand" "")
2591 (match_operand:DI 2 "general_operand" "")))]
2597 div = gen_reg_rtx (DImode);
2598 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
2600 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
2602 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
2606 (define_insn_and_split "divdi3_internal_lat"
2607 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2608 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2609 (match_operand:TF 2 "fr_register_operand" "f"))))
2610 (clobber (match_scratch:TF 3 "=&f"))
2611 (clobber (match_scratch:TF 4 "=&f"))
2612 (clobber (match_scratch:TF 5 "=&f"))
2613 (clobber (match_scratch:BI 6 "=c"))]
2614 "TARGET_INLINE_DIV_LAT"
2616 "&& reload_completed"
2617 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2618 (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
2619 (use (const_int 1))])
2620 (cond_exec (ne (match_dup 6) (const_int 0))
2621 (parallel [(set (match_dup 3)
2622 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2624 (use (const_int 1))]))
2625 (cond_exec (ne (match_dup 6) (const_int 0))
2626 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
2627 (use (const_int 1))]))
2628 (cond_exec (ne (match_dup 6) (const_int 0))
2629 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
2630 (use (const_int 1))]))
2631 (cond_exec (ne (match_dup 6) (const_int 0))
2632 (parallel [(set (match_dup 4)
2633 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
2635 (use (const_int 1))]))
2636 (cond_exec (ne (match_dup 6) (const_int 0))
2637 (parallel [(set (match_dup 0)
2638 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2640 (use (const_int 1))]))
2641 (cond_exec (ne (match_dup 6) (const_int 0))
2642 (parallel [(set (match_dup 3)
2643 (plus:TF (mult:TF (match_dup 5) (match_dup 4))
2645 (use (const_int 1))]))
2646 (cond_exec (ne (match_dup 6) (const_int 0))
2647 (parallel [(set (match_dup 0)
2648 (plus:TF (mult:TF (match_dup 5) (match_dup 0))
2650 (use (const_int 1))]))
2651 (cond_exec (ne (match_dup 6) (const_int 0))
2652 (parallel [(set (match_dup 4)
2653 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2655 (use (const_int 1))]))
2656 (cond_exec (ne (match_dup 6) (const_int 0))
2657 (parallel [(set (match_dup 0)
2658 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2660 (use (const_int 1))]))
2662 "operands[7] = CONST1_RTX (TFmode);"
2663 [(set_attr "predicable" "no")])
2665 (define_insn_and_split "divdi3_internal_thr"
2666 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
2667 (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f")
2668 (match_operand:TF 2 "fr_register_operand" "f"))))
2669 (clobber (match_scratch:TF 3 "=&f"))
2670 (clobber (match_scratch:TF 4 "=f"))
2671 (clobber (match_scratch:BI 5 "=c"))]
2672 "TARGET_INLINE_DIV_THR"
2674 "&& reload_completed"
2675 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
2676 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
2677 (use (const_int 1))])
2678 (cond_exec (ne (match_dup 5) (const_int 0))
2679 (parallel [(set (match_dup 3)
2680 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
2682 (use (const_int 1))]))
2683 (cond_exec (ne (match_dup 5) (const_int 0))
2684 (parallel [(set (match_dup 0)
2685 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2687 (use (const_int 1))]))
2688 (cond_exec (ne (match_dup 5) (const_int 0))
2689 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
2690 (use (const_int 1))]))
2691 (cond_exec (ne (match_dup 5) (const_int 0))
2692 (parallel [(set (match_dup 0)
2693 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
2695 (use (const_int 1))]))
2696 (cond_exec (ne (match_dup 5) (const_int 0))
2697 (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1)))
2698 (use (const_int 1))]))
2699 (cond_exec (ne (match_dup 5) (const_int 0))
2700 (parallel [(set (match_dup 4)
2701 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
2703 (use (const_int 1))]))
2704 (cond_exec (ne (match_dup 5) (const_int 0))
2705 (parallel [(set (match_dup 0)
2706 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
2708 (use (const_int 1))]))
2710 "operands[6] = CONST1_RTX (TFmode);"
2711 [(set_attr "predicable" "no")])
2713 ;; ::::::::::::::::::::
2715 ;; :: 32 bit floating point arithmetic
2717 ;; ::::::::::::::::::::
2719 (define_insn "addsf3"
2720 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2721 (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
2722 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2724 "fadd.s %0 = %1, %F2%B0"
2725 [(set_attr "type" "F")])
2727 (define_insn "subsf3"
2728 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2729 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2730 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2732 "fsub.s %0 = %F1, %F2%B0"
2733 [(set_attr "type" "F")])
2735 (define_insn "mulsf3"
2736 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2737 (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
2738 (match_operand:SF 2 "fr_register_operand" "f")))]
2740 "fmpy.s %0 = %1, %2%B0"
2741 [(set_attr "type" "F")])
2743 (define_insn "abssf2"
2744 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2745 (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2748 [(set_attr "type" "F")])
2750 (define_insn "negsf2"
2751 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2752 (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
2755 [(set_attr "type" "F")])
2757 (define_insn "*nabssf2"
2758 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2759 (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
2761 "fnegabs %0 = %1%B0"
2762 [(set_attr "type" "F")])
2764 (define_insn "minsf3"
2765 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2766 (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
2767 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2769 "fmin %0 = %1, %F2%B0"
2770 [(set_attr "type" "F")])
2772 (define_insn "maxsf3"
2773 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2774 (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
2775 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2777 "fmax %0 = %1, %F2%B0"
2778 [(set_attr "type" "F")])
2780 (define_insn "*maddsf4"
2781 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2782 (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2783 (match_operand:SF 2 "fr_register_operand" "f"))
2784 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2786 "fma.s %0 = %1, %2, %F3%B0"
2787 [(set_attr "type" "F")])
2789 (define_insn "*msubsf4"
2790 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2791 (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2792 (match_operand:SF 2 "fr_register_operand" "f"))
2793 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2795 "fms.s %0 = %1, %2, %F3%B0"
2796 [(set_attr "type" "F")])
2798 (define_insn "*nmulsf3"
2799 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2800 (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
2801 (match_operand:SF 2 "fr_register_operand" "f"))))]
2803 "fnmpy.s %0 = %1, %2%B0"
2804 [(set_attr "type" "F")])
2806 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
2808 (define_insn "*nmaddsf4"
2809 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2810 (plus:SF (neg:SF (mult:SF
2811 (match_operand:SF 1 "fr_register_operand" "f")
2812 (match_operand:SF 2 "fr_register_operand" "f")))
2813 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2815 "fnma.s %0 = %1, %2, %F3%B0"
2816 [(set_attr "type" "F")])
2818 (define_expand "divsf3"
2819 [(set (match_operand:SF 0 "fr_register_operand" "")
2820 (div:SF (match_operand:SF 1 "fr_register_operand" "")
2821 (match_operand:SF 2 "fr_register_operand" "")))]
2826 if (TARGET_INLINE_DIV_LAT)
2827 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
2829 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
2834 (define_insn_and_split "divsf3_internal_lat"
2835 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2836 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2837 (match_operand:SF 2 "fr_register_operand" "f")))
2838 (clobber (match_scratch:TF 3 "=&f"))
2839 (clobber (match_scratch:TF 4 "=f"))
2840 (clobber (match_scratch:BI 5 "=c"))]
2841 "TARGET_INLINE_DIV_LAT"
2843 "&& reload_completed"
2844 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2845 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
2846 (use (const_int 1))])
2847 (cond_exec (ne (match_dup 5) (const_int 0))
2848 (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
2849 (use (const_int 1))]))
2850 (cond_exec (ne (match_dup 5) (const_int 0))
2851 (parallel [(set (match_dup 4)
2852 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2854 (use (const_int 1))]))
2855 (cond_exec (ne (match_dup 5) (const_int 0))
2856 (parallel [(set (match_dup 3)
2857 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2859 (use (const_int 1))]))
2860 (cond_exec (ne (match_dup 5) (const_int 0))
2861 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2862 (use (const_int 1))]))
2863 (cond_exec (ne (match_dup 5) (const_int 0))
2864 (parallel [(set (match_dup 3)
2865 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2867 (use (const_int 1))]))
2868 (cond_exec (ne (match_dup 5) (const_int 0))
2869 (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4)))
2870 (use (const_int 1))]))
2871 (cond_exec (ne (match_dup 5) (const_int 0))
2872 (parallel [(set (match_dup 9)
2874 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
2876 (use (const_int 1))]))
2877 (cond_exec (ne (match_dup 5) (const_int 0))
2879 (float_truncate:SF (match_dup 6))))
2881 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2882 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2883 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2884 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
2885 operands[10] = CONST1_RTX (TFmode);"
2886 [(set_attr "predicable" "no")])
2888 (define_insn_and_split "divsf3_internal_thr"
2889 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
2890 (div:SF (match_operand:SF 1 "fr_register_operand" "f")
2891 (match_operand:SF 2 "fr_register_operand" "f")))
2892 (clobber (match_scratch:TF 3 "=&f"))
2893 (clobber (match_scratch:TF 4 "=f"))
2894 (clobber (match_scratch:BI 5 "=c"))]
2895 "TARGET_INLINE_DIV_THR"
2897 "&& reload_completed"
2898 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
2899 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
2900 (use (const_int 1))])
2901 (cond_exec (ne (match_dup 5) (const_int 0))
2902 (parallel [(set (match_dup 3)
2903 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
2905 (use (const_int 1))]))
2906 (cond_exec (ne (match_dup 5) (const_int 0))
2907 (parallel [(set (match_dup 3)
2908 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
2910 (use (const_int 1))]))
2911 (cond_exec (ne (match_dup 5) (const_int 0))
2912 (parallel [(set (match_dup 6)
2913 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
2915 (use (const_int 1))]))
2916 (cond_exec (ne (match_dup 5) (const_int 0))
2917 (parallel [(set (match_dup 9)
2919 (mult:TF (match_dup 7) (match_dup 6))))
2920 (use (const_int 1))]))
2921 (cond_exec (ne (match_dup 5) (const_int 0))
2922 (parallel [(set (match_dup 4)
2923 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3)))
2925 (use (const_int 1))]))
2926 (cond_exec (ne (match_dup 5) (const_int 0))
2929 (plus:TF (mult:TF (match_dup 4) (match_dup 6))
2932 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
2933 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
2934 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
2935 operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
2936 operands[10] = CONST1_RTX (TFmode);"
2937 [(set_attr "predicable" "no")])
2939 ;; ::::::::::::::::::::
2941 ;; :: 64 bit floating point arithmetic
2943 ;; ::::::::::::::::::::
2945 (define_insn "adddf3"
2946 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2947 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2948 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2950 "fadd.d %0 = %1, %F2%B0"
2951 [(set_attr "type" "F")])
2953 (define_insn "*adddf3_trunc"
2954 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2956 (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
2957 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2959 "fadd.s %0 = %1, %F2%B0"
2960 [(set_attr "type" "F")])
2962 (define_insn "subdf3"
2963 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2964 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2965 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2967 "fsub.d %0 = %F1, %F2%B0"
2968 [(set_attr "type" "F")])
2970 (define_insn "*subdf3_trunc"
2971 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2973 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2974 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2976 "fsub.s %0 = %F1, %F2%B0"
2977 [(set_attr "type" "F")])
2979 (define_insn "muldf3"
2980 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2981 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2982 (match_operand:DF 2 "fr_register_operand" "f")))]
2984 "fmpy.d %0 = %1, %2%B0"
2985 [(set_attr "type" "F")])
2987 (define_insn "*muldf3_trunc"
2988 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2990 (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
2991 (match_operand:DF 2 "fr_register_operand" "f"))))]
2993 "fmpy.s %0 = %1, %2%B0"
2994 [(set_attr "type" "F")])
2996 (define_insn "absdf2"
2997 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2998 (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3001 [(set_attr "type" "F")])
3003 (define_insn "negdf2"
3004 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3005 (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
3008 [(set_attr "type" "F")])
3010 (define_insn "*nabsdf2"
3011 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3012 (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
3014 "fnegabs %0 = %1%B0"
3015 [(set_attr "type" "F")])
3017 (define_insn "mindf3"
3018 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3019 (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
3020 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3022 "fmin %0 = %1, %F2%B0"
3023 [(set_attr "type" "F")])
3025 (define_insn "maxdf3"
3026 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3027 (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
3028 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
3030 "fmax %0 = %1, %F2%B0"
3031 [(set_attr "type" "F")])
3033 (define_insn "*madddf4"
3034 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3035 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3036 (match_operand:DF 2 "fr_register_operand" "f"))
3037 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3039 "fma.d %0 = %1, %2, %F3%B0"
3040 [(set_attr "type" "F")])
3042 (define_insn "*madddf4_trunc"
3043 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3045 (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3046 (match_operand:DF 2 "fr_register_operand" "f"))
3047 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3049 "fma.s %0 = %1, %2, %F3%B0"
3050 [(set_attr "type" "F")])
3052 (define_insn "*msubdf4"
3053 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3054 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3055 (match_operand:DF 2 "fr_register_operand" "f"))
3056 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3058 "fms.d %0 = %1, %2, %F3%B0"
3059 [(set_attr "type" "F")])
3061 (define_insn "*msubdf4_trunc"
3062 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3064 (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3065 (match_operand:DF 2 "fr_register_operand" "f"))
3066 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3068 "fms.s %0 = %1, %2, %F3%B0"
3069 [(set_attr "type" "F")])
3071 (define_insn "*nmuldf3"
3072 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3073 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3074 (match_operand:DF 2 "fr_register_operand" "f"))))]
3076 "fnmpy.d %0 = %1, %2%B0"
3077 [(set_attr "type" "F")])
3079 (define_insn "*nmuldf3_trunc"
3080 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3082 (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
3083 (match_operand:DF 2 "fr_register_operand" "f")))))]
3085 "fnmpy.s %0 = %1, %2%B0"
3086 [(set_attr "type" "F")])
3088 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
3090 (define_insn "*nmadddf4"
3091 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3092 (plus:DF (neg:DF (mult:DF
3093 (match_operand:DF 1 "fr_register_operand" "f")
3094 (match_operand:DF 2 "fr_register_operand" "f")))
3095 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
3097 "fnma.d %0 = %1, %2, %F3%B0"
3098 [(set_attr "type" "F")])
3100 (define_insn "*nmadddf4_alts"
3101 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3102 (plus:DF (neg:DF (mult:DF
3103 (match_operand:DF 1 "fr_register_operand" "f")
3104 (match_operand:DF 2 "fr_register_operand" "f")))
3105 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))
3106 (use (match_operand:SI 4 "const_int_operand" ""))]
3108 "fnma.d.s%4 %0 = %1, %2, %F3%B0"
3109 [(set_attr "type" "F")])
3111 (define_insn "*nmadddf4_trunc"
3112 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3114 (plus:DF (neg:DF (mult:DF
3115 (match_operand:DF 1 "fr_register_operand" "f")
3116 (match_operand:DF 2 "fr_register_operand" "f")))
3117 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
3119 "fnma.s %0 = %1, %2, %F3%B0"
3120 [(set_attr "type" "F")])
3122 (define_expand "divdf3"
3123 [(set (match_operand:DF 0 "fr_register_operand" "")
3124 (div:DF (match_operand:DF 1 "fr_register_operand" "")
3125 (match_operand:DF 2 "fr_register_operand" "")))]
3130 if (TARGET_INLINE_DIV_LAT)
3131 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
3133 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
3138 (define_insn_and_split "divdf3_internal_lat"
3139 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3140 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3141 (match_operand:DF 2 "fr_register_operand" "f")))
3142 (clobber (match_scratch:TF 3 "=&f"))
3143 (clobber (match_scratch:TF 4 "=&f"))
3144 (clobber (match_scratch:TF 5 "=&f"))
3145 (clobber (match_scratch:BI 6 "=c"))]
3146 "TARGET_INLINE_DIV_LAT"
3148 "&& reload_completed"
3149 [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
3150 (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5))
3151 (use (const_int 1))])
3152 (cond_exec (ne (match_dup 6) (const_int 0))
3153 (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
3154 (use (const_int 1))]))
3155 (cond_exec (ne (match_dup 6) (const_int 0))
3156 (parallel [(set (match_dup 4)
3157 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7)))
3159 (use (const_int 1))]))
3160 (cond_exec (ne (match_dup 6) (const_int 0))
3161 (parallel [(set (match_dup 3)
3162 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3164 (use (const_int 1))]))
3165 (cond_exec (ne (match_dup 6) (const_int 0))
3166 (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4)))
3167 (use (const_int 1))]))
3168 (cond_exec (ne (match_dup 6) (const_int 0))
3169 (parallel [(set (match_dup 7)
3170 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3172 (use (const_int 1))]))
3173 (cond_exec (ne (match_dup 6) (const_int 0))
3174 (parallel [(set (match_dup 3)
3175 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3177 (use (const_int 1))]))
3178 (cond_exec (ne (match_dup 6) (const_int 0))
3179 (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5)))
3180 (use (const_int 1))]))
3181 (cond_exec (ne (match_dup 6) (const_int 0))
3182 (parallel [(set (match_dup 7)
3183 (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3185 (use (const_int 1))]))
3186 (cond_exec (ne (match_dup 6) (const_int 0))
3187 (parallel [(set (match_dup 10)
3189 (plus:TF (mult:TF (match_dup 4) (match_dup 3))
3191 (use (const_int 1))]))
3192 (cond_exec (ne (match_dup 6) (const_int 0))
3193 (parallel [(set (match_dup 7)
3194 (plus:TF (mult:TF (match_dup 4) (match_dup 7))
3196 (use (const_int 1))]))
3197 (cond_exec (ne (match_dup 6) (const_int 0))
3198 (parallel [(set (match_dup 11)
3200 (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3)))
3202 (use (const_int 1))]))
3203 (cond_exec (ne (match_dup 6) (const_int 0))
3205 (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
3208 "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3209 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3210 operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3211 operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3212 operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
3213 operands[12] = CONST1_RTX (TFmode);"
3214 [(set_attr "predicable" "no")])
3216 (define_insn_and_split "divdf3_internal_thr"
3217 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
3218 (div:DF (match_operand:DF 1 "fr_register_operand" "f")
3219 (match_operand:DF 2 "fr_register_operand" "f")))
3220 (clobber (match_scratch:TF 3 "=&f"))
3221 (clobber (match_scratch:DF 4 "=f"))
3222 (clobber (match_scratch:BI 5 "=c"))]
3223 "TARGET_INLINE_DIV_THR"
3225 "&& reload_completed"
3226 [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
3227 (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
3228 (use (const_int 1))])
3229 (cond_exec (ne (match_dup 5) (const_int 0))
3230 (parallel [(set (match_dup 3)
3231 (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6)))
3233 (use (const_int 1))]))
3234 (cond_exec (ne (match_dup 5) (const_int 0))
3235 (parallel [(set (match_dup 6)
3236 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3238 (use (const_int 1))]))
3239 (cond_exec (ne (match_dup 5) (const_int 0))
3240 (parallel [(set (match_dup 3)
3241 (mult:TF (match_dup 3) (match_dup 3)))
3242 (use (const_int 1))]))
3243 (cond_exec (ne (match_dup 5) (const_int 0))
3244 (parallel [(set (match_dup 6)
3245 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3247 (use (const_int 1))]))
3248 (cond_exec (ne (match_dup 5) (const_int 0))
3249 (parallel [(set (match_dup 3)
3250 (mult:TF (match_dup 3) (match_dup 3)))
3251 (use (const_int 1))]))
3252 (cond_exec (ne (match_dup 5) (const_int 0))
3253 (parallel [(set (match_dup 6)
3254 (plus:TF (mult:TF (match_dup 3) (match_dup 6))
3256 (use (const_int 1))]))
3257 (cond_exec (ne (match_dup 5) (const_int 0))
3258 (parallel [(set (match_dup 9)
3260 (mult:TF (match_dup 7) (match_dup 3))))
3261 (use (const_int 1))]))
3262 (cond_exec (ne (match_dup 5) (const_int 0))
3263 (parallel [(set (match_dup 4)
3264 (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9)))
3266 (use (const_int 1))]))
3267 (cond_exec (ne (match_dup 5) (const_int 0))
3269 (plus:DF (mult:DF (match_dup 4) (match_dup 0))
3272 "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
3273 operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
3274 operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
3275 operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
3276 operands[10] = CONST1_RTX (TFmode);"
3277 [(set_attr "predicable" "no")])
3279 ;; ::::::::::::::::::::
3281 ;; :: 80 bit floating point arithmetic
3283 ;; ::::::::::::::::::::
3285 (define_insn "addtf3"
3286 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3287 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3288 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3290 "fadd %0 = %F1, %F2%B0"
3291 [(set_attr "type" "F")])
3293 (define_insn "*addtf3_truncsf"
3294 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3296 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3297 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3299 "fadd.s %0 = %F1, %F2%B0"
3300 [(set_attr "type" "F")])
3302 (define_insn "*addtf3_truncdf"
3303 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3305 (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3306 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3308 "fadd.d %0 = %F1, %F2%B0"
3309 [(set_attr "type" "F")])
3311 (define_insn "subtf3"
3312 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3313 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3314 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3316 "fsub %0 = %F1, %F2%B0"
3317 [(set_attr "type" "F")])
3319 (define_insn "*subtf3_truncsf"
3320 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3322 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3323 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3325 "fsub.s %0 = %F1, %F2%B0"
3326 [(set_attr "type" "F")])
3328 (define_insn "*subtf3_truncdf"
3329 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3331 (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3332 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3334 "fsub.d %0 = %F1, %F2%B0"
3335 [(set_attr "type" "F")])
3337 (define_insn "multf3"
3338 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3339 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3340 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3342 "fmpy %0 = %F1, %F2%B0"
3343 [(set_attr "type" "F")])
3345 (define_insn "*multf3_truncsf"
3346 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3348 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3349 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3351 "fmpy.s %0 = %F1, %F2%B0"
3352 [(set_attr "type" "F")])
3354 (define_insn "*multf3_truncdf"
3355 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3357 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3358 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3360 "fmpy.d %0 = %F1, %F2%B0"
3361 [(set_attr "type" "F")])
3363 (define_insn "*multf3_alts"
3364 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3365 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3366 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3367 (use (match_operand:SI 3 "const_int_operand" ""))]
3369 "fmpy.s%3 %0 = %F1, %F2%B0"
3370 [(set_attr "type" "F")])
3372 (define_insn "*multf3_truncsf_alts"
3373 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3375 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3376 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3377 (use (match_operand:SI 3 "const_int_operand" ""))]
3379 "fmpy.s.s%3 %0 = %F1, %F2%B0"
3380 [(set_attr "type" "F")])
3382 (define_insn "*multf3_truncdf_alts"
3383 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3385 (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3386 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))
3387 (use (match_operand:SI 3 "const_int_operand" ""))]
3389 "fmpy.d.s%3 %0 = %F1, %F2%B0"
3390 [(set_attr "type" "F")])
3392 (define_insn "abstf2"
3393 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3394 (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3397 [(set_attr "type" "F")])
3399 (define_insn "negtf2"
3400 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3401 (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))]
3404 [(set_attr "type" "F")])
3406 (define_insn "*nabstf2"
3407 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3408 (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))]
3410 "fnegabs %0 = %F1%B0"
3411 [(set_attr "type" "F")])
3413 (define_insn "mintf3"
3414 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3415 (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3416 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3418 "fmin %0 = %F1, %F2%B0"
3419 [(set_attr "type" "F")])
3421 (define_insn "maxtf3"
3422 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3423 (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3424 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))]
3426 "fmax %0 = %F1, %F2%B0"
3427 [(set_attr "type" "F")])
3429 (define_insn "*maddtf4"
3430 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3431 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3432 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3433 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3435 "fma %0 = %F1, %F2, %F3%B0"
3436 [(set_attr "type" "F")])
3438 (define_insn "*maddtf4_truncsf"
3439 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3441 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3442 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3443 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3445 "fma.s %0 = %F1, %F2, %F3%B0"
3446 [(set_attr "type" "F")])
3448 (define_insn "*maddtf4_truncdf"
3449 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3451 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3452 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3453 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3455 "fma.d %0 = %F1, %F2, %F3%B0"
3456 [(set_attr "type" "F")])
3458 (define_insn "*maddtf4_alts"
3459 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3460 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3461 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3462 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3463 (use (match_operand:SI 4 "const_int_operand" ""))]
3465 "fma.s%4 %0 = %F1, %F2, %F3%B0"
3466 [(set_attr "type" "F")])
3468 (define_insn "*maddtf4_alts_truncdf"
3469 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3471 (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3472 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3473 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3474 (use (match_operand:SI 4 "const_int_operand" ""))]
3476 "fma.d.s%4 %0 = %F1, %F2, %F3%B0"
3477 [(set_attr "type" "F")])
3479 (define_insn "*msubtf4"
3480 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3481 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3482 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3483 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3485 "fms %0 = %F1, %F2, %F3%B0"
3486 [(set_attr "type" "F")])
3488 (define_insn "*msubtf4_truncsf"
3489 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3491 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3492 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3493 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3495 "fms.s %0 = %F1, %F2, %F3%B0"
3496 [(set_attr "type" "F")])
3498 (define_insn "*msubtf4_truncdf"
3499 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3501 (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3502 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))
3503 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3505 "fms.d %0 = %F1, %F2, %F3%B0"
3506 [(set_attr "type" "F")])
3508 (define_insn "*nmultf3"
3509 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3510 (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3511 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))]
3513 "fnmpy %0 = %F1, %F2%B0"
3514 [(set_attr "type" "F")])
3516 (define_insn "*nmultf3_truncsf"
3517 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3520 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3521 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3523 "fnmpy.s %0 = %F1, %F2%B0"
3524 [(set_attr "type" "F")])
3526 (define_insn "*nmultf3_truncdf"
3527 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3530 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3531 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))]
3533 "fnmpy.d %0 = %F1, %F2%B0"
3534 [(set_attr "type" "F")])
3536 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
3538 (define_insn "*nmaddtf4"
3539 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3540 (plus:TF (neg:TF (mult:TF
3541 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3542 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3543 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))]
3545 "fnma %0 = %F1, %F2, %F3%B0"
3546 [(set_attr "type" "F")])
3548 (define_insn "*nmaddtf4_truncsf"
3549 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3551 (plus:TF (neg:TF (mult:TF
3552 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3553 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3554 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3556 "fnma.s %0 = %F1, %F2, %F3%B0"
3557 [(set_attr "type" "F")])
3559 (define_insn "*nmaddtf4_truncdf"
3560 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3562 (plus:TF (neg:TF (mult:TF
3563 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3564 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3565 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))]
3567 "fnma.d %0 = %F1, %F2, %F3%B0"
3568 [(set_attr "type" "F")])
3570 (define_insn "*nmaddtf4_alts"
3571 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3572 (plus:TF (neg:TF (mult:TF
3573 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3574 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3575 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))
3576 (use (match_operand:SI 4 "const_int_operand" ""))]
3578 "fnma.s%4 %0 = %F1, %F2, %F3%B0"
3579 [(set_attr "type" "F")])
3581 (define_insn "*nmaddtf4_truncdf_alts"
3582 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3586 (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")
3587 (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))
3588 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))
3589 (use (match_operand:SI 4 "const_int_operand" ""))]
3591 "fnma.d.s%4 %0 = %F1, %F2, %F3%B0"
3592 [(set_attr "type" "F")])
3594 (define_expand "divtf3"
3595 [(set (match_operand:TF 0 "fr_register_operand" "")
3596 (div:TF (match_operand:TF 1 "fr_register_operand" "")
3597 (match_operand:TF 2 "fr_register_operand" "")))]
3602 if (TARGET_INLINE_DIV_LAT)
3603 insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
3605 insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
3610 (define_insn_and_split "divtf3_internal_lat"
3611 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3612 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3613 (match_operand:TF 2 "fr_register_operand" "f")))
3614 (clobber (match_scratch:TF 3 "=&f"))
3615 (clobber (match_scratch:TF 4 "=&f"))
3616 (clobber (match_scratch:TF 5 "=&f"))
3617 (clobber (match_scratch:TF 6 "=&f"))
3618 (clobber (match_scratch:BI 7 "=c"))]
3619 "TARGET_INLINE_DIV_LAT"
3621 "&& reload_completed"
3622 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3623 (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
3624 (use (const_int 1))])
3625 (cond_exec (ne (match_dup 7) (const_int 0))
3626 (parallel [(set (match_dup 3)
3627 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3629 (use (const_int 1))]))
3630 (cond_exec (ne (match_dup 7) (const_int 0))
3631 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3632 (use (const_int 1))]))
3633 (cond_exec (ne (match_dup 7) (const_int 0))
3634 (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3)))
3635 (use (const_int 1))]))
3636 (cond_exec (ne (match_dup 7) (const_int 0))
3637 (parallel [(set (match_dup 6)
3638 (plus:TF (mult:TF (match_dup 3) (match_dup 3))
3640 (use (const_int 1))]))
3641 (cond_exec (ne (match_dup 7) (const_int 0))
3642 (parallel [(set (match_dup 3)
3643 (plus:TF (mult:TF (match_dup 5) (match_dup 5))
3645 (use (const_int 1))]))
3646 (cond_exec (ne (match_dup 7) (const_int 0))
3647 (parallel [(set (match_dup 5)
3648 (plus:TF (mult:TF (match_dup 6) (match_dup 0))
3650 (use (const_int 1))]))
3651 (cond_exec (ne (match_dup 7) (const_int 0))
3652 (parallel [(set (match_dup 0)
3653 (plus:TF (mult:TF (match_dup 5) (match_dup 3))
3655 (use (const_int 1))]))
3656 (cond_exec (ne (match_dup 7) (const_int 0))
3657 (parallel [(set (match_dup 4)
3658 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3660 (use (const_int 1))]))
3661 (cond_exec (ne (match_dup 7) (const_int 0))
3662 (parallel [(set (match_dup 3)
3663 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3665 (use (const_int 1))]))
3666 (cond_exec (ne (match_dup 7) (const_int 0))
3667 (parallel [(set (match_dup 5)
3668 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3670 (use (const_int 1))]))
3671 (cond_exec (ne (match_dup 7) (const_int 0))
3672 (parallel [(set (match_dup 0)
3673 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3675 (use (const_int 1))]))
3676 (cond_exec (ne (match_dup 7) (const_int 0))
3677 (parallel [(set (match_dup 4)
3678 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3680 (use (const_int 1))]))
3681 (cond_exec (ne (match_dup 7) (const_int 0))
3683 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3686 "operands[8] = CONST1_RTX (TFmode);"
3687 [(set_attr "predicable" "no")])
3689 (define_insn_and_split "divtf3_internal_thr"
3690 [(set (match_operand:TF 0 "fr_register_operand" "=&f")
3691 (div:TF (match_operand:TF 1 "fr_register_operand" "f")
3692 (match_operand:TF 2 "fr_register_operand" "f")))
3693 (clobber (match_scratch:TF 3 "=&f"))
3694 (clobber (match_scratch:TF 4 "=&f"))
3695 (clobber (match_scratch:BI 5 "=c"))]
3696 "TARGET_INLINE_DIV_THR"
3698 "&& reload_completed"
3699 [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
3700 (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
3701 (use (const_int 1))])
3702 (cond_exec (ne (match_dup 5) (const_int 0))
3703 (parallel [(set (match_dup 3)
3704 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3706 (use (const_int 1))]))
3707 (cond_exec (ne (match_dup 5) (const_int 0))
3708 (parallel [(set (match_dup 4)
3709 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3711 (use (const_int 1))]))
3712 (cond_exec (ne (match_dup 5) (const_int 0))
3713 (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3)))
3714 (use (const_int 1))]))
3715 (cond_exec (ne (match_dup 5) (const_int 0))
3716 (parallel [(set (match_dup 3)
3717 (plus:TF (mult:TF (match_dup 3) (match_dup 4))
3719 (use (const_int 1))]))
3720 (cond_exec (ne (match_dup 5) (const_int 0))
3721 (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
3722 (use (const_int 1))]))
3723 (cond_exec (ne (match_dup 5) (const_int 0))
3724 (parallel [(set (match_dup 0)
3725 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3727 (use (const_int 1))]))
3728 (cond_exec (ne (match_dup 5) (const_int 0))
3729 (parallel [(set (match_dup 0)
3730 (plus:TF (mult:TF (match_dup 0) (match_dup 3))
3732 (use (const_int 1))]))
3733 (cond_exec (ne (match_dup 5) (const_int 0))
3734 (parallel [(set (match_dup 3)
3735 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4)))
3737 (use (const_int 1))]))
3738 (cond_exec (ne (match_dup 5) (const_int 0))
3739 (parallel [(set (match_dup 3)
3740 (plus:TF (mult:TF (match_dup 3) (match_dup 0))
3742 (use (const_int 1))]))
3743 (cond_exec (ne (match_dup 5) (const_int 0))
3744 (parallel [(set (match_dup 4)
3745 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0)))
3747 (use (const_int 1))]))
3748 (cond_exec (ne (match_dup 5) (const_int 0))
3749 (parallel [(set (match_dup 0)
3750 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3752 (use (const_int 1))]))
3753 (cond_exec (ne (match_dup 5) (const_int 0))
3754 (parallel [(set (match_dup 4)
3755 (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3)))
3757 (use (const_int 1))]))
3758 (cond_exec (ne (match_dup 5) (const_int 0))
3760 (plus:TF (mult:TF (match_dup 4) (match_dup 0))
3763 "operands[6] = CONST1_RTX (TFmode);"
3764 [(set_attr "predicable" "no")])
3766 ;; ??? frcpa works like cmp.foo.unc.
3768 (define_insn "*recip_approx"
3769 [(set (match_operand:TF 0 "fr_register_operand" "=f")
3770 (div:TF (const_int 1)
3771 (match_operand:TF 3 "fr_register_operand" "f")))
3772 (set (match_operand:BI 1 "register_operand" "=c")
3773 (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
3775 (use (match_operand:SI 4 "const_int_operand" ""))]
3777 "frcpa.s%4 %0, %1 = %2, %3"
3778 [(set_attr "type" "F")
3779 (set_attr "predicable" "no")])
3781 ;; ::::::::::::::::::::
3783 ;; :: 32 bit Integer Shifts and Rotates
3785 ;; ::::::::::::::::::::
3787 (define_expand "ashlsi3"
3788 [(set (match_operand:SI 0 "gr_register_operand" "")
3789 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3790 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3794 if (GET_CODE (operands[2]) != CONST_INT)
3796 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3797 we've got to get rid of stray bits outside the SImode register. */
3798 rtx subshift = gen_reg_rtx (DImode);
3799 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3800 operands[2] = subshift;
3804 (define_insn "*ashlsi3_internal"
3805 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3806 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3807 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
3810 shladd %0 = %1, %2, r0
3811 dep.z %0 = %1, %2, %E2
3813 [(set_attr "type" "A,I,I")])
3815 (define_expand "ashrsi3"
3816 [(set (match_operand:SI 0 "gr_register_operand" "")
3817 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3818 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3822 rtx subtarget = gen_reg_rtx (DImode);
3823 if (GET_CODE (operands[2]) == CONST_INT)
3824 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3825 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3828 rtx subshift = gen_reg_rtx (DImode);
3829 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
3830 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3831 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
3833 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3837 (define_expand "lshrsi3"
3838 [(set (match_operand:SI 0 "gr_register_operand" "")
3839 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3840 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3844 rtx subtarget = gen_reg_rtx (DImode);
3845 if (GET_CODE (operands[2]) == CONST_INT)
3846 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3847 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3850 rtx subshift = gen_reg_rtx (DImode);
3851 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
3852 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3853 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
3855 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3859 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
3860 ;; here, instead of 64 like the patterns above.
3862 (define_expand "rotrsi3"
3864 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" ""))
3865 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3867 (lshiftrt:DI (match_dup 3)
3868 (match_operand:DI 2 "nonmemory_operand" "")))
3869 (set (match_operand:SI 0 "gr_register_operand" "") (match_dup 4))]
3873 if (! shift_32bit_count_operand (operands[2], SImode))
3875 operands[3] = gen_reg_rtx (DImode);
3876 operands[4] = gen_lowpart (SImode, operands[3]);
3879 ;; ::::::::::::::::::::
3881 ;; :: 64 bit Integer Shifts and Rotates
3883 ;; ::::::::::::::::::::
3885 (define_insn "ashldi3"
3886 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3887 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3888 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,rM")))]
3891 shladd %0 = %1, %2, r0
3893 [(set_attr "type" "A,I")])
3895 ;; ??? Maybe combine this with the multiply and add instruction?
3897 (define_insn "*shladd"
3898 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3899 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3900 (match_operand:DI 2 "shladd_operand" "n"))
3901 (match_operand:DI 3 "gr_register_operand" "r")))]
3903 "shladd %0 = %1, %S2, %3"
3904 [(set_attr "type" "A")])
3906 ;; This can be created by register elimination if operand3 of shladd is an
3907 ;; eliminable register or has reg_equiv_constant set.
3909 ;; We have to use nonmemory_operand for operand 4, to ensure that the
3910 ;; validate_changes call inside eliminate_regs will always succeed. If it
3911 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
3914 (define_insn_and_split "*shladd_elim"
3915 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
3916 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3917 (match_operand:DI 2 "shladd_operand" "n"))
3918 (match_operand:DI 3 "nonmemory_operand" "r"))
3919 (match_operand:DI 4 "nonmemory_operand" "rI")))]
3920 "reload_in_progress"
3923 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
3925 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
3927 [(set_attr "type" "unknown")])
3929 (define_insn "ashrdi3"
3930 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3931 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
3932 (match_operand:DI 2 "gr_reg_or_6bit_operand" "rM")))]
3935 [(set_attr "type" "I")])
3937 (define_insn "lshrdi3"
3938 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3939 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
3940 (match_operand:DI 2 "gr_reg_or_6bit_operand" "rM")))]
3943 [(set_attr "type" "I")])
3945 ;; Using a predicate that accepts only constants doesn't work, because optabs
3946 ;; will load the operand into a register and call the pattern if the predicate
3947 ;; did not accept it on the first try. So we use nonmemory_operand and then
3948 ;; verify that we have an appropriate constant in the expander.
3950 (define_expand "rotrdi3"
3951 [(set (match_operand:DI 0 "gr_register_operand" "")
3952 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
3953 (match_operand:DI 2 "nonmemory_operand" "")))]
3957 if (! shift_count_operand (operands[2], DImode))
3961 (define_insn "*rotrdi3_internal"
3962 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3963 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
3964 (match_operand:DI 2 "shift_count_operand" "M")))]
3966 "shrp %0 = %1, %1, %2"
3967 [(set_attr "type" "I")])
3970 ;; ::::::::::::::::::::
3972 ;; :: 32 bit Integer Logical operations
3974 ;; ::::::::::::::::::::
3976 ;; We don't seem to need any other 32-bit logical operations, because gcc
3977 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
3978 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
3979 ;; This doesn't work for unary logical operations, because we don't call
3980 ;; apply_distributive_law for them.
3982 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
3983 ;; apply_distributive_law. We get inefficient code for
3984 ;; int sub4 (int i, int j) { return i & ~j; }
3985 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
3986 ;; (zero_extend (and (not A) B)) in combine.
3987 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
3988 ;; one_cmplsi2 pattern.
3990 (define_insn "one_cmplsi2"
3991 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3992 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
3995 [(set_attr "type" "A")])
3997 ;; ::::::::::::::::::::
3999 ;; :: 64 bit Integer Logical operations
4001 ;; ::::::::::::::::::::
4003 (define_insn "anddi3"
4004 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4005 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4006 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4010 fand %0 = %2, %1%B0"
4011 [(set_attr "type" "A,F")])
4013 (define_insn "*andnot"
4014 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4015 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
4016 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4020 fandcm %0 = %2, %1%B0"
4021 [(set_attr "type" "A,F")])
4023 (define_insn "iordi3"
4024 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4025 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4026 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4031 [(set_attr "type" "A,F")])
4033 (define_insn "xordi3"
4034 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
4035 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
4036 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4040 fxor %0 = %2, %1%B0"
4041 [(set_attr "type" "A,F")])
4043 (define_insn "one_cmpldi2"
4044 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4045 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
4048 [(set_attr "type" "A")])
4050 ;; ::::::::::::::::::::
4054 ;; ::::::::::::::::::::
4056 (define_expand "cmpbi"
4058 (compare (match_operand:BI 0 "register_operand" "")
4059 (match_operand:BI 1 "const_int_operand" "")))]
4063 ia64_compare_op0 = operands[0];
4064 ia64_compare_op1 = operands[1];
4068 (define_expand "cmpsi"
4070 (compare (match_operand:SI 0 "gr_register_operand" "")
4071 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4075 ia64_compare_op0 = operands[0];
4076 ia64_compare_op1 = operands[1];
4080 (define_expand "cmpdi"
4082 (compare (match_operand:DI 0 "gr_register_operand" "")
4083 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4087 ia64_compare_op0 = operands[0];
4088 ia64_compare_op1 = operands[1];
4092 (define_expand "cmpsf"
4094 (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
4095 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
4099 ia64_compare_op0 = operands[0];
4100 ia64_compare_op1 = operands[1];
4104 (define_expand "cmpdf"
4106 (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
4107 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
4111 ia64_compare_op0 = operands[0];
4112 ia64_compare_op1 = operands[1];
4116 (define_expand "cmptf"
4118 (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
4119 (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
4123 ia64_compare_op0 = operands[0];
4124 ia64_compare_op1 = operands[1];
4128 (define_insn "*cmpsi_normal"
4129 [(set (match_operand:BI 0 "register_operand" "=c")
4130 (match_operator:BI 1 "normal_comparison_operator"
4131 [(match_operand:SI 2 "gr_register_operand" "r")
4132 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
4134 "cmp4.%C1 %0, %I0 = %3, %2"
4135 [(set_attr "type" "A")])
4137 (define_insn "*cmpsi_adjusted"
4138 [(set (match_operand:BI 0 "register_operand" "=c")
4139 (match_operator:BI 1 "adjusted_comparison_operator"
4140 [(match_operand:SI 2 "gr_register_operand" "r")
4141 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4143 "cmp4.%C1 %0, %I0 = %3, %2"
4144 [(set_attr "type" "A")])
4146 (define_insn "*cmpdi_normal"
4147 [(set (match_operand:BI 0 "register_operand" "=c")
4148 (match_operator:BI 1 "normal_comparison_operator"
4149 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
4150 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
4152 "cmp.%C1 %0, %I0 = %3, %r2"
4153 [(set_attr "type" "A")])
4155 (define_insn "*cmpdi_adjusted"
4156 [(set (match_operand:BI 0 "register_operand" "=c")
4157 (match_operator:BI 1 "adjusted_comparison_operator"
4158 [(match_operand:DI 2 "gr_register_operand" "r")
4159 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4161 "cmp.%C1 %0, %I0 = %3, %2"
4162 [(set_attr "type" "A")])
4164 (define_insn "*cmpsf_internal"
4165 [(set (match_operand:BI 0 "register_operand" "=c")
4166 (match_operator:BI 1 "comparison_operator"
4167 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
4168 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
4170 "fcmp.%D1 %0, %I0 = %F2, %F3"
4171 [(set_attr "type" "F")])
4173 (define_insn "*cmpdf_internal"
4174 [(set (match_operand:BI 0 "register_operand" "=c")
4175 (match_operator:BI 1 "comparison_operator"
4176 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
4177 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
4179 "fcmp.%D1 %0, %I0 = %F2, %F3"
4180 [(set_attr "type" "F")])
4182 (define_insn "*cmptf_internal"
4183 [(set (match_operand:BI 0 "register_operand" "=c")
4184 (match_operator:BI 1 "comparison_operator"
4185 [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG")
4186 (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))]
4188 "fcmp.%D1 %0, %I0 = %F2, %F3"
4189 [(set_attr "type" "F")])
4191 ;; ??? Can this pattern be generated?
4193 (define_insn "*bit_zero"
4194 [(set (match_operand:BI 0 "register_operand" "=c")
4195 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4197 (match_operand:DI 2 "immediate_operand" "n"))
4200 "tbit.z %0, %I0 = %1, %2"
4201 [(set_attr "type" "I")])
4203 (define_insn "*bit_one"
4204 [(set (match_operand:BI 0 "register_operand" "=c")
4205 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
4207 (match_operand:DI 2 "immediate_operand" "n"))
4210 "tbit.nz %0, %I0 = %1, %2"
4211 [(set_attr "type" "I")])
4213 ;; ::::::::::::::::::::
4217 ;; ::::::::::::::::::::
4219 (define_expand "beq"
4221 (if_then_else (match_dup 1)
4222 (label_ref (match_operand 0 "" ""))
4225 "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
4227 (define_expand "bne"
4229 (if_then_else (match_dup 1)
4230 (label_ref (match_operand 0 "" ""))
4233 "operands[1] = ia64_expand_compare (NE, VOIDmode);")
4235 (define_expand "blt"
4237 (if_then_else (match_dup 1)
4238 (label_ref (match_operand 0 "" ""))
4241 "operands[1] = ia64_expand_compare (LT, VOIDmode);")
4243 (define_expand "ble"
4245 (if_then_else (match_dup 1)
4246 (label_ref (match_operand 0 "" ""))
4249 "operands[1] = ia64_expand_compare (LE, VOIDmode);")
4251 (define_expand "bgt"
4253 (if_then_else (match_dup 1)
4254 (label_ref (match_operand 0 "" ""))
4257 "operands[1] = ia64_expand_compare (GT, VOIDmode);")
4259 (define_expand "bge"
4261 (if_then_else (match_dup 1)
4262 (label_ref (match_operand 0 "" ""))
4265 "operands[1] = ia64_expand_compare (GE, VOIDmode);")
4267 (define_expand "bltu"
4269 (if_then_else (match_dup 1)
4270 (label_ref (match_operand 0 "" ""))
4273 "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
4275 (define_expand "bleu"
4277 (if_then_else (match_dup 1)
4278 (label_ref (match_operand 0 "" ""))
4281 "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
4283 (define_expand "bgtu"
4285 (if_then_else (match_dup 1)
4286 (label_ref (match_operand 0 "" ""))
4289 "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
4291 (define_expand "bgeu"
4293 (if_then_else (match_dup 1)
4294 (label_ref (match_operand 0 "" ""))
4297 "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
4299 (define_expand "bunordered"
4301 (if_then_else (match_dup 1)
4302 (label_ref (match_operand 0 "" ""))
4305 "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
4307 (define_expand "bordered"
4309 (if_then_else (match_dup 1)
4310 (label_ref (match_operand 0 "" ""))
4313 "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
4315 (define_insn "*br_true"
4317 (if_then_else (match_operator 0 "predicate_operator"
4318 [(match_operand:BI 1 "register_operand" "c")
4320 (label_ref (match_operand 2 "" ""))
4323 "(%J0) br.cond%+ %l2"
4324 [(set_attr "type" "B")
4325 (set_attr "predicable" "no")])
4327 (define_insn "*br_false"
4329 (if_then_else (match_operator 0 "predicate_operator"
4330 [(match_operand:BI 1 "register_operand" "c")
4333 (label_ref (match_operand 2 "" ""))))]
4335 "(%j0) br.cond%+ %l2"
4336 [(set_attr "type" "B")
4337 (set_attr "predicable" "no")])
4339 ;; ::::::::::::::::::::
4341 ;; :: Counted loop operations
4343 ;; ::::::::::::::::::::
4345 (define_expand "doloop_end"
4346 [(use (match_operand 0 "" "")) ; loop pseudo
4347 (use (match_operand 1 "" "")) ; iterations; zero if unknown
4348 (use (match_operand 2 "" "")) ; max iterations
4349 (use (match_operand 3 "" "")) ; loop level
4350 (use (match_operand 4 "" ""))] ; label
4354 /* Only use cloop on innermost loops. */
4355 if (INTVAL (operands[3]) > 1)
4357 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
4362 (define_insn "doloop_end_internal"
4363 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
4365 (label_ref (match_operand 1 "" ""))
4367 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
4369 (plus:DI (match_dup 0) (const_int -1))))]
4371 "br.cloop.sptk.few %l1"
4372 [(set_attr "type" "B")
4373 (set_attr "predicable" "no")])
4375 ;; ::::::::::::::::::::
4377 ;; :: Set flag operations
4379 ;; ::::::::::::::::::::
4381 (define_expand "seq"
4382 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4384 "operands[1] = ia64_expand_compare (EQ, DImode);")
4386 (define_expand "sne"
4387 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4389 "operands[1] = ia64_expand_compare (NE, DImode);")
4391 (define_expand "slt"
4392 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4394 "operands[1] = ia64_expand_compare (LT, DImode);")
4396 (define_expand "sle"
4397 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4399 "operands[1] = ia64_expand_compare (LE, DImode);")
4401 (define_expand "sgt"
4402 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4404 "operands[1] = ia64_expand_compare (GT, DImode);")
4406 (define_expand "sge"
4407 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4409 "operands[1] = ia64_expand_compare (GE, DImode);")
4411 (define_expand "sltu"
4412 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4414 "operands[1] = ia64_expand_compare (LTU, DImode);")
4416 (define_expand "sleu"
4417 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4419 "operands[1] = ia64_expand_compare (LEU, DImode);")
4421 (define_expand "sgtu"
4422 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4424 "operands[1] = ia64_expand_compare (GTU, DImode);")
4426 (define_expand "sgeu"
4427 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4429 "operands[1] = ia64_expand_compare (GEU, DImode);")
4431 (define_expand "sunordered"
4432 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4434 "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
4436 (define_expand "sordered"
4437 [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
4439 "operands[1] = ia64_expand_compare (ORDERED, DImode);")
4441 ;; Don't allow memory as destination here, because cmov/cmov/st is more
4442 ;; efficient than mov/mov/cst/cst.
4444 (define_insn_and_split "*sne_internal"
4445 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4446 (ne:DI (match_operand:BI 1 "register_operand" "c")
4451 [(cond_exec (ne (match_dup 1) (const_int 0))
4452 (set (match_dup 0) (const_int 1)))
4453 (cond_exec (eq (match_dup 1) (const_int 0))
4454 (set (match_dup 0) (const_int 0)))]
4456 [(set_attr "type" "unknown")])
4458 (define_insn_and_split "*seq_internal"
4459 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4460 (eq:DI (match_operand:BI 1 "register_operand" "c")
4465 [(cond_exec (ne (match_dup 1) (const_int 0))
4466 (set (match_dup 0) (const_int 0)))
4467 (cond_exec (eq (match_dup 1) (const_int 0))
4468 (set (match_dup 0) (const_int 1)))]
4470 [(set_attr "type" "unknown")])
4472 ;; ::::::::::::::::::::
4474 ;; :: Conditional move instructions.
4476 ;; ::::::::::::::::::::
4478 ;; ??? Add movXXcc patterns?
4481 ;; DImode if_then_else patterns.
4484 ;; Errata 72 workaround.
4485 (define_insn "*cmovdi_internal_astep"
4486 [(set (match_operand:DI 0 "register_operand"
4487 "=r,*f,*b,r,*f,*b,r,*f,*b")
4489 (match_operator 4 "predicate_operator"
4490 [(match_operand:BI 1 "register_operand"
4491 "c,c,c,c,c,c,c,c,c")
4493 (match_operand:DI 2 "move_operand"
4494 "0,0,0,ri*f*b,rO,r,ri*f*b,rO,r")
4495 (match_operand:DI 3 "move_operand"
4496 "ri*f*b,rO,r,0,0,0,ri*f*b,rO,r")))]
4498 && ia64_move_ok (operands[0], operands[2])
4499 && ia64_move_ok (operands[0], operands[3])"
4501 [(set_attr "predicable" "no")])
4503 (define_insn "*cmovdi_internal"
4504 [(set (match_operand:DI 0 "destination_operand"
4505 "=r,m,*f,Q,*b,*d*e,r,m,*f,Q,*b,*d*e,r,m,*f,Q,*b,*d*e")
4507 (match_operator 4 "predicate_operator"
4508 [(match_operand:BI 1 "register_operand"
4509 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
4511 (match_operand:DI 2 "move_operand"
4512 "0,0,0,0,0,0,rim*f*b*d*e,rO,rOQ,*f,rO,rK,rim*f*b*d*e,rO,rOQ,*f,rO,rK")
4513 (match_operand:DI 3 "move_operand"
4514 "rim*f*b*d*e,rO,rOQ,*f,rO,rK,0,0,0,0,0,0,rim*f*b*d*e,rO,rOQ,*f,rO,rK")))]
4516 && ia64_move_ok (operands[0], operands[2])
4517 && ia64_move_ok (operands[0], operands[3])"
4519 [(set_attr "predicable" "no")])
4522 [(set (match_operand 0 "destination_operand" "")
4524 (match_operator 4 "predicate_operator"
4525 [(match_operand:BI 1 "register_operand" "")
4527 (match_operand 2 "move_operand" "")
4528 (match_operand 3 "move_operand" "")))]
4534 if (! rtx_equal_p (operands[0], operands[2]))
4536 tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]);
4537 tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp);
4540 if (! rtx_equal_p (operands[0], operands[3]))
4542 tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4543 VOIDmode, operands[1], const0_rtx);
4544 tmp = gen_rtx_COND_EXEC (VOIDmode, tmp,
4545 gen_rtx_SET (VOIDmode, operands[0],
4552 ;; Absolute value pattern.
4554 (define_insn "*absdi2_internal"
4555 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4557 (match_operator 4 "predicate_operator"
4558 [(match_operand:BI 1 "register_operand" "c,c")
4560 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4561 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
4564 [(set_attr "type" "A,unknown")
4565 (set_attr "predicable" "no")])
4568 [(set (match_operand:DI 0 "register_operand" "")
4570 (match_operator 4 "predicate_operator"
4571 [(match_operand:BI 1 "register_operand" "c,c")
4573 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4574 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4575 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4579 (neg:DI (match_dup 2))))]
4583 [(set (match_operand:DI 0 "register_operand" "")
4585 (match_operator 4 "predicate_operator"
4586 [(match_operand:BI 1 "register_operand" "c,c")
4588 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4589 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4593 (set (match_dup 0) (neg:DI (match_dup 2))))
4596 (set (match_dup 0) (match_dup 3)))]
4599 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4600 VOIDmode, operands[1], const0_rtx);
4604 ;; SImode if_then_else patterns.
4607 (define_insn "*cmovsi_internal_astep"
4608 [(set (match_operand:SI 0 "register_operand" "=r,*f,r,*f,r,*f")
4610 (match_operator 4 "predicate_operator"
4611 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c")
4613 (match_operand:SI 2 "move_operand" "0,0,ri*f,rO,ri*f,rO")
4614 (match_operand:SI 3 "move_operand" "ri*f,rO,0,0,ri*f,rO")))]
4616 && ia64_move_ok (operands[0], operands[2])
4617 && ia64_move_ok (operands[0], operands[3])"
4619 [(set_attr "predicable" "no")])
4621 (define_insn "*cmovsi_internal"
4622 [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
4624 (match_operator 4 "predicate_operator"
4625 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
4627 (match_operand:SI 2 "move_operand"
4628 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
4629 (match_operand:SI 3 "move_operand"
4630 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
4632 && ia64_move_ok (operands[0], operands[2])
4633 && ia64_move_ok (operands[0], operands[3])"
4635 [(set_attr "predicable" "no")])
4637 (define_insn "*abssi2_internal"
4638 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
4640 (match_operator 4 "predicate_operator"
4641 [(match_operand:BI 1 "register_operand" "c,c")
4643 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4644 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
4647 [(set_attr "type" "A,unknown")
4648 (set_attr "predicable" "no")])
4651 [(set (match_operand:SI 0 "register_operand" "")
4653 (match_operator 4 "predicate_operator"
4654 [(match_operand:BI 1 "register_operand" "c,c")
4656 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4657 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4658 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4662 (neg:SI (match_dup 2))))]
4666 [(set (match_operand:SI 0 "register_operand" "")
4668 (match_operator 4 "predicate_operator"
4669 [(match_operand:BI 1 "register_operand" "c,c")
4671 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4672 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4676 (set (match_dup 0) (neg:SI (match_dup 2))))
4679 (set (match_dup 0) (match_dup 3)))]
4682 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4683 VOIDmode, operands[1], const0_rtx);
4687 ;; ::::::::::::::::::::
4689 ;; :: Call and branch instructions
4691 ;; ::::::::::::::::::::
4693 ;; Subroutine call instruction returning no value. Operand 0 is the function
4694 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4695 ;; `SImode', except it is normally a
`const_int'); operand 2 is the number of
4696 ;; registers used as operands.
4698 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4699 ;; is supplied for the sake of some RISC machines which need to put this
4700 ;; information into the assembler code; they can put it in the RTL instead of
4703 (define_expand "call"
4704 [(use (match_operand:DI 0 "" ""))
4705 (use (match_operand 1 "" ""))
4706 (use (match_operand 2 "" ""))
4707 (use (match_operand 3 "" ""))]
4711 /* ??? Stripping off the MEM isn't correct. Will lose alias info. */
4712 rtx addr = XEXP (operands[0], 0);
4713 enum machine_mode mode = GET_MODE (addr);
4715 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
4716 emit_call_insn (gen_call_internal (addr, operands[1],
4717 gen_rtx_REG (DImode, R_BR (0))));
4719 /* If this is an indirect call, then we have the address of a descriptor. */
4720 else if (! symbolic_operand (addr, mode))
4721 emit_insn (gen_indirect_call_pic (addr, operands[1]));
4722 else if (TARGET_CONST_GP)
4723 emit_call_insn (gen_call_internal (addr, operands[1],
4724 gen_rtx_REG (DImode, R_BR (0))));
4726 emit_insn (gen_call_pic (addr, operands[1]));
4731 (define_expand "indirect_call_pic"
4732 [(set (match_dup 2) (reg:DI 1))
4733 (set (match_dup 3) (mem:DI (match_operand 0 "" "")))
4734 (set (match_dup 4) (plus:DI (match_dup 0) (const_int 8)))
4735 (set (reg:DI 1) (mem:DI (match_dup 4)))
4736 (parallel [(call (mem:DI (match_dup 3)) (match_operand 1 "" ""))
4738 (clobber (reg:DI 320))])
4739 (set (reg:DI 1) (match_dup 2))]
4743 operands[2] = ia64_gp_save_reg (0);
4744 operands[3] = gen_reg_rtx (DImode);
4745 operands[4] = gen_reg_rtx (DImode);
4748 ;; ??? Saving/restoring the GP register is not needed if we are calling
4749 ;; a function in the same module.
4751 (define_expand "call_pic"
4752 [(set (match_dup 2) (reg:DI 1))
4753 (parallel [(call (mem:DI (match_operand 0 "" "")) (match_operand 1 "" ""))
4755 (clobber (reg:DI 320))])
4756 (set (reg:DI 1) (match_dup 2))]
4760 /* ??? Using setjmp_operand is an unsatisfying solution. Should rethink. */
4761 operands[2] = ia64_gp_save_reg (setjmp_operand (XEXP (operands[0], 0),
4765 (define_insn "call_internal"
4766 [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
4767 (match_operand 1 "" ""))
4768 (clobber (match_operand:DI 2 "register_operand" "=b"))]
4770 "br.call%+.many %2 = %0"
4771 [(set_attr "type" "B")])
4773 (define_insn "*call_internal1"
4774 [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
4775 (match_operand 1 "" ""))
4777 (clobber (match_operand:DI 2 "register_operand" "=b"))]
4779 "br.call%+.many %2 = %0"
4780 [(set_attr "type" "B")])
4782 ;; Subroutine call instruction returning a value. Operand 0 is the hard
4783 ;; register in which the value is returned. There are three more operands, the
4784 ;; same as the three operands of the `call' instruction (but with numbers
4785 ;; increased by one).
4787 ;; Subroutines that return
`BLKmode' objects use the `call' insn.
4789 (define_expand "call_value"
4790 [(use (match_operand
0 "" ""))
4791 (use (match_operand:DI
1 "" ""))
4792 (use (match_operand
2 "" ""))
4793 (use (match_operand
3 "" ""))
4794 (use (match_operand
4 "" ""))]
4798 /* ??? Stripping off the MEM isn't correct. Will lose alias info. */
4799 rtx addr = XEXP (operands[
1],
0);
4800 enum machine_mode mode = GET_MODE (addr);
4802 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
4803 emit_call_insn (gen_call_value_internal (operands[
0], addr, operands[
2],
4804 gen_rtx_REG (DImode, R_BR (
0))));
4806 /* If this is an indirect call, then we have the address of a descriptor. */
4807 else if (! symbolic_operand (addr, mode))
4809 /* This is for HFA returns. */
4810 if (GET_CODE (operands[
0]) == PARALLEL)
4811 emit_insn (gen_indirect_call_multiple_values_pic (operands[
0], addr,
4814 emit_insn (gen_indirect_call_value_pic (operands[
0], addr,
4817 else if (TARGET_CONST_GP)
4818 emit_call_insn (gen_call_value_internal (operands[
0], addr, operands[
2],
4819 gen_rtx_REG (DImode, R_BR (
0))));
4820 /* This is for HFA returns. */
4821 else if (GET_CODE (operands[
0]) == PARALLEL)
4822 emit_insn (gen_call_multiple_values_pic (operands[
0], addr, operands[
2]));
4824 emit_insn (gen_call_value_pic (operands[
0], addr, operands[
2]));
4829 (define_expand "indirect_call_value_pic"
4830 [(set (match_dup
3) (reg:DI
1))
4831 (set (match_dup
4) (mem:DI (match_operand
1 "" "")))
4832 (set (match_dup
5) (plus:DI (match_dup
1) (const_int
8)))
4833 (set (reg:DI
1) (mem:DI (match_dup
5)))
4834 (parallel [(set (match_operand
0 "" "")
4835 (call (mem:DI (match_dup
4)) (match_operand
2 "" "")))
4837 (clobber (reg:DI
320))])
4838 (set (reg:DI
1) (match_dup
3))]
4842 operands[
3] = ia64_gp_save_reg (
0);
4843 operands[
4] = gen_reg_rtx (DImode);
4844 operands[
5] = gen_reg_rtx (DImode);
4847 (define_expand "indirect_call_multiple_values_pic"
4848 [(set (match_dup
3) (reg:DI
1))
4849 (set (match_dup
4) (mem:DI (match_operand
1 "" "")))
4850 (set (match_dup
5) (plus:DI (match_dup
1) (const_int
8)))
4851 (set (reg:DI
1) (mem:DI (match_dup
5)))
4852 (match_par_dup
6 [(set (match_operand
0 "" "")
4853 (call (mem:DI (match_dup
4))
4854 (match_operand
2 "" "")))
4856 (clobber (reg:DI
320))])
4857 (set (reg:DI
1) (match_dup
3))]
4865 operands[
3] = ia64_gp_save_reg (
0);
4866 operands[
4] = gen_reg_rtx (DImode);
4867 operands[
5] = gen_reg_rtx (DImode);
4869 /* This code is the same as the code in call_multiple_values_pic, except
4870 that op3 was replaced with op6 and op1 was replaced with op4. */
4871 call = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (DImode, operands[
4]),
4874 count = XVECLEN (operands[
0],
0);
4875 operands[
6] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count +
2));
4877 XVECEXP (operands[
6],
0,
0)
4878 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[
0],
0,
0),
0), call);
4880 XVECEXP (operands[
6],
0,
1)
4881 = gen_rtx_USE (DImode, gen_rtx_REG (DImode, GR_REG (
1)));
4882 XVECEXP (operands[
6],
0,
2)
4883 = gen_rtx_CLOBBER (DImode, gen_rtx_REG (DImode, BR_REG (
0)));
4885 for (i =
1; i < count; i++)
4886 XVECEXP (operands[
6],
0, i +
2)
4887 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[
0],
0, i),
0), call);
4891 ;; ??? Saving/restoring the GP register is not needed if we are calling
4892 ;; a function in the same module.
4894 (define_expand "call_value_pic"
4895 [(set (match_dup
3) (reg:DI
1))
4896 (parallel [(set (match_operand
0 "" "")
4897 (call (mem:DI (match_operand
1 "" ""))
4898 (match_operand
2 "" "")))
4900 (clobber (reg:DI
320))])
4901 (set (reg:DI
1) (match_dup
3))]
4905 /* ??? Using setjmp_operand is an unsatisfying solution. Should rethink. */
4906 operands[
3] = ia64_gp_save_reg (setjmp_operand (XEXP (operands[
1],
0),
4910 ;; ??? Saving/restoring the GP register is not needed if we are calling
4911 ;; a function in the same module.
4913 (define_expand "call_multiple_values_pic"
4914 [(set (match_dup
4) (reg:DI
1))
4915 (match_par_dup
3 [(set (match_operand
0 "" "")
4916 (call (mem:DI (match_operand
1 "" ""))
4917 (match_operand
2 "" "")))
4919 (clobber (reg:DI
320))])
4920 (set (reg:DI
1) (match_dup
4))]
4928 operands[
4] = ia64_gp_save_reg (
0);
4930 call = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (DImode, operands[
1]),
4933 count = XVECLEN (operands[
0],
0);
4934 operands[
3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count +
2));
4936 XVECEXP (operands[
3],
0,
0)
4937 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[
0],
0,
0),
0), call);
4939 XVECEXP (operands[
3],
0,
1)
4940 = gen_rtx_USE (DImode, gen_rtx_REG (DImode, GR_REG (
1)));
4941 XVECEXP (operands[
3],
0,
2)
4942 = gen_rtx_CLOBBER (DImode, gen_rtx_REG (DImode, BR_REG (
0)));
4944 for (i =
1; i < count; i++)
4945 XVECEXP (operands[
3],
0, i +
2)
4946 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[
0],
0, i),
0), call);
4949 (define_insn "call_value_internal"
4950 [(set (match_operand
0 "register_operand" "=rf")
4951 (call (mem:DI (match_operand:DI
1 "call_operand" "bi"))
4952 (match_operand
2 "" "")))
4953 (clobber (match_operand:DI
3 "register_operand" "=b"))]
4955 "br.call%+.many %
3 = %
1"
4956 [(set_attr "type" "B")])
4958 (define_insn "*call_value_internal1"
4959 [(set (match_operand
0 "register_operand" "=rf")
4960 (call (mem:DI (match_operand:DI
1 "call_operand" "bi"))
4961 (match_operand
2 "" "")))
4963 (clobber (match_operand:DI
3 "register_operand" "=b"))]
4965 "br.call%+.many %
3 = %
1"
4966 [(set_attr "type" "B")])
4968 (define_insn "*call_multiple_values_internal1"
4969 [(match_parallel
0 "call_multiple_values_operation"
4970 [(set (match_operand
1 "register_operand" "=rf")
4971 (call (mem:DI (match_operand:DI
2 "call_operand" "bi"))
4972 (match_operand
3 "" "")))
4974 (clobber (match_operand:DI
4 "register_operand" "=b"))])]
4976 "br.call%+.many %
4 = %
2"
4977 [(set_attr "type" "B")])
4979 ;; Call subroutine returning any type.
4981 (define_expand "untyped_call"
4982 [(parallel [(call (match_operand
0 "" "")
4984 (match_operand
1 "" "")
4985 (match_operand
2 "" "")])]
4991 emit_call_insn (gen_call (operands[
0], const0_rtx, NULL, const0_rtx));
4993 for (i =
0; i < XVECLEN (operands[
2],
0); i++)
4995 rtx set = XVECEXP (operands[
2],
0, i);
4996 emit_move_insn (SET_DEST (set), SET_SRC (set));
4999 /* The optimizer does not know that the call sets the function value
5000 registers we stored in the result block. We avoid problems by
5001 claiming that all hard registers are used and clobbered at this
5003 emit_insn (gen_blockage ());
5008 (define_insn "return_internal"
5010 (use (match_operand:DI
0 "register_operand" "b"))]
5012 "br.ret.sptk.many %
0"
5013 [(set_attr "type" "B")])
5015 (define_insn "return"
5017 "ia64_direct_return ()"
5018 "br.ret.sptk.many rp"
5019 [(set_attr "type" "B")])
5021 (define_insn "*return_true"
5023 (if_then_else (match_operator
0 "predicate_operator"
5024 [(match_operand:BI
1 "register_operand" "c")
5028 "ia64_direct_return ()"
5029 "(%J0) br.ret%+.many rp"
5030 [(set_attr "type" "B")
5031 (set_attr "predicable" "no")])
5033 (define_insn "*return_false"
5035 (if_then_else (match_operator
0 "predicate_operator"
5036 [(match_operand:BI
1 "register_operand" "c")
5040 "ia64_direct_return ()"
5041 "(%j0) br.ret%+.many rp"
5042 [(set_attr "type" "B")
5043 (set_attr "predicable" "no")])
5046 [(set (pc) (label_ref (match_operand
0 "" "")))]
5049 [(set_attr "type" "B")])
5051 (define_insn "indirect_jump"
5052 [(set (pc) (match_operand:DI
0 "register_operand" "b"))]
5055 [(set_attr "type" "B")])
5057 (define_expand "tablejump"
5058 [(match_operand:DI
0 "register_operand" "")
5059 (match_operand
1 "" "")]
5063 rtx tmp1 = gen_reg_rtx (DImode);
5064 rtx tmp2 = gen_reg_rtx (DImode);
5066 emit_move_insn (tmp1, gen_rtx_LABEL_REF (Pmode, operands[
1]));
5067 emit_insn (gen_adddi3 (tmp2, operands[
0], tmp1));
5068 emit_jump_insn (gen_tablejump_internal (tmp2, operands[
1]));
5072 (define_insn "tablejump_internal"
5073 [(set (pc) (match_operand:DI
0 "register_operand" "b"))
5074 (use (label_ref (match_operand
1 "" "")))]
5077 [(set_attr "type" "B")])
5080 ;; ::::::::::::::::::::
5082 ;; :: Prologue and Epilogue instructions
5084 ;; ::::::::::::::::::::
5086 (define_expand "prologue"
5091 ia64_expand_prologue ();
5095 (define_expand "epilogue"
5100 ia64_expand_epilogue ();
5104 ;; This prevents the scheduler from moving the SP decrement past FP-relative
5105 ;; stack accesses. This is the same as adddi3 plus the extra set.
5107 (define_insn "prologue_allocate_stack"
5108 [(set (match_operand:DI
0 "register_operand" "=r,r,r")
5109 (plus:DI (match_operand:DI
1 "register_operand" "%r,r,a")
5110 (match_operand:DI
2 "gr_reg_or_22bit_operand" "r,I,J")))
5111 (set (match_operand:DI
3 "register_operand" "=r,r,r")
5118 [(set_attr "type" "A")])
5120 ;; This prevents the scheduler from moving the SP restore past FP-relative
5121 ;; stack accesses. This is similar to movdi plus the extra set.
5123 (define_insn "epilogue_deallocate_stack"
5124 [(set (match_operand:DI
0 "register_operand" "=r")
5125 (match_operand:DI
1 "register_operand" "+r"))
5126 (set (match_dup
1) (match_dup
1))]
5129 [(set_attr "type" "A")])
5131 ;; Allocate a new register frame.
5133 (define_insn "alloc"
5134 [(set (match_operand:DI
0 "register_operand" "=r")
5135 (unspec_volatile:DI [(const_int
0)]
0))
5136 (use (match_operand:DI
1 "const_int_operand" "i"))
5137 (use (match_operand:DI
2 "const_int_operand" "i"))
5138 (use (match_operand:DI
3 "const_int_operand" "i"))
5139 (use (match_operand:DI
4 "const_int_operand" "i"))]
5141 "alloc %
0 = ar.pfs, %
1, %
2, %
3, %
4"
5142 [(set_attr "type" "M")
5143 (set_attr "predicable" "no")])
5146 (define_expand "gr_spill"
5147 [(parallel [(set (match_operand:DI
0 "memory_operand" "=m")
5148 (unspec:DI [(match_operand:DI
1 "register_operand" "r")
5149 (match_operand:DI
2 "const_int_operand" "")]
1))
5150 (clobber (match_dup
3))])]
5152 "operands[
3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5154 (define_insn "gr_spill_internal"
5155 [(set (match_operand:DI
0 "memory_operand" "=m")
5156 (unspec:DI [(match_operand:DI
1 "register_operand" "r")
5157 (match_operand:DI
2 "const_int_operand" "")]
1))
5158 (clobber (match_operand:DI
3 "register_operand" ""))]
5160 ".mem.offset %
2,
0\;st8.spill %
0 = %
1%P0"
5161 [(set_attr "type" "M")])
5164 (define_expand "gr_restore"
5165 [(parallel [(set (match_operand:DI
0 "register_operand" "=r")
5166 (unspec:DI [(match_operand:DI
1 "memory_operand" "m")
5167 (match_operand:DI
2 "const_int_operand" "")]
2))
5168 (use (match_dup
3))])]
5170 "operands[
3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5172 (define_insn "gr_restore_internal"
5173 [(set (match_operand:DI
0 "register_operand" "=r")
5174 (unspec:DI [(match_operand:DI
1 "memory_operand" "m")
5175 (match_operand:DI
2 "const_int_operand" "")]
2))
5176 (use (match_operand:DI
3 "register_operand" ""))]
5178 ".mem.offset %
2,
0\;ld8.fill %
0 = %
1%P1"
5179 [(set_attr "type" "M")])
5181 (define_insn "fr_spill"
5182 [(set (match_operand:TF
0 "memory_operand" "=m")
5183 (unspec:TF [(match_operand:TF
1 "register_operand" "f")]
3))]
5185 "stf.spill %
0 = %
1%P0"
5186 [(set_attr "type" "M")])
5188 (define_insn "fr_restore"
5189 [(set (match_operand:TF
0 "register_operand" "=f")
5190 (unspec:TF [(match_operand:TF
1 "memory_operand" "m")]
4))]
5192 "ldf.fill %
0 = %
1%P1"
5193 [(set_attr "type" "M")])
5195 (define_insn "bsp_value"
5196 [(set (match_operand:DI
0 "register_operand" "=r")
5197 (unspec:DI [(const_int
0)]
20))]
5200 [(set_attr "type" "I")])
5202 (define_insn "set_bsp"
5203 [(unspec_volatile [(const_int
0)]
5)
5204 (use (match_operand:DI
0 "register_operand" "r"))]
5206 "flushrs\;mov r19=ar.rsc\;;;\;and r19=
0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%
0\;;;\;or r19=
0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
5207 [(set_attr "type" "unknown")
5208 (set_attr "predicable" "no")])
5210 (define_insn "flushrs"
5211 [(unspec [(const_int
0)]
21)]
5214 [(set_attr "type" "M")])
5216 ;; ::::::::::::::::::::
5218 ;; :: Miscellaneous instructions
5220 ;; ::::::::::::::::::::
5222 ;; ??? Emiting a NOP instruction isn't very useful. This should probably
5223 ;; be emitting ";;" to force a break in the instruction packing.
5225 ;; No operation, needed in case the user uses -g but not -O.
5230 [(set_attr "type" "unknown")])
5232 ;; Pseudo instruction that prevents the scheduler from moving code above this
5234 (define_insn "blockage"
5235 [(unspec_volatile [(const_int
0)]
1)]
5238 [(set_attr "type" "unknown")
5239 (set_attr "predicable" "no")])
5241 (define_insn "insn_group_barrier"
5242 [(unspec_volatile [(const_int
0)]
2)]
5245 [(set_attr "type" "S")
5246 (set_attr "predicable" "no")])
5249 ;; Non-local goto support.
5251 (define_expand "save_stack_nonlocal"
5252 [(use (match_operand:OI
0 "memory_operand" ""))
5253 (use (match_operand:DI
1 "register_operand" ""))]
5257 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5258 \"__ia64_save_stack_nonlocal
\"),
5259 0, VOIDmode,
2, XEXP (operands[
0],
0), Pmode,
5260 operands[
1], Pmode);
5264 (define_expand "nonlocal_goto"
5265 [(use (match_operand
0 "general_operand" ""))
5266 (use (match_operand
1 "general_operand" ""))
5267 (use (match_operand
2 "general_operand" ""))
5268 (use (match_operand
3 "general_operand" ""))]
5272 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
\"__ia64_nonlocal_goto
\"),
5275 copy_to_reg (XEXP (operands[
2],
0)), Pmode,
5276 operands[
3], Pmode);
5281 ;; Restore the GP after the exception/longjmp. The preceeding call will
5282 ;; have tucked it away.
5283 (define_expand "exception_receiver"
5284 [(set (reg:DI
1) (match_dup
0))]
5286 "operands[
0] = ia64_gp_save_reg (
0);")
5288 ;; The rest of the setjmp processing happens with the nonlocal_goto expander.
5289 ;; ??? This is not tested.
5290 (define_expand "builtin_setjmp_setup"
5291 [(use (match_operand:DI
0 "" ""))]
5295 emit_move_insn (ia64_gp_save_reg (
0), gen_rtx_REG (DImode, GR_REG (
1)));
5299 (define_expand "builtin_setjmp_receiver"
5300 [(use (match_operand:DI
0 "" ""))]
5304 emit_move_insn (gen_rtx_REG (DImode, GR_REG (
1)), ia64_gp_save_reg (
0));
5308 (define_expand "eh_epilogue"
5309 [(use (match_operand:DI
0 "register_operand" "r"))
5310 (use (match_operand:DI
1 "register_operand" "r"))
5311 (use (match_operand:DI
2 "register_operand" "r"))]
5315 rtx bsp = gen_rtx_REG (Pmode,
10);
5316 rtx sp = gen_rtx_REG (Pmode,
9);
5318 if (GET_CODE (operands[
0]) != REG || REGNO (operands[
0]) !=
10)
5320 emit_move_insn (bsp, operands[
0]);
5323 if (GET_CODE (operands[
2]) != REG || REGNO (operands[
2]) !=
9)
5325 emit_move_insn (sp, operands[
2]);
5328 emit_insn (gen_rtx_USE (VOIDmode, sp));
5329 emit_insn (gen_rtx_USE (VOIDmode, bsp));
5331 cfun->machine->ia64_eh_epilogue_sp = sp;
5332 cfun->machine->ia64_eh_epilogue_bsp = bsp;
5335 ;; Builtin apply support.
5337 (define_expand "restore_stack_nonlocal"
5338 [(use (match_operand:DI
0 "register_operand" ""))
5339 (use (match_operand:OI
1 "memory_operand" ""))]
5343 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5344 \"__ia64_restore_stack_nonlocal
\"),
5346 copy_to_reg (XEXP (operands[
1],
0)), Pmode);
5351 ;;; Intrinsics support.
5354 [(set (mem:BLK (match_dup
0))
5355 (unspec:BLK [(mem:BLK (match_dup
0))]
12))]
5359 operands[
0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
5360 MEM_VOLATILE_P (operands[
0]) =
1;
5363 (define_insn "*mf_internal"
5364 [(set (match_operand:BLK
0 "" "")
5365 (unspec:BLK [(match_operand:BLK
1 "" "")]
12))]
5368 [(set_attr "type" "M")])
5370 (define_insn "fetchadd_acq_si"
5371 [(set (match_operand:SI
0 "gr_register_operand" "=r")
5373 (set (match_operand:SI
1 "not_postinc_memory_operand" "+S")
5374 (unspec:SI [(match_dup
1)
5375 (match_operand:SI
2 "fetchadd_operand" "n")]
19))]
5377 "fetchadd4.acq %
0 = %
1, %
2"
5378 [(set_attr "type" "M")])
5380 (define_insn "fetchadd_acq_di"
5381 [(set (match_operand:DI
0 "gr_register_operand" "=r")
5383 (set (match_operand:DI
1 "not_postinc_memory_operand" "+S")
5384 (unspec:DI [(match_dup
1)
5385 (match_operand:DI
2 "fetchadd_operand" "n")]
19))]
5387 "fetchadd8.acq %
0 = %
1, %
2"
5388 [(set_attr "type" "M")])
5390 (define_insn "cmpxchg_acq_si"
5391 [(set (match_operand:SI
0 "gr_register_operand" "=r")
5393 (set (match_operand:SI
1 "not_postinc_memory_operand" "+S")
5394 (unspec:SI [(match_dup
1)
5395 (match_operand:SI
2 "gr_register_operand" "r")
5396 (match_operand:SI
3 "ar_ccv_reg_operand" "")]
13))]
5398 "cmpxchg4.acq %
0 = %
1, %
2, %
3"
5399 [(set_attr "type" "M")])
5401 (define_insn "cmpxchg_acq_di"
5402 [(set (match_operand:DI
0 "gr_register_operand" "=r")
5404 (set (match_operand:DI
1 "not_postinc_memory_operand" "+S")
5405 (unspec:DI [(match_dup
1)
5406 (match_operand:DI
2 "gr_register_operand" "r")
5407 (match_operand:DI
3 "ar_ccv_reg_operand" "")]
13))]
5409 "cmpxchg8.acq %
0 = %
1, %
2, %
3"
5410 [(set_attr "type" "M")])
5412 (define_insn "xchgsi"
5413 [(set (match_operand:SI
0 "gr_register_operand" "=r")
5414 (match_operand:SI
1 "not_postinc_memory_operand" "+S"))
5416 (match_operand:SI
2 "gr_register_operand" "r"))]
5419 [(set_attr "type" "M")])
5421 (define_insn "xchgdi"
5422 [(set (match_operand:DI
0 "gr_register_operand" "=r")
5423 (match_operand:DI
1 "not_postinc_memory_operand" "+S"))
5425 (match_operand:DI
2 "gr_register_operand" "r"))]
5428 [(set_attr "type" "M")])
5433 [(match_operator
0 "predicate_operator"
5434 [(match_operand:BI
1 "register_operand" "c")
5439 (define_insn "pred_rel_mutex"
5440 [(set (match_operand:BI
0 "register_operand" "+c")
5441 (unspec:BI [(match_dup
0)]
7))]
5443 ".pred.rel.mutex %
0, %I0"
5444 [(set_attr "type" "unknown")
5445 (set_attr "predicable" "no")])
5447 (define_insn "safe_across_calls_all"
5448 [(unspec_volatile [(const_int
0)]
8)]
5450 ".pred.safe_across_calls p1-p63"
5451 [(set_attr "type" "unknown")
5452 (set_attr "predicable" "no")])
5454 (define_insn "safe_across_calls_normal"
5455 [(unspec_volatile [(const_int
0)]
9)]
5459 emit_safe_across_calls (asm_out_file);
5462 [(set_attr "type" "unknown")
5463 (set_attr "predicable" "no")])