1 ;; IA-
64 Machine description template
2 ;; Copyright (C)
1999,
2000,
2001,
2002,
2003 Free Software Foundation, Inc.
3 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
4 ;; David Mosberger <davidm@hpl.hp.com>.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version
2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
21 ;; Boston, MA
02111-
1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26 ;; reload. This will be fixed once scheduling support is turned on.
28 ;; ??? Optimize for post-increment addressing modes.
30 ;; ??? fselect is not supported, because there is no integer register
33 ;; ??? fp abs/min/max instructions may also work for integer values.
35 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36 ;; it assumes the operand is a register and takes REGNO of it without checking.
38 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39 ;; it assumes the operand is a register and takes REGNO of it without checking.
41 ;; ??? Go through list of documented named patterns and look for more to
44 ;; ??? Go through instruction manual and look for more instructions that
47 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
49 ;; ??? Need a better way to describe alternate fp status registers.
53 (UNSPEC_LTOFF_DTPMOD
0)
54 (UNSPEC_LTOFF_DTPREL
1)
56 (UNSPEC_LTOFF_TPREL
3)
61 (UNSPEC_GR_RESTORE
11)
63 (UNSPEC_FR_RESTORE
13)
64 (UNSPEC_FR_RECIP_APPROX
14)
65 (UNSPEC_PRED_REL_MUTEX
15)
69 (UNSPEC_CMPXCHG_ACQ
19)
70 (UNSPEC_FETCHADD_ACQ
20)
73 (UNSPEC_BUNDLE_SELECTOR
23)
75 (UNSPEC_PROLOGUE_USE
25)
78 (UNSPEC_FR_SQRT_RECIP_APPROX
28)
84 (UNSPECV_INSN_GROUP_BARRIER
2)
87 (UNSPECV_PSAC_ALL
5) ; pred.safe_across_calls
88 (UNSPECV_PSAC_NORMAL
6)
89 (UNSPECV_SETJMP_RECEIVER
7)
92 ;; ::::::::::::::::::::
96 ;; ::::::::::::::::::::
98 ;; Processor type. This attribute must exactly match the processor_type
99 ;; enumeration in ia64.h.
100 (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune")))
102 ;; Instruction type. This primarily determines how instructions can be
103 ;; packed in bundles, and secondarily affects scheduling to function units.
105 ;; A alu, can go in I or M syllable of a bundle
110 ;; L long immediate, takes two syllables
113 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
114 ;; check this in md_reorg? Currently use unknown for patterns which emit
115 ;; multiple instructions, patterns which emit
0 instructions, and patterns
116 ;; which emit instruction that can go in any slot (e.g. nop).
118 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
119 fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
120 chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
121 syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f,
122 nop_i,nop_m,nop_x,lfetch,pre_cycle"
123 (const_string "unknown"))
125 ;; chk_s has an I and an M form; use type A for convenience.
126 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
127 (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M")
128 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
129 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
130 (eq_attr "itanium_class" "lfetch") (const_string "M")
131 (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A")
132 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
133 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
134 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
135 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
136 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
137 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
138 (eq_attr "itanium_class" "stop_bit") (const_string "S")
139 (eq_attr "itanium_class" "nop_x") (const_string "X")
140 (eq_attr "itanium_class" "long_i") (const_string "L")]
141 (const_string "unknown")))
143 (define_attr "itanium_requires_unit0" "no,yes"
144 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
145 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
146 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
147 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
148 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
149 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
150 (const_string "no")))
152 ;; Predication. True iff this instruction can be predicated.
154 (define_attr "predicable" "no,yes" (const_string "yes"))
158 ;; DFA descriptions of ia64 processors used for insn scheduling and
161 (automata_option "ndfa")
163 ;; Uncomment the following line to output automata for debugging.
164 ;; (automata_option "v")
166 (automata_option "w")
168 ;;(automata_option "no-minimization")
171 (include "itanium1.md")
172 (include "itanium2.md")
175 ;; ::::::::::::::::::::
179 ;; ::::::::::::::::::::
181 ;; Set of a single predicate register. This is only used to implement
182 ;; pr-to-pr move and complement.
184 (define_insn "*movcci"
185 [(set (match_operand:CCI
0 "register_operand" "=c,c,c")
186 (match_operand:CCI
1 "nonmemory_operand" "O,n,c"))]
189 cmp.ne %
0, p0 = r0, r0
190 cmp.eq %
0, p0 = r0, r0
191 (%
1) cmp.eq.unc %
0, p0 = r0, r0"
192 [(set_attr "itanium_class" "icmp")
193 (set_attr "predicable" "no")])
196 [(set (match_operand:BI
0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
197 (match_operand:BI
1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
200 cmp.ne %
0, %I0 = r0, r0
201 cmp.eq %
0, %I0 = r0, r0
204 tbit.nz %
0, %I0 = %
1,
0
209 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
212 [(set (match_operand:BI
0 "register_operand" "")
213 (match_operand:BI
1 "register_operand" ""))]
215 && GET_CODE (operands[
0]) == REG && GR_REGNO_P (REGNO (operands[
0]))
216 && GET_CODE (operands[
1]) == REG && PR_REGNO_P (REGNO (operands[
1]))"
217 [(cond_exec (ne (match_dup
1) (const_int
0))
218 (set (match_dup
0) (const_int
1)))
219 (cond_exec (eq (match_dup
1) (const_int
0))
220 (set (match_dup
0) (const_int
0)))]
224 [(set (match_operand:BI
0 "register_operand" "")
225 (match_operand:BI
1 "register_operand" ""))]
227 && GET_CODE (operands[
0]) == REG && PR_REGNO_P (REGNO (operands[
0]))
228 && GET_CODE (operands[
1]) == REG && PR_REGNO_P (REGNO (operands[
1]))"
229 [(set (match_dup
2) (match_dup
4))
230 (set (match_dup
3) (match_dup
5))
231 (set (match_dup
0) (unspec:BI [(match_dup
0)] UNSPEC_PRED_REL_MUTEX))]
232 "operands[
2] = gen_rtx_REG (CCImode, REGNO (operands[
0]));
233 operands[
3] = gen_rtx_REG (CCImode, REGNO (operands[
0]) +
1);
234 operands[
4] = gen_rtx_REG (CCImode, REGNO (operands[
1]));
235 operands[
5] = gen_rtx_REG (CCImode, REGNO (operands[
1]) +
1);")
237 (define_expand "movqi"
238 [(set (match_operand:QI
0 "general_operand" "")
239 (match_operand:QI
1 "general_operand" ""))]
242 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
248 (define_insn "*movqi_internal"
249 [(set (match_operand:QI
0 "destination_operand" "=r,r,r, m, r,*f,*f")
250 (match_operand:QI
1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
251 "ia64_move_ok (operands[
0], operands[
1])"
260 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
262 (define_expand "movhi"
263 [(set (match_operand:HI
0 "general_operand" "")
264 (match_operand:HI
1 "general_operand" ""))]
267 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
273 (define_insn "*movhi_internal"
274 [(set (match_operand:HI
0 "destination_operand" "=r,r,r, m, r,*f,*f")
275 (match_operand:HI
1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
276 "ia64_move_ok (operands[
0], operands[
1])"
285 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
287 (define_expand "movsi"
288 [(set (match_operand:SI
0 "general_operand" "")
289 (match_operand:SI
1 "general_operand" ""))]
292 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
298 (define_insn "*movsi_internal"
299 [(set (match_operand:SI
0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
300 (match_operand:SI
1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))]
301 "ia64_move_ok (operands[
0], operands[
1])"
313 ;; frar_m, toar_m ??? why not frar_i and toar_i
314 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
316 (define_expand "movdi"
317 [(set (match_operand:DI
0 "general_operand" "")
318 (match_operand:DI
1 "general_operand" ""))]
321 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
327 (define_insn "*movdi_internal"
328 [(set (match_operand:DI
0 "destination_operand"
329 "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
330 (match_operand:DI
1 "move_operand"
331 "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
332 "ia64_move_ok (operands[
0], operands[
1])"
334 static const char * const alt[] = {
336 "%,addl %
0 = %
1, r0",
338 "%,ld8%O1 %
0 = %
1%P1",
339 "%,st8%Q0 %
0 = %r1%P0",
340 "%,getf.sig %
0 = %
1",
341 "%,setf.sig %
0 = %r1",
355 if (which_alternative ==
2 && ! TARGET_NO_PIC
356 && symbolic_operand (operands[
1], VOIDmode))
359 return alt[which_alternative];
361 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
364 [(set (match_operand
0 "register_operand" "")
365 (match_operand
1 "symbolic_operand" ""))]
366 "reload_completed && ! TARGET_NO_PIC"
369 ia64_expand_load_address (operands[
0], operands[
1]);
373 (define_expand "load_fptr"
375 (plus:DI (reg:DI
1) (match_operand
1 "function_operand" "")))
376 (set (match_operand:DI
0 "register_operand" "") (match_dup
3))]
379 operands[
2] = no_new_pseudos ? operands[
0] : gen_reg_rtx (DImode);
380 operands[
3] = gen_rtx_MEM (DImode, operands[
2]);
381 RTX_UNCHANGING_P (operands[
3]) =
1;
384 (define_insn "*load_fptr_internal1"
385 [(set (match_operand:DI
0 "register_operand" "=r")
386 (plus:DI (reg:DI
1) (match_operand
1 "function_operand" "s")))]
388 "addl %
0 = @ltoff(@fptr(%
1)), gp"
389 [(set_attr "itanium_class" "ialu")])
391 (define_insn "load_gprel"
392 [(set (match_operand:DI
0 "register_operand" "=r")
393 (plus:DI (reg:DI
1) (match_operand
1 "sdata_symbolic_operand" "s")))]
395 "addl %
0 = @gprel(%
1), gp"
396 [(set_attr "itanium_class" "ialu")])
398 (define_insn "gprel64_offset"
399 [(set (match_operand:DI
0 "register_operand" "=r")
400 (minus:DI (match_operand:DI
1 "symbolic_operand" "") (reg:DI
1)))]
402 "movl %
0 = @gprel(%
1)"
403 [(set_attr "itanium_class" "long_i")])
405 (define_expand "load_gprel64"
407 (minus:DI (match_operand:DI
1 "symbolic_operand" "") (match_dup
3)))
408 (set (match_operand:DI
0 "register_operand" "")
409 (plus:DI (match_dup
3) (match_dup
2)))]
412 operands[
2] = no_new_pseudos ? operands[
0] : gen_reg_rtx (DImode);
413 operands[
3] = pic_offset_table_rtx;
416 ;; This is used as a placeholder for the return address during early
417 ;; compilation. We won't know where we've placed this until during
418 ;; reload, at which point it can wind up in b0, a general register,
419 ;; or memory. The only safe destination under these conditions is a
422 (define_insn_and_split "*movdi_ret_addr"
423 [(set (match_operand:DI
0 "register_operand" "=r")
424 (unspec:DI [(const_int
0)] UNSPEC_RET_ADDR))]
430 ia64_split_return_addr_rtx (operands[
0]);
433 [(set_attr "itanium_class" "ialu")])
435 (define_insn "*load_symptr_high"
436 [(set (match_operand:DI
0 "register_operand" "=r")
437 (plus:DI (high:DI (match_operand
1 "got_symbolic_operand" "s"))
438 (match_operand:DI
2 "register_operand" "a")))]
441 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
442 return "%,addl %
0 = @ltoffx(%
1), %
2";
444 return "%,addl %
0 = @ltoff(%
1), %
2";
446 [(set_attr "itanium_class" "ialu")])
448 (define_insn "*load_symptr_low"
449 [(set (match_operand:DI
0 "register_operand" "=r")
450 (lo_sum:DI (match_operand:DI
1 "register_operand" "r")
451 (match_operand
2 "got_symbolic_operand" "s")))]
454 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
455 return "%,ld8.mov %
0 = [%
1], %
2";
457 return "%,ld8 %
0 = [%
1]";
459 [(set_attr "itanium_class" "ld")])
461 (define_insn "load_ltoff_dtpmod"
462 [(set (match_operand:DI
0 "register_operand" "=r")
464 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
465 UNSPEC_LTOFF_DTPMOD)))]
467 "addl %
0 = @ltoff(@dtpmod(%
1)), gp"
468 [(set_attr "itanium_class" "ialu")])
470 (define_insn "load_ltoff_dtprel"
471 [(set (match_operand:DI
0 "register_operand" "=r")
473 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
474 UNSPEC_LTOFF_DTPREL)))]
476 "addl %
0 = @ltoff(@dtprel(%
1)), gp"
477 [(set_attr "itanium_class" "ialu")])
479 (define_expand "load_dtprel"
480 [(set (match_operand:DI
0 "register_operand" "")
481 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
486 (define_insn "*load_dtprel64"
487 [(set (match_operand:DI
0 "register_operand" "=r")
488 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
491 "movl %
0 = @dtprel(%
1)"
492 [(set_attr "itanium_class" "long_i")])
494 (define_insn "*load_dtprel22"
495 [(set (match_operand:DI
0 "register_operand" "=r")
496 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
499 "addl %
0 = @dtprel(%
1), r0"
500 [(set_attr "itanium_class" "ialu")])
502 (define_expand "add_dtprel"
503 [(set (match_operand:DI
0 "register_operand" "")
504 (plus:DI (match_operand:DI
1 "register_operand" "")
505 (unspec:DI [(match_operand:DI
2 "symbolic_operand" "")]
510 (define_insn "*add_dtprel14"
511 [(set (match_operand:DI
0 "register_operand" "=r")
512 (plus:DI (match_operand:DI
1 "register_operand" "r")
513 (unspec:DI [(match_operand:DI
2 "symbolic_operand" "")]
516 "adds %
0 = @dtprel(%
2), %
1"
517 [(set_attr "itanium_class" "ialu")])
519 (define_insn "*add_dtprel22"
520 [(set (match_operand:DI
0 "register_operand" "=r")
521 (plus:DI (match_operand:DI
1 "register_operand" "a")
522 (unspec:DI [(match_operand:DI
2 "symbolic_operand" "")]
525 "addl %
0 = @dtprel(%
2), %
1"
526 [(set_attr "itanium_class" "ialu")])
528 (define_insn "load_ltoff_tprel"
529 [(set (match_operand:DI
0 "register_operand" "=r")
531 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
532 UNSPEC_LTOFF_TPREL)))]
534 "addl %
0 = @ltoff(@tprel(%
1)), gp"
535 [(set_attr "itanium_class" "ialu")])
537 (define_expand "load_tprel"
538 [(set (match_operand:DI
0 "register_operand" "")
539 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
544 (define_insn "*load_tprel64"
545 [(set (match_operand:DI
0 "register_operand" "=r")
546 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
549 "movl %
0 = @tprel(%
1)"
550 [(set_attr "itanium_class" "long_i")])
552 (define_insn "*load_tprel22"
553 [(set (match_operand:DI
0 "register_operand" "=r")
554 (unspec:DI [(match_operand:DI
1 "symbolic_operand" "")]
557 "addl %
0 = @tprel(%
1), r0"
558 [(set_attr "itanium_class" "ialu")])
560 (define_expand "add_tprel"
561 [(set (match_operand:DI
0 "register_operand" "")
562 (plus:DI (match_operand:DI
1 "register_operand" "")
563 (unspec:DI [(match_operand:DI
2 "symbolic_operand" "")]
568 (define_insn "*add_tprel14"
569 [(set (match_operand:DI
0 "register_operand" "=r")
570 (plus:DI (match_operand:DI
1 "register_operand" "r")
571 (unspec:DI [(match_operand:DI
2 "symbolic_operand" "")]
574 "adds %
0 = @tprel(%
2), %
1"
575 [(set_attr "itanium_class" "ialu")])
577 (define_insn "*add_tprel22"
578 [(set (match_operand:DI
0 "register_operand" "=r")
579 (plus:DI (match_operand:DI
1 "register_operand" "a")
580 (unspec:DI [(match_operand:DI
2 "symbolic_operand" "")]
583 "addl %
0 = @tprel(%
2), %
1"
584 [(set_attr "itanium_class" "ialu")])
586 ;; With no offsettable memory references, we've got to have a scratch
587 ;; around to play with the second word.
588 (define_expand "movti"
589 [(parallel [(set (match_operand:TI
0 "general_operand" "")
590 (match_operand:TI
1 "general_operand" ""))
591 (clobber (match_scratch:DI
2 ""))])]
594 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
600 (define_insn_and_split "*movti_internal"
601 [(set (match_operand:TI
0 "nonimmediate_operand" "=r,r,m")
602 (match_operand:TI
1 "general_operand" "ri,m,r"))
603 (clobber (match_scratch:DI
2 "=X,&r,&r"))]
604 "ia64_move_ok (operands[
0], operands[
1])"
609 ia64_split_tmode_move (operands);
612 [(set_attr "itanium_class" "unknown")
613 (set_attr "predicable" "no")])
615 (define_expand "reload_inti"
616 [(parallel [(set (match_operand:TI
0 "register_operand" "=r")
617 (match_operand:TI
1 "memory_operand" "m"))
618 (clobber (match_operand:DI
2 "register_operand" "=&r"))])]
622 (define_expand "reload_outti"
623 [(parallel [(set (match_operand:TI
0 "memory_operand" "=m")
624 (match_operand:TI
1 "register_operand" "r"))
625 (clobber (match_operand:DI
2 "register_operand" "=&r"))])]
629 ;; Floating Point Moves
631 ;; Note - Patterns for SF mode moves are compulsory, but
632 ;; patterns for DF are optional, as GCC can synthesize them.
634 (define_expand "movsf"
635 [(set (match_operand:SF
0 "general_operand" "")
636 (match_operand:SF
1 "general_operand" ""))]
639 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
645 (define_insn "*movsf_internal"
646 [(set (match_operand:SF
0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
647 (match_operand:SF
1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
648 "ia64_move_ok (operands[
0], operands[
1])"
658 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
660 (define_expand "movdf"
661 [(set (match_operand:DF
0 "general_operand" "")
662 (match_operand:DF
1 "general_operand" ""))]
665 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
671 (define_insn "*movdf_internal"
672 [(set (match_operand:DF
0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
673 (match_operand:DF
1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))]
674 "ia64_move_ok (operands[
0], operands[
1])"
684 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
686 ;; With no offsettable memory references, we've got to have a scratch
687 ;; around to play with the second word if the variable winds up in GRs.
688 (define_expand "movxf"
689 [(set (match_operand:XF
0 "general_operand" "")
690 (match_operand:XF
1 "general_operand" ""))]
693 /* We must support XFmode loads into general registers for stdarg/vararg
694 and unprototyped calls. We split them into DImode loads for convenience.
695 We don't need XFmode stores from general regs, because a stdarg/vararg
696 routine does a block store to memory of unnamed arguments. */
697 if (GET_CODE (operands[
0]) == REG
698 && GR_REGNO_P (REGNO (operands[
0])))
700 /* We're hoping to transform everything that deals with XFmode
701 quantities and GR registers early in the compiler. */
705 /* Struct to register can just use TImode instead. */
706 if ((GET_CODE (operands[
1]) == SUBREG
707 && GET_MODE (SUBREG_REG (operands[
1])) == TImode)
708 || (GET_CODE (operands[
1]) == REG
709 && GR_REGNO_P (REGNO (operands[
1]))))
711 emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[
0])),
712 SUBREG_REG (operands[
1]));
716 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
718 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[
0])),
719 operand_subword (operands[
1],
0,
0, XFmode));
720 emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[
0]) +
1),
721 operand_subword (operands[
1],
1,
0, XFmode));
725 /* If the quantity is in a register not known to be GR, spill it. */
726 if (register_operand (operands[
1], XFmode))
727 operands[
1] = spill_xfmode_operand (operands[
1],
1);
729 if (GET_CODE (operands[
1]) == MEM)
733 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[
0]));
734 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[
0])+
1);
736 emit_move_insn (out[
0], adjust_address (operands[
1], DImode,
0));
737 emit_move_insn (out[
1], adjust_address (operands[
1], DImode,
8));
744 if (! reload_in_progress && ! reload_completed)
746 operands[
0] = spill_xfmode_operand (operands[
0],
0);
747 operands[
1] = spill_xfmode_operand (operands[
1],
0);
749 if (! ia64_move_ok (operands[
0], operands[
1]))
750 operands[
1] = force_reg (XFmode, operands[
1]);
754 ;; ??? There's no easy way to mind volatile acquire/release semantics.
756 (define_insn "*movxf_internal"
757 [(set (match_operand:XF
0 "destination_xfmode_operand" "=f,f, m")
758 (match_operand:XF
1 "general_xfmode_operand" "fG,m,fG"))]
759 "ia64_move_ok (operands[
0], operands[
1])"
764 [(set_attr "itanium_class" "fmisc,fld,stf")])
766 ;; Better code generation via insns that deal with TFmode register pairs
768 ;; With no offsettable memory references, we've got to have a scratch
769 ;; around to play with the second word.
770 (define_expand "movtf"
771 [(parallel [(set (match_operand:TF
0 "general_operand" "")
772 (match_operand:TF
1 "general_operand" ""))
773 (clobber (match_scratch:DI
2 ""))])]
776 rtx op1 = ia64_expand_move (operands[
0], operands[
1]);
782 (define_insn_and_split "*movtf_internal"
783 [(set (match_operand:TF
0 "nonimmediate_operand" "=r,r,m")
784 (match_operand:TF
1 "general_operand" "ri,m,r"))
785 (clobber (match_scratch:DI
2 "=X,&r,&r"))]
786 "ia64_move_ok (operands[
0], operands[
1])"
791 ia64_split_tmode_move (operands);
794 [(set_attr "itanium_class" "unknown")
795 (set_attr "predicable" "no")])
797 (define_expand "reload_intf"
798 [(parallel [(set (match_operand:TF
0 "register_operand" "=r")
799 (match_operand:TF
1 "memory_operand" "m"))
800 (clobber (match_operand:DI
2 "register_operand" "=&r"))])]
804 (define_expand "reload_outtf"
805 [(parallel [(set (match_operand:TF
0 "memory_operand" "=m")
806 (match_operand:TF
1 "register_operand" "r"))
807 (clobber (match_operand:DI
2 "register_operand" "=&r"))])]
811 ;; ::::::::::::::::::::
815 ;; ::::::::::::::::::::
817 ;; Signed conversions from a smaller integer to a larger integer
819 (define_insn "extendqidi2"
820 [(set (match_operand:DI
0 "gr_register_operand" "=r")
821 (sign_extend:DI (match_operand:QI
1 "gr_register_operand" "r")))]
824 [(set_attr "itanium_class" "xtd")])
826 (define_insn "extendhidi2"
827 [(set (match_operand:DI
0 "gr_register_operand" "=r")
828 (sign_extend:DI (match_operand:HI
1 "gr_register_operand" "r")))]
831 [(set_attr "itanium_class" "xtd")])
833 (define_insn "extendsidi2"
834 [(set (match_operand:DI
0 "grfr_register_operand" "=r,?f")
835 (sign_extend:DI (match_operand:SI
1 "grfr_register_operand" "r,f")))]
840 [(set_attr "itanium_class" "xtd,fmisc")])
842 ;; Unsigned conversions from a smaller integer to a larger integer
844 (define_insn "zero_extendqidi2"
845 [(set (match_operand:DI
0 "gr_register_operand" "=r,r")
846 (zero_extend:DI (match_operand:QI
1 "gr_nonimmediate_operand" "r,m")))]
851 [(set_attr "itanium_class" "xtd,ld")])
853 (define_insn "zero_extendhidi2"
854 [(set (match_operand:DI
0 "gr_register_operand" "=r,r")
855 (zero_extend:DI (match_operand:HI
1 "gr_nonimmediate_operand" "r,m")))]
860 [(set_attr "itanium_class" "xtd,ld")])
862 (define_insn "zero_extendsidi2"
863 [(set (match_operand:DI
0 "grfr_register_operand" "=r,r,?f")
865 (match_operand:SI
1 "grfr_nonimmediate_operand" "r,m,f")))]
871 [(set_attr "itanium_class" "xtd,ld,fmisc")])
873 ;; Convert between floating point types of different sizes.
875 ;; At first glance, it would appear that emitting fnorm for an extending
876 ;; conversion is unnecessary. However, the stf and getf instructions work
877 ;; correctly only if the input is properly rounded for its type. In
878 ;; particular, we get the wrong result for getf.d/stfd if the input is a
879 ;; denorm single. Since we don't know what the next instruction will be, we
880 ;; have to emit an fnorm.
882 ;; ??? Optimization opportunity here. Get rid of the insn altogether
883 ;; when we can. Should probably use a scheme like has been proposed
884 ;; for ia32 in dealing with operands that match unary operators. This
885 ;; would let combine merge the thing into adjacent insns. See also how the
886 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
887 ;; se_register_operand.
889 (define_insn "extendsfdf2"
890 [(set (match_operand:DF
0 "fr_register_operand" "=f")
891 (float_extend:DF (match_operand:SF
1 "fr_register_operand" "f")))]
894 [(set_attr "itanium_class" "fmac")])
896 (define_insn "extendsfxf2"
897 [(set (match_operand:XF
0 "fr_register_operand" "=f")
898 (float_extend:XF (match_operand:SF
1 "fr_register_operand" "f")))]
901 [(set_attr "itanium_class" "fmac")])
903 (define_insn "extenddfxf2"
904 [(set (match_operand:XF
0 "fr_register_operand" "=f")
905 (float_extend:XF (match_operand:DF
1 "fr_register_operand" "f")))]
908 [(set_attr "itanium_class" "fmac")])
910 (define_insn "truncdfsf2"
911 [(set (match_operand:SF
0 "fr_register_operand" "=f")
912 (float_truncate:SF (match_operand:DF
1 "fr_register_operand" "f")))]
915 [(set_attr "itanium_class" "fmac")])
917 (define_insn "truncxfsf2"
918 [(set (match_operand:SF
0 "fr_register_operand" "=f")
919 (float_truncate:SF (match_operand:XF
1 "fr_register_operand" "f")))]
922 [(set_attr "itanium_class" "fmac")])
924 (define_insn "truncxfdf2"
925 [(set (match_operand:DF
0 "fr_register_operand" "=f")
926 (float_truncate:DF (match_operand:XF
1 "fr_register_operand" "f")))]
929 [(set_attr "itanium_class" "fmac")])
931 ;; Convert between signed integer types and floating point.
933 (define_insn "floatdixf2"
934 [(set (match_operand:XF
0 "fr_register_operand" "=f")
935 (float:XF (match_operand:DI
1 "fr_register_operand" "f")))]
938 [(set_attr "itanium_class" "fcvtfx")])
940 (define_insn "fix_truncsfdi2"
941 [(set (match_operand:DI
0 "fr_register_operand" "=f")
942 (fix:DI (match_operand:SF
1 "fr_register_operand" "f")))]
944 "fcvt.fx.trunc %
0 = %
1"
945 [(set_attr "itanium_class" "fcvtfx")])
947 (define_insn "fix_truncdfdi2"
948 [(set (match_operand:DI
0 "fr_register_operand" "=f")
949 (fix:DI (match_operand:DF
1 "fr_register_operand" "f")))]
951 "fcvt.fx.trunc %
0 = %
1"
952 [(set_attr "itanium_class" "fcvtfx")])
954 (define_insn "fix_truncxfdi2"
955 [(set (match_operand:DI
0 "fr_register_operand" "=f")
956 (fix:DI (match_operand:XF
1 "fr_register_operand" "f")))]
958 "fcvt.fx.trunc %
0 = %
1"
959 [(set_attr "itanium_class" "fcvtfx")])
961 (define_insn "fix_truncxfdi2_alts"
962 [(set (match_operand:DI
0 "fr_register_operand" "=f")
963 (fix:DI (match_operand:XF
1 "fr_register_operand" "f")))
964 (use (match_operand:SI
2 "const_int_operand" ""))]
966 "fcvt.fx.trunc.s%
2 %
0 = %
1"
967 [(set_attr "itanium_class" "fcvtfx")])
969 ;; Convert between unsigned integer types and floating point.
971 (define_insn "floatunsdisf2"
972 [(set (match_operand:SF
0 "fr_register_operand" "=f")
973 (unsigned_float:SF (match_operand:DI
1 "fr_register_operand" "f")))]
976 [(set_attr "itanium_class" "fcvtfx")])
978 (define_insn "floatunsdidf2"
979 [(set (match_operand:DF
0 "fr_register_operand" "=f")
980 (unsigned_float:DF (match_operand:DI
1 "fr_register_operand" "f")))]
983 [(set_attr "itanium_class" "fcvtfx")])
985 (define_insn "floatunsdixf2"
986 [(set (match_operand:XF
0 "fr_register_operand" "=f")
987 (unsigned_float:XF (match_operand:DI
1 "fr_register_operand" "f")))]
990 [(set_attr "itanium_class" "fcvtfx")])
992 (define_insn "fixuns_truncsfdi2"
993 [(set (match_operand:DI
0 "fr_register_operand" "=f")
994 (unsigned_fix:DI (match_operand:SF
1 "fr_register_operand" "f")))]
996 "fcvt.fxu.trunc %
0 = %
1"
997 [(set_attr "itanium_class" "fcvtfx")])
999 (define_insn "fixuns_truncdfdi2"
1000 [(set (match_operand:DI
0 "fr_register_operand" "=f")
1001 (unsigned_fix:DI (match_operand:DF
1 "fr_register_operand" "f")))]
1003 "fcvt.fxu.trunc %
0 = %
1"
1004 [(set_attr "itanium_class" "fcvtfx")])
1006 (define_insn "fixuns_truncxfdi2"
1007 [(set (match_operand:DI
0 "fr_register_operand" "=f")
1008 (unsigned_fix:DI (match_operand:XF
1 "fr_register_operand" "f")))]
1010 "fcvt.fxu.trunc %
0 = %
1"
1011 [(set_attr "itanium_class" "fcvtfx")])
1013 (define_insn "fixuns_truncxfdi2_alts"
1014 [(set (match_operand:DI
0 "fr_register_operand" "=f")
1015 (unsigned_fix:DI (match_operand:XF
1 "fr_register_operand" "f")))
1016 (use (match_operand:SI
2 "const_int_operand" ""))]
1018 "fcvt.fxu.trunc.s%
2 %
0 = %
1"
1019 [(set_attr "itanium_class" "fcvtfx")])
1021 ;; ::::::::::::::::::::
1023 ;; :: Bit field extraction
1025 ;; ::::::::::::::::::::
1028 [(set (match_operand:DI
0 "gr_register_operand" "=r")
1029 (sign_extract:DI (match_operand:DI
1 "gr_register_operand" "r")
1030 (match_operand:DI
2 "const_int_operand" "n")
1031 (match_operand:DI
3 "const_int_operand" "n")))]
1033 "extr %
0 = %
1, %
3, %
2"
1034 [(set_attr "itanium_class" "ishf")])
1036 (define_insn "extzv"
1037 [(set (match_operand:DI
0 "gr_register_operand" "=r")
1038 (zero_extract:DI (match_operand:DI
1 "gr_register_operand" "r")
1039 (match_operand:DI
2 "const_int_operand" "n")
1040 (match_operand:DI
3 "const_int_operand" "n")))]
1042 "extr.u %
0 = %
1, %
3, %
2"
1043 [(set_attr "itanium_class" "ishf")])
1045 ;; Insert a bit field.
1046 ;; Can have
3 operands, source1 (inserter), source2 (insertee), dest.
1047 ;; Source1 can be
0 or -
1.
1048 ;; Source2 can be
0.
1050 ;; ??? Actual dep instruction is more powerful than what these insv
1051 ;; patterns support. Unfortunately, combine is unable to create patterns
1052 ;; where source2 != dest.
1054 (define_expand "insv"
1055 [(set (zero_extract:DI (match_operand:DI
0 "gr_register_operand" "")
1056 (match_operand:DI
1 "const_int_operand" "")
1057 (match_operand:DI
2 "const_int_operand" ""))
1058 (match_operand:DI
3 "nonmemory_operand" ""))]
1061 int width = INTVAL (operands[
1]);
1062 int shift = INTVAL (operands[
2]);
1064 /* If operand[
3] is a constant, and isn't
0 or -
1, then load it into a
1066 if (! register_operand (operands[
3], DImode)
1067 && operands[
3] != const0_rtx && operands[
3] != constm1_rtx)
1068 operands[
3] = force_reg (DImode, operands[
3]);
1070 /* If this is a single dep instruction, we have nothing to do. */
1071 if (! ((register_operand (operands[
3], DImode) && width <=
16)
1072 || operands[
3] == const0_rtx || operands[
3] == constm1_rtx))
1074 /* Check for cases that can be implemented with a mix instruction. */
1075 if (width ==
32 && shift ==
0)
1077 /* Directly generating the mix4left instruction confuses
1078 optimize_bit_field in function.c. Since this is performing
1079 a useful optimization, we defer generation of the complicated
1080 mix4left RTL to the first splitting phase. */
1081 rtx tmp = gen_reg_rtx (DImode);
1082 emit_insn (gen_shift_mix4left (operands[
0], operands[
3], tmp));
1085 else if (width ==
32 && shift ==
32)
1087 emit_insn (gen_mix4right (operands[
0], operands[
3]));
1091 /* We could handle remaining cases by emitting multiple dep
1094 If we need more than two dep instructions then we lose. A
6
1095 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1096 mov;;dep,shr;;dep,shr;;dep. The former can be executed in
3 cycles,
1097 the latter is
6 cycles on an Itanium (TM) processor, because there is
1098 only one function unit that can execute dep and shr immed.
1100 If we only need two dep instruction, then we still lose.
1101 mov;;dep,shr;;dep is still
4 cycles. Even if we optimize away
1102 the unnecessary mov, this is still undesirable because it will be
1103 hard to optimize, and it creates unnecessary pressure on the I0
1109 /* This code may be useful for other IA-
64 processors, so we leave it in
1115 emit_insn (gen_insv (operands[
0], GEN_INT (
16), GEN_INT (shift),
1119 tmp = gen_reg_rtx (DImode);
1120 emit_insn (gen_lshrdi3 (tmp, operands[
3], GEN_INT (
16)));
1123 operands[
1] = GEN_INT (width);
1124 operands[
2] = GEN_INT (shift);
1129 (define_insn "*insv_internal"
1130 [(set (zero_extract:DI (match_operand:DI
0 "gr_register_operand" "+r")
1131 (match_operand:DI
1 "const_int_operand" "n")
1132 (match_operand:DI
2 "const_int_operand" "n"))
1133 (match_operand:DI
3 "nonmemory_operand" "rP"))]
1134 "(gr_register_operand (operands[
3], DImode) && INTVAL (operands[
1]) <=
16)
1135 || operands[
3] == const0_rtx || operands[
3] == constm1_rtx"
1136 "dep %
0 = %
3, %
0, %
2, %
1"
1137 [(set_attr "itanium_class" "ishf")])
1139 ;; Combine doesn't like to create bit-field insertions into zero.
1140 (define_insn "*depz_internal"
1141 [(set (match_operand:DI
0 "gr_register_operand" "=r")
1142 (and:DI (ashift:DI (match_operand:DI
1 "gr_register_operand" "r")
1143 (match_operand:DI
2 "const_int_operand" "n"))
1144 (match_operand:DI
3 "const_int_operand" "n")))]
1145 "CONST_OK_FOR_M (INTVAL (operands[
2]))
1146 && ia64_depz_field_mask (operands[
3], operands[
2]) >
0"
1148 operands[
3] = GEN_INT (ia64_depz_field_mask (operands[
3], operands[
2]));
1149 return "%,dep.z %
0 = %
1, %
2, %
3";
1151 [(set_attr "itanium_class" "ishf")])
1153 (define_insn "shift_mix4left"
1154 [(set (zero_extract:DI (match_operand:DI
0 "gr_register_operand" "+r")
1155 (const_int
32) (const_int
0))
1156 (match_operand:DI
1 "gr_register_operand" "r"))
1157 (clobber (match_operand:DI
2 "gr_register_operand" "=r"))]
1160 [(set_attr "itanium_class" "unknown")])
1163 [(set (zero_extract:DI (match_operand:DI
0 "register_operand" "")
1164 (const_int
32) (const_int
0))
1165 (match_operand:DI
1 "register_operand" ""))
1166 (clobber (match_operand:DI
2 "register_operand" ""))]
1168 [(set (match_dup
3) (ashift:DI (match_dup
1) (const_int
32)))
1169 (set (zero_extract:DI (match_dup
0) (const_int
32) (const_int
0))
1170 (lshiftrt:DI (match_dup
3) (const_int
32)))]
1171 "operands[
3] = operands[
2];")
1174 [(set (zero_extract:DI (match_operand:DI
0 "register_operand" "")
1175 (const_int
32) (const_int
0))
1176 (match_operand:DI
1 "register_operand" ""))
1177 (clobber (match_operand:DI
2 "register_operand" ""))]
1178 "! reload_completed"
1179 [(set (match_dup
3) (ashift:DI (match_dup
1) (const_int
32)))
1180 (set (zero_extract:DI (match_dup
0) (const_int
32) (const_int
0))
1181 (lshiftrt:DI (match_dup
3) (const_int
32)))]
1182 "operands[
3] = operands[
2];")
1184 (define_insn "*mix4left"
1185 [(set (zero_extract:DI (match_operand:DI
0 "gr_register_operand" "+r")
1186 (const_int
32) (const_int
0))
1187 (lshiftrt:DI (match_operand:DI
1 "gr_register_operand" "r")
1190 "mix4.l %
0 = %
0, %r1"
1191 [(set_attr "itanium_class" "mmshf")])
1193 (define_insn "mix4right"
1194 [(set (zero_extract:DI (match_operand:DI
0 "gr_register_operand" "+r")
1195 (const_int
32) (const_int
32))
1196 (match_operand:DI
1 "gr_reg_or_0_operand" "rO"))]
1198 "mix4.r %
0 = %r1, %
0"
1199 [(set_attr "itanium_class" "mmshf")])
1201 ;; This is used by the rotrsi3 pattern.
1203 (define_insn "*mix4right_3op"
1204 [(set (match_operand:DI
0 "gr_register_operand" "=r")
1205 (ior:DI (zero_extend:DI (match_operand:SI
1 "gr_register_operand" "r"))
1206 (ashift:DI (zero_extend:DI
1207 (match_operand:SI
2 "gr_register_operand" "r"))
1210 "mix4.r %
0 = %
2, %
1"
1211 [(set_attr "itanium_class" "mmshf")])
1214 ;; ::::::::::::::::::::
1216 ;; ::
1 bit Integer arithmetic
1218 ;; ::::::::::::::::::::
1220 (define_insn_and_split "andbi3"
1221 [(set (match_operand:BI
0 "register_operand" "=c,c,r")
1222 (and:BI (match_operand:BI
1 "register_operand" "%
0,
0,r")
1223 (match_operand:BI
2 "register_operand" "c,r,r")))]
1227 tbit.nz.and.orcm %
0, %I0 = %
2,
0
1230 && GET_CODE (operands[
0]) == REG && PR_REGNO_P (REGNO (operands[
0]))
1231 && GET_CODE (operands[
2]) == REG && PR_REGNO_P (REGNO (operands[
2]))"
1232 [(cond_exec (eq (match_dup
2) (const_int
0))
1233 (set (match_dup
0) (and:BI (ne:BI (const_int
0) (const_int
0))
1236 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1238 (define_insn_and_split "*andcmbi3"
1239 [(set (match_operand:BI
0 "register_operand" "=c,c,r")
1240 (and:BI (not:BI (match_operand:BI
1 "register_operand" "c,r,r"))
1241 (match_operand:BI
2 "register_operand" "
0,
0,r")))]
1245 tbit.z.and.orcm %
0, %I0 = %
1,
0
1248 && GET_CODE (operands[
0]) == REG && PR_REGNO_P (REGNO (operands[
0]))
1249 && GET_CODE (operands[
1]) == REG && PR_REGNO_P (REGNO (operands[
1]))"
1250 [(cond_exec (ne (match_dup
1) (const_int
0))
1251 (set (match_dup
0) (and:BI (ne:BI (const_int
0) (const_int
0))
1254 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1256 (define_insn_and_split "iorbi3"
1257 [(set (match_operand:BI
0 "register_operand" "=c,c,r")
1258 (ior:BI (match_operand:BI
1 "register_operand" "%
0,
0,r")
1259 (match_operand:BI
2 "register_operand" "c,r,r")))]
1263 tbit.nz.or.andcm %
0, %I0 = %
2,
0
1266 && GET_CODE (operands[
0]) == REG && PR_REGNO_P (REGNO (operands[
0]))
1267 && GET_CODE (operands[
2]) == REG && PR_REGNO_P (REGNO (operands[
2]))"
1268 [(cond_exec (ne (match_dup
2) (const_int
0))
1269 (set (match_dup
0) (ior:BI (eq:BI (const_int
0) (const_int
0))
1272 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1274 (define_insn_and_split "*iorcmbi3"
1275 [(set (match_operand:BI
0 "register_operand" "=c,c")
1276 (ior:BI (not:BI (match_operand:BI
1 "register_operand" "c,r"))
1277 (match_operand:BI
2 "register_operand" "
0,
0")))]
1281 tbit.z.or.andcm %
0, %I0 = %
1,
0"
1283 && GET_CODE (operands[
0]) == REG && PR_REGNO_P (REGNO (operands[
0]))
1284 && GET_CODE (operands[
1]) == REG && PR_REGNO_P (REGNO (operands[
1]))"
1285 [(cond_exec (eq (match_dup
1) (const_int
0))
1286 (set (match_dup
0) (ior:BI (eq:BI (const_int
0) (const_int
0))
1289 [(set_attr "itanium_class" "unknown,tbit")])
1291 (define_insn "one_cmplbi2"
1292 [(set (match_operand:BI
0 "register_operand" "=c,r,c,&c")
1293 (not:BI (match_operand:BI
1 "register_operand" "r,r,
0,c")))
1294 (clobber (match_scratch:BI
2 "=X,X,c,X"))]
1297 tbit.z %
0, %I0 = %
1,
0
1301 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1304 [(set (match_operand:BI
0 "register_operand" "")
1305 (not:BI (match_operand:BI
1 "register_operand" "")))
1306 (clobber (match_scratch:BI
2 ""))]
1308 && GET_CODE (operands[
0]) == REG && PR_REGNO_P (REGNO (operands[
0]))
1309 && rtx_equal_p (operands[
0], operands[
1])"
1310 [(set (match_dup
4) (match_dup
3))
1311 (set (match_dup
0) (const_int
1))
1312 (cond_exec (ne (match_dup
2) (const_int
0))
1313 (set (match_dup
0) (const_int
0)))
1314 (set (match_dup
0) (unspec:BI [(match_dup
0)] UNSPEC_PRED_REL_MUTEX))]
1315 "operands[
3] = gen_rtx_REG (CCImode, REGNO (operands[
1]));
1316 operands[
4] = gen_rtx_REG (CCImode, REGNO (operands[
2]));")
1319 [(set (match_operand:BI
0 "register_operand" "")
1320 (not:BI (match_operand:BI
1 "register_operand" "")))
1321 (clobber (match_scratch:BI
2 ""))]
1323 && GET_CODE (operands[
0]) == REG && PR_REGNO_P (REGNO (operands[
0]))
1324 && GET_CODE (operands[
1]) == REG && PR_REGNO_P (REGNO (operands[
1]))
1325 && ! rtx_equal_p (operands[
0], operands[
1])"
1326 [(cond_exec (ne (match_dup
1) (const_int
0))
1327 (set (match_dup
0) (const_int
0)))
1328 (cond_exec (eq (match_dup
1) (const_int
0))
1329 (set (match_dup
0) (const_int
1)))
1330 (set (match_dup
0) (unspec:BI [(match_dup
0)] UNSPEC_PRED_REL_MUTEX))]
1333 (define_insn "*cmpsi_and_0"
1334 [(set (match_operand:BI
0 "register_operand" "=c")
1335 (and:BI (match_operator:BI
4 "predicate_operator"
1336 [(match_operand:SI
2 "gr_reg_or_0_operand" "rO")
1337 (match_operand:SI
3 "gr_reg_or_8bit_operand" "rK")])
1338 (match_operand:BI
1 "register_operand" "
0")))]
1340 "cmp4.%C4.and.orcm %
0, %I0 = %
3, %r2"
1341 [(set_attr "itanium_class" "icmp")])
1343 (define_insn "*cmpsi_and_1"
1344 [(set (match_operand:BI
0 "register_operand" "=c")
1345 (and:BI (match_operator:BI
3 "signed_inequality_operator"
1346 [(match_operand:SI
2 "gr_register_operand" "r")
1348 (match_operand:BI
1 "register_operand" "
0")))]
1350 "cmp4.%C3.and.orcm %
0, %I0 = r0, %
2"
1351 [(set_attr "itanium_class" "icmp")])
1353 (define_insn "*cmpsi_andnot_0"
1354 [(set (match_operand:BI
0 "register_operand" "=c")
1355 (and:BI (not:BI (match_operator:BI
4 "predicate_operator"
1356 [(match_operand:SI
2 "gr_reg_or_0_operand" "rO")
1357 (match_operand:SI
3 "gr_reg_or_8bit_operand" "rK")]))
1358 (match_operand:BI
1 "register_operand" "
0")))]
1360 "cmp4.%C4.or.andcm %I0, %
0 = %
3, %r2"
1361 [(set_attr "itanium_class" "icmp")])
1363 (define_insn "*cmpsi_andnot_1"
1364 [(set (match_operand:BI
0 "register_operand" "=c")
1365 (and:BI (not:BI (match_operator:BI
3 "signed_inequality_operator"
1366 [(match_operand:SI
2 "gr_register_operand" "r")
1368 (match_operand:BI
1 "register_operand" "
0")))]
1370 "cmp4.%C3.or.andcm %I0, %
0 = r0, %
2"
1371 [(set_attr "itanium_class" "icmp")])
1373 (define_insn "*cmpdi_and_0"
1374 [(set (match_operand:BI
0 "register_operand" "=c")
1375 (and:BI (match_operator:BI
4 "predicate_operator"
1376 [(match_operand:DI
2 "gr_register_operand" "r")
1377 (match_operand:DI
3 "gr_reg_or_8bit_operand" "rK")])
1378 (match_operand:BI
1 "register_operand" "
0")))]
1380 "cmp.%C4.and.orcm %
0, %I0 = %
3, %
2"
1381 [(set_attr "itanium_class" "icmp")])
1383 (define_insn "*cmpdi_and_1"
1384 [(set (match_operand:BI
0 "register_operand" "=c")
1385 (and:BI (match_operator:BI
3 "signed_inequality_operator"
1386 [(match_operand:DI
2 "gr_register_operand" "r")
1388 (match_operand:BI
1 "register_operand" "
0")))]
1390 "cmp.%C3.and.orcm %
0, %I0 = r0, %
2"
1391 [(set_attr "itanium_class" "icmp")])
1393 (define_insn "*cmpdi_andnot_0"
1394 [(set (match_operand:BI
0 "register_operand" "=c")
1395 (and:BI (not:BI (match_operator:BI
4 "predicate_operator"
1396 [(match_operand:DI
2 "gr_register_operand" "r")
1397 (match_operand:DI
3 "gr_reg_or_8bit_operand" "rK")]))
1398 (match_operand:BI
1 "register_operand" "
0")))]
1400 "cmp.%C4.or.andcm %I0, %
0 = %
3, %
2"
1401 [(set_attr "itanium_class" "icmp")])
1403 (define_insn "*cmpdi_andnot_1"
1404 [(set (match_operand:BI
0 "register_operand" "=c")
1405 (and:BI (not:BI (match_operator:BI
3 "signed_inequality_operator"
1406 [(match_operand:DI
2 "gr_register_operand" "r")
1408 (match_operand:BI
1 "register_operand" "
0")))]
1410 "cmp.%C3.or.andcm %I0, %
0 = r0, %
2"
1411 [(set_attr "itanium_class" "icmp")])
1413 (define_insn "*tbit_and_0"
1414 [(set (match_operand:BI
0 "register_operand" "=c")
1415 (and:BI (ne:BI (and:DI (match_operand:DI
1 "gr_register_operand" "r")
1418 (match_operand:BI
2 "register_operand" "
0")))]
1420 "tbit.nz.and.orcm %
0, %I0 = %
1,
0"
1421 [(set_attr "itanium_class" "tbit")])
1423 (define_insn "*tbit_and_1"
1424 [(set (match_operand:BI
0 "register_operand" "=c")
1425 (and:BI (eq:BI (and:DI (match_operand:DI
1 "gr_register_operand" "r")
1428 (match_operand:BI
2 "register_operand" "
0")))]
1430 "tbit.z.and.orcm %
0, %I0 = %
1,
0"
1431 [(set_attr "itanium_class" "tbit")])
1433 (define_insn "*tbit_and_2"
1434 [(set (match_operand:BI
0 "register_operand" "=c")
1435 (and:BI (ne:BI (zero_extract:DI
1436 (match_operand:DI
1 "gr_register_operand" "r")
1438 (match_operand:DI
2 "const_int_operand" "n"))
1440 (match_operand:BI
3 "register_operand" "
0")))]
1442 "tbit.nz.and.orcm %
0, %I0 = %
1, %
2"
1443 [(set_attr "itanium_class" "tbit")])
1445 (define_insn "*tbit_and_3"
1446 [(set (match_operand:BI
0 "register_operand" "=c")
1447 (and:BI (eq:BI (zero_extract:DI
1448 (match_operand:DI
1 "gr_register_operand" "r")
1450 (match_operand:DI
2 "const_int_operand" "n"))
1452 (match_operand:BI
3 "register_operand" "
0")))]
1454 "tbit.z.and.orcm %
0, %I0 = %
1, %
2"
1455 [(set_attr "itanium_class" "tbit")])
1457 (define_insn "*cmpsi_or_0"
1458 [(set (match_operand:BI
0 "register_operand" "=c")
1459 (ior:BI (match_operator:BI
4 "predicate_operator"
1460 [(match_operand:SI
2 "gr_reg_or_0_operand" "rO")
1461 (match_operand:SI
3 "gr_reg_or_8bit_operand" "rK")])
1462 (match_operand:BI
1 "register_operand" "
0")))]
1464 "cmp4.%C4.or.andcm %
0, %I0 = %
3, %r2"
1465 [(set_attr "itanium_class" "icmp")])
1467 (define_insn "*cmpsi_or_1"
1468 [(set (match_operand:BI
0 "register_operand" "=c")
1469 (ior:BI (match_operator:BI
3 "signed_inequality_operator"
1470 [(match_operand:SI
2 "gr_register_operand" "r")
1472 (match_operand:BI
1 "register_operand" "
0")))]
1474 "cmp4.%C3.or.andcm %
0, %I0 = r0, %
2"
1475 [(set_attr "itanium_class" "icmp")])
1477 (define_insn "*cmpsi_orcm_0"
1478 [(set (match_operand:BI
0 "register_operand" "=c")
1479 (ior:BI (not:BI (match_operator:BI
4 "predicate_operator"
1480 [(match_operand:SI
2 "gr_reg_or_0_operand" "rO")
1481 (match_operand:SI
3 "gr_reg_or_8bit_operand" "rK")]))
1482 (match_operand:BI
1 "register_operand" "
0")))]
1484 "cmp4.%C4.and.orcm %I0, %
0 = %
3, %r2"
1485 [(set_attr "itanium_class" "icmp")])
1487 (define_insn "*cmpsi_orcm_1"
1488 [(set (match_operand:BI
0 "register_operand" "=c")
1489 (ior:BI (not:BI (match_operator:BI
3 "signed_inequality_operator"
1490 [(match_operand:SI
2 "gr_register_operand" "r")
1492 (match_operand:BI
1 "register_operand" "
0")))]
1494 "cmp4.%C3.and.orcm %I0, %
0 = r0, %
2"
1495 [(set_attr "itanium_class" "icmp")])
1497 (define_insn "*cmpdi_or_0"
1498 [(set (match_operand:BI
0 "register_operand" "=c")
1499 (ior:BI (match_operator:BI
4 "predicate_operator"
1500 [(match_operand:DI
2 "gr_register_operand" "r")
1501 (match_operand:DI
3 "gr_reg_or_8bit_operand" "rK")])
1502 (match_operand:BI
1 "register_operand" "
0")))]
1504 "cmp.%C4.or.andcm %
0, %I0 = %
3, %
2"
1505 [(set_attr "itanium_class" "icmp")])
1507 (define_insn "*cmpdi_or_1"
1508 [(set (match_operand:BI
0 "register_operand" "=c")
1509 (ior:BI (match_operator:BI
3 "signed_inequality_operator"
1510 [(match_operand:DI
2 "gr_register_operand" "r")
1512 (match_operand:BI
1 "register_operand" "
0")))]
1514 "cmp.%C3.or.andcm %
0, %I0 = r0, %
2"
1515 [(set_attr "itanium_class" "icmp")])
1517 (define_insn "*cmpdi_orcm_0"
1518 [(set (match_operand:BI
0 "register_operand" "=c")
1519 (ior:BI (not:BI (match_operator:BI
4 "predicate_operator"
1520 [(match_operand:DI
2 "gr_register_operand" "r")
1521 (match_operand:DI
3 "gr_reg_or_8bit_operand" "rK")]))
1522 (match_operand:BI
1 "register_operand" "
0")))]
1524 "cmp.%C4.and.orcm %I0, %
0 = %
3, %
2"
1525 [(set_attr "itanium_class" "icmp")])
1527 (define_insn "*cmpdi_orcm_1"
1528 [(set (match_operand:BI
0 "register_operand" "=c")
1529 (ior:BI (not:BI (match_operator:BI
3 "signed_inequality_operator"
1530 [(match_operand:DI
2 "gr_register_operand" "r")
1532 (match_operand:BI
1 "register_operand" "
0")))]
1534 "cmp.%C3.and.orcm %I0, %
0 = r0, %
2"
1535 [(set_attr "itanium_class" "icmp")])
1537 (define_insn "*tbit_or_0"
1538 [(set (match_operand:BI
0 "register_operand" "=c")
1539 (ior:BI (ne:BI (and:DI (match_operand:DI
1 "gr_register_operand" "r")
1542 (match_operand:BI
2 "register_operand" "
0")))]
1544 "tbit.nz.or.andcm %
0, %I0 = %
1,
0"
1545 [(set_attr "itanium_class" "tbit")])
1547 (define_insn "*tbit_or_1"
1548 [(set (match_operand:BI
0 "register_operand" "=c")
1549 (ior:BI (eq:BI (and:DI (match_operand:DI
1 "gr_register_operand" "r")
1552 (match_operand:BI
2 "register_operand" "
0")))]
1554 "tbit.z.or.andcm %
0, %I0 = %
1,
0"
1555 [(set_attr "itanium_class" "tbit")])
1557 (define_insn "*tbit_or_2"
1558 [(set (match_operand:BI
0 "register_operand" "=c")
1559 (ior:BI (ne:BI (zero_extract:DI
1560 (match_operand:DI
1 "gr_register_operand" "r")
1562 (match_operand:DI
2 "const_int_operand" "n"))
1564 (match_operand:BI
3 "register_operand" "
0")))]
1566 "tbit.nz.or.andcm %
0, %I0 = %
1, %
2"
1567 [(set_attr "itanium_class" "tbit")])
1569 (define_insn "*tbit_or_3"
1570 [(set (match_operand:BI
0 "register_operand" "=c")
1571 (ior:BI (eq:BI (zero_extract:DI
1572 (match_operand:DI
1 "gr_register_operand" "r")
1574 (match_operand:DI
2 "const_int_operand" "n"))
1576 (match_operand:BI
3 "register_operand" "
0")))]
1578 "tbit.z.or.andcm %
0, %I0 = %
1, %
2"
1579 [(set_attr "itanium_class" "tbit")])
1581 ;; Transform test of and/or of setcc into parallel comparisons.
1584 [(set (match_operand:BI
0 "register_operand" "")
1585 (ne:BI (and:DI (ne:DI (match_operand:BI
2 "register_operand" "")
1587 (match_operand:DI
3 "register_operand" ""))
1591 (and:BI (ne:BI (and:DI (match_dup
3) (const_int
1)) (const_int
0))
1596 [(set (match_operand:BI
0 "register_operand" "")
1597 (eq:BI (and:DI (ne:DI (match_operand:BI
2 "register_operand" "")
1599 (match_operand:DI
3 "register_operand" ""))
1603 (and:BI (ne:BI (and:DI (match_dup
3) (const_int
1)) (const_int
0))
1605 (parallel [(set (match_dup
0) (not:BI (match_dup
0)))
1606 (clobber (scratch))])]
1610 [(set (match_operand:BI
0 "register_operand" "")
1611 (ne:BI (ior:DI (ne:DI (match_operand:BI
2 "register_operand" "")
1613 (match_operand:DI
3 "register_operand" ""))
1617 (ior:BI (ne:BI (match_dup
3) (const_int
0))
1622 [(set (match_operand:BI
0 "register_operand" "")
1623 (eq:BI (ior:DI (ne:DI (match_operand:BI
2 "register_operand" "")
1625 (match_operand:DI
3 "register_operand" ""))
1629 (ior:BI (ne:BI (match_dup
3) (const_int
0))
1631 (parallel [(set (match_dup
0) (not:BI (match_dup
0)))
1632 (clobber (scratch))])]
1635 ;; ??? Incredibly hackish. Either need four proper patterns with all
1636 ;; the alternatives, or rely on sched1 to split the insn and hope that
1637 ;; nothing bad happens to the comparisons in the meantime.
1639 ;; Alternately, adjust combine to allow
2->
2 and
3->
3 splits, assuming
1640 ;; that we're doing height reduction.
1642 ;(define_insn_and_split ""
1643 ; [(set (match_operand:BI
0 "register_operand" "=c")
1644 ; (and:BI (and:BI (match_operator:BI
1 "comparison_operator"
1645 ; [(match_operand
2 "" "")
1646 ; (match_operand
3 "" "")])
1647 ; (match_operator:BI
4 "comparison_operator"
1648 ; [(match_operand
5 "" "")
1649 ; (match_operand
6 "" "")]))
1651 ; "flag_schedule_insns"
1654 ; [(set (match_dup
0) (and:BI (match_dup
1) (match_dup
0)))
1655 ; (set (match_dup
0) (and:BI (match_dup
4) (match_dup
0)))]
1658 ;(define_insn_and_split ""
1659 ; [(set (match_operand:BI
0 "register_operand" "=c")
1660 ; (ior:BI (ior:BI (match_operator:BI
1 "comparison_operator"
1661 ; [(match_operand
2 "" "")
1662 ; (match_operand
3 "" "")])
1663 ; (match_operator:BI
4 "comparison_operator"
1664 ; [(match_operand
5 "" "")
1665 ; (match_operand
6 "" "")]))
1667 ; "flag_schedule_insns"
1670 ; [(set (match_dup
0) (ior:BI (match_dup
1) (match_dup
0)))
1671 ; (set (match_dup
0) (ior:BI (match_dup
4) (match_dup
0)))]
1675 ; [(set (match_operand:BI
0 "register_operand" "")
1676 ; (and:BI (and:BI (match_operator:BI
1 "comparison_operator"
1677 ; [(match_operand
2 "" "")
1678 ; (match_operand
3 "" "")])
1679 ; (match_operand:BI
7 "register_operand" ""))
1680 ; (and:BI (match_operator:BI
4 "comparison_operator"
1681 ; [(match_operand
5 "" "")
1682 ; (match_operand
6 "" "")])
1683 ; (match_operand:BI
8 "register_operand" ""))))]
1685 ; [(set (match_dup
0) (and:BI (match_dup
7) (match_dup
8)))
1686 ; (set (match_dup
0) (and:BI (and:BI (match_dup
1) (match_dup
4))
1691 ; [(set (match_operand:BI
0 "register_operand" "")
1692 ; (ior:BI (ior:BI (match_operator:BI
1 "comparison_operator"
1693 ; [(match_operand
2 "" "")
1694 ; (match_operand
3 "" "")])
1695 ; (match_operand:BI
7 "register_operand" ""))
1696 ; (ior:BI (match_operator:BI
4 "comparison_operator"
1697 ; [(match_operand
5 "" "")
1698 ; (match_operand
6 "" "")])
1699 ; (match_operand:BI
8 "register_operand" ""))))]
1701 ; [(set (match_dup
0) (ior:BI (match_dup
7) (match_dup
8)))
1702 ; (set (match_dup
0) (ior:BI (ior:BI (match_dup
1) (match_dup
4))
1706 ;; Try harder to avoid predicate copies by duplicating compares.
1707 ;; Note that we'll have already split the predicate copy, which
1708 ;; is kind of a pain, but oh well.
1711 [(set (match_operand:BI
0 "register_operand" "")
1712 (match_operand:BI
1 "comparison_operator" ""))
1713 (set (match_operand:CCI
2 "register_operand" "")
1714 (match_operand:CCI
3 "register_operand" ""))
1715 (set (match_operand:CCI
4 "register_operand" "")
1716 (match_operand:CCI
5 "register_operand" ""))
1717 (set (match_operand:BI
6 "register_operand" "")
1718 (unspec:BI [(match_dup
6)] UNSPEC_PRED_REL_MUTEX))]
1719 "REGNO (operands[
3]) == REGNO (operands[
0])
1720 && REGNO (operands[
4]) == REGNO (operands[
0]) +
1
1721 && REGNO (operands[
4]) == REGNO (operands[
2]) +
1
1722 && REGNO (operands[
6]) == REGNO (operands[
2])"
1723 [(set (match_dup
0) (match_dup
1))
1724 (set (match_dup
6) (match_dup
7))]
1725 "operands[
7] = copy_rtx (operands[
1]);")
1727 ;; ::::::::::::::::::::
1729 ;; ::
16 bit Integer arithmetic
1731 ;; ::::::::::::::::::::
1733 (define_insn "mulhi3"
1734 [(set (match_operand:HI
0 "gr_register_operand" "=r")
1735 (mult:HI (match_operand:HI
1 "gr_register_operand" "r")
1736 (match_operand:HI
2 "gr_register_operand" "r")))]
1738 "pmpy2.r %
0 = %
1, %
2"
1739 [(set_attr "itanium_class" "mmmul")])
1742 ;; ::::::::::::::::::::
1744 ;; ::
32 bit Integer arithmetic
1746 ;; ::::::::::::::::::::
1748 (define_insn "addsi3"
1749 [(set (match_operand:SI
0 "gr_register_operand" "=r,r,r")
1750 (plus:SI (match_operand:SI
1 "gr_register_operand" "%r,r,a")
1751 (match_operand:SI
2 "gr_reg_or_22bit_operand" "r,I,J")))]
1757 [(set_attr "itanium_class" "ialu")])
1759 (define_insn "*addsi3_plus1"
1760 [(set (match_operand:SI
0 "gr_register_operand" "=r")
1761 (plus:SI (plus:SI (match_operand:SI
1 "gr_register_operand" "r")
1762 (match_operand:SI
2 "gr_register_operand" "r"))
1765 "add %
0 = %
1, %
2,
1"
1766 [(set_attr "itanium_class" "ialu")])
1768 (define_insn "*addsi3_plus1_alt"
1769 [(set (match_operand:SI
0 "gr_register_operand" "=r")
1770 (plus:SI (mult:SI (match_operand:SI
1 "gr_register_operand" "r")
1774 "add %
0 = %
1, %
1,
1"
1775 [(set_attr "itanium_class" "ialu")])
1777 (define_insn "*addsi3_shladd"
1778 [(set (match_operand:SI
0 "gr_register_operand" "=r")
1779 (plus:SI (mult:SI (match_operand:SI
1 "gr_register_operand" "r")
1780 (match_operand:SI
2 "shladd_operand" "n"))
1781 (match_operand:SI
3 "gr_register_operand" "r")))]
1783 "shladd %
0 = %
1, %S2, %
3"
1784 [(set_attr "itanium_class" "ialu")])
1786 (define_insn "subsi3"
1787 [(set (match_operand:SI
0 "gr_register_operand" "=r")
1788 (minus:SI (match_operand:SI
1 "gr_reg_or_8bit_operand" "rK")
1789 (match_operand:SI
2 "gr_register_operand" "r")))]
1792 [(set_attr "itanium_class" "ialu")])
1794 (define_insn "*subsi3_minus1"
1795 [(set (match_operand:SI
0 "gr_register_operand" "=r")
1796 (plus:SI (not:SI (match_operand:SI
1 "gr_register_operand" "r"))
1797 (match_operand:SI
2 "gr_register_operand" "r")))]
1799 "sub %
0 = %
2, %
1,
1"
1800 [(set_attr "itanium_class" "ialu")])
1802 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
1804 (define_insn "mulsi3"
1805 [(set (match_operand:SI
0 "fr_register_operand" "=f")
1806 (mult:SI (match_operand:SI
1 "grfr_register_operand" "f")
1807 (match_operand:SI
2 "grfr_register_operand" "f")))]
1809 "xmpy.l %
0 = %
1, %
2"
1810 [(set_attr "itanium_class" "xmpy")])
1812 (define_insn "maddsi4"
1813 [(set (match_operand:SI
0 "fr_register_operand" "=f")
1814 (plus:SI (mult:SI (match_operand:SI
1 "grfr_register_operand" "f")
1815 (match_operand:SI
2 "grfr_register_operand" "f"))
1816 (match_operand:SI
3 "grfr_register_operand" "f")))]
1818 "xma.l %
0 = %
1, %
2, %
3"
1819 [(set_attr "itanium_class" "xmpy")])
1821 (define_insn "negsi2"
1822 [(set (match_operand:SI
0 "gr_register_operand" "=r")
1823 (neg:SI (match_operand:SI
1 "gr_register_operand" "r")))]
1826 [(set_attr "itanium_class" "ialu")])
1828 (define_expand "abssi2"
1830 (ge:BI (match_operand:SI
1 "gr_register_operand" "") (const_int
0)))
1831 (set (match_operand:SI
0 "gr_register_operand" "")
1832 (if_then_else:SI (eq (match_dup
2) (const_int
0))
1833 (neg:SI (match_dup
1))
1836 { operands[
2] = gen_reg_rtx (BImode); })
1838 (define_expand "sminsi3"
1840 (ge:BI (match_operand:SI
1 "gr_register_operand" "")
1841 (match_operand:SI
2 "gr_register_operand" "")))
1842 (set (match_operand:SI
0 "gr_register_operand" "")
1843 (if_then_else:SI (ne (match_dup
3) (const_int
0))
1844 (match_dup
2) (match_dup
1)))]
1846 { operands[
3] = gen_reg_rtx (BImode); })
1848 (define_expand "smaxsi3"
1850 (ge:BI (match_operand:SI
1 "gr_register_operand" "")
1851 (match_operand:SI
2 "gr_register_operand" "")))
1852 (set (match_operand:SI
0 "gr_register_operand" "")
1853 (if_then_else:SI (ne (match_dup
3) (const_int
0))
1854 (match_dup
1) (match_dup
2)))]
1856 { operands[
3] = gen_reg_rtx (BImode); })
1858 (define_expand "uminsi3"
1860 (geu:BI (match_operand:SI
1 "gr_register_operand" "")
1861 (match_operand:SI
2 "gr_register_operand" "")))
1862 (set (match_operand:SI
0 "gr_register_operand" "")
1863 (if_then_else:SI (ne (match_dup
3) (const_int
0))
1864 (match_dup
2) (match_dup
1)))]
1866 { operands[
3] = gen_reg_rtx (BImode); })
1868 (define_expand "umaxsi3"
1870 (geu:BI (match_operand:SI
1 "gr_register_operand" "")
1871 (match_operand:SI
2 "gr_register_operand" "")))
1872 (set (match_operand:SI
0 "gr_register_operand" "")
1873 (if_then_else:SI (ne (match_dup
3) (const_int
0))
1874 (match_dup
1) (match_dup
2)))]
1876 { operands[
3] = gen_reg_rtx (BImode); })
1878 (define_expand "divsi3"
1879 [(set (match_operand:SI
0 "register_operand" "")
1880 (div:SI (match_operand:SI
1 "general_operand" "")
1881 (match_operand:SI
2 "general_operand" "")))]
1882 "TARGET_INLINE_INT_DIV"
1884 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
1885 REAL_VALUE_TYPE twon34_r;
1887 op0_xf = gen_reg_rtx (XFmode);
1888 op0_di = gen_reg_rtx (DImode);
1890 if (CONSTANT_P (operands[
1]))
1891 operands[
1] = force_reg (SImode, operands[
1]);
1892 op1_xf = gen_reg_rtx (XFmode);
1893 expand_float (op1_xf, operands[
1],
0);
1895 if (CONSTANT_P (operands[
2]))
1896 operands[
2] = force_reg (SImode, operands[
2]);
1897 op2_xf = gen_reg_rtx (XFmode);
1898 expand_float (op2_xf, operands[
2],
0);
1901 real_2expN (&twon34_r, -
34);
1902 twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
1903 twon34 = force_reg (XFmode, twon34);
1905 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
1907 emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
1908 emit_move_insn (operands[
0], gen_lowpart (SImode, op0_di));
1912 (define_expand "modsi3"
1913 [(set (match_operand:SI
0 "register_operand" "")
1914 (mod:SI (match_operand:SI
1 "general_operand" "")
1915 (match_operand:SI
2 "general_operand" "")))]
1916 "TARGET_INLINE_INT_DIV"
1918 rtx op2_neg, op1_di, div;
1920 div = gen_reg_rtx (SImode);
1921 emit_insn (gen_divsi3 (div, operands[
1], operands[
2]));
1923 op2_neg = expand_unop (SImode, neg_optab, operands[
2], NULL_RTX,
0);
1925 /* This is a trick to get us to reuse the value that we're sure to
1926 have already copied to the FP regs. */
1927 op1_di = gen_reg_rtx (DImode);
1928 convert_move (op1_di, operands[
1],
0);
1930 emit_insn (gen_maddsi4 (operands[
0], div, op2_neg,
1931 gen_lowpart (SImode, op1_di)));
1935 (define_expand "udivsi3"
1936 [(set (match_operand:SI
0 "register_operand" "")
1937 (udiv:SI (match_operand:SI
1 "general_operand" "")
1938 (match_operand:SI
2 "general_operand" "")))]
1939 "TARGET_INLINE_INT_DIV"
1941 rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
1942 REAL_VALUE_TYPE twon34_r;
1944 op0_xf = gen_reg_rtx (XFmode);
1945 op0_di = gen_reg_rtx (DImode);
1947 if (CONSTANT_P (operands[
1]))
1948 operands[
1] = force_reg (SImode, operands[
1]);
1949 op1_xf = gen_reg_rtx (XFmode);
1950 expand_float (op1_xf, operands[
1],
1);
1952 if (CONSTANT_P (operands[
2]))
1953 operands[
2] = force_reg (SImode, operands[
2]);
1954 op2_xf = gen_reg_rtx (XFmode);
1955 expand_float (op2_xf, operands[
2],
1);
1958 real_2expN (&twon34_r, -
34);
1959 twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
1960 twon34 = force_reg (XFmode, twon34);
1962 emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
1964 emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx));
1965 emit_move_insn (operands[
0], gen_lowpart (SImode, op0_di));
1969 (define_expand "umodsi3"
1970 [(set (match_operand:SI
0 "register_operand" "")
1971 (umod:SI (match_operand:SI
1 "general_operand" "")
1972 (match_operand:SI
2 "general_operand" "")))]
1973 "TARGET_INLINE_INT_DIV"
1975 rtx op2_neg, op1_di, div;
1977 div = gen_reg_rtx (SImode);
1978 emit_insn (gen_udivsi3 (div, operands[
1], operands[
2]));
1980 op2_neg = expand_unop (SImode, neg_optab, operands[
2], NULL_RTX,
0);
1982 /* This is a trick to get us to reuse the value that we're sure to
1983 have already copied to the FP regs. */
1984 op1_di = gen_reg_rtx (DImode);
1985 convert_move (op1_di, operands[
1],
1);
1987 emit_insn (gen_maddsi4 (operands[
0], div, op2_neg,
1988 gen_lowpart (SImode, op1_di)));
1992 (define_insn_and_split "divsi3_internal"
1993 [(set (match_operand:XF
0 "fr_register_operand" "=&f")
1994 (float:XF (div:SI (match_operand:XF
1 "fr_register_operand" "f")
1995 (match_operand:XF
2 "fr_register_operand" "f"))))
1996 (clobber (match_scratch:XF
4 "=&f"))
1997 (clobber (match_scratch:XF
5 "=&f"))
1998 (clobber (match_scratch:BI
6 "=c"))
1999 (use (match_operand:XF
3 "fr_register_operand" "f"))]
2000 "TARGET_INLINE_INT_DIV"
2002 "&& reload_completed"
2003 [(parallel [(set (match_dup
0) (div:XF (const_int
1) (match_dup
2)))
2004 (set (match_dup
6) (unspec:BI [(match_dup
1) (match_dup
2)]
2005 UNSPEC_FR_RECIP_APPROX))
2006 (use (const_int
1))])
2007 (cond_exec (ne (match_dup
6) (const_int
0))
2008 (parallel [(set (match_dup
4) (mult:XF (match_dup
1) (match_dup
0)))
2009 (use (const_int
1))]))
2010 (cond_exec (ne (match_dup
6) (const_int
0))
2011 (parallel [(set (match_dup
5)
2012 (minus:XF (match_dup
7)
2013 (mult:XF (match_dup
2) (match_dup
0))))
2014 (use (const_int
1))]))
2015 (cond_exec (ne (match_dup
6) (const_int
0))
2016 (parallel [(set (match_dup
4)
2017 (plus:XF (mult:XF (match_dup
5) (match_dup
4))
2019 (use (const_int
1))]))
2020 (cond_exec (ne (match_dup
6) (const_int
0))
2021 (parallel [(set (match_dup
5)
2022 (plus:XF (mult:XF (match_dup
5) (match_dup
5))
2024 (use (const_int
1))]))
2025 (cond_exec (ne (match_dup
6) (const_int
0))
2026 (parallel [(set (match_dup
0)
2027 (plus:XF (mult:XF (match_dup
5) (match_dup
4))
2029 (use (const_int
1))]))
2031 "operands[
7] = CONST1_RTX (XFmode);"
2032 [(set_attr "predicable" "no")])
2034 ;; ::::::::::::::::::::
2036 ;; ::
64 bit Integer arithmetic
2038 ;; ::::::::::::::::::::
2040 (define_insn "adddi3"
2041 [(set (match_operand:DI
0 "gr_register_operand" "=r,r,r")
2042 (plus:DI (match_operand:DI
1 "gr_register_operand" "%r,r,a")
2043 (match_operand:DI
2 "gr_reg_or_22bit_operand" "r,I,J")))]
2049 [(set_attr "itanium_class" "ialu")])
2051 (define_insn "*adddi3_plus1"
2052 [(set (match_operand:DI
0 "gr_register_operand" "=r")
2053 (plus:DI (plus:DI (match_operand:DI
1 "gr_register_operand" "r")
2054 (match_operand:DI
2 "gr_register_operand" "r"))
2057 "add %
0 = %
1, %
2,
1"
2058 [(set_attr "itanium_class" "ialu")])
2060 ;; This has some of the same problems as shladd. We let the shladd
2061 ;; eliminator hack handle it, which results in the
1 being forced into
2062 ;; a register, but not more ugliness here.
2063 (define_insn "*adddi3_plus1_alt"
2064 [(set (match_operand:DI
0 "gr_register_operand" "=r")
2065 (plus:DI (mult:DI (match_operand:DI
1 "gr_register_operand" "r")
2069 "add %
0 = %
1, %
1,
1"
2070 [(set_attr "itanium_class" "ialu")])
2072 (define_insn "subdi3"
2073 [(set (match_operand:DI
0 "gr_register_operand" "=r")
2074 (minus:DI (match_operand:DI
1 "gr_reg_or_8bit_operand" "rK")
2075 (match_operand:DI
2 "gr_register_operand" "r")))]
2078 [(set_attr "itanium_class" "ialu")])
2080 (define_insn "*subdi3_minus1"
2081 [(set (match_operand:DI
0 "gr_register_operand" "=r")
2082 (plus:DI (not:DI (match_operand:DI
1 "gr_register_operand" "r"))
2083 (match_operand:DI
2 "gr_register_operand" "r")))]
2085 "sub %
0 = %
2, %
1,
1"
2086 [(set_attr "itanium_class" "ialu")])
2088 ;; ??? Use grfr instead of fr because of virtual register elimination
2089 ;; and silly test cases multiplying by the frame pointer.
2090 (define_insn "muldi3"
2091 [(set (match_operand:DI
0 "fr_register_operand" "=f")
2092 (mult:DI (match_operand:DI
1 "grfr_register_operand" "f")
2093 (match_operand:DI
2 "grfr_register_operand" "f")))]
2095 "xmpy.l %
0 = %
1, %
2"
2096 [(set_attr "itanium_class" "xmpy")])
2098 ;; ??? If operand
3 is an eliminable reg, then register elimination causes the
2099 ;; same problem that we have with shladd below. Unfortunately, this case is
2100 ;; much harder to fix because the multiply puts the result in an FP register,
2101 ;; but the add needs inputs from a general register. We add a spurious clobber
2102 ;; here so that it will be present just in case register elimination gives us
2103 ;; the funny result.
2105 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2107 ;; ??? Maybe we should change how adds are canonicalized.
2109 (define_insn "madddi4"
2110 [(set (match_operand:DI
0 "fr_register_operand" "=f")
2111 (plus:DI (mult:DI (match_operand:DI
1 "grfr_register_operand" "f")
2112 (match_operand:DI
2 "grfr_register_operand" "f"))
2113 (match_operand:DI
3 "grfr_register_operand" "f")))
2114 (clobber (match_scratch:DI
4 "=X"))]
2116 "xma.l %
0 = %
1, %
2, %
3"
2117 [(set_attr "itanium_class" "xmpy")])
2119 ;; This can be created by register elimination if operand3 of shladd is an
2120 ;; eliminable register or has reg_equiv_constant set.
2122 ;; We have to use nonmemory_operand for operand
4, to ensure that the
2123 ;; validate_changes call inside eliminate_regs will always succeed. If it
2124 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2127 (define_insn "*madddi4_elim"
2128 [(set (match_operand:DI
0 "register_operand" "=&r")
2129 (plus:DI (plus:DI (mult:DI (match_operand:DI
1 "register_operand" "f")
2130 (match_operand:DI
2 "register_operand" "f"))
2131 (match_operand:DI
3 "register_operand" "f"))
2132 (match_operand:DI
4 "nonmemory_operand" "rI")))
2133 (clobber (match_scratch:DI
5 "=f"))]
2134 "reload_in_progress"
2136 [(set_attr "itanium_class" "unknown")])
2139 [(set (match_operand:DI
0 "register_operand" "")
2140 (plus:DI (plus:DI (mult:DI (match_operand:DI
1 "register_operand" "")
2141 (match_operand:DI
2 "register_operand" ""))
2142 (match_operand:DI
3 "register_operand" ""))
2143 (match_operand:DI
4 "gr_reg_or_14bit_operand" "")))
2144 (clobber (match_scratch:DI
5 ""))]
2146 [(parallel [(set (match_dup
5) (plus:DI (mult:DI (match_dup
1) (match_dup
2))
2148 (clobber (match_dup
0))])
2149 (set (match_dup
0) (match_dup
5))
2150 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
4)))]
2153 ;; ??? There are highpart multiply and add instructions, but we have no way
2154 ;; to generate them.
2156 (define_insn "smuldi3_highpart"
2157 [(set (match_operand:DI
0 "fr_register_operand" "=f")
2160 (mult:TI (sign_extend:TI
2161 (match_operand:DI
1 "fr_register_operand" "f"))
2163 (match_operand:DI
2 "fr_register_operand" "f")))
2166 "xmpy.h %
0 = %
1, %
2"
2167 [(set_attr "itanium_class" "xmpy")])
2169 (define_insn "umuldi3_highpart"
2170 [(set (match_operand:DI
0 "fr_register_operand" "=f")
2173 (mult:TI (zero_extend:TI
2174 (match_operand:DI
1 "fr_register_operand" "f"))
2176 (match_operand:DI
2 "fr_register_operand" "f")))
2179 "xmpy.hu %
0 = %
1, %
2"
2180 [(set_attr "itanium_class" "xmpy")])
2182 (define_insn "negdi2"
2183 [(set (match_operand:DI
0 "gr_register_operand" "=r")
2184 (neg:DI (match_operand:DI
1 "gr_register_operand" "r")))]
2187 [(set_attr "itanium_class" "ialu")])
2189 (define_expand "absdi2"
2191 (ge:BI (match_operand:DI
1 "gr_register_operand" "") (const_int
0)))
2192 (set (match_operand:DI
0 "gr_register_operand" "")
2193 (if_then_else:DI (eq (match_dup
2) (const_int
0))
2194 (neg:DI (match_dup
1))
2197 { operands[
2] = gen_reg_rtx (BImode); })
2199 (define_expand "smindi3"
2201 (ge:BI (match_operand:DI
1 "gr_register_operand" "")
2202 (match_operand:DI
2 "gr_register_operand" "")))
2203 (set (match_operand:DI
0 "gr_register_operand" "")
2204 (if_then_else:DI (ne (match_dup
3) (const_int
0))
2205 (match_dup
2) (match_dup
1)))]
2207 { operands[
3] = gen_reg_rtx (BImode); })
2209 (define_expand "smaxdi3"
2211 (ge:BI (match_operand:DI
1 "gr_register_operand" "")
2212 (match_operand:DI
2 "gr_register_operand" "")))
2213 (set (match_operand:DI
0 "gr_register_operand" "")
2214 (if_then_else:DI (ne (match_dup
3) (const_int
0))
2215 (match_dup
1) (match_dup
2)))]
2217 { operands[
3] = gen_reg_rtx (BImode); })
2219 (define_expand "umindi3"
2221 (geu:BI (match_operand:DI
1 "gr_register_operand" "")
2222 (match_operand:DI
2 "gr_register_operand" "")))
2223 (set (match_operand:DI
0 "gr_register_operand" "")
2224 (if_then_else:DI (ne (match_dup
3) (const_int
0))
2225 (match_dup
2) (match_dup
1)))]
2227 { operands[
3] = gen_reg_rtx (BImode); })
2229 (define_expand "umaxdi3"
2231 (geu:BI (match_operand:DI
1 "gr_register_operand" "")
2232 (match_operand:DI
2 "gr_register_operand" "")))
2233 (set (match_operand:DI
0 "gr_register_operand" "")
2234 (if_then_else:DI (ne (match_dup
3) (const_int
0))
2235 (match_dup
1) (match_dup
2)))]
2237 { operands[
3] = gen_reg_rtx (BImode); })
2239 (define_expand "ffsdi2"
2241 (eq:BI (match_operand:DI
1 "gr_register_operand" "") (const_int
0)))
2242 (set (match_dup
2) (plus:DI (match_dup
1) (const_int -
1)))
2243 (set (match_dup
5) (const_int
0))
2244 (set (match_dup
3) (xor:DI (match_dup
1) (match_dup
2)))
2245 (set (match_dup
4) (popcount:DI (match_dup
3)))
2246 (set (match_operand:DI
0 "gr_register_operand" "")
2247 (if_then_else:DI (ne (match_dup
6) (const_int
0))
2248 (match_dup
5) (match_dup
4)))]
2251 operands[
2] = gen_reg_rtx (DImode);
2252 operands[
3] = gen_reg_rtx (DImode);
2253 operands[
4] = gen_reg_rtx (DImode);
2254 operands[
5] = gen_reg_rtx (DImode);
2255 operands[
6] = gen_reg_rtx (BImode);
2258 (define_expand "ctzdi2"
2259 [(set (match_dup
2) (plus:DI (match_operand:DI
1 "gr_register_operand" "")
2261 (set (match_dup
3) (not:DI (match_dup
1)))
2262 (set (match_dup
4) (and:DI (match_dup
2) (match_dup
3)))
2263 (set (match_operand:DI
0 "gr_register_operand" "")
2264 (popcount:DI (match_dup
4)))]
2267 operands[
2] = gen_reg_rtx (DImode);
2268 operands[
3] = gen_reg_rtx (DImode);
2269 operands[
4] = gen_reg_rtx (DImode);
2272 ;; Note the computation here is op0 =
63 - (exp -
0xffff).
2273 (define_expand "clzdi2"
2275 (unsigned_float:XF (match_operand:DI
1 "fr_register_operand" "")))
2277 (unspec:DI [(match_dup
2)] UNSPEC_GETF_EXP))
2278 (set (match_dup
4) (const_int
65598))
2279 (set (match_operand:DI
0 "gr_register_operand" "")
2280 (minus:DI (match_dup
4) (match_dup
3)))]
2283 operands[
2] = gen_reg_rtx (XFmode);
2284 operands[
3] = gen_reg_rtx (DImode);
2285 operands[
4] = gen_reg_rtx (DImode);
2288 (define_insn "popcountdi2"
2289 [(set (match_operand:DI
0 "gr_register_operand" "=r")
2290 (popcount:DI (match_operand:DI
1 "gr_register_operand" "r")))]
2293 [(set_attr "itanium_class" "mmmul")])
2295 (define_insn "*getf_exp_xf"
2296 [(set (match_operand:DI
0 "gr_register_operand" "=r")
2297 (unspec:DI [(match_operand:XF
1 "fr_register_operand" "f")]
2301 [(set_attr "itanium_class" "frfr")])
2303 (define_expand "divdi3"
2304 [(set (match_operand:DI
0 "register_operand" "")
2305 (div:DI (match_operand:DI
1 "general_operand" "")
2306 (match_operand:DI
2 "general_operand" "")))]
2307 "TARGET_INLINE_INT_DIV"
2309 rtx op1_xf, op2_xf, op0_xf;
2311 op0_xf = gen_reg_rtx (XFmode);
2313 if (CONSTANT_P (operands[
1]))
2314 operands[
1] = force_reg (DImode, operands[
1]);
2315 op1_xf = gen_reg_rtx (XFmode);
2316 expand_float (op1_xf, operands[
1],
0);
2318 if (CONSTANT_P (operands[
2]))
2319 operands[
2] = force_reg (DImode, operands[
2]);
2320 op2_xf = gen_reg_rtx (XFmode);
2321 expand_float (op2_xf, operands[
2],
0);
2323 if (TARGET_INLINE_INT_DIV_LAT)
2324 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2326 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2328 emit_insn (gen_fix_truncxfdi2_alts (operands[
0], op0_xf, const1_rtx));
2332 (define_expand "moddi3"
2333 [(set (match_operand:DI
0 "register_operand" "")
2334 (mod:SI (match_operand:DI
1 "general_operand" "")
2335 (match_operand:DI
2 "general_operand" "")))]
2336 "TARGET_INLINE_INT_DIV"
2340 div = gen_reg_rtx (DImode);
2341 emit_insn (gen_divdi3 (div, operands[
1], operands[
2]));
2343 op2_neg = expand_unop (DImode, neg_optab, operands[
2], NULL_RTX,
0);
2345 emit_insn (gen_madddi4 (operands[
0], div, op2_neg, operands[
1]));
2349 (define_expand "udivdi3"
2350 [(set (match_operand:DI
0 "register_operand" "")
2351 (udiv:DI (match_operand:DI
1 "general_operand" "")
2352 (match_operand:DI
2 "general_operand" "")))]
2353 "TARGET_INLINE_INT_DIV"
2355 rtx op1_xf, op2_xf, op0_xf;
2357 op0_xf = gen_reg_rtx (XFmode);
2359 if (CONSTANT_P (operands[
1]))
2360 operands[
1] = force_reg (DImode, operands[
1]);
2361 op1_xf = gen_reg_rtx (XFmode);
2362 expand_float (op1_xf, operands[
1],
1);
2364 if (CONSTANT_P (operands[
2]))
2365 operands[
2] = force_reg (DImode, operands[
2]);
2366 op2_xf = gen_reg_rtx (XFmode);
2367 expand_float (op2_xf, operands[
2],
1);
2369 if (TARGET_INLINE_INT_DIV_LAT)
2370 emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
2372 emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
2374 emit_insn (gen_fixuns_truncxfdi2_alts (operands[
0], op0_xf, const1_rtx));
2378 (define_expand "umoddi3"
2379 [(set (match_operand:DI
0 "register_operand" "")
2380 (umod:DI (match_operand:DI
1 "general_operand" "")
2381 (match_operand:DI
2 "general_operand" "")))]
2382 "TARGET_INLINE_INT_DIV"
2386 div = gen_reg_rtx (DImode);
2387 emit_insn (gen_udivdi3 (div, operands[
1], operands[
2]));
2389 op2_neg = expand_unop (DImode, neg_optab, operands[
2], NULL_RTX,
0);
2391 emit_insn (gen_madddi4 (operands[
0], div, op2_neg, operands[
1]));
2395 (define_insn_and_split "divdi3_internal_lat"
2396 [(set (match_operand:XF
0 "fr_register_operand" "=&f")
2397 (float:XF (div:SI (match_operand:XF
1 "fr_register_operand" "f")
2398 (match_operand:XF
2 "fr_register_operand" "f"))))
2399 (clobber (match_scratch:XF
3 "=&f"))
2400 (clobber (match_scratch:XF
4 "=&f"))
2401 (clobber (match_scratch:XF
5 "=&f"))
2402 (clobber (match_scratch:BI
6 "=c"))]
2403 "TARGET_INLINE_INT_DIV_LAT"
2405 "&& reload_completed"
2406 [(parallel [(set (match_dup
0) (div:XF (const_int
1) (match_dup
2)))
2407 (set (match_dup
6) (unspec:BI [(match_dup
1) (match_dup
2)]
2408 UNSPEC_FR_RECIP_APPROX))
2409 (use (const_int
1))])
2410 (cond_exec (ne (match_dup
6) (const_int
0))
2411 (parallel [(set (match_dup
3)
2412 (minus:XF (match_dup
7)
2413 (mult:XF (match_dup
2) (match_dup
0))))
2414 (use (const_int
1))]))
2415 (cond_exec (ne (match_dup
6) (const_int
0))
2416 (parallel [(set (match_dup
4) (mult:XF (match_dup
1) (match_dup
0)))
2417 (use (const_int
1))]))
2418 (cond_exec (ne (match_dup
6) (const_int
0))
2419 (parallel [(set (match_dup
5) (mult:XF (match_dup
3) (match_dup
3)))
2420 (use (const_int
1))]))
2421 (cond_exec (ne (match_dup
6) (const_int
0))
2422 (parallel [(set (match_dup
4)
2423 (plus:XF (mult:XF (match_dup
3) (match_dup
4))
2425 (use (const_int
1))]))
2426 (cond_exec (ne (match_dup
6) (const_int
0))
2427 (parallel [(set (match_dup
0)
2428 (plus:XF (mult:XF (match_dup
3) (match_dup
0))
2430 (use (const_int
1))]))
2431 (cond_exec (ne (match_dup
6) (const_int
0))
2432 (parallel [(set (match_dup
3)
2433 (plus:XF (mult:XF (match_dup
5) (match_dup
4))
2435 (use (const_int
1))]))
2436 (cond_exec (ne (match_dup
6) (const_int
0))
2437 (parallel [(set (match_dup
0)
2438 (plus:XF (mult:XF (match_dup
5) (match_dup
0))
2440 (use (const_int
1))]))
2441 (cond_exec (ne (match_dup
6) (const_int
0))
2442 (parallel [(set (match_dup
4)
2443 (minus:XF (match_dup
1)
2444 (mult:XF (match_dup
2) (match_dup
3))))
2445 (use (const_int
1))]))
2446 (cond_exec (ne (match_dup
6) (const_int
0))
2447 (parallel [(set (match_dup
0)
2448 (plus:XF (mult:XF (match_dup
4) (match_dup
0))
2450 (use (const_int
1))]))
2452 "operands[
7] = CONST1_RTX (XFmode);"
2453 [(set_attr "predicable" "no")])
2455 (define_insn_and_split "divdi3_internal_thr"
2456 [(set (match_operand:XF
0 "fr_register_operand" "=&f")
2457 (float:XF (div:SI (match_operand:XF
1 "fr_register_operand" "f")
2458 (match_operand:XF
2 "fr_register_operand" "f"))))
2459 (clobber (match_scratch:XF
3 "=&f"))
2460 (clobber (match_scratch:XF
4 "=f"))
2461 (clobber (match_scratch:BI
5 "=c"))]
2462 "TARGET_INLINE_INT_DIV_THR"
2464 "&& reload_completed"
2465 [(parallel [(set (match_dup
0) (div:XF (const_int
1) (match_dup
2)))
2466 (set (match_dup
5) (unspec:BI [(match_dup
1) (match_dup
2)]
2467 UNSPEC_FR_RECIP_APPROX))
2468 (use (const_int
1))])
2469 (cond_exec (ne (match_dup
5) (const_int
0))
2470 (parallel [(set (match_dup
3)
2471 (minus:XF (match_dup
6)
2472 (mult:XF (match_dup
2) (match_dup
0))))
2473 (use (const_int
1))]))
2474 (cond_exec (ne (match_dup
5) (const_int
0))
2475 (parallel [(set (match_dup
0)
2476 (plus:XF (mult:XF (match_dup
3) (match_dup
0))
2478 (use (const_int
1))]))
2479 (cond_exec (ne (match_dup
5) (const_int
0))
2480 (parallel [(set (match_dup
3) (mult:XF (match_dup
3) (match_dup
3)))
2481 (use (const_int
1))]))
2482 (cond_exec (ne (match_dup
5) (const_int
0))
2483 (parallel [(set (match_dup
0)
2484 (plus:XF (mult:XF (match_dup
3) (match_dup
0))
2486 (use (const_int
1))]))
2487 (cond_exec (ne (match_dup
5) (const_int
0))
2488 (parallel [(set (match_dup
3) (mult:XF (match_dup
0) (match_dup
1)))
2489 (use (const_int
1))]))
2490 (cond_exec (ne (match_dup
5) (const_int
0))
2491 (parallel [(set (match_dup
4)
2492 (minus:XF (match_dup
1)
2493 (mult:XF (match_dup
2) (match_dup
3))))
2494 (use (const_int
1))]))
2495 (cond_exec (ne (match_dup
5) (const_int
0))
2496 (parallel [(set (match_dup
0)
2497 (plus:XF (mult:XF (match_dup
4) (match_dup
0))
2499 (use (const_int
1))]))
2501 "operands[
6] = CONST1_RTX (XFmode);"
2502 [(set_attr "predicable" "no")])
2504 ;; ::::::::::::::::::::
2506 ;; ::
32 bit floating point arithmetic
2508 ;; ::::::::::::::::::::
2510 (define_insn "addsf3"
2511 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2512 (plus:SF (match_operand:SF
1 "fr_register_operand" "%f")
2513 (match_operand:SF
2 "fr_reg_or_fp01_operand" "fG")))]
2515 "fadd.s %
0 = %
1, %F2"
2516 [(set_attr "itanium_class" "fmac")])
2518 (define_insn "subsf3"
2519 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2520 (minus:SF (match_operand:SF
1 "fr_reg_or_fp01_operand" "fG")
2521 (match_operand:SF
2 "fr_reg_or_fp01_operand" "fG")))]
2523 "fsub.s %
0 = %F1, %F2"
2524 [(set_attr "itanium_class" "fmac")])
2526 (define_insn "mulsf3"
2527 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2528 (mult:SF (match_operand:SF
1 "fr_register_operand" "%f")
2529 (match_operand:SF
2 "fr_register_operand" "f")))]
2531 "fmpy.s %
0 = %
1, %
2"
2532 [(set_attr "itanium_class" "fmac")])
2534 (define_insn "abssf2"
2535 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2536 (abs:SF (match_operand:SF
1 "fr_register_operand" "f")))]
2539 [(set_attr "itanium_class" "fmisc")])
2541 (define_insn "negsf2"
2542 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2543 (neg:SF (match_operand:SF
1 "fr_register_operand" "f")))]
2546 [(set_attr "itanium_class" "fmisc")])
2548 (define_insn "*nabssf2"
2549 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2550 (neg:SF (abs:SF (match_operand:SF
1 "fr_register_operand" "f"))))]
2553 [(set_attr "itanium_class" "fmisc")])
2555 (define_insn "minsf3"
2556 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2557 (smin:SF (match_operand:SF
1 "fr_register_operand" "f")
2558 (match_operand:SF
2 "fr_reg_or_fp01_operand" "fG")))]
2561 [(set_attr "itanium_class" "fmisc")])
2563 (define_insn "maxsf3"
2564 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2565 (smax:SF (match_operand:SF
1 "fr_register_operand" "f")
2566 (match_operand:SF
2 "fr_reg_or_fp01_operand" "fG")))]
2569 [(set_attr "itanium_class" "fmisc")])
2571 (define_insn "*maddsf4"
2572 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2573 (plus:SF (mult:SF (match_operand:SF
1 "fr_register_operand" "f")
2574 (match_operand:SF
2 "fr_register_operand" "f"))
2575 (match_operand:SF
3 "fr_reg_or_fp01_operand" "fG")))]
2577 "fma.s %
0 = %
1, %
2, %F3"
2578 [(set_attr "itanium_class" "fmac")])
2580 (define_insn "*msubsf4"
2581 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2582 (minus:SF (mult:SF (match_operand:SF
1 "fr_register_operand" "f")
2583 (match_operand:SF
2 "fr_register_operand" "f"))
2584 (match_operand:SF
3 "fr_reg_or_fp01_operand" "fG")))]
2586 "fms.s %
0 = %
1, %
2, %F3"
2587 [(set_attr "itanium_class" "fmac")])
2589 (define_insn "*nmulsf3"
2590 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2591 (neg:SF (mult:SF (match_operand:SF
1 "fr_register_operand" "f")
2592 (match_operand:SF
2 "fr_register_operand" "f"))))]
2594 "fnmpy.s %
0 = %
1, %
2"
2595 [(set_attr "itanium_class" "fmac")])
2597 (define_insn "*nmaddsf4"
2598 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2599 (minus:SF (match_operand:SF
3 "fr_reg_or_fp01_operand" "fG")
2600 (mult:SF (match_operand:SF
1 "fr_register_operand" "f")
2601 (match_operand:SF
2 "fr_register_operand" "f"))))]
2603 "fnma.s %
0 = %
1, %
2, %F3"
2604 [(set_attr "itanium_class" "fmac")])
2606 (define_insn "*nmaddsf4_alts"
2607 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2608 (minus:SF (match_operand:SF
3 "fr_reg_or_fp01_operand" "fG")
2609 (mult:SF (match_operand:SF
1 "fr_register_operand" "f")
2610 (match_operand:SF
2 "fr_register_operand" "f"))))
2611 (use (match_operand:SI
4 "const_int_operand" ""))]
2613 "fnma.s.s%
4 %
0 = %
1, %
2, %F3"
2614 [(set_attr "itanium_class" "fmac")])
2616 (define_expand "divsf3"
2617 [(set (match_operand:SF
0 "fr_register_operand" "")
2618 (div:SF (match_operand:SF
1 "fr_register_operand" "")
2619 (match_operand:SF
2 "fr_register_operand" "")))]
2620 "TARGET_INLINE_FLOAT_DIV"
2623 if (TARGET_INLINE_FLOAT_DIV_LAT)
2624 insn = gen_divsf3_internal_lat (operands[
0], operands[
1], operands[
2]);
2626 insn = gen_divsf3_internal_thr (operands[
0], operands[
1], operands[
2]);
2631 (define_insn_and_split "divsf3_internal_lat"
2632 [(set (match_operand:SF
0 "fr_register_operand" "=&f")
2633 (div:SF (match_operand:SF
1 "fr_register_operand" "f")
2634 (match_operand:SF
2 "fr_register_operand" "f")))
2635 (clobber (match_scratch:XF
3 "=&f"))
2636 (clobber (match_scratch:XF
4 "=f"))
2637 (clobber (match_scratch:BI
5 "=c"))]
2638 "TARGET_INLINE_FLOAT_DIV_LAT"
2640 "&& reload_completed"
2641 [(parallel [(set (match_dup
6) (div:XF (const_int
1) (match_dup
8)))
2642 (set (match_dup
5) (unspec:BI [(match_dup
7) (match_dup
8)]
2643 UNSPEC_FR_RECIP_APPROX))
2644 (use (const_int
1))])
2645 (cond_exec (ne (match_dup
5) (const_int
0))
2646 (parallel [(set (match_dup
3) (mult:XF (match_dup
7) (match_dup
6)))
2647 (use (const_int
1))]))
2648 (cond_exec (ne (match_dup
5) (const_int
0))
2649 (parallel [(set (match_dup
4)
2650 (minus:XF (match_dup
10)
2651 (mult:XF (match_dup
8) (match_dup
6))))
2652 (use (const_int
1))]))
2653 (cond_exec (ne (match_dup
5) (const_int
0))
2654 (parallel [(set (match_dup
3)
2655 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
2657 (use (const_int
1))]))
2658 (cond_exec (ne (match_dup
5) (const_int
0))
2659 (parallel [(set (match_dup
4) (mult:XF (match_dup
4) (match_dup
4)))
2660 (use (const_int
1))]))
2661 (cond_exec (ne (match_dup
5) (const_int
0))
2662 (parallel [(set (match_dup
3)
2663 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
2665 (use (const_int
1))]))
2666 (cond_exec (ne (match_dup
5) (const_int
0))
2667 (parallel [(set (match_dup
4) (mult:XF (match_dup
4) (match_dup
4)))
2668 (use (const_int
1))]))
2669 (cond_exec (ne (match_dup
5) (const_int
0))
2670 (parallel [(set (match_dup
9)
2672 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
2674 (use (const_int
1))]))
2675 (cond_exec (ne (match_dup
5) (const_int
0))
2677 (float_truncate:SF (match_dup
6))))
2680 operands[
6] = gen_rtx_REG (XFmode, REGNO (operands[
0]));
2681 operands[
7] = gen_rtx_REG (XFmode, REGNO (operands[
1]));
2682 operands[
8] = gen_rtx_REG (XFmode, REGNO (operands[
2]));
2683 operands[
9] = gen_rtx_REG (DFmode, REGNO (operands[
0]));
2684 operands[
10] = CONST1_RTX (XFmode);
2686 [(set_attr "predicable" "no")])
2688 (define_insn_and_split "divsf3_internal_thr"
2689 [(set (match_operand:SF
0 "fr_register_operand" "=&f")
2690 (div:SF (match_operand:SF
1 "fr_register_operand" "f")
2691 (match_operand:SF
2 "fr_register_operand" "f")))
2692 (clobber (match_scratch:XF
3 "=&f"))
2693 (clobber (match_scratch:XF
4 "=f"))
2694 (clobber (match_scratch:BI
5 "=c"))]
2695 "TARGET_INLINE_FLOAT_DIV_THR"
2697 "&& reload_completed"
2698 [(parallel [(set (match_dup
6) (div:XF (const_int
1) (match_dup
8)))
2699 (set (match_dup
5) (unspec:BI [(match_dup
7) (match_dup
8)]
2700 UNSPEC_FR_RECIP_APPROX))
2701 (use (const_int
1))])
2702 (cond_exec (ne (match_dup
5) (const_int
0))
2703 (parallel [(set (match_dup
3)
2704 (minus:XF (match_dup
10)
2705 (mult:XF (match_dup
8) (match_dup
6))))
2706 (use (const_int
1))]))
2707 (cond_exec (ne (match_dup
5) (const_int
0))
2708 (parallel [(set (match_dup
3)
2709 (plus:XF (mult:XF (match_dup
3) (match_dup
3))
2711 (use (const_int
1))]))
2712 (cond_exec (ne (match_dup
5) (const_int
0))
2713 (parallel [(set (match_dup
6)
2714 (plus:XF (mult:XF (match_dup
3) (match_dup
6))
2716 (use (const_int
1))]))
2717 (cond_exec (ne (match_dup
5) (const_int
0))
2718 (parallel [(set (match_dup
9)
2720 (mult:XF (match_dup
7) (match_dup
6))))
2721 (use (const_int
1))]))
2722 (cond_exec (ne (match_dup
5) (const_int
0))
2723 (parallel [(set (match_dup
4)
2724 (minus:XF (match_dup
7)
2725 (mult:XF (match_dup
8) (match_dup
3))))
2726 (use (const_int
1))]))
2727 (cond_exec (ne (match_dup
5) (const_int
0))
2730 (plus:XF (mult:XF (match_dup
4) (match_dup
6))
2734 operands[
6] = gen_rtx_REG (XFmode, REGNO (operands[
0]));
2735 operands[
7] = gen_rtx_REG (XFmode, REGNO (operands[
1]));
2736 operands[
8] = gen_rtx_REG (XFmode, REGNO (operands[
2]));
2737 operands[
9] = gen_rtx_REG (SFmode, REGNO (operands[
3]));
2738 operands[
10] = CONST1_RTX (XFmode);
2740 [(set_attr "predicable" "no")])
2742 ;; Inline square root.
2744 (define_insn "*sqrt_approx"
2745 [(set (match_operand:XF
0 "fr_register_operand" "=f")
2746 (div:XF (const_int
1)
2747 (sqrt:XF (match_operand:XF
2 "fr_register_operand" "f"))))
2748 (set (match_operand:BI
1 "register_operand" "=c")
2749 (unspec:BI [(match_dup
2)] UNSPEC_FR_SQRT_RECIP_APPROX))
2750 (use (match_operand:SI
3 "const_int_operand" "")) ]
2752 "frsqrta.s%
3 %
0, %
1 = %
2"
2753 [(set_attr "itanium_class" "fmisc")
2754 (set_attr "predicable" "no")])
2756 (define_insn "*setf_exp_xf"
2757 [(set (match_operand:XF
0 "fr_register_operand" "=f")
2758 (unspec:XF [(match_operand:DI
1 "register_operand" "r")]
2762 [(set_attr "itanium_class" "frfr")])
2764 (define_expand "sqrtsf2"
2765 [(set (match_operand:SF
0 "fr_register_operand" "=&f")
2766 (sqrt:SF (match_operand:SF
1 "fr_register_operand" "f")))]
2767 "TARGET_INLINE_SQRT"
2770 if (TARGET_INLINE_SQRT_LAT)
2772 insn = gen_sqrtsf2_internal_lat (operands[
0], operands[
1]);
2777 insn = gen_sqrtsf2_internal_thr (operands[
0], operands[
1]);
2782 ;; Latency-optimized square root.
2783 ;; FIXME: Implement.
2785 ;; Throughput-optimized square root.
2787 (define_insn_and_split "sqrtsf2_internal_thr"
2788 [(set (match_operand:SF
0 "fr_register_operand" "=&f")
2789 (sqrt:SF (match_operand:SF
1 "fr_register_operand" "f")))
2790 ;; Register r2 in optimization guide.
2791 (clobber (match_scratch:DI
2 "=r"))
2792 ;; Register f8 in optimization guide
2793 (clobber (match_scratch:XF
3 "=&f"))
2794 ;; Register f9 in optimization guide
2795 (clobber (match_scratch:XF
4 "=&f"))
2796 ;; Register f10 in optimization guide
2797 (clobber (match_scratch:XF
5 "=&f"))
2798 ;; Register p6 in optimization guide.
2799 (clobber (match_scratch:BI
6 "=c"))]
2800 "TARGET_INLINE_SQRT_THR"
2802 "&& reload_completed"
2803 [ ;; exponent of +
1/
2 in r2
2804 (set (match_dup
2) (const_int
65534))
2807 (unspec:XF [(match_dup
2)] UNSPEC_SETF_EXP))
2809 ;; y0 =
1/sqrt(a) in f7
2810 (parallel [(set (match_dup
7)
2811 (div:XF (const_int
1)
2812 (sqrt:XF (match_dup
8))))
2814 (unspec:BI [(match_dup
8)]
2815 UNSPEC_FR_SQRT_RECIP_APPROX))
2816 (use (const_int
0))])
2818 ;; H0 =
1/
2 * y0 in f9
2819 (cond_exec (ne (match_dup
6) (const_int
0))
2820 (parallel [(set (match_dup
4)
2821 (plus:XF (mult:XF (match_dup
3) (match_dup
7))
2823 (use (const_int
1))]))
2825 ;; S0 = a * y0 in f7
2826 (cond_exec (ne (match_dup
6) (const_int
0))
2827 (parallel [(set (match_dup
7)
2828 (plus:XF (mult:XF (match_dup
8) (match_dup
7))
2830 (use (const_int
1))]))
2832 ;; d =
1/
2 - S0 * H0 in f10
2833 (cond_exec (ne (match_dup
6) (const_int
0))
2834 (parallel [(set (match_dup
5)
2835 (minus:XF (match_dup
3)
2836 (mult:XF (match_dup
7) (match_dup
4))))
2837 (use (const_int
1))]))
2839 ;; d' = d +
1/
2 * d in f8
2840 (cond_exec (ne (match_dup
6) (const_int
0))
2841 (parallel [(set (match_dup
3)
2842 (plus:XF (mult:XF (match_dup
3) (match_dup
5))
2844 (use (const_int
1))]))
2846 ;; e = d + d * d' in f8
2847 (cond_exec (ne (match_dup
6) (const_int
0))
2848 (parallel [(set (match_dup
3)
2849 (plus:XF (mult:XF (match_dup
5) (match_dup
3))
2851 (use (const_int
1))]))
2853 ;; S1 = S0 + e * S0 in f7
2854 (cond_exec (ne (match_dup
6) (const_int
0))
2855 (parallel [(set (match_dup
0)
2857 (plus:XF (mult:XF (match_dup
3) (match_dup
7))
2859 (use (const_int
1))]))
2861 ;; H1 = H0 + e * H0 in f8
2862 (cond_exec (ne (match_dup
6) (const_int
0))
2863 (parallel [(set (match_dup
3)
2864 (plus:XF (mult:XF (match_dup
3) (match_dup
4))
2866 (use (const_int
1))]))
2868 ;; d1 = a - S1 * S1 in f9
2869 (cond_exec (ne (match_dup
6) (const_int
0))
2870 (parallel [(set (match_dup
4)
2871 (minus:XF (match_dup
8)
2872 (mult:XF (match_dup
7) (match_dup
7))))
2873 (use (const_int
1))]))
2875 ;; S = S1 + d1 * H1 in f7
2876 (cond_exec (ne (match_dup
6) (const_int
0))
2877 (parallel [(set (match_dup
0)
2879 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
2881 (use (const_int
0))]))]
2883 /* Generate
82-bit versions of the input and output operands. */
2884 operands[
7] = gen_rtx_REG (XFmode, REGNO (operands[
0]));
2885 operands[
8] = gen_rtx_REG (XFmode, REGNO (operands[
1]));
2886 /* Generate required floating-point constants. */
2887 operands[
9] = CONST0_RTX (XFmode);
2889 [(set_attr "predicable" "no")])
2891 ;; ::::::::::::::::::::
2893 ;; ::
64 bit floating point arithmetic
2895 ;; ::::::::::::::::::::
2897 (define_insn "adddf3"
2898 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2899 (plus:DF (match_operand:DF
1 "fr_register_operand" "%f")
2900 (match_operand:DF
2 "fr_reg_or_fp01_operand" "fG")))]
2902 "fadd.d %
0 = %
1, %F2"
2903 [(set_attr "itanium_class" "fmac")])
2905 (define_insn "*adddf3_trunc"
2906 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2908 (plus:DF (match_operand:DF
1 "fr_register_operand" "%f")
2909 (match_operand:DF
2 "fr_reg_or_fp01_operand" "fG"))))]
2911 "fadd.s %
0 = %
1, %F2"
2912 [(set_attr "itanium_class" "fmac")])
2914 (define_insn "subdf3"
2915 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2916 (minus:DF (match_operand:DF
1 "fr_reg_or_fp01_operand" "fG")
2917 (match_operand:DF
2 "fr_reg_or_fp01_operand" "fG")))]
2919 "fsub.d %
0 = %F1, %F2"
2920 [(set_attr "itanium_class" "fmac")])
2922 (define_insn "*subdf3_trunc"
2923 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2925 (minus:DF (match_operand:DF
1 "fr_reg_or_fp01_operand" "fG")
2926 (match_operand:DF
2 "fr_reg_or_fp01_operand" "fG"))))]
2928 "fsub.s %
0 = %F1, %F2"
2929 [(set_attr "itanium_class" "fmac")])
2931 (define_insn "muldf3"
2932 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2933 (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
2934 (match_operand:DF
2 "fr_register_operand" "f")))]
2936 "fmpy.d %
0 = %
1, %
2"
2937 [(set_attr "itanium_class" "fmac")])
2939 (define_insn "*muldf3_trunc"
2940 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2942 (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
2943 (match_operand:DF
2 "fr_register_operand" "f"))))]
2945 "fmpy.s %
0 = %
1, %
2"
2946 [(set_attr "itanium_class" "fmac")])
2948 (define_insn "absdf2"
2949 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2950 (abs:DF (match_operand:DF
1 "fr_register_operand" "f")))]
2953 [(set_attr "itanium_class" "fmisc")])
2955 (define_insn "negdf2"
2956 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2957 (neg:DF (match_operand:DF
1 "fr_register_operand" "f")))]
2960 [(set_attr "itanium_class" "fmisc")])
2962 (define_insn "*nabsdf2"
2963 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2964 (neg:DF (abs:DF (match_operand:DF
1 "fr_register_operand" "f"))))]
2967 [(set_attr "itanium_class" "fmisc")])
2969 (define_insn "mindf3"
2970 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2971 (smin:DF (match_operand:DF
1 "fr_register_operand" "f")
2972 (match_operand:DF
2 "fr_reg_or_fp01_operand" "fG")))]
2975 [(set_attr "itanium_class" "fmisc")])
2977 (define_insn "maxdf3"
2978 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2979 (smax:DF (match_operand:DF
1 "fr_register_operand" "f")
2980 (match_operand:DF
2 "fr_reg_or_fp01_operand" "fG")))]
2983 [(set_attr "itanium_class" "fmisc")])
2985 (define_insn "*madddf4"
2986 [(set (match_operand:DF
0 "fr_register_operand" "=f")
2987 (plus:DF (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
2988 (match_operand:DF
2 "fr_register_operand" "f"))
2989 (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG")))]
2991 "fma.d %
0 = %
1, %
2, %F3"
2992 [(set_attr "itanium_class" "fmac")])
2994 (define_insn "*madddf4_trunc"
2995 [(set (match_operand:SF
0 "fr_register_operand" "=f")
2997 (plus:DF (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
2998 (match_operand:DF
2 "fr_register_operand" "f"))
2999 (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG"))))]
3001 "fma.s %
0 = %
1, %
2, %F3"
3002 [(set_attr "itanium_class" "fmac")])
3004 (define_insn "*msubdf4"
3005 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3006 (minus:DF (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3007 (match_operand:DF
2 "fr_register_operand" "f"))
3008 (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG")))]
3010 "fms.d %
0 = %
1, %
2, %F3"
3011 [(set_attr "itanium_class" "fmac")])
3013 (define_insn "*msubdf4_trunc"
3014 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3016 (minus:DF (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3017 (match_operand:DF
2 "fr_register_operand" "f"))
3018 (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG"))))]
3020 "fms.s %
0 = %
1, %
2, %F3"
3021 [(set_attr "itanium_class" "fmac")])
3023 (define_insn "*nmuldf3"
3024 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3025 (neg:DF (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3026 (match_operand:DF
2 "fr_register_operand" "f"))))]
3028 "fnmpy.d %
0 = %
1, %
2"
3029 [(set_attr "itanium_class" "fmac")])
3031 (define_insn "*nmuldf3_trunc"
3032 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3034 (neg:DF (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3035 (match_operand:DF
2 "fr_register_operand" "f")))))]
3037 "fnmpy.s %
0 = %
1, %
2"
3038 [(set_attr "itanium_class" "fmac")])
3040 (define_insn "*nmadddf4"
3041 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3042 (minus:DF (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG")
3043 (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3044 (match_operand:DF
2 "fr_register_operand" "f"))))]
3046 "fnma.d %
0 = %
1, %
2, %F3"
3047 [(set_attr "itanium_class" "fmac")])
3049 (define_insn "*nmadddf4_alts"
3050 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3051 (minus:DF (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG")
3052 (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3053 (match_operand:DF
2 "fr_register_operand" "f"))))
3054 (use (match_operand:SI
4 "const_int_operand" ""))]
3056 "fnma.d.s%
4 %
0 = %
1, %
2, %F3"
3057 [(set_attr "itanium_class" "fmac")])
3059 (define_insn "*nmadddf4_truncsf"
3060 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3062 (minus:DF (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG")
3063 (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3064 (match_operand:DF
2 "fr_register_operand" "f")))))]
3066 "fnma.s %
0 = %
1, %
2, %F3"
3067 [(set_attr "itanium_class" "fmac")])
3069 (define_insn "*nmadddf4_truncsf_alts"
3070 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3072 (minus:DF (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG")
3073 (mult:DF (match_operand:DF
1 "fr_register_operand" "f")
3074 (match_operand:DF
2 "fr_register_operand" "f")))))
3075 (use (match_operand:SI
4 "const_int_operand" ""))]
3077 "fnma.s.s%
4 %
0 = %
1, %
2, %F3"
3078 [(set_attr "itanium_class" "fmac")])
3080 (define_expand "divdf3"
3081 [(set (match_operand:DF
0 "fr_register_operand" "")
3082 (div:DF (match_operand:DF
1 "fr_register_operand" "")
3083 (match_operand:DF
2 "fr_register_operand" "")))]
3084 "TARGET_INLINE_FLOAT_DIV"
3087 if (TARGET_INLINE_FLOAT_DIV_LAT)
3088 insn = gen_divdf3_internal_lat (operands[
0], operands[
1], operands[
2]);
3090 insn = gen_divdf3_internal_thr (operands[
0], operands[
1], operands[
2]);
3095 (define_insn_and_split "divdf3_internal_lat"
3096 [(set (match_operand:DF
0 "fr_register_operand" "=&f")
3097 (div:DF (match_operand:DF
1 "fr_register_operand" "f")
3098 (match_operand:DF
2 "fr_register_operand" "f")))
3099 (clobber (match_scratch:XF
3 "=&f"))
3100 (clobber (match_scratch:XF
4 "=&f"))
3101 (clobber (match_scratch:XF
5 "=&f"))
3102 (clobber (match_scratch:BI
6 "=c"))]
3103 "TARGET_INLINE_FLOAT_DIV_LAT"
3105 "&& reload_completed"
3106 [(parallel [(set (match_dup
7) (div:XF (const_int
1) (match_dup
9)))
3107 (set (match_dup
6) (unspec:BI [(match_dup
8) (match_dup
9)]
3108 UNSPEC_FR_RECIP_APPROX))
3109 (use (const_int
1))])
3110 (cond_exec (ne (match_dup
6) (const_int
0))
3111 (parallel [(set (match_dup
3) (mult:XF (match_dup
8) (match_dup
7)))
3112 (use (const_int
1))]))
3113 (cond_exec (ne (match_dup
6) (const_int
0))
3114 (parallel [(set (match_dup
4)
3115 (minus:XF (match_dup
12)
3116 (mult:XF (match_dup
9) (match_dup
7))))
3117 (use (const_int
1))]))
3118 (cond_exec (ne (match_dup
6) (const_int
0))
3119 (parallel [(set (match_dup
3)
3120 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
3122 (use (const_int
1))]))
3123 (cond_exec (ne (match_dup
6) (const_int
0))
3124 (parallel [(set (match_dup
5) (mult:XF (match_dup
4) (match_dup
4)))
3125 (use (const_int
1))]))
3126 (cond_exec (ne (match_dup
6) (const_int
0))
3127 (parallel [(set (match_dup
7)
3128 (plus:XF (mult:XF (match_dup
4) (match_dup
7))
3130 (use (const_int
1))]))
3131 (cond_exec (ne (match_dup
6) (const_int
0))
3132 (parallel [(set (match_dup
3)
3133 (plus:XF (mult:XF (match_dup
5) (match_dup
3))
3135 (use (const_int
1))]))
3136 (cond_exec (ne (match_dup
6) (const_int
0))
3137 (parallel [(set (match_dup
4) (mult:XF (match_dup
5) (match_dup
5)))
3138 (use (const_int
1))]))
3139 (cond_exec (ne (match_dup
6) (const_int
0))
3140 (parallel [(set (match_dup
7)
3141 (plus:XF (mult:XF (match_dup
5) (match_dup
7))
3143 (use (const_int
1))]))
3144 (cond_exec (ne (match_dup
6) (const_int
0))
3145 (parallel [(set (match_dup
10)
3147 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
3149 (use (const_int
1))]))
3150 (cond_exec (ne (match_dup
6) (const_int
0))
3151 (parallel [(set (match_dup
7)
3152 (plus:XF (mult:XF (match_dup
4) (match_dup
7))
3154 (use (const_int
1))]))
3155 (cond_exec (ne (match_dup
6) (const_int
0))
3156 (parallel [(set (match_dup
11)
3158 (minus:XF (match_dup
8)
3159 (mult:XF (match_dup
9) (match_dup
3)))))
3160 (use (const_int
1))]))
3161 (cond_exec (ne (match_dup
6) (const_int
0))
3163 (float_truncate:DF (plus:XF (mult:XF (match_dup
5) (match_dup
7))
3167 operands[
7] = gen_rtx_REG (XFmode, REGNO (operands[
0]));
3168 operands[
8] = gen_rtx_REG (XFmode, REGNO (operands[
1]));
3169 operands[
9] = gen_rtx_REG (XFmode, REGNO (operands[
2]));
3170 operands[
10] = gen_rtx_REG (DFmode, REGNO (operands[
3]));
3171 operands[
11] = gen_rtx_REG (DFmode, REGNO (operands[
5]));
3172 operands[
12] = CONST1_RTX (XFmode);
3174 [(set_attr "predicable" "no")])
3176 (define_insn_and_split "divdf3_internal_thr"
3177 [(set (match_operand:DF
0 "fr_register_operand" "=&f")
3178 (div:DF (match_operand:DF
1 "fr_register_operand" "f")
3179 (match_operand:DF
2 "fr_register_operand" "f")))
3180 (clobber (match_scratch:XF
3 "=&f"))
3181 (clobber (match_scratch:DF
4 "=f"))
3182 (clobber (match_scratch:BI
5 "=c"))]
3183 "TARGET_INLINE_FLOAT_DIV_THR"
3185 "&& reload_completed"
3186 [(parallel [(set (match_dup
6) (div:XF (const_int
1) (match_dup
8)))
3187 (set (match_dup
5) (unspec:BI [(match_dup
7) (match_dup
8)]
3188 UNSPEC_FR_RECIP_APPROX))
3189 (use (const_int
1))])
3190 (cond_exec (ne (match_dup
5) (const_int
0))
3191 (parallel [(set (match_dup
3)
3192 (minus:XF (match_dup
10)
3193 (mult:XF (match_dup
8) (match_dup
6))))
3194 (use (const_int
1))]))
3195 (cond_exec (ne (match_dup
5) (const_int
0))
3196 (parallel [(set (match_dup
6)
3197 (plus:XF (mult:XF (match_dup
3) (match_dup
6))
3199 (use (const_int
1))]))
3200 (cond_exec (ne (match_dup
5) (const_int
0))
3201 (parallel [(set (match_dup
3)
3202 (mult:XF (match_dup
3) (match_dup
3)))
3203 (use (const_int
1))]))
3204 (cond_exec (ne (match_dup
5) (const_int
0))
3205 (parallel [(set (match_dup
6)
3206 (plus:XF (mult:XF (match_dup
3) (match_dup
6))
3208 (use (const_int
1))]))
3209 (cond_exec (ne (match_dup
5) (const_int
0))
3210 (parallel [(set (match_dup
3)
3211 (mult:XF (match_dup
3) (match_dup
3)))
3212 (use (const_int
1))]))
3213 (cond_exec (ne (match_dup
5) (const_int
0))
3214 (parallel [(set (match_dup
6)
3215 (plus:XF (mult:XF (match_dup
3) (match_dup
6))
3217 (use (const_int
1))]))
3218 (cond_exec (ne (match_dup
5) (const_int
0))
3219 (parallel [(set (match_dup
9)
3221 (mult:XF (match_dup
7) (match_dup
3))))
3222 (use (const_int
1))]))
3223 (cond_exec (ne (match_dup
5) (const_int
0))
3224 (parallel [(set (match_dup
4)
3225 (minus:DF (match_dup
1)
3226 (mult:DF (match_dup
2) (match_dup
9))))
3227 (use (const_int
1))]))
3228 (cond_exec (ne (match_dup
5) (const_int
0))
3230 (plus:DF (mult:DF (match_dup
4) (match_dup
0))
3234 operands[
6] = gen_rtx_REG (XFmode, REGNO (operands[
0]));
3235 operands[
7] = gen_rtx_REG (XFmode, REGNO (operands[
1]));
3236 operands[
8] = gen_rtx_REG (XFmode, REGNO (operands[
2]));
3237 operands[
9] = gen_rtx_REG (DFmode, REGNO (operands[
3]));
3238 operands[
10] = CONST1_RTX (XFmode);
3240 [(set_attr "predicable" "no")])
3242 ;; Inline square root.
3244 (define_expand "sqrtdf2"
3245 [(set (match_operand:DF
0 "fr_register_operand" "=&f")
3246 (sqrt:DF (match_operand:DF
1 "fr_register_operand" "f")))]
3247 "TARGET_INLINE_SQRT"
3250 if (TARGET_INLINE_SQRT_LAT)
3252 insn = gen_sqrtdf2_internal_lat (operands[
0], operands[
1]);
3257 insn = gen_sqrtdf2_internal_thr (operands[
0], operands[
1]);
3262 ;; Latency-optimized square root.
3263 ;; FIXME: Implement.
3265 ;; Throughput-optimized square root.
3267 (define_insn_and_split "sqrtdf2_internal_thr"
3268 [(set (match_operand:DF
0 "fr_register_operand" "=&f")
3269 (sqrt:DF (match_operand:DF
1 "fr_register_operand" "f")))
3270 ;; Register r2 in optimization guide.
3271 (clobber (match_scratch:DI
2 "=r"))
3272 ;; Register f8 in optimization guide
3273 (clobber (match_scratch:XF
3 "=&f"))
3274 ;; Register f9 in optimization guide
3275 (clobber (match_scratch:XF
4 "=&f"))
3276 ;; Register f10 in optimization guide
3277 (clobber (match_scratch:XF
5 "=&f"))
3278 ;; Register p6 in optimization guide.
3279 (clobber (match_scratch:BI
6 "=c"))]
3280 "TARGET_INLINE_SQRT_THR"
3282 "&& reload_completed"
3283 [ ;; exponent of +
1/
2 in r2
3284 (set (match_dup
2) (const_int
65534))
3287 (unspec:XF [(match_dup
2)] UNSPEC_SETF_EXP))
3289 ;; y0 =
1/sqrt(a) in f7
3290 (parallel [(set (match_dup
7)
3291 (div:XF (const_int
1)
3292 (sqrt:XF (match_dup
8))))
3294 (unspec:BI [(match_dup
8)]
3295 UNSPEC_FR_SQRT_RECIP_APPROX))
3296 (use (const_int
0))])
3298 ;; H0 =
1/
2 * y0 in f8
3299 (cond_exec (ne (match_dup
6) (const_int
0))
3300 (parallel [(set (match_dup
3)
3301 (plus:XF (mult:XF (match_dup
5) (match_dup
7))
3303 (use (const_int
1))]))
3305 ;; G0 = a * y0 in f7
3306 (cond_exec (ne (match_dup
6) (const_int
0))
3307 (parallel [(set (match_dup
7)
3308 (plus:XF (mult:XF (match_dup
8) (match_dup
7))
3310 (use (const_int
1))]))
3312 ;; r0 =
1/
2 - G0 * H0 in f9
3313 (cond_exec (ne (match_dup
6) (const_int
0))
3314 (parallel [(set (match_dup
4)
3315 (minus:XF (match_dup
5)
3316 (mult:XF (match_dup
7) (match_dup
3))))
3317 (use (const_int
1))]))
3319 ;; H1 = H0 + r0 * H0 in f8
3320 (cond_exec (ne (match_dup
6) (const_int
0))
3321 (parallel [(set (match_dup
3)
3322 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
3324 (use (const_int
1))]))
3326 ;; G1 = G0 + r0 * G0 in f7
3327 (cond_exec (ne (match_dup
6) (const_int
0))
3328 (parallel [(set (match_dup
7)
3329 (plus:XF (mult:XF (match_dup
4) (match_dup
7))
3331 (use (const_int
1))]))
3333 ;; r1 =
1/
2 - G1 * H1 in f9
3334 (cond_exec (ne (match_dup
6) (const_int
0))
3335 (parallel [(set (match_dup
4)
3336 (minus:XF (match_dup
5)
3337 (mult:XF (match_dup
7) (match_dup
3))))
3338 (use (const_int
1))]))
3340 ;; H2 = H1 + r1 * H1 in f8
3341 (cond_exec (ne (match_dup
6) (const_int
0))
3342 (parallel [(set (match_dup
3)
3343 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
3345 (use (const_int
1))]))
3347 ;; G2 = G1 + r1 * G1 in f7
3348 (cond_exec (ne (match_dup
6) (const_int
0))
3349 (parallel [(set (match_dup
7)
3350 (plus:XF (mult:XF (match_dup
4) (match_dup
7))
3352 (use (const_int
1))]))
3354 ;; d2 = a - G2 * G2 in f9
3355 (cond_exec (ne (match_dup
6) (const_int
0))
3356 (parallel [(set (match_dup
4)
3357 (minus:XF (match_dup
8)
3358 (mult:XF (match_dup
7) (match_dup
7))))
3359 (use (const_int
1))]))
3361 ;; G3 = G2 + d2 * H2 in f7
3362 (cond_exec (ne (match_dup
6) (const_int
0))
3363 (parallel [(set (match_dup
7)
3364 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
3366 (use (const_int
1))]))
3368 ;; d3 = a - G3 * G3 in f9
3369 (cond_exec (ne (match_dup
6) (const_int
0))
3370 (parallel [(set (match_dup
4)
3371 (minus:XF (match_dup
8)
3372 (mult:XF (match_dup
7) (match_dup
7))))
3373 (use (const_int
1))]))
3375 ;; S = G3 + d3 * H2 in f7
3376 (cond_exec (ne (match_dup
6) (const_int
0))
3377 (parallel [(set (match_dup
0)
3379 (plus:XF (mult:XF (match_dup
4) (match_dup
3))
3381 (use (const_int
0))]))]
3383 /* Generate
82-bit versions of the input and output operands. */
3384 operands[
7] = gen_rtx_REG (XFmode, REGNO (operands[
0]));
3385 operands[
8] = gen_rtx_REG (XFmode, REGNO (operands[
1]));
3386 /* Generate required floating-point constants. */
3387 operands[
9] = CONST0_RTX (XFmode);
3389 [(set_attr "predicable" "no")])
3391 ;; ::::::::::::::::::::
3393 ;; ::
80 bit floating point arithmetic
3395 ;; ::::::::::::::::::::
3397 (define_insn "addxf3"
3398 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3399 (plus:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3400 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))]
3402 "fadd %
0 = %F1, %F2"
3403 [(set_attr "itanium_class" "fmac")])
3405 (define_insn "*addxf3_truncsf"
3406 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3408 (plus:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3409 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))]
3411 "fadd.s %
0 = %F1, %F2"
3412 [(set_attr "itanium_class" "fmac")])
3414 (define_insn "*addxf3_truncdf"
3415 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3417 (plus:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3418 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))]
3420 "fadd.d %
0 = %F1, %F2"
3421 [(set_attr "itanium_class" "fmac")])
3423 (define_insn "subxf3"
3424 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3425 (minus:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3426 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))]
3428 "fsub %
0 = %F1, %F2"
3429 [(set_attr "itanium_class" "fmac")])
3431 (define_insn "*subxf3_truncsf"
3432 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3434 (minus:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3435 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))]
3437 "fsub.s %
0 = %F1, %F2"
3438 [(set_attr "itanium_class" "fmac")])
3440 (define_insn "*subxf3_truncdf"
3441 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3443 (minus:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3444 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))]
3446 "fsub.d %
0 = %F1, %F2"
3447 [(set_attr "itanium_class" "fmac")])
3449 (define_insn "mulxf3"
3450 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3451 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3452 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))]
3454 "fmpy %
0 = %F1, %F2"
3455 [(set_attr "itanium_class" "fmac")])
3457 (define_insn "*mulxf3_truncsf"
3458 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3460 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3461 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))]
3463 "fmpy.s %
0 = %F1, %F2"
3464 [(set_attr "itanium_class" "fmac")])
3466 (define_insn "*mulxf3_truncdf"
3467 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3469 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3470 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))]
3472 "fmpy.d %
0 = %F1, %F2"
3473 [(set_attr "itanium_class" "fmac")])
3475 (define_insn "*mulxf3_alts"
3476 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3477 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3478 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))
3479 (use (match_operand:SI
3 "const_int_operand" ""))]
3481 "fmpy.s%
3 %
0 = %F1, %F2"
3482 [(set_attr "itanium_class" "fmac")])
3484 (define_insn "*mulxf3_truncsf_alts"
3485 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3487 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3488 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))
3489 (use (match_operand:SI
3 "const_int_operand" ""))]
3491 "fmpy.s.s%
3 %
0 = %F1, %F2"
3492 [(set_attr "itanium_class" "fmac")])
3494 (define_insn "*mulxf3_truncdf_alts"
3495 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3497 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3498 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))
3499 (use (match_operand:SI
3 "const_int_operand" ""))]
3501 "fmpy.d.s%
3 %
0 = %F1, %F2"
3502 [(set_attr "itanium_class" "fmac")])
3504 (define_insn "absxf2"
3505 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3506 (abs:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")))]
3509 [(set_attr "itanium_class" "fmisc")])
3511 (define_insn "negxf2"
3512 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3513 (neg:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")))]
3516 [(set_attr "itanium_class" "fmisc")])
3518 (define_insn "*nabsxf2"
3519 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3520 (neg:XF (abs:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG"))))]
3523 [(set_attr "itanium_class" "fmisc")])
3525 (define_insn "minxf3"
3526 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3527 (smin:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3528 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))]
3530 "fmin %
0 = %F1, %F2"
3531 [(set_attr "itanium_class" "fmisc")])
3533 (define_insn "maxxf3"
3534 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3535 (smax:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3536 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))]
3538 "fmax %
0 = %F1, %F2"
3539 [(set_attr "itanium_class" "fmisc")])
3541 (define_insn "*maddxf4"
3542 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3543 (plus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3544 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3545 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")))]
3547 "fma %
0 = %F1, %F2, %F3"
3548 [(set_attr "itanium_class" "fmac")])
3550 (define_insn "*maddxf4_truncsf"
3551 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3553 (plus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3554 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3555 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG"))))]
3557 "fma.s %
0 = %F1, %F2, %F3"
3558 [(set_attr "itanium_class" "fmac")])
3560 (define_insn "*maddxf4_truncdf"
3561 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3563 (plus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3564 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3565 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG"))))]
3567 "fma.d %
0 = %F1, %F2, %F3"
3568 [(set_attr "itanium_class" "fmac")])
3570 (define_insn "*maddxf4_alts"
3571 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3572 (plus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3573 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3574 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")))
3575 (use (match_operand:SI
4 "const_int_operand" ""))]
3577 "fma.s%
4 %
0 = %F1, %F2, %F3"
3578 [(set_attr "itanium_class" "fmac")])
3580 (define_insn "*maddxf4_alts_truncsf"
3581 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3583 (plus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3584 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3585 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG"))))
3586 (use (match_operand:SI
4 "const_int_operand" ""))]
3588 "fma.s.s%
4 %
0 = %F1, %F2, %F3"
3589 [(set_attr "itanium_class" "fmac")])
3591 (define_insn "*maddxf4_alts_truncdf"
3592 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3594 (plus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3595 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3596 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG"))))
3597 (use (match_operand:SI
4 "const_int_operand" ""))]
3599 "fma.d.s%
4 %
0 = %F1, %F2, %F3"
3600 [(set_attr "itanium_class" "fmac")])
3602 (define_insn "*msubxf4"
3603 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3604 (minus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3605 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3606 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")))]
3608 "fms %
0 = %F1, %F2, %F3"
3609 [(set_attr "itanium_class" "fmac")])
3611 (define_insn "*msubxf4_truncsf"
3612 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3614 (minus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3615 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3616 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG"))))]
3618 "fms.s %
0 = %F1, %F2, %F3"
3619 [(set_attr "itanium_class" "fmac")])
3621 (define_insn "*msubxf4_truncdf"
3622 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3624 (minus:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3625 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))
3626 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG"))))]
3628 "fms.d %
0 = %F1, %F2, %F3"
3629 [(set_attr "itanium_class" "fmac")])
3631 (define_insn "*nmulxf3"
3632 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3633 (neg:XF (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3634 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG"))))]
3636 "fnmpy %
0 = %F1, %F2"
3637 [(set_attr "itanium_class" "fmac")])
3639 (define_insn "*nmulxf3_truncsf"
3640 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3643 (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3644 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))))]
3646 "fnmpy.s %
0 = %F1, %F2"
3647 [(set_attr "itanium_class" "fmac")])
3649 (define_insn "*nmulxf3_truncdf"
3650 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3653 (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3654 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")))))]
3656 "fnmpy.d %
0 = %F1, %F2"
3657 [(set_attr "itanium_class" "fmac")])
3659 (define_insn "*nmaddxf4"
3660 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3661 (minus:XF (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")
3662 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3663 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")
3666 "fnma %
0 = %F1, %F2, %F3"
3667 [(set_attr "itanium_class" "fmac")])
3669 (define_insn "*nmaddxf4_truncsf"
3670 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3672 (minus:XF (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")
3673 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3674 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")
3677 "fnma.s %
0 = %F1, %F2, %F3"
3678 [(set_attr "itanium_class" "fmac")])
3680 (define_insn "*nmaddxf4_truncdf"
3681 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3683 (minus:XF (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")
3684 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3685 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")
3688 "fnma.d %
0 = %F1, %F2, %F3"
3689 [(set_attr "itanium_class" "fmac")])
3691 (define_insn "*nmaddxf4_alts"
3692 [(set (match_operand:XF
0 "fr_register_operand" "=f")
3693 (minus:XF (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")
3694 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3695 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")
3697 (use (match_operand:SI
4 "const_int_operand" ""))]
3699 "fnma.s%
4 %
0 = %F1, %F2, %F3"
3700 [(set_attr "itanium_class" "fmac")])
3702 (define_insn "*nmaddxf4_truncsf_alts"
3703 [(set (match_operand:SF
0 "fr_register_operand" "=f")
3705 (minus:XF (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")
3706 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3707 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")
3709 (use (match_operand:SI
4 "const_int_operand" ""))]
3711 "fnma.s.s%
4 %
0 = %F1, %F2, %F3"
3712 [(set_attr "itanium_class" "fmac")])
3714 (define_insn "*nmaddxf4_truncdf_alts"
3715 [(set (match_operand:DF
0 "fr_register_operand" "=f")
3717 (minus:XF (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")
3718 (mult:XF (match_operand:XF
1 "xfreg_or_fp01_operand" "fG")
3719 (match_operand:XF
2 "xfreg_or_fp01_operand" "fG")
3721 (use (match_operand:SI
4 "const_int_operand" ""))]
3723 "fnma.d.s%
4 %
0 = %F1, %F2, %F3"
3724 [(set_attr "itanium_class" "fmac")])
3726 (define_expand "divxf3"
3727 [(set (match_operand:XF
0 "fr_register_operand" "")
3728 (div:XF (match_operand:XF
1 "fr_register_operand" "")
3729 (match_operand:XF
2 "fr_register_operand" "")))]
3730 "TARGET_INLINE_FLOAT_DIV"
3733 if (TARGET_INLINE_FLOAT_DIV_LAT)
3734 insn = gen_divxf3_internal_lat (operands[
0], operands[
1], operands[
2]);
3736 insn = gen_divxf3_internal_thr (operands[
0], operands[
1], operands[
2]);
3741 (define_insn_and_split "divxf3_internal_lat"
3742 [(set (match_operand:XF
0 "fr_register_operand" "=&f")
3743 (div:XF (match_operand:XF
1 "fr_register_operand" "f")
3744 (match_operand:XF
2 "fr_register_operand" "f")))
3745 (clobber (match_scratch:XF
3 "=&f"))
3746 (clobber (match_scratch:XF
4 "=&f"))
3747 (clobber (match_scratch:XF
5 "=&f"))
3748 (clobber (match_scratch:XF
6 "=&f"))
3749 (clobber (match_scratch:BI
7 "=c"))]
3750 "TARGET_INLINE_FLOAT_DIV_LAT"
3752 "&& reload_completed"
3753 [(parallel [(set (match_dup
0) (div:XF (const_int
1) (match_dup
2)))
3754 (set (match_dup
7) (unspec:BI [(match_dup
1) (match_dup
2)]
3755 UNSPEC_FR_RECIP_APPROX))
3756 (use (const_int
1))])
3757 (cond_exec (ne (match_dup
7) (const_int
0))
3758 (parallel [(set (match_dup
3)
3759 (minus:XF (match_dup
8)
3760 (mult:XF (match_dup
2) (match_dup
0))))
3761 (use (const_int
1))]))
3762 (cond_exec (ne (match_dup
7) (const_int
0))
3763 (parallel [(set (match_dup
4) (mult:XF (match_dup
1) (match_dup
0)))
3764 (use (const_int
1))]))
3765 (cond_exec (ne (match_dup
7) (const_int
0))
3766 (parallel [(set (match_dup
5) (mult:XF (match_dup
3) (match_dup
3)))
3767 (use (const_int
1))]))
3768 (cond_exec (ne (match_dup
7) (const_int
0))
3769 (parallel [(set (match_dup
6)
3770 (plus:XF (mult:XF (match_dup
3) (match_dup
3))
3772 (use (const_int
1))]))
3773 (cond_exec (ne (match_dup
7) (const_int
0))
3774 (parallel [(set (match_dup
3)
3775 (plus:XF (mult:XF (match_dup
5) (match_dup
5))
3777 (use (const_int
1))]))
3778 (cond_exec (ne (match_dup
7) (const_int
0))
3779 (parallel [(set (match_dup
5)
3780 (plus:XF (mult:XF (match_dup
6) (match_dup
0))
3782 (use (const_int
1))]))
3783 (cond_exec (ne (match_dup
7) (const_int
0))
3784 (parallel [(set (match_dup
0)
3785 (plus:XF (mult:XF (match_dup
5) (match_dup
3))
3787 (use (const_int
1))]))
3788 (cond_exec (ne (match_dup
7) (const_int
0))
3789 (parallel [(set (match_dup
4)
3790 (minus:XF (match_dup
1)
3791 (mult:XF (match_dup
2) (match_dup
4))))
3792 (use (const_int
1))]))
3793 (cond_exec (ne (match_dup
7) (const_int
0))
3794 (parallel [(set (match_dup
3)
3795 (plus:XF (mult:XF (match_dup
3) (match_dup
0))
3797 (use (const_int
1))]))
3798 (cond_exec (ne (match_dup
7) (const_int
0))
3799 (parallel [(set (match_dup
5)
3800 (minus:XF (match_dup
8)
3801 (mult:XF (match_dup
2) (match_dup
0))))
3802 (use (const_int
1))]))
3803 (cond_exec (ne (match_dup
7) (const_int
0))
3804 (parallel [(set (match_dup
0)
3805 (plus:XF (mult:XF (match_dup
4) (match_dup
0))
3807 (use (const_int
1))]))
3808 (cond_exec (ne (match_dup
7) (const_int
0))
3809 (parallel [(set (match_dup
4)
3810 (minus:XF (match_dup
1)
3811 (mult:XF (match_dup
2) (match_dup
3))))
3812 (use (const_int
1))]))
3813 (cond_exec (ne (match_dup
7) (const_int
0))
3815 (plus:XF (mult:XF (match_dup
4) (match_dup
0))
3818 "operands[
8] = CONST1_RTX (XFmode);"
3819 [(set_attr "predicable" "no")])
3821 (define_insn_and_split "divxf3_internal_thr"
3822 [(set (match_operand:XF
0 "fr_register_operand" "=&f")
3823 (div:XF (match_operand:XF
1 "fr_register_operand" "f")
3824 (match_operand:XF
2 "fr_register_operand" "f")))
3825 (clobber (match_scratch:XF
3 "=&f"))
3826 (clobber (match_scratch:XF
4 "=&f"))
3827 (clobber (match_scratch:BI
5 "=c"))]
3828 "TARGET_INLINE_FLOAT_DIV_THR"
3830 "&& reload_completed"
3831 [(parallel [(set (match_dup
0) (div:XF (const_int
1) (match_dup
2)))
3832 (set (match_dup
5) (unspec:BI [(match_dup
1) (match_dup
2)]
3833 UNSPEC_FR_RECIP_APPROX))
3834 (use (const_int
1))])
3835 (cond_exec (ne (match_dup
5) (const_int
0))
3836 (parallel [(set (match_dup
3)
3837 (minus:XF (match_dup
6)
3838 (mult:XF (match_dup
2) (match_dup
0))))
3839 (use (const_int
1))]))
3840 (cond_exec (ne (match_dup
5) (const_int
0))
3841 (parallel [(set (match_dup
4)
3842 (plus:XF (mult:XF (match_dup
3) (match_dup
0))
3844 (use (const_int
1))]))
3845 (cond_exec (ne (match_dup
5) (const_int
0))
3846 (parallel [(set (match_dup
3) (mult:XF (match_dup
3) (match_dup
3)))
3847 (use (const_int
1))]))
3848 (cond_exec (ne (match_dup
5) (const_int
0))
3849 (parallel [(set (match_dup
3)
3850 (plus:XF (mult:XF (match_dup
3) (match_dup
4))
3852 (use (const_int
1))]))
3853 (cond_exec (ne (match_dup
5) (const_int
0))
3854 (parallel [(set (match_dup
4) (mult:XF (match_dup
1) (match_dup
0)))
3855 (use (const_int
1))]))
3856 (cond_exec (ne (match_dup
5) (const_int
0))
3857 (parallel [(set (match_dup
0)
3858 (minus:XF (match_dup
6)
3859 (mult:XF (match_dup
2) (match_dup
3))))
3860 (use (const_int
1))]))
3861 (cond_exec (ne (match_dup
5) (const_int
0))
3862 (parallel [(set (match_dup
0)
3863 (plus:XF (mult:XF (match_dup
0) (match_dup
3))
3865 (use (const_int
1))]))
3866 (cond_exec (ne (match_dup
5) (const_int
0))
3867 (parallel [(set (match_dup
3)
3868 (minus:XF (match_dup
1)
3869 (mult:XF (match_dup
2) (match_dup
4))))
3870 (use (const_int
1))]))
3871 (cond_exec (ne (match_dup
5) (const_int
0))
3872 (parallel [(set (match_dup
3)
3873 (plus:XF (mult:XF (match_dup
3) (match_dup
0))
3875 (use (const_int
1))]))
3876 (cond_exec (ne (match_dup
5) (const_int
0))
3877 (parallel [(set (match_dup
4)
3878 (minus:XF (match_dup
6)
3879 (mult:XF (match_dup
2) (match_dup
0))))
3880 (use (const_int
1))]))
3881 (cond_exec (ne (match_dup
5) (const_int
0))
3882 (parallel [(set (match_dup
0)
3883 (plus:XF (mult:XF (match_dup
4) (match_dup
0))
3885 (use (const_int
1))]))
3886 (cond_exec (ne (match_dup
5) (const_int
0))
3887 (parallel [(set (match_dup
4)
3888 (minus:XF (match_dup
1)
3889 (mult:XF (match_dup
2) (match_dup
3))))
3890 (use (const_int
1))]))
3891 (cond_exec (ne (match_dup
5) (const_int
0))
3893 (plus:XF (mult:XF (match_dup
4) (match_dup
0))
3896 "operands[
6] = CONST1_RTX (XFmode);"
3897 [(set_attr "predicable" "no")])
3899 ;; Inline square root.
3901 (define_expand "sqrtxf2"
3902 [(set (match_operand:XF
0 "fr_register_operand" "=&f")
3903 (sqrt:XF (match_operand:XF
1 "fr_register_operand" "f")))]
3904 "TARGET_INLINE_SQRT"
3907 if (TARGET_INLINE_SQRT_LAT)
3909 insn = gen_sqrtxf2_internal_lat (operands[
0], operands[
1]);
3914 insn = gen_sqrtxf2_internal_thr (operands[
0], operands[
1]);
3919 ;; Latency-optimized square root.
3920 ;; FIXME: Implement.
3922 ;; Throughput-optimized square root.
3924 (define_insn_and_split "sqrtxf2_internal_thr"
3925 [(set (match_operand:XF
0 "fr_register_operand" "=&f")
3926 (sqrt:XF (match_operand:XF
1 "fr_register_operand" "f")))
3927 ;; Register r2 in optimization guide.
3928 (clobber (match_scratch:DI
2 "=r"))
3929 ;; Register f8 in optimization guide
3930 (clobber (match_scratch:XF
3 "=&f"))
3931 ;; Register f9 in optimization guide
3932 (clobber (match_scratch:XF
4 "=&f"))
3933 ;; Register f10 in optimization guide
3934 (clobber (match_scratch:XF
5 "=&f"))
3935 ;; Register f11 in optimization guide
3936 (clobber (match_scratch:XF
6 "=&f"))
3937 ;; Register p6 in optimization guide.
3938 (clobber (match_scratch:BI
7 "=c"))]
3939 "TARGET_INLINE_SQRT_THR"
3941 "&& reload_completed"
3942 [ ;; exponent of +
1/
2 in r2
3943 (set (match_dup
2) (const_int
65534))
3944 ;; +
1/
2 in f8. The Intel manual mistakenly specifies f10.
3946 (unspec:XF [(match_dup
2)] UNSPEC_SETF_EXP))
3948 ;; y0 =
1/sqrt(a) in f7
3949 (parallel [(set (match_dup
8)
3950 (div:XF (const_int
1)
3951 (sqrt:XF (match_dup
9))))
3953 (unspec:BI [(match_dup
9)]
3954 UNSPEC_FR_SQRT_RECIP_APPROX))
3955 (use (const_int
0))])
3957 ;; H0 =
1/
2 * y0 in f9
3958 (cond_exec (ne (match_dup
7) (const_int
0))
3959 (parallel [(set (match_dup
4)
3960 (plus:XF (mult:XF (match_dup
3) (match_dup
8))
3962 (use (const_int
1))]))
3964 ;; S0 = a * y0 in f7
3965 (cond_exec (ne (match_dup
7) (const_int
0))
3966 (parallel [(set (match_dup
8)
3967 (plus:XF (mult:XF (match_dup
9) (match_dup
8))
3969 (use (const_int
1))]))
3971 ;; d0 =
1/
2 - S0 * H0 in f10
3972 (cond_exec (ne (match_dup
7) (const_int
0))
3973 (parallel [(set (match_dup
5)
3974 (minus:XF (match_dup
3)
3975 (mult:XF (match_dup
8) (match_dup
4))))
3976 (use (const_int
1))]))
3978 ;; H1 = H0 + d0 * H0 in f9
3979 (cond_exec (ne (match_dup
7) (const_int
0))
3980 (parallel [(set (match_dup
4)
3981 (plus:XF (mult:XF (match_dup
5) (match_dup
4))
3983 (use (const_int
1))]))
3985 ;; S1 = S0 + d0 * S0 in f7
3986 (cond_exec (ne (match_dup
7) (const_int
0))
3987 (parallel [(set (match_dup
8)
3988 (plus:XF (mult:XF (match_dup
5) (match_dup
8))
3990 (use (const_int
1))]))
3992 ;; d1 =
1/
2 - S1 * H1 in f10
3993 (cond_exec (ne (match_dup
7) (const_int
0))
3994 (parallel [(set (match_dup
5)
3995 (minus:XF (match_dup
3)
3996 (mult:XF (match_dup
8) (match_dup
4))))
3997 (use (const_int
1))]))
3999 ;; H2 = H1 + d1 * H1 in f9
4000 (cond_exec (ne (match_dup
7) (const_int
0))
4001 (parallel [(set (match_dup
4)
4002 (plus:XF (mult:XF (match_dup
5) (match_dup
4))
4004 (use (const_int
1))]))
4006 ;; S2 = S1 + d1 * S1 in f7
4007 (cond_exec (ne (match_dup
7) (const_int
0))
4008 (parallel [(set (match_dup
8)
4009 (plus:XF (mult:XF (match_dup
5) (match_dup
8))
4011 (use (const_int
1))]))
4013 ;; d2 =
1/
2 - S2 * H2 in f10
4014 (cond_exec (ne (match_dup
7) (const_int
0))
4015 (parallel [(set (match_dup
5)
4016 (minus:XF (match_dup
3)
4017 (mult:XF (match_dup
8) (match_dup
4))))
4018 (use (const_int
1))]))
4020 ;; e2 = a - S2 * S2 in f8
4021 (cond_exec (ne (match_dup
7) (const_int
0))
4022 (parallel [(set (match_dup
3)
4023 (minus:XF (match_dup
9)
4024 (mult:XF (match_dup
8) (match_dup
8))))
4025 (use (const_int
1))]))
4027 ;; S3 = S2 + e2 * H2 in f7
4028 (cond_exec (ne (match_dup
7) (const_int
0))
4029 (parallel [(set (match_dup
8)
4030 (plus:XF (mult:XF (match_dup
3) (match_dup
4))
4032 (use (const_int
1))]))
4034 ;; H3 = H2 + d2 * H2 in f9
4035 (cond_exec (ne (match_dup
7) (const_int
0))
4036 (parallel [(set (match_dup
4)
4037 (plus:XF (mult:XF (match_dup
5) (match_dup
4))
4039 (use (const_int
1))]))
4041 ;; e3 = a - S3 * S3 in f8
4042 (cond_exec (ne (match_dup
7) (const_int
0))
4043 (parallel [(set (match_dup
3)
4044 (minus:XF (match_dup
9)
4045 (mult:XF (match_dup
8) (match_dup
8))))
4046 (use (const_int
1))]))
4048 ;; S = S3 + e3 * H3 in f7
4049 (cond_exec (ne (match_dup
7) (const_int
0))
4050 (parallel [(set (match_dup
0)
4051 (plus:XF (mult:XF (match_dup
3) (match_dup
4))
4053 (use (const_int
0))]))]
4055 /* Generate
82-bit versions of the input and output operands. */
4056 operands[
8] = gen_rtx_REG (XFmode, REGNO (operands[
0]));
4057 operands[
9] = gen_rtx_REG (XFmode, REGNO (operands[
1]));
4058 /* Generate required floating-point constants. */
4059 operands[
10] = CONST0_RTX (XFmode);
4061 [(set_attr "predicable" "no")])
4063 ;; ??? frcpa works like cmp.foo.unc.
4065 (define_insn "*recip_approx"
4066 [(set (match_operand:XF
0 "fr_register_operand" "=f")
4067 (div:XF (const_int
1)
4068 (match_operand:XF
3 "fr_register_operand" "f")))
4069 (set (match_operand:BI
1 "register_operand" "=c")
4070 (unspec:BI [(match_operand:XF
2 "fr_register_operand" "f")
4071 (match_dup
3)] UNSPEC_FR_RECIP_APPROX))
4072 (use (match_operand:SI
4 "const_int_operand" ""))]
4074 "frcpa.s%
4 %
0, %
1 = %
2, %
3"
4075 [(set_attr "itanium_class" "fmisc")
4076 (set_attr "predicable" "no")])
4078 ;; ::::::::::::::::::::
4080 ;; ::
32 bit Integer Shifts and Rotates
4082 ;; ::::::::::::::::::::
4084 (define_expand "ashlsi3"
4085 [(set (match_operand:SI
0 "gr_register_operand" "")
4086 (ashift:SI (match_operand:SI
1 "gr_register_operand" "")
4087 (match_operand:SI
2 "gr_reg_or_5bit_operand" "")))]
4090 if (GET_CODE (operands[
2]) != CONST_INT)
4092 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
4093 we've got to get rid of stray bits outside the SImode register. */
4094 rtx subshift = gen_reg_rtx (DImode);
4095 emit_insn (gen_zero_extendsidi2 (subshift, operands[
2]));
4096 operands[
2] = subshift;
4100 (define_insn "*ashlsi3_internal"
4101 [(set (match_operand:SI
0 "gr_register_operand" "=r,r,r")
4102 (ashift:SI (match_operand:SI
1 "gr_register_operand" "r,r,r")
4103 (match_operand:DI
2 "gr_reg_or_5bit_operand" "R,n,r")))]
4106 shladd %
0 = %
1, %
2, r0
4107 dep.z %
0 = %
1, %
2, %E2
4109 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
4111 (define_expand "ashrsi3"
4112 [(set (match_operand:SI
0 "gr_register_operand" "")
4113 (ashiftrt:SI (match_operand:SI
1 "gr_register_operand" "")
4114 (match_operand:SI
2 "gr_reg_or_5bit_operand" "")))]
4117 rtx subtarget = gen_reg_rtx (DImode);
4118 if (GET_CODE (operands[
2]) == CONST_INT)
4119 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[
1]),
4120 GEN_INT (
32 - INTVAL (operands[
2])), operands[
2]));
4123 rtx subshift = gen_reg_rtx (DImode);
4124 emit_insn (gen_extendsidi2 (subtarget, operands[
1]));
4125 emit_insn (gen_zero_extendsidi2 (subshift, operands[
2]));
4126 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
4128 emit_move_insn (gen_lowpart (DImode, operands[
0]), subtarget);
4132 (define_expand "lshrsi3"
4133 [(set (match_operand:SI
0 "gr_register_operand" "")
4134 (lshiftrt:SI (match_operand:SI
1 "gr_register_operand" "")
4135 (match_operand:SI
2 "gr_reg_or_5bit_operand" "")))]
4138 rtx subtarget = gen_reg_rtx (DImode);
4139 if (GET_CODE (operands[
2]) == CONST_INT)
4140 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[
1]),
4141 GEN_INT (
32 - INTVAL (operands[
2])), operands[
2]));
4144 rtx subshift = gen_reg_rtx (DImode);
4145 emit_insn (gen_zero_extendsidi2 (subtarget, operands[
1]));
4146 emit_insn (gen_zero_extendsidi2 (subshift, operands[
2]));
4147 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
4149 emit_move_insn (gen_lowpart (DImode, operands[
0]), subtarget);
4153 ;; Use mix4.r/shr to implement rotrsi3. We only get
32 bits of valid result
4154 ;; here, instead of
64 like the patterns above. Keep the pattern together
4155 ;; until after combine; otherwise it won't get matched often.
4157 (define_expand "rotrsi3"
4158 [(set (match_operand:SI
0 "gr_register_operand" "")
4159 (rotatert:SI (match_operand:SI
1 "gr_register_operand" "")
4160 (match_operand:SI
2 "gr_reg_or_5bit_operand" "")))]
4163 if (GET_MODE (operands[
2]) != VOIDmode)
4165 rtx tmp = gen_reg_rtx (DImode);
4166 emit_insn (gen_zero_extendsidi2 (tmp, operands[
2]));
4171 (define_insn_and_split "*rotrsi3_internal"
4172 [(set (match_operand:SI
0 "gr_register_operand" "=&r")
4173 (rotatert:SI (match_operand:SI
1 "gr_register_operand" "r")
4174 (match_operand:DI
2 "gr_reg_or_5bit_operand" "rM")))]
4179 (ior:DI (zero_extend:DI (match_dup
1))
4180 (ashift:DI (zero_extend:DI (match_dup
1)) (const_int
32))))
4182 (lshiftrt:DI (match_dup
3) (match_dup
2)))]
4183 "operands[
3] = gen_rtx_REG (DImode, REGNO (operands[
0]));")
4185 (define_expand "rotlsi3"
4186 [(set (match_operand:SI
0 "gr_register_operand" "")
4187 (rotate:SI (match_operand:SI
1 "gr_register_operand" "")
4188 (match_operand:SI
2 "gr_reg_or_5bit_operand" "")))]
4191 if (! shift_32bit_count_operand (operands[
2], SImode))
4193 rtx tmp = gen_reg_rtx (SImode);
4194 emit_insn (gen_subsi3 (tmp, GEN_INT (
32), operands[
2]));
4195 emit_insn (gen_rotrsi3 (operands[
0], operands[
1], tmp));
4200 (define_insn_and_split "*rotlsi3_internal"
4201 [(set (match_operand:SI
0 "gr_register_operand" "=r")
4202 (rotate:SI (match_operand:SI
1 "gr_register_operand" "r")
4203 (match_operand:SI
2 "shift_32bit_count_operand" "n")))]
4208 (ior:DI (zero_extend:DI (match_dup
1))
4209 (ashift:DI (zero_extend:DI (match_dup
1)) (const_int
32))))
4211 (lshiftrt:DI (match_dup
3) (match_dup
2)))]
4213 operands[
3] = gen_rtx_REG (DImode, REGNO (operands[
0]));
4214 operands[
2] = GEN_INT (
32 - INTVAL (operands[
2]));
4217 ;; ::::::::::::::::::::
4219 ;; ::
64 bit Integer Shifts and Rotates
4221 ;; ::::::::::::::::::::
4223 (define_insn "ashldi3"
4224 [(set (match_operand:DI
0 "gr_register_operand" "=r,r,r")
4225 (ashift:DI (match_operand:DI
1 "gr_register_operand" "r,r,r")
4226 (match_operand:DI
2 "gr_reg_or_6bit_operand" "R,r,rM")))]
4229 shladd %
0 = %
1, %
2, r0
4232 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
4234 ;; ??? Maybe combine this with the multiply and add instruction?
4236 (define_insn "*shladd"
4237 [(set (match_operand:DI
0 "gr_register_operand" "=r")
4238 (plus:DI (mult:DI (match_operand:DI
1 "gr_register_operand" "r")
4239 (match_operand:DI
2 "shladd_operand" "n"))
4240 (match_operand:DI
3 "gr_register_operand" "r")))]
4242 "shladd %
0 = %
1, %S2, %
3"
4243 [(set_attr "itanium_class" "ialu")])
4245 ;; This can be created by register elimination if operand3 of shladd is an
4246 ;; eliminable register or has reg_equiv_constant set.
4248 ;; We have to use nonmemory_operand for operand
4, to ensure that the
4249 ;; validate_changes call inside eliminate_regs will always succeed. If it
4250 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
4253 (define_insn_and_split "*shladd_elim"
4254 [(set (match_operand:DI
0 "gr_register_operand" "=&r")
4255 (plus:DI (plus:DI (mult:DI (match_operand:DI
1 "gr_register_operand" "r")
4256 (match_operand:DI
2 "shladd_operand" "n"))
4257 (match_operand:DI
3 "nonmemory_operand" "r"))
4258 (match_operand:DI
4 "nonmemory_operand" "rI")))]
4259 "reload_in_progress"
4262 [(set (match_dup
0) (plus:DI (mult:DI (match_dup
1) (match_dup
2))
4264 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
4)))]
4266 [(set_attr "itanium_class" "unknown")])
4268 (define_insn "ashrdi3"
4269 [(set (match_operand:DI
0 "gr_register_operand" "=r,r")
4270 (ashiftrt:DI (match_operand:DI
1 "gr_register_operand" "r,r")
4271 (match_operand:DI
2 "gr_reg_or_6bit_operand" "r,rM")))]
4276 [(set_attr "itanium_class" "mmshf,mmshfi")])
4278 (define_insn "lshrdi3"
4279 [(set (match_operand:DI
0 "gr_register_operand" "=r,r")
4280 (lshiftrt:DI (match_operand:DI
1 "gr_register_operand" "r,r")
4281 (match_operand:DI
2 "gr_reg_or_6bit_operand" "r,rM")))]
4286 [(set_attr "itanium_class" "mmshf,mmshfi")])
4288 ;; Using a predicate that accepts only constants doesn't work, because optabs
4289 ;; will load the operand into a register and call the pattern if the predicate
4290 ;; did not accept it on the first try. So we use nonmemory_operand and then
4291 ;; verify that we have an appropriate constant in the expander.
4293 (define_expand "rotrdi3"
4294 [(set (match_operand:DI
0 "gr_register_operand" "")
4295 (rotatert:DI (match_operand:DI
1 "gr_register_operand" "")
4296 (match_operand:DI
2 "nonmemory_operand" "")))]
4299 if (! shift_count_operand (operands[
2], DImode))
4303 (define_insn "*rotrdi3_internal"
4304 [(set (match_operand:DI
0 "gr_register_operand" "=r")
4305 (rotatert:DI (match_operand:DI
1 "gr_register_operand" "r")
4306 (match_operand:DI
2 "shift_count_operand" "M")))]
4308 "shrp %
0 = %
1, %
1, %
2"
4309 [(set_attr "itanium_class" "ishf")])
4311 (define_expand "rotldi3"
4312 [(set (match_operand:DI
0 "gr_register_operand" "")
4313 (rotate:DI (match_operand:DI
1 "gr_register_operand" "")
4314 (match_operand:DI
2 "nonmemory_operand" "")))]
4317 if (! shift_count_operand (operands[
2], DImode))
4321 (define_insn "*rotldi3_internal"
4322 [(set (match_operand:DI
0 "gr_register_operand" "=r")
4323 (rotate:DI (match_operand:DI
1 "gr_register_operand" "r")
4324 (match_operand:DI
2 "shift_count_operand" "M")))]
4326 "shrp %
0 = %
1, %
1, %e2"
4327 [(set_attr "itanium_class" "ishf")])
4329 ;; ::::::::::::::::::::
4331 ;; ::
32 bit Integer Logical operations
4333 ;; ::::::::::::::::::::
4335 ;; We don't seem to need any other
32-bit logical operations, because gcc
4336 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
4337 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
4338 ;; This doesn't work for unary logical operations, because we don't call
4339 ;; apply_distributive_law for them.
4341 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
4342 ;; apply_distributive_law. We get inefficient code for
4343 ;; int sub4 (int i, int j) { return i & ~j; }
4344 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
4345 ;; (zero_extend (and (not A) B)) in combine.
4346 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
4347 ;; one_cmplsi2 pattern.
4349 (define_insn "one_cmplsi2"
4350 [(set (match_operand:SI
0 "gr_register_operand" "=r")
4351 (not:SI (match_operand:SI
1 "gr_register_operand" "r")))]
4354 [(set_attr "itanium_class" "ilog")])
4356 ;; ::::::::::::::::::::
4358 ;; ::
64 bit Integer Logical operations
4360 ;; ::::::::::::::::::::
4362 (define_insn "anddi3"
4363 [(set (match_operand:DI
0 "grfr_register_operand" "=r,*f")
4364 (and:DI (match_operand:DI
1 "grfr_register_operand" "%r,*f")
4365 (match_operand:DI
2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4370 [(set_attr "itanium_class" "ilog,fmisc")])
4372 (define_insn "*andnot"
4373 [(set (match_operand:DI
0 "grfr_register_operand" "=r,*f")
4374 (and:DI (not:DI (match_operand:DI
1 "grfr_register_operand" "r,*f"))
4375 (match_operand:DI
2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4380 [(set_attr "itanium_class" "ilog,fmisc")])
4382 (define_insn "iordi3"
4383 [(set (match_operand:DI
0 "grfr_register_operand" "=r,*f")
4384 (ior:DI (match_operand:DI
1 "grfr_register_operand" "%r,*f")
4385 (match_operand:DI
2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4390 [(set_attr "itanium_class" "ilog,fmisc")])
4392 (define_insn "xordi3"
4393 [(set (match_operand:DI
0 "grfr_register_operand" "=r,*f")
4394 (xor:DI (match_operand:DI
1 "grfr_register_operand" "%r,*f")
4395 (match_operand:DI
2 "grfr_reg_or_8bit_operand" "rK,*f")))]
4400 [(set_attr "itanium_class" "ilog,fmisc")])
4402 (define_insn "one_cmpldi2"
4403 [(set (match_operand:DI
0 "gr_register_operand" "=r")
4404 (not:DI (match_operand:DI
1 "gr_register_operand" "r")))]
4407 [(set_attr "itanium_class" "ilog")])
4409 ;; ::::::::::::::::::::
4413 ;; ::::::::::::::::::::
4415 (define_expand "cmpbi"
4417 (compare (match_operand:BI
0 "register_operand" "")
4418 (match_operand:BI
1 "const_int_operand" "")))]
4421 ia64_compare_op0 = operands[
0];
4422 ia64_compare_op1 = operands[
1];
4426 (define_expand "cmpsi"
4428 (compare (match_operand:SI
0 "gr_register_operand" "")
4429 (match_operand:SI
1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4432 ia64_compare_op0 = operands[
0];
4433 ia64_compare_op1 = operands[
1];
4437 (define_expand "cmpdi"
4439 (compare (match_operand:DI
0 "gr_register_operand" "")
4440 (match_operand:DI
1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
4443 ia64_compare_op0 = operands[
0];
4444 ia64_compare_op1 = operands[
1];
4448 (define_expand "cmpsf"
4450 (compare (match_operand:SF
0 "fr_reg_or_fp01_operand" "")
4451 (match_operand:SF
1 "fr_reg_or_fp01_operand" "")))]
4454 ia64_compare_op0 = operands[
0];
4455 ia64_compare_op1 = operands[
1];
4459 (define_expand "cmpdf"
4461 (compare (match_operand:DF
0 "fr_reg_or_fp01_operand" "")
4462 (match_operand:DF
1 "fr_reg_or_fp01_operand" "")))]
4465 ia64_compare_op0 = operands[
0];
4466 ia64_compare_op1 = operands[
1];
4470 (define_expand "cmpxf"
4472 (compare (match_operand:XF
0 "xfreg_or_fp01_operand" "")
4473 (match_operand:XF
1 "xfreg_or_fp01_operand" "")))]
4476 ia64_compare_op0 = operands[
0];
4477 ia64_compare_op1 = operands[
1];
4481 (define_expand "cmptf"
4483 (compare (match_operand:TF
0 "gr_register_operand" "")
4484 (match_operand:TF
1 "gr_register_operand" "")))]
4487 ia64_compare_op0 = operands[
0];
4488 ia64_compare_op1 = operands[
1];
4492 (define_insn "*cmpsi_normal"
4493 [(set (match_operand:BI
0 "register_operand" "=c")
4494 (match_operator:BI
1 "normal_comparison_operator"
4495 [(match_operand:SI
2 "gr_register_operand" "r")
4496 (match_operand:SI
3 "gr_reg_or_8bit_operand" "rK")]))]
4498 "cmp4.%C1 %
0, %I0 = %
3, %
2"
4499 [(set_attr "itanium_class" "icmp")])
4501 ;; We use %r3 because it is possible for us to match a
0, and two of the
4502 ;; unsigned comparisons don't accept immediate operands of zero.
4504 (define_insn "*cmpsi_adjusted"
4505 [(set (match_operand:BI
0 "register_operand" "=c")
4506 (match_operator:BI
1 "adjusted_comparison_operator"
4507 [(match_operand:SI
2 "gr_register_operand" "r")
4508 (match_operand:SI
3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4510 "cmp4.%C1 %
0, %I0 = %r3, %
2"
4511 [(set_attr "itanium_class" "icmp")])
4513 (define_insn "*cmpdi_normal"
4514 [(set (match_operand:BI
0 "register_operand" "=c")
4515 (match_operator:BI
1 "normal_comparison_operator"
4516 [(match_operand:DI
2 "gr_reg_or_0_operand" "rO")
4517 (match_operand:DI
3 "gr_reg_or_8bit_operand" "rK")]))]
4519 "cmp.%C1 %
0, %I0 = %
3, %r2"
4520 [(set_attr "itanium_class" "icmp")])
4522 ;; We use %r3 because it is possible for us to match a
0, and two of the
4523 ;; unsigned comparisons don't accept immediate operands of zero.
4525 (define_insn "*cmpdi_adjusted"
4526 [(set (match_operand:BI
0 "register_operand" "=c")
4527 (match_operator:BI
1 "adjusted_comparison_operator"
4528 [(match_operand:DI
2 "gr_register_operand" "r")
4529 (match_operand:DI
3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
4531 "cmp.%C1 %
0, %I0 = %r3, %
2"
4532 [(set_attr "itanium_class" "icmp")])
4534 (define_insn "*cmpsf_internal"
4535 [(set (match_operand:BI
0 "register_operand" "=c")
4536 (match_operator:BI
1 "comparison_operator"
4537 [(match_operand:SF
2 "fr_reg_or_fp01_operand" "fG")
4538 (match_operand:SF
3 "fr_reg_or_fp01_operand" "fG")]))]
4540 "fcmp.%D1 %
0, %I0 = %F2, %F3"
4541 [(set_attr "itanium_class" "fcmp")])
4543 (define_insn "*cmpdf_internal"
4544 [(set (match_operand:BI
0 "register_operand" "=c")
4545 (match_operator:BI
1 "comparison_operator"
4546 [(match_operand:DF
2 "fr_reg_or_fp01_operand" "fG")
4547 (match_operand:DF
3 "fr_reg_or_fp01_operand" "fG")]))]
4549 "fcmp.%D1 %
0, %I0 = %F2, %F3"
4550 [(set_attr "itanium_class" "fcmp")])
4552 (define_insn "*cmpxf_internal"
4553 [(set (match_operand:BI
0 "register_operand" "=c")
4554 (match_operator:BI
1 "comparison_operator"
4555 [(match_operand:XF
2 "xfreg_or_fp01_operand" "fG")
4556 (match_operand:XF
3 "xfreg_or_fp01_operand" "fG")]))]
4558 "fcmp.%D1 %
0, %I0 = %F2, %F3"
4559 [(set_attr "itanium_class" "fcmp")])
4561 ;; ??? Can this pattern be generated?
4563 (define_insn "*bit_zero"
4564 [(set (match_operand:BI
0 "register_operand" "=c")
4565 (eq:BI (zero_extract:DI (match_operand:DI
1 "gr_register_operand" "r")
4567 (match_operand:DI
2 "immediate_operand" "n"))
4570 "tbit.z %
0, %I0 = %
1, %
2"
4571 [(set_attr "itanium_class" "tbit")])
4573 (define_insn "*bit_one"
4574 [(set (match_operand:BI
0 "register_operand" "=c")
4575 (ne:BI (zero_extract:DI (match_operand:DI
1 "gr_register_operand" "r")
4577 (match_operand:DI
2 "immediate_operand" "n"))
4580 "tbit.nz %
0, %I0 = %
1, %
2"
4581 [(set_attr "itanium_class" "tbit")])
4583 ;; ::::::::::::::::::::
4587 ;; ::::::::::::::::::::
4589 (define_expand "beq"
4591 (if_then_else (match_dup
1)
4592 (label_ref (match_operand
0 "" ""))
4595 "operands[
1] = ia64_expand_compare (EQ, VOIDmode);")
4597 (define_expand "bne"
4599 (if_then_else (match_dup
1)
4600 (label_ref (match_operand
0 "" ""))
4603 "operands[
1] = ia64_expand_compare (NE, VOIDmode);")
4605 (define_expand "blt"
4607 (if_then_else (match_dup
1)
4608 (label_ref (match_operand
0 "" ""))
4611 "operands[
1] = ia64_expand_compare (LT, VOIDmode);")
4613 (define_expand "ble"
4615 (if_then_else (match_dup
1)
4616 (label_ref (match_operand
0 "" ""))
4619 "operands[
1] = ia64_expand_compare (LE, VOIDmode);")
4621 (define_expand "bgt"
4623 (if_then_else (match_dup
1)
4624 (label_ref (match_operand
0 "" ""))
4627 "operands[
1] = ia64_expand_compare (GT, VOIDmode);")
4629 (define_expand "bge"
4631 (if_then_else (match_dup
1)
4632 (label_ref (match_operand
0 "" ""))
4635 "operands[
1] = ia64_expand_compare (GE, VOIDmode);")
4637 (define_expand "bltu"
4639 (if_then_else (match_dup
1)
4640 (label_ref (match_operand
0 "" ""))
4643 "operands[
1] = ia64_expand_compare (LTU, VOIDmode);")
4645 (define_expand "bleu"
4647 (if_then_else (match_dup
1)
4648 (label_ref (match_operand
0 "" ""))
4651 "operands[
1] = ia64_expand_compare (LEU, VOIDmode);")
4653 (define_expand "bgtu"
4655 (if_then_else (match_dup
1)
4656 (label_ref (match_operand
0 "" ""))
4659 "operands[
1] = ia64_expand_compare (GTU, VOIDmode);")
4661 (define_expand "bgeu"
4663 (if_then_else (match_dup
1)
4664 (label_ref (match_operand
0 "" ""))
4667 "operands[
1] = ia64_expand_compare (GEU, VOIDmode);")
4669 (define_expand "bunordered"
4671 (if_then_else (match_dup
1)
4672 (label_ref (match_operand
0 "" ""))
4675 "operands[
1] = ia64_expand_compare (UNORDERED, VOIDmode);")
4677 (define_expand "bordered"
4679 (if_then_else (match_dup
1)
4680 (label_ref (match_operand
0 "" ""))
4683 "operands[
1] = ia64_expand_compare (ORDERED, VOIDmode);")
4685 (define_insn "*br_true"
4687 (if_then_else (match_operator
0 "predicate_operator"
4688 [(match_operand:BI
1 "register_operand" "c")
4690 (label_ref (match_operand
2 "" ""))
4693 "(%J0) br.cond%+ %l2"
4694 [(set_attr "itanium_class" "br")
4695 (set_attr "predicable" "no")])
4697 (define_insn "*br_false"
4699 (if_then_else (match_operator
0 "predicate_operator"
4700 [(match_operand:BI
1 "register_operand" "c")
4703 (label_ref (match_operand
2 "" ""))))]
4705 "(%j0) br.cond%+ %l2"
4706 [(set_attr "itanium_class" "br")
4707 (set_attr "predicable" "no")])
4709 ;; ::::::::::::::::::::
4711 ;; :: Counted loop operations
4713 ;; ::::::::::::::::::::
4715 (define_expand "doloop_end"
4716 [(use (match_operand
0 "" "")) ; loop pseudo
4717 (use (match_operand
1 "" "")) ; iterations; zero if unknown
4718 (use (match_operand
2 "" "")) ; max iterations
4719 (use (match_operand
3 "" "")) ; loop level
4720 (use (match_operand
4 "" ""))] ; label
4723 /* Only use cloop on innermost loops. */
4724 if (INTVAL (operands[
3]) >
1)
4726 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
4731 (define_insn "doloop_end_internal"
4732 [(set (pc) (if_then_else (ne (match_operand:DI
0 "ar_lc_reg_operand" "")
4734 (label_ref (match_operand
1 "" ""))
4736 (set (match_dup
0) (if_then_else:DI (ne (match_dup
0) (const_int
0))
4737 (plus:DI (match_dup
0) (const_int -
1))
4740 "br.cloop.sptk.few %l1"
4741 [(set_attr "itanium_class" "br")
4742 (set_attr "predicable" "no")])
4744 ;; ::::::::::::::::::::
4746 ;; :: Set flag operations
4748 ;; ::::::::::::::::::::
4750 (define_expand "seq"
4751 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4753 "operands[
1] = ia64_expand_compare (EQ, DImode);")
4755 (define_expand "sne"
4756 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4758 "operands[
1] = ia64_expand_compare (NE, DImode);")
4760 (define_expand "slt"
4761 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4763 "operands[
1] = ia64_expand_compare (LT, DImode);")
4765 (define_expand "sle"
4766 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4768 "operands[
1] = ia64_expand_compare (LE, DImode);")
4770 (define_expand "sgt"
4771 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4773 "operands[
1] = ia64_expand_compare (GT, DImode);")
4775 (define_expand "sge"
4776 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4778 "operands[
1] = ia64_expand_compare (GE, DImode);")
4780 (define_expand "sltu"
4781 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4783 "operands[
1] = ia64_expand_compare (LTU, DImode);")
4785 (define_expand "sleu"
4786 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4788 "operands[
1] = ia64_expand_compare (LEU, DImode);")
4790 (define_expand "sgtu"
4791 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4793 "operands[
1] = ia64_expand_compare (GTU, DImode);")
4795 (define_expand "sgeu"
4796 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4798 "operands[
1] = ia64_expand_compare (GEU, DImode);")
4800 (define_expand "sunordered"
4801 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4803 "operands[
1] = ia64_expand_compare (UNORDERED, DImode);")
4805 (define_expand "sordered"
4806 [(set (match_operand:DI
0 "gr_register_operand" "") (match_dup
1))]
4808 "operands[
1] = ia64_expand_compare (ORDERED, DImode);")
4810 ;; Don't allow memory as destination here, because cmov/cmov/st is more
4811 ;; efficient than mov/mov/cst/cst.
4813 (define_insn_and_split "*sne_internal"
4814 [(set (match_operand:DI
0 "gr_register_operand" "=r")
4815 (ne:DI (match_operand:BI
1 "register_operand" "c")
4820 [(cond_exec (ne (match_dup
1) (const_int
0))
4821 (set (match_dup
0) (const_int
1)))
4822 (cond_exec (eq (match_dup
1) (const_int
0))
4823 (set (match_dup
0) (const_int
0)))]
4825 [(set_attr "itanium_class" "unknown")])
4827 (define_insn_and_split "*seq_internal"
4828 [(set (match_operand:DI
0 "gr_register_operand" "=r")
4829 (eq:DI (match_operand:BI
1 "register_operand" "c")
4834 [(cond_exec (ne (match_dup
1) (const_int
0))
4835 (set (match_dup
0) (const_int
0)))
4836 (cond_exec (eq (match_dup
1) (const_int
0))
4837 (set (match_dup
0) (const_int
1)))]
4839 [(set_attr "itanium_class" "unknown")])
4841 ;; ::::::::::::::::::::
4843 ;; :: Conditional move instructions.
4845 ;; ::::::::::::::::::::
4847 ;; ??? Add movXXcc patterns?
4850 ;; DImode if_then_else patterns.
4853 (define_insn "*cmovdi_internal"
4854 [(set (match_operand:DI
0 "destination_operand"
4855 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
4857 (match_operator
4 "predicate_operator"
4858 [(match_operand:BI
1 "register_operand"
4859 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
4861 (match_operand:DI
2 "move_operand"
4862 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
4863 (match_operand:DI
3 "move_operand"
4864 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
4865 "ia64_move_ok (operands[
0], operands[
2])
4866 && ia64_move_ok (operands[
0], operands[
3])"
4868 [(set_attr "predicable" "no")])
4871 [(set (match_operand
0 "destination_operand" "")
4873 (match_operator
4 "predicate_operator"
4874 [(match_operand:BI
1 "register_operand" "")
4876 (match_operand
2 "move_operand" "")
4877 (match_operand
3 "move_operand" "")))]
4881 bool emitted_something = false;
4882 rtx dest = operands[
0];
4883 rtx srct = operands[
2];
4884 rtx srcf = operands[
3];
4885 rtx cond = operands[
4];
4887 if (! rtx_equal_p (dest, srct))
4889 ia64_emit_cond_move (dest, srct, cond);
4890 emitted_something = true;
4892 if (! rtx_equal_p (dest, srcf))
4894 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
4895 VOIDmode, operands[
1], const0_rtx);
4896 ia64_emit_cond_move (dest, srcf, cond);
4897 emitted_something = true;
4899 if (! emitted_something)
4900 emit_note (NOTE_INSN_DELETED);
4904 ;; Absolute value pattern.
4906 (define_insn "*absdi2_internal"
4907 [(set (match_operand:DI
0 "gr_register_operand" "=r,r")
4909 (match_operator
4 "predicate_operator"
4910 [(match_operand:BI
1 "register_operand" "c,c")
4912 (neg:DI (match_operand:DI
2 "gr_reg_or_22bit_operand" "rI,rI"))
4913 (match_operand:DI
3 "gr_reg_or_22bit_operand" "
0,rI")))]
4916 [(set_attr "itanium_class" "ialu,unknown")
4917 (set_attr "predicable" "no")])
4920 [(set (match_operand:DI
0 "register_operand" "")
4922 (match_operator
4 "predicate_operator"
4923 [(match_operand:BI
1 "register_operand" "c,c")
4925 (neg:DI (match_operand:DI
2 "gr_reg_or_22bit_operand" ""))
4926 (match_operand:DI
3 "gr_reg_or_22bit_operand" "")))]
4927 "reload_completed && rtx_equal_p (operands[
0], operands[
3])"
4931 (neg:DI (match_dup
2))))]
4935 [(set (match_operand:DI
0 "register_operand" "")
4937 (match_operator
4 "predicate_operator"
4938 [(match_operand:BI
1 "register_operand" "c,c")
4940 (neg:DI (match_operand:DI
2 "gr_reg_or_22bit_operand" ""))
4941 (match_operand:DI
3 "gr_reg_or_22bit_operand" "")))]
4945 (set (match_dup
0) (neg:DI (match_dup
2))))
4948 (set (match_dup
0) (match_dup
3)))]
4950 operands[
5] = gen_rtx_fmt_ee (GET_CODE (operands[
4]) == NE ? EQ : NE,
4951 VOIDmode, operands[
1], const0_rtx);
4955 ;; SImode if_then_else patterns.
4958 (define_insn "*cmovsi_internal"
4959 [(set (match_operand:SI
0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f")
4961 (match_operator
4 "predicate_operator"
4962 [(match_operand:BI
1 "register_operand" "c,c,c,c,c,c,c,c,c")
4964 (match_operand:SI
2 "move_operand"
4965 "
0,
0,
0,rim*f,rO,rO,rim*f,rO,rO")
4966 (match_operand:SI
3 "move_operand"
4967 "rim*f,rO,rO,
0,
0,
0,rim*f,rO,rO")))]
4968 "ia64_move_ok (operands[
0], operands[
2])
4969 && ia64_move_ok (operands[
0], operands[
3])"
4971 [(set_attr "predicable" "no")])
4973 (define_insn "*abssi2_internal"
4974 [(set (match_operand:SI
0 "gr_register_operand" "=r,r")
4976 (match_operator
4 "predicate_operator"
4977 [(match_operand:BI
1 "register_operand" "c,c")
4979 (neg:SI (match_operand:SI
3 "gr_reg_or_22bit_operand" "rI,rI"))
4980 (match_operand:SI
2 "gr_reg_or_22bit_operand" "
0,rI")))]
4983 [(set_attr "itanium_class" "ialu,unknown")
4984 (set_attr "predicable" "no")])
4987 [(set (match_operand:SI
0 "register_operand" "")
4989 (match_operator
4 "predicate_operator"
4990 [(match_operand:BI
1 "register_operand" "c,c")
4992 (neg:SI (match_operand:SI
2 "gr_reg_or_22bit_operand" ""))
4993 (match_operand:SI
3 "gr_reg_or_22bit_operand" "")))]
4994 "reload_completed && rtx_equal_p (operands[
0], operands[
3])"
4998 (neg:SI (match_dup
2))))]
5002 [(set (match_operand:SI
0 "register_operand" "")
5004 (match_operator
4 "predicate_operator"
5005 [(match_operand:BI
1 "register_operand" "c,c")
5007 (neg:SI (match_operand:SI
2 "gr_reg_or_22bit_operand" ""))
5008 (match_operand:SI
3 "gr_reg_or_22bit_operand" "")))]
5012 (set (match_dup
0) (neg:SI (match_dup
2))))
5015 (set (match_dup
0) (match_dup
3)))]
5017 operands[
5] = gen_rtx_fmt_ee (GET_CODE (operands[
4]) == NE ? EQ : NE,
5018 VOIDmode, operands[
1], const0_rtx);
5021 (define_insn_and_split "*cond_opsi2_internal"
5022 [(set (match_operand:SI
0 "gr_register_operand" "=r")
5023 (match_operator:SI
5 "condop_operator"
5025 (match_operator
6 "predicate_operator"
5026 [(match_operand:BI
1 "register_operand" "c")
5028 (match_operand:SI
2 "gr_register_operand" "r")
5029 (match_operand:SI
3 "gr_register_operand" "r"))
5030 (match_operand:SI
4 "gr_register_operand" "r")]))]
5036 (set (match_dup
0) (match_op_dup:SI
5 [(match_dup
2) (match_dup
4)])))
5039 (set (match_dup
0) (match_op_dup:SI
5 [(match_dup
3) (match_dup
4)])))]
5041 operands[
7] = gen_rtx_fmt_ee (GET_CODE (operands[
6]) == NE ? EQ : NE,
5042 VOIDmode, operands[
1], const0_rtx);
5044 [(set_attr "itanium_class" "ialu")
5045 (set_attr "predicable" "no")])
5048 (define_insn_and_split "*cond_opsi2_internal_b"
5049 [(set (match_operand:SI
0 "gr_register_operand" "=r")
5050 (match_operator:SI
5 "condop_operator"
5051 [(match_operand:SI
4 "gr_register_operand" "r")
5053 (match_operator
6 "predicate_operator"
5054 [(match_operand:BI
1 "register_operand" "c")
5056 (match_operand:SI
2 "gr_register_operand" "r")
5057 (match_operand:SI
3 "gr_register_operand" "r"))]))]
5063 (set (match_dup
0) (match_op_dup:SI
5 [(match_dup
4) (match_dup
2)])))
5066 (set (match_dup
0) (match_op_dup:SI
5 [(match_dup
4) (match_dup
3)])))]
5068 operands[
7] = gen_rtx_fmt_ee (GET_CODE (operands[
6]) == NE ? EQ : NE,
5069 VOIDmode, operands[
1], const0_rtx);
5071 [(set_attr "itanium_class" "ialu")
5072 (set_attr "predicable" "no")])
5075 ;; ::::::::::::::::::::
5077 ;; :: Call and branch instructions
5079 ;; ::::::::::::::::::::
5081 ;; Subroutine call instruction returning no value. Operand
0 is the function
5082 ;; to call; operand
1 is the number of bytes of arguments pushed (in mode
5083 ;;
`SImode', except it is normally a `const_int'); operand
2 is the number of
5084 ;; registers used as operands.
5086 ;; On most machines, operand
2 is not actually stored into the RTL pattern. It
5087 ;; is supplied for the sake of some RISC machines which need to put this
5088 ;; information into the assembler code; they can put it in the RTL instead of
5091 (define_expand "call"
5092 [(use (match_operand:DI
0 "" ""))
5093 (use (match_operand
1 "" ""))
5094 (use (match_operand
2 "" ""))
5095 (use (match_operand
3 "" ""))]
5098 ia64_expand_call (NULL_RTX, operands[
0], operands[
2], false);
5102 (define_expand "sibcall"
5103 [(use (match_operand:DI
0 "" ""))
5104 (use (match_operand
1 "" ""))
5105 (use (match_operand
2 "" ""))
5106 (use (match_operand
3 "" ""))]
5109 ia64_expand_call (NULL_RTX, operands[
0], operands[
2], true);
5113 ;; Subroutine call instruction returning a value. Operand
0 is the hard
5114 ;; register in which the value is returned. There are three more operands,
5115 ;; the same as the three operands of the
`call' instruction (but with numbers
5116 ;; increased by one).
5118 ;; Subroutines that return `BLKmode' objects use the
`call' insn.
5120 (define_expand "call_value"
5121 [(use (match_operand 0 "" ""))
5122 (use (match_operand:DI 1 "" ""))
5123 (use (match_operand 2 "" ""))
5124 (use (match_operand 3 "" ""))
5125 (use (match_operand 4 "" ""))]
5128 ia64_expand_call (operands[0], operands[1], operands[3], false);
5132 (define_expand "sibcall_value"
5133 [(use (match_operand 0 "" ""))
5134 (use (match_operand:DI 1 "" ""))
5135 (use (match_operand 2 "" ""))
5136 (use (match_operand 3 "" ""))
5137 (use (match_operand 4 "" ""))]
5140 ia64_expand_call (operands[0], operands[1], operands[3], true);
5144 ;; Call subroutine returning any type.
5146 (define_expand "untyped_call"
5147 [(parallel [(call (match_operand 0 "" "")
5149 (match_operand 1 "" "")
5150 (match_operand 2 "" "")])]
5155 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
5157 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5159 rtx set = XVECEXP (operands[2], 0, i);
5160 emit_move_insn (SET_DEST (set), SET_SRC (set));
5163 /* The optimizer does not know that the call sets the function value
5164 registers we stored in the result block. We avoid problems by
5165 claiming that all hard registers are used and clobbered at this
5167 emit_insn (gen_blockage ());
5172 (define_insn "call_nogp"
5173 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5175 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
5177 "br.call%+.many %1 = %0"
5178 [(set_attr "itanium_class" "br,scall")])
5180 (define_insn "call_value_nogp"
5181 [(set (match_operand 0 "" "")
5182 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
5184 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
5186 "br.call%+.many %2 = %1"
5187 [(set_attr "itanium_class" "br,scall")])
5189 (define_insn "sibcall_nogp"
5190 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
5194 [(set_attr "itanium_class" "br,scall")])
5196 (define_insn "call_gp"
5197 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5199 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
5200 (clobber (match_scratch:DI 2 "=&r,X"))
5201 (clobber (match_scratch:DI 3 "=b,X"))]
5204 [(set_attr "itanium_class" "br,scall")])
5206 ;; Irritatingly, we don't have access to INSN within the split body.
5207 ;; See commentary in ia64_split_call as to why these aren't peep2.
5209 [(call (mem (match_operand 0 "call_operand" ""))
5211 (clobber (match_operand:DI 1 "register_operand" ""))
5212 (clobber (match_scratch:DI 2 ""))
5213 (clobber (match_scratch:DI 3 ""))]
5214 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5217 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5218 operands[3], true, false);
5223 [(call (mem (match_operand 0 "call_operand" ""))
5225 (clobber (match_operand:DI 1 "register_operand" ""))
5226 (clobber (match_scratch:DI 2 ""))
5227 (clobber (match_scratch:DI 3 ""))]
5231 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
5232 operands[3], false, false);
5236 (define_insn "call_value_gp"
5237 [(set (match_operand 0 "" "")
5238 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
5240 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
5241 (clobber (match_scratch:DI 3 "=&r,X"))
5242 (clobber (match_scratch:DI 4 "=b,X"))]
5245 [(set_attr "itanium_class" "br,scall")])
5248 [(set (match_operand 0 "" "")
5249 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5251 (clobber (match_operand:DI 2 "register_operand" ""))
5252 (clobber (match_scratch:DI 3 ""))
5253 (clobber (match_scratch:DI 4 ""))]
5254 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
5257 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5258 operands[4], true, false);
5263 [(set (match_operand 0 "" "")
5264 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
5266 (clobber (match_operand:DI 2 "register_operand" ""))
5267 (clobber (match_scratch:DI 3 ""))
5268 (clobber (match_scratch:DI 4 ""))]
5272 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
5273 operands[4], false, false);
5277 (define_insn_and_split "sibcall_gp"
5278 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
5280 (clobber (match_scratch:DI 1 "=&r,X"))
5281 (clobber (match_scratch:DI 2 "=b,X"))]
5287 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
5288 operands[2], true, true);
5291 [(set_attr "itanium_class" "br")])
5293 (define_insn "return_internal"
5295 (use (match_operand:DI 0 "register_operand" "b"))]
5297 "br.ret.sptk.many %0"
5298 [(set_attr "itanium_class" "br")])
5300 (define_insn "return"
5302 "ia64_direct_return ()"
5303 "br.ret.sptk.many rp"
5304 [(set_attr "itanium_class" "br")])
5306 (define_insn "*return_true"
5308 (if_then_else (match_operator 0 "predicate_operator"
5309 [(match_operand:BI 1 "register_operand" "c")
5313 "ia64_direct_return ()"
5314 "(%J0) br.ret%+.many rp"
5315 [(set_attr "itanium_class" "br")
5316 (set_attr "predicable" "no")])
5318 (define_insn "*return_false"
5320 (if_then_else (match_operator 0 "predicate_operator"
5321 [(match_operand:BI 1 "register_operand" "c")
5325 "ia64_direct_return ()"
5326 "(%j0) br.ret%+.many rp"
5327 [(set_attr "itanium_class" "br")
5328 (set_attr "predicable" "no")])
5331 [(set (pc) (label_ref (match_operand 0 "" "")))]
5334 [(set_attr "itanium_class" "br")])
5336 (define_insn "indirect_jump"
5337 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
5340 [(set_attr "itanium_class" "br")])
5342 (define_expand "tablejump"
5343 [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" ""))
5344 (use (label_ref (match_operand 1 "" "")))])]
5347 rtx op0 = operands[0];
5350 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
5351 element into a register without bothering to see whether that
5352 is necessary given the operand predicate. Check for MEM just
5353 in case someone fixes this. */
5354 if (GET_CODE (op0) == MEM)
5355 addr = XEXP (op0, 0);
5358 /* Otherwise, cheat and guess that the previous insn in the
5359 stream was the memory load. Grab the address from that.
5360 Note we have to momentarily pop out of the sequence started
5361 by the insn-emit wrapper in order to grab the last insn. */
5365 last = get_last_insn ();
5367 set = single_set (last);
5369 if (! rtx_equal_p (SET_DEST (set), op0)
5370 || GET_CODE (SET_SRC (set)) != MEM)
5372 addr = XEXP (SET_SRC (set), 0);
5373 if (rtx_equal_p (addr, op0))
5377 /* Jump table elements are stored pc-relative. That is, a displacement
5378 from the entry to the label. Thus to convert to an absolute address
5379 we add the address of the memory from which the value is loaded. */
5380 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
5381 NULL_RTX, 1, OPTAB_DIRECT);
5384 (define_insn "*tablejump_internal"
5385 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
5386 (use (label_ref (match_operand 1 "" "")))]
5389 [(set_attr "itanium_class" "br")])
5392 ;; ::::::::::::::::::::
5394 ;; :: Prologue and Epilogue instructions
5396 ;; ::::::::::::::::::::
5398 (define_expand "prologue"
5402 ia64_expand_prologue ();
5406 (define_expand "epilogue"
5410 ia64_expand_epilogue (0);
5414 (define_expand "sibcall_epilogue"
5418 ia64_expand_epilogue (1);
5422 ;; This prevents the scheduler from moving the SP decrement past FP-relative
5423 ;; stack accesses. This is the same as adddi3 plus the extra set.
5425 (define_insn "prologue_allocate_stack"
5426 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
5427 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
5428 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
5429 (set (match_operand:DI 3 "register_operand" "+r,r,r")
5436 [(set_attr "itanium_class" "ialu")])
5438 ;; This prevents the scheduler from moving the SP restore past FP-relative
5439 ;; stack accesses. This is similar to movdi plus the extra set.
5441 (define_insn "epilogue_deallocate_stack"
5442 [(set (match_operand:DI 0 "register_operand" "=r")
5443 (match_operand:DI 1 "register_operand" "+r"))
5444 (set (match_dup 1) (match_dup 1))]
5447 [(set_attr "itanium_class" "ialu")])
5449 ;; As USE insns aren't meaningful after reload, this is used instead
5450 ;; to prevent deleting instructions setting registers for EH handling
5451 (define_insn "prologue_use"
5452 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
5453 UNSPEC_PROLOGUE_USE)]
5456 [(set_attr "itanium_class" "ignore")
5457 (set_attr "predicable" "no")])
5459 ;; Allocate a new register frame.
5461 (define_insn "alloc"
5462 [(set (match_operand:DI 0 "register_operand" "=r")
5463 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
5464 (use (match_operand:DI 1 "const_int_operand" "i"))
5465 (use (match_operand:DI 2 "const_int_operand" "i"))
5466 (use (match_operand:DI 3 "const_int_operand" "i"))
5467 (use (match_operand:DI 4 "const_int_operand" "i"))]
5469 "alloc %0 = ar.pfs, %1, %2, %3, %4"
5470 [(set_attr "itanium_class" "syst_m0")
5471 (set_attr "predicable" "no")])
5474 (define_expand "gr_spill"
5475 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
5476 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5477 (match_operand:DI 2 "const_int_operand" "")]
5479 (clobber (match_dup 3))])]
5481 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5483 (define_insn "gr_spill_internal"
5484 [(set (match_operand:DI 0 "memory_operand" "=m")
5485 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5486 (match_operand:DI 2 "const_int_operand" "")]
5488 (clobber (match_operand:DI 3 "register_operand" ""))]
5491 /* Note that we use a C output pattern here to avoid the predicate
5492 being automatically added before the .mem.offset directive. */
5493 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
5495 [(set_attr "itanium_class" "st")])
5498 (define_expand "gr_restore"
5499 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
5500 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5501 (match_operand:DI 2 "const_int_operand" "")]
5503 (use (match_dup 3))])]
5505 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
5507 (define_insn "gr_restore_internal"
5508 [(set (match_operand:DI 0 "register_operand" "=r")
5509 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
5510 (match_operand:DI 2 "const_int_operand" "")]
5512 (use (match_operand:DI 3 "register_operand" ""))]
5514 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
5515 [(set_attr "itanium_class" "ld")])
5517 (define_insn "fr_spill"
5518 [(set (match_operand:XF 0 "memory_operand" "=m")
5519 (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
5522 "stf.spill %0 = %1%P0"
5523 [(set_attr "itanium_class" "stf")])
5525 (define_insn "fr_restore"
5526 [(set (match_operand:XF 0 "register_operand" "=f")
5527 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
5528 UNSPEC_FR_RESTORE))]
5530 "ldf.fill %0 = %1%P1"
5531 [(set_attr "itanium_class" "fld")])
5533 ;; ??? The explicit stop is not ideal. It would be better if
5534 ;; rtx_needs_barrier took care of this, but this is something that can be
5535 ;; fixed later. This avoids an RSE DV.
5537 (define_insn "bsp_value"
5538 [(set (match_operand:DI 0 "register_operand" "=r")
5539 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
5543 return \";;\;%,mov %0 = ar.bsp\";
5545 [(set_attr "itanium_class" "frar_i")])
5547 (define_insn "set_bsp"
5548 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
5566 [(set_attr "itanium_class" "unknown")
5567 (set_attr "predicable" "no")])
5569 ;; ??? The explicit stops are not ideal. It would be better if
5570 ;; rtx_needs_barrier took care of this, but this is something that can be
5571 ;; fixed later. This avoids an RSE DV.
5573 (define_insn "flushrs"
5574 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
5577 [(set_attr "itanium_class" "rse_m")
5578 (set_attr "predicable" "no")])
5580 ;; ::::::::::::::::::::
5582 ;; :: Miscellaneous instructions
5584 ;; ::::::::::::::::::::
5586 ;; ??? Emitting a NOP instruction isn't very useful. This should probably
5587 ;; be emitting ";;" to force a break in the instruction packing.
5589 ;; No operation, needed in case the user uses -g but not -O.
5594 [(set_attr "itanium_class" "nop")])
5596 (define_insn "nop_m"
5600 [(set_attr "itanium_class" "nop_m")])
5602 (define_insn "nop_i"
5606 [(set_attr "itanium_class" "nop_i")])
5608 (define_insn "nop_f"
5612 [(set_attr "itanium_class" "nop_f")])
5614 (define_insn "nop_b"
5618 [(set_attr "itanium_class" "nop_b")])
5620 (define_insn "nop_x"
5624 [(set_attr "itanium_class" "nop_x")])
5626 ;; The following insn will be never generated. It is used only by
5627 ;; insn scheduler to change state before advancing cycle.
5628 (define_insn "pre_cycle"
5632 [(set_attr "itanium_class" "pre_cycle")])
5634 (define_insn "bundle_selector"
5635 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
5637 { return get_bundle_name (INTVAL (operands[0])); }
5638 [(set_attr "itanium_class" "ignore")
5639 (set_attr "predicable" "no")])
5641 ;; Pseudo instruction that prevents the scheduler from moving code above this
5643 (define_insn "blockage"
5644 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
5647 [(set_attr "itanium_class" "ignore")
5648 (set_attr "predicable" "no")])
5650 (define_insn "insn_group_barrier"
5651 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
5652 UNSPECV_INSN_GROUP_BARRIER)]
5655 [(set_attr "itanium_class" "stop_bit")
5656 (set_attr "predicable" "no")])
5658 (define_expand "trap"
5659 [(trap_if (const_int 1) (const_int 0))]
5663 ;; ??? We don't have a match-any slot type. Setting the type to unknown
5664 ;; produces worse code that setting the slot type to A.
5666 (define_insn "*trap"
5667 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
5670 [(set_attr "itanium_class" "chk_s")])
5672 (define_expand "conditional_trap"
5673 [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
5676 operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode);
5679 (define_insn "*conditional_trap"
5680 [(trap_if (match_operator 0 "predicate_operator"
5681 [(match_operand:BI 1 "register_operand" "c")
5683 (match_operand 2 "const_int_operand" ""))]
5686 [(set_attr "itanium_class" "chk_s")
5687 (set_attr "predicable" "no")])
5689 (define_insn "break_f"
5690 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
5693 [(set_attr "itanium_class" "nop_f")])
5695 (define_insn "prefetch"
5696 [(prefetch (match_operand:DI 0 "address_operand" "p")
5697 (match_operand:DI 1 "const_int_operand" "n")
5698 (match_operand:DI 2 "const_int_operand" "n"))]
5701 static const char * const alt[2][4] = {
5703 "%,lfetch.nta [%0]",
5704 "%,lfetch.nt1 [%0]",
5705 "%,lfetch.nt2 [%0]",
5709 "%,lfetch.excl.nta [%0]",
5710 "%,lfetch.excl.nt1 [%0]",
5711 "%,lfetch.excl.nt2 [%0]",
5712 "%,lfetch.excl [%0]"
5715 int i = (INTVAL (operands[1]));
5716 int j = (INTVAL (operands[2]));
5718 if (i != 0 && i != 1)
5724 [(set_attr "itanium_class" "lfetch")])
5726 ;; Non-local goto support.
5728 (define_expand "save_stack_nonlocal"
5729 [(use (match_operand:OI 0 "memory_operand" ""))
5730 (use (match_operand:DI 1 "register_operand" ""))]
5733 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5734 \"__ia64_save_stack_nonlocal\"),
5735 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
5736 operands[1], Pmode);
5740 (define_expand "nonlocal_goto"
5741 [(use (match_operand 0 "general_operand" ""))
5742 (use (match_operand 1 "general_operand" ""))
5743 (use (match_operand 2 "general_operand" ""))
5744 (use (match_operand 3 "general_operand" ""))]
5747 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
5748 LCT_NORETURN, VOIDmode, 3,
5750 copy_to_reg (XEXP (operands[2], 0)), Pmode,
5751 operands[3], Pmode);
5756 (define_insn_and_split "builtin_setjmp_receiver"
5757 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
5767 (define_expand "eh_epilogue"
5768 [(use (match_operand:DI 0 "register_operand" "r"))
5769 (use (match_operand:DI 1 "register_operand" "r"))
5770 (use (match_operand:DI 2 "register_operand" "r"))]
5773 rtx bsp = gen_rtx_REG (Pmode, 10);
5774 rtx sp = gen_rtx_REG (Pmode, 9);
5776 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5778 emit_move_insn (bsp, operands[0]);
5781 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5783 emit_move_insn (sp, operands[2]);
5786 emit_insn (gen_rtx_USE (VOIDmode, sp));
5787 emit_insn (gen_rtx_USE (VOIDmode, bsp));
5789 cfun->machine->ia64_eh_epilogue_sp = sp;
5790 cfun->machine->ia64_eh_epilogue_bsp = bsp;
5793 ;; Builtin apply support.
5795 (define_expand "restore_stack_nonlocal"
5796 [(use (match_operand:DI 0 "register_operand" ""))
5797 (use (match_operand:OI 1 "memory_operand" ""))]
5800 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5801 "__ia64_restore_stack_nonlocal"),
5803 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5808 ;;; Intrinsics support.
5811 [(set (mem:BLK (match_dup 0))
5812 (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
5815 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
5816 MEM_VOLATILE_P (operands[0]) = 1;
5819 (define_insn "*mf_internal"
5820 [(set (match_operand:BLK 0 "" "")
5821 (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
5824 [(set_attr "itanium_class" "syst_m")])
5826 (define_insn "fetchadd_acq_si"
5827 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5829 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5830 (unspec:SI [(match_dup 1)
5831 (match_operand:SI 2 "fetchadd_operand" "n")]
5832 UNSPEC_FETCHADD_ACQ))]
5834 "fetchadd4.acq %0 = %1, %2"
5835 [(set_attr "itanium_class" "sem")])
5837 (define_insn "fetchadd_acq_di"
5838 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5840 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5841 (unspec:DI [(match_dup 1)
5842 (match_operand:DI 2 "fetchadd_operand" "n")]
5843 UNSPEC_FETCHADD_ACQ))]
5845 "fetchadd8.acq %0 = %1, %2"
5846 [(set_attr "itanium_class" "sem")])
5848 (define_insn "cmpxchg_acq_si"
5849 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5851 (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
5852 (unspec:SI [(match_dup 1)
5853 (match_operand:SI 2 "gr_register_operand" "r")
5854 (match_operand:DI 3 "ar_ccv_reg_operand" "")]
5855 UNSPEC_CMPXCHG_ACQ))]
5857 "cmpxchg4.acq %0 = %1, %2, %3"
5858 [(set_attr "itanium_class" "sem")])
5860 (define_insn "cmpxchg_acq_di"
5861 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5863 (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
5864 (unspec:DI [(match_dup 1)
5865 (match_operand:DI 2 "gr_register_operand" "r")
5866 (match_operand:DI 3 "ar_ccv_reg_operand" "")]
5867 UNSPEC_CMPXCHG_ACQ))]
5869 "cmpxchg8.acq %0 = %1, %2, %3"
5870 [(set_attr "itanium_class" "sem")])
5872 (define_insn "xchgsi"
5873 [(set (match_operand:SI 0 "gr_register_operand" "=r")
5874 (match_operand:SI 1 "not_postinc_memory_operand" "+S"))
5876 (match_operand:SI 2 "gr_register_operand" "r"))]
5879 [(set_attr "itanium_class" "sem")])
5881 (define_insn "xchgdi"
5882 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5883 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
5885 (match_operand:DI 2 "gr_register_operand" "r"))]
5888 [(set_attr "itanium_class" "sem")])
5893 [(match_operator 0 "predicate_operator"
5894 [(match_operand:BI 1 "register_operand" "c")
5899 (define_insn "pred_rel_mutex"
5900 [(set (match_operand:BI 0 "register_operand" "+c")
5901 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
5903 ".pred.rel.mutex %0, %I0"
5904 [(set_attr "itanium_class" "ignore")
5905 (set_attr "predicable" "no")])
5907 (define_insn "safe_across_calls_all"
5908 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
5910 ".pred.safe_across_calls p1-p63"
5911 [(set_attr "itanium_class" "ignore")
5912 (set_attr "predicable" "no")])
5914 (define_insn "safe_across_calls_normal"
5915 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
5918 emit_safe_across_calls ();
5921 [(set_attr "itanium_class" "ignore")
5922 (set_attr "predicable" "no")])
5924 ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
5925 ;; pointer. This is used by the HP-UX 32 bit mode.
5927 (define_insn "ptr_extend"
5928 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5929 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
5933 [(set_attr "itanium_class" "ialu")])
5936 ;; Optimizations for ptr_extend
5938 (define_insn "ptr_extend_plus_imm"
5939 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5941 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
5942 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
5944 "addp4_optimize_ok (operands[1], operands[2])"
5946 [(set_attr "itanium_class" "ialu")])
5948 (define_insn "*ptr_extend_plus_2"
5949 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5951 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
5952 (match_operand:SI 2 "basereg_operand" "r"))]
5954 "addp4_optimize_ok (operands[1], operands[2])"
5956 [(set_attr "itanium_class" "ialu")])