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[gcc.git] / gcc / config / ia64 / ia64.c
1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by James E. Wilson <wilson@cygnus.com> and
6 David Mosberger <davidm@hpl.hp.com>.
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "coretypes.h"
27 #include "tm.h"
28 #include "rtl.h"
29 #include "tree.h"
30 #include "regs.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "output.h"
35 #include "insn-attr.h"
36 #include "flags.h"
37 #include "recog.h"
38 #include "expr.h"
39 #include "optabs.h"
40 #include "except.h"
41 #include "function.h"
42 #include "ggc.h"
43 #include "basic-block.h"
44 #include "libfuncs.h"
45 #include "diagnostic-core.h"
46 #include "toplev.h"
47 #include "sched-int.h"
48 #include "timevar.h"
49 #include "target.h"
50 #include "target-def.h"
51 #include "tm_p.h"
52 #include "hashtab.h"
53 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "gimple.h"
56 #include "intl.h"
57 #include "df.h"
58 #include "debug.h"
59 #include "params.h"
60 #include "dbgcnt.h"
61 #include "tm-constrs.h"
62 #include "sel-sched.h"
63 #include "reload.h"
64
65 /* This is used for communication between ASM_OUTPUT_LABEL and
66 ASM_OUTPUT_LABELREF. */
67 int ia64_asm_output_label = 0;
68
69 /* Register names for ia64_expand_prologue. */
70 static const char * const ia64_reg_numbers[96] =
71 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
72 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
73 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
74 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
75 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
76 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
77 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
78 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
79 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
80 "r104","r105","r106","r107","r108","r109","r110","r111",
81 "r112","r113","r114","r115","r116","r117","r118","r119",
82 "r120","r121","r122","r123","r124","r125","r126","r127"};
83
84 /* ??? These strings could be shared with REGISTER_NAMES. */
85 static const char * const ia64_input_reg_names[8] =
86 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
87
88 /* ??? These strings could be shared with REGISTER_NAMES. */
89 static const char * const ia64_local_reg_names[80] =
90 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
91 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
92 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
93 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
94 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
95 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
96 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
97 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
98 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
99 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
100
101 /* ??? These strings could be shared with REGISTER_NAMES. */
102 static const char * const ia64_output_reg_names[8] =
103 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
104
105 /* Which cpu are we scheduling for. */
106 enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
107
108 /* Determines whether we run our final scheduling pass or not. We always
109 avoid the normal second scheduling pass. */
110 static int ia64_flag_schedule_insns2;
111
112 /* Determines whether we run variable tracking in machine dependent
113 reorganization. */
114 static int ia64_flag_var_tracking;
115
116 /* Variables which are this size or smaller are put in the sdata/sbss
117 sections. */
118
119 unsigned int ia64_section_threshold;
120
121 /* The following variable is used by the DFA insn scheduler. The value is
122 TRUE if we do insn bundling instead of insn scheduling. */
123 int bundling_p = 0;
124
125 enum ia64_frame_regs
126 {
127 reg_fp,
128 reg_save_b0,
129 reg_save_pr,
130 reg_save_ar_pfs,
131 reg_save_ar_unat,
132 reg_save_ar_lc,
133 reg_save_gp,
134 number_of_ia64_frame_regs
135 };
136
137 /* Structure to be filled in by ia64_compute_frame_size with register
138 save masks and offsets for the current function. */
139
140 struct ia64_frame_info
141 {
142 HOST_WIDE_INT total_size; /* size of the stack frame, not including
143 the caller's scratch area. */
144 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
145 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
146 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
147 HARD_REG_SET mask; /* mask of saved registers. */
148 unsigned int gr_used_mask; /* mask of registers in use as gr spill
149 registers or long-term scratches. */
150 int n_spilled; /* number of spilled registers. */
151 int r[number_of_ia64_frame_regs]; /* Frame related registers. */
152 int n_input_regs; /* number of input registers used. */
153 int n_local_regs; /* number of local registers used. */
154 int n_output_regs; /* number of output registers used. */
155 int n_rotate_regs; /* number of rotating registers used. */
156
157 char need_regstk; /* true if a .regstk directive needed. */
158 char initialized; /* true if the data is finalized. */
159 };
160
161 /* Current frame information calculated by ia64_compute_frame_size. */
162 static struct ia64_frame_info current_frame_info;
163 /* The actual registers that are emitted. */
164 static int emitted_frame_related_regs[number_of_ia64_frame_regs];
165 \f
166 static int ia64_first_cycle_multipass_dfa_lookahead (void);
167 static void ia64_dependencies_evaluation_hook (rtx, rtx);
168 static void ia64_init_dfa_pre_cycle_insn (void);
169 static rtx ia64_dfa_pre_cycle_insn (void);
170 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
171 static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx);
172 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
173 static void ia64_h_i_d_extended (void);
174 static void * ia64_alloc_sched_context (void);
175 static void ia64_init_sched_context (void *, bool);
176 static void ia64_set_sched_context (void *);
177 static void ia64_clear_sched_context (void *);
178 static void ia64_free_sched_context (void *);
179 static int ia64_mode_to_int (enum machine_mode);
180 static void ia64_set_sched_flags (spec_info_t);
181 static ds_t ia64_get_insn_spec_ds (rtx);
182 static ds_t ia64_get_insn_checked_ds (rtx);
183 static bool ia64_skip_rtx_p (const_rtx);
184 static int ia64_speculate_insn (rtx, ds_t, rtx *);
185 static bool ia64_needs_block_p (int);
186 static rtx ia64_gen_spec_check (rtx, rtx, ds_t);
187 static int ia64_spec_check_p (rtx);
188 static int ia64_spec_check_src_p (rtx);
189 static rtx gen_tls_get_addr (void);
190 static rtx gen_thread_pointer (void);
191 static int find_gr_spill (enum ia64_frame_regs, int);
192 static int next_scratch_gr_reg (void);
193 static void mark_reg_gr_used_mask (rtx, void *);
194 static void ia64_compute_frame_size (HOST_WIDE_INT);
195 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
196 static void finish_spill_pointers (void);
197 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
198 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
199 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
200 static rtx gen_movdi_x (rtx, rtx, rtx);
201 static rtx gen_fr_spill_x (rtx, rtx, rtx);
202 static rtx gen_fr_restore_x (rtx, rtx, rtx);
203
204 static void ia64_option_override (void);
205 static void ia64_option_optimization (int, int);
206 static bool ia64_can_eliminate (const int, const int);
207 static enum machine_mode hfa_element_mode (const_tree, bool);
208 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
209 tree, int *, int);
210 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
211 tree, bool);
212 static bool ia64_function_ok_for_sibcall (tree, tree);
213 static bool ia64_return_in_memory (const_tree, const_tree);
214 static rtx ia64_function_value (const_tree, const_tree, bool);
215 static rtx ia64_libcall_value (enum machine_mode, const_rtx);
216 static bool ia64_function_value_regno_p (const unsigned int);
217 static int ia64_register_move_cost (enum machine_mode, reg_class_t,
218 reg_class_t);
219 static int ia64_memory_move_cost (enum machine_mode mode, reg_class_t,
220 bool);
221 static bool ia64_rtx_costs (rtx, int, int, int *, bool);
222 static int ia64_unspec_may_trap_p (const_rtx, unsigned);
223 static void fix_range (const char *);
224 static bool ia64_handle_option (size_t, const char *, int);
225 static struct machine_function * ia64_init_machine_status (void);
226 static void emit_insn_group_barriers (FILE *);
227 static void emit_all_insn_group_barriers (FILE *);
228 static void final_emit_insn_group_barriers (FILE *);
229 static void emit_predicate_relation_info (void);
230 static void ia64_reorg (void);
231 static bool ia64_in_small_data_p (const_tree);
232 static void process_epilogue (FILE *, rtx, bool, bool);
233
234 static bool ia64_assemble_integer (rtx, unsigned int, int);
235 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
236 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
237 static void ia64_output_function_end_prologue (FILE *);
238
239 static int ia64_issue_rate (void);
240 static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t);
241 static void ia64_sched_init (FILE *, int, int);
242 static void ia64_sched_init_global (FILE *, int, int);
243 static void ia64_sched_finish_global (FILE *, int);
244 static void ia64_sched_finish (FILE *, int);
245 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
246 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
247 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
248 static int ia64_variable_issue (FILE *, int, rtx, int);
249
250 static void ia64_asm_unwind_emit (FILE *, rtx);
251 static void ia64_asm_emit_except_personality (rtx);
252 static void ia64_asm_init_sections (void);
253
254 static enum unwind_info_type ia64_debug_unwind_info (void);
255 static enum unwind_info_type ia64_except_unwind_info (void);
256
257 static struct bundle_state *get_free_bundle_state (void);
258 static void free_bundle_state (struct bundle_state *);
259 static void initiate_bundle_states (void);
260 static void finish_bundle_states (void);
261 static unsigned bundle_state_hash (const void *);
262 static int bundle_state_eq_p (const void *, const void *);
263 static int insert_bundle_state (struct bundle_state *);
264 static void initiate_bundle_state_table (void);
265 static void finish_bundle_state_table (void);
266 static int try_issue_nops (struct bundle_state *, int);
267 static int try_issue_insn (struct bundle_state *, rtx);
268 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
269 static int get_max_pos (state_t);
270 static int get_template (state_t, int);
271
272 static rtx get_next_important_insn (rtx, rtx);
273 static bool important_for_bundling_p (rtx);
274 static void bundling (FILE *, int, rtx, rtx);
275
276 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
277 HOST_WIDE_INT, tree);
278 static void ia64_file_start (void);
279 static void ia64_globalize_decl_name (FILE *, tree);
280
281 static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
282 static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED;
283 static section *ia64_select_rtx_section (enum machine_mode, rtx,
284 unsigned HOST_WIDE_INT);
285 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
286 ATTRIBUTE_UNUSED;
287 static unsigned int ia64_section_type_flags (tree, const char *, int);
288 static void ia64_init_libfuncs (void)
289 ATTRIBUTE_UNUSED;
290 static void ia64_hpux_init_libfuncs (void)
291 ATTRIBUTE_UNUSED;
292 static void ia64_sysv4_init_libfuncs (void)
293 ATTRIBUTE_UNUSED;
294 static void ia64_vms_init_libfuncs (void)
295 ATTRIBUTE_UNUSED;
296 static void ia64_soft_fp_init_libfuncs (void)
297 ATTRIBUTE_UNUSED;
298 static bool ia64_vms_valid_pointer_mode (enum machine_mode mode)
299 ATTRIBUTE_UNUSED;
300 static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *)
301 ATTRIBUTE_UNUSED;
302
303 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
304 static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *);
305 static void ia64_encode_section_info (tree, rtx, int);
306 static rtx ia64_struct_value_rtx (tree, int);
307 static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
308 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
309 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
310 static bool ia64_cannot_force_const_mem (rtx);
311 static const char *ia64_mangle_type (const_tree);
312 static const char *ia64_invalid_conversion (const_tree, const_tree);
313 static const char *ia64_invalid_unary_op (int, const_tree);
314 static const char *ia64_invalid_binary_op (int, const_tree, const_tree);
315 static enum machine_mode ia64_c_mode_for_suffix (char);
316 static enum machine_mode ia64_promote_function_mode (const_tree,
317 enum machine_mode,
318 int *,
319 const_tree,
320 int);
321 static void ia64_trampoline_init (rtx, tree, rtx);
322 static void ia64_override_options_after_change (void);
323
324 static void ia64_dwarf_handle_frame_unspec (const char *, rtx, int);
325 static tree ia64_builtin_decl (unsigned, bool);
326 \f
327 /* Table of valid machine attributes. */
328 static const struct attribute_spec ia64_attribute_table[] =
329 {
330 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
331 { "syscall_linkage", 0, 0, false, true, true, NULL },
332 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
333 #if TARGET_ABI_OPEN_VMS
334 { "common_object", 1, 1, true, false, false, ia64_vms_common_object_attribute},
335 #endif
336 { "version_id", 1, 1, true, false, false,
337 ia64_handle_version_id_attribute },
338 { NULL, 0, 0, false, false, false, NULL }
339 };
340
341 /* Initialize the GCC target structure. */
342 #undef TARGET_ATTRIBUTE_TABLE
343 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
344
345 #undef TARGET_INIT_BUILTINS
346 #define TARGET_INIT_BUILTINS ia64_init_builtins
347
348 #undef TARGET_EXPAND_BUILTIN
349 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
350
351 #undef TARGET_BUILTIN_DECL
352 #define TARGET_BUILTIN_DECL ia64_builtin_decl
353
354 #undef TARGET_ASM_BYTE_OP
355 #define TARGET_ASM_BYTE_OP "\tdata1\t"
356 #undef TARGET_ASM_ALIGNED_HI_OP
357 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
358 #undef TARGET_ASM_ALIGNED_SI_OP
359 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
360 #undef TARGET_ASM_ALIGNED_DI_OP
361 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
362 #undef TARGET_ASM_UNALIGNED_HI_OP
363 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
364 #undef TARGET_ASM_UNALIGNED_SI_OP
365 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
366 #undef TARGET_ASM_UNALIGNED_DI_OP
367 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
368 #undef TARGET_ASM_INTEGER
369 #define TARGET_ASM_INTEGER ia64_assemble_integer
370
371 #undef TARGET_OPTION_OVERRIDE
372 #define TARGET_OPTION_OVERRIDE ia64_option_override
373 #undef TARGET_OPTION_OPTIMIZATION
374 #define TARGET_OPTION_OPTIMIZATION ia64_option_optimization
375
376 #undef TARGET_ASM_FUNCTION_PROLOGUE
377 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
378 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
379 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
380 #undef TARGET_ASM_FUNCTION_EPILOGUE
381 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
382
383 #undef TARGET_IN_SMALL_DATA_P
384 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
385
386 #undef TARGET_SCHED_ADJUST_COST_2
387 #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2
388 #undef TARGET_SCHED_ISSUE_RATE
389 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
390 #undef TARGET_SCHED_VARIABLE_ISSUE
391 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
392 #undef TARGET_SCHED_INIT
393 #define TARGET_SCHED_INIT ia64_sched_init
394 #undef TARGET_SCHED_FINISH
395 #define TARGET_SCHED_FINISH ia64_sched_finish
396 #undef TARGET_SCHED_INIT_GLOBAL
397 #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global
398 #undef TARGET_SCHED_FINISH_GLOBAL
399 #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global
400 #undef TARGET_SCHED_REORDER
401 #define TARGET_SCHED_REORDER ia64_sched_reorder
402 #undef TARGET_SCHED_REORDER2
403 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
404
405 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
406 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
407
408 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
409 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
410
411 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
412 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
413 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
414 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
415
416 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
417 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
418 ia64_first_cycle_multipass_dfa_lookahead_guard
419
420 #undef TARGET_SCHED_DFA_NEW_CYCLE
421 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
422
423 #undef TARGET_SCHED_H_I_D_EXTENDED
424 #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended
425
426 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
427 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context
428
429 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
430 #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context
431
432 #undef TARGET_SCHED_SET_SCHED_CONTEXT
433 #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context
434
435 #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT
436 #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context
437
438 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
439 #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context
440
441 #undef TARGET_SCHED_SET_SCHED_FLAGS
442 #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags
443
444 #undef TARGET_SCHED_GET_INSN_SPEC_DS
445 #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds
446
447 #undef TARGET_SCHED_GET_INSN_CHECKED_DS
448 #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds
449
450 #undef TARGET_SCHED_SPECULATE_INSN
451 #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn
452
453 #undef TARGET_SCHED_NEEDS_BLOCK_P
454 #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p
455
456 #undef TARGET_SCHED_GEN_SPEC_CHECK
457 #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check
458
459 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC
460 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\
461 ia64_first_cycle_multipass_dfa_lookahead_guard_spec
462
463 #undef TARGET_SCHED_SKIP_RTX_P
464 #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p
465
466 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
467 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
468 #undef TARGET_ARG_PARTIAL_BYTES
469 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
470
471 #undef TARGET_ASM_OUTPUT_MI_THUNK
472 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
473 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
474 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
475
476 #undef TARGET_ASM_FILE_START
477 #define TARGET_ASM_FILE_START ia64_file_start
478
479 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
480 #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name
481
482 #undef TARGET_REGISTER_MOVE_COST
483 #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost
484 #undef TARGET_MEMORY_MOVE_COST
485 #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost
486 #undef TARGET_RTX_COSTS
487 #define TARGET_RTX_COSTS ia64_rtx_costs
488 #undef TARGET_ADDRESS_COST
489 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
490
491 #undef TARGET_UNSPEC_MAY_TRAP_P
492 #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p
493
494 #undef TARGET_MACHINE_DEPENDENT_REORG
495 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
496
497 #undef TARGET_ENCODE_SECTION_INFO
498 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
499
500 #undef TARGET_SECTION_TYPE_FLAGS
501 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
502
503 #ifdef HAVE_AS_TLS
504 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
505 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
506 #endif
507
508 #undef TARGET_PROMOTE_FUNCTION_MODE
509 #define TARGET_PROMOTE_FUNCTION_MODE ia64_promote_function_mode
510
511 /* ??? Investigate. */
512 #if 0
513 #undef TARGET_PROMOTE_PROTOTYPES
514 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
515 #endif
516
517 #undef TARGET_FUNCTION_VALUE
518 #define TARGET_FUNCTION_VALUE ia64_function_value
519 #undef TARGET_LIBCALL_VALUE
520 #define TARGET_LIBCALL_VALUE ia64_libcall_value
521 #undef TARGET_FUNCTION_VALUE_REGNO_P
522 #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p
523
524 #undef TARGET_STRUCT_VALUE_RTX
525 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
526 #undef TARGET_RETURN_IN_MEMORY
527 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
528 #undef TARGET_SETUP_INCOMING_VARARGS
529 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
530 #undef TARGET_STRICT_ARGUMENT_NAMING
531 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
532 #undef TARGET_MUST_PASS_IN_STACK
533 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
534
535 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
536 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
537
538 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
539 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ia64_dwarf_handle_frame_unspec
540 #undef TARGET_ASM_UNWIND_EMIT
541 #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit
542 #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY
543 #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality
544 #undef TARGET_ASM_INIT_SECTIONS
545 #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections
546
547 #undef TARGET_DEBUG_UNWIND_INFO
548 #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info
549 #undef TARGET_EXCEPT_UNWIND_INFO
550 #define TARGET_EXCEPT_UNWIND_INFO ia64_except_unwind_info
551
552 #undef TARGET_SCALAR_MODE_SUPPORTED_P
553 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
554 #undef TARGET_VECTOR_MODE_SUPPORTED_P
555 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
556
557 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
558 in an order different from the specified program order. */
559 #undef TARGET_RELAXED_ORDERING
560 #define TARGET_RELAXED_ORDERING true
561
562 #undef TARGET_DEFAULT_TARGET_FLAGS
563 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
564 #undef TARGET_HANDLE_OPTION
565 #define TARGET_HANDLE_OPTION ia64_handle_option
566
567 #undef TARGET_CANNOT_FORCE_CONST_MEM
568 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
569
570 #undef TARGET_MANGLE_TYPE
571 #define TARGET_MANGLE_TYPE ia64_mangle_type
572
573 #undef TARGET_INVALID_CONVERSION
574 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
575 #undef TARGET_INVALID_UNARY_OP
576 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
577 #undef TARGET_INVALID_BINARY_OP
578 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
579
580 #undef TARGET_C_MODE_FOR_SUFFIX
581 #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix
582
583 #undef TARGET_CAN_ELIMINATE
584 #define TARGET_CAN_ELIMINATE ia64_can_eliminate
585
586 #undef TARGET_TRAMPOLINE_INIT
587 #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init
588
589 #undef TARGET_INVALID_WITHIN_DOLOOP
590 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
591
592 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
593 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change
594
595 struct gcc_target targetm = TARGET_INITIALIZER;
596 \f
597 typedef enum
598 {
599 ADDR_AREA_NORMAL, /* normal address area */
600 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
601 }
602 ia64_addr_area;
603
604 static GTY(()) tree small_ident1;
605 static GTY(()) tree small_ident2;
606
607 static void
608 init_idents (void)
609 {
610 if (small_ident1 == 0)
611 {
612 small_ident1 = get_identifier ("small");
613 small_ident2 = get_identifier ("__small__");
614 }
615 }
616
617 /* Retrieve the address area that has been chosen for the given decl. */
618
619 static ia64_addr_area
620 ia64_get_addr_area (tree decl)
621 {
622 tree model_attr;
623
624 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
625 if (model_attr)
626 {
627 tree id;
628
629 init_idents ();
630 id = TREE_VALUE (TREE_VALUE (model_attr));
631 if (id == small_ident1 || id == small_ident2)
632 return ADDR_AREA_SMALL;
633 }
634 return ADDR_AREA_NORMAL;
635 }
636
637 static tree
638 ia64_handle_model_attribute (tree *node, tree name, tree args,
639 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
640 {
641 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
642 ia64_addr_area area;
643 tree arg, decl = *node;
644
645 init_idents ();
646 arg = TREE_VALUE (args);
647 if (arg == small_ident1 || arg == small_ident2)
648 {
649 addr_area = ADDR_AREA_SMALL;
650 }
651 else
652 {
653 warning (OPT_Wattributes, "invalid argument of %qE attribute",
654 name);
655 *no_add_attrs = true;
656 }
657
658 switch (TREE_CODE (decl))
659 {
660 case VAR_DECL:
661 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
662 == FUNCTION_DECL)
663 && !TREE_STATIC (decl))
664 {
665 error_at (DECL_SOURCE_LOCATION (decl),
666 "an address area attribute cannot be specified for "
667 "local variables");
668 *no_add_attrs = true;
669 }
670 area = ia64_get_addr_area (decl);
671 if (area != ADDR_AREA_NORMAL && addr_area != area)
672 {
673 error ("address area of %q+D conflicts with previous "
674 "declaration", decl);
675 *no_add_attrs = true;
676 }
677 break;
678
679 case FUNCTION_DECL:
680 error_at (DECL_SOURCE_LOCATION (decl),
681 "address area attribute cannot be specified for "
682 "functions");
683 *no_add_attrs = true;
684 break;
685
686 default:
687 warning (OPT_Wattributes, "%qE attribute ignored",
688 name);
689 *no_add_attrs = true;
690 break;
691 }
692
693 return NULL_TREE;
694 }
695
696 /* The section must have global and overlaid attributes. */
697 #define SECTION_VMS_OVERLAY SECTION_MACH_DEP
698
699 /* Part of the low level implementation of DEC Ada pragma Common_Object which
700 enables the shared use of variables stored in overlaid linker areas
701 corresponding to the use of Fortran COMMON. */
702
703 static tree
704 ia64_vms_common_object_attribute (tree *node, tree name, tree args,
705 int flags ATTRIBUTE_UNUSED,
706 bool *no_add_attrs)
707 {
708 tree decl = *node;
709 tree id, val;
710 if (! DECL_P (decl))
711 abort ();
712
713 DECL_COMMON (decl) = 1;
714 id = TREE_VALUE (args);
715 if (TREE_CODE (id) == IDENTIFIER_NODE)
716 val = build_string (IDENTIFIER_LENGTH (id), IDENTIFIER_POINTER (id));
717 else if (TREE_CODE (id) == STRING_CST)
718 val = id;
719 else
720 {
721 warning (OPT_Wattributes,
722 "%qE attribute requires a string constant argument", name);
723 *no_add_attrs = true;
724 return NULL_TREE;
725 }
726 DECL_SECTION_NAME (decl) = val;
727 return NULL_TREE;
728 }
729
730 /* Part of the low level implementation of DEC Ada pragma Common_Object. */
731
732 void
733 ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name,
734 unsigned HOST_WIDE_INT size,
735 unsigned int align)
736 {
737 tree attr = DECL_ATTRIBUTES (decl);
738
739 /* As common_object attribute set DECL_SECTION_NAME check it before
740 looking up the attribute. */
741 if (DECL_SECTION_NAME (decl) && attr)
742 attr = lookup_attribute ("common_object", attr);
743 else
744 attr = NULL_TREE;
745
746 if (!attr)
747 {
748 /* Code from elfos.h. */
749 fprintf (file, "%s", COMMON_ASM_OP);
750 assemble_name (file, name);
751 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
752 size, align / BITS_PER_UNIT);
753 }
754 else
755 {
756 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
757 ASM_OUTPUT_LABEL (file, name);
758 ASM_OUTPUT_SKIP (file, size ? size : 1);
759 }
760 }
761
762 /* Definition of TARGET_ASM_NAMED_SECTION for VMS. */
763
764 void
765 ia64_vms_elf_asm_named_section (const char *name, unsigned int flags,
766 tree decl)
767 {
768 if (!(flags & SECTION_VMS_OVERLAY))
769 {
770 default_elf_asm_named_section (name, flags, decl);
771 return;
772 }
773 if (flags != (SECTION_VMS_OVERLAY | SECTION_WRITE))
774 abort ();
775
776 if (flags & SECTION_DECLARED)
777 {
778 fprintf (asm_out_file, "\t.section\t%s\n", name);
779 return;
780 }
781
782 fprintf (asm_out_file, "\t.section\t%s,\"awgO\"\n", name);
783 }
784
785 static void
786 ia64_encode_addr_area (tree decl, rtx symbol)
787 {
788 int flags;
789
790 flags = SYMBOL_REF_FLAGS (symbol);
791 switch (ia64_get_addr_area (decl))
792 {
793 case ADDR_AREA_NORMAL: break;
794 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
795 default: gcc_unreachable ();
796 }
797 SYMBOL_REF_FLAGS (symbol) = flags;
798 }
799
800 static void
801 ia64_encode_section_info (tree decl, rtx rtl, int first)
802 {
803 default_encode_section_info (decl, rtl, first);
804
805 /* Careful not to prod global register variables. */
806 if (TREE_CODE (decl) == VAR_DECL
807 && GET_CODE (DECL_RTL (decl)) == MEM
808 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
809 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
810 ia64_encode_addr_area (decl, XEXP (rtl, 0));
811 }
812 \f
813 /* Return 1 if the operands of a move are ok. */
814
815 int
816 ia64_move_ok (rtx dst, rtx src)
817 {
818 /* If we're under init_recog_no_volatile, we'll not be able to use
819 memory_operand. So check the code directly and don't worry about
820 the validity of the underlying address, which should have been
821 checked elsewhere anyway. */
822 if (GET_CODE (dst) != MEM)
823 return 1;
824 if (GET_CODE (src) == MEM)
825 return 0;
826 if (register_operand (src, VOIDmode))
827 return 1;
828
829 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
830 if (INTEGRAL_MODE_P (GET_MODE (dst)))
831 return src == const0_rtx;
832 else
833 return satisfies_constraint_G (src);
834 }
835
836 /* Return 1 if the operands are ok for a floating point load pair. */
837
838 int
839 ia64_load_pair_ok (rtx dst, rtx src)
840 {
841 if (GET_CODE (dst) != REG || !FP_REGNO_P (REGNO (dst)))
842 return 0;
843 if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
844 return 0;
845 switch (GET_CODE (XEXP (src, 0)))
846 {
847 case REG:
848 case POST_INC:
849 break;
850 case POST_DEC:
851 return 0;
852 case POST_MODIFY:
853 {
854 rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
855
856 if (GET_CODE (adjust) != CONST_INT
857 || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
858 return 0;
859 }
860 break;
861 default:
862 abort ();
863 }
864 return 1;
865 }
866
867 int
868 addp4_optimize_ok (rtx op1, rtx op2)
869 {
870 return (basereg_operand (op1, GET_MODE(op1)) !=
871 basereg_operand (op2, GET_MODE(op2)));
872 }
873
874 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
875 Return the length of the field, or <= 0 on failure. */
876
877 int
878 ia64_depz_field_mask (rtx rop, rtx rshift)
879 {
880 unsigned HOST_WIDE_INT op = INTVAL (rop);
881 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
882
883 /* Get rid of the zero bits we're shifting in. */
884 op >>= shift;
885
886 /* We must now have a solid block of 1's at bit 0. */
887 return exact_log2 (op + 1);
888 }
889
890 /* Return the TLS model to use for ADDR. */
891
892 static enum tls_model
893 tls_symbolic_operand_type (rtx addr)
894 {
895 enum tls_model tls_kind = TLS_MODEL_NONE;
896
897 if (GET_CODE (addr) == CONST)
898 {
899 if (GET_CODE (XEXP (addr, 0)) == PLUS
900 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
901 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
902 }
903 else if (GET_CODE (addr) == SYMBOL_REF)
904 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
905
906 return tls_kind;
907 }
908
909 /* Return true if X is a constant that is valid for some immediate
910 field in an instruction. */
911
912 bool
913 ia64_legitimate_constant_p (rtx x)
914 {
915 switch (GET_CODE (x))
916 {
917 case CONST_INT:
918 case LABEL_REF:
919 return true;
920
921 case CONST_DOUBLE:
922 if (GET_MODE (x) == VOIDmode || GET_MODE (x) == SFmode
923 || GET_MODE (x) == DFmode)
924 return true;
925 return satisfies_constraint_G (x);
926
927 case CONST:
928 case SYMBOL_REF:
929 /* ??? Short term workaround for PR 28490. We must make the code here
930 match the code in ia64_expand_move and move_operand, even though they
931 are both technically wrong. */
932 if (tls_symbolic_operand_type (x) == 0)
933 {
934 HOST_WIDE_INT addend = 0;
935 rtx op = x;
936
937 if (GET_CODE (op) == CONST
938 && GET_CODE (XEXP (op, 0)) == PLUS
939 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
940 {
941 addend = INTVAL (XEXP (XEXP (op, 0), 1));
942 op = XEXP (XEXP (op, 0), 0);
943 }
944
945 if (any_offset_symbol_operand (op, GET_MODE (op))
946 || function_operand (op, GET_MODE (op)))
947 return true;
948 if (aligned_offset_symbol_operand (op, GET_MODE (op)))
949 return (addend & 0x3fff) == 0;
950 return false;
951 }
952 return false;
953
954 case CONST_VECTOR:
955 {
956 enum machine_mode mode = GET_MODE (x);
957
958 if (mode == V2SFmode)
959 return satisfies_constraint_Y (x);
960
961 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
962 && GET_MODE_SIZE (mode) <= 8);
963 }
964
965 default:
966 return false;
967 }
968 }
969
970 /* Don't allow TLS addresses to get spilled to memory. */
971
972 static bool
973 ia64_cannot_force_const_mem (rtx x)
974 {
975 if (GET_MODE (x) == RFmode)
976 return true;
977 return tls_symbolic_operand_type (x) != 0;
978 }
979
980 /* Expand a symbolic constant load. */
981
982 bool
983 ia64_expand_load_address (rtx dest, rtx src)
984 {
985 gcc_assert (GET_CODE (dest) == REG);
986
987 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
988 having to pointer-extend the value afterward. Other forms of address
989 computation below are also more natural to compute as 64-bit quantities.
990 If we've been given an SImode destination register, change it. */
991 if (GET_MODE (dest) != Pmode)
992 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest),
993 byte_lowpart_offset (Pmode, GET_MODE (dest)));
994
995 if (TARGET_NO_PIC)
996 return false;
997 if (small_addr_symbolic_operand (src, VOIDmode))
998 return false;
999
1000 if (TARGET_AUTO_PIC)
1001 emit_insn (gen_load_gprel64 (dest, src));
1002 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1003 emit_insn (gen_load_fptr (dest, src));
1004 else if (sdata_symbolic_operand (src, VOIDmode))
1005 emit_insn (gen_load_gprel (dest, src));
1006 else
1007 {
1008 HOST_WIDE_INT addend = 0;
1009 rtx tmp;
1010
1011 /* We did split constant offsets in ia64_expand_move, and we did try
1012 to keep them split in move_operand, but we also allowed reload to
1013 rematerialize arbitrary constants rather than spill the value to
1014 the stack and reload it. So we have to be prepared here to split
1015 them apart again. */
1016 if (GET_CODE (src) == CONST)
1017 {
1018 HOST_WIDE_INT hi, lo;
1019
1020 hi = INTVAL (XEXP (XEXP (src, 0), 1));
1021 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
1022 hi = hi - lo;
1023
1024 if (lo != 0)
1025 {
1026 addend = lo;
1027 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
1028 }
1029 }
1030
1031 tmp = gen_rtx_HIGH (Pmode, src);
1032 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1033 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1034
1035 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
1036 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1037
1038 if (addend)
1039 {
1040 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
1041 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1042 }
1043 }
1044
1045 return true;
1046 }
1047
1048 static GTY(()) rtx gen_tls_tga;
1049 static rtx
1050 gen_tls_get_addr (void)
1051 {
1052 if (!gen_tls_tga)
1053 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1054 return gen_tls_tga;
1055 }
1056
1057 static GTY(()) rtx thread_pointer_rtx;
1058 static rtx
1059 gen_thread_pointer (void)
1060 {
1061 if (!thread_pointer_rtx)
1062 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1063 return thread_pointer_rtx;
1064 }
1065
1066 static rtx
1067 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
1068 rtx orig_op1, HOST_WIDE_INT addend)
1069 {
1070 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1071 rtx orig_op0 = op0;
1072 HOST_WIDE_INT addend_lo, addend_hi;
1073
1074 switch (tls_kind)
1075 {
1076 case TLS_MODEL_GLOBAL_DYNAMIC:
1077 start_sequence ();
1078
1079 tga_op1 = gen_reg_rtx (Pmode);
1080 emit_insn (gen_load_dtpmod (tga_op1, op1));
1081
1082 tga_op2 = gen_reg_rtx (Pmode);
1083 emit_insn (gen_load_dtprel (tga_op2, op1));
1084
1085 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1086 LCT_CONST, Pmode, 2, tga_op1,
1087 Pmode, tga_op2, Pmode);
1088
1089 insns = get_insns ();
1090 end_sequence ();
1091
1092 if (GET_MODE (op0) != Pmode)
1093 op0 = tga_ret;
1094 emit_libcall_block (insns, op0, tga_ret, op1);
1095 break;
1096
1097 case TLS_MODEL_LOCAL_DYNAMIC:
1098 /* ??? This isn't the completely proper way to do local-dynamic
1099 If the call to __tls_get_addr is used only by a single symbol,
1100 then we should (somehow) move the dtprel to the second arg
1101 to avoid the extra add. */
1102 start_sequence ();
1103
1104 tga_op1 = gen_reg_rtx (Pmode);
1105 emit_insn (gen_load_dtpmod (tga_op1, op1));
1106
1107 tga_op2 = const0_rtx;
1108
1109 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1110 LCT_CONST, Pmode, 2, tga_op1,
1111 Pmode, tga_op2, Pmode);
1112
1113 insns = get_insns ();
1114 end_sequence ();
1115
1116 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1117 UNSPEC_LD_BASE);
1118 tmp = gen_reg_rtx (Pmode);
1119 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1120
1121 if (!register_operand (op0, Pmode))
1122 op0 = gen_reg_rtx (Pmode);
1123 if (TARGET_TLS64)
1124 {
1125 emit_insn (gen_load_dtprel (op0, op1));
1126 emit_insn (gen_adddi3 (op0, tmp, op0));
1127 }
1128 else
1129 emit_insn (gen_add_dtprel (op0, op1, tmp));
1130 break;
1131
1132 case TLS_MODEL_INITIAL_EXEC:
1133 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1134 addend_hi = addend - addend_lo;
1135
1136 op1 = plus_constant (op1, addend_hi);
1137 addend = addend_lo;
1138
1139 tmp = gen_reg_rtx (Pmode);
1140 emit_insn (gen_load_tprel (tmp, op1));
1141
1142 if (!register_operand (op0, Pmode))
1143 op0 = gen_reg_rtx (Pmode);
1144 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
1145 break;
1146
1147 case TLS_MODEL_LOCAL_EXEC:
1148 if (!register_operand (op0, Pmode))
1149 op0 = gen_reg_rtx (Pmode);
1150
1151 op1 = orig_op1;
1152 addend = 0;
1153 if (TARGET_TLS64)
1154 {
1155 emit_insn (gen_load_tprel (op0, op1));
1156 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
1157 }
1158 else
1159 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
1160 break;
1161
1162 default:
1163 gcc_unreachable ();
1164 }
1165
1166 if (addend)
1167 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
1168 orig_op0, 1, OPTAB_DIRECT);
1169 if (orig_op0 == op0)
1170 return NULL_RTX;
1171 if (GET_MODE (orig_op0) == Pmode)
1172 return op0;
1173 return gen_lowpart (GET_MODE (orig_op0), op0);
1174 }
1175
1176 rtx
1177 ia64_expand_move (rtx op0, rtx op1)
1178 {
1179 enum machine_mode mode = GET_MODE (op0);
1180
1181 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1182 op1 = force_reg (mode, op1);
1183
1184 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1185 {
1186 HOST_WIDE_INT addend = 0;
1187 enum tls_model tls_kind;
1188 rtx sym = op1;
1189
1190 if (GET_CODE (op1) == CONST
1191 && GET_CODE (XEXP (op1, 0)) == PLUS
1192 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
1193 {
1194 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
1195 sym = XEXP (XEXP (op1, 0), 0);
1196 }
1197
1198 tls_kind = tls_symbolic_operand_type (sym);
1199 if (tls_kind)
1200 return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend);
1201
1202 if (any_offset_symbol_operand (sym, mode))
1203 addend = 0;
1204 else if (aligned_offset_symbol_operand (sym, mode))
1205 {
1206 HOST_WIDE_INT addend_lo, addend_hi;
1207
1208 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1209 addend_hi = addend - addend_lo;
1210
1211 if (addend_lo != 0)
1212 {
1213 op1 = plus_constant (sym, addend_hi);
1214 addend = addend_lo;
1215 }
1216 else
1217 addend = 0;
1218 }
1219 else
1220 op1 = sym;
1221
1222 if (reload_completed)
1223 {
1224 /* We really should have taken care of this offset earlier. */
1225 gcc_assert (addend == 0);
1226 if (ia64_expand_load_address (op0, op1))
1227 return NULL_RTX;
1228 }
1229
1230 if (addend)
1231 {
1232 rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode);
1233
1234 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1235
1236 op1 = expand_simple_binop (mode, PLUS, subtarget,
1237 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1238 if (op0 == op1)
1239 return NULL_RTX;
1240 }
1241 }
1242
1243 return op1;
1244 }
1245
1246 /* Split a move from OP1 to OP0 conditional on COND. */
1247
1248 void
1249 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1250 {
1251 rtx insn, first = get_last_insn ();
1252
1253 emit_move_insn (op0, op1);
1254
1255 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1256 if (INSN_P (insn))
1257 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1258 PATTERN (insn));
1259 }
1260
1261 /* Split a post-reload TImode or TFmode reference into two DImode
1262 components. This is made extra difficult by the fact that we do
1263 not get any scratch registers to work with, because reload cannot
1264 be prevented from giving us a scratch that overlaps the register
1265 pair involved. So instead, when addressing memory, we tweak the
1266 pointer register up and back down with POST_INCs. Or up and not
1267 back down when we can get away with it.
1268
1269 REVERSED is true when the loads must be done in reversed order
1270 (high word first) for correctness. DEAD is true when the pointer
1271 dies with the second insn we generate and therefore the second
1272 address must not carry a postmodify.
1273
1274 May return an insn which is to be emitted after the moves. */
1275
1276 static rtx
1277 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1278 {
1279 rtx fixup = 0;
1280
1281 switch (GET_CODE (in))
1282 {
1283 case REG:
1284 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1285 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1286 break;
1287
1288 case CONST_INT:
1289 case CONST_DOUBLE:
1290 /* Cannot occur reversed. */
1291 gcc_assert (!reversed);
1292
1293 if (GET_MODE (in) != TFmode)
1294 split_double (in, &out[0], &out[1]);
1295 else
1296 /* split_double does not understand how to split a TFmode
1297 quantity into a pair of DImode constants. */
1298 {
1299 REAL_VALUE_TYPE r;
1300 unsigned HOST_WIDE_INT p[2];
1301 long l[4]; /* TFmode is 128 bits */
1302
1303 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1304 real_to_target (l, &r, TFmode);
1305
1306 if (FLOAT_WORDS_BIG_ENDIAN)
1307 {
1308 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1309 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1310 }
1311 else
1312 {
1313 p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1314 p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1315 }
1316 out[0] = GEN_INT (p[0]);
1317 out[1] = GEN_INT (p[1]);
1318 }
1319 break;
1320
1321 case MEM:
1322 {
1323 rtx base = XEXP (in, 0);
1324 rtx offset;
1325
1326 switch (GET_CODE (base))
1327 {
1328 case REG:
1329 if (!reversed)
1330 {
1331 out[0] = adjust_automodify_address
1332 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1333 out[1] = adjust_automodify_address
1334 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1335 }
1336 else
1337 {
1338 /* Reversal requires a pre-increment, which can only
1339 be done as a separate insn. */
1340 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1341 out[0] = adjust_automodify_address
1342 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1343 out[1] = adjust_address (in, DImode, 0);
1344 }
1345 break;
1346
1347 case POST_INC:
1348 gcc_assert (!reversed && !dead);
1349
1350 /* Just do the increment in two steps. */
1351 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1352 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1353 break;
1354
1355 case POST_DEC:
1356 gcc_assert (!reversed && !dead);
1357
1358 /* Add 8, subtract 24. */
1359 base = XEXP (base, 0);
1360 out[0] = adjust_automodify_address
1361 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1362 out[1] = adjust_automodify_address
1363 (in, DImode,
1364 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1365 8);
1366 break;
1367
1368 case POST_MODIFY:
1369 gcc_assert (!reversed && !dead);
1370
1371 /* Extract and adjust the modification. This case is
1372 trickier than the others, because we might have an
1373 index register, or we might have a combined offset that
1374 doesn't fit a signed 9-bit displacement field. We can
1375 assume the incoming expression is already legitimate. */
1376 offset = XEXP (base, 1);
1377 base = XEXP (base, 0);
1378
1379 out[0] = adjust_automodify_address
1380 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1381
1382 if (GET_CODE (XEXP (offset, 1)) == REG)
1383 {
1384 /* Can't adjust the postmodify to match. Emit the
1385 original, then a separate addition insn. */
1386 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1387 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1388 }
1389 else
1390 {
1391 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1392 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1393 {
1394 /* Again the postmodify cannot be made to match,
1395 but in this case it's more efficient to get rid
1396 of the postmodify entirely and fix up with an
1397 add insn. */
1398 out[1] = adjust_automodify_address (in, DImode, base, 8);
1399 fixup = gen_adddi3
1400 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1401 }
1402 else
1403 {
1404 /* Combined offset still fits in the displacement field.
1405 (We cannot overflow it at the high end.) */
1406 out[1] = adjust_automodify_address
1407 (in, DImode, gen_rtx_POST_MODIFY
1408 (Pmode, base, gen_rtx_PLUS
1409 (Pmode, base,
1410 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1411 8);
1412 }
1413 }
1414 break;
1415
1416 default:
1417 gcc_unreachable ();
1418 }
1419 break;
1420 }
1421
1422 default:
1423 gcc_unreachable ();
1424 }
1425
1426 return fixup;
1427 }
1428
1429 /* Split a TImode or TFmode move instruction after reload.
1430 This is used by *movtf_internal and *movti_internal. */
1431 void
1432 ia64_split_tmode_move (rtx operands[])
1433 {
1434 rtx in[2], out[2], insn;
1435 rtx fixup[2];
1436 bool dead = false;
1437 bool reversed = false;
1438
1439 /* It is possible for reload to decide to overwrite a pointer with
1440 the value it points to. In that case we have to do the loads in
1441 the appropriate order so that the pointer is not destroyed too
1442 early. Also we must not generate a postmodify for that second
1443 load, or rws_access_regno will die. */
1444 if (GET_CODE (operands[1]) == MEM
1445 && reg_overlap_mentioned_p (operands[0], operands[1]))
1446 {
1447 rtx base = XEXP (operands[1], 0);
1448 while (GET_CODE (base) != REG)
1449 base = XEXP (base, 0);
1450
1451 if (REGNO (base) == REGNO (operands[0]))
1452 reversed = true;
1453 dead = true;
1454 }
1455 /* Another reason to do the moves in reversed order is if the first
1456 element of the target register pair is also the second element of
1457 the source register pair. */
1458 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1459 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1460 reversed = true;
1461
1462 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1463 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1464
1465 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1466 if (GET_CODE (EXP) == MEM \
1467 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1468 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1469 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1470 add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0))
1471
1472 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1473 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1474 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1475
1476 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1477 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1478 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1479
1480 if (fixup[0])
1481 emit_insn (fixup[0]);
1482 if (fixup[1])
1483 emit_insn (fixup[1]);
1484
1485 #undef MAYBE_ADD_REG_INC_NOTE
1486 }
1487
1488 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1489 through memory plus an extra GR scratch register. Except that you can
1490 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1491 SECONDARY_RELOAD_CLASS, but not both.
1492
1493 We got into problems in the first place by allowing a construct like
1494 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1495 This solution attempts to prevent this situation from occurring. When
1496 we see something like the above, we spill the inner register to memory. */
1497
1498 static rtx
1499 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1500 {
1501 if (GET_CODE (in) == SUBREG
1502 && GET_MODE (SUBREG_REG (in)) == TImode
1503 && GET_CODE (SUBREG_REG (in)) == REG)
1504 {
1505 rtx memt = assign_stack_temp (TImode, 16, 0);
1506 emit_move_insn (memt, SUBREG_REG (in));
1507 return adjust_address (memt, mode, 0);
1508 }
1509 else if (force && GET_CODE (in) == REG)
1510 {
1511 rtx memx = assign_stack_temp (mode, 16, 0);
1512 emit_move_insn (memx, in);
1513 return memx;
1514 }
1515 else
1516 return in;
1517 }
1518
1519 /* Expand the movxf or movrf pattern (MODE says which) with the given
1520 OPERANDS, returning true if the pattern should then invoke
1521 DONE. */
1522
1523 bool
1524 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1525 {
1526 rtx op0 = operands[0];
1527
1528 if (GET_CODE (op0) == SUBREG)
1529 op0 = SUBREG_REG (op0);
1530
1531 /* We must support XFmode loads into general registers for stdarg/vararg,
1532 unprototyped calls, and a rare case where a long double is passed as
1533 an argument after a float HFA fills the FP registers. We split them into
1534 DImode loads for convenience. We also need to support XFmode stores
1535 for the last case. This case does not happen for stdarg/vararg routines,
1536 because we do a block store to memory of unnamed arguments. */
1537
1538 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1539 {
1540 rtx out[2];
1541
1542 /* We're hoping to transform everything that deals with XFmode
1543 quantities and GR registers early in the compiler. */
1544 gcc_assert (can_create_pseudo_p ());
1545
1546 /* Struct to register can just use TImode instead. */
1547 if ((GET_CODE (operands[1]) == SUBREG
1548 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1549 || (GET_CODE (operands[1]) == REG
1550 && GR_REGNO_P (REGNO (operands[1]))))
1551 {
1552 rtx op1 = operands[1];
1553
1554 if (GET_CODE (op1) == SUBREG)
1555 op1 = SUBREG_REG (op1);
1556 else
1557 op1 = gen_rtx_REG (TImode, REGNO (op1));
1558
1559 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1560 return true;
1561 }
1562
1563 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1564 {
1565 /* Don't word-swap when reading in the constant. */
1566 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1567 operand_subword (operands[1], WORDS_BIG_ENDIAN,
1568 0, mode));
1569 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1570 operand_subword (operands[1], !WORDS_BIG_ENDIAN,
1571 0, mode));
1572 return true;
1573 }
1574
1575 /* If the quantity is in a register not known to be GR, spill it. */
1576 if (register_operand (operands[1], mode))
1577 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1578
1579 gcc_assert (GET_CODE (operands[1]) == MEM);
1580
1581 /* Don't word-swap when reading in the value. */
1582 out[0] = gen_rtx_REG (DImode, REGNO (op0));
1583 out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1584
1585 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1586 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1587 return true;
1588 }
1589
1590 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1591 {
1592 /* We're hoping to transform everything that deals with XFmode
1593 quantities and GR registers early in the compiler. */
1594 gcc_assert (can_create_pseudo_p ());
1595
1596 /* Op0 can't be a GR_REG here, as that case is handled above.
1597 If op0 is a register, then we spill op1, so that we now have a
1598 MEM operand. This requires creating an XFmode subreg of a TImode reg
1599 to force the spill. */
1600 if (register_operand (operands[0], mode))
1601 {
1602 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1603 op1 = gen_rtx_SUBREG (mode, op1, 0);
1604 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1605 }
1606
1607 else
1608 {
1609 rtx in[2];
1610
1611 gcc_assert (GET_CODE (operands[0]) == MEM);
1612
1613 /* Don't word-swap when writing out the value. */
1614 in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
1615 in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1616
1617 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1618 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1619 return true;
1620 }
1621 }
1622
1623 if (!reload_in_progress && !reload_completed)
1624 {
1625 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1626
1627 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1628 {
1629 rtx memt, memx, in = operands[1];
1630 if (CONSTANT_P (in))
1631 in = validize_mem (force_const_mem (mode, in));
1632 if (GET_CODE (in) == MEM)
1633 memt = adjust_address (in, TImode, 0);
1634 else
1635 {
1636 memt = assign_stack_temp (TImode, 16, 0);
1637 memx = adjust_address (memt, mode, 0);
1638 emit_move_insn (memx, in);
1639 }
1640 emit_move_insn (op0, memt);
1641 return true;
1642 }
1643
1644 if (!ia64_move_ok (operands[0], operands[1]))
1645 operands[1] = force_reg (mode, operands[1]);
1646 }
1647
1648 return false;
1649 }
1650
1651 /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
1652 with the expression that holds the compare result (in VOIDmode). */
1653
1654 static GTY(()) rtx cmptf_libfunc;
1655
1656 void
1657 ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
1658 {
1659 enum rtx_code code = GET_CODE (*expr);
1660 rtx cmp;
1661
1662 /* If we have a BImode input, then we already have a compare result, and
1663 do not need to emit another comparison. */
1664 if (GET_MODE (*op0) == BImode)
1665 {
1666 gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
1667 cmp = *op0;
1668 }
1669 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1670 magic number as its third argument, that indicates what to do.
1671 The return value is an integer to be compared against zero. */
1672 else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
1673 {
1674 enum qfcmp_magic {
1675 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1676 QCMP_UNORD = 2,
1677 QCMP_EQ = 4,
1678 QCMP_LT = 8,
1679 QCMP_GT = 16
1680 };
1681 int magic;
1682 enum rtx_code ncode;
1683 rtx ret, insns;
1684
1685 gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
1686 switch (code)
1687 {
1688 /* 1 = equal, 0 = not equal. Equality operators do
1689 not raise FP_INVALID when given an SNaN operand. */
1690 case EQ: magic = QCMP_EQ; ncode = NE; break;
1691 case NE: magic = QCMP_EQ; ncode = EQ; break;
1692 /* isunordered() from C99. */
1693 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1694 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1695 /* Relational operators raise FP_INVALID when given
1696 an SNaN operand. */
1697 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1698 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1699 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1700 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1701 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1702 Expanders for buneq etc. weuld have to be added to ia64.md
1703 for this to be useful. */
1704 default: gcc_unreachable ();
1705 }
1706
1707 start_sequence ();
1708
1709 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1710 *op0, TFmode, *op1, TFmode,
1711 GEN_INT (magic), DImode);
1712 cmp = gen_reg_rtx (BImode);
1713 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1714 gen_rtx_fmt_ee (ncode, BImode,
1715 ret, const0_rtx)));
1716
1717 insns = get_insns ();
1718 end_sequence ();
1719
1720 emit_libcall_block (insns, cmp, cmp,
1721 gen_rtx_fmt_ee (code, BImode, *op0, *op1));
1722 code = NE;
1723 }
1724 else
1725 {
1726 cmp = gen_reg_rtx (BImode);
1727 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1728 gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
1729 code = NE;
1730 }
1731
1732 *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
1733 *op0 = cmp;
1734 *op1 = const0_rtx;
1735 }
1736
1737 /* Generate an integral vector comparison. Return true if the condition has
1738 been reversed, and so the sense of the comparison should be inverted. */
1739
1740 static bool
1741 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1742 rtx dest, rtx op0, rtx op1)
1743 {
1744 bool negate = false;
1745 rtx x;
1746
1747 /* Canonicalize the comparison to EQ, GT, GTU. */
1748 switch (code)
1749 {
1750 case EQ:
1751 case GT:
1752 case GTU:
1753 break;
1754
1755 case NE:
1756 case LE:
1757 case LEU:
1758 code = reverse_condition (code);
1759 negate = true;
1760 break;
1761
1762 case GE:
1763 case GEU:
1764 code = reverse_condition (code);
1765 negate = true;
1766 /* FALLTHRU */
1767
1768 case LT:
1769 case LTU:
1770 code = swap_condition (code);
1771 x = op0, op0 = op1, op1 = x;
1772 break;
1773
1774 default:
1775 gcc_unreachable ();
1776 }
1777
1778 /* Unsigned parallel compare is not supported by the hardware. Play some
1779 tricks to turn this into a signed comparison against 0. */
1780 if (code == GTU)
1781 {
1782 switch (mode)
1783 {
1784 case V2SImode:
1785 {
1786 rtx t1, t2, mask;
1787
1788 /* Subtract (-(INT MAX) - 1) from both operands to make
1789 them signed. */
1790 mask = GEN_INT (0x80000000);
1791 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1792 mask = force_reg (mode, mask);
1793 t1 = gen_reg_rtx (mode);
1794 emit_insn (gen_subv2si3 (t1, op0, mask));
1795 t2 = gen_reg_rtx (mode);
1796 emit_insn (gen_subv2si3 (t2, op1, mask));
1797 op0 = t1;
1798 op1 = t2;
1799 code = GT;
1800 }
1801 break;
1802
1803 case V8QImode:
1804 case V4HImode:
1805 /* Perform a parallel unsigned saturating subtraction. */
1806 x = gen_reg_rtx (mode);
1807 emit_insn (gen_rtx_SET (VOIDmode, x,
1808 gen_rtx_US_MINUS (mode, op0, op1)));
1809
1810 code = EQ;
1811 op0 = x;
1812 op1 = CONST0_RTX (mode);
1813 negate = !negate;
1814 break;
1815
1816 default:
1817 gcc_unreachable ();
1818 }
1819 }
1820
1821 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1822 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1823
1824 return negate;
1825 }
1826
1827 /* Emit an integral vector conditional move. */
1828
1829 void
1830 ia64_expand_vecint_cmov (rtx operands[])
1831 {
1832 enum machine_mode mode = GET_MODE (operands[0]);
1833 enum rtx_code code = GET_CODE (operands[3]);
1834 bool negate;
1835 rtx cmp, x, ot, of;
1836
1837 cmp = gen_reg_rtx (mode);
1838 negate = ia64_expand_vecint_compare (code, mode, cmp,
1839 operands[4], operands[5]);
1840
1841 ot = operands[1+negate];
1842 of = operands[2-negate];
1843
1844 if (ot == CONST0_RTX (mode))
1845 {
1846 if (of == CONST0_RTX (mode))
1847 {
1848 emit_move_insn (operands[0], ot);
1849 return;
1850 }
1851
1852 x = gen_rtx_NOT (mode, cmp);
1853 x = gen_rtx_AND (mode, x, of);
1854 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1855 }
1856 else if (of == CONST0_RTX (mode))
1857 {
1858 x = gen_rtx_AND (mode, cmp, ot);
1859 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1860 }
1861 else
1862 {
1863 rtx t, f;
1864
1865 t = gen_reg_rtx (mode);
1866 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1867 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1868
1869 f = gen_reg_rtx (mode);
1870 x = gen_rtx_NOT (mode, cmp);
1871 x = gen_rtx_AND (mode, x, operands[2-negate]);
1872 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1873
1874 x = gen_rtx_IOR (mode, t, f);
1875 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1876 }
1877 }
1878
1879 /* Emit an integral vector min or max operation. Return true if all done. */
1880
1881 bool
1882 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1883 rtx operands[])
1884 {
1885 rtx xops[6];
1886
1887 /* These four combinations are supported directly. */
1888 if (mode == V8QImode && (code == UMIN || code == UMAX))
1889 return false;
1890 if (mode == V4HImode && (code == SMIN || code == SMAX))
1891 return false;
1892
1893 /* This combination can be implemented with only saturating subtraction. */
1894 if (mode == V4HImode && code == UMAX)
1895 {
1896 rtx x, tmp = gen_reg_rtx (mode);
1897
1898 x = gen_rtx_US_MINUS (mode, operands[1], operands[2]);
1899 emit_insn (gen_rtx_SET (VOIDmode, tmp, x));
1900
1901 emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2]));
1902 return true;
1903 }
1904
1905 /* Everything else implemented via vector comparisons. */
1906 xops[0] = operands[0];
1907 xops[4] = xops[1] = operands[1];
1908 xops[5] = xops[2] = operands[2];
1909
1910 switch (code)
1911 {
1912 case UMIN:
1913 code = LTU;
1914 break;
1915 case UMAX:
1916 code = GTU;
1917 break;
1918 case SMIN:
1919 code = LT;
1920 break;
1921 case SMAX:
1922 code = GT;
1923 break;
1924 default:
1925 gcc_unreachable ();
1926 }
1927 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1928
1929 ia64_expand_vecint_cmov (xops);
1930 return true;
1931 }
1932
1933 /* Emit an integral vector widening sum operations. */
1934
1935 void
1936 ia64_expand_widen_sum (rtx operands[3], bool unsignedp)
1937 {
1938 rtx l, h, x, s;
1939 enum machine_mode wmode, mode;
1940 rtx (*unpack_l) (rtx, rtx, rtx);
1941 rtx (*unpack_h) (rtx, rtx, rtx);
1942 rtx (*plus) (rtx, rtx, rtx);
1943
1944 wmode = GET_MODE (operands[0]);
1945 mode = GET_MODE (operands[1]);
1946
1947 switch (mode)
1948 {
1949 case V8QImode:
1950 unpack_l = gen_unpack1_l;
1951 unpack_h = gen_unpack1_h;
1952 plus = gen_addv4hi3;
1953 break;
1954 case V4HImode:
1955 unpack_l = gen_unpack2_l;
1956 unpack_h = gen_unpack2_h;
1957 plus = gen_addv2si3;
1958 break;
1959 default:
1960 gcc_unreachable ();
1961 }
1962
1963 /* Fill in x with the sign extension of each element in op1. */
1964 if (unsignedp)
1965 x = CONST0_RTX (mode);
1966 else
1967 {
1968 bool neg;
1969
1970 x = gen_reg_rtx (mode);
1971
1972 neg = ia64_expand_vecint_compare (LT, mode, x, operands[1],
1973 CONST0_RTX (mode));
1974 gcc_assert (!neg);
1975 }
1976
1977 l = gen_reg_rtx (wmode);
1978 h = gen_reg_rtx (wmode);
1979 s = gen_reg_rtx (wmode);
1980
1981 emit_insn (unpack_l (gen_lowpart (mode, l), operands[1], x));
1982 emit_insn (unpack_h (gen_lowpart (mode, h), operands[1], x));
1983 emit_insn (plus (s, l, operands[2]));
1984 emit_insn (plus (operands[0], h, s));
1985 }
1986
1987 /* Emit a signed or unsigned V8QI dot product operation. */
1988
1989 void
1990 ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp)
1991 {
1992 rtx l1, l2, h1, h2, x1, x2, p1, p2, p3, p4, s1, s2, s3;
1993
1994 /* Fill in x1 and x2 with the sign extension of each element. */
1995 if (unsignedp)
1996 x1 = x2 = CONST0_RTX (V8QImode);
1997 else
1998 {
1999 bool neg;
2000
2001 x1 = gen_reg_rtx (V8QImode);
2002 x2 = gen_reg_rtx (V8QImode);
2003
2004 neg = ia64_expand_vecint_compare (LT, V8QImode, x1, operands[1],
2005 CONST0_RTX (V8QImode));
2006 gcc_assert (!neg);
2007 neg = ia64_expand_vecint_compare (LT, V8QImode, x2, operands[2],
2008 CONST0_RTX (V8QImode));
2009 gcc_assert (!neg);
2010 }
2011
2012 l1 = gen_reg_rtx (V4HImode);
2013 l2 = gen_reg_rtx (V4HImode);
2014 h1 = gen_reg_rtx (V4HImode);
2015 h2 = gen_reg_rtx (V4HImode);
2016
2017 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l1), operands[1], x1));
2018 emit_insn (gen_unpack1_l (gen_lowpart (V8QImode, l2), operands[2], x2));
2019 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h1), operands[1], x1));
2020 emit_insn (gen_unpack1_h (gen_lowpart (V8QImode, h2), operands[2], x2));
2021
2022 p1 = gen_reg_rtx (V2SImode);
2023 p2 = gen_reg_rtx (V2SImode);
2024 p3 = gen_reg_rtx (V2SImode);
2025 p4 = gen_reg_rtx (V2SImode);
2026 emit_insn (gen_pmpy2_r (p1, l1, l2));
2027 emit_insn (gen_pmpy2_l (p2, l1, l2));
2028 emit_insn (gen_pmpy2_r (p3, h1, h2));
2029 emit_insn (gen_pmpy2_l (p4, h1, h2));
2030
2031 s1 = gen_reg_rtx (V2SImode);
2032 s2 = gen_reg_rtx (V2SImode);
2033 s3 = gen_reg_rtx (V2SImode);
2034 emit_insn (gen_addv2si3 (s1, p1, p2));
2035 emit_insn (gen_addv2si3 (s2, p3, p4));
2036 emit_insn (gen_addv2si3 (s3, s1, operands[3]));
2037 emit_insn (gen_addv2si3 (operands[0], s2, s3));
2038 }
2039
2040 /* Emit the appropriate sequence for a call. */
2041
2042 void
2043 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
2044 int sibcall_p)
2045 {
2046 rtx insn, b0;
2047
2048 addr = XEXP (addr, 0);
2049 addr = convert_memory_address (DImode, addr);
2050 b0 = gen_rtx_REG (DImode, R_BR (0));
2051
2052 /* ??? Should do this for functions known to bind local too. */
2053 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2054 {
2055 if (sibcall_p)
2056 insn = gen_sibcall_nogp (addr);
2057 else if (! retval)
2058 insn = gen_call_nogp (addr, b0);
2059 else
2060 insn = gen_call_value_nogp (retval, addr, b0);
2061 insn = emit_call_insn (insn);
2062 }
2063 else
2064 {
2065 if (sibcall_p)
2066 insn = gen_sibcall_gp (addr);
2067 else if (! retval)
2068 insn = gen_call_gp (addr, b0);
2069 else
2070 insn = gen_call_value_gp (retval, addr, b0);
2071 insn = emit_call_insn (insn);
2072
2073 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2074 }
2075
2076 if (sibcall_p)
2077 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
2078
2079 if (TARGET_ABI_OPEN_VMS)
2080 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2081 gen_rtx_REG (DImode, GR_REG (25)));
2082 }
2083
2084 static void
2085 reg_emitted (enum ia64_frame_regs r)
2086 {
2087 if (emitted_frame_related_regs[r] == 0)
2088 emitted_frame_related_regs[r] = current_frame_info.r[r];
2089 else
2090 gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]);
2091 }
2092
2093 static int
2094 get_reg (enum ia64_frame_regs r)
2095 {
2096 reg_emitted (r);
2097 return current_frame_info.r[r];
2098 }
2099
2100 static bool
2101 is_emitted (int regno)
2102 {
2103 unsigned int r;
2104
2105 for (r = reg_fp; r < number_of_ia64_frame_regs; r++)
2106 if (emitted_frame_related_regs[r] == regno)
2107 return true;
2108 return false;
2109 }
2110
2111 void
2112 ia64_reload_gp (void)
2113 {
2114 rtx tmp;
2115
2116 if (current_frame_info.r[reg_save_gp])
2117 {
2118 tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp));
2119 }
2120 else
2121 {
2122 HOST_WIDE_INT offset;
2123 rtx offset_r;
2124
2125 offset = (current_frame_info.spill_cfa_off
2126 + current_frame_info.spill_size);
2127 if (frame_pointer_needed)
2128 {
2129 tmp = hard_frame_pointer_rtx;
2130 offset = -offset;
2131 }
2132 else
2133 {
2134 tmp = stack_pointer_rtx;
2135 offset = current_frame_info.total_size - offset;
2136 }
2137
2138 offset_r = GEN_INT (offset);
2139 if (satisfies_constraint_I (offset_r))
2140 emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r));
2141 else
2142 {
2143 emit_move_insn (pic_offset_table_rtx, offset_r);
2144 emit_insn (gen_adddi3 (pic_offset_table_rtx,
2145 pic_offset_table_rtx, tmp));
2146 }
2147
2148 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
2149 }
2150
2151 emit_move_insn (pic_offset_table_rtx, tmp);
2152 }
2153
2154 void
2155 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
2156 rtx scratch_b, int noreturn_p, int sibcall_p)
2157 {
2158 rtx insn;
2159 bool is_desc = false;
2160
2161 /* If we find we're calling through a register, then we're actually
2162 calling through a descriptor, so load up the values. */
2163 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
2164 {
2165 rtx tmp;
2166 bool addr_dead_p;
2167
2168 /* ??? We are currently constrained to *not* use peep2, because
2169 we can legitimately change the global lifetime of the GP
2170 (in the form of killing where previously live). This is
2171 because a call through a descriptor doesn't use the previous
2172 value of the GP, while a direct call does, and we do not
2173 commit to either form until the split here.
2174
2175 That said, this means that we lack precise life info for
2176 whether ADDR is dead after this call. This is not terribly
2177 important, since we can fix things up essentially for free
2178 with the POST_DEC below, but it's nice to not use it when we
2179 can immediately tell it's not necessary. */
2180 addr_dead_p = ((noreturn_p || sibcall_p
2181 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
2182 REGNO (addr)))
2183 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
2184
2185 /* Load the code address into scratch_b. */
2186 tmp = gen_rtx_POST_INC (Pmode, addr);
2187 tmp = gen_rtx_MEM (Pmode, tmp);
2188 emit_move_insn (scratch_r, tmp);
2189 emit_move_insn (scratch_b, scratch_r);
2190
2191 /* Load the GP address. If ADDR is not dead here, then we must
2192 revert the change made above via the POST_INCREMENT. */
2193 if (!addr_dead_p)
2194 tmp = gen_rtx_POST_DEC (Pmode, addr);
2195 else
2196 tmp = addr;
2197 tmp = gen_rtx_MEM (Pmode, tmp);
2198 emit_move_insn (pic_offset_table_rtx, tmp);
2199
2200 is_desc = true;
2201 addr = scratch_b;
2202 }
2203
2204 if (sibcall_p)
2205 insn = gen_sibcall_nogp (addr);
2206 else if (retval)
2207 insn = gen_call_value_nogp (retval, addr, retaddr);
2208 else
2209 insn = gen_call_nogp (addr, retaddr);
2210 emit_call_insn (insn);
2211
2212 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
2213 ia64_reload_gp ();
2214 }
2215
2216 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
2217
2218 This differs from the generic code in that we know about the zero-extending
2219 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
2220 also know that ld.acq+cmpxchg.rel equals a full barrier.
2221
2222 The loop we want to generate looks like
2223
2224 cmp_reg = mem;
2225 label:
2226 old_reg = cmp_reg;
2227 new_reg = cmp_reg op val;
2228 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
2229 if (cmp_reg != old_reg)
2230 goto label;
2231
2232 Note that we only do the plain load from memory once. Subsequent
2233 iterations use the value loaded by the compare-and-swap pattern. */
2234
2235 void
2236 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
2237 rtx old_dst, rtx new_dst)
2238 {
2239 enum machine_mode mode = GET_MODE (mem);
2240 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
2241 enum insn_code icode;
2242
2243 /* Special case for using fetchadd. */
2244 if ((mode == SImode || mode == DImode)
2245 && (code == PLUS || code == MINUS)
2246 && fetchadd_operand (val, mode))
2247 {
2248 if (code == MINUS)
2249 val = GEN_INT (-INTVAL (val));
2250
2251 if (!old_dst)
2252 old_dst = gen_reg_rtx (mode);
2253
2254 emit_insn (gen_memory_barrier ());
2255
2256 if (mode == SImode)
2257 icode = CODE_FOR_fetchadd_acq_si;
2258 else
2259 icode = CODE_FOR_fetchadd_acq_di;
2260 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
2261
2262 if (new_dst)
2263 {
2264 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
2265 true, OPTAB_WIDEN);
2266 if (new_reg != new_dst)
2267 emit_move_insn (new_dst, new_reg);
2268 }
2269 return;
2270 }
2271
2272 /* Because of the volatile mem read, we get an ld.acq, which is the
2273 front half of the full barrier. The end half is the cmpxchg.rel. */
2274 gcc_assert (MEM_VOLATILE_P (mem));
2275
2276 old_reg = gen_reg_rtx (DImode);
2277 cmp_reg = gen_reg_rtx (DImode);
2278 label = gen_label_rtx ();
2279
2280 if (mode != DImode)
2281 {
2282 val = simplify_gen_subreg (DImode, val, mode, 0);
2283 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
2284 }
2285 else
2286 emit_move_insn (cmp_reg, mem);
2287
2288 emit_label (label);
2289
2290 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
2291 emit_move_insn (old_reg, cmp_reg);
2292 emit_move_insn (ar_ccv, cmp_reg);
2293
2294 if (old_dst)
2295 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
2296
2297 new_reg = cmp_reg;
2298 if (code == NOT)
2299 {
2300 new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX,
2301 true, OPTAB_DIRECT);
2302 new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true);
2303 }
2304 else
2305 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
2306 true, OPTAB_DIRECT);
2307
2308 if (mode != DImode)
2309 new_reg = gen_lowpart (mode, new_reg);
2310 if (new_dst)
2311 emit_move_insn (new_dst, new_reg);
2312
2313 switch (mode)
2314 {
2315 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
2316 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
2317 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
2318 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
2319 default:
2320 gcc_unreachable ();
2321 }
2322
2323 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
2324
2325 emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label);
2326 }
2327 \f
2328 /* Begin the assembly file. */
2329
2330 static void
2331 ia64_file_start (void)
2332 {
2333 /* Variable tracking should be run after all optimizations which change order
2334 of insns. It also needs a valid CFG. This can't be done in
2335 ia64_option_override, because flag_var_tracking is finalized after
2336 that. */
2337 ia64_flag_var_tracking = flag_var_tracking;
2338 flag_var_tracking = 0;
2339
2340 default_file_start ();
2341 emit_safe_across_calls ();
2342 }
2343
2344 void
2345 emit_safe_across_calls (void)
2346 {
2347 unsigned int rs, re;
2348 int out_state;
2349
2350 rs = 1;
2351 out_state = 0;
2352 while (1)
2353 {
2354 while (rs < 64 && call_used_regs[PR_REG (rs)])
2355 rs++;
2356 if (rs >= 64)
2357 break;
2358 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2359 continue;
2360 if (out_state == 0)
2361 {
2362 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2363 out_state = 1;
2364 }
2365 else
2366 fputc (',', asm_out_file);
2367 if (re == rs + 1)
2368 fprintf (asm_out_file, "p%u", rs);
2369 else
2370 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2371 rs = re + 1;
2372 }
2373 if (out_state)
2374 fputc ('\n', asm_out_file);
2375 }
2376
2377 /* Globalize a declaration. */
2378
2379 static void
2380 ia64_globalize_decl_name (FILE * stream, tree decl)
2381 {
2382 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2383 tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl));
2384 if (version_attr)
2385 {
2386 tree v = TREE_VALUE (TREE_VALUE (version_attr));
2387 const char *p = TREE_STRING_POINTER (v);
2388 fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p);
2389 }
2390 targetm.asm_out.globalize_label (stream, name);
2391 if (TREE_CODE (decl) == FUNCTION_DECL)
2392 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function");
2393 }
2394
2395 /* Helper function for ia64_compute_frame_size: find an appropriate general
2396 register to spill some special register to. SPECIAL_SPILL_MASK contains
2397 bits in GR0 to GR31 that have already been allocated by this routine.
2398 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2399
2400 static int
2401 find_gr_spill (enum ia64_frame_regs r, int try_locals)
2402 {
2403 int regno;
2404
2405 if (emitted_frame_related_regs[r] != 0)
2406 {
2407 regno = emitted_frame_related_regs[r];
2408 if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed)
2409 && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1)
2410 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2411 else if (current_function_is_leaf
2412 && regno >= GR_REG (1) && regno <= GR_REG (31))
2413 current_frame_info.gr_used_mask |= 1 << regno;
2414
2415 return regno;
2416 }
2417
2418 /* If this is a leaf function, first try an otherwise unused
2419 call-clobbered register. */
2420 if (current_function_is_leaf)
2421 {
2422 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2423 if (! df_regs_ever_live_p (regno)
2424 && call_used_regs[regno]
2425 && ! fixed_regs[regno]
2426 && ! global_regs[regno]
2427 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0
2428 && ! is_emitted (regno))
2429 {
2430 current_frame_info.gr_used_mask |= 1 << regno;
2431 return regno;
2432 }
2433 }
2434
2435 if (try_locals)
2436 {
2437 regno = current_frame_info.n_local_regs;
2438 /* If there is a frame pointer, then we can't use loc79, because
2439 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2440 reg_name switching code in ia64_expand_prologue. */
2441 while (regno < (80 - frame_pointer_needed))
2442 if (! is_emitted (LOC_REG (regno++)))
2443 {
2444 current_frame_info.n_local_regs = regno;
2445 return LOC_REG (regno - 1);
2446 }
2447 }
2448
2449 /* Failed to find a general register to spill to. Must use stack. */
2450 return 0;
2451 }
2452
2453 /* In order to make for nice schedules, we try to allocate every temporary
2454 to a different register. We must of course stay away from call-saved,
2455 fixed, and global registers. We must also stay away from registers
2456 allocated in current_frame_info.gr_used_mask, since those include regs
2457 used all through the prologue.
2458
2459 Any register allocated here must be used immediately. The idea is to
2460 aid scheduling, not to solve data flow problems. */
2461
2462 static int last_scratch_gr_reg;
2463
2464 static int
2465 next_scratch_gr_reg (void)
2466 {
2467 int i, regno;
2468
2469 for (i = 0; i < 32; ++i)
2470 {
2471 regno = (last_scratch_gr_reg + i + 1) & 31;
2472 if (call_used_regs[regno]
2473 && ! fixed_regs[regno]
2474 && ! global_regs[regno]
2475 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2476 {
2477 last_scratch_gr_reg = regno;
2478 return regno;
2479 }
2480 }
2481
2482 /* There must be _something_ available. */
2483 gcc_unreachable ();
2484 }
2485
2486 /* Helper function for ia64_compute_frame_size, called through
2487 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2488
2489 static void
2490 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2491 {
2492 unsigned int regno = REGNO (reg);
2493 if (regno < 32)
2494 {
2495 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2496 for (i = 0; i < n; ++i)
2497 current_frame_info.gr_used_mask |= 1 << (regno + i);
2498 }
2499 }
2500
2501
2502 /* Returns the number of bytes offset between the frame pointer and the stack
2503 pointer for the current function. SIZE is the number of bytes of space
2504 needed for local variables. */
2505
2506 static void
2507 ia64_compute_frame_size (HOST_WIDE_INT size)
2508 {
2509 HOST_WIDE_INT total_size;
2510 HOST_WIDE_INT spill_size = 0;
2511 HOST_WIDE_INT extra_spill_size = 0;
2512 HOST_WIDE_INT pretend_args_size;
2513 HARD_REG_SET mask;
2514 int n_spilled = 0;
2515 int spilled_gr_p = 0;
2516 int spilled_fr_p = 0;
2517 unsigned int regno;
2518 int min_regno;
2519 int max_regno;
2520 int i;
2521
2522 if (current_frame_info.initialized)
2523 return;
2524
2525 memset (&current_frame_info, 0, sizeof current_frame_info);
2526 CLEAR_HARD_REG_SET (mask);
2527
2528 /* Don't allocate scratches to the return register. */
2529 diddle_return_value (mark_reg_gr_used_mask, NULL);
2530
2531 /* Don't allocate scratches to the EH scratch registers. */
2532 if (cfun->machine->ia64_eh_epilogue_sp)
2533 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2534 if (cfun->machine->ia64_eh_epilogue_bsp)
2535 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2536
2537 /* Find the size of the register stack frame. We have only 80 local
2538 registers, because we reserve 8 for the inputs and 8 for the
2539 outputs. */
2540
2541 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2542 since we'll be adjusting that down later. */
2543 regno = LOC_REG (78) + ! frame_pointer_needed;
2544 for (; regno >= LOC_REG (0); regno--)
2545 if (df_regs_ever_live_p (regno) && !is_emitted (regno))
2546 break;
2547 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2548
2549 /* For functions marked with the syscall_linkage attribute, we must mark
2550 all eight input registers as in use, so that locals aren't visible to
2551 the caller. */
2552
2553 if (cfun->machine->n_varargs > 0
2554 || lookup_attribute ("syscall_linkage",
2555 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2556 current_frame_info.n_input_regs = 8;
2557 else
2558 {
2559 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2560 if (df_regs_ever_live_p (regno))
2561 break;
2562 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2563 }
2564
2565 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2566 if (df_regs_ever_live_p (regno))
2567 break;
2568 i = regno - OUT_REG (0) + 1;
2569
2570 #ifndef PROFILE_HOOK
2571 /* When -p profiling, we need one output register for the mcount argument.
2572 Likewise for -a profiling for the bb_init_func argument. For -ax
2573 profiling, we need two output registers for the two bb_init_trace_func
2574 arguments. */
2575 if (crtl->profile)
2576 i = MAX (i, 1);
2577 #endif
2578 current_frame_info.n_output_regs = i;
2579
2580 /* ??? No rotating register support yet. */
2581 current_frame_info.n_rotate_regs = 0;
2582
2583 /* Discover which registers need spilling, and how much room that
2584 will take. Begin with floating point and general registers,
2585 which will always wind up on the stack. */
2586
2587 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2588 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2589 {
2590 SET_HARD_REG_BIT (mask, regno);
2591 spill_size += 16;
2592 n_spilled += 1;
2593 spilled_fr_p = 1;
2594 }
2595
2596 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2597 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2598 {
2599 SET_HARD_REG_BIT (mask, regno);
2600 spill_size += 8;
2601 n_spilled += 1;
2602 spilled_gr_p = 1;
2603 }
2604
2605 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2606 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2607 {
2608 SET_HARD_REG_BIT (mask, regno);
2609 spill_size += 8;
2610 n_spilled += 1;
2611 }
2612
2613 /* Now come all special registers that might get saved in other
2614 general registers. */
2615
2616 if (frame_pointer_needed)
2617 {
2618 current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1);
2619 /* If we did not get a register, then we take LOC79. This is guaranteed
2620 to be free, even if regs_ever_live is already set, because this is
2621 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2622 as we don't count loc79 above. */
2623 if (current_frame_info.r[reg_fp] == 0)
2624 {
2625 current_frame_info.r[reg_fp] = LOC_REG (79);
2626 current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1;
2627 }
2628 }
2629
2630 if (! current_function_is_leaf)
2631 {
2632 /* Emit a save of BR0 if we call other functions. Do this even
2633 if this function doesn't return, as EH depends on this to be
2634 able to unwind the stack. */
2635 SET_HARD_REG_BIT (mask, BR_REG (0));
2636
2637 current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1);
2638 if (current_frame_info.r[reg_save_b0] == 0)
2639 {
2640 extra_spill_size += 8;
2641 n_spilled += 1;
2642 }
2643
2644 /* Similarly for ar.pfs. */
2645 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2646 current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1);
2647 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2648 {
2649 extra_spill_size += 8;
2650 n_spilled += 1;
2651 }
2652
2653 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2654 registers are clobbered, so we fall back to the stack. */
2655 current_frame_info.r[reg_save_gp]
2656 = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1));
2657 if (current_frame_info.r[reg_save_gp] == 0)
2658 {
2659 SET_HARD_REG_BIT (mask, GR_REG (1));
2660 spill_size += 8;
2661 n_spilled += 1;
2662 }
2663 }
2664 else
2665 {
2666 if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)])
2667 {
2668 SET_HARD_REG_BIT (mask, BR_REG (0));
2669 extra_spill_size += 8;
2670 n_spilled += 1;
2671 }
2672
2673 if (df_regs_ever_live_p (AR_PFS_REGNUM))
2674 {
2675 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2676 current_frame_info.r[reg_save_ar_pfs]
2677 = find_gr_spill (reg_save_ar_pfs, 1);
2678 if (current_frame_info.r[reg_save_ar_pfs] == 0)
2679 {
2680 extra_spill_size += 8;
2681 n_spilled += 1;
2682 }
2683 }
2684 }
2685
2686 /* Unwind descriptor hackery: things are most efficient if we allocate
2687 consecutive GR save registers for RP, PFS, FP in that order. However,
2688 it is absolutely critical that FP get the only hard register that's
2689 guaranteed to be free, so we allocated it first. If all three did
2690 happen to be allocated hard regs, and are consecutive, rearrange them
2691 into the preferred order now.
2692
2693 If we have already emitted code for any of those registers,
2694 then it's already too late to change. */
2695 min_regno = MIN (current_frame_info.r[reg_fp],
2696 MIN (current_frame_info.r[reg_save_b0],
2697 current_frame_info.r[reg_save_ar_pfs]));
2698 max_regno = MAX (current_frame_info.r[reg_fp],
2699 MAX (current_frame_info.r[reg_save_b0],
2700 current_frame_info.r[reg_save_ar_pfs]));
2701 if (min_regno > 0
2702 && min_regno + 2 == max_regno
2703 && (current_frame_info.r[reg_fp] == min_regno + 1
2704 || current_frame_info.r[reg_save_b0] == min_regno + 1
2705 || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1)
2706 && (emitted_frame_related_regs[reg_save_b0] == 0
2707 || emitted_frame_related_regs[reg_save_b0] == min_regno)
2708 && (emitted_frame_related_regs[reg_save_ar_pfs] == 0
2709 || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1)
2710 && (emitted_frame_related_regs[reg_fp] == 0
2711 || emitted_frame_related_regs[reg_fp] == min_regno + 2))
2712 {
2713 current_frame_info.r[reg_save_b0] = min_regno;
2714 current_frame_info.r[reg_save_ar_pfs] = min_regno + 1;
2715 current_frame_info.r[reg_fp] = min_regno + 2;
2716 }
2717
2718 /* See if we need to store the predicate register block. */
2719 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2720 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
2721 break;
2722 if (regno <= PR_REG (63))
2723 {
2724 SET_HARD_REG_BIT (mask, PR_REG (0));
2725 current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1);
2726 if (current_frame_info.r[reg_save_pr] == 0)
2727 {
2728 extra_spill_size += 8;
2729 n_spilled += 1;
2730 }
2731
2732 /* ??? Mark them all as used so that register renaming and such
2733 are free to use them. */
2734 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2735 df_set_regs_ever_live (regno, true);
2736 }
2737
2738 /* If we're forced to use st8.spill, we're forced to save and restore
2739 ar.unat as well. The check for existing liveness allows inline asm
2740 to touch ar.unat. */
2741 if (spilled_gr_p || cfun->machine->n_varargs
2742 || df_regs_ever_live_p (AR_UNAT_REGNUM))
2743 {
2744 df_set_regs_ever_live (AR_UNAT_REGNUM, true);
2745 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2746 current_frame_info.r[reg_save_ar_unat]
2747 = find_gr_spill (reg_save_ar_unat, spill_size == 0);
2748 if (current_frame_info.r[reg_save_ar_unat] == 0)
2749 {
2750 extra_spill_size += 8;
2751 n_spilled += 1;
2752 }
2753 }
2754
2755 if (df_regs_ever_live_p (AR_LC_REGNUM))
2756 {
2757 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2758 current_frame_info.r[reg_save_ar_lc]
2759 = find_gr_spill (reg_save_ar_lc, spill_size == 0);
2760 if (current_frame_info.r[reg_save_ar_lc] == 0)
2761 {
2762 extra_spill_size += 8;
2763 n_spilled += 1;
2764 }
2765 }
2766
2767 /* If we have an odd number of words of pretend arguments written to
2768 the stack, then the FR save area will be unaligned. We round the
2769 size of this area up to keep things 16 byte aligned. */
2770 if (spilled_fr_p)
2771 pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size);
2772 else
2773 pretend_args_size = crtl->args.pretend_args_size;
2774
2775 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2776 + crtl->outgoing_args_size);
2777 total_size = IA64_STACK_ALIGN (total_size);
2778
2779 /* We always use the 16-byte scratch area provided by the caller, but
2780 if we are a leaf function, there's no one to which we need to provide
2781 a scratch area. */
2782 if (current_function_is_leaf)
2783 total_size = MAX (0, total_size - 16);
2784
2785 current_frame_info.total_size = total_size;
2786 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2787 current_frame_info.spill_size = spill_size;
2788 current_frame_info.extra_spill_size = extra_spill_size;
2789 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2790 current_frame_info.n_spilled = n_spilled;
2791 current_frame_info.initialized = reload_completed;
2792 }
2793
2794 /* Worker function for TARGET_CAN_ELIMINATE. */
2795
2796 bool
2797 ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
2798 {
2799 return (to == BR_REG (0) ? current_function_is_leaf : true);
2800 }
2801
2802 /* Compute the initial difference between the specified pair of registers. */
2803
2804 HOST_WIDE_INT
2805 ia64_initial_elimination_offset (int from, int to)
2806 {
2807 HOST_WIDE_INT offset;
2808
2809 ia64_compute_frame_size (get_frame_size ());
2810 switch (from)
2811 {
2812 case FRAME_POINTER_REGNUM:
2813 switch (to)
2814 {
2815 case HARD_FRAME_POINTER_REGNUM:
2816 if (current_function_is_leaf)
2817 offset = -current_frame_info.total_size;
2818 else
2819 offset = -(current_frame_info.total_size
2820 - crtl->outgoing_args_size - 16);
2821 break;
2822
2823 case STACK_POINTER_REGNUM:
2824 if (current_function_is_leaf)
2825 offset = 0;
2826 else
2827 offset = 16 + crtl->outgoing_args_size;
2828 break;
2829
2830 default:
2831 gcc_unreachable ();
2832 }
2833 break;
2834
2835 case ARG_POINTER_REGNUM:
2836 /* Arguments start above the 16 byte save area, unless stdarg
2837 in which case we store through the 16 byte save area. */
2838 switch (to)
2839 {
2840 case HARD_FRAME_POINTER_REGNUM:
2841 offset = 16 - crtl->args.pretend_args_size;
2842 break;
2843
2844 case STACK_POINTER_REGNUM:
2845 offset = (current_frame_info.total_size
2846 + 16 - crtl->args.pretend_args_size);
2847 break;
2848
2849 default:
2850 gcc_unreachable ();
2851 }
2852 break;
2853
2854 default:
2855 gcc_unreachable ();
2856 }
2857
2858 return offset;
2859 }
2860
2861 /* If there are more than a trivial number of register spills, we use
2862 two interleaved iterators so that we can get two memory references
2863 per insn group.
2864
2865 In order to simplify things in the prologue and epilogue expanders,
2866 we use helper functions to fix up the memory references after the
2867 fact with the appropriate offsets to a POST_MODIFY memory mode.
2868 The following data structure tracks the state of the two iterators
2869 while insns are being emitted. */
2870
2871 struct spill_fill_data
2872 {
2873 rtx init_after; /* point at which to emit initializations */
2874 rtx init_reg[2]; /* initial base register */
2875 rtx iter_reg[2]; /* the iterator registers */
2876 rtx *prev_addr[2]; /* address of last memory use */
2877 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2878 HOST_WIDE_INT prev_off[2]; /* last offset */
2879 int n_iter; /* number of iterators in use */
2880 int next_iter; /* next iterator to use */
2881 unsigned int save_gr_used_mask;
2882 };
2883
2884 static struct spill_fill_data spill_fill_data;
2885
2886 static void
2887 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2888 {
2889 int i;
2890
2891 spill_fill_data.init_after = get_last_insn ();
2892 spill_fill_data.init_reg[0] = init_reg;
2893 spill_fill_data.init_reg[1] = init_reg;
2894 spill_fill_data.prev_addr[0] = NULL;
2895 spill_fill_data.prev_addr[1] = NULL;
2896 spill_fill_data.prev_insn[0] = NULL;
2897 spill_fill_data.prev_insn[1] = NULL;
2898 spill_fill_data.prev_off[0] = cfa_off;
2899 spill_fill_data.prev_off[1] = cfa_off;
2900 spill_fill_data.next_iter = 0;
2901 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2902
2903 spill_fill_data.n_iter = 1 + (n_spills > 2);
2904 for (i = 0; i < spill_fill_data.n_iter; ++i)
2905 {
2906 int regno = next_scratch_gr_reg ();
2907 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2908 current_frame_info.gr_used_mask |= 1 << regno;
2909 }
2910 }
2911
2912 static void
2913 finish_spill_pointers (void)
2914 {
2915 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2916 }
2917
2918 static rtx
2919 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2920 {
2921 int iter = spill_fill_data.next_iter;
2922 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2923 rtx disp_rtx = GEN_INT (disp);
2924 rtx mem;
2925
2926 if (spill_fill_data.prev_addr[iter])
2927 {
2928 if (satisfies_constraint_N (disp_rtx))
2929 {
2930 *spill_fill_data.prev_addr[iter]
2931 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2932 gen_rtx_PLUS (DImode,
2933 spill_fill_data.iter_reg[iter],
2934 disp_rtx));
2935 add_reg_note (spill_fill_data.prev_insn[iter],
2936 REG_INC, spill_fill_data.iter_reg[iter]);
2937 }
2938 else
2939 {
2940 /* ??? Could use register post_modify for loads. */
2941 if (!satisfies_constraint_I (disp_rtx))
2942 {
2943 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2944 emit_move_insn (tmp, disp_rtx);
2945 disp_rtx = tmp;
2946 }
2947 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2948 spill_fill_data.iter_reg[iter], disp_rtx));
2949 }
2950 }
2951 /* Micro-optimization: if we've created a frame pointer, it's at
2952 CFA 0, which may allow the real iterator to be initialized lower,
2953 slightly increasing parallelism. Also, if there are few saves
2954 it may eliminate the iterator entirely. */
2955 else if (disp == 0
2956 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2957 && frame_pointer_needed)
2958 {
2959 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2960 set_mem_alias_set (mem, get_varargs_alias_set ());
2961 return mem;
2962 }
2963 else
2964 {
2965 rtx seq, insn;
2966
2967 if (disp == 0)
2968 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2969 spill_fill_data.init_reg[iter]);
2970 else
2971 {
2972 start_sequence ();
2973
2974 if (!satisfies_constraint_I (disp_rtx))
2975 {
2976 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2977 emit_move_insn (tmp, disp_rtx);
2978 disp_rtx = tmp;
2979 }
2980
2981 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2982 spill_fill_data.init_reg[iter],
2983 disp_rtx));
2984
2985 seq = get_insns ();
2986 end_sequence ();
2987 }
2988
2989 /* Careful for being the first insn in a sequence. */
2990 if (spill_fill_data.init_after)
2991 insn = emit_insn_after (seq, spill_fill_data.init_after);
2992 else
2993 {
2994 rtx first = get_insns ();
2995 if (first)
2996 insn = emit_insn_before (seq, first);
2997 else
2998 insn = emit_insn (seq);
2999 }
3000 spill_fill_data.init_after = insn;
3001 }
3002
3003 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
3004
3005 /* ??? Not all of the spills are for varargs, but some of them are.
3006 The rest of the spills belong in an alias set of their own. But
3007 it doesn't actually hurt to include them here. */
3008 set_mem_alias_set (mem, get_varargs_alias_set ());
3009
3010 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
3011 spill_fill_data.prev_off[iter] = cfa_off;
3012
3013 if (++iter >= spill_fill_data.n_iter)
3014 iter = 0;
3015 spill_fill_data.next_iter = iter;
3016
3017 return mem;
3018 }
3019
3020 static void
3021 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
3022 rtx frame_reg)
3023 {
3024 int iter = spill_fill_data.next_iter;
3025 rtx mem, insn;
3026
3027 mem = spill_restore_mem (reg, cfa_off);
3028 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
3029 spill_fill_data.prev_insn[iter] = insn;
3030
3031 if (frame_reg)
3032 {
3033 rtx base;
3034 HOST_WIDE_INT off;
3035
3036 RTX_FRAME_RELATED_P (insn) = 1;
3037
3038 /* Don't even pretend that the unwind code can intuit its way
3039 through a pair of interleaved post_modify iterators. Just
3040 provide the correct answer. */
3041
3042 if (frame_pointer_needed)
3043 {
3044 base = hard_frame_pointer_rtx;
3045 off = - cfa_off;
3046 }
3047 else
3048 {
3049 base = stack_pointer_rtx;
3050 off = current_frame_info.total_size - cfa_off;
3051 }
3052
3053 add_reg_note (insn, REG_CFA_OFFSET,
3054 gen_rtx_SET (VOIDmode,
3055 gen_rtx_MEM (GET_MODE (reg),
3056 plus_constant (base, off)),
3057 frame_reg));
3058 }
3059 }
3060
3061 static void
3062 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
3063 {
3064 int iter = spill_fill_data.next_iter;
3065 rtx insn;
3066
3067 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
3068 GEN_INT (cfa_off)));
3069 spill_fill_data.prev_insn[iter] = insn;
3070 }
3071
3072 /* Wrapper functions that discards the CONST_INT spill offset. These
3073 exist so that we can give gr_spill/gr_fill the offset they need and
3074 use a consistent function interface. */
3075
3076 static rtx
3077 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3078 {
3079 return gen_movdi (dest, src);
3080 }
3081
3082 static rtx
3083 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3084 {
3085 return gen_fr_spill (dest, src);
3086 }
3087
3088 static rtx
3089 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
3090 {
3091 return gen_fr_restore (dest, src);
3092 }
3093
3094 /* Called after register allocation to add any instructions needed for the
3095 prologue. Using a prologue insn is favored compared to putting all of the
3096 instructions in output_function_prologue(), since it allows the scheduler
3097 to intermix instructions with the saves of the caller saved registers. In
3098 some cases, it might be necessary to emit a barrier instruction as the last
3099 insn to prevent such scheduling.
3100
3101 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
3102 so that the debug info generation code can handle them properly.
3103
3104 The register save area is layed out like so:
3105 cfa+16
3106 [ varargs spill area ]
3107 [ fr register spill area ]
3108 [ br register spill area ]
3109 [ ar register spill area ]
3110 [ pr register spill area ]
3111 [ gr register spill area ] */
3112
3113 /* ??? Get inefficient code when the frame size is larger than can fit in an
3114 adds instruction. */
3115
3116 void
3117 ia64_expand_prologue (void)
3118 {
3119 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
3120 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
3121 rtx reg, alt_reg;
3122
3123 ia64_compute_frame_size (get_frame_size ());
3124 last_scratch_gr_reg = 15;
3125
3126 if (flag_stack_usage)
3127 current_function_static_stack_size = current_frame_info.total_size;
3128
3129 if (dump_file)
3130 {
3131 fprintf (dump_file, "ia64 frame related registers "
3132 "recorded in current_frame_info.r[]:\n");
3133 #define PRINTREG(a) if (current_frame_info.r[a]) \
3134 fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a])
3135 PRINTREG(reg_fp);
3136 PRINTREG(reg_save_b0);
3137 PRINTREG(reg_save_pr);
3138 PRINTREG(reg_save_ar_pfs);
3139 PRINTREG(reg_save_ar_unat);
3140 PRINTREG(reg_save_ar_lc);
3141 PRINTREG(reg_save_gp);
3142 #undef PRINTREG
3143 }
3144
3145 /* If there is no epilogue, then we don't need some prologue insns.
3146 We need to avoid emitting the dead prologue insns, because flow
3147 will complain about them. */
3148 if (optimize)
3149 {
3150 edge e;
3151 edge_iterator ei;
3152
3153 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
3154 if ((e->flags & EDGE_FAKE) == 0
3155 && (e->flags & EDGE_FALLTHRU) != 0)
3156 break;
3157 epilogue_p = (e != NULL);
3158 }
3159 else
3160 epilogue_p = 1;
3161
3162 /* Set the local, input, and output register names. We need to do this
3163 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
3164 half. If we use in/loc/out register names, then we get assembler errors
3165 in crtn.S because there is no alloc insn or regstk directive in there. */
3166 if (! TARGET_REG_NAMES)
3167 {
3168 int inputs = current_frame_info.n_input_regs;
3169 int locals = current_frame_info.n_local_regs;
3170 int outputs = current_frame_info.n_output_regs;
3171
3172 for (i = 0; i < inputs; i++)
3173 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
3174 for (i = 0; i < locals; i++)
3175 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
3176 for (i = 0; i < outputs; i++)
3177 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
3178 }
3179
3180 /* Set the frame pointer register name. The regnum is logically loc79,
3181 but of course we'll not have allocated that many locals. Rather than
3182 worrying about renumbering the existing rtxs, we adjust the name. */
3183 /* ??? This code means that we can never use one local register when
3184 there is a frame pointer. loc79 gets wasted in this case, as it is
3185 renamed to a register that will never be used. See also the try_locals
3186 code in find_gr_spill. */
3187 if (current_frame_info.r[reg_fp])
3188 {
3189 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3190 reg_names[HARD_FRAME_POINTER_REGNUM]
3191 = reg_names[current_frame_info.r[reg_fp]];
3192 reg_names[current_frame_info.r[reg_fp]] = tmp;
3193 }
3194
3195 /* We don't need an alloc instruction if we've used no outputs or locals. */
3196 if (current_frame_info.n_local_regs == 0
3197 && current_frame_info.n_output_regs == 0
3198 && current_frame_info.n_input_regs <= crtl->args.info.int_regs
3199 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3200 {
3201 /* If there is no alloc, but there are input registers used, then we
3202 need a .regstk directive. */
3203 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
3204 ar_pfs_save_reg = NULL_RTX;
3205 }
3206 else
3207 {
3208 current_frame_info.need_regstk = 0;
3209
3210 if (current_frame_info.r[reg_save_ar_pfs])
3211 {
3212 regno = current_frame_info.r[reg_save_ar_pfs];
3213 reg_emitted (reg_save_ar_pfs);
3214 }
3215 else
3216 regno = next_scratch_gr_reg ();
3217 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
3218
3219 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
3220 GEN_INT (current_frame_info.n_input_regs),
3221 GEN_INT (current_frame_info.n_local_regs),
3222 GEN_INT (current_frame_info.n_output_regs),
3223 GEN_INT (current_frame_info.n_rotate_regs)));
3224 RTX_FRAME_RELATED_P (insn) = (current_frame_info.r[reg_save_ar_pfs] != 0);
3225 }
3226
3227 /* Set up frame pointer, stack pointer, and spill iterators. */
3228
3229 n_varargs = cfun->machine->n_varargs;
3230 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
3231 stack_pointer_rtx, 0);
3232
3233 if (frame_pointer_needed)
3234 {
3235 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3236 RTX_FRAME_RELATED_P (insn) = 1;
3237
3238 /* Force the unwind info to recognize this as defining a new CFA,
3239 rather than some temp register setup. */
3240 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX);
3241 }
3242
3243 if (current_frame_info.total_size != 0)
3244 {
3245 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
3246 rtx offset;
3247
3248 if (satisfies_constraint_I (frame_size_rtx))
3249 offset = frame_size_rtx;
3250 else
3251 {
3252 regno = next_scratch_gr_reg ();
3253 offset = gen_rtx_REG (DImode, regno);
3254 emit_move_insn (offset, frame_size_rtx);
3255 }
3256
3257 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
3258 stack_pointer_rtx, offset));
3259
3260 if (! frame_pointer_needed)
3261 {
3262 RTX_FRAME_RELATED_P (insn) = 1;
3263 add_reg_note (insn, REG_CFA_ADJUST_CFA,
3264 gen_rtx_SET (VOIDmode,
3265 stack_pointer_rtx,
3266 gen_rtx_PLUS (DImode,
3267 stack_pointer_rtx,
3268 frame_size_rtx)));
3269 }
3270
3271 /* ??? At this point we must generate a magic insn that appears to
3272 modify the stack pointer, the frame pointer, and all spill
3273 iterators. This would allow the most scheduling freedom. For
3274 now, just hard stop. */
3275 emit_insn (gen_blockage ());
3276 }
3277
3278 /* Must copy out ar.unat before doing any integer spills. */
3279 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3280 {
3281 if (current_frame_info.r[reg_save_ar_unat])
3282 {
3283 ar_unat_save_reg
3284 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3285 reg_emitted (reg_save_ar_unat);
3286 }
3287 else
3288 {
3289 alt_regno = next_scratch_gr_reg ();
3290 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3291 current_frame_info.gr_used_mask |= 1 << alt_regno;
3292 }
3293
3294 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3295 insn = emit_move_insn (ar_unat_save_reg, reg);
3296 if (current_frame_info.r[reg_save_ar_unat])
3297 {
3298 RTX_FRAME_RELATED_P (insn) = 1;
3299 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3300 }
3301
3302 /* Even if we're not going to generate an epilogue, we still
3303 need to save the register so that EH works. */
3304 if (! epilogue_p && current_frame_info.r[reg_save_ar_unat])
3305 emit_insn (gen_prologue_use (ar_unat_save_reg));
3306 }
3307 else
3308 ar_unat_save_reg = NULL_RTX;
3309
3310 /* Spill all varargs registers. Do this before spilling any GR registers,
3311 since we want the UNAT bits for the GR registers to override the UNAT
3312 bits from varargs, which we don't care about. */
3313
3314 cfa_off = -16;
3315 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
3316 {
3317 reg = gen_rtx_REG (DImode, regno);
3318 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
3319 }
3320
3321 /* Locate the bottom of the register save area. */
3322 cfa_off = (current_frame_info.spill_cfa_off
3323 + current_frame_info.spill_size
3324 + current_frame_info.extra_spill_size);
3325
3326 /* Save the predicate register block either in a register or in memory. */
3327 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3328 {
3329 reg = gen_rtx_REG (DImode, PR_REG (0));
3330 if (current_frame_info.r[reg_save_pr] != 0)
3331 {
3332 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3333 reg_emitted (reg_save_pr);
3334 insn = emit_move_insn (alt_reg, reg);
3335
3336 /* ??? Denote pr spill/fill by a DImode move that modifies all
3337 64 hard registers. */
3338 RTX_FRAME_RELATED_P (insn) = 1;
3339 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3340
3341 /* Even if we're not going to generate an epilogue, we still
3342 need to save the register so that EH works. */
3343 if (! epilogue_p)
3344 emit_insn (gen_prologue_use (alt_reg));
3345 }
3346 else
3347 {
3348 alt_regno = next_scratch_gr_reg ();
3349 alt_reg = gen_rtx_REG (DImode, alt_regno);
3350 insn = emit_move_insn (alt_reg, reg);
3351 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3352 cfa_off -= 8;
3353 }
3354 }
3355
3356 /* Handle AR regs in numerical order. All of them get special handling. */
3357 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
3358 && current_frame_info.r[reg_save_ar_unat] == 0)
3359 {
3360 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3361 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
3362 cfa_off -= 8;
3363 }
3364
3365 /* The alloc insn already copied ar.pfs into a general register. The
3366 only thing we have to do now is copy that register to a stack slot
3367 if we'd not allocated a local register for the job. */
3368 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
3369 && current_frame_info.r[reg_save_ar_pfs] == 0)
3370 {
3371 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3372 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
3373 cfa_off -= 8;
3374 }
3375
3376 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3377 {
3378 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3379 if (current_frame_info.r[reg_save_ar_lc] != 0)
3380 {
3381 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3382 reg_emitted (reg_save_ar_lc);
3383 insn = emit_move_insn (alt_reg, reg);
3384 RTX_FRAME_RELATED_P (insn) = 1;
3385 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3386
3387 /* Even if we're not going to generate an epilogue, we still
3388 need to save the register so that EH works. */
3389 if (! epilogue_p)
3390 emit_insn (gen_prologue_use (alt_reg));
3391 }
3392 else
3393 {
3394 alt_regno = next_scratch_gr_reg ();
3395 alt_reg = gen_rtx_REG (DImode, alt_regno);
3396 emit_move_insn (alt_reg, reg);
3397 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3398 cfa_off -= 8;
3399 }
3400 }
3401
3402 /* Save the return pointer. */
3403 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3404 {
3405 reg = gen_rtx_REG (DImode, BR_REG (0));
3406 if (current_frame_info.r[reg_save_b0] != 0)
3407 {
3408 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3409 reg_emitted (reg_save_b0);
3410 insn = emit_move_insn (alt_reg, reg);
3411 RTX_FRAME_RELATED_P (insn) = 1;
3412 add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX);
3413
3414 /* Even if we're not going to generate an epilogue, we still
3415 need to save the register so that EH works. */
3416 if (! epilogue_p)
3417 emit_insn (gen_prologue_use (alt_reg));
3418 }
3419 else
3420 {
3421 alt_regno = next_scratch_gr_reg ();
3422 alt_reg = gen_rtx_REG (DImode, alt_regno);
3423 emit_move_insn (alt_reg, reg);
3424 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3425 cfa_off -= 8;
3426 }
3427 }
3428
3429 if (current_frame_info.r[reg_save_gp])
3430 {
3431 reg_emitted (reg_save_gp);
3432 insn = emit_move_insn (gen_rtx_REG (DImode,
3433 current_frame_info.r[reg_save_gp]),
3434 pic_offset_table_rtx);
3435 }
3436
3437 /* We should now be at the base of the gr/br/fr spill area. */
3438 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3439 + current_frame_info.spill_size));
3440
3441 /* Spill all general registers. */
3442 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3443 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3444 {
3445 reg = gen_rtx_REG (DImode, regno);
3446 do_spill (gen_gr_spill, reg, cfa_off, reg);
3447 cfa_off -= 8;
3448 }
3449
3450 /* Spill the rest of the BR registers. */
3451 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3452 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3453 {
3454 alt_regno = next_scratch_gr_reg ();
3455 alt_reg = gen_rtx_REG (DImode, alt_regno);
3456 reg = gen_rtx_REG (DImode, regno);
3457 emit_move_insn (alt_reg, reg);
3458 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3459 cfa_off -= 8;
3460 }
3461
3462 /* Align the frame and spill all FR registers. */
3463 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3464 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3465 {
3466 gcc_assert (!(cfa_off & 15));
3467 reg = gen_rtx_REG (XFmode, regno);
3468 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3469 cfa_off -= 16;
3470 }
3471
3472 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3473
3474 finish_spill_pointers ();
3475 }
3476
3477 /* Output the textual info surrounding the prologue. */
3478
3479 void
3480 ia64_start_function (FILE *file, const char *fnname,
3481 tree decl ATTRIBUTE_UNUSED)
3482 {
3483 #if VMS_DEBUGGING_INFO
3484 if (vms_debug_main
3485 && strncmp (vms_debug_main, fnname, strlen (vms_debug_main)) == 0)
3486 {
3487 targetm.asm_out.globalize_label (asm_out_file, VMS_DEBUG_MAIN_POINTER);
3488 ASM_OUTPUT_DEF (asm_out_file, VMS_DEBUG_MAIN_POINTER, fnname);
3489 dwarf2out_vms_debug_main_pointer ();
3490 vms_debug_main = 0;
3491 }
3492 #endif
3493
3494 fputs ("\t.proc ", file);
3495 assemble_name (file, fnname);
3496 fputc ('\n', file);
3497 ASM_OUTPUT_LABEL (file, fnname);
3498 }
3499
3500 /* Called after register allocation to add any instructions needed for the
3501 epilogue. Using an epilogue insn is favored compared to putting all of the
3502 instructions in output_function_prologue(), since it allows the scheduler
3503 to intermix instructions with the saves of the caller saved registers. In
3504 some cases, it might be necessary to emit a barrier instruction as the last
3505 insn to prevent such scheduling. */
3506
3507 void
3508 ia64_expand_epilogue (int sibcall_p)
3509 {
3510 rtx insn, reg, alt_reg, ar_unat_save_reg;
3511 int regno, alt_regno, cfa_off;
3512
3513 ia64_compute_frame_size (get_frame_size ());
3514
3515 /* If there is a frame pointer, then we use it instead of the stack
3516 pointer, so that the stack pointer does not need to be valid when
3517 the epilogue starts. See EXIT_IGNORE_STACK. */
3518 if (frame_pointer_needed)
3519 setup_spill_pointers (current_frame_info.n_spilled,
3520 hard_frame_pointer_rtx, 0);
3521 else
3522 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3523 current_frame_info.total_size);
3524
3525 if (current_frame_info.total_size != 0)
3526 {
3527 /* ??? At this point we must generate a magic insn that appears to
3528 modify the spill iterators and the frame pointer. This would
3529 allow the most scheduling freedom. For now, just hard stop. */
3530 emit_insn (gen_blockage ());
3531 }
3532
3533 /* Locate the bottom of the register save area. */
3534 cfa_off = (current_frame_info.spill_cfa_off
3535 + current_frame_info.spill_size
3536 + current_frame_info.extra_spill_size);
3537
3538 /* Restore the predicate registers. */
3539 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3540 {
3541 if (current_frame_info.r[reg_save_pr] != 0)
3542 {
3543 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]);
3544 reg_emitted (reg_save_pr);
3545 }
3546 else
3547 {
3548 alt_regno = next_scratch_gr_reg ();
3549 alt_reg = gen_rtx_REG (DImode, alt_regno);
3550 do_restore (gen_movdi_x, alt_reg, cfa_off);
3551 cfa_off -= 8;
3552 }
3553 reg = gen_rtx_REG (DImode, PR_REG (0));
3554 emit_move_insn (reg, alt_reg);
3555 }
3556
3557 /* Restore the application registers. */
3558
3559 /* Load the saved unat from the stack, but do not restore it until
3560 after the GRs have been restored. */
3561 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3562 {
3563 if (current_frame_info.r[reg_save_ar_unat] != 0)
3564 {
3565 ar_unat_save_reg
3566 = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]);
3567 reg_emitted (reg_save_ar_unat);
3568 }
3569 else
3570 {
3571 alt_regno = next_scratch_gr_reg ();
3572 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3573 current_frame_info.gr_used_mask |= 1 << alt_regno;
3574 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3575 cfa_off -= 8;
3576 }
3577 }
3578 else
3579 ar_unat_save_reg = NULL_RTX;
3580
3581 if (current_frame_info.r[reg_save_ar_pfs] != 0)
3582 {
3583 reg_emitted (reg_save_ar_pfs);
3584 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]);
3585 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3586 emit_move_insn (reg, alt_reg);
3587 }
3588 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3589 {
3590 alt_regno = next_scratch_gr_reg ();
3591 alt_reg = gen_rtx_REG (DImode, alt_regno);
3592 do_restore (gen_movdi_x, alt_reg, cfa_off);
3593 cfa_off -= 8;
3594 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3595 emit_move_insn (reg, alt_reg);
3596 }
3597
3598 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3599 {
3600 if (current_frame_info.r[reg_save_ar_lc] != 0)
3601 {
3602 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]);
3603 reg_emitted (reg_save_ar_lc);
3604 }
3605 else
3606 {
3607 alt_regno = next_scratch_gr_reg ();
3608 alt_reg = gen_rtx_REG (DImode, alt_regno);
3609 do_restore (gen_movdi_x, alt_reg, cfa_off);
3610 cfa_off -= 8;
3611 }
3612 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3613 emit_move_insn (reg, alt_reg);
3614 }
3615
3616 /* Restore the return pointer. */
3617 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3618 {
3619 if (current_frame_info.r[reg_save_b0] != 0)
3620 {
3621 alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3622 reg_emitted (reg_save_b0);
3623 }
3624 else
3625 {
3626 alt_regno = next_scratch_gr_reg ();
3627 alt_reg = gen_rtx_REG (DImode, alt_regno);
3628 do_restore (gen_movdi_x, alt_reg, cfa_off);
3629 cfa_off -= 8;
3630 }
3631 reg = gen_rtx_REG (DImode, BR_REG (0));
3632 emit_move_insn (reg, alt_reg);
3633 }
3634
3635 /* We should now be at the base of the gr/br/fr spill area. */
3636 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3637 + current_frame_info.spill_size));
3638
3639 /* The GP may be stored on the stack in the prologue, but it's
3640 never restored in the epilogue. Skip the stack slot. */
3641 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3642 cfa_off -= 8;
3643
3644 /* Restore all general registers. */
3645 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3646 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3647 {
3648 reg = gen_rtx_REG (DImode, regno);
3649 do_restore (gen_gr_restore, reg, cfa_off);
3650 cfa_off -= 8;
3651 }
3652
3653 /* Restore the branch registers. */
3654 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3655 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3656 {
3657 alt_regno = next_scratch_gr_reg ();
3658 alt_reg = gen_rtx_REG (DImode, alt_regno);
3659 do_restore (gen_movdi_x, alt_reg, cfa_off);
3660 cfa_off -= 8;
3661 reg = gen_rtx_REG (DImode, regno);
3662 emit_move_insn (reg, alt_reg);
3663 }
3664
3665 /* Restore floating point registers. */
3666 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3667 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3668 {
3669 gcc_assert (!(cfa_off & 15));
3670 reg = gen_rtx_REG (XFmode, regno);
3671 do_restore (gen_fr_restore_x, reg, cfa_off);
3672 cfa_off -= 16;
3673 }
3674
3675 /* Restore ar.unat for real. */
3676 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3677 {
3678 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3679 emit_move_insn (reg, ar_unat_save_reg);
3680 }
3681
3682 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3683
3684 finish_spill_pointers ();
3685
3686 if (current_frame_info.total_size
3687 || cfun->machine->ia64_eh_epilogue_sp
3688 || frame_pointer_needed)
3689 {
3690 /* ??? At this point we must generate a magic insn that appears to
3691 modify the spill iterators, the stack pointer, and the frame
3692 pointer. This would allow the most scheduling freedom. For now,
3693 just hard stop. */
3694 emit_insn (gen_blockage ());
3695 }
3696
3697 if (cfun->machine->ia64_eh_epilogue_sp)
3698 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3699 else if (frame_pointer_needed)
3700 {
3701 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3702 RTX_FRAME_RELATED_P (insn) = 1;
3703 add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL);
3704 }
3705 else if (current_frame_info.total_size)
3706 {
3707 rtx offset, frame_size_rtx;
3708
3709 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3710 if (satisfies_constraint_I (frame_size_rtx))
3711 offset = frame_size_rtx;
3712 else
3713 {
3714 regno = next_scratch_gr_reg ();
3715 offset = gen_rtx_REG (DImode, regno);
3716 emit_move_insn (offset, frame_size_rtx);
3717 }
3718
3719 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3720 offset));
3721
3722 RTX_FRAME_RELATED_P (insn) = 1;
3723 add_reg_note (insn, REG_CFA_ADJUST_CFA,
3724 gen_rtx_SET (VOIDmode,
3725 stack_pointer_rtx,
3726 gen_rtx_PLUS (DImode,
3727 stack_pointer_rtx,
3728 frame_size_rtx)));
3729 }
3730
3731 if (cfun->machine->ia64_eh_epilogue_bsp)
3732 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3733
3734 if (! sibcall_p)
3735 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3736 else
3737 {
3738 int fp = GR_REG (2);
3739 /* We need a throw away register here, r0 and r1 are reserved,
3740 so r2 is the first available call clobbered register. If
3741 there was a frame_pointer register, we may have swapped the
3742 names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make
3743 sure we're using the string "r2" when emitting the register
3744 name for the assembler. */
3745 if (current_frame_info.r[reg_fp]
3746 && current_frame_info.r[reg_fp] == GR_REG (2))
3747 fp = HARD_FRAME_POINTER_REGNUM;
3748
3749 /* We must emit an alloc to force the input registers to become output
3750 registers. Otherwise, if the callee tries to pass its parameters
3751 through to another call without an intervening alloc, then these
3752 values get lost. */
3753 /* ??? We don't need to preserve all input registers. We only need to
3754 preserve those input registers used as arguments to the sibling call.
3755 It is unclear how to compute that number here. */
3756 if (current_frame_info.n_input_regs != 0)
3757 {
3758 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3759 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3760 const0_rtx, const0_rtx,
3761 n_inputs, const0_rtx));
3762 RTX_FRAME_RELATED_P (insn) = 1;
3763 }
3764 }
3765 }
3766
3767 /* Return 1 if br.ret can do all the work required to return from a
3768 function. */
3769
3770 int
3771 ia64_direct_return (void)
3772 {
3773 if (reload_completed && ! frame_pointer_needed)
3774 {
3775 ia64_compute_frame_size (get_frame_size ());
3776
3777 return (current_frame_info.total_size == 0
3778 && current_frame_info.n_spilled == 0
3779 && current_frame_info.r[reg_save_b0] == 0
3780 && current_frame_info.r[reg_save_pr] == 0
3781 && current_frame_info.r[reg_save_ar_pfs] == 0
3782 && current_frame_info.r[reg_save_ar_unat] == 0
3783 && current_frame_info.r[reg_save_ar_lc] == 0);
3784 }
3785 return 0;
3786 }
3787
3788 /* Return the magic cookie that we use to hold the return address
3789 during early compilation. */
3790
3791 rtx
3792 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3793 {
3794 if (count != 0)
3795 return NULL;
3796 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3797 }
3798
3799 /* Split this value after reload, now that we know where the return
3800 address is saved. */
3801
3802 void
3803 ia64_split_return_addr_rtx (rtx dest)
3804 {
3805 rtx src;
3806
3807 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3808 {
3809 if (current_frame_info.r[reg_save_b0] != 0)
3810 {
3811 src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]);
3812 reg_emitted (reg_save_b0);
3813 }
3814 else
3815 {
3816 HOST_WIDE_INT off;
3817 unsigned int regno;
3818 rtx off_r;
3819
3820 /* Compute offset from CFA for BR0. */
3821 /* ??? Must be kept in sync with ia64_expand_prologue. */
3822 off = (current_frame_info.spill_cfa_off
3823 + current_frame_info.spill_size);
3824 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3825 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3826 off -= 8;
3827
3828 /* Convert CFA offset to a register based offset. */
3829 if (frame_pointer_needed)
3830 src = hard_frame_pointer_rtx;
3831 else
3832 {
3833 src = stack_pointer_rtx;
3834 off += current_frame_info.total_size;
3835 }
3836
3837 /* Load address into scratch register. */
3838 off_r = GEN_INT (off);
3839 if (satisfies_constraint_I (off_r))
3840 emit_insn (gen_adddi3 (dest, src, off_r));
3841 else
3842 {
3843 emit_move_insn (dest, off_r);
3844 emit_insn (gen_adddi3 (dest, src, dest));
3845 }
3846
3847 src = gen_rtx_MEM (Pmode, dest);
3848 }
3849 }
3850 else
3851 src = gen_rtx_REG (DImode, BR_REG (0));
3852
3853 emit_move_insn (dest, src);
3854 }
3855
3856 int
3857 ia64_hard_regno_rename_ok (int from, int to)
3858 {
3859 /* Don't clobber any of the registers we reserved for the prologue. */
3860 unsigned int r;
3861
3862 for (r = reg_fp; r <= reg_save_ar_lc; r++)
3863 if (to == current_frame_info.r[r]
3864 || from == current_frame_info.r[r]
3865 || to == emitted_frame_related_regs[r]
3866 || from == emitted_frame_related_regs[r])
3867 return 0;
3868
3869 /* Don't use output registers outside the register frame. */
3870 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3871 return 0;
3872
3873 /* Retain even/oddness on predicate register pairs. */
3874 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3875 return (from & 1) == (to & 1);
3876
3877 return 1;
3878 }
3879
3880 /* Target hook for assembling integer objects. Handle word-sized
3881 aligned objects and detect the cases when @fptr is needed. */
3882
3883 static bool
3884 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3885 {
3886 if (size == POINTER_SIZE / BITS_PER_UNIT
3887 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3888 && GET_CODE (x) == SYMBOL_REF
3889 && SYMBOL_REF_FUNCTION_P (x))
3890 {
3891 static const char * const directive[2][2] = {
3892 /* 64-bit pointer */ /* 32-bit pointer */
3893 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3894 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3895 };
3896 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3897 output_addr_const (asm_out_file, x);
3898 fputs (")\n", asm_out_file);
3899 return true;
3900 }
3901 return default_assemble_integer (x, size, aligned_p);
3902 }
3903
3904 /* Emit the function prologue. */
3905
3906 static void
3907 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3908 {
3909 int mask, grsave, grsave_prev;
3910
3911 if (current_frame_info.need_regstk)
3912 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3913 current_frame_info.n_input_regs,
3914 current_frame_info.n_local_regs,
3915 current_frame_info.n_output_regs,
3916 current_frame_info.n_rotate_regs);
3917
3918 if (ia64_except_unwind_info () != UI_TARGET)
3919 return;
3920
3921 /* Emit the .prologue directive. */
3922
3923 mask = 0;
3924 grsave = grsave_prev = 0;
3925 if (current_frame_info.r[reg_save_b0] != 0)
3926 {
3927 mask |= 8;
3928 grsave = grsave_prev = current_frame_info.r[reg_save_b0];
3929 }
3930 if (current_frame_info.r[reg_save_ar_pfs] != 0
3931 && (grsave_prev == 0
3932 || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1))
3933 {
3934 mask |= 4;
3935 if (grsave_prev == 0)
3936 grsave = current_frame_info.r[reg_save_ar_pfs];
3937 grsave_prev = current_frame_info.r[reg_save_ar_pfs];
3938 }
3939 if (current_frame_info.r[reg_fp] != 0
3940 && (grsave_prev == 0
3941 || current_frame_info.r[reg_fp] == grsave_prev + 1))
3942 {
3943 mask |= 2;
3944 if (grsave_prev == 0)
3945 grsave = HARD_FRAME_POINTER_REGNUM;
3946 grsave_prev = current_frame_info.r[reg_fp];
3947 }
3948 if (current_frame_info.r[reg_save_pr] != 0
3949 && (grsave_prev == 0
3950 || current_frame_info.r[reg_save_pr] == grsave_prev + 1))
3951 {
3952 mask |= 1;
3953 if (grsave_prev == 0)
3954 grsave = current_frame_info.r[reg_save_pr];
3955 }
3956
3957 if (mask && TARGET_GNU_AS)
3958 fprintf (file, "\t.prologue %d, %d\n", mask,
3959 ia64_dbx_register_number (grsave));
3960 else
3961 fputs ("\t.prologue\n", file);
3962
3963 /* Emit a .spill directive, if necessary, to relocate the base of
3964 the register spill area. */
3965 if (current_frame_info.spill_cfa_off != -16)
3966 fprintf (file, "\t.spill %ld\n",
3967 (long) (current_frame_info.spill_cfa_off
3968 + current_frame_info.spill_size));
3969 }
3970
3971 /* Emit the .body directive at the scheduled end of the prologue. */
3972
3973 static void
3974 ia64_output_function_end_prologue (FILE *file)
3975 {
3976 if (ia64_except_unwind_info () != UI_TARGET)
3977 return;
3978
3979 fputs ("\t.body\n", file);
3980 }
3981
3982 /* Emit the function epilogue. */
3983
3984 static void
3985 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3986 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3987 {
3988 int i;
3989
3990 if (current_frame_info.r[reg_fp])
3991 {
3992 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3993 reg_names[HARD_FRAME_POINTER_REGNUM]
3994 = reg_names[current_frame_info.r[reg_fp]];
3995 reg_names[current_frame_info.r[reg_fp]] = tmp;
3996 reg_emitted (reg_fp);
3997 }
3998 if (! TARGET_REG_NAMES)
3999 {
4000 for (i = 0; i < current_frame_info.n_input_regs; i++)
4001 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
4002 for (i = 0; i < current_frame_info.n_local_regs; i++)
4003 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
4004 for (i = 0; i < current_frame_info.n_output_regs; i++)
4005 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
4006 }
4007
4008 current_frame_info.initialized = 0;
4009 }
4010
4011 int
4012 ia64_dbx_register_number (int regno)
4013 {
4014 /* In ia64_expand_prologue we quite literally renamed the frame pointer
4015 from its home at loc79 to something inside the register frame. We
4016 must perform the same renumbering here for the debug info. */
4017 if (current_frame_info.r[reg_fp])
4018 {
4019 if (regno == HARD_FRAME_POINTER_REGNUM)
4020 regno = current_frame_info.r[reg_fp];
4021 else if (regno == current_frame_info.r[reg_fp])
4022 regno = HARD_FRAME_POINTER_REGNUM;
4023 }
4024
4025 if (IN_REGNO_P (regno))
4026 return 32 + regno - IN_REG (0);
4027 else if (LOC_REGNO_P (regno))
4028 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
4029 else if (OUT_REGNO_P (regno))
4030 return (32 + current_frame_info.n_input_regs
4031 + current_frame_info.n_local_regs + regno - OUT_REG (0));
4032 else
4033 return regno;
4034 }
4035
4036 /* Implement TARGET_TRAMPOLINE_INIT.
4037
4038 The trampoline should set the static chain pointer to value placed
4039 into the trampoline and should branch to the specified routine.
4040 To make the normal indirect-subroutine calling convention work,
4041 the trampoline must look like a function descriptor; the first
4042 word being the target address and the second being the target's
4043 global pointer.
4044
4045 We abuse the concept of a global pointer by arranging for it
4046 to point to the data we need to load. The complete trampoline
4047 has the following form:
4048
4049 +-------------------+ \
4050 TRAMP: | __ia64_trampoline | |
4051 +-------------------+ > fake function descriptor
4052 | TRAMP+16 | |
4053 +-------------------+ /
4054 | target descriptor |
4055 +-------------------+
4056 | static link |
4057 +-------------------+
4058 */
4059
4060 static void
4061 ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain)
4062 {
4063 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
4064 rtx addr, addr_reg, tramp, eight = GEN_INT (8);
4065
4066 /* The Intel assembler requires that the global __ia64_trampoline symbol
4067 be declared explicitly */
4068 if (!TARGET_GNU_AS)
4069 {
4070 static bool declared_ia64_trampoline = false;
4071
4072 if (!declared_ia64_trampoline)
4073 {
4074 declared_ia64_trampoline = true;
4075 (*targetm.asm_out.globalize_label) (asm_out_file,
4076 "__ia64_trampoline");
4077 }
4078 }
4079
4080 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
4081 addr = convert_memory_address (Pmode, XEXP (m_tramp, 0));
4082 fnaddr = convert_memory_address (Pmode, fnaddr);
4083 static_chain = convert_memory_address (Pmode, static_chain);
4084
4085 /* Load up our iterator. */
4086 addr_reg = copy_to_reg (addr);
4087 m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0);
4088
4089 /* The first two words are the fake descriptor:
4090 __ia64_trampoline, ADDR+16. */
4091 tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline");
4092 if (TARGET_ABI_OPEN_VMS)
4093 {
4094 /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity
4095 in the Macro-32 compiler) and changed the semantics of the LTOFF22
4096 relocation against function symbols to make it identical to the
4097 LTOFF_FPTR22 relocation. Emit the latter directly to stay within
4098 strict ELF and dereference to get the bare code address. */
4099 rtx reg = gen_reg_rtx (Pmode);
4100 SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION;
4101 emit_move_insn (reg, tramp);
4102 emit_move_insn (reg, gen_rtx_MEM (Pmode, reg));
4103 tramp = reg;
4104 }
4105 emit_move_insn (m_tramp, tramp);
4106 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4107 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4108
4109 emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (addr, 16)));
4110 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4111 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4112
4113 /* The third word is the target descriptor. */
4114 emit_move_insn (m_tramp, force_reg (Pmode, fnaddr));
4115 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
4116 m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8);
4117
4118 /* The fourth word is the static chain. */
4119 emit_move_insn (m_tramp, static_chain);
4120 }
4121 \f
4122 /* Do any needed setup for a variadic function. CUM has not been updated
4123 for the last named argument which has type TYPE and mode MODE.
4124
4125 We generate the actual spill instructions during prologue generation. */
4126
4127 static void
4128 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4129 tree type, int * pretend_size,
4130 int second_time ATTRIBUTE_UNUSED)
4131 {
4132 CUMULATIVE_ARGS next_cum = *cum;
4133
4134 /* Skip the current argument. */
4135 ia64_function_arg_advance (&next_cum, mode, type, 1);
4136
4137 if (next_cum.words < MAX_ARGUMENT_SLOTS)
4138 {
4139 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
4140 *pretend_size = n * UNITS_PER_WORD;
4141 cfun->machine->n_varargs = n;
4142 }
4143 }
4144
4145 /* Check whether TYPE is a homogeneous floating point aggregate. If
4146 it is, return the mode of the floating point type that appears
4147 in all leafs. If it is not, return VOIDmode.
4148
4149 An aggregate is a homogeneous floating point aggregate is if all
4150 fields/elements in it have the same floating point type (e.g,
4151 SFmode). 128-bit quad-precision floats are excluded.
4152
4153 Variable sized aggregates should never arrive here, since we should
4154 have already decided to pass them by reference. Top-level zero-sized
4155 aggregates are excluded because our parallels crash the middle-end. */
4156
4157 static enum machine_mode
4158 hfa_element_mode (const_tree type, bool nested)
4159 {
4160 enum machine_mode element_mode = VOIDmode;
4161 enum machine_mode mode;
4162 enum tree_code code = TREE_CODE (type);
4163 int know_element_mode = 0;
4164 tree t;
4165
4166 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
4167 return VOIDmode;
4168
4169 switch (code)
4170 {
4171 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
4172 case BOOLEAN_TYPE: case POINTER_TYPE:
4173 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
4174 case LANG_TYPE: case FUNCTION_TYPE:
4175 return VOIDmode;
4176
4177 /* Fortran complex types are supposed to be HFAs, so we need to handle
4178 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
4179 types though. */
4180 case COMPLEX_TYPE:
4181 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
4182 && TYPE_MODE (type) != TCmode)
4183 return GET_MODE_INNER (TYPE_MODE (type));
4184 else
4185 return VOIDmode;
4186
4187 case REAL_TYPE:
4188 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
4189 mode if this is contained within an aggregate. */
4190 if (nested && TYPE_MODE (type) != TFmode)
4191 return TYPE_MODE (type);
4192 else
4193 return VOIDmode;
4194
4195 case ARRAY_TYPE:
4196 return hfa_element_mode (TREE_TYPE (type), 1);
4197
4198 case RECORD_TYPE:
4199 case UNION_TYPE:
4200 case QUAL_UNION_TYPE:
4201 for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t))
4202 {
4203 if (TREE_CODE (t) != FIELD_DECL)
4204 continue;
4205
4206 mode = hfa_element_mode (TREE_TYPE (t), 1);
4207 if (know_element_mode)
4208 {
4209 if (mode != element_mode)
4210 return VOIDmode;
4211 }
4212 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
4213 return VOIDmode;
4214 else
4215 {
4216 know_element_mode = 1;
4217 element_mode = mode;
4218 }
4219 }
4220 return element_mode;
4221
4222 default:
4223 /* If we reach here, we probably have some front-end specific type
4224 that the backend doesn't know about. This can happen via the
4225 aggregate_value_p call in init_function_start. All we can do is
4226 ignore unknown tree types. */
4227 return VOIDmode;
4228 }
4229
4230 return VOIDmode;
4231 }
4232
4233 /* Return the number of words required to hold a quantity of TYPE and MODE
4234 when passed as an argument. */
4235 static int
4236 ia64_function_arg_words (tree type, enum machine_mode mode)
4237 {
4238 int words;
4239
4240 if (mode == BLKmode)
4241 words = int_size_in_bytes (type);
4242 else
4243 words = GET_MODE_SIZE (mode);
4244
4245 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
4246 }
4247
4248 /* Return the number of registers that should be skipped so the current
4249 argument (described by TYPE and WORDS) will be properly aligned.
4250
4251 Integer and float arguments larger than 8 bytes start at the next
4252 even boundary. Aggregates larger than 8 bytes start at the next
4253 even boundary if the aggregate has 16 byte alignment. Note that
4254 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
4255 but are still to be aligned in registers.
4256
4257 ??? The ABI does not specify how to handle aggregates with
4258 alignment from 9 to 15 bytes, or greater than 16. We handle them
4259 all as if they had 16 byte alignment. Such aggregates can occur
4260 only if gcc extensions are used. */
4261 static int
4262 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
4263 {
4264 /* No registers are skipped on VMS. */
4265 if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0)
4266 return 0;
4267
4268 if (type
4269 && TREE_CODE (type) != INTEGER_TYPE
4270 && TREE_CODE (type) != REAL_TYPE)
4271 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
4272 else
4273 return words > 1;
4274 }
4275
4276 /* Return rtx for register where argument is passed, or zero if it is passed
4277 on the stack. */
4278 /* ??? 128-bit quad-precision floats are always passed in general
4279 registers. */
4280
4281 rtx
4282 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
4283 int named, int incoming)
4284 {
4285 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
4286 int words = ia64_function_arg_words (type, mode);
4287 int offset = ia64_function_arg_offset (cum, type, words);
4288 enum machine_mode hfa_mode = VOIDmode;
4289
4290 /* For OPEN VMS, emit the instruction setting up the argument register here,
4291 when we know this will be together with the other arguments setup related
4292 insns. This is not the conceptually best place to do this, but this is
4293 the easiest as we have convenient access to cumulative args info. */
4294
4295 if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node
4296 && named == 1)
4297 {
4298 unsigned HOST_WIDE_INT regval = cum->words;
4299 int i;
4300
4301 for (i = 0; i < 8; i++)
4302 regval |= ((int) cum->atypes[i]) << (i * 3 + 8);
4303
4304 emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)),
4305 GEN_INT (regval));
4306 }
4307
4308 /* If all argument slots are used, then it must go on the stack. */
4309 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4310 return 0;
4311
4312 /* Check for and handle homogeneous FP aggregates. */
4313 if (type)
4314 hfa_mode = hfa_element_mode (type, 0);
4315
4316 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4317 and unprototyped hfas are passed specially. */
4318 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4319 {
4320 rtx loc[16];
4321 int i = 0;
4322 int fp_regs = cum->fp_regs;
4323 int int_regs = cum->words + offset;
4324 int hfa_size = GET_MODE_SIZE (hfa_mode);
4325 int byte_size;
4326 int args_byte_size;
4327
4328 /* If prototyped, pass it in FR regs then GR regs.
4329 If not prototyped, pass it in both FR and GR regs.
4330
4331 If this is an SFmode aggregate, then it is possible to run out of
4332 FR regs while GR regs are still left. In that case, we pass the
4333 remaining part in the GR regs. */
4334
4335 /* Fill the FP regs. We do this always. We stop if we reach the end
4336 of the argument, the last FP register, or the last argument slot. */
4337
4338 byte_size = ((mode == BLKmode)
4339 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4340 args_byte_size = int_regs * UNITS_PER_WORD;
4341 offset = 0;
4342 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4343 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
4344 {
4345 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4346 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
4347 + fp_regs)),
4348 GEN_INT (offset));
4349 offset += hfa_size;
4350 args_byte_size += hfa_size;
4351 fp_regs++;
4352 }
4353
4354 /* If no prototype, then the whole thing must go in GR regs. */
4355 if (! cum->prototype)
4356 offset = 0;
4357 /* If this is an SFmode aggregate, then we might have some left over
4358 that needs to go in GR regs. */
4359 else if (byte_size != offset)
4360 int_regs += offset / UNITS_PER_WORD;
4361
4362 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
4363
4364 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
4365 {
4366 enum machine_mode gr_mode = DImode;
4367 unsigned int gr_size;
4368
4369 /* If we have an odd 4 byte hunk because we ran out of FR regs,
4370 then this goes in a GR reg left adjusted/little endian, right
4371 adjusted/big endian. */
4372 /* ??? Currently this is handled wrong, because 4-byte hunks are
4373 always right adjusted/little endian. */
4374 if (offset & 0x4)
4375 gr_mode = SImode;
4376 /* If we have an even 4 byte hunk because the aggregate is a
4377 multiple of 4 bytes in size, then this goes in a GR reg right
4378 adjusted/little endian. */
4379 else if (byte_size - offset == 4)
4380 gr_mode = SImode;
4381
4382 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4383 gen_rtx_REG (gr_mode, (basereg
4384 + int_regs)),
4385 GEN_INT (offset));
4386
4387 gr_size = GET_MODE_SIZE (gr_mode);
4388 offset += gr_size;
4389 if (gr_size == UNITS_PER_WORD
4390 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
4391 int_regs++;
4392 else if (gr_size > UNITS_PER_WORD)
4393 int_regs += gr_size / UNITS_PER_WORD;
4394 }
4395 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4396 }
4397
4398 /* On OpenVMS variable argument is either in Rn or Fn. */
4399 else if (TARGET_ABI_OPEN_VMS && named == 0)
4400 {
4401 if (FLOAT_MODE_P (mode))
4402 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words);
4403 else
4404 return gen_rtx_REG (mode, basereg + cum->words);
4405 }
4406
4407 /* Integral and aggregates go in general registers. If we have run out of
4408 FR registers, then FP values must also go in general registers. This can
4409 happen when we have a SFmode HFA. */
4410 else if (mode == TFmode || mode == TCmode
4411 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4412 {
4413 int byte_size = ((mode == BLKmode)
4414 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4415 if (BYTES_BIG_ENDIAN
4416 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
4417 && byte_size < UNITS_PER_WORD
4418 && byte_size > 0)
4419 {
4420 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4421 gen_rtx_REG (DImode,
4422 (basereg + cum->words
4423 + offset)),
4424 const0_rtx);
4425 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
4426 }
4427 else
4428 return gen_rtx_REG (mode, basereg + cum->words + offset);
4429
4430 }
4431
4432 /* If there is a prototype, then FP values go in a FR register when
4433 named, and in a GR register when unnamed. */
4434 else if (cum->prototype)
4435 {
4436 if (named)
4437 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
4438 /* In big-endian mode, an anonymous SFmode value must be represented
4439 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
4440 the value into the high half of the general register. */
4441 else if (BYTES_BIG_ENDIAN && mode == SFmode)
4442 return gen_rtx_PARALLEL (mode,
4443 gen_rtvec (1,
4444 gen_rtx_EXPR_LIST (VOIDmode,
4445 gen_rtx_REG (DImode, basereg + cum->words + offset),
4446 const0_rtx)));
4447 else
4448 return gen_rtx_REG (mode, basereg + cum->words + offset);
4449 }
4450 /* If there is no prototype, then FP values go in both FR and GR
4451 registers. */
4452 else
4453 {
4454 /* See comment above. */
4455 enum machine_mode inner_mode =
4456 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
4457
4458 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
4459 gen_rtx_REG (mode, (FR_ARG_FIRST
4460 + cum->fp_regs)),
4461 const0_rtx);
4462 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
4463 gen_rtx_REG (inner_mode,
4464 (basereg + cum->words
4465 + offset)),
4466 const0_rtx);
4467
4468 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
4469 }
4470 }
4471
4472 /* Return number of bytes, at the beginning of the argument, that must be
4473 put in registers. 0 is the argument is entirely in registers or entirely
4474 in memory. */
4475
4476 static int
4477 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4478 tree type, bool named ATTRIBUTE_UNUSED)
4479 {
4480 int words = ia64_function_arg_words (type, mode);
4481 int offset = ia64_function_arg_offset (cum, type, words);
4482
4483 /* If all argument slots are used, then it must go on the stack. */
4484 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
4485 return 0;
4486
4487 /* It doesn't matter whether the argument goes in FR or GR regs. If
4488 it fits within the 8 argument slots, then it goes entirely in
4489 registers. If it extends past the last argument slot, then the rest
4490 goes on the stack. */
4491
4492 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
4493 return 0;
4494
4495 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
4496 }
4497
4498 /* Return ivms_arg_type based on machine_mode. */
4499
4500 static enum ivms_arg_type
4501 ia64_arg_type (enum machine_mode mode)
4502 {
4503 switch (mode)
4504 {
4505 case SFmode:
4506 return FS;
4507 case DFmode:
4508 return FT;
4509 default:
4510 return I64;
4511 }
4512 }
4513
4514 /* Update CUM to point after this argument. This is patterned after
4515 ia64_function_arg. */
4516
4517 void
4518 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4519 tree type, int named)
4520 {
4521 int words = ia64_function_arg_words (type, mode);
4522 int offset = ia64_function_arg_offset (cum, type, words);
4523 enum machine_mode hfa_mode = VOIDmode;
4524
4525 /* If all arg slots are already full, then there is nothing to do. */
4526 if (cum->words >= MAX_ARGUMENT_SLOTS)
4527 {
4528 cum->words += words + offset;
4529 return;
4530 }
4531
4532 cum->atypes[cum->words] = ia64_arg_type (mode);
4533 cum->words += words + offset;
4534
4535 /* Check for and handle homogeneous FP aggregates. */
4536 if (type)
4537 hfa_mode = hfa_element_mode (type, 0);
4538
4539 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
4540 and unprototyped hfas are passed specially. */
4541 if (hfa_mode != VOIDmode && (! cum->prototype || named))
4542 {
4543 int fp_regs = cum->fp_regs;
4544 /* This is the original value of cum->words + offset. */
4545 int int_regs = cum->words - words;
4546 int hfa_size = GET_MODE_SIZE (hfa_mode);
4547 int byte_size;
4548 int args_byte_size;
4549
4550 /* If prototyped, pass it in FR regs then GR regs.
4551 If not prototyped, pass it in both FR and GR regs.
4552
4553 If this is an SFmode aggregate, then it is possible to run out of
4554 FR regs while GR regs are still left. In that case, we pass the
4555 remaining part in the GR regs. */
4556
4557 /* Fill the FP regs. We do this always. We stop if we reach the end
4558 of the argument, the last FP register, or the last argument slot. */
4559
4560 byte_size = ((mode == BLKmode)
4561 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4562 args_byte_size = int_regs * UNITS_PER_WORD;
4563 offset = 0;
4564 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4565 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4566 {
4567 offset += hfa_size;
4568 args_byte_size += hfa_size;
4569 fp_regs++;
4570 }
4571
4572 cum->fp_regs = fp_regs;
4573 }
4574
4575 /* On OpenVMS variable argument is either in Rn or Fn. */
4576 else if (TARGET_ABI_OPEN_VMS && named == 0)
4577 {
4578 cum->int_regs = cum->words;
4579 cum->fp_regs = cum->words;
4580 }
4581
4582 /* Integral and aggregates go in general registers. So do TFmode FP values.
4583 If we have run out of FR registers, then other FP values must also go in
4584 general registers. This can happen when we have a SFmode HFA. */
4585 else if (mode == TFmode || mode == TCmode
4586 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4587 cum->int_regs = cum->words;
4588
4589 /* If there is a prototype, then FP values go in a FR register when
4590 named, and in a GR register when unnamed. */
4591 else if (cum->prototype)
4592 {
4593 if (! named)
4594 cum->int_regs = cum->words;
4595 else
4596 /* ??? Complex types should not reach here. */
4597 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4598 }
4599 /* If there is no prototype, then FP values go in both FR and GR
4600 registers. */
4601 else
4602 {
4603 /* ??? Complex types should not reach here. */
4604 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4605 cum->int_regs = cum->words;
4606 }
4607 }
4608
4609 /* Arguments with alignment larger than 8 bytes start at the next even
4610 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4611 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4612
4613 int
4614 ia64_function_arg_boundary (enum machine_mode mode, tree type)
4615 {
4616
4617 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4618 return PARM_BOUNDARY * 2;
4619
4620 if (type)
4621 {
4622 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4623 return PARM_BOUNDARY * 2;
4624 else
4625 return PARM_BOUNDARY;
4626 }
4627
4628 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4629 return PARM_BOUNDARY * 2;
4630 else
4631 return PARM_BOUNDARY;
4632 }
4633
4634 /* True if it is OK to do sibling call optimization for the specified
4635 call expression EXP. DECL will be the called function, or NULL if
4636 this is an indirect call. */
4637 static bool
4638 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4639 {
4640 /* We can't perform a sibcall if the current function has the syscall_linkage
4641 attribute. */
4642 if (lookup_attribute ("syscall_linkage",
4643 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4644 return false;
4645
4646 /* We must always return with our current GP. This means we can
4647 only sibcall to functions defined in the current module unless
4648 TARGET_CONST_GP is set to true. */
4649 return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP;
4650 }
4651 \f
4652
4653 /* Implement va_arg. */
4654
4655 static tree
4656 ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
4657 gimple_seq *post_p)
4658 {
4659 /* Variable sized types are passed by reference. */
4660 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4661 {
4662 tree ptrtype = build_pointer_type (type);
4663 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4664 return build_va_arg_indirect_ref (addr);
4665 }
4666
4667 /* Aggregate arguments with alignment larger than 8 bytes start at
4668 the next even boundary. Integer and floating point arguments
4669 do so if they are larger than 8 bytes, whether or not they are
4670 also aligned larger than 8 bytes. */
4671 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4672 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4673 {
4674 tree t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (valist), valist,
4675 size_int (2 * UNITS_PER_WORD - 1));
4676 t = fold_convert (sizetype, t);
4677 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4678 size_int (-2 * UNITS_PER_WORD));
4679 t = fold_convert (TREE_TYPE (valist), t);
4680 gimplify_assign (unshare_expr (valist), t, pre_p);
4681 }
4682
4683 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4684 }
4685 \f
4686 /* Return 1 if function return value returned in memory. Return 0 if it is
4687 in a register. */
4688
4689 static bool
4690 ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED)
4691 {
4692 enum machine_mode mode;
4693 enum machine_mode hfa_mode;
4694 HOST_WIDE_INT byte_size;
4695
4696 mode = TYPE_MODE (valtype);
4697 byte_size = GET_MODE_SIZE (mode);
4698 if (mode == BLKmode)
4699 {
4700 byte_size = int_size_in_bytes (valtype);
4701 if (byte_size < 0)
4702 return true;
4703 }
4704
4705 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4706
4707 hfa_mode = hfa_element_mode (valtype, 0);
4708 if (hfa_mode != VOIDmode)
4709 {
4710 int hfa_size = GET_MODE_SIZE (hfa_mode);
4711
4712 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4713 return true;
4714 else
4715 return false;
4716 }
4717 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4718 return true;
4719 else
4720 return false;
4721 }
4722
4723 /* Return rtx for register that holds the function return value. */
4724
4725 static rtx
4726 ia64_function_value (const_tree valtype,
4727 const_tree fn_decl_or_type,
4728 bool outgoing ATTRIBUTE_UNUSED)
4729 {
4730 enum machine_mode mode;
4731 enum machine_mode hfa_mode;
4732 int unsignedp;
4733 const_tree func = fn_decl_or_type;
4734
4735 if (fn_decl_or_type
4736 && !DECL_P (fn_decl_or_type))
4737 func = NULL;
4738
4739 mode = TYPE_MODE (valtype);
4740 hfa_mode = hfa_element_mode (valtype, 0);
4741
4742 if (hfa_mode != VOIDmode)
4743 {
4744 rtx loc[8];
4745 int i;
4746 int hfa_size;
4747 int byte_size;
4748 int offset;
4749
4750 hfa_size = GET_MODE_SIZE (hfa_mode);
4751 byte_size = ((mode == BLKmode)
4752 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4753 offset = 0;
4754 for (i = 0; offset < byte_size; i++)
4755 {
4756 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4757 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4758 GEN_INT (offset));
4759 offset += hfa_size;
4760 }
4761 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4762 }
4763 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4764 return gen_rtx_REG (mode, FR_ARG_FIRST);
4765 else
4766 {
4767 bool need_parallel = false;
4768
4769 /* In big-endian mode, we need to manage the layout of aggregates
4770 in the registers so that we get the bits properly aligned in
4771 the highpart of the registers. */
4772 if (BYTES_BIG_ENDIAN
4773 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4774 need_parallel = true;
4775
4776 /* Something like struct S { long double x; char a[0] } is not an
4777 HFA structure, and therefore doesn't go in fp registers. But
4778 the middle-end will give it XFmode anyway, and XFmode values
4779 don't normally fit in integer registers. So we need to smuggle
4780 the value inside a parallel. */
4781 else if (mode == XFmode || mode == XCmode || mode == RFmode)
4782 need_parallel = true;
4783
4784 if (need_parallel)
4785 {
4786 rtx loc[8];
4787 int offset;
4788 int bytesize;
4789 int i;
4790
4791 offset = 0;
4792 bytesize = int_size_in_bytes (valtype);
4793 /* An empty PARALLEL is invalid here, but the return value
4794 doesn't matter for empty structs. */
4795 if (bytesize == 0)
4796 return gen_rtx_REG (mode, GR_RET_FIRST);
4797 for (i = 0; offset < bytesize; i++)
4798 {
4799 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4800 gen_rtx_REG (DImode,
4801 GR_RET_FIRST + i),
4802 GEN_INT (offset));
4803 offset += UNITS_PER_WORD;
4804 }
4805 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4806 }
4807
4808 mode = ia64_promote_function_mode (valtype, mode, &unsignedp,
4809 func ? TREE_TYPE (func) : NULL_TREE,
4810 true);
4811
4812 return gen_rtx_REG (mode, GR_RET_FIRST);
4813 }
4814 }
4815
4816 /* Worker function for TARGET_LIBCALL_VALUE. */
4817
4818 static rtx
4819 ia64_libcall_value (enum machine_mode mode,
4820 const_rtx fun ATTRIBUTE_UNUSED)
4821 {
4822 return gen_rtx_REG (mode,
4823 (((GET_MODE_CLASS (mode) == MODE_FLOAT
4824 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4825 && (mode) != TFmode)
4826 ? FR_RET_FIRST : GR_RET_FIRST));
4827 }
4828
4829 /* Worker function for FUNCTION_VALUE_REGNO_P. */
4830
4831 static bool
4832 ia64_function_value_regno_p (const unsigned int regno)
4833 {
4834 return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST)
4835 || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST));
4836 }
4837
4838 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4839 We need to emit DTP-relative relocations. */
4840
4841 static void
4842 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4843 {
4844 gcc_assert (size == 4 || size == 8);
4845 if (size == 4)
4846 fputs ("\tdata4.ua\t@dtprel(", file);
4847 else
4848 fputs ("\tdata8.ua\t@dtprel(", file);
4849 output_addr_const (file, x);
4850 fputs (")", file);
4851 }
4852
4853 /* Print a memory address as an operand to reference that memory location. */
4854
4855 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4856 also call this from ia64_print_operand for memory addresses. */
4857
4858 void
4859 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4860 rtx address ATTRIBUTE_UNUSED)
4861 {
4862 }
4863
4864 /* Print an operand to an assembler instruction.
4865 C Swap and print a comparison operator.
4866 D Print an FP comparison operator.
4867 E Print 32 - constant, for SImode shifts as extract.
4868 e Print 64 - constant, for DImode rotates.
4869 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4870 a floating point register emitted normally.
4871 G A floating point constant.
4872 I Invert a predicate register by adding 1.
4873 J Select the proper predicate register for a condition.
4874 j Select the inverse predicate register for a condition.
4875 O Append .acq for volatile load.
4876 P Postincrement of a MEM.
4877 Q Append .rel for volatile store.
4878 R Print .s .d or nothing for a single, double or no truncation.
4879 S Shift amount for shladd instruction.
4880 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4881 for Intel assembler.
4882 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4883 for Intel assembler.
4884 X A pair of floating point registers.
4885 r Print register name, or constant 0 as r0. HP compatibility for
4886 Linux kernel.
4887 v Print vector constant value as an 8-byte integer value. */
4888
4889 void
4890 ia64_print_operand (FILE * file, rtx x, int code)
4891 {
4892 const char *str;
4893
4894 switch (code)
4895 {
4896 case 0:
4897 /* Handled below. */
4898 break;
4899
4900 case 'C':
4901 {
4902 enum rtx_code c = swap_condition (GET_CODE (x));
4903 fputs (GET_RTX_NAME (c), file);
4904 return;
4905 }
4906
4907 case 'D':
4908 switch (GET_CODE (x))
4909 {
4910 case NE:
4911 str = "neq";
4912 break;
4913 case UNORDERED:
4914 str = "unord";
4915 break;
4916 case ORDERED:
4917 str = "ord";
4918 break;
4919 case UNLT:
4920 str = "nge";
4921 break;
4922 case UNLE:
4923 str = "ngt";
4924 break;
4925 case UNGT:
4926 str = "nle";
4927 break;
4928 case UNGE:
4929 str = "nlt";
4930 break;
4931 default:
4932 str = GET_RTX_NAME (GET_CODE (x));
4933 break;
4934 }
4935 fputs (str, file);
4936 return;
4937
4938 case 'E':
4939 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4940 return;
4941
4942 case 'e':
4943 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4944 return;
4945
4946 case 'F':
4947 if (x == CONST0_RTX (GET_MODE (x)))
4948 str = reg_names [FR_REG (0)];
4949 else if (x == CONST1_RTX (GET_MODE (x)))
4950 str = reg_names [FR_REG (1)];
4951 else
4952 {
4953 gcc_assert (GET_CODE (x) == REG);
4954 str = reg_names [REGNO (x)];
4955 }
4956 fputs (str, file);
4957 return;
4958
4959 case 'G':
4960 {
4961 long val[4];
4962 REAL_VALUE_TYPE rv;
4963 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
4964 real_to_target (val, &rv, GET_MODE (x));
4965 if (GET_MODE (x) == SFmode)
4966 fprintf (file, "0x%08lx", val[0] & 0xffffffff);
4967 else if (GET_MODE (x) == DFmode)
4968 fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1])
4969 & 0xffffffff,
4970 (WORDS_BIG_ENDIAN ? val[1] : val[0])
4971 & 0xffffffff);
4972 else
4973 output_operand_lossage ("invalid %%G mode");
4974 }
4975 return;
4976
4977 case 'I':
4978 fputs (reg_names [REGNO (x) + 1], file);
4979 return;
4980
4981 case 'J':
4982 case 'j':
4983 {
4984 unsigned int regno = REGNO (XEXP (x, 0));
4985 if (GET_CODE (x) == EQ)
4986 regno += 1;
4987 if (code == 'j')
4988 regno ^= 1;
4989 fputs (reg_names [regno], file);
4990 }
4991 return;
4992
4993 case 'O':
4994 if (MEM_VOLATILE_P (x))
4995 fputs(".acq", file);
4996 return;
4997
4998 case 'P':
4999 {
5000 HOST_WIDE_INT value;
5001
5002 switch (GET_CODE (XEXP (x, 0)))
5003 {
5004 default:
5005 return;
5006
5007 case POST_MODIFY:
5008 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
5009 if (GET_CODE (x) == CONST_INT)
5010 value = INTVAL (x);
5011 else
5012 {
5013 gcc_assert (GET_CODE (x) == REG);
5014 fprintf (file, ", %s", reg_names[REGNO (x)]);
5015 return;
5016 }
5017 break;
5018
5019 case POST_INC:
5020 value = GET_MODE_SIZE (GET_MODE (x));
5021 break;
5022
5023 case POST_DEC:
5024 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
5025 break;
5026 }
5027
5028 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
5029 return;
5030 }
5031
5032 case 'Q':
5033 if (MEM_VOLATILE_P (x))
5034 fputs(".rel", file);
5035 return;
5036
5037 case 'R':
5038 if (x == CONST0_RTX (GET_MODE (x)))
5039 fputs(".s", file);
5040 else if (x == CONST1_RTX (GET_MODE (x)))
5041 fputs(".d", file);
5042 else if (x == CONST2_RTX (GET_MODE (x)))
5043 ;
5044 else
5045 output_operand_lossage ("invalid %%R value");
5046 return;
5047
5048 case 'S':
5049 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5050 return;
5051
5052 case 'T':
5053 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5054 {
5055 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
5056 return;
5057 }
5058 break;
5059
5060 case 'U':
5061 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
5062 {
5063 const char *prefix = "0x";
5064 if (INTVAL (x) & 0x80000000)
5065 {
5066 fprintf (file, "0xffffffff");
5067 prefix = "";
5068 }
5069 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
5070 return;
5071 }
5072 break;
5073
5074 case 'X':
5075 {
5076 unsigned int regno = REGNO (x);
5077 fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]);
5078 }
5079 return;
5080
5081 case 'r':
5082 /* If this operand is the constant zero, write it as register zero.
5083 Any register, zero, or CONST_INT value is OK here. */
5084 if (GET_CODE (x) == REG)
5085 fputs (reg_names[REGNO (x)], file);
5086 else if (x == CONST0_RTX (GET_MODE (x)))
5087 fputs ("r0", file);
5088 else if (GET_CODE (x) == CONST_INT)
5089 output_addr_const (file, x);
5090 else
5091 output_operand_lossage ("invalid %%r value");
5092 return;
5093
5094 case 'v':
5095 gcc_assert (GET_CODE (x) == CONST_VECTOR);
5096 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
5097 break;
5098
5099 case '+':
5100 {
5101 const char *which;
5102
5103 /* For conditional branches, returns or calls, substitute
5104 sptk, dptk, dpnt, or spnt for %s. */
5105 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
5106 if (x)
5107 {
5108 int pred_val = INTVAL (XEXP (x, 0));
5109
5110 /* Guess top and bottom 10% statically predicted. */
5111 if (pred_val < REG_BR_PROB_BASE / 50
5112 && br_prob_note_reliable_p (x))
5113 which = ".spnt";
5114 else if (pred_val < REG_BR_PROB_BASE / 2)
5115 which = ".dpnt";
5116 else if (pred_val < REG_BR_PROB_BASE / 100 * 98
5117 || !br_prob_note_reliable_p (x))
5118 which = ".dptk";
5119 else
5120 which = ".sptk";
5121 }
5122 else if (GET_CODE (current_output_insn) == CALL_INSN)
5123 which = ".sptk";
5124 else
5125 which = ".dptk";
5126
5127 fputs (which, file);
5128 return;
5129 }
5130
5131 case ',':
5132 x = current_insn_predicate;
5133 if (x)
5134 {
5135 unsigned int regno = REGNO (XEXP (x, 0));
5136 if (GET_CODE (x) == EQ)
5137 regno += 1;
5138 fprintf (file, "(%s) ", reg_names [regno]);
5139 }
5140 return;
5141
5142 default:
5143 output_operand_lossage ("ia64_print_operand: unknown code");
5144 return;
5145 }
5146
5147 switch (GET_CODE (x))
5148 {
5149 /* This happens for the spill/restore instructions. */
5150 case POST_INC:
5151 case POST_DEC:
5152 case POST_MODIFY:
5153 x = XEXP (x, 0);
5154 /* ... fall through ... */
5155
5156 case REG:
5157 fputs (reg_names [REGNO (x)], file);
5158 break;
5159
5160 case MEM:
5161 {
5162 rtx addr = XEXP (x, 0);
5163 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
5164 addr = XEXP (addr, 0);
5165 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
5166 break;
5167 }
5168
5169 default:
5170 output_addr_const (file, x);
5171 break;
5172 }
5173
5174 return;
5175 }
5176 \f
5177 /* Compute a (partial) cost for rtx X. Return true if the complete
5178 cost has been computed, and false if subexpressions should be
5179 scanned. In either case, *TOTAL contains the cost result. */
5180 /* ??? This is incomplete. */
5181
5182 static bool
5183 ia64_rtx_costs (rtx x, int code, int outer_code, int *total,
5184 bool speed ATTRIBUTE_UNUSED)
5185 {
5186 switch (code)
5187 {
5188 case CONST_INT:
5189 switch (outer_code)
5190 {
5191 case SET:
5192 *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1);
5193 return true;
5194 case PLUS:
5195 if (satisfies_constraint_I (x))
5196 *total = 0;
5197 else if (satisfies_constraint_J (x))
5198 *total = 1;
5199 else
5200 *total = COSTS_N_INSNS (1);
5201 return true;
5202 default:
5203 if (satisfies_constraint_K (x) || satisfies_constraint_L (x))
5204 *total = 0;
5205 else
5206 *total = COSTS_N_INSNS (1);
5207 return true;
5208 }
5209
5210 case CONST_DOUBLE:
5211 *total = COSTS_N_INSNS (1);
5212 return true;
5213
5214 case CONST:
5215 case SYMBOL_REF:
5216 case LABEL_REF:
5217 *total = COSTS_N_INSNS (3);
5218 return true;
5219
5220 case MULT:
5221 /* For multiplies wider than HImode, we have to go to the FPU,
5222 which normally involves copies. Plus there's the latency
5223 of the multiply itself, and the latency of the instructions to
5224 transfer integer regs to FP regs. */
5225 /* ??? Check for FP mode. */
5226 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
5227 *total = COSTS_N_INSNS (10);
5228 else
5229 *total = COSTS_N_INSNS (2);
5230 return true;
5231
5232 case PLUS:
5233 case MINUS:
5234 case ASHIFT:
5235 case ASHIFTRT:
5236 case LSHIFTRT:
5237 *total = COSTS_N_INSNS (1);
5238 return true;
5239
5240 case DIV:
5241 case UDIV:
5242 case MOD:
5243 case UMOD:
5244 /* We make divide expensive, so that divide-by-constant will be
5245 optimized to a multiply. */
5246 *total = COSTS_N_INSNS (60);
5247 return true;
5248
5249 default:
5250 return false;
5251 }
5252 }
5253
5254 /* Calculate the cost of moving data from a register in class FROM to
5255 one in class TO, using MODE. */
5256
5257 static int
5258 ia64_register_move_cost (enum machine_mode mode, reg_class_t from_i,
5259 reg_class_t to_i)
5260 {
5261 enum reg_class from = (enum reg_class) from_i;
5262 enum reg_class to = (enum reg_class) to_i;
5263
5264 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
5265 if (to == ADDL_REGS)
5266 to = GR_REGS;
5267 if (from == ADDL_REGS)
5268 from = GR_REGS;
5269
5270 /* All costs are symmetric, so reduce cases by putting the
5271 lower number class as the destination. */
5272 if (from < to)
5273 {
5274 enum reg_class tmp = to;
5275 to = from, from = tmp;
5276 }
5277
5278 /* Moving from FR<->GR in XFmode must be more expensive than 2,
5279 so that we get secondary memory reloads. Between FR_REGS,
5280 we have to make this at least as expensive as memory_move_cost
5281 to avoid spectacularly poor register class preferencing. */
5282 if (mode == XFmode || mode == RFmode)
5283 {
5284 if (to != GR_REGS || from != GR_REGS)
5285 return memory_move_cost (mode, to, false);
5286 else
5287 return 3;
5288 }
5289
5290 switch (to)
5291 {
5292 case PR_REGS:
5293 /* Moving between PR registers takes two insns. */
5294 if (from == PR_REGS)
5295 return 3;
5296 /* Moving between PR and anything but GR is impossible. */
5297 if (from != GR_REGS)
5298 return memory_move_cost (mode, to, false);
5299 break;
5300
5301 case BR_REGS:
5302 /* Moving between BR and anything but GR is impossible. */
5303 if (from != GR_REGS && from != GR_AND_BR_REGS)
5304 return memory_move_cost (mode, to, false);
5305 break;
5306
5307 case AR_I_REGS:
5308 case AR_M_REGS:
5309 /* Moving between AR and anything but GR is impossible. */
5310 if (from != GR_REGS)
5311 return memory_move_cost (mode, to, false);
5312 break;
5313
5314 case GR_REGS:
5315 case FR_REGS:
5316 case FP_REGS:
5317 case GR_AND_FR_REGS:
5318 case GR_AND_BR_REGS:
5319 case ALL_REGS:
5320 break;
5321
5322 default:
5323 gcc_unreachable ();
5324 }
5325
5326 return 2;
5327 }
5328
5329 /* Calculate the cost of moving data of MODE from a register to or from
5330 memory. */
5331
5332 static int
5333 ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
5334 reg_class_t rclass,
5335 bool in ATTRIBUTE_UNUSED)
5336 {
5337 if (rclass == GENERAL_REGS
5338 || rclass == FR_REGS
5339 || rclass == FP_REGS
5340 || rclass == GR_AND_FR_REGS)
5341 return 4;
5342 else
5343 return 10;
5344 }
5345
5346 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on RCLASS
5347 to use when copying X into that class. */
5348
5349 enum reg_class
5350 ia64_preferred_reload_class (rtx x, enum reg_class rclass)
5351 {
5352 switch (rclass)
5353 {
5354 case FR_REGS:
5355 case FP_REGS:
5356 /* Don't allow volatile mem reloads into floating point registers.
5357 This is defined to force reload to choose the r/m case instead
5358 of the f/f case when reloading (set (reg fX) (mem/v)). */
5359 if (MEM_P (x) && MEM_VOLATILE_P (x))
5360 return NO_REGS;
5361
5362 /* Force all unrecognized constants into the constant pool. */
5363 if (CONSTANT_P (x))
5364 return NO_REGS;
5365 break;
5366
5367 case AR_M_REGS:
5368 case AR_I_REGS:
5369 if (!OBJECT_P (x))
5370 return NO_REGS;
5371 break;
5372
5373 default:
5374 break;
5375 }
5376
5377 return rclass;
5378 }
5379
5380 /* This function returns the register class required for a secondary
5381 register when copying between one of the registers in RCLASS, and X,
5382 using MODE. A return value of NO_REGS means that no secondary register
5383 is required. */
5384
5385 enum reg_class
5386 ia64_secondary_reload_class (enum reg_class rclass,
5387 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
5388 {
5389 int regno = -1;
5390
5391 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
5392 regno = true_regnum (x);
5393
5394 switch (rclass)
5395 {
5396 case BR_REGS:
5397 case AR_M_REGS:
5398 case AR_I_REGS:
5399 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
5400 interaction. We end up with two pseudos with overlapping lifetimes
5401 both of which are equiv to the same constant, and both which need
5402 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
5403 changes depending on the path length, which means the qty_first_reg
5404 check in make_regs_eqv can give different answers at different times.
5405 At some point I'll probably need a reload_indi pattern to handle
5406 this.
5407
5408 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
5409 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
5410 non-general registers for good measure. */
5411 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
5412 return GR_REGS;
5413
5414 /* This is needed if a pseudo used as a call_operand gets spilled to a
5415 stack slot. */
5416 if (GET_CODE (x) == MEM)
5417 return GR_REGS;
5418 break;
5419
5420 case FR_REGS:
5421 case FP_REGS:
5422 /* Need to go through general registers to get to other class regs. */
5423 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
5424 return GR_REGS;
5425
5426 /* This can happen when a paradoxical subreg is an operand to the
5427 muldi3 pattern. */
5428 /* ??? This shouldn't be necessary after instruction scheduling is
5429 enabled, because paradoxical subregs are not accepted by
5430 register_operand when INSN_SCHEDULING is defined. Or alternatively,
5431 stop the paradoxical subreg stupidity in the *_operand functions
5432 in recog.c. */
5433 if (GET_CODE (x) == MEM
5434 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
5435 || GET_MODE (x) == QImode))
5436 return GR_REGS;
5437
5438 /* This can happen because of the ior/and/etc patterns that accept FP
5439 registers as operands. If the third operand is a constant, then it
5440 needs to be reloaded into a FP register. */
5441 if (GET_CODE (x) == CONST_INT)
5442 return GR_REGS;
5443
5444 /* This can happen because of register elimination in a muldi3 insn.
5445 E.g. `26107 * (unsigned long)&u'. */
5446 if (GET_CODE (x) == PLUS)
5447 return GR_REGS;
5448 break;
5449
5450 case PR_REGS:
5451 /* ??? This happens if we cse/gcse a BImode value across a call,
5452 and the function has a nonlocal goto. This is because global
5453 does not allocate call crossing pseudos to hard registers when
5454 crtl->has_nonlocal_goto is true. This is relatively
5455 common for C++ programs that use exceptions. To reproduce,
5456 return NO_REGS and compile libstdc++. */
5457 if (GET_CODE (x) == MEM)
5458 return GR_REGS;
5459
5460 /* This can happen when we take a BImode subreg of a DImode value,
5461 and that DImode value winds up in some non-GR register. */
5462 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
5463 return GR_REGS;
5464 break;
5465
5466 default:
5467 break;
5468 }
5469
5470 return NO_REGS;
5471 }
5472
5473 \f
5474 /* Implement targetm.unspec_may_trap_p hook. */
5475 static int
5476 ia64_unspec_may_trap_p (const_rtx x, unsigned flags)
5477 {
5478 if (GET_CODE (x) == UNSPEC)
5479 {
5480 switch (XINT (x, 1))
5481 {
5482 case UNSPEC_LDA:
5483 case UNSPEC_LDS:
5484 case UNSPEC_LDSA:
5485 case UNSPEC_LDCCLR:
5486 case UNSPEC_CHKACLR:
5487 case UNSPEC_CHKS:
5488 /* These unspecs are just wrappers. */
5489 return may_trap_p_1 (XVECEXP (x, 0, 0), flags);
5490 }
5491 }
5492
5493 return default_unspec_may_trap_p (x, flags);
5494 }
5495
5496 \f
5497 /* Parse the -mfixed-range= option string. */
5498
5499 static void
5500 fix_range (const char *const_str)
5501 {
5502 int i, first, last;
5503 char *str, *dash, *comma;
5504
5505 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
5506 REG2 are either register names or register numbers. The effect
5507 of this option is to mark the registers in the range from REG1 to
5508 REG2 as ``fixed'' so they won't be used by the compiler. This is
5509 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
5510
5511 i = strlen (const_str);
5512 str = (char *) alloca (i + 1);
5513 memcpy (str, const_str, i + 1);
5514
5515 while (1)
5516 {
5517 dash = strchr (str, '-');
5518 if (!dash)
5519 {
5520 warning (0, "value of -mfixed-range must have form REG1-REG2");
5521 return;
5522 }
5523 *dash = '\0';
5524
5525 comma = strchr (dash + 1, ',');
5526 if (comma)
5527 *comma = '\0';
5528
5529 first = decode_reg_name (str);
5530 if (first < 0)
5531 {
5532 warning (0, "unknown register name: %s", str);
5533 return;
5534 }
5535
5536 last = decode_reg_name (dash + 1);
5537 if (last < 0)
5538 {
5539 warning (0, "unknown register name: %s", dash + 1);
5540 return;
5541 }
5542
5543 *dash = '-';
5544
5545 if (first > last)
5546 {
5547 warning (0, "%s-%s is an empty range", str, dash + 1);
5548 return;
5549 }
5550
5551 for (i = first; i <= last; ++i)
5552 fixed_regs[i] = call_used_regs[i] = 1;
5553
5554 if (!comma)
5555 break;
5556
5557 *comma = ',';
5558 str = comma + 1;
5559 }
5560 }
5561
5562 /* Implement TARGET_HANDLE_OPTION. */
5563
5564 static bool
5565 ia64_handle_option (size_t code, const char *arg, int value)
5566 {
5567 switch (code)
5568 {
5569 case OPT_G:
5570 g_switch_value = value;
5571 g_switch_set = true;
5572 return true;
5573
5574 case OPT_mfixed_range_:
5575 fix_range (arg);
5576 return true;
5577
5578 case OPT_mtls_size_:
5579 if (value != 14 && value != 22 && value != 64)
5580 error ("bad value %<%s%> for -mtls-size= switch", arg);
5581 return true;
5582
5583 case OPT_mtune_:
5584 {
5585 static struct pta
5586 {
5587 const char *name; /* processor name or nickname. */
5588 enum processor_type processor;
5589 }
5590 const processor_alias_table[] =
5591 {
5592 {"itanium2", PROCESSOR_ITANIUM2},
5593 {"mckinley", PROCESSOR_ITANIUM2},
5594 };
5595 int const pta_size = ARRAY_SIZE (processor_alias_table);
5596 int i;
5597
5598 for (i = 0; i < pta_size; i++)
5599 if (!strcmp (arg, processor_alias_table[i].name))
5600 {
5601 ia64_tune = processor_alias_table[i].processor;
5602 break;
5603 }
5604 if (i == pta_size)
5605 error ("bad value %<%s%> for -mtune= switch", arg);
5606 return true;
5607 }
5608
5609 default:
5610 return true;
5611 }
5612 }
5613
5614 /* Implement TARGET_OPTION_OVERRIDE. */
5615
5616 static void
5617 ia64_option_override (void)
5618 {
5619 if (TARGET_AUTO_PIC)
5620 target_flags |= MASK_CONST_GP;
5621
5622 /* Numerous experiment shows that IRA based loop pressure
5623 calculation works better for RTL loop invariant motion on targets
5624 with enough (>= 32) registers. It is an expensive optimization.
5625 So it is on only for peak performance. */
5626 if (optimize >= 3)
5627 flag_ira_loop_pressure = 1;
5628
5629
5630 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
5631
5632 init_machine_status = ia64_init_machine_status;
5633
5634 if (align_functions <= 0)
5635 align_functions = 64;
5636 if (align_loops <= 0)
5637 align_loops = 32;
5638 if (TARGET_ABI_OPEN_VMS)
5639 flag_no_common = 1;
5640
5641 ia64_override_options_after_change();
5642 }
5643
5644 /* Implement targetm.override_options_after_change. */
5645
5646 static void
5647 ia64_override_options_after_change (void)
5648 {
5649 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
5650 flag_schedule_insns_after_reload = 0;
5651
5652 if (optimize >= 3
5653 && !global_options_set.x_flag_selective_scheduling
5654 && !global_options_set.x_flag_selective_scheduling2)
5655 {
5656 flag_selective_scheduling2 = 1;
5657 flag_sel_sched_pipelining = 1;
5658 }
5659 if (mflag_sched_control_spec == 2)
5660 {
5661 /* Control speculation is on by default for the selective scheduler,
5662 but not for the Haifa scheduler. */
5663 mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0;
5664 }
5665 if (flag_sel_sched_pipelining && flag_auto_inc_dec)
5666 {
5667 /* FIXME: remove this when we'd implement breaking autoinsns as
5668 a transformation. */
5669 flag_auto_inc_dec = 0;
5670 }
5671 }
5672
5673 /* Initialize the record of emitted frame related registers. */
5674
5675 void ia64_init_expanders (void)
5676 {
5677 memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs));
5678 }
5679
5680 static struct machine_function *
5681 ia64_init_machine_status (void)
5682 {
5683 return ggc_alloc_cleared_machine_function ();
5684 }
5685 \f
5686 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
5687 static enum attr_type ia64_safe_type (rtx);
5688
5689 static enum attr_itanium_class
5690 ia64_safe_itanium_class (rtx insn)
5691 {
5692 if (recog_memoized (insn) >= 0)
5693 return get_attr_itanium_class (insn);
5694 else if (DEBUG_INSN_P (insn))
5695 return ITANIUM_CLASS_IGNORE;
5696 else
5697 return ITANIUM_CLASS_UNKNOWN;
5698 }
5699
5700 static enum attr_type
5701 ia64_safe_type (rtx insn)
5702 {
5703 if (recog_memoized (insn) >= 0)
5704 return get_attr_type (insn);
5705 else
5706 return TYPE_UNKNOWN;
5707 }
5708 \f
5709 /* The following collection of routines emit instruction group stop bits as
5710 necessary to avoid dependencies. */
5711
5712 /* Need to track some additional registers as far as serialization is
5713 concerned so we can properly handle br.call and br.ret. We could
5714 make these registers visible to gcc, but since these registers are
5715 never explicitly used in gcc generated code, it seems wasteful to
5716 do so (plus it would make the call and return patterns needlessly
5717 complex). */
5718 #define REG_RP (BR_REG (0))
5719 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5720 /* This is used for volatile asms which may require a stop bit immediately
5721 before and after them. */
5722 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5723 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5724 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5725
5726 /* For each register, we keep track of how it has been written in the
5727 current instruction group.
5728
5729 If a register is written unconditionally (no qualifying predicate),
5730 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5731
5732 If a register is written if its qualifying predicate P is true, we
5733 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5734 may be written again by the complement of P (P^1) and when this happens,
5735 WRITE_COUNT gets set to 2.
5736
5737 The result of this is that whenever an insn attempts to write a register
5738 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5739
5740 If a predicate register is written by a floating-point insn, we set
5741 WRITTEN_BY_FP to true.
5742
5743 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5744 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5745
5746 #if GCC_VERSION >= 4000
5747 #define RWS_FIELD_TYPE __extension__ unsigned short
5748 #else
5749 #define RWS_FIELD_TYPE unsigned int
5750 #endif
5751 struct reg_write_state
5752 {
5753 RWS_FIELD_TYPE write_count : 2;
5754 RWS_FIELD_TYPE first_pred : 10;
5755 RWS_FIELD_TYPE written_by_fp : 1;
5756 RWS_FIELD_TYPE written_by_and : 1;
5757 RWS_FIELD_TYPE written_by_or : 1;
5758 };
5759
5760 /* Cumulative info for the current instruction group. */
5761 struct reg_write_state rws_sum[NUM_REGS];
5762 #ifdef ENABLE_CHECKING
5763 /* Bitmap whether a register has been written in the current insn. */
5764 HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1)
5765 / HOST_BITS_PER_WIDEST_FAST_INT];
5766
5767 static inline void
5768 rws_insn_set (int regno)
5769 {
5770 gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno));
5771 SET_HARD_REG_BIT (rws_insn, regno);
5772 }
5773
5774 static inline int
5775 rws_insn_test (int regno)
5776 {
5777 return TEST_HARD_REG_BIT (rws_insn, regno);
5778 }
5779 #else
5780 /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */
5781 unsigned char rws_insn[2];
5782
5783 static inline void
5784 rws_insn_set (int regno)
5785 {
5786 if (regno == REG_AR_CFM)
5787 rws_insn[0] = 1;
5788 else if (regno == REG_VOLATILE)
5789 rws_insn[1] = 1;
5790 }
5791
5792 static inline int
5793 rws_insn_test (int regno)
5794 {
5795 if (regno == REG_AR_CFM)
5796 return rws_insn[0];
5797 if (regno == REG_VOLATILE)
5798 return rws_insn[1];
5799 return 0;
5800 }
5801 #endif
5802
5803 /* Indicates whether this is the first instruction after a stop bit,
5804 in which case we don't need another stop bit. Without this,
5805 ia64_variable_issue will die when scheduling an alloc. */
5806 static int first_instruction;
5807
5808 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5809 RTL for one instruction. */
5810 struct reg_flags
5811 {
5812 unsigned int is_write : 1; /* Is register being written? */
5813 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5814 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5815 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5816 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5817 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
5818 };
5819
5820 static void rws_update (int, struct reg_flags, int);
5821 static int rws_access_regno (int, struct reg_flags, int);
5822 static int rws_access_reg (rtx, struct reg_flags, int);
5823 static void update_set_flags (rtx, struct reg_flags *);
5824 static int set_src_needs_barrier (rtx, struct reg_flags, int);
5825 static int rtx_needs_barrier (rtx, struct reg_flags, int);
5826 static void init_insn_group_barriers (void);
5827 static int group_barrier_needed (rtx);
5828 static int safe_group_barrier_needed (rtx);
5829 static int in_safe_group_barrier;
5830
5831 /* Update *RWS for REGNO, which is being written by the current instruction,
5832 with predicate PRED, and associated register flags in FLAGS. */
5833
5834 static void
5835 rws_update (int regno, struct reg_flags flags, int pred)
5836 {
5837 if (pred)
5838 rws_sum[regno].write_count++;
5839 else
5840 rws_sum[regno].write_count = 2;
5841 rws_sum[regno].written_by_fp |= flags.is_fp;
5842 /* ??? Not tracking and/or across differing predicates. */
5843 rws_sum[regno].written_by_and = flags.is_and;
5844 rws_sum[regno].written_by_or = flags.is_or;
5845 rws_sum[regno].first_pred = pred;
5846 }
5847
5848 /* Handle an access to register REGNO of type FLAGS using predicate register
5849 PRED. Update rws_sum array. Return 1 if this access creates
5850 a dependency with an earlier instruction in the same group. */
5851
5852 static int
5853 rws_access_regno (int regno, struct reg_flags flags, int pred)
5854 {
5855 int need_barrier = 0;
5856
5857 gcc_assert (regno < NUM_REGS);
5858
5859 if (! PR_REGNO_P (regno))
5860 flags.is_and = flags.is_or = 0;
5861
5862 if (flags.is_write)
5863 {
5864 int write_count;
5865
5866 rws_insn_set (regno);
5867 write_count = rws_sum[regno].write_count;
5868
5869 switch (write_count)
5870 {
5871 case 0:
5872 /* The register has not been written yet. */
5873 if (!in_safe_group_barrier)
5874 rws_update (regno, flags, pred);
5875 break;
5876
5877 case 1:
5878 /* The register has been written via a predicate. If this is
5879 not a complementary predicate, then we need a barrier. */
5880 /* ??? This assumes that P and P+1 are always complementary
5881 predicates for P even. */
5882 if (flags.is_and && rws_sum[regno].written_by_and)
5883 ;
5884 else if (flags.is_or && rws_sum[regno].written_by_or)
5885 ;
5886 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5887 need_barrier = 1;
5888 if (!in_safe_group_barrier)
5889 rws_update (regno, flags, pred);
5890 break;
5891
5892 case 2:
5893 /* The register has been unconditionally written already. We
5894 need a barrier. */
5895 if (flags.is_and && rws_sum[regno].written_by_and)
5896 ;
5897 else if (flags.is_or && rws_sum[regno].written_by_or)
5898 ;
5899 else
5900 need_barrier = 1;
5901 if (!in_safe_group_barrier)
5902 {
5903 rws_sum[regno].written_by_and = flags.is_and;
5904 rws_sum[regno].written_by_or = flags.is_or;
5905 }
5906 break;
5907
5908 default:
5909 gcc_unreachable ();
5910 }
5911 }
5912 else
5913 {
5914 if (flags.is_branch)
5915 {
5916 /* Branches have several RAW exceptions that allow to avoid
5917 barriers. */
5918
5919 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5920 /* RAW dependencies on branch regs are permissible as long
5921 as the writer is a non-branch instruction. Since we
5922 never generate code that uses a branch register written
5923 by a branch instruction, handling this case is
5924 easy. */
5925 return 0;
5926
5927 if (REGNO_REG_CLASS (regno) == PR_REGS
5928 && ! rws_sum[regno].written_by_fp)
5929 /* The predicates of a branch are available within the
5930 same insn group as long as the predicate was written by
5931 something other than a floating-point instruction. */
5932 return 0;
5933 }
5934
5935 if (flags.is_and && rws_sum[regno].written_by_and)
5936 return 0;
5937 if (flags.is_or && rws_sum[regno].written_by_or)
5938 return 0;
5939
5940 switch (rws_sum[regno].write_count)
5941 {
5942 case 0:
5943 /* The register has not been written yet. */
5944 break;
5945
5946 case 1:
5947 /* The register has been written via a predicate. If this is
5948 not a complementary predicate, then we need a barrier. */
5949 /* ??? This assumes that P and P+1 are always complementary
5950 predicates for P even. */
5951 if ((rws_sum[regno].first_pred ^ 1) != pred)
5952 need_barrier = 1;
5953 break;
5954
5955 case 2:
5956 /* The register has been unconditionally written already. We
5957 need a barrier. */
5958 need_barrier = 1;
5959 break;
5960
5961 default:
5962 gcc_unreachable ();
5963 }
5964 }
5965
5966 return need_barrier;
5967 }
5968
5969 static int
5970 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5971 {
5972 int regno = REGNO (reg);
5973 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5974
5975 if (n == 1)
5976 return rws_access_regno (regno, flags, pred);
5977 else
5978 {
5979 int need_barrier = 0;
5980 while (--n >= 0)
5981 need_barrier |= rws_access_regno (regno + n, flags, pred);
5982 return need_barrier;
5983 }
5984 }
5985
5986 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5987 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5988
5989 static void
5990 update_set_flags (rtx x, struct reg_flags *pflags)
5991 {
5992 rtx src = SET_SRC (x);
5993
5994 switch (GET_CODE (src))
5995 {
5996 case CALL:
5997 return;
5998
5999 case IF_THEN_ELSE:
6000 /* There are four cases here:
6001 (1) The destination is (pc), in which case this is a branch,
6002 nothing here applies.
6003 (2) The destination is ar.lc, in which case this is a
6004 doloop_end_internal,
6005 (3) The destination is an fp register, in which case this is
6006 an fselect instruction.
6007 (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case
6008 this is a check load.
6009 In all cases, nothing we do in this function applies. */
6010 return;
6011
6012 default:
6013 if (COMPARISON_P (src)
6014 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
6015 /* Set pflags->is_fp to 1 so that we know we're dealing
6016 with a floating point comparison when processing the
6017 destination of the SET. */
6018 pflags->is_fp = 1;
6019
6020 /* Discover if this is a parallel comparison. We only handle
6021 and.orcm and or.andcm at present, since we must retain a
6022 strict inverse on the predicate pair. */
6023 else if (GET_CODE (src) == AND)
6024 pflags->is_and = 1;
6025 else if (GET_CODE (src) == IOR)
6026 pflags->is_or = 1;
6027
6028 break;
6029 }
6030 }
6031
6032 /* Subroutine of rtx_needs_barrier; this function determines whether the
6033 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
6034 are as in rtx_needs_barrier. COND is an rtx that holds the condition
6035 for this insn. */
6036
6037 static int
6038 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
6039 {
6040 int need_barrier = 0;
6041 rtx dst;
6042 rtx src = SET_SRC (x);
6043
6044 if (GET_CODE (src) == CALL)
6045 /* We don't need to worry about the result registers that
6046 get written by subroutine call. */
6047 return rtx_needs_barrier (src, flags, pred);
6048 else if (SET_DEST (x) == pc_rtx)
6049 {
6050 /* X is a conditional branch. */
6051 /* ??? This seems redundant, as the caller sets this bit for
6052 all JUMP_INSNs. */
6053 if (!ia64_spec_check_src_p (src))
6054 flags.is_branch = 1;
6055 return rtx_needs_barrier (src, flags, pred);
6056 }
6057
6058 if (ia64_spec_check_src_p (src))
6059 /* Avoid checking one register twice (in condition
6060 and in 'then' section) for ldc pattern. */
6061 {
6062 gcc_assert (REG_P (XEXP (src, 2)));
6063 need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred);
6064
6065 /* We process MEM below. */
6066 src = XEXP (src, 1);
6067 }
6068
6069 need_barrier |= rtx_needs_barrier (src, flags, pred);
6070
6071 dst = SET_DEST (x);
6072 if (GET_CODE (dst) == ZERO_EXTRACT)
6073 {
6074 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
6075 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
6076 }
6077 return need_barrier;
6078 }
6079
6080 /* Handle an access to rtx X of type FLAGS using predicate register
6081 PRED. Return 1 if this access creates a dependency with an earlier
6082 instruction in the same group. */
6083
6084 static int
6085 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
6086 {
6087 int i, j;
6088 int is_complemented = 0;
6089 int need_barrier = 0;
6090 const char *format_ptr;
6091 struct reg_flags new_flags;
6092 rtx cond;
6093
6094 if (! x)
6095 return 0;
6096
6097 new_flags = flags;
6098
6099 switch (GET_CODE (x))
6100 {
6101 case SET:
6102 update_set_flags (x, &new_flags);
6103 need_barrier = set_src_needs_barrier (x, new_flags, pred);
6104 if (GET_CODE (SET_SRC (x)) != CALL)
6105 {
6106 new_flags.is_write = 1;
6107 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
6108 }
6109 break;
6110
6111 case CALL:
6112 new_flags.is_write = 0;
6113 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6114
6115 /* Avoid multiple register writes, in case this is a pattern with
6116 multiple CALL rtx. This avoids a failure in rws_access_reg. */
6117 if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM))
6118 {
6119 new_flags.is_write = 1;
6120 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
6121 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
6122 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6123 }
6124 break;
6125
6126 case COND_EXEC:
6127 /* X is a predicated instruction. */
6128
6129 cond = COND_EXEC_TEST (x);
6130 gcc_assert (!pred);
6131 need_barrier = rtx_needs_barrier (cond, flags, 0);
6132
6133 if (GET_CODE (cond) == EQ)
6134 is_complemented = 1;
6135 cond = XEXP (cond, 0);
6136 gcc_assert (GET_CODE (cond) == REG
6137 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
6138 pred = REGNO (cond);
6139 if (is_complemented)
6140 ++pred;
6141
6142 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
6143 return need_barrier;
6144
6145 case CLOBBER:
6146 case USE:
6147 /* Clobber & use are for earlier compiler-phases only. */
6148 break;
6149
6150 case ASM_OPERANDS:
6151 case ASM_INPUT:
6152 /* We always emit stop bits for traditional asms. We emit stop bits
6153 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
6154 if (GET_CODE (x) != ASM_OPERANDS
6155 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
6156 {
6157 /* Avoid writing the register multiple times if we have multiple
6158 asm outputs. This avoids a failure in rws_access_reg. */
6159 if (! rws_insn_test (REG_VOLATILE))
6160 {
6161 new_flags.is_write = 1;
6162 rws_access_regno (REG_VOLATILE, new_flags, pred);
6163 }
6164 return 1;
6165 }
6166
6167 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
6168 We cannot just fall through here since then we would be confused
6169 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
6170 traditional asms unlike their normal usage. */
6171
6172 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
6173 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
6174 need_barrier = 1;
6175 break;
6176
6177 case PARALLEL:
6178 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6179 {
6180 rtx pat = XVECEXP (x, 0, i);
6181 switch (GET_CODE (pat))
6182 {
6183 case SET:
6184 update_set_flags (pat, &new_flags);
6185 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
6186 break;
6187
6188 case USE:
6189 case CALL:
6190 case ASM_OPERANDS:
6191 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6192 break;
6193
6194 case CLOBBER:
6195 case RETURN:
6196 break;
6197
6198 default:
6199 gcc_unreachable ();
6200 }
6201 }
6202 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
6203 {
6204 rtx pat = XVECEXP (x, 0, i);
6205 if (GET_CODE (pat) == SET)
6206 {
6207 if (GET_CODE (SET_SRC (pat)) != CALL)
6208 {
6209 new_flags.is_write = 1;
6210 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
6211 pred);
6212 }
6213 }
6214 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
6215 need_barrier |= rtx_needs_barrier (pat, flags, pred);
6216 }
6217 break;
6218
6219 case SUBREG:
6220 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
6221 break;
6222 case REG:
6223 if (REGNO (x) == AR_UNAT_REGNUM)
6224 {
6225 for (i = 0; i < 64; ++i)
6226 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
6227 }
6228 else
6229 need_barrier = rws_access_reg (x, flags, pred);
6230 break;
6231
6232 case MEM:
6233 /* Find the regs used in memory address computation. */
6234 new_flags.is_write = 0;
6235 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6236 break;
6237
6238 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
6239 case SYMBOL_REF: case LABEL_REF: case CONST:
6240 break;
6241
6242 /* Operators with side-effects. */
6243 case POST_INC: case POST_DEC:
6244 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6245
6246 new_flags.is_write = 0;
6247 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6248 new_flags.is_write = 1;
6249 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6250 break;
6251
6252 case POST_MODIFY:
6253 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
6254
6255 new_flags.is_write = 0;
6256 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
6257 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6258 new_flags.is_write = 1;
6259 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
6260 break;
6261
6262 /* Handle common unary and binary ops for efficiency. */
6263 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
6264 case MOD: case UDIV: case UMOD: case AND: case IOR:
6265 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
6266 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
6267 case NE: case EQ: case GE: case GT: case LE:
6268 case LT: case GEU: case GTU: case LEU: case LTU:
6269 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
6270 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
6271 break;
6272
6273 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
6274 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
6275 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
6276 case SQRT: case FFS: case POPCOUNT:
6277 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6278 break;
6279
6280 case VEC_SELECT:
6281 /* VEC_SELECT's second argument is a PARALLEL with integers that
6282 describe the elements selected. On ia64, those integers are
6283 always constants. Avoid walking the PARALLEL so that we don't
6284 get confused with "normal" parallels and then die. */
6285 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
6286 break;
6287
6288 case UNSPEC:
6289 switch (XINT (x, 1))
6290 {
6291 case UNSPEC_LTOFF_DTPMOD:
6292 case UNSPEC_LTOFF_DTPREL:
6293 case UNSPEC_DTPREL:
6294 case UNSPEC_LTOFF_TPREL:
6295 case UNSPEC_TPREL:
6296 case UNSPEC_PRED_REL_MUTEX:
6297 case UNSPEC_PIC_CALL:
6298 case UNSPEC_MF:
6299 case UNSPEC_FETCHADD_ACQ:
6300 case UNSPEC_BSP_VALUE:
6301 case UNSPEC_FLUSHRS:
6302 case UNSPEC_BUNDLE_SELECTOR:
6303 break;
6304
6305 case UNSPEC_GR_SPILL:
6306 case UNSPEC_GR_RESTORE:
6307 {
6308 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
6309 HOST_WIDE_INT bit = (offset >> 3) & 63;
6310
6311 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6312 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
6313 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
6314 new_flags, pred);
6315 break;
6316 }
6317
6318 case UNSPEC_FR_SPILL:
6319 case UNSPEC_FR_RESTORE:
6320 case UNSPEC_GETF_EXP:
6321 case UNSPEC_SETF_EXP:
6322 case UNSPEC_ADDP4:
6323 case UNSPEC_FR_SQRT_RECIP_APPROX:
6324 case UNSPEC_FR_SQRT_RECIP_APPROX_RES:
6325 case UNSPEC_LDA:
6326 case UNSPEC_LDS:
6327 case UNSPEC_LDS_A:
6328 case UNSPEC_LDSA:
6329 case UNSPEC_CHKACLR:
6330 case UNSPEC_CHKS:
6331 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6332 break;
6333
6334 case UNSPEC_FR_RECIP_APPROX:
6335 case UNSPEC_SHRP:
6336 case UNSPEC_COPYSIGN:
6337 case UNSPEC_FR_RECIP_APPROX_RES:
6338 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
6339 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6340 break;
6341
6342 case UNSPEC_CMPXCHG_ACQ:
6343 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
6344 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
6345 break;
6346
6347 default:
6348 gcc_unreachable ();
6349 }
6350 break;
6351
6352 case UNSPEC_VOLATILE:
6353 switch (XINT (x, 1))
6354 {
6355 case UNSPECV_ALLOC:
6356 /* Alloc must always be the first instruction of a group.
6357 We force this by always returning true. */
6358 /* ??? We might get better scheduling if we explicitly check for
6359 input/local/output register dependencies, and modify the
6360 scheduler so that alloc is always reordered to the start of
6361 the current group. We could then eliminate all of the
6362 first_instruction code. */
6363 rws_access_regno (AR_PFS_REGNUM, flags, pred);
6364
6365 new_flags.is_write = 1;
6366 rws_access_regno (REG_AR_CFM, new_flags, pred);
6367 return 1;
6368
6369 case UNSPECV_SET_BSP:
6370 need_barrier = 1;
6371 break;
6372
6373 case UNSPECV_BLOCKAGE:
6374 case UNSPECV_INSN_GROUP_BARRIER:
6375 case UNSPECV_BREAK:
6376 case UNSPECV_PSAC_ALL:
6377 case UNSPECV_PSAC_NORMAL:
6378 return 0;
6379
6380 default:
6381 gcc_unreachable ();
6382 }
6383 break;
6384
6385 case RETURN:
6386 new_flags.is_write = 0;
6387 need_barrier = rws_access_regno (REG_RP, flags, pred);
6388 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
6389
6390 new_flags.is_write = 1;
6391 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
6392 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
6393 break;
6394
6395 default:
6396 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
6397 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6398 switch (format_ptr[i])
6399 {
6400 case '0': /* unused field */
6401 case 'i': /* integer */
6402 case 'n': /* note */
6403 case 'w': /* wide integer */
6404 case 's': /* pointer to string */
6405 case 'S': /* optional pointer to string */
6406 break;
6407
6408 case 'e':
6409 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
6410 need_barrier = 1;
6411 break;
6412
6413 case 'E':
6414 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
6415 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
6416 need_barrier = 1;
6417 break;
6418
6419 default:
6420 gcc_unreachable ();
6421 }
6422 break;
6423 }
6424 return need_barrier;
6425 }
6426
6427 /* Clear out the state for group_barrier_needed at the start of a
6428 sequence of insns. */
6429
6430 static void
6431 init_insn_group_barriers (void)
6432 {
6433 memset (rws_sum, 0, sizeof (rws_sum));
6434 first_instruction = 1;
6435 }
6436
6437 /* Given the current state, determine whether a group barrier (a stop bit) is
6438 necessary before INSN. Return nonzero if so. This modifies the state to
6439 include the effects of INSN as a side-effect. */
6440
6441 static int
6442 group_barrier_needed (rtx insn)
6443 {
6444 rtx pat;
6445 int need_barrier = 0;
6446 struct reg_flags flags;
6447
6448 memset (&flags, 0, sizeof (flags));
6449 switch (GET_CODE (insn))
6450 {
6451 case NOTE:
6452 case DEBUG_INSN:
6453 break;
6454
6455 case BARRIER:
6456 /* A barrier doesn't imply an instruction group boundary. */
6457 break;
6458
6459 case CODE_LABEL:
6460 memset (rws_insn, 0, sizeof (rws_insn));
6461 return 1;
6462
6463 case CALL_INSN:
6464 flags.is_branch = 1;
6465 flags.is_sibcall = SIBLING_CALL_P (insn);
6466 memset (rws_insn, 0, sizeof (rws_insn));
6467
6468 /* Don't bundle a call following another call. */
6469 if ((pat = prev_active_insn (insn))
6470 && GET_CODE (pat) == CALL_INSN)
6471 {
6472 need_barrier = 1;
6473 break;
6474 }
6475
6476 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
6477 break;
6478
6479 case JUMP_INSN:
6480 if (!ia64_spec_check_p (insn))
6481 flags.is_branch = 1;
6482
6483 /* Don't bundle a jump following a call. */
6484 if ((pat = prev_active_insn (insn))
6485 && GET_CODE (pat) == CALL_INSN)
6486 {
6487 need_barrier = 1;
6488 break;
6489 }
6490 /* FALLTHRU */
6491
6492 case INSN:
6493 if (GET_CODE (PATTERN (insn)) == USE
6494 || GET_CODE (PATTERN (insn)) == CLOBBER)
6495 /* Don't care about USE and CLOBBER "insns"---those are used to
6496 indicate to the optimizer that it shouldn't get rid of
6497 certain operations. */
6498 break;
6499
6500 pat = PATTERN (insn);
6501
6502 /* Ug. Hack hacks hacked elsewhere. */
6503 switch (recog_memoized (insn))
6504 {
6505 /* We play dependency tricks with the epilogue in order
6506 to get proper schedules. Undo this for dv analysis. */
6507 case CODE_FOR_epilogue_deallocate_stack:
6508 case CODE_FOR_prologue_allocate_stack:
6509 pat = XVECEXP (pat, 0, 0);
6510 break;
6511
6512 /* The pattern we use for br.cloop confuses the code above.
6513 The second element of the vector is representative. */
6514 case CODE_FOR_doloop_end_internal:
6515 pat = XVECEXP (pat, 0, 1);
6516 break;
6517
6518 /* Doesn't generate code. */
6519 case CODE_FOR_pred_rel_mutex:
6520 case CODE_FOR_prologue_use:
6521 return 0;
6522
6523 default:
6524 break;
6525 }
6526
6527 memset (rws_insn, 0, sizeof (rws_insn));
6528 need_barrier = rtx_needs_barrier (pat, flags, 0);
6529
6530 /* Check to see if the previous instruction was a volatile
6531 asm. */
6532 if (! need_barrier)
6533 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
6534
6535 break;
6536
6537 default:
6538 gcc_unreachable ();
6539 }
6540
6541 if (first_instruction && INSN_P (insn)
6542 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6543 && GET_CODE (PATTERN (insn)) != USE
6544 && GET_CODE (PATTERN (insn)) != CLOBBER)
6545 {
6546 need_barrier = 0;
6547 first_instruction = 0;
6548 }
6549
6550 return need_barrier;
6551 }
6552
6553 /* Like group_barrier_needed, but do not clobber the current state. */
6554
6555 static int
6556 safe_group_barrier_needed (rtx insn)
6557 {
6558 int saved_first_instruction;
6559 int t;
6560
6561 saved_first_instruction = first_instruction;
6562 in_safe_group_barrier = 1;
6563
6564 t = group_barrier_needed (insn);
6565
6566 first_instruction = saved_first_instruction;
6567 in_safe_group_barrier = 0;
6568
6569 return t;
6570 }
6571
6572 /* Scan the current function and insert stop bits as necessary to
6573 eliminate dependencies. This function assumes that a final
6574 instruction scheduling pass has been run which has already
6575 inserted most of the necessary stop bits. This function only
6576 inserts new ones at basic block boundaries, since these are
6577 invisible to the scheduler. */
6578
6579 static void
6580 emit_insn_group_barriers (FILE *dump)
6581 {
6582 rtx insn;
6583 rtx last_label = 0;
6584 int insns_since_last_label = 0;
6585
6586 init_insn_group_barriers ();
6587
6588 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6589 {
6590 if (GET_CODE (insn) == CODE_LABEL)
6591 {
6592 if (insns_since_last_label)
6593 last_label = insn;
6594 insns_since_last_label = 0;
6595 }
6596 else if (GET_CODE (insn) == NOTE
6597 && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK)
6598 {
6599 if (insns_since_last_label)
6600 last_label = insn;
6601 insns_since_last_label = 0;
6602 }
6603 else if (GET_CODE (insn) == INSN
6604 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
6605 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
6606 {
6607 init_insn_group_barriers ();
6608 last_label = 0;
6609 }
6610 else if (NONDEBUG_INSN_P (insn))
6611 {
6612 insns_since_last_label = 1;
6613
6614 if (group_barrier_needed (insn))
6615 {
6616 if (last_label)
6617 {
6618 if (dump)
6619 fprintf (dump, "Emitting stop before label %d\n",
6620 INSN_UID (last_label));
6621 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
6622 insn = last_label;
6623
6624 init_insn_group_barriers ();
6625 last_label = 0;
6626 }
6627 }
6628 }
6629 }
6630 }
6631
6632 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
6633 This function has to emit all necessary group barriers. */
6634
6635 static void
6636 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
6637 {
6638 rtx insn;
6639
6640 init_insn_group_barriers ();
6641
6642 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6643 {
6644 if (GET_CODE (insn) == BARRIER)
6645 {
6646 rtx last = prev_active_insn (insn);
6647
6648 if (! last)
6649 continue;
6650 if (GET_CODE (last) == JUMP_INSN
6651 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6652 last = prev_active_insn (last);
6653 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6654 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6655
6656 init_insn_group_barriers ();
6657 }
6658 else if (NONDEBUG_INSN_P (insn))
6659 {
6660 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6661 init_insn_group_barriers ();
6662 else if (group_barrier_needed (insn))
6663 {
6664 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
6665 init_insn_group_barriers ();
6666 group_barrier_needed (insn);
6667 }
6668 }
6669 }
6670 }
6671
6672 \f
6673
6674 /* Instruction scheduling support. */
6675
6676 #define NR_BUNDLES 10
6677
6678 /* A list of names of all available bundles. */
6679
6680 static const char *bundle_name [NR_BUNDLES] =
6681 {
6682 ".mii",
6683 ".mmi",
6684 ".mfi",
6685 ".mmf",
6686 #if NR_BUNDLES == 10
6687 ".bbb",
6688 ".mbb",
6689 #endif
6690 ".mib",
6691 ".mmb",
6692 ".mfb",
6693 ".mlx"
6694 };
6695
6696 /* Nonzero if we should insert stop bits into the schedule. */
6697
6698 int ia64_final_schedule = 0;
6699
6700 /* Codes of the corresponding queried units: */
6701
6702 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
6703 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
6704
6705 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
6706 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
6707
6708 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
6709
6710 /* The following variable value is an insn group barrier. */
6711
6712 static rtx dfa_stop_insn;
6713
6714 /* The following variable value is the last issued insn. */
6715
6716 static rtx last_scheduled_insn;
6717
6718 /* The following variable value is pointer to a DFA state used as
6719 temporary variable. */
6720
6721 static state_t temp_dfa_state = NULL;
6722
6723 /* The following variable value is DFA state after issuing the last
6724 insn. */
6725
6726 static state_t prev_cycle_state = NULL;
6727
6728 /* The following array element values are TRUE if the corresponding
6729 insn requires to add stop bits before it. */
6730
6731 static char *stops_p = NULL;
6732
6733 /* The following variable is used to set up the mentioned above array. */
6734
6735 static int stop_before_p = 0;
6736
6737 /* The following variable value is length of the arrays `clocks' and
6738 `add_cycles'. */
6739
6740 static int clocks_length;
6741
6742 /* The following variable value is number of data speculations in progress. */
6743 static int pending_data_specs = 0;
6744
6745 /* Number of memory references on current and three future processor cycles. */
6746 static char mem_ops_in_group[4];
6747
6748 /* Number of current processor cycle (from scheduler's point of view). */
6749 static int current_cycle;
6750
6751 static rtx ia64_single_set (rtx);
6752 static void ia64_emit_insn_before (rtx, rtx);
6753
6754 /* Map a bundle number to its pseudo-op. */
6755
6756 const char *
6757 get_bundle_name (int b)
6758 {
6759 return bundle_name[b];
6760 }
6761
6762
6763 /* Return the maximum number of instructions a cpu can issue. */
6764
6765 static int
6766 ia64_issue_rate (void)
6767 {
6768 return 6;
6769 }
6770
6771 /* Helper function - like single_set, but look inside COND_EXEC. */
6772
6773 static rtx
6774 ia64_single_set (rtx insn)
6775 {
6776 rtx x = PATTERN (insn), ret;
6777 if (GET_CODE (x) == COND_EXEC)
6778 x = COND_EXEC_CODE (x);
6779 if (GET_CODE (x) == SET)
6780 return x;
6781
6782 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6783 Although they are not classical single set, the second set is there just
6784 to protect it from moving past FP-relative stack accesses. */
6785 switch (recog_memoized (insn))
6786 {
6787 case CODE_FOR_prologue_allocate_stack:
6788 case CODE_FOR_epilogue_deallocate_stack:
6789 ret = XVECEXP (x, 0, 0);
6790 break;
6791
6792 default:
6793 ret = single_set_2 (insn, x);
6794 break;
6795 }
6796
6797 return ret;
6798 }
6799
6800 /* Adjust the cost of a scheduling dependency.
6801 Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN.
6802 COST is the current cost, DW is dependency weakness. */
6803 static int
6804 ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw)
6805 {
6806 enum reg_note dep_type = (enum reg_note) dep_type1;
6807 enum attr_itanium_class dep_class;
6808 enum attr_itanium_class insn_class;
6809
6810 insn_class = ia64_safe_itanium_class (insn);
6811 dep_class = ia64_safe_itanium_class (dep_insn);
6812
6813 /* Treat true memory dependencies separately. Ignore apparent true
6814 dependence between store and call (call has a MEM inside a SYMBOL_REF). */
6815 if (dep_type == REG_DEP_TRUE
6816 && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF)
6817 && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL))
6818 return 0;
6819
6820 if (dw == MIN_DEP_WEAK)
6821 /* Store and load are likely to alias, use higher cost to avoid stall. */
6822 return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST);
6823 else if (dw > MIN_DEP_WEAK)
6824 {
6825 /* Store and load are less likely to alias. */
6826 if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF)
6827 /* Assume there will be no cache conflict for floating-point data.
6828 For integer data, L1 conflict penalty is huge (17 cycles), so we
6829 never assume it will not cause a conflict. */
6830 return 0;
6831 else
6832 return cost;
6833 }
6834
6835 if (dep_type != REG_DEP_OUTPUT)
6836 return cost;
6837
6838 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6839 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6840 return 0;
6841
6842 return cost;
6843 }
6844
6845 /* Like emit_insn_before, but skip cycle_display notes.
6846 ??? When cycle display notes are implemented, update this. */
6847
6848 static void
6849 ia64_emit_insn_before (rtx insn, rtx before)
6850 {
6851 emit_insn_before (insn, before);
6852 }
6853
6854 /* The following function marks insns who produce addresses for load
6855 and store insns. Such insns will be placed into M slots because it
6856 decrease latency time for Itanium1 (see function
6857 `ia64_produce_address_p' and the DFA descriptions). */
6858
6859 static void
6860 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6861 {
6862 rtx insn, next, next_tail;
6863
6864 /* Before reload, which_alternative is not set, which means that
6865 ia64_safe_itanium_class will produce wrong results for (at least)
6866 move instructions. */
6867 if (!reload_completed)
6868 return;
6869
6870 next_tail = NEXT_INSN (tail);
6871 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6872 if (INSN_P (insn))
6873 insn->call = 0;
6874 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6875 if (INSN_P (insn)
6876 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6877 {
6878 sd_iterator_def sd_it;
6879 dep_t dep;
6880 bool has_mem_op_consumer_p = false;
6881
6882 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
6883 {
6884 enum attr_itanium_class c;
6885
6886 if (DEP_TYPE (dep) != REG_DEP_TRUE)
6887 continue;
6888
6889 next = DEP_CON (dep);
6890 c = ia64_safe_itanium_class (next);
6891 if ((c == ITANIUM_CLASS_ST
6892 || c == ITANIUM_CLASS_STF)
6893 && ia64_st_address_bypass_p (insn, next))
6894 {
6895 has_mem_op_consumer_p = true;
6896 break;
6897 }
6898 else if ((c == ITANIUM_CLASS_LD
6899 || c == ITANIUM_CLASS_FLD
6900 || c == ITANIUM_CLASS_FLDP)
6901 && ia64_ld_address_bypass_p (insn, next))
6902 {
6903 has_mem_op_consumer_p = true;
6904 break;
6905 }
6906 }
6907
6908 insn->call = has_mem_op_consumer_p;
6909 }
6910 }
6911
6912 /* We're beginning a new block. Initialize data structures as necessary. */
6913
6914 static void
6915 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6916 int sched_verbose ATTRIBUTE_UNUSED,
6917 int max_ready ATTRIBUTE_UNUSED)
6918 {
6919 #ifdef ENABLE_CHECKING
6920 rtx insn;
6921
6922 if (!sel_sched_p () && reload_completed)
6923 for (insn = NEXT_INSN (current_sched_info->prev_head);
6924 insn != current_sched_info->next_tail;
6925 insn = NEXT_INSN (insn))
6926 gcc_assert (!SCHED_GROUP_P (insn));
6927 #endif
6928 last_scheduled_insn = NULL_RTX;
6929 init_insn_group_barriers ();
6930
6931 current_cycle = 0;
6932 memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group));
6933 }
6934
6935 /* We're beginning a scheduling pass. Check assertion. */
6936
6937 static void
6938 ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED,
6939 int sched_verbose ATTRIBUTE_UNUSED,
6940 int max_ready ATTRIBUTE_UNUSED)
6941 {
6942 gcc_assert (pending_data_specs == 0);
6943 }
6944
6945 /* Scheduling pass is now finished. Free/reset static variable. */
6946 static void
6947 ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6948 int sched_verbose ATTRIBUTE_UNUSED)
6949 {
6950 gcc_assert (pending_data_specs == 0);
6951 }
6952
6953 /* Return TRUE if INSN is a load (either normal or speculative, but not a
6954 speculation check), FALSE otherwise. */
6955 static bool
6956 is_load_p (rtx insn)
6957 {
6958 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
6959
6960 return
6961 ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD)
6962 && get_attr_check_load (insn) == CHECK_LOAD_NO);
6963 }
6964
6965 /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array
6966 (taking account for 3-cycle cache reference postponing for stores: Intel
6967 Itanium 2 Reference Manual for Software Development and Optimization,
6968 6.7.3.1). */
6969 static void
6970 record_memory_reference (rtx insn)
6971 {
6972 enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn);
6973
6974 switch (insn_class) {
6975 case ITANIUM_CLASS_FLD:
6976 case ITANIUM_CLASS_LD:
6977 mem_ops_in_group[current_cycle % 4]++;
6978 break;
6979 case ITANIUM_CLASS_STF:
6980 case ITANIUM_CLASS_ST:
6981 mem_ops_in_group[(current_cycle + 3) % 4]++;
6982 break;
6983 default:;
6984 }
6985 }
6986
6987 /* We are about to being issuing insns for this clock cycle.
6988 Override the default sort algorithm to better slot instructions. */
6989
6990 static int
6991 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6992 int *pn_ready, int clock_var,
6993 int reorder_type)
6994 {
6995 int n_asms;
6996 int n_ready = *pn_ready;
6997 rtx *e_ready = ready + n_ready;
6998 rtx *insnp;
6999
7000 if (sched_verbose)
7001 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
7002
7003 if (reorder_type == 0)
7004 {
7005 /* First, move all USEs, CLOBBERs and other crud out of the way. */
7006 n_asms = 0;
7007 for (insnp = ready; insnp < e_ready; insnp++)
7008 if (insnp < e_ready)
7009 {
7010 rtx insn = *insnp;
7011 enum attr_type t = ia64_safe_type (insn);
7012 if (t == TYPE_UNKNOWN)
7013 {
7014 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
7015 || asm_noperands (PATTERN (insn)) >= 0)
7016 {
7017 rtx lowest = ready[n_asms];
7018 ready[n_asms] = insn;
7019 *insnp = lowest;
7020 n_asms++;
7021 }
7022 else
7023 {
7024 rtx highest = ready[n_ready - 1];
7025 ready[n_ready - 1] = insn;
7026 *insnp = highest;
7027 return 1;
7028 }
7029 }
7030 }
7031
7032 if (n_asms < n_ready)
7033 {
7034 /* Some normal insns to process. Skip the asms. */
7035 ready += n_asms;
7036 n_ready -= n_asms;
7037 }
7038 else if (n_ready > 0)
7039 return 1;
7040 }
7041
7042 if (ia64_final_schedule)
7043 {
7044 int deleted = 0;
7045 int nr_need_stop = 0;
7046
7047 for (insnp = ready; insnp < e_ready; insnp++)
7048 if (safe_group_barrier_needed (*insnp))
7049 nr_need_stop++;
7050
7051 if (reorder_type == 1 && n_ready == nr_need_stop)
7052 return 0;
7053 if (reorder_type == 0)
7054 return 1;
7055 insnp = e_ready;
7056 /* Move down everything that needs a stop bit, preserving
7057 relative order. */
7058 while (insnp-- > ready + deleted)
7059 while (insnp >= ready + deleted)
7060 {
7061 rtx insn = *insnp;
7062 if (! safe_group_barrier_needed (insn))
7063 break;
7064 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7065 *ready = insn;
7066 deleted++;
7067 }
7068 n_ready -= deleted;
7069 ready += deleted;
7070 }
7071
7072 current_cycle = clock_var;
7073 if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns)
7074 {
7075 int moved = 0;
7076
7077 insnp = e_ready;
7078 /* Move down loads/stores, preserving relative order. */
7079 while (insnp-- > ready + moved)
7080 while (insnp >= ready + moved)
7081 {
7082 rtx insn = *insnp;
7083 if (! is_load_p (insn))
7084 break;
7085 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
7086 *ready = insn;
7087 moved++;
7088 }
7089 n_ready -= moved;
7090 ready += moved;
7091 }
7092
7093 return 1;
7094 }
7095
7096 /* We are about to being issuing insns for this clock cycle. Override
7097 the default sort algorithm to better slot instructions. */
7098
7099 static int
7100 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
7101 int clock_var)
7102 {
7103 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
7104 pn_ready, clock_var, 0);
7105 }
7106
7107 /* Like ia64_sched_reorder, but called after issuing each insn.
7108 Override the default sort algorithm to better slot instructions. */
7109
7110 static int
7111 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
7112 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
7113 int *pn_ready, int clock_var)
7114 {
7115 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
7116 clock_var, 1);
7117 }
7118
7119 /* We are about to issue INSN. Return the number of insns left on the
7120 ready queue that can be issued this cycle. */
7121
7122 static int
7123 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
7124 int sched_verbose ATTRIBUTE_UNUSED,
7125 rtx insn ATTRIBUTE_UNUSED,
7126 int can_issue_more ATTRIBUTE_UNUSED)
7127 {
7128 if (sched_deps_info->generate_spec_deps && !sel_sched_p ())
7129 /* Modulo scheduling does not extend h_i_d when emitting
7130 new instructions. Don't use h_i_d, if we don't have to. */
7131 {
7132 if (DONE_SPEC (insn) & BEGIN_DATA)
7133 pending_data_specs++;
7134 if (CHECK_SPEC (insn) & BEGIN_DATA)
7135 pending_data_specs--;
7136 }
7137
7138 if (DEBUG_INSN_P (insn))
7139 return 1;
7140
7141 last_scheduled_insn = insn;
7142 memcpy (prev_cycle_state, curr_state, dfa_state_size);
7143 if (reload_completed)
7144 {
7145 int needed = group_barrier_needed (insn);
7146
7147 gcc_assert (!needed);
7148 if (GET_CODE (insn) == CALL_INSN)
7149 init_insn_group_barriers ();
7150 stops_p [INSN_UID (insn)] = stop_before_p;
7151 stop_before_p = 0;
7152
7153 record_memory_reference (insn);
7154 }
7155 return 1;
7156 }
7157
7158 /* We are choosing insn from the ready queue. Return nonzero if INSN
7159 can be chosen. */
7160
7161 static int
7162 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
7163 {
7164 gcc_assert (insn && INSN_P (insn));
7165 return ((!reload_completed
7166 || !safe_group_barrier_needed (insn))
7167 && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn)
7168 && (!mflag_sched_mem_insns_hard_limit
7169 || !is_load_p (insn)
7170 || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns));
7171 }
7172
7173 /* We are choosing insn from the ready queue. Return nonzero if INSN
7174 can be chosen. */
7175
7176 static bool
7177 ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn)
7178 {
7179 gcc_assert (insn && INSN_P (insn));
7180 /* Size of ALAT is 32. As far as we perform conservative data speculation,
7181 we keep ALAT half-empty. */
7182 return (pending_data_specs < 16
7183 || !(TODO_SPEC (insn) & BEGIN_DATA));
7184 }
7185
7186 /* The following variable value is pseudo-insn used by the DFA insn
7187 scheduler to change the DFA state when the simulated clock is
7188 increased. */
7189
7190 static rtx dfa_pre_cycle_insn;
7191
7192 /* Returns 1 when a meaningful insn was scheduled between the last group
7193 barrier and LAST. */
7194 static int
7195 scheduled_good_insn (rtx last)
7196 {
7197 if (last && recog_memoized (last) >= 0)
7198 return 1;
7199
7200 for ( ;
7201 last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last)
7202 && !stops_p[INSN_UID (last)];
7203 last = PREV_INSN (last))
7204 /* We could hit a NOTE_INSN_DELETED here which is actually outside
7205 the ebb we're scheduling. */
7206 if (INSN_P (last) && recog_memoized (last) >= 0)
7207 return 1;
7208
7209 return 0;
7210 }
7211
7212 /* We are about to being issuing INSN. Return nonzero if we cannot
7213 issue it on given cycle CLOCK and return zero if we should not sort
7214 the ready queue on the next clock start. */
7215
7216 static int
7217 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
7218 int clock, int *sort_p)
7219 {
7220 gcc_assert (insn && INSN_P (insn));
7221
7222 if (DEBUG_INSN_P (insn))
7223 return 0;
7224
7225 /* When a group barrier is needed for insn, last_scheduled_insn
7226 should be set. */
7227 gcc_assert (!(reload_completed && safe_group_barrier_needed (insn))
7228 || last_scheduled_insn);
7229
7230 if ((reload_completed
7231 && (safe_group_barrier_needed (insn)
7232 || (mflag_sched_stop_bits_after_every_cycle
7233 && last_clock != clock
7234 && last_scheduled_insn
7235 && scheduled_good_insn (last_scheduled_insn))))
7236 || (last_scheduled_insn
7237 && (GET_CODE (last_scheduled_insn) == CALL_INSN
7238 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
7239 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
7240 {
7241 init_insn_group_barriers ();
7242
7243 if (verbose && dump)
7244 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
7245 last_clock == clock ? " + cycle advance" : "");
7246
7247 stop_before_p = 1;
7248 current_cycle = clock;
7249 mem_ops_in_group[current_cycle % 4] = 0;
7250
7251 if (last_clock == clock)
7252 {
7253 state_transition (curr_state, dfa_stop_insn);
7254 if (TARGET_EARLY_STOP_BITS)
7255 *sort_p = (last_scheduled_insn == NULL_RTX
7256 || GET_CODE (last_scheduled_insn) != CALL_INSN);
7257 else
7258 *sort_p = 0;
7259 return 1;
7260 }
7261
7262 if (last_scheduled_insn)
7263 {
7264 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
7265 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
7266 state_reset (curr_state);
7267 else
7268 {
7269 memcpy (curr_state, prev_cycle_state, dfa_state_size);
7270 state_transition (curr_state, dfa_stop_insn);
7271 state_transition (curr_state, dfa_pre_cycle_insn);
7272 state_transition (curr_state, NULL);
7273 }
7274 }
7275 }
7276 return 0;
7277 }
7278
7279 /* Implement targetm.sched.h_i_d_extended hook.
7280 Extend internal data structures. */
7281 static void
7282 ia64_h_i_d_extended (void)
7283 {
7284 if (stops_p != NULL)
7285 {
7286 int new_clocks_length = get_max_uid () * 3 / 2;
7287 stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1);
7288 clocks_length = new_clocks_length;
7289 }
7290 }
7291 \f
7292
7293 /* This structure describes the data used by the backend to guide scheduling.
7294 When the current scheduling point is switched, this data should be saved
7295 and restored later, if the scheduler returns to this point. */
7296 struct _ia64_sched_context
7297 {
7298 state_t prev_cycle_state;
7299 rtx last_scheduled_insn;
7300 struct reg_write_state rws_sum[NUM_REGS];
7301 struct reg_write_state rws_insn[NUM_REGS];
7302 int first_instruction;
7303 int pending_data_specs;
7304 int current_cycle;
7305 char mem_ops_in_group[4];
7306 };
7307 typedef struct _ia64_sched_context *ia64_sched_context_t;
7308
7309 /* Allocates a scheduling context. */
7310 static void *
7311 ia64_alloc_sched_context (void)
7312 {
7313 return xmalloc (sizeof (struct _ia64_sched_context));
7314 }
7315
7316 /* Initializes the _SC context with clean data, if CLEAN_P, and from
7317 the global context otherwise. */
7318 static void
7319 ia64_init_sched_context (void *_sc, bool clean_p)
7320 {
7321 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7322
7323 sc->prev_cycle_state = xmalloc (dfa_state_size);
7324 if (clean_p)
7325 {
7326 state_reset (sc->prev_cycle_state);
7327 sc->last_scheduled_insn = NULL_RTX;
7328 memset (sc->rws_sum, 0, sizeof (rws_sum));
7329 memset (sc->rws_insn, 0, sizeof (rws_insn));
7330 sc->first_instruction = 1;
7331 sc->pending_data_specs = 0;
7332 sc->current_cycle = 0;
7333 memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group));
7334 }
7335 else
7336 {
7337 memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size);
7338 sc->last_scheduled_insn = last_scheduled_insn;
7339 memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum));
7340 memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn));
7341 sc->first_instruction = first_instruction;
7342 sc->pending_data_specs = pending_data_specs;
7343 sc->current_cycle = current_cycle;
7344 memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group));
7345 }
7346 }
7347
7348 /* Sets the global scheduling context to the one pointed to by _SC. */
7349 static void
7350 ia64_set_sched_context (void *_sc)
7351 {
7352 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7353
7354 gcc_assert (sc != NULL);
7355
7356 memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size);
7357 last_scheduled_insn = sc->last_scheduled_insn;
7358 memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum));
7359 memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn));
7360 first_instruction = sc->first_instruction;
7361 pending_data_specs = sc->pending_data_specs;
7362 current_cycle = sc->current_cycle;
7363 memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group));
7364 }
7365
7366 /* Clears the data in the _SC scheduling context. */
7367 static void
7368 ia64_clear_sched_context (void *_sc)
7369 {
7370 ia64_sched_context_t sc = (ia64_sched_context_t) _sc;
7371
7372 free (sc->prev_cycle_state);
7373 sc->prev_cycle_state = NULL;
7374 }
7375
7376 /* Frees the _SC scheduling context. */
7377 static void
7378 ia64_free_sched_context (void *_sc)
7379 {
7380 gcc_assert (_sc != NULL);
7381
7382 free (_sc);
7383 }
7384
7385 typedef rtx (* gen_func_t) (rtx, rtx);
7386
7387 /* Return a function that will generate a load of mode MODE_NO
7388 with speculation types TS. */
7389 static gen_func_t
7390 get_spec_load_gen_function (ds_t ts, int mode_no)
7391 {
7392 static gen_func_t gen_ld_[] = {
7393 gen_movbi,
7394 gen_movqi_internal,
7395 gen_movhi_internal,
7396 gen_movsi_internal,
7397 gen_movdi_internal,
7398 gen_movsf_internal,
7399 gen_movdf_internal,
7400 gen_movxf_internal,
7401 gen_movti_internal,
7402 gen_zero_extendqidi2,
7403 gen_zero_extendhidi2,
7404 gen_zero_extendsidi2,
7405 };
7406
7407 static gen_func_t gen_ld_a[] = {
7408 gen_movbi_advanced,
7409 gen_movqi_advanced,
7410 gen_movhi_advanced,
7411 gen_movsi_advanced,
7412 gen_movdi_advanced,
7413 gen_movsf_advanced,
7414 gen_movdf_advanced,
7415 gen_movxf_advanced,
7416 gen_movti_advanced,
7417 gen_zero_extendqidi2_advanced,
7418 gen_zero_extendhidi2_advanced,
7419 gen_zero_extendsidi2_advanced,
7420 };
7421 static gen_func_t gen_ld_s[] = {
7422 gen_movbi_speculative,
7423 gen_movqi_speculative,
7424 gen_movhi_speculative,
7425 gen_movsi_speculative,
7426 gen_movdi_speculative,
7427 gen_movsf_speculative,
7428 gen_movdf_speculative,
7429 gen_movxf_speculative,
7430 gen_movti_speculative,
7431 gen_zero_extendqidi2_speculative,
7432 gen_zero_extendhidi2_speculative,
7433 gen_zero_extendsidi2_speculative,
7434 };
7435 static gen_func_t gen_ld_sa[] = {
7436 gen_movbi_speculative_advanced,
7437 gen_movqi_speculative_advanced,
7438 gen_movhi_speculative_advanced,
7439 gen_movsi_speculative_advanced,
7440 gen_movdi_speculative_advanced,
7441 gen_movsf_speculative_advanced,
7442 gen_movdf_speculative_advanced,
7443 gen_movxf_speculative_advanced,
7444 gen_movti_speculative_advanced,
7445 gen_zero_extendqidi2_speculative_advanced,
7446 gen_zero_extendhidi2_speculative_advanced,
7447 gen_zero_extendsidi2_speculative_advanced,
7448 };
7449 static gen_func_t gen_ld_s_a[] = {
7450 gen_movbi_speculative_a,
7451 gen_movqi_speculative_a,
7452 gen_movhi_speculative_a,
7453 gen_movsi_speculative_a,
7454 gen_movdi_speculative_a,
7455 gen_movsf_speculative_a,
7456 gen_movdf_speculative_a,
7457 gen_movxf_speculative_a,
7458 gen_movti_speculative_a,
7459 gen_zero_extendqidi2_speculative_a,
7460 gen_zero_extendhidi2_speculative_a,
7461 gen_zero_extendsidi2_speculative_a,
7462 };
7463
7464 gen_func_t *gen_ld;
7465
7466 if (ts & BEGIN_DATA)
7467 {
7468 if (ts & BEGIN_CONTROL)
7469 gen_ld = gen_ld_sa;
7470 else
7471 gen_ld = gen_ld_a;
7472 }
7473 else if (ts & BEGIN_CONTROL)
7474 {
7475 if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL)
7476 || ia64_needs_block_p (ts))
7477 gen_ld = gen_ld_s;
7478 else
7479 gen_ld = gen_ld_s_a;
7480 }
7481 else if (ts == 0)
7482 gen_ld = gen_ld_;
7483 else
7484 gcc_unreachable ();
7485
7486 return gen_ld[mode_no];
7487 }
7488
7489 /* Constants that help mapping 'enum machine_mode' to int. */
7490 enum SPEC_MODES
7491 {
7492 SPEC_MODE_INVALID = -1,
7493 SPEC_MODE_FIRST = 0,
7494 SPEC_MODE_FOR_EXTEND_FIRST = 1,
7495 SPEC_MODE_FOR_EXTEND_LAST = 3,
7496 SPEC_MODE_LAST = 8
7497 };
7498
7499 enum
7500 {
7501 /* Offset to reach ZERO_EXTEND patterns. */
7502 SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1
7503 };
7504
7505 /* Return index of the MODE. */
7506 static int
7507 ia64_mode_to_int (enum machine_mode mode)
7508 {
7509 switch (mode)
7510 {
7511 case BImode: return 0; /* SPEC_MODE_FIRST */
7512 case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */
7513 case HImode: return 2;
7514 case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */
7515 case DImode: return 4;
7516 case SFmode: return 5;
7517 case DFmode: return 6;
7518 case XFmode: return 7;
7519 case TImode:
7520 /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not
7521 mentioned in itanium[12].md. Predicate fp_register_operand also
7522 needs to be defined. Bottom line: better disable for now. */
7523 return SPEC_MODE_INVALID;
7524 default: return SPEC_MODE_INVALID;
7525 }
7526 }
7527
7528 /* Provide information about speculation capabilities. */
7529 static void
7530 ia64_set_sched_flags (spec_info_t spec_info)
7531 {
7532 unsigned int *flags = &(current_sched_info->flags);
7533
7534 if (*flags & SCHED_RGN
7535 || *flags & SCHED_EBB
7536 || *flags & SEL_SCHED)
7537 {
7538 int mask = 0;
7539
7540 if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0)
7541 || (mflag_sched_ar_data_spec && reload_completed))
7542 {
7543 mask |= BEGIN_DATA;
7544
7545 if (!sel_sched_p ()
7546 && ((mflag_sched_br_in_data_spec && !reload_completed)
7547 || (mflag_sched_ar_in_data_spec && reload_completed)))
7548 mask |= BE_IN_DATA;
7549 }
7550
7551 if (mflag_sched_control_spec
7552 && (!sel_sched_p ()
7553 || reload_completed))
7554 {
7555 mask |= BEGIN_CONTROL;
7556
7557 if (!sel_sched_p () && mflag_sched_in_control_spec)
7558 mask |= BE_IN_CONTROL;
7559 }
7560
7561 spec_info->mask = mask;
7562
7563 if (mask)
7564 {
7565 *flags |= USE_DEPS_LIST | DO_SPECULATION;
7566
7567 if (mask & BE_IN_SPEC)
7568 *flags |= NEW_BBS;
7569
7570 spec_info->flags = 0;
7571
7572 if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns)
7573 spec_info->flags |= PREFER_NON_DATA_SPEC;
7574
7575 if (mask & CONTROL_SPEC)
7576 {
7577 if (mflag_sched_prefer_non_control_spec_insns)
7578 spec_info->flags |= PREFER_NON_CONTROL_SPEC;
7579
7580 if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec)
7581 spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL;
7582 }
7583
7584 if (sched_verbose >= 1)
7585 spec_info->dump = sched_dump;
7586 else
7587 spec_info->dump = 0;
7588
7589 if (mflag_sched_count_spec_in_critical_path)
7590 spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH;
7591 }
7592 }
7593 else
7594 spec_info->mask = 0;
7595 }
7596
7597 /* If INSN is an appropriate load return its mode.
7598 Return -1 otherwise. */
7599 static int
7600 get_mode_no_for_insn (rtx insn)
7601 {
7602 rtx reg, mem, mode_rtx;
7603 int mode_no;
7604 bool extend_p;
7605
7606 extract_insn_cached (insn);
7607
7608 /* We use WHICH_ALTERNATIVE only after reload. This will
7609 guarantee that reload won't touch a speculative insn. */
7610
7611 if (recog_data.n_operands != 2)
7612 return -1;
7613
7614 reg = recog_data.operand[0];
7615 mem = recog_data.operand[1];
7616
7617 /* We should use MEM's mode since REG's mode in presence of
7618 ZERO_EXTEND will always be DImode. */
7619 if (get_attr_speculable1 (insn) == SPECULABLE1_YES)
7620 /* Process non-speculative ld. */
7621 {
7622 if (!reload_completed)
7623 {
7624 /* Do not speculate into regs like ar.lc. */
7625 if (!REG_P (reg) || AR_REGNO_P (REGNO (reg)))
7626 return -1;
7627
7628 if (!MEM_P (mem))
7629 return -1;
7630
7631 {
7632 rtx mem_reg = XEXP (mem, 0);
7633
7634 if (!REG_P (mem_reg))
7635 return -1;
7636 }
7637
7638 mode_rtx = mem;
7639 }
7640 else if (get_attr_speculable2 (insn) == SPECULABLE2_YES)
7641 {
7642 gcc_assert (REG_P (reg) && MEM_P (mem));
7643 mode_rtx = mem;
7644 }
7645 else
7646 return -1;
7647 }
7648 else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES
7649 || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES
7650 || get_attr_check_load (insn) == CHECK_LOAD_YES)
7651 /* Process speculative ld or ld.c. */
7652 {
7653 gcc_assert (REG_P (reg) && MEM_P (mem));
7654 mode_rtx = mem;
7655 }
7656 else
7657 {
7658 enum attr_itanium_class attr_class = get_attr_itanium_class (insn);
7659
7660 if (attr_class == ITANIUM_CLASS_CHK_A
7661 || attr_class == ITANIUM_CLASS_CHK_S_I
7662 || attr_class == ITANIUM_CLASS_CHK_S_F)
7663 /* Process chk. */
7664 mode_rtx = reg;
7665 else
7666 return -1;
7667 }
7668
7669 mode_no = ia64_mode_to_int (GET_MODE (mode_rtx));
7670
7671 if (mode_no == SPEC_MODE_INVALID)
7672 return -1;
7673
7674 extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx));
7675
7676 if (extend_p)
7677 {
7678 if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no
7679 && mode_no <= SPEC_MODE_FOR_EXTEND_LAST))
7680 return -1;
7681
7682 mode_no += SPEC_GEN_EXTEND_OFFSET;
7683 }
7684
7685 return mode_no;
7686 }
7687
7688 /* If X is an unspec part of a speculative load, return its code.
7689 Return -1 otherwise. */
7690 static int
7691 get_spec_unspec_code (const_rtx x)
7692 {
7693 if (GET_CODE (x) != UNSPEC)
7694 return -1;
7695
7696 {
7697 int code;
7698
7699 code = XINT (x, 1);
7700
7701 switch (code)
7702 {
7703 case UNSPEC_LDA:
7704 case UNSPEC_LDS:
7705 case UNSPEC_LDS_A:
7706 case UNSPEC_LDSA:
7707 return code;
7708
7709 default:
7710 return -1;
7711 }
7712 }
7713 }
7714
7715 /* Implement skip_rtx_p hook. */
7716 static bool
7717 ia64_skip_rtx_p (const_rtx x)
7718 {
7719 return get_spec_unspec_code (x) != -1;
7720 }
7721
7722 /* If INSN is a speculative load, return its UNSPEC code.
7723 Return -1 otherwise. */
7724 static int
7725 get_insn_spec_code (const_rtx insn)
7726 {
7727 rtx pat, reg, mem;
7728
7729 pat = PATTERN (insn);
7730
7731 if (GET_CODE (pat) == COND_EXEC)
7732 pat = COND_EXEC_CODE (pat);
7733
7734 if (GET_CODE (pat) != SET)
7735 return -1;
7736
7737 reg = SET_DEST (pat);
7738 if (!REG_P (reg))
7739 return -1;
7740
7741 mem = SET_SRC (pat);
7742 if (GET_CODE (mem) == ZERO_EXTEND)
7743 mem = XEXP (mem, 0);
7744
7745 return get_spec_unspec_code (mem);
7746 }
7747
7748 /* If INSN is a speculative load, return a ds with the speculation types.
7749 Otherwise [if INSN is a normal instruction] return 0. */
7750 static ds_t
7751 ia64_get_insn_spec_ds (rtx insn)
7752 {
7753 int code = get_insn_spec_code (insn);
7754
7755 switch (code)
7756 {
7757 case UNSPEC_LDA:
7758 return BEGIN_DATA;
7759
7760 case UNSPEC_LDS:
7761 case UNSPEC_LDS_A:
7762 return BEGIN_CONTROL;
7763
7764 case UNSPEC_LDSA:
7765 return BEGIN_DATA | BEGIN_CONTROL;
7766
7767 default:
7768 return 0;
7769 }
7770 }
7771
7772 /* If INSN is a speculative load return a ds with the speculation types that
7773 will be checked.
7774 Otherwise [if INSN is a normal instruction] return 0. */
7775 static ds_t
7776 ia64_get_insn_checked_ds (rtx insn)
7777 {
7778 int code = get_insn_spec_code (insn);
7779
7780 switch (code)
7781 {
7782 case UNSPEC_LDA:
7783 return BEGIN_DATA | BEGIN_CONTROL;
7784
7785 case UNSPEC_LDS:
7786 return BEGIN_CONTROL;
7787
7788 case UNSPEC_LDS_A:
7789 case UNSPEC_LDSA:
7790 return BEGIN_DATA | BEGIN_CONTROL;
7791
7792 default:
7793 return 0;
7794 }
7795 }
7796
7797 /* If GEN_P is true, calculate the index of needed speculation check and return
7798 speculative pattern for INSN with speculative mode TS, machine mode
7799 MODE_NO and with ZERO_EXTEND (if EXTEND_P is true).
7800 If GEN_P is false, just calculate the index of needed speculation check. */
7801 static rtx
7802 ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no)
7803 {
7804 rtx pat, new_pat;
7805 gen_func_t gen_load;
7806
7807 gen_load = get_spec_load_gen_function (ts, mode_no);
7808
7809 new_pat = gen_load (copy_rtx (recog_data.operand[0]),
7810 copy_rtx (recog_data.operand[1]));
7811
7812 pat = PATTERN (insn);
7813 if (GET_CODE (pat) == COND_EXEC)
7814 new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
7815 new_pat);
7816
7817 return new_pat;
7818 }
7819
7820 static bool
7821 insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED,
7822 ds_t ds ATTRIBUTE_UNUSED)
7823 {
7824 return false;
7825 }
7826
7827 /* Implement targetm.sched.speculate_insn hook.
7828 Check if the INSN can be TS speculative.
7829 If 'no' - return -1.
7830 If 'yes' - generate speculative pattern in the NEW_PAT and return 1.
7831 If current pattern of the INSN already provides TS speculation,
7832 return 0. */
7833 static int
7834 ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat)
7835 {
7836 int mode_no;
7837 int res;
7838
7839 gcc_assert (!(ts & ~SPECULATIVE));
7840
7841 if (ia64_spec_check_p (insn))
7842 return -1;
7843
7844 if ((ts & BE_IN_SPEC)
7845 && !insn_can_be_in_speculative_p (insn, ts))
7846 return -1;
7847
7848 mode_no = get_mode_no_for_insn (insn);
7849
7850 if (mode_no != SPEC_MODE_INVALID)
7851 {
7852 if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts))
7853 res = 0;
7854 else
7855 {
7856 res = 1;
7857 *new_pat = ia64_gen_spec_load (insn, ts, mode_no);
7858 }
7859 }
7860 else
7861 res = -1;
7862
7863 return res;
7864 }
7865
7866 /* Return a function that will generate a check for speculation TS with mode
7867 MODE_NO.
7868 If simple check is needed, pass true for SIMPLE_CHECK_P.
7869 If clearing check is needed, pass true for CLEARING_CHECK_P. */
7870 static gen_func_t
7871 get_spec_check_gen_function (ds_t ts, int mode_no,
7872 bool simple_check_p, bool clearing_check_p)
7873 {
7874 static gen_func_t gen_ld_c_clr[] = {
7875 gen_movbi_clr,
7876 gen_movqi_clr,
7877 gen_movhi_clr,
7878 gen_movsi_clr,
7879 gen_movdi_clr,
7880 gen_movsf_clr,
7881 gen_movdf_clr,
7882 gen_movxf_clr,
7883 gen_movti_clr,
7884 gen_zero_extendqidi2_clr,
7885 gen_zero_extendhidi2_clr,
7886 gen_zero_extendsidi2_clr,
7887 };
7888 static gen_func_t gen_ld_c_nc[] = {
7889 gen_movbi_nc,
7890 gen_movqi_nc,
7891 gen_movhi_nc,
7892 gen_movsi_nc,
7893 gen_movdi_nc,
7894 gen_movsf_nc,
7895 gen_movdf_nc,
7896 gen_movxf_nc,
7897 gen_movti_nc,
7898 gen_zero_extendqidi2_nc,
7899 gen_zero_extendhidi2_nc,
7900 gen_zero_extendsidi2_nc,
7901 };
7902 static gen_func_t gen_chk_a_clr[] = {
7903 gen_advanced_load_check_clr_bi,
7904 gen_advanced_load_check_clr_qi,
7905 gen_advanced_load_check_clr_hi,
7906 gen_advanced_load_check_clr_si,
7907 gen_advanced_load_check_clr_di,
7908 gen_advanced_load_check_clr_sf,
7909 gen_advanced_load_check_clr_df,
7910 gen_advanced_load_check_clr_xf,
7911 gen_advanced_load_check_clr_ti,
7912 gen_advanced_load_check_clr_di,
7913 gen_advanced_load_check_clr_di,
7914 gen_advanced_load_check_clr_di,
7915 };
7916 static gen_func_t gen_chk_a_nc[] = {
7917 gen_advanced_load_check_nc_bi,
7918 gen_advanced_load_check_nc_qi,
7919 gen_advanced_load_check_nc_hi,
7920 gen_advanced_load_check_nc_si,
7921 gen_advanced_load_check_nc_di,
7922 gen_advanced_load_check_nc_sf,
7923 gen_advanced_load_check_nc_df,
7924 gen_advanced_load_check_nc_xf,
7925 gen_advanced_load_check_nc_ti,
7926 gen_advanced_load_check_nc_di,
7927 gen_advanced_load_check_nc_di,
7928 gen_advanced_load_check_nc_di,
7929 };
7930 static gen_func_t gen_chk_s[] = {
7931 gen_speculation_check_bi,
7932 gen_speculation_check_qi,
7933 gen_speculation_check_hi,
7934 gen_speculation_check_si,
7935 gen_speculation_check_di,
7936 gen_speculation_check_sf,
7937 gen_speculation_check_df,
7938 gen_speculation_check_xf,
7939 gen_speculation_check_ti,
7940 gen_speculation_check_di,
7941 gen_speculation_check_di,
7942 gen_speculation_check_di,
7943 };
7944
7945 gen_func_t *gen_check;
7946
7947 if (ts & BEGIN_DATA)
7948 {
7949 /* We don't need recovery because even if this is ld.sa
7950 ALAT entry will be allocated only if NAT bit is set to zero.
7951 So it is enough to use ld.c here. */
7952
7953 if (simple_check_p)
7954 {
7955 gcc_assert (mflag_sched_spec_ldc);
7956
7957 if (clearing_check_p)
7958 gen_check = gen_ld_c_clr;
7959 else
7960 gen_check = gen_ld_c_nc;
7961 }
7962 else
7963 {
7964 if (clearing_check_p)
7965 gen_check = gen_chk_a_clr;
7966 else
7967 gen_check = gen_chk_a_nc;
7968 }
7969 }
7970 else if (ts & BEGIN_CONTROL)
7971 {
7972 if (simple_check_p)
7973 /* We might want to use ld.sa -> ld.c instead of
7974 ld.s -> chk.s. */
7975 {
7976 gcc_assert (!ia64_needs_block_p (ts));
7977
7978 if (clearing_check_p)
7979 gen_check = gen_ld_c_clr;
7980 else
7981 gen_check = gen_ld_c_nc;
7982 }
7983 else
7984 {
7985 gen_check = gen_chk_s;
7986 }
7987 }
7988 else
7989 gcc_unreachable ();
7990
7991 gcc_assert (mode_no >= 0);
7992 return gen_check[mode_no];
7993 }
7994
7995 /* Return nonzero, if INSN needs branchy recovery check. */
7996 static bool
7997 ia64_needs_block_p (ds_t ts)
7998 {
7999 if (ts & BEGIN_DATA)
8000 return !mflag_sched_spec_ldc;
8001
8002 gcc_assert ((ts & BEGIN_CONTROL) != 0);
8003
8004 return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc);
8005 }
8006
8007 /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN.
8008 If (LABEL != 0 || MUTATE_P), generate branchy recovery check.
8009 Otherwise, generate a simple check. */
8010 static rtx
8011 ia64_gen_spec_check (rtx insn, rtx label, ds_t ds)
8012 {
8013 rtx op1, pat, check_pat;
8014 gen_func_t gen_check;
8015 int mode_no;
8016
8017 mode_no = get_mode_no_for_insn (insn);
8018 gcc_assert (mode_no >= 0);
8019
8020 if (label)
8021 op1 = label;
8022 else
8023 {
8024 gcc_assert (!ia64_needs_block_p (ds));
8025 op1 = copy_rtx (recog_data.operand[1]);
8026 }
8027
8028 gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX,
8029 true);
8030
8031 check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1);
8032
8033 pat = PATTERN (insn);
8034 if (GET_CODE (pat) == COND_EXEC)
8035 check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)),
8036 check_pat);
8037
8038 return check_pat;
8039 }
8040
8041 /* Return nonzero, if X is branchy recovery check. */
8042 static int
8043 ia64_spec_check_p (rtx x)
8044 {
8045 x = PATTERN (x);
8046 if (GET_CODE (x) == COND_EXEC)
8047 x = COND_EXEC_CODE (x);
8048 if (GET_CODE (x) == SET)
8049 return ia64_spec_check_src_p (SET_SRC (x));
8050 return 0;
8051 }
8052
8053 /* Return nonzero, if SRC belongs to recovery check. */
8054 static int
8055 ia64_spec_check_src_p (rtx src)
8056 {
8057 if (GET_CODE (src) == IF_THEN_ELSE)
8058 {
8059 rtx t;
8060
8061 t = XEXP (src, 0);
8062 if (GET_CODE (t) == NE)
8063 {
8064 t = XEXP (t, 0);
8065
8066 if (GET_CODE (t) == UNSPEC)
8067 {
8068 int code;
8069
8070 code = XINT (t, 1);
8071
8072 if (code == UNSPEC_LDCCLR
8073 || code == UNSPEC_LDCNC
8074 || code == UNSPEC_CHKACLR
8075 || code == UNSPEC_CHKANC
8076 || code == UNSPEC_CHKS)
8077 {
8078 gcc_assert (code != 0);
8079 return code;
8080 }
8081 }
8082 }
8083 }
8084 return 0;
8085 }
8086 \f
8087
8088 /* The following page contains abstract data `bundle states' which are
8089 used for bundling insns (inserting nops and template generation). */
8090
8091 /* The following describes state of insn bundling. */
8092
8093 struct bundle_state
8094 {
8095 /* Unique bundle state number to identify them in the debugging
8096 output */
8097 int unique_num;
8098 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
8099 /* number nops before and after the insn */
8100 short before_nops_num, after_nops_num;
8101 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
8102 insn */
8103 int cost; /* cost of the state in cycles */
8104 int accumulated_insns_num; /* number of all previous insns including
8105 nops. L is considered as 2 insns */
8106 int branch_deviation; /* deviation of previous branches from 3rd slots */
8107 int middle_bundle_stops; /* number of stop bits in the middle of bundles */
8108 struct bundle_state *next; /* next state with the same insn_num */
8109 struct bundle_state *originator; /* originator (previous insn state) */
8110 /* All bundle states are in the following chain. */
8111 struct bundle_state *allocated_states_chain;
8112 /* The DFA State after issuing the insn and the nops. */
8113 state_t dfa_state;
8114 };
8115
8116 /* The following is map insn number to the corresponding bundle state. */
8117
8118 static struct bundle_state **index_to_bundle_states;
8119
8120 /* The unique number of next bundle state. */
8121
8122 static int bundle_states_num;
8123
8124 /* All allocated bundle states are in the following chain. */
8125
8126 static struct bundle_state *allocated_bundle_states_chain;
8127
8128 /* All allocated but not used bundle states are in the following
8129 chain. */
8130
8131 static struct bundle_state *free_bundle_state_chain;
8132
8133
8134 /* The following function returns a free bundle state. */
8135
8136 static struct bundle_state *
8137 get_free_bundle_state (void)
8138 {
8139 struct bundle_state *result;
8140
8141 if (free_bundle_state_chain != NULL)
8142 {
8143 result = free_bundle_state_chain;
8144 free_bundle_state_chain = result->next;
8145 }
8146 else
8147 {
8148 result = XNEW (struct bundle_state);
8149 result->dfa_state = xmalloc (dfa_state_size);
8150 result->allocated_states_chain = allocated_bundle_states_chain;
8151 allocated_bundle_states_chain = result;
8152 }
8153 result->unique_num = bundle_states_num++;
8154 return result;
8155
8156 }
8157
8158 /* The following function frees given bundle state. */
8159
8160 static void
8161 free_bundle_state (struct bundle_state *state)
8162 {
8163 state->next = free_bundle_state_chain;
8164 free_bundle_state_chain = state;
8165 }
8166
8167 /* Start work with abstract data `bundle states'. */
8168
8169 static void
8170 initiate_bundle_states (void)
8171 {
8172 bundle_states_num = 0;
8173 free_bundle_state_chain = NULL;
8174 allocated_bundle_states_chain = NULL;
8175 }
8176
8177 /* Finish work with abstract data `bundle states'. */
8178
8179 static void
8180 finish_bundle_states (void)
8181 {
8182 struct bundle_state *curr_state, *next_state;
8183
8184 for (curr_state = allocated_bundle_states_chain;
8185 curr_state != NULL;
8186 curr_state = next_state)
8187 {
8188 next_state = curr_state->allocated_states_chain;
8189 free (curr_state->dfa_state);
8190 free (curr_state);
8191 }
8192 }
8193
8194 /* Hash table of the bundle states. The key is dfa_state and insn_num
8195 of the bundle states. */
8196
8197 static htab_t bundle_state_table;
8198
8199 /* The function returns hash of BUNDLE_STATE. */
8200
8201 static unsigned
8202 bundle_state_hash (const void *bundle_state)
8203 {
8204 const struct bundle_state *const state
8205 = (const struct bundle_state *) bundle_state;
8206 unsigned result, i;
8207
8208 for (result = i = 0; i < dfa_state_size; i++)
8209 result += (((unsigned char *) state->dfa_state) [i]
8210 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
8211 return result + state->insn_num;
8212 }
8213
8214 /* The function returns nonzero if the bundle state keys are equal. */
8215
8216 static int
8217 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
8218 {
8219 const struct bundle_state *const state1
8220 = (const struct bundle_state *) bundle_state_1;
8221 const struct bundle_state *const state2
8222 = (const struct bundle_state *) bundle_state_2;
8223
8224 return (state1->insn_num == state2->insn_num
8225 && memcmp (state1->dfa_state, state2->dfa_state,
8226 dfa_state_size) == 0);
8227 }
8228
8229 /* The function inserts the BUNDLE_STATE into the hash table. The
8230 function returns nonzero if the bundle has been inserted into the
8231 table. The table contains the best bundle state with given key. */
8232
8233 static int
8234 insert_bundle_state (struct bundle_state *bundle_state)
8235 {
8236 void **entry_ptr;
8237
8238 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, INSERT);
8239 if (*entry_ptr == NULL)
8240 {
8241 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
8242 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
8243 *entry_ptr = (void *) bundle_state;
8244 return TRUE;
8245 }
8246 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
8247 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
8248 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
8249 > bundle_state->accumulated_insns_num
8250 || (((struct bundle_state *)
8251 *entry_ptr)->accumulated_insns_num
8252 == bundle_state->accumulated_insns_num
8253 && (((struct bundle_state *)
8254 *entry_ptr)->branch_deviation
8255 > bundle_state->branch_deviation
8256 || (((struct bundle_state *)
8257 *entry_ptr)->branch_deviation
8258 == bundle_state->branch_deviation
8259 && ((struct bundle_state *)
8260 *entry_ptr)->middle_bundle_stops
8261 > bundle_state->middle_bundle_stops))))))
8262
8263 {
8264 struct bundle_state temp;
8265
8266 temp = *(struct bundle_state *) *entry_ptr;
8267 *(struct bundle_state *) *entry_ptr = *bundle_state;
8268 ((struct bundle_state *) *entry_ptr)->next = temp.next;
8269 *bundle_state = temp;
8270 }
8271 return FALSE;
8272 }
8273
8274 /* Start work with the hash table. */
8275
8276 static void
8277 initiate_bundle_state_table (void)
8278 {
8279 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
8280 (htab_del) 0);
8281 }
8282
8283 /* Finish work with the hash table. */
8284
8285 static void
8286 finish_bundle_state_table (void)
8287 {
8288 htab_delete (bundle_state_table);
8289 }
8290
8291 \f
8292
8293 /* The following variable is a insn `nop' used to check bundle states
8294 with different number of inserted nops. */
8295
8296 static rtx ia64_nop;
8297
8298 /* The following function tries to issue NOPS_NUM nops for the current
8299 state without advancing processor cycle. If it failed, the
8300 function returns FALSE and frees the current state. */
8301
8302 static int
8303 try_issue_nops (struct bundle_state *curr_state, int nops_num)
8304 {
8305 int i;
8306
8307 for (i = 0; i < nops_num; i++)
8308 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
8309 {
8310 free_bundle_state (curr_state);
8311 return FALSE;
8312 }
8313 return TRUE;
8314 }
8315
8316 /* The following function tries to issue INSN for the current
8317 state without advancing processor cycle. If it failed, the
8318 function returns FALSE and frees the current state. */
8319
8320 static int
8321 try_issue_insn (struct bundle_state *curr_state, rtx insn)
8322 {
8323 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
8324 {
8325 free_bundle_state (curr_state);
8326 return FALSE;
8327 }
8328 return TRUE;
8329 }
8330
8331 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
8332 starting with ORIGINATOR without advancing processor cycle. If
8333 TRY_BUNDLE_END_P is TRUE, the function also/only (if
8334 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
8335 If it was successful, the function creates new bundle state and
8336 insert into the hash table and into `index_to_bundle_states'. */
8337
8338 static void
8339 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
8340 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
8341 {
8342 struct bundle_state *curr_state;
8343
8344 curr_state = get_free_bundle_state ();
8345 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
8346 curr_state->insn = insn;
8347 curr_state->insn_num = originator->insn_num + 1;
8348 curr_state->cost = originator->cost;
8349 curr_state->originator = originator;
8350 curr_state->before_nops_num = before_nops_num;
8351 curr_state->after_nops_num = 0;
8352 curr_state->accumulated_insns_num
8353 = originator->accumulated_insns_num + before_nops_num;
8354 curr_state->branch_deviation = originator->branch_deviation;
8355 curr_state->middle_bundle_stops = originator->middle_bundle_stops;
8356 gcc_assert (insn);
8357 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
8358 {
8359 gcc_assert (GET_MODE (insn) != TImode);
8360 if (!try_issue_nops (curr_state, before_nops_num))
8361 return;
8362 if (!try_issue_insn (curr_state, insn))
8363 return;
8364 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
8365 if (curr_state->accumulated_insns_num % 3 != 0)
8366 curr_state->middle_bundle_stops++;
8367 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
8368 && curr_state->accumulated_insns_num % 3 != 0)
8369 {
8370 free_bundle_state (curr_state);
8371 return;
8372 }
8373 }
8374 else if (GET_MODE (insn) != TImode)
8375 {
8376 if (!try_issue_nops (curr_state, before_nops_num))
8377 return;
8378 if (!try_issue_insn (curr_state, insn))
8379 return;
8380 curr_state->accumulated_insns_num++;
8381 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
8382 && asm_noperands (PATTERN (insn)) < 0);
8383
8384 if (ia64_safe_type (insn) == TYPE_L)
8385 curr_state->accumulated_insns_num++;
8386 }
8387 else
8388 {
8389 /* If this is an insn that must be first in a group, then don't allow
8390 nops to be emitted before it. Currently, alloc is the only such
8391 supported instruction. */
8392 /* ??? The bundling automatons should handle this for us, but they do
8393 not yet have support for the first_insn attribute. */
8394 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
8395 {
8396 free_bundle_state (curr_state);
8397 return;
8398 }
8399
8400 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
8401 state_transition (curr_state->dfa_state, NULL);
8402 curr_state->cost++;
8403 if (!try_issue_nops (curr_state, before_nops_num))
8404 return;
8405 if (!try_issue_insn (curr_state, insn))
8406 return;
8407 curr_state->accumulated_insns_num++;
8408 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
8409 || asm_noperands (PATTERN (insn)) >= 0)
8410 {
8411 /* Finish bundle containing asm insn. */
8412 curr_state->after_nops_num
8413 = 3 - curr_state->accumulated_insns_num % 3;
8414 curr_state->accumulated_insns_num
8415 += 3 - curr_state->accumulated_insns_num % 3;
8416 }
8417 else if (ia64_safe_type (insn) == TYPE_L)
8418 curr_state->accumulated_insns_num++;
8419 }
8420 if (ia64_safe_type (insn) == TYPE_B)
8421 curr_state->branch_deviation
8422 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
8423 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
8424 {
8425 if (!only_bundle_end_p && insert_bundle_state (curr_state))
8426 {
8427 state_t dfa_state;
8428 struct bundle_state *curr_state1;
8429 struct bundle_state *allocated_states_chain;
8430
8431 curr_state1 = get_free_bundle_state ();
8432 dfa_state = curr_state1->dfa_state;
8433 allocated_states_chain = curr_state1->allocated_states_chain;
8434 *curr_state1 = *curr_state;
8435 curr_state1->dfa_state = dfa_state;
8436 curr_state1->allocated_states_chain = allocated_states_chain;
8437 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
8438 dfa_state_size);
8439 curr_state = curr_state1;
8440 }
8441 if (!try_issue_nops (curr_state,
8442 3 - curr_state->accumulated_insns_num % 3))
8443 return;
8444 curr_state->after_nops_num
8445 = 3 - curr_state->accumulated_insns_num % 3;
8446 curr_state->accumulated_insns_num
8447 += 3 - curr_state->accumulated_insns_num % 3;
8448 }
8449 if (!insert_bundle_state (curr_state))
8450 free_bundle_state (curr_state);
8451 return;
8452 }
8453
8454 /* The following function returns position in the two window bundle
8455 for given STATE. */
8456
8457 static int
8458 get_max_pos (state_t state)
8459 {
8460 if (cpu_unit_reservation_p (state, pos_6))
8461 return 6;
8462 else if (cpu_unit_reservation_p (state, pos_5))
8463 return 5;
8464 else if (cpu_unit_reservation_p (state, pos_4))
8465 return 4;
8466 else if (cpu_unit_reservation_p (state, pos_3))
8467 return 3;
8468 else if (cpu_unit_reservation_p (state, pos_2))
8469 return 2;
8470 else if (cpu_unit_reservation_p (state, pos_1))
8471 return 1;
8472 else
8473 return 0;
8474 }
8475
8476 /* The function returns code of a possible template for given position
8477 and state. The function should be called only with 2 values of
8478 position equal to 3 or 6. We avoid generating F NOPs by putting
8479 templates containing F insns at the end of the template search
8480 because undocumented anomaly in McKinley derived cores which can
8481 cause stalls if an F-unit insn (including a NOP) is issued within a
8482 six-cycle window after reading certain application registers (such
8483 as ar.bsp). Furthermore, power-considerations also argue against
8484 the use of F-unit instructions unless they're really needed. */
8485
8486 static int
8487 get_template (state_t state, int pos)
8488 {
8489 switch (pos)
8490 {
8491 case 3:
8492 if (cpu_unit_reservation_p (state, _0mmi_))
8493 return 1;
8494 else if (cpu_unit_reservation_p (state, _0mii_))
8495 return 0;
8496 else if (cpu_unit_reservation_p (state, _0mmb_))
8497 return 7;
8498 else if (cpu_unit_reservation_p (state, _0mib_))
8499 return 6;
8500 else if (cpu_unit_reservation_p (state, _0mbb_))
8501 return 5;
8502 else if (cpu_unit_reservation_p (state, _0bbb_))
8503 return 4;
8504 else if (cpu_unit_reservation_p (state, _0mmf_))
8505 return 3;
8506 else if (cpu_unit_reservation_p (state, _0mfi_))
8507 return 2;
8508 else if (cpu_unit_reservation_p (state, _0mfb_))
8509 return 8;
8510 else if (cpu_unit_reservation_p (state, _0mlx_))
8511 return 9;
8512 else
8513 gcc_unreachable ();
8514 case 6:
8515 if (cpu_unit_reservation_p (state, _1mmi_))
8516 return 1;
8517 else if (cpu_unit_reservation_p (state, _1mii_))
8518 return 0;
8519 else if (cpu_unit_reservation_p (state, _1mmb_))
8520 return 7;
8521 else if (cpu_unit_reservation_p (state, _1mib_))
8522 return 6;
8523 else if (cpu_unit_reservation_p (state, _1mbb_))
8524 return 5;
8525 else if (cpu_unit_reservation_p (state, _1bbb_))
8526 return 4;
8527 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
8528 return 3;
8529 else if (cpu_unit_reservation_p (state, _1mfi_))
8530 return 2;
8531 else if (cpu_unit_reservation_p (state, _1mfb_))
8532 return 8;
8533 else if (cpu_unit_reservation_p (state, _1mlx_))
8534 return 9;
8535 else
8536 gcc_unreachable ();
8537 default:
8538 gcc_unreachable ();
8539 }
8540 }
8541
8542 /* True when INSN is important for bundling. */
8543 static bool
8544 important_for_bundling_p (rtx insn)
8545 {
8546 return (INSN_P (insn)
8547 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8548 && GET_CODE (PATTERN (insn)) != USE
8549 && GET_CODE (PATTERN (insn)) != CLOBBER);
8550 }
8551
8552 /* The following function returns an insn important for insn bundling
8553 followed by INSN and before TAIL. */
8554
8555 static rtx
8556 get_next_important_insn (rtx insn, rtx tail)
8557 {
8558 for (; insn && insn != tail; insn = NEXT_INSN (insn))
8559 if (important_for_bundling_p (insn))
8560 return insn;
8561 return NULL_RTX;
8562 }
8563
8564 /* Add a bundle selector TEMPLATE0 before INSN. */
8565
8566 static void
8567 ia64_add_bundle_selector_before (int template0, rtx insn)
8568 {
8569 rtx b = gen_bundle_selector (GEN_INT (template0));
8570
8571 ia64_emit_insn_before (b, insn);
8572 #if NR_BUNDLES == 10
8573 if ((template0 == 4 || template0 == 5)
8574 && ia64_except_unwind_info () == UI_TARGET)
8575 {
8576 int i;
8577 rtx note = NULL_RTX;
8578
8579 /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the
8580 first or second slot. If it is and has REG_EH_NOTE set, copy it
8581 to following nops, as br.call sets rp to the address of following
8582 bundle and therefore an EH region end must be on a bundle
8583 boundary. */
8584 insn = PREV_INSN (insn);
8585 for (i = 0; i < 3; i++)
8586 {
8587 do
8588 insn = next_active_insn (insn);
8589 while (GET_CODE (insn) == INSN
8590 && get_attr_empty (insn) == EMPTY_YES);
8591 if (GET_CODE (insn) == CALL_INSN)
8592 note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8593 else if (note)
8594 {
8595 int code;
8596
8597 gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop
8598 || code == CODE_FOR_nop_b);
8599 if (find_reg_note (insn, REG_EH_REGION, NULL_RTX))
8600 note = NULL_RTX;
8601 else
8602 add_reg_note (insn, REG_EH_REGION, XEXP (note, 0));
8603 }
8604 }
8605 }
8606 #endif
8607 }
8608
8609 /* The following function does insn bundling. Bundling means
8610 inserting templates and nop insns to fit insn groups into permitted
8611 templates. Instruction scheduling uses NDFA (non-deterministic
8612 finite automata) encoding informations about the templates and the
8613 inserted nops. Nondeterminism of the automata permits follows
8614 all possible insn sequences very fast.
8615
8616 Unfortunately it is not possible to get information about inserting
8617 nop insns and used templates from the automata states. The
8618 automata only says that we can issue an insn possibly inserting
8619 some nops before it and using some template. Therefore insn
8620 bundling in this function is implemented by using DFA
8621 (deterministic finite automata). We follow all possible insn
8622 sequences by inserting 0-2 nops (that is what the NDFA describe for
8623 insn scheduling) before/after each insn being bundled. We know the
8624 start of simulated processor cycle from insn scheduling (insn
8625 starting a new cycle has TImode).
8626
8627 Simple implementation of insn bundling would create enormous
8628 number of possible insn sequences satisfying information about new
8629 cycle ticks taken from the insn scheduling. To make the algorithm
8630 practical we use dynamic programming. Each decision (about
8631 inserting nops and implicitly about previous decisions) is described
8632 by structure bundle_state (see above). If we generate the same
8633 bundle state (key is automaton state after issuing the insns and
8634 nops for it), we reuse already generated one. As consequence we
8635 reject some decisions which cannot improve the solution and
8636 reduce memory for the algorithm.
8637
8638 When we reach the end of EBB (extended basic block), we choose the
8639 best sequence and then, moving back in EBB, insert templates for
8640 the best alternative. The templates are taken from querying
8641 automaton state for each insn in chosen bundle states.
8642
8643 So the algorithm makes two (forward and backward) passes through
8644 EBB. */
8645
8646 static void
8647 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
8648 {
8649 struct bundle_state *curr_state, *next_state, *best_state;
8650 rtx insn, next_insn;
8651 int insn_num;
8652 int i, bundle_end_p, only_bundle_end_p, asm_p;
8653 int pos = 0, max_pos, template0, template1;
8654 rtx b;
8655 rtx nop;
8656 enum attr_type type;
8657
8658 insn_num = 0;
8659 /* Count insns in the EBB. */
8660 for (insn = NEXT_INSN (prev_head_insn);
8661 insn && insn != tail;
8662 insn = NEXT_INSN (insn))
8663 if (INSN_P (insn))
8664 insn_num++;
8665 if (insn_num == 0)
8666 return;
8667 bundling_p = 1;
8668 dfa_clean_insn_cache ();
8669 initiate_bundle_state_table ();
8670 index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2);
8671 /* First (forward) pass -- generation of bundle states. */
8672 curr_state = get_free_bundle_state ();
8673 curr_state->insn = NULL;
8674 curr_state->before_nops_num = 0;
8675 curr_state->after_nops_num = 0;
8676 curr_state->insn_num = 0;
8677 curr_state->cost = 0;
8678 curr_state->accumulated_insns_num = 0;
8679 curr_state->branch_deviation = 0;
8680 curr_state->middle_bundle_stops = 0;
8681 curr_state->next = NULL;
8682 curr_state->originator = NULL;
8683 state_reset (curr_state->dfa_state);
8684 index_to_bundle_states [0] = curr_state;
8685 insn_num = 0;
8686 /* Shift cycle mark if it is put on insn which could be ignored. */
8687 for (insn = NEXT_INSN (prev_head_insn);
8688 insn != tail;
8689 insn = NEXT_INSN (insn))
8690 if (INSN_P (insn)
8691 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
8692 || GET_CODE (PATTERN (insn)) == USE
8693 || GET_CODE (PATTERN (insn)) == CLOBBER)
8694 && GET_MODE (insn) == TImode)
8695 {
8696 PUT_MODE (insn, VOIDmode);
8697 for (next_insn = NEXT_INSN (insn);
8698 next_insn != tail;
8699 next_insn = NEXT_INSN (next_insn))
8700 if (INSN_P (next_insn)
8701 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
8702 && GET_CODE (PATTERN (next_insn)) != USE
8703 && GET_CODE (PATTERN (next_insn)) != CLOBBER
8704 && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier)
8705 {
8706 PUT_MODE (next_insn, TImode);
8707 break;
8708 }
8709 }
8710 /* Forward pass: generation of bundle states. */
8711 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
8712 insn != NULL_RTX;
8713 insn = next_insn)
8714 {
8715 gcc_assert (INSN_P (insn)
8716 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
8717 && GET_CODE (PATTERN (insn)) != USE
8718 && GET_CODE (PATTERN (insn)) != CLOBBER);
8719 type = ia64_safe_type (insn);
8720 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
8721 insn_num++;
8722 index_to_bundle_states [insn_num] = NULL;
8723 for (curr_state = index_to_bundle_states [insn_num - 1];
8724 curr_state != NULL;
8725 curr_state = next_state)
8726 {
8727 pos = curr_state->accumulated_insns_num % 3;
8728 next_state = curr_state->next;
8729 /* We must fill up the current bundle in order to start a
8730 subsequent asm insn in a new bundle. Asm insn is always
8731 placed in a separate bundle. */
8732 only_bundle_end_p
8733 = (next_insn != NULL_RTX
8734 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
8735 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
8736 /* We may fill up the current bundle if it is the cycle end
8737 without a group barrier. */
8738 bundle_end_p
8739 = (only_bundle_end_p || next_insn == NULL_RTX
8740 || (GET_MODE (next_insn) == TImode
8741 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
8742 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
8743 || type == TYPE_S)
8744 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
8745 only_bundle_end_p);
8746 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
8747 only_bundle_end_p);
8748 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
8749 only_bundle_end_p);
8750 }
8751 gcc_assert (index_to_bundle_states [insn_num]);
8752 for (curr_state = index_to_bundle_states [insn_num];
8753 curr_state != NULL;
8754 curr_state = curr_state->next)
8755 if (verbose >= 2 && dump)
8756 {
8757 /* This structure is taken from generated code of the
8758 pipeline hazard recognizer (see file insn-attrtab.c).
8759 Please don't forget to change the structure if a new
8760 automaton is added to .md file. */
8761 struct DFA_chip
8762 {
8763 unsigned short one_automaton_state;
8764 unsigned short oneb_automaton_state;
8765 unsigned short two_automaton_state;
8766 unsigned short twob_automaton_state;
8767 };
8768
8769 fprintf
8770 (dump,
8771 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n",
8772 curr_state->unique_num,
8773 (curr_state->originator == NULL
8774 ? -1 : curr_state->originator->unique_num),
8775 curr_state->cost,
8776 curr_state->before_nops_num, curr_state->after_nops_num,
8777 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8778 curr_state->middle_bundle_stops,
8779 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
8780 INSN_UID (insn));
8781 }
8782 }
8783
8784 /* We should find a solution because the 2nd insn scheduling has
8785 found one. */
8786 gcc_assert (index_to_bundle_states [insn_num]);
8787 /* Find a state corresponding to the best insn sequence. */
8788 best_state = NULL;
8789 for (curr_state = index_to_bundle_states [insn_num];
8790 curr_state != NULL;
8791 curr_state = curr_state->next)
8792 /* We are just looking at the states with fully filled up last
8793 bundle. The first we prefer insn sequences with minimal cost
8794 then with minimal inserted nops and finally with branch insns
8795 placed in the 3rd slots. */
8796 if (curr_state->accumulated_insns_num % 3 == 0
8797 && (best_state == NULL || best_state->cost > curr_state->cost
8798 || (best_state->cost == curr_state->cost
8799 && (curr_state->accumulated_insns_num
8800 < best_state->accumulated_insns_num
8801 || (curr_state->accumulated_insns_num
8802 == best_state->accumulated_insns_num
8803 && (curr_state->branch_deviation
8804 < best_state->branch_deviation
8805 || (curr_state->branch_deviation
8806 == best_state->branch_deviation
8807 && curr_state->middle_bundle_stops
8808 < best_state->middle_bundle_stops)))))))
8809 best_state = curr_state;
8810 /* Second (backward) pass: adding nops and templates. */
8811 gcc_assert (best_state);
8812 insn_num = best_state->before_nops_num;
8813 template0 = template1 = -1;
8814 for (curr_state = best_state;
8815 curr_state->originator != NULL;
8816 curr_state = curr_state->originator)
8817 {
8818 insn = curr_state->insn;
8819 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
8820 || asm_noperands (PATTERN (insn)) >= 0);
8821 insn_num++;
8822 if (verbose >= 2 && dump)
8823 {
8824 struct DFA_chip
8825 {
8826 unsigned short one_automaton_state;
8827 unsigned short oneb_automaton_state;
8828 unsigned short two_automaton_state;
8829 unsigned short twob_automaton_state;
8830 };
8831
8832 fprintf
8833 (dump,
8834 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n",
8835 curr_state->unique_num,
8836 (curr_state->originator == NULL
8837 ? -1 : curr_state->originator->unique_num),
8838 curr_state->cost,
8839 curr_state->before_nops_num, curr_state->after_nops_num,
8840 curr_state->accumulated_insns_num, curr_state->branch_deviation,
8841 curr_state->middle_bundle_stops,
8842 ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state,
8843 INSN_UID (insn));
8844 }
8845 /* Find the position in the current bundle window. The window can
8846 contain at most two bundles. Two bundle window means that
8847 the processor will make two bundle rotation. */
8848 max_pos = get_max_pos (curr_state->dfa_state);
8849 if (max_pos == 6
8850 /* The following (negative template number) means that the
8851 processor did one bundle rotation. */
8852 || (max_pos == 3 && template0 < 0))
8853 {
8854 /* We are at the end of the window -- find template(s) for
8855 its bundle(s). */
8856 pos = max_pos;
8857 if (max_pos == 3)
8858 template0 = get_template (curr_state->dfa_state, 3);
8859 else
8860 {
8861 template1 = get_template (curr_state->dfa_state, 3);
8862 template0 = get_template (curr_state->dfa_state, 6);
8863 }
8864 }
8865 if (max_pos > 3 && template1 < 0)
8866 /* It may happen when we have the stop inside a bundle. */
8867 {
8868 gcc_assert (pos <= 3);
8869 template1 = get_template (curr_state->dfa_state, 3);
8870 pos += 3;
8871 }
8872 if (!asm_p)
8873 /* Emit nops after the current insn. */
8874 for (i = 0; i < curr_state->after_nops_num; i++)
8875 {
8876 nop = gen_nop ();
8877 emit_insn_after (nop, insn);
8878 pos--;
8879 gcc_assert (pos >= 0);
8880 if (pos % 3 == 0)
8881 {
8882 /* We are at the start of a bundle: emit the template
8883 (it should be defined). */
8884 gcc_assert (template0 >= 0);
8885 ia64_add_bundle_selector_before (template0, nop);
8886 /* If we have two bundle window, we make one bundle
8887 rotation. Otherwise template0 will be undefined
8888 (negative value). */
8889 template0 = template1;
8890 template1 = -1;
8891 }
8892 }
8893 /* Move the position backward in the window. Group barrier has
8894 no slot. Asm insn takes all bundle. */
8895 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8896 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8897 && asm_noperands (PATTERN (insn)) < 0)
8898 pos--;
8899 /* Long insn takes 2 slots. */
8900 if (ia64_safe_type (insn) == TYPE_L)
8901 pos--;
8902 gcc_assert (pos >= 0);
8903 if (pos % 3 == 0
8904 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
8905 && GET_CODE (PATTERN (insn)) != ASM_INPUT
8906 && asm_noperands (PATTERN (insn)) < 0)
8907 {
8908 /* The current insn is at the bundle start: emit the
8909 template. */
8910 gcc_assert (template0 >= 0);
8911 ia64_add_bundle_selector_before (template0, insn);
8912 b = PREV_INSN (insn);
8913 insn = b;
8914 /* See comment above in analogous place for emitting nops
8915 after the insn. */
8916 template0 = template1;
8917 template1 = -1;
8918 }
8919 /* Emit nops after the current insn. */
8920 for (i = 0; i < curr_state->before_nops_num; i++)
8921 {
8922 nop = gen_nop ();
8923 ia64_emit_insn_before (nop, insn);
8924 nop = PREV_INSN (insn);
8925 insn = nop;
8926 pos--;
8927 gcc_assert (pos >= 0);
8928 if (pos % 3 == 0)
8929 {
8930 /* See comment above in analogous place for emitting nops
8931 after the insn. */
8932 gcc_assert (template0 >= 0);
8933 ia64_add_bundle_selector_before (template0, insn);
8934 b = PREV_INSN (insn);
8935 insn = b;
8936 template0 = template1;
8937 template1 = -1;
8938 }
8939 }
8940 }
8941
8942 #ifdef ENABLE_CHECKING
8943 {
8944 /* Assert right calculation of middle_bundle_stops. */
8945 int num = best_state->middle_bundle_stops;
8946 bool start_bundle = true, end_bundle = false;
8947
8948 for (insn = NEXT_INSN (prev_head_insn);
8949 insn && insn != tail;
8950 insn = NEXT_INSN (insn))
8951 {
8952 if (!INSN_P (insn))
8953 continue;
8954 if (recog_memoized (insn) == CODE_FOR_bundle_selector)
8955 start_bundle = true;
8956 else
8957 {
8958 rtx next_insn;
8959
8960 for (next_insn = NEXT_INSN (insn);
8961 next_insn && next_insn != tail;
8962 next_insn = NEXT_INSN (next_insn))
8963 if (INSN_P (next_insn)
8964 && (ia64_safe_itanium_class (next_insn)
8965 != ITANIUM_CLASS_IGNORE
8966 || recog_memoized (next_insn)
8967 == CODE_FOR_bundle_selector)
8968 && GET_CODE (PATTERN (next_insn)) != USE
8969 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
8970 break;
8971
8972 end_bundle = next_insn == NULL_RTX
8973 || next_insn == tail
8974 || (INSN_P (next_insn)
8975 && recog_memoized (next_insn)
8976 == CODE_FOR_bundle_selector);
8977 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier
8978 && !start_bundle && !end_bundle
8979 && next_insn
8980 && GET_CODE (PATTERN (next_insn)) != ASM_INPUT
8981 && asm_noperands (PATTERN (next_insn)) < 0)
8982 num--;
8983
8984 start_bundle = false;
8985 }
8986 }
8987
8988 gcc_assert (num == 0);
8989 }
8990 #endif
8991
8992 free (index_to_bundle_states);
8993 finish_bundle_state_table ();
8994 bundling_p = 0;
8995 dfa_clean_insn_cache ();
8996 }
8997
8998 /* The following function is called at the end of scheduling BB or
8999 EBB. After reload, it inserts stop bits and does insn bundling. */
9000
9001 static void
9002 ia64_sched_finish (FILE *dump, int sched_verbose)
9003 {
9004 if (sched_verbose)
9005 fprintf (dump, "// Finishing schedule.\n");
9006 if (!reload_completed)
9007 return;
9008 if (reload_completed)
9009 {
9010 final_emit_insn_group_barriers (dump);
9011 bundling (dump, sched_verbose, current_sched_info->prev_head,
9012 current_sched_info->next_tail);
9013 if (sched_verbose && dump)
9014 fprintf (dump, "// finishing %d-%d\n",
9015 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
9016 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
9017
9018 return;
9019 }
9020 }
9021
9022 /* The following function inserts stop bits in scheduled BB or EBB. */
9023
9024 static void
9025 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
9026 {
9027 rtx insn;
9028 int need_barrier_p = 0;
9029 int seen_good_insn = 0;
9030
9031 init_insn_group_barriers ();
9032
9033 for (insn = NEXT_INSN (current_sched_info->prev_head);
9034 insn != current_sched_info->next_tail;
9035 insn = NEXT_INSN (insn))
9036 {
9037 if (GET_CODE (insn) == BARRIER)
9038 {
9039 rtx last = prev_active_insn (insn);
9040
9041 if (! last)
9042 continue;
9043 if (GET_CODE (last) == JUMP_INSN
9044 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
9045 last = prev_active_insn (last);
9046 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
9047 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
9048
9049 init_insn_group_barriers ();
9050 seen_good_insn = 0;
9051 need_barrier_p = 0;
9052 }
9053 else if (NONDEBUG_INSN_P (insn))
9054 {
9055 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
9056 {
9057 init_insn_group_barriers ();
9058 seen_good_insn = 0;
9059 need_barrier_p = 0;
9060 }
9061 else if (need_barrier_p || group_barrier_needed (insn)
9062 || (mflag_sched_stop_bits_after_every_cycle
9063 && GET_MODE (insn) == TImode
9064 && seen_good_insn))
9065 {
9066 if (TARGET_EARLY_STOP_BITS)
9067 {
9068 rtx last;
9069
9070 for (last = insn;
9071 last != current_sched_info->prev_head;
9072 last = PREV_INSN (last))
9073 if (INSN_P (last) && GET_MODE (last) == TImode
9074 && stops_p [INSN_UID (last)])
9075 break;
9076 if (last == current_sched_info->prev_head)
9077 last = insn;
9078 last = prev_active_insn (last);
9079 if (last
9080 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
9081 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
9082 last);
9083 init_insn_group_barriers ();
9084 for (last = NEXT_INSN (last);
9085 last != insn;
9086 last = NEXT_INSN (last))
9087 if (INSN_P (last))
9088 {
9089 group_barrier_needed (last);
9090 if (recog_memoized (last) >= 0
9091 && important_for_bundling_p (last))
9092 seen_good_insn = 1;
9093 }
9094 }
9095 else
9096 {
9097 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
9098 insn);
9099 init_insn_group_barriers ();
9100 seen_good_insn = 0;
9101 }
9102 group_barrier_needed (insn);
9103 if (recog_memoized (insn) >= 0
9104 && important_for_bundling_p (insn))
9105 seen_good_insn = 1;
9106 }
9107 else if (recog_memoized (insn) >= 0
9108 && important_for_bundling_p (insn))
9109 seen_good_insn = 1;
9110 need_barrier_p = (GET_CODE (insn) == CALL_INSN
9111 || GET_CODE (PATTERN (insn)) == ASM_INPUT
9112 || asm_noperands (PATTERN (insn)) >= 0);
9113 }
9114 }
9115 }
9116
9117 \f
9118
9119 /* If the following function returns TRUE, we will use the DFA
9120 insn scheduler. */
9121
9122 static int
9123 ia64_first_cycle_multipass_dfa_lookahead (void)
9124 {
9125 return (reload_completed ? 6 : 4);
9126 }
9127
9128 /* The following function initiates variable `dfa_pre_cycle_insn'. */
9129
9130 static void
9131 ia64_init_dfa_pre_cycle_insn (void)
9132 {
9133 if (temp_dfa_state == NULL)
9134 {
9135 dfa_state_size = state_size ();
9136 temp_dfa_state = xmalloc (dfa_state_size);
9137 prev_cycle_state = xmalloc (dfa_state_size);
9138 }
9139 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
9140 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
9141 recog_memoized (dfa_pre_cycle_insn);
9142 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
9143 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
9144 recog_memoized (dfa_stop_insn);
9145 }
9146
9147 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
9148 used by the DFA insn scheduler. */
9149
9150 static rtx
9151 ia64_dfa_pre_cycle_insn (void)
9152 {
9153 return dfa_pre_cycle_insn;
9154 }
9155
9156 /* The following function returns TRUE if PRODUCER (of type ilog or
9157 ld) produces address for CONSUMER (of type st or stf). */
9158
9159 int
9160 ia64_st_address_bypass_p (rtx producer, rtx consumer)
9161 {
9162 rtx dest, reg, mem;
9163
9164 gcc_assert (producer && consumer);
9165 dest = ia64_single_set (producer);
9166 gcc_assert (dest);
9167 reg = SET_DEST (dest);
9168 gcc_assert (reg);
9169 if (GET_CODE (reg) == SUBREG)
9170 reg = SUBREG_REG (reg);
9171 gcc_assert (GET_CODE (reg) == REG);
9172
9173 dest = ia64_single_set (consumer);
9174 gcc_assert (dest);
9175 mem = SET_DEST (dest);
9176 gcc_assert (mem && GET_CODE (mem) == MEM);
9177 return reg_mentioned_p (reg, mem);
9178 }
9179
9180 /* The following function returns TRUE if PRODUCER (of type ilog or
9181 ld) produces address for CONSUMER (of type ld or fld). */
9182
9183 int
9184 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
9185 {
9186 rtx dest, src, reg, mem;
9187
9188 gcc_assert (producer && consumer);
9189 dest = ia64_single_set (producer);
9190 gcc_assert (dest);
9191 reg = SET_DEST (dest);
9192 gcc_assert (reg);
9193 if (GET_CODE (reg) == SUBREG)
9194 reg = SUBREG_REG (reg);
9195 gcc_assert (GET_CODE (reg) == REG);
9196
9197 src = ia64_single_set (consumer);
9198 gcc_assert (src);
9199 mem = SET_SRC (src);
9200 gcc_assert (mem);
9201
9202 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
9203 mem = XVECEXP (mem, 0, 0);
9204 else if (GET_CODE (mem) == IF_THEN_ELSE)
9205 /* ??? Is this bypass necessary for ld.c? */
9206 {
9207 gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR);
9208 mem = XEXP (mem, 1);
9209 }
9210
9211 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
9212 mem = XEXP (mem, 0);
9213
9214 if (GET_CODE (mem) == UNSPEC)
9215 {
9216 int c = XINT (mem, 1);
9217
9218 gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A
9219 || c == UNSPEC_LDSA);
9220 mem = XVECEXP (mem, 0, 0);
9221 }
9222
9223 /* Note that LO_SUM is used for GOT loads. */
9224 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
9225
9226 return reg_mentioned_p (reg, mem);
9227 }
9228
9229 /* The following function returns TRUE if INSN produces address for a
9230 load/store insn. We will place such insns into M slot because it
9231 decreases its latency time. */
9232
9233 int
9234 ia64_produce_address_p (rtx insn)
9235 {
9236 return insn->call;
9237 }
9238
9239 \f
9240 /* Emit pseudo-ops for the assembler to describe predicate relations.
9241 At present this assumes that we only consider predicate pairs to
9242 be mutex, and that the assembler can deduce proper values from
9243 straight-line code. */
9244
9245 static void
9246 emit_predicate_relation_info (void)
9247 {
9248 basic_block bb;
9249
9250 FOR_EACH_BB_REVERSE (bb)
9251 {
9252 int r;
9253 rtx head = BB_HEAD (bb);
9254
9255 /* We only need such notes at code labels. */
9256 if (GET_CODE (head) != CODE_LABEL)
9257 continue;
9258 if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head)))
9259 head = NEXT_INSN (head);
9260
9261 /* Skip p0, which may be thought to be live due to (reg:DI p0)
9262 grabbing the entire block of predicate registers. */
9263 for (r = PR_REG (2); r < PR_REG (64); r += 2)
9264 if (REGNO_REG_SET_P (df_get_live_in (bb), r))
9265 {
9266 rtx p = gen_rtx_REG (BImode, r);
9267 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
9268 if (head == BB_END (bb))
9269 BB_END (bb) = n;
9270 head = n;
9271 }
9272 }
9273
9274 /* Look for conditional calls that do not return, and protect predicate
9275 relations around them. Otherwise the assembler will assume the call
9276 returns, and complain about uses of call-clobbered predicates after
9277 the call. */
9278 FOR_EACH_BB_REVERSE (bb)
9279 {
9280 rtx insn = BB_HEAD (bb);
9281
9282 while (1)
9283 {
9284 if (GET_CODE (insn) == CALL_INSN
9285 && GET_CODE (PATTERN (insn)) == COND_EXEC
9286 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
9287 {
9288 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
9289 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
9290 if (BB_HEAD (bb) == insn)
9291 BB_HEAD (bb) = b;
9292 if (BB_END (bb) == insn)
9293 BB_END (bb) = a;
9294 }
9295
9296 if (insn == BB_END (bb))
9297 break;
9298 insn = NEXT_INSN (insn);
9299 }
9300 }
9301 }
9302
9303 /* Perform machine dependent operations on the rtl chain INSNS. */
9304
9305 static void
9306 ia64_reorg (void)
9307 {
9308 /* We are freeing block_for_insn in the toplev to keep compatibility
9309 with old MDEP_REORGS that are not CFG based. Recompute it now. */
9310 compute_bb_for_insn ();
9311
9312 /* If optimizing, we'll have split before scheduling. */
9313 if (optimize == 0)
9314 split_all_insns ();
9315
9316 if (optimize && ia64_flag_schedule_insns2
9317 && dbg_cnt (ia64_sched2))
9318 {
9319 timevar_push (TV_SCHED2);
9320 ia64_final_schedule = 1;
9321
9322 initiate_bundle_states ();
9323 ia64_nop = make_insn_raw (gen_nop ());
9324 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
9325 recog_memoized (ia64_nop);
9326 clocks_length = get_max_uid () + 1;
9327 stops_p = XCNEWVEC (char, clocks_length);
9328
9329 if (ia64_tune == PROCESSOR_ITANIUM2)
9330 {
9331 pos_1 = get_cpu_unit_code ("2_1");
9332 pos_2 = get_cpu_unit_code ("2_2");
9333 pos_3 = get_cpu_unit_code ("2_3");
9334 pos_4 = get_cpu_unit_code ("2_4");
9335 pos_5 = get_cpu_unit_code ("2_5");
9336 pos_6 = get_cpu_unit_code ("2_6");
9337 _0mii_ = get_cpu_unit_code ("2b_0mii.");
9338 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
9339 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
9340 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
9341 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
9342 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
9343 _0mib_ = get_cpu_unit_code ("2b_0mib.");
9344 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
9345 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
9346 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
9347 _1mii_ = get_cpu_unit_code ("2b_1mii.");
9348 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
9349 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
9350 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
9351 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
9352 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
9353 _1mib_ = get_cpu_unit_code ("2b_1mib.");
9354 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
9355 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
9356 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
9357 }
9358 else
9359 {
9360 pos_1 = get_cpu_unit_code ("1_1");
9361 pos_2 = get_cpu_unit_code ("1_2");
9362 pos_3 = get_cpu_unit_code ("1_3");
9363 pos_4 = get_cpu_unit_code ("1_4");
9364 pos_5 = get_cpu_unit_code ("1_5");
9365 pos_6 = get_cpu_unit_code ("1_6");
9366 _0mii_ = get_cpu_unit_code ("1b_0mii.");
9367 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
9368 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
9369 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
9370 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
9371 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
9372 _0mib_ = get_cpu_unit_code ("1b_0mib.");
9373 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
9374 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
9375 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
9376 _1mii_ = get_cpu_unit_code ("1b_1mii.");
9377 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
9378 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
9379 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
9380 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
9381 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
9382 _1mib_ = get_cpu_unit_code ("1b_1mib.");
9383 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
9384 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
9385 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
9386 }
9387
9388 if (flag_selective_scheduling2
9389 && !maybe_skip_selective_scheduling ())
9390 run_selective_scheduling ();
9391 else
9392 schedule_ebbs ();
9393
9394 /* Redo alignment computation, as it might gone wrong. */
9395 compute_alignments ();
9396
9397 /* We cannot reuse this one because it has been corrupted by the
9398 evil glat. */
9399 finish_bundle_states ();
9400 free (stops_p);
9401 stops_p = NULL;
9402 emit_insn_group_barriers (dump_file);
9403
9404 ia64_final_schedule = 0;
9405 timevar_pop (TV_SCHED2);
9406 }
9407 else
9408 emit_all_insn_group_barriers (dump_file);
9409
9410 df_analyze ();
9411
9412 /* A call must not be the last instruction in a function, so that the
9413 return address is still within the function, so that unwinding works
9414 properly. Note that IA-64 differs from dwarf2 on this point. */
9415 if (ia64_except_unwind_info () == UI_TARGET)
9416 {
9417 rtx insn;
9418 int saw_stop = 0;
9419
9420 insn = get_last_insn ();
9421 if (! INSN_P (insn))
9422 insn = prev_active_insn (insn);
9423 if (insn)
9424 {
9425 /* Skip over insns that expand to nothing. */
9426 while (GET_CODE (insn) == INSN
9427 && get_attr_empty (insn) == EMPTY_YES)
9428 {
9429 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
9430 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
9431 saw_stop = 1;
9432 insn = prev_active_insn (insn);
9433 }
9434 if (GET_CODE (insn) == CALL_INSN)
9435 {
9436 if (! saw_stop)
9437 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9438 emit_insn (gen_break_f ());
9439 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
9440 }
9441 }
9442 }
9443
9444 emit_predicate_relation_info ();
9445
9446 if (ia64_flag_var_tracking)
9447 {
9448 timevar_push (TV_VAR_TRACKING);
9449 variable_tracking_main ();
9450 timevar_pop (TV_VAR_TRACKING);
9451 }
9452 df_finish_pass (false);
9453 }
9454 \f
9455 /* Return true if REGNO is used by the epilogue. */
9456
9457 int
9458 ia64_epilogue_uses (int regno)
9459 {
9460 switch (regno)
9461 {
9462 case R_GR (1):
9463 /* With a call to a function in another module, we will write a new
9464 value to "gp". After returning from such a call, we need to make
9465 sure the function restores the original gp-value, even if the
9466 function itself does not use the gp anymore. */
9467 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
9468
9469 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
9470 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
9471 /* For functions defined with the syscall_linkage attribute, all
9472 input registers are marked as live at all function exits. This
9473 prevents the register allocator from using the input registers,
9474 which in turn makes it possible to restart a system call after
9475 an interrupt without having to save/restore the input registers.
9476 This also prevents kernel data from leaking to application code. */
9477 return lookup_attribute ("syscall_linkage",
9478 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
9479
9480 case R_BR (0):
9481 /* Conditional return patterns can't represent the use of `b0' as
9482 the return address, so we force the value live this way. */
9483 return 1;
9484
9485 case AR_PFS_REGNUM:
9486 /* Likewise for ar.pfs, which is used by br.ret. */
9487 return 1;
9488
9489 default:
9490 return 0;
9491 }
9492 }
9493
9494 /* Return true if REGNO is used by the frame unwinder. */
9495
9496 int
9497 ia64_eh_uses (int regno)
9498 {
9499 unsigned int r;
9500
9501 if (! reload_completed)
9502 return 0;
9503
9504 if (regno == 0)
9505 return 0;
9506
9507 for (r = reg_save_b0; r <= reg_save_ar_lc; r++)
9508 if (regno == current_frame_info.r[r]
9509 || regno == emitted_frame_related_regs[r])
9510 return 1;
9511
9512 return 0;
9513 }
9514 \f
9515 /* Return true if this goes in small data/bss. */
9516
9517 /* ??? We could also support own long data here. Generating movl/add/ld8
9518 instead of addl,ld8/ld8. This makes the code bigger, but should make the
9519 code faster because there is one less load. This also includes incomplete
9520 types which can't go in sdata/sbss. */
9521
9522 static bool
9523 ia64_in_small_data_p (const_tree exp)
9524 {
9525 if (TARGET_NO_SDATA)
9526 return false;
9527
9528 /* We want to merge strings, so we never consider them small data. */
9529 if (TREE_CODE (exp) == STRING_CST)
9530 return false;
9531
9532 /* Functions are never small data. */
9533 if (TREE_CODE (exp) == FUNCTION_DECL)
9534 return false;
9535
9536 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
9537 {
9538 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
9539
9540 if (strcmp (section, ".sdata") == 0
9541 || strncmp (section, ".sdata.", 7) == 0
9542 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9543 || strcmp (section, ".sbss") == 0
9544 || strncmp (section, ".sbss.", 6) == 0
9545 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9546 return true;
9547 }
9548 else
9549 {
9550 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
9551
9552 /* If this is an incomplete type with size 0, then we can't put it
9553 in sdata because it might be too big when completed. */
9554 if (size > 0 && size <= ia64_section_threshold)
9555 return true;
9556 }
9557
9558 return false;
9559 }
9560 \f
9561 /* Output assembly directives for prologue regions. */
9562
9563 /* The current basic block number. */
9564
9565 static bool last_block;
9566
9567 /* True if we need a copy_state command at the start of the next block. */
9568
9569 static bool need_copy_state;
9570
9571 #ifndef MAX_ARTIFICIAL_LABEL_BYTES
9572 # define MAX_ARTIFICIAL_LABEL_BYTES 30
9573 #endif
9574
9575 /* Emit a debugging label after a call-frame-related insn. We'd
9576 rather output the label right away, but we'd have to output it
9577 after, not before, the instruction, and the instruction has not
9578 been output yet. So we emit the label after the insn, delete it to
9579 avoid introducing basic blocks, and mark it as preserved, such that
9580 it is still output, given that it is referenced in debug info. */
9581
9582 static const char *
9583 ia64_emit_deleted_label_after_insn (rtx insn)
9584 {
9585 char label[MAX_ARTIFICIAL_LABEL_BYTES];
9586 rtx lb = gen_label_rtx ();
9587 rtx label_insn = emit_label_after (lb, insn);
9588
9589 LABEL_PRESERVE_P (lb) = 1;
9590
9591 delete_insn (label_insn);
9592
9593 ASM_GENERATE_INTERNAL_LABEL (label, "L", CODE_LABEL_NUMBER (label_insn));
9594
9595 return xstrdup (label);
9596 }
9597
9598 /* Define the CFA after INSN with the steady-state definition. */
9599
9600 static void
9601 ia64_dwarf2out_def_steady_cfa (rtx insn, bool frame)
9602 {
9603 rtx fp = frame_pointer_needed
9604 ? hard_frame_pointer_rtx
9605 : stack_pointer_rtx;
9606 const char *label = ia64_emit_deleted_label_after_insn (insn);
9607
9608 if (!frame)
9609 return;
9610
9611 dwarf2out_def_cfa
9612 (label, REGNO (fp),
9613 ia64_initial_elimination_offset
9614 (REGNO (arg_pointer_rtx), REGNO (fp))
9615 + ARG_POINTER_CFA_OFFSET (current_function_decl));
9616 }
9617
9618 /* All we need to do here is avoid a crash in the generic dwarf2
9619 processing. The real CFA definition is set up above. */
9620
9621 static void
9622 ia64_dwarf_handle_frame_unspec (const char * ARG_UNUSED (label),
9623 rtx ARG_UNUSED (pattern),
9624 int index)
9625 {
9626 gcc_assert (index == UNSPECV_ALLOC);
9627 }
9628
9629 /* The generic dwarf2 frame debug info generator does not define a
9630 separate region for the very end of the epilogue, so refrain from
9631 doing so in the IA64-specific code as well. */
9632
9633 #define IA64_CHANGE_CFA_IN_EPILOGUE 0
9634
9635 /* The function emits unwind directives for the start of an epilogue. */
9636
9637 static void
9638 process_epilogue (FILE *asm_out_file, rtx insn, bool unwind, bool frame)
9639 {
9640 /* If this isn't the last block of the function, then we need to label the
9641 current state, and copy it back in at the start of the next block. */
9642
9643 if (!last_block)
9644 {
9645 if (unwind)
9646 fprintf (asm_out_file, "\t.label_state %d\n",
9647 ++cfun->machine->state_num);
9648 need_copy_state = true;
9649 }
9650
9651 if (unwind)
9652 fprintf (asm_out_file, "\t.restore sp\n");
9653 if (IA64_CHANGE_CFA_IN_EPILOGUE && frame)
9654 dwarf2out_def_cfa (ia64_emit_deleted_label_after_insn (insn),
9655 STACK_POINTER_REGNUM, INCOMING_FRAME_SP_OFFSET);
9656 }
9657
9658 /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */
9659
9660 static void
9661 process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn,
9662 bool unwind, bool frame)
9663 {
9664 rtx dest = SET_DEST (pat);
9665 rtx src = SET_SRC (pat);
9666
9667 if (dest == stack_pointer_rtx)
9668 {
9669 if (GET_CODE (src) == PLUS)
9670 {
9671 rtx op0 = XEXP (src, 0);
9672 rtx op1 = XEXP (src, 1);
9673
9674 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
9675
9676 if (INTVAL (op1) < 0)
9677 {
9678 gcc_assert (!frame_pointer_needed);
9679 if (unwind)
9680 fprintf (asm_out_file,
9681 "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
9682 -INTVAL (op1));
9683 ia64_dwarf2out_def_steady_cfa (insn, frame);
9684 }
9685 else
9686 process_epilogue (asm_out_file, insn, unwind, frame);
9687 }
9688 else
9689 {
9690 gcc_assert (src == hard_frame_pointer_rtx);
9691 process_epilogue (asm_out_file, insn, unwind, frame);
9692 }
9693 }
9694 else if (dest == hard_frame_pointer_rtx)
9695 {
9696 gcc_assert (src == stack_pointer_rtx);
9697 gcc_assert (frame_pointer_needed);
9698
9699 if (unwind)
9700 fprintf (asm_out_file, "\t.vframe r%d\n",
9701 ia64_dbx_register_number (REGNO (dest)));
9702 ia64_dwarf2out_def_steady_cfa (insn, frame);
9703 }
9704 else
9705 gcc_unreachable ();
9706 }
9707
9708 /* This function processes a SET pattern for REG_CFA_REGISTER. */
9709
9710 static void
9711 process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind)
9712 {
9713 rtx dest = SET_DEST (pat);
9714 rtx src = SET_SRC (pat);
9715
9716 int dest_regno = REGNO (dest);
9717 int src_regno = REGNO (src);
9718
9719 switch (src_regno)
9720 {
9721 case BR_REG (0):
9722 /* Saving return address pointer. */
9723 gcc_assert (dest_regno == current_frame_info.r[reg_save_b0]);
9724 if (unwind)
9725 fprintf (asm_out_file, "\t.save rp, r%d\n",
9726 ia64_dbx_register_number (dest_regno));
9727 break;
9728
9729 case PR_REG (0):
9730 gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]);
9731 if (unwind)
9732 fprintf (asm_out_file, "\t.save pr, r%d\n",
9733 ia64_dbx_register_number (dest_regno));
9734 break;
9735
9736 case AR_UNAT_REGNUM:
9737 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]);
9738 if (unwind)
9739 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
9740 ia64_dbx_register_number (dest_regno));
9741 break;
9742
9743 case AR_LC_REGNUM:
9744 gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]);
9745 if (unwind)
9746 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
9747 ia64_dbx_register_number (dest_regno));
9748 break;
9749
9750 default:
9751 /* Everything else should indicate being stored to memory. */
9752 gcc_unreachable ();
9753 }
9754 }
9755
9756 /* This function processes a SET pattern for REG_CFA_OFFSET. */
9757
9758 static void
9759 process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
9760 {
9761 rtx dest = SET_DEST (pat);
9762 rtx src = SET_SRC (pat);
9763 int src_regno = REGNO (src);
9764 const char *saveop;
9765 HOST_WIDE_INT off;
9766 rtx base;
9767
9768 gcc_assert (MEM_P (dest));
9769 if (GET_CODE (XEXP (dest, 0)) == REG)
9770 {
9771 base = XEXP (dest, 0);
9772 off = 0;
9773 }
9774 else
9775 {
9776 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
9777 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
9778 base = XEXP (XEXP (dest, 0), 0);
9779 off = INTVAL (XEXP (XEXP (dest, 0), 1));
9780 }
9781
9782 if (base == hard_frame_pointer_rtx)
9783 {
9784 saveop = ".savepsp";
9785 off = - off;
9786 }
9787 else
9788 {
9789 gcc_assert (base == stack_pointer_rtx);
9790 saveop = ".savesp";
9791 }
9792
9793 src_regno = REGNO (src);
9794 switch (src_regno)
9795 {
9796 case BR_REG (0):
9797 gcc_assert (!current_frame_info.r[reg_save_b0]);
9798 if (unwind)
9799 fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n",
9800 saveop, off);
9801 break;
9802
9803 case PR_REG (0):
9804 gcc_assert (!current_frame_info.r[reg_save_pr]);
9805 if (unwind)
9806 fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n",
9807 saveop, off);
9808 break;
9809
9810 case AR_LC_REGNUM:
9811 gcc_assert (!current_frame_info.r[reg_save_ar_lc]);
9812 if (unwind)
9813 fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n",
9814 saveop, off);
9815 break;
9816
9817 case AR_PFS_REGNUM:
9818 gcc_assert (!current_frame_info.r[reg_save_ar_pfs]);
9819 if (unwind)
9820 fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n",
9821 saveop, off);
9822 break;
9823
9824 case AR_UNAT_REGNUM:
9825 gcc_assert (!current_frame_info.r[reg_save_ar_unat]);
9826 if (unwind)
9827 fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n",
9828 saveop, off);
9829 break;
9830
9831 case GR_REG (4):
9832 case GR_REG (5):
9833 case GR_REG (6):
9834 case GR_REG (7):
9835 if (unwind)
9836 fprintf (asm_out_file, "\t.save.g 0x%x\n",
9837 1 << (src_regno - GR_REG (4)));
9838 break;
9839
9840 case BR_REG (1):
9841 case BR_REG (2):
9842 case BR_REG (3):
9843 case BR_REG (4):
9844 case BR_REG (5):
9845 if (unwind)
9846 fprintf (asm_out_file, "\t.save.b 0x%x\n",
9847 1 << (src_regno - BR_REG (1)));
9848 break;
9849
9850 case FR_REG (2):
9851 case FR_REG (3):
9852 case FR_REG (4):
9853 case FR_REG (5):
9854 if (unwind)
9855 fprintf (asm_out_file, "\t.save.f 0x%x\n",
9856 1 << (src_regno - FR_REG (2)));
9857 break;
9858
9859 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
9860 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
9861 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
9862 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
9863 if (unwind)
9864 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
9865 1 << (src_regno - FR_REG (12)));
9866 break;
9867
9868 default:
9869 /* ??? For some reason we mark other general registers, even those
9870 we can't represent in the unwind info. Ignore them. */
9871 break;
9872 }
9873 }
9874
9875 /* This function looks at a single insn and emits any directives
9876 required to unwind this insn. */
9877
9878 static void
9879 ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn)
9880 {
9881 bool unwind = ia64_except_unwind_info () == UI_TARGET;
9882 bool frame = dwarf2out_do_frame ();
9883 rtx note, pat;
9884 bool handled_one;
9885
9886 if (!unwind && !frame)
9887 return;
9888
9889 if (NOTE_INSN_BASIC_BLOCK_P (insn))
9890 {
9891 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
9892
9893 /* Restore unwind state from immediately before the epilogue. */
9894 if (need_copy_state)
9895 {
9896 if (unwind)
9897 {
9898 fprintf (asm_out_file, "\t.body\n");
9899 fprintf (asm_out_file, "\t.copy_state %d\n",
9900 cfun->machine->state_num);
9901 }
9902 if (IA64_CHANGE_CFA_IN_EPILOGUE)
9903 ia64_dwarf2out_def_steady_cfa (insn, frame);
9904 need_copy_state = false;
9905 }
9906 }
9907
9908 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
9909 return;
9910
9911 /* Look for the ALLOC insn. */
9912 if (INSN_CODE (insn) == CODE_FOR_alloc)
9913 {
9914 rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
9915 int dest_regno = REGNO (dest);
9916
9917 /* If this is the final destination for ar.pfs, then this must
9918 be the alloc in the prologue. */
9919 if (dest_regno == current_frame_info.r[reg_save_ar_pfs])
9920 {
9921 if (unwind)
9922 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
9923 ia64_dbx_register_number (dest_regno));
9924 }
9925 else
9926 {
9927 /* This must be an alloc before a sibcall. We must drop the
9928 old frame info. The easiest way to drop the old frame
9929 info is to ensure we had a ".restore sp" directive
9930 followed by a new prologue. If the procedure doesn't
9931 have a memory-stack frame, we'll issue a dummy ".restore
9932 sp" now. */
9933 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
9934 /* if haven't done process_epilogue() yet, do it now */
9935 process_epilogue (asm_out_file, insn, unwind, frame);
9936 if (unwind)
9937 fprintf (asm_out_file, "\t.prologue\n");
9938 }
9939 return;
9940 }
9941
9942 handled_one = false;
9943 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9944 switch (REG_NOTE_KIND (note))
9945 {
9946 case REG_CFA_ADJUST_CFA:
9947 pat = XEXP (note, 0);
9948 if (pat == NULL)
9949 pat = PATTERN (insn);
9950 process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame);
9951 handled_one = true;
9952 break;
9953
9954 case REG_CFA_OFFSET:
9955 pat = XEXP (note, 0);
9956 if (pat == NULL)
9957 pat = PATTERN (insn);
9958 process_cfa_offset (asm_out_file, pat, unwind);
9959 handled_one = true;
9960 break;
9961
9962 case REG_CFA_REGISTER:
9963 pat = XEXP (note, 0);
9964 if (pat == NULL)
9965 pat = PATTERN (insn);
9966 process_cfa_register (asm_out_file, pat, unwind);
9967 handled_one = true;
9968 break;
9969
9970 case REG_FRAME_RELATED_EXPR:
9971 case REG_CFA_DEF_CFA:
9972 case REG_CFA_EXPRESSION:
9973 case REG_CFA_RESTORE:
9974 case REG_CFA_SET_VDRAP:
9975 /* Not used in the ia64 port. */
9976 gcc_unreachable ();
9977
9978 default:
9979 /* Not a frame-related note. */
9980 break;
9981 }
9982
9983 /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the
9984 explicit action to take. No guessing required. */
9985 gcc_assert (handled_one);
9986 }
9987
9988 /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */
9989
9990 static void
9991 ia64_asm_emit_except_personality (rtx personality)
9992 {
9993 fputs ("\t.personality\t", asm_out_file);
9994 output_addr_const (asm_out_file, personality);
9995 fputc ('\n', asm_out_file);
9996 }
9997
9998 /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */
9999
10000 static void
10001 ia64_asm_init_sections (void)
10002 {
10003 exception_section = get_unnamed_section (0, output_section_asm_op,
10004 "\t.handlerdata");
10005 }
10006
10007 /* Implement TARGET_DEBUG_UNWIND_INFO. */
10008
10009 static enum unwind_info_type
10010 ia64_debug_unwind_info (void)
10011 {
10012 return UI_TARGET;
10013 }
10014
10015 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
10016
10017 static enum unwind_info_type
10018 ia64_except_unwind_info (void)
10019 {
10020 /* Honor the --enable-sjlj-exceptions configure switch. */
10021 #ifdef CONFIG_UNWIND_EXCEPTIONS
10022 if (CONFIG_UNWIND_EXCEPTIONS)
10023 return UI_SJLJ;
10024 #endif
10025
10026 /* For simplicity elsewhere in this file, indicate that all unwind
10027 info is disabled if we're not emitting unwind tables. */
10028 if (!flag_exceptions && !flag_unwind_tables)
10029 return UI_NONE;
10030
10031 return UI_TARGET;
10032 }
10033 \f
10034 enum ia64_builtins
10035 {
10036 IA64_BUILTIN_BSP,
10037 IA64_BUILTIN_COPYSIGNQ,
10038 IA64_BUILTIN_FABSQ,
10039 IA64_BUILTIN_FLUSHRS,
10040 IA64_BUILTIN_INFQ,
10041 IA64_BUILTIN_HUGE_VALQ,
10042 IA64_BUILTIN_max
10043 };
10044
10045 static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max];
10046
10047 void
10048 ia64_init_builtins (void)
10049 {
10050 tree fpreg_type;
10051 tree float80_type;
10052 tree decl;
10053
10054 /* The __fpreg type. */
10055 fpreg_type = make_node (REAL_TYPE);
10056 TYPE_PRECISION (fpreg_type) = 82;
10057 layout_type (fpreg_type);
10058 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
10059
10060 /* The __float80 type. */
10061 float80_type = make_node (REAL_TYPE);
10062 TYPE_PRECISION (float80_type) = 80;
10063 layout_type (float80_type);
10064 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
10065
10066 /* The __float128 type. */
10067 if (!TARGET_HPUX)
10068 {
10069 tree ftype;
10070 tree float128_type = make_node (REAL_TYPE);
10071
10072 TYPE_PRECISION (float128_type) = 128;
10073 layout_type (float128_type);
10074 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
10075
10076 /* TFmode support builtins. */
10077 ftype = build_function_type (float128_type, void_list_node);
10078 decl = add_builtin_function ("__builtin_infq", ftype,
10079 IA64_BUILTIN_INFQ, BUILT_IN_MD,
10080 NULL, NULL_TREE);
10081 ia64_builtins[IA64_BUILTIN_INFQ] = decl;
10082
10083 decl = add_builtin_function ("__builtin_huge_valq", ftype,
10084 IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
10085 NULL, NULL_TREE);
10086 ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl;
10087
10088 ftype = build_function_type_list (float128_type,
10089 float128_type,
10090 NULL_TREE);
10091 decl = add_builtin_function ("__builtin_fabsq", ftype,
10092 IA64_BUILTIN_FABSQ, BUILT_IN_MD,
10093 "__fabstf2", NULL_TREE);
10094 TREE_READONLY (decl) = 1;
10095 ia64_builtins[IA64_BUILTIN_FABSQ] = decl;
10096
10097 ftype = build_function_type_list (float128_type,
10098 float128_type,
10099 float128_type,
10100 NULL_TREE);
10101 decl = add_builtin_function ("__builtin_copysignq", ftype,
10102 IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
10103 "__copysigntf3", NULL_TREE);
10104 TREE_READONLY (decl) = 1;
10105 ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl;
10106 }
10107 else
10108 /* Under HPUX, this is a synonym for "long double". */
10109 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
10110 "__float128");
10111
10112 /* Fwrite on VMS is non-standard. */
10113 if (TARGET_ABI_OPEN_VMS)
10114 {
10115 implicit_built_in_decls[(int) BUILT_IN_FWRITE] = NULL_TREE;
10116 implicit_built_in_decls[(int) BUILT_IN_FWRITE_UNLOCKED] = NULL_TREE;
10117 }
10118
10119 #define def_builtin(name, type, code) \
10120 add_builtin_function ((name), (type), (code), BUILT_IN_MD, \
10121 NULL, NULL_TREE)
10122
10123 decl = def_builtin ("__builtin_ia64_bsp",
10124 build_function_type (ptr_type_node, void_list_node),
10125 IA64_BUILTIN_BSP);
10126 ia64_builtins[IA64_BUILTIN_BSP] = decl;
10127
10128 decl = def_builtin ("__builtin_ia64_flushrs",
10129 build_function_type (void_type_node, void_list_node),
10130 IA64_BUILTIN_FLUSHRS);
10131 ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl;
10132
10133 #undef def_builtin
10134
10135 if (TARGET_HPUX)
10136 {
10137 if (built_in_decls [BUILT_IN_FINITE])
10138 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE],
10139 "_Isfinite");
10140 if (built_in_decls [BUILT_IN_FINITEF])
10141 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF],
10142 "_Isfinitef");
10143 if (built_in_decls [BUILT_IN_FINITEL])
10144 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEL],
10145 "_Isfinitef128");
10146 }
10147 }
10148
10149 rtx
10150 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10151 enum machine_mode mode ATTRIBUTE_UNUSED,
10152 int ignore ATTRIBUTE_UNUSED)
10153 {
10154 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10155 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10156
10157 switch (fcode)
10158 {
10159 case IA64_BUILTIN_BSP:
10160 if (! target || ! register_operand (target, DImode))
10161 target = gen_reg_rtx (DImode);
10162 emit_insn (gen_bsp_value (target));
10163 #ifdef POINTERS_EXTEND_UNSIGNED
10164 target = convert_memory_address (ptr_mode, target);
10165 #endif
10166 return target;
10167
10168 case IA64_BUILTIN_FLUSHRS:
10169 emit_insn (gen_flushrs ());
10170 return const0_rtx;
10171
10172 case IA64_BUILTIN_INFQ:
10173 case IA64_BUILTIN_HUGE_VALQ:
10174 {
10175 REAL_VALUE_TYPE inf;
10176 rtx tmp;
10177
10178 real_inf (&inf);
10179 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
10180
10181 tmp = validize_mem (force_const_mem (mode, tmp));
10182
10183 if (target == 0)
10184 target = gen_reg_rtx (mode);
10185
10186 emit_move_insn (target, tmp);
10187 return target;
10188 }
10189
10190 case IA64_BUILTIN_FABSQ:
10191 case IA64_BUILTIN_COPYSIGNQ:
10192 return expand_call (exp, target, ignore);
10193
10194 default:
10195 gcc_unreachable ();
10196 }
10197
10198 return NULL_RTX;
10199 }
10200
10201 /* Return the ia64 builtin for CODE. */
10202
10203 static tree
10204 ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10205 {
10206 if (code >= IA64_BUILTIN_max)
10207 return error_mark_node;
10208
10209 return ia64_builtins[code];
10210 }
10211
10212 /* For the HP-UX IA64 aggregate parameters are passed stored in the
10213 most significant bits of the stack slot. */
10214
10215 enum direction
10216 ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type)
10217 {
10218 /* Exception to normal case for structures/unions/etc. */
10219
10220 if (type && AGGREGATE_TYPE_P (type)
10221 && int_size_in_bytes (type) < UNITS_PER_WORD)
10222 return upward;
10223
10224 /* Fall back to the default. */
10225 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
10226 }
10227
10228 /* Emit text to declare externally defined variables and functions, because
10229 the Intel assembler does not support undefined externals. */
10230
10231 void
10232 ia64_asm_output_external (FILE *file, tree decl, const char *name)
10233 {
10234 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
10235 set in order to avoid putting out names that are never really
10236 used. */
10237 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
10238 {
10239 /* maybe_assemble_visibility will return 1 if the assembler
10240 visibility directive is output. */
10241 int need_visibility = ((*targetm.binds_local_p) (decl)
10242 && maybe_assemble_visibility (decl));
10243
10244 #ifdef DO_CRTL_NAMES
10245 DO_CRTL_NAMES;
10246 #endif
10247
10248 /* GNU as does not need anything here, but the HP linker does
10249 need something for external functions. */
10250 if ((TARGET_HPUX_LD || !TARGET_GNU_AS)
10251 && TREE_CODE (decl) == FUNCTION_DECL)
10252 (*targetm.asm_out.globalize_decl_name) (file, decl);
10253 else if (need_visibility && !TARGET_GNU_AS)
10254 (*targetm.asm_out.globalize_label) (file, name);
10255 }
10256 }
10257
10258 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
10259 modes of word_mode and larger. Rename the TFmode libfuncs using the
10260 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
10261 backward compatibility. */
10262
10263 static void
10264 ia64_init_libfuncs (void)
10265 {
10266 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
10267 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
10268 set_optab_libfunc (smod_optab, SImode, "__modsi3");
10269 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
10270
10271 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
10272 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
10273 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
10274 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
10275 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
10276
10277 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
10278 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
10279 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
10280 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
10281 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
10282 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
10283
10284 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
10285 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
10286 set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad");
10287 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
10288 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
10289
10290 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
10291 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
10292 set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad");
10293 /* HP-UX 11.23 libc does not have a function for unsigned
10294 SImode-to-TFmode conversion. */
10295 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad");
10296 }
10297
10298 /* Rename all the TFmode libfuncs using the HPUX conventions. */
10299
10300 static void
10301 ia64_hpux_init_libfuncs (void)
10302 {
10303 ia64_init_libfuncs ();
10304
10305 /* The HP SI millicode division and mod functions expect DI arguments.
10306 By turning them off completely we avoid using both libgcc and the
10307 non-standard millicode routines and use the HP DI millicode routines
10308 instead. */
10309
10310 set_optab_libfunc (sdiv_optab, SImode, 0);
10311 set_optab_libfunc (udiv_optab, SImode, 0);
10312 set_optab_libfunc (smod_optab, SImode, 0);
10313 set_optab_libfunc (umod_optab, SImode, 0);
10314
10315 set_optab_libfunc (sdiv_optab, DImode, "__milli_divI");
10316 set_optab_libfunc (udiv_optab, DImode, "__milli_divU");
10317 set_optab_libfunc (smod_optab, DImode, "__milli_remI");
10318 set_optab_libfunc (umod_optab, DImode, "__milli_remU");
10319
10320 /* HP-UX libc has TF min/max/abs routines in it. */
10321 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
10322 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
10323 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
10324
10325 /* ia64_expand_compare uses this. */
10326 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
10327
10328 /* These should never be used. */
10329 set_optab_libfunc (eq_optab, TFmode, 0);
10330 set_optab_libfunc (ne_optab, TFmode, 0);
10331 set_optab_libfunc (gt_optab, TFmode, 0);
10332 set_optab_libfunc (ge_optab, TFmode, 0);
10333 set_optab_libfunc (lt_optab, TFmode, 0);
10334 set_optab_libfunc (le_optab, TFmode, 0);
10335 }
10336
10337 /* Rename the division and modulus functions in VMS. */
10338
10339 static void
10340 ia64_vms_init_libfuncs (void)
10341 {
10342 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10343 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10344 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10345 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10346 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10347 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10348 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10349 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10350 abort_libfunc = init_one_libfunc ("decc$abort");
10351 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10352 #ifdef MEM_LIBFUNCS_INIT
10353 MEM_LIBFUNCS_INIT;
10354 #endif
10355 }
10356
10357 /* Rename the TFmode libfuncs available from soft-fp in glibc using
10358 the HPUX conventions. */
10359
10360 static void
10361 ia64_sysv4_init_libfuncs (void)
10362 {
10363 ia64_init_libfuncs ();
10364
10365 /* These functions are not part of the HPUX TFmode interface. We
10366 use them instead of _U_Qfcmp, which doesn't work the way we
10367 expect. */
10368 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
10369 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
10370 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
10371 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
10372 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
10373 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
10374
10375 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
10376 glibc doesn't have them. */
10377 }
10378
10379 /* Use soft-fp. */
10380
10381 static void
10382 ia64_soft_fp_init_libfuncs (void)
10383 {
10384 }
10385
10386 static bool
10387 ia64_vms_valid_pointer_mode (enum machine_mode mode)
10388 {
10389 return (mode == SImode || mode == DImode);
10390 }
10391 \f
10392 /* For HPUX, it is illegal to have relocations in shared segments. */
10393
10394 static int
10395 ia64_hpux_reloc_rw_mask (void)
10396 {
10397 return 3;
10398 }
10399
10400 /* For others, relax this so that relocations to local data goes in
10401 read-only segments, but we still cannot allow global relocations
10402 in read-only segments. */
10403
10404 static int
10405 ia64_reloc_rw_mask (void)
10406 {
10407 return flag_pic ? 3 : 2;
10408 }
10409
10410 /* Return the section to use for X. The only special thing we do here
10411 is to honor small data. */
10412
10413 static section *
10414 ia64_select_rtx_section (enum machine_mode mode, rtx x,
10415 unsigned HOST_WIDE_INT align)
10416 {
10417 if (GET_MODE_SIZE (mode) > 0
10418 && GET_MODE_SIZE (mode) <= ia64_section_threshold
10419 && !TARGET_NO_SDATA)
10420 return sdata_section;
10421 else
10422 return default_elf_select_rtx_section (mode, x, align);
10423 }
10424
10425 static unsigned int
10426 ia64_section_type_flags (tree decl, const char *name, int reloc)
10427 {
10428 unsigned int flags = 0;
10429
10430 if (strcmp (name, ".sdata") == 0
10431 || strncmp (name, ".sdata.", 7) == 0
10432 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
10433 || strncmp (name, ".sdata2.", 8) == 0
10434 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
10435 || strcmp (name, ".sbss") == 0
10436 || strncmp (name, ".sbss.", 6) == 0
10437 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
10438 flags = SECTION_SMALL;
10439
10440 #if TARGET_ABI_OPEN_VMS
10441 if (decl && DECL_ATTRIBUTES (decl)
10442 && lookup_attribute ("common_object", DECL_ATTRIBUTES (decl)))
10443 flags |= SECTION_VMS_OVERLAY;
10444 #endif
10445
10446 flags |= default_section_type_flags (decl, name, reloc);
10447 return flags;
10448 }
10449
10450 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
10451 structure type and that the address of that type should be passed
10452 in out0, rather than in r8. */
10453
10454 static bool
10455 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
10456 {
10457 tree ret_type = TREE_TYPE (fntype);
10458
10459 /* The Itanium C++ ABI requires that out0, rather than r8, be used
10460 as the structure return address parameter, if the return value
10461 type has a non-trivial copy constructor or destructor. It is not
10462 clear if this same convention should be used for other
10463 programming languages. Until G++ 3.4, we incorrectly used r8 for
10464 these return values. */
10465 return (abi_version_at_least (2)
10466 && ret_type
10467 && TYPE_MODE (ret_type) == BLKmode
10468 && TREE_ADDRESSABLE (ret_type)
10469 && strcmp (lang_hooks.name, "GNU C++") == 0);
10470 }
10471
10472 /* Output the assembler code for a thunk function. THUNK_DECL is the
10473 declaration for the thunk function itself, FUNCTION is the decl for
10474 the target function. DELTA is an immediate constant offset to be
10475 added to THIS. If VCALL_OFFSET is nonzero, the word at
10476 *(*this + vcall_offset) should be added to THIS. */
10477
10478 static void
10479 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10480 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10481 tree function)
10482 {
10483 rtx this_rtx, insn, funexp;
10484 unsigned int this_parmno;
10485 unsigned int this_regno;
10486 rtx delta_rtx;
10487
10488 reload_completed = 1;
10489 epilogue_completed = 1;
10490
10491 /* Set things up as ia64_expand_prologue might. */
10492 last_scratch_gr_reg = 15;
10493
10494 memset (&current_frame_info, 0, sizeof (current_frame_info));
10495 current_frame_info.spill_cfa_off = -16;
10496 current_frame_info.n_input_regs = 1;
10497 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
10498
10499 /* Mark the end of the (empty) prologue. */
10500 emit_note (NOTE_INSN_PROLOGUE_END);
10501
10502 /* Figure out whether "this" will be the first parameter (the
10503 typical case) or the second parameter (as happens when the
10504 virtual function returns certain class objects). */
10505 this_parmno
10506 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
10507 ? 1 : 0);
10508 this_regno = IN_REG (this_parmno);
10509 if (!TARGET_REG_NAMES)
10510 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
10511
10512 this_rtx = gen_rtx_REG (Pmode, this_regno);
10513
10514 /* Apply the constant offset, if required. */
10515 delta_rtx = GEN_INT (delta);
10516 if (TARGET_ILP32)
10517 {
10518 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
10519 REG_POINTER (tmp) = 1;
10520 if (delta && satisfies_constraint_I (delta_rtx))
10521 {
10522 emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx));
10523 delta = 0;
10524 }
10525 else
10526 emit_insn (gen_ptr_extend (this_rtx, tmp));
10527 }
10528 if (delta)
10529 {
10530 if (!satisfies_constraint_I (delta_rtx))
10531 {
10532 rtx tmp = gen_rtx_REG (Pmode, 2);
10533 emit_move_insn (tmp, delta_rtx);
10534 delta_rtx = tmp;
10535 }
10536 emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx));
10537 }
10538
10539 /* Apply the offset from the vtable, if required. */
10540 if (vcall_offset)
10541 {
10542 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
10543 rtx tmp = gen_rtx_REG (Pmode, 2);
10544
10545 if (TARGET_ILP32)
10546 {
10547 rtx t = gen_rtx_REG (ptr_mode, 2);
10548 REG_POINTER (t) = 1;
10549 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx));
10550 if (satisfies_constraint_I (vcall_offset_rtx))
10551 {
10552 emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx));
10553 vcall_offset = 0;
10554 }
10555 else
10556 emit_insn (gen_ptr_extend (tmp, t));
10557 }
10558 else
10559 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
10560
10561 if (vcall_offset)
10562 {
10563 if (!satisfies_constraint_J (vcall_offset_rtx))
10564 {
10565 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
10566 emit_move_insn (tmp2, vcall_offset_rtx);
10567 vcall_offset_rtx = tmp2;
10568 }
10569 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
10570 }
10571
10572 if (TARGET_ILP32)
10573 emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp)));
10574 else
10575 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
10576
10577 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
10578 }
10579
10580 /* Generate a tail call to the target function. */
10581 if (! TREE_USED (function))
10582 {
10583 assemble_external (function);
10584 TREE_USED (function) = 1;
10585 }
10586 funexp = XEXP (DECL_RTL (function), 0);
10587 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
10588 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
10589 insn = get_last_insn ();
10590 SIBLING_CALL_P (insn) = 1;
10591
10592 /* Code generation for calls relies on splitting. */
10593 reload_completed = 1;
10594 epilogue_completed = 1;
10595 try_split (PATTERN (insn), insn, 0);
10596
10597 emit_barrier ();
10598
10599 /* Run just enough of rest_of_compilation to get the insns emitted.
10600 There's not really enough bulk here to make other passes such as
10601 instruction scheduling worth while. Note that use_thunk calls
10602 assemble_start_function and assemble_end_function. */
10603
10604 insn_locators_alloc ();
10605 emit_all_insn_group_barriers (NULL);
10606 insn = get_insns ();
10607 shorten_branches (insn);
10608 final_start_function (insn, file, 1);
10609 final (insn, file, 1);
10610 final_end_function ();
10611
10612 reload_completed = 0;
10613 epilogue_completed = 0;
10614 }
10615
10616 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
10617
10618 static rtx
10619 ia64_struct_value_rtx (tree fntype,
10620 int incoming ATTRIBUTE_UNUSED)
10621 {
10622 if (TARGET_ABI_OPEN_VMS ||
10623 (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype)))
10624 return NULL_RTX;
10625 return gen_rtx_REG (Pmode, GR_REG (8));
10626 }
10627
10628 static bool
10629 ia64_scalar_mode_supported_p (enum machine_mode mode)
10630 {
10631 switch (mode)
10632 {
10633 case QImode:
10634 case HImode:
10635 case SImode:
10636 case DImode:
10637 case TImode:
10638 return true;
10639
10640 case SFmode:
10641 case DFmode:
10642 case XFmode:
10643 case RFmode:
10644 return true;
10645
10646 case TFmode:
10647 return true;
10648
10649 default:
10650 return false;
10651 }
10652 }
10653
10654 static bool
10655 ia64_vector_mode_supported_p (enum machine_mode mode)
10656 {
10657 switch (mode)
10658 {
10659 case V8QImode:
10660 case V4HImode:
10661 case V2SImode:
10662 return true;
10663
10664 case V2SFmode:
10665 return true;
10666
10667 default:
10668 return false;
10669 }
10670 }
10671
10672 /* Implement the FUNCTION_PROFILER macro. */
10673
10674 void
10675 ia64_output_function_profiler (FILE *file, int labelno)
10676 {
10677 bool indirect_call;
10678
10679 /* If the function needs a static chain and the static chain
10680 register is r15, we use an indirect call so as to bypass
10681 the PLT stub in case the executable is dynamically linked,
10682 because the stub clobbers r15 as per 5.3.6 of the psABI.
10683 We don't need to do that in non canonical PIC mode. */
10684
10685 if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC)
10686 {
10687 gcc_assert (STATIC_CHAIN_REGNUM == 15);
10688 indirect_call = true;
10689 }
10690 else
10691 indirect_call = false;
10692
10693 if (TARGET_GNU_AS)
10694 fputs ("\t.prologue 4, r40\n", file);
10695 else
10696 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
10697 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
10698
10699 if (NO_PROFILE_COUNTERS)
10700 fputs ("\tmov out3 = r0\n", file);
10701 else
10702 {
10703 char buf[20];
10704 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10705
10706 if (TARGET_AUTO_PIC)
10707 fputs ("\tmovl out3 = @gprel(", file);
10708 else
10709 fputs ("\taddl out3 = @ltoff(", file);
10710 assemble_name (file, buf);
10711 if (TARGET_AUTO_PIC)
10712 fputs (")\n", file);
10713 else
10714 fputs ("), r1\n", file);
10715 }
10716
10717 if (indirect_call)
10718 fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file);
10719 fputs ("\t;;\n", file);
10720
10721 fputs ("\t.save rp, r42\n", file);
10722 fputs ("\tmov out2 = b0\n", file);
10723 if (indirect_call)
10724 fputs ("\tld8 r14 = [r14]\n\t;;\n", file);
10725 fputs ("\t.body\n", file);
10726 fputs ("\tmov out1 = r1\n", file);
10727 if (indirect_call)
10728 {
10729 fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file);
10730 fputs ("\tmov b6 = r16\n", file);
10731 fputs ("\tld8 r1 = [r14]\n", file);
10732 fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file);
10733 }
10734 else
10735 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
10736 }
10737
10738 static GTY(()) rtx mcount_func_rtx;
10739 static rtx
10740 gen_mcount_func_rtx (void)
10741 {
10742 if (!mcount_func_rtx)
10743 mcount_func_rtx = init_one_libfunc ("_mcount");
10744 return mcount_func_rtx;
10745 }
10746
10747 void
10748 ia64_profile_hook (int labelno)
10749 {
10750 rtx label, ip;
10751
10752 if (NO_PROFILE_COUNTERS)
10753 label = const0_rtx;
10754 else
10755 {
10756 char buf[30];
10757 const char *label_name;
10758 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
10759 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
10760 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
10761 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
10762 }
10763 ip = gen_reg_rtx (Pmode);
10764 emit_insn (gen_ip_value (ip));
10765 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
10766 VOIDmode, 3,
10767 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
10768 ip, Pmode,
10769 label, Pmode);
10770 }
10771
10772 /* Return the mangling of TYPE if it is an extended fundamental type. */
10773
10774 static const char *
10775 ia64_mangle_type (const_tree type)
10776 {
10777 type = TYPE_MAIN_VARIANT (type);
10778
10779 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
10780 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
10781 return NULL;
10782
10783 /* On HP-UX, "long double" is mangled as "e" so __float128 is
10784 mangled as "e". */
10785 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
10786 return "g";
10787 /* On HP-UX, "e" is not available as a mangling of __float80 so use
10788 an extended mangling. Elsewhere, "e" is available since long
10789 double is 80 bits. */
10790 if (TYPE_MODE (type) == XFmode)
10791 return TARGET_HPUX ? "u9__float80" : "e";
10792 if (TYPE_MODE (type) == RFmode)
10793 return "u7__fpreg";
10794 return NULL;
10795 }
10796
10797 /* Return the diagnostic message string if conversion from FROMTYPE to
10798 TOTYPE is not allowed, NULL otherwise. */
10799 static const char *
10800 ia64_invalid_conversion (const_tree fromtype, const_tree totype)
10801 {
10802 /* Reject nontrivial conversion to or from __fpreg. */
10803 if (TYPE_MODE (fromtype) == RFmode
10804 && TYPE_MODE (totype) != RFmode
10805 && TYPE_MODE (totype) != VOIDmode)
10806 return N_("invalid conversion from %<__fpreg%>");
10807 if (TYPE_MODE (totype) == RFmode
10808 && TYPE_MODE (fromtype) != RFmode)
10809 return N_("invalid conversion to %<__fpreg%>");
10810 return NULL;
10811 }
10812
10813 /* Return the diagnostic message string if the unary operation OP is
10814 not permitted on TYPE, NULL otherwise. */
10815 static const char *
10816 ia64_invalid_unary_op (int op, const_tree type)
10817 {
10818 /* Reject operations on __fpreg other than unary + or &. */
10819 if (TYPE_MODE (type) == RFmode
10820 && op != CONVERT_EXPR
10821 && op != ADDR_EXPR)
10822 return N_("invalid operation on %<__fpreg%>");
10823 return NULL;
10824 }
10825
10826 /* Return the diagnostic message string if the binary operation OP is
10827 not permitted on TYPE1 and TYPE2, NULL otherwise. */
10828 static const char *
10829 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2)
10830 {
10831 /* Reject operations on __fpreg. */
10832 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
10833 return N_("invalid operation on %<__fpreg%>");
10834 return NULL;
10835 }
10836
10837 /* Implement overriding of the optimization options. */
10838 static void
10839 ia64_option_optimization (int level ATTRIBUTE_UNUSED,
10840 int size ATTRIBUTE_UNUSED)
10841 {
10842 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
10843 SUBTARGET_OPTIMIZATION_OPTIONS;
10844 #endif
10845
10846 /* Let the scheduler form additional regions. */
10847 set_param_value ("max-sched-extend-regions-iters", 2);
10848
10849 /* Set the default values for cache-related parameters. */
10850 set_param_value ("simultaneous-prefetches", 6);
10851 set_param_value ("l1-cache-line-size", 32);
10852
10853 set_param_value("sched-mem-true-dep-cost", 4);
10854 }
10855
10856 /* HP-UX version_id attribute.
10857 For object foo, if the version_id is set to 1234 put out an alias
10858 of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything
10859 other than an alias statement because it is an illegal symbol name. */
10860
10861 static tree
10862 ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED,
10863 tree name ATTRIBUTE_UNUSED,
10864 tree args,
10865 int flags ATTRIBUTE_UNUSED,
10866 bool *no_add_attrs)
10867 {
10868 tree arg = TREE_VALUE (args);
10869
10870 if (TREE_CODE (arg) != STRING_CST)
10871 {
10872 error("version attribute is not a string");
10873 *no_add_attrs = true;
10874 return NULL_TREE;
10875 }
10876 return NULL_TREE;
10877 }
10878
10879 /* Target hook for c_mode_for_suffix. */
10880
10881 static enum machine_mode
10882 ia64_c_mode_for_suffix (char suffix)
10883 {
10884 if (suffix == 'q')
10885 return TFmode;
10886 if (suffix == 'w')
10887 return XFmode;
10888
10889 return VOIDmode;
10890 }
10891
10892 static enum machine_mode
10893 ia64_promote_function_mode (const_tree type,
10894 enum machine_mode mode,
10895 int *punsignedp,
10896 const_tree funtype,
10897 int for_return)
10898 {
10899 /* Special processing required for OpenVMS ... */
10900
10901 if (!TARGET_ABI_OPEN_VMS)
10902 return default_promote_function_mode(type, mode, punsignedp, funtype,
10903 for_return);
10904
10905 /* HP OpenVMS Calling Standard dated June, 2004, that describes
10906 HP OpenVMS I64 Version 8.2EFT,
10907 chapter 4 "OpenVMS I64 Conventions"
10908 section 4.7 "Procedure Linkage"
10909 subsection 4.7.5.2, "Normal Register Parameters"
10910
10911 "Unsigned integral (except unsigned 32-bit), set, and VAX floating-point
10912 values passed in registers are zero-filled; signed integral values as
10913 well as unsigned 32-bit integral values are sign-extended to 64 bits.
10914 For all other types passed in the general registers, unused bits are
10915 undefined." */
10916
10917 if (!AGGREGATE_TYPE_P (type)
10918 && GET_MODE_CLASS (mode) == MODE_INT
10919 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
10920 {
10921 if (mode == SImode)
10922 *punsignedp = 0;
10923 return DImode;
10924 }
10925 else
10926 return promote_mode (type, mode, punsignedp);
10927 }
10928
10929 static GTY(()) rtx ia64_dconst_0_5_rtx;
10930
10931 rtx
10932 ia64_dconst_0_5 (void)
10933 {
10934 if (! ia64_dconst_0_5_rtx)
10935 {
10936 REAL_VALUE_TYPE rv;
10937 real_from_string (&rv, "0.5");
10938 ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode);
10939 }
10940 return ia64_dconst_0_5_rtx;
10941 }
10942
10943 static GTY(()) rtx ia64_dconst_0_375_rtx;
10944
10945 rtx
10946 ia64_dconst_0_375 (void)
10947 {
10948 if (! ia64_dconst_0_375_rtx)
10949 {
10950 REAL_VALUE_TYPE rv;
10951 real_from_string (&rv, "0.375");
10952 ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode);
10953 }
10954 return ia64_dconst_0_375_rtx;
10955 }
10956
10957
10958 #include "gt-ia64.h"
GNU Compiler Collection
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