1 /* Definitions of target machine for GNU compiler, for Intel 80960
2 Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files may include this one and then override
26 many of the definitions that relate to assembler syntax. */
28 #define MULTILIB_DEFAULTS { "mnumerics" }
30 /* Names to predefine in the preprocessor for this target machine. */
31 #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
33 /* Name to predefine in the preprocessor for processor variations. */
34 #define CPP_SPEC "%{mic*:-D__i960\
35 %{mka:-D__i960KA}%{mkb:-D__i960KB}\
36 %{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\
38 %{msa:-D__i960SA}%{msb:-D__i960SB}\
40 %{mca:-D__i960CA}%{mcc:-D__i960CC}\
42 %{mka:-D__i960KA__ -D__i960_KA__}\
43 %{mkb:-D__i960KB__ -D__i960_KB__}\
44 %{msa:-D__i960SA__ -D__i960_SA__}\
45 %{msb:-D__i960SB__ -D__i960_SB__}\
46 %{mmc:-D__i960MC__ -D__i960_MC__}\
47 %{mca:-D__i960CA__ -D__i960_CA__}\
48 %{mcc:-D__i960CC__ -D__i960_CC__}\
49 %{mcf:-D__i960CF__ -D__i960_CF__}\
50 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
51 %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}\
52 %{mlong-double-64:-D__LONG_DOUBLE_64__}"
54 /* -mic* options make characters signed by default. */
55 /* Use #if rather than ?: because MIPS C compiler rejects ?: in
57 #if DEFAULT_SIGNED_CHAR
58 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
60 #define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
63 /* Specs for the compiler, to handle processor variations.
64 If the user gives an explicit -gstabs or -gcoff option, then do not
65 try to add an implicit one, as this will fail. */
67 "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
68 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
69 %{mcoff:%{g*:-gcoff}}\
70 %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"
72 /* Specs for the assembler, to handle processor variations.
73 For compatibility with Intel's gnu960 tool chain, pass -A options to
76 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
77 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
78 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
79 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-AKB}}}}}}}}}}}}\
80 %{mlink-relax:-linkrelax}"
82 /* Specs for the linker, to handle processor variations.
83 For compatibility with Intel's gnu960 tool chain, pass -F and -A options
86 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
87 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
88 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
89 %{mbout:-Fbout}%{mcoff:-Fcoff}\
90 %{mlink-relax:-relax}"
92 /* Specs for the libraries to link with, to handle processor variations.
93 Compatible with Intel's gnu960 tool chain. */
94 #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
95 %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
97 /* Defining the macro shows we can debug even without a frame pointer.
98 Actually, we can debug without FP. But defining the macro results in
99 that -O means FP elimination. Addressing through sp requires
100 negative offset and more one word addressing in the most cases
101 (offsets except for 0-4095 require one more word). Therefore we've
102 not defined the macro. */
103 /*#define CAN_DEBUG_WITHOUT_FP*/
105 /* Do leaf procedure and tail call optimizations for -O2 and higher. */
106 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
110 target_flags |= TARGET_FLAG_LEAFPROC; \
111 target_flags |= TARGET_FLAG_TAILCALL; \
115 /* Print subsidiary information on the compiler version in use. */
116 #define TARGET_VERSION fprintf (stderr," (intel 80960)");
118 /* Generate DBX debugging information. */
119 #define DBX_DEBUGGING_INFO
121 /* Generate SDB style debugging information. */
122 #define SDB_DEBUGGING_INFO
123 #define EXTENDED_SDB_BASIC_TYPES
125 /* Generate DBX_DEBUGGING_INFO by default. */
126 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
128 /* Redefine this to print in hex. No value adjustment is necessary
130 #define PUT_SDB_TYPE(A) \
131 fprintf (asm_out_file, "\t.type\t0x%x;", A)
133 /* Handle pragmas for compatibility with Intel's compilers. */
134 #define HANDLE_PRAGMA(GET, UNGET, NAME) process_pragma (GET, UNGET, NAME)
136 /* Run-time compilation parameters selecting different hardware subsets. */
138 /* 960 architecture with floating-point. */
139 #define TARGET_FLAG_NUMERICS 0x01
140 #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
142 /* 960 architecture with memory management. */
143 /* ??? Not used currently. */
144 #define TARGET_FLAG_PROTECTED 0x02
145 #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
147 /* The following three are mainly used to provide a little sanity checking
148 against the -mARCH flags given. The Jx series, for the purposes of
149 gcc, is a Kx with a data cache. */
151 /* Nonzero if we should generate code for the KA and similar processors.
152 No FPU, no microcode instructions. */
153 #define TARGET_FLAG_K_SERIES 0x04
154 #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
156 /* Nonzero if we should generate code for the MC processor.
157 Not really different from KB for our purposes. */
158 #define TARGET_FLAG_MC 0x08
159 #define TARGET_MC (target_flags & TARGET_FLAG_MC)
161 /* Nonzero if we should generate code for the CA processor.
162 Enables different optimization strategies. */
163 #define TARGET_FLAG_C_SERIES 0x10
164 #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
166 /* Nonzero if we should generate leaf-procedures when we find them.
167 You may not want to do this because leaf-proc entries are
168 slower when not entered via BAL - this would be true when
169 a linker not supporting the optimization is used. */
170 #define TARGET_FLAG_LEAFPROC 0x20
171 #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
173 /* Nonzero if we should perform tail-call optimizations when we find them.
174 You may not want to do this because the detection of cases where
175 this is not valid is not totally complete. */
176 #define TARGET_FLAG_TAILCALL 0x40
177 #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
179 /* Nonzero if use of a complex addressing mode is a win on this implementation.
180 Complex addressing modes are probably not worthwhile on the K-series,
181 but they definitely are on the C-series. */
182 #define TARGET_FLAG_COMPLEX_ADDR 0x80
183 #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
185 /* Align code to 8 byte boundaries for faster fetching. */
186 #define TARGET_FLAG_CODE_ALIGN 0x100
187 #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
189 /* Append branch prediction suffixes to branch opcodes. */
190 /* ??? Not used currently. */
191 #define TARGET_FLAG_BRANCH_PREDICT 0x200
192 #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
194 /* Forces prototype and return promotions. */
195 /* ??? This does not work. */
196 #define TARGET_FLAG_CLEAN_LINKAGE 0x400
197 #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
199 /* For compatibility with iC960 v3.0. */
200 #define TARGET_FLAG_IC_COMPAT3_0 0x800
201 #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
203 /* For compatibility with iC960 v2.0. */
204 #define TARGET_FLAG_IC_COMPAT2_0 0x1000
205 #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
207 /* If no unaligned accesses are to be permitted. */
208 #define TARGET_FLAG_STRICT_ALIGN 0x2000
209 #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
211 /* For compatibility with iC960 assembler. */
212 #define TARGET_FLAG_ASM_COMPAT 0x4000
213 #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
215 /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
216 alignment rules. Also, turns on STRICT_ALIGNMENT. */
217 #define TARGET_FLAG_OLD_ALIGN 0x8000
218 #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
220 /* Nonzero if long doubles are to be 64 bits. Useful for soft-float targets
221 if 80 bit long double support is missing. */
222 #define TARGET_FLAG_LONG_DOUBLE_64 0x10000
223 #define TARGET_LONG_DOUBLE_64 (target_flags & TARGET_FLAG_LONG_DOUBLE_64)
225 extern int target_flags
;
227 /* Macro to define tables used to set the flags.
228 This is a list in braces of pairs in braces,
229 each pair being { "NAME", VALUE }
230 where VALUE is the bits to set or minus the bits to clear.
231 An empty string NAME is used to identify the default VALUE. */
233 /* ??? Not all ten of these architecture variations actually exist, but I
234 am not sure which are real and which aren't. */
236 #define TARGET_SWITCHES \
237 { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
238 "Generate SA code"}, \
239 {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
240 TARGET_FLAG_COMPLEX_ADDR), \
241 "Generate SB code"}, \
242 /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
243 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
244 "Generate SC code"}, */ \
245 {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
246 "Generate KA code"}, \
247 {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
248 TARGET_FLAG_COMPLEX_ADDR), \
249 "Generate KB code"}, \
250 /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
251 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
252 "Generate KC code"}, */ \
253 {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
254 "Generate JA code"}, \
255 {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
256 "Generate JD code"}, \
257 {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
258 TARGET_FLAG_COMPLEX_ADDR), \
259 "Generate JF code"}, \
260 {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
261 "generate RP code"}, \
262 {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
263 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
264 "Generate MC code"}, \
265 {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
266 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
267 "Generate CA code"}, \
268 /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES| \
269 TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\
270 "Generate CB code"}, \
271 {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
272 TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
273 TARGET_FLAG_CODE_ALIGN), \
274 "Generate CC code"}, */ \
275 {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
276 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
277 "Generate CF code"}, \
278 {"numerics", (TARGET_FLAG_NUMERICS), \
279 "Use hardware floating point instructions"}, \
280 {"soft-float", -(TARGET_FLAG_NUMERICS), \
281 "Use software floating point"}, \
282 {"leaf-procedures", TARGET_FLAG_LEAFPROC, \
283 "Use alternate leaf function entries"}, \
284 {"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC), \
285 "Do not use alternate leaf function entries"}, \
286 {"tail-call", TARGET_FLAG_TAILCALL, \
287 "Perform tail call optimization"}, \
288 {"no-tail-call", -(TARGET_FLAG_TAILCALL), \
289 "Do not perform tail call optimization"}, \
290 {"complex-addr", TARGET_FLAG_COMPLEX_ADDR, \
291 "Use complex addressing modes"}, \
292 {"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR), \
293 "Do not use complex addressing modes"}, \
294 {"code-align", TARGET_FLAG_CODE_ALIGN, \
295 "Align code to 8 byte boundary"}, \
296 {"no-code-align", -(TARGET_FLAG_CODE_ALIGN), \
297 "Do not align code to 8 byte boundary"}, \
298 /* {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE), \
299 "Force use of prototypes"}, \
300 {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE), \
301 "Do not force use of prototypes"}, */ \
302 {"ic-compat", TARGET_FLAG_IC_COMPAT2_0, \
303 "Enable compatibility with iC960 v2.0"}, \
304 {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0, \
305 "Enable compatibility with iC960 v2.0"}, \
306 {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0, \
307 "Enable compatibility with iC960 v3.0"}, \
308 {"asm-compat", TARGET_FLAG_ASM_COMPAT, \
309 "Enable compatibility with ic960 assembler"}, \
310 {"intel-asm", TARGET_FLAG_ASM_COMPAT, \
311 "Enable compatibility with ic960 assembler"}, \
312 {"strict-align", TARGET_FLAG_STRICT_ALIGN, \
313 "Do not permit unaligned accesses"}, \
314 {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN), \
315 "Permit unaligned accesses"}, \
316 {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
317 "Layout types like Intel's v1.3 gcc"}, \
318 {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
319 "Do not layout types like Intel's v1.3 gcc"}, \
320 {"long-double-64", TARGET_FLAG_LONG_DOUBLE_64, \
321 "Use 64 bit long doubles"}, \
323 "Enable linker relaxation"}, \
324 {"no-link-relax", 0, \
325 "Do not enable linker relaxation"}, \
327 { "", TARGET_DEFAULT, \
330 /* This are meant to be redefined in the host dependent files */
331 #define SUBTARGET_SWITCHES
333 /* Override conflicting target switch options.
334 Doesn't actually detect if more than one -mARCH option is given, but
335 does handle the case of two blatantly conflicting -mARCH options. */
336 #define OVERRIDE_OPTIONS \
338 if (TARGET_K_SERIES && TARGET_C_SERIES) \
340 warning ("conflicting architectures defined - using C series"); \
341 target_flags &= ~TARGET_FLAG_K_SERIES; \
343 if (TARGET_K_SERIES && TARGET_MC) \
345 warning ("conflicting architectures defined - using K series"); \
346 target_flags &= ~TARGET_FLAG_MC; \
348 if (TARGET_C_SERIES && TARGET_MC) \
350 warning ("conflicting architectures defined - using C series");\
351 target_flags &= ~TARGET_FLAG_MC; \
353 if (TARGET_IC_COMPAT3_0) \
355 flag_short_enums = 1; \
356 flag_signed_char = 1; \
357 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
358 if (TARGET_IC_COMPAT2_0) \
360 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0"); \
361 target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
364 if (TARGET_IC_COMPAT2_0) \
366 flag_signed_char = 1; \
367 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
369 /* ??? See the LONG_DOUBLE_TYPE_SIZE definition below. */ \
370 if (TARGET_LONG_DOUBLE_64) \
371 warning ("The -mlong-double-64 option does not work yet.");\
372 i960_initialize (); \
375 /* Don't enable anything by default. The user is expected to supply a -mARCH
376 option. If none is given, then -mka is added by CC1_SPEC. */
377 #define TARGET_DEFAULT 0
379 /* Target machine storage layout. */
381 /* Define for cross-compilation from a host with a different float format
382 or endianness, as well as to support 80 bit long doubles on the i960. */
383 #define REAL_ARITHMETIC
385 /* Define this if most significant bit is lowest numbered
386 in instructions that operate on numbered bit-fields. */
387 #define BITS_BIG_ENDIAN 0
389 /* Define this if most significant byte of a word is the lowest numbered.
390 The i960 case be either big endian or little endian. We only support
391 little endian, which is the most common. */
392 #define BYTES_BIG_ENDIAN 0
394 /* Define this if most significant word of a multiword number is lowest
396 #define WORDS_BIG_ENDIAN 0
398 /* Number of bits in an addressable storage unit. */
399 #define BITS_PER_UNIT 8
401 /* Bitfields cannot cross word boundaries. */
402 #define BITFIELD_NBYTES_LIMITED 1
404 /* Width in bits of a "word", which is the contents of a machine register.
405 Note that this is not necessarily the width of data type `int';
406 if using 16-bit ints on a 68000, this would still be 32.
407 But on a machine with 16-bit registers, this would be 16. */
408 #define BITS_PER_WORD 32
410 /* Width of a word, in units (bytes). */
411 #define UNITS_PER_WORD 4
413 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
414 #define POINTER_SIZE 32
416 /* Width in bits of a long double. Define to 96, and let
417 ROUND_TYPE_ALIGN adjust the alignment for speed. */
418 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)
420 /* ??? This must be a constant, because real.c and real.h test it with #if. */
421 #undef LONG_DOUBLE_TYPE_SIZE
422 #define LONG_DOUBLE_TYPE_SIZE 96
424 /* Define this to set long double type size to use in libgcc2.c, which can
425 not depend on target_flags. */
426 #if defined(__LONG_DOUBLE_64__)
427 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
429 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
432 /* Allocation boundary (in *bits*) for storing pointers in memory. */
433 #define POINTER_BOUNDARY 32
435 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
436 #define PARM_BOUNDARY 32
438 /* Boundary (in *bits*) on which stack pointer should be aligned. */
439 #define STACK_BOUNDARY 128
441 /* Allocation boundary (in *bits*) for the code of a function. */
442 #define FUNCTION_BOUNDARY 128
444 /* Alignment of field after `int : 0' in a structure. */
445 #define EMPTY_FIELD_BOUNDARY 32
447 /* This makes zero-length anonymous fields lay the next field
448 at a word boundary. It also makes the whole struct have
449 at least word alignment if there are any bitfields at all. */
450 #define PCC_BITFIELD_TYPE_MATTERS 1
452 /* Every structure's size must be a multiple of this. */
453 #define STRUCTURE_SIZE_BOUNDARY 8
455 /* No data type wants to be aligned rounder than this.
456 Extended precision floats gets 4-word alignment. */
457 #define BIGGEST_ALIGNMENT 128
459 /* Define this if move instructions will actually fail to work
460 when given unaligned data.
461 80960 will work even with unaligned data, but it is slow. */
462 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
464 /* Specify alignment for string literals (which might be higher than the
465 base type's minimal alignment requirement. This allows strings to be
466 aligned on word boundaries, and optimizes calls to the str* and mem*
467 library functions. */
468 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
469 (TREE_CODE (EXP) == STRING_CST \
470 && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
471 ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
474 /* Make XFmode floating point quantities be 128 bit aligned. */
475 #define DATA_ALIGNMENT(TYPE, ALIGN) \
476 (TREE_CODE (TYPE) == ARRAY_TYPE \
477 && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \
478 && (ALIGN) < 128 ? 128 : (ALIGN))
480 /* Macros to determine size of aggregates (structures and unions
481 in C). Normally, these may be defined to simply return the maximum
482 alignment and simple rounded-up size, but on some machines (like
483 the i960), the total size of a structure is based on a non-trivial
486 #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
487 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
488 ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \
489 : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE) \
490 && TREE_CODE (TYPE) == RECORD_TYPE) \
491 ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
492 : MAX ((COMPUTED), (SPECIFIED))))
494 #define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \
495 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
496 ? bitsize_int (128) : round_up (COMPUTED, SPECIFIED))
497 #define ROUND_TYPE_SIZE_UNIT(TYPE, COMPUTED, SPECIFIED) \
498 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
499 ? bitsize_int (16) : round_up (COMPUTED, SPECIFIED))
502 /* Standard register usage. */
504 /* Number of actual hardware registers.
505 The hardware registers are assigned numbers for the compiler
506 from 0 to just below FIRST_PSEUDO_REGISTER.
507 All registers that the compiler knows about must be given numbers,
508 even those that are not normally considered general registers.
510 Registers 0-15 are the global registers (g0-g15).
511 Registers 16-31 are the local registers (r0-r15).
512 Register 32-35 are the fp registers (fp0-fp3).
513 Register 36 is the condition code register.
514 Register 37 is unused. */
516 #define FIRST_PSEUDO_REGISTER 38
518 /* 1 for registers that have pervasive standard uses and are not available
519 for the register allocator. On 80960, this includes the frame pointer
520 (g15), the previous FP (r0), the stack pointer (r1), the return
521 instruction pointer (r2), and the argument pointer (g14). */
522 #define FIXED_REGISTERS \
523 {0, 0, 0, 0, 0, 0, 0, 0, \
524 0, 0, 0, 0, 0, 0, 1, 1, \
525 1, 1, 1, 0, 0, 0, 0, 0, \
526 0, 0, 0, 0, 0, 0, 0, 0, \
529 /* 1 for registers not available across function calls.
530 These must include the FIXED_REGISTERS and also any
531 registers that can be used without being saved.
532 The latter must include the registers where values are returned
533 and the register where structure-value addresses are passed.
534 Aside from that, you can include as many other registers as you like. */
536 /* On the 80960, note that:
537 g0..g3 are used for return values,
538 g0..g7 may always be used for parameters,
539 g8..g11 may be used for parameters, but are preserved if they aren't,
540 g12 is the static chain if needed, otherwise is preserved
541 g13 is the struct return ptr if used, or temp, but may be trashed,
542 g14 is the leaf return ptr or the arg block ptr otherwise zero,
543 must be reset to zero before returning if it was used,
544 g15 is the frame pointer,
545 r0 is the previous FP,
546 r1 is the stack pointer,
547 r2 is the return instruction pointer,
548 r3-r15 are always available,
549 r3 is clobbered by calls in functions that use the arg pointer
550 r4-r11 may be clobbered by the mcount call when profiling
551 r4-r15 if otherwise unused may be used for preserving global registers
552 fp0..fp3 are never available. */
553 #define CALL_USED_REGISTERS \
554 {1, 1, 1, 1, 1, 1, 1, 1, \
555 0, 0, 0, 0, 0, 1, 1, 1, \
556 1, 1, 1, 0, 0, 0, 0, 0, \
557 0, 0, 0, 0, 0, 0, 0, 0, \
560 /* If no fp unit, make all of the fp registers fixed so that they can't
562 #define CONDITIONAL_REGISTER_USAGE \
563 if (! TARGET_NUMERICS) { \
564 fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
567 /* Return number of consecutive hard regs needed starting at reg REGNO
568 to hold something of mode MODE.
569 This is ordinarily the length in words of a value of mode MODE
570 but can be less for certain modes in special long registers.
572 On 80960, ordinary registers hold 32 bits worth, but can be ganged
573 together to hold double or extended precision floating point numbers,
574 and the floating point registers hold any size floating point number */
575 #define HARD_REGNO_NREGS(REGNO, MODE) \
577 ? (((MODE) == VOIDmode) \
578 ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
579 : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
581 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
582 On 80960, the cpu registers can hold any mode but the float registers
583 can only hold SFmode, DFmode, or XFmode. */
584 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
586 /* Value is 1 if it is a good idea to tie two pseudo registers
587 when one has mode MODE1 and one has mode MODE2.
588 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
589 for any hard reg, then this must be 0 for correct output. */
591 #define MODES_TIEABLE_P(MODE1, MODE2) \
592 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
594 /* Specify the registers used for certain standard purposes.
595 The values of these macros are register numbers. */
597 /* 80960 pc isn't overloaded on a register that the compiler knows about. */
598 /* #define PC_REGNUM */
600 /* Register to use for pushing function arguments. */
601 #define STACK_POINTER_REGNUM 17
603 /* Actual top-of-stack address is same as
604 the contents of the stack pointer register. */
605 #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
607 /* Base register for access to local variables of the function. */
608 #define FRAME_POINTER_REGNUM 15
610 /* Value should be nonzero if functions must have frame pointers.
611 Zero means the frame pointer need not be set up (and parms
612 may be accessed via the stack pointer) in functions that seem suitable.
613 This is computed in `reload', in reload1.c. */
614 /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
615 fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
616 caused this to fail. */
617 #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
619 /* Definitions for register eliminations.
621 This is an array of structures. Each structure initializes one pair
622 of eliminable registers. The "from" register number is given first,
623 followed by "to". Eliminations of the same "from" register are listed
624 in order of preference.. */
626 #define ELIMINABLE_REGS {{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
628 /* Given FROM and TO register numbers, say whether this elimination is allowed.
629 Frame pointer elimination is automatically handled. */
630 #define CAN_ELIMINATE(FROM, TO) 1
632 /* Define the offset between two registers, one to be eliminated, and
633 the other its replacement, at the start of a routine.
635 Since the stack grows upward on the i960, this must be a negative number.
636 This includes the 64 byte hardware register save area and the size of
639 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
640 do { (OFFSET) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
642 /* Base register for access to arguments of the function. */
643 #define ARG_POINTER_REGNUM 14
645 /* Register in which static-chain is passed to a function.
646 On i960, we use g12. We can't use any local register, because we need
647 a register that can be set before a call or before a jump. */
648 #define STATIC_CHAIN_REGNUM 12
650 /* Functions which return large structures get the address
651 to place the wanted value at in g13. */
653 #define STRUCT_VALUE_REGNUM 13
655 /* The order in which to allocate registers. */
657 #define REG_ALLOC_ORDER \
658 { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
659 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
660 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
661 11, 12, /* g11, g12 */ \
662 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
663 /* We can't actually allocate these. */ \
664 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
666 /* Define the classes of registers for register constraints in the
667 machine description. Also define ranges of constants.
669 One of the classes must always be named ALL_REGS and include all hard regs.
670 If there is more than one class, another class must be named NO_REGS
671 and contain no registers.
673 The name GENERAL_REGS must be the name of a class (or an alias for
674 another name such as ALL_REGS). This is the class of registers
675 that is allowed by "g" or "r" in a register constraint.
676 Also, registers outside this class are allocated only when
677 instructions express preferences for them.
679 The classes must be numbered in nondecreasing order; that is,
680 a larger-numbered class must never be contained completely
681 in a smaller-numbered class.
683 For any two classes, it is very desirable that there be another
684 class that represents their union. */
686 /* The 80960 has four kinds of registers, global, local, floating point,
687 and condition code. The cc register is never allocated, so no class
688 needs to be defined for it. */
690 enum reg_class
{ NO_REGS
, GLOBAL_REGS
, LOCAL_REGS
, LOCAL_OR_GLOBAL_REGS
,
691 FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
693 /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
695 #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
697 #define N_REG_CLASSES (int) LIM_REG_CLASSES
699 /* Give names of register classes as strings for dump file. */
701 #define REG_CLASS_NAMES \
702 { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
703 "FP_REGS", "ALL_REGS" }
705 /* Define which registers fit in which classes.
706 This is an initializer for a vector of HARD_REG_SET
707 of length N_REG_CLASSES. */
709 #define REG_CLASS_CONTENTS \
710 { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
712 /* The same information, inverted:
713 Return the class number of the smallest class containing
714 reg number REGNO. This could be a conditional expression
715 or could index an array. */
717 #define REGNO_REG_CLASS(REGNO) \
718 ((REGNO) < 16 ? GLOBAL_REGS \
719 : (REGNO) < 32 ? LOCAL_REGS \
720 : (REGNO) < 36 ? FP_REGS \
723 /* The class value for index registers, and the one for base regs.
724 There is currently no difference between base and index registers on the
725 i960, but this distinction may one day be useful. */
726 #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
727 #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
729 /* Get reg_class from a letter such as appears in the machine description.
730 'f' is a floating point register (fp0..fp3)
731 'l' is a local register (r0-r15)
732 'b' is a global register (g0-g15)
733 'd' is any local or global register
734 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
735 /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
736 the same thing, since 'r' may include the fp registers. */
737 #define REG_CLASS_FROM_LETTER(C) \
738 (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
739 (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
741 /* The letters I, J, K, L and M in a register constraint string
742 can be used to stand for particular ranges of immediate operands.
743 This macro defines what the ranges are.
744 C is the letter, and VALUE is a constant value.
745 Return 1 if VALUE is in the range specified by C.
748 'I' is used for literal values 0..31
752 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
753 ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
754 : (C) == 'J' ? ((VALUE) == 0) \
755 : (C) == 'K' ? ((VALUE) >= -31 && (VALUE) <= 0) \
756 : (C) == 'M' ? ((VALUE) >= -32 && (VALUE) <= 0) \
759 /* Similar, but for floating constants, and defining letters G and H.
760 Here VALUE is the CONST_DOUBLE rtx itself.
761 For the 80960, G is 0.0 and H is 1.0. */
763 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
764 ((TARGET_NUMERICS) && \
765 (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
766 || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE))))))
768 /* Given an rtx X being reloaded into a reg required to be
769 in class CLASS, return the class of reg to actually use.
770 In general this is just CLASS; but on some machines
771 in some cases it is preferable to use a more restrictive class. */
773 /* On 960, can't load constant into floating-point reg except
776 Any hard reg is ok as a src operand of a reload insn. */
778 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
779 (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
781 : ((CLASS) == FP_REGS && CONSTANT_P (X) \
782 && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
783 && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
785 : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
787 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
788 secondary_reload_class (CLASS, MODE, IN)
790 /* Return the maximum number of consecutive registers
791 needed to represent mode MODE in a register of class CLASS. */
792 /* On 80960, this is the size of MODE in words,
793 except in the FP regs, where a single reg is always enough. */
794 #define CLASS_MAX_NREGS(CLASS, MODE) \
795 ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
797 /* Stack layout; function entry, exit and calling. */
799 /* Define this if pushing a word on the stack
800 makes the stack pointer a smaller address. */
801 /* #define STACK_GROWS_DOWNWARD */
803 /* Define this if the nominal address of the stack frame
804 is at the high-address end of the local variables;
805 that is, each additional local variable allocated
806 goes at a more negative offset in the frame. */
807 /* #define FRAME_GROWS_DOWNWARD */
809 /* Offset within stack frame to start allocating local variables at.
810 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
811 first local allocated. Otherwise, it is the offset to the BEGINNING
812 of the first local allocated.
814 The i960 has a 64 byte register save area, plus possibly some extra
815 bytes allocated for varargs functions. */
816 #define STARTING_FRAME_OFFSET 64
818 /* If we generate an insn to push BYTES bytes,
819 this says how many the stack pointer really advances by.
820 On 80960, don't define this because there are no push insns. */
821 /* #define PUSH_ROUNDING(BYTES) BYTES */
823 /* Offset of first parameter from the argument pointer register value. */
824 #define FIRST_PARM_OFFSET(FNDECL) 0
826 /* When a parameter is passed in a register, no stack space is
827 allocated for it. However, when args are passed in the
828 stack, space is allocated for every register parameter. */
829 #define MAYBE_REG_PARM_STACK_SPACE 48
830 #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
831 i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
832 #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
833 #define OUTGOING_REG_PARM_STACK_SPACE
835 /* Keep the stack pointer constant throughout the function. */
836 #define ACCUMULATE_OUTGOING_ARGS 1
838 /* Value is 1 if returning from a function call automatically
839 pops the arguments described by the number-of-args field in the call.
840 FUNDECL is the declaration node of the function (as a tree),
841 FUNTYPE is the data type of the function (as a tree),
842 or for a library call it is an identifier node for the subroutine name. */
844 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
846 /* Define how to find the value returned by a library function
847 assuming the value has mode MODE. */
849 #define LIBCALL_VALUE(MODE) gen_rtx_REG ((MODE), 0)
851 /* 1 if N is a possible register number for a function value
852 as seen by the caller.
853 On 80960, returns are in g0..g3 */
855 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
857 /* 1 if N is a possible register number for function argument passing.
858 On 80960, parameters are passed in g0..g11 */
860 #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
862 /* Perform any needed actions needed for a function that is receiving a
863 variable number of arguments.
867 MODE and TYPE are the mode and type of the current parameter.
869 PRETEND_SIZE is a variable that should be set to the amount of stack
870 that must be pushed by the prolog to pretend that our caller pushed
873 Normally, this macro will push all remaining incoming registers on the
874 stack and set PRETEND_SIZE to the length of the registers pushed. */
876 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
877 i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
879 /* Define the `__builtin_va_list' type for the ABI. */
880 #define BUILD_VA_LIST_TYPE(VALIST) \
881 (VALIST) = i960_build_va_list ()
883 /* Implement `va_start' for varargs and stdarg. */
884 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
885 i960_va_start (stdarg, valist, nextarg)
887 /* Implement `va_arg'. */
888 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
889 i960_va_arg (valist, type)
891 /* Define a data type for recording info about an argument list
892 during the scan of that argument list. This data type should
893 hold all necessary information about the function itself
894 and about the args processed so far, enough to enable macros
895 such as FUNCTION_ARG to determine where the next arg should go.
897 On 80960, this is two integers, which count the number of register
898 parameters and the number of stack parameters seen so far. */
900 struct cum_args
{ int ca_nregparms
; int ca_nstackparms
; };
902 #define CUMULATIVE_ARGS struct cum_args
904 /* Define the number of registers that can hold parameters.
905 This macro is used only in macro definitions below and/or i960.c. */
906 #define NPARM_REGS 12
908 /* Define how to round to the next parameter boundary.
909 This macro is used only in macro definitions below and/or i960.c. */
910 #define ROUND_PARM(X, MULTIPLE_OF) \
911 ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
913 /* Initialize a variable CUM of type CUMULATIVE_ARGS
914 for a call to a function whose data type is FNTYPE.
915 For a library call, FNTYPE is 0.
917 On 80960, the offset always starts at 0; the first parm reg is g0. */
919 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
920 ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
922 /* Update the data in CUM to advance over an argument
923 of mode MODE and data type TYPE.
924 CUM should be advanced to align with the data type accessed and
925 also the size of that data type in # of regs.
926 (TYPE is null for libcalls where that information may not be available.) */
928 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
929 i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
931 /* Indicate the alignment boundary for an argument of the specified mode and
933 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
935 ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
937 : TYPE_ALIGN (TYPE)) \
938 : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
940 : GET_MODE_ALIGNMENT (MODE)))
942 /* Determine where to put an argument to a function.
943 Value is zero to push the argument on the stack,
944 or a hard register in which to store the argument.
946 MODE is the argument's machine mode.
947 TYPE is the data type of the argument (as a tree).
948 This is null for libcalls where that information may
950 CUM is a variable of type CUMULATIVE_ARGS which gives info about
951 the preceding args and about the function being called.
952 NAMED is nonzero if this argument is a named parameter
953 (otherwise it is an extra parameter matching an ellipsis). */
955 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
956 i960_function_arg(&CUM, MODE, TYPE, NAMED)
958 /* Define how to find the value returned by a function.
959 VALTYPE is the data type of the value (as a tree).
960 If the precise function being called is known, FUNC is its FUNCTION_DECL;
961 otherwise, FUNC is 0. */
963 #define FUNCTION_VALUE(TYPE, FUNC) \
964 gen_rtx_REG (TYPE_MODE (TYPE), 0)
966 /* Force aggregates and objects larger than 16 bytes to be returned in memory,
967 since we only have 4 registers available for return values. */
969 #define RETURN_IN_MEMORY(TYPE) \
970 (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
972 /* Don't default to pcc-struct-return, because we have already specified
973 exactly how to return structures in the RETURN_IN_MEMORY macro. */
974 #define DEFAULT_PCC_STRUCT_RETURN 0
976 /* For an arg passed partly in registers and partly in memory,
977 this is the number of registers used.
978 This never happens on 80960. */
980 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
982 /* Output the label for a function definition.
983 This handles leaf functions and a few other things for the i960. */
985 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
986 i960_function_name_declare (FILE, NAME, DECL)
988 /* This macro generates the assembly code for function entry.
989 FILE is a stdio stream to output the code to.
990 SIZE is an int: how many units of temporary storage to allocate.
991 Refer to the array `regs_ever_live' to determine which registers
992 to save; `regs_ever_live[I]' is nonzero if register number I
993 is ever used in the function. This macro is responsible for
994 knowing which registers should not be saved even if used. */
996 #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
998 /* Output assembler code to FILE to increment profiler label # LABELNO
999 for profiling a function entry. */
1001 #define FUNCTION_PROFILER(FILE, LABELNO) \
1002 output_function_profiler ((FILE), (LABELNO));
1004 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1005 the stack pointer does not matter. The value is tested only in
1006 functions that have frame pointers.
1007 No definition is equivalent to always zero. */
1009 #define EXIT_IGNORE_STACK 1
1011 /* This macro generates the assembly code for function exit,
1012 on machines that need it. If FUNCTION_EPILOGUE is not defined
1013 then individual return instructions are generated for each
1014 return statement. Args are same as for FUNCTION_PROLOGUE.
1016 The function epilogue should not depend on the current stack pointer!
1017 It should use the frame pointer only. This is mandatory because
1018 of alloca; we also take advantage of it to omit stack adjustments
1019 before returning. */
1021 #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
1023 /* Addressing modes, and classification of registers for them. */
1025 /* #define HAVE_POST_INCREMENT 0 */
1026 /* #define HAVE_POST_DECREMENT 0 */
1028 /* #define HAVE_PRE_DECREMENT 0 */
1029 /* #define HAVE_PRE_INCREMENT 0 */
1031 /* Macros to check register numbers against specific register classes. */
1033 /* These assume that REGNO is a hard or pseudo reg number.
1034 They give nonzero only if REGNO is a hard reg of the suitable class
1035 or a pseudo reg currently allocated to a suitable hard reg.
1036 Since they use reg_renumber, they are safe only once reg_renumber
1037 has been allocated, which happens in local-alloc.c. */
1039 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1040 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
1041 #define REGNO_OK_FOR_BASE_P(REGNO) \
1042 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
1043 #define REGNO_OK_FOR_FP_P(REGNO) \
1044 ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
1046 /* Now macros that check whether X is a register and also,
1047 strictly, whether it is in a specified class.
1049 These macros are specific to the 960, and may be used only
1050 in code for printing assembler insns and in conditions for
1051 define_optimization. */
1053 /* 1 if X is an fp register. */
1055 #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
1057 /* Maximum number of registers that can appear in a valid memory address. */
1058 #define MAX_REGS_PER_ADDRESS 2
1060 #define CONSTANT_ADDRESS_P(X) \
1061 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1062 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1063 || GET_CODE (X) == HIGH)
1065 /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
1066 is a legitimate general operand.
1067 It is given that X satisfies CONSTANT_P.
1069 Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0.
1071 ??? This probably should be defined to 1. */
1073 #define LEGITIMATE_CONSTANT_P(X) \
1074 ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X)))
1076 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1077 and check its validity for a certain class.
1078 We have two alternate definitions for each of them.
1079 The usual definition accepts all pseudo regs; the other rejects
1080 them unless they have been allocated suitable hard regs.
1081 The symbol REG_OK_STRICT causes the latter definition to be used.
1083 Most source files want to accept pseudo regs in the hope that
1084 they will get allocated to the class that the insn wants them to be in.
1085 Source files for reload pass need to be strict.
1086 After reload, it makes no difference, since pseudo regs have
1087 been eliminated by then. */
1089 #ifndef REG_OK_STRICT
1091 /* Nonzero if X is a hard reg that can be used as an index
1092 or if it is a pseudo reg. */
1093 #define REG_OK_FOR_INDEX_P(X) \
1094 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1095 /* Nonzero if X is a hard reg that can be used as a base reg
1096 or if it is a pseudo reg. */
1097 #define REG_OK_FOR_BASE_P(X) \
1098 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1100 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1101 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1105 /* Nonzero if X is a hard reg that can be used as an index. */
1106 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1107 /* Nonzero if X is a hard reg that can be used as a base reg. */
1108 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1112 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1113 that is a valid memory address for an instruction.
1114 The MODE argument is the machine mode for the MEM expression
1115 that wants to use this address.
1117 On 80960, legitimate addresses are:
1119 disp (12 or 32 bit) ld foo,r0
1120 base + index ld (g0)[g1*1],r0
1121 base + displ ld 0xf00(g0),r0
1122 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1123 index*scale + base ld (g0)[g1*4],r0
1124 index*scale + displ ld 0xf00[g1*4],r0
1125 index*scale ld [g1*4],r0
1126 index + base + displ ld 0xf00(g0)[g1*1],r0
1128 In each case, scale can be 1, 2, 4, 8, or 16. */
1130 /* Returns 1 if the scale factor of an index term is valid. */
1131 #define SCALE_TERM_P(X) \
1132 (GET_CODE (X) == CONST_INT \
1133 && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
1134 || INTVAL(X) == 8 || INTVAL (X) == 16))
1137 #ifdef REG_OK_STRICT
1138 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1139 { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
1141 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1142 { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
1145 /* Try machine-dependent ways of modifying an illegitimate address
1146 to be legitimate. If we find one, return the new, valid address.
1147 This macro is used in only one place: `memory_address' in explow.c.
1149 OLDX is the address as it was before break_out_memory_refs was called.
1150 In some cases it is useful to look at this to decide what needs to be done.
1152 MODE and WIN are passed so that this macro can use
1153 GO_IF_LEGITIMATE_ADDRESS.
1155 It is always safe for this macro to do nothing. It exists to recognize
1156 opportunities to optimize the output. */
1158 /* On 80960, convert non-canonical addresses to canonical form. */
1160 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1161 { rtx orig_x = (X); \
1162 (X) = legitimize_address (X, OLDX, MODE); \
1163 if ((X) != orig_x && memory_address_p (MODE, X)) \
1166 /* Go to LABEL if ADDR (a legitimate address expression)
1167 has an effect that depends on the machine mode it is used for.
1168 On the 960 this is never true. */
1170 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1172 /* Specify the machine mode that this machine uses
1173 for the index in the tablejump instruction. */
1174 #define CASE_VECTOR_MODE SImode
1176 /* Define as C expression which evaluates to nonzero if the tablejump
1177 instruction expects the table to contain offsets from the address of the
1179 Do not define this if the table should contain absolute addresses. */
1180 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1182 /* Specify the tree operation to be used to convert reals to integers. */
1183 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1185 /* This is the kind of divide that is easiest to do in the general case. */
1186 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1188 /* Define this as 1 if `char' should by default be signed; else as 0. */
1189 #define DEFAULT_SIGNED_CHAR 0
1191 /* Allow and ignore #sccs directives. */
1192 #define SCCS_DIRECTIVE
1194 /* Max number of bytes we can move from memory to memory
1195 in one reasonably fast instruction. */
1198 /* Define if operations between registers always perform the operation
1199 on the full register even if a narrower mode is specified. */
1200 #define WORD_REGISTER_OPERATIONS
1202 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1203 will either zero-extend or sign-extend. The value of this macro should
1204 be the code that says which one of the two operations is implicitly
1205 done, NIL if none. */
1206 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1208 /* Nonzero if access to memory by bytes is no faster than for words.
1209 Value changed to 1 after reports of poor bitfield code with g++.
1210 Indications are that code is usually as good, sometimes better. */
1212 #define SLOW_BYTE_ACCESS 1
1214 /* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the
1215 change in SLOW_BYTE_ACCESS would have changed it to 4. */
1217 #define BOOL_TYPE_SIZE CHAR_TYPE_SIZE
1219 /* We assume that the store-condition-codes instructions store 0 for false
1220 and some other value for true. This is the value stored for true. */
1222 #define STORE_FLAG_VALUE 1
1224 /* Define this to be nonzero if shift instructions ignore all but the low-order
1226 #define SHIFT_COUNT_TRUNCATED 0
1228 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1229 is done just by pretending it is already truncated. */
1230 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1232 /* Specify the machine mode that pointers have.
1233 After generation of rtl, the compiler makes no further distinction
1234 between pointers and any other objects of this machine mode. */
1235 #define Pmode SImode
1237 /* Specify the widest mode that BLKmode objects can be promoted to */
1238 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1240 /* These global variables are used to pass information between
1241 cc setter and cc user at insn emit time. */
1243 extern struct rtx_def
*i960_compare_op0
, *i960_compare_op1
;
1245 /* Add any extra modes needed to represent the condition code.
1247 Also, signed and unsigned comparisons are distinguished, as
1248 are operations which are compatible with chkbit insns. */
1249 #define EXTRA_CC_MODES \
1250 CC(CC_UNSmode, "CC_UNS") \
1251 CC(CC_CHKmode, "CC_CHK")
1253 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1254 return the mode to be used for the comparison. For floating-point, CCFPmode
1255 should be used. CC_NOOVmode should be used when the first operand is a
1256 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1258 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1260 /* A function address in a call instruction is a byte address
1261 (for indexing purposes) so give the MEM rtx a byte's mode. */
1262 #define FUNCTION_MODE SImode
1264 /* Define this if addresses of constant functions
1265 shouldn't be put through pseudo regs where they can be cse'd.
1266 Desirable on machines where ordinary constants are expensive
1267 but a CALL with constant address is cheap. */
1268 #define NO_FUNCTION_CSE
1270 /* Use memcpy, etc. instead of bcopy. */
1273 #define TARGET_MEM_FUNCTIONS 1
1276 /* Compute the cost of computing a constant rtl expression RTX
1277 whose rtx-code is CODE. The body of this macro is a portion
1278 of a switch statement. If the code is computed here,
1279 return it with a return statement. Otherwise, break from the switch. */
1281 /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1282 that can be non-ldconst operands in rare cases are cost 1. Other constants
1283 have higher costs. */
1285 /* Must check for OUTER_CODE of SET for power2_operand, because
1286 reload_cse_move2add calls us with OUTER_CODE of PLUS to decide when
1287 to replace set with add. */
1289 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1291 if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1292 || (OUTER_CODE == SET && power2_operand (RTX, VOIDmode))) \
1294 else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1299 return (TARGET_C_SERIES ? 6 : 8); \
1300 case CONST_DOUBLE: \
1301 if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1302 || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1306 /* The i960 offers addressing modes which are "as cheap as a register".
1307 See i960.c (or gcc.texinfo) for details. */
1309 #define ADDRESS_COST(RTX) \
1310 (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1312 /* Control the assembler format that we output. */
1314 /* Output at beginning of assembler file. */
1316 #define ASM_FILE_START(file)
1318 /* Output to assembler file text saying following lines
1319 may contain character constants, extra white space, comments, etc. */
1321 #define ASM_APP_ON ""
1323 /* Output to assembler file text saying following lines
1324 no longer contain unusual constructs. */
1326 #define ASM_APP_OFF ""
1328 /* Output before read-only data. */
1330 #define TEXT_SECTION_ASM_OP ".text"
1332 /* Output before writable data. */
1334 #define DATA_SECTION_ASM_OP ".data"
1336 /* How to refer to registers in assembler output.
1337 This sequence is indexed by compiler's hard-register-number (see above). */
1339 #define REGISTER_NAMES { \
1340 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1341 "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1342 "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1343 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1344 "fp0","fp1","fp2", "fp3", "cc", "fake" }
1346 /* How to renumber registers for dbx and gdb.
1347 In the 960 encoding, g0..g15 are registers 16..31. */
1349 #define DBX_REGISTER_NUMBER(REGNO) \
1350 (((REGNO) < 16) ? (REGNO) + 16 \
1351 : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1353 /* Don't emit dbx records longer than this. This is an arbitrary value. */
1354 #define DBX_CONTIN_LENGTH 1500
1356 /* This is how to output a note to DBX telling it the line number
1357 to which the following sequence of instructions corresponds. */
1359 #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1360 { if (write_symbols == SDB_DEBUG) { \
1361 fprintf ((FILE), "\t.ln %d\n", \
1362 (sdb_begin_function_line \
1363 ? (LINE) - sdb_begin_function_line : 1)); \
1364 } else if (write_symbols == DBX_DEBUG) { \
1365 fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1368 /* This is how to output the definition of a user-level label named NAME,
1369 such as the label on a static function or variable NAME. */
1371 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1372 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1374 /* This is how to output a command to make the user-level label named NAME
1375 defined for reference from other files. */
1377 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1378 { fputs ("\t.globl ", FILE); \
1379 assemble_name (FILE, NAME); \
1380 fputs ("\n", FILE); }
1382 /* The prefix to add to user-visible assembler symbols. */
1384 #define USER_LABEL_PREFIX "_"
1386 /* This is how to output an internal numbered label where
1387 PREFIX is the class of label and NUM is the number within the class. */
1389 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1390 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1392 /* This is how to store into the string LABEL
1393 the symbol_ref name of an internal numbered label where
1394 PREFIX is the class of label and NUM is the number within the class.
1395 This is suitable for output with `assemble_name'. */
1397 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1398 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1400 /* This is how to output an assembler line defining a `long double'
1403 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) i960_output_long_double(FILE, VALUE)
1405 /* This is how to output an assembler line defining a `double' constant. */
1407 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1409 /* This is how to output an assembler line defining a `float' constant. */
1411 #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1413 /* This is how to output an assembler line defining an `int' constant. */
1415 #define ASM_OUTPUT_INT(FILE,VALUE) \
1416 ( fprintf (FILE, "\t.word "), \
1417 output_addr_const (FILE, (VALUE)), \
1418 fprintf (FILE, "\n"))
1420 /* Likewise for `char' and `short' constants. */
1422 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1423 ( fprintf (FILE, "\t.short "), \
1424 output_addr_const (FILE, (VALUE)), \
1425 fprintf (FILE, "\n"))
1427 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1428 ( fprintf (FILE, "\t.byte "), \
1429 output_addr_const (FILE, (VALUE)), \
1430 fprintf (FILE, "\n"))
1432 /* This is how to output an assembler line for a numeric constant byte. */
1434 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1435 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1437 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1438 fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1440 /* This is how to output an insn to pop a register from the stack.
1441 It need not be very fast code. */
1443 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1444 fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1446 /* This is how to output an element of a case-vector that is absolute. */
1448 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1449 fprintf (FILE, "\t.word L%d\n", VALUE)
1451 /* This is how to output an element of a case-vector that is relative. */
1453 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1454 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1456 /* This is how to output an assembler line that says to advance the
1457 location counter to a multiple of 2**LOG bytes. */
1459 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1460 fprintf (FILE, "\t.align %d\n", (LOG))
1462 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1463 fprintf (FILE, "\t.space %d\n", (SIZE))
1465 /* This says how to output an assembler line
1466 to define a global common symbol. */
1468 /* For common objects, output unpadded size... gld960 & lnk960 both
1469 have code to align each common object at link time. Also, if size
1470 is 0, treat this as a declaration, not a definition - i.e.,
1471 do nothing at all. */
1473 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1474 { if ((SIZE) != 0) \
1476 fputs (".globl ", (FILE)), \
1477 assemble_name ((FILE), (NAME)), \
1478 fputs ("\n.comm ", (FILE)), \
1479 assemble_name ((FILE), (NAME)), \
1480 fprintf ((FILE), ",%d\n", (SIZE)); \
1484 /* This says how to output an assembler line to define a local common symbol.
1485 Output unpadded size, with request to linker to align as requested.
1486 0 size should not be possible here. */
1488 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1489 ( fputs (".bss\t", (FILE)), \
1490 assemble_name ((FILE), (NAME)), \
1491 fprintf ((FILE), ",%d,%d\n", (SIZE), \
1492 (floor_log2 ((ALIGN) / BITS_PER_UNIT))))
1494 /* A C statement (sans semicolon) to output to the stdio stream
1495 FILE the assembler definition of uninitialized global DECL named
1496 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1497 Try to use asm_output_aligned_bss to implement this macro. */
1499 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1501 fputs (".globl ", (FILE)); \
1502 assemble_name ((FILE), (NAME)); \
1503 fputs ("\n", (FILE)); \
1504 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
1507 /* Output text for an #ident directive. */
1508 #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1510 /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1512 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_CODE_ALIGN ? 3 : 0)
1514 /* Store in OUTPUT a string (made with alloca) containing
1515 an assembler-name for a local static variable named NAME.
1516 LABELNO is an integer which is different for each call. */
1518 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1519 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1520 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1522 /* Define the parentheses used to group arithmetic operations
1523 in assembler code. */
1525 #define ASM_OPEN_PAREN "("
1526 #define ASM_CLOSE_PAREN ")"
1528 /* Define results of standard character escape sequences. */
1529 #define TARGET_BELL 007
1530 #define TARGET_BS 010
1531 #define TARGET_TAB 011
1532 #define TARGET_NEWLINE 012
1533 #define TARGET_VT 013
1534 #define TARGET_FF 014
1535 #define TARGET_CR 015
1537 /* Output assembler code to FILE to initialize this source file's
1538 basic block profiling info, if that has not already been done. */
1540 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1541 { fprintf (FILE, "\tld LPBX0,g12\n"); \
1542 fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1543 fprintf (FILE, "\tlda LPBX0,g12\n"); \
1544 fprintf (FILE, "\tcall ___bb_init_func\n"); \
1545 fprintf (FILE, "LPY%d:\n",LABELNO); }
1547 /* Output assembler code to FILE to increment the entry-count for
1548 the BLOCKNO'th basic block in this source file. */
1550 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1551 { int blockn = (BLOCKNO); \
1552 fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1553 fprintf (FILE, "\taddo g12,1,g12\n"); \
1554 fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1556 /* Print operand X (an rtx) in assembler syntax to file FILE.
1557 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1558 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1560 #define PRINT_OPERAND(FILE, X, CODE) \
1561 i960_print_operand (FILE, X, CODE);
1563 /* Print a memory address as an operand to reference that memory location. */
1565 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1566 i960_print_operand_addr (FILE, ADDR)
1568 /* Determine which codes are valid without a following integer. These must
1569 not be alphabetic (the characters are chosen so that
1570 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
1573 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '+')
1575 /* Output assembler code for a block containing the constant parts
1576 of a trampoline, leaving space for the variable parts. */
1578 /* On the i960, the trampoline contains three instructions:
1579 ldconst _function, r4
1580 ldconst static addr, g12
1583 #define TRAMPOLINE_TEMPLATE(FILE) \
1585 ASM_OUTPUT_INT (FILE, GEN_INT (0x8C203000)); \
1586 ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
1587 ASM_OUTPUT_INT (FILE, GEN_INT (0x8CE03000)); \
1588 ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
1589 ASM_OUTPUT_INT (FILE, GEN_INT (0x84212000)); \
1592 /* Length in units of the trampoline for entering a nested function. */
1594 #define TRAMPOLINE_SIZE 20
1596 /* Emit RTL insns to initialize the variable parts of a trampoline.
1597 FNADDR is an RTX for the address of the function's pure code.
1598 CXT is an RTX for the static chain value for the function. */
1600 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1602 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), FNADDR); \
1603 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), CXT); \
1606 /* Generate RTL to flush the register windows so as to make arbitrary frames
1608 #define SETUP_FRAME_ADDRESSES() \
1609 emit_insn (gen_flush_register_windows ())
1611 #define BUILTIN_SETJMP_FRAME_VALUE hard_frame_pointer_rtx
1614 /* Promote char and short arguments to ints, when want compatibility with
1615 the iC960 compilers. */
1617 /* ??? In order for this to work, all users would need to be changed
1618 to test the value of the macro at run time. */
1619 #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1620 /* ??? This does not exist. */
1621 #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1624 /* Instruction type definitions. Used to alternate instructions types for
1625 better performance on the C series chips. */
1627 enum insn_types
{ I_TYPE_REG
, I_TYPE_MEM
, I_TYPE_CTRL
};
1629 /* Holds the insn type of the last insn output to the assembly file. */
1631 extern enum insn_types i960_last_insn_type
;
1633 /* Parse opcodes, and set the insn last insn type based on them. */
1635 #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1637 /* Table listing what rtl codes each predicate in i960.c will accept. */
1639 #define PREDICATE_CODES \
1640 {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1641 LABEL_REF, SUBREG, REG, MEM}}, \
1642 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1643 {"logic_operand", {SUBREG, REG, CONST_INT}}, \
1644 {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1645 {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1646 {"literal", {CONST_INT}}, \
1647 {"fp_literal_one", {CONST_DOUBLE}}, \
1648 {"fp_literal_double", {CONST_DOUBLE}}, \
1649 {"fp_literal", {CONST_DOUBLE}}, \
1650 {"signed_literal", {CONST_INT}}, \
1651 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1652 {"eq_or_neq", {EQ, NE}}, \
1653 {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1654 CONST_DOUBLE, CONST}}, \
1655 {"power2_operand", {CONST_INT}}, \
1656 {"cmplpower2_operand", {CONST_INT}},
1658 /* Defined in reload.c, and used in insn-recog.c. */
1660 extern int rtx_equal_function_value_matters
;
1662 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
1663 Used for C++ multiple inheritance. */
1664 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1667 if (d < 0 && d > -32) \
1668 fprintf (FILE, "\tsubo %d,g0,g0\n", -d); \
1669 else if (d > 0 && d < 32) \
1670 fprintf (FILE, "\taddo %d,g0,g0\n", d); \
1673 fprintf (FILE, "\tldconst %d,r5\n", d); \
1674 fprintf (FILE, "\taddo r5,g0,g0\n"); \
1676 fprintf (FILE, "\tbx "); \
1677 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
1678 fprintf (FILE, "\n"); \