1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-flags.h"
36 #include "insn-attr.h"
39 #include "insn-codes.h"
47 /* Save the operands last given to a compare for use when we
48 generate a scc or bcc insn. */
50 rtx i960_compare_op0
, i960_compare_op1
;
52 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
55 static int i960_maxbitalignment
;
56 static int i960_last_maxbitalignment
;
58 /* Used to implement switching between MEM and ALU insn types, for better
59 C series performance. */
61 enum insn_types i960_last_insn_type
;
63 /* The leaf-procedure return register. Set only if this is a leaf routine. */
65 static int i960_leaf_ret_reg
;
67 /* True if replacing tail calls with jumps is OK. */
69 static int tail_call_ok
;
71 /* A string containing a list of insns to emit in the epilogue so as to
72 restore all registers saved by the prologue. Created by the prologue
73 code as it saves registers away. */
75 char epilogue_string
[1000];
77 /* A unique number (per function) for return labels. */
79 static int ret_label
= 0;
81 /* This is true if FNDECL is either a varargs or a stdarg function.
82 This is used to help identify functions that use an argument block. */
84 #define VARARGS_STDARG_FUNCTION(FNDECL) \
85 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
86 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
87 || current_function_varargs)
89 /* Handle pragmas for compatibility with Intel's compilers. */
91 /* ??? This is incomplete, since it does not handle all pragmas that the
92 intel compilers understand. */
95 process_pragma (p_getc
, p_ungetc
, pname
)
96 int (* p_getc
) PARAMS ((void));
97 void (* p_ungetc
) PARAMS ((int));
105 /* Should be pragma 'far' or equivalent for callx/balx here. */
106 if (strcmp (pname
, "align") != 0)
113 while (c
== ' ' || c
== '\t');
118 while (c
>= '0' && c
<= '9')
120 if (s
< buf
+ sizeof buf
- 1)
127 /* We had to read a non-numerical character to get out of the
128 while loop---often a newline. So, we have to put it back to
129 make sure we continue to parse everything properly. */
138 /* Return to last alignment. */
139 align
= i960_last_maxbitalignment
/ 8;
146 i960_last_maxbitalignment
= i960_maxbitalignment
;
147 i960_maxbitalignment
= align
* 8;
151 /* Silently ignore bad values. */
155 /* NOTE: ic960 R3.0 pragma align definition:
157 #pragma align [(size)] | (identifier=size[,...])
158 #pragma noalign [(identifier)[,...]]
160 (all parens are optional)
162 - size is [1,2,4,8,16]
163 - noalign means size==1
164 - applies only to component elements of a struct (and union?)
165 - identifier applies to structure tag (only)
166 - missing identifier means next struct
168 - alignment rules for bitfields need more investigation */
173 /* Initialize variables before compiling any files. */
178 if (TARGET_IC_COMPAT2_0
)
180 i960_maxbitalignment
= 8;
181 i960_last_maxbitalignment
= 128;
185 i960_maxbitalignment
= 128;
186 i960_last_maxbitalignment
= 8;
190 /* Return true if OP can be used as the source of an fp move insn. */
193 fpmove_src_operand (op
, mode
)
195 enum machine_mode mode
;
197 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
201 /* Return true if OP is a register or zero. */
204 reg_or_zero_operand (op
, mode
)
206 enum machine_mode mode
;
208 return register_operand (op
, mode
) || op
== const0_rtx
;
212 /* Return truth value of whether OP can be used as an operands in a three
213 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
216 arith_operand (op
, mode
)
218 enum machine_mode mode
;
220 return (register_operand (op
, mode
) || literal (op
, mode
));
223 /* Return truth value of whether OP can be used as an operands in a three
224 address logic insn, possibly complementing OP, of mode MODE. */
227 logic_operand (op
, mode
)
229 enum machine_mode mode
;
231 return (register_operand (op
, mode
)
232 || (GET_CODE (op
) == CONST_INT
233 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
236 /* Return true if OP is a register or a valid floating point literal. */
239 fp_arith_operand (op
, mode
)
241 enum machine_mode mode
;
243 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
246 /* Return true is OP is a register or a valid signed integer literal. */
249 signed_arith_operand (op
, mode
)
251 enum machine_mode mode
;
253 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
256 /* Return truth value of whether OP is a integer which fits the
257 range constraining immediate operands in three-address insns. */
262 enum machine_mode mode ATTRIBUTE_UNUSED
;
264 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
267 /* Return true if OP is a float constant of 1. */
270 fp_literal_one (op
, mode
)
272 enum machine_mode mode
;
274 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
277 /* Return true if OP is a float constant of 0. */
280 fp_literal_zero (op
, mode
)
282 enum machine_mode mode
;
284 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
287 /* Return true if OP is a valid floating point literal. */
292 enum machine_mode mode
;
294 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
297 /* Return true if OP is a valid signed immediate constant. */
300 signed_literal(op
, mode
)
302 enum machine_mode mode ATTRIBUTE_UNUSED
;
304 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
307 /* Return truth value of statement that OP is a symbolic memory
308 operand of mode MODE. */
311 symbolic_memory_operand (op
, mode
)
313 enum machine_mode mode ATTRIBUTE_UNUSED
;
315 if (GET_CODE (op
) == SUBREG
)
316 op
= SUBREG_REG (op
);
317 if (GET_CODE (op
) != MEM
)
320 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
321 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
324 /* Return truth value of whether OP is EQ or NE. */
329 enum machine_mode mode ATTRIBUTE_UNUSED
;
331 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
334 /* OP is an integer register or a constant. */
337 arith32_operand (op
, mode
)
339 enum machine_mode mode
;
341 if (register_operand (op
, mode
))
343 return (CONSTANT_P (op
));
346 /* Return true if OP is an integer constant which is a power of 2. */
349 power2_operand (op
,mode
)
351 enum machine_mode mode ATTRIBUTE_UNUSED
;
353 if (GET_CODE (op
) != CONST_INT
)
356 return exact_log2 (INTVAL (op
)) >= 0;
359 /* Return true if OP is an integer constant which is the complement of a
363 cmplpower2_operand (op
, mode
)
365 enum machine_mode mode ATTRIBUTE_UNUSED
;
367 if (GET_CODE (op
) != CONST_INT
)
370 return exact_log2 (~ INTVAL (op
)) >= 0;
373 /* If VAL has only one bit set, return the index of that bit. Otherwise
382 for (i
= 0; val
!= 0; i
++, val
>>= 1)
394 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
395 The return value indicates how many consecutive non-zero bits exist
396 if this is a mask. This is the same as the next function, except that
397 it does not indicate what the start and stop bit positions are. */
403 register int start
, end
, i
;
406 for (i
= 0; val
!= 0; val
>>= 1, i
++)
416 /* Still looking for the first bit. */
420 /* We've seen the start of a bit sequence, and now a zero. There
421 must be more one bits, otherwise we would have exited the loop.
422 Therefore, it is not a mask. */
427 /* The bit string has ones from START to END bit positions only. */
428 return end
- start
+ 1;
431 /* If VAL is a mask, then return nonzero, with S set to the starting bit
432 position and E set to the ending bit position of the mask. The return
433 value indicates how many consecutive bits exist in the mask. This is
434 the same as the previous function, except that it also indicates the
435 start and end bit positions of the mask. */
442 register int start
, end
, i
;
446 for (i
= 0; val
!= 0; val
>>= 1, i
++)
457 /* Still looking for the first bit. */
461 /* We've seen the start of a bit sequence, and now a zero. There
462 must be more one bits, otherwise we would have exited the loop.
463 Therefor, it is not a mask. */
472 /* The bit string has ones from START to END bit positions only. */
475 return ((start
< 0) ? 0 : end
- start
+ 1);
478 /* Return the machine mode to use for a comparison. */
481 select_cc_mode (op
, x
)
483 rtx x ATTRIBUTE_UNUSED
;
485 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
490 /* X and Y are two things to compare using CODE. Emit the compare insn and
491 return the rtx for register 36 in the proper mode. */
494 gen_compare_reg (code
, x
, y
)
499 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
500 enum machine_mode mode
501 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
505 if (! arith_operand (x
, mode
))
506 x
= force_reg (SImode
, x
);
507 if (! arith_operand (y
, mode
))
508 y
= force_reg (SImode
, y
);
511 cc_reg
= gen_rtx_REG (ccmode
, 36);
512 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
513 gen_rtx_COMPARE (ccmode
, x
, y
)));
518 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
519 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
520 are 4. Indexed addresses are cost 6. */
522 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
525 i960_address_cost (x
)
529 /* Handled before calling here. */
530 if (GET_CODE (x
) == REG
)
533 /* This is a MEMA operand -- it's free. */
534 if (GET_CODE (x
) == CONST_INT
536 && INTVAL (x
) < 4096)
539 if (GET_CODE (x
) == PLUS
)
541 rtx base
= XEXP (x
, 0);
542 rtx offset
= XEXP (x
, 1);
544 if (GET_CODE (base
) == SUBREG
)
545 base
= SUBREG_REG (base
);
546 if (GET_CODE (offset
) == SUBREG
)
547 offset
= SUBREG_REG (offset
);
549 if (GET_CODE (base
) == REG
)
551 if (GET_CODE (offset
) == REG
)
553 if (GET_CODE (offset
) == CONST_INT
)
555 if ((unsigned)INTVAL (offset
) < 2047)
559 if (CONSTANT_P (offset
))
562 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
565 /* This is an invalid address. The return value doesn't matter, but
566 for convenience we make this more expensive than anything else. */
569 if (GET_CODE (x
) == MULT
)
572 /* Symbol_refs and other unrecognized addresses are cost 4. */
576 /* Emit insns to move operands[1] into operands[0].
578 Return 1 if we have written out everything that needs to be done to
579 do the move. Otherwise, return 0 and the caller will emit the move
583 emit_move_sequence (operands
, mode
)
585 enum machine_mode mode
;
587 /* We can only store registers to memory. */
589 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
590 && (operands
[1] != const0_rtx
|| current_function_args_size
591 || current_function_varargs
|| current_function_stdarg
592 || rtx_equal_function_value_matters
))
593 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
594 operands
[1] = force_reg (mode
, operands
[1]);
596 /* Storing multi-word values in unaligned hard registers to memory may
597 require a scratch since we have to store them a register at a time and
598 adding 4 to the memory address may not yield a valid insn. */
599 /* ??? We don't always need the scratch, but that would complicate things.
601 /* ??? We must also handle stores to pseudos here, because the pseudo may be
602 replaced with a MEM later. This would be cleaner if we didn't have
603 a separate pattern for unaligned DImode/TImode stores. */
604 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
605 && (GET_CODE (operands
[0]) == MEM
606 || (GET_CODE (operands
[0]) == REG
607 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
608 && GET_CODE (operands
[1]) == REG
609 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
610 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
612 emit_insn (gen_rtx_PARALLEL
615 gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]),
616 gen_rtx_CLOBBER (VOIDmode
,
617 gen_rtx_SCRATCH (Pmode
)))));
624 /* Output assembler to move a double word value. */
627 i960_output_move_double (dst
, src
)
632 if (GET_CODE (dst
) == REG
633 && GET_CODE (src
) == REG
)
635 if ((REGNO (src
) & 1)
636 || (REGNO (dst
) & 1))
638 /* We normally copy the low-numbered register first. However, if
639 the second source register is the same as the first destination
640 register, we must copy in the opposite order. */
641 if (REGNO (src
) + 1 == REGNO (dst
))
642 return "mov %D1,%D0\n\tmov %1,%0";
644 return "mov %1,%0\n\tmov %D1,%D0";
649 else if (GET_CODE (dst
) == REG
650 && GET_CODE (src
) == CONST_INT
651 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
654 return "mov %1,%0\n\tmov 0,%D0";
658 else if (GET_CODE (dst
) == REG
659 && GET_CODE (src
) == MEM
)
663 /* One can optimize a few cases here, but you have to be
664 careful of clobbering registers used in the address and
668 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 1);
669 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
670 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
671 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
677 else if (GET_CODE (dst
) == MEM
678 && GET_CODE (src
) == REG
)
683 operands
[1] = adj_offsettable_operand (dst
, UNITS_PER_WORD
);
684 if (! memory_address_p (word_mode
, XEXP (operands
[1], 0)))
687 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands
);
696 /* Output assembler to move a double word zero. */
699 i960_output_move_double_zero (dst
)
706 operands
[1] = adj_offsettable_operand (dst
, 4);
707 output_asm_insn ("st g14,%0\n\tst g14,%1", operands
);
712 /* Output assembler to move a quad word value. */
715 i960_output_move_quad (dst
, src
)
720 if (GET_CODE (dst
) == REG
721 && GET_CODE (src
) == REG
)
723 if ((REGNO (src
) & 3)
724 || (REGNO (dst
) & 3))
726 /* We normally copy starting with the low numbered register.
727 However, if there is an overlap such that the first dest reg
728 is <= the last source reg but not < the first source reg, we
729 must copy in the opposite order. */
730 if (REGNO (dst
) <= REGNO (src
) + 3
731 && REGNO (dst
) >= REGNO (src
))
732 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
734 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
739 else if (GET_CODE (dst
) == REG
740 && GET_CODE (src
) == CONST_INT
741 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
744 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
748 else if (GET_CODE (dst
) == REG
749 && GET_CODE (src
) == MEM
)
753 /* One can optimize a few cases here, but you have to be
754 careful of clobbering registers used in the address and
758 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 3);
759 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
760 operands
[4] = adj_offsettable_operand (operands
[3], UNITS_PER_WORD
);
761 operands
[5] = adj_offsettable_operand (operands
[4], UNITS_PER_WORD
);
762 operands
[6] = adj_offsettable_operand (operands
[5], UNITS_PER_WORD
);
763 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
769 else if (GET_CODE (dst
) == MEM
770 && GET_CODE (src
) == REG
)
775 operands
[1] = adj_offsettable_operand (dst
, UNITS_PER_WORD
);
776 operands
[2] = adj_offsettable_operand (dst
, 2*UNITS_PER_WORD
);
777 operands
[3] = adj_offsettable_operand (dst
, 3*UNITS_PER_WORD
);
778 if (! memory_address_p (word_mode
, XEXP (operands
[3], 0)))
781 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands
);
790 /* Output assembler to move a quad word zero. */
793 i960_output_move_quad_zero (dst
)
800 operands
[1] = adj_offsettable_operand (dst
, 4);
801 operands
[2] = adj_offsettable_operand (dst
, 8);
802 operands
[3] = adj_offsettable_operand (dst
, 12);
803 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands
);
809 /* Emit insns to load a constant to non-floating point registers.
810 Uses several strategies to try to use as few insns as possible. */
813 i960_output_ldconst (dst
, src
)
814 register rtx dst
, src
;
817 register unsigned rsrc2
;
818 enum machine_mode mode
= GET_MODE (dst
);
821 operands
[0] = operands
[2] = dst
;
822 operands
[1] = operands
[3] = src
;
824 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
825 must be a ldconst insn. */
827 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
829 output_asm_insn ("ldconst %1,%0", operands
);
832 else if (mode
== XFmode
)
838 if (fp_literal_zero (src
, XFmode
))
841 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
842 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
844 output_asm_insn ("# ldconst %1,%0",operands
);
846 for (i
= 0; i
< 3; i
++)
848 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + i
);
849 operands
[1] = GEN_INT (value_long
[i
]);
850 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
856 else if (mode
== DFmode
)
860 if (fp_literal_zero (src
, DFmode
))
863 split_double (src
, &first
, &second
);
865 output_asm_insn ("# ldconst %1,%0",operands
);
867 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
869 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
871 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
872 operands
[1] = second
;
873 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
877 else if (mode
== SFmode
)
882 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
883 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
885 output_asm_insn ("# ldconst %1,%0",operands
);
886 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
887 operands
[1] = GEN_INT (value
);
888 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
892 else if (mode
== TImode
)
894 /* ??? This is currently not handled at all. */
897 /* Note: lowest order word goes in lowest numbered reg. */
898 rsrc1
= INTVAL (src
);
899 if (rsrc1
>= 0 && rsrc1
< 32)
902 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
903 /* Go pick up the low-order word. */
905 else if (mode
== DImode
)
907 rtx upperhalf
, lowerhalf
, xoperands
[2];
909 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
910 split_double (src
, &lowerhalf
, &upperhalf
);
915 /* Note: lowest order word goes in lowest numbered reg. */
916 /* Numbers from 0 to 31 can be handled with a single insn. */
917 rsrc1
= INTVAL (lowerhalf
);
918 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
921 /* Output the upper half with a recursive call. */
922 xoperands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
923 xoperands
[1] = upperhalf
;
924 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
926 /* The lower word is emitted as normally. */
930 rsrc1
= INTVAL (src
);
936 else if (mode
== HImode
)
945 /* ldconst 0..31,X -> mov 0..31,X */
948 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
953 /* ldconst 32..63,X -> add 31,nn,X */
956 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
958 operands
[1] = GEN_INT (rsrc1
- 31);
959 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
965 /* ldconst -1..-31 -> sub 0,0..31,X */
968 /* return 'sub -(%1),0,%0' */
969 operands
[1] = GEN_INT (- rsrc1
);
970 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
974 /* ldconst -32 -> not 31,X */
977 operands
[1] = GEN_INT (~rsrc1
);
978 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
983 /* If const is a single bit. */
984 if (bitpos (rsrc1
) >= 0)
986 operands
[1] = GEN_INT (bitpos (rsrc1
));
987 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
991 /* If const is a bit string of less than 6 bits (1..31 shifted). */
996 if (bitstr (rsrc1
, &s
, &e
) < 6)
998 rsrc2
= ((unsigned int) rsrc1
) >> s
;
999 operands
[1] = GEN_INT (rsrc2
);
1000 operands
[2] = GEN_INT (s
);
1001 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
1006 /* Unimplemented cases:
1007 const is in range 0..31 but rotated around end of word:
1008 ror 31,3,g0 -> ldconst 0xe0000003,g0
1010 and any 2 instruction cases that might be worthwhile */
1012 output_asm_insn ("ldconst %1,%0", operands
);
1016 /* Determine if there is an opportunity for a bypass optimization.
1017 Bypass succeeds on the 960K* if the destination of the previous
1018 instruction is the second operand of the current instruction.
1019 Bypass always succeeds on the C*.
1021 Return 1 if the pattern should interchange the operands.
1023 CMPBR_FLAG is true if this is for a compare-and-branch insn.
1024 OP1 and OP2 are the two source operands of a 3 operand insn. */
1027 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
1028 register rtx insn
, op1
, op2
;
1031 register rtx prev_insn
, prev_dest
;
1033 if (TARGET_C_SERIES
)
1036 /* Can't do this if op1 isn't a register. */
1040 /* Can't do this for a compare-and-branch if both ops aren't regs. */
1041 if (cmpbr_flag
&& ! REG_P (op2
))
1044 prev_insn
= prev_real_insn (insn
);
1046 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
1047 && GET_CODE (PATTERN (prev_insn
)) == SET
)
1049 prev_dest
= SET_DEST (PATTERN (prev_insn
));
1050 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
1051 || (GET_CODE (prev_dest
) == SUBREG
1052 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
1053 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
1059 /* Output the code which declares the function name. This also handles
1060 leaf routines, which have special requirements, and initializes some
1061 global variables. */
1064 i960_function_name_declare (file
, name
, fndecl
)
1073 /* Increment global return label. */
1077 /* Compute whether tail calls and leaf routine optimizations can be performed
1078 for this function. */
1080 if (TARGET_TAILCALL
)
1085 if (TARGET_LEAFPROC
)
1090 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1091 argblock, because argblock uses g14 implicitly. */
1093 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1099 /* See if caller passes in an address to return value. */
1101 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1107 /* Can not use tail calls or make this a leaf routine if there is a non
1110 if (get_frame_size () != 0)
1113 /* I don't understand this condition, and do not think that it is correct.
1114 Apparently this is just checking whether the frame pointer is used, and
1115 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1118 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1119 if (GET_CODE (insn
) == INSN
1120 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1126 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1129 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1130 if (GET_CODE (insn
) == CALL_INSN
)
1136 /* Can not be a leaf routine if any non-call clobbered registers are
1137 used in this function. */
1140 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1141 if (regs_ever_live
[i
]
1142 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1144 /* Global registers. */
1145 if (i
< 16 && i
> 7 && i
!= 13)
1147 /* Local registers. */
1152 /* Now choose a leaf return register, if we can find one, and if it is
1153 OK for this to be a leaf routine. */
1155 i960_leaf_ret_reg
= -1;
1157 if (optimize
&& leaf_proc_ok
)
1159 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1160 if (regs_ever_live
[i
] == 0)
1162 i960_leaf_ret_reg
= i
;
1163 regs_ever_live
[i
] = 1;
1168 /* Do this after choosing the leaf return register, so it will be listed
1169 if one was chosen. */
1171 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1172 fprintf (file
, "\t# Registers used: ");
1174 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1176 if (regs_ever_live
[i
])
1178 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1180 if (i
> 15 && j
== 0)
1182 fprintf (file
,"\n\t#\t\t ");
1188 fprintf (file
, "\n");
1190 if (i960_leaf_ret_reg
>= 0)
1192 /* Make it a leaf procedure. */
1194 if (TREE_PUBLIC (fndecl
))
1195 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1197 fprintf (file
, "\t.leafproc\t");
1198 assemble_name (file
, name
);
1199 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1200 ASM_OUTPUT_LABEL (file
, name
);
1201 fprintf (file
, "\tlda Li960R%d,g14\n", ret_label
);
1202 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1203 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1205 if (TARGET_C_SERIES
)
1207 fprintf (file
, "\tlda 0,g14\n");
1208 i960_last_insn_type
= I_TYPE_MEM
;
1212 fprintf (file
, "\tmov 0,g14\n");
1213 i960_last_insn_type
= I_TYPE_REG
;
1218 ASM_OUTPUT_LABEL (file
, name
);
1219 i960_last_insn_type
= I_TYPE_CTRL
;
1223 /* Compute and return the frame size. */
1226 compute_frame_size (size
)
1230 int outgoing_args_size
= current_function_outgoing_args_size
;
1232 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1233 as size is concerned. */
1234 actual_fsize
= (size
+ 15) & -16;
1235 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1237 return actual_fsize
;
1240 /* Here register group is range of registers which can be moved by
1241 one i960 instruction. */
1249 static int i960_form_reg_groups
PARAMS ((int, int, int *, int, struct reg_group
*));
1250 static int i960_reg_group_compare
PARAMS ((const void *, const void *));
1251 static int i960_split_reg_group
PARAMS ((struct reg_group
*, int, int));
1252 static void i960_arg_size_and_align
PARAMS ((enum machine_mode
, tree
, int *, int *));
1254 /* The following functions forms the biggest as possible register
1255 groups with registers in STATE. REGS contain states of the
1256 registers in range [start, finish_reg). The function returns the
1257 number of groups formed. */
1259 i960_form_reg_groups (start_reg
, finish_reg
, regs
, state
, reg_groups
)
1264 struct reg_group
*reg_groups
;
1269 for (i
= start_reg
; i
< finish_reg
; )
1271 if (regs
[i
] != state
)
1276 else if (i
% 2 != 0 || regs
[i
+ 1] != state
)
1277 reg_groups
[nw
].length
= 1;
1278 else if (i
% 4 != 0 || regs
[i
+ 2] != state
)
1279 reg_groups
[nw
].length
= 2;
1280 else if (regs
[i
+ 3] != state
)
1281 reg_groups
[nw
].length
= 3;
1283 reg_groups
[nw
].length
= 4;
1284 reg_groups
[nw
].start_reg
= i
;
1285 i
+= reg_groups
[nw
].length
;
1291 /* We sort register winodws in descending order by length. */
1293 i960_reg_group_compare (group1
, group2
)
1297 const struct reg_group
*w1
= group1
;
1298 const struct reg_group
*w2
= group2
;
1300 if (w1
->length
> w2
->length
)
1302 else if (w1
->length
< w2
->length
)
1308 /* Split the first register group in REG_GROUPS on subgroups one of
1309 which will contain SUBGROUP_LENGTH registers. The function
1310 returns new number of winodws. */
1312 i960_split_reg_group (reg_groups
, nw
, subgroup_length
)
1313 struct reg_group
*reg_groups
;
1315 int subgroup_length
;
1317 if (subgroup_length
< reg_groups
->length
- subgroup_length
)
1318 /* This guarantees correct alignments of the two subgroups for
1319 i960 (see spliting for the group length 2, 3, 4). More
1320 generalized algorithm would require splitting the group more
1322 subgroup_length
= reg_groups
->length
- subgroup_length
;
1323 /* More generalized algorithm would require to try merging
1324 subgroups here. But in case i960 it always results in failure
1325 because of register group alignment. */
1326 reg_groups
[nw
].length
= reg_groups
->length
- subgroup_length
;
1327 reg_groups
[nw
].start_reg
= reg_groups
->start_reg
+ subgroup_length
;
1329 reg_groups
->length
= subgroup_length
;
1330 qsort (reg_groups
, nw
, sizeof (struct reg_group
), i960_reg_group_compare
);
1334 /* Output code for the function prologue. */
1337 i960_function_prologue (file
, size
)
1341 register int i
, j
, nr
;
1342 int n_saved_regs
= 0;
1343 int n_remaining_saved_regs
;
1345 int actual_fsize
, offset
;
1347 struct reg_group
*g
, *l
;
1349 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1351 int regs
[FIRST_PSEUDO_REGISTER
];
1352 /* All global registers (which must be saved) divided by groups. */
1353 struct reg_group global_reg_groups
[16];
1354 /* All local registers (which are available) divided by groups. */
1355 struct reg_group local_reg_groups
[16];
1358 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1359 if (regs_ever_live
[i
]
1360 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12))
1361 /* No need to save the static chain pointer. */
1362 && ! (i
== STATIC_CHAIN_REGNUM
&& current_function_needs_context
))
1365 /* Count global registers that need saving. */
1372 n_remaining_saved_regs
= n_saved_regs
;
1374 epilogue_string
[0] = '\0';
1376 if (profile_flag
|| profile_block_flag
)
1378 /* When profiling, we may use registers 20 to 27 to save arguments, so
1379 they can't be used here for saving globals. J is the number of
1380 argument registers the mcount call will save. */
1381 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1384 for (i
= 20; i
<= j
+ 20; i
++)
1388 gnw
= i960_form_reg_groups (0, 16, regs
, -1, global_reg_groups
);
1389 lnw
= i960_form_reg_groups (19, 32, regs
, 0, local_reg_groups
);
1390 qsort (global_reg_groups
, gnw
, sizeof (struct reg_group
),
1391 i960_reg_group_compare
);
1392 qsort (local_reg_groups
, lnw
, sizeof (struct reg_group
),
1393 i960_reg_group_compare
);
1394 for (g
= global_reg_groups
, l
= local_reg_groups
; lnw
!= 0 && gnw
!= 0;)
1396 if (g
->length
== l
->length
)
1398 fprintf (file
, "\tmov%s %s,%s\n",
1399 ((g
->length
== 4) ? "q" :
1400 (g
->length
== 3) ? "t" :
1401 (g
->length
== 2) ? "l" : ""),
1402 reg_names
[(unsigned char) g
->start_reg
],
1403 reg_names
[(unsigned char) l
->start_reg
]);
1404 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1405 ((g
->length
== 4) ? "q" :
1406 (g
->length
== 3) ? "t" :
1407 (g
->length
== 2) ? "l" : ""),
1408 reg_names
[(unsigned char) l
->start_reg
],
1409 reg_names
[(unsigned char) g
->start_reg
]);
1410 strcat (epilogue_string
, tmpstr
);
1411 n_remaining_saved_regs
-= g
->length
;
1412 for (i
= 0; i
< g
->length
; i
++)
1414 regs
[i
+ g
->start_reg
] = 1;
1415 regs
[i
+ l
->start_reg
] = -1;
1416 regs_ever_live
[i
+ l
->start_reg
] = 1;
1423 else if (g
->length
> l
->length
)
1424 gnw
= i960_split_reg_group (g
, gnw
, l
->length
);
1426 lnw
= i960_split_reg_group (l
, lnw
, g
->length
);
1429 actual_fsize
= compute_frame_size (size
);
1431 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1432 size up to the nearest multiple of 16. I don't know whether this is
1433 necessary, or even desirable.
1435 The frame pointer must be aligned, but the call instruction takes care of
1436 that. If we leave the stack pointer unaligned, we may save a little on
1437 dynamic stack allocation. And we don't lose, at least according to the
1439 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1442 /* Check stack limit if necessary. */
1443 if (current_function_limit_stack
)
1445 rtx min_stack
= stack_limit_rtx
;
1446 if (actual_fsize
!= 0)
1447 min_stack
= plus_constant (stack_limit_rtx
, -actual_fsize
);
1449 /* Now, emulate a little bit of reload. We want to turn 'min_stack'
1450 into an arith_operand. Use register 20 as the temporary. */
1451 if (legitimate_address_p (Pmode
, min_stack
, 1)
1452 && !arith_operand (min_stack
, Pmode
))
1454 rtx tmp
= gen_rtx_MEM (Pmode
, min_stack
);
1455 fputs ("\tlda\t", file
);
1456 i960_print_operand (file
, tmp
, 0);
1457 fputs (",r4\n", file
);
1458 min_stack
= gen_rtx_REG (Pmode
, 20);
1460 if (arith_operand (min_stack
, Pmode
))
1462 fputs ("\tcmpo\tsp,", file
);
1463 i960_print_operand (file
, min_stack
, 0);
1464 fputs ("\n\tfaultge.f\n", file
);
1467 warning ("stack limit expression is not supported");
1470 /* Allocate space for register save and locals. */
1471 if (actual_fsize
> 0)
1473 if (actual_fsize
< 32)
1474 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1476 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1479 /* Take hardware register save area created by the call instruction
1480 into account, but store them before the argument block area. */
1481 lvar_size
= actual_fsize
- compute_frame_size (0) - n_saved_regs
* 4;
1482 offset
= STARTING_FRAME_OFFSET
+ lvar_size
;
1483 /* Save registers on stack if needed. */
1484 /* ??? Is it worth to use the same algorithm as one for saving
1485 global registers in local registers? */
1486 for (i
= 0, j
= n_remaining_saved_regs
; j
> 0 && i
< 16; i
++)
1493 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1496 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1500 if (nr
== 3 && regs
[i
+3] == -1)
1503 fprintf (file
,"\tst%s %s,%d(fp)\n",
1506 (nr
== 2) ? "l" : ""),
1507 reg_names
[i
], offset
);
1508 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1511 (nr
== 2) ? "l" : ""),
1512 offset
, reg_names
[i
]);
1513 strcat (epilogue_string
, tmpstr
);
1519 if (actual_fsize
== 0)
1522 fprintf (file
, "\t#Prologue stats:\n");
1523 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1526 fprintf (file
, "\t# Local Variable Size: %d bytes\n", lvar_size
);
1528 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1529 n_saved_regs
, n_saved_regs
* 4);
1530 fprintf (file
, "\t#End Prologue#\n");
1533 /* Output code for the function profiler. */
1536 output_function_profiler (file
, labelno
)
1540 /* The last used parameter register. */
1542 int i
, j
, increment
;
1543 int varargs_stdarg_function
1544 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1546 /* Figure out the last used parameter register. The proper thing to do
1547 is to walk incoming args of the function. A function might have live
1548 parameter registers even if it has no incoming args. Note that we
1549 don't have to save parameter registers g8 to g11 because they are
1552 /* See also output_function_prologue, which tries to use local registers
1553 for preserved call-saved global registers. */
1555 for (last_parm_reg
= 7;
1556 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1560 /* Save parameter registers in regs r4 (20) to r11 (27). */
1562 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1564 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1566 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1568 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1573 fprintf (file
, "\tmov%s g%d,r%d\n",
1574 (increment
== 4 ? "q" : increment
== 3 ? "t"
1575 : increment
== 2 ? "l": ""), i
, j
);
1578 /* If this function uses the arg pointer, then save it in r3 and then
1581 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1582 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1584 /* Load location address into g0 and call mcount. */
1586 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1588 /* If this function uses the arg pointer, restore it. */
1590 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1591 fprintf (file
, "\tmov r3,g14\n");
1593 /* Restore parameter registers. */
1595 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1597 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1599 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1601 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1606 fprintf (file
, "\tmov%s r%d,g%d\n",
1607 (increment
== 4 ? "q" : increment
== 3 ? "t"
1608 : increment
== 2 ? "l": ""), j
, i
);
1612 /* Output code for the function epilogue. */
1615 i960_function_epilogue (file
, size
)
1617 unsigned int size ATTRIBUTE_UNUSED
;
1619 if (i960_leaf_ret_reg
>= 0)
1621 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1625 if (*epilogue_string
== 0)
1629 /* Emit a return insn, but only if control can fall through to here. */
1631 tmp
= get_last_insn ();
1634 if (GET_CODE (tmp
) == BARRIER
)
1636 if (GET_CODE (tmp
) == CODE_LABEL
)
1638 if (GET_CODE (tmp
) == JUMP_INSN
)
1640 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1644 if (GET_CODE (tmp
) == NOTE
)
1646 tmp
= PREV_INSN (tmp
);
1651 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1655 fprintf (file
, "Li960R%d:\n", ret_label
);
1657 fprintf (file
, "\t#EPILOGUE#\n");
1659 /* Output the string created by the prologue which will restore all
1660 registers saved by the prologue. */
1662 if (epilogue_string
[0] != '\0')
1663 fprintf (file
, "%s", epilogue_string
);
1665 /* Must clear g14 on return if this function set it.
1666 Only varargs/stdarg functions modify g14. */
1668 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1669 fprintf (file
, "\tmov 0,g14\n");
1671 fprintf (file
, "\tret\n");
1672 fprintf (file
, "\t#End Epilogue#\n");
1675 /* Output code for a call insn. */
1678 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1679 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1681 int argsize
= INTVAL (argsize_rtx
);
1682 rtx nexti
= next_real_insn (insn
);
1684 int varargs_stdarg_function
1685 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1687 operands
[0] = target
;
1688 operands
[1] = arg_pointer
;
1690 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1691 output_asm_insn ("mov g14,r3", operands
);
1694 output_asm_insn ("lda %a1,g14", operands
);
1695 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1696 output_asm_insn ("mov 0,g14", operands
);
1698 /* The code used to assume that calls to SYMBOL_REFs could not be more
1699 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1700 feature is now implemented by relaxing in the GNU linker. It can convert
1701 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1703 /* Nexti could be zero if the called routine is volatile. */
1704 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1705 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1707 /* Delete following return insn. */
1708 if (nexti
&& no_labels_between_p (insn
, nexti
))
1709 delete_insn (nexti
);
1710 output_asm_insn ("bx %0", operands
);
1711 return "# notreached";
1714 output_asm_insn ("callx %0", operands
);
1716 /* If the caller sets g14 to the address of the argblock, then the caller
1717 must clear it after the return. */
1719 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1720 output_asm_insn ("mov r3,g14", operands
);
1721 else if (argsize
> 48)
1722 output_asm_insn ("mov 0,g14", operands
);
1727 /* Output code for a return insn. */
1730 i960_output_ret_insn (insn
)
1733 static char lbuf
[20];
1735 if (*epilogue_string
!= 0)
1737 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1740 sprintf (lbuf
, "b Li960R%d", ret_label
);
1744 /* Must clear g14 on return if this function set it.
1745 Only varargs/stdarg functions modify g14. */
1747 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1748 output_asm_insn ("mov 0,g14", 0);
1750 if (i960_leaf_ret_reg
>= 0)
1752 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1758 /* Print the operand represented by rtx X formatted by code CODE. */
1761 i960_print_operand (file
, x
, code
)
1766 enum rtx_code rtxcode
= x
? GET_CODE (x
) : NIL
;
1773 /* Second reg of a double or quad. */
1774 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1778 /* Third reg of a quad. */
1779 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1783 /* Fourth reg of a quad. */
1784 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1788 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1796 else if (rtxcode
== MEM
)
1798 output_address (XEXP (x
, 0));
1801 else if (rtxcode
== CONST_INT
)
1803 HOST_WIDE_INT val
= INTVAL (x
);
1806 if (val
> 9999 || val
< -999)
1807 fprintf (file
, "0x%x", val
);
1809 fprintf (file
, "%d", val
);
1812 else if (rtxcode
== CONST_DOUBLE
)
1817 if (x
== CONST0_RTX (GET_MODE (x
)))
1819 fprintf (file
, "0f0.0");
1822 else if (x
== CONST1_RTX (GET_MODE (x
)))
1824 fprintf (file
, "0f1.0");
1828 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1829 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1830 fprintf (file
, "0f%s", dstr
);
1837 /* Branch or jump, depending on assembler. */
1838 if (TARGET_ASM_COMPAT
)
1845 /* Sign of condition. */
1846 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1847 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1849 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1850 || (rtxcode
== GE
) || (rtxcode
== LE
))
1857 /* Inverted condition. */
1858 rtxcode
= reverse_condition (rtxcode
);
1862 /* Inverted condition w/ reversed operands. */
1863 rtxcode
= reverse_condition (rtxcode
);
1867 /* Reversed operand condition. */
1868 rtxcode
= swap_condition (rtxcode
);
1872 /* Normal condition. */
1874 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1875 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1876 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1877 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1878 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1879 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1880 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1881 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1882 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1883 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1888 /* For conditional branches, substitute ".t" or ".f". */
1889 if (TARGET_BRANCH_PREDICT
)
1891 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1894 int pred_val
= INTVAL (XEXP (x
, 0));
1895 fputs ((pred_val
< REG_BR_PROB_BASE
/ 2 ? ".f" : ".t"), file
);
1901 output_addr_const (file
, x
);
1911 /* Print a memory address as an operand to reference that memory location.
1913 This is exactly the same as legitimate_address_p, except that it the prints
1914 addresses instead of recognizing them. */
1917 i960_print_operand_addr (file
, addr
)
1929 if (GET_CODE (addr
) == REG
)
1931 else if (CONSTANT_P (addr
))
1933 else if (GET_CODE (addr
) == PLUS
)
1937 op0
= XEXP (addr
, 0);
1938 op1
= XEXP (addr
, 1);
1940 if (GET_CODE (op0
) == REG
)
1943 if (GET_CODE (op1
) == REG
)
1945 else if (CONSTANT_P (op1
))
1950 else if (GET_CODE (op0
) == PLUS
)
1952 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1954 ireg
= XEXP (XEXP (op0
, 0), 0);
1955 scale
= XEXP (XEXP (op0
, 0), 1);
1956 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1958 breg
= XEXP (op0
, 1);
1964 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1966 breg
= XEXP (op0
, 0);
1967 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1969 ireg
= XEXP (op0
, 1);
1978 else if (GET_CODE (op0
) == MULT
)
1980 ireg
= XEXP (op0
, 0);
1981 scale
= XEXP (op0
, 1);
1982 if (GET_CODE (op1
) == REG
)
1984 else if (CONSTANT_P (op1
))
1992 else if (GET_CODE (addr
) == MULT
)
1994 ireg
= XEXP (addr
, 0);
1995 scale
= XEXP (addr
, 1);
2001 output_addr_const (file
, offset
);
2003 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
2005 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
2008 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2009 that is a valid memory address for an instruction.
2010 The MODE argument is the machine mode for the MEM expression
2011 that wants to use this address.
2013 On 80960, legitimate addresses are:
2015 disp (12 or 32 bit) ld foo,r0
2016 base + index ld (g0)[g1*1],r0
2017 base + displ ld 0xf00(g0),r0
2018 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
2019 index*scale + base ld (g0)[g1*4],r0
2020 index*scale + displ ld 0xf00[g1*4],r0
2021 index*scale ld [g1*4],r0
2022 index + base + displ ld 0xf00(g0)[g1*1],r0
2024 In each case, scale can be 1, 2, 4, 8, or 16. */
2026 /* This is exactly the same as i960_print_operand_addr, except that
2027 it recognizes addresses instead of printing them.
2029 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2030 convert common non-canonical forms to canonical form so that they will
2033 /* These two macros allow us to accept either a REG or a SUBREG anyplace
2034 where a register is valid. */
2036 #define RTX_OK_FOR_BASE_P(X, STRICT) \
2037 ((GET_CODE (X) == REG \
2038 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
2039 || (GET_CODE (X) == SUBREG \
2040 && GET_CODE (SUBREG_REG (X)) == REG \
2041 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
2042 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
2044 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
2045 ((GET_CODE (X) == REG \
2046 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
2047 || (GET_CODE (X) == SUBREG \
2048 && GET_CODE (SUBREG_REG (X)) == REG \
2049 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
2050 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
2053 legitimate_address_p (mode
, addr
, strict
)
2054 enum machine_mode mode ATTRIBUTE_UNUSED
;
2058 if (RTX_OK_FOR_BASE_P (addr
, strict
))
2060 else if (CONSTANT_P (addr
))
2062 else if (GET_CODE (addr
) == PLUS
)
2066 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2069 op0
= XEXP (addr
, 0);
2070 op1
= XEXP (addr
, 1);
2072 if (RTX_OK_FOR_BASE_P (op0
, strict
))
2074 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
2076 else if (CONSTANT_P (op1
))
2081 else if (GET_CODE (op0
) == PLUS
)
2083 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
2085 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
2086 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
2089 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
2090 && CONSTANT_P (op1
))
2095 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
2097 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
2098 && CONSTANT_P (op1
))
2106 else if (GET_CODE (op0
) == MULT
)
2108 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
2109 && SCALE_TERM_P (XEXP (op0
, 1))))
2112 if (RTX_OK_FOR_BASE_P (op1
, strict
))
2114 else if (CONSTANT_P (op1
))
2122 else if (GET_CODE (addr
) == MULT
)
2124 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2127 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
2128 && SCALE_TERM_P (XEXP (addr
, 1)));
2134 /* Try machine-dependent ways of modifying an illegitimate address
2135 to be legitimate. If we find one, return the new, valid address.
2136 This macro is used in only one place: `memory_address' in explow.c.
2138 This converts some non-canonical addresses to canonical form so they
2139 can be recognized. */
2142 legitimize_address (x
, oldx
, mode
)
2144 register rtx oldx ATTRIBUTE_UNUSED
;
2145 enum machine_mode mode ATTRIBUTE_UNUSED
;
2147 if (GET_CODE (x
) == SYMBOL_REF
)
2150 x
= copy_to_reg (x
);
2153 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2156 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2157 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2158 created by virtual register instantiation, register elimination, and
2159 similar optimizations. */
2160 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2161 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2162 x
= gen_rtx_PLUS (Pmode
,
2163 gen_rtx_PLUS (Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2164 XEXP (XEXP (x
, 1), 1));
2166 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2167 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2168 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2169 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2170 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2171 && CONSTANT_P (XEXP (x
, 1)))
2173 rtx constant
, other
;
2175 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2177 constant
= XEXP (x
, 1);
2178 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2180 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2182 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2183 other
= XEXP (x
, 1);
2189 x
= gen_rtx_PLUS (Pmode
,
2190 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
2191 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2192 plus_constant (other
, INTVAL (constant
)));
2199 /* Return the most stringent alignment that we are willing to consider
2200 objects of size SIZE and known alignment ALIGN as having. */
2203 i960_alignment (size
, align
)
2209 if (! TARGET_STRICT_ALIGN
)
2210 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2212 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2223 hard_regno_mode_ok (regno
, mode
)
2225 enum machine_mode mode
;
2231 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2234 case DImode
: case DFmode
:
2235 return (regno
& 1) == 0;
2237 case TImode
: case XFmode
:
2238 return (regno
& 3) == 0;
2244 else if (regno
>= 32 && regno
< 36)
2248 case SFmode
: case DFmode
: case XFmode
:
2249 case SCmode
: case DCmode
:
2256 else if (regno
== 36)
2260 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2267 else if (regno
== 37)
2274 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2275 advantage of machine specific facts, such as knowing that the frame pointer
2276 is always 16 byte aligned. */
2279 i960_expr_alignment (x
, size
)
2288 switch (GET_CODE(x
))
2293 if ((align
& 0xf) == 0)
2295 else if ((align
& 0x7) == 0)
2297 else if ((align
& 0x3) == 0)
2299 else if ((align
& 0x1) == 0)
2306 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2307 i960_expr_alignment (XEXP (x
, 1), size
));
2311 /* If this is a valid program, objects are guaranteed to be
2312 correctly aligned for whatever size the reference actually is. */
2313 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2317 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2322 align
= i960_expr_alignment (XEXP (x
, 0), size
);
2324 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2326 align
= align
<< INTVAL (XEXP (x
, 1));
2327 align
= MIN (align
, 16);
2332 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2333 i960_expr_alignment (XEXP (x
, 1), size
));
2335 align
= MIN (align
, 16);
2344 /* Return true if it is possible to reference both BASE and OFFSET, which
2345 have alignment at least as great as 4 byte, as if they had alignment valid
2346 for an object of size SIZE. */
2349 i960_improve_align (base
, offset
, size
)
2356 /* We have at least a word reference to the object, so we know it has to
2357 be aligned at least to 4 bytes. */
2359 i
= MIN (i960_expr_alignment (base
, 4),
2360 i960_expr_alignment (offset
, 4));
2364 /* We know the size of the request. If strict align is not enabled, we
2365 can guess that the alignment is OK for the requested size. */
2367 if (! TARGET_STRICT_ALIGN
)
2368 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2374 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2375 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2378 i960_si_ti (base
, offset
)
2382 return i960_improve_align (base
, offset
, 16);
2385 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2386 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2389 i960_si_di (base
, offset
)
2393 return i960_improve_align (base
, offset
, 8);
2396 /* Return raw values of size and alignment (in words) for the data
2397 type being accessed. These values will be rounded by the caller. */
2400 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2401 enum machine_mode mode
;
2408 /* Use formal alignment requirements of type being passed, except make
2409 it at least a word. If we don't have a type, this is a library call,
2410 and the parm has to be of scalar type. In this case, consider its
2411 formal alignment requirement to be its size in words. */
2413 if (mode
== BLKmode
)
2414 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2415 else if (mode
== VOIDmode
)
2417 /* End of parm list. */
2418 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2423 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2427 /* ??? This is a hack to properly correct the alignment of XFmode
2428 values without affecting anything else. */
2434 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2435 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2443 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2444 Any arg that is bigger than 4 words is placed on the stack and all
2445 subsequent arguments are placed on the stack.
2447 Additionally, parameters with an alignment requirement stronger than
2448 a word must be aligned appropriately. Note that this means that a
2449 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2450 passed in an odd/even register pair. */
2452 /* Update CUM to advance past an argument described by MODE and TYPE. */
2455 i960_function_arg_advance (cum
, mode
, type
, named
)
2456 CUMULATIVE_ARGS
*cum
;
2457 enum machine_mode mode
;
2459 int named ATTRIBUTE_UNUSED
;
2463 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2465 if (size
> 4 || cum
->ca_nstackparms
!= 0
2466 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2467 || MUST_PASS_IN_STACK (mode
, type
))
2469 /* Indicate that all the registers are in use, even if all are not,
2470 so va_start will compute the right value. */
2471 cum
->ca_nregparms
= NPARM_REGS
;
2472 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2475 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2478 /* Return the register that the argument described by MODE and TYPE is
2479 passed in, or else return 0 if it is passed on the stack. */
2482 i960_function_arg (cum
, mode
, type
, named
)
2483 CUMULATIVE_ARGS
*cum
;
2484 enum machine_mode mode
;
2486 int named ATTRIBUTE_UNUSED
;
2491 if (mode
== VOIDmode
)
2494 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2496 if (size
> 4 || cum
->ca_nstackparms
!= 0
2497 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2498 || MUST_PASS_IN_STACK (mode
, type
))
2500 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2505 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2506 ret
= gen_rtx_REG (mode
, cum
->ca_nregparms
);
2512 /* Floating-point support. */
2515 i960_output_long_double (file
, value
)
2517 REAL_VALUE_TYPE value
;
2522 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2523 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2526 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2527 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2528 fprintf (file
, "\t.word\t0x0\n");
2532 i960_output_double (file
, value
)
2534 REAL_VALUE_TYPE value
;
2539 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2540 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2542 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2543 value_long
[0], dstr
, value_long
[1]);
2547 i960_output_float (file
, value
)
2549 REAL_VALUE_TYPE value
;
2554 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2555 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2557 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2560 /* Return the number of bits that an object of size N bytes is aligned to. */
2563 i960_object_bytes_bitalign (n
)
2567 else if (n
> 4) n
= 64;
2568 else if (n
> 2) n
= 32;
2569 else if (n
> 1) n
= 16;
2575 /* Compute the alignment for an aggregate type TSIZE.
2576 Alignment is MAX (greatest member alignment,
2577 MIN (pragma align, structure size alignment)). */
2580 i960_round_align (align
, tsize
)
2586 if (! tsize
|| TREE_CODE (tsize
) != INTEGER_CST
)
2589 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2591 /* Handle #pragma align. */
2592 if (new_align
> i960_maxbitalignment
)
2593 new_align
= i960_maxbitalignment
;
2595 if (align
< new_align
)
2601 /* Do any needed setup for a varargs function. For the i960, we must
2602 create a register parameter block if one doesn't exist, and then copy
2603 all register parameters to memory. */
2606 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2607 CUMULATIVE_ARGS
*cum
;
2608 enum machine_mode mode ATTRIBUTE_UNUSED
;
2609 tree type ATTRIBUTE_UNUSED
;
2610 int *pretend_size ATTRIBUTE_UNUSED
;
2613 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2614 int first_reg
= cum
->ca_nregparms
;
2616 /* Copy only unnamed register arguments to memory. If there are
2617 any stack parms, there are no unnamed arguments in registers, and
2618 an argument block was already allocated by the caller.
2619 Remember that any arg bigger than 4 words is passed on the stack as
2620 are all subsequent args.
2622 If there are no stack arguments but there are exactly NPARM_REGS
2623 registers, either there were no extra arguments or the caller
2624 allocated an argument block. */
2626 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2628 rtx label
= gen_label_rtx ();
2631 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2632 and we need to allocate a chunk to save the registers (if any
2633 arguments were passed on the stack the caller would allocate the
2634 48 bytes as well). We must allocate all 48 bytes (12*4) because
2635 va_start assumes it. */
2636 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2637 emit_jump_insn (gen_bne (label
));
2638 emit_insn (gen_rtx_SET (VOIDmode
, arg_pointer_rtx
,
2639 stack_pointer_rtx
));
2640 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
2641 memory_address (SImode
,
2642 plus_constant (stack_pointer_rtx
,
2646 /* ??? Note that we unnecessarily store one extra register for stdarg
2647 fns. We could optimize this, but it's kept as for now. */
2648 regblock
= gen_rtx_MEM (BLKmode
,
2649 plus_constant (arg_pointer_rtx
,
2651 MEM_ALIAS_SET (regblock
) = get_varargs_alias_set ();
2652 move_block_from_reg (first_reg
, regblock
,
2653 NPARM_REGS
- first_reg
,
2654 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2658 /* Define the `__builtin_va_list' type for the ABI. */
2661 i960_build_va_list ()
2663 return build_array_type (unsigned_type_node
,
2664 build_index_type (size_one_node
));
2667 /* Implement `va_start' for varargs and stdarg. */
2670 i960_va_start (stdarg_p
, valist
, nextarg
)
2671 int stdarg_p ATTRIBUTE_UNUSED
;
2673 rtx nextarg ATTRIBUTE_UNUSED
;
2675 tree s
, t
, base
, num
;
2677 /* The array type always decays to a pointer before we get here, so we
2678 can't use ARRAY_REF. */
2679 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2680 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2681 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2682 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2684 s
= make_tree (unsigned_type_node
, arg_pointer_rtx
);
2685 t
= build (MODIFY_EXPR
, unsigned_type_node
, base
, s
);
2686 TREE_SIDE_EFFECTS (t
) = 1;
2687 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2689 s
= build_int_2 ((current_function_args_info
.ca_nregparms
2690 + current_function_args_info
.ca_nstackparms
) * 4, 0);
2691 t
= build (MODIFY_EXPR
, unsigned_type_node
, num
, s
);
2692 TREE_SIDE_EFFECTS (t
) = 1;
2693 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2696 /* Implement `va_arg'. */
2699 i960_va_arg (valist
, type
)
2702 HOST_WIDE_INT siz
, ali
;
2703 tree base
, num
, pad
, next
, this, t1
, t2
, int48
;
2706 /* The array type always decays to a pointer before we get here, so we
2707 can't use ARRAY_REF. */
2708 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2709 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2710 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2711 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2713 /* Round up sizeof(type) to a word. */
2714 siz
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
2716 /* Round up alignment to a word. */
2717 ali
= TYPE_ALIGN (type
);
2718 if (ali
< BITS_PER_WORD
)
2719 ali
= BITS_PER_WORD
;
2720 ali
/= BITS_PER_UNIT
;
2722 /* Align NUM appropriate for the argument. */
2723 pad
= fold (build (PLUS_EXPR
, unsigned_type_node
, num
,
2724 build_int_2 (ali
- 1, 0)));
2725 pad
= fold (build (BIT_AND_EXPR
, unsigned_type_node
, pad
,
2726 build_int_2 (-ali
, -1)));
2727 pad
= save_expr (pad
);
2729 /* Increment VPAD past this argument. */
2730 next
= fold (build (PLUS_EXPR
, unsigned_type_node
, pad
,
2731 build_int_2 (siz
, 0)));
2732 next
= save_expr (next
);
2734 /* Find the offset for the current argument. Mind peculiar overflow
2735 from registers to stack. */
2736 int48
= build_int_2 (48, 0);
2738 t2
= integer_one_node
;
2740 t2
= fold (build (GT_EXPR
, integer_type_node
, next
, int48
));
2741 t1
= fold (build (LE_EXPR
, integer_type_node
, num
, int48
));
2742 t1
= fold (build (TRUTH_AND_EXPR
, integer_type_node
, t1
, t2
));
2743 this = fold (build (COND_EXPR
, unsigned_type_node
, t1
, int48
, pad
));
2745 /* Find the address for the current argument. */
2746 t1
= fold (build (PLUS_EXPR
, unsigned_type_node
, base
, this));
2747 t1
= build1 (NOP_EXPR
, ptr_type_node
, t1
);
2748 addr_rtx
= expand_expr (t1
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
2750 /* Increment NUM. */
2751 t1
= build (MODIFY_EXPR
, unsigned_type_node
, num
, next
);
2752 TREE_SIDE_EFFECTS (t1
) = 1;
2753 expand_expr (t1
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2758 /* Calculate the final size of the reg parm stack space for the current
2759 function, based on how many bytes would be allocated on the stack. */
2762 i960_final_reg_parm_stack_space (const_size
, var_size
)
2766 if (var_size
|| const_size
> 48)
2772 /* Calculate the size of the reg parm stack space. This is a bit complicated
2776 i960_reg_parm_stack_space (fndecl
)
2779 /* In this case, we are called from emit_library_call, and we don't need
2780 to pretend we have more space for parameters than what's apparent. */
2784 /* In this case, we are called from locate_and_pad_parms when we're
2785 not IN_REGS, so we have an arg block. */
2786 if (fndecl
!= current_function_decl
)
2789 /* Otherwise, we have an arg block if the current function has more than
2790 48 bytes of parameters. */
2791 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2797 /* Return the register class of a scratch register needed to copy IN into
2798 or out of a register in CLASS in MODE. If it can be done directly,
2799 NO_REGS is returned. */
2802 secondary_reload_class (class, mode
, in
)
2803 enum reg_class
class;
2804 enum machine_mode mode
;
2809 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2810 regno
= true_regnum (in
);
2812 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2813 LOCAL_OR_GLOBAL_REGS into anything. */
2814 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2815 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2818 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2819 if (class == FP_REGS
2820 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2821 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2824 return LOCAL_OR_GLOBAL_REGS
;
2827 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2828 function unit it executed on. */
2830 /* ??? This would make more sense as an attribute. */
2833 i960_scan_opcode (p
)
2845 /* Ret is not actually of type REG, but it won't matter, because no
2846 insn will ever follow it. */
2849 i960_last_insn_type
= I_TYPE_REG
;
2853 if (p
[1] == 'x' || p
[3] == 'x')
2854 i960_last_insn_type
= I_TYPE_MEM
;
2855 i960_last_insn_type
= I_TYPE_CTRL
;
2860 i960_last_insn_type
= I_TYPE_CTRL
;
2867 i960_last_insn_type
= I_TYPE_MEM
;
2869 i960_last_insn_type
= I_TYPE_CTRL
;
2871 else if (p
[1] == 'm')
2874 i960_last_insn_type
= I_TYPE_REG
;
2875 else if (p
[4] == 'b' || p
[4] == 'j')
2876 i960_last_insn_type
= I_TYPE_CTRL
;
2878 i960_last_insn_type
= I_TYPE_REG
;
2881 i960_last_insn_type
= I_TYPE_REG
;
2885 i960_last_insn_type
= I_TYPE_MEM
;
2890 i960_last_insn_type
= I_TYPE_MEM
;
2892 i960_last_insn_type
= I_TYPE_REG
;