1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
47 static void i960_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
48 static void i960_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
50 /* Save the operands last given to a compare for use when we
51 generate a scc or bcc insn. */
53 rtx i960_compare_op0
, i960_compare_op1
;
55 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
58 int i960_maxbitalignment
;
59 int i960_last_maxbitalignment
;
61 /* Used to implement switching between MEM and ALU insn types, for better
62 C series performance. */
64 enum insn_types i960_last_insn_type
;
66 /* The leaf-procedure return register. Set only if this is a leaf routine. */
68 static int i960_leaf_ret_reg
;
70 /* True if replacing tail calls with jumps is OK. */
72 static int tail_call_ok
;
74 /* A string containing a list of insns to emit in the epilogue so as to
75 restore all registers saved by the prologue. Created by the prologue
76 code as it saves registers away. */
78 char epilogue_string
[1000];
80 /* A unique number (per function) for return labels. */
82 static int ret_label
= 0;
84 /* This is true if FNDECL is either a varargs or a stdarg function.
85 This is used to help identify functions that use an argument block. */
87 #define VARARGS_STDARG_FUNCTION(FNDECL) \
88 (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
89 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL))))) \
92 /* Initialize the GCC target structure. */
93 #undef TARGET_ASM_ALIGNED_SI_OP
94 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
96 #undef TARGET_ASM_FUNCTION_PROLOGUE
97 #define TARGET_ASM_FUNCTION_PROLOGUE i960_output_function_prologue
98 #undef TARGET_ASM_FUNCTION_EPILOGUE
99 #define TARGET_ASM_FUNCTION_EPILOGUE i960_output_function_epilogue
101 struct gcc_target targetm
= TARGET_INITIALIZER
;
103 /* Override conflicting target switch options.
104 Doesn't actually detect if more than one -mARCH option is given, but
105 does handle the case of two blatantly conflicting -mARCH options.
107 Also initialize variables before compiling any files. */
112 if (TARGET_K_SERIES
&& TARGET_C_SERIES
)
114 warning ("conflicting architectures defined - using C series");
115 target_flags
&= ~TARGET_FLAG_K_SERIES
;
117 if (TARGET_K_SERIES
&& TARGET_MC
)
119 warning ("conflicting architectures defined - using K series");
120 target_flags
&= ~TARGET_FLAG_MC
;
122 if (TARGET_C_SERIES
&& TARGET_MC
)
124 warning ("conflicting architectures defined - using C series");
125 target_flags
&= ~TARGET_FLAG_MC
;
127 if (TARGET_IC_COMPAT3_0
)
129 flag_short_enums
= 1;
130 flag_signed_char
= 1;
131 target_flags
|= TARGET_FLAG_CLEAN_LINKAGE
;
132 if (TARGET_IC_COMPAT2_0
)
134 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0");
135 target_flags
&= ~TARGET_FLAG_IC_COMPAT2_0
;
138 if (TARGET_IC_COMPAT2_0
)
140 flag_signed_char
= 1;
141 target_flags
|= TARGET_FLAG_CLEAN_LINKAGE
;
144 if (TARGET_IC_COMPAT2_0
)
146 i960_maxbitalignment
= 8;
147 i960_last_maxbitalignment
= 128;
151 i960_maxbitalignment
= 128;
152 i960_last_maxbitalignment
= 8;
155 /* Tell the compiler which flavor of XFmode we're using. */
156 real_format_for_mode
[XFmode
- QFmode
] = &ieee_extended_intel_96_format
;
159 /* Return true if OP can be used as the source of an fp move insn. */
162 fpmove_src_operand (op
, mode
)
164 enum machine_mode mode
;
166 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
170 /* Return true if OP is a register or zero. */
173 reg_or_zero_operand (op
, mode
)
175 enum machine_mode mode
;
177 return register_operand (op
, mode
) || op
== const0_rtx
;
181 /* Return truth value of whether OP can be used as an operands in a three
182 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
185 arith_operand (op
, mode
)
187 enum machine_mode mode
;
189 return (register_operand (op
, mode
) || literal (op
, mode
));
192 /* Return truth value of whether OP can be used as an operands in a three
193 address logic insn, possibly complementing OP, of mode MODE. */
196 logic_operand (op
, mode
)
198 enum machine_mode mode
;
200 return (register_operand (op
, mode
)
201 || (GET_CODE (op
) == CONST_INT
202 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
205 /* Return true if OP is a register or a valid floating point literal. */
208 fp_arith_operand (op
, mode
)
210 enum machine_mode mode
;
212 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
215 /* Return true if OP is a register or a valid signed integer literal. */
218 signed_arith_operand (op
, mode
)
220 enum machine_mode mode
;
222 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
225 /* Return truth value of whether OP is an integer which fits the
226 range constraining immediate operands in three-address insns. */
231 enum machine_mode mode ATTRIBUTE_UNUSED
;
233 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
236 /* Return true if OP is a float constant of 1. */
239 fp_literal_one (op
, mode
)
241 enum machine_mode mode
;
243 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
246 /* Return true if OP is a float constant of 0. */
249 fp_literal_zero (op
, mode
)
251 enum machine_mode mode
;
253 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
256 /* Return true if OP is a valid floating point literal. */
261 enum machine_mode mode
;
263 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
266 /* Return true if OP is a valid signed immediate constant. */
269 signed_literal(op
, mode
)
271 enum machine_mode mode ATTRIBUTE_UNUSED
;
273 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
276 /* Return truth value of statement that OP is a symbolic memory
277 operand of mode MODE. */
280 symbolic_memory_operand (op
, mode
)
282 enum machine_mode mode ATTRIBUTE_UNUSED
;
284 if (GET_CODE (op
) == SUBREG
)
285 op
= SUBREG_REG (op
);
286 if (GET_CODE (op
) != MEM
)
289 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
290 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
293 /* Return truth value of whether OP is EQ or NE. */
298 enum machine_mode mode ATTRIBUTE_UNUSED
;
300 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
303 /* OP is an integer register or a constant. */
306 arith32_operand (op
, mode
)
308 enum machine_mode mode
;
310 if (register_operand (op
, mode
))
312 return (CONSTANT_P (op
));
315 /* Return true if OP is an integer constant which is a power of 2. */
318 power2_operand (op
,mode
)
320 enum machine_mode mode ATTRIBUTE_UNUSED
;
322 if (GET_CODE (op
) != CONST_INT
)
325 return exact_log2 (INTVAL (op
)) >= 0;
328 /* Return true if OP is an integer constant which is the complement of a
332 cmplpower2_operand (op
, mode
)
334 enum machine_mode mode ATTRIBUTE_UNUSED
;
336 if (GET_CODE (op
) != CONST_INT
)
339 return exact_log2 (~ INTVAL (op
)) >= 0;
342 /* If VAL has only one bit set, return the index of that bit. Otherwise
351 for (i
= 0; val
!= 0; i
++, val
>>= 1)
363 /* Return nonzero if OP is a mask, i.e. all one bits are consecutive.
364 The return value indicates how many consecutive nonzero bits exist
365 if this is a mask. This is the same as the next function, except that
366 it does not indicate what the start and stop bit positions are. */
372 register int start
, end
= 0, i
;
375 for (i
= 0; val
!= 0; val
>>= 1, i
++)
385 /* Still looking for the first bit. */
389 /* We've seen the start of a bit sequence, and now a zero. There
390 must be more one bits, otherwise we would have exited the loop.
391 Therefore, it is not a mask. */
396 /* The bit string has ones from START to END bit positions only. */
397 return end
- start
+ 1;
400 /* If VAL is a mask, then return nonzero, with S set to the starting bit
401 position and E set to the ending bit position of the mask. The return
402 value indicates how many consecutive bits exist in the mask. This is
403 the same as the previous function, except that it also indicates the
404 start and end bit positions of the mask. */
411 register int start
, end
, i
;
415 for (i
= 0; val
!= 0; val
>>= 1, i
++)
426 /* Still looking for the first bit. */
430 /* We've seen the start of a bit sequence, and now a zero. There
431 must be more one bits, otherwise we would have exited the loop.
432 Therefor, it is not a mask. */
441 /* The bit string has ones from START to END bit positions only. */
444 return ((start
< 0) ? 0 : end
- start
+ 1);
447 /* Return the machine mode to use for a comparison. */
450 select_cc_mode (op
, x
)
452 rtx x ATTRIBUTE_UNUSED
;
454 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
459 /* X and Y are two things to compare using CODE. Emit the compare insn and
460 return the rtx for register 36 in the proper mode. */
463 gen_compare_reg (code
, x
, y
)
468 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
469 enum machine_mode mode
470 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
474 if (! arith_operand (x
, mode
))
475 x
= force_reg (SImode
, x
);
476 if (! arith_operand (y
, mode
))
477 y
= force_reg (SImode
, y
);
480 cc_reg
= gen_rtx_REG (ccmode
, 36);
481 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
482 gen_rtx_COMPARE (ccmode
, x
, y
)));
487 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
488 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
489 are 4. Indexed addresses are cost 6. */
491 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
494 i960_address_cost (x
)
498 /* Handled before calling here. */
499 if (GET_CODE (x
) == REG
)
502 /* This is a MEMA operand -- it's free. */
503 if (GET_CODE (x
) == CONST_INT
505 && INTVAL (x
) < 4096)
508 if (GET_CODE (x
) == PLUS
)
510 rtx base
= XEXP (x
, 0);
511 rtx offset
= XEXP (x
, 1);
513 if (GET_CODE (base
) == SUBREG
)
514 base
= SUBREG_REG (base
);
515 if (GET_CODE (offset
) == SUBREG
)
516 offset
= SUBREG_REG (offset
);
518 if (GET_CODE (base
) == REG
)
520 if (GET_CODE (offset
) == REG
)
522 if (GET_CODE (offset
) == CONST_INT
)
524 if ((unsigned)INTVAL (offset
) < 2047)
528 if (CONSTANT_P (offset
))
531 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
534 /* This is an invalid address. The return value doesn't matter, but
535 for convenience we make this more expensive than anything else. */
538 if (GET_CODE (x
) == MULT
)
541 /* Symbol_refs and other unrecognized addresses are cost 4. */
545 /* Emit insns to move operands[1] into operands[0].
547 Return 1 if we have written out everything that needs to be done to
548 do the move. Otherwise, return 0 and the caller will emit the move
552 emit_move_sequence (operands
, mode
)
554 enum machine_mode mode
;
556 /* We can only store registers to memory. */
558 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
559 && (operands
[1] != const0_rtx
|| current_function_args_size
560 || current_function_stdarg
561 || rtx_equal_function_value_matters
))
562 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
563 operands
[1] = force_reg (mode
, operands
[1]);
565 /* Storing multi-word values in unaligned hard registers to memory may
566 require a scratch since we have to store them a register at a time and
567 adding 4 to the memory address may not yield a valid insn. */
568 /* ??? We don't always need the scratch, but that would complicate things.
570 /* ??? We must also handle stores to pseudos here, because the pseudo may be
571 replaced with a MEM later. This would be cleaner if we didn't have
572 a separate pattern for unaligned DImode/TImode stores. */
573 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
574 && (GET_CODE (operands
[0]) == MEM
575 || (GET_CODE (operands
[0]) == REG
576 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
577 && GET_CODE (operands
[1]) == REG
578 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
579 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
581 emit_insn (gen_rtx_PARALLEL
584 gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]),
585 gen_rtx_CLOBBER (VOIDmode
,
586 gen_rtx_SCRATCH (Pmode
)))));
593 /* Output assembler to move a double word value. */
596 i960_output_move_double (dst
, src
)
601 if (GET_CODE (dst
) == REG
602 && GET_CODE (src
) == REG
)
604 if ((REGNO (src
) & 1)
605 || (REGNO (dst
) & 1))
607 /* We normally copy the low-numbered register first. However, if
608 the second source register is the same as the first destination
609 register, we must copy in the opposite order. */
610 if (REGNO (src
) + 1 == REGNO (dst
))
611 return "mov %D1,%D0\n\tmov %1,%0";
613 return "mov %1,%0\n\tmov %D1,%D0";
618 else if (GET_CODE (dst
) == REG
619 && GET_CODE (src
) == CONST_INT
620 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
623 return "mov %1,%0\n\tmov 0,%D0";
627 else if (GET_CODE (dst
) == REG
628 && GET_CODE (src
) == MEM
)
632 /* One can optimize a few cases here, but you have to be
633 careful of clobbering registers used in the address and
637 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 1);
638 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
639 operands
[4] = adjust_address (operands
[3], word_mode
,
642 ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
648 else if (GET_CODE (dst
) == MEM
649 && GET_CODE (src
) == REG
)
654 operands
[1] = adjust_address (dst
, word_mode
, UNITS_PER_WORD
);
655 if (! memory_address_p (word_mode
, XEXP (operands
[1], 0)))
658 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands
);
667 /* Output assembler to move a double word zero. */
670 i960_output_move_double_zero (dst
)
677 operands
[1] = adjust_address (dst
, word_mode
, 4);
678 output_asm_insn ("st g14,%0\n\tst g14,%1", operands
);
683 /* Output assembler to move a quad word value. */
686 i960_output_move_quad (dst
, src
)
691 if (GET_CODE (dst
) == REG
692 && GET_CODE (src
) == REG
)
694 if ((REGNO (src
) & 3)
695 || (REGNO (dst
) & 3))
697 /* We normally copy starting with the low numbered register.
698 However, if there is an overlap such that the first dest reg
699 is <= the last source reg but not < the first source reg, we
700 must copy in the opposite order. */
701 if (REGNO (dst
) <= REGNO (src
) + 3
702 && REGNO (dst
) >= REGNO (src
))
703 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
705 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
710 else if (GET_CODE (dst
) == REG
711 && GET_CODE (src
) == CONST_INT
712 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
715 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
719 else if (GET_CODE (dst
) == REG
720 && GET_CODE (src
) == MEM
)
724 /* One can optimize a few cases here, but you have to be
725 careful of clobbering registers used in the address and
729 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 3);
730 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
732 = adjust_address (operands
[3], word_mode
, UNITS_PER_WORD
);
734 = adjust_address (operands
[4], word_mode
, UNITS_PER_WORD
);
736 = adjust_address (operands
[5], word_mode
, UNITS_PER_WORD
);
737 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
743 else if (GET_CODE (dst
) == MEM
744 && GET_CODE (src
) == REG
)
749 operands
[1] = adjust_address (dst
, word_mode
, UNITS_PER_WORD
);
750 operands
[2] = adjust_address (dst
, word_mode
, 2 * UNITS_PER_WORD
);
751 operands
[3] = adjust_address (dst
, word_mode
, 3 * UNITS_PER_WORD
);
752 if (! memory_address_p (word_mode
, XEXP (operands
[3], 0)))
755 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands
);
764 /* Output assembler to move a quad word zero. */
767 i960_output_move_quad_zero (dst
)
774 operands
[1] = adjust_address (dst
, word_mode
, 4);
775 operands
[2] = adjust_address (dst
, word_mode
, 8);
776 operands
[3] = adjust_address (dst
, word_mode
, 12);
777 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands
);
783 /* Emit insns to load a constant to non-floating point registers.
784 Uses several strategies to try to use as few insns as possible. */
787 i960_output_ldconst (dst
, src
)
788 register rtx dst
, src
;
791 register unsigned rsrc2
;
792 enum machine_mode mode
= GET_MODE (dst
);
795 operands
[0] = operands
[2] = dst
;
796 operands
[1] = operands
[3] = src
;
798 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
799 must be a ldconst insn. */
801 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
803 output_asm_insn ("ldconst %1,%0", operands
);
806 else if (mode
== XFmode
)
812 if (fp_literal_zero (src
, XFmode
))
815 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
816 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
818 output_asm_insn ("# ldconst %1,%0",operands
);
820 for (i
= 0; i
< 3; i
++)
822 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + i
);
823 operands
[1] = GEN_INT (value_long
[i
]);
824 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
830 else if (mode
== DFmode
)
834 if (fp_literal_zero (src
, DFmode
))
837 split_double (src
, &first
, &second
);
839 output_asm_insn ("# ldconst %1,%0",operands
);
841 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
843 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
845 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
846 operands
[1] = second
;
847 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
851 else if (mode
== SFmode
)
856 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
857 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
859 output_asm_insn ("# ldconst %1,%0",operands
);
860 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
861 operands
[1] = GEN_INT (value
);
862 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
866 else if (mode
== TImode
)
868 /* ??? This is currently not handled at all. */
871 /* Note: lowest order word goes in lowest numbered reg. */
872 rsrc1
= INTVAL (src
);
873 if (rsrc1
>= 0 && rsrc1
< 32)
876 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
877 /* Go pick up the low-order word. */
879 else if (mode
== DImode
)
881 rtx upperhalf
, lowerhalf
, xoperands
[2];
883 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
884 split_double (src
, &lowerhalf
, &upperhalf
);
889 /* Note: lowest order word goes in lowest numbered reg. */
890 /* Numbers from 0 to 31 can be handled with a single insn. */
891 rsrc1
= INTVAL (lowerhalf
);
892 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
895 /* Output the upper half with a recursive call. */
896 xoperands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
897 xoperands
[1] = upperhalf
;
898 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
900 /* The lower word is emitted as normally. */
904 rsrc1
= INTVAL (src
);
910 else if (mode
== HImode
)
919 /* ldconst 0..31,X -> mov 0..31,X */
922 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
927 /* ldconst 32..63,X -> add 31,nn,X */
930 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
932 operands
[1] = GEN_INT (rsrc1
- 31);
933 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
939 /* ldconst -1..-31 -> sub 0,0..31,X */
942 /* return 'sub -(%1),0,%0' */
943 operands
[1] = GEN_INT (- rsrc1
);
944 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
948 /* ldconst -32 -> not 31,X */
951 operands
[1] = GEN_INT (~rsrc1
);
952 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
957 /* If const is a single bit. */
958 if (bitpos (rsrc1
) >= 0)
960 operands
[1] = GEN_INT (bitpos (rsrc1
));
961 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
965 /* If const is a bit string of less than 6 bits (1..31 shifted). */
970 if (bitstr (rsrc1
, &s
, &e
) < 6)
972 rsrc2
= ((unsigned int) rsrc1
) >> s
;
973 operands
[1] = GEN_INT (rsrc2
);
974 operands
[2] = GEN_INT (s
);
975 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
980 /* Unimplemented cases:
981 const is in range 0..31 but rotated around end of word:
982 ror 31,3,g0 -> ldconst 0xe0000003,g0
984 and any 2 instruction cases that might be worthwhile */
986 output_asm_insn ("ldconst %1,%0", operands
);
990 /* Determine if there is an opportunity for a bypass optimization.
991 Bypass succeeds on the 960K* if the destination of the previous
992 instruction is the second operand of the current instruction.
993 Bypass always succeeds on the C*.
995 Return 1 if the pattern should interchange the operands.
997 CMPBR_FLAG is true if this is for a compare-and-branch insn.
998 OP1 and OP2 are the two source operands of a 3 operand insn. */
1001 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
1002 register rtx insn
, op1
, op2
;
1005 register rtx prev_insn
, prev_dest
;
1007 if (TARGET_C_SERIES
)
1010 /* Can't do this if op1 isn't a register. */
1014 /* Can't do this for a compare-and-branch if both ops aren't regs. */
1015 if (cmpbr_flag
&& ! REG_P (op2
))
1018 prev_insn
= prev_real_insn (insn
);
1020 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
1021 && GET_CODE (PATTERN (prev_insn
)) == SET
)
1023 prev_dest
= SET_DEST (PATTERN (prev_insn
));
1024 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
1025 || (GET_CODE (prev_dest
) == SUBREG
1026 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
1027 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
1033 /* Output the code which declares the function name. This also handles
1034 leaf routines, which have special requirements, and initializes some
1035 global variables. */
1038 i960_function_name_declare (file
, name
, fndecl
)
1047 /* Increment global return label. */
1051 /* Compute whether tail calls and leaf routine optimizations can be performed
1052 for this function. */
1054 if (TARGET_TAILCALL
)
1059 if (TARGET_LEAFPROC
)
1064 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1065 argblock, because argblock uses g14 implicitly. */
1067 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1073 /* See if caller passes in an address to return value. */
1075 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1081 /* Can not use tail calls or make this a leaf routine if there is a non
1084 if (get_frame_size () != 0)
1087 /* I don't understand this condition, and do not think that it is correct.
1088 Apparently this is just checking whether the frame pointer is used, and
1089 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1092 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1093 if (GET_CODE (insn
) == INSN
1094 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1100 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1103 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1104 if (GET_CODE (insn
) == CALL_INSN
)
1110 /* Can not be a leaf routine if any non-call clobbered registers are
1111 used in this function. */
1114 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1115 if (regs_ever_live
[i
]
1116 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1118 /* Global registers. */
1119 if (i
< 16 && i
> 7 && i
!= 13)
1121 /* Local registers. */
1126 /* Now choose a leaf return register, if we can find one, and if it is
1127 OK for this to be a leaf routine. */
1129 i960_leaf_ret_reg
= -1;
1131 if (optimize
&& leaf_proc_ok
)
1133 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1134 if (regs_ever_live
[i
] == 0)
1136 i960_leaf_ret_reg
= i
;
1137 regs_ever_live
[i
] = 1;
1142 /* Do this after choosing the leaf return register, so it will be listed
1143 if one was chosen. */
1145 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1146 fprintf (file
, "\t# Registers used: ");
1148 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1150 if (regs_ever_live
[i
])
1152 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1154 if (i
> 15 && j
== 0)
1156 fprintf (file
,"\n\t#\t\t ");
1162 fprintf (file
, "\n");
1164 if (i960_leaf_ret_reg
>= 0)
1166 /* Make it a leaf procedure. */
1168 if (TREE_PUBLIC (fndecl
))
1169 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1171 fprintf (file
, "\t.leafproc\t");
1172 assemble_name (file
, name
);
1173 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1174 ASM_OUTPUT_LABEL (file
, name
);
1175 fprintf (file
, "\tlda Li960R%d,g14\n", ret_label
);
1176 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1177 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1179 if (TARGET_C_SERIES
)
1181 fprintf (file
, "\tlda 0,g14\n");
1182 i960_last_insn_type
= I_TYPE_MEM
;
1186 fprintf (file
, "\tmov 0,g14\n");
1187 i960_last_insn_type
= I_TYPE_REG
;
1192 ASM_OUTPUT_LABEL (file
, name
);
1193 i960_last_insn_type
= I_TYPE_CTRL
;
1197 /* Compute and return the frame size. */
1200 compute_frame_size (size
)
1204 int outgoing_args_size
= current_function_outgoing_args_size
;
1206 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1207 as size is concerned. */
1208 actual_fsize
= (size
+ 15) & -16;
1209 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1211 return actual_fsize
;
1214 /* Here register group is range of registers which can be moved by
1215 one i960 instruction. */
1223 static int i960_form_reg_groups
PARAMS ((int, int, int *, int, struct reg_group
*));
1224 static int i960_reg_group_compare
PARAMS ((const void *, const void *));
1225 static int i960_split_reg_group
PARAMS ((struct reg_group
*, int, int));
1226 static void i960_arg_size_and_align
PARAMS ((enum machine_mode
, tree
, int *, int *));
1228 /* The following functions forms the biggest as possible register
1229 groups with registers in STATE. REGS contain states of the
1230 registers in range [start, finish_reg). The function returns the
1231 number of groups formed. */
1233 i960_form_reg_groups (start_reg
, finish_reg
, regs
, state
, reg_groups
)
1238 struct reg_group
*reg_groups
;
1243 for (i
= start_reg
; i
< finish_reg
; )
1245 if (regs
[i
] != state
)
1250 else if (i
% 2 != 0 || regs
[i
+ 1] != state
)
1251 reg_groups
[nw
].length
= 1;
1252 else if (i
% 4 != 0 || regs
[i
+ 2] != state
)
1253 reg_groups
[nw
].length
= 2;
1254 else if (regs
[i
+ 3] != state
)
1255 reg_groups
[nw
].length
= 3;
1257 reg_groups
[nw
].length
= 4;
1258 reg_groups
[nw
].start_reg
= i
;
1259 i
+= reg_groups
[nw
].length
;
1265 /* We sort register winodws in descending order by length. */
1267 i960_reg_group_compare (group1
, group2
)
1271 const struct reg_group
*w1
= group1
;
1272 const struct reg_group
*w2
= group2
;
1274 if (w1
->length
> w2
->length
)
1276 else if (w1
->length
< w2
->length
)
1282 /* Split the first register group in REG_GROUPS on subgroups one of
1283 which will contain SUBGROUP_LENGTH registers. The function
1284 returns new number of winodws. */
1286 i960_split_reg_group (reg_groups
, nw
, subgroup_length
)
1287 struct reg_group
*reg_groups
;
1289 int subgroup_length
;
1291 if (subgroup_length
< reg_groups
->length
- subgroup_length
)
1292 /* This guarantees correct alignments of the two subgroups for
1293 i960 (see spliting for the group length 2, 3, 4). More
1294 generalized algorithm would require splitting the group more
1296 subgroup_length
= reg_groups
->length
- subgroup_length
;
1297 /* More generalized algorithm would require to try merging
1298 subgroups here. But in case i960 it always results in failure
1299 because of register group alignment. */
1300 reg_groups
[nw
].length
= reg_groups
->length
- subgroup_length
;
1301 reg_groups
[nw
].start_reg
= reg_groups
->start_reg
+ subgroup_length
;
1303 reg_groups
->length
= subgroup_length
;
1304 qsort (reg_groups
, nw
, sizeof (struct reg_group
), i960_reg_group_compare
);
1308 /* Output code for the function prologue. */
1311 i960_output_function_prologue (file
, size
)
1315 register int i
, j
, nr
;
1316 int n_saved_regs
= 0;
1317 int n_remaining_saved_regs
;
1318 HOST_WIDE_INT lvar_size
;
1319 HOST_WIDE_INT actual_fsize
, offset
;
1321 struct reg_group
*g
, *l
;
1323 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1325 int regs
[FIRST_PSEUDO_REGISTER
];
1326 /* All global registers (which must be saved) divided by groups. */
1327 struct reg_group global_reg_groups
[16];
1328 /* All local registers (which are available) divided by groups. */
1329 struct reg_group local_reg_groups
[16];
1332 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1333 if (regs_ever_live
[i
]
1334 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12))
1335 /* No need to save the static chain pointer. */
1336 && ! (i
== STATIC_CHAIN_REGNUM
&& current_function_needs_context
))
1339 /* Count global registers that need saving. */
1346 n_remaining_saved_regs
= n_saved_regs
;
1348 epilogue_string
[0] = '\0';
1350 if (current_function_profile
)
1352 /* When profiling, we may use registers 20 to 27 to save arguments, so
1353 they can't be used here for saving globals. J is the number of
1354 argument registers the mcount call will save. */
1355 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1358 for (i
= 20; i
<= j
+ 20; i
++)
1362 gnw
= i960_form_reg_groups (0, 16, regs
, -1, global_reg_groups
);
1363 lnw
= i960_form_reg_groups (19, 32, regs
, 0, local_reg_groups
);
1364 qsort (global_reg_groups
, gnw
, sizeof (struct reg_group
),
1365 i960_reg_group_compare
);
1366 qsort (local_reg_groups
, lnw
, sizeof (struct reg_group
),
1367 i960_reg_group_compare
);
1368 for (g
= global_reg_groups
, l
= local_reg_groups
; lnw
!= 0 && gnw
!= 0;)
1370 if (g
->length
== l
->length
)
1372 fprintf (file
, "\tmov%s %s,%s\n",
1373 ((g
->length
== 4) ? "q" :
1374 (g
->length
== 3) ? "t" :
1375 (g
->length
== 2) ? "l" : ""),
1376 reg_names
[(unsigned char) g
->start_reg
],
1377 reg_names
[(unsigned char) l
->start_reg
]);
1378 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1379 ((g
->length
== 4) ? "q" :
1380 (g
->length
== 3) ? "t" :
1381 (g
->length
== 2) ? "l" : ""),
1382 reg_names
[(unsigned char) l
->start_reg
],
1383 reg_names
[(unsigned char) g
->start_reg
]);
1384 strcat (epilogue_string
, tmpstr
);
1385 n_remaining_saved_regs
-= g
->length
;
1386 for (i
= 0; i
< g
->length
; i
++)
1388 regs
[i
+ g
->start_reg
] = 1;
1389 regs
[i
+ l
->start_reg
] = -1;
1390 regs_ever_live
[i
+ l
->start_reg
] = 1;
1397 else if (g
->length
> l
->length
)
1398 gnw
= i960_split_reg_group (g
, gnw
, l
->length
);
1400 lnw
= i960_split_reg_group (l
, lnw
, g
->length
);
1403 actual_fsize
= compute_frame_size (size
) + 4 * n_remaining_saved_regs
;
1405 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1406 size up to the nearest multiple of 16. I don't know whether this is
1407 necessary, or even desirable.
1409 The frame pointer must be aligned, but the call instruction takes care of
1410 that. If we leave the stack pointer unaligned, we may save a little on
1411 dynamic stack allocation. And we don't lose, at least according to the
1413 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1416 /* Check stack limit if necessary. */
1417 if (current_function_limit_stack
)
1419 rtx min_stack
= stack_limit_rtx
;
1420 if (actual_fsize
!= 0)
1421 min_stack
= plus_constant (stack_limit_rtx
, -actual_fsize
);
1423 /* Now, emulate a little bit of reload. We want to turn 'min_stack'
1424 into an arith_operand. Use register 20 as the temporary. */
1425 if (legitimate_address_p (Pmode
, min_stack
, 1)
1426 && !arith_operand (min_stack
, Pmode
))
1428 rtx tmp
= gen_rtx_MEM (Pmode
, min_stack
);
1429 fputs ("\tlda\t", file
);
1430 i960_print_operand (file
, tmp
, 0);
1431 fputs (",r4\n", file
);
1432 min_stack
= gen_rtx_REG (Pmode
, 20);
1434 if (arith_operand (min_stack
, Pmode
))
1436 fputs ("\tcmpo\tsp,", file
);
1437 i960_print_operand (file
, min_stack
, 0);
1438 fputs ("\n\tfaultge.f\n", file
);
1441 warning ("stack limit expression is not supported");
1444 /* Allocate space for register save and locals. */
1445 if (actual_fsize
> 0)
1447 if (actual_fsize
< 32)
1448 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1450 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1453 /* Take hardware register save area created by the call instruction
1454 into account, but store them before the argument block area. */
1455 lvar_size
= actual_fsize
- compute_frame_size (0) - n_remaining_saved_regs
* 4;
1456 offset
= STARTING_FRAME_OFFSET
+ lvar_size
;
1457 /* Save registers on stack if needed. */
1458 /* ??? Is it worth to use the same algorithm as one for saving
1459 global registers in local registers? */
1460 for (i
= 0, j
= n_remaining_saved_regs
; j
> 0 && i
< 16; i
++)
1467 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1470 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1474 if (nr
== 3 && regs
[i
+3] == -1)
1477 fprintf (file
,"\tst%s %s,%d(fp)\n",
1480 (nr
== 2) ? "l" : ""),
1481 reg_names
[i
], offset
);
1482 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1485 (nr
== 2) ? "l" : ""),
1486 offset
, reg_names
[i
]);
1487 strcat (epilogue_string
, tmpstr
);
1493 if (actual_fsize
== 0)
1496 fprintf (file
, "\t#Prologue stats:\n");
1497 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1500 fprintf (file
, "\t# Local Variable Size: %d bytes\n", lvar_size
);
1502 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1503 n_saved_regs
, n_saved_regs
* 4);
1504 fprintf (file
, "\t#End Prologue#\n");
1507 /* Output code for the function profiler. */
1510 output_function_profiler (file
, labelno
)
1514 /* The last used parameter register. */
1516 int i
, j
, increment
;
1517 int varargs_stdarg_function
1518 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1520 /* Figure out the last used parameter register. The proper thing to do
1521 is to walk incoming args of the function. A function might have live
1522 parameter registers even if it has no incoming args. Note that we
1523 don't have to save parameter registers g8 to g11 because they are
1526 /* See also output_function_prologue, which tries to use local registers
1527 for preserved call-saved global registers. */
1529 for (last_parm_reg
= 7;
1530 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1534 /* Save parameter registers in regs r4 (20) to r11 (27). */
1536 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1538 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1540 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1542 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1547 fprintf (file
, "\tmov%s g%d,r%d\n",
1548 (increment
== 4 ? "q" : increment
== 3 ? "t"
1549 : increment
== 2 ? "l": ""), i
, j
);
1552 /* If this function uses the arg pointer, then save it in r3 and then
1555 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1556 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1558 /* Load location address into g0 and call mcount. */
1560 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1562 /* If this function uses the arg pointer, restore it. */
1564 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1565 fprintf (file
, "\tmov r3,g14\n");
1567 /* Restore parameter registers. */
1569 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1571 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1573 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1575 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1580 fprintf (file
, "\tmov%s r%d,g%d\n",
1581 (increment
== 4 ? "q" : increment
== 3 ? "t"
1582 : increment
== 2 ? "l": ""), j
, i
);
1586 /* Output code for the function epilogue. */
1589 i960_output_function_epilogue (file
, size
)
1591 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
1593 if (i960_leaf_ret_reg
>= 0)
1595 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1599 if (*epilogue_string
== 0)
1603 /* Emit a return insn, but only if control can fall through to here. */
1605 tmp
= get_last_insn ();
1608 if (GET_CODE (tmp
) == BARRIER
)
1610 if (GET_CODE (tmp
) == CODE_LABEL
)
1612 if (GET_CODE (tmp
) == JUMP_INSN
)
1614 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1618 if (GET_CODE (tmp
) == NOTE
)
1620 tmp
= PREV_INSN (tmp
);
1625 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1629 fprintf (file
, "Li960R%d:\n", ret_label
);
1631 fprintf (file
, "\t#EPILOGUE#\n");
1633 /* Output the string created by the prologue which will restore all
1634 registers saved by the prologue. */
1636 if (epilogue_string
[0] != '\0')
1637 fprintf (file
, "%s", epilogue_string
);
1639 /* Must clear g14 on return if this function set it.
1640 Only varargs/stdarg functions modify g14. */
1642 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1643 fprintf (file
, "\tmov 0,g14\n");
1645 fprintf (file
, "\tret\n");
1646 fprintf (file
, "\t#End Epilogue#\n");
1649 /* Output code for a call insn. */
1652 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1653 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1655 int argsize
= INTVAL (argsize_rtx
);
1656 rtx nexti
= next_real_insn (insn
);
1658 int varargs_stdarg_function
1659 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1661 operands
[0] = target
;
1662 operands
[1] = arg_pointer
;
1664 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1665 output_asm_insn ("mov g14,r3", operands
);
1668 output_asm_insn ("lda %a1,g14", operands
);
1669 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1670 output_asm_insn ("mov 0,g14", operands
);
1672 /* The code used to assume that calls to SYMBOL_REFs could not be more
1673 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1674 feature is now implemented by relaxing in the GNU linker. It can convert
1675 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1677 /* Nexti could be zero if the called routine is volatile. */
1678 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1679 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1681 /* Delete following return insn. */
1682 if (nexti
&& no_labels_between_p (insn
, nexti
))
1683 delete_insn (nexti
);
1684 output_asm_insn ("bx %0", operands
);
1685 return "# notreached";
1688 output_asm_insn ("callx %0", operands
);
1690 /* If the caller sets g14 to the address of the argblock, then the caller
1691 must clear it after the return. */
1693 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1694 output_asm_insn ("mov r3,g14", operands
);
1695 else if (argsize
> 48)
1696 output_asm_insn ("mov 0,g14", operands
);
1701 /* Output code for a return insn. */
1704 i960_output_ret_insn (insn
)
1707 static char lbuf
[20];
1709 if (*epilogue_string
!= 0)
1711 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1714 sprintf (lbuf
, "b Li960R%d", ret_label
);
1718 /* Must clear g14 on return if this function set it.
1719 Only varargs/stdarg functions modify g14. */
1721 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1722 output_asm_insn ("mov 0,g14", 0);
1724 if (i960_leaf_ret_reg
>= 0)
1726 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1732 /* Print the operand represented by rtx X formatted by code CODE. */
1735 i960_print_operand (file
, x
, code
)
1740 enum rtx_code rtxcode
= x
? GET_CODE (x
) : NIL
;
1747 /* Second reg of a double or quad. */
1748 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1752 /* Third reg of a quad. */
1753 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1757 /* Fourth reg of a quad. */
1758 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1762 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1770 else if (rtxcode
== MEM
)
1772 output_address (XEXP (x
, 0));
1775 else if (rtxcode
== CONST_INT
)
1777 HOST_WIDE_INT val
= INTVAL (x
);
1780 if (val
> 9999 || val
< -999)
1781 fprintf (file
, "0x%x", val
);
1783 fprintf (file
, "%d", val
);
1786 else if (rtxcode
== CONST_DOUBLE
)
1791 if (x
== CONST0_RTX (GET_MODE (x
)))
1793 fprintf (file
, "0f0.0");
1796 else if (x
== CONST1_RTX (GET_MODE (x
)))
1798 fprintf (file
, "0f1.0");
1802 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1803 REAL_VALUE_TO_DECIMAL (d
, dstr
, -1);
1804 fprintf (file
, "0f%s", dstr
);
1811 /* Branch or jump, depending on assembler. */
1812 if (TARGET_ASM_COMPAT
)
1819 /* Sign of condition. */
1820 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1821 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1823 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1824 || (rtxcode
== GE
) || (rtxcode
== LE
))
1831 /* Inverted condition. */
1832 rtxcode
= reverse_condition (rtxcode
);
1836 /* Inverted condition w/ reversed operands. */
1837 rtxcode
= reverse_condition (rtxcode
);
1841 /* Reversed operand condition. */
1842 rtxcode
= swap_condition (rtxcode
);
1846 /* Normal condition. */
1848 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1849 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1850 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1851 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1852 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1853 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1854 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1855 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1856 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1857 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1862 /* For conditional branches, substitute ".t" or ".f". */
1863 if (TARGET_BRANCH_PREDICT
)
1865 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1868 int pred_val
= INTVAL (XEXP (x
, 0));
1869 fputs ((pred_val
< REG_BR_PROB_BASE
/ 2 ? ".f" : ".t"), file
);
1875 output_addr_const (file
, x
);
1885 /* Print a memory address as an operand to reference that memory location.
1887 This is exactly the same as legitimate_address_p, except that it the prints
1888 addresses instead of recognizing them. */
1891 i960_print_operand_addr (file
, addr
)
1903 if (GET_CODE (addr
) == REG
)
1905 else if (CONSTANT_P (addr
))
1907 else if (GET_CODE (addr
) == PLUS
)
1911 op0
= XEXP (addr
, 0);
1912 op1
= XEXP (addr
, 1);
1914 if (GET_CODE (op0
) == REG
)
1917 if (GET_CODE (op1
) == REG
)
1919 else if (CONSTANT_P (op1
))
1924 else if (GET_CODE (op0
) == PLUS
)
1926 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1928 ireg
= XEXP (XEXP (op0
, 0), 0);
1929 scale
= XEXP (XEXP (op0
, 0), 1);
1930 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1932 breg
= XEXP (op0
, 1);
1938 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1940 breg
= XEXP (op0
, 0);
1941 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1943 ireg
= XEXP (op0
, 1);
1952 else if (GET_CODE (op0
) == MULT
)
1954 ireg
= XEXP (op0
, 0);
1955 scale
= XEXP (op0
, 1);
1956 if (GET_CODE (op1
) == REG
)
1958 else if (CONSTANT_P (op1
))
1966 else if (GET_CODE (addr
) == MULT
)
1968 ireg
= XEXP (addr
, 0);
1969 scale
= XEXP (addr
, 1);
1975 output_addr_const (file
, offset
);
1977 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1979 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1982 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1983 that is a valid memory address for an instruction.
1984 The MODE argument is the machine mode for the MEM expression
1985 that wants to use this address.
1987 On 80960, legitimate addresses are:
1989 disp (12 or 32 bit) ld foo,r0
1990 base + index ld (g0)[g1*1],r0
1991 base + displ ld 0xf00(g0),r0
1992 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1993 index*scale + base ld (g0)[g1*4],r0
1994 index*scale + displ ld 0xf00[g1*4],r0
1995 index*scale ld [g1*4],r0
1996 index + base + displ ld 0xf00(g0)[g1*1],r0
1998 In each case, scale can be 1, 2, 4, 8, or 16. */
2000 /* This is exactly the same as i960_print_operand_addr, except that
2001 it recognizes addresses instead of printing them.
2003 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2004 convert common non-canonical forms to canonical form so that they will
2007 /* These two macros allow us to accept either a REG or a SUBREG anyplace
2008 where a register is valid. */
2010 #define RTX_OK_FOR_BASE_P(X, STRICT) \
2011 ((GET_CODE (X) == REG \
2012 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
2013 || (GET_CODE (X) == SUBREG \
2014 && GET_CODE (SUBREG_REG (X)) == REG \
2015 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
2016 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
2018 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
2019 ((GET_CODE (X) == REG \
2020 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
2021 || (GET_CODE (X) == SUBREG \
2022 && GET_CODE (SUBREG_REG (X)) == REG \
2023 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
2024 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
2027 legitimate_address_p (mode
, addr
, strict
)
2028 enum machine_mode mode ATTRIBUTE_UNUSED
;
2032 if (RTX_OK_FOR_BASE_P (addr
, strict
))
2034 else if (CONSTANT_P (addr
))
2036 else if (GET_CODE (addr
) == PLUS
)
2040 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2043 op0
= XEXP (addr
, 0);
2044 op1
= XEXP (addr
, 1);
2046 if (RTX_OK_FOR_BASE_P (op0
, strict
))
2048 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
2050 else if (CONSTANT_P (op1
))
2055 else if (GET_CODE (op0
) == PLUS
)
2057 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
2059 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
2060 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
2063 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
2064 && CONSTANT_P (op1
))
2069 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
2071 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
2072 && CONSTANT_P (op1
))
2080 else if (GET_CODE (op0
) == MULT
)
2082 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
2083 && SCALE_TERM_P (XEXP (op0
, 1))))
2086 if (RTX_OK_FOR_BASE_P (op1
, strict
))
2088 else if (CONSTANT_P (op1
))
2096 else if (GET_CODE (addr
) == MULT
)
2098 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2101 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
2102 && SCALE_TERM_P (XEXP (addr
, 1)));
2108 /* Try machine-dependent ways of modifying an illegitimate address
2109 to be legitimate. If we find one, return the new, valid address.
2110 This macro is used in only one place: `memory_address' in explow.c.
2112 This converts some non-canonical addresses to canonical form so they
2113 can be recognized. */
2116 legitimize_address (x
, oldx
, mode
)
2118 register rtx oldx ATTRIBUTE_UNUSED
;
2119 enum machine_mode mode ATTRIBUTE_UNUSED
;
2121 if (GET_CODE (x
) == SYMBOL_REF
)
2124 x
= copy_to_reg (x
);
2127 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2130 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2131 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2132 created by virtual register instantiation, register elimination, and
2133 similar optimizations. */
2134 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2135 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2136 x
= gen_rtx_PLUS (Pmode
,
2137 gen_rtx_PLUS (Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2138 XEXP (XEXP (x
, 1), 1));
2140 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2141 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2142 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2143 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2144 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2145 && CONSTANT_P (XEXP (x
, 1)))
2147 rtx constant
, other
;
2149 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2151 constant
= XEXP (x
, 1);
2152 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2154 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2156 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2157 other
= XEXP (x
, 1);
2160 constant
= 0, other
= 0;
2163 x
= gen_rtx_PLUS (Pmode
,
2164 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
2165 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2166 plus_constant (other
, INTVAL (constant
)));
2173 /* Return the most stringent alignment that we are willing to consider
2174 objects of size SIZE and known alignment ALIGN as having. */
2177 i960_alignment (size
, align
)
2183 if (! TARGET_STRICT_ALIGN
)
2184 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2186 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2197 hard_regno_mode_ok (regno
, mode
)
2199 enum machine_mode mode
;
2205 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2208 case DImode
: case DFmode
:
2209 return (regno
& 1) == 0;
2211 case TImode
: case XFmode
:
2212 return (regno
& 3) == 0;
2218 else if (regno
>= 32 && regno
< 36)
2222 case SFmode
: case DFmode
: case XFmode
:
2223 case SCmode
: case DCmode
:
2230 else if (regno
== 36)
2234 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2241 else if (regno
== 37)
2248 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2249 advantage of machine specific facts, such as knowing that the frame pointer
2250 is always 16 byte aligned. */
2253 i960_expr_alignment (x
, size
)
2262 switch (GET_CODE(x
))
2267 if ((align
& 0xf) == 0)
2269 else if ((align
& 0x7) == 0)
2271 else if ((align
& 0x3) == 0)
2273 else if ((align
& 0x1) == 0)
2280 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2281 i960_expr_alignment (XEXP (x
, 1), size
));
2285 /* If this is a valid program, objects are guaranteed to be
2286 correctly aligned for whatever size the reference actually is. */
2287 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2291 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2296 align
= i960_expr_alignment (XEXP (x
, 0), size
);
2298 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2300 align
= align
<< INTVAL (XEXP (x
, 1));
2301 align
= MIN (align
, 16);
2306 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2307 i960_expr_alignment (XEXP (x
, 1), size
));
2309 align
= MIN (align
, 16);
2318 /* Return true if it is possible to reference both BASE and OFFSET, which
2319 have alignment at least as great as 4 byte, as if they had alignment valid
2320 for an object of size SIZE. */
2323 i960_improve_align (base
, offset
, size
)
2330 /* We have at least a word reference to the object, so we know it has to
2331 be aligned at least to 4 bytes. */
2333 i
= MIN (i960_expr_alignment (base
, 4),
2334 i960_expr_alignment (offset
, 4));
2338 /* We know the size of the request. If strict align is not enabled, we
2339 can guess that the alignment is OK for the requested size. */
2341 if (! TARGET_STRICT_ALIGN
)
2342 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2348 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2349 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2352 i960_si_ti (base
, offset
)
2356 return i960_improve_align (base
, offset
, 16);
2359 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2360 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2363 i960_si_di (base
, offset
)
2367 return i960_improve_align (base
, offset
, 8);
2370 /* Return raw values of size and alignment (in words) for the data
2371 type being accessed. These values will be rounded by the caller. */
2374 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2375 enum machine_mode mode
;
2382 /* Use formal alignment requirements of type being passed, except make
2383 it at least a word. If we don't have a type, this is a library call,
2384 and the parm has to be of scalar type. In this case, consider its
2385 formal alignment requirement to be its size in words. */
2387 if (mode
== BLKmode
)
2388 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2389 else if (mode
== VOIDmode
)
2391 /* End of parm list. */
2392 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2397 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2401 /* ??? This is a hack to properly correct the alignment of XFmode
2402 values without affecting anything else. */
2408 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2409 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2417 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2418 Any arg that is bigger than 4 words is placed on the stack and all
2419 subsequent arguments are placed on the stack.
2421 Additionally, parameters with an alignment requirement stronger than
2422 a word must be aligned appropriately. Note that this means that a
2423 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2424 passed in an odd/even register pair. */
2426 /* Update CUM to advance past an argument described by MODE and TYPE. */
2429 i960_function_arg_advance (cum
, mode
, type
, named
)
2430 CUMULATIVE_ARGS
*cum
;
2431 enum machine_mode mode
;
2433 int named ATTRIBUTE_UNUSED
;
2437 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2439 if (size
> 4 || cum
->ca_nstackparms
!= 0
2440 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2441 || MUST_PASS_IN_STACK (mode
, type
))
2443 /* Indicate that all the registers are in use, even if all are not,
2444 so va_start will compute the right value. */
2445 cum
->ca_nregparms
= NPARM_REGS
;
2446 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2449 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2452 /* Return the register that the argument described by MODE and TYPE is
2453 passed in, or else return 0 if it is passed on the stack. */
2456 i960_function_arg (cum
, mode
, type
, named
)
2457 CUMULATIVE_ARGS
*cum
;
2458 enum machine_mode mode
;
2460 int named ATTRIBUTE_UNUSED
;
2465 if (mode
== VOIDmode
)
2468 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2470 if (size
> 4 || cum
->ca_nstackparms
!= 0
2471 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2472 || MUST_PASS_IN_STACK (mode
, type
))
2474 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2479 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2480 ret
= gen_rtx_REG (mode
, cum
->ca_nregparms
);
2486 /* Return the number of bits that an object of size N bytes is aligned to. */
2489 i960_object_bytes_bitalign (n
)
2493 else if (n
> 4) n
= 64;
2494 else if (n
> 2) n
= 32;
2495 else if (n
> 1) n
= 16;
2501 /* Compute the alignment for an aggregate type TSIZE.
2502 Alignment is MAX (greatest member alignment,
2503 MIN (pragma align, structure size alignment)). */
2506 i960_round_align (align
, tsize
)
2512 if (! tsize
|| TREE_CODE (tsize
) != INTEGER_CST
)
2515 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2517 /* Handle #pragma align. */
2518 if (new_align
> i960_maxbitalignment
)
2519 new_align
= i960_maxbitalignment
;
2521 if (align
< new_align
)
2527 /* Do any needed setup for a varargs function. For the i960, we must
2528 create a register parameter block if one doesn't exist, and then copy
2529 all register parameters to memory. */
2532 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2533 CUMULATIVE_ARGS
*cum
;
2534 enum machine_mode mode ATTRIBUTE_UNUSED
;
2535 tree type ATTRIBUTE_UNUSED
;
2536 int *pretend_size ATTRIBUTE_UNUSED
;
2539 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2540 int first_reg
= cum
->ca_nregparms
;
2542 /* Copy only unnamed register arguments to memory. If there are
2543 any stack parms, there are no unnamed arguments in registers, and
2544 an argument block was already allocated by the caller.
2545 Remember that any arg bigger than 4 words is passed on the stack as
2546 are all subsequent args.
2548 If there are no stack arguments but there are exactly NPARM_REGS
2549 registers, either there were no extra arguments or the caller
2550 allocated an argument block. */
2552 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2554 rtx label
= gen_label_rtx ();
2557 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2558 and we need to allocate a chunk to save the registers (if any
2559 arguments were passed on the stack the caller would allocate the
2560 48 bytes as well). We must allocate all 48 bytes (12*4) because
2561 va_start assumes it. */
2562 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2563 emit_jump_insn (gen_bne (label
));
2564 emit_insn (gen_rtx_SET (VOIDmode
, arg_pointer_rtx
,
2565 stack_pointer_rtx
));
2566 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
2567 memory_address (SImode
,
2568 plus_constant (stack_pointer_rtx
,
2572 /* ??? Note that we unnecessarily store one extra register for stdarg
2573 fns. We could optimize this, but it's kept as for now. */
2574 regblock
= gen_rtx_MEM (BLKmode
,
2575 plus_constant (arg_pointer_rtx
, first_reg
* 4));
2576 set_mem_alias_set (regblock
, get_varargs_alias_set ());
2577 set_mem_align (regblock
, BITS_PER_WORD
);
2578 move_block_from_reg (first_reg
, regblock
,
2579 NPARM_REGS
- first_reg
,
2580 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2584 /* Define the `__builtin_va_list' type for the ABI. */
2587 i960_build_va_list ()
2589 return build_array_type (unsigned_type_node
,
2590 build_index_type (size_one_node
));
2593 /* Implement `va_start' for varargs and stdarg. */
2596 i960_va_start (valist
, nextarg
)
2598 rtx nextarg ATTRIBUTE_UNUSED
;
2600 tree s
, t
, base
, num
;
2602 /* The array type always decays to a pointer before we get here, so we
2603 can't use ARRAY_REF. */
2604 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2605 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2606 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2607 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2609 s
= make_tree (unsigned_type_node
, arg_pointer_rtx
);
2610 t
= build (MODIFY_EXPR
, unsigned_type_node
, base
, s
);
2611 TREE_SIDE_EFFECTS (t
) = 1;
2612 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2614 s
= build_int_2 ((current_function_args_info
.ca_nregparms
2615 + current_function_args_info
.ca_nstackparms
) * 4, 0);
2616 t
= build (MODIFY_EXPR
, unsigned_type_node
, num
, s
);
2617 TREE_SIDE_EFFECTS (t
) = 1;
2618 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2621 /* Implement `va_arg'. */
2624 i960_va_arg (valist
, type
)
2627 HOST_WIDE_INT siz
, ali
;
2628 tree base
, num
, pad
, next
, this, t1
, t2
, int48
;
2631 /* The array type always decays to a pointer before we get here, so we
2632 can't use ARRAY_REF. */
2633 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2634 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2635 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2636 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2638 /* Round up sizeof(type) to a word. */
2639 siz
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
2641 /* Round up alignment to a word. */
2642 ali
= TYPE_ALIGN (type
);
2643 if (ali
< BITS_PER_WORD
)
2644 ali
= BITS_PER_WORD
;
2645 ali
/= BITS_PER_UNIT
;
2647 /* Align NUM appropriate for the argument. */
2648 pad
= fold (build (PLUS_EXPR
, unsigned_type_node
, num
,
2649 build_int_2 (ali
- 1, 0)));
2650 pad
= fold (build (BIT_AND_EXPR
, unsigned_type_node
, pad
,
2651 build_int_2 (-ali
, -1)));
2652 pad
= save_expr (pad
);
2654 /* Increment VPAD past this argument. */
2655 next
= fold (build (PLUS_EXPR
, unsigned_type_node
, pad
,
2656 build_int_2 (siz
, 0)));
2657 next
= save_expr (next
);
2659 /* Find the offset for the current argument. Mind peculiar overflow
2660 from registers to stack. */
2661 int48
= build_int_2 (48, 0);
2663 t2
= integer_one_node
;
2665 t2
= fold (build (GT_EXPR
, integer_type_node
, next
, int48
));
2666 t1
= fold (build (LE_EXPR
, integer_type_node
, num
, int48
));
2667 t1
= fold (build (TRUTH_AND_EXPR
, integer_type_node
, t1
, t2
));
2668 this = fold (build (COND_EXPR
, unsigned_type_node
, t1
, int48
, pad
));
2670 /* Find the address for the current argument. */
2671 t1
= fold (build (PLUS_EXPR
, unsigned_type_node
, base
, this));
2672 t1
= build1 (NOP_EXPR
, ptr_type_node
, t1
);
2673 addr_rtx
= expand_expr (t1
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
2675 /* Increment NUM. */
2676 t1
= build (MODIFY_EXPR
, unsigned_type_node
, num
, next
);
2677 TREE_SIDE_EFFECTS (t1
) = 1;
2678 expand_expr (t1
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2683 /* Calculate the final size of the reg parm stack space for the current
2684 function, based on how many bytes would be allocated on the stack. */
2687 i960_final_reg_parm_stack_space (const_size
, var_size
)
2691 if (var_size
|| const_size
> 48)
2697 /* Calculate the size of the reg parm stack space. This is a bit complicated
2701 i960_reg_parm_stack_space (fndecl
)
2704 /* In this case, we are called from emit_library_call, and we don't need
2705 to pretend we have more space for parameters than what's apparent. */
2709 /* In this case, we are called from locate_and_pad_parms when we're
2710 not IN_REGS, so we have an arg block. */
2711 if (fndecl
!= current_function_decl
)
2714 /* Otherwise, we have an arg block if the current function has more than
2715 48 bytes of parameters. */
2716 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2722 /* Return the register class of a scratch register needed to copy IN into
2723 or out of a register in CLASS in MODE. If it can be done directly,
2724 NO_REGS is returned. */
2727 secondary_reload_class (class, mode
, in
)
2728 enum reg_class
class;
2729 enum machine_mode mode
;
2734 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2735 regno
= true_regnum (in
);
2737 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2738 LOCAL_OR_GLOBAL_REGS into anything. */
2739 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2740 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2743 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2744 if (class == FP_REGS
2745 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2746 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2749 return LOCAL_OR_GLOBAL_REGS
;
2752 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2753 function unit it executed on. */
2755 /* ??? This would make more sense as an attribute. */
2758 i960_scan_opcode (p
)
2770 /* Ret is not actually of type REG, but it won't matter, because no
2771 insn will ever follow it. */
2774 i960_last_insn_type
= I_TYPE_REG
;
2778 if (p
[1] == 'x' || p
[3] == 'x')
2779 i960_last_insn_type
= I_TYPE_MEM
;
2780 i960_last_insn_type
= I_TYPE_CTRL
;
2785 i960_last_insn_type
= I_TYPE_CTRL
;
2792 i960_last_insn_type
= I_TYPE_MEM
;
2794 i960_last_insn_type
= I_TYPE_CTRL
;
2796 else if (p
[1] == 'm')
2799 i960_last_insn_type
= I_TYPE_REG
;
2800 else if (p
[4] == 'b' || p
[4] == 'j')
2801 i960_last_insn_type
= I_TYPE_CTRL
;
2803 i960_last_insn_type
= I_TYPE_REG
;
2806 i960_last_insn_type
= I_TYPE_REG
;
2810 i960_last_insn_type
= I_TYPE_MEM
;
2815 i960_last_insn_type
= I_TYPE_MEM
;
2817 i960_last_insn_type
= I_TYPE_REG
;