1 /* Subroutines for insn-output.c for Intel 860
2 Copyright (C) 1989, 1991, 1997, 1998 Free Software Foundation, Inc.
5 Written by Richard Stallman (rms@ai.mit.edu).
7 Hacked substantially by Ron Guilmette (rfg@netcom.com) to cater
8 to the whims of the System V Release 4 assembler.
10 This file is part of GNU CC.
12 GNU CC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
17 GNU CC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GNU CC; see the file COPYING. If not, write to
24 the Free Software Foundation, 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-flags.h"
40 #include "insn-attr.h"
42 static rtx
find_addr_reg ();
44 #ifndef I860_REG_PREFIX
45 #define I860_REG_PREFIX ""
48 char *i860_reg_prefix
= I860_REG_PREFIX
;
50 /* Save information from a "cmpxx" operation until the branch is emitted. */
52 rtx i860_compare_op0
, i860_compare_op1
;
54 /* Return non-zero if this pattern, can be evaluated safely, even if it
57 safe_insn_src_p (op
, mode
)
59 enum machine_mode mode
;
61 /* Just experimenting. */
63 /* No floating point src is safe if it contains an arithmetic
64 operation, since that operation may trap. */
65 switch (GET_CODE (op
))
77 return CONSTANT_ADDRESS_P (XEXP (op
, 0));
79 /* We never need to negate or complement constants. */
81 return (mode
!= SFmode
&& mode
!= DFmode
);
98 return (mode
!= SFmode
&& mode
!= DFmode
);
105 if ((GET_CODE (XEXP (op
, 0)) == CONST_INT
&& ! SMALL_INT (XEXP (op
, 0)))
106 || (GET_CODE (XEXP (op
, 1)) == CONST_INT
&& ! SMALL_INT (XEXP (op
, 1))))
115 /* Return 1 if REG is clobbered in IN.
116 Return 2 if REG is used in IN.
117 Return 3 if REG is both used and clobbered in IN.
118 Return 0 if neither. */
121 reg_clobbered_p (reg
, in
)
125 register enum rtx_code code
;
130 code
= GET_CODE (in
);
132 if (code
== SET
|| code
== CLOBBER
)
134 rtx dest
= SET_DEST (in
);
138 while (GET_CODE (dest
) == STRICT_LOW_PART
139 || GET_CODE (dest
) == SUBREG
140 || GET_CODE (dest
) == SIGN_EXTRACT
141 || GET_CODE (dest
) == ZERO_EXTRACT
)
142 dest
= XEXP (dest
, 0);
146 else if (GET_CODE (dest
) == REG
147 && refers_to_regno_p (REGNO (reg
),
148 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
152 /* Anything that sets just part of the register
153 is considered using as well as setting it.
154 But note that a straight SUBREG of a single-word value
155 clobbers the entire value. */
156 if (dest
!= SET_DEST (in
)
157 && ! (GET_CODE (SET_DEST (in
)) == SUBREG
158 || UNITS_PER_WORD
>= GET_MODE_SIZE (GET_MODE (dest
))))
165 used
= refers_to_regno_p (REGNO (reg
),
166 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
169 used
= refers_to_regno_p (REGNO (reg
),
170 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
174 return set
+ used
* 2;
177 if (refers_to_regno_p (REGNO (reg
),
178 REGNO (reg
) + HARD_REGNO_NREGS (reg
, GET_MODE (reg
)),
184 /* Return non-zero if OP can be written to without screwing up
185 GCC's model of what's going on. It is assumed that this operand
186 appears in the dest position of a SET insn in a conditional
187 branch's delay slot. AFTER is the label to start looking from. */
189 operand_clobbered_before_used_after (op
, after
)
193 /* Just experimenting. */
194 if (GET_CODE (op
) == CC0
)
196 if (GET_CODE (op
) == REG
)
200 if (op
== stack_pointer_rtx
)
203 /* Scan forward from the label, to see if the value of OP
204 is clobbered before the first use. */
206 for (insn
= NEXT_INSN (after
); insn
; insn
= NEXT_INSN (insn
))
208 if (GET_CODE (insn
) == NOTE
)
210 if (GET_CODE (insn
) == INSN
211 || GET_CODE (insn
) == JUMP_INSN
212 || GET_CODE (insn
) == CALL_INSN
)
214 switch (reg_clobbered_p (op
, PATTERN (insn
)))
224 /* If we reach another label without clobbering OP,
225 then we cannot safely write it here. */
226 else if (GET_CODE (insn
) == CODE_LABEL
)
228 if (GET_CODE (insn
) == JUMP_INSN
)
230 if (condjump_p (insn
))
232 /* This is a jump insn which has already
233 been mangled. We can't tell what it does. */
234 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
236 if (! JUMP_LABEL (insn
))
238 /* Keep following jumps. */
239 insn
= JUMP_LABEL (insn
);
245 /* In both of these cases, the first insn executed
246 for this op will be a orh whatever%h,%?r0,%?r31,
247 which is tolerable. */
248 if (GET_CODE (op
) == MEM
)
249 return (CONSTANT_ADDRESS_P (XEXP (op
, 0)));
254 /* Return non-zero if this pattern, as a source to a "SET",
255 is known to yield an instruction of unit size. */
257 single_insn_src_p (op
, mode
)
259 enum machine_mode mode
;
261 switch (GET_CODE (op
))
264 /* This is not always a single insn src, technically,
265 but output_delayed_branch knows how to deal with it. */
270 /* This is not a single insn src, technically,
271 but output_delayed_branch knows how to deal with it. */
280 /* We never need to negate or complement constants. */
282 return (mode
!= DFmode
);
289 /* Detect cases that require multiple instructions. */
290 if (CONSTANT_P (XEXP (op
, 1))
291 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
292 && SMALL_INT (XEXP (op
, 1))))
304 /* Not doing floating point, since they probably
305 take longer than the branch slot they might fill. */
306 return (mode
!= SFmode
&& mode
!= DFmode
);
309 if (GET_CODE (XEXP (op
, 1)) == NOT
)
311 rtx arg
= XEXP (XEXP (op
, 1), 0);
313 && !(GET_CODE (arg
) == CONST_INT
315 || INTVAL (arg
) & 0xffff == 0)))
320 /* Both small and round numbers take one instruction;
322 if (CONSTANT_P (XEXP (op
, 1))
323 && !(GET_CODE (XEXP (op
, 1)) == CONST_INT
324 && (SMALL_INT (XEXP (op
, 1))
325 || INTVAL (XEXP (op
, 1)) & 0xffff == 0)))
334 if (SUBREG_WORD (op
) != 0)
336 return single_insn_src_p (SUBREG_REG (op
), mode
);
338 /* Not doing floating point, since they probably
339 take longer than the branch slot they might fill. */
353 /* Return non-zero only if OP is a register of mode MODE,
356 reg_or_0_operand (op
, mode
)
358 enum machine_mode mode
;
360 return (op
== const0_rtx
|| register_operand (op
, mode
)
361 || op
== CONST0_RTX (mode
));
364 /* Return truth value of whether OP can be used as an operands in a three
365 address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
368 arith_operand (op
, mode
)
370 enum machine_mode mode
;
372 return (register_operand (op
, mode
)
373 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
376 /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
379 logic_operand (op
, mode
)
381 enum machine_mode mode
;
383 return (register_operand (op
, mode
)
384 || (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
)));
387 /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
390 shift_operand (op
, mode
)
392 enum machine_mode mode
;
394 return (register_operand (op
, mode
)
395 || (GET_CODE (op
) == CONST_INT
));
398 /* Return 1 if OP is a valid first operand for either a logical insn
399 or an add insn of mode MODE. */
402 compare_operand (op
, mode
)
404 enum machine_mode mode
;
406 return (register_operand (op
, mode
)
407 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
) && LOGIC_INT (op
)));
410 /* Return truth value of whether OP can be used as the 5-bit immediate
411 operand of a bte or btne insn. */
414 bte_operand (op
, mode
)
416 enum machine_mode mode
;
418 return (register_operand (op
, mode
)
419 || (GET_CODE (op
) == CONST_INT
420 && (unsigned) INTVAL (op
) < 0x20));
423 /* Return 1 if OP is an indexed memory reference of mode MODE. */
426 indexed_operand (op
, mode
)
428 enum machine_mode mode
;
430 return (GET_CODE (op
) == MEM
&& GET_MODE (op
) == mode
431 && GET_CODE (XEXP (op
, 0)) == PLUS
432 && GET_MODE (XEXP (op
, 0)) == SImode
433 && register_operand (XEXP (XEXP (op
, 0), 0), SImode
)
434 && register_operand (XEXP (XEXP (op
, 0), 1), SImode
));
437 /* Return 1 if OP is a suitable source operand for a load insn
441 load_operand (op
, mode
)
443 enum machine_mode mode
;
445 return (memory_operand (op
, mode
) || indexed_operand (op
, mode
));
448 /* Return truth value of whether OP is a integer which fits the
449 range constraining immediate operands in add/subtract insns. */
454 enum machine_mode mode
;
456 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
459 /* Return truth value of whether OP is a integer which fits the
460 range constraining immediate operands in logic insns. */
465 enum machine_mode mode
;
467 return (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
));
470 /* Test for a valid operand for a call instruction.
471 Don't allow the arg pointer register or virtual regs
472 since they may change into reg + const, which the patterns
476 call_insn_operand (op
, mode
)
478 enum machine_mode mode
;
480 if (GET_CODE (op
) == MEM
481 && (CONSTANT_ADDRESS_P (XEXP (op
, 0))
482 || (GET_CODE (XEXP (op
, 0)) == REG
483 && XEXP (op
, 0) != arg_pointer_rtx
484 && !(REGNO (XEXP (op
, 0)) >= FIRST_PSEUDO_REGISTER
485 && REGNO (XEXP (op
, 0)) <= LAST_VIRTUAL_REGISTER
))))
490 /* Return the best assembler insn template
491 for moving operands[1] into operands[0] as a fullword. */
494 singlemove_string (operands
)
497 if (GET_CODE (operands
[0]) == MEM
)
499 if (GET_CODE (operands
[1]) != MEM
)
500 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
502 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
503 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
504 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
507 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
509 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
510 cc_status
.mdep
= XEXP (operands
[0], 0);
511 return "st.l %r1,%L0(%?r31)";
514 return "st.l %r1,%0";
521 cc_status
.flags
&= ~CC_F0_IS_0
;
522 xoperands
[0] = gen_rtx (REG
, SFmode
, 32);
523 xoperands
[1] = operands
[1];
524 output_asm_insn (singlemove_string (xoperands
), xoperands
);
525 xoperands
[1] = xoperands
[0];
526 xoperands
[0] = operands
[0];
527 output_asm_insn (singlemove_string (xoperands
), xoperands
);
532 if (GET_CODE (operands
[1]) == MEM
)
534 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
536 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
537 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
538 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
541 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
543 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
544 cc_status
.mdep
= XEXP (operands
[1], 0);
545 return "ld.l %L1(%?r31),%0";
547 return "ld.l %m1,%0";
549 if (GET_CODE (operands
[1]) == CONST_INT
)
551 if (operands
[1] == const0_rtx
)
552 return "mov %?r0,%0";
553 if((INTVAL (operands
[1]) & 0xffff0000) == 0)
554 return "or %L1,%?r0,%0";
555 if((INTVAL (operands
[1]) & 0xffff8000) == 0xffff8000)
556 return "adds %1,%?r0,%0";
557 if((INTVAL (operands
[1]) & 0x0000ffff) == 0)
558 return "orh %H1,%?r0,%0";
563 /* Output assembler code to perform a doubleword move insn
564 with operands OPERANDS. */
567 output_move_double (operands
)
570 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
572 rtx addreg0
= 0, addreg1
= 0;
573 int highest_first
= 0;
574 int no_addreg1_decrement
= 0;
576 /* First classify both operands. */
578 if (REG_P (operands
[0]))
580 else if (offsettable_memref_p (operands
[0]))
582 else if (GET_CODE (operands
[0]) == MEM
)
587 if (REG_P (operands
[1]))
589 else if (CONSTANT_P (operands
[1]))
591 else if (offsettable_memref_p (operands
[1]))
593 else if (GET_CODE (operands
[1]) == MEM
)
598 /* Check for the cases that the operand constraints are not
599 supposed to allow to happen. Abort if we get one,
600 because generating code for these cases is painful. */
602 if (optype0
== RNDOP
|| optype1
== RNDOP
)
605 /* If an operand is an unoffsettable memory ref, find a register
606 we can increment temporarily to make it refer to the second word. */
608 if (optype0
== MEMOP
)
609 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
611 if (optype1
== MEMOP
)
612 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
614 /* ??? Perhaps in some cases move double words
615 if there is a spare pair of floating regs. */
617 /* Ok, we can do one word at a time.
618 Normally we do the low-numbered word first,
619 but if either operand is autodecrementing then we
620 do the high-numbered word first.
622 In either case, set up in LATEHALF the operands to use
623 for the high-numbered word and in some cases alter the
624 operands in OPERANDS to be suitable for the low-numbered word. */
626 if (optype0
== REGOP
)
627 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
628 else if (optype0
== OFFSOP
)
629 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
631 latehalf
[0] = operands
[0];
633 if (optype1
== REGOP
)
634 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
635 else if (optype1
== OFFSOP
)
636 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
637 else if (optype1
== CNSTOP
)
639 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
640 split_double (operands
[1], &operands
[1], &latehalf
[1]);
641 else if (CONSTANT_P (operands
[1]))
642 latehalf
[1] = const0_rtx
;
645 latehalf
[1] = operands
[1];
647 /* If the first move would clobber the source of the second one,
648 do them in the other order.
650 RMS says "This happens only for registers;
651 such overlap can't happen in memory unless the user explicitly
652 sets it up, and that is an undefined circumstance."
654 but it happens on the sparc when loading parameter registers,
655 so I am going to define that circumstance, and make it work
658 if (optype0
== REGOP
&& optype1
== REGOP
659 && REGNO (operands
[0]) == REGNO (latehalf
[1]))
661 CC_STATUS_PARTIAL_INIT
;
662 /* Make any unoffsettable addresses point at high-numbered word. */
664 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
666 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
669 output_asm_insn (singlemove_string (latehalf
), latehalf
);
671 /* Undo the adds we just did. */
673 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
675 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
677 /* Do low-numbered word. */
678 return singlemove_string (operands
);
680 else if (optype0
== REGOP
&& optype1
!= REGOP
681 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
683 /* If both halves of dest are used in the src memory address,
684 add the two regs and put them in the low reg (operands[0]).
685 Then it works to load latehalf first. */
686 if (reg_mentioned_p (operands
[0], XEXP (operands
[1], 0))
687 && reg_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
690 xops
[0] = latehalf
[0];
691 xops
[1] = operands
[0];
692 output_asm_insn ("adds %1,%0,%1", xops
);
693 operands
[1] = gen_rtx (MEM
, DImode
, operands
[0]);
694 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
698 /* Only one register in the dest is used in the src memory address,
699 and this is the first register of the dest, so we want to do
700 the late half first here also. */
701 else if (! reg_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
703 /* Only one register in the dest is used in the src memory address,
704 and this is the second register of the dest, so we want to do
705 the late half last. If addreg1 is set, and addreg1 is the same
706 register as latehalf, then we must suppress the trailing decrement,
707 because it would clobber the value just loaded. */
708 else if (addreg1
&& reg_mentioned_p (addreg1
, latehalf
[0]))
709 no_addreg1_decrement
= 1;
712 /* Normal case: do the two words, low-numbered first.
713 Overlap case (highest_first set): do high-numbered word first. */
716 output_asm_insn (singlemove_string (operands
), operands
);
718 CC_STATUS_PARTIAL_INIT
;
719 /* Make any unoffsettable addresses point at high-numbered word. */
721 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
723 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
726 output_asm_insn (singlemove_string (latehalf
), latehalf
);
728 /* Undo the adds we just did. */
730 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
731 if (addreg1
&& !no_addreg1_decrement
)
732 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
735 output_asm_insn (singlemove_string (operands
), operands
);
741 output_fp_move_double (operands
)
744 /* If the source operand is any sort of zero, use f0 instead. */
746 if (operands
[1] == CONST0_RTX (GET_MODE (operands
[1])))
747 operands
[1] = gen_rtx (REG
, DFmode
, F0_REGNUM
);
749 if (FP_REG_P (operands
[0]))
751 if (FP_REG_P (operands
[1]))
752 return "fmov.dd %1,%0";
753 if (GET_CODE (operands
[1]) == REG
)
755 output_asm_insn ("ixfr %1,%0", operands
);
756 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
757 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
760 if (operands
[1] == CONST0_RTX (DFmode
))
761 return "fmov.dd f0,%0";
762 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
764 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
765 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
766 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
769 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
771 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
772 cc_status
.mdep
= XEXP (operands
[1], 0);
773 return "fld.d %L1(%?r31),%0";
775 return "fld.d %1,%0";
777 else if (FP_REG_P (operands
[1]))
779 if (GET_CODE (operands
[0]) == REG
)
781 output_asm_insn ("fxfr %1,%0", operands
);
782 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
783 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
786 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
788 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
789 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
790 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
793 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
795 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
796 cc_status
.mdep
= XEXP (operands
[0], 0);
797 return "fst.d %1,%L0(%?r31)";
799 return "fst.d %1,%0";
807 /* Return a REG that occurs in ADDR with coefficient 1.
808 ADDR can be effectively incremented by incrementing REG. */
814 while (GET_CODE (addr
) == PLUS
)
816 if (GET_CODE (XEXP (addr
, 0)) == REG
)
817 addr
= XEXP (addr
, 0);
818 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
819 addr
= XEXP (addr
, 1);
820 else if (CONSTANT_P (XEXP (addr
, 0)))
821 addr
= XEXP (addr
, 1);
822 else if (CONSTANT_P (XEXP (addr
, 1)))
823 addr
= XEXP (addr
, 0);
827 if (GET_CODE (addr
) == REG
)
834 /* Return a template for a load instruction with mode MODE and
835 arguments from the string ARGS.
837 This string is in static storage. */
840 load_opcode (mode
, args
, reg
)
841 enum machine_mode mode
;
877 sprintf (buf
, "%s %s", opcode
, args
);
881 /* Return a template for a store instruction with mode MODE and
882 arguments from the string ARGS.
884 This string is in static storage. */
887 store_opcode (mode
, args
, reg
)
888 enum machine_mode mode
;
924 sprintf (buf
, "%s %s", opcode
, args
);
928 /* Output a store-in-memory whose operands are OPERANDS[0,1].
929 OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
931 This function returns a template for an insn.
932 This is in static storage.
934 It may also output some insns directly.
935 It may alter the values of operands[0] and operands[1]. */
938 output_store (operands
)
941 enum machine_mode mode
= GET_MODE (operands
[0]);
942 rtx address
= XEXP (operands
[0], 0);
945 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
946 cc_status
.mdep
= address
;
948 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
949 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
950 && address
== cc_prev_status
.mdep
))
953 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
954 cc_prev_status
.mdep
= address
;
957 /* Store zero in two parts when appropriate. */
958 if (mode
== DFmode
&& operands
[1] == CONST0_RTX (DFmode
))
959 return store_opcode (DFmode
, "%r1,%L0(%?r31)", operands
[1]);
961 /* Code below isn't smart enough to move a doubleword in two parts,
962 so use output_move_double to do that in the cases that require it. */
963 if ((mode
== DImode
|| mode
== DFmode
)
964 && ! FP_REG_P (operands
[1]))
965 return output_move_double (operands
);
967 return store_opcode (mode
, "%r1,%L0(%?r31)", operands
[1]);
970 /* Output a load-from-memory whose operands are OPERANDS[0,1].
971 OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
973 This function returns a template for an insn.
974 This is in static storage.
976 It may also output some insns directly.
977 It may alter the values of operands[0] and operands[1]. */
980 output_load (operands
)
983 enum machine_mode mode
= GET_MODE (operands
[0]);
984 rtx address
= XEXP (operands
[1], 0);
986 /* We don't bother trying to see if we know %hi(address).
987 This is because we are doing a load, and if we know the
988 %hi value, we probably also know that value in memory. */
989 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
990 cc_status
.mdep
= address
;
992 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
993 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
994 && address
== cc_prev_status
.mdep
995 && cc_prev_status
.mdep
== cc_status
.mdep
))
998 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
999 cc_prev_status
.mdep
= address
;
1002 /* Code below isn't smart enough to move a doubleword in two parts,
1003 so use output_move_double to do that in the cases that require it. */
1004 if ((mode
== DImode
|| mode
== DFmode
)
1005 && ! FP_REG_P (operands
[0]))
1006 return output_move_double (operands
);
1008 return load_opcode (mode
, "%L1(%?r31),%0", operands
[0]);
1012 /* Load the address specified by OPERANDS[3] into the register
1013 specified by OPERANDS[0].
1015 OPERANDS[3] may be the result of a sum, hence it could either be:
1020 (3) REG + REG + CONST_INT
1021 (4) REG + REG (special case of 3).
1023 Note that (3) is not a legitimate address.
1024 All cases are handled here. */
1027 output_load_address (operands
)
1032 if (CONSTANT_P (operands
[3]))
1034 output_asm_insn ("mov %3,%0", operands
);
1038 if (REG_P (operands
[3]))
1040 if (REGNO (operands
[0]) != REGNO (operands
[3]))
1041 output_asm_insn ("shl %?r0,%3,%0", operands
);
1045 if (GET_CODE (operands
[3]) != PLUS
)
1048 base
= XEXP (operands
[3], 0);
1049 offset
= XEXP (operands
[3], 1);
1051 if (GET_CODE (base
) == CONST_INT
)
1058 if (GET_CODE (offset
) != CONST_INT
)
1060 /* Operand is (PLUS (REG) (REG)). */
1062 offset
= const0_rtx
;
1068 operands
[7] = offset
;
1069 CC_STATUS_PARTIAL_INIT
;
1070 if (SMALL_INT (offset
))
1071 output_asm_insn ("adds %7,%6,%0", operands
);
1073 output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands
);
1075 else if (GET_CODE (base
) == PLUS
)
1077 operands
[6] = XEXP (base
, 0);
1078 operands
[7] = XEXP (base
, 1);
1079 operands
[8] = offset
;
1081 CC_STATUS_PARTIAL_INIT
;
1082 if (SMALL_INT (offset
))
1083 output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands
);
1085 output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands
);
1092 /* Output code to place a size count SIZE in register REG.
1093 Because block moves are pipelined, we don't include the
1094 first element in the transfer of SIZE to REG.
1095 For this, we subtract ALIGN. (Actually, I think it is not
1096 right to subtract on this machine, so right now we don't.) */
1099 output_size_for_block_move (size
, reg
, align
)
1100 rtx size
, reg
, align
;
1105 xoperands
[1] = size
;
1106 xoperands
[2] = align
;
1109 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
1110 output_asm_insn (singlemove_string (xoperands
), xoperands
);
1112 if (GET_CODE (size
) == REG
)
1113 output_asm_insn ("sub %2,%1,%0", xoperands
);
1117 = GEN_INT (INTVAL (size
) - INTVAL (align
));
1118 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
1119 output_asm_insn ("mov %1,%0", xoperands
);
1124 /* Emit code to perform a block move.
1126 OPERANDS[0] is the destination.
1127 OPERANDS[1] is the source.
1128 OPERANDS[2] is the size.
1129 OPERANDS[3] is the known safe alignment.
1130 OPERANDS[4..6] are pseudos we can safely clobber as temps. */
1133 output_block_move (operands
)
1136 /* A vector for our computed operands. Note that load_output_address
1137 makes use of (and can clobber) up to the 8th element of this vector. */
1140 static int movstrsi_label
= 0;
1142 rtx temp1
= operands
[4];
1143 rtx alignrtx
= operands
[3];
1144 int align
= INTVAL (alignrtx
);
1147 xoperands
[0] = operands
[0];
1148 xoperands
[1] = operands
[1];
1149 xoperands
[2] = temp1
;
1151 /* We can't move more than four bytes at a time
1152 because we have only one register to move them through. */
1156 alignrtx
= GEN_INT (4);
1159 /* Recognize special cases of block moves. These occur
1160 when GNU C++ is forced to treat something as BLKmode
1161 to keep it in memory, when its mode could be represented
1162 with something smaller.
1164 We cannot do this for global variables, since we don't know
1165 what pages they don't cross. Sigh. */
1166 if (GET_CODE (operands
[2]) == CONST_INT
1167 && ! CONSTANT_ADDRESS_P (operands
[0])
1168 && ! CONSTANT_ADDRESS_P (operands
[1]))
1170 int size
= INTVAL (operands
[2]);
1171 rtx op0
= xoperands
[0];
1172 rtx op1
= xoperands
[1];
1174 if ((align
& 3) == 0 && (size
& 3) == 0 && (size
>> 2) <= 16)
1176 if (memory_address_p (SImode
, plus_constant (op0
, size
))
1177 && memory_address_p (SImode
, plus_constant (op1
, size
)))
1179 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1180 for (i
= (size
>>2)-1; i
>= 0; i
--)
1182 xoperands
[0] = plus_constant (op0
, i
* 4);
1183 xoperands
[1] = plus_constant (op1
, i
* 4);
1184 output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
1190 else if ((align
& 1) == 0 && (size
& 1) == 0 && (size
>> 1) <= 16)
1192 if (memory_address_p (HImode
, plus_constant (op0
, size
))
1193 && memory_address_p (HImode
, plus_constant (op1
, size
)))
1195 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1196 for (i
= (size
>>1)-1; i
>= 0; i
--)
1198 xoperands
[0] = plus_constant (op0
, i
* 2);
1199 xoperands
[1] = plus_constant (op1
, i
* 2);
1200 output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
1206 else if (size
<= 16)
1208 if (memory_address_p (QImode
, plus_constant (op0
, size
))
1209 && memory_address_p (QImode
, plus_constant (op1
, size
)))
1211 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
1212 for (i
= size
-1; i
>= 0; i
--)
1214 xoperands
[0] = plus_constant (op0
, i
);
1215 xoperands
[1] = plus_constant (op1
, i
);
1216 output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
1224 /* Since we clobber untold things, nix the condition codes. */
1227 /* This is the size of the transfer.
1228 Either use the register which already contains the size,
1229 or use a free register (used by no operands). */
1230 output_size_for_block_move (operands
[2], operands
[4], alignrtx
);
1233 /* Also emit code to decrement the size value by ALIGN. */
1234 zoperands
[0] = operands
[0];
1235 zoperands
[3] = plus_constant (operands
[0], align
);
1236 output_load_address (zoperands
);
1239 /* Generate number for unique label. */
1241 xoperands
[3] = GEN_INT (movstrsi_label
++);
1243 /* Calculate the size of the chunks we will be trying to move first. */
1246 if ((align
& 3) == 0)
1248 else if ((align
& 1) == 0)
1254 /* Copy the increment (negative) to a register for bla insn. */
1256 xoperands
[4] = GEN_INT (- chunk_size
);
1257 xoperands
[5] = operands
[5];
1258 output_asm_insn ("adds %4,%?r0,%5", xoperands
);
1260 /* Predecrement the loop counter. This happens again also in the `bla'
1261 instruction which precedes the loop, but we need to have it done
1262 two times before we enter the loop because of the bizarre semantics
1263 of the bla instruction. */
1265 output_asm_insn ("adds %5,%2,%2", xoperands
);
1267 /* Check for the case where the original count was less than or equal to
1268 zero. Avoid going through the loop at all if the original count was
1269 indeed less than or equal to zero. Note that we treat the count as
1270 if it were a signed 32-bit quantity here, rather than an unsigned one,
1271 even though we really shouldn't. We have to do this because of the
1272 semantics of the `ble' instruction, which assume that the count is
1273 a signed 32-bit value. Anyway, in practice it won't matter because
1274 nobody is going to try to do a memcpy() of more than half of the
1275 entire address space (i.e. 2 gigabytes) anyway. */
1277 output_asm_insn ("bc .Le%3", xoperands
);
1279 /* Make available a register which is a temporary. */
1281 xoperands
[6] = operands
[6];
1283 /* Now the actual loop.
1284 In xoperands, elements 1 and 0 are the input and output vectors.
1285 Element 2 is the loop index. Element 5 is the increment. */
1287 output_asm_insn ("subs %1,%5,%1", xoperands
);
1288 output_asm_insn ("bla %5,%2,.Lm%3", xoperands
);
1289 output_asm_insn ("adds %0,%2,%6", xoperands
);
1290 output_asm_insn ("\n.Lm%3:", xoperands
); /* Label for bla above. */
1291 output_asm_insn ("\n.Ls%3:", xoperands
); /* Loop start label. */
1292 output_asm_insn ("adds %5,%6,%6", xoperands
);
1294 /* NOTE: The code here which is supposed to handle the cases where the
1295 sources and destinations are known to start on a 4 or 2 byte boundary
1296 are currently broken. They fail to do anything about the overflow
1297 bytes which might still need to be copied even after we have copied
1298 some number of words or halfwords. Thus, for now we use the lowest
1299 common denominator, i.e. the code which just copies some number of
1300 totally unaligned individual bytes. (See the calculation of
1301 chunk_size above. */
1303 if (chunk_size
== 4)
1305 output_asm_insn ("ld.l %2(%1),%?r31", xoperands
);
1306 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1307 output_asm_insn ("st.l %?r31,8(%6)", xoperands
);
1309 else if (chunk_size
== 2)
1311 output_asm_insn ("ld.s %2(%1),%?r31", xoperands
);
1312 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1313 output_asm_insn ("st.s %?r31,4(%6)", xoperands
);
1315 else /* chunk_size == 1 */
1317 output_asm_insn ("ld.b %2(%1),%?r31", xoperands
);
1318 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
1319 output_asm_insn ("st.b %?r31,2(%6)", xoperands
);
1321 output_asm_insn ("\n.Le%3:", xoperands
); /* Here if count <= 0. */
1326 /* Output a delayed branch insn with the delay insn in its
1327 branch slot. The delayed branch insn template is in TEMPLATE,
1328 with operands OPERANDS. The insn in its delay slot is INSN.
1330 As a special case, since we know that all memory transfers are via
1331 ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
1332 reference around the branch as
1336 ld/st l%x(%?r31),...
1338 As another special case, we handle loading (SYMBOL_REF ...) and
1339 other large constants around branches as well:
1348 output_delayed_branch (template, operands
, insn
)
1353 rtx src
= XVECEXP (PATTERN (insn
), 0, 1);
1354 rtx dest
= XVECEXP (PATTERN (insn
), 0, 0);
1356 /* See if we are doing some branch together with setting some register
1357 to some 32-bit value which does (or may) have some of the high-order
1358 16 bits set. If so, we need to set the register in two stages. One
1359 stage must be done before the branch, and the other one can be done
1360 in the delay slot. */
1362 if ( (GET_CODE (src
) == CONST_INT
1363 && ((unsigned) INTVAL (src
) & (unsigned) 0xffff0000) != (unsigned) 0)
1364 || (GET_CODE (src
) == SYMBOL_REF
)
1365 || (GET_CODE (src
) == LABEL_REF
)
1366 || (GET_CODE (src
) == CONST
))
1369 xoperands
[0] = dest
;
1372 CC_STATUS_PARTIAL_INIT
;
1373 /* Output the `orh' insn. */
1374 output_asm_insn ("orh %H1,%?r0,%0", xoperands
);
1376 /* Output the branch instruction next. */
1377 output_asm_insn (template, operands
);
1379 /* Now output the `or' insn. */
1380 output_asm_insn ("or %L1,%0,%0", xoperands
);
1382 else if ((GET_CODE (src
) == MEM
1383 && CONSTANT_ADDRESS_P (XEXP (src
, 0)))
1384 || (GET_CODE (dest
) == MEM
1385 && CONSTANT_ADDRESS_P (XEXP (dest
, 0))))
1388 char *split_template
;
1389 xoperands
[0] = dest
;
1392 /* Output the `orh' insn. */
1393 if (GET_CODE (src
) == MEM
)
1395 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1396 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1397 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
1400 output_asm_insn ("orh %h1,%?r0,%?r31", xoperands
);
1402 split_template
= load_opcode (GET_MODE (dest
),
1403 "%L1(%?r31),%0", dest
);
1407 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1408 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1409 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
1412 output_asm_insn ("orh %h0,%?r0,%?r31", xoperands
);
1414 split_template
= store_opcode (GET_MODE (dest
),
1415 "%r1,%L0(%?r31)", src
);
1418 /* Output the branch instruction next. */
1419 output_asm_insn (template, operands
);
1421 /* Now output the load or store.
1422 No need to do a CC_STATUS_INIT, because we are branching anyway. */
1423 output_asm_insn (split_template
, xoperands
);
1427 int insn_code_number
;
1428 rtx pat
= gen_rtx (SET
, VOIDmode
, dest
, src
);
1429 rtx delay_insn
= gen_rtx (INSN
, VOIDmode
, 0, 0, 0, pat
, -1, 0, 0);
1432 /* Output the branch instruction first. */
1433 output_asm_insn (template, operands
);
1435 /* Now recognize the insn which we put in its delay slot.
1436 We must do this after outputting the branch insn,
1437 since operands may just be a pointer to `recog_operand'. */
1438 INSN_CODE (delay_insn
) = insn_code_number
1439 = recog (pat
, delay_insn
, NULL_PTR
);
1440 if (insn_code_number
== -1)
1443 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1445 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1446 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1449 insn_extract (delay_insn
);
1450 if (! constrain_operands (insn_code_number
, 1))
1451 fatal_insn_not_found (delay_insn
);
1453 template = insn_template
[insn_code_number
];
1455 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1456 output_asm_insn (template, recog_operand
);
1462 /* Output a newly constructed insn DELAY_INSN. */
1464 output_delay_insn (delay_insn
)
1468 int insn_code_number
;
1471 /* Now recognize the insn which we put in its delay slot.
1472 We must do this after outputting the branch insn,
1473 since operands may just be a pointer to `recog_operand'. */
1474 insn_code_number
= recog_memoized (delay_insn
);
1475 if (insn_code_number
== -1)
1478 /* Extract the operands of this delay insn. */
1479 INSN_CODE (delay_insn
) = insn_code_number
;
1480 insn_extract (delay_insn
);
1482 /* It is possible that this insn has not been properly scanned by final
1483 yet. If this insn's operands don't appear in the peephole's
1484 actual operands, then they won't be fixed up by final, so we
1485 make sure they get fixed up here. -- This is a kludge. */
1486 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1488 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1489 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1492 #ifdef REGISTER_CONSTRAINTS
1493 if (! constrain_operands (insn_code_number
, 1))
1497 cc_prev_status
= cc_status
;
1499 /* Update `cc_status' for this instruction.
1500 The instruction's output routine may change it further.
1501 If the output routine for a jump insn needs to depend
1502 on the cc status, it should look at cc_prev_status. */
1504 NOTICE_UPDATE_CC (PATTERN (delay_insn
), delay_insn
);
1506 /* Now get the template for what this insn would
1507 have been, without the branch. */
1509 template = insn_template
[insn_code_number
];
1511 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1512 output_asm_insn (template, recog_operand
);
1516 /* Special routine to convert an SFmode value represented as a
1517 CONST_DOUBLE into its equivalent unsigned long bit pattern.
1518 We convert the value from a double precision floating-point
1519 value to single precision first, and thence to a bit-wise
1520 equivalent unsigned long value. This routine is used when
1521 generating an immediate move of an SFmode value directly
1522 into a general register because the svr4 assembler doesn't
1523 grok floating literals in instruction operand contexts. */
1526 sfmode_constant_to_ulong (x
)
1530 union { float f
; unsigned long i
; } u2
;
1532 if (GET_CODE (x
) != CONST_DOUBLE
|| GET_MODE (x
) != SFmode
)
1535 #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
1536 error IEEE emulation needed
1538 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1543 /* This function generates the assembly code for function entry.
1544 The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
1546 ASM_FILE is a stdio stream to output the code to.
1547 SIZE is an int: how many units of temporary storage to allocate.
1549 Refer to the array `regs_ever_live' to determine which registers
1550 to save; `regs_ever_live[I]' is nonzero if register number I
1551 is ever used in the function. This macro is responsible for
1552 knowing which registers should not be saved even if used.
1554 NOTE: `frame_lower_bytes' is the count of bytes which will lie
1555 between the new `fp' value and the new `sp' value after the
1556 prologue is done. `frame_upper_bytes' is the count of bytes
1557 that will lie between the new `fp' and the *old* `sp' value
1558 after the new `fp' is setup (in the prologue). The upper
1559 part of each frame always includes at least 2 words (8 bytes)
1560 to hold the saved frame pointer and the saved return address.
1562 The svr4 ABI for the i860 now requires that the values of the
1563 stack pointer and frame pointer registers be kept aligned to
1564 16-byte boundaries at all times. We obey that restriction here.
1566 The svr4 ABI for the i860 is entirely vague when it comes to specifying
1567 exactly where the "preserved" registers should be saved. The native
1568 svr4 C compiler I now have doesn't help to clarify the requirements
1569 very much because it is plainly out-of-date and non-ABI-compliant
1570 (in at least one important way, i.e. how it generates function
1573 The native svr4 C compiler saves the "preserved" registers (i.e.
1574 r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1575 offsets from the frame pointer).
1577 Previous versions of GCC also saved the "preserved" registers in the
1578 "negative" part of the frame, but they saved them using positive
1579 offsets from the (adjusted) stack pointer (after it had been adjusted
1580 to allocate space for the new frame). That's just plain wrong
1581 because if the current function calls alloca(), the stack pointer
1582 will get moved, and it will be impossible to restore the registers
1583 properly again after that.
1585 Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1586 by copying their values either into various "preserved" registers or
1587 into stack slots in the lower part of the current frame (as seemed
1588 appropriate, depending upon subsequent usage of these values).
1590 Here we want to save the preserved registers at some offset from the
1591 frame pointer register so as to avoid any possible problems arising
1592 from calls to alloca(). We can either save them at small positive
1593 offsets from the frame pointer, or at small negative offsets from
1594 the frame pointer. If we save them at small negative offsets from
1595 the frame pointer (i.e. in the lower part of the frame) then we
1596 must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1597 many bytes of space we plan to use in the lower part of the frame
1598 for this purpose. Since other parts of the compiler reference the
1599 value of STARTING_FRAME_OFFSET long before final() calls this function,
1600 we would have to go ahead and assume the worst-case storage requirements
1601 for saving all of the "preserved" registers (and use that number, i.e.
1602 `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1603 the lower part of the frame. That could potentially be very wasteful,
1604 and that wastefulness could really hamper people compiling for embedded
1605 i860 targets with very tight limits on stack space. Thus, we choose
1606 here to save the preserved registers in the upper part of the
1607 frame, so that we can decide at the very last minute how much (or how
1608 little) space we must allocate for this purpose.
1610 To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
1611 registers must always be saved so that the saved values of registers
1612 with higher numbers are at higher addresses. We obey that restriction
1615 There are two somewhat different ways that you can generate prologues
1616 here... i.e. pedantically ABI-compliant, and the "other" way. The
1617 "other" way is more consistent with what is currently generated by the
1618 "native" svr4 C compiler for the i860. That's important if you want
1619 to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
1620 The SVR4 SDB for the i860 insists on having function prologues be
1623 To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1624 in the i860svr4.h file. (By default this is *not* defined).
1626 The differences between the ABI-compliant and non-ABI-compliant prologues
1627 are that (a) the ABI version seems to require the use of *signed*
1628 (rather than unsigned) adds and subtracts, and (b) the ordering of
1629 the various steps (e.g. saving preserved registers, saving the
1630 return address, setting up the new frame pointer value) is different.
1632 For strict ABI compliance, it seems to be the case that the very last
1633 thing that is supposed to happen in the prologue is getting the frame
1634 pointer set to its new value (but only after everything else has
1635 already been properly setup). We do that here, but only if the symbol
1636 I860_STRICT_ABI_PROLOGUES is defined.
1639 #ifndef STACK_ALIGNMENT
1640 #define STACK_ALIGNMENT 16
1643 extern char call_used_regs
[];
1644 extern int leaf_function_p ();
1646 char *current_function_original_name
;
1648 static int must_preserve_r1
;
1649 static unsigned must_preserve_bytes
;
1652 function_prologue (asm_file
, local_bytes
)
1653 register FILE *asm_file
;
1654 register unsigned local_bytes
;
1656 register unsigned frame_lower_bytes
;
1657 register unsigned frame_upper_bytes
;
1658 register unsigned total_fsize
;
1659 register unsigned preserved_reg_bytes
= 0;
1660 register unsigned i
;
1661 register unsigned preserved_so_far
= 0;
1663 must_preserve_r1
= (optimize
< 2 || ! leaf_function_p ());
1664 must_preserve_bytes
= 4 + (must_preserve_r1
? 4 : 0);
1666 /* Count registers that need preserving. Ignore r0. It never needs
1669 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
1671 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1672 preserved_reg_bytes
+= 4;
1675 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1677 frame_lower_bytes
= (local_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1679 /* The upper part of each frame will contain the saved fp,
1680 the saved r1, and stack slots for all of the other "preserved"
1681 registers that we find we will need to save & restore. */
1683 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
1685 /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1688 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1690 total_fsize
= frame_upper_bytes
+ frame_lower_bytes
;
1692 #ifndef I860_STRICT_ABI_PROLOGUES
1694 /* There are two kinds of function prologues.
1695 You use the "small" version if the total frame size is
1696 small enough so that it can fit into an immediate 16-bit
1697 value in one instruction. Otherwise, you use the "large"
1698 version of the function prologue. */
1700 if (total_fsize
> 0x7fff)
1702 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1703 but the native C compiler on svr4 uses `addu'. */
1705 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1706 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1708 /* Save the old frame pointer. */
1710 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1711 i860_reg_prefix
, i860_reg_prefix
);
1713 /* Setup the new frame pointer. The ABI sez to do this after
1714 preserving registers (using adds), but that's not what the
1715 native C compiler on svr4 does. */
1717 fprintf (asm_file
, "\taddu 0,%ssp,%sfp\n",
1718 i860_reg_prefix
, i860_reg_prefix
);
1720 /* Get the value of frame_lower_bytes into r31. */
1722 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1723 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1724 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1725 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1727 /* Now re-adjust the stack pointer using the value in r31.
1728 The ABI sez to do this with `subs' but SDB may prefer `subu'. */
1730 fprintf (asm_file
, "\tsubu %ssp,%sr31,%ssp\n",
1731 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1733 /* Preserve registers. The ABI sez to do this before setting
1734 up the new frame pointer, but that's not what the native
1735 C compiler on svr4 does. */
1737 for (i
= 1; i
< 32; i
++)
1738 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1739 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1740 i860_reg_prefix
, reg_names
[i
],
1741 must_preserve_bytes
+ (4 * preserved_so_far
++),
1744 for (i
= 32; i
< 64; i
++)
1745 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1746 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1747 i860_reg_prefix
, reg_names
[i
],
1748 must_preserve_bytes
+ (4 * preserved_so_far
++),
1751 /* Save the return address. */
1753 if (must_preserve_r1
)
1754 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1755 i860_reg_prefix
, i860_reg_prefix
);
1759 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1760 but the native C compiler on svr4 uses `addu'. */
1762 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1763 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1765 /* Save the old frame pointer. */
1767 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1768 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1770 /* Setup the new frame pointer. The ABI sez to do this after
1771 preserving registers and after saving the return address,
1772 (and its saz to do this using adds), but that's not what the
1773 native C compiler on svr4 does. */
1775 fprintf (asm_file
, "\taddu %d,%ssp,%sfp\n",
1776 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1778 /* Preserve registers. The ABI sez to do this before setting
1779 up the new frame pointer, but that's not what the native
1780 compiler on svr4 does. */
1782 for (i
= 1; i
< 32; i
++)
1783 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1784 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1785 i860_reg_prefix
, reg_names
[i
],
1786 must_preserve_bytes
+ (4 * preserved_so_far
++),
1789 for (i
= 32; i
< 64; i
++)
1790 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1791 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1792 i860_reg_prefix
, reg_names
[i
],
1793 must_preserve_bytes
+ (4 * preserved_so_far
++),
1796 /* Save the return address. The ABI sez to do this earlier,
1797 and also via an offset from %sp, but the native C compiler
1798 on svr4 does it later (i.e. now) and uses an offset from
1801 if (must_preserve_r1
)
1802 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1803 i860_reg_prefix
, i860_reg_prefix
);
1806 #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1808 /* There are two kinds of function prologues.
1809 You use the "small" version if the total frame size is
1810 small enough so that it can fit into an immediate 16-bit
1811 value in one instruction. Otherwise, you use the "large"
1812 version of the function prologue. */
1814 if (total_fsize
> 0x7fff)
1816 /* Adjust the stack pointer (thereby allocating a new frame). */
1818 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1819 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1821 /* Save the caller's frame pointer. */
1823 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1824 i860_reg_prefix
, i860_reg_prefix
);
1826 /* Save return address. */
1828 if (must_preserve_r1
)
1829 fprintf (asm_file
, "\tst.l %sr1,4(%ssp)\n",
1830 i860_reg_prefix
, i860_reg_prefix
);
1832 /* Get the value of frame_lower_bytes into r31 for later use. */
1834 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1835 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1836 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1837 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1839 /* Now re-adjust the stack pointer using the value in r31. */
1841 fprintf (asm_file
, "\tsubs %ssp,%sr31,%ssp\n",
1842 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1844 /* Pre-compute value to be used as the new frame pointer. */
1846 fprintf (asm_file
, "\tadds %ssp,%sr31,%sr31\n",
1847 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1849 /* Preserve registers. */
1851 for (i
= 1; i
< 32; i
++)
1852 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1853 fprintf (asm_file
, "\tst.l %s%s,%d(%sr31)\n",
1854 i860_reg_prefix
, reg_names
[i
],
1855 must_preserve_bytes
+ (4 * preserved_so_far
++),
1858 for (i
= 32; i
< 64; i
++)
1859 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1860 fprintf (asm_file
, "\tfst.l %s%s,%d(%sr31)\n",
1861 i860_reg_prefix
, reg_names
[i
],
1862 must_preserve_bytes
+ (4 * preserved_so_far
++),
1865 /* Actually set the new value of the frame pointer. */
1867 fprintf (asm_file
, "\tmov %sr31,%sfp\n",
1868 i860_reg_prefix
, i860_reg_prefix
);
1872 /* Adjust the stack pointer. */
1874 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1875 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1877 /* Save the caller's frame pointer. */
1879 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1880 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1882 /* Save the return address. */
1884 if (must_preserve_r1
)
1885 fprintf (asm_file
, "\tst.l %sr1,%d(%ssp)\n",
1886 i860_reg_prefix
, frame_lower_bytes
+ 4, i860_reg_prefix
);
1888 /* Preserve registers. */
1890 for (i
= 1; i
< 32; i
++)
1891 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1892 fprintf (asm_file
, "\tst.l %s%s,%d(%ssp)\n",
1893 i860_reg_prefix
, reg_names
[i
],
1894 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1897 for (i
= 32; i
< 64; i
++)
1898 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1899 fprintf (asm_file
, "\tfst.l %s%s,%d(%ssp)\n",
1900 i860_reg_prefix
, reg_names
[i
],
1901 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1904 /* Setup the new frame pointer. */
1906 fprintf (asm_file
, "\tadds %d,%ssp,%sfp\n",
1907 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1909 #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1911 #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
1912 ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file
);
1913 #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
1916 /* This function generates the assembly code for function exit.
1917 The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
1919 ASM_FILE is a stdio stream to output the code to.
1920 SIZE is an int: how many units of temporary storage to allocate.
1922 The function epilogue should not depend on the current stack pointer!
1923 It should use the frame pointer only. This is mandatory because
1924 of alloca; we also take advantage of it to omit stack adjustments
1927 Note that when we go to restore the preserved register values we must
1928 not try to address their slots by using offsets from the stack pointer.
1929 That's because the stack pointer may have been moved during the function
1930 execution due to a call to alloca(). Rather, we must restore all
1931 preserved registers via offsets from the frame pointer value.
1933 Note also that when the current frame is being "popped" (by adjusting
1934 the value of the stack pointer) on function exit, we must (for the
1935 sake of alloca) set the new value of the stack pointer based upon
1936 the current value of the frame pointer. We can't just add what we
1937 believe to be the (static) frame size to the stack pointer because
1938 if we did that, and alloca() had been called during this function,
1939 we would end up returning *without* having fully deallocated all of
1940 the space grabbed by alloca. If that happened, and a function
1941 containing one or more alloca() calls was called over and over again,
1942 then the stack would grow without limit!
1944 Finally note that the epilogues generated here are completely ABI
1945 compliant. They go out of their way to insure that the value in
1946 the frame pointer register is never less than the value in the stack
1947 pointer register. It's not clear why this relationship needs to be
1948 maintained at all times, but maintaining it only costs one extra
1949 instruction, so what the hell.
1952 /* This corresponds to a version 4 TDESC structure. Lower numbered
1953 versions successively omit the last word of the structure. We
1954 don't try to handle version 5 here. */
1956 typedef struct TDESC_flags
{
1959 int callable_block
:1;
1961 int fregs
:6; /* fp regs 2-7 */
1962 int iregs
:16; /* regs 0-15 */
1965 typedef struct TDESC
{
1967 int integer_reg_offset
; /* same as must_preserve_bytes */
1968 int floating_point_reg_offset
;
1969 unsigned int positive_frame_size
; /* same as frame_upper_bytes */
1970 unsigned int negative_frame_size
; /* same as frame_lower_bytes */
1974 function_epilogue (asm_file
, local_bytes
)
1975 register FILE *asm_file
;
1976 register unsigned local_bytes
;
1978 register unsigned frame_upper_bytes
;
1979 register unsigned frame_lower_bytes
;
1980 register unsigned preserved_reg_bytes
= 0;
1981 register unsigned i
;
1982 register unsigned restored_so_far
= 0;
1983 register unsigned int_restored
;
1984 register unsigned mask
;
1985 unsigned intflags
=0;
1986 register TDESC_flags
*flags
= (TDESC_flags
*) &intflags
;
1989 flags
->reg_packing
= 1;
1990 flags
->iregs
= 8; /* old fp always gets saved */
1992 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1994 frame_lower_bytes
= (local_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1996 /* Count the number of registers that were preserved in the prologue.
1997 Ignore r0. It is never preserved. */
1999 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
2001 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2002 preserved_reg_bytes
+= 4;
2005 /* The upper part of each frame will contain only saved fp,
2006 the saved r1, and stack slots for all of the other "preserved"
2007 registers that we find we will need to save & restore. */
2009 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
2011 /* Round-up frame_upper_bytes so that t is a multiple of 16. */
2014 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
2016 /* Restore all of the "preserved" registers that need restoring. */
2020 for (i
= 1; i
< 32; i
++, mask
<<=1)
2021 if (regs_ever_live
[i
] && ! call_used_regs
[i
]) {
2022 fprintf (asm_file
, "\tld.l %d(%sfp),%s%s\n",
2023 must_preserve_bytes
+ (4 * restored_so_far
++),
2024 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
2025 if (i
> 3 && i
< 16)
2026 flags
->iregs
|= mask
;
2029 int_restored
= restored_so_far
;
2032 for (i
= 32; i
< 64; i
++) {
2033 if (regs_ever_live
[i
] && ! call_used_regs
[i
]) {
2034 fprintf (asm_file
, "\tfld.l %d(%sfp),%s%s\n",
2035 must_preserve_bytes
+ (4 * restored_so_far
++),
2036 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
2037 if (i
> 33 & i
< 40)
2038 flags
->fregs
|= mask
;
2040 if (i
> 33 && i
< 40)
2044 /* Get the value we plan to use to restore the stack pointer into r31. */
2046 fprintf (asm_file
, "\tadds %d,%sfp,%sr31\n",
2047 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
2049 /* Restore the return address and the old frame pointer. */
2051 if (must_preserve_r1
) {
2052 fprintf (asm_file
, "\tld.l 4(%sfp),%sr1\n",
2053 i860_reg_prefix
, i860_reg_prefix
);
2057 fprintf (asm_file
, "\tld.l 0(%sfp),%sfp\n",
2058 i860_reg_prefix
, i860_reg_prefix
);
2060 /* Return and restore the old stack pointer value. */
2062 fprintf (asm_file
, "\tbri %sr1\n\tmov %sr31,%ssp\n",
2063 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
2065 #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
2066 if (! frame_lower_bytes
) {
2068 if (! frame_upper_bytes
) {
2070 if (restored_so_far
== int_restored
) /* No FP saves */
2074 assemble_name(asm_file
,current_function_original_name
);
2075 fputs(".TDESC:\n", asm_file
);
2076 fprintf(asm_file
, "%s 0x%0x\n", ASM_LONG
, intflags
);
2077 fprintf(asm_file
, "%s %d\n", ASM_LONG
,
2078 int_restored
? must_preserve_bytes
: 0);
2079 if (flags
->version
> 1) {
2080 fprintf(asm_file
, "%s %d\n", ASM_LONG
,
2081 (restored_so_far
== int_restored
) ? 0 : must_preserve_bytes
+
2082 (4 * int_restored
));
2083 if (flags
->version
> 2) {
2084 fprintf(asm_file
, "%s %d\n", ASM_LONG
, frame_upper_bytes
);
2085 if (flags
->version
> 3)
2086 fprintf(asm_file
, "%s %d\n", ASM_LONG
, frame_lower_bytes
);
2090 fprintf(asm_file
, "%s ", ASM_LONG
);
2091 assemble_name(asm_file
, current_function_original_name
);
2092 fprintf(asm_file
, "\n%s ", ASM_LONG
);
2093 assemble_name(asm_file
, current_function_original_name
);
2094 fputs(".TDESC\n", asm_file
);