2 /* Return non-zero only if OP is a register of mode MODE,
5 reg_or_0_operand (op
, mode
)
7 enum machine_mode mode
;
9 return (op
== const0_rtx
|| register_operand (op
, mode
)
10 || op
== CONST0_RTX (mode
));
13 /* Return truth value of whether OP can be used as an operands in a three
14 address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
17 arith_operand (op
, mode
)
19 enum machine_mode mode
;
21 return (register_operand (op
, mode
)
22 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
25 /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
28 logic_operand (op
, mode
)
30 enum machine_mode mode
;
32 return (register_operand (op
, mode
)
33 || (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
)));
36 /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
39 shift_operand (op
, mode
)
41 enum machine_mode mode
;
43 return (register_operand (op
, mode
)
44 || (GET_CODE (op
) == CONST_INT
));
47 /* Return 1 if OP is a valid first operand for either a logical insn
48 or an add insn of mode MODE. */
51 compare_operand (op
, mode
)
53 enum machine_mode mode
;
55 return (register_operand (op
, mode
)
56 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
) && LOGIC_INT (op
)));
59 /* Return truth value of whether OP can be used as the 5-bit immediate
60 operand of a bte or btne insn. */
63 bte_operand (op
, mode
)
65 enum machine_mode mode
;
67 return (register_operand (op
, mode
)
68 || (GET_CODE (op
) == CONST_INT
69 && (unsigned) INTVAL (op
) < 0x20));
72 /* Return 1 if OP is an indexed memory reference of mode MODE. */
75 indexed_operand (op
, mode
)
77 enum machine_mode mode
;
79 return (GET_CODE (op
) == MEM
&& GET_MODE (op
) == mode
80 && GET_CODE (XEXP (op
, 0)) == PLUS
81 && GET_MODE (XEXP (op
, 0)) == SImode
82 && register_operand (XEXP (XEXP (op
, 0), 0), SImode
)
83 && register_operand (XEXP (XEXP (op
, 0), 1), SImode
));
86 /* Return 1 if OP is a suitable source operand for a load insn
90 load_operand (op
, mode
)
92 enum machine_mode mode
;
94 return (memory_operand (op
, mode
) || indexed_operand (op
, mode
));
97 /* Return truth value of whether OP is a integer which fits the
98 range constraining immediate operands in add/subtract insns. */
103 enum machine_mode mode
;
105 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
108 /* Return truth value of whether OP is a integer which fits the
109 range constraining immediate operands in logic insns. */
114 enum machine_mode mode
;
116 return (GET_CODE (op
) == CONST_INT
&& LOGIC_INT (op
));
119 /* Return the best assembler insn template
120 for moving operands[1] into operands[0] as a fullword. */
123 singlemove_string (operands
)
126 if (GET_CODE (operands
[0]) == MEM
)
128 if (GET_CODE (operands
[1]) != MEM
)
129 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
131 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
132 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
133 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
136 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
138 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
139 cc_status
.mdep
= XEXP (operands
[0], 0);
140 return "st.l %r1,%L0(%?r31)";
143 return "st.l %r1,%0";
150 cc_status
.flags
&= ~CC_F0_IS_0
;
151 xoperands
[0] = gen_rtx (REG
, SFmode
, 32);
152 xoperands
[1] = operands
[1];
153 output_asm_insn (singlemove_string (xoperands
), xoperands
);
154 xoperands
[1] = xoperands
[0];
155 xoperands
[0] = operands
[0];
156 output_asm_insn (singlemove_string (xoperands
), xoperands
);
161 if (GET_CODE (operands
[1]) == MEM
)
163 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
165 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
166 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
167 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
170 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
172 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
173 cc_status
.mdep
= XEXP (operands
[1], 0);
174 return "ld.l %L1(%?r31),%0";
176 return "ld.l %m1,%0";
178 if (GET_CODE (operands
[1]) == CONST_INT
)
180 if (operands
[1] == const0_rtx
)
181 return "mov %?r0,%0";
182 if((INTVAL (operands
[1]) & 0xffff0000) == 0)
183 return "or %L1,%?r0,%0";
184 if((INTVAL (operands
[1]) & 0xffff8000) == 0xffff8000)
185 return "adds %1,%?r0,%0";
186 if((INTVAL (operands
[1]) & 0x0000ffff) == 0)
187 return "orh %H1,%?r0,%0";
192 /* Output assembler code to perform a doubleword move insn
193 with operands OPERANDS. */
196 output_move_double (operands
)
199 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype0
, optype1
;
201 rtx addreg0
= 0, addreg1
= 0;
203 /* First classify both operands. */
205 if (REG_P (operands
[0]))
207 else if (offsettable_memref_p (operands
[0]))
209 else if (GET_CODE (operands
[0]) == MEM
)
214 if (REG_P (operands
[1]))
216 else if (CONSTANT_P (operands
[1]))
218 else if (offsettable_memref_p (operands
[1]))
220 else if (GET_CODE (operands
[1]) == MEM
)
225 /* Check for the cases that the operand constraints are not
226 supposed to allow to happen. Abort if we get one,
227 because generating code for these cases is painful. */
229 if (optype0
== RNDOP
|| optype1
== RNDOP
)
232 /* If an operand is an unoffsettable memory ref, find a register
233 we can increment temporarily to make it refer to the second word. */
235 if (optype0
== MEMOP
)
236 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
238 if (optype1
== MEMOP
)
239 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
241 /* ??? Perhaps in some cases move double words
242 if there is a spare pair of floating regs. */
244 /* Ok, we can do one word at a time.
245 Normally we do the low-numbered word first,
246 but if either operand is autodecrementing then we
247 do the high-numbered word first.
249 In either case, set up in LATEHALF the operands to use
250 for the high-numbered word and in some cases alter the
251 operands in OPERANDS to be suitable for the low-numbered word. */
253 if (optype0
== REGOP
)
254 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
255 else if (optype0
== OFFSOP
)
256 latehalf
[0] = adj_offsettable_operand (operands
[0], 4);
258 latehalf
[0] = operands
[0];
260 if (optype1
== REGOP
)
261 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
262 else if (optype1
== OFFSOP
)
263 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
264 else if (optype1
== CNSTOP
)
266 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
267 split_double (operands
[1], &operands
[1], &latehalf
[1]);
268 else if (CONSTANT_P (operands
[1]))
269 latehalf
[1] = const0_rtx
;
272 latehalf
[1] = operands
[1];
274 /* If the first move would clobber the source of the second one,
275 do them in the other order.
277 RMS says "This happens only for registers;
278 such overlap can't happen in memory unless the user explicitly
279 sets it up, and that is an undefined circumstance."
281 but it happens on the sparc when loading parameter registers,
282 so I am going to define that circumstance, and make it work
285 if (optype0
== REGOP
&& optype1
== REGOP
286 && REGNO (operands
[0]) == REGNO (latehalf
[1]))
288 CC_STATUS_PARTIAL_INIT
;
289 /* Make any unoffsettable addresses point at high-numbered word. */
291 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
293 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
296 output_asm_insn (singlemove_string (latehalf
), latehalf
);
298 /* Undo the adds we just did. */
300 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
302 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
304 /* Do low-numbered word. */
305 return singlemove_string (operands
);
307 else if (optype0
== REGOP
&& optype1
!= REGOP
308 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
310 /* Do the late half first. */
311 output_asm_insn (singlemove_string (latehalf
), latehalf
);
313 return singlemove_string (operands
);
316 /* Normal case: do the two words, low-numbered first. */
318 output_asm_insn (singlemove_string (operands
), operands
);
320 CC_STATUS_PARTIAL_INIT
;
321 /* Make any unoffsettable addresses point at high-numbered word. */
323 output_asm_insn ("adds 0x4,%0,%0", &addreg0
);
325 output_asm_insn ("adds 0x4,%0,%0", &addreg1
);
328 output_asm_insn (singlemove_string (latehalf
), latehalf
);
330 /* Undo the adds we just did. */
332 output_asm_insn ("adds -0x4,%0,%0", &addreg0
);
334 output_asm_insn ("adds -0x4,%0,%0", &addreg1
);
340 output_fp_move_double (operands
)
343 /* If the source operand is any sort of zero, use f0 instead. */
345 if (operands
[1] == CONST0_RTX (GET_MODE (operands
[1])))
346 operands
[1] = gen_rtx (REG
, DFmode
, F0_REGNUM
);
348 if (FP_REG_P (operands
[0]))
350 if (FP_REG_P (operands
[1]))
351 return "fmov.dd %1,%0";
352 if (GET_CODE (operands
[1]) == REG
)
354 output_asm_insn ("ixfr %1,%0", operands
);
355 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
356 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
359 if (operands
[1] == CONST0_RTX (DFmode
))
360 return "fmov.dd f0,%0";
361 if (CONSTANT_ADDRESS_P (XEXP (operands
[1], 0)))
363 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
364 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
365 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
368 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
370 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
371 cc_status
.mdep
= XEXP (operands
[1], 0);
372 return "fld.d %L1(%?r31),%0";
374 return "fld.d %1,%0";
376 else if (FP_REG_P (operands
[1]))
378 if (GET_CODE (operands
[0]) == REG
)
380 output_asm_insn ("fxfr %1,%0", operands
);
381 operands
[0] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[0]) + 1);
382 operands
[1] = gen_rtx (REG
, VOIDmode
, REGNO (operands
[1]) + 1);
385 if (CONSTANT_ADDRESS_P (XEXP (operands
[0], 0)))
387 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
388 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
389 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
392 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
394 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
395 cc_status
.mdep
= XEXP (operands
[0], 0);
396 return "fst.d %1,%L0(%?r31)";
398 return "fst.d %1,%0";
406 /* Return a REG that occurs in ADDR with coefficient 1.
407 ADDR can be effectively incremented by incrementing REG. */
413 while (GET_CODE (addr
) == PLUS
)
415 if (GET_CODE (XEXP (addr
, 0)) == REG
)
416 addr
= XEXP (addr
, 0);
417 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
418 addr
= XEXP (addr
, 1);
419 else if (CONSTANT_P (XEXP (addr
, 0)))
420 addr
= XEXP (addr
, 1);
421 else if (CONSTANT_P (XEXP (addr
, 1)))
422 addr
= XEXP (addr
, 0);
426 if (GET_CODE (addr
) == REG
)
433 /* Return a template for a load instruction with mode MODE and
434 arguments from the string ARGS.
436 This string is in static storage. */
439 load_opcode (mode
, args
, reg
)
440 enum machine_mode mode
;
476 sprintf (buf
, "%s %s", opcode
, args
);
480 /* Return a template for a store instruction with mode MODE and
481 arguments from the string ARGS.
483 This string is in static storage. */
486 store_opcode (mode
, args
, reg
)
487 enum machine_mode mode
;
523 sprintf (buf
, "%s %s", opcode
, args
);
527 /* Output a store-in-memory whose operands are OPERANDS[0,1].
528 OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
530 This function returns a template for an insn.
531 This is in static storage.
533 It may also output some insns directly.
534 It may alter the values of operands[0] and operands[1]. */
537 output_store (operands
)
540 enum machine_mode mode
= GET_MODE (operands
[0]);
541 rtx address
= XEXP (operands
[0], 0);
544 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
545 cc_status
.mdep
= address
;
547 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
548 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
549 && address
== cc_prev_status
.mdep
))
552 output_asm_insn ("orh %h0,%?r0,%?r31", operands
);
553 cc_prev_status
.mdep
= address
;
556 /* Store zero in two parts when appropriate. */
557 if (mode
== DFmode
&& operands
[1] == CONST0_RTX (DFmode
))
558 return store_opcode (DFmode
, "%r1,%L0(%?r31)", operands
[1]);
560 /* Code below isn't smart enough to move a doubleword in two parts,
561 so use output_move_double to do that in the cases that require it. */
562 if ((mode
== DImode
|| mode
== DFmode
)
563 && ! FP_REG_P (operands
[1]))
564 return output_move_double (operands
);
566 return store_opcode (mode
, "%r1,%L0(%?r31)", operands
[1]);
569 /* Output a load-from-memory whose operands are OPERANDS[0,1].
570 OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
572 This function returns a template for an insn.
573 This is in static storage.
575 It may also output some insns directly.
576 It may alter the values of operands[0] and operands[1]. */
579 output_load (operands
)
582 enum machine_mode mode
= GET_MODE (operands
[0]);
583 rtx address
= XEXP (operands
[1], 0);
585 /* We don't bother trying to see if we know %hi(address).
586 This is because we are doing a load, and if we know the
587 %hi value, we probably also know that value in memory. */
588 cc_status
.flags
|= CC_KNOW_HI_R31
| CC_HI_R31_ADJ
;
589 cc_status
.mdep
= address
;
591 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
592 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
593 && address
== cc_prev_status
.mdep
594 && cc_prev_status
.mdep
== cc_status
.mdep
))
597 output_asm_insn ("orh %h1,%?r0,%?r31", operands
);
598 cc_prev_status
.mdep
= address
;
601 /* Code below isn't smart enough to move a doubleword in two parts,
602 so use output_move_double to do that in the cases that require it. */
603 if ((mode
== DImode
|| mode
== DFmode
)
604 && ! FP_REG_P (operands
[0]))
605 return output_move_double (operands
);
607 return load_opcode (mode
, "%L1(%?r31),%0", operands
[0]);
611 /* Load the address specified by OPERANDS[3] into the register
612 specified by OPERANDS[0].
614 OPERANDS[3] may be the result of a sum, hence it could either be:
619 (3) REG + REG + CONST_INT
620 (4) REG + REG (special case of 3).
622 Note that (3) is not a legitimate address.
623 All cases are handled here. */
626 output_load_address (operands
)
631 if (CONSTANT_P (operands
[3]))
633 output_asm_insn ("mov %3,%0", operands
);
637 if (REG_P (operands
[3]))
639 if (REGNO (operands
[0]) != REGNO (operands
[3]))
640 output_asm_insn ("shl %?r0,%3,%0", operands
);
644 if (GET_CODE (operands
[3]) != PLUS
)
647 base
= XEXP (operands
[3], 0);
648 offset
= XEXP (operands
[3], 1);
650 if (GET_CODE (base
) == CONST_INT
)
657 if (GET_CODE (offset
) != CONST_INT
)
659 /* Operand is (PLUS (REG) (REG)). */
667 operands
[7] = offset
;
668 CC_STATUS_PARTIAL_INIT
;
669 if (SMALL_INT (offset
))
670 output_asm_insn ("adds %7,%6,%0", operands
);
672 output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands
);
674 else if (GET_CODE (base
) == PLUS
)
676 operands
[6] = XEXP (base
, 0);
677 operands
[7] = XEXP (base
, 1);
678 operands
[8] = offset
;
680 CC_STATUS_PARTIAL_INIT
;
681 if (SMALL_INT (offset
))
682 output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands
);
684 output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands
);
691 /* Output code to place a size count SIZE in register REG.
692 Because block moves are pipelined, we don't include the
693 first element in the transfer of SIZE to REG.
694 For this, we subtract ALIGN. (Actually, I think it is not
695 right to subtract on this machine, so right now we don't.) */
698 output_size_for_block_move (size
, reg
, align
)
699 rtx size
, reg
, align
;
705 xoperands
[2] = align
;
708 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
709 output_asm_insn (singlemove_string (xoperands
), xoperands
);
711 if (GET_CODE (size
) == REG
)
712 output_asm_insn ("sub %2,%1,%0", xoperands
);
716 = gen_rtx (CONST_INT
, VOIDmode
, INTVAL (size
) - INTVAL (align
));
717 cc_status
.flags
&= ~ CC_KNOW_HI_R31
;
718 output_asm_insn ("mov %1,%0", xoperands
);
723 /* Emit code to perform a block move.
725 OPERANDS[0] is the destination.
726 OPERANDS[1] is the source.
727 OPERANDS[2] is the size.
728 OPERANDS[3] is the known safe alignment.
729 OPERANDS[4..6] are pseudos we can safely clobber as temps. */
732 output_block_move (operands
)
735 /* A vector for our computed operands. Note that load_output_address
736 makes use of (and can clobber) up to the 8th element of this vector. */
739 static int movstrsi_label
= 0;
741 rtx temp1
= operands
[4];
742 rtx alignrtx
= operands
[3];
743 int align
= INTVAL (alignrtx
);
746 xoperands
[0] = operands
[0];
747 xoperands
[1] = operands
[1];
748 xoperands
[2] = temp1
;
750 /* We can't move more than four bytes at a time
751 because we have only one register to move them through. */
755 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, 4);
758 /* Recognize special cases of block moves. These occur
759 when GNU C++ is forced to treat something as BLKmode
760 to keep it in memory, when its mode could be represented
761 with something smaller.
763 We cannot do this for global variables, since we don't know
764 what pages they don't cross. Sigh. */
765 if (GET_CODE (operands
[2]) == CONST_INT
766 && ! CONSTANT_ADDRESS_P (operands
[0])
767 && ! CONSTANT_ADDRESS_P (operands
[1]))
769 int size
= INTVAL (operands
[2]);
770 rtx op0
= xoperands
[0];
771 rtx op1
= xoperands
[1];
773 if ((align
& 3) == 0 && (size
& 3) == 0 && (size
>> 2) <= 16)
775 if (memory_address_p (SImode
, plus_constant (op0
, size
))
776 && memory_address_p (SImode
, plus_constant (op1
, size
)))
778 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
779 for (i
= (size
>>2)-1; i
>= 0; i
--)
781 xoperands
[0] = plus_constant (op0
, i
* 4);
782 xoperands
[1] = plus_constant (op1
, i
* 4);
783 output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
789 else if ((align
& 1) == 0 && (size
& 1) == 0 && (size
>> 1) <= 16)
791 if (memory_address_p (HImode
, plus_constant (op0
, size
))
792 && memory_address_p (HImode
, plus_constant (op1
, size
)))
794 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
795 for (i
= (size
>>1)-1; i
>= 0; i
--)
797 xoperands
[0] = plus_constant (op0
, i
* 2);
798 xoperands
[1] = plus_constant (op1
, i
* 2);
799 output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
807 if (memory_address_p (QImode
, plus_constant (op0
, size
))
808 && memory_address_p (QImode
, plus_constant (op1
, size
)))
810 cc_status
.flags
&= ~CC_KNOW_HI_R31
;
811 for (i
= size
-1; i
>= 0; i
--)
813 xoperands
[0] = plus_constant (op0
, i
);
814 xoperands
[1] = plus_constant (op1
, i
);
815 output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
823 /* Since we clobber untold things, nix the condition codes. */
826 /* This is the size of the transfer.
827 Either use the register which already contains the size,
828 or use a free register (used by no operands). */
829 output_size_for_block_move (operands
[2], operands
[4], alignrtx
);
832 /* Also emit code to decrement the size value by ALIGN. */
833 zoperands
[0] = operands
[0];
834 zoperands
[3] = plus_constant (operands
[0], align
);
835 output_load_address (zoperands
);
838 /* Generate number for unique label. */
840 xoperands
[3] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
842 /* Calculate the size of the chunks we will be trying to move first. */
845 if ((align
& 3) == 0)
847 else if ((align
& 1) == 0)
853 /* Copy the increment (negative) to a register for bla insn. */
855 xoperands
[4] = gen_rtx (CONST_INT
, VOIDmode
, - chunk_size
);
856 xoperands
[5] = operands
[5];
857 output_asm_insn ("adds %4,%?r0,%5", xoperands
);
859 /* Predecrement the loop counter. This happens again also in the `bla'
860 instruction which precedes the loop, but we need to have it done
861 two times before we enter the loop because of the bizarre semantics
862 of the bla instruction. */
864 output_asm_insn ("adds %5,%2,%2", xoperands
);
866 /* Check for the case where the original count was less than or equal to
867 zero. Avoid going through the loop at all if the original count was
868 indeed less than or equal to zero. Note that we treat the count as
869 if it were a signed 32-bit quantity here, rather than an unsigned one,
870 even though we really shouldn't. We have to do this because of the
871 semantics of the `ble' instruction, which assume that the count is
872 a signed 32-bit value. Anyway, in practice it won't matter because
873 nobody is going to try to do a memcpy() of more than half of the
874 entire address space (i.e. 2 gigabytes) anyway. */
876 output_asm_insn ("bc .Le%3", xoperands
);
878 /* Make available a register which is a temporary. */
880 xoperands
[6] = operands
[6];
882 /* Now the actual loop.
883 In xoperands, elements 1 and 0 are the input and output vectors.
884 Element 2 is the loop index. Element 5 is the increment. */
886 output_asm_insn ("subs %1,%5,%1", xoperands
);
887 output_asm_insn ("bla %5,%2,.Lm%3", xoperands
);
888 output_asm_insn ("adds %0,%2,%6", xoperands
);
889 output_asm_insn ("\n.Lm%3:", xoperands
); /* Label for bla above. */
890 output_asm_insn ("\n.Ls%3:", xoperands
); /* Loop start label. */
891 output_asm_insn ("adds %5,%6,%6", xoperands
);
893 /* NOTE: The code here which is supposed to handle the cases where the
894 sources and destinations are known to start on a 4 or 2 byte boundary
895 are currently broken. They fail to do anything about the overflow
896 bytes which might still need to be copied even after we have copied
897 some number of words or halfwords. Thus, for now we use the lowest
898 common denominator, i.e. the code which just copies some number of
899 totally unaligned individual bytes. (See the calculation of
904 output_asm_insn ("ld.l %2(%1),%?r31", xoperands
);
905 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
906 output_asm_insn ("st.l %?r31,8(%6)", xoperands
);
908 else if (chunk_size
== 2)
910 output_asm_insn ("ld.s %2(%1),%?r31", xoperands
);
911 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
912 output_asm_insn ("st.s %?r31,4(%6)", xoperands
);
914 else /* chunk_size == 1 */
916 output_asm_insn ("ld.b %2(%1),%?r31", xoperands
);
917 output_asm_insn ("bla %5,%2,.Ls%3", xoperands
);
918 output_asm_insn ("st.b %?r31,2(%6)", xoperands
);
920 output_asm_insn ("\n.Le%3:", xoperands
); /* Here if count <= 0. */
925 /* Output a delayed branch insn with the delay insn in its
926 branch slot. The delayed branch insn template is in TEMPLATE,
927 with operands OPERANDS. The insn in its delay slot is INSN.
929 As a special case, since we know that all memory transfers are via
930 ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
931 reference around the branch as
937 As another special case, we handle loading (SYMBOL_REF ...) and
938 other large constants around branches as well:
947 output_delayed_branch (template, operands
, insn
)
952 rtx src
= XVECEXP (PATTERN (insn
), 0, 1);
953 rtx dest
= XVECEXP (PATTERN (insn
), 0, 0);
955 /* See if we are doing some branch together with setting some register
956 to some 32-bit value which does (or may) have some of the high-order
957 16 bits set. If so, we need to set the register in two stages. One
958 stage must be done before the branch, and the other one can be done
959 in the delay slot. */
961 if ( (GET_CODE (src
) == CONST_INT
962 && ((unsigned) INTVAL (src
) & (unsigned) 0xffff0000) != (unsigned) 0)
963 || (GET_CODE (src
) == SYMBOL_REF
)
964 || (GET_CODE (src
) == LABEL_REF
)
965 || (GET_CODE (src
) == CONST
))
971 CC_STATUS_PARTIAL_INIT
;
972 /* Output the `orh' insn. */
973 output_asm_insn ("orh %H1,%?r0,%0", xoperands
);
975 /* Output the branch instruction next. */
976 output_asm_insn (template, operands
);
978 /* Now output the `or' insn. */
979 output_asm_insn ("or %L1,%0,%0", xoperands
);
981 else if ((GET_CODE (src
) == MEM
982 && CONSTANT_ADDRESS_P (XEXP (src
, 0)))
983 || (GET_CODE (dest
) == MEM
984 && CONSTANT_ADDRESS_P (XEXP (dest
, 0))))
987 char *split_template
;
991 /* Output the `orh' insn. */
992 if (GET_CODE (src
) == MEM
)
994 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
995 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
996 && cc_prev_status
.mdep
== XEXP (operands
[1], 0)))
999 output_asm_insn ("orh %h1,%?r0,%?r31", xoperands
);
1001 split_template
= load_opcode (GET_MODE (dest
),
1002 "%L1(%?r31),%0", dest
);
1006 if (! ((cc_prev_status
.flags
& CC_KNOW_HI_R31
)
1007 && (cc_prev_status
.flags
& CC_HI_R31_ADJ
)
1008 && cc_prev_status
.mdep
== XEXP (operands
[0], 0)))
1011 output_asm_insn ("orh %h0,%?r0,%?r31", xoperands
);
1013 split_template
= store_opcode (GET_MODE (dest
),
1014 "%r1,%L0(%?r31)", src
);
1017 /* Output the branch instruction next. */
1018 output_asm_insn (template, operands
);
1020 /* Now output the load or store.
1021 No need to do a CC_STATUS_INIT, because we are branching anyway. */
1022 output_asm_insn (split_template
, xoperands
);
1026 int insn_code_number
;
1027 rtx pat
= gen_rtx (SET
, VOIDmode
, dest
, src
);
1028 rtx delay_insn
= gen_rtx (INSN
, VOIDmode
, 0, 0, 0, pat
, -1, 0, 0);
1031 /* Output the branch instruction first. */
1032 output_asm_insn (template, operands
);
1034 /* Now recognize the insn which we put in its delay slot.
1035 We must do this after outputting the branch insn,
1036 since operands may just be a pointer to `recog_operand'. */
1037 INSN_CODE (delay_insn
) = insn_code_number
= recog (pat
, delay_insn
);
1038 if (insn_code_number
== -1)
1041 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1043 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1044 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1047 insn_extract (delay_insn
);
1048 if (! constrain_operands (insn_code_number
, 1))
1049 fatal_insn_not_found (delay_insn
);
1051 template = insn_template
[insn_code_number
];
1053 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1054 output_asm_insn (template, recog_operand
);
1060 /* Output a newly constructed insn DELAY_INSN. */
1062 output_delay_insn (delay_insn
)
1066 int insn_code_number
;
1069 /* Now recognize the insn which we put in its delay slot.
1070 We must do this after outputting the branch insn,
1071 since operands may just be a pointer to `recog_operand'. */
1072 insn_code_number
= recog_memoized (delay_insn
);
1073 if (insn_code_number
== -1)
1076 /* Extract the operands of this delay insn. */
1077 INSN_CODE (delay_insn
) = insn_code_number
;
1078 insn_extract (delay_insn
);
1080 /* It is possible that this insn has not been properly scanned by final
1081 yet. If this insn's operands don't appear in the peephole's
1082 actual operands, then they won't be fixed up by final, so we
1083 make sure they get fixed up here. -- This is a kludge. */
1084 for (i
= 0; i
< insn_n_operands
[insn_code_number
]; i
++)
1086 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
1087 recog_operand
[i
] = alter_subreg (recog_operand
[i
]);
1090 #ifdef REGISTER_CONSTRAINTS
1091 if (! constrain_operands (insn_code_number
))
1095 cc_prev_status
= cc_status
;
1097 /* Update `cc_status' for this instruction.
1098 The instruction's output routine may change it further.
1099 If the output routine for a jump insn needs to depend
1100 on the cc status, it should look at cc_prev_status. */
1102 NOTICE_UPDATE_CC (PATTERN (delay_insn
), delay_insn
);
1104 /* Now get the template for what this insn would
1105 have been, without the branch. */
1107 template = insn_template
[insn_code_number
];
1109 template = (*insn_outfun
[insn_code_number
]) (recog_operand
, delay_insn
);
1110 output_asm_insn (template, recog_operand
);
1114 /* Special routine to convert an SFmode value represented as a
1115 CONST_DOUBLE into its equivalent unsigned long bit pattern.
1116 We convert the value from a double precision floating-point
1117 value to single precision first, and thence to a bit-wise
1118 equivalent unsigned long value. This routine is used when
1119 generating an immediate move of an SFmode value directly
1120 into a general register because the svr4 assembler doesn't
1121 grok floating literals in instruction operand contexts. */
1124 sfmode_constant_to_ulong (x
)
1128 union { float f
; unsigned long i
; } u2
;
1130 if (GET_CODE (x
) != CONST_DOUBLE
|| GET_MODE (x
) != SFmode
)
1133 #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
1134 error IEEE emulation needed
1136 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1141 /* This function generates the assembly code for function entry.
1142 The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
1144 ASM_FILE is a stdio stream to output the code to.
1145 SIZE is an int: how many units of temporary storage to allocate.
1147 Refer to the array `regs_ever_live' to determine which registers
1148 to save; `regs_ever_live[I]' is nonzero if register number I
1149 is ever used in the function. This macro is responsible for
1150 knowing which registers should not be saved even if used.
1152 NOTE: `frame_lower_bytes' is the count of bytes which will lie
1153 between the new `fp' value and the new `sp' value after the
1154 prologue is done. `frame_upper_bytes' is the count of bytes
1155 that will lie between the new `fp' and the *old* `sp' value
1156 after the new `fp' is setup (in the prologue). The upper
1157 part of each frame always includes at least 2 words (8 bytes)
1158 to hold the saved frame pointer and the saved return address.
1160 The svr4 ABI for the i860 now requires that the values of the
1161 stack pointer and frame pointer registers be kept aligned to
1162 16-byte boundaries at all times. We obey that restriction here.
1164 The svr4 ABI for the i860 is entirely vague when it comes to specifying
1165 exactly where the "preserved" registers should be saved. The native
1166 svr4 C compiler I now have doesn't help to clarify the requirements
1167 very much because it is plainly out-of-date and non-ABI-compliant
1168 (in at least one important way, i.e. how it generates function
1171 The native svr4 C compiler saves the "preserved" registers (i.e.
1172 r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1173 offsets from the frame pointer).
1175 Previous versions of GCC also saved the "preserved" registers in the
1176 "negative" part of the frame, but they saved them using positive
1177 offsets from the (adjusted) stack pointer (after it had been adjusted
1178 to allocate space for the new frame). That's just plain wrong
1179 because if the current function calls alloca(), the stack pointer
1180 will get moved, and it will be impossible to restore the registers
1181 properly again after that.
1183 Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1184 by copying their values either into various "preserved" registers or
1185 into stack slots in the lower part of the current frame (as seemed
1186 appropriate, depending upon subsequent usage of these values).
1188 Here we want to save the preserved registers at some offset from the
1189 frame pointer register so as to avoid any possible problems arising
1190 from calls to alloca(). We can either save them at small positive
1191 offsets from the frame pointer, or at small negative offsets from
1192 the frame pointer. If we save them at small negative offsets from
1193 the frame pointer (i.e. in the lower part of the frame) then we
1194 must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1195 many bytes of space we plan to use in the lower part of the frame
1196 for this purpose. Since other parts of the compiler reference the
1197 value of STARTING_FRAME_OFFSET long before final() calls this function,
1198 we would have to go ahead and assume the worst-case storage requirements
1199 for saving all of the "preserved" registers (and use that number, i.e.
1200 `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1201 the lower part of the frame. That could potentially be very wasteful,
1202 and that could cause serious problems when compiling for embedded
1203 i860 targets with very tight limits on stack space. Thus, we choose
1204 here to save the preserved registers in the upper part of the
1205 frame, so that we can decide at the very last minute how much (or how
1206 little) space we must allocate for this purpose.
1208 To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
1209 registers must always be saved so that the saved values of registers
1210 with higher numbers are at higher addresses. We obey that restriction
1213 There are two somewhat different ways that you can generate prologues
1214 here... i.e. pedantically ABI-compliant, and the "other" way. The
1215 "other" way is more consistent with what is currently generated by the
1216 "native" svr4 C compiler for the i860. That's important if you want
1217 to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
1218 The SVR4 SDB for the i860 insists on having function prologues be
1221 To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1222 in the i860svr4.h file. (By default this is *not* defined).
1224 The differences between the ABI-compliant and non-ABI-compliant prologues
1225 are that (a) the ABI version seems to require the use of *signed*
1226 (rather than unsigned) adds and subtracts, and (b) the ordering of
1227 the various steps (e.g. saving preserved registers, saving the
1228 return address, setting up the new frame pointer value) is different.
1230 For strict ABI compliance, it seems to be the case that the very last
1231 thing that is supposed to happen in the prologue is getting the frame
1232 pointer set to its new value (but only after everything else has
1233 already been properly setup). We do that here, but only if the symbol
1234 I860_STRICT_ABI_PROLOGUES is defined.
1237 #ifndef STACK_ALIGNMENT
1238 #define STACK_ALIGNMENT 16
1241 extern char call_used_regs
[];
1242 extern int leaf_function_p ();
1244 char *current_function_original_name
;
1246 static int must_preserve_r1
;
1247 static unsigned must_preserve_bytes
;
1250 function_prologue (asm_file
, local_bytes
)
1251 register FILE *asm_file
;
1252 register unsigned local_bytes
;
1254 register unsigned frame_lower_bytes
;
1255 register unsigned frame_upper_bytes
;
1256 register unsigned total_fsize
;
1257 register unsigned preserved_reg_bytes
= 0;
1258 register unsigned i
;
1259 register unsigned preserved_so_far
= 0;
1261 must_preserve_r1
= (optimize
< 2 || ! leaf_function_p ());
1262 must_preserve_bytes
= 4 + (must_preserve_r1
? 4 : 0);
1264 /* Count registers that need preserving. Ignore r0. It never needs
1267 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
1269 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1270 preserved_reg_bytes
+= 4;
1273 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1275 frame_lower_bytes
= (local_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1277 /* The upper part of each frame will contain the saved fp,
1278 the saved r1, and stack slots for all of the other "preserved"
1279 registers that we find we will need to save & restore. */
1281 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
1283 /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1286 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1288 total_fsize
= frame_upper_bytes
+ frame_lower_bytes
;
1290 #ifndef I860_STRICT_ABI_PROLOGUES
1292 /* There are two kinds of function prologues.
1293 You use the "small" version if the total frame size is
1294 small enough so that it can fit into an immediate 16-bit
1295 value in one instruction. Otherwise, you use the "large"
1296 version of the function prologue. */
1298 if (total_fsize
> 0x7fff)
1300 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1301 but the native C compiler on svr4 uses `addu'. */
1303 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1304 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1306 /* Save the old frame pointer. */
1308 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1309 i860_reg_prefix
, i860_reg_prefix
);
1311 /* Setup the new frame pointer. The ABI sez to do this after
1312 preserving registers (using adds), but that's not what the
1313 native C compiler on svr4 does. */
1315 fprintf (asm_file
, "\taddu 0,%ssp,%sfp\n",
1316 i860_reg_prefix
, i860_reg_prefix
);
1318 /* Get the value of frame_lower_bytes into r31. */
1320 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1321 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1322 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1323 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1325 /* Now re-adjust the stack pointer using the value in r31.
1326 The ABI sez to do this with `subs' but SDB may prefer `subu'. */
1328 fprintf (asm_file
, "\tsubu %ssp,%sr31,%ssp\n",
1329 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1331 /* Preserve registers. The ABI sez to do this before setting
1332 up the new frame pointer, but that's not what the native
1333 C compiler on svr4 does. */
1335 for (i
= 1; i
< 32; i
++)
1336 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1337 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1338 i860_reg_prefix
, reg_names
[i
],
1339 must_preserve_bytes
+ (4 * preserved_so_far
++),
1342 for (i
= 32; i
< 64; i
++)
1343 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1344 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1345 i860_reg_prefix
, reg_names
[i
],
1346 must_preserve_bytes
+ (4 * preserved_so_far
++),
1349 /* Save the return address. */
1351 if (must_preserve_r1
)
1352 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1353 i860_reg_prefix
, i860_reg_prefix
);
1357 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1358 but the native C compiler on svr4 uses `addu'. */
1360 fprintf (asm_file
, "\taddu -%d,%ssp,%ssp\n",
1361 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1363 /* Save the old frame pointer. */
1365 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1366 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1368 /* Setup the new frame pointer. The ABI sez to do this after
1369 preserving registers and after saving the return address,
1370 (and its saz to do this using adds), but that's not what the
1371 native C compiler on svr4 does. */
1373 fprintf (asm_file
, "\taddu %d,%ssp,%sfp\n",
1374 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1376 /* Preserve registers. The ABI sez to do this before setting
1377 up the new frame pointer, but that's not what the native
1378 compiler on svr4 does. */
1380 for (i
= 1; i
< 32; i
++)
1381 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1382 fprintf (asm_file
, "\tst.l %s%s,%d(%sfp)\n",
1383 i860_reg_prefix
, reg_names
[i
],
1384 must_preserve_bytes
+ (4 * preserved_so_far
++),
1387 for (i
= 32; i
< 64; i
++)
1388 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1389 fprintf (asm_file
, "\tfst.l %s%s,%d(%sfp)\n",
1390 i860_reg_prefix
, reg_names
[i
],
1391 must_preserve_bytes
+ (4 * preserved_so_far
++),
1394 /* Save the return address. The ABI sez to do this earlier,
1395 and also via an offset from %sp, but the native C compiler
1396 on svr4 does it later (i.e. now) and uses an offset from
1399 if (must_preserve_r1
)
1400 fprintf (asm_file
, "\tst.l %sr1,4(%sfp)\n",
1401 i860_reg_prefix
, i860_reg_prefix
);
1404 #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1406 /* There are two kinds of function prologues.
1407 You use the "small" version if the total frame size is
1408 small enough so that it can fit into an immediate 16-bit
1409 value in one instruction. Otherwise, you use the "large"
1410 version of the function prologue. */
1412 if (total_fsize
> 0x7fff)
1414 /* Adjust the stack pointer (thereby allocating a new frame). */
1416 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1417 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1419 /* Save the caller's frame pointer. */
1421 fprintf (asm_file
, "\tst.l %sfp,0(%ssp)\n",
1422 i860_reg_prefix
, i860_reg_prefix
);
1424 /* Save return address. */
1426 if (must_preserve_r1
)
1427 fprintf (asm_file
, "\tst.l %sr1,4(%ssp)\n",
1428 i860_reg_prefix
, i860_reg_prefix
);
1430 /* Get the value of frame_lower_bytes into r31 for later use. */
1432 fprintf (asm_file
, "\torh %d,%sr0,%sr31\n",
1433 frame_lower_bytes
>> 16, i860_reg_prefix
, i860_reg_prefix
);
1434 fprintf (asm_file
, "\tor %d,%sr31,%sr31\n",
1435 frame_lower_bytes
& 0xffff, i860_reg_prefix
, i860_reg_prefix
);
1437 /* Now re-adjust the stack pointer using the value in r31. */
1439 fprintf (asm_file
, "\tsubs %ssp,%sr31,%ssp\n",
1440 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1442 /* Pre-compute value to be used as the new frame pointer. */
1444 fprintf (asm_file
, "\tadds %ssp,%sr31,%sr31\n",
1445 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1447 /* Preserve registers. */
1449 for (i
= 1; i
< 32; i
++)
1450 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1451 fprintf (asm_file
, "\tst.l %s%s,%d(%sr31)\n",
1452 i860_reg_prefix
, reg_names
[i
],
1453 must_preserve_bytes
+ (4 * preserved_so_far
++),
1456 for (i
= 32; i
< 64; i
++)
1457 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1458 fprintf (asm_file
, "\tfst.l %s%s,%d(%sr31)\n",
1459 i860_reg_prefix
, reg_names
[i
],
1460 must_preserve_bytes
+ (4 * preserved_so_far
++),
1463 /* Actually set the new value of the frame pointer. */
1465 fprintf (asm_file
, "\tmov %sr31,%sfp\n",
1466 i860_reg_prefix
, i860_reg_prefix
);
1470 /* Adjust the stack pointer. */
1472 fprintf (asm_file
, "\tadds -%d,%ssp,%ssp\n",
1473 total_fsize
, i860_reg_prefix
, i860_reg_prefix
);
1475 /* Save the caller's frame pointer. */
1477 fprintf (asm_file
, "\tst.l %sfp,%d(%ssp)\n",
1478 i860_reg_prefix
, frame_lower_bytes
, i860_reg_prefix
);
1480 /* Save the return address. */
1482 if (must_preserve_r1
)
1483 fprintf (asm_file
, "\tst.l %sr1,%d(%ssp)\n",
1484 i860_reg_prefix
, frame_lower_bytes
+ 4, i860_reg_prefix
);
1486 /* Preserve registers. */
1488 for (i
= 1; i
< 32; i
++)
1489 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1490 fprintf (asm_file
, "\tst.l %s%s,%d(%ssp)\n",
1491 i860_reg_prefix
, reg_names
[i
],
1492 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1495 for (i
= 32; i
< 64; i
++)
1496 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1497 fprintf (asm_file
, "\tfst.l %s%s,%d(%ssp)\n",
1498 i860_reg_prefix
, reg_names
[i
],
1499 frame_lower_bytes
+ must_preserve_bytes
+ (4 * preserved_so_far
++),
1502 /* Setup the new frame pointer. */
1504 fprintf (asm_file
, "\tadds %d,%ssp,%sfp\n",
1505 frame_lower_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1507 #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1509 #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
1510 ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file
);
1511 #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
1514 /* This function generates the assembly code for function exit.
1515 The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
1517 ASM_FILE is a stdio stream to output the code to.
1518 SIZE is an int: how many units of temporary storage to allocate.
1520 The function epilogue should not depend on the current stack pointer!
1521 It should use the frame pointer only. This is mandatory because
1522 of alloca; we also take advantage of it to omit stack adjustments
1525 Note that when we go to restore the preserved register values we must
1526 not try to address their slots by using offsets from the stack pointer.
1527 That's because the stack pointer may have been moved during the function
1528 execution due to a call to alloca(). Rather, we must restore all
1529 preserved registers via offsets from the frame pointer value.
1531 Note also that when the current frame is being "popped" (by adjusting
1532 the value of the stack pointer) on function exit, we must (for the
1533 sake of alloca) set the new value of the stack pointer based upon
1534 the current value of the frame pointer. We can't just add what we
1535 believe to be the (static) frame size to the stack pointer because
1536 if we did that, and alloca() had been called during this function,
1537 we would end up returning *without* having fully deallocated all of
1538 the space grabbed by alloca. If that happened, and a function
1539 containing one or more alloca() calls was called over and over again,
1540 then the stack would grow without limit!
1542 Finally note that the epilogues generated here are completely ABI
1543 compliant. They go out of their way to insure that the value in
1544 the frame pointer register is never less than the value in the stack
1545 pointer register. It's not clear why this relationship needs to be
1546 maintained at all times, but maintaining it only costs one extra
1547 instruction, so what the hell.
1550 /* This corresponds to a version 4 TDESC structure. Lower numbered
1551 versions successively omit the last word of the structure. We
1552 don't try to handle version 5 here. */
1554 typedef struct TDESC_flags
{
1557 int callable_block
:1;
1559 int fregs
:6; /* fp regs 2-7 */
1560 int iregs
:16; /* regs 0-15 */
1563 typedef struct TDESC
{
1565 int integer_reg_offset
; /* same as must_preserve_bytes */
1566 int floating_point_reg_offset
;
1567 unsigned int positive_frame_size
; /* same as frame_upper_bytes */
1568 unsigned int negative_frame_size
; /* same as frame_lower_bytes */
1572 function_epilogue (asm_file
, local_bytes
)
1573 register FILE *asm_file
;
1574 register unsigned local_bytes
;
1576 register unsigned frame_upper_bytes
;
1577 register unsigned frame_lower_bytes
;
1578 register unsigned preserved_reg_bytes
= 0;
1579 register unsigned i
;
1580 register unsigned restored_so_far
= 0;
1581 register unsigned int_restored
;
1582 register unsigned mask
;
1583 unsigned intflags
=0;
1584 register TDESC_flags
*flags
= (TDESC_flags
*) &intflags
;
1587 flags
->reg_packing
= 1;
1588 flags
->iregs
= 8; /* old fp always gets saved */
1590 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1592 frame_lower_bytes
= (local_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1594 /* Count the number of registers that were preserved in the prologue.
1595 Ignore r0. It is never preserved. */
1597 for (i
= 1; i
< FIRST_PSEUDO_REGISTER
; i
++)
1599 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1600 preserved_reg_bytes
+= 4;
1603 /* The upper part of each frame will contain only saved fp,
1604 the saved r1, and stack slots for all of the other "preserved"
1605 registers that we find we will need to save & restore. */
1607 frame_upper_bytes
= must_preserve_bytes
+ preserved_reg_bytes
;
1609 /* Round-up frame_upper_bytes so that t is a multiple of 16. */
1612 = (frame_upper_bytes
+ STACK_ALIGNMENT
- 1) & -STACK_ALIGNMENT
;
1614 /* Restore all of the "preserved" registers that need restoring. */
1618 for (i
= 1; i
< 32; i
++, mask
<<=1)
1619 if (regs_ever_live
[i
] && ! call_used_regs
[i
]) {
1620 fprintf (asm_file
, "\tld.l %d(%sfp),%s%s\n",
1621 must_preserve_bytes
+ (4 * restored_so_far
++),
1622 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
1623 if (i
> 3 && i
< 16)
1624 flags
->iregs
|= mask
;
1627 int_restored
= restored_so_far
;
1630 for (i
= 32; i
< 64; i
++) {
1631 if (regs_ever_live
[i
] && ! call_used_regs
[i
]) {
1632 fprintf (asm_file
, "\tfld.l %d(%sfp),%s%s\n",
1633 must_preserve_bytes
+ (4 * restored_so_far
++),
1634 i860_reg_prefix
, i860_reg_prefix
, reg_names
[i
]);
1635 if (i
> 33 & i
< 40)
1636 flags
->fregs
|= mask
;
1638 if (i
> 33 && i
< 40)
1642 /* Get the value we plan to use to restore the stack pointer into r31. */
1644 fprintf (asm_file
, "\tadds %d,%sfp,%sr31\n",
1645 frame_upper_bytes
, i860_reg_prefix
, i860_reg_prefix
);
1647 /* Restore the return address and the old frame pointer. */
1649 if (must_preserve_r1
) {
1650 fprintf (asm_file
, "\tld.l 4(%sfp),%sr1\n",
1651 i860_reg_prefix
, i860_reg_prefix
);
1655 fprintf (asm_file
, "\tld.l 0(%sfp),%sfp\n",
1656 i860_reg_prefix
, i860_reg_prefix
);
1658 /* Return and restore the old stack pointer value. */
1660 fprintf (asm_file
, "\tbri %sr1\n\tmov %sr31,%ssp\n",
1661 i860_reg_prefix
, i860_reg_prefix
, i860_reg_prefix
);
1663 #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
1664 if (! frame_lower_bytes
) {
1666 if (! frame_upper_bytes
) {
1668 if (restored_so_far
== int_restored
) /* No FP saves */
1672 assemble_name(asm_file
,current_function_original_name
);
1673 fputs(".TDESC:\n", asm_file
);
1674 fprintf(asm_file
, "%s 0x%0x\n", ASM_LONG
, intflags
);
1675 fprintf(asm_file
, "%s %d\n", ASM_LONG
,
1676 int_restored
? must_preserve_bytes
: 0);
1677 if (flags
->version
> 1) {
1678 fprintf(asm_file
, "%s %d\n", ASM_LONG
,
1679 (restored_so_far
== int_restored
) ? 0 : must_preserve_bytes
+
1680 (4 * int_restored
));
1681 if (flags
->version
> 2) {
1682 fprintf(asm_file
, "%s %d\n", ASM_LONG
, frame_upper_bytes
);
1683 if (flags
->version
> 3)
1684 fprintf(asm_file
, "%s %d\n", ASM_LONG
, frame_lower_bytes
);
1688 fprintf(asm_file
, "%s ", ASM_LONG
);
1689 assemble_name(asm_file
, current_function_original_name
);
1690 fprintf(asm_file
, "\n%s ", ASM_LONG
);
1691 assemble_name(asm_file
, current_function_original_name
);
1692 fputs(".TDESC\n", asm_file
);