1 ;; GCC machine description for Intel
80386.
2 ;; Copyright (C)
1988,
1994 Free Software Foundation, Inc.
3 ;; Mostly by William Schelter.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation,
675 Mass Ave, Cambridge, MA
02139, USA.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
27 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
28 ;; updates for most instructions.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; the special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a
32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a
16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an
8-bit integer opcode.
39 ;; 'S' Print the opcode suffix for a
32-bit float opcode.
40 ;; 'Q' Print the opcode suffix for a
64-bit float opcode.
42 ;; 'b' Print the QImode name of the register for the indicated operand.
43 ;; %b0 would print %al if operands[
0] is reg
0.
44 ;; 'w' Likewise, print the HImode name of the register.
45 ;; 'k' Likewise, print the SImode name of the register.
46 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
47 ;; 'y' Print "st(
0)" instead of "st" as a register.
48 ;; 'T' Print the opcode suffix for an
80-bit extended real XFmode float opcode.
51 ;;
0 This is a
`scas' operation. The mode of the UNSPEC is always SImode.
52 ;; operand 0 is the memory address to scan.
53 ;; operand 1 is a register containing the value to scan for. The mode
54 ;; of the scas opcode will be the same as the mode of this operand.
55 ;; operand 2 is the known alignment of operand 0.
56 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
57 ;; operand
0 is the argument for
`sin'.
58 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
59 ;; operand
0 is the argument for
`cos'.
61 ;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM".
62 ;; But restricting MEM here would mean that gcc could not remove a redundant
63 ;; test in cases like "incl MEM / je TARGET".
65 ;; We don't want to allow a constant operand for test insns because
66 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
67 ;; be folded while optimizing anyway.
69 ;; All test insns have expanders that save the operands away without
70 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
71 ;; after the tstM or cmp) will actually emit the tstM or cmpM.
73 (define_insn "tstsi_1"
75 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
79 if (REG_P (operands[0]))
80 return AS2 (test%L0,%0,%0);
82 operands[1] = const0_rtx;
83 return AS2 (cmp%L0,%1,%0);
86 (define_expand "tstsi"
88 (match_operand:SI 0 "nonimmediate_operand" ""))]
92 i386_compare_gen = gen_tstsi_1;
93 i386_compare_op0 = operands[0];
97 (define_insn "tsthi_1"
99 (match_operand:HI 0 "nonimmediate_operand" "rm"))]
103 if (REG_P (operands[0]))
104 return AS2 (test%W0,%0,%0);
106 operands[1] = const0_rtx;
107 return AS2 (cmp%W0,%1,%0);
110 (define_expand "tsthi"
112 (match_operand:HI 0 "nonimmediate_operand" ""))]
116 i386_compare_gen = gen_tsthi_1;
117 i386_compare_op0 = operands[0];
121 (define_insn "tstqi_1"
123 (match_operand:QI 0 "nonimmediate_operand" "qm"))]
127 if (REG_P (operands[0]))
128 return AS2 (test%B0,%0,%0);
130 operands[1] = const0_rtx;
131 return AS2 (cmp%B0,%1,%0);
134 (define_expand "tstqi"
136 (match_operand:QI 0 "nonimmediate_operand" ""))]
140 i386_compare_gen = gen_tstqi_1;
141 i386_compare_op0 = operands[0];
145 (define_insn "tstsf_cc"
147 (match_operand:SF 0 "register_operand" "f"))
148 (clobber (match_scratch:HI 1 "=a"))]
149 "TARGET_80387 && ! TARGET_IEEE_FP"
152 if (! STACK_TOP_P (operands[0]))
155 output_asm_insn (\"ftst\", operands);
157 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
158 output_asm_insn (AS1 (fstp,%y0), operands);
160 return (char *) output_fp_cc0_set (insn);
163 ;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode
164 ;; isn't IEEE compliant.
166 (define_expand "tstsf"
167 [(parallel [(set (cc0)
168 (match_operand:SF
0 "register_operand" ""))
169 (clobber (match_scratch:HI
1 ""))])]
170 "TARGET_80387 && ! TARGET_IEEE_FP"
173 i386_compare_gen = gen_tstsf_cc;
174 i386_compare_op0 = operands[
0];
178 (define_insn "tstdf_cc"
180 (match_operand:DF
0 "register_operand" "f"))
181 (clobber (match_scratch:HI
1 "=a"))]
182 "TARGET_80387 && ! TARGET_IEEE_FP"
185 if (! STACK_TOP_P (operands[
0]))
188 output_asm_insn (
\"ftst
\", operands);
190 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
191 output_asm_insn (AS1 (fstp,%y0), operands);
193 return (char *) output_fp_cc0_set (insn);
196 ;; Don't generate tstdf if generating IEEE code, since the
`ftst' opcode
197 ;; isn't IEEE compliant.
199 (define_expand "tstdf"
200 [(parallel [(set (cc0)
201 (match_operand:DF 0 "register_operand" ""))
202 (clobber (match_scratch:HI 1 ""))])]
203 "TARGET_80387 && ! TARGET_IEEE_FP"
206 i386_compare_gen = gen_tstdf_cc;
207 i386_compare_op0 = operands[0];
211 (define_insn "tstxf_cc"
213 (match_operand:XF 0 "register_operand" "f"))
214 (clobber (match_scratch:HI 1 "=a"))]
215 "TARGET_80387 && ! TARGET_IEEE_FP"
218 if (! STACK_TOP_P (operands[0]))
221 output_asm_insn (\"ftst\", operands);
223 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
224 output_asm_insn (AS1 (fstp,%y0), operands);
226 return (char *) output_fp_cc0_set (insn);
229 ;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode
230 ;; isn't IEEE compliant.
232 (define_expand "tstxf"
233 [(parallel [(set (cc0)
234 (match_operand:XF
0 "register_operand" ""))
235 (clobber (match_scratch:HI
1 ""))])]
236 "TARGET_80387 && ! TARGET_IEEE_FP"
239 i386_compare_gen = gen_tstxf_cc;
240 i386_compare_op0 = operands[
0];
244 ;;- compare instructions. See comments above tstM patterns about
245 ;; expansion of these insns.
247 (define_insn "cmpsi_1"
249 (compare (match_operand:SI
0 "nonimmediate_operand" "mr,r")
250 (match_operand:SI
1 "general_operand" "ri,mr")))]
251 "GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != MEM"
254 if (CONSTANT_P (operands[
0]) || GET_CODE (operands[
1]) == MEM)
256 cc_status.flags |= CC_REVERSED;
257 return AS2 (cmp%L0,%
0,%
1);
259 return AS2 (cmp%L0,%
1,%
0);
262 (define_expand "cmpsi"
264 (compare (match_operand:SI
0 "nonimmediate_operand" "")
265 (match_operand:SI
1 "general_operand" "")))]
269 if (GET_CODE (operands[
0]) == MEM && GET_CODE (operands[
1]) == MEM)
270 operands[
0] = force_reg (SImode, operands[
0]);
272 i386_compare_gen = gen_cmpsi_1;
273 i386_compare_op0 = operands[
0];
274 i386_compare_op1 = operands[
1];
278 (define_insn "cmphi_1"
280 (compare (match_operand:HI
0 "nonimmediate_operand" "mr,r")
281 (match_operand:HI
1 "general_operand" "ri,mr")))]
282 "GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != MEM"
285 if (CONSTANT_P (operands[
0]) || GET_CODE (operands[
1]) == MEM)
287 cc_status.flags |= CC_REVERSED;
288 return AS2 (cmp%W0,%
0,%
1);
290 return AS2 (cmp%W0,%
1,%
0);
293 (define_expand "cmphi"
295 (compare (match_operand:HI
0 "nonimmediate_operand" "")
296 (match_operand:HI
1 "general_operand" "")))]
300 if (GET_CODE (operands[
0]) == MEM && GET_CODE (operands[
1]) == MEM)
301 operands[
0] = force_reg (HImode, operands[
0]);
303 i386_compare_gen = gen_cmphi_1;
304 i386_compare_op0 = operands[
0];
305 i386_compare_op1 = operands[
1];
309 (define_insn "cmpqi_1"
311 (compare (match_operand:QI
0 "nonimmediate_operand" "q,mq")
312 (match_operand:QI
1 "general_operand" "qm,nq")))]
313 "GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != MEM"
316 if (CONSTANT_P (operands[
0]) || GET_CODE (operands[
1]) == MEM)
318 cc_status.flags |= CC_REVERSED;
319 return AS2 (cmp%B0,%
0,%
1);
321 return AS2 (cmp%B0,%
1,%
0);
324 (define_expand "cmpqi"
326 (compare (match_operand:QI
0 "nonimmediate_operand" "")
327 (match_operand:QI
1 "general_operand" "")))]
331 if (GET_CODE (operands[
0]) == MEM && GET_CODE (operands[
1]) == MEM)
332 operands[
0] = force_reg (QImode, operands[
0]);
334 i386_compare_gen = gen_cmpqi_1;
335 i386_compare_op0 = operands[
0];
336 i386_compare_op1 = operands[
1];
340 ;; These implement float point compares. For each of DFmode and
341 ;; SFmode, there is the normal insn, and an insn where the second operand
342 ;; is converted to the desired mode.
346 (match_operator
2 "VOIDmode_compare_op"
347 [(match_operand:XF
0 "nonimmediate_operand" "f")
348 (match_operand:XF
1 "nonimmediate_operand" "f")]))
349 (clobber (match_scratch:HI
3 "=a"))]
351 && (GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != MEM)"
352 "* return (char *) output_float_compare (insn, operands);")
356 (match_operator
2 "VOIDmode_compare_op"
357 [(match_operand:XF
0 "register_operand" "f")
359 (match_operand:SI
1 "nonimmediate_operand" "rm"))]))
360 (clobber (match_scratch:HI
3 "=a"))]
362 "* return (char *) output_float_compare (insn, operands);")
366 (match_operator
2 "VOIDmode_compare_op"
368 (match_operand:SI
0 "nonimmediate_operand" "rm"))
369 (match_operand:XF
1 "register_operand" "f")]))
370 (clobber (match_scratch:HI
3 "=a"))]
372 "* return (char *) output_float_compare (insn, operands);")
376 (match_operator
2 "VOIDmode_compare_op"
377 [(match_operand:XF
0 "register_operand" "f")
379 (match_operand:DF
1 "nonimmediate_operand" "fm"))]))
380 (clobber (match_scratch:HI
3 "=a"))]
382 "* return (char *) output_float_compare (insn, operands);")
386 (match_operator
2 "VOIDmode_compare_op"
387 [(match_operand:XF
0 "register_operand" "f")
389 (match_operand:SF
1 "nonimmediate_operand" "fm"))]))
390 (clobber (match_scratch:HI
3 "=a"))]
392 "* return (char *) output_float_compare (insn, operands);")
396 (compare:CCFPEQ (match_operand:XF
0 "register_operand" "f")
397 (match_operand:XF
1 "register_operand" "f")))
398 (clobber (match_scratch:HI
2 "=a"))]
400 "* return (char *) output_float_compare (insn, operands);")
404 (match_operator
2 "VOIDmode_compare_op"
405 [(match_operand:DF
0 "nonimmediate_operand" "f,fm")
406 (match_operand:DF
1 "nonimmediate_operand" "fm,f")]))
407 (clobber (match_scratch:HI
3 "=a,a"))]
409 && (GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != MEM)"
410 "* return (char *) output_float_compare (insn, operands);")
414 (match_operator
2 "VOIDmode_compare_op"
415 [(match_operand:DF
0 "register_operand" "f")
417 (match_operand:SI
1 "nonimmediate_operand" "rm"))]))
418 (clobber (match_scratch:HI
3 "=a"))]
420 "* return (char *) output_float_compare (insn, operands);")
424 (match_operator
2 "VOIDmode_compare_op"
426 (match_operand:SI
0 "nonimmediate_operand" "rm"))
427 (match_operand:DF
1 "register_operand" "f")]))
428 (clobber (match_scratch:HI
3 "=a"))]
430 "* return (char *) output_float_compare (insn, operands);")
434 (match_operator
2 "VOIDmode_compare_op"
435 [(match_operand:DF
0 "register_operand" "f")
437 (match_operand:SF
1 "nonimmediate_operand" "fm"))]))
438 (clobber (match_scratch:HI
3 "=a"))]
440 "* return (char *) output_float_compare (insn, operands);")
444 (match_operator
2 "VOIDmode_compare_op"
446 (match_operand:SF
0 "nonimmediate_operand" "fm"))
447 (match_operand:DF
1 "register_operand" "f")]))
448 (clobber (match_scratch:HI
3 "=a"))]
450 "* return (char *) output_float_compare (insn, operands);")
454 (compare:CCFPEQ (match_operand:DF
0 "register_operand" "f")
455 (match_operand:DF
1 "register_operand" "f")))
456 (clobber (match_scratch:HI
2 "=a"))]
458 "* return (char *) output_float_compare (insn, operands);")
460 ;; These two insns will never be generated by combine due to the mode of
464 ; (compare:CCFPEQ (match_operand:DF
0 "register_operand" "f")
466 ; (match_operand:SF
1 "register_operand" "f"))))
467 ; (clobber (match_scratch:HI
2 "=a"))]
469 ; "* return (char *) output_float_compare (insn, operands);")
473 ; (compare:CCFPEQ (float_extend:DF
474 ; (match_operand:SF
0 "register_operand" "f"))
475 ; (match_operand:DF
1 "register_operand" "f")))
476 ; (clobber (match_scratch:HI
2 "=a"))]
478 ; "* return (char *) output_float_compare (insn, operands);")
480 (define_insn "cmpsf_cc_1"
482 (match_operator
2 "VOIDmode_compare_op"
483 [(match_operand:SF
0 "nonimmediate_operand" "f,fm")
484 (match_operand:SF
1 "nonimmediate_operand" "fm,f")]))
485 (clobber (match_scratch:HI
3 "=a,a"))]
487 && (GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != MEM)"
488 "* return (char *) output_float_compare (insn, operands);")
492 (match_operator
2 "VOIDmode_compare_op"
493 [(match_operand:SF
0 "register_operand" "f")
495 (match_operand:SI
1 "nonimmediate_operand" "rm"))]))
496 (clobber (match_scratch:HI
3 "=a"))]
498 "* return (char *) output_float_compare (insn, operands);")
502 (match_operator
2 "VOIDmode_compare_op"
504 (match_operand:SI
0 "nonimmediate_operand" "rm"))
505 (match_operand:SF
1 "register_operand" "f")]))
506 (clobber (match_scratch:HI
3 "=a"))]
508 "* return (char *) output_float_compare (insn, operands);")
512 (compare:CCFPEQ (match_operand:SF
0 "register_operand" "f")
513 (match_operand:SF
1 "register_operand" "f")))
514 (clobber (match_scratch:HI
2 "=a"))]
516 "* return (char *) output_float_compare (insn, operands);")
518 (define_expand "cmpxf"
520 (compare (match_operand:XF
0 "register_operand" "")
521 (match_operand:XF
1 "nonimmediate_operand" "")))]
525 i386_compare_gen = gen_cmpxf_cc;
526 i386_compare_gen_eq = gen_cmpxf_ccfpeq;
527 i386_compare_op0 = operands[
0];
528 i386_compare_op1 = operands[
1];
532 (define_expand "cmpdf"
534 (compare (match_operand:DF
0 "register_operand" "")
535 (match_operand:DF
1 "nonimmediate_operand" "")))]
539 i386_compare_gen = gen_cmpdf_cc;
540 i386_compare_gen_eq = gen_cmpdf_ccfpeq;
541 i386_compare_op0 = operands[
0];
542 i386_compare_op1 = operands[
1];
546 (define_expand "cmpsf"
548 (compare (match_operand:SF
0 "register_operand" "")
549 (match_operand:SF
1 "nonimmediate_operand" "")))]
553 i386_compare_gen = gen_cmpsf_cc;
554 i386_compare_gen_eq = gen_cmpsf_ccfpeq;
555 i386_compare_op0 = operands[
0];
556 i386_compare_op1 = operands[
1];
560 (define_expand "cmpxf_cc"
561 [(parallel [(set (cc0)
562 (compare (match_operand:XF
0 "register_operand" "")
563 (match_operand:XF
1 "register_operand" "")))
564 (clobber (match_scratch:HI
2 ""))])]
568 (define_expand "cmpxf_ccfpeq"
569 [(parallel [(set (cc0)
570 (compare:CCFPEQ (match_operand:XF
0 "register_operand" "")
571 (match_operand:XF
1 "register_operand" "")))
572 (clobber (match_scratch:HI
2 ""))])]
576 if (! register_operand (operands[
1], XFmode))
577 operands[
1] = copy_to_mode_reg (XFmode, operands[
1]);
580 (define_expand "cmpdf_cc"
581 [(parallel [(set (cc0)
582 (compare (match_operand:DF
0 "register_operand" "")
583 (match_operand:DF
1 "register_operand" "")))
584 (clobber (match_scratch:HI
2 ""))])]
588 (define_expand "cmpdf_ccfpeq"
589 [(parallel [(set (cc0)
590 (compare:CCFPEQ (match_operand:DF
0 "register_operand" "")
591 (match_operand:DF
1 "register_operand" "")))
592 (clobber (match_scratch:HI
2 ""))])]
596 if (! register_operand (operands[
1], DFmode))
597 operands[
1] = copy_to_mode_reg (DFmode, operands[
1]);
600 (define_expand "cmpsf_cc"
601 [(parallel [(set (cc0)
602 (compare (match_operand:SF
0 "register_operand" "")
603 (match_operand:SF
1 "register_operand" "")))
604 (clobber (match_scratch:HI
2 ""))])]
608 (define_expand "cmpsf_ccfpeq"
609 [(parallel [(set (cc0)
610 (compare:CCFPEQ (match_operand:SF
0 "register_operand" "")
611 (match_operand:SF
1 "register_operand" "")))
612 (clobber (match_scratch:HI
2 ""))])]
616 if (! register_operand (operands[
1], SFmode))
617 operands[
1] = copy_to_mode_reg (SFmode, operands[
1]);
624 (and:SI (match_operand:SI
0 "general_operand" "%ro")
625 (match_operand:SI
1 "general_operand" "ri")))]
629 /* For small integers, we may actually use testb. */
630 if (GET_CODE (operands[
1]) == CONST_INT
631 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0]))
632 && (! REG_P (operands[
0]) || QI_REG_P (operands[
0])))
634 /* We may set the sign bit spuriously. */
636 if ((INTVAL (operands[
1]) & ~
0xff) ==
0)
638 cc_status.flags |= CC_NOT_NEGATIVE;
639 return AS2 (test%B0,%
1,%b0);
642 if ((INTVAL (operands[
1]) & ~
0xff00) ==
0)
644 cc_status.flags |= CC_NOT_NEGATIVE;
645 operands[
1] = GEN_INT (INTVAL (operands[
1]) >>
8);
647 if (QI_REG_P (operands[
0]))
648 return AS2 (test%B0,%
1,%h0);
651 operands[
0] = adj_offsettable_operand (operands[
0],
1);
652 return AS2 (test%B0,%
1,%b0);
656 if (GET_CODE (operands[
0]) == MEM
657 && (INTVAL (operands[
1]) & ~
0xff0000) ==
0)
659 cc_status.flags |= CC_NOT_NEGATIVE;
660 operands[
1] = GEN_INT (INTVAL (operands[
1]) >>
16);
661 operands[
0] = adj_offsettable_operand (operands[
0],
2);
662 return AS2 (test%B0,%
1,%b0);
665 if (GET_CODE (operands[
0]) == MEM
666 && (INTVAL (operands[
1]) & ~
0xff000000) ==
0)
668 operands[
1] = GEN_INT ((INTVAL (operands[
1]) >>
24) &
0xff);
669 operands[
0] = adj_offsettable_operand (operands[
0],
3);
670 return AS2 (test%B0,%
1,%b0);
674 if (CONSTANT_P (operands[
1]) || GET_CODE (operands[
0]) == MEM)
675 return AS2 (test%L0,%
1,%
0);
677 return AS2 (test%L1,%
0,%
1);
682 (and:HI (match_operand:HI
0 "general_operand" "%ro")
683 (match_operand:HI
1 "general_operand" "ri")))]
687 if (GET_CODE (operands[
1]) == CONST_INT
688 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0]))
689 && (! REG_P (operands[
0]) || QI_REG_P (operands[
0])))
691 if ((INTVAL (operands[
1]) &
0xff00) ==
0)
693 /* ??? This might not be necessary. */
694 if (INTVAL (operands[
1]) &
0xffff0000)
695 operands[
1] = GEN_INT (INTVAL (operands[
1]) &
0xff);
697 /* We may set the sign bit spuriously. */
698 cc_status.flags |= CC_NOT_NEGATIVE;
699 return AS2 (test%B0,%
1,%b0);
702 if ((INTVAL (operands[
1]) &
0xff) ==
0)
704 operands[
1] = GEN_INT ((INTVAL (operands[
1]) >>
8) &
0xff);
706 if (QI_REG_P (operands[
0]))
707 return AS2 (test%B0,%
1,%h0);
710 operands[
0] = adj_offsettable_operand (operands[
0],
1);
711 return AS2 (test%B0,%
1,%b0);
716 if (CONSTANT_P (operands[
1]) || GET_CODE (operands[
0]) == MEM)
717 return AS2 (test%W0,%
1,%
0);
719 return AS2 (test%W1,%
0,%
1);
724 (and:QI (match_operand:QI
0 "general_operand" "%qm")
725 (match_operand:QI
1 "general_operand" "qi")))]
729 if (CONSTANT_P (operands[
1]) || GET_CODE (operands[
0]) == MEM)
730 return AS2 (test%B0,%
1,%
0);
732 return AS2 (test%B1,%
0,%
1);
735 ;; move instructions.
736 ;; There is one for each machine mode,
737 ;; and each is preceded by a corresponding push-insn pattern
738 ;; (since pushes are not general_operands on the
386).
741 [(set (match_operand:SI
0 "push_operand" "=<")
742 (match_operand:SI
1 "general_operand" "g"))]
746 ;; On a
486, it is faster to move MEM to a REG and then push, rather than
747 ;; push MEM directly.
750 [(set (match_operand:SI
0 "push_operand" "=<")
751 (match_operand:SI
1 "general_operand" "ri"))]
755 ;; General case of fullword move.
757 ;; If generating PIC code and operands[
1] is a symbolic CONST, emit a
758 ;; move to get the address of the symbolic object from the GOT.
760 (define_expand "movsi"
761 [(set (match_operand:SI
0 "general_operand" "")
762 (match_operand:SI
1 "general_operand" ""))]
768 if (flag_pic && SYMBOLIC_CONST (operands[
1]))
769 emit_pic_move (operands, SImode);
772 ;; On i486, incl reg is faster than movl $
1,reg.
775 [(set (match_operand:SI
0 "general_operand" "=g,r")
776 (match_operand:SI
1 "general_operand" "ri,m"))]
781 if (operands[
1] == const0_rtx && REG_P (operands[
0]))
782 return AS2 (xor%L0,%
0,%
0);
784 if (operands[
1] == const1_rtx
785 && (link = find_reg_note (insn, REG_WAS_0,
0))
786 /* Make sure the insn that stored the
0 is still present. */
787 && ! INSN_DELETED_P (XEXP (link,
0))
788 && GET_CODE (XEXP (link,
0)) != NOTE
789 /* Make sure cross jumping didn't happen here. */
790 && no_labels_between_p (XEXP (link,
0), insn)
791 /* Make sure the reg hasn't been clobbered. */
792 && ! reg_set_between_p (operands[
0], XEXP (link,
0), insn))
793 /* Fastest way to change a
0 to a
1. */
794 return AS1 (inc%L0,%
0);
796 return AS2 (mov%L0,%
1,%
0);
800 [(set (match_operand:HI
0 "push_operand" "=<")
801 (match_operand:HI
1 "general_operand" "g"))]
805 ;; On i486, an incl and movl are both faster than incw and movw.
808 [(set (match_operand:HI
0 "general_operand" "=g,r")
809 (match_operand:HI
1 "general_operand" "ri,m"))]
814 if (REG_P (operands[
0]) && operands[
1] == const0_rtx)
815 return AS2 (xor%L0,%k0,%k0);
817 if (REG_P (operands[
0]) && operands[
1] == const1_rtx
818 && (link = find_reg_note (insn, REG_WAS_0,
0))
819 /* Make sure the insn that stored the
0 is still present. */
820 && ! INSN_DELETED_P (XEXP (link,
0))
821 && GET_CODE (XEXP (link,
0)) != NOTE
822 /* Make sure cross jumping didn't happen here. */
823 && no_labels_between_p (XEXP (link,
0), insn)
824 /* Make sure the reg hasn't been clobbered. */
825 && ! reg_set_between_p (operands[
0], XEXP (link,
0), insn))
826 /* Fastest way to change a
0 to a
1. */
827 return AS1 (inc%L0,%k0);
829 if (REG_P (operands[
0]))
831 if (REG_P (operands[
1]))
832 return AS2 (mov%L0,%k1,%k0);
833 else if (CONSTANT_P (operands[
1]))
834 return AS2 (mov%L0,%
1,%k0);
837 return AS2 (mov%W0,%
1,%
0);
840 (define_insn "movstricthi"
841 [(set (strict_low_part (match_operand:HI
0 "general_operand" "+g,r"))
842 (match_operand:HI
1 "general_operand" "ri,m"))]
847 if (operands[
1] == const0_rtx && REG_P (operands[
0]))
848 return AS2 (xor%W0,%
0,%
0);
850 if (operands[
1] == const1_rtx
851 && (link = find_reg_note (insn, REG_WAS_0,
0))
852 /* Make sure the insn that stored the
0 is still present. */
853 && ! INSN_DELETED_P (XEXP (link,
0))
854 && GET_CODE (XEXP (link,
0)) != NOTE
855 /* Make sure cross jumping didn't happen here. */
856 && no_labels_between_p (XEXP (link,
0), insn)
857 /* Make sure the reg hasn't been clobbered. */
858 && ! reg_set_between_p (operands[
0], XEXP (link,
0), insn))
859 /* Fastest way to change a
0 to a
1. */
860 return AS1 (inc%W0,%
0);
862 return AS2 (mov%W0,%
1,%
0);
865 ;; emit_push_insn when it calls move_by_pieces
866 ;; requires an insn to "push a byte".
867 ;; But actually we use pushw, which has the effect of rounding
868 ;; the amount pushed up to a halfword.
870 [(set (match_operand:QI
0 "push_operand" "=<")
871 (match_operand:QI
1 "general_operand" "q"))]
875 operands[
1] = gen_rtx (REG, HImode, REGNO (operands[
1]));
876 return AS1 (push%W0,%
1);
879 ;; On i486, incb reg is faster than movb $
1,reg.
881 ;; ??? Do a recognizer for zero_extract that looks just like this, but reads
882 ;; or writes %ah, %bh, %ch, %dh.
885 [(set (match_operand:QI
0 "general_operand" "=q,*r,qm")
886 (match_operand:QI
1 "general_operand" "*g,q,qn"))]
891 if (operands[
1] == const0_rtx && REG_P (operands[
0]))
892 return AS2 (xor%B0,%
0,%
0);
894 if (operands[
1] == const1_rtx
895 && (link = find_reg_note (insn, REG_WAS_0,
0))
896 /* Make sure the insn that stored the
0 is still present. */
897 && ! INSN_DELETED_P (XEXP (link,
0))
898 && GET_CODE (XEXP (link,
0)) != NOTE
899 /* Make sure cross jumping didn't happen here. */
900 && no_labels_between_p (XEXP (link,
0), insn)
901 /* Make sure the reg hasn't been clobbered. */
902 && ! reg_set_between_p (operands[
0], XEXP (link,
0), insn))
903 /* Fastest way to change a
0 to a
1. */
904 return AS1 (inc%B0,%
0);
906 /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */
907 if (NON_QI_REG_P (operands[
0]) || NON_QI_REG_P (operands[
1]))
908 return (AS2 (mov%L0,%k1,%k0));
910 return (AS2 (mov%B0,%
1,%
0));
913 ;; If it becomes necessary to support movstrictqi into %esi or %edi,
914 ;; use the insn sequence:
916 ;; shrdl $
8,srcreg,dstreg
919 ;; If operands[
1] is a constant, then an andl/orl sequence would be
922 (define_insn "movstrictqi"
923 [(set (strict_low_part (match_operand:QI
0 "general_operand" "+qm,q"))
924 (match_operand:QI
1 "general_operand" "*qn,m"))]
929 if (operands[
1] == const0_rtx && REG_P (operands[
0]))
930 return AS2 (xor%B0,%
0,%
0);
932 if (operands[
1] == const1_rtx
933 && (link = find_reg_note (insn, REG_WAS_0,
0))
934 /* Make sure the insn that stored the
0 is still present. */
935 && ! INSN_DELETED_P (XEXP (link,
0))
936 && GET_CODE (XEXP (link,
0)) != NOTE
937 /* Make sure cross jumping didn't happen here. */
938 && no_labels_between_p (XEXP (link,
0), insn)
939 /* Make sure the reg hasn't been clobbered. */
940 && ! reg_set_between_p (operands[
0], XEXP (link,
0), insn))
941 /* Fastest way to change a
0 to a
1. */
942 return AS1 (inc%B0,%
0);
944 /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */
945 if (NON_QI_REG_P (operands[
0]) || NON_QI_REG_P (operands[
1]))
948 return (AS2 (mov%L0,%k1,%k0));
951 return AS2 (mov%B0,%
1,%
0);
955 [(set (match_operand:SF
0 "push_operand" "=<,<")
956 (match_operand:SF
1 "general_operand" "gF,f"))]
960 if (STACK_REG_P (operands[
1]))
964 if (! STACK_TOP_P (operands[
1]))
967 xops[
0] = AT_SP (SFmode);
968 xops[
1] = GEN_INT (
4);
969 xops[
2] = stack_pointer_rtx;
971 output_asm_insn (AS2 (sub%L2,%
1,%
2), xops);
973 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
974 output_asm_insn (AS1 (fstp%S0,%
0), xops);
976 output_asm_insn (AS1 (fst%S0,%
0), xops);
979 return AS1 (push%L1,%
1);
982 ;; Allow MEM-MEM moves before reload. The reload class for such a
983 ;; move will be ALL_REGS. PREFERRED_RELOAD_CLASS will narrow this to
984 ;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS.
987 [(set (match_operand:SF
0 "general_operand" "=*rfm,*rf,f,!*rm")
988 (match_operand:SF
1 "general_operand" "*rf,*rfm,fG,fF"))]
992 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) !=
0;
994 /* First handle a
`pop' insn or a `fld %st(
0)' */
996 if (STACK_TOP_P (operands[
0]) && STACK_TOP_P (operands[
1]))
999 return AS1 (fstp,%y0);
1001 return AS1 (fld,%y0);
1004 /* Handle a transfer between the
387 and a
386 register */
1006 if (STACK_TOP_P (operands[
0]) && NON_STACK_REG_P (operands[
1]))
1008 output_op_from_reg (operands[
1], AS1 (fld%z0,%y1));
1012 if (STACK_TOP_P (operands[
1]) && NON_STACK_REG_P (operands[
0]))
1014 output_to_reg (operands[
0], stack_top_dies);
1018 /* Handle other kinds of writes from the
387 */
1020 if (STACK_TOP_P (operands[
1]))
1023 return AS1 (fstp%z0,%y0);
1025 return AS1 (fst%z0,%y0);
1028 /* Handle other kinds of reads to the
387 */
1030 if (STACK_TOP_P (operands[
0]) && GET_CODE (operands[
1]) == CONST_DOUBLE)
1031 return (char *) output_move_const_single (operands);
1033 if (STACK_TOP_P (operands[
0]))
1034 return AS1 (fld%z1,%y1);
1036 /* Handle all SFmode moves not involving the
387 */
1038 return (char *) singlemove_string (operands);
1041 ;;should change to handle the memory operands[
1] without doing df push..
1043 [(set (match_operand:DF
0 "push_operand" "=<,<")
1044 (match_operand:DF
1 "general_operand" "gF,f"))]
1048 if (STACK_REG_P (operands[
1]))
1052 xops[
0] = AT_SP (SFmode);
1053 xops[
1] = GEN_INT (
8);
1054 xops[
2] = stack_pointer_rtx;
1056 output_asm_insn (AS2 (sub%L2,%
1,%
2), xops);
1058 if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
1059 output_asm_insn (AS1 (fstp%Q0,%
0), xops);
1061 output_asm_insn (AS1 (fst%Q0,%
0), xops);
1066 return (char *) output_move_double (operands);
1069 (define_insn "swapdf"
1070 [(set (match_operand:DF
0 "register_operand" "f")
1071 (match_operand:DF
1 "register_operand" "f"))
1077 if (STACK_TOP_P (operands[
0]))
1078 return AS1 (fxch,%
1);
1080 return AS1 (fxch,%
0);
1083 ;; Allow MEM-MEM moves before reload. The reload class for such a
1084 ;; move will be ALL_REGS. PREFERRED_RELOAD_CLASS will narrow this to
1085 ;; GENERAL_REGS. For the purposes of regclass, prefer FLOAT_REGS.
1087 (define_insn "movdf"
1088 [(set (match_operand:DF
0 "general_operand" "=*rfm,*rf,f,!*rm")
1089 (match_operand:DF
1 "general_operand" "*rf,*rfm,fG,fF"))]
1093 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) !=
0;
1095 /* First handle a
`pop' insn or a `fld %st(
0)' */
1097 if (STACK_TOP_P (operands[
0]) && STACK_TOP_P (operands[
1]))
1100 return AS1 (fstp,%y0);
1102 return AS1 (fld,%y0);
1105 /* Handle a transfer between the
387 and a
386 register */
1107 if (STACK_TOP_P (operands[
0]) && NON_STACK_REG_P (operands[
1]))
1109 output_op_from_reg (operands[
1], AS1 (fld%z0,%y1));
1113 if (STACK_TOP_P (operands[
1]) && NON_STACK_REG_P (operands[
0]))
1115 output_to_reg (operands[
0], stack_top_dies);
1119 /* Handle other kinds of writes from the
387 */
1121 if (STACK_TOP_P (operands[
1]))
1124 return AS1 (fstp%z0,%y0);
1126 return AS1 (fst%z0,%y0);
1129 /* Handle other kinds of reads to the
387 */
1131 if (STACK_TOP_P (operands[
0]) && GET_CODE (operands[
1]) == CONST_DOUBLE)
1132 return (char *) output_move_const_single (operands);
1134 if (STACK_TOP_P (operands[
0]))
1135 return AS1 (fld%z1,%y1);
1137 /* Handle all DFmode moves not involving the
387 */
1139 return (char *) output_move_double (operands);
1143 [(set (match_operand:XF
0 "push_operand" "=<,<")
1144 (match_operand:XF
1 "general_operand" "gF,f"))]
1148 if (STACK_REG_P (operands[
1]))
1152 xops[
0] = AT_SP (SFmode);
1153 xops[
1] = GEN_INT (
12);
1154 xops[
2] = stack_pointer_rtx;
1156 output_asm_insn (AS2 (sub%L2,%
1,%
2), xops);
1157 output_asm_insn (AS1 (fstp%T0,%
0), xops);
1158 if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG))
1159 output_asm_insn (AS1 (fld%T0,%
0), xops);
1164 return (char *) output_move_double (operands);
1167 (define_insn "swapxf"
1168 [(set (match_operand:XF
0 "register_operand" "f")
1169 (match_operand:XF
1 "register_operand" "f"))
1175 if (STACK_TOP_P (operands[
0]))
1176 return AS1 (fxch,%
1);
1178 return AS1 (fxch,%
0);
1181 (define_insn "movxf"
1182 [(set (match_operand:XF
0 "general_operand" "=f,fm,!*rf,!*rm")
1183 (match_operand:XF
1 "general_operand" "fmG,f,*rfm,*rfF"))]
1184 ;; [(set (match_operand:XF
0 "general_operand" "=*rf,*rfm,f,!*rm")
1185 ;; (match_operand:XF
1 "general_operand" "*rfm,*rf,fG,fF"))]
1189 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) !=
0;
1191 /* First handle a
`pop' insn or a `fld %st(
0)' */
1193 if (STACK_TOP_P (operands[
0]) && STACK_TOP_P (operands[
1]))
1196 return AS1 (fstp,%y0);
1198 return AS1 (fld,%y0);
1201 /* Handle a transfer between the
387 and a
386 register */
1203 if (STACK_TOP_P (operands[
0]) && NON_STACK_REG_P (operands[
1]))
1205 output_op_from_reg (operands[
1], AS1 (fld%z0,%y1));
1209 if (STACK_TOP_P (operands[
1]) && NON_STACK_REG_P (operands[
0]))
1211 output_to_reg (operands[
0], stack_top_dies);
1215 /* Handle other kinds of writes from the
387 */
1217 if (STACK_TOP_P (operands[
1]))
1219 output_asm_insn (AS1 (fstp%z0,%y0), operands);
1220 if (! stack_top_dies)
1221 return AS1 (fld%z0,%y0);
1226 /* Handle other kinds of reads to the
387 */
1228 if (STACK_TOP_P (operands[
0]) && GET_CODE (operands[
1]) == CONST_DOUBLE)
1229 return (char *) output_move_const_single (operands);
1231 if (STACK_TOP_P (operands[
0]))
1232 return AS1 (fld%z1,%y1);
1234 /* Handle all XFmode moves not involving the
387 */
1236 return (char *) output_move_double (operands);
1240 [(set (match_operand:DI
0 "push_operand" "=<")
1241 (match_operand:DI
1 "general_operand" "roiF"))]
1245 return (char *) output_move_double (operands);
1248 (define_insn "movdi"
1249 [(set (match_operand:DI
0 "general_operand" "=r,rm")
1250 (match_operand:DI
1 "general_operand" "m,riF"))]
1254 return (char *) output_move_double (operands);
1257 ;;- conversion instructions
1260 ;;- zero extension instructions
1261 ;; See comments by
`andsi' for when andl is faster than movzx.
1263 (define_insn "zero_extendhisi2"
1264 [(set (match_operand:SI 0 "general_operand" "=r")
1266 (match_operand:HI 1 "nonimmediate_operand" "rm")))]
1270 if ((TARGET_486 || REGNO (operands[0]) == 0)
1271 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
1274 xops[0] = operands[0];
1275 xops[1] = GEN_INT (0xffff);
1276 output_asm_insn (AS2 (and%L0,%1,%k0), xops);
1281 return AS2 (movzx,%1,%0);
1283 return AS2 (movz%W0%L0,%1,%0);
1287 (define_insn "zero_extendqihi2"
1288 [(set (match_operand:HI 0 "general_operand" "=r")
1290 (match_operand:QI 1 "nonimmediate_operand" "qm")))]
1294 if ((TARGET_486 || REGNO (operands[0]) == 0)
1295 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
1298 xops[0] = operands[0];
1299 xops[1] = GEN_INT (0xff);
1300 output_asm_insn (AS2 (and%L0,%1,%k0), xops);
1305 return AS2 (movzx,%1,%0);
1307 return AS2 (movz%B0%W0,%1,%0);
1311 (define_insn "zero_extendqisi2"
1312 [(set (match_operand:SI 0 "general_operand" "=r")
1314 (match_operand:QI 1 "nonimmediate_operand" "qm")))]
1318 if ((TARGET_486 || REGNO (operands[0]) == 0)
1319 && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1]))
1322 xops[0] = operands[0];
1323 xops[1] = GEN_INT (0xff);
1324 output_asm_insn (AS2 (and%L0,%1,%k0), xops);
1329 return AS2 (movzx,%1,%0);
1331 return AS2 (movz%B0%L0,%1,%0);
1335 (define_insn "zero_extendsidi2"
1336 [(set (match_operand:DI 0 "register_operand" "=r")
1338 (match_operand:SI 1 "register_operand" "0")))]
1342 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1343 return AS2 (xor%L0,%0,%0);
1346 ;;- sign extension instructions
1348 (define_insn "extendsidi2"
1349 [(set (match_operand:DI 0 "register_operand" "=r")
1351 (match_operand:SI 1 "register_operand" "0")))]
1355 if (REGNO (operands[0]) == 0)
1357 /* This used to be cwtl, but that extends HI to SI somehow. */
1365 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1366 output_asm_insn (AS2 (mov%L0,%0,%1), operands);
1368 operands[0] = GEN_INT (31);
1369 return AS2 (sar%L1,%0,%1);
1372 ;; Note that the i386 programmers' manual says that the opcodes
1373 ;; are named movsx..., but the assembler on Unix does not accept that.
1374 ;; We use what the Unix assembler expects.
1376 (define_insn "extendhisi2"
1377 [(set (match_operand:SI 0 "general_operand" "=r")
1379 (match_operand:HI 1 "nonimmediate_operand" "rm")))]
1383 if (REGNO (operands[0]) == 0
1384 && REG_P (operands[1]) && REGNO (operands[1]) == 0)
1392 return AS2 (movsx,%1,%0);
1394 return AS2 (movs%W0%L0,%1,%0);
1398 (define_insn "extendqihi2"
1399 [(set (match_operand:HI 0 "general_operand" "=r")
1401 (match_operand:QI 1 "nonimmediate_operand" "qm")))]
1405 if (REGNO (operands[0]) == 0
1406 && REG_P (operands[1]) && REGNO (operands[1]) == 0)
1410 return AS2 (movsx,%1,%0);
1412 return AS2 (movs%B0%W0,%1,%0);
1416 (define_insn "extendqisi2"
1417 [(set (match_operand:SI 0 "general_operand" "=r")
1419 (match_operand:QI 1 "nonimmediate_operand" "qm")))]
1424 return AS2 (movsx,%1,%0);
1426 return AS2 (movs%B0%L0,%1,%0);
1430 ;; Conversions between float and double.
1432 (define_insn "extendsfdf2"
1433 [(set (match_operand:DF 0 "general_operand" "=fm,f")
1435 (match_operand:SF 1 "general_operand" "f,fm")))]
1439 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1441 if (NON_STACK_REG_P (operands[1]))
1443 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
1447 if (NON_STACK_REG_P (operands[0]))
1449 output_to_reg (operands[0], stack_top_dies);
1453 if (STACK_TOP_P (operands[0]))
1454 return AS1 (fld%z1,%y1);
1456 if (GET_CODE (operands[0]) == MEM)
1459 return AS1 (fstp%z0,%y0);
1461 return AS1 (fst%z0,%y0);
1467 (define_insn "extenddfxf2"
1468 [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r")
1470 (match_operand:DF 1 "general_operand" "f,fm,!*r,f")))]
1474 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1476 if (NON_STACK_REG_P (operands[1]))
1478 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
1482 if (NON_STACK_REG_P (operands[0]))
1484 output_to_reg (operands[0], stack_top_dies);
1488 if (STACK_TOP_P (operands[0]))
1489 return AS1 (fld%z1,%y1);
1491 if (GET_CODE (operands[0]) == MEM)
1493 output_asm_insn (AS1 (fstp%z0,%y0), operands);
1494 if (! stack_top_dies)
1495 return AS1 (fld%z0,%y0);
1502 (define_insn "extendsfxf2"
1503 [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r")
1505 (match_operand:SF 1 "general_operand" "f,fm,!*r,f")))]
1509 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1511 if (NON_STACK_REG_P (operands[1]))
1513 output_op_from_reg (operands[1], AS1 (fld%z0,%y1));
1517 if (NON_STACK_REG_P (operands[0]))
1519 output_to_reg (operands[0], stack_top_dies);
1523 if (STACK_TOP_P (operands[0]))
1524 return AS1 (fld%z1,%y1);
1526 if (GET_CODE (operands[0]) == MEM)
1528 output_asm_insn (AS1 (fstp%z0,%y0), operands);
1529 if (! stack_top_dies)
1530 return AS1 (fld%z0,%y0);
1537 (define_expand "truncdfsf2"
1538 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
1540 (match_operand:DF 1 "register_operand" "")))
1541 (clobber (match_dup 2))])]
1545 operands[2] = (rtx) assign_386_stack_local (SFmode, 0);
1548 ;; This cannot output into an f-reg because there is no way to be sure
1549 ;; of truncating in that case. Otherwise this is just like a simple move
1550 ;; insn. So we pretend we can output to a reg in order to get better
1551 ;; register preferencing, but we really use a stack slot.
1554 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m")
1556 (match_operand:DF 1 "register_operand" "0,f")))
1557 (clobber (match_operand:SF 2 "memory_operand" "m,m"))]
1561 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1563 if (GET_CODE (operands[0]) == MEM)
1566 return AS1 (fstp%z0,%0);
1568 return AS1 (fst%z0,%0);
1570 else if (STACK_TOP_P (operands[0]))
1572 output_asm_insn (AS1 (fstp%z2,%y2), operands);
1573 return AS1 (fld%z2,%y2);
1579 (define_insn "truncxfsf2"
1580 [(set (match_operand:SF 0 "general_operand" "=m,!*r")
1582 (match_operand:XF 1 "register_operand" "f,f")))]
1586 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1588 if (NON_STACK_REG_P (operands[0]))
1590 if (stack_top_dies == 0)
1592 output_asm_insn (AS1 (fld,%y1), operands);
1595 output_to_reg (operands[0], stack_top_dies);
1598 else if (GET_CODE (operands[0]) == MEM)
1601 return AS1 (fstp%z0,%0);
1604 output_asm_insn (AS1 (fld,%y1), operands);
1605 return AS1 (fstp%z0,%0);
1612 (define_insn "truncxfdf2"
1613 [(set (match_operand:DF 0 "general_operand" "=m,!*r")
1615 (match_operand:XF 1 "register_operand" "f,f")))]
1619 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
1621 if (NON_STACK_REG_P (operands[0]))
1623 if (stack_top_dies == 0)
1625 output_asm_insn (AS1 (fld,%y1), operands);
1628 output_to_reg (operands[0], stack_top_dies);
1631 else if (GET_CODE (operands[0]) == MEM)
1634 return AS1 (fstp%z0,%0);
1637 output_asm_insn (AS1 (fld,%y1), operands);
1638 return AS1 (fstp%z0,%0);
1646 ;; The 387 requires that the stack top dies after converting to DImode.
1648 ;; Represent an unsigned conversion from SImode to MODE_FLOAT by first
1649 ;; doing a signed conversion to DImode, and then taking just the low
1652 (define_expand "fixuns_truncxfsi2"
1654 (match_operand:XF 1 "register_operand" ""))
1655 (parallel [(set (match_dup 2)
1656 (fix:DI (fix:XF (match_dup 4))))
1657 (clobber (match_dup 4))
1658 (clobber (match_dup 5))
1659 (clobber (match_dup 6))
1660 (clobber (match_scratch:SI 7 ""))])
1661 (set (match_operand:SI 0 "general_operand" "")
1666 operands[2] = gen_reg_rtx (DImode);
1667 operands[3] = gen_lowpart (SImode, operands[2]);
1668 operands[4] = gen_reg_rtx (XFmode);
1669 operands[5] = (rtx) assign_386_stack_local (SImode, 0);
1670 operands[6] = (rtx) assign_386_stack_local (SImode, 1);
1673 (define_expand "fixuns_truncdfsi2"
1675 (match_operand:DF 1 "register_operand" ""))
1676 (parallel [(set (match_dup 2)
1677 (fix:DI (fix:DF (match_dup 4))))
1678 (clobber (match_dup 4))
1679 (clobber (match_dup 5))
1680 (clobber (match_dup 6))
1681 (clobber (match_scratch:SI 7 ""))])
1682 (set (match_operand:SI 0 "general_operand" "")
1687 operands[2] = gen_reg_rtx (DImode);
1688 operands[3] = gen_lowpart (SImode, operands[2]);
1689 operands[4] = gen_reg_rtx (DFmode);
1690 operands[5] = (rtx) assign_386_stack_local (SImode, 0);
1691 operands[6] = (rtx) assign_386_stack_local (SImode, 1);
1694 (define_expand "fixuns_truncsfsi2"
1696 (match_operand:SF 1 "register_operand" ""))
1697 (parallel [(set (match_dup 2)
1698 (fix:DI (fix:SF (match_dup 4))))
1699 (clobber (match_dup 4))
1700 (clobber (match_dup 5))
1701 (clobber (match_dup 6))
1702 (clobber (match_scratch:SI 7 ""))])
1703 (set (match_operand:SI 0 "general_operand" "")
1708 operands[2] = gen_reg_rtx (DImode);
1709 operands[3] = gen_lowpart (SImode, operands[2]);
1710 operands[4] = gen_reg_rtx (SFmode);
1711 operands[5] = (rtx) assign_386_stack_local (SImode, 0);
1712 operands[6] = (rtx) assign_386_stack_local (SImode, 1);
1715 ;; Signed conversion to DImode.
1717 (define_expand "fix_truncxfdi2"
1719 (match_operand:XF 1 "register_operand" ""))
1720 (parallel [(set (match_operand:DI 0 "general_operand" "")
1721 (fix:DI (fix:XF (match_dup 2))))
1722 (clobber (match_dup 2))
1723 (clobber (match_dup 3))
1724 (clobber (match_dup 4))
1725 (clobber (match_scratch:SI 5 ""))])]
1729 operands[1] = copy_to_mode_reg (XFmode, operands[1]);
1730 operands[2] = gen_reg_rtx (XFmode);
1731 operands[3] = (rtx) assign_386_stack_local (SImode, 0);
1732 operands[4] = (rtx) assign_386_stack_local (SImode, 1);
1735 (define_expand "fix_truncdfdi2"
1737 (match_operand:DF 1 "register_operand" ""))
1738 (parallel [(set (match_operand:DI 0 "general_operand" "")
1739 (fix:DI (fix:DF (match_dup 2))))
1740 (clobber (match_dup 2))
1741 (clobber (match_dup 3))
1742 (clobber (match_dup 4))
1743 (clobber (match_scratch:SI 5 ""))])]
1747 operands[1] = copy_to_mode_reg (DFmode, operands[1]);
1748 operands[2] = gen_reg_rtx (DFmode);
1749 operands[3] = (rtx) assign_386_stack_local (SImode, 0);
1750 operands[4] = (rtx) assign_386_stack_local (SImode, 1);
1753 (define_expand "fix_truncsfdi2"
1755 (match_operand:SF 1 "register_operand" ""))
1756 (parallel [(set (match_operand:DI 0 "general_operand" "")
1757 (fix:DI (fix:SF (match_dup 2))))
1758 (clobber (match_dup 2))
1759 (clobber (match_dup 3))
1760 (clobber (match_dup 4))
1761 (clobber (match_scratch:SI 5 ""))])]
1765 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
1766 operands[2] = gen_reg_rtx (SFmode);
1767 operands[3] = (rtx) assign_386_stack_local (SImode, 0);
1768 operands[4] = (rtx) assign_386_stack_local (SImode, 1);
1771 ;; These match a signed conversion of either DFmode or SFmode to DImode.
1774 [(set (match_operand:DI 0 "general_operand" "=rm")
1775 (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
1776 (clobber (match_dup 1))
1777 (clobber (match_operand:SI 2 "memory_operand" "m"))
1778 (clobber (match_operand:SI 3 "memory_operand" "m"))
1779 (clobber (match_scratch:SI 4 "=&q"))]
1781 "* return (char *) output_fix_trunc (insn, operands);")
1784 [(set (match_operand:DI 0 "general_operand" "=rm")
1785 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1786 (clobber (match_dup 1))
1787 (clobber (match_operand:SI 2 "memory_operand" "m"))
1788 (clobber (match_operand:SI 3 "memory_operand" "m"))
1789 (clobber (match_scratch:SI 4 "=&q"))]
1791 "* return (char *) output_fix_trunc (insn, operands);")
1794 [(set (match_operand:DI 0 "general_operand" "=rm")
1795 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
1796 (clobber (match_dup 1))
1797 (clobber (match_operand:SI 2 "memory_operand" "m"))
1798 (clobber (match_operand:SI 3 "memory_operand" "m"))
1799 (clobber (match_scratch:SI 4 "=&q"))]
1801 "* return (char *) output_fix_trunc (insn, operands);")
1803 ;; Signed MODE_FLOAT conversion to SImode.
1805 (define_expand "fix_truncxfsi2"
1806 [(parallel [(set (match_operand:SI 0 "general_operand" "")
1808 (fix:XF (match_operand:XF 1 "register_operand" ""))))
1809 (clobber (match_dup 2))
1810 (clobber (match_dup 3))
1811 (clobber (match_scratch:SI 4 ""))])]
1815 operands[2] = (rtx) assign_386_stack_local (SImode, 0);
1816 operands[3] = (rtx) assign_386_stack_local (SImode, 1);
1819 (define_expand "fix_truncdfsi2"
1820 [(parallel [(set (match_operand:SI 0 "general_operand" "")
1822 (fix:DF (match_operand:DF 1 "register_operand" ""))))
1823 (clobber (match_dup 2))
1824 (clobber (match_dup 3))
1825 (clobber (match_scratch:SI 4 ""))])]
1829 operands[2] = (rtx) assign_386_stack_local (SImode, 0);
1830 operands[3] = (rtx) assign_386_stack_local (SImode, 1);
1833 (define_expand "fix_truncsfsi2"
1834 [(parallel [(set (match_operand:SI 0 "general_operand" "")
1836 (fix:SF (match_operand:SF 1 "register_operand" ""))))
1837 (clobber (match_dup 2))
1838 (clobber (match_dup 3))
1839 (clobber (match_scratch:SI 4 ""))])]
1843 operands[2] = (rtx) assign_386_stack_local (SImode, 0);
1844 operands[3] = (rtx) assign_386_stack_local (SImode, 1);
1848 [(set (match_operand:SI 0 "general_operand" "=rm")
1849 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))
1850 (clobber (match_operand:SI 2 "memory_operand" "m"))
1851 (clobber (match_operand:SI 3 "memory_operand" "m"))
1852 (clobber (match_scratch:SI 4 "=&q"))]
1854 "* return (char *) output_fix_trunc (insn, operands);")
1857 [(set (match_operand:SI 0 "general_operand" "=rm")
1858 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1859 (clobber (match_operand:SI 2 "memory_operand" "m"))
1860 (clobber (match_operand:SI 3 "memory_operand" "m"))
1861 (clobber (match_scratch:SI 4 "=&q"))]
1863 "* return (char *) output_fix_trunc (insn, operands);")
1866 [(set (match_operand:SI 0 "general_operand" "=rm")
1867 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))
1868 (clobber (match_operand:SI 2 "memory_operand" "m"))
1869 (clobber (match_operand:SI 3 "memory_operand" "m"))
1870 (clobber (match_scratch:SI 4 "=&q"))]
1872 "* return (char *) output_fix_trunc (insn, operands);")
1874 ;; Conversion between fixed point and floating point.
1875 ;; The actual pattern that matches these is at the end of this file.
1877 ;; ??? Possibly represent floatunssidf2 here in gcc2.
1879 (define_expand "floatsisf2"
1880 [(set (match_operand:SF 0 "register_operand" "")
1881 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
1885 (define_expand "floatdisf2"
1886 [(set (match_operand:SF 0 "register_operand" "")
1887 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
1891 (define_expand "floatsidf2"
1892 [(set (match_operand:DF 0 "register_operand" "")
1893 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
1897 (define_expand "floatdidf2"
1898 [(set (match_operand:DF 0 "register_operand" "")
1899 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
1903 (define_expand "floatsixf2"
1904 [(set (match_operand:XF 0 "register_operand" "")
1905 (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))]
1909 (define_expand "floatdixf2"
1910 [(set (match_operand:XF 0 "register_operand" "")
1911 (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))]
1915 ;; This will convert from SImode or DImode to MODE_FLOAT.
1918 [(set (match_operand:XF 0 "register_operand" "=f")
1919 (float:XF (match_operand:DI 1 "general_operand" "rm")))]
1923 if (NON_STACK_REG_P (operands[1]))
1925 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
1928 else if (GET_CODE (operands[1]) == MEM)
1929 return AS1 (fild%z1,%1);
1935 [(set (match_operand:DF 0 "register_operand" "=f")
1936 (float:DF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
1940 if (NON_STACK_REG_P (operands[1]))
1942 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
1945 else if (GET_CODE (operands[1]) == MEM)
1946 return AS1 (fild%z1,%1);
1952 [(set (match_operand:SF 0 "register_operand" "=f")
1953 (float:SF (match_operand:DI 1 "nonimmediate_operand" "rm")))]
1957 if (NON_STACK_REG_P (operands[1]))
1959 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
1962 else if (GET_CODE (operands[1]) == MEM)
1963 return AS1 (fild%z1,%1);
1969 [(set (match_operand:DF 0 "register_operand" "=f")
1970 (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
1974 if (NON_STACK_REG_P (operands[1]))
1976 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
1979 else if (GET_CODE (operands[1]) == MEM)
1980 return AS1 (fild%z1,%1);
1986 [(set (match_operand:XF 0 "register_operand" "=f,f")
1987 (float:XF (match_operand:SI 1 "general_operand" "m,!*r")))]
1991 if (NON_STACK_REG_P (operands[1]))
1993 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
1996 else if (GET_CODE (operands[1]) == MEM)
1997 return AS1 (fild%z1,%1);
2003 [(set (match_operand:SF 0 "register_operand" "=f")
2004 (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))]
2008 if (NON_STACK_REG_P (operands[1]))
2010 output_op_from_reg (operands[1], AS1 (fild%z0,%1));
2013 else if (GET_CODE (operands[1]) == MEM)
2014 return AS1 (fild%z1,%1);
2019 ;;- add instructions
2021 (define_insn "adddi3"
2022 [(set (match_operand:DI 0 "general_operand" "=&r,ro")
2023 (plus:DI (match_operand:DI 1 "general_operand" "%0,0")
2024 (match_operand:DI 2 "general_operand" "o,riF")))]
2028 rtx low[3], high[3];
2032 split_di (operands, 3, low, high);
2034 if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0)
2036 output_asm_insn (AS2 (add%L0,%2,%0), low);
2037 output_asm_insn (AS2 (adc%L0,%2,%0), high);
2040 output_asm_insn (AS2 (add%L0,%2,%0), high);
2044 ;; On a 486, it is faster to do movl/addl than to do a single leal if
2045 ;; operands[1] and operands[2] are both registers.
2047 (define_insn "addsi3"
2048 [(set (match_operand:SI 0 "general_operand" "=?r,rm,r")
2049 (plus:SI (match_operand:SI 1 "general_operand" "%r,0,0")
2050 (match_operand:SI 2 "general_operand" "ri,ri,rm")))]
2054 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
2056 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
2057 return AS2 (add%L0,%1,%0);
2059 if (! TARGET_486 || ! REG_P (operands[2]))
2063 if (operands[2] == stack_pointer_rtx)
2068 operands[1] = operands[2];
2071 if (operands[2] != stack_pointer_rtx)
2073 operands[1] = SET_SRC (PATTERN (insn));
2074 return AS2 (lea%L0,%a1,%0);
2078 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
2081 if (operands[2] == const1_rtx)
2082 return AS1 (inc%L0,%0);
2084 if (operands[2] == constm1_rtx)
2085 return AS1 (dec%L0,%0);
2087 return AS2 (add%L0,%2,%0);
2090 ;; ??? `lea' here, for three operand add? If leaw is used, only %bx,
2091 ;; %si and %di can appear in SET_SRC, and output_asm_insn might not be
2092 ;; able to handle the operand. But leal always works?
2094 (define_insn "addhi3"
2095 [(set (match_operand:HI
0 "general_operand" "=rm,r")
2096 (plus:HI (match_operand:HI
1 "general_operand" "%
0,
0")
2097 (match_operand:HI
2 "general_operand" "ri,rm")))]
2101 /* ??? what about offsettable memory references? */
2102 if (QI_REG_P (operands[
0])
2103 && GET_CODE (operands[
2]) == CONST_INT
2104 && (INTVAL (operands[
2]) &
0xff) ==
0)
2106 int byteval = (INTVAL (operands[
2]) >>
8) &
0xff;
2110 return AS1 (inc%B0,%h0);
2111 else if (byteval ==
255)
2112 return AS1 (dec%B0,%h0);
2114 operands[
2] = GEN_INT (byteval);
2115 return AS2 (add%B0,%
2,%h0);
2118 if (operands[
2] == const1_rtx)
2119 return AS1 (inc%W0,%
0);
2121 if (operands[
2] == constm1_rtx
2122 || (GET_CODE (operands[
2]) == CONST_INT
2123 && INTVAL (operands[
2]) ==
65535))
2124 return AS1 (dec%W0,%
0);
2126 return AS2 (add%W0,%
2,%
0);
2129 (define_insn "addqi3"
2130 [(set (match_operand:QI
0 "general_operand" "=qm,q")
2131 (plus:QI (match_operand:QI
1 "general_operand" "%
0,
0")
2132 (match_operand:QI
2 "general_operand" "qn,qmn")))]
2136 if (operands[
2] == const1_rtx)
2137 return AS1 (inc%B0,%
0);
2139 if (operands[
2] == constm1_rtx
2140 || (GET_CODE (operands[
2]) == CONST_INT
2141 && INTVAL (operands[
2]) ==
255))
2142 return AS1 (dec%B0,%
0);
2144 return AS2 (add%B0,%
2,%
0);
2147 ;Lennart Augustsson <augustss@cs.chalmers.se>
2148 ;says this pattern just makes slower code:
2152 ; leal -
80(%ebp),%eax
2156 ; [(set (match_operand:SI
0 "push_operand" "=<")
2157 ; (plus:SI (match_operand:SI
1 "general_operand" "%r")
2158 ; (match_operand:SI
2 "general_operand" "ri")))]
2163 ; xops[
0] = operands[
0];
2164 ; xops[
1] = operands[
1];
2165 ; xops[
2] = operands[
2];
2166 ; xops[
3] = gen_rtx (MEM, SImode, stack_pointer_rtx);
2167 ; output_asm_insn (
\"push%z1 %
1\", xops);
2168 ; output_asm_insn (AS2 (add%z3,%
2,%
3), xops);
2172 ;; addsi3 is faster, so put this after.
2175 [(set (match_operand:SI
0 "register_operand" "=r")
2176 (match_operand:QI
1 "address_operand" "p"))]
2181 /* Adding a constant to a register is faster with an add. */
2182 /* ??? can this ever happen? */
2183 if (GET_CODE (operands[
1]) == PLUS
2184 && GET_CODE (XEXP (operands[
1],
1)) == CONST_INT
2185 && rtx_equal_p (operands[
0], XEXP (operands[
1],
0)))
2187 operands[
1] = XEXP (operands[
1],
1);
2189 if (operands[
1] == const1_rtx)
2190 return AS1 (inc%L0,%
0);
2192 if (operands[
1] == constm1_rtx)
2193 return AS1 (dec%L0,%
0);
2195 return AS2 (add%L0,%
1,%
0);
2197 return AS2 (lea%L0,%a1,%
0);
2200 ;; The patterns that match these are at the end of this file.
2202 (define_expand "addxf3"
2203 [(set (match_operand:XF
0 "register_operand" "")
2204 (plus:XF (match_operand:XF
1 "nonimmediate_operand" "")
2205 (match_operand:XF
2 "nonimmediate_operand" "")))]
2209 (define_expand "adddf3"
2210 [(set (match_operand:DF
0 "register_operand" "")
2211 (plus:DF (match_operand:DF
1 "nonimmediate_operand" "")
2212 (match_operand:DF
2 "nonimmediate_operand" "")))]
2216 (define_expand "addsf3"
2217 [(set (match_operand:SF
0 "register_operand" "")
2218 (plus:SF (match_operand:SF
1 "nonimmediate_operand" "")
2219 (match_operand:SF
2 "nonimmediate_operand" "")))]
2223 ;;- subtract instructions
2225 (define_insn "subdi3"
2226 [(set (match_operand:DI
0 "general_operand" "=&r,ro")
2227 (minus:DI (match_operand:DI
1 "general_operand" "
0,
0")
2228 (match_operand:DI
2 "general_operand" "o,riF")))]
2232 rtx low[
3], high[
3];
2236 split_di (operands,
3, low, high);
2238 if (GET_CODE (low[
2]) != CONST_INT || INTVAL (low[
2]) !=
0)
2240 output_asm_insn (AS2 (sub%L0,%
2,%
0), low);
2241 output_asm_insn (AS2 (sbb%L0,%
2,%
0), high);
2244 output_asm_insn (AS2 (sub%L0,%
2,%
0), high);
2249 (define_insn "subsi3"
2250 [(set (match_operand:SI
0 "general_operand" "=rm,r")
2251 (minus:SI (match_operand:SI
1 "general_operand" "
0,
0")
2252 (match_operand:SI
2 "general_operand" "ri,rm")))]
2254 "* return AS2 (sub%L0,%
2,%
0);")
2256 (define_insn "subhi3"
2257 [(set (match_operand:HI
0 "general_operand" "=rm,r")
2258 (minus:HI (match_operand:HI
1 "general_operand" "
0,
0")
2259 (match_operand:HI
2 "general_operand" "ri,rm")))]
2261 "* return AS2 (sub%W0,%
2,%
0);")
2263 (define_insn "subqi3"
2264 [(set (match_operand:QI
0 "general_operand" "=qm,q")
2265 (minus:QI (match_operand:QI
1 "general_operand" "
0,
0")
2266 (match_operand:QI
2 "general_operand" "qn,qmn")))]
2268 "* return AS2 (sub%B0,%
2,%
0);")
2270 ;; The patterns that match these are at the end of this file.
2272 (define_expand "subxf3"
2273 [(set (match_operand:XF
0 "register_operand" "")
2274 (minus:XF (match_operand:XF
1 "nonimmediate_operand" "")
2275 (match_operand:XF
2 "nonimmediate_operand" "")))]
2279 (define_expand "subdf3"
2280 [(set (match_operand:DF
0 "register_operand" "")
2281 (minus:DF (match_operand:DF
1 "nonimmediate_operand" "")
2282 (match_operand:DF
2 "nonimmediate_operand" "")))]
2286 (define_expand "subsf3"
2287 [(set (match_operand:SF
0 "register_operand" "")
2288 (minus:SF (match_operand:SF
1 "nonimmediate_operand" "")
2289 (match_operand:SF
2 "nonimmediate_operand" "")))]
2293 ;;- multiply instructions
2295 ;(define_insn "mulqi3"
2296 ; [(set (match_operand:QI
0 "general_operand" "=a")
2297 ; (mult:QI (match_operand:QI
1 "general_operand" "%
0")
2298 ; (match_operand:QI
2 "general_operand" "qm")))]
2303 [(set (match_operand:HI
0 "general_operand" "=r")
2304 (mult:HI (match_operand:HI
1 "general_operand" "%
0")
2305 (match_operand:HI
2 "general_operand" "r")))]
2306 "GET_CODE (operands[
2]) == CONST_INT && INTVAL (operands[
2]) ==
0x80"
2307 "* return AS2 (imul%W0,%
2,%
0);")
2309 (define_insn "mulhi3"
2310 [(set (match_operand:HI
0 "general_operand" "=r,r")
2311 (mult:HI (match_operand:HI
1 "general_operand" "%
0,rm")
2312 (match_operand:HI
2 "general_operand" "g,i")))]
2316 if (GET_CODE (operands[
1]) == REG
2317 && REGNO (operands[
1]) == REGNO (operands[
0])
2318 && (GET_CODE (operands[
2]) == MEM || GET_CODE (operands[
2]) == REG))
2319 /* Assembler has weird restrictions. */
2320 return AS2 (imul%W0,%
2,%
0);
2321 return AS3 (imul%W0,%
2,%
1,%
0);
2325 [(set (match_operand:SI
0 "general_operand" "=r")
2326 (mult:SI (match_operand:SI
1 "general_operand" "%
0")
2327 (match_operand:SI
2 "general_operand" "r")))]
2328 "GET_CODE (operands[
2]) == CONST_INT && INTVAL (operands[
2]) ==
0x80"
2329 "* return AS2 (imul%L0,%
2,%
0);")
2331 (define_insn "mulsi3"
2332 [(set (match_operand:SI
0 "general_operand" "=r,r")
2333 (mult:SI (match_operand:SI
1 "general_operand" "%
0,rm")
2334 (match_operand:SI
2 "general_operand" "g,i")))]
2338 if (GET_CODE (operands[
1]) == REG
2339 && REGNO (operands[
1]) == REGNO (operands[
0])
2340 && (GET_CODE (operands[
2]) == MEM || GET_CODE (operands[
2]) == REG))
2341 /* Assembler has weird restrictions. */
2342 return AS2 (imul%L0,%
2,%
0);
2343 return AS3 (imul%L0,%
2,%
1,%
0);
2347 [(set (match_operand:HI
0 "general_operand" "=a")
2348 (mult:HI (zero_extend:HI
2349 (match_operand:QI
1 "nonimmediate_operand" "%
0"))
2351 (match_operand:QI
2 "nonimmediate_operand" "qm"))))]
2355 ;; The patterns that match these are at the end of this file.
2357 (define_expand "mulxf3"
2358 [(set (match_operand:XF
0 "register_operand" "")
2359 (mult:XF (match_operand:XF
1 "nonimmediate_operand" "")
2360 (match_operand:XF
2 "nonimmediate_operand" "")))]
2364 (define_expand "muldf3"
2365 [(set (match_operand:DF
0 "register_operand" "")
2366 (mult:DF (match_operand:DF
1 "nonimmediate_operand" "")
2367 (match_operand:DF
2 "nonimmediate_operand" "")))]
2371 (define_expand "mulsf3"
2372 [(set (match_operand:SF
0 "register_operand" "")
2373 (mult:SF (match_operand:SF
1 "nonimmediate_operand" "")
2374 (match_operand:SF
2 "nonimmediate_operand" "")))]
2378 ;;- divide instructions
2380 (define_insn "divqi3"
2381 [(set (match_operand:QI
0 "general_operand" "=a")
2382 (div:QI (match_operand:HI
1 "general_operand" "
0")
2383 (match_operand:QI
2 "general_operand" "qm")))]
2387 (define_insn "udivqi3"
2388 [(set (match_operand:QI
0 "general_operand" "=a")
2389 (udiv:QI (match_operand:HI
1 "general_operand" "
0")
2390 (match_operand:QI
2 "general_operand" "qm")))]
2394 ;; The patterns that match these are at the end of this file.
2396 (define_expand "divxf3"
2397 [(set (match_operand:XF
0 "register_operand" "")
2398 (div:XF (match_operand:XF
1 "nonimmediate_operand" "")
2399 (match_operand:XF
2 "nonimmediate_operand" "")))]
2403 (define_expand "divdf3"
2404 [(set (match_operand:DF
0 "register_operand" "")
2405 (div:DF (match_operand:DF
1 "nonimmediate_operand" "")
2406 (match_operand:DF
2 "nonimmediate_operand" "")))]
2410 (define_expand "divsf3"
2411 [(set (match_operand:SF
0 "register_operand" "")
2412 (div:SF (match_operand:SF
1 "nonimmediate_operand" "")
2413 (match_operand:SF
2 "nonimmediate_operand" "")))]
2417 ;; Remainder instructions.
2419 (define_insn "divmodsi4"
2420 [(set (match_operand:SI
0 "register_operand" "=a")
2421 (div:SI (match_operand:SI
1 "register_operand" "
0")
2422 (match_operand:SI
2 "general_operand" "rm")))
2423 (set (match_operand:SI
3 "register_operand" "=&d")
2424 (mod:SI (match_dup
1) (match_dup
2)))]
2429 output_asm_insn (
\"cdq
\", operands);
2431 output_asm_insn (
\"cltd
\", operands);
2433 return AS1 (idiv%L0,%
2);
2436 (define_insn "divmodhi4"
2437 [(set (match_operand:HI
0 "register_operand" "=a")
2438 (div:HI (match_operand:HI
1 "register_operand" "
0")
2439 (match_operand:HI
2 "general_operand" "rm")))
2440 (set (match_operand:HI
3 "register_operand" "=&d")
2441 (mod:HI (match_dup
1) (match_dup
2)))]
2445 ;; ??? Can we make gcc zero extend operand[
0]?
2446 (define_insn "udivmodsi4"
2447 [(set (match_operand:SI
0 "register_operand" "=a")
2448 (udiv:SI (match_operand:SI
1 "register_operand" "
0")
2449 (match_operand:SI
2 "general_operand" "rm")))
2450 (set (match_operand:SI
3 "register_operand" "=&d")
2451 (umod:SI (match_dup
1) (match_dup
2)))]
2455 output_asm_insn (AS2 (xor%L3,%
3,%
3), operands);
2456 return AS1 (div%L0,%
2);
2459 ;; ??? Can we make gcc zero extend operand[
0]?
2460 (define_insn "udivmodhi4"
2461 [(set (match_operand:HI
0 "register_operand" "=a")
2462 (udiv:HI (match_operand:HI
1 "register_operand" "
0")
2463 (match_operand:HI
2 "general_operand" "rm")))
2464 (set (match_operand:HI
3 "register_operand" "=&d")
2465 (umod:HI (match_dup
1) (match_dup
2)))]
2469 output_asm_insn (AS2 (xor%W0,%
3,%
3), operands);
2470 return AS1 (div%W0,%
2);
2474 ;;this should be a valid double division which we may want to add
2477 [(set (match_operand:SI
0 "register_operand" "=a")
2478 (udiv:DI (match_operand:DI
1 "register_operand" "a")
2479 (match_operand:SI
2 "general_operand" "rm")))
2480 (set (match_operand:SI
3 "register_operand" "=d")
2481 (umod:SI (match_dup
1) (match_dup
2)))]
2486 ;;- and instructions
2493 ;; but if the reg is %eax, then the "andl" is faster.
2495 ;; On i486, the "andl" is always faster than the "movzbl".
2497 ;; On both i386 and i486, a three operand AND is as fast with movzbl or
2498 ;; movzwl as with andl, if operands[
0] != operands[
1].
2500 ;; The
`r' in `rm' for operand
3 looks redundant, but it causes
2501 ;; optional reloads to be generated if op
3 is a pseudo in a stack slot.
2503 ;; ??? What if we only change one byte of an offsettable memory reference?
2504 (define_insn "andsi3"
2505 [(set (match_operand:SI
0 "general_operand" "=r,r,rm,r")
2506 (and:SI (match_operand:SI
1 "general_operand" "%rm,qm,
0,
0")
2507 (match_operand:SI
2 "general_operand" "L,K,ri,rm")))]
2511 if (GET_CODE (operands[
2]) == CONST_INT
2512 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0])))
2514 if (INTVAL (operands[
2]) ==
0xffff && REG_P (operands[
0])
2515 && (! REG_P (operands[
1])
2516 || REGNO (operands[
0]) !=
0 || REGNO (operands[
1]) !=
0)
2517 && (! TARGET_486 || ! rtx_equal_p (operands[
0], operands[
1])))
2519 /* ??? tege: Should forget CC_STATUS only if we clobber a
2520 remembered operand. Fix that later. */
2523 return AS2 (movzx,%w1,%
0);
2525 return AS2 (movz%W0%L0,%w1,%
0);
2529 if (INTVAL (operands[
2]) ==
0xff && REG_P (operands[
0])
2530 && !(REG_P (operands[
1]) && NON_QI_REG_P (operands[
1]))
2531 && (! REG_P (operands[
1])
2532 || REGNO (operands[
0]) !=
0 || REGNO (operands[
1]) !=
0)
2533 && (! TARGET_486 || ! rtx_equal_p (operands[
0], operands[
1])))
2535 /* ??? tege: Should forget CC_STATUS only if we clobber a
2536 remembered operand. Fix that later. */
2539 return AS2 (movzx,%b1,%
0);
2541 return AS2 (movz%B0%L0,%b1,%
0);
2545 if (QI_REG_P (operands[
0]) && ~(INTVAL (operands[
2]) |
0xff) ==
0)
2549 if (INTVAL (operands[
2]) ==
0xffffff00)
2551 operands[
2] = const0_rtx;
2552 return AS2 (mov%B0,%
2,%b0);
2555 operands[
2] = GEN_INT (INTVAL (operands[
2]) &
0xff);
2556 return AS2 (and%B0,%
2,%b0);
2559 if (QI_REG_P (operands[
0]) && ~(INTVAL (operands[
2]) |
0xff00) ==
0)
2563 if (INTVAL (operands[
2]) ==
0xffff00ff)
2565 operands[
2] = const0_rtx;
2566 return AS2 (mov%B0,%
2,%h0);
2569 operands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
8) &
0xff);
2570 return AS2 (and%B0,%
2,%h0);
2573 if (GET_CODE (operands[
0]) == MEM && INTVAL (operands[
2]) ==
0xffff0000)
2575 operands[
2] = const0_rtx;
2576 return AS2 (mov%W0,%
2,%w0);
2580 return AS2 (and%L0,%
2,%
0);
2583 (define_insn "andhi3"
2584 [(set (match_operand:HI
0 "general_operand" "=rm,r")
2585 (and:HI (match_operand:HI
1 "general_operand" "%
0,
0")
2586 (match_operand:HI
2 "general_operand" "ri,rm")))]
2590 if (GET_CODE (operands[
2]) == CONST_INT
2591 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0])))
2593 /* Can we ignore the upper byte? */
2594 if ((! REG_P (operands[
0]) || QI_REG_P (operands[
0]))
2595 && (INTVAL (operands[
2]) &
0xff00) ==
0xff00)
2599 if ((INTVAL (operands[
2]) &
0xff) ==
0)
2601 operands[
2] = const0_rtx;
2602 return AS2 (mov%B0,%
2,%b0);
2605 operands[
2] = GEN_INT (INTVAL (operands[
2]) &
0xff);
2606 return AS2 (and%B0,%
2,%b0);
2609 /* Can we ignore the lower byte? */
2610 /* ??? what about offsettable memory references? */
2611 if (QI_REG_P (operands[
0]) && (INTVAL (operands[
2]) &
0xff) ==
0xff)
2615 if ((INTVAL (operands[
2]) &
0xff00) ==
0)
2617 operands[
2] = const0_rtx;
2618 return AS2 (mov%B0,%
2,%h0);
2621 operands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
8) &
0xff);
2622 return AS2 (and%B0,%
2,%h0);
2626 return AS2 (and%W0,%
2,%
0);
2629 (define_insn "andqi3"
2630 [(set (match_operand:QI
0 "general_operand" "=qm,q")
2631 (and:QI (match_operand:QI
1 "general_operand" "%
0,
0")
2632 (match_operand:QI
2 "general_operand" "qn,qmn")))]
2634 "* return AS2 (and%B0,%
2,%
0);")
2636 /* I am nervous about these two.. add them later..
2637 ;I presume this means that we have something in say op0= eax which is small
2638 ;and we want to and it with memory so we can do this by just an
2639 ;andb m,%al and have success.
2641 [(set (match_operand:SI
0 "general_operand" "=r")
2642 (and:SI (zero_extend:SI
2643 (match_operand:HI
1 "nonimmediate_operand" "rm"))
2644 (match_operand:SI
2 "general_operand" "
0")))]
2645 "GET_CODE (operands[
2]) == CONST_INT
2646 && (unsigned int) INTVAL (operands[
2]) < (
1 << GET_MODE_BITSIZE (HImode))"
2650 [(set (match_operand:SI
0 "general_operand" "=q")
2652 (zero_extend:SI (match_operand:QI
1 "nonimmediate_operand" "qm"))
2653 (match_operand:SI
2 "general_operand" "
0")))]
2654 "GET_CODE (operands[
2]) == CONST_INT
2655 && (unsigned int) INTVAL (operands[
2]) < (
1 << GET_MODE_BITSIZE (QImode))"
2660 ;;- Bit set (inclusive or) instructions
2662 ;; ??? What if we only change one byte of an offsettable memory reference?
2663 (define_insn "iorsi3"
2664 [(set (match_operand:SI
0 "general_operand" "=rm,r")
2665 (ior:SI (match_operand:SI
1 "general_operand" "%
0,
0")
2666 (match_operand:SI
2 "general_operand" "ri,rm")))]
2670 if (GET_CODE (operands[
2]) == CONST_INT
2671 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0])))
2673 if ((! REG_P (operands[
0]) || QI_REG_P (operands[
0]))
2674 && (INTVAL (operands[
2]) & ~
0xff) ==
0)
2678 if (INTVAL (operands[
2]) ==
0xff)
2679 return AS2 (mov%B0,%
2,%b0);
2681 return AS2 (or%B0,%
2,%b0);
2684 if (QI_REG_P (operands[
0]) && (INTVAL (operands[
2]) & ~
0xff00) ==
0)
2687 operands[
2] = GEN_INT (INTVAL (operands[
2]) >>
8);
2689 if (INTVAL (operands[
2]) ==
0xff)
2690 return AS2 (mov%B0,%
2,%h0);
2692 return AS2 (or%B0,%
2,%h0);
2696 return AS2 (or%L0,%
2,%
0);
2699 (define_insn "iorhi3"
2700 [(set (match_operand:HI
0 "general_operand" "=rm,r")
2701 (ior:HI (match_operand:HI
1 "general_operand" "%
0,
0")
2702 (match_operand:HI
2 "general_operand" "ri,rm")))]
2706 if (GET_CODE (operands[
2]) == CONST_INT
2707 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0])))
2709 /* Can we ignore the upper byte? */
2710 if ((! REG_P (operands[
0]) || QI_REG_P (operands[
0]))
2711 && (INTVAL (operands[
2]) &
0xff00) ==
0)
2714 if (INTVAL (operands[
2]) &
0xffff0000)
2715 operands[
2] = GEN_INT (INTVAL (operands[
2]) &
0xffff);
2717 if (INTVAL (operands[
2]) ==
0xff)
2718 return AS2 (mov%B0,%
2,%b0);
2720 return AS2 (or%B0,%
2,%b0);
2723 /* Can we ignore the lower byte? */
2724 /* ??? what about offsettable memory references? */
2725 if (QI_REG_P (operands[
0])
2726 && (INTVAL (operands[
2]) &
0xff) ==
0)
2729 operands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
8) &
0xff);
2731 if (INTVAL (operands[
2]) ==
0xff)
2732 return AS2 (mov%B0,%
2,%h0);
2734 return AS2 (or%B0,%
2,%h0);
2738 return AS2 (or%W0,%
2,%
0);
2741 (define_insn "iorqi3"
2742 [(set (match_operand:QI
0 "general_operand" "=qm,q")
2743 (ior:QI (match_operand:QI
1 "general_operand" "%
0,
0")
2744 (match_operand:QI
2 "general_operand" "qn,qmn")))]
2746 "* return AS2 (or%B0,%
2,%
0);")
2748 ;;- xor instructions
2750 ;; ??? What if we only change one byte of an offsettable memory reference?
2751 (define_insn "xorsi3"
2752 [(set (match_operand:SI
0 "general_operand" "=rm,r")
2753 (xor:SI (match_operand:SI
1 "general_operand" "%
0,
0")
2754 (match_operand:SI
2 "general_operand" "ri,rm")))]
2758 if (GET_CODE (operands[
2]) == CONST_INT
2759 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0])))
2761 if ((! REG_P (operands[
0]) || QI_REG_P (operands[
0]))
2762 && (INTVAL (operands[
2]) & ~
0xff) ==
0)
2766 if (INTVAL (operands[
2]) ==
0xff)
2767 return AS1 (not%B0,%b0);
2769 return AS2 (xor%B0,%
2,%b0);
2772 if (QI_REG_P (operands[
0]) && (INTVAL (operands[
2]) & ~
0xff00) ==
0)
2775 operands[
2] = GEN_INT (INTVAL (operands[
2]) >>
8);
2777 if (INTVAL (operands[
2]) ==
0xff)
2778 return AS1 (not%B0,%h0);
2780 return AS2 (xor%B0,%
2,%h0);
2784 return AS2 (xor%L0,%
2,%
0);
2787 (define_insn "xorhi3"
2788 [(set (match_operand:HI
0 "general_operand" "=rm,r")
2789 (xor:HI (match_operand:HI
1 "general_operand" "%
0,
0")
2790 (match_operand:HI
2 "general_operand" "ri,rm")))]
2794 if (GET_CODE (operands[
2]) == CONST_INT
2795 && ! (GET_CODE (operands[
0]) == MEM && MEM_VOLATILE_P (operands[
0])))
2797 /* Can we ignore the upper byte? */
2798 if ((! REG_P (operands[
0]) || QI_REG_P (operands[
0]))
2799 && (INTVAL (operands[
2]) &
0xff00) ==
0)
2802 if (INTVAL (operands[
2]) &
0xffff0000)
2803 operands[
2] = GEN_INT (INTVAL (operands[
2]) &
0xffff);
2805 if (INTVAL (operands[
2]) ==
0xff)
2806 return AS1 (not%B0,%b0);
2808 return AS2 (xor%B0,%
2,%b0);
2811 /* Can we ignore the lower byte? */
2812 /* ??? what about offsettable memory references? */
2813 if (QI_REG_P (operands[
0])
2814 && (INTVAL (operands[
2]) &
0xff) ==
0)
2817 operands[
2] = GEN_INT ((INTVAL (operands[
2]) >>
8) &
0xff);
2819 if (INTVAL (operands[
2]) ==
0xff)
2820 return AS1 (not%B0,%h0);
2822 return AS2 (xor%B0,%
2,%h0);
2826 return AS2 (xor%W0,%
2,%
0);
2829 (define_insn "xorqi3"
2830 [(set (match_operand:QI
0 "general_operand" "=qm,q")
2831 (xor:QI (match_operand:QI
1 "general_operand" "%
0,
0")
2832 (match_operand:QI
2 "general_operand" "qn,qm")))]
2834 "* return AS2 (xor%B0,%
2,%
0);")
2836 ;;- negation instructions
2838 (define_insn "negdi2"
2839 [(set (match_operand:DI
0 "general_operand" "=&ro")
2840 (neg:DI (match_operand:DI
1 "general_operand" "
0")))]
2844 rtx xops[
2], low[
1], high[
1];
2848 split_di (operands,
1, low, high);
2849 xops[
0] = const0_rtx;
2852 output_asm_insn (AS1 (neg%L0,%
0), low);
2853 output_asm_insn (AS2 (adc%L1,%
0,%
1), xops);
2854 output_asm_insn (AS1 (neg%L0,%
0), high);
2858 (define_insn "negsi2"
2859 [(set (match_operand:SI
0 "general_operand" "=rm")
2860 (neg:SI (match_operand:SI
1 "general_operand" "
0")))]
2864 (define_insn "neghi2"
2865 [(set (match_operand:HI
0 "general_operand" "=rm")
2866 (neg:HI (match_operand:HI
1 "general_operand" "
0")))]
2870 (define_insn "negqi2"
2871 [(set (match_operand:QI
0 "general_operand" "=qm")
2872 (neg:QI (match_operand:QI
1 "general_operand" "
0")))]
2876 (define_insn "negsf2"
2877 [(set (match_operand:SF
0 "register_operand" "=f")
2878 (neg:SF (match_operand:SF
1 "general_operand" "
0")))]
2882 (define_insn "negdf2"
2883 [(set (match_operand:DF
0 "register_operand" "=f")
2884 (neg:DF (match_operand:DF
1 "general_operand" "
0")))]
2889 [(set (match_operand:DF
0 "register_operand" "=f")
2890 (neg:DF (float_extend:DF (match_operand:SF
1 "general_operand" "
0"))))]
2894 (define_insn "negxf2"
2895 [(set (match_operand:XF
0 "register_operand" "=f")
2896 (neg:XF (match_operand:XF
1 "general_operand" "
0")))]
2901 [(set (match_operand:XF
0 "register_operand" "=f")
2902 (neg:XF (float_extend:XF (match_operand:DF
1 "general_operand" "
0"))))]
2906 ;; Absolute value instructions
2908 (define_insn "abssf2"
2909 [(set (match_operand:SF
0 "register_operand" "=f")
2910 (abs:SF (match_operand:SF
1 "general_operand" "
0")))]
2914 (define_insn "absdf2"
2915 [(set (match_operand:DF
0 "register_operand" "=f")
2916 (abs:DF (match_operand:DF
1 "general_operand" "
0")))]
2921 [(set (match_operand:DF
0 "register_operand" "=f")
2922 (abs:DF (float_extend:DF (match_operand:SF
1 "general_operand" "
0"))))]
2926 (define_insn "absxf2"
2927 [(set (match_operand:XF
0 "register_operand" "=f")
2928 (abs:XF (match_operand:XF
1 "general_operand" "
0")))]
2933 [(set (match_operand:XF
0 "register_operand" "=f")
2934 (abs:XF (float_extend:XF (match_operand:DF
1 "general_operand" "
0"))))]
2938 (define_insn "sqrtsf2"
2939 [(set (match_operand:SF
0 "register_operand" "=f")
2940 (sqrt:SF (match_operand:SF
1 "general_operand" "
0")))]
2941 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2944 (define_insn "sqrtdf2"
2945 [(set (match_operand:DF
0 "register_operand" "=f")
2946 (sqrt:DF (match_operand:DF
1 "general_operand" "
0")))]
2947 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2951 [(set (match_operand:DF
0 "register_operand" "=f")
2952 (sqrt:DF (float_extend:DF
2953 (match_operand:SF
1 "general_operand" "
0"))))]
2954 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2957 (define_insn "sqrtxf2"
2958 [(set (match_operand:XF
0 "register_operand" "=f")
2959 (sqrt:XF (match_operand:XF
1 "general_operand" "
0")))]
2960 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2964 [(set (match_operand:XF
0 "register_operand" "=f")
2965 (sqrt:XF (float_extend:XF
2966 (match_operand:DF
1 "general_operand" "
0"))))]
2967 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2971 [(set (match_operand:XF
0 "register_operand" "=f")
2972 (sqrt:XF (float_extend:XF
2973 (match_operand:SF
1 "general_operand" "
0"))))]
2974 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2977 (define_insn "sindf2"
2978 [(set (match_operand:DF
0 "register_operand" "=f")
2979 (unspec:DF [(match_operand:DF
1 "register_operand" "
0")]
1))]
2980 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2983 (define_insn "sinsf2"
2984 [(set (match_operand:SF
0 "register_operand" "=f")
2985 (unspec:SF [(match_operand:SF
1 "register_operand" "
0")]
1))]
2986 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2990 [(set (match_operand:DF
0 "register_operand" "=f")
2991 (unspec:DF [(float_extend:DF
2992 (match_operand:SF
1 "register_operand" "
0"))]
1))]
2993 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
2996 (define_insn "cosdf2"
2997 [(set (match_operand:DF
0 "register_operand" "=f")
2998 (unspec:DF [(match_operand:DF
1 "register_operand" "
0")]
2))]
2999 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
3002 (define_insn "cossf2"
3003 [(set (match_operand:SF
0 "register_operand" "=f")
3004 (unspec:SF [(match_operand:SF
1 "register_operand" "
0")]
2))]
3005 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
3009 [(set (match_operand:DF
0 "register_operand" "=f")
3010 (unspec:DF [(float_extend:DF
3011 (match_operand:SF
1 "register_operand" "
0"))]
2))]
3012 "TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
3015 ;;- one complement instructions
3017 (define_insn "one_cmplsi2"
3018 [(set (match_operand:SI
0 "general_operand" "=rm")
3019 (not:SI (match_operand:SI
1 "general_operand" "
0")))]
3023 (define_insn "one_cmplhi2"
3024 [(set (match_operand:HI
0 "general_operand" "=rm")
3025 (not:HI (match_operand:HI
1 "general_operand" "
0")))]
3029 (define_insn "one_cmplqi2"
3030 [(set (match_operand:QI
0 "general_operand" "=qm")
3031 (not:QI (match_operand:QI
1 "general_operand" "
0")))]
3035 ;;- arithmetic shift instructions
3037 ;; DImode shifts are implemented using the i386 "shift double" opcode,
3038 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
3039 ;; is variable, then the count is in %cl and the "imm" operand is dropped
3040 ;; from the assembler input.
3042 ;; This instruction shifts the target reg/mem as usual, but instead of
3043 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
3044 ;; is a left shift double, bits are taken from the high order bits of
3045 ;; reg, else if the insn is a shift right double, bits are taken from the
3046 ;; low order bits of reg. So if %eax is "
1234" and %edx is "
5678",
3047 ;; "shldl $
8,%edx,%eax" leaves %edx unchanged and sets %eax to "
2345".
3049 ;; Since sh[lr]d does not change the
`reg' operand, that is done
3050 ;; separately, making all shifts emit pairs of shift double and normal
3051 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
3052 ;; support a 63 bit shift, each shift where the count is in a reg expands
3053 ;; to three pairs. If the overall shift is by N bits, then the first two
3054 ;; pairs shift by N / 2 and the last pair by N & 1.
3056 ;; If the shift count is a constant, we need never emit more than one
3057 ;; shift pair, instead using moves and sign extension for counts greater
3060 (define_expand "ashldi3"
3061 [(set (match_operand:DI 0 "register_operand" "")
3062 (ashift:DI (match_operand:DI 1 "register_operand" "")
3063 (match_operand:QI 2 "nonmemory_operand" "")))]
3067 if (GET_CODE (operands[2]) != CONST_INT
3068 || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
3070 operands[2] = copy_to_mode_reg (QImode, operands[2]);
3071 emit_insn (gen_ashldi3_non_const_int (operands[0], operands[1],
3075 emit_insn (gen_ashldi3_const_int (operands[0], operands[1], operands[2]));
3080 (define_insn "ashldi3_const_int"
3081 [(set (match_operand:DI 0 "register_operand" "=&r")
3082 (ashift:DI (match_operand:DI 1 "register_operand" "0")
3083 (match_operand:QI 2 "const_int_operand" "J")))]
3087 rtx xops[4], low[1], high[1];
3091 split_di (operands, 1, low, high);
3092 xops[0] = operands[2];
3093 xops[1] = const1_rtx;
3097 if (INTVAL (xops[0]) > 31)
3099 output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */
3100 output_asm_insn (AS2 (xor%L2,%2,%2), xops);
3102 if (INTVAL (xops[0]) > 32)
3104 xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
3105 output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */
3110 output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops);
3111 output_asm_insn (AS2 (sal%L2,%0,%2), xops);
3116 (define_insn "ashldi3_non_const_int"
3117 [(set (match_operand:DI 0 "register_operand" "=&r")
3118 (ashift:DI (match_operand:DI 1 "register_operand" "0")
3119 (match_operand:QI 2 "register_operand" "c")))
3120 (clobber (match_dup 2))]
3124 rtx xops[4], low[1], high[1];
3128 split_di (operands, 1, low, high);
3129 xops[0] = operands[2];
3130 xops[1] = const1_rtx;
3134 output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */
3136 output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops);
3137 output_asm_insn (AS2 (sal%L2,%0,%2), xops);
3138 output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops);
3139 output_asm_insn (AS2 (sal%L2,%0,%2), xops);
3141 xops[1] = GEN_INT (7); /* shift count & 1 */
3143 output_asm_insn (AS2 (shr%B0,%1,%0), xops);
3145 output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops);
3146 output_asm_insn (AS2 (sal%L2,%0,%2), xops);
3151 ;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg"
3152 ;; On i486, movl/sall appears slightly faster than leal, but the leal
3153 ;; is smaller - use leal for now unless the shift count is 1.
3155 (define_insn "ashlsi3"
3156 [(set (match_operand:SI 0 "general_operand" "=r,rm")
3157 (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
3158 (match_operand:SI 2 "nonmemory_operand" "M,cI")))]
3162 if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1]))
3164 if (TARGET_486 && INTVAL (operands[2]) == 1)
3166 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
3167 return AS2 (add%L0,%1,%0);
3173 if (operands[1] == stack_pointer_rtx)
3175 output_asm_insn (AS2 (mov%L0,%1,%0), operands);
3176 operands[1] = operands[0];
3178 operands[1] = gen_rtx (MULT, SImode, operands[1],
3179 GEN_INT (1 << INTVAL (operands[2])));
3180 return AS2 (lea%L0,%a1,%0);
3184 if (REG_P (operands[2]))
3185 return AS2 (sal%L0,%b2,%0);
3187 if (REG_P (operands[0]) && operands[2] == const1_rtx)
3188 return AS2 (add%L0,%0,%0);
3190 return AS2 (sal%L0,%2,%0);
3193 (define_insn "ashlhi3"
3194 [(set (match_operand:HI 0 "general_operand" "=rm")
3195 (ashift:HI (match_operand:HI 1 "general_operand" "0")
3196 (match_operand:HI 2 "nonmemory_operand" "cI")))]
3200 if (REG_P (operands[2]))
3201 return AS2 (sal%W0,%b2,%0);
3203 if (REG_P (operands[0]) && operands[2] == const1_rtx)
3204 return AS2 (add%W0,%0,%0);
3206 return AS2 (sal%W0,%2,%0);
3209 (define_insn "ashlqi3"
3210 [(set (match_operand:QI 0 "general_operand" "=qm")
3211 (ashift:QI (match_operand:QI 1 "general_operand" "0")
3212 (match_operand:QI 2 "nonmemory_operand" "cI")))]
3216 if (REG_P (operands[2]))
3217 return AS2 (sal%B0,%b2,%0);
3219 if (REG_P (operands[0]) && operands[2] == const1_rtx)
3220 return AS2 (add%B0,%0,%0);
3222 return AS2 (sal%B0,%2,%0);
3225 ;; See comment above `ashldi3' about how this works.
3227 (define_expand "ashrdi3"
3228 [(set (match_operand:DI
0 "register_operand" "")
3229 (ashiftrt:DI (match_operand:DI
1 "register_operand" "")
3230 (match_operand:QI
2 "nonmemory_operand" "")))]
3234 if (GET_CODE (operands[
2]) != CONST_INT
3235 || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[
2]), 'J'))
3237 operands[
2] = copy_to_mode_reg (QImode, operands[
2]);
3238 emit_insn (gen_ashrdi3_non_const_int (operands[
0], operands[
1],
3242 emit_insn (gen_ashrdi3_const_int (operands[
0], operands[
1], operands[
2]));
3247 (define_insn "ashrdi3_const_int"
3248 [(set (match_operand:DI
0 "register_operand" "=&r")
3249 (ashiftrt:DI (match_operand:DI
1 "register_operand" "
0")
3250 (match_operand:QI
2 "const_int_operand" "J")))]
3254 rtx xops[
4], low[
1], high[
1];
3258 split_di (operands,
1, low, high);
3259 xops[
0] = operands[
2];
3260 xops[
1] = const1_rtx;
3264 if (INTVAL (xops[
0]) >
31)
3266 xops[
1] = GEN_INT (
31);
3267 output_asm_insn (AS2 (mov%L2,%
3,%
2), xops);
3268 output_asm_insn (AS2 (sar%L3,%
1,%
3), xops); /* shift by
32 */
3270 if (INTVAL (xops[
0]) >
32)
3272 xops[
0] = GEN_INT (INTVAL (xops[
0]) -
32);
3273 output_asm_insn (AS2 (sar%L2,%
0,%
2), xops); /* Remaining shift */
3278 output_asm_insn (AS3 (shrd%L2,%
0,%
3,%
2), xops);
3279 output_asm_insn (AS2 (sar%L3,%
0,%
3), xops);
3285 (define_insn "ashrdi3_non_const_int"
3286 [(set (match_operand:DI
0 "register_operand" "=&r")
3287 (ashiftrt:DI (match_operand:DI
1 "register_operand" "
0")
3288 (match_operand:QI
2 "register_operand" "c")))
3289 (clobber (match_dup
2))]
3293 rtx xops[
4], low[
1], high[
1];
3297 split_di (operands,
1, low, high);
3298 xops[
0] = operands[
2];
3299 xops[
1] = const1_rtx;
3303 output_asm_insn (AS2 (ror%B0,%
1,%
0), xops); /* shift count /
2 */
3305 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%
0,%
3,%
2), xops);
3306 output_asm_insn (AS2 (sar%L3,%
0,%
3), xops);
3307 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%
0,%
3,%
2), xops);
3308 output_asm_insn (AS2 (sar%L3,%
0,%
3), xops);
3310 xops[
1] = GEN_INT (
7); /* shift count &
1 */
3312 output_asm_insn (AS2 (shr%B0,%
1,%
0), xops);
3314 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%
0,%
3,%
2), xops);
3315 output_asm_insn (AS2 (sar%L3,%
0,%
3), xops);
3320 (define_insn "ashrsi3"
3321 [(set (match_operand:SI
0 "general_operand" "=rm")
3322 (ashiftrt:SI (match_operand:SI
1 "general_operand" "
0")
3323 (match_operand:SI
2 "nonmemory_operand" "cI")))]
3327 if (REG_P (operands[
2]))
3328 return AS2 (sar%L0,%b2,%
0);
3330 return AS2 (sar%L0,%
2,%
0);
3333 (define_insn "ashrhi3"
3334 [(set (match_operand:HI
0 "general_operand" "=rm")
3335 (ashiftrt:HI (match_operand:HI
1 "general_operand" "
0")
3336 (match_operand:HI
2 "nonmemory_operand" "cI")))]
3340 if (REG_P (operands[
2]))
3341 return AS2 (sar%W0,%b2,%
0);
3343 return AS2 (sar%W0,%
2,%
0);
3346 (define_insn "ashrqi3"
3347 [(set (match_operand:QI
0 "general_operand" "=qm")
3348 (ashiftrt:QI (match_operand:QI
1 "general_operand" "
0")
3349 (match_operand:QI
2 "nonmemory_operand" "cI")))]
3353 if (REG_P (operands[
2]))
3354 return AS2 (sar%B0,%b2,%
0);
3356 return AS2 (sar%B0,%
2,%
0);
3359 ;;- logical shift instructions
3361 ;; See comment above
`ashldi3' about how this works.
3363 (define_expand "lshrdi3"
3364 [(set (match_operand:DI 0 "register_operand" "")
3365 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3366 (match_operand:QI 2 "nonmemory_operand" "")))]
3370 if (GET_CODE (operands[2]) != CONST_INT
3371 || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
3373 operands[2] = copy_to_mode_reg (QImode, operands[2]);
3374 emit_insn (gen_lshrdi3_non_const_int (operands[0], operands[1],
3378 emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2]));
3383 (define_insn "lshrdi3_const_int"
3384 [(set (match_operand:DI 0 "register_operand" "=&r")
3385 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
3386 (match_operand:QI 2 "const_int_operand" "J")))]
3390 rtx xops[4], low[1], high[1];
3394 split_di (operands, 1, low, high);
3395 xops[0] = operands[2];
3396 xops[1] = const1_rtx;
3400 if (INTVAL (xops[0]) > 31)
3402 output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */
3403 output_asm_insn (AS2 (xor%L3,%3,%3), xops);
3405 if (INTVAL (xops[0]) > 32)
3407 xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
3408 output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */
3413 output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops);
3414 output_asm_insn (AS2 (shr%L3,%0,%3), xops);
3420 (define_insn "lshrdi3_non_const_int"
3421 [(set (match_operand:DI 0 "register_operand" "=&r")
3422 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
3423 (match_operand:QI 2 "register_operand" "c")))
3424 (clobber (match_dup 2))]
3428 rtx xops[4], low[1], high[1];
3432 split_di (operands, 1, low, high);
3433 xops[0] = operands[2];
3434 xops[1] = const1_rtx;
3438 output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */
3440 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
3441 output_asm_insn (AS2 (shr%L3,%0,%3), xops);
3442 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
3443 output_asm_insn (AS2 (shr%L3,%0,%3), xops);
3445 xops[1] = GEN_INT (7); /* shift count & 1 */
3447 output_asm_insn (AS2 (shr%B0,%1,%0), xops);
3449 output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
3450 output_asm_insn (AS2 (shr%L3,%0,%3), xops);
3455 (define_insn "lshrsi3"
3456 [(set (match_operand:SI 0 "general_operand" "=rm")
3457 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
3458 (match_operand:SI 2 "nonmemory_operand" "cI")))]
3462 if (REG_P (operands[2]))
3463 return AS2 (shr%L0,%b2,%0);
3465 return AS2 (shr%L0,%2,%1);
3468 (define_insn "lshrhi3"
3469 [(set (match_operand:HI 0 "general_operand" "=rm")
3470 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
3471 (match_operand:HI 2 "nonmemory_operand" "cI")))]
3475 if (REG_P (operands[2]))
3476 return AS2 (shr%W0,%b2,%0);
3478 return AS2 (shr%W0,%2,%0);
3481 (define_insn "lshrqi3"
3482 [(set (match_operand:QI 0 "general_operand" "=qm")
3483 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
3484 (match_operand:QI 2 "nonmemory_operand" "cI")))]
3488 if (REG_P (operands[2]))
3489 return AS2 (shr%B0,%b2,%0);
3491 return AS2 (shr%B0,%2,%0);
3494 ;;- rotate instructions
3496 (define_insn "rotlsi3"
3497 [(set (match_operand:SI 0 "general_operand" "=rm")
3498 (rotate:SI (match_operand:SI 1 "general_operand" "0")
3499 (match_operand:SI 2 "nonmemory_operand" "cI")))]
3503 if (REG_P (operands[2]))
3504 return AS2 (rol%L0,%b2,%0);
3506 return AS2 (rol%L0,%2,%0);
3509 (define_insn "rotlhi3"
3510 [(set (match_operand:HI 0 "general_operand" "=rm")
3511 (rotate:HI (match_operand:HI 1 "general_operand" "0")
3512 (match_operand:HI 2 "nonmemory_operand" "cI")))]
3516 if (REG_P (operands[2]))
3517 return AS2 (rol%W0,%b2,%0);
3519 return AS2 (rol%W0,%2,%0);
3522 (define_insn "rotlqi3"
3523 [(set (match_operand:QI 0 "general_operand" "=qm")
3524 (rotate:QI (match_operand:QI 1 "general_operand" "0")
3525 (match_operand:QI 2 "nonmemory_operand" "cI")))]
3529 if (REG_P (operands[2]))
3530 return AS2 (rol%B0,%b2,%0);
3532 return AS2 (rol%B0,%2,%0);
3535 (define_insn "rotrsi3"
3536 [(set (match_operand:SI 0 "general_operand" "=rm")
3537 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
3538 (match_operand:SI 2 "nonmemory_operand" "cI")))]
3542 if (REG_P (operands[2]))
3543 return AS2 (ror%L0,%b2,%0);
3545 return AS2 (ror%L0,%2,%0);
3548 (define_insn "rotrhi3"
3549 [(set (match_operand:HI 0 "general_operand" "=rm")
3550 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
3551 (match_operand:HI 2 "nonmemory_operand" "cI")))]
3555 if (REG_P (operands[2]))
3556 return AS2 (ror%W0,%b2,%0);
3558 return AS2 (ror%W0,%2,%0);
3561 (define_insn "rotrqi3"
3562 [(set (match_operand:QI 0 "general_operand" "=qm")
3563 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
3564 (match_operand:QI 2 "nonmemory_operand" "cI")))]
3568 if (REG_P (operands[2]))
3569 return AS2 (ror%B0,%b2,%0);
3571 return AS2 (ror%B0,%2,%0);
3575 ;; This usually looses. But try a define_expand to recognize a few case
3576 ;; we can do efficiently, such as accessing the "high" QImode registers,
3577 ;; %ah, %bh, %ch, %dh.
3579 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r")
3580 (match_operand:SI 1 "general_operand" "i")
3581 (match_operand:SI 2 "general_operand" "i"))
3582 (match_operand:SI 3 "general_operand" "ri"))]
3586 if (INTVAL (operands[1]) + INTVAL (operands[2]) > GET_MODE_BITSIZE (SImode))
3588 if (GET_CODE (operands[3]) == CONST_INT)
3590 unsigned int mask = (1 << INTVAL (operands[1])) - 1;
3591 operands[1] = GEN_INT (~(mask << INTVAL (operands[2])));
3592 output_asm_insn (AS2 (and%L0,%1,%0), operands);
3593 operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2]));
3594 output_asm_insn (AS2 (or%L0,%3,%0), operands);
3598 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
3599 if (INTVAL (operands[2]))
3600 output_asm_insn (AS2 (ror%L0,%2,%0), operands);
3601 output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands);
3602 operands[2] = GEN_INT (BITS_PER_WORD
3603 - INTVAL (operands[1]) - INTVAL (operands[2]));
3604 if (INTVAL (operands[2]))
3605 output_asm_insn (AS2 (ror%L0,%2,%0), operands);
3611 ;; ??? There are problems with the mode of operand[3]. The point of this
3612 ;; is to represent an HImode move to a "high byte" register.
3614 (define_expand "insv"
3615 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
3616 (match_operand:SI 1 "immediate_operand" "")
3617 (match_operand:SI 2 "immediate_operand" ""))
3618 (match_operand:QI 3 "general_operand" "ri"))]
3622 if (GET_CODE (operands[1]) != CONST_INT
3623 || GET_CODE (operands[2]) != CONST_INT)
3626 if (! (INTVAL (operands[1]) == 8
3627 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 0))
3628 && ! INTVAL (operands[1]) == 1)
3632 ;; ??? Are these constraints right?
3634 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+&qo")
3637 (match_operand:QI 1 "general_operand" "qn"))]
3641 if (REG_P (operands[0]))
3642 return AS2 (mov%B0,%1,%h0);
3644 operands[0] = adj_offsettable_operand (operands[0], 1);
3645 return AS2 (mov%B0,%1,%0);
3649 ;; On i386, the register count for a bit operation is *not* truncated,
3650 ;; so SHIFT_COUNT_TRUNCATED must not be defined.
3652 ;; On i486, the shift & or/and code is faster than bts or btr. If
3653 ;; operands[0] is a MEM, the bt[sr] is half as fast as the normal code.
3655 ;; On i386, bts is a little faster if operands[0] is a reg, and a
3656 ;; little slower if operands[0] is a MEM, than the shift & or/and code.
3657 ;; Use bts & btr, since they reload better.
3659 ;; General bit set and clear.
3661 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+rm")
3663 (match_operand:SI 2 "general_operand" "r"))
3664 (match_operand:SI 3 "const_int_operand" "n"))]
3665 "! TARGET_486 && GET_CODE (operands[2]) != CONST_INT"
3670 if (INTVAL (operands[3]) == 1)
3671 return AS2 (bts%L0,%2,%0);
3673 return AS2 (btr%L0,%2,%0);
3676 ;; Bit complement. See comments on previous pattern.
3677 ;; ??? Is this really worthwhile?
3679 [(set (match_operand:SI 0 "general_operand" "=rm")
3680 (xor:SI (ashift:SI (const_int 1)
3681 (match_operand:SI 1 "general_operand" "r"))
3682 (match_operand:SI 2 "general_operand" "0")))]
3683 "! TARGET_486 && GET_CODE (operands[1]) != CONST_INT"
3688 return AS2 (btc%L0,%1,%0);
3692 [(set (match_operand:SI 0 "general_operand" "=rm")
3693 (xor:SI (match_operand:SI 1 "general_operand" "0")
3694 (ashift:SI (const_int 1)
3695 (match_operand:SI 2 "general_operand" "r"))))]
3696 "! TARGET_486 && GET_CODE (operands[2]) != CONST_INT"
3701 return AS2 (btc%L0,%2,%0);
3704 ;; Recognizers for bit-test instructions.
3706 ;; The bt opcode allows a MEM in operands[0]. But on both i386 and
3707 ;; i486, it is faster to copy a MEM to REG and then use bt, than to use
3708 ;; bt on the MEM directly.
3710 ;; ??? The first argument of a zero_extract must not be reloaded, so
3711 ;; don't allow a MEM in the operand predicate without allowing it in the
3715 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
3717 (match_operand:SI 1 "general_operand" "r")))]
3718 "GET_CODE (operands[1]) != CONST_INT"
3721 cc_status.flags |= CC_Z_IN_NOT_C;
3722 return AS2 (bt%L0,%1,%0);
3726 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
3727 (match_operand:SI 1 "const_int_operand" "n")
3728 (match_operand:SI 2 "const_int_operand" "n")))]
3734 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
3735 operands[1] = GEN_INT (mask);
3737 if (QI_REG_P (operands[0]))
3739 if ((mask & ~0xff) == 0)
3741 cc_status.flags |= CC_NOT_NEGATIVE;
3742 return AS2 (test%B0,%1,%b0);
3745 if ((mask & ~0xff00) == 0)
3747 cc_status.flags |= CC_NOT_NEGATIVE;
3748 operands[1] = GEN_INT (mask >> 8);
3749 return AS2 (test%B0,%1,%h0);
3753 return AS2 (test%L0,%1,%0);
3756 ;; ??? All bets are off if operand 0 is a volatile MEM reference.
3757 ;; The CPU may access unspecified bytes around the actual target byte.
3760 [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "rm")
3761 (match_operand:SI 1 "const_int_operand" "n")
3762 (match_operand:SI 2 "const_int_operand" "n")))]
3763 "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])"
3768 mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
3769 operands[1] = GEN_INT (mask);
3771 if (! REG_P (operands[0]) || QI_REG_P (operands[0]))
3773 if ((mask & ~0xff) == 0)
3775 cc_status.flags |= CC_NOT_NEGATIVE;
3776 return AS2 (test%B0,%1,%b0);
3779 if ((mask & ~0xff00) == 0)
3781 cc_status.flags |= CC_NOT_NEGATIVE;
3782 operands[1] = GEN_INT (mask >> 8);
3784 if (QI_REG_P (operands[0]))
3785 return AS2 (test%B0,%1,%h0);
3788 operands[0] = adj_offsettable_operand (operands[0], 1);
3789 return AS2 (test%B0,%1,%b0);
3793 if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0)
3795 cc_status.flags |= CC_NOT_NEGATIVE;
3796 operands[1] = GEN_INT (mask >> 16);
3797 operands[0] = adj_offsettable_operand (operands[0], 2);
3798 return AS2 (test%B0,%1,%b0);
3801 if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0)
3803 cc_status.flags |= CC_NOT_NEGATIVE;
3804 operands[1] = GEN_INT (mask >> 24);
3805 operands[0] = adj_offsettable_operand (operands[0], 3);
3806 return AS2 (test%B0,%1,%b0);
3810 if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
3811 return AS2 (test%L0,%1,%0);
3813 return AS2 (test%L1,%0,%1);
3816 ;; Store-flag instructions.
3818 ;; For all sCOND expanders, also expand the compare or test insn that
3819 ;; generates cc0. Generate an equality comparison if `seq' or
`sne'.
3821 ;; The 386 sCOND opcodes can write to memory. But a gcc sCOND insn may
3822 ;; not have any input reloads. A MEM write might need an input reload
3823 ;; for the address of the MEM. So don't allow MEM as the SET_DEST.
3825 (define_expand "seq"
3827 (set (match_operand:QI 0 "register_operand" "")
3828 (eq:QI (cc0) (const_int 0)))]
3833 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
3834 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
3836 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
3840 [(set (match_operand:QI 0 "register_operand" "=q")
3841 (eq:QI (cc0) (const_int 0)))]
3845 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3846 return AS1 (setnb,%0);
3848 return AS1 (sete,%0);
3851 (define_expand "sne"
3853 (set (match_operand:QI 0 "register_operand" "")
3854 (ne:QI (cc0) (const_int 0)))]
3859 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
3860 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
3862 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
3866 [(set (match_operand:QI 0 "register_operand" "=q")
3867 (ne:QI (cc0) (const_int 0)))]
3871 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
3872 return AS1 (setb,%0);
3874 return AS1 (setne,%0);
3878 (define_expand "sgt"
3880 (set (match_operand:QI 0 "register_operand" "")
3881 (gt:QI (cc0) (const_int 0)))]
3883 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
3886 [(set (match_operand:QI 0 "register_operand" "=q")
3887 (gt:QI (cc0) (const_int 0)))]
3891 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
3892 return AS1 (sete,%0);
3894 OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR);
3897 (define_expand "sgtu"
3899 (set (match_operand:QI 0 "register_operand" "")
3900 (gtu:QI (cc0) (const_int 0)))]
3902 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
3905 [(set (match_operand:QI 0 "register_operand" "=q")
3906 (gtu:QI (cc0) (const_int 0)))]
3908 "* return \"seta %0\"; ")
3910 (define_expand "slt"
3912 (set (match_operand:QI 0 "register_operand" "")
3913 (lt:QI (cc0) (const_int 0)))]
3915 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
3918 [(set (match_operand:QI 0 "register_operand" "=q")
3919 (lt:QI (cc0) (const_int 0)))]
3923 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
3924 return AS1 (sete,%0);
3926 OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\");
3929 (define_expand "sltu"
3931 (set (match_operand:QI 0 "register_operand" "")
3932 (ltu:QI (cc0) (const_int 0)))]
3934 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
3937 [(set (match_operand:QI 0 "register_operand" "=q")
3938 (ltu:QI (cc0) (const_int 0)))]
3940 "* return \"setb %0\"; ")
3942 (define_expand "sge"
3944 (set (match_operand:QI 0 "register_operand" "")
3945 (ge:QI (cc0) (const_int 0)))]
3947 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
3950 [(set (match_operand:QI 0 "register_operand" "=q")
3951 (ge:QI (cc0) (const_int 0)))]
3955 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
3956 return AS1 (sete,%0);
3958 OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\");
3961 (define_expand "sgeu"
3963 (set (match_operand:QI 0 "register_operand" "")
3964 (geu:QI (cc0) (const_int 0)))]
3966 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
3969 [(set (match_operand:QI 0 "register_operand" "=q")
3970 (geu:QI (cc0) (const_int 0)))]
3972 "* return \"setae %0\"; ")
3974 (define_expand "sle"
3976 (set (match_operand:QI 0 "register_operand" "")
3977 (le:QI (cc0) (const_int 0)))]
3979 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
3982 [(set (match_operand:QI 0 "register_operand" "=q")
3983 (le:QI (cc0) (const_int 0)))]
3987 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
3988 return AS1 (setb,%0);
3990 OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR);
3993 (define_expand "sleu"
3995 (set (match_operand:QI 0 "register_operand" "")
3996 (leu:QI (cc0) (const_int 0)))]
3998 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4001 [(set (match_operand:QI 0 "register_operand" "=q")
4002 (leu:QI (cc0) (const_int 0)))]
4004 "* return \"setbe %0\"; ")
4006 ;; Basic conditional jump instructions.
4007 ;; We ignore the overflow flag for signed branch instructions.
4009 ;; For all bCOND expanders, also expand the compare or test insn that
4010 ;; generates cc0. Generate an equality comparison if `beq' or
`bne'.
4012 (define_expand "beq"
4015 (if_then_else (eq (cc0)
4017 (label_ref (match_operand 0 "" ""))
4023 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
4024 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
4026 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
4031 (if_then_else (eq (cc0)
4033 (label_ref (match_operand 0 "" ""))
4038 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
4044 (define_expand "bne"
4047 (if_then_else (ne (cc0)
4049 (label_ref (match_operand 0 "" ""))
4055 && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT)
4056 operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1);
4058 operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);
4063 (if_then_else (ne (cc0)
4065 (label_ref (match_operand 0 "" ""))
4070 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
4076 (define_expand "bgt"
4079 (if_then_else (gt (cc0)
4081 (label_ref (match_operand 0 "" ""))
4084 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4088 (if_then_else (gt (cc0)
4090 (label_ref (match_operand 0 "" ""))
4095 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4096 return AS1 (je,%l0);
4098 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
4101 (define_expand "bgtu"
4104 (if_then_else (gtu (cc0)
4106 (label_ref (match_operand 0 "" ""))
4109 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4113 (if_then_else (gtu (cc0)
4115 (label_ref (match_operand 0 "" ""))
4120 (define_expand "blt"
4123 (if_then_else (lt (cc0)
4125 (label_ref (match_operand 0 "" ""))
4128 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4132 (if_then_else (lt (cc0)
4134 (label_ref (match_operand 0 "" ""))
4139 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4140 return AS1 (je,%l0);
4142 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\");
4145 (define_expand "bltu"
4148 (if_then_else (ltu (cc0)
4150 (label_ref (match_operand 0 "" ""))
4153 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4157 (if_then_else (ltu (cc0)
4159 (label_ref (match_operand 0 "" ""))
4164 (define_expand "bge"
4167 (if_then_else (ge (cc0)
4169 (label_ref (match_operand 0 "" ""))
4172 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4176 (if_then_else (ge (cc0)
4178 (label_ref (match_operand 0 "" ""))
4183 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4184 return AS1 (je,%l0);
4186 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\");
4189 (define_expand "bgeu"
4192 (if_then_else (geu (cc0)
4194 (label_ref (match_operand 0 "" ""))
4197 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4201 (if_then_else (geu (cc0)
4203 (label_ref (match_operand 0 "" ""))
4208 (define_expand "ble"
4211 (if_then_else (le (cc0)
4213 (label_ref (match_operand 0 "" ""))
4216 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4220 (if_then_else (le (cc0)
4222 (label_ref (match_operand 0 "" ""))
4227 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4228 return AS1 (jb,%l0);
4230 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
4233 (define_expand "bleu"
4236 (if_then_else (leu (cc0)
4238 (label_ref (match_operand 0 "" ""))
4241 "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);")
4245 (if_then_else (leu (cc0)
4247 (label_ref (match_operand 0 "" ""))
4252 ;; Negated conditional jump instructions.
4256 (if_then_else (eq (cc0)
4259 (label_ref (match_operand 0 "" ""))))]
4263 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
4271 (if_then_else (ne (cc0)
4274 (label_ref (match_operand 0 "" ""))))]
4278 if (cc_prev_status.flags & CC_Z_IN_NOT_C)
4286 (if_then_else (gt (cc0)
4289 (label_ref (match_operand 0 "" ""))))]
4293 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4294 return AS1 (jne,%l0);
4296 OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
4301 (if_then_else (gtu (cc0)
4304 (label_ref (match_operand 0 "" ""))))]
4310 (if_then_else (lt (cc0)
4313 (label_ref (match_operand 0 "" ""))))]
4317 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4318 return AS1 (jne,%l0);
4320 OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\");
4325 (if_then_else (ltu (cc0)
4328 (label_ref (match_operand 0 "" ""))))]
4334 (if_then_else (ge (cc0)
4337 (label_ref (match_operand 0 "" ""))))]
4341 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4342 return AS1 (jne,%l0);
4344 OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\");
4349 (if_then_else (geu (cc0)
4352 (label_ref (match_operand 0 "" ""))))]
4358 (if_then_else (le (cc0)
4361 (label_ref (match_operand 0 "" ""))))]
4365 if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
4366 return AS1 (jae,%l0);
4368 OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
4373 (if_then_else (leu (cc0)
4376 (label_ref (match_operand 0 "" ""))))]
4380 ;; Unconditional and other jump instructions
4384 (label_ref (match_operand 0 "" "")))]
4388 (define_insn "indirect_jump"
4389 [(set (pc) (match_operand:SI 0 "general_operand" "rm"))]
4395 return AS1 (jmp,%*%0);
4398 ;; Implement switch statements when generating PIC code. Switches are
4399 ;; implemented by `tablejump' when not using -fpic.
4401 ;; Emit code here to do the range checking and make the index zero based.
4403 (define_expand "casesi"
4405 (minus:SI (match_operand:SI
0 "general_operand" "")
4406 (match_operand:SI
1 "general_operand" "")))
4408 (compare:CC (match_dup
5)
4409 (match_operand:SI
2 "general_operand" "")))
4411 (if_then_else (gtu (cc0)
4413 (label_ref (match_operand
4 "" ""))
4417 (minus:SI (reg:SI
3)
4418 (mem:SI (plus:SI (mult:SI (match_dup
5)
4420 (label_ref (match_operand
3 "" ""))))))
4421 (clobber (match_scratch:SI
6 ""))])]
4425 operands[
5] = gen_reg_rtx (SImode);
4426 current_function_uses_pic_offset_table =
1;
4429 ;; Implement a casesi insn.
4431 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
4434 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
4436 ;;
1. An expression involving an external reference may only use the
4437 ;; addition operator, and only with an assembly-time constant.
4438 ;; The example above satisfies this because ".-.L2" is a constant.
4440 ;;
2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
4441 ;; given the value of "GOT - .", where GOT is the actual address of
4442 ;; the Global Offset Table. Therefore, the .long above actually
4443 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
4444 ;; expression "GOT - .L2" by itself would generate an error from as(
1).
4446 ;; The pattern below emits code that looks like this:
4449 ;; subl TABLE@GOTOFF(%ebx,index,
4),reg
4452 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
4453 ;; the addr_diff_vec is known to be part of this module.
4455 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
4456 ;; evaluates to just ".L2".
4460 (minus:SI (reg:SI
3)
4462 (mult:SI (match_operand:SI
0 "register_operand" "r")
4464 (label_ref (match_operand
1 "" ""))))))
4465 (clobber (match_scratch:SI
2 "=&r"))]
4471 xops[
0] = operands[
0];
4472 xops[
1] = operands[
1];
4473 xops[
2] = operands[
2];
4474 xops[
3] = pic_offset_table_rtx;
4476 output_asm_insn (AS2 (mov%L2,%
3,%
2), xops);
4477 output_asm_insn (
\"sub%L2 %l1@GOTOFF(%
3,%
0,
4),%
2\", xops);
4478 output_asm_insn (AS1 (jmp,%*%
2), xops);
4479 ASM_OUTPUT_ALIGN_CODE (asm_out_file);
4483 (define_insn "tablejump"
4484 [(set (pc) (match_operand:SI
0 "general_operand" "rm"))
4485 (use (label_ref (match_operand
1 "" "")))]
4491 return AS1 (jmp,%*%
0);
4496 ;; If generating PIC code, the predicate indirect_operand will fail
4497 ;; for operands[
0] containing symbolic references on all of the named
4498 ;; call* patterns. Each named pattern is followed by an unnamed pattern
4499 ;; that matches any call to a symbolic CONST (ie, a symbol_ref). The
4500 ;; unnamed patterns are only used while generating PIC code, because
4501 ;; otherwise the named patterns match.
4503 ;; Call subroutine returning no value.
4505 (define_expand "call_pop"
4506 [(parallel [(call (match_operand:QI
0 "indirect_operand" "")
4507 (match_operand:SI
1 "general_operand" ""))
4510 (match_operand:SI
3 "immediate_operand" "")))])]
4517 current_function_uses_pic_offset_table =
1;
4519 /* With half-pic, force the address into a register. */
4520 addr = XEXP (operands[
0],
0);
4521 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
4522 XEXP (operands[
0],
0) = force_reg (Pmode, addr);
4524 if (! expander_call_insn_operand (operands[
0], QImode))
4526 = change_address (operands[
0], VOIDmode,
4527 copy_to_mode_reg (Pmode, XEXP (operands[
0],
0)));
4531 [(call (match_operand:QI
0 "call_insn_operand" "m")
4532 (match_operand:SI
1 "general_operand" "g"))
4533 (set (reg:SI
7) (plus:SI (reg:SI
7)
4534 (match_operand:SI
3 "immediate_operand" "i")))]
4538 if (GET_CODE (operands[
0]) == MEM
4539 && ! CONSTANT_ADDRESS_P (XEXP (operands[
0],
0)))
4541 operands[
0] = XEXP (operands[
0],
0);
4542 return AS1 (call,%*%
0);
4545 return AS1 (call,%P0);
4549 [(call (mem:QI (match_operand:SI
0 "symbolic_operand" ""))
4550 (match_operand:SI
1 "general_operand" "g"))
4551 (set (reg:SI
7) (plus:SI (reg:SI
7)
4552 (match_operand:SI
3 "immediate_operand" "i")))]
4556 (define_expand "call"
4557 [(call (match_operand:QI
0 "indirect_operand" "")
4558 (match_operand:SI
1 "general_operand" ""))]
4559 ;; Operand
1 not used on the i386.
4566 current_function_uses_pic_offset_table =
1;
4568 /* With half-pic, force the address into a register. */
4569 addr = XEXP (operands[
0],
0);
4570 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
4571 XEXP (operands[
0],
0) = force_reg (Pmode, addr);
4573 if (! expander_call_insn_operand (operands[
0], QImode))
4575 = change_address (operands[
0], VOIDmode,
4576 copy_to_mode_reg (Pmode, XEXP (operands[
0],
0)));
4580 [(call (match_operand:QI
0 "call_insn_operand" "m")
4581 (match_operand:SI
1 "general_operand" "g"))]
4582 ;; Operand
1 not used on the i386.
4586 if (GET_CODE (operands[
0]) == MEM
4587 && ! CONSTANT_ADDRESS_P (XEXP (operands[
0],
0)))
4589 operands[
0] = XEXP (operands[
0],
0);
4590 return AS1 (call,%*%
0);
4593 return AS1 (call,%P0);
4597 [(call (mem:QI (match_operand:SI
0 "symbolic_operand" ""))
4598 (match_operand:SI
1 "general_operand" "g"))]
4599 ;; Operand
1 not used on the i386.
4603 ;; Call subroutine, returning value in operand
0
4604 ;; (which must be a hard register).
4606 (define_expand "call_value_pop"
4607 [(parallel [(set (match_operand
0 "" "")
4608 (call (match_operand:QI
1 "indirect_operand" "")
4609 (match_operand:SI
2 "general_operand" "")))
4612 (match_operand:SI
4 "immediate_operand" "")))])]
4619 current_function_uses_pic_offset_table =
1;
4621 /* With half-pic, force the address into a register. */
4622 addr = XEXP (operands[
1],
0);
4623 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
4624 XEXP (operands[
1],
0) = force_reg (Pmode, addr);
4626 if (! expander_call_insn_operand (operands[
1], QImode))
4628 = change_address (operands[
1], VOIDmode,
4629 copy_to_mode_reg (Pmode, XEXP (operands[
1],
0)));
4633 [(set (match_operand
0 "" "=rf")
4634 (call (match_operand:QI
1 "call_insn_operand" "m")
4635 (match_operand:SI
2 "general_operand" "g")))
4636 (set (reg:SI
7) (plus:SI (reg:SI
7)
4637 (match_operand:SI
4 "immediate_operand" "i")))]
4641 if (GET_CODE (operands[
1]) == MEM
4642 && ! CONSTANT_ADDRESS_P (XEXP (operands[
1],
0)))
4644 operands[
1] = XEXP (operands[
1],
0);
4645 output_asm_insn (AS1 (call,%*%
1), operands);
4648 output_asm_insn (AS1 (call,%P1), operands);
4654 [(set (match_operand
0 "" "=rf")
4655 (call (mem:QI (match_operand:SI
1 "symbolic_operand" ""))
4656 (match_operand:SI
2 "general_operand" "g")))
4657 (set (reg:SI
7) (plus:SI (reg:SI
7)
4658 (match_operand:SI
4 "immediate_operand" "i")))]
4662 (define_expand "call_value"
4663 [(set (match_operand
0 "" "")
4664 (call (match_operand:QI
1 "indirect_operand" "")
4665 (match_operand:SI
2 "general_operand" "")))]
4666 ;; Operand
2 not used on the i386.
4673 current_function_uses_pic_offset_table =
1;
4675 /* With half-pic, force the address into a register. */
4676 addr = XEXP (operands[
1],
0);
4677 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
4678 XEXP (operands[
1],
0) = force_reg (Pmode, addr);
4680 if (! expander_call_insn_operand (operands[
1], QImode))
4682 = change_address (operands[
1], VOIDmode,
4683 copy_to_mode_reg (Pmode, XEXP (operands[
1],
0)));
4687 [(set (match_operand
0 "" "=rf")
4688 (call (match_operand:QI
1 "call_insn_operand" "m")
4689 (match_operand:SI
2 "general_operand" "g")))]
4690 ;; Operand
2 not used on the i386.
4694 if (GET_CODE (operands[
1]) == MEM
4695 && ! CONSTANT_ADDRESS_P (XEXP (operands[
1],
0)))
4697 operands[
1] = XEXP (operands[
1],
0);
4698 output_asm_insn (AS1 (call,%*%
1), operands);
4701 output_asm_insn (AS1 (call,%P1), operands);
4707 [(set (match_operand
0 "" "=rf")
4708 (call (mem:QI (match_operand:SI
1 "symbolic_operand" ""))
4709 (match_operand:SI
2 "general_operand" "g")))]
4710 ;; Operand
2 not used on the i386.
4714 (define_expand "untyped_call"
4715 [(parallel [(call (match_operand:QI
0 "indirect_operand" "")
4717 (match_operand:BLK
1 "memory_operand" "")
4718 (match_operand
2 "" "")])]
4725 current_function_uses_pic_offset_table =
1;
4727 /* With half-pic, force the address into a register. */
4728 addr = XEXP (operands[
0],
0);
4729 if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr))
4730 XEXP (operands[
0],
0) = force_reg (Pmode, addr);
4732 operands[
1] = change_address (operands[
1], DImode, XEXP (operands[
1],
0));
4733 if (! expander_call_insn_operand (operands[
1], QImode))
4735 = change_address (operands[
1], VOIDmode,
4736 copy_to_mode_reg (Pmode, XEXP (operands[
1],
0)));
4740 [(call (match_operand:QI
0 "call_insn_operand" "m")
4742 (match_operand:DI
1 "memory_operand" "o")
4743 (match_operand
2 "" "")]
4747 rtx addr = operands[
1];
4749 if (GET_CODE (operands[
0]) == MEM
4750 && ! CONSTANT_ADDRESS_P (XEXP (operands[
0],
0)))
4752 operands[
0] = XEXP (operands[
0],
0);
4753 output_asm_insn (AS1 (call,%*%
0), operands);
4756 output_asm_insn (AS1 (call,%P0), operands);
4758 operands[
2] = gen_rtx (REG, SImode,
0);
4759 output_asm_insn (AS2 (mov%L2,%
2,%
1), operands);
4761 operands[
2] = gen_rtx (REG, SImode,
1);
4762 operands[
1] = adj_offsettable_operand (addr,
4);
4763 output_asm_insn (AS2 (mov%L2,%
2,%
1), operands);
4765 operands[
1] = adj_offsettable_operand (addr,
8);
4766 return AS1 (fnsave,%
1);
4770 [(call (mem:QI (match_operand:SI
0 "symbolic_operand" ""))
4772 (match_operand:DI
1 "memory_operand" "o")
4773 (match_operand
2 "" "")]
4777 rtx addr = operands[
1];
4779 output_asm_insn (AS1 (call,%P0), operands);
4781 operands[
2] = gen_rtx (REG, SImode,
0);
4782 output_asm_insn (AS2 (mov%L2,%
2,%
1), operands);
4784 operands[
2] = gen_rtx (REG, SImode,
1);
4785 operands[
1] = adj_offsettable_operand (addr,
4);
4786 output_asm_insn (AS2 (mov%L2,%
2,%
1), operands);
4788 operands[
1] = adj_offsettable_operand (addr,
8);
4789 return AS1 (fnsave,%
1);
4792 ;; We use fnsave and frstor to save and restore the floating point result.
4793 ;; These are expensive instructions and require a large space to save the
4794 ;; FPU state. An more complicated alternative is to use fnstenv to store
4795 ;; the FPU environment and test whether the stack top is valid. Store the
4796 ;; result of the test, and if it is valid, pop and save the value. The
4797 ;; untyped_return would check the test and optionally push the saved value.
4799 (define_expand "untyped_return"
4800 [(match_operand:BLK
0 "memory_operand" "")
4801 (match_operand
1 "" "")]
4805 rtx valreg1 = gen_rtx (REG, SImode,
0);
4806 rtx valreg2 = gen_rtx (REG, SImode,
1);
4807 rtx result = operands[
0];
4809 /* Restore the FPU state. */
4810 emit_insn (gen_update_return (change_address (result, SImode,
4811 plus_constant (XEXP (result,
0),
4814 /* Reload the function value registers. */
4815 emit_move_insn (valreg1, change_address (result, SImode, XEXP (result,
0)));
4816 emit_move_insn (valreg2,
4817 change_address (result, SImode,
4818 plus_constant (XEXP (result,
0),
4)));
4820 /* Put USE insns before the return. */
4821 emit_insn (gen_rtx (USE, VOIDmode, valreg1));
4822 emit_insn (gen_rtx (USE, VOIDmode, valreg2));
4824 /* Construct the return. */
4825 expand_null_return ();
4830 (define_insn "update_return"
4831 [(unspec:SI [(match_operand:SI
0 "memory_operand" "m")]
0)]
4835 ;; Insn emitted into the body of a function to return from a function.
4836 ;; This is only done if the function's epilogue is known to be simple.
4837 ;; See comments for simple_386_epilogue in i386.c.
4839 (define_insn "return"
4841 "simple_386_epilogue ()"
4844 function_epilogue (asm_out_file, get_frame_size ());
4853 (define_expand "movstrsi"
4854 [(parallel [(set (match_operand:BLK
0 "memory_operand" "")
4855 (match_operand:BLK
1 "memory_operand" ""))
4856 (use (match_operand:SI
2 "const_int_operand" ""))
4857 (use (match_operand:SI
3 "const_int_operand" ""))
4858 (clobber (match_scratch:SI
4 ""))
4859 (clobber (match_dup
5))
4860 (clobber (match_dup
6))])]
4866 if (GET_CODE (operands[
2]) != CONST_INT)
4869 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[
0],
0));
4870 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[
1],
0));
4872 operands[
5] = addr0;
4873 operands[
6] = addr1;
4875 operands[
0] = gen_rtx (MEM, BLKmode, addr0);
4876 operands[
1] = gen_rtx (MEM, BLKmode, addr1);
4879 ;; It might seem that operands
0 &
1 could use predicate register_operand.
4880 ;; But strength reduction might offset the MEM expression. So we let
4881 ;; reload put the address into %edi & %esi.
4884 [(set (mem:BLK (match_operand:SI
0 "address_operand" "D"))
4885 (mem:BLK (match_operand:SI
1 "address_operand" "S")))
4886 (use (match_operand:SI
2 "const_int_operand" "n"))
4887 (use (match_operand:SI
3 "immediate_operand" "i"))
4888 (clobber (match_scratch:SI
4 "=&c"))
4889 (clobber (match_dup
0))
4890 (clobber (match_dup
1))]
4896 output_asm_insn (
\"cld
\", operands);
4897 if (GET_CODE (operands[
2]) == CONST_INT)
4899 if (INTVAL (operands[
2]) & ~
0x03)
4901 xops[
0] = GEN_INT ((INTVAL (operands[
2]) >>
2) &
0x3fffffff);
4902 xops[
1] = operands[
4];
4904 output_asm_insn (AS2 (mov%L1,%
0,%
1), xops);
4906 output_asm_insn (
\"rep movsd
\", xops);
4908 output_asm_insn (
\"rep\;movsl
\", xops);
4911 if (INTVAL (operands[
2]) &
0x02)
4912 output_asm_insn (
\"movsw
\", operands);
4913 if (INTVAL (operands[
2]) &
0x01)
4914 output_asm_insn (
\"movsb
\", operands);
4921 (define_expand "cmpstrsi"
4922 [(parallel [(set (match_operand:SI
0 "general_operand" "")
4923 (compare:SI (match_operand:BLK
1 "general_operand" "")
4924 (match_operand:BLK
2 "general_operand" "")))
4925 (use (match_operand:SI
3 "general_operand" ""))
4926 (use (match_operand:SI
4 "immediate_operand" ""))
4927 (clobber (match_dup
5))
4928 (clobber (match_dup
6))
4929 (clobber (match_dup
3))])]
4935 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[
1],
0));
4936 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[
2],
0));
4937 operands[
3] = copy_to_mode_reg (SImode, operands[
3]);
4939 operands[
5] = addr1;
4940 operands[
6] = addr2;
4942 operands[
1] = gen_rtx (MEM, BLKmode, addr1);
4943 operands[
2] = gen_rtx (MEM, BLKmode, addr2);
4947 ;; memcmp recognizers. The
`cmpsb' opcode does nothing if the count is
4948 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
4950 ;; It might seem that operands 0 & 1 could use predicate register_operand.
4951 ;; But strength reduction might offset the MEM expression. So we let
4952 ;; reload put the address into %edi & %esi.
4954 ;; ??? Most comparisons have a constant length, and it's therefore
4955 ;; possible to know that the length is non-zero, and to avoid the extra
4956 ;; code to handle zero-length compares.
4959 [(set (match_operand:SI 0 "general_operand" "=&r")
4960 (compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S"))
4961 (mem:BLK (match_operand:SI 2 "address_operand" "D"))))
4962 (use (match_operand:SI 3 "register_operand" "c"))
4963 (use (match_operand:SI 4 "immediate_operand" "i"))
4964 (clobber (match_dup 1))
4965 (clobber (match_dup 2))
4966 (clobber (match_dup 3))]
4972 label = gen_label_rtx ();
4974 output_asm_insn (\"cld\", operands);
4975 output_asm_insn (AS2 (xor%L0,%0,%0), operands);
4976 output_asm_insn (\"repz\;cmps%B2\", operands);
4977 output_asm_insn (\"je %l0\", &label);
4979 xops[0] = operands[0];
4980 xops[1] = gen_rtx (MEM, QImode,
4981 gen_rtx (PLUS, SImode, operands[1], constm1_rtx));
4982 xops[2] = gen_rtx (MEM, QImode,
4983 gen_rtx (PLUS, SImode, operands[2], constm1_rtx));
4984 xops[3] = operands[3];
4986 output_asm_insn (AS2 (movz%B1%L0,%1,%0), xops);
4987 output_asm_insn (AS2 (movz%B2%L3,%2,%3), xops);
4989 output_asm_insn (AS2 (sub%L0,%3,%0), xops);
4990 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label));
4996 (compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S"))
4997 (mem:BLK (match_operand:SI 1 "address_operand" "D"))))
4998 (use (match_operand:SI 2 "register_operand" "c"))
4999 (use (match_operand:SI 3 "immediate_operand" "i"))
5000 (clobber (match_dup 0))
5001 (clobber (match_dup 1))
5002 (clobber (match_dup 2))]
5008 cc_status.flags |= CC_NOT_SIGNED;
5010 xops[0] = gen_rtx (REG, QImode, 0);
5011 xops[1] = CONST0_RTX (QImode);
5013 output_asm_insn (\"cld\", operands);
5014 output_asm_insn (AS2 (test%B0,%1,%0), xops);
5015 return \"repz\;cmps%B2\";
5018 (define_expand "ffssi2"
5020 (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" ""))
5022 (set (match_operand:SI 0 "general_operand" "")
5023 (plus:SI (match_dup 2) (const_int 1)))]
5025 "operands[2] = gen_reg_rtx (SImode);")
5028 [(set (match_operand:SI 0 "general_operand" "=&r")
5029 (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" "rm"))
5035 static int ffssi_label_number;
5038 xops[0] = operands[0];
5039 xops[1] = operands[1];
5040 xops[2] = constm1_rtx;
5041 /* Can there be a way to avoid the jump here? */
5042 output_asm_insn (AS2 (bsf%L0,%1,%0), xops);
5043 #ifdef LOCAL_LABEL_PREFIX
5044 sprintf (buffer, \"jnz %sLFFSSI%d\",
5045 LOCAL_LABEL_PREFIX, ffssi_label_number);
5047 sprintf (buffer, \"jnz %sLFFSSI%d\",
5048 \"\", ffssi_label_number);
5050 output_asm_insn (buffer, xops);
5051 output_asm_insn (AS2 (mov%L0,%2,%0), xops);
5052 #ifdef LOCAL_LABEL_PREFIX
5053 sprintf (buffer, \"%sLFFSSI%d:\",
5054 LOCAL_LABEL_PREFIX, ffssi_label_number);
5056 sprintf (buffer, \"%sLFFSSI%d:\",
5057 \"\", ffssi_label_number);
5059 output_asm_insn (buffer, xops);
5061 ffssi_label_number++;
5065 (define_expand "ffshi2"
5067 (plus:HI (ffs:HI (match_operand:HI 1 "general_operand" ""))
5069 (set (match_operand:HI 0 "general_operand" "")
5070 (plus:HI (match_dup 2) (const_int 1)))]
5072 "operands[2] = gen_reg_rtx (HImode);")
5075 [(set (match_operand:HI 0 "general_operand" "=&r")
5076 (plus:HI (ffs:HI (match_operand:SI 1 "general_operand" "rm"))
5082 static int ffshi_label_number;
5085 xops[0] = operands[0];
5086 xops[1] = operands[1];
5087 xops[2] = constm1_rtx;
5088 output_asm_insn (AS2 (bsf%W0,%1,%0), xops);
5089 #ifdef LOCAL_LABEL_PREFIX
5090 sprintf (buffer, \"jnz %sLFFSHI%d\",
5091 LOCAL_LABEL_PREFIX, ffshi_label_number);
5093 sprintf (buffer, \"jnz %sLFFSHI%d\",
5094 \"\", ffshi_label_number);
5096 output_asm_insn (buffer, xops);
5097 output_asm_insn (AS2 (mov%W0,%2,%0), xops);
5098 #ifdef LOCAL_LABEL_PREFIX
5099 sprintf (buffer, \"%sLFFSHI%d:\",
5100 LOCAL_LABEL_PREFIX, ffshi_label_number);
5102 sprintf (buffer, \"%sLFFSHI%d:\",
5103 \"\", ffshi_label_number);
5105 output_asm_insn (buffer, xops);
5107 ffshi_label_number++;
5111 ;; These patterns match the binary 387 instructions for addM3, subM3,
5112 ;; mulM3 and divM3. There are three patterns for each of DFmode and
5113 ;; SFmode. The first is the normal insn, the second the same insn but
5114 ;; with one operand a conversion, and the third the same insn but with
5115 ;; the other operand a conversion. The conversion may be SFmode or
5116 ;; SImode if the target mode DFmode, but only SImode if the target mode
5120 [(set (match_operand:DF 0 "register_operand" "=f,f")
5121 (match_operator:DF 3 "binary_387_op"
5122 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
5123 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
5125 "* return (char *) output_387_binary_op (insn, operands);")
5128 [(set (match_operand:DF 0 "register_operand" "=f")
5129 (match_operator:DF 3 "binary_387_op"
5130 [(float:DF (match_operand:SI 1 "general_operand" "rm"))
5131 (match_operand:DF 2 "general_operand" "0")]))]
5133 "* return (char *) output_387_binary_op (insn, operands);")
5136 [(set (match_operand:XF 0 "register_operand" "=f,f")
5137 (match_operator:XF 3 "binary_387_op"
5138 [(match_operand:XF 1 "nonimmediate_operand" "0,f")
5139 (match_operand:XF 2 "nonimmediate_operand" "f,0")]))]
5141 "* return (char *) output_387_binary_op (insn, operands);")
5144 [(set (match_operand:XF 0 "register_operand" "=f")
5145 (match_operator:XF 3 "binary_387_op"
5146 [(float:XF (match_operand:SI 1 "general_operand" "rm"))
5147 (match_operand:XF 2 "general_operand" "0")]))]
5149 "* return (char *) output_387_binary_op (insn, operands);")
5152 [(set (match_operand:XF 0 "register_operand" "=f,f")
5153 (match_operator:XF 3 "binary_387_op"
5154 [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0"))
5155 (match_operand:XF 2 "general_operand" "0,f")]))]
5157 "* return (char *) output_387_binary_op (insn, operands);")
5160 [(set (match_operand:XF 0 "register_operand" "=f")
5161 (match_operator:XF 3 "binary_387_op"
5162 [(match_operand:XF 1 "general_operand" "0")
5163 (float:XF (match_operand:SI 2 "general_operand" "rm"))]))]
5165 "* return (char *) output_387_binary_op (insn, operands);")
5168 [(set (match_operand:XF 0 "register_operand" "=f,f")
5169 (match_operator:XF 3 "binary_387_op"
5170 [(match_operand:XF 1 "general_operand" "0,f")
5172 (match_operand:SF 2 "general_operand" "fm,0"))]))]
5174 "* return (char *) output_387_binary_op (insn, operands);")
5177 [(set (match_operand:DF 0 "register_operand" "=f,f")
5178 (match_operator:DF 3 "binary_387_op"
5179 [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0"))
5180 (match_operand:DF 2 "general_operand" "0,f")]))]
5182 "* return (char *) output_387_binary_op (insn, operands);")
5185 [(set (match_operand:DF 0 "register_operand" "=f")
5186 (match_operator:DF 3 "binary_387_op"
5187 [(match_operand:DF 1 "general_operand" "0")
5188 (float:DF (match_operand:SI 2 "general_operand" "rm"))]))]
5190 "* return (char *) output_387_binary_op (insn, operands);")
5193 [(set (match_operand:DF 0 "register_operand" "=f,f")
5194 (match_operator:DF 3 "binary_387_op"
5195 [(match_operand:DF 1 "general_operand" "0,f")
5197 (match_operand:SF 2 "general_operand" "fm,0"))]))]
5199 "* return (char *) output_387_binary_op (insn, operands);")
5202 [(set (match_operand:SF 0 "register_operand" "=f,f")
5203 (match_operator:SF 3 "binary_387_op"
5204 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
5205 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
5207 "* return (char *) output_387_binary_op (insn, operands);")
5210 [(set (match_operand:SF 0 "register_operand" "=f")
5211 (match_operator:SF 3 "binary_387_op"
5212 [(float:SF (match_operand:SI 1 "general_operand" "rm"))
5213 (match_operand:SF 2 "general_operand" "0")]))]
5215 "* return (char *) output_387_binary_op (insn, operands);")
5218 [(set (match_operand:SF 0 "register_operand" "=f")
5219 (match_operator:SF 3 "binary_387_op"
5220 [(match_operand:SF 1 "general_operand" "0")
5221 (float:SF (match_operand:SI 2 "general_operand" "rm"))]))]
5223 "* return (char *) output_387_binary_op (insn, operands);")
5225 (define_expand "strlensi"
5226 [(parallel [(set (match_dup 4)
5227 (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" ""))
5228 (match_operand:QI 2 "register_operand" "")
5229 (match_operand:SI 3 "immediate_operand" "")] 0))
5230 (clobber (match_dup 1))])
5232 (not:SI (match_dup 4)))
5233 (set (match_operand:SI 0 "register_operand" "")
5234 (minus:SI (match_dup 5)
5239 operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
5240 operands[4] = gen_reg_rtx (SImode);
5241 operands[5] = gen_reg_rtx (SImode);
5244 ;; It might seem that operands 0 & 1 could use predicate register_operand.
5245 ;; But strength reduction might offset the MEM expression. So we let
5246 ;; reload put the address into %edi.
5249 [(set (match_operand:SI 0 "register_operand" "=&c")
5250 (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D"))
5251 (match_operand:QI 2 "register_operand" "a")
5252 (match_operand:SI 3 "immediate_operand" "i")] 0))
5253 (clobber (match_dup 1))]
5259 xops[0] = operands[0];
5260 xops[1] = constm1_rtx;
5261 output_asm_insn (\"cld\", operands);
5262 output_asm_insn (AS2 (mov%L0,%1,%0), xops);
5263 return \"repnz\;scas%B2\";