1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 #include "basic-block.h"
45 #ifdef EXTRA_CONSTRAINT
46 /* If EXTRA_CONSTRAINT is defined, then the 'S'
47 constraint in REG_CLASS_FROM_LETTER will no longer work, and various
48 asm statements that need 'S' for class SIREG will break. */
49 error EXTRA_CONSTRAINT conflicts with S constraint letter
50 /* The previous line used to be #error, but some compilers barf
51 even if the conditional was untrue. */
54 #ifndef CHECK_STACK_LIMIT
55 #define CHECK_STACK_LIMIT -1
58 /* Processor costs (relative to an add) */
59 struct processor_costs i386_cost
= { /* 386 specific costs */
60 1, /* cost of an add instruction */
61 1, /* cost of a lea instruction */
62 3, /* variable shift costs */
63 2, /* constant shift costs */
64 6, /* cost of starting a multiply */
65 1, /* cost of multiply per each bit set */
66 23, /* cost of a divide/mod */
67 15, /* "large" insn */
69 4, /* cost for loading QImode using movzbl */
70 {2, 4, 2}, /* cost of loading integer registers
71 in QImode, HImode and SImode.
72 Relative to reg-reg move (2). */
73 {2, 4, 2}, /* cost of storing integer registers */
74 2, /* cost of reg,reg fld/fst */
75 {8, 8, 8}, /* cost of loading fp registers
76 in SFmode, DFmode and XFmode */
77 {8, 8, 8} /* cost of loading integer registers */
80 struct processor_costs i486_cost
= { /* 486 specific costs */
81 1, /* cost of an add instruction */
82 1, /* cost of a lea instruction */
83 3, /* variable shift costs */
84 2, /* constant shift costs */
85 12, /* cost of starting a multiply */
86 1, /* cost of multiply per each bit set */
87 40, /* cost of a divide/mod */
88 15, /* "large" insn */
90 4, /* cost for loading QImode using movzbl */
91 {2, 4, 2}, /* cost of loading integer registers
92 in QImode, HImode and SImode.
93 Relative to reg-reg move (2). */
94 {2, 4, 2}, /* cost of storing integer registers */
95 2, /* cost of reg,reg fld/fst */
96 {8, 8, 8}, /* cost of loading fp registers
97 in SFmode, DFmode and XFmode */
98 {8, 8, 8} /* cost of loading integer registers */
101 struct processor_costs pentium_cost
= {
102 1, /* cost of an add instruction */
103 1, /* cost of a lea instruction */
104 4, /* variable shift costs */
105 1, /* constant shift costs */
106 11, /* cost of starting a multiply */
107 0, /* cost of multiply per each bit set */
108 25, /* cost of a divide/mod */
109 8, /* "large" insn */
111 6, /* cost for loading QImode using movzbl */
112 {2, 4, 2}, /* cost of loading integer registers
113 in QImode, HImode and SImode.
114 Relative to reg-reg move (2). */
115 {2, 4, 2}, /* cost of storing integer registers */
116 2, /* cost of reg,reg fld/fst */
117 {2, 2, 6}, /* cost of loading fp registers
118 in SFmode, DFmode and XFmode */
119 {4, 4, 6} /* cost of loading integer registers */
122 struct processor_costs pentiumpro_cost
= {
123 1, /* cost of an add instruction */
124 1, /* cost of a lea instruction */
125 1, /* variable shift costs */
126 1, /* constant shift costs */
127 4, /* cost of starting a multiply */
128 0, /* cost of multiply per each bit set */
129 17, /* cost of a divide/mod */
130 8, /* "large" insn */
132 2, /* cost for loading QImode using movzbl */
133 {4, 4, 4}, /* cost of loading integer registers
134 in QImode, HImode and SImode.
135 Relative to reg-reg move (2). */
136 {2, 2, 2}, /* cost of storing integer registers */
137 2, /* cost of reg,reg fld/fst */
138 {2, 2, 6}, /* cost of loading fp registers
139 in SFmode, DFmode and XFmode */
140 {4, 4, 6} /* cost of loading integer registers */
143 struct processor_costs k6_cost
= {
144 1, /* cost of an add instruction */
145 2, /* cost of a lea instruction */
146 1, /* variable shift costs */
147 1, /* constant shift costs */
148 3, /* cost of starting a multiply */
149 0, /* cost of multiply per each bit set */
150 18, /* cost of a divide/mod */
151 8, /* "large" insn */
153 3, /* cost for loading QImode using movzbl */
154 {4, 5, 4}, /* cost of loading integer registers
155 in QImode, HImode and SImode.
156 Relative to reg-reg move (2). */
157 {2, 3, 2}, /* cost of storing integer registers */
158 4, /* cost of reg,reg fld/fst */
159 {6, 6, 6}, /* cost of loading fp registers
160 in SFmode, DFmode and XFmode */
161 {4, 4, 4} /* cost of loading integer registers */
164 struct processor_costs athlon_cost
= {
165 1, /* cost of an add instruction */
166 1, /* cost of a lea instruction */
167 1, /* variable shift costs */
168 1, /* constant shift costs */
169 5, /* cost of starting a multiply */
170 0, /* cost of multiply per each bit set */
171 19, /* cost of a divide/mod */
172 8, /* "large" insn */
174 4, /* cost for loading QImode using movzbl */
175 {4, 5, 4}, /* cost of loading integer registers
176 in QImode, HImode and SImode.
177 Relative to reg-reg move (2). */
178 {2, 3, 2}, /* cost of storing integer registers */
179 4, /* cost of reg,reg fld/fst */
180 {6, 6, 6}, /* cost of loading fp registers
181 in SFmode, DFmode and XFmode */
182 {4, 4, 4} /* cost of loading integer registers */
185 struct processor_costs
*ix86_cost
= &pentium_cost
;
187 /* Processor feature/optimization bitmasks. */
188 #define m_386 (1<<PROCESSOR_I386)
189 #define m_486 (1<<PROCESSOR_I486)
190 #define m_PENT (1<<PROCESSOR_PENTIUM)
191 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
192 #define m_K6 (1<<PROCESSOR_K6)
193 #define m_ATHLON (1<<PROCESSOR_ATHLON)
195 const int x86_use_leave
= m_386
| m_K6
| m_ATHLON
;
196 const int x86_push_memory
= m_386
| m_K6
| m_ATHLON
;
197 const int x86_zero_extend_with_and
= m_486
| m_PENT
;
198 const int x86_movx
= m_ATHLON
| m_PPRO
/* m_386 | m_K6 */;
199 const int x86_double_with_add
= ~m_386
;
200 const int x86_use_bit_test
= m_386
;
201 const int x86_unroll_strlen
= m_486
| m_PENT
| m_PPRO
| m_ATHLON
| m_K6
;
202 const int x86_use_q_reg
= m_PENT
| m_PPRO
| m_K6
;
203 const int x86_use_any_reg
= m_486
;
204 const int x86_cmove
= m_PPRO
| m_ATHLON
;
205 const int x86_deep_branch
= m_PPRO
| m_K6
| m_ATHLON
;
206 const int x86_use_sahf
= m_PPRO
| m_K6
| m_ATHLON
;
207 const int x86_partial_reg_stall
= m_PPRO
;
208 const int x86_use_loop
= m_K6
;
209 const int x86_use_fiop
= ~(m_PPRO
| m_ATHLON
| m_PENT
);
210 const int x86_use_mov0
= m_K6
;
211 const int x86_use_cltd
= ~(m_PENT
| m_K6
);
212 const int x86_read_modify_write
= ~m_PENT
;
213 const int x86_read_modify
= ~(m_PENT
| m_PPRO
);
214 const int x86_split_long_moves
= m_PPRO
;
215 const int x86_promote_QImode
= m_K6
| m_PENT
| m_386
| m_486
;
216 const int x86_single_stringop
= m_386
;
217 const int x86_qimode_math
= ~(0);
218 const int x86_promote_qi_regs
= 0;
219 const int x86_himode_math
= ~(m_PPRO
);
220 const int x86_promote_hi_regs
= m_PPRO
;
222 #define AT_BP(mode) (gen_rtx_MEM ((mode), hard_frame_pointer_rtx))
224 const char * const hi_reg_name
[] = HI_REGISTER_NAMES
;
225 const char * const qi_reg_name
[] = QI_REGISTER_NAMES
;
226 const char * const qi_high_reg_name
[] = QI_HIGH_REGISTER_NAMES
;
228 /* Array of the smallest class containing reg number REGNO, indexed by
229 REGNO. Used by REGNO_REG_CLASS in i386.h. */
231 enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
] =
234 AREG
, DREG
, CREG
, BREG
,
236 SIREG
, DIREG
, NON_Q_REGS
, NON_Q_REGS
,
238 FP_TOP_REG
, FP_SECOND_REG
, FLOAT_REGS
, FLOAT_REGS
,
239 FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
,
242 /* flags, fpsr, dirflag, frame */
243 NO_REGS
, NO_REGS
, NO_REGS
, NON_Q_REGS
246 /* The "default" register map. */
248 int const dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
250 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
251 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
252 -1, -1, -1, -1, /* arg, flags, fpsr, dir */
255 /* Define the register numbers to be used in Dwarf debugging information.
256 The SVR4 reference port C compiler uses the following register numbers
257 in its Dwarf output code:
258 0 for %eax (gcc regno = 0)
259 1 for %ecx (gcc regno = 2)
260 2 for %edx (gcc regno = 1)
261 3 for %ebx (gcc regno = 3)
262 4 for %esp (gcc regno = 7)
263 5 for %ebp (gcc regno = 6)
264 6 for %esi (gcc regno = 4)
265 7 for %edi (gcc regno = 5)
266 The following three DWARF register numbers are never generated by
267 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
268 believes these numbers have these meanings.
269 8 for %eip (no gcc equivalent)
270 9 for %eflags (gcc regno = 17)
271 10 for %trapno (no gcc equivalent)
272 It is not at all clear how we should number the FP stack registers
273 for the x86 architecture. If the version of SDB on x86/svr4 were
274 a bit less brain dead with respect to floating-point then we would
275 have a precedent to follow with respect to DWARF register numbers
276 for x86 FP registers, but the SDB on x86/svr4 is so completely
277 broken with respect to FP registers that it is hardly worth thinking
278 of it as something to strive for compatibility with.
279 The version of x86/svr4 SDB I have at the moment does (partially)
280 seem to believe that DWARF register number 11 is associated with
281 the x86 register %st(0), but that's about all. Higher DWARF
282 register numbers don't seem to be associated with anything in
283 particular, and even for DWARF regno 11, SDB only seems to under-
284 stand that it should say that a variable lives in %st(0) (when
285 asked via an `=' command) if we said it was in DWARF regno 11,
286 but SDB still prints garbage when asked for the value of the
287 variable in question (via a `/' command).
288 (Also note that the labels SDB prints for various FP stack regs
289 when doing an `x' command are all wrong.)
290 Note that these problems generally don't affect the native SVR4
291 C compiler because it doesn't allow the use of -O with -g and
292 because when it is *not* optimizing, it allocates a memory
293 location for each floating-point variable, and the memory
294 location is what gets described in the DWARF AT_location
295 attribute for the variable in question.
296 Regardless of the severe mental illness of the x86/svr4 SDB, we
297 do something sensible here and we use the following DWARF
298 register numbers. Note that these are all stack-top-relative
300 11 for %st(0) (gcc regno = 8)
301 12 for %st(1) (gcc regno = 9)
302 13 for %st(2) (gcc regno = 10)
303 14 for %st(3) (gcc regno = 11)
304 15 for %st(4) (gcc regno = 12)
305 16 for %st(5) (gcc regno = 13)
306 17 for %st(6) (gcc regno = 14)
307 18 for %st(7) (gcc regno = 15)
309 int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
311 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
312 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
313 -1, 9, -1, -1, /* arg, flags, fpsr, dir */
318 /* Test and compare insns in i386.md store the information needed to
319 generate branch and scc insns here. */
321 struct rtx_def
*ix86_compare_op0
= NULL_RTX
;
322 struct rtx_def
*ix86_compare_op1
= NULL_RTX
;
324 #define MAX_386_STACK_LOCALS 2
326 /* Define the structure for the machine field in struct function. */
327 struct machine_function
329 rtx stack_locals
[(int) MAX_MACHINE_MODE
][MAX_386_STACK_LOCALS
];
332 #define ix86_stack_locals (cfun->machine->stack_locals)
334 /* which cpu are we scheduling for */
335 enum processor_type ix86_cpu
;
337 /* which instruction set architecture to use. */
340 /* Strings to hold which cpu and instruction set architecture to use. */
341 const char *ix86_cpu_string
; /* for -mcpu=<xxx> */
342 const char *ix86_arch_string
; /* for -march=<xxx> */
344 /* Register allocation order */
345 const char *ix86_reg_alloc_order
;
346 static char regs_allocated
[FIRST_PSEUDO_REGISTER
];
348 /* # of registers to use to pass arguments. */
349 const char *ix86_regparm_string
;
351 /* ix86_regparm_string as a number */
354 /* Alignment to use for loops and jumps: */
356 /* Power of two alignment for loops. */
357 const char *ix86_align_loops_string
;
359 /* Power of two alignment for non-loop jumps. */
360 const char *ix86_align_jumps_string
;
362 /* Power of two alignment for stack boundary in bytes. */
363 const char *ix86_preferred_stack_boundary_string
;
365 /* Preferred alignment for stack boundary in bits. */
366 int ix86_preferred_stack_boundary
;
368 /* Values 1-5: see jump.c */
369 int ix86_branch_cost
;
370 const char *ix86_branch_cost_string
;
372 /* Power of two alignment for functions. */
373 int ix86_align_funcs
;
374 const char *ix86_align_funcs_string
;
376 /* Power of two alignment for loops. */
377 int ix86_align_loops
;
379 /* Power of two alignment for non-loop jumps. */
380 int ix86_align_jumps
;
382 static void output_pic_addr_const
PARAMS ((FILE *, rtx
, int));
383 static void put_condition_code
PARAMS ((enum rtx_code
, enum machine_mode
,
385 static enum rtx_code unsigned_comparison
PARAMS ((enum rtx_code code
));
386 static rtx ix86_expand_int_compare
PARAMS ((enum rtx_code
, rtx
, rtx
));
387 static rtx ix86_expand_fp_compare
PARAMS ((enum rtx_code
, rtx
, rtx
, int));
388 static rtx ix86_expand_compare
PARAMS ((enum rtx_code
, int));
389 static rtx gen_push
PARAMS ((rtx
));
390 static int memory_address_length
PARAMS ((rtx addr
));
391 static int ix86_flags_dependant
PARAMS ((rtx
, rtx
, enum attr_type
));
392 static int ix86_agi_dependant
PARAMS ((rtx
, rtx
, enum attr_type
));
393 static int ix86_safe_length
PARAMS ((rtx
));
394 static enum attr_memory ix86_safe_memory
PARAMS ((rtx
));
395 static enum attr_pent_pair ix86_safe_pent_pair
PARAMS ((rtx
));
396 static enum attr_ppro_uops ix86_safe_ppro_uops
PARAMS ((rtx
));
397 static void ix86_dump_ppro_packet
PARAMS ((FILE *));
398 static void ix86_reorder_insn
PARAMS ((rtx
*, rtx
*));
399 static rtx
* ix86_pent_find_pair
PARAMS ((rtx
*, rtx
*, enum attr_pent_pair
,
401 static void ix86_init_machine_status
PARAMS ((struct function
*));
402 static void ix86_mark_machine_status
PARAMS ((struct function
*));
403 static void ix86_split_to_parts
PARAMS ((rtx
, rtx
*, enum machine_mode
));
404 static int ix86_safe_length_prefix
PARAMS ((rtx
));
405 static HOST_WIDE_INT ix86_compute_frame_size
PARAMS((HOST_WIDE_INT
,
406 int *, int *, int *));
407 static int ix86_nsaved_regs
PARAMS((void));
408 static void ix86_emit_save_regs
PARAMS((void));
409 static void ix86_emit_restore_regs_using_mov
PARAMS ((rtx
, int));
410 static void ix86_emit_epilogue_esp_adjustment
PARAMS((int));
411 static void ix86_sched_reorder_pentium
PARAMS((rtx
*, rtx
*));
412 static void ix86_sched_reorder_ppro
PARAMS((rtx
*, rtx
*));
416 rtx base
, index
, disp
;
420 static int ix86_decompose_address
PARAMS ((rtx
, struct ix86_address
*));
422 /* Sometimes certain combinations of command options do not make
423 sense on a particular target machine. You can define a macro
424 `OVERRIDE_OPTIONS' to take account of this. This macro, if
425 defined, is executed once just after all the command options have
428 Don't use this macro to turn on various extra optimizations for
429 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
434 /* Comes from final.c -- no real reason to change it. */
435 #define MAX_CODE_ALIGN 16
439 struct processor_costs
*cost
; /* Processor costs */
440 int target_enable
; /* Target flags to enable. */
441 int target_disable
; /* Target flags to disable. */
442 int align_loop
; /* Default alignments. */
447 const processor_target_table
[PROCESSOR_max
] =
449 {&i386_cost
, 0, 0, 2, 2, 2, 1},
450 {&i486_cost
, 0, 0, 4, 4, 4, 1},
451 {&pentium_cost
, 0, 0, -4, -4, -4, 1},
452 {&pentiumpro_cost
, 0, 0, 4, -4, 4, 1},
453 {&k6_cost
, 0, 0, -5, -5, 4, 1},
454 {&athlon_cost
, 0, 0, 4, -4, 4, 1}
459 const char *name
; /* processor name or nickname. */
460 enum processor_type processor
;
462 const processor_alias_table
[] =
464 {"i386", PROCESSOR_I386
},
465 {"i486", PROCESSOR_I486
},
466 {"i586", PROCESSOR_PENTIUM
},
467 {"pentium", PROCESSOR_PENTIUM
},
468 {"i686", PROCESSOR_PENTIUMPRO
},
469 {"pentiumpro", PROCESSOR_PENTIUMPRO
},
470 {"k6", PROCESSOR_K6
},
471 {"athlon", PROCESSOR_ATHLON
},
474 int const pta_size
= sizeof(processor_alias_table
)/sizeof(struct pta
);
476 #ifdef SUBTARGET_OVERRIDE_OPTIONS
477 SUBTARGET_OVERRIDE_OPTIONS
;
480 ix86_arch
= PROCESSOR_I386
;
481 ix86_cpu
= (enum processor_type
) TARGET_CPU_DEFAULT
;
483 if (ix86_arch_string
!= 0)
486 for (i
= 0; i
< pta_size
; i
++)
487 if (! strcmp (ix86_arch_string
, processor_alias_table
[i
].name
))
489 ix86_arch
= processor_alias_table
[i
].processor
;
490 /* Default cpu tuning to the architecture. */
491 ix86_cpu
= ix86_arch
;
495 error ("bad value (%s) for -march= switch", ix86_arch_string
);
498 if (ix86_cpu_string
!= 0)
501 for (i
= 0; i
< pta_size
; i
++)
502 if (! strcmp (ix86_cpu_string
, processor_alias_table
[i
].name
))
504 ix86_cpu
= processor_alias_table
[i
].processor
;
508 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string
);
511 ix86_cost
= processor_target_table
[ix86_cpu
].cost
;
512 target_flags
|= processor_target_table
[ix86_cpu
].target_enable
;
513 target_flags
&= ~processor_target_table
[ix86_cpu
].target_disable
;
515 /* Arrange to set up i386_stack_locals for all functions. */
516 init_machine_status
= ix86_init_machine_status
;
517 mark_machine_status
= ix86_mark_machine_status
;
519 /* Validate registers in register allocation order. */
520 if (ix86_reg_alloc_order
)
523 for (i
= 0; (ch
= ix86_reg_alloc_order
[i
]) != '\0'; i
++)
529 case 'a': regno
= 0; break;
530 case 'd': regno
= 1; break;
531 case 'c': regno
= 2; break;
532 case 'b': regno
= 3; break;
533 case 'S': regno
= 4; break;
534 case 'D': regno
= 5; break;
535 case 'B': regno
= 6; break;
537 default: fatal ("Register '%c' is unknown", ch
);
540 if (regs_allocated
[regno
])
541 fatal ("Register '%c' already specified in allocation order", ch
);
543 regs_allocated
[regno
] = 1;
547 /* Validate -mregparm= value. */
548 if (ix86_regparm_string
)
550 ix86_regparm
= atoi (ix86_regparm_string
);
551 if (ix86_regparm
< 0 || ix86_regparm
> REGPARM_MAX
)
552 fatal ("-mregparm=%d is not between 0 and %d",
553 ix86_regparm
, REGPARM_MAX
);
556 /* Validate -malign-loops= value, or provide default. */
557 ix86_align_loops
= processor_target_table
[ix86_cpu
].align_loop
;
558 if (ix86_align_loops_string
)
560 ix86_align_loops
= atoi (ix86_align_loops_string
);
561 if (ix86_align_loops
< 0 || ix86_align_loops
> MAX_CODE_ALIGN
)
562 fatal ("-malign-loops=%d is not between 0 and %d",
563 ix86_align_loops
, MAX_CODE_ALIGN
);
566 /* Validate -malign-jumps= value, or provide default. */
567 ix86_align_jumps
= processor_target_table
[ix86_cpu
].align_jump
;
568 if (ix86_align_jumps_string
)
570 ix86_align_jumps
= atoi (ix86_align_jumps_string
);
571 if (ix86_align_jumps
< 0 || ix86_align_jumps
> MAX_CODE_ALIGN
)
572 fatal ("-malign-jumps=%d is not between 0 and %d",
573 ix86_align_jumps
, MAX_CODE_ALIGN
);
576 /* Validate -malign-functions= value, or provide default. */
577 ix86_align_funcs
= processor_target_table
[ix86_cpu
].align_func
;
578 if (ix86_align_funcs_string
)
580 ix86_align_funcs
= atoi (ix86_align_funcs_string
);
581 if (ix86_align_funcs
< 0 || ix86_align_funcs
> MAX_CODE_ALIGN
)
582 fatal ("-malign-functions=%d is not between 0 and %d",
583 ix86_align_funcs
, MAX_CODE_ALIGN
);
586 /* Validate -mpreferred-stack-boundary= value, or provide default.
587 The default of 128 bits is for Pentium III's SSE __m128. */
588 ix86_preferred_stack_boundary
= 128;
589 if (ix86_preferred_stack_boundary_string
)
591 int i
= atoi (ix86_preferred_stack_boundary_string
);
593 fatal ("-mpreferred-stack-boundary=%d is not between 2 and 31", i
);
594 ix86_preferred_stack_boundary
= (1 << i
) * BITS_PER_UNIT
;
597 /* Validate -mbranch-cost= value, or provide default. */
598 ix86_branch_cost
= processor_target_table
[ix86_cpu
].branch_cost
;
599 if (ix86_branch_cost_string
)
601 ix86_branch_cost
= atoi (ix86_branch_cost_string
);
602 if (ix86_branch_cost
< 0 || ix86_branch_cost
> 5)
603 fatal ("-mbranch-cost=%d is not between 0 and 5",
607 /* Keep nonleaf frame pointers. */
608 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
609 flag_omit_frame_pointer
= 1;
611 /* If we're doing fast math, we don't care about comparison order
612 wrt NaNs. This lets us use a shorter comparison sequence. */
614 target_flags
&= ~MASK_IEEE_FP
;
616 /* If we're planning on using `loop', use it. */
617 if (TARGET_USE_LOOP
&& optimize
)
618 flag_branch_on_count_reg
= 1;
621 /* A C statement (sans semicolon) to choose the order in which to
622 allocate hard registers for pseudo-registers local to a basic
625 Store the desired register order in the array `reg_alloc_order'.
626 Element 0 should be the register to allocate first; element 1, the
627 next register; and so on.
629 The macro body should not assume anything about the contents of
630 `reg_alloc_order' before execution of the macro.
632 On most machines, it is not necessary to define this macro. */
635 order_regs_for_local_alloc ()
639 /* User specified the register allocation order. */
641 if (ix86_reg_alloc_order
)
643 for (i
= order
= 0; (ch
= ix86_reg_alloc_order
[i
]) != '\0'; i
++)
649 case 'a': regno
= 0; break;
650 case 'd': regno
= 1; break;
651 case 'c': regno
= 2; break;
652 case 'b': regno
= 3; break;
653 case 'S': regno
= 4; break;
654 case 'D': regno
= 5; break;
655 case 'B': regno
= 6; break;
658 reg_alloc_order
[order
++] = regno
;
661 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
663 if (! regs_allocated
[i
])
664 reg_alloc_order
[order
++] = i
;
668 /* If user did not specify a register allocation order, use natural order. */
671 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
672 reg_alloc_order
[i
] = i
;
677 optimization_options (level
, size
)
679 int size ATTRIBUTE_UNUSED
;
681 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
682 make the problem with not enough registers even worse. */
683 #ifdef INSN_SCHEDULING
685 flag_schedule_insns
= 0;
689 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
690 attribute for DECL. The attributes in ATTRIBUTES have previously been
694 ix86_valid_decl_attribute_p (decl
, attributes
, identifier
, args
)
695 tree decl ATTRIBUTE_UNUSED
;
696 tree attributes ATTRIBUTE_UNUSED
;
697 tree identifier ATTRIBUTE_UNUSED
;
698 tree args ATTRIBUTE_UNUSED
;
703 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
704 attribute for TYPE. The attributes in ATTRIBUTES have previously been
708 ix86_valid_type_attribute_p (type
, attributes
, identifier
, args
)
710 tree attributes ATTRIBUTE_UNUSED
;
714 if (TREE_CODE (type
) != FUNCTION_TYPE
715 && TREE_CODE (type
) != METHOD_TYPE
716 && TREE_CODE (type
) != FIELD_DECL
717 && TREE_CODE (type
) != TYPE_DECL
)
720 /* Stdcall attribute says callee is responsible for popping arguments
721 if they are not variable. */
722 if (is_attribute_p ("stdcall", identifier
))
723 return (args
== NULL_TREE
);
725 /* Cdecl attribute says the callee is a normal C declaration. */
726 if (is_attribute_p ("cdecl", identifier
))
727 return (args
== NULL_TREE
);
729 /* Regparm attribute specifies how many integer arguments are to be
730 passed in registers. */
731 if (is_attribute_p ("regparm", identifier
))
735 if (! args
|| TREE_CODE (args
) != TREE_LIST
736 || TREE_CHAIN (args
) != NULL_TREE
737 || TREE_VALUE (args
) == NULL_TREE
)
740 cst
= TREE_VALUE (args
);
741 if (TREE_CODE (cst
) != INTEGER_CST
)
744 if (compare_tree_int (cst
, REGPARM_MAX
) > 0)
753 /* Return 0 if the attributes for two types are incompatible, 1 if they
754 are compatible, and 2 if they are nearly compatible (which causes a
755 warning to be generated). */
758 ix86_comp_type_attributes (type1
, type2
)
762 /* Check for mismatch of non-default calling convention. */
763 const char *rtdstr
= TARGET_RTD
? "cdecl" : "stdcall";
765 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
768 /* Check for mismatched return types (cdecl vs stdcall). */
769 if (!lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type1
))
770 != !lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type2
)))
775 /* Value is the number of bytes of arguments automatically
776 popped when returning from a subroutine call.
777 FUNDECL is the declaration node of the function (as a tree),
778 FUNTYPE is the data type of the function (as a tree),
779 or for a library call it is an identifier node for the subroutine name.
780 SIZE is the number of bytes of arguments passed on the stack.
782 On the 80386, the RTD insn may be used to pop them if the number
783 of args is fixed, but if the number is variable then the caller
784 must pop them all. RTD can't be used for library calls now
785 because the library is compiled with the Unix compiler.
786 Use of RTD is a selectable option, since it is incompatible with
787 standard Unix calling sequences. If the option is not selected,
788 the caller must always pop the args.
790 The attribute stdcall is equivalent to RTD on a per module basis. */
793 ix86_return_pops_args (fundecl
, funtype
, size
)
798 int rtd
= TARGET_RTD
&& (!fundecl
|| TREE_CODE (fundecl
) != IDENTIFIER_NODE
);
800 /* Cdecl functions override -mrtd, and never pop the stack. */
801 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype
))) {
803 /* Stdcall functions will pop the stack if not variable args. */
804 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype
)))
808 && (TYPE_ARG_TYPES (funtype
) == NULL_TREE
809 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype
)))
814 /* Lose any fake structure return argument. */
815 if (aggregate_value_p (TREE_TYPE (funtype
)))
816 return GET_MODE_SIZE (Pmode
);
821 /* Argument support functions. */
823 /* Initialize a variable CUM of type CUMULATIVE_ARGS
824 for a call to a function whose data type is FNTYPE.
825 For a library call, FNTYPE is 0. */
828 init_cumulative_args (cum
, fntype
, libname
)
829 CUMULATIVE_ARGS
*cum
; /* Argument info to initialize */
830 tree fntype
; /* tree ptr for function decl */
831 rtx libname
; /* SYMBOL_REF of library name or 0 */
833 static CUMULATIVE_ARGS zero_cum
;
834 tree param
, next_param
;
836 if (TARGET_DEBUG_ARG
)
838 fprintf (stderr
, "\ninit_cumulative_args (");
840 fprintf (stderr
, "fntype code = %s, ret code = %s",
841 tree_code_name
[(int) TREE_CODE (fntype
)],
842 tree_code_name
[(int) TREE_CODE (TREE_TYPE (fntype
))]);
844 fprintf (stderr
, "no fntype");
847 fprintf (stderr
, ", libname = %s", XSTR (libname
, 0));
852 /* Set up the number of registers to use for passing arguments. */
853 cum
->nregs
= ix86_regparm
;
856 tree attr
= lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype
));
859 cum
->nregs
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr
)));
862 /* Determine if this function has variable arguments. This is
863 indicated by the last argument being 'void_type_mode' if there
864 are no variable arguments. If there are variable arguments, then
865 we won't pass anything in registers */
869 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
870 param
!= 0; param
= next_param
)
872 next_param
= TREE_CHAIN (param
);
873 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
878 if (TARGET_DEBUG_ARG
)
879 fprintf (stderr
, ", nregs=%d )\n", cum
->nregs
);
884 /* Update the data in CUM to advance over an argument
885 of mode MODE and data type TYPE.
886 (TYPE is null for libcalls where that information may not be available.) */
889 function_arg_advance (cum
, mode
, type
, named
)
890 CUMULATIVE_ARGS
*cum
; /* current arg information */
891 enum machine_mode mode
; /* current arg mode */
892 tree type
; /* type of the argument or 0 if lib support */
893 int named
; /* whether or not the argument was named */
896 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
897 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
899 if (TARGET_DEBUG_ARG
)
901 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
902 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
917 /* Define where to put the arguments to a function.
918 Value is zero to push the argument on the stack,
919 or a hard register in which to store the argument.
921 MODE is the argument's machine mode.
922 TYPE is the data type of the argument (as a tree).
923 This is null for libcalls where that information may
925 CUM is a variable of type CUMULATIVE_ARGS which gives info about
926 the preceding args and about the function being called.
927 NAMED is nonzero if this argument is a named parameter
928 (otherwise it is an extra parameter matching an ellipsis). */
931 function_arg (cum
, mode
, type
, named
)
932 CUMULATIVE_ARGS
*cum
; /* current arg information */
933 enum machine_mode mode
; /* current arg mode */
934 tree type
; /* type of the argument or 0 if lib support */
935 int named
; /* != 0 for normal args, == 0 for ... args */
939 = (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
940 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
944 /* For now, pass fp/complex values on the stack. */
953 if (words
<= cum
->nregs
)
954 ret
= gen_rtx_REG (mode
, cum
->regno
);
958 if (TARGET_DEBUG_ARG
)
961 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
962 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
965 fprintf (stderr
, ", reg=%%e%s", reg_names
[ REGNO(ret
) ]);
967 fprintf (stderr
, ", stack");
969 fprintf (stderr
, " )\n");
975 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
976 reference and a constant. */
979 symbolic_operand (op
, mode
)
981 enum machine_mode mode ATTRIBUTE_UNUSED
;
983 switch (GET_CODE (op
))
991 if (GET_CODE (op
) == SYMBOL_REF
992 || GET_CODE (op
) == LABEL_REF
993 || (GET_CODE (op
) == UNSPEC
995 && XINT (op
, 1) <= 7))
997 if (GET_CODE (op
) != PLUS
998 || GET_CODE (XEXP (op
, 1)) != CONST_INT
)
1002 if (GET_CODE (op
) == SYMBOL_REF
1003 || GET_CODE (op
) == LABEL_REF
)
1005 /* Only @GOTOFF gets offsets. */
1006 if (GET_CODE (op
) != UNSPEC
1007 || XINT (op
, 1) != 7)
1010 op
= XVECEXP (op
, 0, 0);
1011 if (GET_CODE (op
) == SYMBOL_REF
1012 || GET_CODE (op
) == LABEL_REF
)
1021 /* Return true if the operand contains a @GOT or @GOTOFF reference. */
1024 pic_symbolic_operand (op
, mode
)
1026 enum machine_mode mode ATTRIBUTE_UNUSED
;
1028 if (GET_CODE (op
) == CONST
)
1031 if (GET_CODE (op
) == UNSPEC
)
1033 if (GET_CODE (op
) != PLUS
1034 || GET_CODE (XEXP (op
, 1)) != CONST_INT
)
1037 if (GET_CODE (op
) == UNSPEC
)
1043 /* Test for a valid operand for a call instruction. Don't allow the
1044 arg pointer register or virtual regs since they may decay into
1045 reg + const, which the patterns can't handle. */
1048 call_insn_operand (op
, mode
)
1050 enum machine_mode mode ATTRIBUTE_UNUSED
;
1052 if (GET_CODE (op
) != MEM
)
1056 /* Disallow indirect through a virtual register. This leads to
1057 compiler aborts when trying to eliminate them. */
1058 if (GET_CODE (op
) == REG
1059 && (op
== arg_pointer_rtx
1060 || op
== frame_pointer_rtx
1061 || (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1062 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
1065 /* Disallow `call 1234'. Due to varying assembler lameness this
1066 gets either rejected or translated to `call .+1234'. */
1067 if (GET_CODE (op
) == CONST_INT
)
1070 /* Otherwise we can allow any general_operand in the address. */
1071 return general_operand (op
, Pmode
);
1074 /* Like call_insn_operand but allow (mem (symbol_ref ...)) even if pic. */
1077 expander_call_insn_operand (op
, mode
)
1079 enum machine_mode mode
;
1081 if (GET_CODE (op
) == MEM
1082 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
)
1085 return call_insn_operand (op
, mode
);
1089 constant_call_address_operand (op
, mode
)
1091 enum machine_mode mode ATTRIBUTE_UNUSED
;
1093 return GET_CODE (op
) == MEM
&&
1094 CONSTANT_ADDRESS_P (XEXP (op
, 0)) &&
1095 GET_CODE (XEXP (op
, 0)) != CONST_INT
;
1098 /* Match exactly zero and one. */
1101 const0_operand (op
, mode
)
1103 enum machine_mode mode
;
1105 return op
== CONST0_RTX (mode
);
1109 const1_operand (op
, mode
)
1111 enum machine_mode mode ATTRIBUTE_UNUSED
;
1113 return op
== const1_rtx
;
1116 /* Match 2, 4, or 8. Used for leal multiplicands. */
1119 const248_operand (op
, mode
)
1121 enum machine_mode mode ATTRIBUTE_UNUSED
;
1123 return (GET_CODE (op
) == CONST_INT
1124 && (INTVAL (op
) == 2 || INTVAL (op
) == 4 || INTVAL (op
) == 8));
1127 /* True if this is a constant appropriate for an increment or decremenmt. */
1130 incdec_operand (op
, mode
)
1132 enum machine_mode mode
;
1134 if (op
== const1_rtx
|| op
== constm1_rtx
)
1136 if (GET_CODE (op
) != CONST_INT
)
1138 if (mode
== SImode
&& INTVAL (op
) == (HOST_WIDE_INT
) 0xffffffff)
1140 if (mode
== HImode
&& INTVAL (op
) == (HOST_WIDE_INT
) 0xffff)
1142 if (mode
== QImode
&& INTVAL (op
) == (HOST_WIDE_INT
) 0xff)
1147 /* Return false if this is the stack pointer, or any other fake
1148 register eliminable to the stack pointer. Otherwise, this is
1151 This is used to prevent esp from being used as an index reg.
1152 Which would only happen in pathological cases. */
1155 reg_no_sp_operand (op
, mode
)
1157 enum machine_mode mode
;
1160 if (GET_CODE (t
) == SUBREG
)
1162 if (t
== stack_pointer_rtx
|| t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
)
1165 return register_operand (op
, mode
);
1168 /* Return false if this is any eliminable register. Otherwise
1172 general_no_elim_operand (op
, mode
)
1174 enum machine_mode mode
;
1177 if (GET_CODE (t
) == SUBREG
)
1179 if (t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
1180 || t
== virtual_incoming_args_rtx
|| t
== virtual_stack_vars_rtx
1181 || t
== virtual_stack_dynamic_rtx
)
1184 return general_operand (op
, mode
);
1187 /* Return false if this is any eliminable register. Otherwise
1188 register_operand or const_int. */
1191 nonmemory_no_elim_operand (op
, mode
)
1193 enum machine_mode mode
;
1196 if (GET_CODE (t
) == SUBREG
)
1198 if (t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
1199 || t
== virtual_incoming_args_rtx
|| t
== virtual_stack_vars_rtx
1200 || t
== virtual_stack_dynamic_rtx
)
1203 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
1206 /* Return true if op is a Q_REGS class register. */
1209 q_regs_operand (op
, mode
)
1211 enum machine_mode mode
;
1213 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1215 if (GET_CODE (op
) == SUBREG
)
1216 op
= SUBREG_REG (op
);
1217 return QI_REG_P (op
);
1220 /* Return true if op is a NON_Q_REGS class register. */
1223 non_q_regs_operand (op
, mode
)
1225 enum machine_mode mode
;
1227 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1229 if (GET_CODE (op
) == SUBREG
)
1230 op
= SUBREG_REG (op
);
1231 return NON_QI_REG_P (op
);
1234 /* Return 1 if OP is a comparison operator that can use the condition code
1235 generated by a logical operation, which characteristicly does not set
1236 overflow or carry. To be used with CCNOmode. */
1239 no_comparison_operator (op
, mode
)
1241 enum machine_mode mode
;
1243 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1244 && GET_RTX_CLASS (GET_CODE (op
)) == '<'
1245 && GET_CODE (op
) != LE
1246 && GET_CODE (op
) != GT
);
1249 /* Return 1 if OP is a comparison operator that can be issued by fcmov. */
1252 fcmov_comparison_operator (op
, mode
)
1254 enum machine_mode mode
;
1256 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1257 && GET_RTX_CLASS (GET_CODE (op
)) == '<'
1258 && GET_CODE (op
) == unsigned_condition (GET_CODE (op
)));
1261 /* Return 1 if OP is a binary operator that can be promoted to wider mode. */
1264 promotable_binary_operator (op
, mode
)
1266 enum machine_mode mode ATTRIBUTE_UNUSED
;
1268 switch (GET_CODE (op
))
1271 /* Modern CPUs have same latency for HImode and SImode multiply,
1272 but 386 and 486 do HImode multiply faster. */
1273 return ix86_cpu
> PROCESSOR_I486
;
1285 /* Nearly general operand, but accept any const_double, since we wish
1286 to be able to drop them into memory rather than have them get pulled
1290 cmp_fp_expander_operand (op
, mode
)
1292 enum machine_mode mode
;
1294 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
1296 if (GET_CODE (op
) == CONST_DOUBLE
)
1298 return general_operand (op
, mode
);
1301 /* Match an SI or HImode register for a zero_extract. */
1304 ext_register_operand (op
, mode
)
1306 enum machine_mode mode ATTRIBUTE_UNUSED
;
1308 if (GET_MODE (op
) != SImode
&& GET_MODE (op
) != HImode
)
1310 return register_operand (op
, VOIDmode
);
1313 /* Return 1 if this is a valid binary floating-point operation.
1314 OP is the expression matched, and MODE is its mode. */
1317 binary_fp_operator (op
, mode
)
1319 enum machine_mode mode
;
1321 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
1324 switch (GET_CODE (op
))
1330 return GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
;
1338 mult_operator(op
, mode
)
1340 enum machine_mode mode ATTRIBUTE_UNUSED
;
1342 return GET_CODE (op
) == MULT
;
1346 div_operator(op
, mode
)
1348 enum machine_mode mode ATTRIBUTE_UNUSED
;
1350 return GET_CODE (op
) == DIV
;
1354 arith_or_logical_operator (op
, mode
)
1356 enum machine_mode mode
;
1358 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1359 && (GET_RTX_CLASS (GET_CODE (op
)) == 'c'
1360 || GET_RTX_CLASS (GET_CODE (op
)) == '2'));
1363 /* Returns 1 if OP is memory operand with a displacement. */
1366 memory_displacement_operand (op
, mode
)
1368 enum machine_mode mode
;
1370 struct ix86_address parts
;
1372 if (! memory_operand (op
, mode
))
1375 if (! ix86_decompose_address (XEXP (op
, 0), &parts
))
1378 return parts
.disp
!= NULL_RTX
;
1381 /* To avoid problems when jump re-emits comparisons like testqi_ext_0,
1382 re-recognize the operand to avoid a copy_to_mode_reg that will fail.
1384 ??? It seems likely that this will only work because cmpsi is an
1385 expander, and no actual insns use this. */
1388 cmpsi_operand (op
, mode
)
1390 enum machine_mode mode
;
1392 if (general_operand (op
, mode
))
1395 if (GET_CODE (op
) == AND
1396 && GET_MODE (op
) == SImode
1397 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTRACT
1398 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
1399 && GET_CODE (XEXP (XEXP (op
, 0), 2)) == CONST_INT
1400 && INTVAL (XEXP (XEXP (op
, 0), 1)) == 8
1401 && INTVAL (XEXP (XEXP (op
, 0), 2)) == 8
1402 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
1408 /* Returns 1 if OP is memory operand that can not be represented by the
1412 long_memory_operand (op
, mode
)
1414 enum machine_mode mode
;
1416 if (! memory_operand (op
, mode
))
1419 return memory_address_length (op
) != 0;
1422 /* Return nonzero if the rtx is known aligned. */
1425 aligned_operand (op
, mode
)
1427 enum machine_mode mode
;
1429 struct ix86_address parts
;
1431 if (!general_operand (op
, mode
))
1434 /* Registers and immediate operands are always "aligned". */
1435 if (GET_CODE (op
) != MEM
)
1438 /* Don't even try to do any aligned optimizations with volatiles. */
1439 if (MEM_VOLATILE_P (op
))
1444 /* Pushes and pops are only valid on the stack pointer. */
1445 if (GET_CODE (op
) == PRE_DEC
1446 || GET_CODE (op
) == POST_INC
)
1449 /* Decode the address. */
1450 if (! ix86_decompose_address (op
, &parts
))
1453 /* Look for some component that isn't known to be aligned. */
1457 && REGNO_POINTER_ALIGN (REGNO (parts
.index
)) < 4)
1462 if (REGNO_POINTER_ALIGN (REGNO (parts
.base
)) < 4)
1467 if (GET_CODE (parts
.disp
) != CONST_INT
1468 || (INTVAL (parts
.disp
) & 3) != 0)
1472 /* Didn't find one -- this must be an aligned address. */
1476 /* Return true if the constant is something that can be loaded with
1477 a special instruction. Only handle 0.0 and 1.0; others are less
1481 standard_80387_constant_p (x
)
1484 if (GET_CODE (x
) != CONST_DOUBLE
)
1487 #if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC)
1493 if (setjmp (handler
))
1496 set_float_handler (handler
);
1497 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1498 is0
= REAL_VALUES_EQUAL (d
, dconst0
) && !REAL_VALUE_MINUS_ZERO (d
);
1499 is1
= REAL_VALUES_EQUAL (d
, dconst1
);
1500 set_float_handler (NULL_PTR
);
1508 /* Note that on the 80387, other constants, such as pi,
1509 are much slower to load as standard constants
1510 than to load from doubles in memory! */
1511 /* ??? Not true on K6: all constants are equal cost. */
1518 /* Returns 1 if OP contains a symbol reference */
1521 symbolic_reference_mentioned_p (op
)
1524 register const char *fmt
;
1527 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1530 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
1531 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
1537 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1538 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
1542 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
1549 /* Return 1 if it is appropriate to emit `ret' instructions in the
1550 body of a function. Do this only if the epilogue is simple, needing a
1551 couple of insns. Prior to reloading, we can't tell how many registers
1552 must be saved, so return 0 then. Return 0 if there is no frame
1553 marker to de-allocate.
1555 If NON_SAVING_SETJMP is defined and true, then it is not possible
1556 for the epilogue to be simple, so return 0. This is a special case
1557 since NON_SAVING_SETJMP will not cause regs_ever_live to change
1558 until final, but jump_optimize may need to know sooner if a
1562 ix86_can_use_return_insn_p ()
1564 HOST_WIDE_INT tsize
;
1567 #ifdef NON_SAVING_SETJMP
1568 if (NON_SAVING_SETJMP
&& current_function_calls_setjmp
)
1571 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
1572 if (profile_block_flag
== 2)
1576 if (! reload_completed
|| frame_pointer_needed
)
1579 /* Don't allow more than 32 pop, since that's all we can do
1580 with one instruction. */
1581 if (current_function_pops_args
1582 && current_function_args_size
>= 32768)
1585 tsize
= ix86_compute_frame_size (get_frame_size (), &nregs
, NULL
, NULL
);
1586 return tsize
== 0 && nregs
== 0;
1589 static char *pic_label_name
;
1590 static int pic_label_output
;
1591 static char *global_offset_table_name
;
1593 /* This function generates code for -fpic that loads %ebx with
1594 the return address of the caller and then returns. */
1597 asm_output_function_prefix (file
, name
)
1599 const char *name ATTRIBUTE_UNUSED
;
1602 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
1603 || current_function_uses_const_pool
);
1604 xops
[0] = pic_offset_table_rtx
;
1605 xops
[1] = stack_pointer_rtx
;
1607 /* Deep branch prediction favors having a return for every call. */
1608 if (pic_reg_used
&& TARGET_DEEP_BRANCH_PREDICTION
)
1610 if (!pic_label_output
)
1612 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
1613 internal (non-global) label that's being emitted, it didn't make
1614 sense to have .type information for local labels. This caused
1615 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
1616 me debug info for a label that you're declaring non-global?) this
1617 was changed to call ASM_OUTPUT_LABEL() instead. */
1619 ASM_OUTPUT_LABEL (file
, pic_label_name
);
1621 xops
[1] = gen_rtx_MEM (SImode
, xops
[1]);
1622 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops
);
1623 output_asm_insn ("ret", xops
);
1625 pic_label_output
= 1;
1631 load_pic_register ()
1635 if (global_offset_table_name
== NULL
)
1637 global_offset_table_name
=
1638 ggc_alloc_string ("_GLOBAL_OFFSET_TABLE_", 21);
1639 ggc_add_string_root (&global_offset_table_name
, 1);
1641 gotsym
= gen_rtx_SYMBOL_REF (Pmode
, global_offset_table_name
);
1643 if (TARGET_DEEP_BRANCH_PREDICTION
)
1645 if (pic_label_name
== NULL
)
1647 pic_label_name
= ggc_alloc_string (NULL
, 32);
1648 ggc_add_string_root (&pic_label_name
, 1);
1649 ASM_GENERATE_INTERNAL_LABEL (pic_label_name
, "LPR", 0);
1651 pclab
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, pic_label_name
));
1655 pclab
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
1658 emit_insn (gen_prologue_get_pc (pic_offset_table_rtx
, pclab
));
1660 if (! TARGET_DEEP_BRANCH_PREDICTION
)
1661 emit_insn (gen_popsi1 (pic_offset_table_rtx
));
1663 emit_insn (gen_prologue_set_got (pic_offset_table_rtx
, gotsym
, pclab
));
1666 /* Generate an SImode "push" pattern for input ARG. */
1672 return gen_rtx_SET (VOIDmode
,
1673 gen_rtx_MEM (SImode
,
1674 gen_rtx_PRE_DEC (SImode
,
1675 stack_pointer_rtx
)),
1679 /* Return number of registers to be saved on the stack. */
1685 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
1686 || current_function_uses_const_pool
);
1687 int limit
= (frame_pointer_needed
1688 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
1691 for (regno
= limit
- 1; regno
>= 0; regno
--)
1692 if ((regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1693 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1700 /* Return the offset between two registers, one to be eliminated, and the other
1701 its replacement, at the start of a routine. */
1704 ix86_initial_elimination_offset (from
, to
)
1711 /* Stack grows downward:
1717 saved frame pointer if frame_pointer_needed
1718 <- HARD_FRAME_POINTER
1728 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1729 /* Skip saved PC and previous frame pointer.
1730 Executed only when frame_pointer_needed. */
1732 else if (from
== FRAME_POINTER_REGNUM
1733 && to
== HARD_FRAME_POINTER_REGNUM
)
1735 ix86_compute_frame_size (get_frame_size (), &nregs
, &padding1
, (int *)0);
1736 padding1
+= nregs
* UNITS_PER_WORD
;
1741 /* ARG_POINTER or FRAME_POINTER to STACK_POINTER elimination. */
1742 int frame_size
= frame_pointer_needed
? 8 : 4;
1743 HOST_WIDE_INT tsize
= ix86_compute_frame_size (get_frame_size (),
1744 &nregs
, &padding1
, (int *)0);
1747 if (to
!= STACK_POINTER_REGNUM
)
1749 else if (from
== ARG_POINTER_REGNUM
)
1750 return tsize
+ nregs
* UNITS_PER_WORD
+ frame_size
;
1751 else if (from
!= FRAME_POINTER_REGNUM
)
1754 return tsize
- padding1
;
1758 /* Compute the size of local storage taking into consideration the
1759 desired stack alignment which is to be maintained. Also determine
1760 the number of registers saved below the local storage.
1762 PADDING1 returns padding before stack frame and PADDING2 returns
1763 padding after stack frame;
1766 static HOST_WIDE_INT
1767 ix86_compute_frame_size (size
, nregs_on_stack
, rpadding1
, rpadding2
)
1769 int *nregs_on_stack
;
1776 HOST_WIDE_INT total_size
;
1777 int stack_alignment_needed
= cfun
->stack_alignment_needed
/ BITS_PER_UNIT
;
1779 int preferred_alignment
= cfun
->preferred_stack_boundary
/ BITS_PER_UNIT
;
1781 nregs
= ix86_nsaved_regs ();
1784 offset
= frame_pointer_needed
? 8 : 4;
1786 /* Do some sanity checking of stack_alignment_needed and preferred_alignment,
1787 since i386 port is the only using those features that may break easilly. */
1789 if (size
&& !stack_alignment_needed
)
1791 if (!size
&& stack_alignment_needed
!= STACK_BOUNDARY
/ BITS_PER_UNIT
)
1793 if (preferred_alignment
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
1795 if (preferred_alignment
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
1797 if (stack_alignment_needed
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
1800 if (stack_alignment_needed
< 4)
1801 stack_alignment_needed
= 4;
1803 offset
+= nregs
* UNITS_PER_WORD
;
1805 total_size
+= offset
;
1807 /* Align start of frame for local function. */
1808 padding1
= ((offset
+ stack_alignment_needed
- 1)
1809 & -stack_alignment_needed
) - offset
;
1810 total_size
+= padding1
;
1812 /* Align stack boundary. */
1813 padding2
= ((total_size
+ preferred_alignment
- 1)
1814 & -preferred_alignment
) - total_size
;
1817 *nregs_on_stack
= nregs
;
1819 *rpadding1
= padding1
;
1821 *rpadding2
= padding2
;
1823 return size
+ padding1
+ padding2
;
1826 /* Emit code to save registers in the prologue. */
1829 ix86_emit_save_regs ()
1834 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
1835 || current_function_uses_const_pool
);
1836 limit
= (frame_pointer_needed
1837 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
1839 for (regno
= limit
- 1; regno
>= 0; regno
--)
1840 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
1841 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1843 insn
= emit_insn (gen_push (gen_rtx_REG (SImode
, regno
)));
1844 RTX_FRAME_RELATED_P (insn
) = 1;
1848 /* Expand the prologue into a bunch of separate insns. */
1851 ix86_expand_prologue ()
1853 HOST_WIDE_INT tsize
= ix86_compute_frame_size (get_frame_size (), (int *)0, (int *)0,
1856 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
1857 || current_function_uses_const_pool
);
1859 /* Note: AT&T enter does NOT have reversed args. Enter is probably
1860 slower on all targets. Also sdb doesn't like it. */
1862 if (frame_pointer_needed
)
1864 insn
= emit_insn (gen_push (hard_frame_pointer_rtx
));
1865 RTX_FRAME_RELATED_P (insn
) = 1;
1867 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
1868 RTX_FRAME_RELATED_P (insn
) = 1;
1871 ix86_emit_save_regs ();
1875 else if (! TARGET_STACK_PROBE
|| tsize
< CHECK_STACK_LIMIT
)
1877 if (frame_pointer_needed
)
1878 insn
= emit_insn (gen_pro_epilogue_adjust_stack
1879 (stack_pointer_rtx
, stack_pointer_rtx
,
1880 GEN_INT (-tsize
), hard_frame_pointer_rtx
));
1882 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1884 RTX_FRAME_RELATED_P (insn
) = 1;
1888 /* ??? Is this only valid for Win32? */
1892 arg0
= gen_rtx_REG (SImode
, 0);
1893 emit_move_insn (arg0
, GEN_INT (tsize
));
1895 sym
= gen_rtx_MEM (FUNCTION_MODE
,
1896 gen_rtx_SYMBOL_REF (Pmode
, "_alloca"));
1897 insn
= emit_call_insn (gen_call (sym
, const0_rtx
));
1899 CALL_INSN_FUNCTION_USAGE (insn
)
1900 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, arg0
),
1901 CALL_INSN_FUNCTION_USAGE (insn
));
1904 #ifdef SUBTARGET_PROLOGUE
1909 load_pic_register ();
1911 /* If we are profiling, make sure no instructions are scheduled before
1912 the call to mcount. However, if -fpic, the above call will have
1914 if ((profile_flag
|| profile_block_flag
) && ! pic_reg_used
)
1915 emit_insn (gen_blockage ());
1918 /* Emit code to add TSIZE to esp value. Use POP instruction when
1922 ix86_emit_epilogue_esp_adjustment (tsize
)
1925 /* Intel's docs say that for 4 or 8 bytes of stack frame one should
1926 use `pop' and not `add'. */
1927 int use_pop
= tsize
== 4;
1930 /* Use two pops only for the Pentium processors. */
1931 if (tsize
== 8 && !TARGET_386
&& !TARGET_486
)
1933 rtx retval
= current_function_return_rtx
;
1935 edx
= gen_rtx_REG (SImode
, 1);
1937 /* This case is a bit more complex. Since we cannot pop into
1938 %ecx twice we need a second register. But this is only
1939 available if the return value is not of DImode in which
1940 case the %edx register is not available. */
1941 use_pop
= (retval
== NULL
1942 || !reg_overlap_mentioned_p (edx
, retval
));
1947 ecx
= gen_rtx_REG (SImode
, 2);
1949 /* We have to prevent the two pops here from being scheduled.
1950 GCC otherwise would try in some situation to put other
1951 instructions in between them which has a bad effect. */
1952 emit_insn (gen_blockage ());
1953 emit_insn (gen_popsi1 (ecx
));
1955 emit_insn (gen_popsi1 (edx
));
1959 /* If a frame pointer is present, we must be sure to tie the sp
1960 to the fp so that we don't mis-schedule. */
1961 if (frame_pointer_needed
)
1962 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
1965 hard_frame_pointer_rtx
));
1967 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1972 /* Emit code to restore saved registers using MOV insns. First register
1973 is restored from POINTER + OFFSET. */
1975 ix86_emit_restore_regs_using_mov (pointer
, offset
)
1980 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
1981 || current_function_uses_const_pool
);
1982 int limit
= (frame_pointer_needed
1983 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
);
1985 for (regno
= 0; regno
< limit
; regno
++)
1986 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
1987 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1989 emit_move_insn (gen_rtx_REG (SImode
, regno
),
1990 adj_offsettable_operand (gen_rtx_MEM (SImode
,
1997 /* Restore function stack, frame, and registers. */
2000 ix86_expand_epilogue ()
2005 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
2006 || current_function_uses_const_pool
);
2007 int sp_valid
= !frame_pointer_needed
|| current_function_sp_is_unchanging
;
2008 HOST_WIDE_INT offset
;
2009 HOST_WIDE_INT tsize
= ix86_compute_frame_size (get_frame_size (), &nregs
,
2010 (int *)0, (int *)0);
2013 /* Calculate start of saved registers relative to ebp. */
2014 offset
= -nregs
* UNITS_PER_WORD
;
2016 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
2017 if (profile_block_flag
== 2)
2019 FUNCTION_BLOCK_PROFILER_EXIT
;
2023 /* If we're only restoring one register and sp is not valid then
2024 using a move instruction to restore the register since it's
2025 less work than reloading sp and popping the register.
2027 The default code result in stack adjustment using add/lea instruction,
2028 while this code results in LEAVE instruction (or discrete equivalent),
2029 so it is profitable in some other cases as well. Especially when there
2030 are no registers to restore. We also use this code when TARGET_USE_LEAVE
2031 and there is exactly one register to pop. This heruistic may need some
2032 tuning in future. */
2033 if ((!sp_valid
&& nregs
<= 1)
2034 || (frame_pointer_needed
&& !nregs
&& tsize
)
2035 || (frame_pointer_needed
&& TARGET_USE_LEAVE
&& !optimize_size
2038 /* Restore registers. We can use ebp or esp to address the memory
2039 locations. If both are available, default to ebp, since offsets
2040 are known to be small. Only exception is esp pointing directly to the
2041 end of block of saved registers, where we may simplify addressing
2044 if (!frame_pointer_needed
|| (sp_valid
&& !tsize
))
2045 ix86_emit_restore_regs_using_mov (stack_pointer_rtx
, tsize
);
2047 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx
, offset
);
2049 if (!frame_pointer_needed
)
2050 ix86_emit_epilogue_esp_adjustment (tsize
+ nregs
* UNITS_PER_WORD
);
2051 /* If not an i386, mov & pop is faster than "leave". */
2052 else if (TARGET_USE_LEAVE
|| optimize_size
)
2053 emit_insn (gen_leave ());
2056 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
2057 hard_frame_pointer_rtx
,
2059 hard_frame_pointer_rtx
));
2060 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
2065 /* First step is to deallocate the stack frame so that we can
2066 pop the registers. */
2069 if (!frame_pointer_needed
)
2071 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
2072 hard_frame_pointer_rtx
,
2074 hard_frame_pointer_rtx
));
2077 ix86_emit_epilogue_esp_adjustment (tsize
);
2079 for (regno
= 0; regno
< STACK_POINTER_REGNUM
; regno
++)
2080 if ((regs_ever_live
[regno
] && !call_used_regs
[regno
])
2081 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
2082 emit_insn (gen_popsi1 (gen_rtx_REG (SImode
, regno
)));
2085 if (current_function_pops_args
&& current_function_args_size
)
2087 rtx popc
= GEN_INT (current_function_pops_args
);
2089 /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If
2090 asked to pop more, pop return address, do explicit add, and jump
2091 indirectly to the caller. */
2093 if (current_function_pops_args
>= 32768)
2095 rtx ecx
= gen_rtx_REG (SImode
, 2);
2097 emit_insn (gen_popsi1 (ecx
));
2098 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, popc
));
2099 emit_indirect_jump (ecx
);
2102 emit_jump_insn (gen_return_pop_internal (popc
));
2105 emit_jump_insn (gen_return_internal ());
2108 /* Extract the parts of an RTL expression that is a valid memory address
2109 for an instruction. Return false if the structure of the address is
2113 ix86_decompose_address (addr
, out
)
2115 struct ix86_address
*out
;
2117 rtx base
= NULL_RTX
;
2118 rtx index
= NULL_RTX
;
2119 rtx disp
= NULL_RTX
;
2120 HOST_WIDE_INT scale
= 1;
2121 rtx scale_rtx
= NULL_RTX
;
2123 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == SUBREG
)
2125 else if (GET_CODE (addr
) == PLUS
)
2127 rtx op0
= XEXP (addr
, 0);
2128 rtx op1
= XEXP (addr
, 1);
2129 enum rtx_code code0
= GET_CODE (op0
);
2130 enum rtx_code code1
= GET_CODE (op1
);
2132 if (code0
== REG
|| code0
== SUBREG
)
2134 if (code1
== REG
|| code1
== SUBREG
)
2135 index
= op0
, base
= op1
; /* index + base */
2137 base
= op0
, disp
= op1
; /* base + displacement */
2139 else if (code0
== MULT
)
2141 index
= XEXP (op0
, 0);
2142 scale_rtx
= XEXP (op0
, 1);
2143 if (code1
== REG
|| code1
== SUBREG
)
2144 base
= op1
; /* index*scale + base */
2146 disp
= op1
; /* index*scale + disp */
2148 else if (code0
== PLUS
&& GET_CODE (XEXP (op0
, 0)) == MULT
)
2150 index
= XEXP (XEXP (op0
, 0), 0); /* index*scale + base + disp */
2151 scale_rtx
= XEXP (XEXP (op0
, 0), 1);
2152 base
= XEXP (op0
, 1);
2155 else if (code0
== PLUS
)
2157 index
= XEXP (op0
, 0); /* index + base + disp */
2158 base
= XEXP (op0
, 1);
2164 else if (GET_CODE (addr
) == MULT
)
2166 index
= XEXP (addr
, 0); /* index*scale */
2167 scale_rtx
= XEXP (addr
, 1);
2169 else if (GET_CODE (addr
) == ASHIFT
)
2173 /* We're called for lea too, which implements ashift on occasion. */
2174 index
= XEXP (addr
, 0);
2175 tmp
= XEXP (addr
, 1);
2176 if (GET_CODE (tmp
) != CONST_INT
)
2178 scale
= INTVAL (tmp
);
2179 if ((unsigned HOST_WIDE_INT
) scale
> 3)
2184 disp
= addr
; /* displacement */
2186 /* Extract the integral value of scale. */
2189 if (GET_CODE (scale_rtx
) != CONST_INT
)
2191 scale
= INTVAL (scale_rtx
);
2194 /* Allow arg pointer and stack pointer as index if there is not scaling */
2195 if (base
&& index
&& scale
== 1
2196 && (index
== arg_pointer_rtx
|| index
== frame_pointer_rtx
2197 || index
== stack_pointer_rtx
))
2204 /* Special case: %ebp cannot be encoded as a base without a displacement. */
2205 if ((base
== hard_frame_pointer_rtx
2206 || base
== frame_pointer_rtx
2207 || base
== arg_pointer_rtx
) && !disp
)
2210 /* Special case: on K6, [%esi] makes the instruction vector decoded.
2211 Avoid this by transforming to [%esi+0]. */
2212 if (ix86_cpu
== PROCESSOR_K6
&& !optimize_size
2213 && base
&& !index
&& !disp
2215 && REGNO_REG_CLASS (REGNO (base
)) == SIREG
)
2218 /* Special case: encode reg+reg instead of reg*2. */
2219 if (!base
&& index
&& scale
&& scale
== 2)
2220 base
= index
, scale
= 1;
2222 /* Special case: scaling cannot be encoded without base or displacement. */
2223 if (!base
&& !disp
&& index
&& scale
!= 1)
2234 /* Determine if a given CONST RTX is a valid memory displacement
2238 legitimate_pic_address_disp_p (disp
)
2241 if (GET_CODE (disp
) != CONST
)
2243 disp
= XEXP (disp
, 0);
2245 if (GET_CODE (disp
) == PLUS
)
2247 if (GET_CODE (XEXP (disp
, 1)) != CONST_INT
)
2249 disp
= XEXP (disp
, 0);
2252 if (GET_CODE (disp
) != UNSPEC
2253 || XVECLEN (disp
, 0) != 1)
2256 /* Must be @GOT or @GOTOFF. */
2257 if (XINT (disp
, 1) != 6
2258 && XINT (disp
, 1) != 7)
2261 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2262 && GET_CODE (XVECEXP (disp
, 0, 0)) != LABEL_REF
)
2268 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
2269 memory address for an instruction. The MODE argument is the machine mode
2270 for the MEM expression that wants to use this address.
2272 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2273 convert common non-canonical forms to canonical form so that they will
2277 legitimate_address_p (mode
, addr
, strict
)
2278 enum machine_mode mode
;
2282 struct ix86_address parts
;
2283 rtx base
, index
, disp
;
2284 HOST_WIDE_INT scale
;
2285 const char *reason
= NULL
;
2286 rtx reason_rtx
= NULL_RTX
;
2288 if (TARGET_DEBUG_ADDR
)
2291 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2292 GET_MODE_NAME (mode
), strict
);
2296 if (! ix86_decompose_address (addr
, &parts
))
2298 reason
= "decomposition failed";
2303 index
= parts
.index
;
2305 scale
= parts
.scale
;
2307 /* Validate base register.
2309 Don't allow SUBREG's here, it can lead to spill failures when the base
2310 is one word out of a two word structure, which is represented internally
2317 if (GET_CODE (base
) != REG
)
2319 reason
= "base is not a register";
2323 if (GET_MODE (base
) != Pmode
)
2325 reason
= "base is not in Pmode";
2329 if ((strict
&& ! REG_OK_FOR_BASE_STRICT_P (base
))
2330 || (! strict
&& ! REG_OK_FOR_BASE_NONSTRICT_P (base
)))
2332 reason
= "base is not valid";
2337 /* Validate index register.
2339 Don't allow SUBREG's here, it can lead to spill failures when the index
2340 is one word out of a two word structure, which is represented internally
2347 if (GET_CODE (index
) != REG
)
2349 reason
= "index is not a register";
2353 if (GET_MODE (index
) != Pmode
)
2355 reason
= "index is not in Pmode";
2359 if ((strict
&& ! REG_OK_FOR_INDEX_STRICT_P (index
))
2360 || (! strict
&& ! REG_OK_FOR_INDEX_NONSTRICT_P (index
)))
2362 reason
= "index is not valid";
2367 /* Validate scale factor. */
2370 reason_rtx
= GEN_INT (scale
);
2373 reason
= "scale without index";
2377 if (scale
!= 2 && scale
!= 4 && scale
!= 8)
2379 reason
= "scale is not a valid multiplier";
2384 /* Validate displacement. */
2389 if (!CONSTANT_ADDRESS_P (disp
))
2391 reason
= "displacement is not constant";
2395 if (GET_CODE (disp
) == CONST_DOUBLE
)
2397 reason
= "displacement is a const_double";
2401 if (flag_pic
&& SYMBOLIC_CONST (disp
))
2403 if (! legitimate_pic_address_disp_p (disp
))
2405 reason
= "displacement is an invalid pic construct";
2409 /* Verify that a symbolic pic displacement includes
2410 the pic_offset_table_rtx register. */
2411 if (base
!= pic_offset_table_rtx
2412 && (index
!= pic_offset_table_rtx
|| scale
!= 1))
2414 reason
= "pic displacement against invalid base";
2418 else if (HALF_PIC_P ())
2420 if (! HALF_PIC_ADDRESS_P (disp
)
2421 || (base
!= NULL_RTX
|| index
!= NULL_RTX
))
2423 reason
= "displacement is an invalid half-pic reference";
2429 /* Everything looks valid. */
2430 if (TARGET_DEBUG_ADDR
)
2431 fprintf (stderr
, "Success.\n");
2435 if (TARGET_DEBUG_ADDR
)
2437 fprintf (stderr
, "Error: %s\n", reason
);
2438 debug_rtx (reason_rtx
);
2443 /* Return a legitimate reference for ORIG (an address) using the
2444 register REG. If REG is 0, a new pseudo is generated.
2446 There are two types of references that must be handled:
2448 1. Global data references must load the address from the GOT, via
2449 the PIC reg. An insn is emitted to do this load, and the reg is
2452 2. Static data references, constant pool addresses, and code labels
2453 compute the address as an offset from the GOT, whose base is in
2454 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to
2455 differentiate them from global data objects. The returned
2456 address is the PIC reg + an unspec constant.
2458 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2459 reg also appears in the address. */
2462 legitimize_pic_address (orig
, reg
)
2470 if (GET_CODE (addr
) == LABEL_REF
2471 || (GET_CODE (addr
) == SYMBOL_REF
2472 && (CONSTANT_POOL_ADDRESS_P (addr
)
2473 || SYMBOL_REF_FLAG (addr
))))
2475 /* This symbol may be referenced via a displacement from the PIC
2476 base address (@GOTOFF). */
2478 current_function_uses_pic_offset_table
= 1;
2479 new = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, addr
), 7);
2480 new = gen_rtx_CONST (VOIDmode
, new);
2481 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2485 emit_move_insn (reg
, new);
2489 else if (GET_CODE (addr
) == SYMBOL_REF
)
2491 /* This symbol must be referenced via a load from the
2492 Global Offset Table (@GOT). */
2494 current_function_uses_pic_offset_table
= 1;
2495 new = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, addr
), 6);
2496 new = gen_rtx_CONST (VOIDmode
, new);
2497 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2498 new = gen_rtx_MEM (Pmode
, new);
2499 RTX_UNCHANGING_P (new) = 1;
2502 reg
= gen_reg_rtx (Pmode
);
2503 emit_move_insn (reg
, new);
2508 if (GET_CODE (addr
) == CONST
)
2510 addr
= XEXP (addr
, 0);
2511 if (GET_CODE (addr
) == UNSPEC
)
2513 /* Check that the unspec is one of the ones we generate? */
2515 else if (GET_CODE (addr
) != PLUS
)
2518 if (GET_CODE (addr
) == PLUS
)
2520 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
2522 /* Check first to see if this is a constant offset from a @GOTOFF
2523 symbol reference. */
2524 if ((GET_CODE (op0
) == LABEL_REF
2525 || (GET_CODE (op0
) == SYMBOL_REF
2526 && (CONSTANT_POOL_ADDRESS_P (op0
)
2527 || SYMBOL_REF_FLAG (op0
))))
2528 && GET_CODE (op1
) == CONST_INT
)
2530 current_function_uses_pic_offset_table
= 1;
2531 new = gen_rtx_UNSPEC (VOIDmode
, gen_rtvec (1, op0
), 7);
2532 new = gen_rtx_PLUS (VOIDmode
, new, op1
);
2533 new = gen_rtx_CONST (VOIDmode
, new);
2534 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2538 emit_move_insn (reg
, new);
2544 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
2545 new = legitimize_pic_address (XEXP (addr
, 1),
2546 base
== reg
? NULL_RTX
: reg
);
2548 if (GET_CODE (new) == CONST_INT
)
2549 new = plus_constant (base
, INTVAL (new));
2552 if (GET_CODE (new) == PLUS
&& CONSTANT_P (XEXP (new, 1)))
2554 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new, 0));
2555 new = XEXP (new, 1);
2557 new = gen_rtx_PLUS (Pmode
, base
, new);
2565 /* Try machine-dependent ways of modifying an illegitimate address
2566 to be legitimate. If we find one, return the new, valid address.
2567 This macro is used in only one place: `memory_address' in explow.c.
2569 OLDX is the address as it was before break_out_memory_refs was called.
2570 In some cases it is useful to look at this to decide what needs to be done.
2572 MODE and WIN are passed so that this macro can use
2573 GO_IF_LEGITIMATE_ADDRESS.
2575 It is always safe for this macro to do nothing. It exists to recognize
2576 opportunities to optimize the output.
2578 For the 80386, we handle X+REG by loading X into a register R and
2579 using R+REG. R will go in a general reg and indexing will be used.
2580 However, if REG is a broken-out memory address or multiplication,
2581 nothing needs to be done because REG can certainly go in a general reg.
2583 When -fpic is used, special handling is needed for symbolic references.
2584 See comments by legitimize_pic_address in i386.c for details. */
2587 legitimize_address (x
, oldx
, mode
)
2589 register rtx oldx ATTRIBUTE_UNUSED
;
2590 enum machine_mode mode
;
2595 if (TARGET_DEBUG_ADDR
)
2597 fprintf (stderr
, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
2598 GET_MODE_NAME (mode
));
2602 if (flag_pic
&& SYMBOLIC_CONST (x
))
2603 return legitimize_pic_address (x
, 0);
2605 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2606 if (GET_CODE (x
) == ASHIFT
2607 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2608 && (log
= (unsigned)exact_log2 (INTVAL (XEXP (x
, 1)))) < 4)
2611 x
= gen_rtx_MULT (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
2612 GEN_INT (1 << log
));
2615 if (GET_CODE (x
) == PLUS
)
2617 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
2619 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
2620 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2621 && (log
= (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) < 4)
2624 XEXP (x
, 0) = gen_rtx_MULT (Pmode
,
2625 force_reg (Pmode
, XEXP (XEXP (x
, 0), 0)),
2626 GEN_INT (1 << log
));
2629 if (GET_CODE (XEXP (x
, 1)) == ASHIFT
2630 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2631 && (log
= (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1)))) < 4)
2634 XEXP (x
, 1) = gen_rtx_MULT (Pmode
,
2635 force_reg (Pmode
, XEXP (XEXP (x
, 1), 0)),
2636 GEN_INT (1 << log
));
2639 /* Put multiply first if it isn't already. */
2640 if (GET_CODE (XEXP (x
, 1)) == MULT
)
2642 rtx tmp
= XEXP (x
, 0);
2643 XEXP (x
, 0) = XEXP (x
, 1);
2648 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2649 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2650 created by virtual register instantiation, register elimination, and
2651 similar optimizations. */
2652 if (GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
2655 x
= gen_rtx_PLUS (Pmode
,
2656 gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
2657 XEXP (XEXP (x
, 1), 0)),
2658 XEXP (XEXP (x
, 1), 1));
2662 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2663 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2664 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2665 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2666 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2667 && CONSTANT_P (XEXP (x
, 1)))
2670 rtx other
= NULL_RTX
;
2672 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2674 constant
= XEXP (x
, 1);
2675 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2677 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2679 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2680 other
= XEXP (x
, 1);
2688 x
= gen_rtx_PLUS (Pmode
,
2689 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
2690 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2691 plus_constant (other
, INTVAL (constant
)));
2695 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
2698 if (GET_CODE (XEXP (x
, 0)) == MULT
)
2701 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
2704 if (GET_CODE (XEXP (x
, 1)) == MULT
)
2707 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
2711 && GET_CODE (XEXP (x
, 1)) == REG
2712 && GET_CODE (XEXP (x
, 0)) == REG
)
2715 if (flag_pic
&& SYMBOLIC_CONST (XEXP (x
, 1)))
2718 x
= legitimize_pic_address (x
, 0);
2721 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
2724 if (GET_CODE (XEXP (x
, 0)) == REG
)
2726 register rtx temp
= gen_reg_rtx (Pmode
);
2727 register rtx val
= force_operand (XEXP (x
, 1), temp
);
2729 emit_move_insn (temp
, val
);
2735 else if (GET_CODE (XEXP (x
, 1)) == REG
)
2737 register rtx temp
= gen_reg_rtx (Pmode
);
2738 register rtx val
= force_operand (XEXP (x
, 0), temp
);
2740 emit_move_insn (temp
, val
);
2750 /* Print an integer constant expression in assembler syntax. Addition
2751 and subtraction are the only arithmetic that may appear in these
2752 expressions. FILE is the stdio stream to write to, X is the rtx, and
2753 CODE is the operand print code from the output string. */
2756 output_pic_addr_const (file
, x
, code
)
2763 switch (GET_CODE (x
))
2773 assemble_name (file
, XSTR (x
, 0));
2774 if (code
== 'P' && ! SYMBOL_REF_FLAG (x
))
2775 fputs ("@PLT", file
);
2782 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
2783 assemble_name (asm_out_file
, buf
);
2787 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
2791 /* This used to output parentheses around the expression,
2792 but that does not work on the 386 (either ATT or BSD assembler). */
2793 output_pic_addr_const (file
, XEXP (x
, 0), code
);
2797 if (GET_MODE (x
) == VOIDmode
)
2799 /* We can use %d if the number is <32 bits and positive. */
2800 if (CONST_DOUBLE_HIGH (x
) || CONST_DOUBLE_LOW (x
) < 0)
2801 fprintf (file
, "0x%lx%08lx",
2802 (unsigned long) CONST_DOUBLE_HIGH (x
),
2803 (unsigned long) CONST_DOUBLE_LOW (x
));
2805 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
2808 /* We can't handle floating point constants;
2809 PRINT_OPERAND must handle them. */
2810 output_operand_lossage ("floating constant misused");
2814 /* Some assemblers need integer constants to appear first. */
2815 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
2817 output_pic_addr_const (file
, XEXP (x
, 0), code
);
2819 output_pic_addr_const (file
, XEXP (x
, 1), code
);
2821 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2823 output_pic_addr_const (file
, XEXP (x
, 1), code
);
2825 output_pic_addr_const (file
, XEXP (x
, 0), code
);
2832 putc (ASSEMBLER_DIALECT
? '(' : '[', file
);
2833 output_pic_addr_const (file
, XEXP (x
, 0), code
);
2835 output_pic_addr_const (file
, XEXP (x
, 1), code
);
2836 putc (ASSEMBLER_DIALECT
? ')' : ']', file
);
2840 if (XVECLEN (x
, 0) != 1)
2842 output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
2843 switch (XINT (x
, 1))
2846 fputs ("@GOT", file
);
2849 fputs ("@GOTOFF", file
);
2852 fputs ("@PLT", file
);
2855 output_operand_lossage ("invalid UNSPEC as operand");
2861 output_operand_lossage ("invalid expression as operand");
2865 /* This is called from dwarfout.c via ASM_OUTPUT_DWARF_ADDR_CONST.
2866 We need to handle our special PIC relocations. */
2869 i386_dwarf_output_addr_const (file
, x
)
2873 fprintf (file
, "\t%s\t", INT_ASM_OP
);
2875 output_pic_addr_const (file
, x
, '\0');
2877 output_addr_const (file
, x
);
2881 /* In the name of slightly smaller debug output, and to cater to
2882 general assembler losage, recognize PIC+GOTOFF and turn it back
2883 into a direct symbol reference. */
2886 i386_simplify_dwarf_addr (orig_x
)
2891 if (GET_CODE (x
) != PLUS
2892 || GET_CODE (XEXP (x
, 0)) != REG
2893 || GET_CODE (XEXP (x
, 1)) != CONST
)
2896 x
= XEXP (XEXP (x
, 1), 0);
2897 if (GET_CODE (x
) == UNSPEC
2898 && XINT (x
, 1) == 7)
2899 return XVECEXP (x
, 0, 0);
2901 if (GET_CODE (x
) == PLUS
2902 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2903 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2904 && XINT (XEXP (x
, 0), 1) == 7)
2905 return gen_rtx_PLUS (VOIDmode
, XVECEXP (XEXP (x
, 0), 0, 0), XEXP (x
, 1));
2911 put_condition_code (code
, mode
, reverse
, fp
, file
)
2913 enum machine_mode mode
;
2920 code
= reverse_condition (code
);
2931 if (mode
== CCNOmode
)
2936 /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers.
2937 Those same assemblers have the same but opposite losage on cmov. */
2938 suffix
= fp
? "nbe" : "a";
2941 if (mode
== CCNOmode
)
2950 if (mode
== CCNOmode
)
2957 suffix
= fp
? "nb" : "ae";
2960 if (mode
== CCNOmode
)
2970 fputs (suffix
, file
);
2974 print_reg (x
, code
, file
)
2979 if (REGNO (x
) == ARG_POINTER_REGNUM
2980 || REGNO (x
) == FRAME_POINTER_REGNUM
2981 || REGNO (x
) == FLAGS_REG
2982 || REGNO (x
) == FPSR_REG
)
2985 if (ASSEMBLER_DIALECT
== 0 || USER_LABEL_PREFIX
[0] == 0)
2990 else if (code
== 'b')
2992 else if (code
== 'k')
2994 else if (code
== 'y')
2996 else if (code
== 'h')
2999 code
= GET_MODE_SIZE (GET_MODE (x
));
3004 if (STACK_TOP_P (x
))
3006 fputs ("st(0)", file
);
3017 fputs (hi_reg_name
[REGNO (x
)], file
);
3020 fputs (qi_reg_name
[REGNO (x
)], file
);
3023 fputs (qi_high_reg_name
[REGNO (x
)], file
);
3031 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
3032 C -- print opcode suffix for set/cmov insn.
3033 c -- like C, but print reversed condition
3034 R -- print the prefix for register names.
3035 z -- print the opcode suffix for the size of the current operand.
3036 * -- print a star (in certain assembler syntax)
3037 w -- print the operand as if it's a "word" (HImode) even if it isn't.
3038 s -- print a shift double count, followed by the assemblers argument
3040 b -- print the QImode name of the register for the indicated operand.
3041 %b0 would print %al if operands[0] is reg 0.
3042 w -- likewise, print the HImode name of the register.
3043 k -- likewise, print the SImode name of the register.
3044 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
3045 y -- print "st(0)" instead of "st" as a register. */
3048 print_operand (file
, x
, code
)
3058 if (ASSEMBLER_DIALECT
== 0)
3063 if (ASSEMBLER_DIALECT
== 0)
3068 if (ASSEMBLER_DIALECT
== 0)
3073 if (ASSEMBLER_DIALECT
== 0)
3078 if (ASSEMBLER_DIALECT
== 0)
3083 if (ASSEMBLER_DIALECT
== 0)
3088 if (ASSEMBLER_DIALECT
== 0)
3093 /* 387 opcodes don't get size suffixes if the operands are
3096 if (STACK_REG_P (x
))
3099 /* Intel syntax has no truck with instruction suffixes. */
3100 if (ASSEMBLER_DIALECT
!= 0)
3103 /* this is the size of op from size of operand */
3104 switch (GET_MODE_SIZE (GET_MODE (x
)))
3115 if (GET_MODE (x
) == SFmode
)
3129 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
3131 #ifdef GAS_MNEMONICS
3153 if (GET_CODE (x
) == CONST_INT
|| ! SHIFT_DOUBLE_OMITS_COUNT
)
3155 PRINT_OPERAND (file
, x
, 0);
3161 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 0, file
);
3164 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 1, file
);
3167 /* Like above, but reverse condition */
3169 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 0, file
);
3172 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 1, file
);
3178 sprintf (str
, "invalid operand code `%c'", code
);
3179 output_operand_lossage (str
);
3184 if (GET_CODE (x
) == REG
)
3186 PRINT_REG (x
, code
, file
);
3189 else if (GET_CODE (x
) == MEM
)
3191 /* No `byte ptr' prefix for call instructions. */
3192 if (ASSEMBLER_DIALECT
!= 0 && code
!= 'X' && code
!= 'P')
3195 switch (GET_MODE_SIZE (GET_MODE (x
)))
3197 case 1: size
= "BYTE"; break;
3198 case 2: size
= "WORD"; break;
3199 case 4: size
= "DWORD"; break;
3200 case 8: size
= "QWORD"; break;
3201 case 12: size
= "XWORD"; break;
3206 fputs (" PTR ", file
);
3210 if (flag_pic
&& CONSTANT_ADDRESS_P (x
))
3211 output_pic_addr_const (file
, x
, code
);
3216 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
3221 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3222 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
3224 if (ASSEMBLER_DIALECT
== 0)
3226 fprintf (file
, "0x%lx", l
);
3229 /* These float cases don't actually occur as immediate operands. */
3230 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
3235 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3236 REAL_VALUE_TO_DECIMAL (r
, "%.22e", dstr
);
3237 fprintf (file
, "%s", dstr
);
3240 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == XFmode
)
3245 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3246 REAL_VALUE_TO_DECIMAL (r
, "%.22e", dstr
);
3247 fprintf (file
, "%s", dstr
);
3253 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3255 if (ASSEMBLER_DIALECT
== 0)
3258 else if (GET_CODE (x
) == CONST
|| GET_CODE (x
) == SYMBOL_REF
3259 || GET_CODE (x
) == LABEL_REF
)
3261 if (ASSEMBLER_DIALECT
== 0)
3264 fputs ("OFFSET FLAT:", file
);
3267 if (GET_CODE (x
) == CONST_INT
)
3268 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
3270 output_pic_addr_const (file
, x
, code
);
3272 output_addr_const (file
, x
);
3276 /* Print a memory operand whose address is ADDR. */
3279 print_operand_address (file
, addr
)
3283 struct ix86_address parts
;
3284 rtx base
, index
, disp
;
3287 if (! ix86_decompose_address (addr
, &parts
))
3291 index
= parts
.index
;
3293 scale
= parts
.scale
;
3295 if (!base
&& !index
)
3297 /* Displacement only requires special attention. */
3299 if (GET_CODE (disp
) == CONST_INT
)
3301 if (ASSEMBLER_DIALECT
!= 0)
3302 fputs ("ds:", file
);
3303 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3306 output_pic_addr_const (file
, addr
, 0);
3308 output_addr_const (file
, addr
);
3312 if (ASSEMBLER_DIALECT
== 0)
3317 output_pic_addr_const (file
, disp
, 0);
3318 else if (GET_CODE (disp
) == LABEL_REF
)
3319 output_asm_label (disp
);
3321 output_addr_const (file
, disp
);
3326 PRINT_REG (base
, 0, file
);
3330 PRINT_REG (index
, 0, file
);
3332 fprintf (file
, ",%d", scale
);
3338 rtx offset
= NULL_RTX
;
3342 /* Pull out the offset of a symbol; print any symbol itself. */
3343 if (GET_CODE (disp
) == CONST
3344 && GET_CODE (XEXP (disp
, 0)) == PLUS
3345 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
3347 offset
= XEXP (XEXP (disp
, 0), 1);
3348 disp
= gen_rtx_CONST (VOIDmode
,
3349 XEXP (XEXP (disp
, 0), 0));
3353 output_pic_addr_const (file
, disp
, 0);
3354 else if (GET_CODE (disp
) == LABEL_REF
)
3355 output_asm_label (disp
);
3356 else if (GET_CODE (disp
) == CONST_INT
)
3359 output_addr_const (file
, disp
);
3365 PRINT_REG (base
, 0, file
);
3368 if (INTVAL (offset
) >= 0)
3370 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
3374 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
3381 PRINT_REG (index
, 0, file
);
3383 fprintf (file
, "*%d", scale
);
3390 /* Split one or more DImode RTL references into pairs of SImode
3391 references. The RTL can be REG, offsettable MEM, integer constant, or
3392 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3393 split and "num" is its length. lo_half and hi_half are output arrays
3394 that parallel "operands". */
3397 split_di (operands
, num
, lo_half
, hi_half
)
3400 rtx lo_half
[], hi_half
[];
3404 rtx op
= operands
[num
];
3405 if (CONSTANT_P (op
))
3406 split_double (op
, &lo_half
[num
], &hi_half
[num
]);
3407 else if (! reload_completed
)
3409 lo_half
[num
] = gen_lowpart (SImode
, op
);
3410 hi_half
[num
] = gen_highpart (SImode
, op
);
3412 else if (GET_CODE (op
) == REG
)
3414 lo_half
[num
] = gen_rtx_REG (SImode
, REGNO (op
));
3415 hi_half
[num
] = gen_rtx_REG (SImode
, REGNO (op
) + 1);
3417 else if (offsettable_memref_p (op
))
3419 rtx lo_addr
= XEXP (op
, 0);
3420 rtx hi_addr
= XEXP (adj_offsettable_operand (op
, 4), 0);
3421 lo_half
[num
] = change_address (op
, SImode
, lo_addr
);
3422 hi_half
[num
] = change_address (op
, SImode
, hi_addr
);
3429 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
3430 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
3431 is the expression of the binary operation. The output may either be
3432 emitted here, or returned to the caller, like all output_* functions.
3434 There is no guarantee that the operands are the same mode, as they
3435 might be within FLOAT or FLOAT_EXTEND expressions. */
3438 output_387_binary_op (insn
, operands
)
3442 static char buf
[100];
3446 switch (GET_CODE (operands
[3]))
3449 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3450 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3457 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3458 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3465 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3466 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3473 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3474 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3486 switch (GET_CODE (operands
[3]))
3490 if (REG_P (operands
[2]) && REGNO (operands
[0]) == REGNO (operands
[2]))
3493 operands
[2] = operands
[1];
3497 if (GET_CODE (operands
[2]) == MEM
)
3503 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
3505 if (STACK_TOP_P (operands
[0]))
3506 p
= "p\t{%0,%2|%2, %0}";
3508 p
= "p\t{%2,%0|%0, %2}";
3512 if (STACK_TOP_P (operands
[0]))
3513 p
= "\t{%y2,%0|%0, %y2}";
3515 p
= "\t{%2,%0|%0, %2}";
3520 if (GET_CODE (operands
[1]) == MEM
)
3526 if (GET_CODE (operands
[2]) == MEM
)
3532 if (! STACK_REG_P (operands
[1]) || ! STACK_REG_P (operands
[2]))
3535 /* Note that the Unixware assembler, and the AT&T assembler before
3536 that, are confusingly not reversed from Intel syntax in this
3538 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
3540 if (STACK_TOP_P (operands
[0]))
3547 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[1])))
3549 if (STACK_TOP_P (operands
[0]))
3556 if (STACK_TOP_P (operands
[0]))
3558 if (STACK_TOP_P (operands
[1]))
3564 else if (STACK_TOP_P (operands
[1]))
3578 /* Output code for INSN to convert a float to a signed int. OPERANDS
3579 are the insn operands. The output may be [SD]Imode and the input
3580 operand may be [SDX]Fmode. */
3583 output_fix_trunc (insn
, operands
)
3587 int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
3588 int dimode_p
= GET_MODE (operands
[0]) == DImode
;
3591 /* Jump through a hoop or two for DImode, since the hardware has no
3592 non-popping instruction. We used to do this a different way, but
3593 that was somewhat fragile and broke with post-reload splitters. */
3594 if (dimode_p
&& !stack_top_dies
)
3595 output_asm_insn ("fld\t%y1", operands
);
3597 if (! STACK_TOP_P (operands
[1]))
3600 xops
[0] = GEN_INT (12);
3601 xops
[1] = adj_offsettable_operand (operands
[2], 1);
3602 xops
[1] = change_address (xops
[1], QImode
, NULL_RTX
);
3604 xops
[2] = operands
[0];
3605 if (GET_CODE (operands
[0]) != MEM
)
3606 xops
[2] = operands
[3];
3608 output_asm_insn ("fnstcw\t%2", operands
);
3609 output_asm_insn ("mov{l}\t{%2, %4|%4, %2}", operands
);
3610 output_asm_insn ("mov{b}\t{%0, %1|%1, %0}", xops
);
3611 output_asm_insn ("fldcw\t%2", operands
);
3612 output_asm_insn ("mov{l}\t{%4, %2|%2, %4}", operands
);
3614 if (stack_top_dies
|| dimode_p
)
3615 output_asm_insn ("fistp%z2\t%2", xops
);
3617 output_asm_insn ("fist%z2\t%2", xops
);
3619 output_asm_insn ("fldcw\t%2", operands
);
3621 if (GET_CODE (operands
[0]) != MEM
)
3625 split_di (operands
+0, 1, xops
+0, xops
+1);
3626 split_di (operands
+3, 1, xops
+2, xops
+3);
3627 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops
);
3628 output_asm_insn ("mov{l}\t{%3, %1|%1, %3}", xops
);
3631 output_asm_insn ("mov{l}\t{%3,%0|%0, %3}", operands
);
3637 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
3638 should be used and 2 when fnstsw should be used. UNORDERED_P is true
3639 when fucom should be used. */
3642 output_fp_compare (insn
, operands
, eflags_p
, unordered_p
)
3645 int eflags_p
, unordered_p
;
3648 rtx cmp_op0
= operands
[0];
3649 rtx cmp_op1
= operands
[1];
3654 cmp_op1
= operands
[2];
3657 if (! STACK_TOP_P (cmp_op0
))
3660 stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
3662 if (STACK_REG_P (cmp_op1
)
3664 && find_regno_note (insn
, REG_DEAD
, REGNO (cmp_op1
))
3665 && REGNO (cmp_op1
) != FIRST_STACK_REG
)
3667 /* If both the top of the 387 stack dies, and the other operand
3668 is also a stack register that dies, then this must be a
3669 `fcompp' float compare */
3673 /* There is no double popping fcomi variant. Fortunately,
3674 eflags is immune from the fstp's cc clobbering. */
3676 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands
);
3678 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands
);
3686 return "fucompp\n\tfnstsw\t%0";
3688 return "fcompp\n\tfnstsw\t%0";
3701 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
3703 static const char * const alt
[24] =
3715 "fcomi\t{%y1, %0|%0, %y1}",
3716 "fcomip\t{%y1, %0|%0, %y1}",
3717 "fucomi\t{%y1, %0|%0, %y1}",
3718 "fucomip\t{%y1, %0|%0, %y1}",
3725 "fcom%z2\t%y2\n\tfnstsw\t%0",
3726 "fcomp%z2\t%y2\n\tfnstsw\t%0",
3727 "fucom%z2\t%y2\n\tfnstsw\t%0",
3728 "fucomp%z2\t%y2\n\tfnstsw\t%0",
3730 "ficom%z2\t%y2\n\tfnstsw\t%0",
3731 "ficomp%z2\t%y2\n\tfnstsw\t%0",
3739 mask
= eflags_p
<< 3;
3740 mask
|= (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
) << 2;
3741 mask
|= unordered_p
<< 1;
3742 mask
|= stack_top_dies
;
3754 /* Output assembler code to FILE to initialize basic-block profiling.
3756 If profile_block_flag == 2
3758 Output code to call the subroutine `__bb_init_trace_func'
3759 and pass two parameters to it. The first parameter is
3760 the address of a block allocated in the object module.
3761 The second parameter is the number of the first basic block
3764 The name of the block is a local symbol made with this statement:
3766 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
3768 Of course, since you are writing the definition of
3769 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
3770 can take a short cut in the definition of this macro and use the
3771 name that you know will result.
3773 The number of the first basic block of the function is
3774 passed to the macro in BLOCK_OR_LABEL.
3776 If described in a virtual assembler language the code to be
3780 parameter2 <- BLOCK_OR_LABEL
3781 call __bb_init_trace_func
3783 else if profile_block_flag != 0
3785 Output code to call the subroutine `__bb_init_func'
3786 and pass one single parameter to it, which is the same
3787 as the first parameter to `__bb_init_trace_func'.
3789 The first word of this parameter is a flag which will be nonzero if
3790 the object module has already been initialized. So test this word
3791 first, and do not call `__bb_init_func' if the flag is nonzero.
3792 Note: When profile_block_flag == 2 the test need not be done
3793 but `__bb_init_trace_func' *must* be called.
3795 BLOCK_OR_LABEL may be used to generate a label number as a
3796 branch destination in case `__bb_init_func' will not be called.
3798 If described in a virtual assembler language the code to be
3809 ix86_output_function_block_profiler (file
, block_or_label
)
3813 static int num_func
= 0;
3815 char block_table
[80], false_label
[80];
3817 ASM_GENERATE_INTERNAL_LABEL (block_table
, "LPBX", 0);
3819 xops
[1] = gen_rtx_SYMBOL_REF (VOIDmode
, block_table
);
3820 xops
[5] = stack_pointer_rtx
;
3821 xops
[7] = gen_rtx_REG (Pmode
, 0); /* eax */
3823 CONSTANT_POOL_ADDRESS_P (xops
[1]) = TRUE
;
3825 switch (profile_block_flag
)
3828 xops
[2] = GEN_INT (block_or_label
);
3829 xops
[3] = gen_rtx_MEM (Pmode
,
3830 gen_rtx_SYMBOL_REF (VOIDmode
, "__bb_init_trace_func"));
3831 xops
[6] = GEN_INT (8);
3833 output_asm_insn ("push{l}\t%2", xops
);
3835 output_asm_insn ("push{l}\t%1", xops
);
3838 output_asm_insn ("lea{l}\t{%a1, %7|%7, %a1}", xops
);
3839 output_asm_insn ("push{l}\t%7", xops
);
3841 output_asm_insn ("call\t%P3", xops
);
3842 output_asm_insn ("add{l}\t{%6, %5|%5, %6}", xops
);
3846 ASM_GENERATE_INTERNAL_LABEL (false_label
, "LPBZ", num_func
);
3848 xops
[0] = const0_rtx
;
3849 xops
[2] = gen_rtx_MEM (Pmode
,
3850 gen_rtx_SYMBOL_REF (VOIDmode
, false_label
));
3851 xops
[3] = gen_rtx_MEM (Pmode
,
3852 gen_rtx_SYMBOL_REF (VOIDmode
, "__bb_init_func"));
3853 xops
[4] = gen_rtx_MEM (Pmode
, xops
[1]);
3854 xops
[6] = GEN_INT (4);
3856 CONSTANT_POOL_ADDRESS_P (xops
[2]) = TRUE
;
3858 output_asm_insn ("cmp{l}\t{%0, %4|%4, %0}", xops
);
3859 output_asm_insn ("jne\t%2", xops
);
3862 output_asm_insn ("push{l}\t%1", xops
);
3865 output_asm_insn ("lea{l}\t{%a1, %7|%7, %a2}", xops
);
3866 output_asm_insn ("push{l}\t%7", xops
);
3868 output_asm_insn ("call\t%P3", xops
);
3869 output_asm_insn ("add{l}\t{%6, %5|%5, %6}", xops
);
3870 ASM_OUTPUT_INTERNAL_LABEL (file
, "LPBZ", num_func
);
3876 /* Output assembler code to FILE to increment a counter associated
3877 with basic block number BLOCKNO.
3879 If profile_block_flag == 2
3881 Output code to initialize the global structure `__bb' and
3882 call the function `__bb_trace_func' which will increment the
3885 `__bb' consists of two words. In the first word the number
3886 of the basic block has to be stored. In the second word
3887 the address of a block allocated in the object module
3890 The basic block number is given by BLOCKNO.
3892 The address of the block is given by the label created with
3894 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
3896 by FUNCTION_BLOCK_PROFILER.
3898 Of course, since you are writing the definition of
3899 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
3900 can take a short cut in the definition of this macro and use the
3901 name that you know will result.
3903 If described in a virtual assembler language the code to be
3906 move BLOCKNO -> (__bb)
3907 move LPBX0 -> (__bb+4)
3908 call __bb_trace_func
3910 Note that function `__bb_trace_func' must not change the
3911 machine state, especially the flag register. To grant
3912 this, you must output code to save and restore registers
3913 either in this macro or in the macros MACHINE_STATE_SAVE
3914 and MACHINE_STATE_RESTORE. The last two macros will be
3915 used in the function `__bb_trace_func', so you must make
3916 sure that the function prologue does not change any
3917 register prior to saving it with MACHINE_STATE_SAVE.
3919 else if profile_block_flag != 0
3921 Output code to increment the counter directly.
3922 Basic blocks are numbered separately from zero within each
3923 compiled object module. The count associated with block number
3924 BLOCKNO is at index BLOCKNO in an array of words; the name of
3925 this array is a local symbol made with this statement:
3927 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
3929 Of course, since you are writing the definition of
3930 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
3931 can take a short cut in the definition of this macro and use the
3932 name that you know will result.
3934 If described in a virtual assembler language the code to be
3937 inc (LPBX2+4*BLOCKNO)
3941 ix86_output_block_profiler (file
, blockno
)
3942 FILE *file ATTRIBUTE_UNUSED
;
3945 rtx xops
[8], cnt_rtx
;
3947 char *block_table
= counts
;
3949 switch (profile_block_flag
)
3952 ASM_GENERATE_INTERNAL_LABEL (block_table
, "LPBX", 0);
3954 xops
[1] = gen_rtx_SYMBOL_REF (VOIDmode
, block_table
);
3955 xops
[2] = GEN_INT (blockno
);
3956 xops
[3] = gen_rtx_MEM (Pmode
,
3957 gen_rtx_SYMBOL_REF (VOIDmode
, "__bb_trace_func"));
3958 xops
[4] = gen_rtx_SYMBOL_REF (VOIDmode
, "__bb");
3959 xops
[5] = plus_constant (xops
[4], 4);
3960 xops
[0] = gen_rtx_MEM (SImode
, xops
[4]);
3961 xops
[6] = gen_rtx_MEM (SImode
, xops
[5]);
3963 CONSTANT_POOL_ADDRESS_P (xops
[1]) = TRUE
;
3965 output_asm_insn ("pushf", xops
);
3966 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops
);
3969 xops
[7] = gen_rtx_REG (Pmode
, 0); /* eax */
3970 output_asm_insn ("push{l}\t%7", xops
);
3971 output_asm_insn ("lea{l}\t{%a1, %7|%7, %a1}", xops
);
3972 output_asm_insn ("mov{l}\t{%7, %6|%6, %7}", xops
);
3973 output_asm_insn ("pop{l}\t%7", xops
);
3976 output_asm_insn ("mov{l}\t{%1, %6|%6, %1}", xops
);
3977 output_asm_insn ("call\t%P3", xops
);
3978 output_asm_insn ("popf", xops
);
3983 ASM_GENERATE_INTERNAL_LABEL (counts
, "LPBX", 2);
3984 cnt_rtx
= gen_rtx_SYMBOL_REF (VOIDmode
, counts
);
3985 SYMBOL_REF_FLAG (cnt_rtx
) = TRUE
;
3988 cnt_rtx
= plus_constant (cnt_rtx
, blockno
*4);
3991 cnt_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, cnt_rtx
);
3993 xops
[0] = gen_rtx_MEM (SImode
, cnt_rtx
);
3994 output_asm_insn ("inc{l}\t%0", xops
);
4001 ix86_expand_move (mode
, operands
)
4002 enum machine_mode mode
;
4005 int strict
= (reload_in_progress
|| reload_completed
);
4008 if (flag_pic
&& mode
== Pmode
&& symbolic_operand (operands
[1], Pmode
))
4010 /* Emit insns to move operands[1] into operands[0]. */
4012 if (GET_CODE (operands
[0]) == MEM
)
4013 operands
[1] = force_reg (Pmode
, operands
[1]);
4016 rtx temp
= operands
[0];
4017 if (GET_CODE (temp
) != REG
)
4018 temp
= gen_reg_rtx (Pmode
);
4019 temp
= legitimize_pic_address (operands
[1], temp
);
4020 if (temp
== operands
[0])
4027 if (GET_CODE (operands
[0]) == MEM
4028 && (GET_MODE (operands
[0]) == QImode
4029 || !push_operand (operands
[0], mode
))
4030 && GET_CODE (operands
[1]) == MEM
)
4031 operands
[1] = force_reg (mode
, operands
[1]);
4033 if (push_operand (operands
[0], mode
)
4034 && ! general_no_elim_operand (operands
[1], mode
))
4035 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
4037 if (FLOAT_MODE_P (mode
))
4039 /* If we are loading a floating point constant to a register,
4040 force the value to memory now, since we'll get better code
4041 out the back end. */
4045 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
4046 && register_operand (operands
[0], mode
))
4047 operands
[1] = validize_mem (force_const_mem (mode
, operands
[1]));
4051 insn
= gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
4056 /* Attempt to expand a binary operator. Make the expansion closer to the
4057 actual machine, then just general_operand, which will allow 3 separate
4058 memory references (one output, two input) in a single insn. */
4061 ix86_expand_binary_operator (code
, mode
, operands
)
4063 enum machine_mode mode
;
4066 int matching_memory
;
4067 rtx src1
, src2
, dst
, op
, clob
;
4073 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
4074 if (GET_RTX_CLASS (code
) == 'c'
4075 && (rtx_equal_p (dst
, src2
)
4076 || immediate_operand (src1
, mode
)))
4083 /* If the destination is memory, and we do not have matching source
4084 operands, do things in registers. */
4085 matching_memory
= 0;
4086 if (GET_CODE (dst
) == MEM
)
4088 if (rtx_equal_p (dst
, src1
))
4089 matching_memory
= 1;
4090 else if (GET_RTX_CLASS (code
) == 'c'
4091 && rtx_equal_p (dst
, src2
))
4092 matching_memory
= 2;
4094 dst
= gen_reg_rtx (mode
);
4097 /* Both source operands cannot be in memory. */
4098 if (GET_CODE (src1
) == MEM
&& GET_CODE (src2
) == MEM
)
4100 if (matching_memory
!= 2)
4101 src2
= force_reg (mode
, src2
);
4103 src1
= force_reg (mode
, src1
);
4106 /* If the operation is not commutable, source 1 cannot be a constant
4107 or non-matching memory. */
4108 if ((CONSTANT_P (src1
)
4109 || (!matching_memory
&& GET_CODE (src1
) == MEM
))
4110 && GET_RTX_CLASS (code
) != 'c')
4111 src1
= force_reg (mode
, src1
);
4113 /* If optimizing, copy to regs to improve CSE */
4114 if (optimize
&& !reload_in_progress
&& !reload_completed
)
4116 if (GET_CODE (dst
) == MEM
)
4117 dst
= gen_reg_rtx (mode
);
4118 if (GET_CODE (src1
) == MEM
)
4119 src1
= force_reg (mode
, src1
);
4120 if (GET_CODE (src2
) == MEM
)
4121 src2
= force_reg (mode
, src2
);
4124 /* Emit the instruction. */
4126 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, mode
, src1
, src2
));
4127 if (reload_in_progress
)
4129 /* Reload doesn't know about the flags register, and doesn't know that
4130 it doesn't want to clobber it. We can only do this with PLUS. */
4137 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
4138 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
4141 /* Fix up the destination if needed. */
4142 if (dst
!= operands
[0])
4143 emit_move_insn (operands
[0], dst
);
4146 /* Return TRUE or FALSE depending on whether the binary operator meets the
4147 appropriate constraints. */
4150 ix86_binary_operator_ok (code
, mode
, operands
)
4152 enum machine_mode mode ATTRIBUTE_UNUSED
;
4155 /* Both source operands cannot be in memory. */
4156 if (GET_CODE (operands
[1]) == MEM
&& GET_CODE (operands
[2]) == MEM
)
4158 /* If the operation is not commutable, source 1 cannot be a constant. */
4159 if (CONSTANT_P (operands
[1]) && GET_RTX_CLASS (code
) != 'c')
4161 /* If the destination is memory, we must have a matching source operand. */
4162 if (GET_CODE (operands
[0]) == MEM
4163 && ! (rtx_equal_p (operands
[0], operands
[1])
4164 || (GET_RTX_CLASS (code
) == 'c'
4165 && rtx_equal_p (operands
[0], operands
[2]))))
4167 /* If the operation is not commutable and the source 1 is memory, we must
4168 have a matching destionation. */
4169 if (GET_CODE (operands
[1]) == MEM
4170 && GET_RTX_CLASS (code
) != 'c'
4171 && ! rtx_equal_p (operands
[0], operands
[1]))
4176 /* Attempt to expand a unary operator. Make the expansion closer to the
4177 actual machine, then just general_operand, which will allow 2 separate
4178 memory references (one output, one input) in a single insn. */
4181 ix86_expand_unary_operator (code
, mode
, operands
)
4183 enum machine_mode mode
;
4186 int matching_memory
;
4187 rtx src
, dst
, op
, clob
;
4192 /* If the destination is memory, and we do not have matching source
4193 operands, do things in registers. */
4194 matching_memory
= 0;
4195 if (GET_CODE (dst
) == MEM
)
4197 if (rtx_equal_p (dst
, src
))
4198 matching_memory
= 1;
4200 dst
= gen_reg_rtx (mode
);
4203 /* When source operand is memory, destination must match. */
4204 if (!matching_memory
&& GET_CODE (src
) == MEM
)
4205 src
= force_reg (mode
, src
);
4207 /* If optimizing, copy to regs to improve CSE */
4208 if (optimize
&& !reload_in_progress
&& !reload_completed
)
4210 if (GET_CODE (dst
) == MEM
)
4211 dst
= gen_reg_rtx (mode
);
4212 if (GET_CODE (src
) == MEM
)
4213 src
= force_reg (mode
, src
);
4216 /* Emit the instruction. */
4218 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_e (code
, mode
, src
));
4219 if (reload_in_progress
|| code
== NOT
)
4221 /* Reload doesn't know about the flags register, and doesn't know that
4222 it doesn't want to clobber it. */
4229 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
4230 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
4233 /* Fix up the destination if needed. */
4234 if (dst
!= operands
[0])
4235 emit_move_insn (operands
[0], dst
);
4238 /* Return TRUE or FALSE depending on whether the unary operator meets the
4239 appropriate constraints. */
4242 ix86_unary_operator_ok (code
, mode
, operands
)
4243 enum rtx_code code ATTRIBUTE_UNUSED
;
4244 enum machine_mode mode ATTRIBUTE_UNUSED
;
4245 rtx operands
[2] ATTRIBUTE_UNUSED
;
4247 /* If one of operands is memory, source and destination must match. */
4248 if ((GET_CODE (operands
[0]) == MEM
4249 || GET_CODE (operands
[1]) == MEM
)
4250 && ! rtx_equal_p (operands
[0], operands
[1]))
4255 /* Produce an unsigned comparison for a given signed comparison. */
4257 static enum rtx_code
4258 unsigned_comparison (code
)
4288 /* Generate insn patterns to do an integer compare of OPERANDS. */
4291 ix86_expand_int_compare (code
, op0
, op1
)
4295 enum machine_mode cmpmode
;
4298 cmpmode
= SELECT_CC_MODE (code
, op0
, op1
);
4299 flags
= gen_rtx_REG (cmpmode
, FLAGS_REG
);
4301 /* This is very simple, but making the interface the same as in the
4302 FP case makes the rest of the code easier. */
4303 tmp
= gen_rtx_COMPARE (cmpmode
, op0
, op1
);
4304 emit_insn (gen_rtx_SET (VOIDmode
, flags
, tmp
));
4306 /* Return the test that should be put into the flags user, i.e.
4307 the bcc, scc, or cmov instruction. */
4308 return gen_rtx_fmt_ee (code
, VOIDmode
, flags
, const0_rtx
);
4311 /* Generate insn patterns to do a floating point compare of OPERANDS.
4312 If UNORDERED, allow for unordered compares. */
4315 ix86_expand_fp_compare (code
, op0
, op1
, unordered
)
4320 enum machine_mode fpcmp_mode
;
4321 enum machine_mode intcmp_mode
;
4324 /* When not doing IEEE compliant compares, disable unordered. */
4325 if (! TARGET_IEEE_FP
)
4327 fpcmp_mode
= unordered
? CCFPUmode
: CCFPmode
;
4329 /* ??? If we knew whether invalid-operand exceptions were masked,
4330 we could rely on fcom to raise an exception and take care of
4331 NaNs. But we don't. We could know this from c9x math bits. */
4335 /* All of the unordered compare instructions only work on registers.
4336 The same is true of the XFmode compare instructions. */
4337 if (unordered
|| GET_MODE (op0
) == XFmode
)
4339 op0
= force_reg (GET_MODE (op0
), op0
);
4340 op1
= force_reg (GET_MODE (op1
), op1
);
4344 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
4345 things around if they appear profitable, otherwise force op0
4348 if (standard_80387_constant_p (op0
) == 0
4349 || (GET_CODE (op0
) == MEM
4350 && ! (standard_80387_constant_p (op1
) == 0
4351 || GET_CODE (op1
) == MEM
)))
4354 tmp
= op0
, op0
= op1
, op1
= tmp
;
4355 code
= swap_condition (code
);
4358 if (GET_CODE (op0
) != REG
)
4359 op0
= force_reg (GET_MODE (op0
), op0
);
4361 if (CONSTANT_P (op1
))
4363 if (standard_80387_constant_p (op1
))
4364 op1
= force_reg (GET_MODE (op1
), op1
);
4366 op1
= validize_mem (force_const_mem (GET_MODE (op1
), op1
));
4370 /* %%% fcomi is probably always faster, even when dealing with memory,
4371 since compare-and-branch would be three insns instead of four. */
4372 if (TARGET_CMOVE
&& !unordered
)
4374 if (GET_CODE (op0
) != REG
)
4375 op0
= force_reg (GET_MODE (op0
), op0
);
4376 if (GET_CODE (op1
) != REG
)
4377 op1
= force_reg (GET_MODE (op1
), op1
);
4379 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
4380 tmp
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (fpcmp_mode
, FLAGS_REG
), tmp
);
4383 /* The FP codes work out to act like unsigned. */
4384 code
= unsigned_comparison (code
);
4385 intcmp_mode
= fpcmp_mode
;
4389 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
4392 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
4393 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), 9);
4394 tmp
= gen_reg_rtx (HImode
);
4395 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, tmp2
));
4399 /* We have two options here -- use sahf, or testing bits of ah
4400 directly. On PPRO, they are equivalent, sahf being one byte
4401 smaller. On Pentium, sahf is non-pairable while test is UV
4404 if (TARGET_USE_SAHF
|| optimize_size
)
4408 /* The FP codes work out to act like unsigned. */
4409 code
= unsigned_comparison (code
);
4410 emit_insn (gen_x86_sahf_1 (tmp
));
4411 intcmp_mode
= CCmode
;
4416 * The numbers below correspond to the bits of the FPSW in AH.
4417 * C3, C2, and C0 are in bits 0x40, 0x4, and 0x01 respectively.
4439 /* We'd have to use `xorb 1,ah; andb 0x41,ah', so it's
4440 faster in all cases to just fall back on sahf. */
4458 emit_insn (gen_testqi_ext_0 (tmp
, GEN_INT (mask
)));
4459 intcmp_mode
= CCNOmode
;
4464 /* In the unordered case, we have to check C2 for NaN's, which
4465 doesn't happen to work out to anything nice combination-wise.
4466 So do some bit twiddling on the value we've got in AH to come
4467 up with an appropriate set of condition codes. */
4469 intcmp_mode
= CCNOmode
;
4473 emit_insn (gen_testqi_ext_0 (tmp
, GEN_INT (0x45)));
4477 emit_insn (gen_andqi_ext_0 (tmp
, tmp
, GEN_INT (0x45)));
4478 emit_insn (gen_cmpqi_ext_3 (tmp
, GEN_INT (0x01)));
4479 intcmp_mode
= CCmode
;
4483 emit_insn (gen_testqi_ext_0 (tmp
, GEN_INT (0x05)));
4487 emit_insn (gen_andqi_ext_0 (tmp
, tmp
, GEN_INT (0x45)));
4488 emit_insn (gen_addqi_ext_1 (tmp
, tmp
, constm1_rtx
));
4489 emit_insn (gen_cmpqi_ext_3 (tmp
, GEN_INT (0x40)));
4490 intcmp_mode
= CCmode
;
4494 emit_insn (gen_andqi_ext_0 (tmp
, tmp
, GEN_INT (0x45)));
4495 emit_insn (gen_cmpqi_ext_3 (tmp
, GEN_INT (0x40)));
4496 intcmp_mode
= CCmode
;
4500 emit_insn (gen_andqi_ext_0 (tmp
, tmp
, GEN_INT (0x45)));
4501 emit_insn (gen_xorqi_cc_ext_1 (tmp
, tmp
, GEN_INT (0x40)));
4510 /* Return the test that should be put into the flags user, i.e.
4511 the bcc, scc, or cmov instruction. */
4512 return gen_rtx_fmt_ee (code
, VOIDmode
,
4513 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
4518 ix86_expand_compare (code
, unordered
)
4523 op0
= ix86_compare_op0
;
4524 op1
= ix86_compare_op1
;
4526 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
4527 ret
= ix86_expand_fp_compare (code
, op0
, op1
, unordered
);
4529 ret
= ix86_expand_int_compare (code
, op0
, op1
);
4535 ix86_expand_branch (code
, unordered
, label
)
4540 rtx tmp
, lo
[2], hi
[2], label2
;
4541 enum rtx_code code1
, code2
, code3
;
4543 if (GET_MODE (ix86_compare_op0
) != DImode
)
4545 tmp
= ix86_expand_compare (code
, unordered
);
4546 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
4547 gen_rtx_LABEL_REF (VOIDmode
, label
),
4549 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
4553 /* Expand DImode branch into multiple compare+branch. */
4555 if (CONSTANT_P (ix86_compare_op0
) && ! CONSTANT_P (ix86_compare_op1
))
4557 tmp
= ix86_compare_op0
;
4558 ix86_compare_op0
= ix86_compare_op1
;
4559 ix86_compare_op1
= tmp
;
4560 code
= swap_condition (code
);
4562 split_di (&ix86_compare_op0
, 1, lo
+0, hi
+0);
4563 split_di (&ix86_compare_op1
, 1, lo
+1, hi
+1);
4565 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to avoid
4566 two branches. This costs one extra insn, so disable when optimizing
4569 if ((code
== EQ
|| code
== NE
)
4571 || hi
[1] == const0_rtx
|| lo
[1] == const0_rtx
))
4576 if (hi
[1] != const0_rtx
)
4578 xor1
= expand_binop (SImode
, xor_optab
, xor1
, hi
[1],
4579 NULL_RTX
, 0, OPTAB_WIDEN
);
4583 if (lo
[1] != const0_rtx
)
4585 xor0
= expand_binop (SImode
, xor_optab
, xor0
, lo
[1],
4586 NULL_RTX
, 0, OPTAB_WIDEN
);
4589 tmp
= expand_binop (SImode
, ior_optab
, xor1
, xor0
,
4590 NULL_RTX
, 0, OPTAB_WIDEN
);
4592 ix86_compare_op0
= tmp
;
4593 ix86_compare_op1
= const0_rtx
;
4594 ix86_expand_branch (code
, unordered
, label
);
4598 /* Otherwise, if we are doing less-than, op1 is a constant and the
4599 low word is zero, then we can just examine the high word. */
4601 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
4602 && (code
== LT
|| code
== LTU
))
4604 ix86_compare_op0
= hi
[0];
4605 ix86_compare_op1
= hi
[1];
4606 ix86_expand_branch (code
, unordered
, label
);
4610 /* Otherwise, we need two or three jumps. */
4612 label2
= gen_label_rtx ();
4615 code2
= swap_condition (code
);
4616 code3
= unsigned_condition (code
);
4620 case LT
: case GT
: case LTU
: case GTU
:
4623 case LE
: code1
= LT
; code2
= GT
; break;
4624 case GE
: code1
= GT
; code2
= LT
; break;
4625 case LEU
: code1
= LTU
; code2
= GTU
; break;
4626 case GEU
: code1
= GTU
; code2
= LTU
; break;
4628 case EQ
: code1
= NIL
; code2
= NE
; break;
4629 case NE
: code2
= NIL
; break;
4637 * if (hi(a) < hi(b)) goto true;
4638 * if (hi(a) > hi(b)) goto false;
4639 * if (lo(a) < lo(b)) goto true;
4643 ix86_compare_op0
= hi
[0];
4644 ix86_compare_op1
= hi
[1];
4647 ix86_expand_branch (code1
, unordered
, label
);
4649 ix86_expand_branch (code2
, unordered
, label2
);
4651 ix86_compare_op0
= lo
[0];
4652 ix86_compare_op1
= lo
[1];
4653 ix86_expand_branch (code3
, unordered
, label
);
4656 emit_label (label2
);
4660 ix86_expand_setcc (code
, unordered
, dest
)
4668 if (GET_MODE (ix86_compare_op0
) == DImode
)
4669 return 0; /* FAIL */
4671 /* Three modes of generation:
4672 0 -- destination does not overlap compare sources:
4673 clear dest first, emit strict_low_part setcc.
4674 1 -- destination does overlap compare sources:
4675 emit subreg setcc, zero extend.
4676 2 -- destination is in QImode:
4682 if (GET_MODE (dest
) == QImode
)
4684 else if (reg_overlap_mentioned_p (dest
, ix86_compare_op0
)
4685 || reg_overlap_mentioned_p (dest
, ix86_compare_op1
))
4689 emit_move_insn (dest
, const0_rtx
);
4691 ret
= ix86_expand_compare (code
, unordered
);
4692 PUT_MODE (ret
, QImode
);
4697 tmp
= gen_lowpart (QImode
, dest
);
4698 tmp
= gen_rtx_STRICT_LOW_PART (VOIDmode
, tmp
);
4702 if (!cse_not_expected
)
4703 tmp
= gen_reg_rtx (QImode
);
4705 tmp
= gen_lowpart (QImode
, dest
);
4708 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, ret
));
4714 tmp
= gen_rtx_ZERO_EXTEND (GET_MODE (dest
), tmp
);
4715 tmp
= gen_rtx_SET (VOIDmode
, dest
, tmp
);
4716 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
4717 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
4721 return 1; /* DONE */
4725 ix86_expand_int_movcc (operands
)
4728 enum rtx_code code
= GET_CODE (operands
[1]), compare_code
;
4729 rtx compare_seq
, compare_op
;
4731 /* When the compare code is not LTU or GEU, we can not use sbbl case.
4732 In case comparsion is done with immediate, we can convert it to LTU or
4733 GEU by altering the integer. */
4735 if ((code
== LEU
|| code
== GTU
)
4736 && GET_CODE (ix86_compare_op1
) == CONST_INT
4737 && GET_MODE (operands
[0]) != HImode
4738 && (unsigned int)INTVAL (ix86_compare_op1
) != 0xffffffff
4739 && GET_CODE (operands
[2]) == CONST_INT
4740 && GET_CODE (operands
[3]) == CONST_INT
)
4746 ix86_compare_op1
= GEN_INT (INTVAL (ix86_compare_op1
) + 1);
4749 compare_op
= ix86_expand_compare (code
, code
== EQ
|| code
== NE
);
4750 compare_seq
= gen_sequence ();
4753 compare_code
= GET_CODE (compare_op
);
4755 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
4756 HImode insns, we'd be swallowed in word prefix ops. */
4758 if (GET_MODE (operands
[0]) != HImode
4759 && GET_CODE (operands
[2]) == CONST_INT
4760 && GET_CODE (operands
[3]) == CONST_INT
)
4762 rtx out
= operands
[0];
4763 HOST_WIDE_INT ct
= INTVAL (operands
[2]);
4764 HOST_WIDE_INT cf
= INTVAL (operands
[3]);
4767 if (compare_code
== LTU
|| compare_code
== GEU
)
4770 /* Detect overlap between destination and compare sources. */
4773 /* To simplify rest of code, restrict to the GEU case. */
4774 if (compare_code
== LTU
)
4779 compare_code
= reverse_condition (compare_code
);
4780 code
= reverse_condition (code
);
4784 if (reg_overlap_mentioned_p (out
, ix86_compare_op0
)
4785 || reg_overlap_mentioned_p (out
, ix86_compare_op1
))
4786 tmp
= gen_reg_rtx (SImode
);
4788 emit_insn (compare_seq
);
4789 emit_insn (gen_x86_movsicc_0_m1 (tmp
));
4801 emit_insn (gen_addsi3 (out
, out
, GEN_INT (ct
)));
4812 emit_insn (gen_iorsi3 (out
, out
, GEN_INT (ct
)));
4814 else if (diff
== -1 && ct
)
4824 emit_insn (gen_one_cmplsi2 (tmp
, tmp
));
4826 emit_insn (gen_addsi3 (out
, out
, GEN_INT (cf
)));
4833 * andl cf - ct, dest
4838 emit_insn (gen_andsi3 (out
, out
, GEN_INT (cf
- ct
)));
4840 emit_insn (gen_addsi3 (out
, out
, GEN_INT (ct
)));
4844 emit_move_insn (out
, tmp
);
4846 return 1; /* DONE */
4853 tmp
= ct
, ct
= cf
, cf
= tmp
;
4855 compare_code
= reverse_condition (compare_code
);
4856 code
= reverse_condition (code
);
4858 if (diff
== 1 || diff
== 2 || diff
== 4 || diff
== 8
4859 || diff
== 3 || diff
== 5 || diff
== 9)
4865 * lea cf(dest*(ct-cf)),dest
4869 * This also catches the degenerate setcc-only case.
4875 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
4876 ix86_compare_op1
, VOIDmode
, 0, 1);
4883 tmp
= gen_rtx_MULT (SImode
, out
, GEN_INT (diff
& ~1));
4887 tmp
= gen_rtx_PLUS (SImode
, tmp
, out
);
4893 tmp
= gen_rtx_PLUS (SImode
, tmp
, GEN_INT (cf
));
4899 emit_move_insn (out
, tmp
);
4904 clob
= gen_rtx_REG (CCmode
, FLAGS_REG
);
4905 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
4907 tmp
= gen_rtx_SET (VOIDmode
, out
, tmp
);
4908 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
4912 emit_insn (gen_rtx_SET (VOIDmode
, out
, tmp
));
4914 if (out
!= operands
[0])
4915 emit_move_insn (operands
[0], out
);
4917 return 1; /* DONE */
4921 * General case: Jumpful:
4922 * xorl dest,dest cmpl op1, op2
4923 * cmpl op1, op2 movl ct, dest
4925 * decl dest movl cf, dest
4926 * andl (cf-ct),dest 1:
4931 * This is reasonably steep, but branch mispredict costs are
4932 * high on modern cpus, so consider failing only if optimizing
4935 * %%% Parameterize branch_cost on the tuning architecture, then
4936 * use that. The 80386 couldn't care less about mispredicts.
4939 if (!optimize_size
&& !TARGET_CMOVE
)
4945 compare_code
= reverse_condition (compare_code
);
4946 code
= reverse_condition (code
);
4949 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
4950 ix86_compare_op1
, VOIDmode
, 0, 1);
4952 emit_insn (gen_addsi3 (out
, out
, constm1_rtx
));
4953 emit_insn (gen_andsi3 (out
, out
, GEN_INT (cf
-ct
)));
4955 emit_insn (gen_addsi3 (out
, out
, GEN_INT (ct
)));
4956 if (out
!= operands
[0])
4957 emit_move_insn (operands
[0], out
);
4959 return 1; /* DONE */
4965 /* Try a few things more with specific constants and a variable. */
4968 rtx var
, orig_out
, out
, tmp
;
4971 return 0; /* FAIL */
4973 /* If one of the two operands is an interesting constant, load a
4974 constant with the above and mask it in with a logical operation. */
4976 if (GET_CODE (operands
[2]) == CONST_INT
)
4979 if (INTVAL (operands
[2]) == 0)
4980 operands
[3] = constm1_rtx
, op
= and_optab
;
4981 else if (INTVAL (operands
[2]) == -1)
4982 operands
[3] = const0_rtx
, op
= ior_optab
;
4984 return 0; /* FAIL */
4986 else if (GET_CODE (operands
[3]) == CONST_INT
)
4989 if (INTVAL (operands
[3]) == 0)
4990 operands
[2] = constm1_rtx
, op
= and_optab
;
4991 else if (INTVAL (operands
[3]) == -1)
4992 operands
[2] = const0_rtx
, op
= ior_optab
;
4994 return 0; /* FAIL */
4997 return 0; /* FAIL */
4999 orig_out
= operands
[0];
5000 tmp
= gen_reg_rtx (GET_MODE (orig_out
));
5003 /* Recurse to get the constant loaded. */
5004 if (ix86_expand_int_movcc (operands
) == 0)
5005 return 0; /* FAIL */
5007 /* Mask in the interesting variable. */
5008 out
= expand_binop (GET_MODE (orig_out
), op
, var
, tmp
, orig_out
, 0,
5010 if (out
!= orig_out
)
5011 emit_move_insn (orig_out
, out
);
5013 return 1; /* DONE */
5017 * For comparison with above,
5027 if (! nonimmediate_operand (operands
[2], GET_MODE (operands
[0])))
5028 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
5029 if (! nonimmediate_operand (operands
[3], GET_MODE (operands
[0])))
5030 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
5032 emit_insn (compare_seq
);
5033 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
5034 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
5035 compare_op
, operands
[2],
5038 return 1; /* DONE */
5042 ix86_expand_fp_movcc (operands
)
5046 enum machine_mode mode
;
5049 /* The floating point conditional move instructions don't directly
5050 support conditions resulting from a signed integer comparison. */
5052 code
= GET_CODE (operands
[1]);
5059 tmp
= gen_reg_rtx (QImode
);
5060 ix86_expand_setcc (code
, 0, tmp
);
5062 ix86_compare_op0
= tmp
;
5063 ix86_compare_op1
= const0_rtx
;
5070 mode
= SELECT_CC_MODE (code
, ix86_compare_op0
, ix86_compare_op1
);
5071 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_REG (mode
, FLAGS_REG
),
5072 gen_rtx_COMPARE (mode
,
5074 ix86_compare_op1
)));
5075 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
5076 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
5077 gen_rtx_fmt_ee (code
, VOIDmode
,
5078 gen_rtx_REG (mode
, FLAGS_REG
),
5086 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
5087 works for floating pointer parameters and nonoffsetable memories.
5088 For pushes, it returns just stack offsets; the values will be saved
5089 in the right order. Maximally three parts are generated. */
5092 ix86_split_to_parts (operand
, parts
, mode
)
5095 enum machine_mode mode
;
5097 int size
= GET_MODE_SIZE (mode
) / 4;
5099 if (size
< 2 || size
> 3)
5102 /* Optimize constant pool reference to immediates. This is used by fp moves,
5103 that force all constants to memory to allow combining. */
5105 if (GET_CODE (operand
) == MEM
5106 && GET_CODE (XEXP (operand
, 0)) == SYMBOL_REF
5107 && CONSTANT_POOL_ADDRESS_P (XEXP (operand
, 0)))
5108 operand
= get_pool_constant (XEXP (operand
, 0));
5110 if (GET_CODE (operand
) == MEM
&& !offsettable_memref_p (operand
))
5112 /* The only non-offsetable memories we handle are pushes. */
5113 if (! push_operand (operand
, VOIDmode
))
5116 PUT_MODE (operand
, SImode
);
5117 parts
[0] = parts
[1] = parts
[2] = operand
;
5122 split_di (&operand
, 1, &parts
[0], &parts
[1]);
5125 if (REG_P (operand
))
5127 if (!reload_completed
)
5129 parts
[0] = gen_rtx_REG (SImode
, REGNO (operand
) + 0);
5130 parts
[1] = gen_rtx_REG (SImode
, REGNO (operand
) + 1);
5132 parts
[2] = gen_rtx_REG (SImode
, REGNO (operand
) + 2);
5134 else if (offsettable_memref_p (operand
))
5136 PUT_MODE (operand
, SImode
);
5138 parts
[1] = adj_offsettable_operand (operand
, 4);
5140 parts
[2] = adj_offsettable_operand (operand
, 8);
5142 else if (GET_CODE (operand
) == CONST_DOUBLE
)
5147 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
5151 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
5152 parts
[2] = GEN_INT (l
[2]);
5155 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
5160 parts
[1] = GEN_INT (l
[1]);
5161 parts
[0] = GEN_INT (l
[0]);
5171 /* Emit insns to perform a move or push of DI, DF, and XF values.
5172 Return false when normal moves are needed; true when all required
5173 insns have been emitted. Operands 2-4 contain the input values
5174 int the correct order; operands 5-7 contain the output values. */
5177 ix86_split_long_move (operands1
)
5182 int size
= GET_MODE_SIZE (GET_MODE (operands1
[0])) / 4;
5186 /* Make our own copy to avoid clobbering the operands. */
5187 operands
[0] = copy_rtx (operands1
[0]);
5188 operands
[1] = copy_rtx (operands1
[1]);
5190 if (size
< 2 || size
> 3)
5193 /* The only non-offsettable memory we handle is push. */
5194 if (push_operand (operands
[0], VOIDmode
))
5196 else if (GET_CODE (operands
[0]) == MEM
5197 && ! offsettable_memref_p (operands
[0]))
5200 ix86_split_to_parts (operands
[0], part
[0], GET_MODE (operands1
[0]));
5201 ix86_split_to_parts (operands
[1], part
[1], GET_MODE (operands1
[0]));
5203 /* When emitting push, take care for source operands on the stack. */
5204 if (push
&& GET_CODE (operands
[1]) == MEM
5205 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
5208 part
[1][1] = part
[1][2];
5209 part
[1][0] = part
[1][1];
5212 /* We need to do copy in the right order in case an address register
5213 of the source overlaps the destination. */
5214 if (REG_P (part
[0][0]) && GET_CODE (part
[1][0]) == MEM
)
5216 if (reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0)))
5218 if (reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
5221 && reg_overlap_mentioned_p (part
[0][2], XEXP (part
[1][0], 0)))
5224 /* Collision in the middle part can be handled by reordering. */
5225 if (collisions
== 1 && size
== 3
5226 && reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
5229 tmp
= part
[0][1]; part
[0][1] = part
[0][2]; part
[0][2] = tmp
;
5230 tmp
= part
[1][1]; part
[1][1] = part
[1][2]; part
[1][2] = tmp
;
5233 /* If there are more collisions, we can't handle it by reordering.
5234 Do an lea to the last part and use only one colliding move. */
5235 else if (collisions
> 1)
5238 emit_insn (gen_rtx_SET (VOIDmode
, part
[0][size
- 1],
5239 XEXP (part
[1][0], 0)));
5240 part
[1][0] = change_address (part
[1][0], SImode
, part
[0][size
- 1]);
5241 part
[1][1] = adj_offsettable_operand (part
[1][0], 4);
5243 part
[1][2] = adj_offsettable_operand (part
[1][0], 8);
5250 emit_insn (gen_push (part
[1][2]));
5251 emit_insn (gen_push (part
[1][1]));
5252 emit_insn (gen_push (part
[1][0]));
5256 /* Choose correct order to not overwrite the source before it is copied. */
5257 if ((REG_P (part
[0][0])
5258 && REG_P (part
[1][1])
5259 && (REGNO (part
[0][0]) == REGNO (part
[1][1])
5261 && REGNO (part
[0][0]) == REGNO (part
[1][2]))))
5263 && reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0))))
5267 operands1
[2] = part
[0][2];
5268 operands1
[3] = part
[0][1];
5269 operands1
[4] = part
[0][0];
5270 operands1
[5] = part
[1][2];
5271 operands1
[6] = part
[1][1];
5272 operands1
[7] = part
[1][0];
5276 operands1
[2] = part
[0][1];
5277 operands1
[3] = part
[0][0];
5278 operands1
[5] = part
[1][1];
5279 operands1
[6] = part
[1][0];
5286 operands1
[2] = part
[0][0];
5287 operands1
[3] = part
[0][1];
5288 operands1
[4] = part
[0][2];
5289 operands1
[5] = part
[1][0];
5290 operands1
[6] = part
[1][1];
5291 operands1
[7] = part
[1][2];
5295 operands1
[2] = part
[0][0];
5296 operands1
[3] = part
[0][1];
5297 operands1
[5] = part
[1][0];
5298 operands1
[6] = part
[1][1];
5306 ix86_split_ashldi (operands
, scratch
)
5307 rtx
*operands
, scratch
;
5309 rtx low
[2], high
[2];
5312 if (GET_CODE (operands
[2]) == CONST_INT
)
5314 split_di (operands
, 2, low
, high
);
5315 count
= INTVAL (operands
[2]) & 63;
5319 emit_move_insn (high
[0], low
[1]);
5320 emit_move_insn (low
[0], const0_rtx
);
5323 emit_insn (gen_ashlsi3 (high
[0], high
[0], GEN_INT (count
- 32)));
5327 if (!rtx_equal_p (operands
[0], operands
[1]))
5328 emit_move_insn (operands
[0], operands
[1]);
5329 emit_insn (gen_x86_shld_1 (high
[0], low
[0], GEN_INT (count
)));
5330 emit_insn (gen_ashlsi3 (low
[0], low
[0], GEN_INT (count
)));
5335 if (!rtx_equal_p (operands
[0], operands
[1]))
5336 emit_move_insn (operands
[0], operands
[1]);
5338 split_di (operands
, 1, low
, high
);
5340 emit_insn (gen_x86_shld_1 (high
[0], low
[0], operands
[2]));
5341 emit_insn (gen_ashlsi3 (low
[0], low
[0], operands
[2]));
5343 if (TARGET_CMOVE
&& (! reload_completed
|| scratch
))
5345 if (! reload_completed
)
5346 scratch
= force_reg (SImode
, const0_rtx
);
5348 emit_move_insn (scratch
, const0_rtx
);
5350 emit_insn (gen_x86_shift_adj_1 (high
[0], low
[0], operands
[2],
5354 emit_insn (gen_x86_shift_adj_2 (high
[0], low
[0], operands
[2]));
5359 ix86_split_ashrdi (operands
, scratch
)
5360 rtx
*operands
, scratch
;
5362 rtx low
[2], high
[2];
5365 if (GET_CODE (operands
[2]) == CONST_INT
)
5367 split_di (operands
, 2, low
, high
);
5368 count
= INTVAL (operands
[2]) & 63;
5372 emit_move_insn (low
[0], high
[1]);
5374 if (! reload_completed
)
5375 emit_insn (gen_ashrsi3 (high
[0], low
[0], GEN_INT (31)));
5378 emit_move_insn (high
[0], low
[0]);
5379 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (31)));
5383 emit_insn (gen_ashrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
5387 if (!rtx_equal_p (operands
[0], operands
[1]))
5388 emit_move_insn (operands
[0], operands
[1]);
5389 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
5390 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (count
)));
5395 if (!rtx_equal_p (operands
[0], operands
[1]))
5396 emit_move_insn (operands
[0], operands
[1]);
5398 split_di (operands
, 1, low
, high
);
5400 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
5401 emit_insn (gen_ashrsi3 (high
[0], high
[0], operands
[2]));
5403 if (TARGET_CMOVE
&& (!reload_completed
|| scratch
))
5405 if (! reload_completed
)
5406 scratch
= gen_reg_rtx (SImode
);
5407 emit_move_insn (scratch
, high
[0]);
5408 emit_insn (gen_ashrsi3 (scratch
, scratch
, GEN_INT (31)));
5409 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
5413 emit_insn (gen_x86_shift_adj_3 (low
[0], high
[0], operands
[2]));
5418 ix86_split_lshrdi (operands
, scratch
)
5419 rtx
*operands
, scratch
;
5421 rtx low
[2], high
[2];
5424 if (GET_CODE (operands
[2]) == CONST_INT
)
5426 split_di (operands
, 2, low
, high
);
5427 count
= INTVAL (operands
[2]) & 63;
5431 emit_move_insn (low
[0], high
[1]);
5432 emit_move_insn (high
[0], const0_rtx
);
5435 emit_insn (gen_lshrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
5439 if (!rtx_equal_p (operands
[0], operands
[1]))
5440 emit_move_insn (operands
[0], operands
[1]);
5441 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
5442 emit_insn (gen_lshrsi3 (high
[0], high
[0], GEN_INT (count
)));
5447 if (!rtx_equal_p (operands
[0], operands
[1]))
5448 emit_move_insn (operands
[0], operands
[1]);
5450 split_di (operands
, 1, low
, high
);
5452 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
5453 emit_insn (gen_lshrsi3 (high
[0], high
[0], operands
[2]));
5455 /* Heh. By reversing the arguments, we can reuse this pattern. */
5456 if (TARGET_CMOVE
&& (! reload_completed
|| scratch
))
5458 if (! reload_completed
)
5459 scratch
= force_reg (SImode
, const0_rtx
);
5461 emit_move_insn (scratch
, const0_rtx
);
5463 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
5467 emit_insn (gen_x86_shift_adj_2 (low
[0], high
[0], operands
[2]));
5471 /* Expand the appropriate insns for doing strlen if not just doing
5474 out = result, initialized with the start address
5475 align_rtx = alignment of the address.
5476 scratch = scratch register, initialized with the startaddress when
5477 not aligned, otherwise undefined
5479 This is just the body. It needs the initialisations mentioned above and
5480 some address computing at the end. These things are done in i386.md. */
5483 ix86_expand_strlensi_unroll_1 (out
, align_rtx
, scratch
)
5484 rtx out
, align_rtx
, scratch
;
5488 rtx align_2_label
= NULL_RTX
;
5489 rtx align_3_label
= NULL_RTX
;
5490 rtx align_4_label
= gen_label_rtx ();
5491 rtx end_0_label
= gen_label_rtx ();
5493 rtx flags
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
5494 rtx tmpreg
= gen_reg_rtx (SImode
);
5497 if (GET_CODE (align_rtx
) == CONST_INT
)
5498 align
= INTVAL (align_rtx
);
5500 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
5502 /* Is there a known alignment and is it less than 4? */
5505 /* Is there a known alignment and is it not 2? */
5508 align_3_label
= gen_label_rtx (); /* Label when aligned to 3-byte */
5509 align_2_label
= gen_label_rtx (); /* Label when aligned to 2-byte */
5511 /* Leave just the 3 lower bits. */
5512 align_rtx
= expand_binop (SImode
, and_optab
, scratch
, GEN_INT (3),
5513 NULL_RTX
, 0, OPTAB_WIDEN
);
5515 emit_insn (gen_cmpsi_0 (align_rtx
, const0_rtx
));
5517 tmp
= gen_rtx_EQ (VOIDmode
, flags
, const0_rtx
);
5518 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5519 gen_rtx_LABEL_REF (VOIDmode
,
5522 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5524 emit_insn (gen_cmpsi_1 (align_rtx
, GEN_INT (2)));
5526 tmp
= gen_rtx_EQ (VOIDmode
, flags
, const0_rtx
);
5527 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5528 gen_rtx_LABEL_REF (VOIDmode
,
5531 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5533 tmp
= gen_rtx_GTU (VOIDmode
, flags
, const0_rtx
);
5534 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5535 gen_rtx_LABEL_REF (VOIDmode
,
5538 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5542 /* Since the alignment is 2, we have to check 2 or 0 bytes;
5543 check if is aligned to 4 - byte. */
5545 align_rtx
= expand_binop (SImode
, and_optab
, scratch
, GEN_INT (2),
5546 NULL_RTX
, 0, OPTAB_WIDEN
);
5548 emit_insn (gen_cmpsi_0 (align_rtx
, const0_rtx
));
5550 tmp
= gen_rtx_EQ (VOIDmode
, flags
, const0_rtx
);
5551 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5552 gen_rtx_LABEL_REF (VOIDmode
,
5555 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5558 mem
= gen_rtx_MEM (QImode
, out
);
5560 /* Now compare the bytes. */
5562 /* Compare the first n unaligned byte on a byte per byte basis. */
5563 emit_insn (gen_cmpqi_0 (mem
, const0_rtx
));
5565 tmp
= gen_rtx_EQ (VOIDmode
, flags
, const0_rtx
);
5566 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5567 gen_rtx_LABEL_REF (VOIDmode
, end_0_label
),
5569 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5571 /* Increment the address. */
5572 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
5574 /* Not needed with an alignment of 2 */
5577 emit_label (align_2_label
);
5579 emit_insn (gen_cmpqi_0 (mem
, const0_rtx
));
5581 tmp
= gen_rtx_EQ (VOIDmode
, flags
, const0_rtx
);
5582 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5583 gen_rtx_LABEL_REF (VOIDmode
,
5586 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5588 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
5590 emit_label (align_3_label
);
5593 emit_insn (gen_cmpqi_0 (mem
, const0_rtx
));
5595 tmp
= gen_rtx_EQ (VOIDmode
, flags
, const0_rtx
);
5596 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5597 gen_rtx_LABEL_REF (VOIDmode
, end_0_label
),
5599 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5601 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
5604 /* Generate loop to check 4 bytes at a time. It is not a good idea to
5605 align this loop. It gives only huge programs, but does not help to
5607 emit_label (align_4_label
);
5609 mem
= gen_rtx_MEM (SImode
, out
);
5610 emit_move_insn (scratch
, mem
);
5611 emit_insn (gen_addsi3 (out
, out
, GEN_INT (4)));
5613 /* This formula yields a nonzero result iff one of the bytes is zero.
5614 This saves three branches inside loop and many cycles. */
5616 emit_insn (gen_addsi3 (tmpreg
, scratch
, GEN_INT (-0x01010101)));
5617 emit_insn (gen_one_cmplsi2 (scratch
, scratch
));
5618 emit_insn (gen_andsi3 (tmpreg
, tmpreg
, scratch
));
5619 emit_insn (gen_andsi3 (tmpreg
, tmpreg
, GEN_INT (0x80808080)));
5620 emit_cmp_and_jump_insns (tmpreg
, const0_rtx
, EQ
, 0, SImode
, 1, 0, align_4_label
);
5624 rtx reg
= gen_reg_rtx (SImode
);
5625 emit_move_insn (reg
, tmpreg
);
5626 emit_insn (gen_lshrsi3 (reg
, reg
, GEN_INT (16)));
5628 /* If zero is not in the first two bytes, move two bytes forward. */
5629 emit_insn (gen_testsi_1 (tmpreg
, GEN_INT (0x8080)));
5630 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
5631 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
5632 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
,
5633 gen_rtx_IF_THEN_ELSE (SImode
, tmp
,
5636 /* Emit lea manually to avoid clobbering of flags. */
5637 emit_insn (gen_rtx_SET (SImode
, reg
,
5638 gen_rtx_PLUS (SImode
, out
, GEN_INT (2))));
5640 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
5641 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
5642 emit_insn (gen_rtx_SET (VOIDmode
, out
,
5643 gen_rtx_IF_THEN_ELSE (SImode
, tmp
,
5650 rtx end_2_label
= gen_label_rtx ();
5651 /* Is zero in the first two bytes? */
5653 emit_insn (gen_testsi_1 (tmpreg
, GEN_INT (0x8080)));
5654 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
5655 tmp
= gen_rtx_NE (VOIDmode
, tmp
, const0_rtx
);
5656 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5657 gen_rtx_LABEL_REF (VOIDmode
, end_2_label
),
5659 tmp
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5660 JUMP_LABEL (tmp
) = end_2_label
;
5662 /* Not in the first two. Move two bytes forward. */
5663 emit_insn (gen_lshrsi3 (tmpreg
, tmpreg
, GEN_INT (16)));
5664 emit_insn (gen_addsi3 (out
, out
, GEN_INT (2)));
5666 emit_label (end_2_label
);
5670 /* Avoid branch in fixing the byte. */
5671 tmpreg
= gen_lowpart (QImode
, tmpreg
);
5672 emit_insn (gen_addqi3_cc (tmpreg
, tmpreg
, tmpreg
));
5673 emit_insn (gen_subsi3_carry (out
, out
, GEN_INT (3)));
5675 emit_label (end_0_label
);
5678 /* Clear stack slot assignments remembered from previous functions.
5679 This is called from INIT_EXPANDERS once before RTL is emitted for each
5683 ix86_init_machine_status (p
)
5686 enum machine_mode mode
;
5689 = (struct machine_function
*) xmalloc (sizeof (struct machine_function
));
5691 for (mode
= VOIDmode
; (int) mode
< (int) MAX_MACHINE_MODE
;
5692 mode
= (enum machine_mode
) ((int) mode
+ 1))
5693 for (n
= 0; n
< MAX_386_STACK_LOCALS
; n
++)
5694 ix86_stack_locals
[(int) mode
][n
] = NULL_RTX
;
5697 /* Mark machine specific bits of P for GC. */
5699 ix86_mark_machine_status (p
)
5702 enum machine_mode mode
;
5705 for (mode
= VOIDmode
; (int) mode
< (int) MAX_MACHINE_MODE
;
5706 mode
= (enum machine_mode
) ((int) mode
+ 1))
5707 for (n
= 0; n
< MAX_386_STACK_LOCALS
; n
++)
5708 ggc_mark_rtx (p
->machine
->stack_locals
[(int) mode
][n
]);
5711 /* Return a MEM corresponding to a stack slot with mode MODE.
5712 Allocate a new slot if necessary.
5714 The RTL for a function can have several slots available: N is
5715 which slot to use. */
5718 assign_386_stack_local (mode
, n
)
5719 enum machine_mode mode
;
5722 if (n
< 0 || n
>= MAX_386_STACK_LOCALS
)
5725 if (ix86_stack_locals
[(int) mode
][n
] == NULL_RTX
)
5726 ix86_stack_locals
[(int) mode
][n
]
5727 = assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
5729 return ix86_stack_locals
[(int) mode
][n
];
5732 /* Calculate the length of the memory address in the instruction
5733 encoding. Does not include the one-byte modrm, opcode, or prefix. */
5736 memory_address_length (addr
)
5739 struct ix86_address parts
;
5740 rtx base
, index
, disp
;
5743 if (GET_CODE (addr
) == PRE_DEC
5744 || GET_CODE (addr
) == POST_INC
)
5747 if (! ix86_decompose_address (addr
, &parts
))
5751 index
= parts
.index
;
5755 /* Register Indirect. */
5756 if (base
&& !index
&& !disp
)
5758 /* Special cases: ebp and esp need the two-byte modrm form. */
5759 if (addr
== stack_pointer_rtx
5760 || addr
== arg_pointer_rtx
5761 || addr
== frame_pointer_rtx
5762 || addr
== hard_frame_pointer_rtx
)
5766 /* Direct Addressing. */
5767 else if (disp
&& !base
&& !index
)
5772 /* Find the length of the displacement constant. */
5775 if (GET_CODE (disp
) == CONST_INT
5776 && CONST_OK_FOR_LETTER_P (INTVAL (disp
), 'K'))
5782 /* An index requires the two-byte modrm form. */
5791 ix86_attr_length_default (insn
)
5794 enum attr_type type
;
5797 type
= get_attr_type (insn
);
5798 extract_insn (insn
);
5829 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
5830 if (CONSTANT_P (recog_data
.operand
[i
]))
5832 if (GET_CODE (recog_data
.operand
[i
]) == CONST_INT
5833 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data
.operand
[i
]), 'K'))
5836 len
+= GET_MODE_SIZE (GET_MODE (recog_data
.operand
[0]));
5841 if (CONSTANT_P (recog_data
.operand
[1]))
5842 len
+= GET_MODE_SIZE (GET_MODE (recog_data
.operand
[0]));
5846 if (constant_call_address_operand (recog_data
.operand
[0],
5847 GET_MODE (recog_data
.operand
[0])))
5852 if (constant_call_address_operand (recog_data
.operand
[1],
5853 GET_MODE (recog_data
.operand
[1])))
5859 /* Irritatingly, single_set doesn't work with REG_UNUSED present,
5860 as we'll get from running life_analysis during reg-stack when
5861 not optimizing. Not that it matters anyway, now that
5862 pro_epilogue_adjust_stack uses lea, and is by design not
5864 rtx set
= PATTERN (insn
);
5865 if (GET_CODE (set
) == SET
)
5867 else if (GET_CODE (set
) == PARALLEL
5868 && GET_CODE (XVECEXP (set
, 0, 0)) == SET
)
5869 set
= XVECEXP (set
, 0, 0);
5873 len
+= memory_address_length (SET_SRC (set
));
5882 if (STACK_TOP_P (recog_data
.operand
[0]))
5883 return 2 + (REGNO (recog_data
.operand
[1]) != FIRST_STACK_REG
+ 1);
5885 return 2 + (REGNO (recog_data
.operand
[0]) != FIRST_STACK_REG
+ 1);
5891 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
5892 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
5894 len
+= memory_address_length (XEXP (recog_data
.operand
[i
], 0));
5899 len
+= get_attr_length_opcode (insn
);
5900 len
+= get_attr_length_prefix (insn
);
5905 /* Return the maximum number of instructions a cpu can issue. */
5912 case PROCESSOR_PENTIUM
:
5916 case PROCESSOR_PENTIUMPRO
:
5924 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
5925 by DEP_INSN and nothing set by DEP_INSN. */
5928 ix86_flags_dependant (insn
, dep_insn
, insn_type
)
5930 enum attr_type insn_type
;
5934 /* Simplify the test for uninteresting insns. */
5935 if (insn_type
!= TYPE_SETCC
5936 && insn_type
!= TYPE_ICMOV
5937 && insn_type
!= TYPE_FCMOV
5938 && insn_type
!= TYPE_IBR
)
5941 if ((set
= single_set (dep_insn
)) != 0)
5943 set
= SET_DEST (set
);
5946 else if (GET_CODE (PATTERN (dep_insn
)) == PARALLEL
5947 && XVECLEN (PATTERN (dep_insn
), 0) == 2
5948 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 0)) == SET
5949 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 1)) == SET
)
5951 set
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
5952 set2
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
5957 if (GET_CODE (set
) != REG
|| REGNO (set
) != FLAGS_REG
)
5960 /* This test is true if the dependant insn reads the flags but
5961 not any other potentially set register. */
5962 if (!reg_overlap_mentioned_p (set
, PATTERN (insn
)))
5965 if (set2
&& reg_overlap_mentioned_p (set2
, PATTERN (insn
)))
5971 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
5972 address with operands set by DEP_INSN. */
5975 ix86_agi_dependant (insn
, dep_insn
, insn_type
)
5977 enum attr_type insn_type
;
5981 if (insn_type
== TYPE_LEA
)
5983 addr
= PATTERN (insn
);
5984 if (GET_CODE (addr
) == SET
)
5986 else if (GET_CODE (addr
) == PARALLEL
5987 && GET_CODE (XVECEXP (addr
, 0, 0)) == SET
)
5988 addr
= XVECEXP (addr
, 0, 0);
5991 addr
= SET_SRC (addr
);
5996 extract_insn (insn
);
5997 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
5998 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
6000 addr
= XEXP (recog_data
.operand
[i
], 0);
6007 return modified_in_p (addr
, dep_insn
);
6011 ix86_adjust_cost (insn
, link
, dep_insn
, cost
)
6012 rtx insn
, link
, dep_insn
;
6015 enum attr_type insn_type
, dep_insn_type
;
6017 int dep_insn_code_number
;
6019 /* Anti and output depenancies have zero cost on all CPUs. */
6020 if (REG_NOTE_KIND (link
) != 0)
6023 dep_insn_code_number
= recog_memoized (dep_insn
);
6025 /* If we can't recognize the insns, we can't really do anything. */
6026 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
6029 insn_type
= get_attr_type (insn
);
6030 dep_insn_type
= get_attr_type (dep_insn
);
6032 /* Prologue and epilogue allocators can have a false dependency on ebp.
6033 This results in one cycle extra stall on Pentium prologue scheduling,
6034 so handle this important case manually. */
6035 if (dep_insn_code_number
== CODE_FOR_pro_epilogue_adjust_stack
6036 && dep_insn_type
== TYPE_ALU
6037 && !reg_mentioned_p (stack_pointer_rtx
, insn
))
6042 case PROCESSOR_PENTIUM
:
6043 /* Address Generation Interlock adds a cycle of latency. */
6044 if (ix86_agi_dependant (insn
, dep_insn
, insn_type
))
6047 /* ??? Compares pair with jump/setcc. */
6048 if (ix86_flags_dependant (insn
, dep_insn
, insn_type
))
6051 /* Floating point stores require value to be ready one cycle ealier. */
6052 if (insn_type
== TYPE_FMOV
6053 && get_attr_memory (insn
) == MEMORY_STORE
6054 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
6058 case PROCESSOR_PENTIUMPRO
:
6059 /* Since we can't represent delayed latencies of load+operation,
6060 increase the cost here for non-imov insns. */
6061 if (dep_insn_type
!= TYPE_IMOV
6062 && dep_insn_type
!= TYPE_FMOV
6063 && get_attr_memory (dep_insn
) == MEMORY_LOAD
)
6066 /* INT->FP conversion is expensive. */
6067 if (get_attr_fp_int_src (dep_insn
))
6070 /* There is one cycle extra latency between an FP op and a store. */
6071 if (insn_type
== TYPE_FMOV
6072 && (set
= single_set (dep_insn
)) != NULL_RTX
6073 && (set2
= single_set (insn
)) != NULL_RTX
6074 && rtx_equal_p (SET_DEST (set
), SET_SRC (set2
))
6075 && GET_CODE (SET_DEST (set2
)) == MEM
)
6080 /* The esp dependency is resolved before the instruction is really
6082 if ((insn_type
== TYPE_PUSH
|| insn_type
== TYPE_POP
)
6083 && (dep_insn_type
== TYPE_PUSH
|| dep_insn_type
== TYPE_POP
))
6086 /* Since we can't represent delayed latencies of load+operation,
6087 increase the cost here for non-imov insns. */
6088 if (get_attr_memory (dep_insn
) == MEMORY_LOAD
)
6089 cost
+= (dep_insn_type
!= TYPE_IMOV
) ? 2 : 1;
6091 /* INT->FP conversion is expensive. */
6092 if (get_attr_fp_int_src (dep_insn
))
6096 case PROCESSOR_ATHLON
:
6097 /* Address Generation Interlock cause problems on the Athlon CPU because
6098 the loads and stores are done in order so once one load or store has
6099 to wait, others must too, so penalize the AGIs slightly by one cycle.
6100 We might experiment with this value later. */
6101 if (ix86_agi_dependant (insn
, dep_insn
, insn_type
))
6104 /* Since we can't represent delayed latencies of load+operation,
6105 increase the cost here for non-imov insns. */
6106 if (dep_insn_type
!= TYPE_IMOV
6107 && dep_insn_type
!= TYPE_FMOV
6108 && get_attr_memory (dep_insn
) == MEMORY_LOAD
)
6119 struct ppro_sched_data
6122 int issued_this_cycle
;
6127 ix86_safe_length (insn
)
6130 if (recog_memoized (insn
) >= 0)
6131 return get_attr_length(insn
);
6137 ix86_safe_length_prefix (insn
)
6140 if (recog_memoized (insn
) >= 0)
6141 return get_attr_length(insn
);
6146 static enum attr_memory
6147 ix86_safe_memory (insn
)
6150 if (recog_memoized (insn
) >= 0)
6151 return get_attr_memory(insn
);
6153 return MEMORY_UNKNOWN
;
6156 static enum attr_pent_pair
6157 ix86_safe_pent_pair (insn
)
6160 if (recog_memoized (insn
) >= 0)
6161 return get_attr_pent_pair(insn
);
6163 return PENT_PAIR_NP
;
6166 static enum attr_ppro_uops
6167 ix86_safe_ppro_uops (insn
)
6170 if (recog_memoized (insn
) >= 0)
6171 return get_attr_ppro_uops (insn
);
6173 return PPRO_UOPS_MANY
;
6177 ix86_dump_ppro_packet (dump
)
6180 if (ix86_sched_data
.ppro
.decode
[0])
6182 fprintf (dump
, "PPRO packet: %d",
6183 INSN_UID (ix86_sched_data
.ppro
.decode
[0]));
6184 if (ix86_sched_data
.ppro
.decode
[1])
6185 fprintf (dump
, " %d", INSN_UID (ix86_sched_data
.ppro
.decode
[1]));
6186 if (ix86_sched_data
.ppro
.decode
[2])
6187 fprintf (dump
, " %d", INSN_UID (ix86_sched_data
.ppro
.decode
[2]));
6192 /* We're beginning a new block. Initialize data structures as necessary. */
6195 ix86_sched_init (dump
, sched_verbose
)
6196 FILE *dump ATTRIBUTE_UNUSED
;
6197 int sched_verbose ATTRIBUTE_UNUSED
;
6199 memset (&ix86_sched_data
, 0, sizeof (ix86_sched_data
));
6202 /* Shift INSN to SLOT, and shift everything else down. */
6205 ix86_reorder_insn (insnp
, slot
)
6212 insnp
[0] = insnp
[1];
6213 while (++insnp
!= slot
);
6218 /* Find an instruction with given pairability and minimal amount of cycles
6219 lost by the fact that the CPU waits for both pipelines to finish before
6220 reading next instructions. Also take care that both instructions together
6221 can not exceed 7 bytes. */
6224 ix86_pent_find_pair (e_ready
, ready
, type
, first
)
6227 enum attr_pent_pair type
;
6230 int mincycles
, cycles
;
6231 enum attr_pent_pair tmp
;
6232 enum attr_memory memory
;
6233 rtx
*insnp
, *bestinsnp
= NULL
;
6235 if (ix86_safe_length (first
) > 7 + ix86_safe_length_prefix (first
))
6238 memory
= ix86_safe_memory (first
);
6239 cycles
= result_ready_cost (first
);
6240 mincycles
= INT_MAX
;
6242 for (insnp
= e_ready
; insnp
>= ready
&& mincycles
; --insnp
)
6243 if ((tmp
= ix86_safe_pent_pair (*insnp
)) == type
6244 && ix86_safe_length (*insnp
) <= 7 + ix86_safe_length_prefix (*insnp
))
6246 enum attr_memory second_memory
;
6247 int secondcycles
, currentcycles
;
6249 second_memory
= ix86_safe_memory (*insnp
);
6250 secondcycles
= result_ready_cost (*insnp
);
6251 currentcycles
= abs (cycles
- secondcycles
);
6253 if (secondcycles
>= 1 && cycles
>= 1)
6255 /* Two read/modify/write instructions together takes two
6257 if (memory
== MEMORY_BOTH
&& second_memory
== MEMORY_BOTH
)
6260 /* Read modify/write instruction followed by read/modify
6261 takes one cycle longer. */
6262 if (memory
== MEMORY_BOTH
&& second_memory
== MEMORY_LOAD
6263 && tmp
!= PENT_PAIR_UV
6264 && ix86_safe_pent_pair (first
) != PENT_PAIR_UV
)
6267 if (currentcycles
< mincycles
)
6268 bestinsnp
= insnp
, mincycles
= currentcycles
;
6274 /* Subroutines of ix86_sched_reorder. */
6277 ix86_sched_reorder_pentium (ready
, e_ready
)
6281 enum attr_pent_pair pair1
, pair2
;
6284 /* This wouldn't be necessary if Haifa knew that static insn ordering
6285 is important to which pipe an insn is issued to. So we have to make
6286 some minor rearrangements. */
6288 pair1
= ix86_safe_pent_pair (*e_ready
);
6290 /* If the first insn is non-pairable, let it be. */
6291 if (pair1
== PENT_PAIR_NP
)
6294 pair2
= PENT_PAIR_NP
;
6297 /* If the first insn is UV or PV pairable, search for a PU
6299 if (pair1
== PENT_PAIR_UV
|| pair1
== PENT_PAIR_PV
)
6301 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
6302 PENT_PAIR_PU
, *e_ready
);
6304 pair2
= PENT_PAIR_PU
;
6307 /* If the first insn is PU or UV pairable, search for a PV
6309 if (pair2
== PENT_PAIR_NP
6310 && (pair1
== PENT_PAIR_PU
|| pair1
== PENT_PAIR_UV
))
6312 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
6313 PENT_PAIR_PV
, *e_ready
);
6315 pair2
= PENT_PAIR_PV
;
6318 /* If the first insn is pairable, search for a UV
6320 if (pair2
== PENT_PAIR_NP
)
6322 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
6323 PENT_PAIR_UV
, *e_ready
);
6325 pair2
= PENT_PAIR_UV
;
6328 if (pair2
== PENT_PAIR_NP
)
6331 /* Found something! Decide if we need to swap the order. */
6332 if (pair1
== PENT_PAIR_PV
|| pair2
== PENT_PAIR_PU
6333 || (pair1
== PENT_PAIR_UV
&& pair2
== PENT_PAIR_UV
6334 && ix86_safe_memory (*e_ready
) == MEMORY_BOTH
6335 && ix86_safe_memory (*insnp
) == MEMORY_LOAD
))
6336 ix86_reorder_insn (insnp
, e_ready
);
6338 ix86_reorder_insn (insnp
, e_ready
- 1);
6342 ix86_sched_reorder_ppro (ready
, e_ready
)
6347 enum attr_ppro_uops cur_uops
;
6348 int issued_this_cycle
;
6352 /* At this point .ppro.decode contains the state of the three
6353 decoders from last "cycle". That is, those insns that were
6354 actually independent. But here we're scheduling for the
6355 decoder, and we may find things that are decodable in the
6358 memcpy (decode
, ix86_sched_data
.ppro
.decode
, sizeof(decode
));
6359 issued_this_cycle
= 0;
6362 cur_uops
= ix86_safe_ppro_uops (*insnp
);
6364 /* If the decoders are empty, and we've a complex insn at the
6365 head of the priority queue, let it issue without complaint. */
6366 if (decode
[0] == NULL
)
6368 if (cur_uops
== PPRO_UOPS_MANY
)
6374 /* Otherwise, search for a 2-4 uop unsn to issue. */
6375 while (cur_uops
!= PPRO_UOPS_FEW
)
6379 cur_uops
= ix86_safe_ppro_uops (*--insnp
);
6382 /* If so, move it to the head of the line. */
6383 if (cur_uops
== PPRO_UOPS_FEW
)
6384 ix86_reorder_insn (insnp
, e_ready
);
6386 /* Issue the head of the queue. */
6387 issued_this_cycle
= 1;
6388 decode
[0] = *e_ready
--;
6391 /* Look for simple insns to fill in the other two slots. */
6392 for (i
= 1; i
< 3; ++i
)
6393 if (decode
[i
] == NULL
)
6395 if (ready
>= e_ready
)
6399 cur_uops
= ix86_safe_ppro_uops (*insnp
);
6400 while (cur_uops
!= PPRO_UOPS_ONE
)
6404 cur_uops
= ix86_safe_ppro_uops (*--insnp
);
6407 /* Found one. Move it to the head of the queue and issue it. */
6408 if (cur_uops
== PPRO_UOPS_ONE
)
6410 ix86_reorder_insn (insnp
, e_ready
);
6411 decode
[i
] = *e_ready
--;
6412 issued_this_cycle
++;
6416 /* ??? Didn't find one. Ideally, here we would do a lazy split
6417 of 2-uop insns, issue one and queue the other. */
6421 if (issued_this_cycle
== 0)
6422 issued_this_cycle
= 1;
6423 ix86_sched_data
.ppro
.issued_this_cycle
= issued_this_cycle
;
6427 /* We are about to being issuing insns for this clock cycle.
6428 Override the default sort algorithm to better slot instructions. */
6430 ix86_sched_reorder (dump
, sched_verbose
, ready
, n_ready
, clock_var
)
6431 FILE *dump ATTRIBUTE_UNUSED
;
6432 int sched_verbose ATTRIBUTE_UNUSED
;
6435 int clock_var ATTRIBUTE_UNUSED
;
6437 rtx
*e_ready
= ready
+ n_ready
- 1;
6447 case PROCESSOR_PENTIUM
:
6448 ix86_sched_reorder_pentium (ready
, e_ready
);
6451 case PROCESSOR_PENTIUMPRO
:
6452 ix86_sched_reorder_ppro (ready
, e_ready
);
6457 return ix86_issue_rate ();
6460 /* We are about to issue INSN. Return the number of insns left on the
6461 ready queue that can be issued this cycle. */
6464 ix86_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
)
6474 return can_issue_more
- 1;
6476 case PROCESSOR_PENTIUMPRO
:
6478 enum attr_ppro_uops uops
= ix86_safe_ppro_uops (insn
);
6480 if (uops
== PPRO_UOPS_MANY
)
6483 ix86_dump_ppro_packet (dump
);
6484 ix86_sched_data
.ppro
.decode
[0] = insn
;
6485 ix86_sched_data
.ppro
.decode
[1] = NULL
;
6486 ix86_sched_data
.ppro
.decode
[2] = NULL
;
6488 ix86_dump_ppro_packet (dump
);
6489 ix86_sched_data
.ppro
.decode
[0] = NULL
;
6491 else if (uops
== PPRO_UOPS_FEW
)
6494 ix86_dump_ppro_packet (dump
);
6495 ix86_sched_data
.ppro
.decode
[0] = insn
;
6496 ix86_sched_data
.ppro
.decode
[1] = NULL
;
6497 ix86_sched_data
.ppro
.decode
[2] = NULL
;
6501 for (i
= 0; i
< 3; ++i
)
6502 if (ix86_sched_data
.ppro
.decode
[i
] == NULL
)
6504 ix86_sched_data
.ppro
.decode
[i
] = insn
;
6512 ix86_dump_ppro_packet (dump
);
6513 ix86_sched_data
.ppro
.decode
[0] = NULL
;
6514 ix86_sched_data
.ppro
.decode
[1] = NULL
;
6515 ix86_sched_data
.ppro
.decode
[2] = NULL
;
6519 return --ix86_sched_data
.ppro
.issued_this_cycle
;