1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
52 #ifndef CHECK_STACK_LIMIT
53 #define CHECK_STACK_LIMIT (-1)
56 /* Return index of given mode in mult and division cost tables. */
57 #define MODE_INDEX(mode) \
58 ((mode) == QImode ? 0 \
59 : (mode) == HImode ? 1 \
60 : (mode) == SImode ? 2 \
61 : (mode) == DImode ? 3 \
64 /* Processor costs (relative to an add) */
66 struct processor_costs size_cost
= { /* costs for tunning for size */
67 2, /* cost of an add instruction */
68 3, /* cost of a lea instruction */
69 2, /* variable shift costs */
70 3, /* constant shift costs */
71 {3, 3, 3, 3, 5}, /* cost of starting a multiply */
72 0, /* cost of multiply per each bit set */
73 {3, 3, 3, 3, 5}, /* cost of a divide/mod */
74 3, /* cost of movsx */
75 3, /* cost of movzx */
78 2, /* cost for loading QImode using movzbl */
79 {2, 2, 2}, /* cost of loading integer registers
80 in QImode, HImode and SImode.
81 Relative to reg-reg move (2). */
82 {2, 2, 2}, /* cost of storing integer registers */
83 2, /* cost of reg,reg fld/fst */
84 {2, 2, 2}, /* cost of loading fp registers
85 in SFmode, DFmode and XFmode */
86 {2, 2, 2}, /* cost of loading integer registers */
87 3, /* cost of moving MMX register */
88 {3, 3}, /* cost of loading MMX registers
89 in SImode and DImode */
90 {3, 3}, /* cost of storing MMX registers
91 in SImode and DImode */
92 3, /* cost of moving SSE register */
93 {3, 3, 3}, /* cost of loading SSE registers
94 in SImode, DImode and TImode */
95 {3, 3, 3}, /* cost of storing SSE registers
96 in SImode, DImode and TImode */
97 3, /* MMX or SSE register to integer */
98 0, /* size of prefetch block */
99 0, /* number of parallel prefetches */
101 2, /* cost of FADD and FSUB insns. */
102 2, /* cost of FMUL instruction. */
103 2, /* cost of FDIV instruction. */
104 2, /* cost of FABS instruction. */
105 2, /* cost of FCHS instruction. */
106 2, /* cost of FSQRT instruction. */
109 /* Processor costs (relative to an add) */
111 struct processor_costs i386_cost
= { /* 386 specific costs */
112 1, /* cost of an add instruction */
113 1, /* cost of a lea instruction */
114 3, /* variable shift costs */
115 2, /* constant shift costs */
116 {6, 6, 6, 6, 6}, /* cost of starting a multiply */
117 1, /* cost of multiply per each bit set */
118 {23, 23, 23, 23, 23}, /* cost of a divide/mod */
119 3, /* cost of movsx */
120 2, /* cost of movzx */
121 15, /* "large" insn */
123 4, /* cost for loading QImode using movzbl */
124 {2, 4, 2}, /* cost of loading integer registers
125 in QImode, HImode and SImode.
126 Relative to reg-reg move (2). */
127 {2, 4, 2}, /* cost of storing integer registers */
128 2, /* cost of reg,reg fld/fst */
129 {8, 8, 8}, /* cost of loading fp registers
130 in SFmode, DFmode and XFmode */
131 {8, 8, 8}, /* cost of loading integer registers */
132 2, /* cost of moving MMX register */
133 {4, 8}, /* cost of loading MMX registers
134 in SImode and DImode */
135 {4, 8}, /* cost of storing MMX registers
136 in SImode and DImode */
137 2, /* cost of moving SSE register */
138 {4, 8, 16}, /* cost of loading SSE registers
139 in SImode, DImode and TImode */
140 {4, 8, 16}, /* cost of storing SSE registers
141 in SImode, DImode and TImode */
142 3, /* MMX or SSE register to integer */
143 0, /* size of prefetch block */
144 0, /* number of parallel prefetches */
146 23, /* cost of FADD and FSUB insns. */
147 27, /* cost of FMUL instruction. */
148 88, /* cost of FDIV instruction. */
149 22, /* cost of FABS instruction. */
150 24, /* cost of FCHS instruction. */
151 122, /* cost of FSQRT instruction. */
155 struct processor_costs i486_cost
= { /* 486 specific costs */
156 1, /* cost of an add instruction */
157 1, /* cost of a lea instruction */
158 3, /* variable shift costs */
159 2, /* constant shift costs */
160 {12, 12, 12, 12, 12}, /* cost of starting a multiply */
161 1, /* cost of multiply per each bit set */
162 {40, 40, 40, 40, 40}, /* cost of a divide/mod */
163 3, /* cost of movsx */
164 2, /* cost of movzx */
165 15, /* "large" insn */
167 4, /* cost for loading QImode using movzbl */
168 {2, 4, 2}, /* cost of loading integer registers
169 in QImode, HImode and SImode.
170 Relative to reg-reg move (2). */
171 {2, 4, 2}, /* cost of storing integer registers */
172 2, /* cost of reg,reg fld/fst */
173 {8, 8, 8}, /* cost of loading fp registers
174 in SFmode, DFmode and XFmode */
175 {8, 8, 8}, /* cost of loading integer registers */
176 2, /* cost of moving MMX register */
177 {4, 8}, /* cost of loading MMX registers
178 in SImode and DImode */
179 {4, 8}, /* cost of storing MMX registers
180 in SImode and DImode */
181 2, /* cost of moving SSE register */
182 {4, 8, 16}, /* cost of loading SSE registers
183 in SImode, DImode and TImode */
184 {4, 8, 16}, /* cost of storing SSE registers
185 in SImode, DImode and TImode */
186 3, /* MMX or SSE register to integer */
187 0, /* size of prefetch block */
188 0, /* number of parallel prefetches */
190 8, /* cost of FADD and FSUB insns. */
191 16, /* cost of FMUL instruction. */
192 73, /* cost of FDIV instruction. */
193 3, /* cost of FABS instruction. */
194 3, /* cost of FCHS instruction. */
195 83, /* cost of FSQRT instruction. */
199 struct processor_costs pentium_cost
= {
200 1, /* cost of an add instruction */
201 1, /* cost of a lea instruction */
202 4, /* variable shift costs */
203 1, /* constant shift costs */
204 {11, 11, 11, 11, 11}, /* cost of starting a multiply */
205 0, /* cost of multiply per each bit set */
206 {25, 25, 25, 25, 25}, /* cost of a divide/mod */
207 3, /* cost of movsx */
208 2, /* cost of movzx */
209 8, /* "large" insn */
211 6, /* cost for loading QImode using movzbl */
212 {2, 4, 2}, /* cost of loading integer registers
213 in QImode, HImode and SImode.
214 Relative to reg-reg move (2). */
215 {2, 4, 2}, /* cost of storing integer registers */
216 2, /* cost of reg,reg fld/fst */
217 {2, 2, 6}, /* cost of loading fp registers
218 in SFmode, DFmode and XFmode */
219 {4, 4, 6}, /* cost of loading integer registers */
220 8, /* cost of moving MMX register */
221 {8, 8}, /* cost of loading MMX registers
222 in SImode and DImode */
223 {8, 8}, /* cost of storing MMX registers
224 in SImode and DImode */
225 2, /* cost of moving SSE register */
226 {4, 8, 16}, /* cost of loading SSE registers
227 in SImode, DImode and TImode */
228 {4, 8, 16}, /* cost of storing SSE registers
229 in SImode, DImode and TImode */
230 3, /* MMX or SSE register to integer */
231 0, /* size of prefetch block */
232 0, /* number of parallel prefetches */
234 3, /* cost of FADD and FSUB insns. */
235 3, /* cost of FMUL instruction. */
236 39, /* cost of FDIV instruction. */
237 1, /* cost of FABS instruction. */
238 1, /* cost of FCHS instruction. */
239 70, /* cost of FSQRT instruction. */
243 struct processor_costs pentiumpro_cost
= {
244 1, /* cost of an add instruction */
245 1, /* cost of a lea instruction */
246 1, /* variable shift costs */
247 1, /* constant shift costs */
248 {4, 4, 4, 4, 4}, /* cost of starting a multiply */
249 0, /* cost of multiply per each bit set */
250 {17, 17, 17, 17, 17}, /* cost of a divide/mod */
251 1, /* cost of movsx */
252 1, /* cost of movzx */
253 8, /* "large" insn */
255 2, /* cost for loading QImode using movzbl */
256 {4, 4, 4}, /* cost of loading integer registers
257 in QImode, HImode and SImode.
258 Relative to reg-reg move (2). */
259 {2, 2, 2}, /* cost of storing integer registers */
260 2, /* cost of reg,reg fld/fst */
261 {2, 2, 6}, /* cost of loading fp registers
262 in SFmode, DFmode and XFmode */
263 {4, 4, 6}, /* cost of loading integer registers */
264 2, /* cost of moving MMX register */
265 {2, 2}, /* cost of loading MMX registers
266 in SImode and DImode */
267 {2, 2}, /* cost of storing MMX registers
268 in SImode and DImode */
269 2, /* cost of moving SSE register */
270 {2, 2, 8}, /* cost of loading SSE registers
271 in SImode, DImode and TImode */
272 {2, 2, 8}, /* cost of storing SSE registers
273 in SImode, DImode and TImode */
274 3, /* MMX or SSE register to integer */
275 32, /* size of prefetch block */
276 6, /* number of parallel prefetches */
278 3, /* cost of FADD and FSUB insns. */
279 5, /* cost of FMUL instruction. */
280 56, /* cost of FDIV instruction. */
281 2, /* cost of FABS instruction. */
282 2, /* cost of FCHS instruction. */
283 56, /* cost of FSQRT instruction. */
287 struct processor_costs k6_cost
= {
288 1, /* cost of an add instruction */
289 2, /* cost of a lea instruction */
290 1, /* variable shift costs */
291 1, /* constant shift costs */
292 {3, 3, 3, 3, 3}, /* cost of starting a multiply */
293 0, /* cost of multiply per each bit set */
294 {18, 18, 18, 18, 18}, /* cost of a divide/mod */
295 2, /* cost of movsx */
296 2, /* cost of movzx */
297 8, /* "large" insn */
299 3, /* cost for loading QImode using movzbl */
300 {4, 5, 4}, /* cost of loading integer registers
301 in QImode, HImode and SImode.
302 Relative to reg-reg move (2). */
303 {2, 3, 2}, /* cost of storing integer registers */
304 4, /* cost of reg,reg fld/fst */
305 {6, 6, 6}, /* cost of loading fp registers
306 in SFmode, DFmode and XFmode */
307 {4, 4, 4}, /* cost of loading integer registers */
308 2, /* cost of moving MMX register */
309 {2, 2}, /* cost of loading MMX registers
310 in SImode and DImode */
311 {2, 2}, /* cost of storing MMX registers
312 in SImode and DImode */
313 2, /* cost of moving SSE register */
314 {2, 2, 8}, /* cost of loading SSE registers
315 in SImode, DImode and TImode */
316 {2, 2, 8}, /* cost of storing SSE registers
317 in SImode, DImode and TImode */
318 6, /* MMX or SSE register to integer */
319 32, /* size of prefetch block */
320 1, /* number of parallel prefetches */
322 2, /* cost of FADD and FSUB insns. */
323 2, /* cost of FMUL instruction. */
324 56, /* cost of FDIV instruction. */
325 2, /* cost of FABS instruction. */
326 2, /* cost of FCHS instruction. */
327 56, /* cost of FSQRT instruction. */
331 struct processor_costs athlon_cost
= {
332 1, /* cost of an add instruction */
333 2, /* cost of a lea instruction */
334 1, /* variable shift costs */
335 1, /* constant shift costs */
336 {5, 5, 5, 5, 5}, /* cost of starting a multiply */
337 0, /* cost of multiply per each bit set */
338 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
339 1, /* cost of movsx */
340 1, /* cost of movzx */
341 8, /* "large" insn */
343 4, /* cost for loading QImode using movzbl */
344 {3, 4, 3}, /* cost of loading integer registers
345 in QImode, HImode and SImode.
346 Relative to reg-reg move (2). */
347 {3, 4, 3}, /* cost of storing integer registers */
348 4, /* cost of reg,reg fld/fst */
349 {4, 4, 12}, /* cost of loading fp registers
350 in SFmode, DFmode and XFmode */
351 {6, 6, 8}, /* cost of loading integer registers */
352 2, /* cost of moving MMX register */
353 {4, 4}, /* cost of loading MMX registers
354 in SImode and DImode */
355 {4, 4}, /* cost of storing MMX registers
356 in SImode and DImode */
357 2, /* cost of moving SSE register */
358 {4, 4, 6}, /* cost of loading SSE registers
359 in SImode, DImode and TImode */
360 {4, 4, 5}, /* cost of storing SSE registers
361 in SImode, DImode and TImode */
362 5, /* MMX or SSE register to integer */
363 64, /* size of prefetch block */
364 6, /* number of parallel prefetches */
366 4, /* cost of FADD and FSUB insns. */
367 4, /* cost of FMUL instruction. */
368 24, /* cost of FDIV instruction. */
369 2, /* cost of FABS instruction. */
370 2, /* cost of FCHS instruction. */
371 35, /* cost of FSQRT instruction. */
375 struct processor_costs k8_cost
= {
376 1, /* cost of an add instruction */
377 2, /* cost of a lea instruction */
378 1, /* variable shift costs */
379 1, /* constant shift costs */
380 {3, 4, 3, 4, 5}, /* cost of starting a multiply */
381 0, /* cost of multiply per each bit set */
382 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
383 1, /* cost of movsx */
384 1, /* cost of movzx */
385 8, /* "large" insn */
387 4, /* cost for loading QImode using movzbl */
388 {3, 4, 3}, /* cost of loading integer registers
389 in QImode, HImode and SImode.
390 Relative to reg-reg move (2). */
391 {3, 4, 3}, /* cost of storing integer registers */
392 4, /* cost of reg,reg fld/fst */
393 {4, 4, 12}, /* cost of loading fp registers
394 in SFmode, DFmode and XFmode */
395 {6, 6, 8}, /* cost of loading integer registers */
396 2, /* cost of moving MMX register */
397 {3, 3}, /* cost of loading MMX registers
398 in SImode and DImode */
399 {4, 4}, /* cost of storing MMX registers
400 in SImode and DImode */
401 2, /* cost of moving SSE register */
402 {4, 3, 6}, /* cost of loading SSE registers
403 in SImode, DImode and TImode */
404 {4, 4, 5}, /* cost of storing SSE registers
405 in SImode, DImode and TImode */
406 5, /* MMX or SSE register to integer */
407 64, /* size of prefetch block */
408 6, /* number of parallel prefetches */
410 4, /* cost of FADD and FSUB insns. */
411 4, /* cost of FMUL instruction. */
412 19, /* cost of FDIV instruction. */
413 2, /* cost of FABS instruction. */
414 2, /* cost of FCHS instruction. */
415 35, /* cost of FSQRT instruction. */
419 struct processor_costs pentium4_cost
= {
420 1, /* cost of an add instruction */
421 3, /* cost of a lea instruction */
422 4, /* variable shift costs */
423 4, /* constant shift costs */
424 {15, 15, 15, 15, 15}, /* cost of starting a multiply */
425 0, /* cost of multiply per each bit set */
426 {56, 56, 56, 56, 56}, /* cost of a divide/mod */
427 1, /* cost of movsx */
428 1, /* cost of movzx */
429 16, /* "large" insn */
431 2, /* cost for loading QImode using movzbl */
432 {4, 5, 4}, /* cost of loading integer registers
433 in QImode, HImode and SImode.
434 Relative to reg-reg move (2). */
435 {2, 3, 2}, /* cost of storing integer registers */
436 2, /* cost of reg,reg fld/fst */
437 {2, 2, 6}, /* cost of loading fp registers
438 in SFmode, DFmode and XFmode */
439 {4, 4, 6}, /* cost of loading integer registers */
440 2, /* cost of moving MMX register */
441 {2, 2}, /* cost of loading MMX registers
442 in SImode and DImode */
443 {2, 2}, /* cost of storing MMX registers
444 in SImode and DImode */
445 12, /* cost of moving SSE register */
446 {12, 12, 12}, /* cost of loading SSE registers
447 in SImode, DImode and TImode */
448 {2, 2, 8}, /* cost of storing SSE registers
449 in SImode, DImode and TImode */
450 10, /* MMX or SSE register to integer */
451 64, /* size of prefetch block */
452 6, /* number of parallel prefetches */
454 5, /* cost of FADD and FSUB insns. */
455 7, /* cost of FMUL instruction. */
456 43, /* cost of FDIV instruction. */
457 2, /* cost of FABS instruction. */
458 2, /* cost of FCHS instruction. */
459 43, /* cost of FSQRT instruction. */
463 struct processor_costs nocona_cost
= {
464 1, /* cost of an add instruction */
465 1, /* cost of a lea instruction */
466 1, /* variable shift costs */
467 1, /* constant shift costs */
468 {10, 10, 10, 10, 10}, /* cost of starting a multiply */
469 0, /* cost of multiply per each bit set */
470 {66, 66, 66, 66, 66}, /* cost of a divide/mod */
471 1, /* cost of movsx */
472 1, /* cost of movzx */
473 16, /* "large" insn */
475 4, /* cost for loading QImode using movzbl */
476 {4, 4, 4}, /* cost of loading integer registers
477 in QImode, HImode and SImode.
478 Relative to reg-reg move (2). */
479 {4, 4, 4}, /* cost of storing integer registers */
480 3, /* cost of reg,reg fld/fst */
481 {12, 12, 12}, /* cost of loading fp registers
482 in SFmode, DFmode and XFmode */
483 {4, 4, 4}, /* cost of loading integer registers */
484 6, /* cost of moving MMX register */
485 {12, 12}, /* cost of loading MMX registers
486 in SImode and DImode */
487 {12, 12}, /* cost of storing MMX registers
488 in SImode and DImode */
489 6, /* cost of moving SSE register */
490 {12, 12, 12}, /* cost of loading SSE registers
491 in SImode, DImode and TImode */
492 {12, 12, 12}, /* cost of storing SSE registers
493 in SImode, DImode and TImode */
494 8, /* MMX or SSE register to integer */
495 128, /* size of prefetch block */
496 8, /* number of parallel prefetches */
498 6, /* cost of FADD and FSUB insns. */
499 8, /* cost of FMUL instruction. */
500 40, /* cost of FDIV instruction. */
501 3, /* cost of FABS instruction. */
502 3, /* cost of FCHS instruction. */
503 44, /* cost of FSQRT instruction. */
506 const struct processor_costs
*ix86_cost
= &pentium_cost
;
508 /* Processor feature/optimization bitmasks. */
509 #define m_386 (1<<PROCESSOR_I386)
510 #define m_486 (1<<PROCESSOR_I486)
511 #define m_PENT (1<<PROCESSOR_PENTIUM)
512 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
513 #define m_K6 (1<<PROCESSOR_K6)
514 #define m_ATHLON (1<<PROCESSOR_ATHLON)
515 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
516 #define m_K8 (1<<PROCESSOR_K8)
517 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
518 #define m_NOCONA (1<<PROCESSOR_NOCONA)
520 const int x86_use_leave
= m_386
| m_K6
| m_ATHLON_K8
;
521 const int x86_push_memory
= m_386
| m_K6
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
522 const int x86_zero_extend_with_and
= m_486
| m_PENT
;
523 const int x86_movx
= m_ATHLON_K8
| m_PPRO
| m_PENT4
| m_NOCONA
/* m_386 | m_K6 */;
524 const int x86_double_with_add
= ~m_386
;
525 const int x86_use_bit_test
= m_386
;
526 const int x86_unroll_strlen
= m_486
| m_PENT
| m_PPRO
| m_ATHLON_K8
| m_K6
;
527 const int x86_cmove
= m_PPRO
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
528 const int x86_3dnow_a
= m_ATHLON_K8
;
529 const int x86_deep_branch
= m_PPRO
| m_K6
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
530 /* Branch hints were put in P4 based on simulation result. But
531 after P4 was made, no performance benefit was observed with
532 branch hints. It also increases the code size. As the result,
533 icc never generates branch hints. */
534 const int x86_branch_hints
= 0;
535 const int x86_use_sahf
= m_PPRO
| m_K6
| m_PENT4
| m_NOCONA
;
536 const int x86_partial_reg_stall
= m_PPRO
;
537 const int x86_use_loop
= m_K6
;
538 const int x86_use_fiop
= ~(m_PPRO
| m_ATHLON_K8
| m_PENT
);
539 const int x86_use_mov0
= m_K6
;
540 const int x86_use_cltd
= ~(m_PENT
| m_K6
);
541 const int x86_read_modify_write
= ~m_PENT
;
542 const int x86_read_modify
= ~(m_PENT
| m_PPRO
);
543 const int x86_split_long_moves
= m_PPRO
;
544 const int x86_promote_QImode
= m_K6
| m_PENT
| m_386
| m_486
| m_ATHLON_K8
;
545 const int x86_fast_prefix
= ~(m_PENT
| m_486
| m_386
);
546 const int x86_single_stringop
= m_386
| m_PENT4
| m_NOCONA
;
547 const int x86_qimode_math
= ~(0);
548 const int x86_promote_qi_regs
= 0;
549 const int x86_himode_math
= ~(m_PPRO
);
550 const int x86_promote_hi_regs
= m_PPRO
;
551 const int x86_sub_esp_4
= m_ATHLON_K8
| m_PPRO
| m_PENT4
| m_NOCONA
;
552 const int x86_sub_esp_8
= m_ATHLON_K8
| m_PPRO
| m_386
| m_486
| m_PENT4
| m_NOCONA
;
553 const int x86_add_esp_4
= m_ATHLON_K8
| m_K6
| m_PENT4
| m_NOCONA
;
554 const int x86_add_esp_8
= m_ATHLON_K8
| m_PPRO
| m_K6
| m_386
| m_486
| m_PENT4
| m_NOCONA
;
555 const int x86_integer_DFmode_moves
= ~(m_ATHLON_K8
| m_PENT4
| m_NOCONA
| m_PPRO
);
556 const int x86_partial_reg_dependency
= m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
557 const int x86_memory_mismatch_stall
= m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
558 const int x86_accumulate_outgoing_args
= m_ATHLON_K8
| m_PENT4
| m_NOCONA
| m_PPRO
;
559 const int x86_prologue_using_move
= m_ATHLON_K8
| m_PPRO
;
560 const int x86_epilogue_using_move
= m_ATHLON_K8
| m_PPRO
;
561 const int x86_decompose_lea
= m_PENT4
| m_NOCONA
;
562 const int x86_shift1
= ~m_486
;
563 const int x86_arch_always_fancy_math_387
= m_PENT
| m_PPRO
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
564 const int x86_sse_partial_reg_dependency
= m_PENT4
| m_NOCONA
| m_PPRO
;
565 /* Set for machines where the type and dependencies are resolved on SSE register
566 parts instead of whole registers, so we may maintain just lower part of
567 scalar values in proper format leaving the upper part undefined. */
568 const int x86_sse_partial_regs
= m_ATHLON_K8
;
569 /* Athlon optimizes partial-register FPS special case, thus avoiding the
570 need for extra instructions beforehand */
571 const int x86_sse_partial_regs_for_cvtsd2ss
= 0;
572 const int x86_sse_typeless_stores
= m_ATHLON_K8
;
573 const int x86_sse_load0_by_pxor
= m_PPRO
| m_PENT4
| m_NOCONA
;
574 const int x86_use_ffreep
= m_ATHLON_K8
;
575 const int x86_rep_movl_optimal
= m_386
| m_PENT
| m_PPRO
| m_K6
;
576 const int x86_inter_unit_moves
= ~(m_ATHLON_K8
);
577 const int x86_ext_80387_constants
= m_K6
| m_ATHLON
| m_PENT4
| m_NOCONA
| m_PPRO
;
578 /* Some CPU cores are not able to predict more than 4 branch instructions in
579 the 16 byte window. */
580 const int x86_four_jump_limit
= m_PPRO
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
581 const int x86_schedule
= m_PPRO
| m_ATHLON_K8
| m_K6
| m_PENT
;
583 /* In case the average insn count for single function invocation is
584 lower than this constant, emit fast (but longer) prologue and
586 #define FAST_PROLOGUE_INSN_COUNT 20
588 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
589 static const char *const qi_reg_name
[] = QI_REGISTER_NAMES
;
590 static const char *const qi_high_reg_name
[] = QI_HIGH_REGISTER_NAMES
;
591 static const char *const hi_reg_name
[] = HI_REGISTER_NAMES
;
593 /* Array of the smallest class containing reg number REGNO, indexed by
594 REGNO. Used by REGNO_REG_CLASS in i386.h. */
596 enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
] =
599 AREG
, DREG
, CREG
, BREG
,
601 SIREG
, DIREG
, NON_Q_REGS
, NON_Q_REGS
,
603 FP_TOP_REG
, FP_SECOND_REG
, FLOAT_REGS
, FLOAT_REGS
,
604 FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
,
607 /* flags, fpsr, dirflag, frame */
608 NO_REGS
, NO_REGS
, NO_REGS
, NON_Q_REGS
,
609 SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
,
611 MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
,
613 NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
,
614 NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
,
615 SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
,
619 /* The "default" register map used in 32bit mode. */
621 int const dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
623 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
624 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
625 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
626 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
627 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
628 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
629 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
632 static int const x86_64_int_parameter_registers
[6] =
634 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
635 FIRST_REX_INT_REG
/*R8 */, FIRST_REX_INT_REG
+ 1 /*R9 */
638 static int const x86_64_int_return_registers
[4] =
640 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
643 /* The "default" register map used in 64bit mode. */
644 int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
] =
646 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
647 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
648 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
649 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
650 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
651 8,9,10,11,12,13,14,15, /* extended integer registers */
652 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
655 /* Define the register numbers to be used in Dwarf debugging information.
656 The SVR4 reference port C compiler uses the following register numbers
657 in its Dwarf output code:
658 0 for %eax (gcc regno = 0)
659 1 for %ecx (gcc regno = 2)
660 2 for %edx (gcc regno = 1)
661 3 for %ebx (gcc regno = 3)
662 4 for %esp (gcc regno = 7)
663 5 for %ebp (gcc regno = 6)
664 6 for %esi (gcc regno = 4)
665 7 for %edi (gcc regno = 5)
666 The following three DWARF register numbers are never generated by
667 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
668 believes these numbers have these meanings.
669 8 for %eip (no gcc equivalent)
670 9 for %eflags (gcc regno = 17)
671 10 for %trapno (no gcc equivalent)
672 It is not at all clear how we should number the FP stack registers
673 for the x86 architecture. If the version of SDB on x86/svr4 were
674 a bit less brain dead with respect to floating-point then we would
675 have a precedent to follow with respect to DWARF register numbers
676 for x86 FP registers, but the SDB on x86/svr4 is so completely
677 broken with respect to FP registers that it is hardly worth thinking
678 of it as something to strive for compatibility with.
679 The version of x86/svr4 SDB I have at the moment does (partially)
680 seem to believe that DWARF register number 11 is associated with
681 the x86 register %st(0), but that's about all. Higher DWARF
682 register numbers don't seem to be associated with anything in
683 particular, and even for DWARF regno 11, SDB only seems to under-
684 stand that it should say that a variable lives in %st(0) (when
685 asked via an `=' command) if we said it was in DWARF regno 11,
686 but SDB still prints garbage when asked for the value of the
687 variable in question (via a `/' command).
688 (Also note that the labels SDB prints for various FP stack regs
689 when doing an `x' command are all wrong.)
690 Note that these problems generally don't affect the native SVR4
691 C compiler because it doesn't allow the use of -O with -g and
692 because when it is *not* optimizing, it allocates a memory
693 location for each floating-point variable, and the memory
694 location is what gets described in the DWARF AT_location
695 attribute for the variable in question.
696 Regardless of the severe mental illness of the x86/svr4 SDB, we
697 do something sensible here and we use the following DWARF
698 register numbers. Note that these are all stack-top-relative
700 11 for %st(0) (gcc regno = 8)
701 12 for %st(1) (gcc regno = 9)
702 13 for %st(2) (gcc regno = 10)
703 14 for %st(3) (gcc regno = 11)
704 15 for %st(4) (gcc regno = 12)
705 16 for %st(5) (gcc regno = 13)
706 17 for %st(6) (gcc regno = 14)
707 18 for %st(7) (gcc regno = 15)
709 int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
711 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
712 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
713 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
714 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
715 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
716 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
717 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
720 /* Test and compare insns in i386.md store the information needed to
721 generate branch and scc insns here. */
723 rtx ix86_compare_op0
= NULL_RTX
;
724 rtx ix86_compare_op1
= NULL_RTX
;
726 #define MAX_386_STACK_LOCALS 3
727 /* Size of the register save area. */
728 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
730 /* Define the structure for the machine field in struct function. */
732 struct stack_local_entry
GTY(())
737 struct stack_local_entry
*next
;
740 /* Structure describing stack frame layout.
741 Stack grows downward:
747 saved frame pointer if frame_pointer_needed
748 <- HARD_FRAME_POINTER
754 > to_allocate <- FRAME_POINTER
766 int outgoing_arguments_size
;
769 HOST_WIDE_INT to_allocate
;
770 /* The offsets relative to ARG_POINTER. */
771 HOST_WIDE_INT frame_pointer_offset
;
772 HOST_WIDE_INT hard_frame_pointer_offset
;
773 HOST_WIDE_INT stack_pointer_offset
;
775 /* When save_regs_using_mov is set, emit prologue using
776 move instead of push instructions. */
777 bool save_regs_using_mov
;
780 /* Used to enable/disable debugging features. */
781 const char *ix86_debug_arg_string
, *ix86_debug_addr_string
;
782 /* Code model option as passed by user. */
783 const char *ix86_cmodel_string
;
785 enum cmodel ix86_cmodel
;
787 const char *ix86_asm_string
;
788 enum asm_dialect ix86_asm_dialect
= ASM_ATT
;
790 const char *ix86_tls_dialect_string
;
791 enum tls_dialect ix86_tls_dialect
= TLS_DIALECT_GNU
;
793 /* Which unit we are generating floating point math for. */
794 enum fpmath_unit ix86_fpmath
;
796 /* Which cpu are we scheduling for. */
797 enum processor_type ix86_tune
;
798 /* Which instruction set architecture to use. */
799 enum processor_type ix86_arch
;
801 /* Strings to hold which cpu and instruction set architecture to use. */
802 const char *ix86_tune_string
; /* for -mtune=<xxx> */
803 const char *ix86_arch_string
; /* for -march=<xxx> */
804 const char *ix86_fpmath_string
; /* for -mfpmath=<xxx> */
806 /* # of registers to use to pass arguments. */
807 const char *ix86_regparm_string
;
809 /* true if sse prefetch instruction is not NOOP. */
810 int x86_prefetch_sse
;
812 /* ix86_regparm_string as a number */
815 /* Alignment to use for loops and jumps: */
817 /* Power of two alignment for loops. */
818 const char *ix86_align_loops_string
;
820 /* Power of two alignment for non-loop jumps. */
821 const char *ix86_align_jumps_string
;
823 /* Power of two alignment for stack boundary in bytes. */
824 const char *ix86_preferred_stack_boundary_string
;
826 /* Preferred alignment for stack boundary in bits. */
827 unsigned int ix86_preferred_stack_boundary
;
829 /* Values 1-5: see jump.c */
830 int ix86_branch_cost
;
831 const char *ix86_branch_cost_string
;
833 /* Power of two alignment for functions. */
834 const char *ix86_align_funcs_string
;
836 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
837 char internal_label_prefix
[16];
838 int internal_label_prefix_len
;
840 static void output_pic_addr_const (FILE *, rtx
, int);
841 static void put_condition_code (enum rtx_code
, enum machine_mode
,
843 static const char *get_some_local_dynamic_name (void);
844 static int get_some_local_dynamic_name_1 (rtx
*, void *);
845 static rtx
ix86_expand_int_compare (enum rtx_code
, rtx
, rtx
);
846 static enum rtx_code
ix86_prepare_fp_compare_args (enum rtx_code
, rtx
*,
848 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
849 static enum machine_mode
ix86_cc_modes_compatible (enum machine_mode
,
851 static rtx
get_thread_pointer (int);
852 static rtx
legitimize_tls_address (rtx
, enum tls_model
, int);
853 static void get_pc_thunk_name (char [32], unsigned int);
854 static rtx
gen_push (rtx
);
855 static int ix86_flags_dependant (rtx
, rtx
, enum attr_type
);
856 static int ix86_agi_dependant (rtx
, rtx
, enum attr_type
);
857 static struct machine_function
* ix86_init_machine_status (void);
858 static int ix86_split_to_parts (rtx
, rtx
*, enum machine_mode
);
859 static int ix86_nsaved_regs (void);
860 static void ix86_emit_save_regs (void);
861 static void ix86_emit_save_regs_using_mov (rtx
, HOST_WIDE_INT
);
862 static void ix86_emit_restore_regs_using_mov (rtx
, HOST_WIDE_INT
, int);
863 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT
);
864 static HOST_WIDE_INT
ix86_GOT_alias_set (void);
865 static void ix86_adjust_counter (rtx
, HOST_WIDE_INT
);
866 static rtx
ix86_expand_aligntest (rtx
, int);
867 static void ix86_expand_strlensi_unroll_1 (rtx
, rtx
, rtx
);
868 static int ix86_issue_rate (void);
869 static int ix86_adjust_cost (rtx
, rtx
, rtx
, int);
870 static int ia32_multipass_dfa_lookahead (void);
871 static bool ix86_misaligned_mem_ok (enum machine_mode
);
872 static void ix86_init_mmx_sse_builtins (void);
873 static rtx
x86_this_parameter (tree
);
874 static void x86_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
875 HOST_WIDE_INT
, tree
);
876 static bool x86_can_output_mi_thunk (tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
877 static void x86_file_start (void);
878 static void ix86_reorg (void);
879 static bool ix86_expand_carry_flag_compare (enum rtx_code
, rtx
, rtx
, rtx
*);
880 static tree
ix86_build_builtin_va_list (void);
881 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
883 static tree
ix86_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
884 static bool ix86_vector_mode_supported_p (enum machine_mode
);
886 static int ix86_address_cost (rtx
);
887 static bool ix86_cannot_force_const_mem (rtx
);
888 static rtx
ix86_delegitimize_address (rtx
);
890 struct builtin_description
;
891 static rtx
ix86_expand_sse_comi (const struct builtin_description
*,
893 static rtx
ix86_expand_sse_compare (const struct builtin_description
*,
895 static rtx
ix86_expand_unop1_builtin (enum insn_code
, tree
, rtx
);
896 static rtx
ix86_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
897 static rtx
ix86_expand_binop_builtin (enum insn_code
, tree
, rtx
);
898 static rtx
ix86_expand_store_builtin (enum insn_code
, tree
);
899 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
900 static rtx
ix86_expand_fp_compare (enum rtx_code
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
901 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code
);
902 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code
);
903 static int ix86_fp_comparison_sahf_cost (enum rtx_code code
);
904 static int ix86_fp_comparison_cost (enum rtx_code code
);
905 static unsigned int ix86_select_alt_pic_regnum (void);
906 static int ix86_save_reg (unsigned int, int);
907 static void ix86_compute_frame_layout (struct ix86_frame
*);
908 static int ix86_comp_type_attributes (tree
, tree
);
909 static int ix86_function_regparm (tree
, tree
);
910 const struct attribute_spec ix86_attribute_table
[];
911 static bool ix86_function_ok_for_sibcall (tree
, tree
);
912 static tree
ix86_handle_cdecl_attribute (tree
*, tree
, tree
, int, bool *);
913 static tree
ix86_handle_regparm_attribute (tree
*, tree
, tree
, int, bool *);
914 static int ix86_value_regno (enum machine_mode
);
915 static bool contains_128bit_aligned_vector_p (tree
);
916 static rtx
ix86_struct_value_rtx (tree
, int);
917 static bool ix86_ms_bitfield_layout_p (tree
);
918 static tree
ix86_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
919 static int extended_reg_mentioned_1 (rtx
*, void *);
920 static bool ix86_rtx_costs (rtx
, int, int, int *);
921 static int min_insn_size (rtx
);
922 static tree
ix86_md_asm_clobbers (tree clobbers
);
923 static bool ix86_must_pass_in_stack (enum machine_mode mode
, tree type
);
924 static bool ix86_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
927 #if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION)
928 static void ix86_svr3_asm_out_constructor (rtx
, int);
930 static void i386_solaris_elf_named_section (const char *, unsigned int, tree
);
932 /* Register class used for passing given 64bit part of the argument.
933 These represent classes as documented by the PS ABI, with the exception
934 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
935 use SF or DFmode move instead of DImode to avoid reformatting penalties.
937 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
938 whenever possible (upper half does contain padding).
940 enum x86_64_reg_class
943 X86_64_INTEGER_CLASS
,
944 X86_64_INTEGERSI_CLASS
,
953 static const char * const x86_64_reg_class_name
[] =
954 {"no", "integer", "integerSI", "sse", "sseSF", "sseDF", "sseup", "x87", "x87up", "no"};
956 #define MAX_CLASSES 4
957 static int classify_argument (enum machine_mode
, tree
,
958 enum x86_64_reg_class
[MAX_CLASSES
], int);
959 static int examine_argument (enum machine_mode
, tree
, int, int *, int *);
960 static rtx
construct_container (enum machine_mode
, tree
, int, int, int,
962 static enum x86_64_reg_class
merge_classes (enum x86_64_reg_class
,
963 enum x86_64_reg_class
);
965 /* Table of constants used by fldpi, fldln2, etc.... */
966 static REAL_VALUE_TYPE ext_80387_constants_table
[5];
967 static bool ext_80387_constants_init
= 0;
968 static void init_ext_80387_constants (void);
970 /* Initialize the GCC target structure. */
971 #undef TARGET_ATTRIBUTE_TABLE
972 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
973 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
974 # undef TARGET_MERGE_DECL_ATTRIBUTES
975 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
978 #undef TARGET_COMP_TYPE_ATTRIBUTES
979 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
981 #undef TARGET_INIT_BUILTINS
982 #define TARGET_INIT_BUILTINS ix86_init_builtins
984 #undef TARGET_EXPAND_BUILTIN
985 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
987 #undef TARGET_ASM_FUNCTION_EPILOGUE
988 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
990 #undef TARGET_ASM_OPEN_PAREN
991 #define TARGET_ASM_OPEN_PAREN ""
992 #undef TARGET_ASM_CLOSE_PAREN
993 #define TARGET_ASM_CLOSE_PAREN ""
995 #undef TARGET_ASM_ALIGNED_HI_OP
996 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
997 #undef TARGET_ASM_ALIGNED_SI_OP
998 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
1000 #undef TARGET_ASM_ALIGNED_DI_OP
1001 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1004 #undef TARGET_ASM_UNALIGNED_HI_OP
1005 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1006 #undef TARGET_ASM_UNALIGNED_SI_OP
1007 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1008 #undef TARGET_ASM_UNALIGNED_DI_OP
1009 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1011 #undef TARGET_SCHED_ADJUST_COST
1012 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1013 #undef TARGET_SCHED_ISSUE_RATE
1014 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1015 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1016 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1017 ia32_multipass_dfa_lookahead
1019 #undef TARGET_VECTORIZE_MISALIGNED_MEM_OK
1020 #define TARGET_VECTORIZE_MISALIGNED_MEM_OK ix86_misaligned_mem_ok
1022 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1023 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1026 #undef TARGET_HAVE_TLS
1027 #define TARGET_HAVE_TLS true
1029 #undef TARGET_CANNOT_FORCE_CONST_MEM
1030 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1032 #undef TARGET_DELEGITIMIZE_ADDRESS
1033 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1035 #undef TARGET_MS_BITFIELD_LAYOUT_P
1036 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1038 #undef TARGET_ASM_OUTPUT_MI_THUNK
1039 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1040 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1041 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1043 #undef TARGET_ASM_FILE_START
1044 #define TARGET_ASM_FILE_START x86_file_start
1046 #undef TARGET_RTX_COSTS
1047 #define TARGET_RTX_COSTS ix86_rtx_costs
1048 #undef TARGET_ADDRESS_COST
1049 #define TARGET_ADDRESS_COST ix86_address_cost
1051 #undef TARGET_FIXED_CONDITION_CODE_REGS
1052 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1053 #undef TARGET_CC_MODES_COMPATIBLE
1054 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1056 #undef TARGET_MACHINE_DEPENDENT_REORG
1057 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1059 #undef TARGET_BUILD_BUILTIN_VA_LIST
1060 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1062 #undef TARGET_MD_ASM_CLOBBERS
1063 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1065 #undef TARGET_PROMOTE_PROTOTYPES
1066 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1067 #undef TARGET_STRUCT_VALUE_RTX
1068 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1069 #undef TARGET_SETUP_INCOMING_VARARGS
1070 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1071 #undef TARGET_MUST_PASS_IN_STACK
1072 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1073 #undef TARGET_PASS_BY_REFERENCE
1074 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1076 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1077 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1079 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1080 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1082 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1083 #undef TARGET_INSERT_ATTRIBUTES
1084 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1087 struct gcc_target targetm
= TARGET_INITIALIZER
;
1090 /* The svr4 ABI for the i386 says that records and unions are returned
1092 #ifndef DEFAULT_PCC_STRUCT_RETURN
1093 #define DEFAULT_PCC_STRUCT_RETURN 1
1096 /* Sometimes certain combinations of command options do not make
1097 sense on a particular target machine. You can define a macro
1098 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1099 defined, is executed once just after all the command options have
1102 Don't use this macro to turn on various extra optimizations for
1103 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1106 override_options (void)
1109 int ix86_tune_defaulted
= 0;
1111 /* Comes from final.c -- no real reason to change it. */
1112 #define MAX_CODE_ALIGN 16
1116 const struct processor_costs
*cost
; /* Processor costs */
1117 const int target_enable
; /* Target flags to enable. */
1118 const int target_disable
; /* Target flags to disable. */
1119 const int align_loop
; /* Default alignments. */
1120 const int align_loop_max_skip
;
1121 const int align_jump
;
1122 const int align_jump_max_skip
;
1123 const int align_func
;
1125 const processor_target_table
[PROCESSOR_max
] =
1127 {&i386_cost
, 0, 0, 4, 3, 4, 3, 4},
1128 {&i486_cost
, 0, 0, 16, 15, 16, 15, 16},
1129 {&pentium_cost
, 0, 0, 16, 7, 16, 7, 16},
1130 {&pentiumpro_cost
, 0, 0, 16, 15, 16, 7, 16},
1131 {&k6_cost
, 0, 0, 32, 7, 32, 7, 32},
1132 {&athlon_cost
, 0, 0, 16, 7, 16, 7, 16},
1133 {&pentium4_cost
, 0, 0, 0, 0, 0, 0, 0},
1134 {&k8_cost
, 0, 0, 16, 7, 16, 7, 16},
1135 {&nocona_cost
, 0, 0, 0, 0, 0, 0, 0}
1138 static const char * const cpu_names
[] = TARGET_CPU_DEFAULT_NAMES
;
1141 const char *const name
; /* processor name or nickname. */
1142 const enum processor_type processor
;
1143 const enum pta_flags
1149 PTA_PREFETCH_SSE
= 16,
1155 const processor_alias_table
[] =
1157 {"i386", PROCESSOR_I386
, 0},
1158 {"i486", PROCESSOR_I486
, 0},
1159 {"i586", PROCESSOR_PENTIUM
, 0},
1160 {"pentium", PROCESSOR_PENTIUM
, 0},
1161 {"pentium-mmx", PROCESSOR_PENTIUM
, PTA_MMX
},
1162 {"winchip-c6", PROCESSOR_I486
, PTA_MMX
},
1163 {"winchip2", PROCESSOR_I486
, PTA_MMX
| PTA_3DNOW
},
1164 {"c3", PROCESSOR_I486
, PTA_MMX
| PTA_3DNOW
},
1165 {"c3-2", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_SSE
},
1166 {"i686", PROCESSOR_PENTIUMPRO
, 0},
1167 {"pentiumpro", PROCESSOR_PENTIUMPRO
, 0},
1168 {"pentium2", PROCESSOR_PENTIUMPRO
, PTA_MMX
},
1169 {"pentium3", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_SSE
| PTA_PREFETCH_SSE
},
1170 {"pentium3m", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_SSE
| PTA_PREFETCH_SSE
},
1171 {"pentium-m", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_SSE
| PTA_PREFETCH_SSE
| PTA_SSE2
},
1172 {"pentium4", PROCESSOR_PENTIUM4
, PTA_SSE
| PTA_SSE2
1173 | PTA_MMX
| PTA_PREFETCH_SSE
},
1174 {"pentium4m", PROCESSOR_PENTIUM4
, PTA_SSE
| PTA_SSE2
1175 | PTA_MMX
| PTA_PREFETCH_SSE
},
1176 {"prescott", PROCESSOR_NOCONA
, PTA_SSE
| PTA_SSE2
| PTA_SSE3
1177 | PTA_MMX
| PTA_PREFETCH_SSE
},
1178 {"nocona", PROCESSOR_NOCONA
, PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_64BIT
1179 | PTA_MMX
| PTA_PREFETCH_SSE
},
1180 {"k6", PROCESSOR_K6
, PTA_MMX
},
1181 {"k6-2", PROCESSOR_K6
, PTA_MMX
| PTA_3DNOW
},
1182 {"k6-3", PROCESSOR_K6
, PTA_MMX
| PTA_3DNOW
},
1183 {"athlon", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1185 {"athlon-tbird", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
1186 | PTA_3DNOW
| PTA_3DNOW_A
},
1187 {"athlon-4", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1188 | PTA_3DNOW_A
| PTA_SSE
},
1189 {"athlon-xp", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1190 | PTA_3DNOW_A
| PTA_SSE
},
1191 {"athlon-mp", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1192 | PTA_3DNOW_A
| PTA_SSE
},
1193 {"x86-64", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_64BIT
1194 | PTA_SSE
| PTA_SSE2
},
1195 {"k8", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1196 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1197 {"opteron", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1198 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1199 {"athlon64", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1200 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1201 {"athlon-fx", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1202 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1205 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
1207 /* Set the default values for switches whose default depends on TARGET_64BIT
1208 in case they weren't overwritten by command line options. */
1211 if (flag_omit_frame_pointer
== 2)
1212 flag_omit_frame_pointer
= 1;
1213 if (flag_asynchronous_unwind_tables
== 2)
1214 flag_asynchronous_unwind_tables
= 1;
1215 if (flag_pcc_struct_return
== 2)
1216 flag_pcc_struct_return
= 0;
1220 if (flag_omit_frame_pointer
== 2)
1221 flag_omit_frame_pointer
= 0;
1222 if (flag_asynchronous_unwind_tables
== 2)
1223 flag_asynchronous_unwind_tables
= 0;
1224 if (flag_pcc_struct_return
== 2)
1225 flag_pcc_struct_return
= DEFAULT_PCC_STRUCT_RETURN
;
1228 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1229 SUBTARGET_OVERRIDE_OPTIONS
;
1232 if (!ix86_tune_string
&& ix86_arch_string
)
1233 ix86_tune_string
= ix86_arch_string
;
1234 if (!ix86_tune_string
)
1236 ix86_tune_string
= cpu_names
[TARGET_CPU_DEFAULT
];
1237 ix86_tune_defaulted
= 1;
1239 if (!ix86_arch_string
)
1240 ix86_arch_string
= TARGET_64BIT
? "x86-64" : "i386";
1242 if (ix86_cmodel_string
!= 0)
1244 if (!strcmp (ix86_cmodel_string
, "small"))
1245 ix86_cmodel
= flag_pic
? CM_SMALL_PIC
: CM_SMALL
;
1247 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string
);
1248 else if (!strcmp (ix86_cmodel_string
, "32"))
1249 ix86_cmodel
= CM_32
;
1250 else if (!strcmp (ix86_cmodel_string
, "kernel") && !flag_pic
)
1251 ix86_cmodel
= CM_KERNEL
;
1252 else if (!strcmp (ix86_cmodel_string
, "medium") && !flag_pic
)
1253 ix86_cmodel
= CM_MEDIUM
;
1254 else if (!strcmp (ix86_cmodel_string
, "large") && !flag_pic
)
1255 ix86_cmodel
= CM_LARGE
;
1257 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string
);
1261 ix86_cmodel
= CM_32
;
1263 ix86_cmodel
= flag_pic
? CM_SMALL_PIC
: CM_SMALL
;
1265 if (ix86_asm_string
!= 0)
1267 if (!strcmp (ix86_asm_string
, "intel"))
1268 ix86_asm_dialect
= ASM_INTEL
;
1269 else if (!strcmp (ix86_asm_string
, "att"))
1270 ix86_asm_dialect
= ASM_ATT
;
1272 error ("bad value (%s) for -masm= switch", ix86_asm_string
);
1274 if ((TARGET_64BIT
== 0) != (ix86_cmodel
== CM_32
))
1275 error ("code model %qs not supported in the %s bit mode",
1276 ix86_cmodel_string
, TARGET_64BIT
? "64" : "32");
1277 if (ix86_cmodel
== CM_LARGE
)
1278 sorry ("code model %<large%> not supported yet");
1279 if ((TARGET_64BIT
!= 0) != ((target_flags
& MASK_64BIT
) != 0))
1280 sorry ("%i-bit mode not compiled in",
1281 (target_flags
& MASK_64BIT
) ? 64 : 32);
1283 for (i
= 0; i
< pta_size
; i
++)
1284 if (! strcmp (ix86_arch_string
, processor_alias_table
[i
].name
))
1286 ix86_arch
= processor_alias_table
[i
].processor
;
1287 /* Default cpu tuning to the architecture. */
1288 ix86_tune
= ix86_arch
;
1289 if (processor_alias_table
[i
].flags
& PTA_MMX
1290 && !(target_flags_explicit
& MASK_MMX
))
1291 target_flags
|= MASK_MMX
;
1292 if (processor_alias_table
[i
].flags
& PTA_3DNOW
1293 && !(target_flags_explicit
& MASK_3DNOW
))
1294 target_flags
|= MASK_3DNOW
;
1295 if (processor_alias_table
[i
].flags
& PTA_3DNOW_A
1296 && !(target_flags_explicit
& MASK_3DNOW_A
))
1297 target_flags
|= MASK_3DNOW_A
;
1298 if (processor_alias_table
[i
].flags
& PTA_SSE
1299 && !(target_flags_explicit
& MASK_SSE
))
1300 target_flags
|= MASK_SSE
;
1301 if (processor_alias_table
[i
].flags
& PTA_SSE2
1302 && !(target_flags_explicit
& MASK_SSE2
))
1303 target_flags
|= MASK_SSE2
;
1304 if (processor_alias_table
[i
].flags
& PTA_SSE3
1305 && !(target_flags_explicit
& MASK_SSE3
))
1306 target_flags
|= MASK_SSE3
;
1307 if (processor_alias_table
[i
].flags
& PTA_PREFETCH_SSE
)
1308 x86_prefetch_sse
= true;
1309 if (TARGET_64BIT
&& !(processor_alias_table
[i
].flags
& PTA_64BIT
))
1310 error ("CPU you selected does not support x86-64 "
1316 error ("bad value (%s) for -march= switch", ix86_arch_string
);
1318 for (i
= 0; i
< pta_size
; i
++)
1319 if (! strcmp (ix86_tune_string
, processor_alias_table
[i
].name
))
1321 ix86_tune
= processor_alias_table
[i
].processor
;
1322 if (TARGET_64BIT
&& !(processor_alias_table
[i
].flags
& PTA_64BIT
))
1324 if (ix86_tune_defaulted
)
1326 ix86_tune_string
= "x86-64";
1327 for (i
= 0; i
< pta_size
; i
++)
1328 if (! strcmp (ix86_tune_string
,
1329 processor_alias_table
[i
].name
))
1331 ix86_tune
= processor_alias_table
[i
].processor
;
1334 error ("CPU you selected does not support x86-64 "
1337 /* Intel CPUs have always interpreted SSE prefetch instructions as
1338 NOPs; so, we can enable SSE prefetch instructions even when
1339 -mtune (rather than -march) points us to a processor that has them.
1340 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1341 higher processors. */
1342 if (TARGET_CMOVE
&& (processor_alias_table
[i
].flags
& PTA_PREFETCH_SSE
))
1343 x86_prefetch_sse
= true;
1347 error ("bad value (%s) for -mtune= switch", ix86_tune_string
);
1350 ix86_cost
= &size_cost
;
1352 ix86_cost
= processor_target_table
[ix86_tune
].cost
;
1353 target_flags
|= processor_target_table
[ix86_tune
].target_enable
;
1354 target_flags
&= ~processor_target_table
[ix86_tune
].target_disable
;
1356 /* Arrange to set up i386_stack_locals for all functions. */
1357 init_machine_status
= ix86_init_machine_status
;
1359 /* Validate -mregparm= value. */
1360 if (ix86_regparm_string
)
1362 i
= atoi (ix86_regparm_string
);
1363 if (i
< 0 || i
> REGPARM_MAX
)
1364 error ("-mregparm=%d is not between 0 and %d", i
, REGPARM_MAX
);
1370 ix86_regparm
= REGPARM_MAX
;
1372 /* If the user has provided any of the -malign-* options,
1373 warn and use that value only if -falign-* is not set.
1374 Remove this code in GCC 3.2 or later. */
1375 if (ix86_align_loops_string
)
1377 warning ("-malign-loops is obsolete, use -falign-loops");
1378 if (align_loops
== 0)
1380 i
= atoi (ix86_align_loops_string
);
1381 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1382 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1384 align_loops
= 1 << i
;
1388 if (ix86_align_jumps_string
)
1390 warning ("-malign-jumps is obsolete, use -falign-jumps");
1391 if (align_jumps
== 0)
1393 i
= atoi (ix86_align_jumps_string
);
1394 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1395 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1397 align_jumps
= 1 << i
;
1401 if (ix86_align_funcs_string
)
1403 warning ("-malign-functions is obsolete, use -falign-functions");
1404 if (align_functions
== 0)
1406 i
= atoi (ix86_align_funcs_string
);
1407 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1408 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1410 align_functions
= 1 << i
;
1414 /* Default align_* from the processor table. */
1415 if (align_loops
== 0)
1417 align_loops
= processor_target_table
[ix86_tune
].align_loop
;
1418 align_loops_max_skip
= processor_target_table
[ix86_tune
].align_loop_max_skip
;
1420 if (align_jumps
== 0)
1422 align_jumps
= processor_target_table
[ix86_tune
].align_jump
;
1423 align_jumps_max_skip
= processor_target_table
[ix86_tune
].align_jump_max_skip
;
1425 if (align_functions
== 0)
1427 align_functions
= processor_target_table
[ix86_tune
].align_func
;
1430 /* Validate -mpreferred-stack-boundary= value, or provide default.
1431 The default of 128 bits is for Pentium III's SSE __m128, but we
1432 don't want additional code to keep the stack aligned when
1433 optimizing for code size. */
1434 ix86_preferred_stack_boundary
= (optimize_size
1435 ? TARGET_64BIT
? 128 : 32
1437 if (ix86_preferred_stack_boundary_string
)
1439 i
= atoi (ix86_preferred_stack_boundary_string
);
1440 if (i
< (TARGET_64BIT
? 4 : 2) || i
> 12)
1441 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i
,
1442 TARGET_64BIT
? 4 : 2);
1444 ix86_preferred_stack_boundary
= (1 << i
) * BITS_PER_UNIT
;
1447 /* Validate -mbranch-cost= value, or provide default. */
1448 ix86_branch_cost
= processor_target_table
[ix86_tune
].cost
->branch_cost
;
1449 if (ix86_branch_cost_string
)
1451 i
= atoi (ix86_branch_cost_string
);
1453 error ("-mbranch-cost=%d is not between 0 and 5", i
);
1455 ix86_branch_cost
= i
;
1458 if (ix86_tls_dialect_string
)
1460 if (strcmp (ix86_tls_dialect_string
, "gnu") == 0)
1461 ix86_tls_dialect
= TLS_DIALECT_GNU
;
1462 else if (strcmp (ix86_tls_dialect_string
, "sun") == 0)
1463 ix86_tls_dialect
= TLS_DIALECT_SUN
;
1465 error ("bad value (%s) for -mtls-dialect= switch",
1466 ix86_tls_dialect_string
);
1469 /* Keep nonleaf frame pointers. */
1470 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
1471 flag_omit_frame_pointer
= 1;
1473 /* If we're doing fast math, we don't care about comparison order
1474 wrt NaNs. This lets us use a shorter comparison sequence. */
1475 if (flag_unsafe_math_optimizations
)
1476 target_flags
&= ~MASK_IEEE_FP
;
1478 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1479 since the insns won't need emulation. */
1480 if (x86_arch_always_fancy_math_387
& (1 << ix86_arch
))
1481 target_flags
&= ~MASK_NO_FANCY_MATH_387
;
1483 /* Turn on SSE2 builtins for -msse3. */
1485 target_flags
|= MASK_SSE2
;
1487 /* Turn on SSE builtins for -msse2. */
1489 target_flags
|= MASK_SSE
;
1493 if (TARGET_ALIGN_DOUBLE
)
1494 error ("-malign-double makes no sense in the 64bit mode");
1496 error ("-mrtd calling convention not supported in the 64bit mode");
1497 /* Enable by default the SSE and MMX builtins. */
1498 target_flags
|= (MASK_SSE2
| MASK_SSE
| MASK_MMX
| MASK_128BIT_LONG_DOUBLE
);
1499 ix86_fpmath
= FPMATH_SSE
;
1503 ix86_fpmath
= FPMATH_387
;
1504 /* i386 ABI does not specify red zone. It still makes sense to use it
1505 when programmer takes care to stack from being destroyed. */
1506 if (!(target_flags_explicit
& MASK_NO_RED_ZONE
))
1507 target_flags
|= MASK_NO_RED_ZONE
;
1510 if (ix86_fpmath_string
!= 0)
1512 if (! strcmp (ix86_fpmath_string
, "387"))
1513 ix86_fpmath
= FPMATH_387
;
1514 else if (! strcmp (ix86_fpmath_string
, "sse"))
1518 warning ("SSE instruction set disabled, using 387 arithmetics");
1519 ix86_fpmath
= FPMATH_387
;
1522 ix86_fpmath
= FPMATH_SSE
;
1524 else if (! strcmp (ix86_fpmath_string
, "387,sse")
1525 || ! strcmp (ix86_fpmath_string
, "sse,387"))
1529 warning ("SSE instruction set disabled, using 387 arithmetics");
1530 ix86_fpmath
= FPMATH_387
;
1532 else if (!TARGET_80387
)
1534 warning ("387 instruction set disabled, using SSE arithmetics");
1535 ix86_fpmath
= FPMATH_SSE
;
1538 ix86_fpmath
= FPMATH_SSE
| FPMATH_387
;
1541 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string
);
1544 /* It makes no sense to ask for just SSE builtins, so MMX is also turned
1548 target_flags
|= MASK_MMX
;
1549 x86_prefetch_sse
= true;
1552 /* If it has 3DNow! it also has MMX so MMX is also turned on by -m3dnow */
1555 target_flags
|= MASK_MMX
;
1556 /* If we are targeting the Athlon architecture, enable the 3Dnow/MMX
1557 extensions it adds. */
1558 if (x86_3dnow_a
& (1 << ix86_arch
))
1559 target_flags
|= MASK_3DNOW_A
;
1561 if ((x86_accumulate_outgoing_args
& TUNEMASK
)
1562 && !(target_flags_explicit
& MASK_ACCUMULATE_OUTGOING_ARGS
)
1564 target_flags
|= MASK_ACCUMULATE_OUTGOING_ARGS
;
1566 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1569 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix
, "LX", 0);
1570 p
= strchr (internal_label_prefix
, 'X');
1571 internal_label_prefix_len
= p
- internal_label_prefix
;
1574 /* When scheduling description is not available, disable scheduler pass so it
1575 won't slow down the compilation and make x87 code slower. */
1576 if (!TARGET_SCHEDULE
)
1577 flag_schedule_insns_after_reload
= flag_schedule_insns
= 0;
1581 optimization_options (int level
, int size ATTRIBUTE_UNUSED
)
1583 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
1584 make the problem with not enough registers even worse. */
1585 #ifdef INSN_SCHEDULING
1587 flag_schedule_insns
= 0;
1590 /* The default values of these switches depend on the TARGET_64BIT
1591 that is not known at this moment. Mark these values with 2 and
1592 let user the to override these. In case there is no command line option
1593 specifying them, we will set the defaults in override_options. */
1595 flag_omit_frame_pointer
= 2;
1596 flag_pcc_struct_return
= 2;
1597 flag_asynchronous_unwind_tables
= 2;
1600 /* Table of valid machine attributes. */
1601 const struct attribute_spec ix86_attribute_table
[] =
1603 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1604 /* Stdcall attribute says callee is responsible for popping arguments
1605 if they are not variable. */
1606 { "stdcall", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1607 /* Fastcall attribute says callee is responsible for popping arguments
1608 if they are not variable. */
1609 { "fastcall", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1610 /* Cdecl attribute says the callee is a normal C declaration */
1611 { "cdecl", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1612 /* Regparm attribute specifies how many integer arguments are to be
1613 passed in registers. */
1614 { "regparm", 1, 1, false, true, true, ix86_handle_regparm_attribute
},
1615 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1616 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
1617 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
1618 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute
},
1620 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute
},
1621 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute
},
1622 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1623 SUBTARGET_ATTRIBUTE_TABLE
,
1625 { NULL
, 0, 0, false, false, false, NULL
}
1628 /* Decide whether we can make a sibling call to a function. DECL is the
1629 declaration of the function being targeted by the call and EXP is the
1630 CALL_EXPR representing the call. */
1633 ix86_function_ok_for_sibcall (tree decl
, tree exp
)
1635 /* If we are generating position-independent code, we cannot sibcall
1636 optimize any indirect call, or a direct call to a global function,
1637 as the PLT requires %ebx be live. */
1638 if (!TARGET_64BIT
&& flag_pic
&& (!decl
|| TREE_PUBLIC (decl
)))
1641 /* If we are returning floats on the 80387 register stack, we cannot
1642 make a sibcall from a function that doesn't return a float to a
1643 function that does or, conversely, from a function that does return
1644 a float to a function that doesn't; the necessary stack adjustment
1645 would not be executed. */
1646 if (STACK_REG_P (ix86_function_value (TREE_TYPE (exp
)))
1647 != STACK_REG_P (ix86_function_value (TREE_TYPE (DECL_RESULT (cfun
->decl
)))))
1650 /* If this call is indirect, we'll need to be able to use a call-clobbered
1651 register for the address of the target function. Make sure that all
1652 such registers are not used for passing parameters. */
1653 if (!decl
&& !TARGET_64BIT
)
1657 /* We're looking at the CALL_EXPR, we need the type of the function. */
1658 type
= TREE_OPERAND (exp
, 0); /* pointer expression */
1659 type
= TREE_TYPE (type
); /* pointer type */
1660 type
= TREE_TYPE (type
); /* function type */
1662 if (ix86_function_regparm (type
, NULL
) >= 3)
1664 /* ??? Need to count the actual number of registers to be used,
1665 not the possible number of registers. Fix later. */
1670 /* Otherwise okay. That also includes certain types of indirect calls. */
1674 /* Handle a "cdecl", "stdcall", or "fastcall" attribute;
1675 arguments as in struct attribute_spec.handler. */
1677 ix86_handle_cdecl_attribute (tree
*node
, tree name
,
1678 tree args ATTRIBUTE_UNUSED
,
1679 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1681 if (TREE_CODE (*node
) != FUNCTION_TYPE
1682 && TREE_CODE (*node
) != METHOD_TYPE
1683 && TREE_CODE (*node
) != FIELD_DECL
1684 && TREE_CODE (*node
) != TYPE_DECL
)
1686 warning ("%qs attribute only applies to functions",
1687 IDENTIFIER_POINTER (name
));
1688 *no_add_attrs
= true;
1692 if (is_attribute_p ("fastcall", name
))
1694 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node
)))
1696 error ("fastcall and stdcall attributes are not compatible");
1698 else if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node
)))
1700 error ("fastcall and regparm attributes are not compatible");
1703 else if (is_attribute_p ("stdcall", name
))
1705 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node
)))
1707 error ("fastcall and stdcall attributes are not compatible");
1714 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
1715 *no_add_attrs
= true;
1721 /* Handle a "regparm" attribute;
1722 arguments as in struct attribute_spec.handler. */
1724 ix86_handle_regparm_attribute (tree
*node
, tree name
, tree args
,
1725 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1727 if (TREE_CODE (*node
) != FUNCTION_TYPE
1728 && TREE_CODE (*node
) != METHOD_TYPE
1729 && TREE_CODE (*node
) != FIELD_DECL
1730 && TREE_CODE (*node
) != TYPE_DECL
)
1732 warning ("%qs attribute only applies to functions",
1733 IDENTIFIER_POINTER (name
));
1734 *no_add_attrs
= true;
1740 cst
= TREE_VALUE (args
);
1741 if (TREE_CODE (cst
) != INTEGER_CST
)
1743 warning ("%qs attribute requires an integer constant argument",
1744 IDENTIFIER_POINTER (name
));
1745 *no_add_attrs
= true;
1747 else if (compare_tree_int (cst
, REGPARM_MAX
) > 0)
1749 warning ("argument to %qs attribute larger than %d",
1750 IDENTIFIER_POINTER (name
), REGPARM_MAX
);
1751 *no_add_attrs
= true;
1754 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node
)))
1756 error ("fastcall and regparm attributes are not compatible");
1763 /* Return 0 if the attributes for two types are incompatible, 1 if they
1764 are compatible, and 2 if they are nearly compatible (which causes a
1765 warning to be generated). */
1768 ix86_comp_type_attributes (tree type1
, tree type2
)
1770 /* Check for mismatch of non-default calling convention. */
1771 const char *const rtdstr
= TARGET_RTD
? "cdecl" : "stdcall";
1773 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
1776 /* Check for mismatched fastcall types */
1777 if (!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1
))
1778 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2
)))
1781 /* Check for mismatched return types (cdecl vs stdcall). */
1782 if (!lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type1
))
1783 != !lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type2
)))
1785 if (ix86_function_regparm (type1
, NULL
)
1786 != ix86_function_regparm (type2
, NULL
))
1791 /* Return the regparm value for a fuctio with the indicated TYPE and DECL.
1792 DECL may be NULL when calling function indirectly
1793 or considering a libcall. */
1796 ix86_function_regparm (tree type
, tree decl
)
1799 int regparm
= ix86_regparm
;
1800 bool user_convention
= false;
1804 attr
= lookup_attribute ("regparm", TYPE_ATTRIBUTES (type
));
1807 regparm
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr
)));
1808 user_convention
= true;
1811 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type
)))
1814 user_convention
= true;
1817 /* Use register calling convention for local functions when possible. */
1818 if (!TARGET_64BIT
&& !user_convention
&& decl
1819 && flag_unit_at_a_time
&& !profile_flag
)
1821 struct cgraph_local_info
*i
= cgraph_local_info (decl
);
1824 /* We can't use regparm(3) for nested functions as these use
1825 static chain pointer in third argument. */
1826 if (DECL_CONTEXT (decl
) && !DECL_NO_STATIC_CHAIN (decl
))
1836 /* Return true if EAX is live at the start of the function. Used by
1837 ix86_expand_prologue to determine if we need special help before
1838 calling allocate_stack_worker. */
1841 ix86_eax_live_at_start_p (void)
1843 /* Cheat. Don't bother working forward from ix86_function_regparm
1844 to the function type to whether an actual argument is located in
1845 eax. Instead just look at cfg info, which is still close enough
1846 to correct at this point. This gives false positives for broken
1847 functions that might use uninitialized data that happens to be
1848 allocated in eax, but who cares? */
1849 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->global_live_at_end
, 0);
1852 /* Value is the number of bytes of arguments automatically
1853 popped when returning from a subroutine call.
1854 FUNDECL is the declaration node of the function (as a tree),
1855 FUNTYPE is the data type of the function (as a tree),
1856 or for a library call it is an identifier node for the subroutine name.
1857 SIZE is the number of bytes of arguments passed on the stack.
1859 On the 80386, the RTD insn may be used to pop them if the number
1860 of args is fixed, but if the number is variable then the caller
1861 must pop them all. RTD can't be used for library calls now
1862 because the library is compiled with the Unix compiler.
1863 Use of RTD is a selectable option, since it is incompatible with
1864 standard Unix calling sequences. If the option is not selected,
1865 the caller must always pop the args.
1867 The attribute stdcall is equivalent to RTD on a per module basis. */
1870 ix86_return_pops_args (tree fundecl
, tree funtype
, int size
)
1872 int rtd
= TARGET_RTD
&& (!fundecl
|| TREE_CODE (fundecl
) != IDENTIFIER_NODE
);
1874 /* Cdecl functions override -mrtd, and never pop the stack. */
1875 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype
))) {
1877 /* Stdcall and fastcall functions will pop the stack if not
1879 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype
))
1880 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype
)))
1884 && (TYPE_ARG_TYPES (funtype
) == NULL_TREE
1885 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype
)))
1886 == void_type_node
)))
1890 /* Lose any fake structure return argument if it is passed on the stack. */
1891 if (aggregate_value_p (TREE_TYPE (funtype
), fundecl
)
1893 && !KEEP_AGGREGATE_RETURN_POINTER
)
1895 int nregs
= ix86_function_regparm (funtype
, fundecl
);
1898 return GET_MODE_SIZE (Pmode
);
1904 /* Argument support functions. */
1906 /* Return true when register may be used to pass function parameters. */
1908 ix86_function_arg_regno_p (int regno
)
1912 return (regno
< REGPARM_MAX
1913 || (TARGET_SSE
&& SSE_REGNO_P (regno
) && !fixed_regs
[regno
]));
1914 if (SSE_REGNO_P (regno
) && TARGET_SSE
)
1916 /* RAX is used as hidden argument to va_arg functions. */
1919 for (i
= 0; i
< REGPARM_MAX
; i
++)
1920 if (regno
== x86_64_int_parameter_registers
[i
])
1925 /* Return if we do not know how to pass TYPE solely in registers. */
1928 ix86_must_pass_in_stack (enum machine_mode mode
, tree type
)
1930 if (must_pass_in_stack_var_size_or_pad (mode
, type
))
1932 return (!TARGET_64BIT
&& type
&& mode
== TImode
);
1935 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1936 for a call to a function whose data type is FNTYPE.
1937 For a library call, FNTYPE is 0. */
1940 init_cumulative_args (CUMULATIVE_ARGS
*cum
, /* Argument info to initialize */
1941 tree fntype
, /* tree ptr for function decl */
1942 rtx libname
, /* SYMBOL_REF of library name or 0 */
1945 static CUMULATIVE_ARGS zero_cum
;
1946 tree param
, next_param
;
1948 if (TARGET_DEBUG_ARG
)
1950 fprintf (stderr
, "\ninit_cumulative_args (");
1952 fprintf (stderr
, "fntype code = %s, ret code = %s",
1953 tree_code_name
[(int) TREE_CODE (fntype
)],
1954 tree_code_name
[(int) TREE_CODE (TREE_TYPE (fntype
))]);
1956 fprintf (stderr
, "no fntype");
1959 fprintf (stderr
, ", libname = %s", XSTR (libname
, 0));
1964 /* Set up the number of registers to use for passing arguments. */
1966 cum
->nregs
= ix86_function_regparm (fntype
, fndecl
);
1968 cum
->nregs
= ix86_regparm
;
1970 cum
->sse_nregs
= SSE_REGPARM_MAX
;
1972 cum
->mmx_nregs
= MMX_REGPARM_MAX
;
1973 cum
->warn_sse
= true;
1974 cum
->warn_mmx
= true;
1975 cum
->maybe_vaarg
= false;
1977 /* Use ecx and edx registers if function has fastcall attribute */
1978 if (fntype
&& !TARGET_64BIT
)
1980 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype
)))
1987 /* Determine if this function has variable arguments. This is
1988 indicated by the last argument being 'void_type_mode' if there
1989 are no variable arguments. If there are variable arguments, then
1990 we won't pass anything in registers in 32-bit mode. */
1992 if (cum
->nregs
|| cum
->mmx_nregs
|| cum
->sse_nregs
)
1994 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
1995 param
!= 0; param
= next_param
)
1997 next_param
= TREE_CHAIN (param
);
1998 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
2009 cum
->maybe_vaarg
= true;
2013 if ((!fntype
&& !libname
)
2014 || (fntype
&& !TYPE_ARG_TYPES (fntype
)))
2015 cum
->maybe_vaarg
= 1;
2017 if (TARGET_DEBUG_ARG
)
2018 fprintf (stderr
, ", nregs=%d )\n", cum
->nregs
);
2023 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
2024 of this code is to classify each 8bytes of incoming argument by the register
2025 class and assign registers accordingly. */
2027 /* Return the union class of CLASS1 and CLASS2.
2028 See the x86-64 PS ABI for details. */
2030 static enum x86_64_reg_class
2031 merge_classes (enum x86_64_reg_class class1
, enum x86_64_reg_class class2
)
2033 /* Rule #1: If both classes are equal, this is the resulting class. */
2034 if (class1
== class2
)
2037 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
2039 if (class1
== X86_64_NO_CLASS
)
2041 if (class2
== X86_64_NO_CLASS
)
2044 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
2045 if (class1
== X86_64_MEMORY_CLASS
|| class2
== X86_64_MEMORY_CLASS
)
2046 return X86_64_MEMORY_CLASS
;
2048 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
2049 if ((class1
== X86_64_INTEGERSI_CLASS
&& class2
== X86_64_SSESF_CLASS
)
2050 || (class2
== X86_64_INTEGERSI_CLASS
&& class1
== X86_64_SSESF_CLASS
))
2051 return X86_64_INTEGERSI_CLASS
;
2052 if (class1
== X86_64_INTEGER_CLASS
|| class1
== X86_64_INTEGERSI_CLASS
2053 || class2
== X86_64_INTEGER_CLASS
|| class2
== X86_64_INTEGERSI_CLASS
)
2054 return X86_64_INTEGER_CLASS
;
2056 /* Rule #5: If one of the classes is X87 or X87UP class, MEMORY is used. */
2057 if (class1
== X86_64_X87_CLASS
|| class1
== X86_64_X87UP_CLASS
2058 || class2
== X86_64_X87_CLASS
|| class2
== X86_64_X87UP_CLASS
)
2059 return X86_64_MEMORY_CLASS
;
2061 /* Rule #6: Otherwise class SSE is used. */
2062 return X86_64_SSE_CLASS
;
2065 /* Classify the argument of type TYPE and mode MODE.
2066 CLASSES will be filled by the register class used to pass each word
2067 of the operand. The number of words is returned. In case the parameter
2068 should be passed in memory, 0 is returned. As a special case for zero
2069 sized containers, classes[0] will be NO_CLASS and 1 is returned.
2071 BIT_OFFSET is used internally for handling records and specifies offset
2072 of the offset in bits modulo 256 to avoid overflow cases.
2074 See the x86-64 PS ABI for details.
2078 classify_argument (enum machine_mode mode
, tree type
,
2079 enum x86_64_reg_class classes
[MAX_CLASSES
], int bit_offset
)
2081 HOST_WIDE_INT bytes
=
2082 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2083 int words
= (bytes
+ (bit_offset
% 64) / 8 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2085 /* Variable sized entities are always passed/returned in memory. */
2089 if (mode
!= VOIDmode
2090 && targetm
.calls
.must_pass_in_stack (mode
, type
))
2093 if (type
&& AGGREGATE_TYPE_P (type
))
2097 enum x86_64_reg_class subclasses
[MAX_CLASSES
];
2099 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
2103 for (i
= 0; i
< words
; i
++)
2104 classes
[i
] = X86_64_NO_CLASS
;
2106 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
2107 signalize memory class, so handle it as special case. */
2110 classes
[0] = X86_64_NO_CLASS
;
2114 /* Classify each field of record and merge classes. */
2115 if (TREE_CODE (type
) == RECORD_TYPE
)
2117 /* For classes first merge in the field of the subclasses. */
2118 if (TYPE_BINFO (type
))
2120 tree binfo
, base_binfo
;
2123 for (binfo
= TYPE_BINFO (type
), basenum
= 0;
2124 BINFO_BASE_ITERATE (binfo
, basenum
, base_binfo
); basenum
++)
2127 int offset
= tree_low_cst (BINFO_OFFSET (base_binfo
), 0) * 8;
2128 tree type
= BINFO_TYPE (base_binfo
);
2130 num
= classify_argument (TYPE_MODE (type
),
2132 (offset
+ bit_offset
) % 256);
2135 for (i
= 0; i
< num
; i
++)
2137 int pos
= (offset
+ (bit_offset
% 64)) / 8 / 8;
2139 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
2143 /* And now merge the fields of structure. */
2144 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
2146 if (TREE_CODE (field
) == FIELD_DECL
)
2150 /* Bitfields are always classified as integer. Handle them
2151 early, since later code would consider them to be
2152 misaligned integers. */
2153 if (DECL_BIT_FIELD (field
))
2155 for (i
= int_bit_position (field
) / 8 / 8;
2156 i
< (int_bit_position (field
)
2157 + tree_low_cst (DECL_SIZE (field
), 0)
2160 merge_classes (X86_64_INTEGER_CLASS
,
2165 num
= classify_argument (TYPE_MODE (TREE_TYPE (field
)),
2166 TREE_TYPE (field
), subclasses
,
2167 (int_bit_position (field
)
2168 + bit_offset
) % 256);
2171 for (i
= 0; i
< num
; i
++)
2174 (int_bit_position (field
) + (bit_offset
% 64)) / 8 / 8;
2176 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
2182 /* Arrays are handled as small records. */
2183 else if (TREE_CODE (type
) == ARRAY_TYPE
)
2186 num
= classify_argument (TYPE_MODE (TREE_TYPE (type
)),
2187 TREE_TYPE (type
), subclasses
, bit_offset
);
2191 /* The partial classes are now full classes. */
2192 if (subclasses
[0] == X86_64_SSESF_CLASS
&& bytes
!= 4)
2193 subclasses
[0] = X86_64_SSE_CLASS
;
2194 if (subclasses
[0] == X86_64_INTEGERSI_CLASS
&& bytes
!= 4)
2195 subclasses
[0] = X86_64_INTEGER_CLASS
;
2197 for (i
= 0; i
< words
; i
++)
2198 classes
[i
] = subclasses
[i
% num
];
2200 /* Unions are similar to RECORD_TYPE but offset is always 0. */
2201 else if (TREE_CODE (type
) == UNION_TYPE
2202 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
2204 /* For classes first merge in the field of the subclasses. */
2205 if (TYPE_BINFO (type
))
2207 tree binfo
, base_binfo
;
2210 for (binfo
= TYPE_BINFO (type
), basenum
= 0;
2211 BINFO_BASE_ITERATE (binfo
, basenum
, base_binfo
); basenum
++)
2214 int offset
= tree_low_cst (BINFO_OFFSET (base_binfo
), 0) * 8;
2215 tree type
= BINFO_TYPE (base_binfo
);
2217 num
= classify_argument (TYPE_MODE (type
),
2219 (offset
+ (bit_offset
% 64)) % 256);
2222 for (i
= 0; i
< num
; i
++)
2224 int pos
= (offset
+ (bit_offset
% 64)) / 8 / 8;
2226 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
2230 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
2232 if (TREE_CODE (field
) == FIELD_DECL
)
2235 num
= classify_argument (TYPE_MODE (TREE_TYPE (field
)),
2236 TREE_TYPE (field
), subclasses
,
2240 for (i
= 0; i
< num
; i
++)
2241 classes
[i
] = merge_classes (subclasses
[i
], classes
[i
]);
2245 else if (TREE_CODE (type
) == SET_TYPE
)
2249 classes
[0] = X86_64_INTEGERSI_CLASS
;
2252 else if (bytes
<= 8)
2254 classes
[0] = X86_64_INTEGER_CLASS
;
2257 else if (bytes
<= 12)
2259 classes
[0] = X86_64_INTEGER_CLASS
;
2260 classes
[1] = X86_64_INTEGERSI_CLASS
;
2265 classes
[0] = X86_64_INTEGER_CLASS
;
2266 classes
[1] = X86_64_INTEGER_CLASS
;
2273 /* Final merger cleanup. */
2274 for (i
= 0; i
< words
; i
++)
2276 /* If one class is MEMORY, everything should be passed in
2278 if (classes
[i
] == X86_64_MEMORY_CLASS
)
2281 /* The X86_64_SSEUP_CLASS should be always preceded by
2282 X86_64_SSE_CLASS. */
2283 if (classes
[i
] == X86_64_SSEUP_CLASS
2284 && (i
== 0 || classes
[i
- 1] != X86_64_SSE_CLASS
))
2285 classes
[i
] = X86_64_SSE_CLASS
;
2287 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
2288 if (classes
[i
] == X86_64_X87UP_CLASS
2289 && (i
== 0 || classes
[i
- 1] != X86_64_X87_CLASS
))
2290 classes
[i
] = X86_64_SSE_CLASS
;
2295 /* Compute alignment needed. We align all types to natural boundaries with
2296 exception of XFmode that is aligned to 64bits. */
2297 if (mode
!= VOIDmode
&& mode
!= BLKmode
)
2299 int mode_alignment
= GET_MODE_BITSIZE (mode
);
2302 mode_alignment
= 128;
2303 else if (mode
== XCmode
)
2304 mode_alignment
= 256;
2305 if (COMPLEX_MODE_P (mode
))
2306 mode_alignment
/= 2;
2307 /* Misaligned fields are always returned in memory. */
2308 if (bit_offset
% mode_alignment
)
2312 /* for V1xx modes, just use the base mode */
2313 if (VECTOR_MODE_P (mode
)
2314 && GET_MODE_SIZE (GET_MODE_INNER (mode
)) == bytes
)
2315 mode
= GET_MODE_INNER (mode
);
2317 /* Classification of atomic types. */
2327 if (bit_offset
+ GET_MODE_BITSIZE (mode
) <= 32)
2328 classes
[0] = X86_64_INTEGERSI_CLASS
;
2330 classes
[0] = X86_64_INTEGER_CLASS
;
2334 classes
[0] = classes
[1] = X86_64_INTEGER_CLASS
;
2339 if (!(bit_offset
% 64))
2340 classes
[0] = X86_64_SSESF_CLASS
;
2342 classes
[0] = X86_64_SSE_CLASS
;
2345 classes
[0] = X86_64_SSEDF_CLASS
;
2348 classes
[0] = X86_64_X87_CLASS
;
2349 classes
[1] = X86_64_X87UP_CLASS
;
2352 classes
[0] = X86_64_SSE_CLASS
;
2353 classes
[1] = X86_64_SSEUP_CLASS
;
2356 classes
[0] = X86_64_SSE_CLASS
;
2359 classes
[0] = X86_64_SSEDF_CLASS
;
2360 classes
[1] = X86_64_SSEDF_CLASS
;
2364 /* These modes are larger than 16 bytes. */
2372 classes
[0] = X86_64_SSE_CLASS
;
2373 classes
[1] = X86_64_SSEUP_CLASS
;
2379 classes
[0] = X86_64_SSE_CLASS
;
2385 if (VECTOR_MODE_P (mode
))
2389 if (GET_MODE_CLASS (GET_MODE_INNER (mode
)) == MODE_INT
)
2391 if (bit_offset
+ GET_MODE_BITSIZE (mode
) <= 32)
2392 classes
[0] = X86_64_INTEGERSI_CLASS
;
2394 classes
[0] = X86_64_INTEGER_CLASS
;
2395 classes
[1] = X86_64_INTEGER_CLASS
;
2396 return 1 + (bytes
> 8);
2403 /* Examine the argument and return set number of register required in each
2404 class. Return 0 iff parameter should be passed in memory. */
2406 examine_argument (enum machine_mode mode
, tree type
, int in_return
,
2407 int *int_nregs
, int *sse_nregs
)
2409 enum x86_64_reg_class
class[MAX_CLASSES
];
2410 int n
= classify_argument (mode
, type
, class, 0);
2416 for (n
--; n
>= 0; n
--)
2419 case X86_64_INTEGER_CLASS
:
2420 case X86_64_INTEGERSI_CLASS
:
2423 case X86_64_SSE_CLASS
:
2424 case X86_64_SSESF_CLASS
:
2425 case X86_64_SSEDF_CLASS
:
2428 case X86_64_NO_CLASS
:
2429 case X86_64_SSEUP_CLASS
:
2431 case X86_64_X87_CLASS
:
2432 case X86_64_X87UP_CLASS
:
2436 case X86_64_MEMORY_CLASS
:
2441 /* Construct container for the argument used by GCC interface. See
2442 FUNCTION_ARG for the detailed description. */
2444 construct_container (enum machine_mode mode
, tree type
, int in_return
,
2445 int nintregs
, int nsseregs
, const int * intreg
,
2448 enum machine_mode tmpmode
;
2450 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2451 enum x86_64_reg_class
class[MAX_CLASSES
];
2455 int needed_sseregs
, needed_intregs
;
2456 rtx exp
[MAX_CLASSES
];
2459 n
= classify_argument (mode
, type
, class, 0);
2460 if (TARGET_DEBUG_ARG
)
2463 fprintf (stderr
, "Memory class\n");
2466 fprintf (stderr
, "Classes:");
2467 for (i
= 0; i
< n
; i
++)
2469 fprintf (stderr
, " %s", x86_64_reg_class_name
[class[i
]]);
2471 fprintf (stderr
, "\n");
2476 if (!examine_argument (mode
, type
, in_return
, &needed_intregs
, &needed_sseregs
))
2478 if (needed_intregs
> nintregs
|| needed_sseregs
> nsseregs
)
2481 /* First construct simple cases. Avoid SCmode, since we want to use
2482 single register to pass this type. */
2483 if (n
== 1 && mode
!= SCmode
)
2486 case X86_64_INTEGER_CLASS
:
2487 case X86_64_INTEGERSI_CLASS
:
2488 return gen_rtx_REG (mode
, intreg
[0]);
2489 case X86_64_SSE_CLASS
:
2490 case X86_64_SSESF_CLASS
:
2491 case X86_64_SSEDF_CLASS
:
2492 return gen_rtx_REG (mode
, SSE_REGNO (sse_regno
));
2493 case X86_64_X87_CLASS
:
2494 return gen_rtx_REG (mode
, FIRST_STACK_REG
);
2495 case X86_64_NO_CLASS
:
2496 /* Zero sized array, struct or class. */
2501 if (n
== 2 && class[0] == X86_64_SSE_CLASS
&& class[1] == X86_64_SSEUP_CLASS
2503 return gen_rtx_REG (mode
, SSE_REGNO (sse_regno
));
2505 && class[0] == X86_64_X87_CLASS
&& class[1] == X86_64_X87UP_CLASS
)
2506 return gen_rtx_REG (XFmode
, FIRST_STACK_REG
);
2507 if (n
== 2 && class[0] == X86_64_INTEGER_CLASS
2508 && class[1] == X86_64_INTEGER_CLASS
2509 && (mode
== CDImode
|| mode
== TImode
|| mode
== TFmode
)
2510 && intreg
[0] + 1 == intreg
[1])
2511 return gen_rtx_REG (mode
, intreg
[0]);
2513 && class[0] == X86_64_X87_CLASS
&& class[1] == X86_64_X87UP_CLASS
2514 && class[2] == X86_64_X87_CLASS
&& class[3] == X86_64_X87UP_CLASS
2516 return gen_rtx_REG (XCmode
, FIRST_STACK_REG
);
2518 /* Otherwise figure out the entries of the PARALLEL. */
2519 for (i
= 0; i
< n
; i
++)
2523 case X86_64_NO_CLASS
:
2525 case X86_64_INTEGER_CLASS
:
2526 case X86_64_INTEGERSI_CLASS
:
2527 /* Merge TImodes on aligned occasions here too. */
2528 if (i
* 8 + 8 > bytes
)
2529 tmpmode
= mode_for_size ((bytes
- i
* 8) * BITS_PER_UNIT
, MODE_INT
, 0);
2530 else if (class[i
] == X86_64_INTEGERSI_CLASS
)
2534 /* We've requested 24 bytes we don't have mode for. Use DImode. */
2535 if (tmpmode
== BLKmode
)
2537 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2538 gen_rtx_REG (tmpmode
, *intreg
),
2542 case X86_64_SSESF_CLASS
:
2543 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2544 gen_rtx_REG (SFmode
,
2545 SSE_REGNO (sse_regno
)),
2549 case X86_64_SSEDF_CLASS
:
2550 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2551 gen_rtx_REG (DFmode
,
2552 SSE_REGNO (sse_regno
)),
2556 case X86_64_SSE_CLASS
:
2557 if (i
< n
- 1 && class[i
+ 1] == X86_64_SSEUP_CLASS
)
2561 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2562 gen_rtx_REG (tmpmode
,
2563 SSE_REGNO (sse_regno
)),
2565 if (tmpmode
== TImode
)
2573 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nexps
));
2574 for (i
= 0; i
< nexps
; i
++)
2575 XVECEXP (ret
, 0, i
) = exp
[i
];
2579 /* Update the data in CUM to advance over an argument
2580 of mode MODE and data type TYPE.
2581 (TYPE is null for libcalls where that information may not be available.) */
2584 function_arg_advance (CUMULATIVE_ARGS
*cum
, /* current arg information */
2585 enum machine_mode mode
, /* current arg mode */
2586 tree type
, /* type of the argument or 0 if lib support */
2587 int named
) /* whether or not the argument was named */
2590 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2591 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2593 if (TARGET_DEBUG_ARG
)
2595 "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, mode=%s, named=%d)\n\n",
2596 words
, cum
->words
, cum
->nregs
, cum
->sse_nregs
, GET_MODE_NAME (mode
), named
);
2599 int int_nregs
, sse_nregs
;
2600 if (!examine_argument (mode
, type
, 0, &int_nregs
, &sse_nregs
))
2601 cum
->words
+= words
;
2602 else if (sse_nregs
<= cum
->sse_nregs
&& int_nregs
<= cum
->nregs
)
2604 cum
->nregs
-= int_nregs
;
2605 cum
->sse_nregs
-= sse_nregs
;
2606 cum
->regno
+= int_nregs
;
2607 cum
->sse_regno
+= sse_nregs
;
2610 cum
->words
+= words
;
2614 if (TARGET_SSE
&& SSE_REG_MODE_P (mode
)
2615 && (!type
|| !AGGREGATE_TYPE_P (type
)))
2617 cum
->sse_words
+= words
;
2618 cum
->sse_nregs
-= 1;
2619 cum
->sse_regno
+= 1;
2620 if (cum
->sse_nregs
<= 0)
2626 else if (TARGET_MMX
&& MMX_REG_MODE_P (mode
)
2627 && (!type
|| !AGGREGATE_TYPE_P (type
)))
2629 cum
->mmx_words
+= words
;
2630 cum
->mmx_nregs
-= 1;
2631 cum
->mmx_regno
+= 1;
2632 if (cum
->mmx_nregs
<= 0)
2640 cum
->words
+= words
;
2641 cum
->nregs
-= words
;
2642 cum
->regno
+= words
;
2644 if (cum
->nregs
<= 0)
2654 /* Define where to put the arguments to a function.
2655 Value is zero to push the argument on the stack,
2656 or a hard register in which to store the argument.
2658 MODE is the argument's machine mode.
2659 TYPE is the data type of the argument (as a tree).
2660 This is null for libcalls where that information may
2662 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2663 the preceding args and about the function being called.
2664 NAMED is nonzero if this argument is a named parameter
2665 (otherwise it is an extra parameter matching an ellipsis). */
2668 function_arg (CUMULATIVE_ARGS
*cum
, /* current arg information */
2669 enum machine_mode mode
, /* current arg mode */
2670 tree type
, /* type of the argument or 0 if lib support */
2671 int named
) /* != 0 for normal args, == 0 for ... args */
2675 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2676 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2677 static bool warnedsse
, warnedmmx
;
2679 /* To simplify the code below, represent vector types with a vector mode
2680 even if MMX/SSE are not active. */
2682 && TREE_CODE (type
) == VECTOR_TYPE
2683 && (bytes
== 8 || bytes
== 16)
2684 && GET_MODE_CLASS (TYPE_MODE (type
)) != MODE_VECTOR_INT
2685 && GET_MODE_CLASS (TYPE_MODE (type
)) != MODE_VECTOR_FLOAT
)
2687 enum machine_mode innermode
= TYPE_MODE (TREE_TYPE (type
));
2688 enum machine_mode newmode
2689 = TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
2690 ? MIN_MODE_VECTOR_FLOAT
: MIN_MODE_VECTOR_INT
;
2692 /* Get the mode which has this inner mode and number of units. */
2693 for (; newmode
!= VOIDmode
; newmode
= GET_MODE_WIDER_MODE (newmode
))
2694 if (GET_MODE_NUNITS (newmode
) == TYPE_VECTOR_SUBPARTS (type
)
2695 && GET_MODE_INNER (newmode
) == innermode
)
2702 /* Handle a hidden AL argument containing number of registers for varargs
2703 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
2705 if (mode
== VOIDmode
)
2708 return GEN_INT (cum
->maybe_vaarg
2709 ? (cum
->sse_nregs
< 0
2717 ret
= construct_container (mode
, type
, 0, cum
->nregs
, cum
->sse_nregs
,
2718 &x86_64_int_parameter_registers
[cum
->regno
],
2723 /* For now, pass fp/complex values on the stack. */
2735 if (words
<= cum
->nregs
)
2737 int regno
= cum
->regno
;
2739 /* Fastcall allocates the first two DWORD (SImode) or
2740 smaller arguments to ECX and EDX. */
2743 if (mode
== BLKmode
|| mode
== DImode
)
2746 /* ECX not EAX is the first allocated register. */
2750 ret
= gen_rtx_REG (mode
, regno
);
2760 if (!type
|| !AGGREGATE_TYPE_P (type
))
2762 if (!TARGET_SSE
&& !warnedsse
&& cum
->warn_sse
)
2765 warning ("SSE vector argument without SSE enabled "
2769 ret
= gen_rtx_REG (mode
, cum
->sse_regno
+ FIRST_SSE_REG
);
2776 if (!type
|| !AGGREGATE_TYPE_P (type
))
2778 if (!TARGET_MMX
&& !warnedmmx
&& cum
->warn_mmx
)
2781 warning ("MMX vector argument without MMX enabled "
2785 ret
= gen_rtx_REG (mode
, cum
->mmx_regno
+ FIRST_MMX_REG
);
2790 if (TARGET_DEBUG_ARG
)
2793 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
2794 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
2797 print_simple_rtl (stderr
, ret
);
2799 fprintf (stderr
, ", stack");
2801 fprintf (stderr
, " )\n");
2807 /* A C expression that indicates when an argument must be passed by
2808 reference. If nonzero for an argument, a copy of that argument is
2809 made in memory and a pointer to the argument is passed instead of
2810 the argument itself. The pointer is passed in whatever way is
2811 appropriate for passing a pointer to that type. */
2814 ix86_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2815 enum machine_mode mode ATTRIBUTE_UNUSED
,
2816 tree type
, bool named ATTRIBUTE_UNUSED
)
2821 if (type
&& int_size_in_bytes (type
) == -1)
2823 if (TARGET_DEBUG_ARG
)
2824 fprintf (stderr
, "function_arg_pass_by_reference\n");
2831 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
2832 ABI. Only called if TARGET_SSE. */
2834 contains_128bit_aligned_vector_p (tree type
)
2836 enum machine_mode mode
= TYPE_MODE (type
);
2837 if (SSE_REG_MODE_P (mode
)
2838 && (!TYPE_USER_ALIGN (type
) || TYPE_ALIGN (type
) > 128))
2840 if (TYPE_ALIGN (type
) < 128)
2843 if (AGGREGATE_TYPE_P (type
))
2845 /* Walk the aggregates recursively. */
2846 if (TREE_CODE (type
) == RECORD_TYPE
2847 || TREE_CODE (type
) == UNION_TYPE
2848 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
2852 if (TYPE_BINFO (type
))
2854 tree binfo
, base_binfo
;
2857 for (binfo
= TYPE_BINFO (type
), i
= 0;
2858 BINFO_BASE_ITERATE (binfo
, i
, base_binfo
); i
++)
2859 if (contains_128bit_aligned_vector_p (BINFO_TYPE (base_binfo
)))
2862 /* And now merge the fields of structure. */
2863 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
2865 if (TREE_CODE (field
) == FIELD_DECL
2866 && contains_128bit_aligned_vector_p (TREE_TYPE (field
)))
2870 /* Just for use if some languages passes arrays by value. */
2871 else if (TREE_CODE (type
) == ARRAY_TYPE
)
2873 if (contains_128bit_aligned_vector_p (TREE_TYPE (type
)))
2882 /* Gives the alignment boundary, in bits, of an argument with the
2883 specified mode and type. */
2886 ix86_function_arg_boundary (enum machine_mode mode
, tree type
)
2890 align
= TYPE_ALIGN (type
);
2892 align
= GET_MODE_ALIGNMENT (mode
);
2893 if (align
< PARM_BOUNDARY
)
2894 align
= PARM_BOUNDARY
;
2897 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
2898 make an exception for SSE modes since these require 128bit
2901 The handling here differs from field_alignment. ICC aligns MMX
2902 arguments to 4 byte boundaries, while structure fields are aligned
2903 to 8 byte boundaries. */
2905 align
= PARM_BOUNDARY
;
2908 if (!SSE_REG_MODE_P (mode
))
2909 align
= PARM_BOUNDARY
;
2913 if (!contains_128bit_aligned_vector_p (type
))
2914 align
= PARM_BOUNDARY
;
2922 /* Return true if N is a possible register number of function value. */
2924 ix86_function_value_regno_p (int regno
)
2928 return ((regno
) == 0
2929 || ((regno
) == FIRST_FLOAT_REG
&& TARGET_FLOAT_RETURNS_IN_80387
)
2930 || ((regno
) == FIRST_SSE_REG
&& TARGET_SSE
));
2932 return ((regno
) == 0 || (regno
) == FIRST_FLOAT_REG
2933 || ((regno
) == FIRST_SSE_REG
&& TARGET_SSE
)
2934 || ((regno
) == FIRST_FLOAT_REG
&& TARGET_FLOAT_RETURNS_IN_80387
));
2937 /* Define how to find the value returned by a function.
2938 VALTYPE is the data type of the value (as a tree).
2939 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2940 otherwise, FUNC is 0. */
2942 ix86_function_value (tree valtype
)
2946 rtx ret
= construct_container (TYPE_MODE (valtype
), valtype
, 1,
2947 REGPARM_MAX
, SSE_REGPARM_MAX
,
2948 x86_64_int_return_registers
, 0);
2949 /* For zero sized structures, construct_container return NULL, but we need
2950 to keep rest of compiler happy by returning meaningful value. */
2952 ret
= gen_rtx_REG (TYPE_MODE (valtype
), 0);
2956 return gen_rtx_REG (TYPE_MODE (valtype
),
2957 ix86_value_regno (TYPE_MODE (valtype
)));
2960 /* Return false iff type is returned in memory. */
2962 ix86_return_in_memory (tree type
)
2964 int needed_intregs
, needed_sseregs
, size
;
2965 enum machine_mode mode
= TYPE_MODE (type
);
2968 return !examine_argument (mode
, type
, 1, &needed_intregs
, &needed_sseregs
);
2970 if (mode
== BLKmode
)
2973 size
= int_size_in_bytes (type
);
2975 if (MS_AGGREGATE_RETURN
&& AGGREGATE_TYPE_P (type
) && size
<= 8)
2978 if (VECTOR_MODE_P (mode
) || mode
== TImode
)
2980 /* User-created vectors small enough to fit in EAX. */
2984 /* MMX/3dNow values are returned on the stack, since we've
2985 got to EMMS/FEMMS before returning. */
2989 /* SSE values are returned in XMM0, except when it doesn't exist. */
2991 return (TARGET_SSE
? 0 : 1);
3002 /* When returning SSE vector types, we have a choice of either
3003 (1) being abi incompatible with a -march switch, or
3004 (2) generating an error.
3005 Given no good solution, I think the safest thing is one warning.
3006 The user won't be able to use -Werror, but....
3008 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
3009 called in response to actually generating a caller or callee that
3010 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
3011 via aggregate_value_p for general type probing from tree-ssa. */
3014 ix86_struct_value_rtx (tree type
, int incoming ATTRIBUTE_UNUSED
)
3018 if (!TARGET_SSE
&& type
&& !warned
)
3020 /* Look at the return type of the function, not the function type. */
3021 enum machine_mode mode
= TYPE_MODE (TREE_TYPE (type
));
3024 || (VECTOR_MODE_P (mode
) && GET_MODE_SIZE (mode
) == 16))
3027 warning ("SSE vector return without SSE enabled changes the ABI");
3034 /* Define how to find the value returned by a library function
3035 assuming the value has mode MODE. */
3037 ix86_libcall_value (enum machine_mode mode
)
3048 return gen_rtx_REG (mode
, FIRST_SSE_REG
);
3050 return gen_rtx_REG (mode
, FIRST_FLOAT_REG
);
3055 return gen_rtx_REG (mode
, 0);
3059 return gen_rtx_REG (mode
, ix86_value_regno (mode
));
3062 /* Given a mode, return the register to use for a return value. */
3065 ix86_value_regno (enum machine_mode mode
)
3067 /* Floating point return values in %st(0). */
3068 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& TARGET_FLOAT_RETURNS_IN_80387
)
3069 return FIRST_FLOAT_REG
;
3070 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
3071 we prevent this case when sse is not available. */
3072 if (mode
== TImode
|| (VECTOR_MODE_P (mode
) && GET_MODE_SIZE (mode
) == 16))
3073 return FIRST_SSE_REG
;
3074 /* Everything else in %eax. */
3078 /* Create the va_list data type. */
3081 ix86_build_builtin_va_list (void)
3083 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
3085 /* For i386 we use plain pointer to argument area. */
3087 return build_pointer_type (char_type_node
);
3089 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
3090 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
3092 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gp_offset"),
3093 unsigned_type_node
);
3094 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fp_offset"),
3095 unsigned_type_node
);
3096 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
3098 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
3101 DECL_FIELD_CONTEXT (f_gpr
) = record
;
3102 DECL_FIELD_CONTEXT (f_fpr
) = record
;
3103 DECL_FIELD_CONTEXT (f_ovf
) = record
;
3104 DECL_FIELD_CONTEXT (f_sav
) = record
;
3106 TREE_CHAIN (record
) = type_decl
;
3107 TYPE_NAME (record
) = type_decl
;
3108 TYPE_FIELDS (record
) = f_gpr
;
3109 TREE_CHAIN (f_gpr
) = f_fpr
;
3110 TREE_CHAIN (f_fpr
) = f_ovf
;
3111 TREE_CHAIN (f_ovf
) = f_sav
;
3113 layout_type (record
);
3115 /* The correct type is an array type of one element. */
3116 return build_array_type (record
, build_index_type (size_zero_node
));
3119 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3122 ix86_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3123 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
3126 CUMULATIVE_ARGS next_cum
;
3127 rtx save_area
= NULL_RTX
, mem
;
3140 /* Indicate to allocate space on the stack for varargs save area. */
3141 ix86_save_varrargs_registers
= 1;
3143 cfun
->stack_alignment_needed
= 128;
3145 fntype
= TREE_TYPE (current_function_decl
);
3146 stdarg_p
= (TYPE_ARG_TYPES (fntype
) != 0
3147 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
3148 != void_type_node
));
3150 /* For varargs, we do not want to skip the dummy va_dcl argument.
3151 For stdargs, we do want to skip the last named argument. */
3154 function_arg_advance (&next_cum
, mode
, type
, 1);
3157 save_area
= frame_pointer_rtx
;
3159 set
= get_varargs_alias_set ();
3161 for (i
= next_cum
.regno
; i
< ix86_regparm
; i
++)
3163 mem
= gen_rtx_MEM (Pmode
,
3164 plus_constant (save_area
, i
* UNITS_PER_WORD
));
3165 set_mem_alias_set (mem
, set
);
3166 emit_move_insn (mem
, gen_rtx_REG (Pmode
,
3167 x86_64_int_parameter_registers
[i
]));
3170 if (next_cum
.sse_nregs
)
3172 /* Now emit code to save SSE registers. The AX parameter contains number
3173 of SSE parameter registers used to call this function. We use
3174 sse_prologue_save insn template that produces computed jump across
3175 SSE saves. We need some preparation work to get this working. */
3177 label
= gen_label_rtx ();
3178 label_ref
= gen_rtx_LABEL_REF (Pmode
, label
);
3180 /* Compute address to jump to :
3181 label - 5*eax + nnamed_sse_arguments*5 */
3182 tmp_reg
= gen_reg_rtx (Pmode
);
3183 nsse_reg
= gen_reg_rtx (Pmode
);
3184 emit_insn (gen_zero_extendqidi2 (nsse_reg
, gen_rtx_REG (QImode
, 0)));
3185 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
,
3186 gen_rtx_MULT (Pmode
, nsse_reg
,
3188 if (next_cum
.sse_regno
)
3191 gen_rtx_CONST (DImode
,
3192 gen_rtx_PLUS (DImode
,
3194 GEN_INT (next_cum
.sse_regno
* 4))));
3196 emit_move_insn (nsse_reg
, label_ref
);
3197 emit_insn (gen_subdi3 (nsse_reg
, nsse_reg
, tmp_reg
));
3199 /* Compute address of memory block we save into. We always use pointer
3200 pointing 127 bytes after first byte to store - this is needed to keep
3201 instruction size limited by 4 bytes. */
3202 tmp_reg
= gen_reg_rtx (Pmode
);
3203 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
,
3204 plus_constant (save_area
,
3205 8 * REGPARM_MAX
+ 127)));
3206 mem
= gen_rtx_MEM (BLKmode
, plus_constant (tmp_reg
, -127));
3207 set_mem_alias_set (mem
, set
);
3208 set_mem_align (mem
, BITS_PER_WORD
);
3210 /* And finally do the dirty job! */
3211 emit_insn (gen_sse_prologue_save (mem
, nsse_reg
,
3212 GEN_INT (next_cum
.sse_regno
), label
));
3217 /* Implement va_start. */
3220 ix86_va_start (tree valist
, rtx nextarg
)
3222 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
3223 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
3224 tree gpr
, fpr
, ovf
, sav
, t
;
3226 /* Only 64bit target needs something special. */
3229 std_expand_builtin_va_start (valist
, nextarg
);
3233 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
3234 f_fpr
= TREE_CHAIN (f_gpr
);
3235 f_ovf
= TREE_CHAIN (f_fpr
);
3236 f_sav
= TREE_CHAIN (f_ovf
);
3238 valist
= build1 (INDIRECT_REF
, TREE_TYPE (TREE_TYPE (valist
)), valist
);
3239 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
3240 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
3241 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
3242 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
3244 /* Count number of gp and fp argument registers used. */
3245 words
= current_function_args_info
.words
;
3246 n_gpr
= current_function_args_info
.regno
;
3247 n_fpr
= current_function_args_info
.sse_regno
;
3249 if (TARGET_DEBUG_ARG
)
3250 fprintf (stderr
, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
3251 (int) words
, (int) n_gpr
, (int) n_fpr
);
3253 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
3254 build_int_cst (NULL_TREE
, n_gpr
* 8));
3255 TREE_SIDE_EFFECTS (t
) = 1;
3256 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3258 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
3259 build_int_cst (NULL_TREE
, n_fpr
* 16 + 8*REGPARM_MAX
));
3260 TREE_SIDE_EFFECTS (t
) = 1;
3261 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3263 /* Find the overflow area. */
3264 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
3266 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
3267 build_int_cst (NULL_TREE
, words
* UNITS_PER_WORD
));
3268 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
3269 TREE_SIDE_EFFECTS (t
) = 1;
3270 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3272 /* Find the register save area.
3273 Prologue of the function save it right above stack frame. */
3274 t
= make_tree (TREE_TYPE (sav
), frame_pointer_rtx
);
3275 t
= build (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
3276 TREE_SIDE_EFFECTS (t
) = 1;
3277 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3280 /* Implement va_arg. */
3283 ix86_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
3285 static const int intreg
[6] = { 0, 1, 2, 3, 4, 5 };
3286 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
3287 tree gpr
, fpr
, ovf
, sav
, t
;
3289 tree lab_false
, lab_over
= NULL_TREE
;
3295 /* Only 64bit target needs something special. */
3297 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
3299 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
3300 f_fpr
= TREE_CHAIN (f_gpr
);
3301 f_ovf
= TREE_CHAIN (f_fpr
);
3302 f_sav
= TREE_CHAIN (f_ovf
);
3304 valist
= build_va_arg_indirect_ref (valist
);
3305 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
3306 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
3307 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
3308 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
3310 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
3312 type
= build_pointer_type (type
);
3313 size
= int_size_in_bytes (type
);
3314 rsize
= (size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3316 container
= construct_container (TYPE_MODE (type
), type
, 0,
3317 REGPARM_MAX
, SSE_REGPARM_MAX
, intreg
, 0);
3319 * Pull the value out of the saved registers ...
3322 addr
= create_tmp_var (ptr_type_node
, "addr");
3323 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
3327 int needed_intregs
, needed_sseregs
;
3329 tree int_addr
, sse_addr
;
3331 lab_false
= create_artificial_label ();
3332 lab_over
= create_artificial_label ();
3334 examine_argument (TYPE_MODE (type
), type
, 0,
3335 &needed_intregs
, &needed_sseregs
);
3337 need_temp
= (!REG_P (container
)
3338 && ((needed_intregs
&& TYPE_ALIGN (type
) > 64)
3339 || TYPE_ALIGN (type
) > 128));
3341 /* In case we are passing structure, verify that it is consecutive block
3342 on the register save area. If not we need to do moves. */
3343 if (!need_temp
&& !REG_P (container
))
3345 /* Verify that all registers are strictly consecutive */
3346 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container
, 0, 0), 0))))
3350 for (i
= 0; i
< XVECLEN (container
, 0) && !need_temp
; i
++)
3352 rtx slot
= XVECEXP (container
, 0, i
);
3353 if (REGNO (XEXP (slot
, 0)) != FIRST_SSE_REG
+ (unsigned int) i
3354 || INTVAL (XEXP (slot
, 1)) != i
* 16)
3362 for (i
= 0; i
< XVECLEN (container
, 0) && !need_temp
; i
++)
3364 rtx slot
= XVECEXP (container
, 0, i
);
3365 if (REGNO (XEXP (slot
, 0)) != (unsigned int) i
3366 || INTVAL (XEXP (slot
, 1)) != i
* 8)
3378 int_addr
= create_tmp_var (ptr_type_node
, "int_addr");
3379 DECL_POINTER_ALIAS_SET (int_addr
) = get_varargs_alias_set ();
3380 sse_addr
= create_tmp_var (ptr_type_node
, "sse_addr");
3381 DECL_POINTER_ALIAS_SET (sse_addr
) = get_varargs_alias_set ();
3383 /* First ensure that we fit completely in registers. */
3386 t
= build_int_cst (TREE_TYPE (gpr
),
3387 (REGPARM_MAX
- needed_intregs
+ 1) * 8);
3388 t
= build2 (GE_EXPR
, boolean_type_node
, gpr
, t
);
3389 t2
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
3390 t
= build (COND_EXPR
, void_type_node
, t
, t2
, NULL_TREE
);
3391 gimplify_and_add (t
, pre_p
);
3395 t
= build_int_cst (TREE_TYPE (fpr
),
3396 (SSE_REGPARM_MAX
- needed_sseregs
+ 1) * 16
3398 t
= build2 (GE_EXPR
, boolean_type_node
, fpr
, t
);
3399 t2
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
3400 t
= build (COND_EXPR
, void_type_node
, t
, t2
, NULL_TREE
);
3401 gimplify_and_add (t
, pre_p
);
3404 /* Compute index to start of area used for integer regs. */
3407 /* int_addr = gpr + sav; */
3408 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, gpr
);
3409 t
= build2 (MODIFY_EXPR
, void_type_node
, int_addr
, t
);
3410 gimplify_and_add (t
, pre_p
);
3414 /* sse_addr = fpr + sav; */
3415 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, fpr
);
3416 t
= build2 (MODIFY_EXPR
, void_type_node
, sse_addr
, t
);
3417 gimplify_and_add (t
, pre_p
);
3422 tree temp
= create_tmp_var (type
, "va_arg_tmp");
3425 t
= build1 (ADDR_EXPR
, build_pointer_type (type
), temp
);
3426 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
3427 gimplify_and_add (t
, pre_p
);
3429 for (i
= 0; i
< XVECLEN (container
, 0); i
++)
3431 rtx slot
= XVECEXP (container
, 0, i
);
3432 rtx reg
= XEXP (slot
, 0);
3433 enum machine_mode mode
= GET_MODE (reg
);
3434 tree piece_type
= lang_hooks
.types
.type_for_mode (mode
, 1);
3435 tree addr_type
= build_pointer_type (piece_type
);
3438 tree dest_addr
, dest
;
3440 if (SSE_REGNO_P (REGNO (reg
)))
3442 src_addr
= sse_addr
;
3443 src_offset
= (REGNO (reg
) - FIRST_SSE_REG
) * 16;
3447 src_addr
= int_addr
;
3448 src_offset
= REGNO (reg
) * 8;
3450 src_addr
= fold_convert (addr_type
, src_addr
);
3451 src_addr
= fold (build2 (PLUS_EXPR
, addr_type
, src_addr
,
3452 size_int (src_offset
)));
3453 src
= build_va_arg_indirect_ref (src_addr
);
3455 dest_addr
= fold_convert (addr_type
, addr
);
3456 dest_addr
= fold (build2 (PLUS_EXPR
, addr_type
, dest_addr
,
3457 size_int (INTVAL (XEXP (slot
, 1)))));
3458 dest
= build_va_arg_indirect_ref (dest_addr
);
3460 t
= build2 (MODIFY_EXPR
, void_type_node
, dest
, src
);
3461 gimplify_and_add (t
, pre_p
);
3467 t
= build2 (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
3468 build_int_cst (NULL_TREE
, needed_intregs
* 8));
3469 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
3470 gimplify_and_add (t
, pre_p
);
3474 t
= build2 (PLUS_EXPR
, TREE_TYPE (fpr
), fpr
,
3475 build_int_cst (NULL_TREE
, needed_sseregs
* 16));
3476 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
, t
);
3477 gimplify_and_add (t
, pre_p
);
3480 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
3481 gimplify_and_add (t
, pre_p
);
3483 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
3484 append_to_statement_list (t
, pre_p
);
3487 /* ... otherwise out of the overflow area. */
3489 /* Care for on-stack alignment if needed. */
3490 if (FUNCTION_ARG_BOUNDARY (VOIDmode
, type
) <= 64)
3494 HOST_WIDE_INT align
= FUNCTION_ARG_BOUNDARY (VOIDmode
, type
) / 8;
3495 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), ovf
,
3496 build_int_cst (NULL_TREE
, align
- 1));
3497 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
3498 build_int_cst (NULL_TREE
, -align
));
3500 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
3502 t2
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
3503 gimplify_and_add (t2
, pre_p
);
3505 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
,
3506 build_int_cst (NULL_TREE
, rsize
* UNITS_PER_WORD
));
3507 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
3508 gimplify_and_add (t
, pre_p
);
3512 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
3513 append_to_statement_list (t
, pre_p
);
3516 ptrtype
= build_pointer_type (type
);
3517 addr
= fold_convert (ptrtype
, addr
);
3520 addr
= build_va_arg_indirect_ref (addr
);
3521 return build_va_arg_indirect_ref (addr
);
3524 /* Return nonzero if OPNUM's MEM should be matched
3525 in movabs* patterns. */
3528 ix86_check_movabs (rtx insn
, int opnum
)
3532 set
= PATTERN (insn
);
3533 if (GET_CODE (set
) == PARALLEL
)
3534 set
= XVECEXP (set
, 0, 0);
3535 if (GET_CODE (set
) != SET
)
3537 mem
= XEXP (set
, opnum
);
3538 while (GET_CODE (mem
) == SUBREG
)
3539 mem
= SUBREG_REG (mem
);
3540 if (GET_CODE (mem
) != MEM
)
3542 return (volatile_ok
|| !MEM_VOLATILE_P (mem
));
3545 /* Initialize the table of extra 80387 mathematical constants. */
3548 init_ext_80387_constants (void)
3550 static const char * cst
[5] =
3552 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
3553 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
3554 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
3555 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
3556 "3.1415926535897932385128089594061862044", /* 4: fldpi */
3560 for (i
= 0; i
< 5; i
++)
3562 real_from_string (&ext_80387_constants_table
[i
], cst
[i
]);
3563 /* Ensure each constant is rounded to XFmode precision. */
3564 real_convert (&ext_80387_constants_table
[i
],
3565 XFmode
, &ext_80387_constants_table
[i
]);
3568 ext_80387_constants_init
= 1;
3571 /* Return true if the constant is something that can be loaded with
3572 a special instruction. */
3575 standard_80387_constant_p (rtx x
)
3577 if (GET_CODE (x
) != CONST_DOUBLE
|| !FLOAT_MODE_P (GET_MODE (x
)))
3580 if (x
== CONST0_RTX (GET_MODE (x
)))
3582 if (x
== CONST1_RTX (GET_MODE (x
)))
3585 /* For XFmode constants, try to find a special 80387 instruction when
3586 optimizing for size or on those CPUs that benefit from them. */
3587 if (GET_MODE (x
) == XFmode
3588 && (optimize_size
|| x86_ext_80387_constants
& TUNEMASK
))
3593 if (! ext_80387_constants_init
)
3594 init_ext_80387_constants ();
3596 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3597 for (i
= 0; i
< 5; i
++)
3598 if (real_identical (&r
, &ext_80387_constants_table
[i
]))
3605 /* Return the opcode of the special instruction to be used to load
3609 standard_80387_constant_opcode (rtx x
)
3611 switch (standard_80387_constant_p (x
))
3631 /* Return the CONST_DOUBLE representing the 80387 constant that is
3632 loaded by the specified special instruction. The argument IDX
3633 matches the return value from standard_80387_constant_p. */
3636 standard_80387_constant_rtx (int idx
)
3640 if (! ext_80387_constants_init
)
3641 init_ext_80387_constants ();
3657 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table
[i
],
3661 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
3664 standard_sse_constant_p (rtx x
)
3666 if (x
== const0_rtx
)
3668 return (x
== CONST0_RTX (GET_MODE (x
)));
3671 /* Returns 1 if OP contains a symbol reference */
3674 symbolic_reference_mentioned_p (rtx op
)
3679 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
3682 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3683 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3689 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3690 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3694 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
3701 /* Return 1 if it is appropriate to emit `ret' instructions in the
3702 body of a function. Do this only if the epilogue is simple, needing a
3703 couple of insns. Prior to reloading, we can't tell how many registers
3704 must be saved, so return 0 then. Return 0 if there is no frame
3705 marker to de-allocate.
3707 If NON_SAVING_SETJMP is defined and true, then it is not possible
3708 for the epilogue to be simple, so return 0. This is a special case
3709 since NON_SAVING_SETJMP will not cause regs_ever_live to change
3710 until final, but jump_optimize may need to know sooner if a
3714 ix86_can_use_return_insn_p (void)
3716 struct ix86_frame frame
;
3718 #ifdef NON_SAVING_SETJMP
3719 if (NON_SAVING_SETJMP
&& current_function_calls_setjmp
)
3723 if (! reload_completed
|| frame_pointer_needed
)
3726 /* Don't allow more than 32 pop, since that's all we can do
3727 with one instruction. */
3728 if (current_function_pops_args
3729 && current_function_args_size
>= 32768)
3732 ix86_compute_frame_layout (&frame
);
3733 return frame
.to_allocate
== 0 && frame
.nregs
== 0;
3736 /* Value should be nonzero if functions must have frame pointers.
3737 Zero means the frame pointer need not be set up (and parms may
3738 be accessed via the stack pointer) in functions that seem suitable. */
3741 ix86_frame_pointer_required (void)
3743 /* If we accessed previous frames, then the generated code expects
3744 to be able to access the saved ebp value in our frame. */
3745 if (cfun
->machine
->accesses_prev_frame
)
3748 /* Several x86 os'es need a frame pointer for other reasons,
3749 usually pertaining to setjmp. */
3750 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
3753 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
3754 the frame pointer by default. Turn it back on now if we've not
3755 got a leaf function. */
3756 if (TARGET_OMIT_LEAF_FRAME_POINTER
3757 && (!current_function_is_leaf
))
3760 if (current_function_profile
)
3766 /* Record that the current function accesses previous call frames. */
3769 ix86_setup_frame_addresses (void)
3771 cfun
->machine
->accesses_prev_frame
= 1;
3774 #if defined(HAVE_GAS_HIDDEN) && defined(SUPPORTS_ONE_ONLY)
3775 # define USE_HIDDEN_LINKONCE 1
3777 # define USE_HIDDEN_LINKONCE 0
3780 static int pic_labels_used
;
3782 /* Fills in the label name that should be used for a pc thunk for
3783 the given register. */
3786 get_pc_thunk_name (char name
[32], unsigned int regno
)
3788 if (USE_HIDDEN_LINKONCE
)
3789 sprintf (name
, "__i686.get_pc_thunk.%s", reg_names
[regno
]);
3791 ASM_GENERATE_INTERNAL_LABEL (name
, "LPR", regno
);
3795 /* This function generates code for -fpic that loads %ebx with
3796 the return address of the caller and then returns. */
3799 ix86_file_end (void)
3804 for (regno
= 0; regno
< 8; ++regno
)
3808 if (! ((pic_labels_used
>> regno
) & 1))
3811 get_pc_thunk_name (name
, regno
);
3813 if (USE_HIDDEN_LINKONCE
)
3817 decl
= build_decl (FUNCTION_DECL
, get_identifier (name
),
3819 TREE_PUBLIC (decl
) = 1;
3820 TREE_STATIC (decl
) = 1;
3821 DECL_ONE_ONLY (decl
) = 1;
3823 (*targetm
.asm_out
.unique_section
) (decl
, 0);
3824 named_section (decl
, NULL
, 0);
3826 (*targetm
.asm_out
.globalize_label
) (asm_out_file
, name
);
3827 fputs ("\t.hidden\t", asm_out_file
);
3828 assemble_name (asm_out_file
, name
);
3829 fputc ('\n', asm_out_file
);
3830 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
3835 ASM_OUTPUT_LABEL (asm_out_file
, name
);
3838 xops
[0] = gen_rtx_REG (SImode
, regno
);
3839 xops
[1] = gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3840 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops
);
3841 output_asm_insn ("ret", xops
);
3844 if (NEED_INDICATE_EXEC_STACK
)
3845 file_end_indicate_exec_stack ();
3848 /* Emit code for the SET_GOT patterns. */
3851 output_set_got (rtx dest
)
3856 xops
[1] = gen_rtx_SYMBOL_REF (Pmode
, GOT_SYMBOL_NAME
);
3858 if (! TARGET_DEEP_BRANCH_PREDICTION
|| !flag_pic
)
3860 xops
[2] = gen_rtx_LABEL_REF (Pmode
, gen_label_rtx ());
3863 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops
);
3865 output_asm_insn ("call\t%a2", xops
);
3868 /* Output the "canonical" label name ("Lxx$pb") here too. This
3869 is what will be referred to by the Mach-O PIC subsystem. */
3870 ASM_OUTPUT_LABEL (asm_out_file
, machopic_function_base_name ());
3872 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
3873 CODE_LABEL_NUMBER (XEXP (xops
[2], 0)));
3876 output_asm_insn ("pop{l}\t%0", xops
);
3881 get_pc_thunk_name (name
, REGNO (dest
));
3882 pic_labels_used
|= 1 << REGNO (dest
);
3884 xops
[2] = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3885 xops
[2] = gen_rtx_MEM (QImode
, xops
[2]);
3886 output_asm_insn ("call\t%X2", xops
);
3889 if (!flag_pic
|| TARGET_DEEP_BRANCH_PREDICTION
)
3890 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops
);
3891 else if (!TARGET_MACHO
)
3892 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %a1+(.-%a2)}", xops
);
3897 /* Generate an "push" pattern for input ARG. */
3902 return gen_rtx_SET (VOIDmode
,
3904 gen_rtx_PRE_DEC (Pmode
,
3905 stack_pointer_rtx
)),
3909 /* Return >= 0 if there is an unused call-clobbered register available
3910 for the entire function. */
3913 ix86_select_alt_pic_regnum (void)
3915 if (current_function_is_leaf
&& !current_function_profile
)
3918 for (i
= 2; i
>= 0; --i
)
3919 if (!regs_ever_live
[i
])
3923 return INVALID_REGNUM
;
3926 /* Return 1 if we need to save REGNO. */
3928 ix86_save_reg (unsigned int regno
, int maybe_eh_return
)
3930 if (pic_offset_table_rtx
3931 && regno
== REAL_PIC_OFFSET_TABLE_REGNUM
3932 && (regs_ever_live
[REAL_PIC_OFFSET_TABLE_REGNUM
]
3933 || current_function_profile
3934 || current_function_calls_eh_return
3935 || current_function_uses_const_pool
))
3937 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM
)
3942 if (current_function_calls_eh_return
&& maybe_eh_return
)
3947 unsigned test
= EH_RETURN_DATA_REGNO (i
);
3948 if (test
== INVALID_REGNUM
)
3955 return (regs_ever_live
[regno
]
3956 && !call_used_regs
[regno
]
3957 && !fixed_regs
[regno
]
3958 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
));
3961 /* Return number of registers to be saved on the stack. */
3964 ix86_nsaved_regs (void)
3969 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
3970 if (ix86_save_reg (regno
, true))
3975 /* Return the offset between two registers, one to be eliminated, and the other
3976 its replacement, at the start of a routine. */
3979 ix86_initial_elimination_offset (int from
, int to
)
3981 struct ix86_frame frame
;
3982 ix86_compute_frame_layout (&frame
);
3984 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
3985 return frame
.hard_frame_pointer_offset
;
3986 else if (from
== FRAME_POINTER_REGNUM
3987 && to
== HARD_FRAME_POINTER_REGNUM
)
3988 return frame
.hard_frame_pointer_offset
- frame
.frame_pointer_offset
;
3991 if (to
!= STACK_POINTER_REGNUM
)
3993 else if (from
== ARG_POINTER_REGNUM
)
3994 return frame
.stack_pointer_offset
;
3995 else if (from
!= FRAME_POINTER_REGNUM
)
3998 return frame
.stack_pointer_offset
- frame
.frame_pointer_offset
;
4002 /* Fill structure ix86_frame about frame of currently computed function. */
4005 ix86_compute_frame_layout (struct ix86_frame
*frame
)
4007 HOST_WIDE_INT total_size
;
4008 unsigned int stack_alignment_needed
;
4009 HOST_WIDE_INT offset
;
4010 unsigned int preferred_alignment
;
4011 HOST_WIDE_INT size
= get_frame_size ();
4013 frame
->nregs
= ix86_nsaved_regs ();
4016 stack_alignment_needed
= cfun
->stack_alignment_needed
/ BITS_PER_UNIT
;
4017 preferred_alignment
= cfun
->preferred_stack_boundary
/ BITS_PER_UNIT
;
4019 /* During reload iteration the amount of registers saved can change.
4020 Recompute the value as needed. Do not recompute when amount of registers
4021 didn't change as reload does mutiple calls to the function and does not
4022 expect the decision to change within single iteration. */
4024 && cfun
->machine
->use_fast_prologue_epilogue_nregs
!= frame
->nregs
)
4026 int count
= frame
->nregs
;
4028 cfun
->machine
->use_fast_prologue_epilogue_nregs
= count
;
4029 /* The fast prologue uses move instead of push to save registers. This
4030 is significantly longer, but also executes faster as modern hardware
4031 can execute the moves in parallel, but can't do that for push/pop.
4033 Be careful about choosing what prologue to emit: When function takes
4034 many instructions to execute we may use slow version as well as in
4035 case function is known to be outside hot spot (this is known with
4036 feedback only). Weight the size of function by number of registers
4037 to save as it is cheap to use one or two push instructions but very
4038 slow to use many of them. */
4040 count
= (count
- 1) * FAST_PROLOGUE_INSN_COUNT
;
4041 if (cfun
->function_frequency
< FUNCTION_FREQUENCY_NORMAL
4042 || (flag_branch_probabilities
4043 && cfun
->function_frequency
< FUNCTION_FREQUENCY_HOT
))
4044 cfun
->machine
->use_fast_prologue_epilogue
= false;
4046 cfun
->machine
->use_fast_prologue_epilogue
4047 = !expensive_function_p (count
);
4049 if (TARGET_PROLOGUE_USING_MOVE
4050 && cfun
->machine
->use_fast_prologue_epilogue
)
4051 frame
->save_regs_using_mov
= true;
4053 frame
->save_regs_using_mov
= false;
4056 /* Skip return address and saved base pointer. */
4057 offset
= frame_pointer_needed
? UNITS_PER_WORD
* 2 : UNITS_PER_WORD
;
4059 frame
->hard_frame_pointer_offset
= offset
;
4061 /* Do some sanity checking of stack_alignment_needed and
4062 preferred_alignment, since i386 port is the only using those features
4063 that may break easily. */
4065 if (size
&& !stack_alignment_needed
)
4067 if (preferred_alignment
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
4069 if (preferred_alignment
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
4071 if (stack_alignment_needed
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
4074 if (stack_alignment_needed
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
4075 stack_alignment_needed
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4077 /* Register save area */
4078 offset
+= frame
->nregs
* UNITS_PER_WORD
;
4081 if (ix86_save_varrargs_registers
)
4083 offset
+= X86_64_VARARGS_SIZE
;
4084 frame
->va_arg_size
= X86_64_VARARGS_SIZE
;
4087 frame
->va_arg_size
= 0;
4089 /* Align start of frame for local function. */
4090 frame
->padding1
= ((offset
+ stack_alignment_needed
- 1)
4091 & -stack_alignment_needed
) - offset
;
4093 offset
+= frame
->padding1
;
4095 /* Frame pointer points here. */
4096 frame
->frame_pointer_offset
= offset
;
4100 /* Add outgoing arguments area. Can be skipped if we eliminated
4101 all the function calls as dead code.
4102 Skipping is however impossible when function calls alloca. Alloca
4103 expander assumes that last current_function_outgoing_args_size
4104 of stack frame are unused. */
4105 if (ACCUMULATE_OUTGOING_ARGS
4106 && (!current_function_is_leaf
|| current_function_calls_alloca
))
4108 offset
+= current_function_outgoing_args_size
;
4109 frame
->outgoing_arguments_size
= current_function_outgoing_args_size
;
4112 frame
->outgoing_arguments_size
= 0;
4114 /* Align stack boundary. Only needed if we're calling another function
4116 if (!current_function_is_leaf
|| current_function_calls_alloca
)
4117 frame
->padding2
= ((offset
+ preferred_alignment
- 1)
4118 & -preferred_alignment
) - offset
;
4120 frame
->padding2
= 0;
4122 offset
+= frame
->padding2
;
4124 /* We've reached end of stack frame. */
4125 frame
->stack_pointer_offset
= offset
;
4127 /* Size prologue needs to allocate. */
4128 frame
->to_allocate
=
4129 (size
+ frame
->padding1
+ frame
->padding2
4130 + frame
->outgoing_arguments_size
+ frame
->va_arg_size
);
4132 if ((!frame
->to_allocate
&& frame
->nregs
<= 1)
4133 || (TARGET_64BIT
&& frame
->to_allocate
>= (HOST_WIDE_INT
) 0x80000000))
4134 frame
->save_regs_using_mov
= false;
4136 if (TARGET_RED_ZONE
&& current_function_sp_is_unchanging
4137 && current_function_is_leaf
)
4139 frame
->red_zone_size
= frame
->to_allocate
;
4140 if (frame
->save_regs_using_mov
)
4141 frame
->red_zone_size
+= frame
->nregs
* UNITS_PER_WORD
;
4142 if (frame
->red_zone_size
> RED_ZONE_SIZE
- RED_ZONE_RESERVE
)
4143 frame
->red_zone_size
= RED_ZONE_SIZE
- RED_ZONE_RESERVE
;
4146 frame
->red_zone_size
= 0;
4147 frame
->to_allocate
-= frame
->red_zone_size
;
4148 frame
->stack_pointer_offset
-= frame
->red_zone_size
;
4150 fprintf (stderr
, "nregs: %i\n", frame
->nregs
);
4151 fprintf (stderr
, "size: %i\n", size
);
4152 fprintf (stderr
, "alignment1: %i\n", stack_alignment_needed
);
4153 fprintf (stderr
, "padding1: %i\n", frame
->padding1
);
4154 fprintf (stderr
, "va_arg: %i\n", frame
->va_arg_size
);
4155 fprintf (stderr
, "padding2: %i\n", frame
->padding2
);
4156 fprintf (stderr
, "to_allocate: %i\n", frame
->to_allocate
);
4157 fprintf (stderr
, "red_zone_size: %i\n", frame
->red_zone_size
);
4158 fprintf (stderr
, "frame_pointer_offset: %i\n", frame
->frame_pointer_offset
);
4159 fprintf (stderr
, "hard_frame_pointer_offset: %i\n",
4160 frame
->hard_frame_pointer_offset
);
4161 fprintf (stderr
, "stack_pointer_offset: %i\n", frame
->stack_pointer_offset
);
4165 /* Emit code to save registers in the prologue. */
4168 ix86_emit_save_regs (void)
4173 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
4174 if (ix86_save_reg (regno
, true))
4176 insn
= emit_insn (gen_push (gen_rtx_REG (Pmode
, regno
)));
4177 RTX_FRAME_RELATED_P (insn
) = 1;
4181 /* Emit code to save registers using MOV insns. First register
4182 is restored from POINTER + OFFSET. */
4184 ix86_emit_save_regs_using_mov (rtx pointer
, HOST_WIDE_INT offset
)
4189 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4190 if (ix86_save_reg (regno
, true))
4192 insn
= emit_move_insn (adjust_address (gen_rtx_MEM (Pmode
, pointer
),
4194 gen_rtx_REG (Pmode
, regno
));
4195 RTX_FRAME_RELATED_P (insn
) = 1;
4196 offset
+= UNITS_PER_WORD
;
4200 /* Expand prologue or epilogue stack adjustment.
4201 The pattern exist to put a dependency on all ebp-based memory accesses.
4202 STYLE should be negative if instructions should be marked as frame related,
4203 zero if %r11 register is live and cannot be freely used and positive
4207 pro_epilogue_adjust_stack (rtx dest
, rtx src
, rtx offset
, int style
)
4212 insn
= emit_insn (gen_pro_epilogue_adjust_stack_1 (dest
, src
, offset
));
4213 else if (x86_64_immediate_operand (offset
, DImode
))
4214 insn
= emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest
, src
, offset
));
4218 /* r11 is used by indirect sibcall return as well, set before the
4219 epilogue and used after the epilogue. ATM indirect sibcall
4220 shouldn't be used together with huge frame sizes in one
4221 function because of the frame_size check in sibcall.c. */
4224 r11
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
4225 insn
= emit_insn (gen_rtx_SET (DImode
, r11
, offset
));
4227 RTX_FRAME_RELATED_P (insn
) = 1;
4228 insn
= emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest
, src
, r11
,
4232 RTX_FRAME_RELATED_P (insn
) = 1;
4235 /* Expand the prologue into a bunch of separate insns. */
4238 ix86_expand_prologue (void)
4242 struct ix86_frame frame
;
4243 HOST_WIDE_INT allocate
;
4245 ix86_compute_frame_layout (&frame
);
4247 /* Note: AT&T enter does NOT have reversed args. Enter is probably
4248 slower on all targets. Also sdb doesn't like it. */
4250 if (frame_pointer_needed
)
4252 insn
= emit_insn (gen_push (hard_frame_pointer_rtx
));
4253 RTX_FRAME_RELATED_P (insn
) = 1;
4255 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
4256 RTX_FRAME_RELATED_P (insn
) = 1;
4259 allocate
= frame
.to_allocate
;
4261 if (!frame
.save_regs_using_mov
)
4262 ix86_emit_save_regs ();
4264 allocate
+= frame
.nregs
* UNITS_PER_WORD
;
4266 /* When using red zone we may start register saving before allocating
4267 the stack frame saving one cycle of the prologue. */
4268 if (TARGET_RED_ZONE
&& frame
.save_regs_using_mov
)
4269 ix86_emit_save_regs_using_mov (frame_pointer_needed
? hard_frame_pointer_rtx
4270 : stack_pointer_rtx
,
4271 -frame
.nregs
* UNITS_PER_WORD
);
4275 else if (! TARGET_STACK_PROBE
|| allocate
< CHECK_STACK_LIMIT
)
4276 pro_epilogue_adjust_stack (stack_pointer_rtx
, stack_pointer_rtx
,
4277 GEN_INT (-allocate
), -1);
4280 /* Only valid for Win32. */
4281 rtx eax
= gen_rtx_REG (SImode
, 0);
4282 bool eax_live
= ix86_eax_live_at_start_p ();
4289 emit_insn (gen_push (eax
));
4293 insn
= emit_move_insn (eax
, GEN_INT (allocate
));
4294 RTX_FRAME_RELATED_P (insn
) = 1;
4296 insn
= emit_insn (gen_allocate_stack_worker (eax
));
4297 RTX_FRAME_RELATED_P (insn
) = 1;
4302 if (frame_pointer_needed
)
4303 t
= plus_constant (hard_frame_pointer_rtx
,
4306 - frame
.nregs
* UNITS_PER_WORD
);
4308 t
= plus_constant (stack_pointer_rtx
, allocate
);
4309 emit_move_insn (eax
, gen_rtx_MEM (SImode
, t
));
4313 if (frame
.save_regs_using_mov
&& !TARGET_RED_ZONE
)
4315 if (!frame_pointer_needed
|| !frame
.to_allocate
)
4316 ix86_emit_save_regs_using_mov (stack_pointer_rtx
, frame
.to_allocate
);
4318 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx
,
4319 -frame
.nregs
* UNITS_PER_WORD
);
4322 pic_reg_used
= false;
4323 if (pic_offset_table_rtx
4324 && (regs_ever_live
[REAL_PIC_OFFSET_TABLE_REGNUM
]
4325 || current_function_profile
))
4327 unsigned int alt_pic_reg_used
= ix86_select_alt_pic_regnum ();
4329 if (alt_pic_reg_used
!= INVALID_REGNUM
)
4330 REGNO (pic_offset_table_rtx
) = alt_pic_reg_used
;
4332 pic_reg_used
= true;
4337 insn
= emit_insn (gen_set_got (pic_offset_table_rtx
));
4339 /* Even with accurate pre-reload life analysis, we can wind up
4340 deleting all references to the pic register after reload.
4341 Consider if cross-jumping unifies two sides of a branch
4342 controlled by a comparison vs the only read from a global.
4343 In which case, allow the set_got to be deleted, though we're
4344 too late to do anything about the ebx save in the prologue. */
4345 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, NULL
);
4348 /* Prevent function calls from be scheduled before the call to mcount.
4349 In the pic_reg_used case, make sure that the got load isn't deleted. */
4350 if (current_function_profile
)
4351 emit_insn (gen_blockage (pic_reg_used
? pic_offset_table_rtx
: const0_rtx
));
4354 /* Emit code to restore saved registers using MOV insns. First register
4355 is restored from POINTER + OFFSET. */
4357 ix86_emit_restore_regs_using_mov (rtx pointer
, HOST_WIDE_INT offset
,
4358 int maybe_eh_return
)
4361 rtx base_address
= gen_rtx_MEM (Pmode
, pointer
);
4363 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4364 if (ix86_save_reg (regno
, maybe_eh_return
))
4366 /* Ensure that adjust_address won't be forced to produce pointer
4367 out of range allowed by x86-64 instruction set. */
4368 if (TARGET_64BIT
&& offset
!= trunc_int_for_mode (offset
, SImode
))
4372 r11
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
4373 emit_move_insn (r11
, GEN_INT (offset
));
4374 emit_insn (gen_adddi3 (r11
, r11
, pointer
));
4375 base_address
= gen_rtx_MEM (Pmode
, r11
);
4378 emit_move_insn (gen_rtx_REG (Pmode
, regno
),
4379 adjust_address (base_address
, Pmode
, offset
));
4380 offset
+= UNITS_PER_WORD
;
4384 /* Restore function stack, frame, and registers. */
4387 ix86_expand_epilogue (int style
)
4390 int sp_valid
= !frame_pointer_needed
|| current_function_sp_is_unchanging
;
4391 struct ix86_frame frame
;
4392 HOST_WIDE_INT offset
;
4394 ix86_compute_frame_layout (&frame
);
4396 /* Calculate start of saved registers relative to ebp. Special care
4397 must be taken for the normal return case of a function using
4398 eh_return: the eax and edx registers are marked as saved, but not
4399 restored along this path. */
4400 offset
= frame
.nregs
;
4401 if (current_function_calls_eh_return
&& style
!= 2)
4403 offset
*= -UNITS_PER_WORD
;
4405 /* If we're only restoring one register and sp is not valid then
4406 using a move instruction to restore the register since it's
4407 less work than reloading sp and popping the register.
4409 The default code result in stack adjustment using add/lea instruction,
4410 while this code results in LEAVE instruction (or discrete equivalent),
4411 so it is profitable in some other cases as well. Especially when there
4412 are no registers to restore. We also use this code when TARGET_USE_LEAVE
4413 and there is exactly one register to pop. This heuristic may need some
4414 tuning in future. */
4415 if ((!sp_valid
&& frame
.nregs
<= 1)
4416 || (TARGET_EPILOGUE_USING_MOVE
4417 && cfun
->machine
->use_fast_prologue_epilogue
4418 && (frame
.nregs
> 1 || frame
.to_allocate
))
4419 || (frame_pointer_needed
&& !frame
.nregs
&& frame
.to_allocate
)
4420 || (frame_pointer_needed
&& TARGET_USE_LEAVE
4421 && cfun
->machine
->use_fast_prologue_epilogue
4422 && frame
.nregs
== 1)
4423 || current_function_calls_eh_return
)
4425 /* Restore registers. We can use ebp or esp to address the memory
4426 locations. If both are available, default to ebp, since offsets
4427 are known to be small. Only exception is esp pointing directly to the
4428 end of block of saved registers, where we may simplify addressing
4431 if (!frame_pointer_needed
|| (sp_valid
&& !frame
.to_allocate
))
4432 ix86_emit_restore_regs_using_mov (stack_pointer_rtx
,
4433 frame
.to_allocate
, style
== 2);
4435 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx
,
4436 offset
, style
== 2);
4438 /* eh_return epilogues need %ecx added to the stack pointer. */
4441 rtx tmp
, sa
= EH_RETURN_STACKADJ_RTX
;
4443 if (frame_pointer_needed
)
4445 tmp
= gen_rtx_PLUS (Pmode
, hard_frame_pointer_rtx
, sa
);
4446 tmp
= plus_constant (tmp
, UNITS_PER_WORD
);
4447 emit_insn (gen_rtx_SET (VOIDmode
, sa
, tmp
));
4449 tmp
= gen_rtx_MEM (Pmode
, hard_frame_pointer_rtx
);
4450 emit_move_insn (hard_frame_pointer_rtx
, tmp
);
4452 pro_epilogue_adjust_stack (stack_pointer_rtx
, sa
,
4457 tmp
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, sa
);
4458 tmp
= plus_constant (tmp
, (frame
.to_allocate
4459 + frame
.nregs
* UNITS_PER_WORD
));
4460 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, tmp
));
4463 else if (!frame_pointer_needed
)
4464 pro_epilogue_adjust_stack (stack_pointer_rtx
, stack_pointer_rtx
,
4465 GEN_INT (frame
.to_allocate
4466 + frame
.nregs
* UNITS_PER_WORD
),
4468 /* If not an i386, mov & pop is faster than "leave". */
4469 else if (TARGET_USE_LEAVE
|| optimize_size
4470 || !cfun
->machine
->use_fast_prologue_epilogue
)
4471 emit_insn (TARGET_64BIT
? gen_leave_rex64 () : gen_leave ());
4474 pro_epilogue_adjust_stack (stack_pointer_rtx
,
4475 hard_frame_pointer_rtx
,
4478 emit_insn (gen_popdi1 (hard_frame_pointer_rtx
));
4480 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
4485 /* First step is to deallocate the stack frame so that we can
4486 pop the registers. */
4489 if (!frame_pointer_needed
)
4491 pro_epilogue_adjust_stack (stack_pointer_rtx
,
4492 hard_frame_pointer_rtx
,
4493 GEN_INT (offset
), style
);
4495 else if (frame
.to_allocate
)
4496 pro_epilogue_adjust_stack (stack_pointer_rtx
, stack_pointer_rtx
,
4497 GEN_INT (frame
.to_allocate
), style
);
4499 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4500 if (ix86_save_reg (regno
, false))
4503 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode
, regno
)));
4505 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode
, regno
)));
4507 if (frame_pointer_needed
)
4509 /* Leave results in shorter dependency chains on CPUs that are
4510 able to grok it fast. */
4511 if (TARGET_USE_LEAVE
)
4512 emit_insn (TARGET_64BIT
? gen_leave_rex64 () : gen_leave ());
4513 else if (TARGET_64BIT
)
4514 emit_insn (gen_popdi1 (hard_frame_pointer_rtx
));
4516 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
4520 /* Sibcall epilogues don't want a return instruction. */
4524 if (current_function_pops_args
&& current_function_args_size
)
4526 rtx popc
= GEN_INT (current_function_pops_args
);
4528 /* i386 can only pop 64K bytes. If asked to pop more, pop
4529 return address, do explicit add, and jump indirectly to the
4532 if (current_function_pops_args
>= 65536)
4534 rtx ecx
= gen_rtx_REG (SImode
, 2);
4536 /* There is no "pascal" calling convention in 64bit ABI. */
4540 emit_insn (gen_popsi1 (ecx
));
4541 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, popc
));
4542 emit_jump_insn (gen_return_indirect_internal (ecx
));
4545 emit_jump_insn (gen_return_pop_internal (popc
));
4548 emit_jump_insn (gen_return_internal ());
4551 /* Reset from the function's potential modifications. */
4554 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
4555 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4557 if (pic_offset_table_rtx
)
4558 REGNO (pic_offset_table_rtx
) = REAL_PIC_OFFSET_TABLE_REGNUM
;
4561 /* Extract the parts of an RTL expression that is a valid memory address
4562 for an instruction. Return 0 if the structure of the address is
4563 grossly off. Return -1 if the address contains ASHIFT, so it is not
4564 strictly valid, but still used for computing length of lea instruction. */
4567 ix86_decompose_address (rtx addr
, struct ix86_address
*out
)
4569 rtx base
= NULL_RTX
;
4570 rtx index
= NULL_RTX
;
4571 rtx disp
= NULL_RTX
;
4572 HOST_WIDE_INT scale
= 1;
4573 rtx scale_rtx
= NULL_RTX
;
4575 enum ix86_address_seg seg
= SEG_DEFAULT
;
4577 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == SUBREG
)
4579 else if (GET_CODE (addr
) == PLUS
)
4589 addends
[n
++] = XEXP (op
, 1);
4592 while (GET_CODE (op
) == PLUS
);
4597 for (i
= n
; i
>= 0; --i
)
4600 switch (GET_CODE (op
))
4605 index
= XEXP (op
, 0);
4606 scale_rtx
= XEXP (op
, 1);
4610 if (XINT (op
, 1) == UNSPEC_TP
4611 && TARGET_TLS_DIRECT_SEG_REFS
4612 && seg
== SEG_DEFAULT
)
4613 seg
= TARGET_64BIT
? SEG_FS
: SEG_GS
;
4642 else if (GET_CODE (addr
) == MULT
)
4644 index
= XEXP (addr
, 0); /* index*scale */
4645 scale_rtx
= XEXP (addr
, 1);
4647 else if (GET_CODE (addr
) == ASHIFT
)
4651 /* We're called for lea too, which implements ashift on occasion. */
4652 index
= XEXP (addr
, 0);
4653 tmp
= XEXP (addr
, 1);
4654 if (GET_CODE (tmp
) != CONST_INT
)
4656 scale
= INTVAL (tmp
);
4657 if ((unsigned HOST_WIDE_INT
) scale
> 3)
4663 disp
= addr
; /* displacement */
4665 /* Extract the integral value of scale. */
4668 if (GET_CODE (scale_rtx
) != CONST_INT
)
4670 scale
= INTVAL (scale_rtx
);
4673 /* Allow arg pointer and stack pointer as index if there is not scaling. */
4674 if (base
&& index
&& scale
== 1
4675 && (index
== arg_pointer_rtx
4676 || index
== frame_pointer_rtx
4677 || (REG_P (index
) && REGNO (index
) == STACK_POINTER_REGNUM
)))
4684 /* Special case: %ebp cannot be encoded as a base without a displacement. */
4685 if ((base
== hard_frame_pointer_rtx
4686 || base
== frame_pointer_rtx
4687 || base
== arg_pointer_rtx
) && !disp
)
4690 /* Special case: on K6, [%esi] makes the instruction vector decoded.
4691 Avoid this by transforming to [%esi+0]. */
4692 if (ix86_tune
== PROCESSOR_K6
&& !optimize_size
4693 && base
&& !index
&& !disp
4695 && REGNO_REG_CLASS (REGNO (base
)) == SIREG
)
4698 /* Special case: encode reg+reg instead of reg*2. */
4699 if (!base
&& index
&& scale
&& scale
== 2)
4700 base
= index
, scale
= 1;
4702 /* Special case: scaling cannot be encoded without base or displacement. */
4703 if (!base
&& !disp
&& index
&& scale
!= 1)
4715 /* Return cost of the memory address x.
4716 For i386, it is better to use a complex address than let gcc copy
4717 the address into a reg and make a new pseudo. But not if the address
4718 requires to two regs - that would mean more pseudos with longer
4721 ix86_address_cost (rtx x
)
4723 struct ix86_address parts
;
4726 if (!ix86_decompose_address (x
, &parts
))
4729 /* More complex memory references are better. */
4730 if (parts
.disp
&& parts
.disp
!= const0_rtx
)
4732 if (parts
.seg
!= SEG_DEFAULT
)
4735 /* Attempt to minimize number of registers in the address. */
4737 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
))
4739 && (!REG_P (parts
.index
)
4740 || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)))
4744 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
)
4746 && (!REG_P (parts
.index
) || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)
4747 && parts
.base
!= parts
.index
)
4750 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
4751 since it's predecode logic can't detect the length of instructions
4752 and it degenerates to vector decoded. Increase cost of such
4753 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
4754 to split such addresses or even refuse such addresses at all.
4756 Following addressing modes are affected:
4761 The first and last case may be avoidable by explicitly coding the zero in
4762 memory address, but I don't have AMD-K6 machine handy to check this
4766 && ((!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
!= 1)
4767 || (parts
.disp
&& !parts
.base
&& parts
.index
&& parts
.scale
!= 1)
4768 || (!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
== 1)))
4774 /* If X is a machine specific address (i.e. a symbol or label being
4775 referenced as a displacement from the GOT implemented using an
4776 UNSPEC), then return the base term. Otherwise return X. */
4779 ix86_find_base_term (rtx x
)
4785 if (GET_CODE (x
) != CONST
)
4788 if (GET_CODE (term
) == PLUS
4789 && (GET_CODE (XEXP (term
, 1)) == CONST_INT
4790 || GET_CODE (XEXP (term
, 1)) == CONST_DOUBLE
))
4791 term
= XEXP (term
, 0);
4792 if (GET_CODE (term
) != UNSPEC
4793 || XINT (term
, 1) != UNSPEC_GOTPCREL
)
4796 term
= XVECEXP (term
, 0, 0);
4798 if (GET_CODE (term
) != SYMBOL_REF
4799 && GET_CODE (term
) != LABEL_REF
)
4805 term
= ix86_delegitimize_address (x
);
4807 if (GET_CODE (term
) != SYMBOL_REF
4808 && GET_CODE (term
) != LABEL_REF
)
4814 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
4815 this is used for to form addresses to local data when -fPIC is in
4819 darwin_local_data_pic (rtx disp
)
4821 if (GET_CODE (disp
) == MINUS
)
4823 if (GET_CODE (XEXP (disp
, 0)) == LABEL_REF
4824 || GET_CODE (XEXP (disp
, 0)) == SYMBOL_REF
)
4825 if (GET_CODE (XEXP (disp
, 1)) == SYMBOL_REF
)
4827 const char *sym_name
= XSTR (XEXP (disp
, 1), 0);
4828 if (! strcmp (sym_name
, "<pic base>"))
4836 /* Determine if a given RTX is a valid constant. We already know this
4837 satisfies CONSTANT_P. */
4840 legitimate_constant_p (rtx x
)
4842 switch (GET_CODE (x
))
4847 if (GET_CODE (x
) == PLUS
)
4849 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4854 if (TARGET_MACHO
&& darwin_local_data_pic (x
))
4857 /* Only some unspecs are valid as "constants". */
4858 if (GET_CODE (x
) == UNSPEC
)
4859 switch (XINT (x
, 1))
4863 return local_exec_symbolic_operand (XVECEXP (x
, 0, 0), Pmode
);
4865 return local_dynamic_symbolic_operand (XVECEXP (x
, 0, 0), Pmode
);
4870 /* We must have drilled down to a symbol. */
4871 if (!symbolic_operand (x
, Pmode
))
4876 /* TLS symbols are never valid. */
4877 if (tls_symbolic_operand (x
, Pmode
))
4885 /* Otherwise we handle everything else in the move patterns. */
4889 /* Determine if it's legal to put X into the constant pool. This
4890 is not possible for the address of thread-local symbols, which
4891 is checked above. */
4894 ix86_cannot_force_const_mem (rtx x
)
4896 return !legitimate_constant_p (x
);
4899 /* Determine if a given RTX is a valid constant address. */
4902 constant_address_p (rtx x
)
4904 return CONSTANT_P (x
) && legitimate_address_p (Pmode
, x
, 1);
4907 /* Nonzero if the constant value X is a legitimate general operand
4908 when generating PIC code. It is given that flag_pic is on and
4909 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
4912 legitimate_pic_operand_p (rtx x
)
4916 switch (GET_CODE (x
))
4919 inner
= XEXP (x
, 0);
4921 /* Only some unspecs are valid as "constants". */
4922 if (GET_CODE (inner
) == UNSPEC
)
4923 switch (XINT (inner
, 1))
4926 return local_exec_symbolic_operand (XVECEXP (inner
, 0, 0), Pmode
);
4934 return legitimate_pic_address_disp_p (x
);
4941 /* Determine if a given CONST RTX is a valid memory displacement
4945 legitimate_pic_address_disp_p (rtx disp
)
4949 /* In 64bit mode we can allow direct addresses of symbols and labels
4950 when they are not dynamic symbols. */
4953 /* TLS references should always be enclosed in UNSPEC. */
4954 if (tls_symbolic_operand (disp
, GET_MODE (disp
)))
4956 if (GET_CODE (disp
) == SYMBOL_REF
4957 && ix86_cmodel
== CM_SMALL_PIC
4958 && SYMBOL_REF_LOCAL_P (disp
))
4960 if (GET_CODE (disp
) == LABEL_REF
)
4962 if (GET_CODE (disp
) == CONST
4963 && GET_CODE (XEXP (disp
, 0)) == PLUS
)
4965 rtx op0
= XEXP (XEXP (disp
, 0), 0);
4966 rtx op1
= XEXP (XEXP (disp
, 0), 1);
4968 /* TLS references should always be enclosed in UNSPEC. */
4969 if (tls_symbolic_operand (op0
, GET_MODE (op0
)))
4971 if (((GET_CODE (op0
) == SYMBOL_REF
4972 && ix86_cmodel
== CM_SMALL_PIC
4973 && SYMBOL_REF_LOCAL_P (op0
))
4974 || GET_CODE (op0
) == LABEL_REF
)
4975 && GET_CODE (op1
) == CONST_INT
4976 && INTVAL (op1
) < 16*1024*1024
4977 && INTVAL (op1
) >= -16*1024*1024)
4981 if (GET_CODE (disp
) != CONST
)
4983 disp
= XEXP (disp
, 0);
4987 /* We are unsafe to allow PLUS expressions. This limit allowed distance
4988 of GOT tables. We should not need these anyway. */
4989 if (GET_CODE (disp
) != UNSPEC
4990 || XINT (disp
, 1) != UNSPEC_GOTPCREL
)
4993 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
4994 && GET_CODE (XVECEXP (disp
, 0, 0)) != LABEL_REF
)
5000 if (GET_CODE (disp
) == PLUS
)
5002 if (GET_CODE (XEXP (disp
, 1)) != CONST_INT
)
5004 disp
= XEXP (disp
, 0);
5008 if (TARGET_MACHO
&& darwin_local_data_pic (disp
))
5011 if (GET_CODE (disp
) != UNSPEC
)
5014 switch (XINT (disp
, 1))
5019 return GET_CODE (XVECEXP (disp
, 0, 0)) == SYMBOL_REF
;
5021 if (GET_CODE (XVECEXP (disp
, 0, 0)) == SYMBOL_REF
5022 || GET_CODE (XVECEXP (disp
, 0, 0)) == LABEL_REF
)
5023 return local_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5025 case UNSPEC_GOTTPOFF
:
5026 case UNSPEC_GOTNTPOFF
:
5027 case UNSPEC_INDNTPOFF
:
5030 return initial_exec_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5032 return local_exec_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5034 return local_dynamic_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5040 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
5041 memory address for an instruction. The MODE argument is the machine mode
5042 for the MEM expression that wants to use this address.
5044 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
5045 convert common non-canonical forms to canonical form so that they will
5049 legitimate_address_p (enum machine_mode mode
, rtx addr
, int strict
)
5051 struct ix86_address parts
;
5052 rtx base
, index
, disp
;
5053 HOST_WIDE_INT scale
;
5054 const char *reason
= NULL
;
5055 rtx reason_rtx
= NULL_RTX
;
5057 if (TARGET_DEBUG_ADDR
)
5060 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
5061 GET_MODE_NAME (mode
), strict
);
5065 if (ix86_decompose_address (addr
, &parts
) <= 0)
5067 reason
= "decomposition failed";
5072 index
= parts
.index
;
5074 scale
= parts
.scale
;
5076 /* Validate base register.
5078 Don't allow SUBREG's here, it can lead to spill failures when the base
5079 is one word out of a two word structure, which is represented internally
5086 if (GET_CODE (base
) != REG
)
5088 reason
= "base is not a register";
5092 if (GET_MODE (base
) != Pmode
)
5094 reason
= "base is not in Pmode";
5098 if ((strict
&& ! REG_OK_FOR_BASE_STRICT_P (base
))
5099 || (! strict
&& ! REG_OK_FOR_BASE_NONSTRICT_P (base
)))
5101 reason
= "base is not valid";
5106 /* Validate index register.
5108 Don't allow SUBREG's here, it can lead to spill failures when the index
5109 is one word out of a two word structure, which is represented internally
5116 if (GET_CODE (index
) != REG
)
5118 reason
= "index is not a register";
5122 if (GET_MODE (index
) != Pmode
)
5124 reason
= "index is not in Pmode";
5128 if ((strict
&& ! REG_OK_FOR_INDEX_STRICT_P (index
))
5129 || (! strict
&& ! REG_OK_FOR_INDEX_NONSTRICT_P (index
)))
5131 reason
= "index is not valid";
5136 /* Validate scale factor. */
5139 reason_rtx
= GEN_INT (scale
);
5142 reason
= "scale without index";
5146 if (scale
!= 2 && scale
!= 4 && scale
!= 8)
5148 reason
= "scale is not a valid multiplier";
5153 /* Validate displacement. */
5158 if (GET_CODE (disp
) == CONST
5159 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
)
5160 switch (XINT (XEXP (disp
, 0), 1))
5164 case UNSPEC_GOTPCREL
:
5167 goto is_legitimate_pic
;
5169 case UNSPEC_GOTTPOFF
:
5170 case UNSPEC_GOTNTPOFF
:
5171 case UNSPEC_INDNTPOFF
:
5177 reason
= "invalid address unspec";
5181 else if (flag_pic
&& (SYMBOLIC_CONST (disp
)
5183 && !machopic_operand_p (disp
)
5188 if (TARGET_64BIT
&& (index
|| base
))
5190 /* foo@dtpoff(%rX) is ok. */
5191 if (GET_CODE (disp
) != CONST
5192 || GET_CODE (XEXP (disp
, 0)) != PLUS
5193 || GET_CODE (XEXP (XEXP (disp
, 0), 0)) != UNSPEC
5194 || GET_CODE (XEXP (XEXP (disp
, 0), 1)) != CONST_INT
5195 || (XINT (XEXP (XEXP (disp
, 0), 0), 1) != UNSPEC_DTPOFF
5196 && XINT (XEXP (XEXP (disp
, 0), 0), 1) != UNSPEC_NTPOFF
))
5198 reason
= "non-constant pic memory reference";
5202 else if (! legitimate_pic_address_disp_p (disp
))
5204 reason
= "displacement is an invalid pic construct";
5208 /* This code used to verify that a symbolic pic displacement
5209 includes the pic_offset_table_rtx register.
5211 While this is good idea, unfortunately these constructs may
5212 be created by "adds using lea" optimization for incorrect
5221 This code is nonsensical, but results in addressing
5222 GOT table with pic_offset_table_rtx base. We can't
5223 just refuse it easily, since it gets matched by
5224 "addsi3" pattern, that later gets split to lea in the
5225 case output register differs from input. While this
5226 can be handled by separate addsi pattern for this case
5227 that never results in lea, this seems to be easier and
5228 correct fix for crash to disable this test. */
5230 else if (GET_CODE (disp
) != LABEL_REF
5231 && GET_CODE (disp
) != CONST_INT
5232 && (GET_CODE (disp
) != CONST
5233 || !legitimate_constant_p (disp
))
5234 && (GET_CODE (disp
) != SYMBOL_REF
5235 || !legitimate_constant_p (disp
)))
5237 reason
= "displacement is not constant";
5240 else if (TARGET_64BIT
5241 && !x86_64_immediate_operand (disp
, VOIDmode
))
5243 reason
= "displacement is out of range";
5248 /* Everything looks valid. */
5249 if (TARGET_DEBUG_ADDR
)
5250 fprintf (stderr
, "Success.\n");
5254 if (TARGET_DEBUG_ADDR
)
5256 fprintf (stderr
, "Error: %s\n", reason
);
5257 debug_rtx (reason_rtx
);
5262 /* Return an unique alias set for the GOT. */
5264 static HOST_WIDE_INT
5265 ix86_GOT_alias_set (void)
5267 static HOST_WIDE_INT set
= -1;
5269 set
= new_alias_set ();
5273 /* Return a legitimate reference for ORIG (an address) using the
5274 register REG. If REG is 0, a new pseudo is generated.
5276 There are two types of references that must be handled:
5278 1. Global data references must load the address from the GOT, via
5279 the PIC reg. An insn is emitted to do this load, and the reg is
5282 2. Static data references, constant pool addresses, and code labels
5283 compute the address as an offset from the GOT, whose base is in
5284 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
5285 differentiate them from global data objects. The returned
5286 address is the PIC reg + an unspec constant.
5288 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
5289 reg also appears in the address. */
5292 legitimize_pic_address (rtx orig
, rtx reg
)
5300 reg
= gen_reg_rtx (Pmode
);
5301 /* Use the generic Mach-O PIC machinery. */
5302 return machopic_legitimize_pic_address (orig
, GET_MODE (orig
), reg
);
5305 if (TARGET_64BIT
&& legitimate_pic_address_disp_p (addr
))
5307 else if (!TARGET_64BIT
&& local_symbolic_operand (addr
, Pmode
))
5309 /* This symbol may be referenced via a displacement from the PIC
5310 base address (@GOTOFF). */
5312 if (reload_in_progress
)
5313 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5314 if (GET_CODE (addr
) == CONST
)
5315 addr
= XEXP (addr
, 0);
5316 if (GET_CODE (addr
) == PLUS
)
5318 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (addr
, 0)), UNSPEC_GOTOFF
);
5319 new = gen_rtx_PLUS (Pmode
, new, XEXP (addr
, 1));
5322 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
5323 new = gen_rtx_CONST (Pmode
, new);
5324 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5328 emit_move_insn (reg
, new);
5332 else if (GET_CODE (addr
) == SYMBOL_REF
)
5336 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTPCREL
);
5337 new = gen_rtx_CONST (Pmode
, new);
5338 new = gen_const_mem (Pmode
, new);
5339 set_mem_alias_set (new, ix86_GOT_alias_set ());
5342 reg
= gen_reg_rtx (Pmode
);
5343 /* Use directly gen_movsi, otherwise the address is loaded
5344 into register for CSE. We don't want to CSE this addresses,
5345 instead we CSE addresses from the GOT table, so skip this. */
5346 emit_insn (gen_movsi (reg
, new));
5351 /* This symbol must be referenced via a load from the
5352 Global Offset Table (@GOT). */
5354 if (reload_in_progress
)
5355 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5356 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
5357 new = gen_rtx_CONST (Pmode
, new);
5358 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5359 new = gen_const_mem (Pmode
, new);
5360 set_mem_alias_set (new, ix86_GOT_alias_set ());
5363 reg
= gen_reg_rtx (Pmode
);
5364 emit_move_insn (reg
, new);
5370 if (GET_CODE (addr
) == CONST
)
5372 addr
= XEXP (addr
, 0);
5374 /* We must match stuff we generate before. Assume the only
5375 unspecs that can get here are ours. Not that we could do
5376 anything with them anyway.... */
5377 if (GET_CODE (addr
) == UNSPEC
5378 || (GET_CODE (addr
) == PLUS
5379 && GET_CODE (XEXP (addr
, 0)) == UNSPEC
))
5381 if (GET_CODE (addr
) != PLUS
)
5384 if (GET_CODE (addr
) == PLUS
)
5386 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
5388 /* Check first to see if this is a constant offset from a @GOTOFF
5389 symbol reference. */
5390 if (local_symbolic_operand (op0
, Pmode
)
5391 && GET_CODE (op1
) == CONST_INT
)
5395 if (reload_in_progress
)
5396 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5397 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
5399 new = gen_rtx_PLUS (Pmode
, new, op1
);
5400 new = gen_rtx_CONST (Pmode
, new);
5401 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5405 emit_move_insn (reg
, new);
5411 if (INTVAL (op1
) < -16*1024*1024
5412 || INTVAL (op1
) >= 16*1024*1024)
5413 new = gen_rtx_PLUS (Pmode
, force_reg (Pmode
, op0
), op1
);
5418 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
5419 new = legitimize_pic_address (XEXP (addr
, 1),
5420 base
== reg
? NULL_RTX
: reg
);
5422 if (GET_CODE (new) == CONST_INT
)
5423 new = plus_constant (base
, INTVAL (new));
5426 if (GET_CODE (new) == PLUS
&& CONSTANT_P (XEXP (new, 1)))
5428 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new, 0));
5429 new = XEXP (new, 1);
5431 new = gen_rtx_PLUS (Pmode
, base
, new);
5439 /* Load the thread pointer. If TO_REG is true, force it into a register. */
5442 get_thread_pointer (int to_reg
)
5446 tp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TP
);
5450 reg
= gen_reg_rtx (Pmode
);
5451 insn
= gen_rtx_SET (VOIDmode
, reg
, tp
);
5452 insn
= emit_insn (insn
);
5457 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
5458 false if we expect this to be used for a memory address and true if
5459 we expect to load the address into a register. */
5462 legitimize_tls_address (rtx x
, enum tls_model model
, int for_mov
)
5464 rtx dest
, base
, off
, pic
;
5469 case TLS_MODEL_GLOBAL_DYNAMIC
:
5470 dest
= gen_reg_rtx (Pmode
);
5473 rtx rax
= gen_rtx_REG (Pmode
, 0), insns
;
5476 emit_call_insn (gen_tls_global_dynamic_64 (rax
, x
));
5477 insns
= get_insns ();
5480 emit_libcall_block (insns
, dest
, rax
, x
);
5483 emit_insn (gen_tls_global_dynamic_32 (dest
, x
));
5486 case TLS_MODEL_LOCAL_DYNAMIC
:
5487 base
= gen_reg_rtx (Pmode
);
5490 rtx rax
= gen_rtx_REG (Pmode
, 0), insns
, note
;
5493 emit_call_insn (gen_tls_local_dynamic_base_64 (rax
));
5494 insns
= get_insns ();
5497 note
= gen_rtx_EXPR_LIST (VOIDmode
, const0_rtx
, NULL
);
5498 note
= gen_rtx_EXPR_LIST (VOIDmode
, ix86_tls_get_addr (), note
);
5499 emit_libcall_block (insns
, base
, rax
, note
);
5502 emit_insn (gen_tls_local_dynamic_base_32 (base
));
5504 off
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPOFF
);
5505 off
= gen_rtx_CONST (Pmode
, off
);
5507 return gen_rtx_PLUS (Pmode
, base
, off
);
5509 case TLS_MODEL_INITIAL_EXEC
:
5513 type
= UNSPEC_GOTNTPOFF
;
5517 if (reload_in_progress
)
5518 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5519 pic
= pic_offset_table_rtx
;
5520 type
= TARGET_GNU_TLS
? UNSPEC_GOTNTPOFF
: UNSPEC_GOTTPOFF
;
5522 else if (!TARGET_GNU_TLS
)
5524 pic
= gen_reg_rtx (Pmode
);
5525 emit_insn (gen_set_got (pic
));
5526 type
= UNSPEC_GOTTPOFF
;
5531 type
= UNSPEC_INDNTPOFF
;
5534 off
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), type
);
5535 off
= gen_rtx_CONST (Pmode
, off
);
5537 off
= gen_rtx_PLUS (Pmode
, pic
, off
);
5538 off
= gen_const_mem (Pmode
, off
);
5539 set_mem_alias_set (off
, ix86_GOT_alias_set ());
5541 if (TARGET_64BIT
|| TARGET_GNU_TLS
)
5543 base
= get_thread_pointer (for_mov
|| !TARGET_TLS_DIRECT_SEG_REFS
);
5544 off
= force_reg (Pmode
, off
);
5545 return gen_rtx_PLUS (Pmode
, base
, off
);
5549 base
= get_thread_pointer (true);
5550 dest
= gen_reg_rtx (Pmode
);
5551 emit_insn (gen_subsi3 (dest
, base
, off
));
5555 case TLS_MODEL_LOCAL_EXEC
:
5556 off
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
),
5557 (TARGET_64BIT
|| TARGET_GNU_TLS
)
5558 ? UNSPEC_NTPOFF
: UNSPEC_TPOFF
);
5559 off
= gen_rtx_CONST (Pmode
, off
);
5561 if (TARGET_64BIT
|| TARGET_GNU_TLS
)
5563 base
= get_thread_pointer (for_mov
|| !TARGET_TLS_DIRECT_SEG_REFS
);
5564 return gen_rtx_PLUS (Pmode
, base
, off
);
5568 base
= get_thread_pointer (true);
5569 dest
= gen_reg_rtx (Pmode
);
5570 emit_insn (gen_subsi3 (dest
, base
, off
));
5581 /* Try machine-dependent ways of modifying an illegitimate address
5582 to be legitimate. If we find one, return the new, valid address.
5583 This macro is used in only one place: `memory_address' in explow.c.
5585 OLDX is the address as it was before break_out_memory_refs was called.
5586 In some cases it is useful to look at this to decide what needs to be done.
5588 MODE and WIN are passed so that this macro can use
5589 GO_IF_LEGITIMATE_ADDRESS.
5591 It is always safe for this macro to do nothing. It exists to recognize
5592 opportunities to optimize the output.
5594 For the 80386, we handle X+REG by loading X into a register R and
5595 using R+REG. R will go in a general reg and indexing will be used.
5596 However, if REG is a broken-out memory address or multiplication,
5597 nothing needs to be done because REG can certainly go in a general reg.
5599 When -fpic is used, special handling is needed for symbolic references.
5600 See comments by legitimize_pic_address in i386.c for details. */
5603 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5608 if (TARGET_DEBUG_ADDR
)
5610 fprintf (stderr
, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
5611 GET_MODE_NAME (mode
));
5615 log
= GET_CODE (x
) == SYMBOL_REF
? SYMBOL_REF_TLS_MODEL (x
) : 0;
5617 return legitimize_tls_address (x
, log
, false);
5618 if (GET_CODE (x
) == CONST
5619 && GET_CODE (XEXP (x
, 0)) == PLUS
5620 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5621 && (log
= SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0))))
5623 rtx t
= legitimize_tls_address (XEXP (XEXP (x
, 0), 0), log
, false);
5624 return gen_rtx_PLUS (Pmode
, t
, XEXP (XEXP (x
, 0), 1));
5627 if (flag_pic
&& SYMBOLIC_CONST (x
))
5628 return legitimize_pic_address (x
, 0);
5630 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
5631 if (GET_CODE (x
) == ASHIFT
5632 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5633 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (x
, 1)))) < 4)
5636 x
= gen_rtx_MULT (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
5637 GEN_INT (1 << log
));
5640 if (GET_CODE (x
) == PLUS
)
5642 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
5644 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
5645 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5646 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) < 4)
5649 XEXP (x
, 0) = gen_rtx_MULT (Pmode
,
5650 force_reg (Pmode
, XEXP (XEXP (x
, 0), 0)),
5651 GEN_INT (1 << log
));
5654 if (GET_CODE (XEXP (x
, 1)) == ASHIFT
5655 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5656 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1)))) < 4)
5659 XEXP (x
, 1) = gen_rtx_MULT (Pmode
,
5660 force_reg (Pmode
, XEXP (XEXP (x
, 1), 0)),
5661 GEN_INT (1 << log
));
5664 /* Put multiply first if it isn't already. */
5665 if (GET_CODE (XEXP (x
, 1)) == MULT
)
5667 rtx tmp
= XEXP (x
, 0);
5668 XEXP (x
, 0) = XEXP (x
, 1);
5673 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
5674 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
5675 created by virtual register instantiation, register elimination, and
5676 similar optimizations. */
5677 if (GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
5680 x
= gen_rtx_PLUS (Pmode
,
5681 gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5682 XEXP (XEXP (x
, 1), 0)),
5683 XEXP (XEXP (x
, 1), 1));
5687 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
5688 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
5689 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
5690 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
5691 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
5692 && CONSTANT_P (XEXP (x
, 1)))
5695 rtx other
= NULL_RTX
;
5697 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5699 constant
= XEXP (x
, 1);
5700 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5702 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
5704 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5705 other
= XEXP (x
, 1);
5713 x
= gen_rtx_PLUS (Pmode
,
5714 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
5715 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
5716 plus_constant (other
, INTVAL (constant
)));
5720 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
5723 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5726 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
5729 if (GET_CODE (XEXP (x
, 1)) == MULT
)
5732 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
5736 && GET_CODE (XEXP (x
, 1)) == REG
5737 && GET_CODE (XEXP (x
, 0)) == REG
)
5740 if (flag_pic
&& SYMBOLIC_CONST (XEXP (x
, 1)))
5743 x
= legitimize_pic_address (x
, 0);
5746 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
5749 if (GET_CODE (XEXP (x
, 0)) == REG
)
5751 rtx temp
= gen_reg_rtx (Pmode
);
5752 rtx val
= force_operand (XEXP (x
, 1), temp
);
5754 emit_move_insn (temp
, val
);
5760 else if (GET_CODE (XEXP (x
, 1)) == REG
)
5762 rtx temp
= gen_reg_rtx (Pmode
);
5763 rtx val
= force_operand (XEXP (x
, 0), temp
);
5765 emit_move_insn (temp
, val
);
5775 /* Print an integer constant expression in assembler syntax. Addition
5776 and subtraction are the only arithmetic that may appear in these
5777 expressions. FILE is the stdio stream to write to, X is the rtx, and
5778 CODE is the operand print code from the output string. */
5781 output_pic_addr_const (FILE *file
, rtx x
, int code
)
5785 switch (GET_CODE (x
))
5795 /* Mark the decl as referenced so that cgraph will output the function. */
5796 if (SYMBOL_REF_DECL (x
))
5797 mark_decl_referenced (SYMBOL_REF_DECL (x
));
5799 assemble_name (file
, XSTR (x
, 0));
5800 if (!TARGET_MACHO
&& code
== 'P' && ! SYMBOL_REF_LOCAL_P (x
))
5801 fputs ("@PLT", file
);
5808 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
5809 assemble_name (asm_out_file
, buf
);
5813 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5817 /* This used to output parentheses around the expression,
5818 but that does not work on the 386 (either ATT or BSD assembler). */
5819 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5823 if (GET_MODE (x
) == VOIDmode
)
5825 /* We can use %d if the number is <32 bits and positive. */
5826 if (CONST_DOUBLE_HIGH (x
) || CONST_DOUBLE_LOW (x
) < 0)
5827 fprintf (file
, "0x%lx%08lx",
5828 (unsigned long) CONST_DOUBLE_HIGH (x
),
5829 (unsigned long) CONST_DOUBLE_LOW (x
));
5831 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
5834 /* We can't handle floating point constants;
5835 PRINT_OPERAND must handle them. */
5836 output_operand_lossage ("floating constant misused");
5840 /* Some assemblers need integer constants to appear first. */
5841 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5843 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5845 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5847 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5849 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5851 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5859 putc (ASSEMBLER_DIALECT
== ASM_INTEL
? '(' : '[', file
);
5860 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5862 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5864 putc (ASSEMBLER_DIALECT
== ASM_INTEL
? ')' : ']', file
);
5868 if (XVECLEN (x
, 0) != 1)
5870 output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
5871 switch (XINT (x
, 1))
5874 fputs ("@GOT", file
);
5877 fputs ("@GOTOFF", file
);
5879 case UNSPEC_GOTPCREL
:
5880 fputs ("@GOTPCREL(%rip)", file
);
5882 case UNSPEC_GOTTPOFF
:
5883 /* FIXME: This might be @TPOFF in Sun ld too. */
5884 fputs ("@GOTTPOFF", file
);
5887 fputs ("@TPOFF", file
);
5891 fputs ("@TPOFF", file
);
5893 fputs ("@NTPOFF", file
);
5896 fputs ("@DTPOFF", file
);
5898 case UNSPEC_GOTNTPOFF
:
5900 fputs ("@GOTTPOFF(%rip)", file
);
5902 fputs ("@GOTNTPOFF", file
);
5904 case UNSPEC_INDNTPOFF
:
5905 fputs ("@INDNTPOFF", file
);
5908 output_operand_lossage ("invalid UNSPEC as operand");
5914 output_operand_lossage ("invalid expression as operand");
5918 /* This is called from dwarfout.c via ASM_OUTPUT_DWARF_ADDR_CONST.
5919 We need to handle our special PIC relocations. */
5922 i386_dwarf_output_addr_const (FILE *file
, rtx x
)
5925 fprintf (file
, "%s", TARGET_64BIT
? ASM_QUAD
: ASM_LONG
);
5929 fprintf (file
, "%s", ASM_LONG
);
5932 output_pic_addr_const (file
, x
, '\0');
5934 output_addr_const (file
, x
);
5938 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
5939 We need to emit DTP-relative relocations. */
5942 i386_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5944 fputs (ASM_LONG
, file
);
5945 output_addr_const (file
, x
);
5946 fputs ("@DTPOFF", file
);
5952 fputs (", 0", file
);
5959 /* In the name of slightly smaller debug output, and to cater to
5960 general assembler losage, recognize PIC+GOTOFF and turn it back
5961 into a direct symbol reference. */
5964 ix86_delegitimize_address (rtx orig_x
)
5968 if (GET_CODE (x
) == MEM
)
5973 if (GET_CODE (x
) != CONST
5974 || GET_CODE (XEXP (x
, 0)) != UNSPEC
5975 || XINT (XEXP (x
, 0), 1) != UNSPEC_GOTPCREL
5976 || GET_CODE (orig_x
) != MEM
)
5978 return XVECEXP (XEXP (x
, 0), 0, 0);
5981 if (GET_CODE (x
) != PLUS
5982 || GET_CODE (XEXP (x
, 1)) != CONST
)
5985 if (GET_CODE (XEXP (x
, 0)) == REG
5986 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5987 /* %ebx + GOT/GOTOFF */
5989 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5991 /* %ebx + %reg * scale + GOT/GOTOFF */
5993 if (GET_CODE (XEXP (y
, 0)) == REG
5994 && REGNO (XEXP (y
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5996 else if (GET_CODE (XEXP (y
, 1)) == REG
5997 && REGNO (XEXP (y
, 1)) == PIC_OFFSET_TABLE_REGNUM
)
6001 if (GET_CODE (y
) != REG
6002 && GET_CODE (y
) != MULT
6003 && GET_CODE (y
) != ASHIFT
)
6009 x
= XEXP (XEXP (x
, 1), 0);
6010 if (GET_CODE (x
) == UNSPEC
6011 && ((XINT (x
, 1) == UNSPEC_GOT
&& GET_CODE (orig_x
) == MEM
)
6012 || (XINT (x
, 1) == UNSPEC_GOTOFF
&& GET_CODE (orig_x
) != MEM
)))
6015 return gen_rtx_PLUS (Pmode
, y
, XVECEXP (x
, 0, 0));
6016 return XVECEXP (x
, 0, 0);
6019 if (GET_CODE (x
) == PLUS
6020 && GET_CODE (XEXP (x
, 0)) == UNSPEC
6021 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6022 && ((XINT (XEXP (x
, 0), 1) == UNSPEC_GOT
&& GET_CODE (orig_x
) == MEM
)
6023 || (XINT (XEXP (x
, 0), 1) == UNSPEC_GOTOFF
6024 && GET_CODE (orig_x
) != MEM
)))
6026 x
= gen_rtx_PLUS (VOIDmode
, XVECEXP (XEXP (x
, 0), 0, 0), XEXP (x
, 1));
6028 return gen_rtx_PLUS (Pmode
, y
, x
);
6036 put_condition_code (enum rtx_code code
, enum machine_mode mode
, int reverse
,
6041 if (mode
== CCFPmode
|| mode
== CCFPUmode
)
6043 enum rtx_code second_code
, bypass_code
;
6044 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
6045 if (bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
)
6047 code
= ix86_fp_compare_code_to_integer (code
);
6051 code
= reverse_condition (code
);
6062 if (mode
!= CCmode
&& mode
!= CCNOmode
&& mode
!= CCGCmode
)
6067 /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers.
6068 Those same assemblers have the same but opposite losage on cmov. */
6071 suffix
= fp
? "nbe" : "a";
6074 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
6076 else if (mode
== CCmode
|| mode
== CCGCmode
)
6087 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
6089 else if (mode
== CCmode
|| mode
== CCGCmode
)
6098 suffix
= fp
? "nb" : "ae";
6101 if (mode
!= CCmode
&& mode
!= CCGCmode
&& mode
!= CCNOmode
)
6111 suffix
= fp
? "u" : "p";
6114 suffix
= fp
? "nu" : "np";
6119 fputs (suffix
, file
);
6122 /* Print the name of register X to FILE based on its machine mode and number.
6123 If CODE is 'w', pretend the mode is HImode.
6124 If CODE is 'b', pretend the mode is QImode.
6125 If CODE is 'k', pretend the mode is SImode.
6126 If CODE is 'q', pretend the mode is DImode.
6127 If CODE is 'h', pretend the reg is the `high' byte register.
6128 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
6131 print_reg (rtx x
, int code
, FILE *file
)
6133 if (REGNO (x
) == ARG_POINTER_REGNUM
6134 || REGNO (x
) == FRAME_POINTER_REGNUM
6135 || REGNO (x
) == FLAGS_REG
6136 || REGNO (x
) == FPSR_REG
)
6139 if (ASSEMBLER_DIALECT
== ASM_ATT
|| USER_LABEL_PREFIX
[0] == 0)
6142 if (code
== 'w' || MMX_REG_P (x
))
6144 else if (code
== 'b')
6146 else if (code
== 'k')
6148 else if (code
== 'q')
6150 else if (code
== 'y')
6152 else if (code
== 'h')
6155 code
= GET_MODE_SIZE (GET_MODE (x
));
6157 /* Irritatingly, AMD extended registers use different naming convention
6158 from the normal registers. */
6159 if (REX_INT_REG_P (x
))
6166 error ("extended registers have no high halves");
6169 fprintf (file
, "r%ib", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6172 fprintf (file
, "r%iw", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6175 fprintf (file
, "r%id", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6178 fprintf (file
, "r%i", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6181 error ("unsupported operand size for extended register");
6189 if (STACK_TOP_P (x
))
6191 fputs ("st(0)", file
);
6198 if (! ANY_FP_REG_P (x
))
6199 putc (code
== 8 && TARGET_64BIT
? 'r' : 'e', file
);
6204 fputs (hi_reg_name
[REGNO (x
)], file
);
6207 if (REGNO (x
) >= ARRAY_SIZE (qi_reg_name
))
6209 fputs (qi_reg_name
[REGNO (x
)], file
);
6212 if (REGNO (x
) >= ARRAY_SIZE (qi_high_reg_name
))
6214 fputs (qi_high_reg_name
[REGNO (x
)], file
);
6221 /* Locate some local-dynamic symbol still in use by this function
6222 so that we can print its name in some tls_local_dynamic_base
6226 get_some_local_dynamic_name (void)
6230 if (cfun
->machine
->some_ld_name
)
6231 return cfun
->machine
->some_ld_name
;
6233 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6235 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
6236 return cfun
->machine
->some_ld_name
;
6242 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6246 if (GET_CODE (x
) == SYMBOL_REF
6247 && local_dynamic_symbolic_operand (x
, Pmode
))
6249 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
6257 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
6258 C -- print opcode suffix for set/cmov insn.
6259 c -- like C, but print reversed condition
6260 F,f -- likewise, but for floating-point.
6261 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
6263 R -- print the prefix for register names.
6264 z -- print the opcode suffix for the size of the current operand.
6265 * -- print a star (in certain assembler syntax)
6266 A -- print an absolute memory reference.
6267 w -- print the operand as if it's a "word" (HImode) even if it isn't.
6268 s -- print a shift double count, followed by the assemblers argument
6270 b -- print the QImode name of the register for the indicated operand.
6271 %b0 would print %al if operands[0] is reg 0.
6272 w -- likewise, print the HImode name of the register.
6273 k -- likewise, print the SImode name of the register.
6274 q -- likewise, print the DImode name of the register.
6275 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
6276 y -- print "st(0)" instead of "st" as a register.
6277 D -- print condition for SSE cmp instruction.
6278 P -- if PIC, print an @PLT suffix.
6279 X -- don't print any sort of PIC '@' suffix for a symbol.
6280 & -- print some in-use local-dynamic symbol name.
6284 print_operand (FILE *file
, rtx x
, int code
)
6291 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6296 assemble_name (file
, get_some_local_dynamic_name ());
6300 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6302 else if (ASSEMBLER_DIALECT
== ASM_INTEL
)
6304 /* Intel syntax. For absolute addresses, registers should not
6305 be surrounded by braces. */
6306 if (GET_CODE (x
) != REG
)
6309 PRINT_OPERAND (file
, x
, 0);
6317 PRINT_OPERAND (file
, x
, 0);
6322 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6327 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6332 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6337 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6342 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6347 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6352 /* 387 opcodes don't get size suffixes if the operands are
6354 if (STACK_REG_P (x
))
6357 /* Likewise if using Intel opcodes. */
6358 if (ASSEMBLER_DIALECT
== ASM_INTEL
)
6361 /* This is the size of op from size of operand. */
6362 switch (GET_MODE_SIZE (GET_MODE (x
)))
6365 #ifdef HAVE_GAS_FILDS_FISTS
6371 if (GET_MODE (x
) == SFmode
)
6386 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
6388 #ifdef GAS_MNEMONICS
6414 if (GET_CODE (x
) == CONST_INT
|| ! SHIFT_DOUBLE_OMITS_COUNT
)
6416 PRINT_OPERAND (file
, x
, 0);
6422 /* Little bit of braindamage here. The SSE compare instructions
6423 does use completely different names for the comparisons that the
6424 fp conditional moves. */
6425 switch (GET_CODE (x
))
6440 fputs ("unord", file
);
6444 fputs ("neq", file
);
6448 fputs ("nlt", file
);
6452 fputs ("nle", file
);
6455 fputs ("ord", file
);
6463 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
6464 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6466 switch (GET_MODE (x
))
6468 case HImode
: putc ('w', file
); break;
6470 case SFmode
: putc ('l', file
); break;
6472 case DFmode
: putc ('q', file
); break;
6480 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 0, file
);
6483 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
6484 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6487 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 1, file
);
6490 /* Like above, but reverse condition */
6492 /* Check to see if argument to %c is really a constant
6493 and not a condition code which needs to be reversed. */
6494 if (!COMPARISON_P (x
))
6496 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
6499 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 0, file
);
6502 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
6503 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6506 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 1, file
);
6512 if (!optimize
|| optimize_size
|| !TARGET_BRANCH_PREDICTION_HINTS
)
6515 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
6518 int pred_val
= INTVAL (XEXP (x
, 0));
6520 if (pred_val
< REG_BR_PROB_BASE
* 45 / 100
6521 || pred_val
> REG_BR_PROB_BASE
* 55 / 100)
6523 int taken
= pred_val
> REG_BR_PROB_BASE
/ 2;
6524 int cputaken
= final_forward_branch_p (current_output_insn
) == 0;
6526 /* Emit hints only in the case default branch prediction
6527 heuristics would fail. */
6528 if (taken
!= cputaken
)
6530 /* We use 3e (DS) prefix for taken branches and
6531 2e (CS) prefix for not taken branches. */
6533 fputs ("ds ; ", file
);
6535 fputs ("cs ; ", file
);
6542 output_operand_lossage ("invalid operand code '%c'", code
);
6546 if (GET_CODE (x
) == REG
)
6547 print_reg (x
, code
, file
);
6549 else if (GET_CODE (x
) == MEM
)
6551 /* No `byte ptr' prefix for call instructions. */
6552 if (ASSEMBLER_DIALECT
== ASM_INTEL
&& code
!= 'X' && code
!= 'P')
6555 switch (GET_MODE_SIZE (GET_MODE (x
)))
6557 case 1: size
= "BYTE"; break;
6558 case 2: size
= "WORD"; break;
6559 case 4: size
= "DWORD"; break;
6560 case 8: size
= "QWORD"; break;
6561 case 12: size
= "XWORD"; break;
6562 case 16: size
= "XMMWORD"; break;
6567 /* Check for explicit size override (codes 'b', 'w' and 'k') */
6570 else if (code
== 'w')
6572 else if (code
== 'k')
6576 fputs (" PTR ", file
);
6580 /* Avoid (%rip) for call operands. */
6581 if (CONSTANT_ADDRESS_P (x
) && code
== 'P'
6582 && GET_CODE (x
) != CONST_INT
)
6583 output_addr_const (file
, x
);
6584 else if (this_is_asm_operands
&& ! address_operand (x
, VOIDmode
))
6585 output_operand_lossage ("invalid constraints for operand");
6590 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
6595 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6596 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
6598 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6600 fprintf (file
, "0x%08lx", l
);
6603 /* These float cases don't actually occur as immediate operands. */
6604 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
6608 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (dstr
), 0, 1);
6609 fprintf (file
, "%s", dstr
);
6612 else if (GET_CODE (x
) == CONST_DOUBLE
6613 && GET_MODE (x
) == XFmode
)
6617 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (dstr
), 0, 1);
6618 fprintf (file
, "%s", dstr
);
6625 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
6627 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6630 else if (GET_CODE (x
) == CONST
|| GET_CODE (x
) == SYMBOL_REF
6631 || GET_CODE (x
) == LABEL_REF
)
6633 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6636 fputs ("OFFSET FLAT:", file
);
6639 if (GET_CODE (x
) == CONST_INT
)
6640 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
6642 output_pic_addr_const (file
, x
, code
);
6644 output_addr_const (file
, x
);
6648 /* Print a memory operand whose address is ADDR. */
6651 print_operand_address (FILE *file
, rtx addr
)
6653 struct ix86_address parts
;
6654 rtx base
, index
, disp
;
6657 if (! ix86_decompose_address (addr
, &parts
))
6661 index
= parts
.index
;
6663 scale
= parts
.scale
;
6671 if (USER_LABEL_PREFIX
[0] == 0)
6673 fputs ((parts
.seg
== SEG_FS
? "fs:" : "gs:"), file
);
6679 if (!base
&& !index
)
6681 /* Displacement only requires special attention. */
6683 if (GET_CODE (disp
) == CONST_INT
)
6685 if (ASSEMBLER_DIALECT
== ASM_INTEL
&& parts
.seg
== SEG_DEFAULT
)
6687 if (USER_LABEL_PREFIX
[0] == 0)
6689 fputs ("ds:", file
);
6691 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (disp
));
6694 output_pic_addr_const (file
, disp
, 0);
6696 output_addr_const (file
, disp
);
6698 /* Use one byte shorter RIP relative addressing for 64bit mode. */
6700 && ((GET_CODE (disp
) == SYMBOL_REF
6701 && ! tls_symbolic_operand (disp
, GET_MODE (disp
)))
6702 || GET_CODE (disp
) == LABEL_REF
6703 || (GET_CODE (disp
) == CONST
6704 && GET_CODE (XEXP (disp
, 0)) == PLUS
6705 && (GET_CODE (XEXP (XEXP (disp
, 0), 0)) == SYMBOL_REF
6706 || GET_CODE (XEXP (XEXP (disp
, 0), 0)) == LABEL_REF
)
6707 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)))
6708 fputs ("(%rip)", file
);
6712 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6717 output_pic_addr_const (file
, disp
, 0);
6718 else if (GET_CODE (disp
) == LABEL_REF
)
6719 output_asm_label (disp
);
6721 output_addr_const (file
, disp
);
6726 print_reg (base
, 0, file
);
6730 print_reg (index
, 0, file
);
6732 fprintf (file
, ",%d", scale
);
6738 rtx offset
= NULL_RTX
;
6742 /* Pull out the offset of a symbol; print any symbol itself. */
6743 if (GET_CODE (disp
) == CONST
6744 && GET_CODE (XEXP (disp
, 0)) == PLUS
6745 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
6747 offset
= XEXP (XEXP (disp
, 0), 1);
6748 disp
= gen_rtx_CONST (VOIDmode
,
6749 XEXP (XEXP (disp
, 0), 0));
6753 output_pic_addr_const (file
, disp
, 0);
6754 else if (GET_CODE (disp
) == LABEL_REF
)
6755 output_asm_label (disp
);
6756 else if (GET_CODE (disp
) == CONST_INT
)
6759 output_addr_const (file
, disp
);
6765 print_reg (base
, 0, file
);
6768 if (INTVAL (offset
) >= 0)
6770 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
6774 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
6781 print_reg (index
, 0, file
);
6783 fprintf (file
, "*%d", scale
);
6791 output_addr_const_extra (FILE *file
, rtx x
)
6795 if (GET_CODE (x
) != UNSPEC
)
6798 op
= XVECEXP (x
, 0, 0);
6799 switch (XINT (x
, 1))
6801 case UNSPEC_GOTTPOFF
:
6802 output_addr_const (file
, op
);
6803 /* FIXME: This might be @TPOFF in Sun ld. */
6804 fputs ("@GOTTPOFF", file
);
6807 output_addr_const (file
, op
);
6808 fputs ("@TPOFF", file
);
6811 output_addr_const (file
, op
);
6813 fputs ("@TPOFF", file
);
6815 fputs ("@NTPOFF", file
);
6818 output_addr_const (file
, op
);
6819 fputs ("@DTPOFF", file
);
6821 case UNSPEC_GOTNTPOFF
:
6822 output_addr_const (file
, op
);
6824 fputs ("@GOTTPOFF(%rip)", file
);
6826 fputs ("@GOTNTPOFF", file
);
6828 case UNSPEC_INDNTPOFF
:
6829 output_addr_const (file
, op
);
6830 fputs ("@INDNTPOFF", file
);
6840 /* Split one or more DImode RTL references into pairs of SImode
6841 references. The RTL can be REG, offsettable MEM, integer constant, or
6842 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
6843 split and "num" is its length. lo_half and hi_half are output arrays
6844 that parallel "operands". */
6847 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
6851 rtx op
= operands
[num
];
6853 /* simplify_subreg refuse to split volatile memory addresses,
6854 but we still have to handle it. */
6855 if (GET_CODE (op
) == MEM
)
6857 lo_half
[num
] = adjust_address (op
, SImode
, 0);
6858 hi_half
[num
] = adjust_address (op
, SImode
, 4);
6862 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
6863 GET_MODE (op
) == VOIDmode
6864 ? DImode
: GET_MODE (op
), 0);
6865 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
6866 GET_MODE (op
) == VOIDmode
6867 ? DImode
: GET_MODE (op
), 4);
6871 /* Split one or more TImode RTL references into pairs of SImode
6872 references. The RTL can be REG, offsettable MEM, integer constant, or
6873 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
6874 split and "num" is its length. lo_half and hi_half are output arrays
6875 that parallel "operands". */
6878 split_ti (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
6882 rtx op
= operands
[num
];
6884 /* simplify_subreg refuse to split volatile memory addresses, but we
6885 still have to handle it. */
6886 if (GET_CODE (op
) == MEM
)
6888 lo_half
[num
] = adjust_address (op
, DImode
, 0);
6889 hi_half
[num
] = adjust_address (op
, DImode
, 8);
6893 lo_half
[num
] = simplify_gen_subreg (DImode
, op
, TImode
, 0);
6894 hi_half
[num
] = simplify_gen_subreg (DImode
, op
, TImode
, 8);
6899 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
6900 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
6901 is the expression of the binary operation. The output may either be
6902 emitted here, or returned to the caller, like all output_* functions.
6904 There is no guarantee that the operands are the same mode, as they
6905 might be within FLOAT or FLOAT_EXTEND expressions. */
6907 #ifndef SYSV386_COMPAT
6908 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
6909 wants to fix the assemblers because that causes incompatibility
6910 with gcc. No-one wants to fix gcc because that causes
6911 incompatibility with assemblers... You can use the option of
6912 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
6913 #define SYSV386_COMPAT 1
6917 output_387_binary_op (rtx insn
, rtx
*operands
)
6919 static char buf
[30];
6922 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]) | SSE_REG_P (operands
[2]);
6924 #ifdef ENABLE_CHECKING
6925 /* Even if we do not want to check the inputs, this documents input
6926 constraints. Which helps in understanding the following code. */
6927 if (STACK_REG_P (operands
[0])
6928 && ((REG_P (operands
[1])
6929 && REGNO (operands
[0]) == REGNO (operands
[1])
6930 && (STACK_REG_P (operands
[2]) || GET_CODE (operands
[2]) == MEM
))
6931 || (REG_P (operands
[2])
6932 && REGNO (operands
[0]) == REGNO (operands
[2])
6933 && (STACK_REG_P (operands
[1]) || GET_CODE (operands
[1]) == MEM
)))
6934 && (STACK_TOP_P (operands
[1]) || STACK_TOP_P (operands
[2])))
6940 switch (GET_CODE (operands
[3]))
6943 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6944 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6952 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6953 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6961 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6962 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6970 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6971 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6985 if (GET_MODE (operands
[0]) == SFmode
)
6986 strcat (buf
, "ss\t{%2, %0|%0, %2}");
6988 strcat (buf
, "sd\t{%2, %0|%0, %2}");
6993 switch (GET_CODE (operands
[3]))
6997 if (REG_P (operands
[2]) && REGNO (operands
[0]) == REGNO (operands
[2]))
6999 rtx temp
= operands
[2];
7000 operands
[2] = operands
[1];
7004 /* know operands[0] == operands[1]. */
7006 if (GET_CODE (operands
[2]) == MEM
)
7012 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
7014 if (STACK_TOP_P (operands
[0]))
7015 /* How is it that we are storing to a dead operand[2]?
7016 Well, presumably operands[1] is dead too. We can't
7017 store the result to st(0) as st(0) gets popped on this
7018 instruction. Instead store to operands[2] (which I
7019 think has to be st(1)). st(1) will be popped later.
7020 gcc <= 2.8.1 didn't have this check and generated
7021 assembly code that the Unixware assembler rejected. */
7022 p
= "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7024 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7028 if (STACK_TOP_P (operands
[0]))
7029 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7031 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7036 if (GET_CODE (operands
[1]) == MEM
)
7042 if (GET_CODE (operands
[2]) == MEM
)
7048 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
7051 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
7052 derived assemblers, confusingly reverse the direction of
7053 the operation for fsub{r} and fdiv{r} when the
7054 destination register is not st(0). The Intel assembler
7055 doesn't have this brain damage. Read !SYSV386_COMPAT to
7056 figure out what the hardware really does. */
7057 if (STACK_TOP_P (operands
[0]))
7058 p
= "{p\t%0, %2|rp\t%2, %0}";
7060 p
= "{rp\t%2, %0|p\t%0, %2}";
7062 if (STACK_TOP_P (operands
[0]))
7063 /* As above for fmul/fadd, we can't store to st(0). */
7064 p
= "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7066 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7071 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[1])))
7074 if (STACK_TOP_P (operands
[0]))
7075 p
= "{rp\t%0, %1|p\t%1, %0}";
7077 p
= "{p\t%1, %0|rp\t%0, %1}";
7079 if (STACK_TOP_P (operands
[0]))
7080 p
= "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
7082 p
= "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
7087 if (STACK_TOP_P (operands
[0]))
7089 if (STACK_TOP_P (operands
[1]))
7090 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7092 p
= "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
7095 else if (STACK_TOP_P (operands
[1]))
7098 p
= "{\t%1, %0|r\t%0, %1}";
7100 p
= "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
7106 p
= "{r\t%2, %0|\t%0, %2}";
7108 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7121 /* Output code to initialize control word copies used by trunc?f?i and
7122 rounding patterns. CURRENT_MODE is set to current control word,
7123 while NEW_MODE is set to new control word. */
7126 emit_i387_cw_initialization (rtx current_mode
, rtx new_mode
, int mode
)
7128 rtx reg
= gen_reg_rtx (HImode
);
7130 emit_insn (gen_x86_fnstcw_1 (current_mode
));
7131 emit_move_insn (reg
, current_mode
);
7133 if (!TARGET_PARTIAL_REG_STALL
&& !optimize_size
7139 /* round down toward -oo */
7140 emit_insn (gen_movsi_insv_1 (reg
, GEN_INT (0x4)));
7144 /* round up toward +oo */
7145 emit_insn (gen_movsi_insv_1 (reg
, GEN_INT (0x8)));
7149 /* round toward zero (truncate) */
7150 emit_insn (gen_movsi_insv_1 (reg
, GEN_INT (0xc)));
7153 case I387_CW_MASK_PM
:
7154 /* mask precision exception for nearbyint() */
7155 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0020)));
7167 /* round down toward -oo */
7168 emit_insn (gen_andhi3 (reg
, reg
, GEN_INT (~0x0c00)));
7169 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0400)));
7173 /* round up toward +oo */
7174 emit_insn (gen_andhi3 (reg
, reg
, GEN_INT (~0x0c00)));
7175 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0800)));
7179 /* round toward zero (truncate) */
7180 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0c00)));
7183 case I387_CW_MASK_PM
:
7184 /* mask precision exception for nearbyint() */
7185 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0020)));
7193 emit_move_insn (new_mode
, reg
);
7196 /* Output code for INSN to convert a float to a signed int. OPERANDS
7197 are the insn operands. The output may be [HSD]Imode and the input
7198 operand may be [SDX]Fmode. */
7201 output_fix_trunc (rtx insn
, rtx
*operands
)
7203 int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
7204 int dimode_p
= GET_MODE (operands
[0]) == DImode
;
7206 /* Jump through a hoop or two for DImode, since the hardware has no
7207 non-popping instruction. We used to do this a different way, but
7208 that was somewhat fragile and broke with post-reload splitters. */
7209 if (dimode_p
&& !stack_top_dies
)
7210 output_asm_insn ("fld\t%y1", operands
);
7212 if (!STACK_TOP_P (operands
[1]))
7215 if (GET_CODE (operands
[0]) != MEM
)
7218 output_asm_insn ("fldcw\t%3", operands
);
7219 if (stack_top_dies
|| dimode_p
)
7220 output_asm_insn ("fistp%z0\t%0", operands
);
7222 output_asm_insn ("fist%z0\t%0", operands
);
7223 output_asm_insn ("fldcw\t%2", operands
);
7228 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
7229 should be used and 2 when fnstsw should be used. UNORDERED_P is true
7230 when fucom should be used. */
7233 output_fp_compare (rtx insn
, rtx
*operands
, int eflags_p
, int unordered_p
)
7236 rtx cmp_op0
, cmp_op1
;
7237 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]);
7241 cmp_op0
= operands
[1];
7242 cmp_op1
= operands
[2];
7246 cmp_op0
= operands
[0];
7247 cmp_op1
= operands
[1];
7252 if (GET_MODE (operands
[0]) == SFmode
)
7254 return "ucomiss\t{%1, %0|%0, %1}";
7256 return "comiss\t{%1, %0|%0, %1}";
7259 return "ucomisd\t{%1, %0|%0, %1}";
7261 return "comisd\t{%1, %0|%0, %1}";
7264 if (! STACK_TOP_P (cmp_op0
))
7267 stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
7269 if (cmp_op1
== CONST0_RTX (GET_MODE (cmp_op1
)))
7273 output_asm_insn ("ftst\n\tfnstsw\t%0", operands
);
7274 return TARGET_USE_FFREEP
? "ffreep\t%y1" : "fstp\t%y1";
7277 return "ftst\n\tfnstsw\t%0";
7280 if (STACK_REG_P (cmp_op1
)
7282 && find_regno_note (insn
, REG_DEAD
, REGNO (cmp_op1
))
7283 && REGNO (cmp_op1
) != FIRST_STACK_REG
)
7285 /* If both the top of the 387 stack dies, and the other operand
7286 is also a stack register that dies, then this must be a
7287 `fcompp' float compare */
7291 /* There is no double popping fcomi variant. Fortunately,
7292 eflags is immune from the fstp's cc clobbering. */
7294 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands
);
7296 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands
);
7297 return TARGET_USE_FFREEP
? "ffreep\t%y0" : "fstp\t%y0";
7304 return "fucompp\n\tfnstsw\t%0";
7306 return "fcompp\n\tfnstsw\t%0";
7319 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
7321 static const char * const alt
[24] =
7333 "fcomi\t{%y1, %0|%0, %y1}",
7334 "fcomip\t{%y1, %0|%0, %y1}",
7335 "fucomi\t{%y1, %0|%0, %y1}",
7336 "fucomip\t{%y1, %0|%0, %y1}",
7343 "fcom%z2\t%y2\n\tfnstsw\t%0",
7344 "fcomp%z2\t%y2\n\tfnstsw\t%0",
7345 "fucom%z2\t%y2\n\tfnstsw\t%0",
7346 "fucomp%z2\t%y2\n\tfnstsw\t%0",
7348 "ficom%z2\t%y2\n\tfnstsw\t%0",
7349 "ficomp%z2\t%y2\n\tfnstsw\t%0",
7357 mask
= eflags_p
<< 3;
7358 mask
|= (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
) << 2;
7359 mask
|= unordered_p
<< 1;
7360 mask
|= stack_top_dies
;
7373 ix86_output_addr_vec_elt (FILE *file
, int value
)
7375 const char *directive
= ASM_LONG
;
7380 directive
= ASM_QUAD
;
7386 fprintf (file
, "%s%s%d\n", directive
, LPREFIX
, value
);
7390 ix86_output_addr_diff_elt (FILE *file
, int value
, int rel
)
7393 fprintf (file
, "%s%s%d-%s%d\n",
7394 ASM_LONG
, LPREFIX
, value
, LPREFIX
, rel
);
7395 else if (HAVE_AS_GOTOFF_IN_DATA
)
7396 fprintf (file
, "%s%s%d@GOTOFF\n", ASM_LONG
, LPREFIX
, value
);
7398 else if (TARGET_MACHO
)
7400 fprintf (file
, "%s%s%d-", ASM_LONG
, LPREFIX
, value
);
7401 machopic_output_function_base_name (file
);
7402 fprintf(file
, "\n");
7406 asm_fprintf (file
, "%s%U%s+[.-%s%d]\n",
7407 ASM_LONG
, GOT_SYMBOL_NAME
, LPREFIX
, value
);
7410 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
7414 ix86_expand_clear (rtx dest
)
7418 /* We play register width games, which are only valid after reload. */
7419 if (!reload_completed
)
7422 /* Avoid HImode and its attendant prefix byte. */
7423 if (GET_MODE_SIZE (GET_MODE (dest
)) < 4)
7424 dest
= gen_rtx_REG (SImode
, REGNO (dest
));
7426 tmp
= gen_rtx_SET (VOIDmode
, dest
, const0_rtx
);
7428 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
7429 if (reload_completed
&& (!TARGET_USE_MOV0
|| optimize_size
))
7431 rtx clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, 17));
7432 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
7438 /* X is an unchanging MEM. If it is a constant pool reference, return
7439 the constant pool rtx, else NULL. */
7442 maybe_get_pool_constant (rtx x
)
7444 x
= ix86_delegitimize_address (XEXP (x
, 0));
7446 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
7447 return get_pool_constant (x
);
7453 ix86_expand_move (enum machine_mode mode
, rtx operands
[])
7455 int strict
= (reload_in_progress
|| reload_completed
);
7457 enum tls_model model
;
7462 model
= GET_CODE (op1
) == SYMBOL_REF
? SYMBOL_REF_TLS_MODEL (op1
) : 0;
7465 op1
= legitimize_tls_address (op1
, model
, true);
7466 op1
= force_operand (op1
, op0
);
7471 if (flag_pic
&& mode
== Pmode
&& symbolic_operand (op1
, Pmode
))
7476 rtx temp
= ((reload_in_progress
7477 || ((op0
&& GET_CODE (op0
) == REG
)
7479 ? op0
: gen_reg_rtx (Pmode
));
7480 op1
= machopic_indirect_data_reference (op1
, temp
);
7481 op1
= machopic_legitimize_pic_address (op1
, mode
,
7482 temp
== op1
? 0 : temp
);
7484 else if (MACHOPIC_INDIRECT
)
7485 op1
= machopic_indirect_data_reference (op1
, 0);
7489 if (GET_CODE (op0
) == MEM
)
7490 op1
= force_reg (Pmode
, op1
);
7492 op1
= legitimize_address (op1
, op1
, Pmode
);
7493 #endif /* TARGET_MACHO */
7497 if (GET_CODE (op0
) == MEM
7498 && (PUSH_ROUNDING (GET_MODE_SIZE (mode
)) != GET_MODE_SIZE (mode
)
7499 || !push_operand (op0
, mode
))
7500 && GET_CODE (op1
) == MEM
)
7501 op1
= force_reg (mode
, op1
);
7503 if (push_operand (op0
, mode
)
7504 && ! general_no_elim_operand (op1
, mode
))
7505 op1
= copy_to_mode_reg (mode
, op1
);
7507 /* Force large constants in 64bit compilation into register
7508 to get them CSEed. */
7509 if (TARGET_64BIT
&& mode
== DImode
7510 && immediate_operand (op1
, mode
)
7511 && !x86_64_zext_immediate_operand (op1
, VOIDmode
)
7512 && !register_operand (op0
, mode
)
7513 && optimize
&& !reload_completed
&& !reload_in_progress
)
7514 op1
= copy_to_mode_reg (mode
, op1
);
7516 if (FLOAT_MODE_P (mode
))
7518 /* If we are loading a floating point constant to a register,
7519 force the value to memory now, since we'll get better code
7520 out the back end. */
7524 else if (GET_CODE (op1
) == CONST_DOUBLE
)
7526 op1
= validize_mem (force_const_mem (mode
, op1
));
7527 if (!register_operand (op0
, mode
))
7529 rtx temp
= gen_reg_rtx (mode
);
7530 emit_insn (gen_rtx_SET (VOIDmode
, temp
, op1
));
7531 emit_move_insn (op0
, temp
);
7538 emit_insn (gen_rtx_SET (VOIDmode
, op0
, op1
));
7542 ix86_expand_vector_move (enum machine_mode mode
, rtx operands
[])
7544 /* Force constants other than zero into memory. We do not know how
7545 the instructions used to build constants modify the upper 64 bits
7546 of the register, once we have that information we may be able
7547 to handle some of them more efficiently. */
7548 if ((reload_in_progress
| reload_completed
) == 0
7549 && register_operand (operands
[0], mode
)
7550 && CONSTANT_P (operands
[1]) && operands
[1] != CONST0_RTX (mode
))
7551 operands
[1] = validize_mem (force_const_mem (mode
, operands
[1]));
7553 /* Make operand1 a register if it isn't already. */
7555 && !register_operand (operands
[0], mode
)
7556 && !register_operand (operands
[1], mode
))
7558 rtx temp
= force_reg (GET_MODE (operands
[1]), operands
[1]);
7559 emit_move_insn (operands
[0], temp
);
7563 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7566 /* Attempt to expand a binary operator. Make the expansion closer to the
7567 actual machine, then just general_operand, which will allow 3 separate
7568 memory references (one output, two input) in a single insn. */
7571 ix86_expand_binary_operator (enum rtx_code code
, enum machine_mode mode
,
7574 int matching_memory
;
7575 rtx src1
, src2
, dst
, op
, clob
;
7581 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
7582 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
7583 && (rtx_equal_p (dst
, src2
)
7584 || immediate_operand (src1
, mode
)))
7591 /* If the destination is memory, and we do not have matching source
7592 operands, do things in registers. */
7593 matching_memory
= 0;
7594 if (GET_CODE (dst
) == MEM
)
7596 if (rtx_equal_p (dst
, src1
))
7597 matching_memory
= 1;
7598 else if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
7599 && rtx_equal_p (dst
, src2
))
7600 matching_memory
= 2;
7602 dst
= gen_reg_rtx (mode
);
7605 /* Both source operands cannot be in memory. */
7606 if (GET_CODE (src1
) == MEM
&& GET_CODE (src2
) == MEM
)
7608 if (matching_memory
!= 2)
7609 src2
= force_reg (mode
, src2
);
7611 src1
= force_reg (mode
, src1
);
7614 /* If the operation is not commutable, source 1 cannot be a constant
7615 or non-matching memory. */
7616 if ((CONSTANT_P (src1
)
7617 || (!matching_memory
&& GET_CODE (src1
) == MEM
))
7618 && GET_RTX_CLASS (code
) != RTX_COMM_ARITH
)
7619 src1
= force_reg (mode
, src1
);
7621 /* If optimizing, copy to regs to improve CSE */
7622 if (optimize
&& ! no_new_pseudos
)
7624 if (GET_CODE (dst
) == MEM
)
7625 dst
= gen_reg_rtx (mode
);
7626 if (GET_CODE (src1
) == MEM
)
7627 src1
= force_reg (mode
, src1
);
7628 if (GET_CODE (src2
) == MEM
)
7629 src2
= force_reg (mode
, src2
);
7632 /* Emit the instruction. */
7634 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, mode
, src1
, src2
));
7635 if (reload_in_progress
)
7637 /* Reload doesn't know about the flags register, and doesn't know that
7638 it doesn't want to clobber it. We can only do this with PLUS. */
7645 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
7646 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
7649 /* Fix up the destination if needed. */
7650 if (dst
!= operands
[0])
7651 emit_move_insn (operands
[0], dst
);
7654 /* Return TRUE or FALSE depending on whether the binary operator meets the
7655 appropriate constraints. */
7658 ix86_binary_operator_ok (enum rtx_code code
,
7659 enum machine_mode mode ATTRIBUTE_UNUSED
,
7662 /* Both source operands cannot be in memory. */
7663 if (GET_CODE (operands
[1]) == MEM
&& GET_CODE (operands
[2]) == MEM
)
7665 /* If the operation is not commutable, source 1 cannot be a constant. */
7666 if (CONSTANT_P (operands
[1]) && GET_RTX_CLASS (code
) != RTX_COMM_ARITH
)
7668 /* If the destination is memory, we must have a matching source operand. */
7669 if (GET_CODE (operands
[0]) == MEM
7670 && ! (rtx_equal_p (operands
[0], operands
[1])
7671 || (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
7672 && rtx_equal_p (operands
[0], operands
[2]))))
7674 /* If the operation is not commutable and the source 1 is memory, we must
7675 have a matching destination. */
7676 if (GET_CODE (operands
[1]) == MEM
7677 && GET_RTX_CLASS (code
) != RTX_COMM_ARITH
7678 && ! rtx_equal_p (operands
[0], operands
[1]))
7683 /* Attempt to expand a unary operator. Make the expansion closer to the
7684 actual machine, then just general_operand, which will allow 2 separate
7685 memory references (one output, one input) in a single insn. */
7688 ix86_expand_unary_operator (enum rtx_code code
, enum machine_mode mode
,
7691 int matching_memory
;
7692 rtx src
, dst
, op
, clob
;
7697 /* If the destination is memory, and we do not have matching source
7698 operands, do things in registers. */
7699 matching_memory
= 0;
7700 if (GET_CODE (dst
) == MEM
)
7702 if (rtx_equal_p (dst
, src
))
7703 matching_memory
= 1;
7705 dst
= gen_reg_rtx (mode
);
7708 /* When source operand is memory, destination must match. */
7709 if (!matching_memory
&& GET_CODE (src
) == MEM
)
7710 src
= force_reg (mode
, src
);
7712 /* If optimizing, copy to regs to improve CSE */
7713 if (optimize
&& ! no_new_pseudos
)
7715 if (GET_CODE (dst
) == MEM
)
7716 dst
= gen_reg_rtx (mode
);
7717 if (GET_CODE (src
) == MEM
)
7718 src
= force_reg (mode
, src
);
7721 /* Emit the instruction. */
7723 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_e (code
, mode
, src
));
7724 if (reload_in_progress
|| code
== NOT
)
7726 /* Reload doesn't know about the flags register, and doesn't know that
7727 it doesn't want to clobber it. */
7734 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
7735 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
7738 /* Fix up the destination if needed. */
7739 if (dst
!= operands
[0])
7740 emit_move_insn (operands
[0], dst
);
7743 /* Return TRUE or FALSE depending on whether the unary operator meets the
7744 appropriate constraints. */
7747 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED
,
7748 enum machine_mode mode ATTRIBUTE_UNUSED
,
7749 rtx operands
[2] ATTRIBUTE_UNUSED
)
7751 /* If one of operands is memory, source and destination must match. */
7752 if ((GET_CODE (operands
[0]) == MEM
7753 || GET_CODE (operands
[1]) == MEM
)
7754 && ! rtx_equal_p (operands
[0], operands
[1]))
7759 /* Return TRUE or FALSE depending on whether the first SET in INSN
7760 has source and destination with matching CC modes, and that the
7761 CC mode is at least as constrained as REQ_MODE. */
7764 ix86_match_ccmode (rtx insn
, enum machine_mode req_mode
)
7767 enum machine_mode set_mode
;
7769 set
= PATTERN (insn
);
7770 if (GET_CODE (set
) == PARALLEL
)
7771 set
= XVECEXP (set
, 0, 0);
7772 if (GET_CODE (set
) != SET
)
7774 if (GET_CODE (SET_SRC (set
)) != COMPARE
)
7777 set_mode
= GET_MODE (SET_DEST (set
));
7781 if (req_mode
!= CCNOmode
7782 && (req_mode
!= CCmode
7783 || XEXP (SET_SRC (set
), 1) != const0_rtx
))
7787 if (req_mode
== CCGCmode
)
7791 if (req_mode
== CCGOCmode
|| req_mode
== CCNOmode
)
7795 if (req_mode
== CCZmode
)
7805 return (GET_MODE (SET_SRC (set
)) == set_mode
);
7808 /* Generate insn patterns to do an integer compare of OPERANDS. */
7811 ix86_expand_int_compare (enum rtx_code code
, rtx op0
, rtx op1
)
7813 enum machine_mode cmpmode
;
7816 cmpmode
= SELECT_CC_MODE (code
, op0
, op1
);
7817 flags
= gen_rtx_REG (cmpmode
, FLAGS_REG
);
7819 /* This is very simple, but making the interface the same as in the
7820 FP case makes the rest of the code easier. */
7821 tmp
= gen_rtx_COMPARE (cmpmode
, op0
, op1
);
7822 emit_insn (gen_rtx_SET (VOIDmode
, flags
, tmp
));
7824 /* Return the test that should be put into the flags user, i.e.
7825 the bcc, scc, or cmov instruction. */
7826 return gen_rtx_fmt_ee (code
, VOIDmode
, flags
, const0_rtx
);
7829 /* Figure out whether to use ordered or unordered fp comparisons.
7830 Return the appropriate mode to use. */
7833 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED
)
7835 /* ??? In order to make all comparisons reversible, we do all comparisons
7836 non-trapping when compiling for IEEE. Once gcc is able to distinguish
7837 all forms trapping and nontrapping comparisons, we can make inequality
7838 comparisons trapping again, since it results in better code when using
7839 FCOM based compares. */
7840 return TARGET_IEEE_FP
? CCFPUmode
: CCFPmode
;
7844 ix86_cc_mode (enum rtx_code code
, rtx op0
, rtx op1
)
7846 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
7847 return ix86_fp_compare_mode (code
);
7850 /* Only zero flag is needed. */
7852 case NE
: /* ZF!=0 */
7854 /* Codes needing carry flag. */
7855 case GEU
: /* CF=0 */
7856 case GTU
: /* CF=0 & ZF=0 */
7857 case LTU
: /* CF=1 */
7858 case LEU
: /* CF=1 | ZF=1 */
7860 /* Codes possibly doable only with sign flag when
7861 comparing against zero. */
7862 case GE
: /* SF=OF or SF=0 */
7863 case LT
: /* SF<>OF or SF=1 */
7864 if (op1
== const0_rtx
)
7867 /* For other cases Carry flag is not required. */
7869 /* Codes doable only with sign flag when comparing
7870 against zero, but we miss jump instruction for it
7871 so we need to use relational tests against overflow
7872 that thus needs to be zero. */
7873 case GT
: /* ZF=0 & SF=OF */
7874 case LE
: /* ZF=1 | SF<>OF */
7875 if (op1
== const0_rtx
)
7879 /* strcmp pattern do (use flags) and combine may ask us for proper
7888 /* Return the fixed registers used for condition codes. */
7891 ix86_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
7898 /* If two condition code modes are compatible, return a condition code
7899 mode which is compatible with both. Otherwise, return
7902 static enum machine_mode
7903 ix86_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
7908 if (GET_MODE_CLASS (m1
) != MODE_CC
|| GET_MODE_CLASS (m2
) != MODE_CC
)
7911 if ((m1
== CCGCmode
&& m2
== CCGOCmode
)
7912 || (m1
== CCGOCmode
&& m2
== CCGCmode
))
7940 /* These are only compatible with themselves, which we already
7946 /* Return true if we should use an FCOMI instruction for this fp comparison. */
7949 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED
)
7951 enum rtx_code swapped_code
= swap_condition (code
);
7952 return ((ix86_fp_comparison_cost (code
) == ix86_fp_comparison_fcomi_cost (code
))
7953 || (ix86_fp_comparison_cost (swapped_code
)
7954 == ix86_fp_comparison_fcomi_cost (swapped_code
)));
7957 /* Swap, force into registers, or otherwise massage the two operands
7958 to a fp comparison. The operands are updated in place; the new
7959 comparison code is returned. */
7961 static enum rtx_code
7962 ix86_prepare_fp_compare_args (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
7964 enum machine_mode fpcmp_mode
= ix86_fp_compare_mode (code
);
7965 rtx op0
= *pop0
, op1
= *pop1
;
7966 enum machine_mode op_mode
= GET_MODE (op0
);
7967 int is_sse
= SSE_REG_P (op0
) | SSE_REG_P (op1
);
7969 /* All of the unordered compare instructions only work on registers.
7970 The same is true of the fcomi compare instructions. The same is
7971 true of the XFmode compare instructions if not comparing with
7972 zero (ftst insn is used in this case). */
7975 && (fpcmp_mode
== CCFPUmode
7976 || (op_mode
== XFmode
7977 && ! (standard_80387_constant_p (op0
) == 1
7978 || standard_80387_constant_p (op1
) == 1))
7979 || ix86_use_fcomi_compare (code
)))
7981 op0
= force_reg (op_mode
, op0
);
7982 op1
= force_reg (op_mode
, op1
);
7986 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
7987 things around if they appear profitable, otherwise force op0
7990 if (standard_80387_constant_p (op0
) == 0
7991 || (GET_CODE (op0
) == MEM
7992 && ! (standard_80387_constant_p (op1
) == 0
7993 || GET_CODE (op1
) == MEM
)))
7996 tmp
= op0
, op0
= op1
, op1
= tmp
;
7997 code
= swap_condition (code
);
8000 if (GET_CODE (op0
) != REG
)
8001 op0
= force_reg (op_mode
, op0
);
8003 if (CONSTANT_P (op1
))
8005 int tmp
= standard_80387_constant_p (op1
);
8007 op1
= validize_mem (force_const_mem (op_mode
, op1
));
8011 op1
= force_reg (op_mode
, op1
);
8014 op1
= force_reg (op_mode
, op1
);
8018 /* Try to rearrange the comparison to make it cheaper. */
8019 if (ix86_fp_comparison_cost (code
)
8020 > ix86_fp_comparison_cost (swap_condition (code
))
8021 && (GET_CODE (op1
) == REG
|| !no_new_pseudos
))
8024 tmp
= op0
, op0
= op1
, op1
= tmp
;
8025 code
= swap_condition (code
);
8026 if (GET_CODE (op0
) != REG
)
8027 op0
= force_reg (op_mode
, op0
);
8035 /* Convert comparison codes we use to represent FP comparison to integer
8036 code that will result in proper branch. Return UNKNOWN if no such code
8040 ix86_fp_compare_code_to_integer (enum rtx_code code
)
8069 /* Split comparison code CODE into comparisons we can do using branch
8070 instructions. BYPASS_CODE is comparison code for branch that will
8071 branch around FIRST_CODE and SECOND_CODE. If some of branches
8072 is not required, set value to UNKNOWN.
8073 We never require more than two branches. */
8076 ix86_fp_comparison_codes (enum rtx_code code
, enum rtx_code
*bypass_code
,
8077 enum rtx_code
*first_code
,
8078 enum rtx_code
*second_code
)
8081 *bypass_code
= UNKNOWN
;
8082 *second_code
= UNKNOWN
;
8084 /* The fcomi comparison sets flags as follows:
8094 case GT
: /* GTU - CF=0 & ZF=0 */
8095 case GE
: /* GEU - CF=0 */
8096 case ORDERED
: /* PF=0 */
8097 case UNORDERED
: /* PF=1 */
8098 case UNEQ
: /* EQ - ZF=1 */
8099 case UNLT
: /* LTU - CF=1 */
8100 case UNLE
: /* LEU - CF=1 | ZF=1 */
8101 case LTGT
: /* EQ - ZF=0 */
8103 case LT
: /* LTU - CF=1 - fails on unordered */
8105 *bypass_code
= UNORDERED
;
8107 case LE
: /* LEU - CF=1 | ZF=1 - fails on unordered */
8109 *bypass_code
= UNORDERED
;
8111 case EQ
: /* EQ - ZF=1 - fails on unordered */
8113 *bypass_code
= UNORDERED
;
8115 case NE
: /* NE - ZF=0 - fails on unordered */
8117 *second_code
= UNORDERED
;
8119 case UNGE
: /* GEU - CF=0 - fails on unordered */
8121 *second_code
= UNORDERED
;
8123 case UNGT
: /* GTU - CF=0 & ZF=0 - fails on unordered */
8125 *second_code
= UNORDERED
;
8130 if (!TARGET_IEEE_FP
)
8132 *second_code
= UNKNOWN
;
8133 *bypass_code
= UNKNOWN
;
8137 /* Return cost of comparison done fcom + arithmetics operations on AX.
8138 All following functions do use number of instructions as a cost metrics.
8139 In future this should be tweaked to compute bytes for optimize_size and
8140 take into account performance of various instructions on various CPUs. */
8142 ix86_fp_comparison_arithmetics_cost (enum rtx_code code
)
8144 if (!TARGET_IEEE_FP
)
8146 /* The cost of code output by ix86_expand_fp_compare. */
8174 /* Return cost of comparison done using fcomi operation.
8175 See ix86_fp_comparison_arithmetics_cost for the metrics. */
8177 ix86_fp_comparison_fcomi_cost (enum rtx_code code
)
8179 enum rtx_code bypass_code
, first_code
, second_code
;
8180 /* Return arbitrarily high cost when instruction is not supported - this
8181 prevents gcc from using it. */
8184 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8185 return (bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
) + 2;
8188 /* Return cost of comparison done using sahf operation.
8189 See ix86_fp_comparison_arithmetics_cost for the metrics. */
8191 ix86_fp_comparison_sahf_cost (enum rtx_code code
)
8193 enum rtx_code bypass_code
, first_code
, second_code
;
8194 /* Return arbitrarily high cost when instruction is not preferred - this
8195 avoids gcc from using it. */
8196 if (!TARGET_USE_SAHF
&& !optimize_size
)
8198 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8199 return (bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
) + 3;
8202 /* Compute cost of the comparison done using any method.
8203 See ix86_fp_comparison_arithmetics_cost for the metrics. */
8205 ix86_fp_comparison_cost (enum rtx_code code
)
8207 int fcomi_cost
, sahf_cost
, arithmetics_cost
= 1024;
8210 fcomi_cost
= ix86_fp_comparison_fcomi_cost (code
);
8211 sahf_cost
= ix86_fp_comparison_sahf_cost (code
);
8213 min
= arithmetics_cost
= ix86_fp_comparison_arithmetics_cost (code
);
8214 if (min
> sahf_cost
)
8216 if (min
> fcomi_cost
)
8221 /* Generate insn patterns to do a floating point compare of OPERANDS. */
8224 ix86_expand_fp_compare (enum rtx_code code
, rtx op0
, rtx op1
, rtx scratch
,
8225 rtx
*second_test
, rtx
*bypass_test
)
8227 enum machine_mode fpcmp_mode
, intcmp_mode
;
8229 int cost
= ix86_fp_comparison_cost (code
);
8230 enum rtx_code bypass_code
, first_code
, second_code
;
8232 fpcmp_mode
= ix86_fp_compare_mode (code
);
8233 code
= ix86_prepare_fp_compare_args (code
, &op0
, &op1
);
8236 *second_test
= NULL_RTX
;
8238 *bypass_test
= NULL_RTX
;
8240 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8242 /* Do fcomi/sahf based test when profitable. */
8243 if ((bypass_code
== UNKNOWN
|| bypass_test
)
8244 && (second_code
== UNKNOWN
|| second_test
)
8245 && ix86_fp_comparison_arithmetics_cost (code
) > cost
)
8249 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
8250 tmp
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (fpcmp_mode
, FLAGS_REG
),
8256 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
8257 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), UNSPEC_FNSTSW
);
8259 scratch
= gen_reg_rtx (HImode
);
8260 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
8261 emit_insn (gen_x86_sahf_1 (scratch
));
8264 /* The FP codes work out to act like unsigned. */
8265 intcmp_mode
= fpcmp_mode
;
8267 if (bypass_code
!= UNKNOWN
)
8268 *bypass_test
= gen_rtx_fmt_ee (bypass_code
, VOIDmode
,
8269 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
8271 if (second_code
!= UNKNOWN
)
8272 *second_test
= gen_rtx_fmt_ee (second_code
, VOIDmode
,
8273 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
8278 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
8279 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
8280 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), UNSPEC_FNSTSW
);
8282 scratch
= gen_reg_rtx (HImode
);
8283 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
8285 /* In the unordered case, we have to check C2 for NaN's, which
8286 doesn't happen to work out to anything nice combination-wise.
8287 So do some bit twiddling on the value we've got in AH to come
8288 up with an appropriate set of condition codes. */
8290 intcmp_mode
= CCNOmode
;
8295 if (code
== GT
|| !TARGET_IEEE_FP
)
8297 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
8302 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8303 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
8304 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x44)));
8305 intcmp_mode
= CCmode
;
8311 if (code
== LT
&& TARGET_IEEE_FP
)
8313 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8314 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x01)));
8315 intcmp_mode
= CCmode
;
8320 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x01)));
8326 if (code
== GE
|| !TARGET_IEEE_FP
)
8328 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x05)));
8333 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8334 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
8341 if (code
== LE
&& TARGET_IEEE_FP
)
8343 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8344 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
8345 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
8346 intcmp_mode
= CCmode
;
8351 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
8357 if (code
== EQ
&& TARGET_IEEE_FP
)
8359 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8360 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
8361 intcmp_mode
= CCmode
;
8366 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
8373 if (code
== NE
&& TARGET_IEEE_FP
)
8375 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8376 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
8382 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
8388 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
8392 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
8401 /* Return the test that should be put into the flags user, i.e.
8402 the bcc, scc, or cmov instruction. */
8403 return gen_rtx_fmt_ee (code
, VOIDmode
,
8404 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
8409 ix86_expand_compare (enum rtx_code code
, rtx
*second_test
, rtx
*bypass_test
)
8412 op0
= ix86_compare_op0
;
8413 op1
= ix86_compare_op1
;
8416 *second_test
= NULL_RTX
;
8418 *bypass_test
= NULL_RTX
;
8420 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
8421 ret
= ix86_expand_fp_compare (code
, op0
, op1
, NULL_RTX
,
8422 second_test
, bypass_test
);
8424 ret
= ix86_expand_int_compare (code
, op0
, op1
);
8429 /* Return true if the CODE will result in nontrivial jump sequence. */
8431 ix86_fp_jump_nontrivial_p (enum rtx_code code
)
8433 enum rtx_code bypass_code
, first_code
, second_code
;
8436 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8437 return bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
;
8441 ix86_expand_branch (enum rtx_code code
, rtx label
)
8445 switch (GET_MODE (ix86_compare_op0
))
8451 tmp
= ix86_expand_compare (code
, NULL
, NULL
);
8452 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
8453 gen_rtx_LABEL_REF (VOIDmode
, label
),
8455 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
8464 enum rtx_code bypass_code
, first_code
, second_code
;
8466 code
= ix86_prepare_fp_compare_args (code
, &ix86_compare_op0
,
8469 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8471 /* Check whether we will use the natural sequence with one jump. If
8472 so, we can expand jump early. Otherwise delay expansion by
8473 creating compound insn to not confuse optimizers. */
8474 if (bypass_code
== UNKNOWN
&& second_code
== UNKNOWN
8477 ix86_split_fp_branch (code
, ix86_compare_op0
, ix86_compare_op1
,
8478 gen_rtx_LABEL_REF (VOIDmode
, label
),
8483 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
,
8484 ix86_compare_op0
, ix86_compare_op1
);
8485 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
8486 gen_rtx_LABEL_REF (VOIDmode
, label
),
8488 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
8490 use_fcomi
= ix86_use_fcomi_compare (code
);
8491 vec
= rtvec_alloc (3 + !use_fcomi
);
8492 RTVEC_ELT (vec
, 0) = tmp
;
8494 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
8496 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
8499 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
8501 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
8509 /* Expand DImode branch into multiple compare+branch. */
8511 rtx lo
[2], hi
[2], label2
;
8512 enum rtx_code code1
, code2
, code3
;
8514 if (CONSTANT_P (ix86_compare_op0
) && ! CONSTANT_P (ix86_compare_op1
))
8516 tmp
= ix86_compare_op0
;
8517 ix86_compare_op0
= ix86_compare_op1
;
8518 ix86_compare_op1
= tmp
;
8519 code
= swap_condition (code
);
8521 split_di (&ix86_compare_op0
, 1, lo
+0, hi
+0);
8522 split_di (&ix86_compare_op1
, 1, lo
+1, hi
+1);
8524 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
8525 avoid two branches. This costs one extra insn, so disable when
8526 optimizing for size. */
8528 if ((code
== EQ
|| code
== NE
)
8530 || hi
[1] == const0_rtx
|| lo
[1] == const0_rtx
))
8535 if (hi
[1] != const0_rtx
)
8536 xor1
= expand_binop (SImode
, xor_optab
, xor1
, hi
[1],
8537 NULL_RTX
, 0, OPTAB_WIDEN
);
8540 if (lo
[1] != const0_rtx
)
8541 xor0
= expand_binop (SImode
, xor_optab
, xor0
, lo
[1],
8542 NULL_RTX
, 0, OPTAB_WIDEN
);
8544 tmp
= expand_binop (SImode
, ior_optab
, xor1
, xor0
,
8545 NULL_RTX
, 0, OPTAB_WIDEN
);
8547 ix86_compare_op0
= tmp
;
8548 ix86_compare_op1
= const0_rtx
;
8549 ix86_expand_branch (code
, label
);
8553 /* Otherwise, if we are doing less-than or greater-or-equal-than,
8554 op1 is a constant and the low word is zero, then we can just
8555 examine the high word. */
8557 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
)
8560 case LT
: case LTU
: case GE
: case GEU
:
8561 ix86_compare_op0
= hi
[0];
8562 ix86_compare_op1
= hi
[1];
8563 ix86_expand_branch (code
, label
);
8569 /* Otherwise, we need two or three jumps. */
8571 label2
= gen_label_rtx ();
8574 code2
= swap_condition (code
);
8575 code3
= unsigned_condition (code
);
8579 case LT
: case GT
: case LTU
: case GTU
:
8582 case LE
: code1
= LT
; code2
= GT
; break;
8583 case GE
: code1
= GT
; code2
= LT
; break;
8584 case LEU
: code1
= LTU
; code2
= GTU
; break;
8585 case GEU
: code1
= GTU
; code2
= LTU
; break;
8587 case EQ
: code1
= UNKNOWN
; code2
= NE
; break;
8588 case NE
: code2
= UNKNOWN
; break;
8596 * if (hi(a) < hi(b)) goto true;
8597 * if (hi(a) > hi(b)) goto false;
8598 * if (lo(a) < lo(b)) goto true;
8602 ix86_compare_op0
= hi
[0];
8603 ix86_compare_op1
= hi
[1];
8605 if (code1
!= UNKNOWN
)
8606 ix86_expand_branch (code1
, label
);
8607 if (code2
!= UNKNOWN
)
8608 ix86_expand_branch (code2
, label2
);
8610 ix86_compare_op0
= lo
[0];
8611 ix86_compare_op1
= lo
[1];
8612 ix86_expand_branch (code3
, label
);
8614 if (code2
!= UNKNOWN
)
8615 emit_label (label2
);
8624 /* Split branch based on floating point condition. */
8626 ix86_split_fp_branch (enum rtx_code code
, rtx op1
, rtx op2
,
8627 rtx target1
, rtx target2
, rtx tmp
)
8630 rtx label
= NULL_RTX
;
8632 int bypass_probability
= -1, second_probability
= -1, probability
= -1;
8635 if (target2
!= pc_rtx
)
8638 code
= reverse_condition_maybe_unordered (code
);
8643 condition
= ix86_expand_fp_compare (code
, op1
, op2
,
8644 tmp
, &second
, &bypass
);
8646 if (split_branch_probability
>= 0)
8648 /* Distribute the probabilities across the jumps.
8649 Assume the BYPASS and SECOND to be always test
8651 probability
= split_branch_probability
;
8653 /* Value of 1 is low enough to make no need for probability
8654 to be updated. Later we may run some experiments and see
8655 if unordered values are more frequent in practice. */
8657 bypass_probability
= 1;
8659 second_probability
= 1;
8661 if (bypass
!= NULL_RTX
)
8663 label
= gen_label_rtx ();
8664 i
= emit_jump_insn (gen_rtx_SET
8666 gen_rtx_IF_THEN_ELSE (VOIDmode
,
8668 gen_rtx_LABEL_REF (VOIDmode
,
8671 if (bypass_probability
>= 0)
8673 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
8674 GEN_INT (bypass_probability
),
8677 i
= emit_jump_insn (gen_rtx_SET
8679 gen_rtx_IF_THEN_ELSE (VOIDmode
,
8680 condition
, target1
, target2
)));
8681 if (probability
>= 0)
8683 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
8684 GEN_INT (probability
),
8686 if (second
!= NULL_RTX
)
8688 i
= emit_jump_insn (gen_rtx_SET
8690 gen_rtx_IF_THEN_ELSE (VOIDmode
, second
, target1
,
8692 if (second_probability
>= 0)
8694 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
8695 GEN_INT (second_probability
),
8698 if (label
!= NULL_RTX
)
8703 ix86_expand_setcc (enum rtx_code code
, rtx dest
)
8705 rtx ret
, tmp
, tmpreg
, equiv
;
8706 rtx second_test
, bypass_test
;
8708 if (GET_MODE (ix86_compare_op0
) == DImode
8710 return 0; /* FAIL */
8712 if (GET_MODE (dest
) != QImode
)
8715 ret
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
8716 PUT_MODE (ret
, QImode
);
8721 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, ret
));
8722 if (bypass_test
|| second_test
)
8724 rtx test
= second_test
;
8726 rtx tmp2
= gen_reg_rtx (QImode
);
8733 PUT_CODE (test
, reverse_condition_maybe_unordered (GET_CODE (test
)));
8735 PUT_MODE (test
, QImode
);
8736 emit_insn (gen_rtx_SET (VOIDmode
, tmp2
, test
));
8739 emit_insn (gen_andqi3 (tmp
, tmpreg
, tmp2
));
8741 emit_insn (gen_iorqi3 (tmp
, tmpreg
, tmp2
));
8744 /* Attach a REG_EQUAL note describing the comparison result. */
8745 equiv
= simplify_gen_relational (code
, QImode
,
8746 GET_MODE (ix86_compare_op0
),
8747 ix86_compare_op0
, ix86_compare_op1
);
8748 set_unique_reg_note (get_last_insn (), REG_EQUAL
, equiv
);
8750 return 1; /* DONE */
8753 /* Expand comparison setting or clearing carry flag. Return true when
8754 successful and set pop for the operation. */
8756 ix86_expand_carry_flag_compare (enum rtx_code code
, rtx op0
, rtx op1
, rtx
*pop
)
8758 enum machine_mode mode
=
8759 GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
8761 /* Do not handle DImode compares that go trought special path. Also we can't
8762 deal with FP compares yet. This is possible to add. */
8763 if ((mode
== DImode
&& !TARGET_64BIT
))
8765 if (FLOAT_MODE_P (mode
))
8767 rtx second_test
= NULL
, bypass_test
= NULL
;
8768 rtx compare_op
, compare_seq
;
8770 /* Shortcut: following common codes never translate into carry flag compares. */
8771 if (code
== EQ
|| code
== NE
|| code
== UNEQ
|| code
== LTGT
8772 || code
== ORDERED
|| code
== UNORDERED
)
8775 /* These comparisons require zero flag; swap operands so they won't. */
8776 if ((code
== GT
|| code
== UNLE
|| code
== LE
|| code
== UNGT
)
8782 code
= swap_condition (code
);
8785 /* Try to expand the comparison and verify that we end up with carry flag
8786 based comparison. This is fails to be true only when we decide to expand
8787 comparison using arithmetic that is not too common scenario. */
8789 compare_op
= ix86_expand_fp_compare (code
, op0
, op1
, NULL_RTX
,
8790 &second_test
, &bypass_test
);
8791 compare_seq
= get_insns ();
8794 if (second_test
|| bypass_test
)
8796 if (GET_MODE (XEXP (compare_op
, 0)) == CCFPmode
8797 || GET_MODE (XEXP (compare_op
, 0)) == CCFPUmode
)
8798 code
= ix86_fp_compare_code_to_integer (GET_CODE (compare_op
));
8800 code
= GET_CODE (compare_op
);
8801 if (code
!= LTU
&& code
!= GEU
)
8803 emit_insn (compare_seq
);
8807 if (!INTEGRAL_MODE_P (mode
))
8815 /* Convert a==0 into (unsigned)a<1. */
8818 if (op1
!= const0_rtx
)
8821 code
= (code
== EQ
? LTU
: GEU
);
8824 /* Convert a>b into b<a or a>=b-1. */
8827 if (GET_CODE (op1
) == CONST_INT
)
8829 op1
= gen_int_mode (INTVAL (op1
) + 1, GET_MODE (op0
));
8830 /* Bail out on overflow. We still can swap operands but that
8831 would force loading of the constant into register. */
8832 if (op1
== const0_rtx
8833 || !x86_64_immediate_operand (op1
, GET_MODE (op1
)))
8835 code
= (code
== GTU
? GEU
: LTU
);
8842 code
= (code
== GTU
? LTU
: GEU
);
8846 /* Convert a>=0 into (unsigned)a<0x80000000. */
8849 if (mode
== DImode
|| op1
!= const0_rtx
)
8851 op1
= gen_int_mode (1 << (GET_MODE_BITSIZE (mode
) - 1), mode
);
8852 code
= (code
== LT
? GEU
: LTU
);
8856 if (mode
== DImode
|| op1
!= constm1_rtx
)
8858 op1
= gen_int_mode (1 << (GET_MODE_BITSIZE (mode
) - 1), mode
);
8859 code
= (code
== LE
? GEU
: LTU
);
8865 /* Swapping operands may cause constant to appear as first operand. */
8866 if (!nonimmediate_operand (op0
, VOIDmode
))
8870 op0
= force_reg (mode
, op0
);
8872 ix86_compare_op0
= op0
;
8873 ix86_compare_op1
= op1
;
8874 *pop
= ix86_expand_compare (code
, NULL
, NULL
);
8875 if (GET_CODE (*pop
) != LTU
&& GET_CODE (*pop
) != GEU
)
8881 ix86_expand_int_movcc (rtx operands
[])
8883 enum rtx_code code
= GET_CODE (operands
[1]), compare_code
;
8884 rtx compare_seq
, compare_op
;
8885 rtx second_test
, bypass_test
;
8886 enum machine_mode mode
= GET_MODE (operands
[0]);
8887 bool sign_bit_compare_p
= false;;
8890 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
8891 compare_seq
= get_insns ();
8894 compare_code
= GET_CODE (compare_op
);
8896 if ((ix86_compare_op1
== const0_rtx
&& (code
== GE
|| code
== LT
))
8897 || (ix86_compare_op1
== constm1_rtx
&& (code
== GT
|| code
== LE
)))
8898 sign_bit_compare_p
= true;
8900 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
8901 HImode insns, we'd be swallowed in word prefix ops. */
8903 if ((mode
!= HImode
|| TARGET_FAST_PREFIX
)
8904 && (mode
!= DImode
|| TARGET_64BIT
)
8905 && GET_CODE (operands
[2]) == CONST_INT
8906 && GET_CODE (operands
[3]) == CONST_INT
)
8908 rtx out
= operands
[0];
8909 HOST_WIDE_INT ct
= INTVAL (operands
[2]);
8910 HOST_WIDE_INT cf
= INTVAL (operands
[3]);
8914 /* Sign bit compares are better done using shifts than we do by using
8916 if (sign_bit_compare_p
8917 || ix86_expand_carry_flag_compare (code
, ix86_compare_op0
,
8918 ix86_compare_op1
, &compare_op
))
8920 /* Detect overlap between destination and compare sources. */
8923 if (!sign_bit_compare_p
)
8927 compare_code
= GET_CODE (compare_op
);
8929 if (GET_MODE (XEXP (compare_op
, 0)) == CCFPmode
8930 || GET_MODE (XEXP (compare_op
, 0)) == CCFPUmode
)
8933 compare_code
= ix86_fp_compare_code_to_integer (compare_code
);
8936 /* To simplify rest of code, restrict to the GEU case. */
8937 if (compare_code
== LTU
)
8939 HOST_WIDE_INT tmp
= ct
;
8942 compare_code
= reverse_condition (compare_code
);
8943 code
= reverse_condition (code
);
8948 PUT_CODE (compare_op
,
8949 reverse_condition_maybe_unordered
8950 (GET_CODE (compare_op
)));
8952 PUT_CODE (compare_op
, reverse_condition (GET_CODE (compare_op
)));
8956 if (reg_overlap_mentioned_p (out
, ix86_compare_op0
)
8957 || reg_overlap_mentioned_p (out
, ix86_compare_op1
))
8958 tmp
= gen_reg_rtx (mode
);
8961 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp
, compare_op
));
8963 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode
, tmp
), compare_op
));
8967 if (code
== GT
|| code
== GE
)
8968 code
= reverse_condition (code
);
8971 HOST_WIDE_INT tmp
= ct
;
8976 tmp
= emit_store_flag (tmp
, code
, ix86_compare_op0
,
8977 ix86_compare_op1
, VOIDmode
, 0, -1);
8990 tmp
= expand_simple_binop (mode
, PLUS
,
8992 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9003 tmp
= expand_simple_binop (mode
, IOR
,
9005 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9007 else if (diff
== -1 && ct
)
9017 tmp
= expand_simple_unop (mode
, NOT
, tmp
, copy_rtx (tmp
), 1);
9019 tmp
= expand_simple_binop (mode
, PLUS
,
9020 copy_rtx (tmp
), GEN_INT (cf
),
9021 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9029 * andl cf - ct, dest
9039 tmp
= expand_simple_unop (mode
, NOT
, tmp
, copy_rtx (tmp
), 1);
9042 tmp
= expand_simple_binop (mode
, AND
,
9044 gen_int_mode (cf
- ct
, mode
),
9045 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9047 tmp
= expand_simple_binop (mode
, PLUS
,
9048 copy_rtx (tmp
), GEN_INT (ct
),
9049 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9052 if (!rtx_equal_p (tmp
, out
))
9053 emit_move_insn (copy_rtx (out
), copy_rtx (tmp
));
9055 return 1; /* DONE */
9061 tmp
= ct
, ct
= cf
, cf
= tmp
;
9063 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
9065 /* We may be reversing unordered compare to normal compare, that
9066 is not valid in general (we may convert non-trapping condition
9067 to trapping one), however on i386 we currently emit all
9068 comparisons unordered. */
9069 compare_code
= reverse_condition_maybe_unordered (compare_code
);
9070 code
= reverse_condition_maybe_unordered (code
);
9074 compare_code
= reverse_condition (compare_code
);
9075 code
= reverse_condition (code
);
9079 compare_code
= UNKNOWN
;
9080 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0
)) == MODE_INT
9081 && GET_CODE (ix86_compare_op1
) == CONST_INT
)
9083 if (ix86_compare_op1
== const0_rtx
9084 && (code
== LT
|| code
== GE
))
9085 compare_code
= code
;
9086 else if (ix86_compare_op1
== constm1_rtx
)
9090 else if (code
== GT
)
9095 /* Optimize dest = (op0 < 0) ? -1 : cf. */
9096 if (compare_code
!= UNKNOWN
9097 && GET_MODE (ix86_compare_op0
) == GET_MODE (out
)
9098 && (cf
== -1 || ct
== -1))
9100 /* If lea code below could be used, only optimize
9101 if it results in a 2 insn sequence. */
9103 if (! (diff
== 1 || diff
== 2 || diff
== 4 || diff
== 8
9104 || diff
== 3 || diff
== 5 || diff
== 9)
9105 || (compare_code
== LT
&& ct
== -1)
9106 || (compare_code
== GE
&& cf
== -1))
9109 * notl op1 (if necessary)
9117 code
= reverse_condition (code
);
9120 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9121 ix86_compare_op1
, VOIDmode
, 0, -1);
9123 out
= expand_simple_binop (mode
, IOR
,
9125 out
, 1, OPTAB_DIRECT
);
9126 if (out
!= operands
[0])
9127 emit_move_insn (operands
[0], out
);
9129 return 1; /* DONE */
9134 if ((diff
== 1 || diff
== 2 || diff
== 4 || diff
== 8
9135 || diff
== 3 || diff
== 5 || diff
== 9)
9136 && ((mode
!= QImode
&& mode
!= HImode
) || !TARGET_PARTIAL_REG_STALL
)
9138 || x86_64_immediate_operand (GEN_INT (cf
), VOIDmode
)))
9144 * lea cf(dest*(ct-cf)),dest
9148 * This also catches the degenerate setcc-only case.
9154 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9155 ix86_compare_op1
, VOIDmode
, 0, 1);
9158 /* On x86_64 the lea instruction operates on Pmode, so we need
9159 to get arithmetics done in proper mode to match. */
9161 tmp
= copy_rtx (out
);
9165 out1
= copy_rtx (out
);
9166 tmp
= gen_rtx_MULT (mode
, out1
, GEN_INT (diff
& ~1));
9170 tmp
= gen_rtx_PLUS (mode
, tmp
, out1
);
9176 tmp
= gen_rtx_PLUS (mode
, tmp
, GEN_INT (cf
));
9179 if (!rtx_equal_p (tmp
, out
))
9182 out
= force_operand (tmp
, copy_rtx (out
));
9184 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (out
), copy_rtx (tmp
)));
9186 if (!rtx_equal_p (out
, operands
[0]))
9187 emit_move_insn (operands
[0], copy_rtx (out
));
9189 return 1; /* DONE */
9193 * General case: Jumpful:
9194 * xorl dest,dest cmpl op1, op2
9195 * cmpl op1, op2 movl ct, dest
9197 * decl dest movl cf, dest
9198 * andl (cf-ct),dest 1:
9203 * This is reasonably steep, but branch mispredict costs are
9204 * high on modern cpus, so consider failing only if optimizing
9208 if ((!TARGET_CMOVE
|| (mode
== QImode
&& TARGET_PARTIAL_REG_STALL
))
9209 && BRANCH_COST
>= 2)
9215 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
9216 /* We may be reversing unordered compare to normal compare,
9217 that is not valid in general (we may convert non-trapping
9218 condition to trapping one), however on i386 we currently
9219 emit all comparisons unordered. */
9220 code
= reverse_condition_maybe_unordered (code
);
9223 code
= reverse_condition (code
);
9224 if (compare_code
!= UNKNOWN
)
9225 compare_code
= reverse_condition (compare_code
);
9229 if (compare_code
!= UNKNOWN
)
9231 /* notl op1 (if needed)
9236 For x < 0 (resp. x <= -1) there will be no notl,
9237 so if possible swap the constants to get rid of the
9239 True/false will be -1/0 while code below (store flag
9240 followed by decrement) is 0/-1, so the constants need
9241 to be exchanged once more. */
9243 if (compare_code
== GE
|| !cf
)
9245 code
= reverse_condition (code
);
9250 HOST_WIDE_INT tmp
= cf
;
9255 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9256 ix86_compare_op1
, VOIDmode
, 0, -1);
9260 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9261 ix86_compare_op1
, VOIDmode
, 0, 1);
9263 out
= expand_simple_binop (mode
, PLUS
, copy_rtx (out
), constm1_rtx
,
9264 copy_rtx (out
), 1, OPTAB_DIRECT
);
9267 out
= expand_simple_binop (mode
, AND
, copy_rtx (out
),
9268 gen_int_mode (cf
- ct
, mode
),
9269 copy_rtx (out
), 1, OPTAB_DIRECT
);
9271 out
= expand_simple_binop (mode
, PLUS
, copy_rtx (out
), GEN_INT (ct
),
9272 copy_rtx (out
), 1, OPTAB_DIRECT
);
9273 if (!rtx_equal_p (out
, operands
[0]))
9274 emit_move_insn (operands
[0], copy_rtx (out
));
9276 return 1; /* DONE */
9280 if (!TARGET_CMOVE
|| (mode
== QImode
&& TARGET_PARTIAL_REG_STALL
))
9282 /* Try a few things more with specific constants and a variable. */
9285 rtx var
, orig_out
, out
, tmp
;
9287 if (BRANCH_COST
<= 2)
9288 return 0; /* FAIL */
9290 /* If one of the two operands is an interesting constant, load a
9291 constant with the above and mask it in with a logical operation. */
9293 if (GET_CODE (operands
[2]) == CONST_INT
)
9296 if (INTVAL (operands
[2]) == 0 && operands
[3] != constm1_rtx
)
9297 operands
[3] = constm1_rtx
, op
= and_optab
;
9298 else if (INTVAL (operands
[2]) == -1 && operands
[3] != const0_rtx
)
9299 operands
[3] = const0_rtx
, op
= ior_optab
;
9301 return 0; /* FAIL */
9303 else if (GET_CODE (operands
[3]) == CONST_INT
)
9306 if (INTVAL (operands
[3]) == 0 && operands
[2] != constm1_rtx
)
9307 operands
[2] = constm1_rtx
, op
= and_optab
;
9308 else if (INTVAL (operands
[3]) == -1 && operands
[3] != const0_rtx
)
9309 operands
[2] = const0_rtx
, op
= ior_optab
;
9311 return 0; /* FAIL */
9314 return 0; /* FAIL */
9316 orig_out
= operands
[0];
9317 tmp
= gen_reg_rtx (mode
);
9320 /* Recurse to get the constant loaded. */
9321 if (ix86_expand_int_movcc (operands
) == 0)
9322 return 0; /* FAIL */
9324 /* Mask in the interesting variable. */
9325 out
= expand_binop (mode
, op
, var
, tmp
, orig_out
, 0,
9327 if (!rtx_equal_p (out
, orig_out
))
9328 emit_move_insn (copy_rtx (orig_out
), copy_rtx (out
));
9330 return 1; /* DONE */
9334 * For comparison with above,
9344 if (! nonimmediate_operand (operands
[2], mode
))
9345 operands
[2] = force_reg (mode
, operands
[2]);
9346 if (! nonimmediate_operand (operands
[3], mode
))
9347 operands
[3] = force_reg (mode
, operands
[3]);
9349 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
9351 rtx tmp
= gen_reg_rtx (mode
);
9352 emit_move_insn (tmp
, operands
[3]);
9355 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
9357 rtx tmp
= gen_reg_rtx (mode
);
9358 emit_move_insn (tmp
, operands
[2]);
9362 if (! register_operand (operands
[2], VOIDmode
)
9364 || ! register_operand (operands
[3], VOIDmode
)))
9365 operands
[2] = force_reg (mode
, operands
[2]);
9368 && ! register_operand (operands
[3], VOIDmode
))
9369 operands
[3] = force_reg (mode
, operands
[3]);
9371 emit_insn (compare_seq
);
9372 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9373 gen_rtx_IF_THEN_ELSE (mode
,
9374 compare_op
, operands
[2],
9377 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
9378 gen_rtx_IF_THEN_ELSE (mode
,
9380 copy_rtx (operands
[3]),
9381 copy_rtx (operands
[0]))));
9383 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
9384 gen_rtx_IF_THEN_ELSE (mode
,
9386 copy_rtx (operands
[2]),
9387 copy_rtx (operands
[0]))));
9389 return 1; /* DONE */
9393 ix86_expand_fp_movcc (rtx operands
[])
9397 rtx compare_op
, second_test
, bypass_test
;
9399 /* For SF/DFmode conditional moves based on comparisons
9400 in same mode, we may want to use SSE min/max instructions. */
9401 if (((TARGET_SSE_MATH
&& GET_MODE (operands
[0]) == SFmode
)
9402 || (TARGET_SSE2
&& TARGET_SSE_MATH
&& GET_MODE (operands
[0]) == DFmode
))
9403 && GET_MODE (ix86_compare_op0
) == GET_MODE (operands
[0])
9404 /* The SSE comparisons does not support the LTGT/UNEQ pair. */
9406 || (GET_CODE (operands
[1]) != LTGT
&& GET_CODE (operands
[1]) != UNEQ
))
9407 /* We may be called from the post-reload splitter. */
9408 && (!REG_P (operands
[0])
9409 || SSE_REG_P (operands
[0])
9410 || REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
9412 rtx op0
= ix86_compare_op0
, op1
= ix86_compare_op1
;
9413 code
= GET_CODE (operands
[1]);
9415 /* See if we have (cross) match between comparison operands and
9416 conditional move operands. */
9417 if (rtx_equal_p (operands
[2], op1
))
9422 code
= reverse_condition_maybe_unordered (code
);
9424 if (rtx_equal_p (operands
[2], op0
) && rtx_equal_p (operands
[3], op1
))
9426 /* Check for min operation. */
9427 if (code
== LT
|| code
== UNLE
)
9435 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
9436 if (memory_operand (op0
, VOIDmode
))
9437 op0
= force_reg (GET_MODE (operands
[0]), op0
);
9438 if (GET_MODE (operands
[0]) == SFmode
)
9439 emit_insn (gen_minsf3 (operands
[0], op0
, op1
));
9441 emit_insn (gen_mindf3 (operands
[0], op0
, op1
));
9444 /* Check for max operation. */
9445 if (code
== GT
|| code
== UNGE
)
9453 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
9454 if (memory_operand (op0
, VOIDmode
))
9455 op0
= force_reg (GET_MODE (operands
[0]), op0
);
9456 if (GET_MODE (operands
[0]) == SFmode
)
9457 emit_insn (gen_maxsf3 (operands
[0], op0
, op1
));
9459 emit_insn (gen_maxdf3 (operands
[0], op0
, op1
));
9463 /* Manage condition to be sse_comparison_operator. In case we are
9464 in non-ieee mode, try to canonicalize the destination operand
9465 to be first in the comparison - this helps reload to avoid extra
9467 if (!sse_comparison_operator (operands
[1], VOIDmode
)
9468 || (rtx_equal_p (operands
[0], ix86_compare_op1
) && !TARGET_IEEE_FP
))
9470 rtx tmp
= ix86_compare_op0
;
9471 ix86_compare_op0
= ix86_compare_op1
;
9472 ix86_compare_op1
= tmp
;
9473 operands
[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands
[1])),
9474 VOIDmode
, ix86_compare_op0
,
9477 /* Similarly try to manage result to be first operand of conditional
9478 move. We also don't support the NE comparison on SSE, so try to
9480 if ((rtx_equal_p (operands
[0], operands
[3])
9481 && (!TARGET_IEEE_FP
|| GET_CODE (operands
[1]) != EQ
))
9482 || (GET_CODE (operands
[1]) == NE
&& TARGET_IEEE_FP
))
9484 rtx tmp
= operands
[2];
9485 operands
[2] = operands
[3];
9487 operands
[1] = gen_rtx_fmt_ee (reverse_condition_maybe_unordered
9488 (GET_CODE (operands
[1])),
9489 VOIDmode
, ix86_compare_op0
,
9492 if (GET_MODE (operands
[0]) == SFmode
)
9493 emit_insn (gen_sse_movsfcc (operands
[0], operands
[1],
9494 operands
[2], operands
[3],
9495 ix86_compare_op0
, ix86_compare_op1
));
9497 emit_insn (gen_sse_movdfcc (operands
[0], operands
[1],
9498 operands
[2], operands
[3],
9499 ix86_compare_op0
, ix86_compare_op1
));
9503 /* The floating point conditional move instructions don't directly
9504 support conditions resulting from a signed integer comparison. */
9506 code
= GET_CODE (operands
[1]);
9507 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
9509 /* The floating point conditional move instructions don't directly
9510 support signed integer comparisons. */
9512 if (!fcmov_comparison_operator (compare_op
, VOIDmode
))
9514 if (second_test
!= NULL
|| bypass_test
!= NULL
)
9516 tmp
= gen_reg_rtx (QImode
);
9517 ix86_expand_setcc (code
, tmp
);
9519 ix86_compare_op0
= tmp
;
9520 ix86_compare_op1
= const0_rtx
;
9521 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
9523 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
9525 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
9526 emit_move_insn (tmp
, operands
[3]);
9529 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
9531 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
9532 emit_move_insn (tmp
, operands
[2]);
9536 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9537 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
9542 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9543 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
9548 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9549 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
9557 /* Expand conditional increment or decrement using adb/sbb instructions.
9558 The default case using setcc followed by the conditional move can be
9559 done by generic code. */
9561 ix86_expand_int_addcc (rtx operands
[])
9563 enum rtx_code code
= GET_CODE (operands
[1]);
9565 rtx val
= const0_rtx
;
9567 enum machine_mode mode
= GET_MODE (operands
[0]);
9569 if (operands
[3] != const1_rtx
9570 && operands
[3] != constm1_rtx
)
9572 if (!ix86_expand_carry_flag_compare (code
, ix86_compare_op0
,
9573 ix86_compare_op1
, &compare_op
))
9575 code
= GET_CODE (compare_op
);
9577 if (GET_MODE (XEXP (compare_op
, 0)) == CCFPmode
9578 || GET_MODE (XEXP (compare_op
, 0)) == CCFPUmode
)
9581 code
= ix86_fp_compare_code_to_integer (code
);
9588 PUT_CODE (compare_op
,
9589 reverse_condition_maybe_unordered
9590 (GET_CODE (compare_op
)));
9592 PUT_CODE (compare_op
, reverse_condition (GET_CODE (compare_op
)));
9594 PUT_MODE (compare_op
, mode
);
9596 /* Construct either adc or sbb insn. */
9597 if ((code
== LTU
) == (operands
[3] == constm1_rtx
))
9599 switch (GET_MODE (operands
[0]))
9602 emit_insn (gen_subqi3_carry (operands
[0], operands
[2], val
, compare_op
));
9605 emit_insn (gen_subhi3_carry (operands
[0], operands
[2], val
, compare_op
));
9608 emit_insn (gen_subsi3_carry (operands
[0], operands
[2], val
, compare_op
));
9611 emit_insn (gen_subdi3_carry_rex64 (operands
[0], operands
[2], val
, compare_op
));
9619 switch (GET_MODE (operands
[0]))
9622 emit_insn (gen_addqi3_carry (operands
[0], operands
[2], val
, compare_op
));
9625 emit_insn (gen_addhi3_carry (operands
[0], operands
[2], val
, compare_op
));
9628 emit_insn (gen_addsi3_carry (operands
[0], operands
[2], val
, compare_op
));
9631 emit_insn (gen_adddi3_carry_rex64 (operands
[0], operands
[2], val
, compare_op
));
9637 return 1; /* DONE */
9641 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
9642 works for floating pointer parameters and nonoffsetable memories.
9643 For pushes, it returns just stack offsets; the values will be saved
9644 in the right order. Maximally three parts are generated. */
9647 ix86_split_to_parts (rtx operand
, rtx
*parts
, enum machine_mode mode
)
9652 size
= mode
==XFmode
? 3 : GET_MODE_SIZE (mode
) / 4;
9654 size
= (GET_MODE_SIZE (mode
) + 4) / 8;
9656 if (GET_CODE (operand
) == REG
&& MMX_REGNO_P (REGNO (operand
)))
9658 if (size
< 2 || size
> 3)
9661 /* Optimize constant pool reference to immediates. This is used by fp
9662 moves, that force all constants to memory to allow combining. */
9663 if (GET_CODE (operand
) == MEM
&& MEM_READONLY_P (operand
))
9665 rtx tmp
= maybe_get_pool_constant (operand
);
9670 if (GET_CODE (operand
) == MEM
&& !offsettable_memref_p (operand
))
9672 /* The only non-offsetable memories we handle are pushes. */
9673 if (! push_operand (operand
, VOIDmode
))
9676 operand
= copy_rtx (operand
);
9677 PUT_MODE (operand
, Pmode
);
9678 parts
[0] = parts
[1] = parts
[2] = operand
;
9680 else if (!TARGET_64BIT
)
9683 split_di (&operand
, 1, &parts
[0], &parts
[1]);
9686 if (REG_P (operand
))
9688 if (!reload_completed
)
9690 parts
[0] = gen_rtx_REG (SImode
, REGNO (operand
) + 0);
9691 parts
[1] = gen_rtx_REG (SImode
, REGNO (operand
) + 1);
9693 parts
[2] = gen_rtx_REG (SImode
, REGNO (operand
) + 2);
9695 else if (offsettable_memref_p (operand
))
9697 operand
= adjust_address (operand
, SImode
, 0);
9699 parts
[1] = adjust_address (operand
, SImode
, 4);
9701 parts
[2] = adjust_address (operand
, SImode
, 8);
9703 else if (GET_CODE (operand
) == CONST_DOUBLE
)
9708 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
9712 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
9713 parts
[2] = gen_int_mode (l
[2], SImode
);
9716 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
9721 parts
[1] = gen_int_mode (l
[1], SImode
);
9722 parts
[0] = gen_int_mode (l
[0], SImode
);
9731 split_ti (&operand
, 1, &parts
[0], &parts
[1]);
9732 if (mode
== XFmode
|| mode
== TFmode
)
9734 enum machine_mode upper_mode
= mode
==XFmode
? SImode
: DImode
;
9735 if (REG_P (operand
))
9737 if (!reload_completed
)
9739 parts
[0] = gen_rtx_REG (DImode
, REGNO (operand
) + 0);
9740 parts
[1] = gen_rtx_REG (upper_mode
, REGNO (operand
) + 1);
9742 else if (offsettable_memref_p (operand
))
9744 operand
= adjust_address (operand
, DImode
, 0);
9746 parts
[1] = adjust_address (operand
, upper_mode
, 8);
9748 else if (GET_CODE (operand
) == CONST_DOUBLE
)
9753 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
9754 real_to_target (l
, &r
, mode
);
9755 /* Do not use shift by 32 to avoid warning on 32bit systems. */
9756 if (HOST_BITS_PER_WIDE_INT
>= 64)
9759 ((l
[0] & (((HOST_WIDE_INT
) 2 << 31) - 1))
9760 + ((((HOST_WIDE_INT
) l
[1]) << 31) << 1),
9763 parts
[0] = immed_double_const (l
[0], l
[1], DImode
);
9764 if (upper_mode
== SImode
)
9765 parts
[1] = gen_int_mode (l
[2], SImode
);
9766 else if (HOST_BITS_PER_WIDE_INT
>= 64)
9769 ((l
[2] & (((HOST_WIDE_INT
) 2 << 31) - 1))
9770 + ((((HOST_WIDE_INT
) l
[3]) << 31) << 1),
9773 parts
[1] = immed_double_const (l
[2], l
[3], DImode
);
9783 /* Emit insns to perform a move or push of DI, DF, and XF values.
9784 Return false when normal moves are needed; true when all required
9785 insns have been emitted. Operands 2-4 contain the input values
9786 int the correct order; operands 5-7 contain the output values. */
9789 ix86_split_long_move (rtx operands
[])
9795 enum machine_mode mode
= GET_MODE (operands
[0]);
9797 /* The DFmode expanders may ask us to move double.
9798 For 64bit target this is single move. By hiding the fact
9799 here we simplify i386.md splitters. */
9800 if (GET_MODE_SIZE (GET_MODE (operands
[0])) == 8 && TARGET_64BIT
)
9802 /* Optimize constant pool reference to immediates. This is used by
9803 fp moves, that force all constants to memory to allow combining. */
9805 if (GET_CODE (operands
[1]) == MEM
9806 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
9807 && CONSTANT_POOL_ADDRESS_P (XEXP (operands
[1], 0)))
9808 operands
[1] = get_pool_constant (XEXP (operands
[1], 0));
9809 if (push_operand (operands
[0], VOIDmode
))
9811 operands
[0] = copy_rtx (operands
[0]);
9812 PUT_MODE (operands
[0], Pmode
);
9815 operands
[0] = gen_lowpart (DImode
, operands
[0]);
9816 operands
[1] = gen_lowpart (DImode
, operands
[1]);
9817 emit_move_insn (operands
[0], operands
[1]);
9821 /* The only non-offsettable memory we handle is push. */
9822 if (push_operand (operands
[0], VOIDmode
))
9824 else if (GET_CODE (operands
[0]) == MEM
9825 && ! offsettable_memref_p (operands
[0]))
9828 nparts
= ix86_split_to_parts (operands
[1], part
[1], GET_MODE (operands
[0]));
9829 ix86_split_to_parts (operands
[0], part
[0], GET_MODE (operands
[0]));
9831 /* When emitting push, take care for source operands on the stack. */
9832 if (push
&& GET_CODE (operands
[1]) == MEM
9833 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
9836 part
[1][1] = change_address (part
[1][1], GET_MODE (part
[1][1]),
9837 XEXP (part
[1][2], 0));
9838 part
[1][0] = change_address (part
[1][0], GET_MODE (part
[1][0]),
9839 XEXP (part
[1][1], 0));
9842 /* We need to do copy in the right order in case an address register
9843 of the source overlaps the destination. */
9844 if (REG_P (part
[0][0]) && GET_CODE (part
[1][0]) == MEM
)
9846 if (reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0)))
9848 if (reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
9851 && reg_overlap_mentioned_p (part
[0][2], XEXP (part
[1][0], 0)))
9854 /* Collision in the middle part can be handled by reordering. */
9855 if (collisions
== 1 && nparts
== 3
9856 && reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
9859 tmp
= part
[0][1]; part
[0][1] = part
[0][2]; part
[0][2] = tmp
;
9860 tmp
= part
[1][1]; part
[1][1] = part
[1][2]; part
[1][2] = tmp
;
9863 /* If there are more collisions, we can't handle it by reordering.
9864 Do an lea to the last part and use only one colliding move. */
9865 else if (collisions
> 1)
9871 base
= part
[0][nparts
- 1];
9873 /* Handle the case when the last part isn't valid for lea.
9874 Happens in 64-bit mode storing the 12-byte XFmode. */
9875 if (GET_MODE (base
) != Pmode
)
9876 base
= gen_rtx_REG (Pmode
, REGNO (base
));
9878 emit_insn (gen_rtx_SET (VOIDmode
, base
, XEXP (part
[1][0], 0)));
9879 part
[1][0] = replace_equiv_address (part
[1][0], base
);
9880 part
[1][1] = replace_equiv_address (part
[1][1],
9881 plus_constant (base
, UNITS_PER_WORD
));
9883 part
[1][2] = replace_equiv_address (part
[1][2],
9884 plus_constant (base
, 8));
9894 if (TARGET_128BIT_LONG_DOUBLE
&& mode
== XFmode
)
9895 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, GEN_INT (-4)));
9896 emit_move_insn (part
[0][2], part
[1][2]);
9901 /* In 64bit mode we don't have 32bit push available. In case this is
9902 register, it is OK - we will just use larger counterpart. We also
9903 retype memory - these comes from attempt to avoid REX prefix on
9904 moving of second half of TFmode value. */
9905 if (GET_MODE (part
[1][1]) == SImode
)
9907 if (GET_CODE (part
[1][1]) == MEM
)
9908 part
[1][1] = adjust_address (part
[1][1], DImode
, 0);
9909 else if (REG_P (part
[1][1]))
9910 part
[1][1] = gen_rtx_REG (DImode
, REGNO (part
[1][1]));
9913 if (GET_MODE (part
[1][0]) == SImode
)
9914 part
[1][0] = part
[1][1];
9917 emit_move_insn (part
[0][1], part
[1][1]);
9918 emit_move_insn (part
[0][0], part
[1][0]);
9922 /* Choose correct order to not overwrite the source before it is copied. */
9923 if ((REG_P (part
[0][0])
9924 && REG_P (part
[1][1])
9925 && (REGNO (part
[0][0]) == REGNO (part
[1][1])
9927 && REGNO (part
[0][0]) == REGNO (part
[1][2]))))
9929 && reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0))))
9933 operands
[2] = part
[0][2];
9934 operands
[3] = part
[0][1];
9935 operands
[4] = part
[0][0];
9936 operands
[5] = part
[1][2];
9937 operands
[6] = part
[1][1];
9938 operands
[7] = part
[1][0];
9942 operands
[2] = part
[0][1];
9943 operands
[3] = part
[0][0];
9944 operands
[5] = part
[1][1];
9945 operands
[6] = part
[1][0];
9952 operands
[2] = part
[0][0];
9953 operands
[3] = part
[0][1];
9954 operands
[4] = part
[0][2];
9955 operands
[5] = part
[1][0];
9956 operands
[6] = part
[1][1];
9957 operands
[7] = part
[1][2];
9961 operands
[2] = part
[0][0];
9962 operands
[3] = part
[0][1];
9963 operands
[5] = part
[1][0];
9964 operands
[6] = part
[1][1];
9968 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
9971 if (GET_CODE (operands
[5]) == CONST_INT
9972 && operands
[5] != const0_rtx
9973 && REG_P (operands
[2]))
9975 if (GET_CODE (operands
[6]) == CONST_INT
9976 && INTVAL (operands
[6]) == INTVAL (operands
[5]))
9977 operands
[6] = operands
[2];
9980 && GET_CODE (operands
[7]) == CONST_INT
9981 && INTVAL (operands
[7]) == INTVAL (operands
[5]))
9982 operands
[7] = operands
[2];
9986 && GET_CODE (operands
[6]) == CONST_INT
9987 && operands
[6] != const0_rtx
9988 && REG_P (operands
[3])
9989 && GET_CODE (operands
[7]) == CONST_INT
9990 && INTVAL (operands
[7]) == INTVAL (operands
[6]))
9991 operands
[7] = operands
[3];
9994 emit_move_insn (operands
[2], operands
[5]);
9995 emit_move_insn (operands
[3], operands
[6]);
9997 emit_move_insn (operands
[4], operands
[7]);
10002 /* Helper function of ix86_split_ashldi used to generate an SImode
10003 left shift by a constant, either using a single shift or
10004 a sequence of add instructions. */
10007 ix86_expand_ashlsi3_const (rtx operand
, int count
)
10010 emit_insn (gen_addsi3 (operand
, operand
, operand
));
10011 else if (!optimize_size
10012 && count
* ix86_cost
->add
<= ix86_cost
->shift_const
)
10015 for (i
=0; i
<count
; i
++)
10016 emit_insn (gen_addsi3 (operand
, operand
, operand
));
10019 emit_insn (gen_ashlsi3 (operand
, operand
, GEN_INT (count
)));
10023 ix86_split_ashldi (rtx
*operands
, rtx scratch
)
10025 rtx low
[2], high
[2];
10028 if (GET_CODE (operands
[2]) == CONST_INT
)
10030 split_di (operands
, 2, low
, high
);
10031 count
= INTVAL (operands
[2]) & 63;
10035 emit_move_insn (high
[0], low
[1]);
10036 emit_move_insn (low
[0], const0_rtx
);
10039 ix86_expand_ashlsi3_const (high
[0], count
- 32);
10043 if (!rtx_equal_p (operands
[0], operands
[1]))
10044 emit_move_insn (operands
[0], operands
[1]);
10045 emit_insn (gen_x86_shld_1 (high
[0], low
[0], GEN_INT (count
)));
10046 ix86_expand_ashlsi3_const (low
[0], count
);
10051 split_di (operands
, 1, low
, high
);
10053 if (operands
[1] == const1_rtx
)
10055 /* Assuming we've chosen a QImode capable registers, then 1LL << N
10056 can be done with two 32-bit shifts, no branches, no cmoves. */
10057 if (ANY_QI_REG_P (low
[0]) && ANY_QI_REG_P (high
[0]))
10059 rtx s
, d
, flags
= gen_rtx_REG (CCZmode
, FLAGS_REG
);
10061 ix86_expand_clear (low
[0]);
10062 ix86_expand_clear (high
[0]);
10063 emit_insn (gen_testqi_ccz_1 (operands
[2], GEN_INT (32)));
10065 d
= gen_lowpart (QImode
, low
[0]);
10066 d
= gen_rtx_STRICT_LOW_PART (VOIDmode
, d
);
10067 s
= gen_rtx_EQ (QImode
, flags
, const0_rtx
);
10068 emit_insn (gen_rtx_SET (VOIDmode
, d
, s
));
10070 d
= gen_lowpart (QImode
, high
[0]);
10071 d
= gen_rtx_STRICT_LOW_PART (VOIDmode
, d
);
10072 s
= gen_rtx_NE (QImode
, flags
, const0_rtx
);
10073 emit_insn (gen_rtx_SET (VOIDmode
, d
, s
));
10076 /* Otherwise, we can get the same results by manually performing
10077 a bit extract operation on bit 5, and then performing the two
10078 shifts. The two methods of getting 0/1 into low/high are exactly
10079 the same size. Avoiding the shift in the bit extract case helps
10080 pentium4 a bit; no one else seems to care much either way. */
10085 if (TARGET_PARTIAL_REG_STALL
&& !optimize_size
)
10086 x
= gen_rtx_ZERO_EXTEND (SImode
, operands
[2]);
10088 x
= gen_lowpart (SImode
, operands
[2]);
10089 emit_insn (gen_rtx_SET (VOIDmode
, high
[0], x
));
10091 emit_insn (gen_lshrsi3 (high
[0], high
[0], GEN_INT (5)));
10092 emit_insn (gen_andsi3 (high
[0], high
[0], GEN_INT (1)));
10093 emit_move_insn (low
[0], high
[0]);
10094 emit_insn (gen_xorsi3 (low
[0], low
[0], GEN_INT (1)));
10097 emit_insn (gen_ashlsi3 (low
[0], low
[0], operands
[2]));
10098 emit_insn (gen_ashlsi3 (high
[0], high
[0], operands
[2]));
10102 if (operands
[1] == constm1_rtx
)
10104 /* For -1LL << N, we can avoid the shld instruction, because we
10105 know that we're shifting 0...31 ones into a -1. */
10106 emit_move_insn (low
[0], constm1_rtx
);
10108 emit_move_insn (high
[0], low
[0]);
10110 emit_move_insn (high
[0], constm1_rtx
);
10114 if (!rtx_equal_p (operands
[0], operands
[1]))
10115 emit_move_insn (operands
[0], operands
[1]);
10117 split_di (operands
, 1, low
, high
);
10118 emit_insn (gen_x86_shld_1 (high
[0], low
[0], operands
[2]));
10121 emit_insn (gen_ashlsi3 (low
[0], low
[0], operands
[2]));
10123 if (TARGET_CMOVE
&& scratch
)
10125 ix86_expand_clear (scratch
);
10126 emit_insn (gen_x86_shift_adj_1 (high
[0], low
[0], operands
[2], scratch
));
10129 emit_insn (gen_x86_shift_adj_2 (high
[0], low
[0], operands
[2]));
10133 ix86_split_ashrdi (rtx
*operands
, rtx scratch
)
10135 rtx low
[2], high
[2];
10138 if (GET_CODE (operands
[2]) == CONST_INT
)
10140 split_di (operands
, 2, low
, high
);
10141 count
= INTVAL (operands
[2]) & 63;
10145 emit_move_insn (high
[0], high
[1]);
10146 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (31)));
10147 emit_move_insn (low
[0], high
[0]);
10150 else if (count
>= 32)
10152 emit_move_insn (low
[0], high
[1]);
10153 emit_move_insn (high
[0], low
[0]);
10154 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (31)));
10156 emit_insn (gen_ashrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
10160 if (!rtx_equal_p (operands
[0], operands
[1]))
10161 emit_move_insn (operands
[0], operands
[1]);
10162 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
10163 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (count
)));
10168 if (!rtx_equal_p (operands
[0], operands
[1]))
10169 emit_move_insn (operands
[0], operands
[1]);
10171 split_di (operands
, 1, low
, high
);
10173 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
10174 emit_insn (gen_ashrsi3 (high
[0], high
[0], operands
[2]));
10176 if (TARGET_CMOVE
&& scratch
)
10178 emit_move_insn (scratch
, high
[0]);
10179 emit_insn (gen_ashrsi3 (scratch
, scratch
, GEN_INT (31)));
10180 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
10184 emit_insn (gen_x86_shift_adj_3 (low
[0], high
[0], operands
[2]));
10189 ix86_split_lshrdi (rtx
*operands
, rtx scratch
)
10191 rtx low
[2], high
[2];
10194 if (GET_CODE (operands
[2]) == CONST_INT
)
10196 split_di (operands
, 2, low
, high
);
10197 count
= INTVAL (operands
[2]) & 63;
10201 emit_move_insn (low
[0], high
[1]);
10202 ix86_expand_clear (high
[0]);
10205 emit_insn (gen_lshrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
10209 if (!rtx_equal_p (operands
[0], operands
[1]))
10210 emit_move_insn (operands
[0], operands
[1]);
10211 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
10212 emit_insn (gen_lshrsi3 (high
[0], high
[0], GEN_INT (count
)));
10217 if (!rtx_equal_p (operands
[0], operands
[1]))
10218 emit_move_insn (operands
[0], operands
[1]);
10220 split_di (operands
, 1, low
, high
);
10222 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
10223 emit_insn (gen_lshrsi3 (high
[0], high
[0], operands
[2]));
10225 /* Heh. By reversing the arguments, we can reuse this pattern. */
10226 if (TARGET_CMOVE
&& scratch
)
10228 ix86_expand_clear (scratch
);
10229 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
10233 emit_insn (gen_x86_shift_adj_2 (low
[0], high
[0], operands
[2]));
10237 /* Helper function for the string operations below. Dest VARIABLE whether
10238 it is aligned to VALUE bytes. If true, jump to the label. */
10240 ix86_expand_aligntest (rtx variable
, int value
)
10242 rtx label
= gen_label_rtx ();
10243 rtx tmpcount
= gen_reg_rtx (GET_MODE (variable
));
10244 if (GET_MODE (variable
) == DImode
)
10245 emit_insn (gen_anddi3 (tmpcount
, variable
, GEN_INT (value
)));
10247 emit_insn (gen_andsi3 (tmpcount
, variable
, GEN_INT (value
)));
10248 emit_cmp_and_jump_insns (tmpcount
, const0_rtx
, EQ
, 0, GET_MODE (variable
),
10253 /* Adjust COUNTER by the VALUE. */
10255 ix86_adjust_counter (rtx countreg
, HOST_WIDE_INT value
)
10257 if (GET_MODE (countreg
) == DImode
)
10258 emit_insn (gen_adddi3 (countreg
, countreg
, GEN_INT (-value
)));
10260 emit_insn (gen_addsi3 (countreg
, countreg
, GEN_INT (-value
)));
10263 /* Zero extend possibly SImode EXP to Pmode register. */
10265 ix86_zero_extend_to_Pmode (rtx exp
)
10268 if (GET_MODE (exp
) == VOIDmode
)
10269 return force_reg (Pmode
, exp
);
10270 if (GET_MODE (exp
) == Pmode
)
10271 return copy_to_mode_reg (Pmode
, exp
);
10272 r
= gen_reg_rtx (Pmode
);
10273 emit_insn (gen_zero_extendsidi2 (r
, exp
));
10277 /* Expand string move (memcpy) operation. Use i386 string operations when
10278 profitable. expand_clrmem contains similar code. */
10280 ix86_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
)
10282 rtx srcreg
, destreg
, countreg
, srcexp
, destexp
;
10283 enum machine_mode counter_mode
;
10284 HOST_WIDE_INT align
= 0;
10285 unsigned HOST_WIDE_INT count
= 0;
10287 if (GET_CODE (align_exp
) == CONST_INT
)
10288 align
= INTVAL (align_exp
);
10290 /* Can't use any of this if the user has appropriated esi or edi. */
10291 if (global_regs
[4] || global_regs
[5])
10294 /* This simple hack avoids all inlining code and simplifies code below. */
10295 if (!TARGET_ALIGN_STRINGOPS
)
10298 if (GET_CODE (count_exp
) == CONST_INT
)
10300 count
= INTVAL (count_exp
);
10301 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
10305 /* Figure out proper mode for counter. For 32bits it is always SImode,
10306 for 64bits use SImode when possible, otherwise DImode.
10307 Set count to number of bytes copied when known at compile time. */
10309 || GET_MODE (count_exp
) == SImode
10310 || x86_64_zext_immediate_operand (count_exp
, VOIDmode
))
10311 counter_mode
= SImode
;
10313 counter_mode
= DImode
;
10315 if (counter_mode
!= SImode
&& counter_mode
!= DImode
)
10318 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
10319 if (destreg
!= XEXP (dst
, 0))
10320 dst
= replace_equiv_address_nv (dst
, destreg
);
10321 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
10322 if (srcreg
!= XEXP (src
, 0))
10323 src
= replace_equiv_address_nv (src
, srcreg
);
10325 /* When optimizing for size emit simple rep ; movsb instruction for
10326 counts not divisible by 4. */
10328 if ((!optimize
|| optimize_size
) && (count
== 0 || (count
& 0x03)))
10330 emit_insn (gen_cld ());
10331 countreg
= ix86_zero_extend_to_Pmode (count_exp
);
10332 destexp
= gen_rtx_PLUS (Pmode
, destreg
, countreg
);
10333 srcexp
= gen_rtx_PLUS (Pmode
, srcreg
, countreg
);
10334 emit_insn (gen_rep_mov (destreg
, dst
, srcreg
, src
, countreg
,
10338 /* For constant aligned (or small unaligned) copies use rep movsl
10339 followed by code copying the rest. For PentiumPro ensure 8 byte
10340 alignment to allow rep movsl acceleration. */
10342 else if (count
!= 0
10344 || (!TARGET_PENTIUMPRO
&& !TARGET_64BIT
&& align
>= 4)
10345 || optimize_size
|| count
< (unsigned int) 64))
10347 unsigned HOST_WIDE_INT offset
= 0;
10348 int size
= TARGET_64BIT
&& !optimize_size
? 8 : 4;
10349 rtx srcmem
, dstmem
;
10351 emit_insn (gen_cld ());
10352 if (count
& ~(size
- 1))
10354 countreg
= copy_to_mode_reg (counter_mode
,
10355 GEN_INT ((count
>> (size
== 4 ? 2 : 3))
10356 & (TARGET_64BIT
? -1 : 0x3fffffff)));
10357 countreg
= ix86_zero_extend_to_Pmode (countreg
);
10359 destexp
= gen_rtx_ASHIFT (Pmode
, countreg
,
10360 GEN_INT (size
== 4 ? 2 : 3));
10361 srcexp
= gen_rtx_PLUS (Pmode
, destexp
, srcreg
);
10362 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10364 emit_insn (gen_rep_mov (destreg
, dst
, srcreg
, src
,
10365 countreg
, destexp
, srcexp
));
10366 offset
= count
& ~(size
- 1);
10368 if (size
== 8 && (count
& 0x04))
10370 srcmem
= adjust_automodify_address_nv (src
, SImode
, srcreg
,
10372 dstmem
= adjust_automodify_address_nv (dst
, SImode
, destreg
,
10374 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10379 srcmem
= adjust_automodify_address_nv (src
, HImode
, srcreg
,
10381 dstmem
= adjust_automodify_address_nv (dst
, HImode
, destreg
,
10383 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10388 srcmem
= adjust_automodify_address_nv (src
, QImode
, srcreg
,
10390 dstmem
= adjust_automodify_address_nv (dst
, QImode
, destreg
,
10392 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10395 /* The generic code based on the glibc implementation:
10396 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
10397 allowing accelerated copying there)
10398 - copy the data using rep movsl
10399 - copy the rest. */
10404 rtx srcmem
, dstmem
;
10405 int desired_alignment
= (TARGET_PENTIUMPRO
10406 && (count
== 0 || count
>= (unsigned int) 260)
10407 ? 8 : UNITS_PER_WORD
);
10408 /* Get rid of MEM_OFFSETs, they won't be accurate. */
10409 dst
= change_address (dst
, BLKmode
, destreg
);
10410 src
= change_address (src
, BLKmode
, srcreg
);
10412 /* In case we don't know anything about the alignment, default to
10413 library version, since it is usually equally fast and result in
10416 Also emit call when we know that the count is large and call overhead
10417 will not be important. */
10418 if (!TARGET_INLINE_ALL_STRINGOPS
10419 && (align
< UNITS_PER_WORD
|| !TARGET_REP_MOVL_OPTIMAL
))
10422 if (TARGET_SINGLE_STRINGOP
)
10423 emit_insn (gen_cld ());
10425 countreg2
= gen_reg_rtx (Pmode
);
10426 countreg
= copy_to_mode_reg (counter_mode
, count_exp
);
10428 /* We don't use loops to align destination and to copy parts smaller
10429 than 4 bytes, because gcc is able to optimize such code better (in
10430 the case the destination or the count really is aligned, gcc is often
10431 able to predict the branches) and also it is friendlier to the
10432 hardware branch prediction.
10434 Using loops is beneficial for generic case, because we can
10435 handle small counts using the loops. Many CPUs (such as Athlon)
10436 have large REP prefix setup costs.
10438 This is quite costly. Maybe we can revisit this decision later or
10439 add some customizability to this code. */
10441 if (count
== 0 && align
< desired_alignment
)
10443 label
= gen_label_rtx ();
10444 emit_cmp_and_jump_insns (countreg
, GEN_INT (desired_alignment
- 1),
10445 LEU
, 0, counter_mode
, 1, label
);
10449 rtx label
= ix86_expand_aligntest (destreg
, 1);
10450 srcmem
= change_address (src
, QImode
, srcreg
);
10451 dstmem
= change_address (dst
, QImode
, destreg
);
10452 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10453 ix86_adjust_counter (countreg
, 1);
10454 emit_label (label
);
10455 LABEL_NUSES (label
) = 1;
10459 rtx label
= ix86_expand_aligntest (destreg
, 2);
10460 srcmem
= change_address (src
, HImode
, srcreg
);
10461 dstmem
= change_address (dst
, HImode
, destreg
);
10462 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10463 ix86_adjust_counter (countreg
, 2);
10464 emit_label (label
);
10465 LABEL_NUSES (label
) = 1;
10467 if (align
<= 4 && desired_alignment
> 4)
10469 rtx label
= ix86_expand_aligntest (destreg
, 4);
10470 srcmem
= change_address (src
, SImode
, srcreg
);
10471 dstmem
= change_address (dst
, SImode
, destreg
);
10472 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10473 ix86_adjust_counter (countreg
, 4);
10474 emit_label (label
);
10475 LABEL_NUSES (label
) = 1;
10478 if (label
&& desired_alignment
> 4 && !TARGET_64BIT
)
10480 emit_label (label
);
10481 LABEL_NUSES (label
) = 1;
10484 if (!TARGET_SINGLE_STRINGOP
)
10485 emit_insn (gen_cld ());
10488 emit_insn (gen_lshrdi3 (countreg2
, ix86_zero_extend_to_Pmode (countreg
),
10490 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, GEN_INT (3));
10494 emit_insn (gen_lshrsi3 (countreg2
, countreg
, const2_rtx
));
10495 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, const2_rtx
);
10497 srcexp
= gen_rtx_PLUS (Pmode
, destexp
, srcreg
);
10498 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10499 emit_insn (gen_rep_mov (destreg
, dst
, srcreg
, src
,
10500 countreg2
, destexp
, srcexp
));
10504 emit_label (label
);
10505 LABEL_NUSES (label
) = 1;
10507 if (TARGET_64BIT
&& align
> 4 && count
!= 0 && (count
& 4))
10509 srcmem
= change_address (src
, SImode
, srcreg
);
10510 dstmem
= change_address (dst
, SImode
, destreg
);
10511 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10513 if ((align
<= 4 || count
== 0) && TARGET_64BIT
)
10515 rtx label
= ix86_expand_aligntest (countreg
, 4);
10516 srcmem
= change_address (src
, SImode
, srcreg
);
10517 dstmem
= change_address (dst
, SImode
, destreg
);
10518 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10519 emit_label (label
);
10520 LABEL_NUSES (label
) = 1;
10522 if (align
> 2 && count
!= 0 && (count
& 2))
10524 srcmem
= change_address (src
, HImode
, srcreg
);
10525 dstmem
= change_address (dst
, HImode
, destreg
);
10526 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10528 if (align
<= 2 || count
== 0)
10530 rtx label
= ix86_expand_aligntest (countreg
, 2);
10531 srcmem
= change_address (src
, HImode
, srcreg
);
10532 dstmem
= change_address (dst
, HImode
, destreg
);
10533 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10534 emit_label (label
);
10535 LABEL_NUSES (label
) = 1;
10537 if (align
> 1 && count
!= 0 && (count
& 1))
10539 srcmem
= change_address (src
, QImode
, srcreg
);
10540 dstmem
= change_address (dst
, QImode
, destreg
);
10541 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10543 if (align
<= 1 || count
== 0)
10545 rtx label
= ix86_expand_aligntest (countreg
, 1);
10546 srcmem
= change_address (src
, QImode
, srcreg
);
10547 dstmem
= change_address (dst
, QImode
, destreg
);
10548 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10549 emit_label (label
);
10550 LABEL_NUSES (label
) = 1;
10557 /* Expand string clear operation (bzero). Use i386 string operations when
10558 profitable. expand_movmem contains similar code. */
10560 ix86_expand_clrmem (rtx dst
, rtx count_exp
, rtx align_exp
)
10562 rtx destreg
, zeroreg
, countreg
, destexp
;
10563 enum machine_mode counter_mode
;
10564 HOST_WIDE_INT align
= 0;
10565 unsigned HOST_WIDE_INT count
= 0;
10567 if (GET_CODE (align_exp
) == CONST_INT
)
10568 align
= INTVAL (align_exp
);
10570 /* Can't use any of this if the user has appropriated esi. */
10571 if (global_regs
[4])
10574 /* This simple hack avoids all inlining code and simplifies code below. */
10575 if (!TARGET_ALIGN_STRINGOPS
)
10578 if (GET_CODE (count_exp
) == CONST_INT
)
10580 count
= INTVAL (count_exp
);
10581 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
10584 /* Figure out proper mode for counter. For 32bits it is always SImode,
10585 for 64bits use SImode when possible, otherwise DImode.
10586 Set count to number of bytes copied when known at compile time. */
10588 || GET_MODE (count_exp
) == SImode
10589 || x86_64_zext_immediate_operand (count_exp
, VOIDmode
))
10590 counter_mode
= SImode
;
10592 counter_mode
= DImode
;
10594 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
10595 if (destreg
!= XEXP (dst
, 0))
10596 dst
= replace_equiv_address_nv (dst
, destreg
);
10599 /* When optimizing for size emit simple rep ; movsb instruction for
10600 counts not divisible by 4. The movl $N, %ecx; rep; stosb
10601 sequence is 7 bytes long, so if optimizing for size and count is
10602 small enough that some stosl, stosw and stosb instructions without
10603 rep are shorter, fall back into the next if. */
10605 if ((!optimize
|| optimize_size
)
10608 && (!optimize_size
|| (count
& 0x03) + (count
>> 2) > 7))))
10610 emit_insn (gen_cld ());
10612 countreg
= ix86_zero_extend_to_Pmode (count_exp
);
10613 zeroreg
= copy_to_mode_reg (QImode
, const0_rtx
);
10614 destexp
= gen_rtx_PLUS (Pmode
, destreg
, countreg
);
10615 emit_insn (gen_rep_stos (destreg
, countreg
, dst
, zeroreg
, destexp
));
10617 else if (count
!= 0
10619 || (!TARGET_PENTIUMPRO
&& !TARGET_64BIT
&& align
>= 4)
10620 || optimize_size
|| count
< (unsigned int) 64))
10622 int size
= TARGET_64BIT
&& !optimize_size
? 8 : 4;
10623 unsigned HOST_WIDE_INT offset
= 0;
10625 emit_insn (gen_cld ());
10627 zeroreg
= copy_to_mode_reg (size
== 4 ? SImode
: DImode
, const0_rtx
);
10628 if (count
& ~(size
- 1))
10630 unsigned HOST_WIDE_INT repcount
;
10631 unsigned int max_nonrep
;
10633 repcount
= count
>> (size
== 4 ? 2 : 3);
10635 repcount
&= 0x3fffffff;
10637 /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes.
10638 movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN
10639 bytes. In both cases the latter seems to be faster for small
10641 max_nonrep
= size
== 4 ? 7 : 4;
10642 if (!optimize_size
)
10645 case PROCESSOR_PENTIUM4
:
10646 case PROCESSOR_NOCONA
:
10653 if (repcount
<= max_nonrep
)
10654 while (repcount
-- > 0)
10656 rtx mem
= adjust_automodify_address_nv (dst
,
10657 GET_MODE (zeroreg
),
10659 emit_insn (gen_strset (destreg
, mem
, zeroreg
));
10664 countreg
= copy_to_mode_reg (counter_mode
, GEN_INT (repcount
));
10665 countreg
= ix86_zero_extend_to_Pmode (countreg
);
10666 destexp
= gen_rtx_ASHIFT (Pmode
, countreg
,
10667 GEN_INT (size
== 4 ? 2 : 3));
10668 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10669 emit_insn (gen_rep_stos (destreg
, countreg
, dst
, zeroreg
,
10671 offset
= count
& ~(size
- 1);
10674 if (size
== 8 && (count
& 0x04))
10676 rtx mem
= adjust_automodify_address_nv (dst
, SImode
, destreg
,
10678 emit_insn (gen_strset (destreg
, mem
,
10679 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
10684 rtx mem
= adjust_automodify_address_nv (dst
, HImode
, destreg
,
10686 emit_insn (gen_strset (destreg
, mem
,
10687 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10692 rtx mem
= adjust_automodify_address_nv (dst
, QImode
, destreg
,
10694 emit_insn (gen_strset (destreg
, mem
,
10695 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10702 /* Compute desired alignment of the string operation. */
10703 int desired_alignment
= (TARGET_PENTIUMPRO
10704 && (count
== 0 || count
>= (unsigned int) 260)
10705 ? 8 : UNITS_PER_WORD
);
10707 /* In case we don't know anything about the alignment, default to
10708 library version, since it is usually equally fast and result in
10711 Also emit call when we know that the count is large and call overhead
10712 will not be important. */
10713 if (!TARGET_INLINE_ALL_STRINGOPS
10714 && (align
< UNITS_PER_WORD
|| !TARGET_REP_MOVL_OPTIMAL
))
10717 if (TARGET_SINGLE_STRINGOP
)
10718 emit_insn (gen_cld ());
10720 countreg2
= gen_reg_rtx (Pmode
);
10721 countreg
= copy_to_mode_reg (counter_mode
, count_exp
);
10722 zeroreg
= copy_to_mode_reg (Pmode
, const0_rtx
);
10723 /* Get rid of MEM_OFFSET, it won't be accurate. */
10724 dst
= change_address (dst
, BLKmode
, destreg
);
10726 if (count
== 0 && align
< desired_alignment
)
10728 label
= gen_label_rtx ();
10729 emit_cmp_and_jump_insns (countreg
, GEN_INT (desired_alignment
- 1),
10730 LEU
, 0, counter_mode
, 1, label
);
10734 rtx label
= ix86_expand_aligntest (destreg
, 1);
10735 emit_insn (gen_strset (destreg
, dst
,
10736 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10737 ix86_adjust_counter (countreg
, 1);
10738 emit_label (label
);
10739 LABEL_NUSES (label
) = 1;
10743 rtx label
= ix86_expand_aligntest (destreg
, 2);
10744 emit_insn (gen_strset (destreg
, dst
,
10745 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10746 ix86_adjust_counter (countreg
, 2);
10747 emit_label (label
);
10748 LABEL_NUSES (label
) = 1;
10750 if (align
<= 4 && desired_alignment
> 4)
10752 rtx label
= ix86_expand_aligntest (destreg
, 4);
10753 emit_insn (gen_strset (destreg
, dst
,
10755 ? gen_rtx_SUBREG (SImode
, zeroreg
, 0)
10757 ix86_adjust_counter (countreg
, 4);
10758 emit_label (label
);
10759 LABEL_NUSES (label
) = 1;
10762 if (label
&& desired_alignment
> 4 && !TARGET_64BIT
)
10764 emit_label (label
);
10765 LABEL_NUSES (label
) = 1;
10769 if (!TARGET_SINGLE_STRINGOP
)
10770 emit_insn (gen_cld ());
10773 emit_insn (gen_lshrdi3 (countreg2
, ix86_zero_extend_to_Pmode (countreg
),
10775 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, GEN_INT (3));
10779 emit_insn (gen_lshrsi3 (countreg2
, countreg
, const2_rtx
));
10780 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, const2_rtx
);
10782 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10783 emit_insn (gen_rep_stos (destreg
, countreg2
, dst
, zeroreg
, destexp
));
10787 emit_label (label
);
10788 LABEL_NUSES (label
) = 1;
10791 if (TARGET_64BIT
&& align
> 4 && count
!= 0 && (count
& 4))
10792 emit_insn (gen_strset (destreg
, dst
,
10793 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
10794 if (TARGET_64BIT
&& (align
<= 4 || count
== 0))
10796 rtx label
= ix86_expand_aligntest (countreg
, 4);
10797 emit_insn (gen_strset (destreg
, dst
,
10798 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
10799 emit_label (label
);
10800 LABEL_NUSES (label
) = 1;
10802 if (align
> 2 && count
!= 0 && (count
& 2))
10803 emit_insn (gen_strset (destreg
, dst
,
10804 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10805 if (align
<= 2 || count
== 0)
10807 rtx label
= ix86_expand_aligntest (countreg
, 2);
10808 emit_insn (gen_strset (destreg
, dst
,
10809 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10810 emit_label (label
);
10811 LABEL_NUSES (label
) = 1;
10813 if (align
> 1 && count
!= 0 && (count
& 1))
10814 emit_insn (gen_strset (destreg
, dst
,
10815 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10816 if (align
<= 1 || count
== 0)
10818 rtx label
= ix86_expand_aligntest (countreg
, 1);
10819 emit_insn (gen_strset (destreg
, dst
,
10820 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10821 emit_label (label
);
10822 LABEL_NUSES (label
) = 1;
10828 /* Expand strlen. */
10830 ix86_expand_strlen (rtx out
, rtx src
, rtx eoschar
, rtx align
)
10832 rtx addr
, scratch1
, scratch2
, scratch3
, scratch4
;
10834 /* The generic case of strlen expander is long. Avoid it's
10835 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
10837 if (TARGET_UNROLL_STRLEN
&& eoschar
== const0_rtx
&& optimize
> 1
10838 && !TARGET_INLINE_ALL_STRINGOPS
10840 && (GET_CODE (align
) != CONST_INT
|| INTVAL (align
) < 4))
10843 addr
= force_reg (Pmode
, XEXP (src
, 0));
10844 scratch1
= gen_reg_rtx (Pmode
);
10846 if (TARGET_UNROLL_STRLEN
&& eoschar
== const0_rtx
&& optimize
> 1
10849 /* Well it seems that some optimizer does not combine a call like
10850 foo(strlen(bar), strlen(bar));
10851 when the move and the subtraction is done here. It does calculate
10852 the length just once when these instructions are done inside of
10853 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
10854 often used and I use one fewer register for the lifetime of
10855 output_strlen_unroll() this is better. */
10857 emit_move_insn (out
, addr
);
10859 ix86_expand_strlensi_unroll_1 (out
, src
, align
);
10861 /* strlensi_unroll_1 returns the address of the zero at the end of
10862 the string, like memchr(), so compute the length by subtracting
10863 the start address. */
10865 emit_insn (gen_subdi3 (out
, out
, addr
));
10867 emit_insn (gen_subsi3 (out
, out
, addr
));
10872 scratch2
= gen_reg_rtx (Pmode
);
10873 scratch3
= gen_reg_rtx (Pmode
);
10874 scratch4
= force_reg (Pmode
, constm1_rtx
);
10876 emit_move_insn (scratch3
, addr
);
10877 eoschar
= force_reg (QImode
, eoschar
);
10879 emit_insn (gen_cld ());
10880 src
= replace_equiv_address_nv (src
, scratch3
);
10882 /* If .md starts supporting :P, this can be done in .md. */
10883 unspec
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (4, src
, eoschar
, align
,
10884 scratch4
), UNSPEC_SCAS
);
10885 emit_insn (gen_strlenqi_1 (scratch1
, scratch3
, unspec
));
10888 emit_insn (gen_one_cmpldi2 (scratch2
, scratch1
));
10889 emit_insn (gen_adddi3 (out
, scratch2
, constm1_rtx
));
10893 emit_insn (gen_one_cmplsi2 (scratch2
, scratch1
));
10894 emit_insn (gen_addsi3 (out
, scratch2
, constm1_rtx
));
10900 /* Expand the appropriate insns for doing strlen if not just doing
10903 out = result, initialized with the start address
10904 align_rtx = alignment of the address.
10905 scratch = scratch register, initialized with the startaddress when
10906 not aligned, otherwise undefined
10908 This is just the body. It needs the initializations mentioned above and
10909 some address computing at the end. These things are done in i386.md. */
10912 ix86_expand_strlensi_unroll_1 (rtx out
, rtx src
, rtx align_rtx
)
10916 rtx align_2_label
= NULL_RTX
;
10917 rtx align_3_label
= NULL_RTX
;
10918 rtx align_4_label
= gen_label_rtx ();
10919 rtx end_0_label
= gen_label_rtx ();
10921 rtx tmpreg
= gen_reg_rtx (SImode
);
10922 rtx scratch
= gen_reg_rtx (SImode
);
10926 if (GET_CODE (align_rtx
) == CONST_INT
)
10927 align
= INTVAL (align_rtx
);
10929 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
10931 /* Is there a known alignment and is it less than 4? */
10934 rtx scratch1
= gen_reg_rtx (Pmode
);
10935 emit_move_insn (scratch1
, out
);
10936 /* Is there a known alignment and is it not 2? */
10939 align_3_label
= gen_label_rtx (); /* Label when aligned to 3-byte */
10940 align_2_label
= gen_label_rtx (); /* Label when aligned to 2-byte */
10942 /* Leave just the 3 lower bits. */
10943 align_rtx
= expand_binop (Pmode
, and_optab
, scratch1
, GEN_INT (3),
10944 NULL_RTX
, 0, OPTAB_WIDEN
);
10946 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
10947 Pmode
, 1, align_4_label
);
10948 emit_cmp_and_jump_insns (align_rtx
, const2_rtx
, EQ
, NULL
,
10949 Pmode
, 1, align_2_label
);
10950 emit_cmp_and_jump_insns (align_rtx
, const2_rtx
, GTU
, NULL
,
10951 Pmode
, 1, align_3_label
);
10955 /* Since the alignment is 2, we have to check 2 or 0 bytes;
10956 check if is aligned to 4 - byte. */
10958 align_rtx
= expand_binop (Pmode
, and_optab
, scratch1
, const2_rtx
,
10959 NULL_RTX
, 0, OPTAB_WIDEN
);
10961 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
10962 Pmode
, 1, align_4_label
);
10965 mem
= change_address (src
, QImode
, out
);
10967 /* Now compare the bytes. */
10969 /* Compare the first n unaligned byte on a byte per byte basis. */
10970 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
,
10971 QImode
, 1, end_0_label
);
10973 /* Increment the address. */
10975 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
10977 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
10979 /* Not needed with an alignment of 2 */
10982 emit_label (align_2_label
);
10984 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
, QImode
, 1,
10988 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
10990 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
10992 emit_label (align_3_label
);
10995 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
, QImode
, 1,
10999 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
11001 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
11004 /* Generate loop to check 4 bytes at a time. It is not a good idea to
11005 align this loop. It gives only huge programs, but does not help to
11007 emit_label (align_4_label
);
11009 mem
= change_address (src
, SImode
, out
);
11010 emit_move_insn (scratch
, mem
);
11012 emit_insn (gen_adddi3 (out
, out
, GEN_INT (4)));
11014 emit_insn (gen_addsi3 (out
, out
, GEN_INT (4)));
11016 /* This formula yields a nonzero result iff one of the bytes is zero.
11017 This saves three branches inside loop and many cycles. */
11019 emit_insn (gen_addsi3 (tmpreg
, scratch
, GEN_INT (-0x01010101)));
11020 emit_insn (gen_one_cmplsi2 (scratch
, scratch
));
11021 emit_insn (gen_andsi3 (tmpreg
, tmpreg
, scratch
));
11022 emit_insn (gen_andsi3 (tmpreg
, tmpreg
,
11023 gen_int_mode (0x80808080, SImode
)));
11024 emit_cmp_and_jump_insns (tmpreg
, const0_rtx
, EQ
, 0, SImode
, 1,
11029 rtx reg
= gen_reg_rtx (SImode
);
11030 rtx reg2
= gen_reg_rtx (Pmode
);
11031 emit_move_insn (reg
, tmpreg
);
11032 emit_insn (gen_lshrsi3 (reg
, reg
, GEN_INT (16)));
11034 /* If zero is not in the first two bytes, move two bytes forward. */
11035 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
11036 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
11037 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
11038 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
,
11039 gen_rtx_IF_THEN_ELSE (SImode
, tmp
,
11042 /* Emit lea manually to avoid clobbering of flags. */
11043 emit_insn (gen_rtx_SET (SImode
, reg2
,
11044 gen_rtx_PLUS (Pmode
, out
, const2_rtx
)));
11046 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
11047 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
11048 emit_insn (gen_rtx_SET (VOIDmode
, out
,
11049 gen_rtx_IF_THEN_ELSE (Pmode
, tmp
,
11056 rtx end_2_label
= gen_label_rtx ();
11057 /* Is zero in the first two bytes? */
11059 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
11060 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
11061 tmp
= gen_rtx_NE (VOIDmode
, tmp
, const0_rtx
);
11062 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
11063 gen_rtx_LABEL_REF (VOIDmode
, end_2_label
),
11065 tmp
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
11066 JUMP_LABEL (tmp
) = end_2_label
;
11068 /* Not in the first two. Move two bytes forward. */
11069 emit_insn (gen_lshrsi3 (tmpreg
, tmpreg
, GEN_INT (16)));
11071 emit_insn (gen_adddi3 (out
, out
, const2_rtx
));
11073 emit_insn (gen_addsi3 (out
, out
, const2_rtx
));
11075 emit_label (end_2_label
);
11079 /* Avoid branch in fixing the byte. */
11080 tmpreg
= gen_lowpart (QImode
, tmpreg
);
11081 emit_insn (gen_addqi3_cc (tmpreg
, tmpreg
, tmpreg
));
11082 cmp
= gen_rtx_LTU (Pmode
, gen_rtx_REG (CCmode
, 17), const0_rtx
);
11084 emit_insn (gen_subdi3_carry_rex64 (out
, out
, GEN_INT (3), cmp
));
11086 emit_insn (gen_subsi3_carry (out
, out
, GEN_INT (3), cmp
));
11088 emit_label (end_0_label
);
11092 ix86_expand_call (rtx retval
, rtx fnaddr
, rtx callarg1
,
11093 rtx callarg2 ATTRIBUTE_UNUSED
,
11094 rtx pop
, int sibcall
)
11096 rtx use
= NULL
, call
;
11098 if (pop
== const0_rtx
)
11100 if (TARGET_64BIT
&& pop
)
11104 if (flag_pic
&& GET_CODE (XEXP (fnaddr
, 0)) == SYMBOL_REF
)
11105 fnaddr
= machopic_indirect_call_target (fnaddr
);
11107 /* Static functions and indirect calls don't need the pic register. */
11108 if (! TARGET_64BIT
&& flag_pic
11109 && GET_CODE (XEXP (fnaddr
, 0)) == SYMBOL_REF
11110 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr
, 0)))
11111 use_reg (&use
, pic_offset_table_rtx
);
11113 if (TARGET_64BIT
&& INTVAL (callarg2
) >= 0)
11115 rtx al
= gen_rtx_REG (QImode
, 0);
11116 emit_move_insn (al
, callarg2
);
11117 use_reg (&use
, al
);
11119 #endif /* TARGET_MACHO */
11121 if (! call_insn_operand (XEXP (fnaddr
, 0), Pmode
))
11123 fnaddr
= copy_to_mode_reg (Pmode
, XEXP (fnaddr
, 0));
11124 fnaddr
= gen_rtx_MEM (QImode
, fnaddr
);
11126 if (sibcall
&& TARGET_64BIT
11127 && !constant_call_address_operand (XEXP (fnaddr
, 0), Pmode
))
11130 addr
= copy_to_mode_reg (Pmode
, XEXP (fnaddr
, 0));
11131 fnaddr
= gen_rtx_REG (Pmode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
11132 emit_move_insn (fnaddr
, addr
);
11133 fnaddr
= gen_rtx_MEM (QImode
, fnaddr
);
11136 call
= gen_rtx_CALL (VOIDmode
, fnaddr
, callarg1
);
11138 call
= gen_rtx_SET (VOIDmode
, retval
, call
);
11141 pop
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, pop
);
11142 pop
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, pop
);
11143 call
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, call
, pop
));
11146 call
= emit_call_insn (call
);
11148 CALL_INSN_FUNCTION_USAGE (call
) = use
;
11152 /* Clear stack slot assignments remembered from previous functions.
11153 This is called from INIT_EXPANDERS once before RTL is emitted for each
11156 static struct machine_function
*
11157 ix86_init_machine_status (void)
11159 struct machine_function
*f
;
11161 f
= ggc_alloc_cleared (sizeof (struct machine_function
));
11162 f
->use_fast_prologue_epilogue_nregs
= -1;
11167 /* Return a MEM corresponding to a stack slot with mode MODE.
11168 Allocate a new slot if necessary.
11170 The RTL for a function can have several slots available: N is
11171 which slot to use. */
11174 assign_386_stack_local (enum machine_mode mode
, int n
)
11176 struct stack_local_entry
*s
;
11178 if (n
< 0 || n
>= MAX_386_STACK_LOCALS
)
11181 for (s
= ix86_stack_locals
; s
; s
= s
->next
)
11182 if (s
->mode
== mode
&& s
->n
== n
)
11185 s
= (struct stack_local_entry
*)
11186 ggc_alloc (sizeof (struct stack_local_entry
));
11189 s
->rtl
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
11191 s
->next
= ix86_stack_locals
;
11192 ix86_stack_locals
= s
;
11196 /* Construct the SYMBOL_REF for the tls_get_addr function. */
11198 static GTY(()) rtx ix86_tls_symbol
;
11200 ix86_tls_get_addr (void)
11203 if (!ix86_tls_symbol
)
11205 ix86_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
,
11206 (TARGET_GNU_TLS
&& !TARGET_64BIT
)
11207 ? "___tls_get_addr"
11208 : "__tls_get_addr");
11211 return ix86_tls_symbol
;
11214 /* Calculate the length of the memory address in the instruction
11215 encoding. Does not include the one-byte modrm, opcode, or prefix. */
11218 memory_address_length (rtx addr
)
11220 struct ix86_address parts
;
11221 rtx base
, index
, disp
;
11224 if (GET_CODE (addr
) == PRE_DEC
11225 || GET_CODE (addr
) == POST_INC
11226 || GET_CODE (addr
) == PRE_MODIFY
11227 || GET_CODE (addr
) == POST_MODIFY
)
11230 if (! ix86_decompose_address (addr
, &parts
))
11234 index
= parts
.index
;
11239 - esp as the base always wants an index,
11240 - ebp as the base always wants a displacement. */
11242 /* Register Indirect. */
11243 if (base
&& !index
&& !disp
)
11245 /* esp (for its index) and ebp (for its displacement) need
11246 the two-byte modrm form. */
11247 if (addr
== stack_pointer_rtx
11248 || addr
== arg_pointer_rtx
11249 || addr
== frame_pointer_rtx
11250 || addr
== hard_frame_pointer_rtx
)
11254 /* Direct Addressing. */
11255 else if (disp
&& !base
&& !index
)
11260 /* Find the length of the displacement constant. */
11263 if (GET_CODE (disp
) == CONST_INT
11264 && CONST_OK_FOR_LETTER_P (INTVAL (disp
), 'K')
11270 /* ebp always wants a displacement. */
11271 else if (base
== hard_frame_pointer_rtx
)
11274 /* An index requires the two-byte modrm form.... */
11276 /* ...like esp, which always wants an index. */
11277 || base
== stack_pointer_rtx
11278 || base
== arg_pointer_rtx
11279 || base
== frame_pointer_rtx
)
11286 /* Compute default value for "length_immediate" attribute. When SHORTFORM
11287 is set, expect that insn have 8bit immediate alternative. */
11289 ix86_attr_length_immediate_default (rtx insn
, int shortform
)
11293 extract_insn_cached (insn
);
11294 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
11295 if (CONSTANT_P (recog_data
.operand
[i
]))
11300 && GET_CODE (recog_data
.operand
[i
]) == CONST_INT
11301 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data
.operand
[i
]), 'K'))
11305 switch (get_attr_mode (insn
))
11316 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
11321 fatal_insn ("unknown insn mode", insn
);
11327 /* Compute default value for "length_address" attribute. */
11329 ix86_attr_length_address_default (rtx insn
)
11333 if (get_attr_type (insn
) == TYPE_LEA
)
11335 rtx set
= PATTERN (insn
);
11336 if (GET_CODE (set
) == SET
)
11338 else if (GET_CODE (set
) == PARALLEL
11339 && GET_CODE (XVECEXP (set
, 0, 0)) == SET
)
11340 set
= XVECEXP (set
, 0, 0);
11343 #ifdef ENABLE_CHECKING
11349 return memory_address_length (SET_SRC (set
));
11352 extract_insn_cached (insn
);
11353 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
11354 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
11356 return memory_address_length (XEXP (recog_data
.operand
[i
], 0));
11362 /* Return the maximum number of instructions a cpu can issue. */
11365 ix86_issue_rate (void)
11369 case PROCESSOR_PENTIUM
:
11373 case PROCESSOR_PENTIUMPRO
:
11374 case PROCESSOR_PENTIUM4
:
11375 case PROCESSOR_ATHLON
:
11377 case PROCESSOR_NOCONA
:
11385 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
11386 by DEP_INSN and nothing set by DEP_INSN. */
11389 ix86_flags_dependant (rtx insn
, rtx dep_insn
, enum attr_type insn_type
)
11393 /* Simplify the test for uninteresting insns. */
11394 if (insn_type
!= TYPE_SETCC
11395 && insn_type
!= TYPE_ICMOV
11396 && insn_type
!= TYPE_FCMOV
11397 && insn_type
!= TYPE_IBR
)
11400 if ((set
= single_set (dep_insn
)) != 0)
11402 set
= SET_DEST (set
);
11405 else if (GET_CODE (PATTERN (dep_insn
)) == PARALLEL
11406 && XVECLEN (PATTERN (dep_insn
), 0) == 2
11407 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 0)) == SET
11408 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 1)) == SET
)
11410 set
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
11411 set2
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
11416 if (GET_CODE (set
) != REG
|| REGNO (set
) != FLAGS_REG
)
11419 /* This test is true if the dependent insn reads the flags but
11420 not any other potentially set register. */
11421 if (!reg_overlap_mentioned_p (set
, PATTERN (insn
)))
11424 if (set2
&& reg_overlap_mentioned_p (set2
, PATTERN (insn
)))
11430 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
11431 address with operands set by DEP_INSN. */
11434 ix86_agi_dependant (rtx insn
, rtx dep_insn
, enum attr_type insn_type
)
11438 if (insn_type
== TYPE_LEA
11441 addr
= PATTERN (insn
);
11442 if (GET_CODE (addr
) == SET
)
11444 else if (GET_CODE (addr
) == PARALLEL
11445 && GET_CODE (XVECEXP (addr
, 0, 0)) == SET
)
11446 addr
= XVECEXP (addr
, 0, 0);
11449 addr
= SET_SRC (addr
);
11454 extract_insn_cached (insn
);
11455 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
11456 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
11458 addr
= XEXP (recog_data
.operand
[i
], 0);
11465 return modified_in_p (addr
, dep_insn
);
11469 ix86_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
11471 enum attr_type insn_type
, dep_insn_type
;
11472 enum attr_memory memory
;
11474 int dep_insn_code_number
;
11476 /* Anti and output dependencies have zero cost on all CPUs. */
11477 if (REG_NOTE_KIND (link
) != 0)
11480 dep_insn_code_number
= recog_memoized (dep_insn
);
11482 /* If we can't recognize the insns, we can't really do anything. */
11483 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
11486 insn_type
= get_attr_type (insn
);
11487 dep_insn_type
= get_attr_type (dep_insn
);
11491 case PROCESSOR_PENTIUM
:
11492 /* Address Generation Interlock adds a cycle of latency. */
11493 if (ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11496 /* ??? Compares pair with jump/setcc. */
11497 if (ix86_flags_dependant (insn
, dep_insn
, insn_type
))
11500 /* Floating point stores require value to be ready one cycle earlier. */
11501 if (insn_type
== TYPE_FMOV
11502 && get_attr_memory (insn
) == MEMORY_STORE
11503 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11507 case PROCESSOR_PENTIUMPRO
:
11508 memory
= get_attr_memory (insn
);
11510 /* INT->FP conversion is expensive. */
11511 if (get_attr_fp_int_src (dep_insn
))
11514 /* There is one cycle extra latency between an FP op and a store. */
11515 if (insn_type
== TYPE_FMOV
11516 && (set
= single_set (dep_insn
)) != NULL_RTX
11517 && (set2
= single_set (insn
)) != NULL_RTX
11518 && rtx_equal_p (SET_DEST (set
), SET_SRC (set2
))
11519 && GET_CODE (SET_DEST (set2
)) == MEM
)
11522 /* Show ability of reorder buffer to hide latency of load by executing
11523 in parallel with previous instruction in case
11524 previous instruction is not needed to compute the address. */
11525 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
11526 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11528 /* Claim moves to take one cycle, as core can issue one load
11529 at time and the next load can start cycle later. */
11530 if (dep_insn_type
== TYPE_IMOV
11531 || dep_insn_type
== TYPE_FMOV
)
11539 memory
= get_attr_memory (insn
);
11541 /* The esp dependency is resolved before the instruction is really
11543 if ((insn_type
== TYPE_PUSH
|| insn_type
== TYPE_POP
)
11544 && (dep_insn_type
== TYPE_PUSH
|| dep_insn_type
== TYPE_POP
))
11547 /* INT->FP conversion is expensive. */
11548 if (get_attr_fp_int_src (dep_insn
))
11551 /* Show ability of reorder buffer to hide latency of load by executing
11552 in parallel with previous instruction in case
11553 previous instruction is not needed to compute the address. */
11554 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
11555 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11557 /* Claim moves to take one cycle, as core can issue one load
11558 at time and the next load can start cycle later. */
11559 if (dep_insn_type
== TYPE_IMOV
11560 || dep_insn_type
== TYPE_FMOV
)
11569 case PROCESSOR_ATHLON
:
11571 memory
= get_attr_memory (insn
);
11573 /* Show ability of reorder buffer to hide latency of load by executing
11574 in parallel with previous instruction in case
11575 previous instruction is not needed to compute the address. */
11576 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
11577 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11579 enum attr_unit unit
= get_attr_unit (insn
);
11582 /* Because of the difference between the length of integer and
11583 floating unit pipeline preparation stages, the memory operands
11584 for floating point are cheaper.
11586 ??? For Athlon it the difference is most probably 2. */
11587 if (unit
== UNIT_INTEGER
|| unit
== UNIT_UNKNOWN
)
11590 loadcost
= TARGET_ATHLON
? 2 : 0;
11592 if (cost
>= loadcost
)
11605 /* How many alternative schedules to try. This should be as wide as the
11606 scheduling freedom in the DFA, but no wider. Making this value too
11607 large results extra work for the scheduler. */
11610 ia32_multipass_dfa_lookahead (void)
11612 if (ix86_tune
== PROCESSOR_PENTIUM
)
11615 if (ix86_tune
== PROCESSOR_PENTIUMPRO
11616 || ix86_tune
== PROCESSOR_K6
)
11624 /* Implement the target hook targetm.vectorize.misaligned_mem_ok. */
11627 ix86_misaligned_mem_ok (enum machine_mode mode
)
11629 if (TARGET_MMX
&& VALID_MMX_REG_MODE (mode
))
11635 /* Compute the alignment given to a constant that is being placed in memory.
11636 EXP is the constant and ALIGN is the alignment that the object would
11638 The value of this function is used instead of that alignment to align
11642 ix86_constant_alignment (tree exp
, int align
)
11644 if (TREE_CODE (exp
) == REAL_CST
)
11646 if (TYPE_MODE (TREE_TYPE (exp
)) == DFmode
&& align
< 64)
11648 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp
))) && align
< 128)
11651 else if (!optimize_size
&& TREE_CODE (exp
) == STRING_CST
11652 && TREE_STRING_LENGTH (exp
) >= 31 && align
< BITS_PER_WORD
)
11653 return BITS_PER_WORD
;
11658 /* Compute the alignment for a static variable.
11659 TYPE is the data type, and ALIGN is the alignment that
11660 the object would ordinarily have. The value of this function is used
11661 instead of that alignment to align the object. */
11664 ix86_data_alignment (tree type
, int align
)
11666 if (AGGREGATE_TYPE_P (type
)
11667 && TYPE_SIZE (type
)
11668 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
11669 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 256
11670 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 256)
11673 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
11674 to 16byte boundary. */
11677 if (AGGREGATE_TYPE_P (type
)
11678 && TYPE_SIZE (type
)
11679 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
11680 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 128
11681 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 128)
11685 if (TREE_CODE (type
) == ARRAY_TYPE
)
11687 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
11689 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
11692 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
11695 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
11697 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
11700 else if ((TREE_CODE (type
) == RECORD_TYPE
11701 || TREE_CODE (type
) == UNION_TYPE
11702 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
11703 && TYPE_FIELDS (type
))
11705 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
11707 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
11710 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
11711 || TREE_CODE (type
) == INTEGER_TYPE
)
11713 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
11715 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
11722 /* Compute the alignment for a local variable.
11723 TYPE is the data type, and ALIGN is the alignment that
11724 the object would ordinarily have. The value of this macro is used
11725 instead of that alignment to align the object. */
11728 ix86_local_alignment (tree type
, int align
)
11730 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
11731 to 16byte boundary. */
11734 if (AGGREGATE_TYPE_P (type
)
11735 && TYPE_SIZE (type
)
11736 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
11737 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 16
11738 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 128)
11741 if (TREE_CODE (type
) == ARRAY_TYPE
)
11743 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
11745 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
11748 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
11750 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
11752 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
11755 else if ((TREE_CODE (type
) == RECORD_TYPE
11756 || TREE_CODE (type
) == UNION_TYPE
11757 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
11758 && TYPE_FIELDS (type
))
11760 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
11762 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
11765 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
11766 || TREE_CODE (type
) == INTEGER_TYPE
)
11769 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
11771 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
11777 /* Emit RTL insns to initialize the variable parts of a trampoline.
11778 FNADDR is an RTX for the address of the function's pure code.
11779 CXT is an RTX for the static chain value for the function. */
11781 x86_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
11785 /* Compute offset from the end of the jmp to the target function. */
11786 rtx disp
= expand_binop (SImode
, sub_optab
, fnaddr
,
11787 plus_constant (tramp
, 10),
11788 NULL_RTX
, 1, OPTAB_DIRECT
);
11789 emit_move_insn (gen_rtx_MEM (QImode
, tramp
),
11790 gen_int_mode (0xb9, QImode
));
11791 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 1)), cxt
);
11792 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 5)),
11793 gen_int_mode (0xe9, QImode
));
11794 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 6)), disp
);
11799 /* Try to load address using shorter movl instead of movabs.
11800 We may want to support movq for kernel mode, but kernel does not use
11801 trampolines at the moment. */
11802 if (x86_64_zext_immediate_operand (fnaddr
, VOIDmode
))
11804 fnaddr
= copy_to_mode_reg (DImode
, fnaddr
);
11805 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11806 gen_int_mode (0xbb41, HImode
));
11807 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, offset
+ 2)),
11808 gen_lowpart (SImode
, fnaddr
));
11813 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11814 gen_int_mode (0xbb49, HImode
));
11815 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, offset
+ 2)),
11819 /* Load static chain using movabs to r10. */
11820 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11821 gen_int_mode (0xba49, HImode
));
11822 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, offset
+ 2)),
11825 /* Jump to the r11 */
11826 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11827 gen_int_mode (0xff49, HImode
));
11828 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, offset
+2)),
11829 gen_int_mode (0xe3, QImode
));
11831 if (offset
> TRAMPOLINE_SIZE
)
11835 #ifdef ENABLE_EXECUTE_STACK
11836 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
11837 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
11841 #define def_builtin(MASK, NAME, TYPE, CODE) \
11843 if ((MASK) & target_flags \
11844 && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \
11845 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
11846 NULL, NULL_TREE); \
11849 struct builtin_description
11851 const unsigned int mask
;
11852 const enum insn_code icode
;
11853 const char *const name
;
11854 const enum ix86_builtins code
;
11855 const enum rtx_code comparison
;
11856 const unsigned int flag
;
11859 static const struct builtin_description bdesc_comi
[] =
11861 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS
, UNEQ
, 0 },
11862 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS
, UNLT
, 0 },
11863 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS
, UNLE
, 0 },
11864 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS
, GT
, 0 },
11865 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS
, GE
, 0 },
11866 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS
, LTGT
, 0 },
11867 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS
, UNEQ
, 0 },
11868 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS
, UNLT
, 0 },
11869 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS
, UNLE
, 0 },
11870 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS
, GT
, 0 },
11871 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS
, GE
, 0 },
11872 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS
, LTGT
, 0 },
11873 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD
, UNEQ
, 0 },
11874 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD
, UNLT
, 0 },
11875 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD
, UNLE
, 0 },
11876 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD
, GT
, 0 },
11877 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD
, GE
, 0 },
11878 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD
, LTGT
, 0 },
11879 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD
, UNEQ
, 0 },
11880 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD
, UNLT
, 0 },
11881 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD
, UNLE
, 0 },
11882 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD
, GT
, 0 },
11883 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD
, GE
, 0 },
11884 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD
, LTGT
, 0 },
11887 static const struct builtin_description bdesc_2arg
[] =
11890 { MASK_SSE
, CODE_FOR_addv4sf3
, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS
, 0, 0 },
11891 { MASK_SSE
, CODE_FOR_subv4sf3
, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS
, 0, 0 },
11892 { MASK_SSE
, CODE_FOR_mulv4sf3
, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS
, 0, 0 },
11893 { MASK_SSE
, CODE_FOR_divv4sf3
, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS
, 0, 0 },
11894 { MASK_SSE
, CODE_FOR_vmaddv4sf3
, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS
, 0, 0 },
11895 { MASK_SSE
, CODE_FOR_vmsubv4sf3
, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS
, 0, 0 },
11896 { MASK_SSE
, CODE_FOR_vmmulv4sf3
, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS
, 0, 0 },
11897 { MASK_SSE
, CODE_FOR_vmdivv4sf3
, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS
, 0, 0 },
11899 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS
, EQ
, 0 },
11900 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS
, LT
, 0 },
11901 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS
, LE
, 0 },
11902 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS
, LT
, 1 },
11903 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS
, LE
, 1 },
11904 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS
, UNORDERED
, 0 },
11905 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS
, EQ
, 0 },
11906 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS
, LT
, 0 },
11907 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS
, LE
, 0 },
11908 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS
, LT
, 1 },
11909 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS
, LE
, 1 },
11910 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS
, UNORDERED
, 0 },
11911 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS
, EQ
, 0 },
11912 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS
, LT
, 0 },
11913 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS
, LE
, 0 },
11914 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS
, UNORDERED
, 0 },
11915 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS
, EQ
, 0 },
11916 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS
, LT
, 0 },
11917 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS
, LE
, 0 },
11918 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS
, UNORDERED
, 0 },
11920 { MASK_SSE
, CODE_FOR_sminv4sf3
, "__builtin_ia32_minps", IX86_BUILTIN_MINPS
, 0, 0 },
11921 { MASK_SSE
, CODE_FOR_smaxv4sf3
, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS
, 0, 0 },
11922 { MASK_SSE
, CODE_FOR_vmsminv4sf3
, "__builtin_ia32_minss", IX86_BUILTIN_MINSS
, 0, 0 },
11923 { MASK_SSE
, CODE_FOR_vmsmaxv4sf3
, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS
, 0, 0 },
11925 { MASK_SSE
, CODE_FOR_sse_andv4sf3
, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS
, 0, 0 },
11926 { MASK_SSE
, CODE_FOR_sse_nandv4sf3
, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS
, 0, 0 },
11927 { MASK_SSE
, CODE_FOR_sse_iorv4sf3
, "__builtin_ia32_orps", IX86_BUILTIN_ORPS
, 0, 0 },
11928 { MASK_SSE
, CODE_FOR_sse_xorv4sf3
, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS
, 0, 0 },
11930 { MASK_SSE
, CODE_FOR_sse_movss
, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS
, 0, 0 },
11931 { MASK_SSE
, CODE_FOR_sse_movhlps
, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS
, 0, 0 },
11932 { MASK_SSE
, CODE_FOR_sse_movlhps
, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS
, 0, 0 },
11933 { MASK_SSE
, CODE_FOR_sse_unpckhps
, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS
, 0, 0 },
11934 { MASK_SSE
, CODE_FOR_sse_unpcklps
, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS
, 0, 0 },
11937 { MASK_MMX
, CODE_FOR_addv8qi3
, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB
, 0, 0 },
11938 { MASK_MMX
, CODE_FOR_addv4hi3
, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW
, 0, 0 },
11939 { MASK_MMX
, CODE_FOR_addv2si3
, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD
, 0, 0 },
11940 { MASK_MMX
, CODE_FOR_mmx_adddi3
, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ
, 0, 0 },
11941 { MASK_MMX
, CODE_FOR_subv8qi3
, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB
, 0, 0 },
11942 { MASK_MMX
, CODE_FOR_subv4hi3
, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW
, 0, 0 },
11943 { MASK_MMX
, CODE_FOR_subv2si3
, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD
, 0, 0 },
11944 { MASK_MMX
, CODE_FOR_mmx_subdi3
, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ
, 0, 0 },
11946 { MASK_MMX
, CODE_FOR_ssaddv8qi3
, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB
, 0, 0 },
11947 { MASK_MMX
, CODE_FOR_ssaddv4hi3
, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW
, 0, 0 },
11948 { MASK_MMX
, CODE_FOR_sssubv8qi3
, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB
, 0, 0 },
11949 { MASK_MMX
, CODE_FOR_sssubv4hi3
, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW
, 0, 0 },
11950 { MASK_MMX
, CODE_FOR_usaddv8qi3
, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB
, 0, 0 },
11951 { MASK_MMX
, CODE_FOR_usaddv4hi3
, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW
, 0, 0 },
11952 { MASK_MMX
, CODE_FOR_ussubv8qi3
, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB
, 0, 0 },
11953 { MASK_MMX
, CODE_FOR_ussubv4hi3
, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW
, 0, 0 },
11955 { MASK_MMX
, CODE_FOR_mulv4hi3
, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW
, 0, 0 },
11956 { MASK_MMX
, CODE_FOR_smulv4hi3_highpart
, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW
, 0, 0 },
11957 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_umulv4hi3_highpart
, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW
, 0, 0 },
11959 { MASK_MMX
, CODE_FOR_mmx_anddi3
, "__builtin_ia32_pand", IX86_BUILTIN_PAND
, 0, 0 },
11960 { MASK_MMX
, CODE_FOR_mmx_nanddi3
, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN
, 0, 0 },
11961 { MASK_MMX
, CODE_FOR_mmx_iordi3
, "__builtin_ia32_por", IX86_BUILTIN_POR
, 0, 0 },
11962 { MASK_MMX
, CODE_FOR_mmx_xordi3
, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR
, 0, 0 },
11964 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_uavgv8qi3
, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB
, 0, 0 },
11965 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_uavgv4hi3
, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW
, 0, 0 },
11967 { MASK_MMX
, CODE_FOR_eqv8qi3
, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB
, 0, 0 },
11968 { MASK_MMX
, CODE_FOR_eqv4hi3
, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW
, 0, 0 },
11969 { MASK_MMX
, CODE_FOR_eqv2si3
, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD
, 0, 0 },
11970 { MASK_MMX
, CODE_FOR_gtv8qi3
, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB
, 0, 0 },
11971 { MASK_MMX
, CODE_FOR_gtv4hi3
, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW
, 0, 0 },
11972 { MASK_MMX
, CODE_FOR_gtv2si3
, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD
, 0, 0 },
11974 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_umaxv8qi3
, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB
, 0, 0 },
11975 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_smaxv4hi3
, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW
, 0, 0 },
11976 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_uminv8qi3
, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB
, 0, 0 },
11977 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_sminv4hi3
, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW
, 0, 0 },
11979 { MASK_MMX
, CODE_FOR_mmx_punpckhbw
, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW
, 0, 0 },
11980 { MASK_MMX
, CODE_FOR_mmx_punpckhwd
, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD
, 0, 0 },
11981 { MASK_MMX
, CODE_FOR_mmx_punpckhdq
, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ
, 0, 0 },
11982 { MASK_MMX
, CODE_FOR_mmx_punpcklbw
, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW
, 0, 0 },
11983 { MASK_MMX
, CODE_FOR_mmx_punpcklwd
, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD
, 0, 0 },
11984 { MASK_MMX
, CODE_FOR_mmx_punpckldq
, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ
, 0, 0 },
11987 { MASK_MMX
, CODE_FOR_mmx_packsswb
, 0, IX86_BUILTIN_PACKSSWB
, 0, 0 },
11988 { MASK_MMX
, CODE_FOR_mmx_packssdw
, 0, IX86_BUILTIN_PACKSSDW
, 0, 0 },
11989 { MASK_MMX
, CODE_FOR_mmx_packuswb
, 0, IX86_BUILTIN_PACKUSWB
, 0, 0 },
11991 { MASK_SSE
, CODE_FOR_cvtpi2ps
, 0, IX86_BUILTIN_CVTPI2PS
, 0, 0 },
11992 { MASK_SSE
, CODE_FOR_cvtsi2ss
, 0, IX86_BUILTIN_CVTSI2SS
, 0, 0 },
11993 { MASK_SSE
| MASK_64BIT
, CODE_FOR_cvtsi2ssq
, 0, IX86_BUILTIN_CVTSI642SS
, 0, 0 },
11995 { MASK_MMX
, CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLW
, 0, 0 },
11996 { MASK_MMX
, CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLWI
, 0, 0 },
11997 { MASK_MMX
, CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLD
, 0, 0 },
11998 { MASK_MMX
, CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLDI
, 0, 0 },
11999 { MASK_MMX
, CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQ
, 0, 0 },
12000 { MASK_MMX
, CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQI
, 0, 0 },
12002 { MASK_MMX
, CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLW
, 0, 0 },
12003 { MASK_MMX
, CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLWI
, 0, 0 },
12004 { MASK_MMX
, CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLD
, 0, 0 },
12005 { MASK_MMX
, CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLDI
, 0, 0 },
12006 { MASK_MMX
, CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQ
, 0, 0 },
12007 { MASK_MMX
, CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQI
, 0, 0 },
12009 { MASK_MMX
, CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAW
, 0, 0 },
12010 { MASK_MMX
, CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAWI
, 0, 0 },
12011 { MASK_MMX
, CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRAD
, 0, 0 },
12012 { MASK_MMX
, CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRADI
, 0, 0 },
12014 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_psadbw
, 0, IX86_BUILTIN_PSADBW
, 0, 0 },
12015 { MASK_MMX
, CODE_FOR_mmx_pmaddwd
, 0, IX86_BUILTIN_PMADDWD
, 0, 0 },
12018 { MASK_SSE2
, CODE_FOR_addv2df3
, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD
, 0, 0 },
12019 { MASK_SSE2
, CODE_FOR_subv2df3
, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD
, 0, 0 },
12020 { MASK_SSE2
, CODE_FOR_mulv2df3
, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD
, 0, 0 },
12021 { MASK_SSE2
, CODE_FOR_divv2df3
, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD
, 0, 0 },
12022 { MASK_SSE2
, CODE_FOR_vmaddv2df3
, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD
, 0, 0 },
12023 { MASK_SSE2
, CODE_FOR_vmsubv2df3
, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD
, 0, 0 },
12024 { MASK_SSE2
, CODE_FOR_vmmulv2df3
, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD
, 0, 0 },
12025 { MASK_SSE2
, CODE_FOR_vmdivv2df3
, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD
, 0, 0 },
12027 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD
, EQ
, 0 },
12028 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD
, LT
, 0 },
12029 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD
, LE
, 0 },
12030 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD
, LT
, 1 },
12031 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD
, LE
, 1 },
12032 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD
, UNORDERED
, 0 },
12033 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD
, EQ
, 0 },
12034 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD
, LT
, 0 },
12035 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD
, LE
, 0 },
12036 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD
, LT
, 1 },
12037 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD
, LE
, 1 },
12038 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD
, UNORDERED
, 0 },
12039 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD
, EQ
, 0 },
12040 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD
, LT
, 0 },
12041 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD
, LE
, 0 },
12042 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD
, UNORDERED
, 0 },
12043 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD
, EQ
, 0 },
12044 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD
, LT
, 0 },
12045 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD
, LE
, 0 },
12046 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD
, UNORDERED
, 0 },
12048 { MASK_SSE2
, CODE_FOR_sminv2df3
, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD
, 0, 0 },
12049 { MASK_SSE2
, CODE_FOR_smaxv2df3
, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD
, 0, 0 },
12050 { MASK_SSE2
, CODE_FOR_vmsminv2df3
, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD
, 0, 0 },
12051 { MASK_SSE2
, CODE_FOR_vmsmaxv2df3
, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD
, 0, 0 },
12053 { MASK_SSE2
, CODE_FOR_sse2_andv2df3
, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD
, 0, 0 },
12054 { MASK_SSE2
, CODE_FOR_sse2_nandv2df3
, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD
, 0, 0 },
12055 { MASK_SSE2
, CODE_FOR_sse2_iorv2df3
, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD
, 0, 0 },
12056 { MASK_SSE2
, CODE_FOR_sse2_xorv2df3
, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD
, 0, 0 },
12058 { MASK_SSE2
, CODE_FOR_sse2_movsd
, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD
, 0, 0 },
12059 { MASK_SSE2
, CODE_FOR_sse2_unpckhpd
, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD
, 0, 0 },
12060 { MASK_SSE2
, CODE_FOR_sse2_unpcklpd
, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD
, 0, 0 },
12063 { MASK_SSE2
, CODE_FOR_addv16qi3
, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128
, 0, 0 },
12064 { MASK_SSE2
, CODE_FOR_addv8hi3
, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128
, 0, 0 },
12065 { MASK_SSE2
, CODE_FOR_addv4si3
, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128
, 0, 0 },
12066 { MASK_SSE2
, CODE_FOR_addv2di3
, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128
, 0, 0 },
12067 { MASK_SSE2
, CODE_FOR_subv16qi3
, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128
, 0, 0 },
12068 { MASK_SSE2
, CODE_FOR_subv8hi3
, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128
, 0, 0 },
12069 { MASK_SSE2
, CODE_FOR_subv4si3
, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128
, 0, 0 },
12070 { MASK_SSE2
, CODE_FOR_subv2di3
, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128
, 0, 0 },
12072 { MASK_MMX
, CODE_FOR_ssaddv16qi3
, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128
, 0, 0 },
12073 { MASK_MMX
, CODE_FOR_ssaddv8hi3
, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128
, 0, 0 },
12074 { MASK_MMX
, CODE_FOR_sssubv16qi3
, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128
, 0, 0 },
12075 { MASK_MMX
, CODE_FOR_sssubv8hi3
, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128
, 0, 0 },
12076 { MASK_MMX
, CODE_FOR_usaddv16qi3
, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128
, 0, 0 },
12077 { MASK_MMX
, CODE_FOR_usaddv8hi3
, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128
, 0, 0 },
12078 { MASK_MMX
, CODE_FOR_ussubv16qi3
, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128
, 0, 0 },
12079 { MASK_MMX
, CODE_FOR_ussubv8hi3
, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128
, 0, 0 },
12081 { MASK_SSE2
, CODE_FOR_mulv8hi3
, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128
, 0, 0 },
12082 { MASK_SSE2
, CODE_FOR_smulv8hi3_highpart
, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128
, 0, 0 },
12084 { MASK_SSE2
, CODE_FOR_sse2_andv2di3
, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128
, 0, 0 },
12085 { MASK_SSE2
, CODE_FOR_sse2_nandv2di3
, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128
, 0, 0 },
12086 { MASK_SSE2
, CODE_FOR_sse2_iorv2di3
, "__builtin_ia32_por128", IX86_BUILTIN_POR128
, 0, 0 },
12087 { MASK_SSE2
, CODE_FOR_sse2_xorv2di3
, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128
, 0, 0 },
12089 { MASK_SSE2
, CODE_FOR_sse2_uavgv16qi3
, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128
, 0, 0 },
12090 { MASK_SSE2
, CODE_FOR_sse2_uavgv8hi3
, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128
, 0, 0 },
12092 { MASK_SSE2
, CODE_FOR_eqv16qi3
, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128
, 0, 0 },
12093 { MASK_SSE2
, CODE_FOR_eqv8hi3
, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128
, 0, 0 },
12094 { MASK_SSE2
, CODE_FOR_eqv4si3
, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128
, 0, 0 },
12095 { MASK_SSE2
, CODE_FOR_gtv16qi3
, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128
, 0, 0 },
12096 { MASK_SSE2
, CODE_FOR_gtv8hi3
, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128
, 0, 0 },
12097 { MASK_SSE2
, CODE_FOR_gtv4si3
, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128
, 0, 0 },
12099 { MASK_SSE2
, CODE_FOR_umaxv16qi3
, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128
, 0, 0 },
12100 { MASK_SSE2
, CODE_FOR_smaxv8hi3
, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128
, 0, 0 },
12101 { MASK_SSE2
, CODE_FOR_uminv16qi3
, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128
, 0, 0 },
12102 { MASK_SSE2
, CODE_FOR_sminv8hi3
, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128
, 0, 0 },
12104 { MASK_SSE2
, CODE_FOR_sse2_punpckhbw
, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128
, 0, 0 },
12105 { MASK_SSE2
, CODE_FOR_sse2_punpckhwd
, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128
, 0, 0 },
12106 { MASK_SSE2
, CODE_FOR_sse2_punpckhdq
, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128
, 0, 0 },
12107 { MASK_SSE2
, CODE_FOR_sse2_punpckhqdq
, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128
, 0, 0 },
12108 { MASK_SSE2
, CODE_FOR_sse2_punpcklbw
, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128
, 0, 0 },
12109 { MASK_SSE2
, CODE_FOR_sse2_punpcklwd
, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128
, 0, 0 },
12110 { MASK_SSE2
, CODE_FOR_sse2_punpckldq
, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128
, 0, 0 },
12111 { MASK_SSE2
, CODE_FOR_sse2_punpcklqdq
, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128
, 0, 0 },
12113 { MASK_SSE2
, CODE_FOR_sse2_packsswb
, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128
, 0, 0 },
12114 { MASK_SSE2
, CODE_FOR_sse2_packssdw
, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128
, 0, 0 },
12115 { MASK_SSE2
, CODE_FOR_sse2_packuswb
, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128
, 0, 0 },
12117 { MASK_SSE2
, CODE_FOR_umulv8hi3_highpart
, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128
, 0, 0 },
12118 { MASK_SSE2
, CODE_FOR_sse2_psadbw
, 0, IX86_BUILTIN_PSADBW128
, 0, 0 },
12120 { MASK_SSE2
, CODE_FOR_sse2_umulsidi3
, 0, IX86_BUILTIN_PMULUDQ
, 0, 0 },
12121 { MASK_SSE2
, CODE_FOR_sse2_umulv2siv2di3
, 0, IX86_BUILTIN_PMULUDQ128
, 0, 0 },
12123 { MASK_SSE2
, CODE_FOR_ashlv8hi3_ti
, 0, IX86_BUILTIN_PSLLW128
, 0, 0 },
12124 { MASK_SSE2
, CODE_FOR_ashlv8hi3
, 0, IX86_BUILTIN_PSLLWI128
, 0, 0 },
12125 { MASK_SSE2
, CODE_FOR_ashlv4si3_ti
, 0, IX86_BUILTIN_PSLLD128
, 0, 0 },
12126 { MASK_SSE2
, CODE_FOR_ashlv4si3
, 0, IX86_BUILTIN_PSLLDI128
, 0, 0 },
12127 { MASK_SSE2
, CODE_FOR_ashlv2di3_ti
, 0, IX86_BUILTIN_PSLLQ128
, 0, 0 },
12128 { MASK_SSE2
, CODE_FOR_ashlv2di3
, 0, IX86_BUILTIN_PSLLQI128
, 0, 0 },
12130 { MASK_SSE2
, CODE_FOR_lshrv8hi3_ti
, 0, IX86_BUILTIN_PSRLW128
, 0, 0 },
12131 { MASK_SSE2
, CODE_FOR_lshrv8hi3
, 0, IX86_BUILTIN_PSRLWI128
, 0, 0 },
12132 { MASK_SSE2
, CODE_FOR_lshrv4si3_ti
, 0, IX86_BUILTIN_PSRLD128
, 0, 0 },
12133 { MASK_SSE2
, CODE_FOR_lshrv4si3
, 0, IX86_BUILTIN_PSRLDI128
, 0, 0 },
12134 { MASK_SSE2
, CODE_FOR_lshrv2di3_ti
, 0, IX86_BUILTIN_PSRLQ128
, 0, 0 },
12135 { MASK_SSE2
, CODE_FOR_lshrv2di3
, 0, IX86_BUILTIN_PSRLQI128
, 0, 0 },
12137 { MASK_SSE2
, CODE_FOR_ashrv8hi3_ti
, 0, IX86_BUILTIN_PSRAW128
, 0, 0 },
12138 { MASK_SSE2
, CODE_FOR_ashrv8hi3
, 0, IX86_BUILTIN_PSRAWI128
, 0, 0 },
12139 { MASK_SSE2
, CODE_FOR_ashrv4si3_ti
, 0, IX86_BUILTIN_PSRAD128
, 0, 0 },
12140 { MASK_SSE2
, CODE_FOR_ashrv4si3
, 0, IX86_BUILTIN_PSRADI128
, 0, 0 },
12142 { MASK_SSE2
, CODE_FOR_sse2_pmaddwd
, 0, IX86_BUILTIN_PMADDWD128
, 0, 0 },
12144 { MASK_SSE2
, CODE_FOR_cvtsi2sd
, 0, IX86_BUILTIN_CVTSI2SD
, 0, 0 },
12145 { MASK_SSE2
| MASK_64BIT
, CODE_FOR_cvtsi2sdq
, 0, IX86_BUILTIN_CVTSI642SD
, 0, 0 },
12146 { MASK_SSE2
, CODE_FOR_cvtsd2ss
, 0, IX86_BUILTIN_CVTSD2SS
, 0, 0 },
12147 { MASK_SSE2
, CODE_FOR_cvtss2sd
, 0, IX86_BUILTIN_CVTSS2SD
, 0, 0 },
12150 { MASK_SSE3
, CODE_FOR_addsubv4sf3
, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS
, 0, 0 },
12151 { MASK_SSE3
, CODE_FOR_addsubv2df3
, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD
, 0, 0 },
12152 { MASK_SSE3
, CODE_FOR_haddv4sf3
, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS
, 0, 0 },
12153 { MASK_SSE3
, CODE_FOR_haddv2df3
, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD
, 0, 0 },
12154 { MASK_SSE3
, CODE_FOR_hsubv4sf3
, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS
, 0, 0 },
12155 { MASK_SSE3
, CODE_FOR_hsubv2df3
, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD
, 0, 0 }
12158 static const struct builtin_description bdesc_1arg
[] =
12160 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_pmovmskb
, 0, IX86_BUILTIN_PMOVMSKB
, 0, 0 },
12161 { MASK_SSE
, CODE_FOR_sse_movmskps
, 0, IX86_BUILTIN_MOVMSKPS
, 0, 0 },
12163 { MASK_SSE
, CODE_FOR_sqrtv4sf2
, 0, IX86_BUILTIN_SQRTPS
, 0, 0 },
12164 { MASK_SSE
, CODE_FOR_rsqrtv4sf2
, 0, IX86_BUILTIN_RSQRTPS
, 0, 0 },
12165 { MASK_SSE
, CODE_FOR_rcpv4sf2
, 0, IX86_BUILTIN_RCPPS
, 0, 0 },
12167 { MASK_SSE
, CODE_FOR_cvtps2pi
, 0, IX86_BUILTIN_CVTPS2PI
, 0, 0 },
12168 { MASK_SSE
, CODE_FOR_cvtss2si
, 0, IX86_BUILTIN_CVTSS2SI
, 0, 0 },
12169 { MASK_SSE
| MASK_64BIT
, CODE_FOR_cvtss2siq
, 0, IX86_BUILTIN_CVTSS2SI64
, 0, 0 },
12170 { MASK_SSE
, CODE_FOR_cvttps2pi
, 0, IX86_BUILTIN_CVTTPS2PI
, 0, 0 },
12171 { MASK_SSE
, CODE_FOR_cvttss2si
, 0, IX86_BUILTIN_CVTTSS2SI
, 0, 0 },
12172 { MASK_SSE
| MASK_64BIT
, CODE_FOR_cvttss2siq
, 0, IX86_BUILTIN_CVTTSS2SI64
, 0, 0 },
12174 { MASK_SSE2
, CODE_FOR_sse2_pmovmskb
, 0, IX86_BUILTIN_PMOVMSKB128
, 0, 0 },
12175 { MASK_SSE2
, CODE_FOR_sse2_movmskpd
, 0, IX86_BUILTIN_MOVMSKPD
, 0, 0 },
12176 { MASK_SSE2
, CODE_FOR_sse2_movq2dq
, 0, IX86_BUILTIN_MOVQ2DQ
, 0, 0 },
12177 { MASK_SSE2
, CODE_FOR_sse2_movdq2q
, 0, IX86_BUILTIN_MOVDQ2Q
, 0, 0 },
12179 { MASK_SSE2
, CODE_FOR_sqrtv2df2
, 0, IX86_BUILTIN_SQRTPD
, 0, 0 },
12181 { MASK_SSE2
, CODE_FOR_cvtdq2pd
, 0, IX86_BUILTIN_CVTDQ2PD
, 0, 0 },
12182 { MASK_SSE2
, CODE_FOR_cvtdq2ps
, 0, IX86_BUILTIN_CVTDQ2PS
, 0, 0 },
12184 { MASK_SSE2
, CODE_FOR_cvtpd2dq
, 0, IX86_BUILTIN_CVTPD2DQ
, 0, 0 },
12185 { MASK_SSE2
, CODE_FOR_cvtpd2pi
, 0, IX86_BUILTIN_CVTPD2PI
, 0, 0 },
12186 { MASK_SSE2
, CODE_FOR_cvtpd2ps
, 0, IX86_BUILTIN_CVTPD2PS
, 0, 0 },
12187 { MASK_SSE2
, CODE_FOR_cvttpd2dq
, 0, IX86_BUILTIN_CVTTPD2DQ
, 0, 0 },
12188 { MASK_SSE2
, CODE_FOR_cvttpd2pi
, 0, IX86_BUILTIN_CVTTPD2PI
, 0, 0 },
12190 { MASK_SSE2
, CODE_FOR_cvtpi2pd
, 0, IX86_BUILTIN_CVTPI2PD
, 0, 0 },
12192 { MASK_SSE2
, CODE_FOR_cvtsd2si
, 0, IX86_BUILTIN_CVTSD2SI
, 0, 0 },
12193 { MASK_SSE2
, CODE_FOR_cvttsd2si
, 0, IX86_BUILTIN_CVTTSD2SI
, 0, 0 },
12194 { MASK_SSE2
| MASK_64BIT
, CODE_FOR_cvtsd2siq
, 0, IX86_BUILTIN_CVTSD2SI64
, 0, 0 },
12195 { MASK_SSE2
| MASK_64BIT
, CODE_FOR_cvttsd2siq
, 0, IX86_BUILTIN_CVTTSD2SI64
, 0, 0 },
12197 { MASK_SSE2
, CODE_FOR_cvtps2dq
, 0, IX86_BUILTIN_CVTPS2DQ
, 0, 0 },
12198 { MASK_SSE2
, CODE_FOR_cvtps2pd
, 0, IX86_BUILTIN_CVTPS2PD
, 0, 0 },
12199 { MASK_SSE2
, CODE_FOR_cvttps2dq
, 0, IX86_BUILTIN_CVTTPS2DQ
, 0, 0 },
12201 { MASK_SSE2
, CODE_FOR_sse2_movq
, 0, IX86_BUILTIN_MOVQ
, 0, 0 },
12204 { MASK_SSE3
, CODE_FOR_movshdup
, 0, IX86_BUILTIN_MOVSHDUP
, 0, 0 },
12205 { MASK_SSE3
, CODE_FOR_movsldup
, 0, IX86_BUILTIN_MOVSLDUP
, 0, 0 },
12206 { MASK_SSE3
, CODE_FOR_movddup
, 0, IX86_BUILTIN_MOVDDUP
, 0, 0 }
12210 ix86_init_builtins (void)
12213 ix86_init_mmx_sse_builtins ();
12216 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
12217 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
12220 ix86_init_mmx_sse_builtins (void)
12222 const struct builtin_description
* d
;
12225 tree V16QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V16QImode
);
12226 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12227 tree V2SF_type_node
= build_vector_type_for_mode (float_type_node
, V2SFmode
);
12228 tree V2DI_type_node
= build_vector_type_for_mode (intDI_type_node
, V2DImode
);
12229 tree V2DF_type_node
= build_vector_type_for_mode (double_type_node
, V2DFmode
);
12230 tree V4SF_type_node
= build_vector_type_for_mode (float_type_node
, V4SFmode
);
12231 tree V4SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V4SImode
);
12232 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12233 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12234 tree V8HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V8HImode
);
12236 tree pchar_type_node
= build_pointer_type (char_type_node
);
12237 tree pcchar_type_node
= build_pointer_type (
12238 build_type_variant (char_type_node
, 1, 0));
12239 tree pfloat_type_node
= build_pointer_type (float_type_node
);
12240 tree pcfloat_type_node
= build_pointer_type (
12241 build_type_variant (float_type_node
, 1, 0));
12242 tree pv2si_type_node
= build_pointer_type (V2SI_type_node
);
12243 tree pv2di_type_node
= build_pointer_type (V2DI_type_node
);
12244 tree pdi_type_node
= build_pointer_type (long_long_unsigned_type_node
);
12247 tree int_ftype_v4sf_v4sf
12248 = build_function_type_list (integer_type_node
,
12249 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12250 tree v4si_ftype_v4sf_v4sf
12251 = build_function_type_list (V4SI_type_node
,
12252 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12253 /* MMX/SSE/integer conversions. */
12254 tree int_ftype_v4sf
12255 = build_function_type_list (integer_type_node
,
12256 V4SF_type_node
, NULL_TREE
);
12257 tree int64_ftype_v4sf
12258 = build_function_type_list (long_long_integer_type_node
,
12259 V4SF_type_node
, NULL_TREE
);
12260 tree int_ftype_v8qi
12261 = build_function_type_list (integer_type_node
, V8QI_type_node
, NULL_TREE
);
12262 tree v4sf_ftype_v4sf_int
12263 = build_function_type_list (V4SF_type_node
,
12264 V4SF_type_node
, integer_type_node
, NULL_TREE
);
12265 tree v4sf_ftype_v4sf_int64
12266 = build_function_type_list (V4SF_type_node
,
12267 V4SF_type_node
, long_long_integer_type_node
,
12269 tree v4sf_ftype_v4sf_v2si
12270 = build_function_type_list (V4SF_type_node
,
12271 V4SF_type_node
, V2SI_type_node
, NULL_TREE
);
12272 tree int_ftype_v4hi_int
12273 = build_function_type_list (integer_type_node
,
12274 V4HI_type_node
, integer_type_node
, NULL_TREE
);
12275 tree v4hi_ftype_v4hi_int_int
12276 = build_function_type_list (V4HI_type_node
, V4HI_type_node
,
12277 integer_type_node
, integer_type_node
,
12279 /* Miscellaneous. */
12280 tree v8qi_ftype_v4hi_v4hi
12281 = build_function_type_list (V8QI_type_node
,
12282 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
12283 tree v4hi_ftype_v2si_v2si
12284 = build_function_type_list (V4HI_type_node
,
12285 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12286 tree v4sf_ftype_v4sf_v4sf_int
12287 = build_function_type_list (V4SF_type_node
,
12288 V4SF_type_node
, V4SF_type_node
,
12289 integer_type_node
, NULL_TREE
);
12290 tree v2si_ftype_v4hi_v4hi
12291 = build_function_type_list (V2SI_type_node
,
12292 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
12293 tree v4hi_ftype_v4hi_int
12294 = build_function_type_list (V4HI_type_node
,
12295 V4HI_type_node
, integer_type_node
, NULL_TREE
);
12296 tree v4hi_ftype_v4hi_di
12297 = build_function_type_list (V4HI_type_node
,
12298 V4HI_type_node
, long_long_unsigned_type_node
,
12300 tree v2si_ftype_v2si_di
12301 = build_function_type_list (V2SI_type_node
,
12302 V2SI_type_node
, long_long_unsigned_type_node
,
12304 tree void_ftype_void
12305 = build_function_type (void_type_node
, void_list_node
);
12306 tree void_ftype_unsigned
12307 = build_function_type_list (void_type_node
, unsigned_type_node
, NULL_TREE
);
12308 tree void_ftype_unsigned_unsigned
12309 = build_function_type_list (void_type_node
, unsigned_type_node
,
12310 unsigned_type_node
, NULL_TREE
);
12311 tree void_ftype_pcvoid_unsigned_unsigned
12312 = build_function_type_list (void_type_node
, const_ptr_type_node
,
12313 unsigned_type_node
, unsigned_type_node
,
12315 tree unsigned_ftype_void
12316 = build_function_type (unsigned_type_node
, void_list_node
);
12318 = build_function_type (long_long_unsigned_type_node
, void_list_node
);
12319 tree v4sf_ftype_void
12320 = build_function_type (V4SF_type_node
, void_list_node
);
12321 tree v2si_ftype_v4sf
12322 = build_function_type_list (V2SI_type_node
, V4SF_type_node
, NULL_TREE
);
12323 /* Loads/stores. */
12324 tree void_ftype_v8qi_v8qi_pchar
12325 = build_function_type_list (void_type_node
,
12326 V8QI_type_node
, V8QI_type_node
,
12327 pchar_type_node
, NULL_TREE
);
12328 tree v4sf_ftype_pcfloat
12329 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
12330 /* @@@ the type is bogus */
12331 tree v4sf_ftype_v4sf_pv2si
12332 = build_function_type_list (V4SF_type_node
,
12333 V4SF_type_node
, pv2si_type_node
, NULL_TREE
);
12334 tree void_ftype_pv2si_v4sf
12335 = build_function_type_list (void_type_node
,
12336 pv2si_type_node
, V4SF_type_node
, NULL_TREE
);
12337 tree void_ftype_pfloat_v4sf
12338 = build_function_type_list (void_type_node
,
12339 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
12340 tree void_ftype_pdi_di
12341 = build_function_type_list (void_type_node
,
12342 pdi_type_node
, long_long_unsigned_type_node
,
12344 tree void_ftype_pv2di_v2di
12345 = build_function_type_list (void_type_node
,
12346 pv2di_type_node
, V2DI_type_node
, NULL_TREE
);
12347 /* Normal vector unops. */
12348 tree v4sf_ftype_v4sf
12349 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12351 /* Normal vector binops. */
12352 tree v4sf_ftype_v4sf_v4sf
12353 = build_function_type_list (V4SF_type_node
,
12354 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12355 tree v8qi_ftype_v8qi_v8qi
12356 = build_function_type_list (V8QI_type_node
,
12357 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
12358 tree v4hi_ftype_v4hi_v4hi
12359 = build_function_type_list (V4HI_type_node
,
12360 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
12361 tree v2si_ftype_v2si_v2si
12362 = build_function_type_list (V2SI_type_node
,
12363 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12364 tree di_ftype_di_di
12365 = build_function_type_list (long_long_unsigned_type_node
,
12366 long_long_unsigned_type_node
,
12367 long_long_unsigned_type_node
, NULL_TREE
);
12369 tree v2si_ftype_v2sf
12370 = build_function_type_list (V2SI_type_node
, V2SF_type_node
, NULL_TREE
);
12371 tree v2sf_ftype_v2si
12372 = build_function_type_list (V2SF_type_node
, V2SI_type_node
, NULL_TREE
);
12373 tree v2si_ftype_v2si
12374 = build_function_type_list (V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12375 tree v2sf_ftype_v2sf
12376 = build_function_type_list (V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
12377 tree v2sf_ftype_v2sf_v2sf
12378 = build_function_type_list (V2SF_type_node
,
12379 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
12380 tree v2si_ftype_v2sf_v2sf
12381 = build_function_type_list (V2SI_type_node
,
12382 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
12383 tree pint_type_node
= build_pointer_type (integer_type_node
);
12384 tree pcint_type_node
= build_pointer_type (
12385 build_type_variant (integer_type_node
, 1, 0));
12386 tree pdouble_type_node
= build_pointer_type (double_type_node
);
12387 tree pcdouble_type_node
= build_pointer_type (
12388 build_type_variant (double_type_node
, 1, 0));
12389 tree int_ftype_v2df_v2df
12390 = build_function_type_list (integer_type_node
,
12391 V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12394 = build_function_type (intTI_type_node
, void_list_node
);
12395 tree v2di_ftype_void
12396 = build_function_type (V2DI_type_node
, void_list_node
);
12397 tree ti_ftype_ti_ti
12398 = build_function_type_list (intTI_type_node
,
12399 intTI_type_node
, intTI_type_node
, NULL_TREE
);
12400 tree void_ftype_pcvoid
12401 = build_function_type_list (void_type_node
, const_ptr_type_node
, NULL_TREE
);
12403 = build_function_type_list (V2DI_type_node
,
12404 long_long_unsigned_type_node
, NULL_TREE
);
12406 = build_function_type_list (long_long_unsigned_type_node
,
12407 V2DI_type_node
, NULL_TREE
);
12408 tree v4sf_ftype_v4si
12409 = build_function_type_list (V4SF_type_node
, V4SI_type_node
, NULL_TREE
);
12410 tree v4si_ftype_v4sf
12411 = build_function_type_list (V4SI_type_node
, V4SF_type_node
, NULL_TREE
);
12412 tree v2df_ftype_v4si
12413 = build_function_type_list (V2DF_type_node
, V4SI_type_node
, NULL_TREE
);
12414 tree v4si_ftype_v2df
12415 = build_function_type_list (V4SI_type_node
, V2DF_type_node
, NULL_TREE
);
12416 tree v2si_ftype_v2df
12417 = build_function_type_list (V2SI_type_node
, V2DF_type_node
, NULL_TREE
);
12418 tree v4sf_ftype_v2df
12419 = build_function_type_list (V4SF_type_node
, V2DF_type_node
, NULL_TREE
);
12420 tree v2df_ftype_v2si
12421 = build_function_type_list (V2DF_type_node
, V2SI_type_node
, NULL_TREE
);
12422 tree v2df_ftype_v4sf
12423 = build_function_type_list (V2DF_type_node
, V4SF_type_node
, NULL_TREE
);
12424 tree int_ftype_v2df
12425 = build_function_type_list (integer_type_node
, V2DF_type_node
, NULL_TREE
);
12426 tree int64_ftype_v2df
12427 = build_function_type_list (long_long_integer_type_node
,
12428 V2DF_type_node
, NULL_TREE
);
12429 tree v2df_ftype_v2df_int
12430 = build_function_type_list (V2DF_type_node
,
12431 V2DF_type_node
, integer_type_node
, NULL_TREE
);
12432 tree v2df_ftype_v2df_int64
12433 = build_function_type_list (V2DF_type_node
,
12434 V2DF_type_node
, long_long_integer_type_node
,
12436 tree v4sf_ftype_v4sf_v2df
12437 = build_function_type_list (V4SF_type_node
,
12438 V4SF_type_node
, V2DF_type_node
, NULL_TREE
);
12439 tree v2df_ftype_v2df_v4sf
12440 = build_function_type_list (V2DF_type_node
,
12441 V2DF_type_node
, V4SF_type_node
, NULL_TREE
);
12442 tree v2df_ftype_v2df_v2df_int
12443 = build_function_type_list (V2DF_type_node
,
12444 V2DF_type_node
, V2DF_type_node
,
12447 tree v2df_ftype_v2df_pv2si
12448 = build_function_type_list (V2DF_type_node
,
12449 V2DF_type_node
, pv2si_type_node
, NULL_TREE
);
12450 tree void_ftype_pv2si_v2df
12451 = build_function_type_list (void_type_node
,
12452 pv2si_type_node
, V2DF_type_node
, NULL_TREE
);
12453 tree void_ftype_pdouble_v2df
12454 = build_function_type_list (void_type_node
,
12455 pdouble_type_node
, V2DF_type_node
, NULL_TREE
);
12456 tree void_ftype_pint_int
12457 = build_function_type_list (void_type_node
,
12458 pint_type_node
, integer_type_node
, NULL_TREE
);
12459 tree void_ftype_v16qi_v16qi_pchar
12460 = build_function_type_list (void_type_node
,
12461 V16QI_type_node
, V16QI_type_node
,
12462 pchar_type_node
, NULL_TREE
);
12463 tree v2df_ftype_pcdouble
12464 = build_function_type_list (V2DF_type_node
, pcdouble_type_node
, NULL_TREE
);
12465 tree v2df_ftype_v2df_v2df
12466 = build_function_type_list (V2DF_type_node
,
12467 V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12468 tree v16qi_ftype_v16qi_v16qi
12469 = build_function_type_list (V16QI_type_node
,
12470 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12471 tree v8hi_ftype_v8hi_v8hi
12472 = build_function_type_list (V8HI_type_node
,
12473 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12474 tree v4si_ftype_v4si_v4si
12475 = build_function_type_list (V4SI_type_node
,
12476 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12477 tree v2di_ftype_v2di_v2di
12478 = build_function_type_list (V2DI_type_node
,
12479 V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
12480 tree v2di_ftype_v2df_v2df
12481 = build_function_type_list (V2DI_type_node
,
12482 V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12483 tree v2df_ftype_v2df
12484 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12485 tree v2df_ftype_double
12486 = build_function_type_list (V2DF_type_node
, double_type_node
, NULL_TREE
);
12487 tree v2df_ftype_double_double
12488 = build_function_type_list (V2DF_type_node
,
12489 double_type_node
, double_type_node
, NULL_TREE
);
12490 tree int_ftype_v8hi_int
12491 = build_function_type_list (integer_type_node
,
12492 V8HI_type_node
, integer_type_node
, NULL_TREE
);
12493 tree v8hi_ftype_v8hi_int_int
12494 = build_function_type_list (V8HI_type_node
,
12495 V8HI_type_node
, integer_type_node
,
12496 integer_type_node
, NULL_TREE
);
12497 tree v2di_ftype_v2di_int
12498 = build_function_type_list (V2DI_type_node
,
12499 V2DI_type_node
, integer_type_node
, NULL_TREE
);
12500 tree v4si_ftype_v4si_int
12501 = build_function_type_list (V4SI_type_node
,
12502 V4SI_type_node
, integer_type_node
, NULL_TREE
);
12503 tree v8hi_ftype_v8hi_int
12504 = build_function_type_list (V8HI_type_node
,
12505 V8HI_type_node
, integer_type_node
, NULL_TREE
);
12506 tree v8hi_ftype_v8hi_v2di
12507 = build_function_type_list (V8HI_type_node
,
12508 V8HI_type_node
, V2DI_type_node
, NULL_TREE
);
12509 tree v4si_ftype_v4si_v2di
12510 = build_function_type_list (V4SI_type_node
,
12511 V4SI_type_node
, V2DI_type_node
, NULL_TREE
);
12512 tree v4si_ftype_v8hi_v8hi
12513 = build_function_type_list (V4SI_type_node
,
12514 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12515 tree di_ftype_v8qi_v8qi
12516 = build_function_type_list (long_long_unsigned_type_node
,
12517 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
12518 tree di_ftype_v2si_v2si
12519 = build_function_type_list (long_long_unsigned_type_node
,
12520 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12521 tree v2di_ftype_v16qi_v16qi
12522 = build_function_type_list (V2DI_type_node
,
12523 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12524 tree v2di_ftype_v4si_v4si
12525 = build_function_type_list (V2DI_type_node
,
12526 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12527 tree int_ftype_v16qi
12528 = build_function_type_list (integer_type_node
, V16QI_type_node
, NULL_TREE
);
12529 tree v16qi_ftype_pcchar
12530 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
12531 tree void_ftype_pchar_v16qi
12532 = build_function_type_list (void_type_node
,
12533 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
12534 tree v4si_ftype_pcint
12535 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
12536 tree void_ftype_pcint_v4si
12537 = build_function_type_list (void_type_node
,
12538 pcint_type_node
, V4SI_type_node
, NULL_TREE
);
12539 tree v2di_ftype_v2di
12540 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
12543 tree float128_type
;
12545 /* The __float80 type. */
12546 if (TYPE_MODE (long_double_type_node
) == XFmode
)
12547 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
12551 /* The __float80 type. */
12552 float80_type
= make_node (REAL_TYPE
);
12553 TYPE_PRECISION (float80_type
) = 80;
12554 layout_type (float80_type
);
12555 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
12558 float128_type
= make_node (REAL_TYPE
);
12559 TYPE_PRECISION (float128_type
) = 128;
12560 layout_type (float128_type
);
12561 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
12563 /* Add all builtins that are more or less simple operations on two
12565 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12567 /* Use one of the operands; the target can have a different mode for
12568 mask-generating compares. */
12569 enum machine_mode mode
;
12574 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12579 type
= v16qi_ftype_v16qi_v16qi
;
12582 type
= v8hi_ftype_v8hi_v8hi
;
12585 type
= v4si_ftype_v4si_v4si
;
12588 type
= v2di_ftype_v2di_v2di
;
12591 type
= v2df_ftype_v2df_v2df
;
12594 type
= ti_ftype_ti_ti
;
12597 type
= v4sf_ftype_v4sf_v4sf
;
12600 type
= v8qi_ftype_v8qi_v8qi
;
12603 type
= v4hi_ftype_v4hi_v4hi
;
12606 type
= v2si_ftype_v2si_v2si
;
12609 type
= di_ftype_di_di
;
12616 /* Override for comparisons. */
12617 if (d
->icode
== CODE_FOR_maskcmpv4sf3
12618 || d
->icode
== CODE_FOR_maskncmpv4sf3
12619 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
12620 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
)
12621 type
= v4si_ftype_v4sf_v4sf
;
12623 if (d
->icode
== CODE_FOR_maskcmpv2df3
12624 || d
->icode
== CODE_FOR_maskncmpv2df3
12625 || d
->icode
== CODE_FOR_vmmaskcmpv2df3
12626 || d
->icode
== CODE_FOR_vmmaskncmpv2df3
)
12627 type
= v2di_ftype_v2df_v2df
;
12629 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
12632 /* Add the remaining MMX insns with somewhat more complicated types. */
12633 def_builtin (MASK_MMX
, "__builtin_ia32_mmx_zero", di_ftype_void
, IX86_BUILTIN_MMX_ZERO
);
12634 def_builtin (MASK_MMX
, "__builtin_ia32_emms", void_ftype_void
, IX86_BUILTIN_EMMS
);
12635 def_builtin (MASK_MMX
, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSLLW
);
12636 def_builtin (MASK_MMX
, "__builtin_ia32_pslld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSLLD
);
12637 def_builtin (MASK_MMX
, "__builtin_ia32_psllq", di_ftype_di_di
, IX86_BUILTIN_PSLLQ
);
12639 def_builtin (MASK_MMX
, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRLW
);
12640 def_builtin (MASK_MMX
, "__builtin_ia32_psrld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRLD
);
12641 def_builtin (MASK_MMX
, "__builtin_ia32_psrlq", di_ftype_di_di
, IX86_BUILTIN_PSRLQ
);
12643 def_builtin (MASK_MMX
, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRAW
);
12644 def_builtin (MASK_MMX
, "__builtin_ia32_psrad", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRAD
);
12646 def_builtin (MASK_MMX
, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int
, IX86_BUILTIN_PSHUFW
);
12647 def_builtin (MASK_MMX
, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi
, IX86_BUILTIN_PMADDWD
);
12649 /* comi/ucomi insns. */
12650 for (i
= 0, d
= bdesc_comi
; i
< ARRAY_SIZE (bdesc_comi
); i
++, d
++)
12651 if (d
->mask
== MASK_SSE2
)
12652 def_builtin (d
->mask
, d
->name
, int_ftype_v2df_v2df
, d
->code
);
12654 def_builtin (d
->mask
, d
->name
, int_ftype_v4sf_v4sf
, d
->code
);
12656 def_builtin (MASK_MMX
, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKSSWB
);
12657 def_builtin (MASK_MMX
, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si
, IX86_BUILTIN_PACKSSDW
);
12658 def_builtin (MASK_MMX
, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKUSWB
);
12660 def_builtin (MASK_SSE
, "__builtin_ia32_ldmxcsr", void_ftype_unsigned
, IX86_BUILTIN_LDMXCSR
);
12661 def_builtin (MASK_SSE
, "__builtin_ia32_stmxcsr", unsigned_ftype_void
, IX86_BUILTIN_STMXCSR
);
12662 def_builtin (MASK_SSE
, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si
, IX86_BUILTIN_CVTPI2PS
);
12663 def_builtin (MASK_SSE
, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTPS2PI
);
12664 def_builtin (MASK_SSE
, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int
, IX86_BUILTIN_CVTSI2SS
);
12665 def_builtin (MASK_SSE
| MASK_64BIT
, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64
, IX86_BUILTIN_CVTSI642SS
);
12666 def_builtin (MASK_SSE
, "__builtin_ia32_cvtss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTSS2SI
);
12667 def_builtin (MASK_SSE
| MASK_64BIT
, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf
, IX86_BUILTIN_CVTSS2SI64
);
12668 def_builtin (MASK_SSE
, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTTPS2PI
);
12669 def_builtin (MASK_SSE
, "__builtin_ia32_cvttss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTTSS2SI
);
12670 def_builtin (MASK_SSE
| MASK_64BIT
, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf
, IX86_BUILTIN_CVTTSS2SI64
);
12672 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pextrw", int_ftype_v4hi_int
, IX86_BUILTIN_PEXTRW
);
12673 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pinsrw", v4hi_ftype_v4hi_int_int
, IX86_BUILTIN_PINSRW
);
12675 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar
, IX86_BUILTIN_MASKMOVQ
);
12677 def_builtin (MASK_SSE
, "__builtin_ia32_loadaps", v4sf_ftype_pcfloat
, IX86_BUILTIN_LOADAPS
);
12678 def_builtin (MASK_SSE
, "__builtin_ia32_loadups", v4sf_ftype_pcfloat
, IX86_BUILTIN_LOADUPS
);
12679 def_builtin (MASK_SSE
, "__builtin_ia32_loadss", v4sf_ftype_pcfloat
, IX86_BUILTIN_LOADSS
);
12680 def_builtin (MASK_SSE
, "__builtin_ia32_storeaps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREAPS
);
12681 def_builtin (MASK_SSE
, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREUPS
);
12682 def_builtin (MASK_SSE
, "__builtin_ia32_storess", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STORESS
);
12684 def_builtin (MASK_SSE
, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADHPS
);
12685 def_builtin (MASK_SSE
, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADLPS
);
12686 def_builtin (MASK_SSE
, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf
, IX86_BUILTIN_STOREHPS
);
12687 def_builtin (MASK_SSE
, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf
, IX86_BUILTIN_STORELPS
);
12689 def_builtin (MASK_SSE
, "__builtin_ia32_movmskps", int_ftype_v4sf
, IX86_BUILTIN_MOVMSKPS
);
12690 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pmovmskb", int_ftype_v8qi
, IX86_BUILTIN_PMOVMSKB
);
12691 def_builtin (MASK_SSE
, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_MOVNTPS
);
12692 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_movntq", void_ftype_pdi_di
, IX86_BUILTIN_MOVNTQ
);
12694 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_sfence", void_ftype_void
, IX86_BUILTIN_SFENCE
);
12696 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi
, IX86_BUILTIN_PSADBW
);
12698 def_builtin (MASK_SSE
, "__builtin_ia32_rcpps", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPPS
);
12699 def_builtin (MASK_SSE
, "__builtin_ia32_rcpss", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPSS
);
12700 def_builtin (MASK_SSE
, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTPS
);
12701 def_builtin (MASK_SSE
, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTSS
);
12702 def_builtin (MASK_SSE
, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTPS
);
12703 def_builtin (MASK_SSE
, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTSS
);
12705 def_builtin (MASK_SSE
, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int
, IX86_BUILTIN_SHUFPS
);
12707 /* Original 3DNow! */
12708 def_builtin (MASK_3DNOW
, "__builtin_ia32_femms", void_ftype_void
, IX86_BUILTIN_FEMMS
);
12709 def_builtin (MASK_3DNOW
, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi
, IX86_BUILTIN_PAVGUSB
);
12710 def_builtin (MASK_3DNOW
, "__builtin_ia32_pf2id", v2si_ftype_v2sf
, IX86_BUILTIN_PF2ID
);
12711 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFACC
);
12712 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFADD
);
12713 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPEQ
);
12714 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPGE
);
12715 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPGT
);
12716 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMAX
);
12717 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMIN
);
12718 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMUL
);
12719 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf
, IX86_BUILTIN_PFRCP
);
12720 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRCPIT1
);
12721 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRCPIT2
);
12722 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf
, IX86_BUILTIN_PFRSQRT
);
12723 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRSQIT1
);
12724 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFSUB
);
12725 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFSUBR
);
12726 def_builtin (MASK_3DNOW
, "__builtin_ia32_pi2fd", v2sf_ftype_v2si
, IX86_BUILTIN_PI2FD
);
12727 def_builtin (MASK_3DNOW
, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi
, IX86_BUILTIN_PMULHRW
);
12729 /* 3DNow! extension as used in the Athlon CPU. */
12730 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pf2iw", v2si_ftype_v2sf
, IX86_BUILTIN_PF2IW
);
12731 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFNACC
);
12732 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFPNACC
);
12733 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pi2fw", v2sf_ftype_v2si
, IX86_BUILTIN_PI2FW
);
12734 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf
, IX86_BUILTIN_PSWAPDSF
);
12735 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pswapdsi", v2si_ftype_v2si
, IX86_BUILTIN_PSWAPDSI
);
12737 def_builtin (MASK_SSE
, "__builtin_ia32_setzerops", v4sf_ftype_void
, IX86_BUILTIN_SSE_ZERO
);
12740 def_builtin (MASK_SSE2
, "__builtin_ia32_pextrw128", int_ftype_v8hi_int
, IX86_BUILTIN_PEXTRW128
);
12741 def_builtin (MASK_SSE2
, "__builtin_ia32_pinsrw128", v8hi_ftype_v8hi_int_int
, IX86_BUILTIN_PINSRW128
);
12743 def_builtin (MASK_SSE2
, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar
, IX86_BUILTIN_MASKMOVDQU
);
12744 def_builtin (MASK_SSE2
, "__builtin_ia32_movq2dq", v2di_ftype_di
, IX86_BUILTIN_MOVQ2DQ
);
12745 def_builtin (MASK_SSE2
, "__builtin_ia32_movdq2q", di_ftype_v2di
, IX86_BUILTIN_MOVDQ2Q
);
12747 def_builtin (MASK_SSE2
, "__builtin_ia32_loadapd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADAPD
);
12748 def_builtin (MASK_SSE2
, "__builtin_ia32_loadupd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADUPD
);
12749 def_builtin (MASK_SSE2
, "__builtin_ia32_loadsd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADSD
);
12750 def_builtin (MASK_SSE2
, "__builtin_ia32_storeapd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STOREAPD
);
12751 def_builtin (MASK_SSE2
, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STOREUPD
);
12752 def_builtin (MASK_SSE2
, "__builtin_ia32_storesd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STORESD
);
12754 def_builtin (MASK_SSE2
, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pv2si
, IX86_BUILTIN_LOADHPD
);
12755 def_builtin (MASK_SSE2
, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pv2si
, IX86_BUILTIN_LOADLPD
);
12756 def_builtin (MASK_SSE2
, "__builtin_ia32_storehpd", void_ftype_pv2si_v2df
, IX86_BUILTIN_STOREHPD
);
12757 def_builtin (MASK_SSE2
, "__builtin_ia32_storelpd", void_ftype_pv2si_v2df
, IX86_BUILTIN_STORELPD
);
12759 def_builtin (MASK_SSE2
, "__builtin_ia32_movmskpd", int_ftype_v2df
, IX86_BUILTIN_MOVMSKPD
);
12760 def_builtin (MASK_SSE2
, "__builtin_ia32_pmovmskb128", int_ftype_v16qi
, IX86_BUILTIN_PMOVMSKB128
);
12761 def_builtin (MASK_SSE2
, "__builtin_ia32_movnti", void_ftype_pint_int
, IX86_BUILTIN_MOVNTI
);
12762 def_builtin (MASK_SSE2
, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df
, IX86_BUILTIN_MOVNTPD
);
12763 def_builtin (MASK_SSE2
, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di
, IX86_BUILTIN_MOVNTDQ
);
12765 def_builtin (MASK_SSE2
, "__builtin_ia32_pshufd", v4si_ftype_v4si_int
, IX86_BUILTIN_PSHUFD
);
12766 def_builtin (MASK_SSE2
, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSHUFLW
);
12767 def_builtin (MASK_SSE2
, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSHUFHW
);
12768 def_builtin (MASK_SSE2
, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi
, IX86_BUILTIN_PSADBW128
);
12770 def_builtin (MASK_SSE2
, "__builtin_ia32_sqrtpd", v2df_ftype_v2df
, IX86_BUILTIN_SQRTPD
);
12771 def_builtin (MASK_SSE2
, "__builtin_ia32_sqrtsd", v2df_ftype_v2df
, IX86_BUILTIN_SQRTSD
);
12773 def_builtin (MASK_SSE2
, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int
, IX86_BUILTIN_SHUFPD
);
12775 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si
, IX86_BUILTIN_CVTDQ2PD
);
12776 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si
, IX86_BUILTIN_CVTDQ2PS
);
12778 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df
, IX86_BUILTIN_CVTPD2DQ
);
12779 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df
, IX86_BUILTIN_CVTPD2PI
);
12780 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df
, IX86_BUILTIN_CVTPD2PS
);
12781 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df
, IX86_BUILTIN_CVTTPD2DQ
);
12782 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df
, IX86_BUILTIN_CVTTPD2PI
);
12784 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si
, IX86_BUILTIN_CVTPI2PD
);
12786 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtsd2si", int_ftype_v2df
, IX86_BUILTIN_CVTSD2SI
);
12787 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttsd2si", int_ftype_v2df
, IX86_BUILTIN_CVTTSD2SI
);
12788 def_builtin (MASK_SSE2
| MASK_64BIT
, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df
, IX86_BUILTIN_CVTSD2SI64
);
12789 def_builtin (MASK_SSE2
| MASK_64BIT
, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df
, IX86_BUILTIN_CVTTSD2SI64
);
12791 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf
, IX86_BUILTIN_CVTPS2DQ
);
12792 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf
, IX86_BUILTIN_CVTPS2PD
);
12793 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf
, IX86_BUILTIN_CVTTPS2DQ
);
12795 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int
, IX86_BUILTIN_CVTSI2SD
);
12796 def_builtin (MASK_SSE2
| MASK_64BIT
, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64
, IX86_BUILTIN_CVTSI642SD
);
12797 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df
, IX86_BUILTIN_CVTSD2SS
);
12798 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf
, IX86_BUILTIN_CVTSS2SD
);
12800 def_builtin (MASK_SSE2
, "__builtin_ia32_setpd1", v2df_ftype_double
, IX86_BUILTIN_SETPD1
);
12801 def_builtin (MASK_SSE2
, "__builtin_ia32_setpd", v2df_ftype_double_double
, IX86_BUILTIN_SETPD
);
12802 def_builtin (MASK_SSE2
, "__builtin_ia32_setzeropd", ti_ftype_void
, IX86_BUILTIN_CLRPD
);
12803 def_builtin (MASK_SSE2
, "__builtin_ia32_loadpd1", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADPD1
);
12804 def_builtin (MASK_SSE2
, "__builtin_ia32_loadrpd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADRPD
);
12805 def_builtin (MASK_SSE2
, "__builtin_ia32_storepd1", void_ftype_pdouble_v2df
, IX86_BUILTIN_STOREPD1
);
12806 def_builtin (MASK_SSE2
, "__builtin_ia32_storerpd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STORERPD
);
12808 def_builtin (MASK_SSE2
, "__builtin_ia32_clflush", void_ftype_pcvoid
, IX86_BUILTIN_CLFLUSH
);
12809 def_builtin (MASK_SSE2
, "__builtin_ia32_lfence", void_ftype_void
, IX86_BUILTIN_LFENCE
);
12810 def_builtin (MASK_SSE2
, "__builtin_ia32_mfence", void_ftype_void
, IX86_BUILTIN_MFENCE
);
12812 def_builtin (MASK_SSE2
, "__builtin_ia32_loaddqa", v16qi_ftype_pcchar
, IX86_BUILTIN_LOADDQA
);
12813 def_builtin (MASK_SSE2
, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar
, IX86_BUILTIN_LOADDQU
);
12814 def_builtin (MASK_SSE2
, "__builtin_ia32_loadd", v4si_ftype_pcint
, IX86_BUILTIN_LOADD
);
12815 def_builtin (MASK_SSE2
, "__builtin_ia32_storedqa", void_ftype_pchar_v16qi
, IX86_BUILTIN_STOREDQA
);
12816 def_builtin (MASK_SSE2
, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi
, IX86_BUILTIN_STOREDQU
);
12817 def_builtin (MASK_SSE2
, "__builtin_ia32_stored", void_ftype_pcint_v4si
, IX86_BUILTIN_STORED
);
12818 def_builtin (MASK_SSE2
, "__builtin_ia32_movq", v2di_ftype_v2di
, IX86_BUILTIN_MOVQ
);
12820 def_builtin (MASK_SSE
, "__builtin_ia32_setzero128", v2di_ftype_void
, IX86_BUILTIN_CLRTI
);
12822 def_builtin (MASK_SSE2
, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si
, IX86_BUILTIN_PMULUDQ
);
12823 def_builtin (MASK_SSE2
, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si
, IX86_BUILTIN_PMULUDQ128
);
12825 def_builtin (MASK_SSE2
, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di
, IX86_BUILTIN_PSLLW128
);
12826 def_builtin (MASK_SSE2
, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di
, IX86_BUILTIN_PSLLD128
);
12827 def_builtin (MASK_SSE2
, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di
, IX86_BUILTIN_PSLLQ128
);
12829 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di
, IX86_BUILTIN_PSRLW128
);
12830 def_builtin (MASK_SSE2
, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di
, IX86_BUILTIN_PSRLD128
);
12831 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di
, IX86_BUILTIN_PSRLQ128
);
12833 def_builtin (MASK_SSE2
, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di
, IX86_BUILTIN_PSRAW128
);
12834 def_builtin (MASK_SSE2
, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di
, IX86_BUILTIN_PSRAD128
);
12836 def_builtin (MASK_SSE2
, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSLLDQI128
);
12837 def_builtin (MASK_SSE2
, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSLLWI128
);
12838 def_builtin (MASK_SSE2
, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int
, IX86_BUILTIN_PSLLDI128
);
12839 def_builtin (MASK_SSE2
, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSLLQI128
);
12841 def_builtin (MASK_SSE2
, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSRLDQI128
);
12842 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSRLWI128
);
12843 def_builtin (MASK_SSE2
, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int
, IX86_BUILTIN_PSRLDI128
);
12844 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSRLQI128
);
12846 def_builtin (MASK_SSE2
, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSRAWI128
);
12847 def_builtin (MASK_SSE2
, "__builtin_ia32_psradi128", v4si_ftype_v4si_int
, IX86_BUILTIN_PSRADI128
);
12849 def_builtin (MASK_SSE2
, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi
, IX86_BUILTIN_PMADDWD128
);
12851 /* Prescott New Instructions. */
12852 def_builtin (MASK_SSE3
, "__builtin_ia32_monitor",
12853 void_ftype_pcvoid_unsigned_unsigned
,
12854 IX86_BUILTIN_MONITOR
);
12855 def_builtin (MASK_SSE3
, "__builtin_ia32_mwait",
12856 void_ftype_unsigned_unsigned
,
12857 IX86_BUILTIN_MWAIT
);
12858 def_builtin (MASK_SSE3
, "__builtin_ia32_movshdup",
12860 IX86_BUILTIN_MOVSHDUP
);
12861 def_builtin (MASK_SSE3
, "__builtin_ia32_movsldup",
12863 IX86_BUILTIN_MOVSLDUP
);
12864 def_builtin (MASK_SSE3
, "__builtin_ia32_lddqu",
12865 v16qi_ftype_pcchar
, IX86_BUILTIN_LDDQU
);
12866 def_builtin (MASK_SSE3
, "__builtin_ia32_loadddup",
12867 v2df_ftype_pcdouble
, IX86_BUILTIN_LOADDDUP
);
12868 def_builtin (MASK_SSE3
, "__builtin_ia32_movddup",
12869 v2df_ftype_v2df
, IX86_BUILTIN_MOVDDUP
);
12872 /* Errors in the source file can cause expand_expr to return const0_rtx
12873 where we expect a vector. To avoid crashing, use one of the vector
12874 clear instructions. */
12876 safe_vector_operand (rtx x
, enum machine_mode mode
)
12878 if (x
!= const0_rtx
)
12880 x
= gen_reg_rtx (mode
);
12882 if (VALID_MMX_REG_MODE (mode
) || VALID_MMX_REG_MODE_3DNOW (mode
))
12883 emit_insn (gen_mmx_clrdi (mode
== DImode
? x
12884 : gen_rtx_SUBREG (DImode
, x
, 0)));
12886 emit_insn (gen_sse_clrv4sf (mode
== V4SFmode
? x
12887 : gen_rtx_SUBREG (V4SFmode
, x
, 0),
12888 CONST0_RTX (V4SFmode
)));
12892 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
12895 ix86_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
12898 tree arg0
= TREE_VALUE (arglist
);
12899 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12900 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12901 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12902 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12903 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12904 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12906 if (VECTOR_MODE_P (mode0
))
12907 op0
= safe_vector_operand (op0
, mode0
);
12908 if (VECTOR_MODE_P (mode1
))
12909 op1
= safe_vector_operand (op1
, mode1
);
12912 || GET_MODE (target
) != tmode
12913 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12914 target
= gen_reg_rtx (tmode
);
12916 if (GET_MODE (op1
) == SImode
&& mode1
== TImode
)
12918 rtx x
= gen_reg_rtx (V4SImode
);
12919 emit_insn (gen_sse2_loadd (x
, op1
));
12920 op1
= gen_lowpart (TImode
, x
);
12923 /* In case the insn wants input operands in modes different from
12924 the result, abort. */
12925 if ((GET_MODE (op0
) != mode0
&& GET_MODE (op0
) != VOIDmode
)
12926 || (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
))
12929 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12930 op0
= copy_to_mode_reg (mode0
, op0
);
12931 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12932 op1
= copy_to_mode_reg (mode1
, op1
);
12934 /* In the commutative cases, both op0 and op1 are nonimmediate_operand,
12935 yet one of the two must not be a memory. This is normally enforced
12936 by expanders, but we didn't bother to create one here. */
12937 if (GET_CODE (op0
) == MEM
&& GET_CODE (op1
) == MEM
)
12938 op0
= copy_to_mode_reg (mode0
, op0
);
12940 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12947 /* Subroutine of ix86_expand_builtin to take care of stores. */
12950 ix86_expand_store_builtin (enum insn_code icode
, tree arglist
)
12953 tree arg0
= TREE_VALUE (arglist
);
12954 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12955 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12956 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12957 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12958 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12960 if (VECTOR_MODE_P (mode1
))
12961 op1
= safe_vector_operand (op1
, mode1
);
12963 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12964 op1
= copy_to_mode_reg (mode1
, op1
);
12966 pat
= GEN_FCN (icode
) (op0
, op1
);
12972 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
12975 ix86_expand_unop_builtin (enum insn_code icode
, tree arglist
,
12976 rtx target
, int do_load
)
12979 tree arg0
= TREE_VALUE (arglist
);
12980 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12981 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12982 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12985 || GET_MODE (target
) != tmode
12986 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12987 target
= gen_reg_rtx (tmode
);
12989 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12992 if (VECTOR_MODE_P (mode0
))
12993 op0
= safe_vector_operand (op0
, mode0
);
12995 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12996 op0
= copy_to_mode_reg (mode0
, op0
);
12999 pat
= GEN_FCN (icode
) (target
, op0
);
13006 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
13007 sqrtss, rsqrtss, rcpss. */
13010 ix86_expand_unop1_builtin (enum insn_code icode
, tree arglist
, rtx target
)
13013 tree arg0
= TREE_VALUE (arglist
);
13014 rtx op1
, op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13015 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13016 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13019 || GET_MODE (target
) != tmode
13020 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13021 target
= gen_reg_rtx (tmode
);
13023 if (VECTOR_MODE_P (mode0
))
13024 op0
= safe_vector_operand (op0
, mode0
);
13026 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13027 op0
= copy_to_mode_reg (mode0
, op0
);
13030 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode0
))
13031 op1
= copy_to_mode_reg (mode0
, op1
);
13033 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13040 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
13043 ix86_expand_sse_compare (const struct builtin_description
*d
, tree arglist
,
13047 tree arg0
= TREE_VALUE (arglist
);
13048 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13049 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13050 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13052 enum machine_mode tmode
= insn_data
[d
->icode
].operand
[0].mode
;
13053 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[1].mode
;
13054 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[2].mode
;
13055 enum rtx_code comparison
= d
->comparison
;
13057 if (VECTOR_MODE_P (mode0
))
13058 op0
= safe_vector_operand (op0
, mode0
);
13059 if (VECTOR_MODE_P (mode1
))
13060 op1
= safe_vector_operand (op1
, mode1
);
13062 /* Swap operands if we have a comparison that isn't available in
13066 rtx tmp
= gen_reg_rtx (mode1
);
13067 emit_move_insn (tmp
, op1
);
13073 || GET_MODE (target
) != tmode
13074 || ! (*insn_data
[d
->icode
].operand
[0].predicate
) (target
, tmode
))
13075 target
= gen_reg_rtx (tmode
);
13077 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op0
, mode0
))
13078 op0
= copy_to_mode_reg (mode0
, op0
);
13079 if (! (*insn_data
[d
->icode
].operand
[2].predicate
) (op1
, mode1
))
13080 op1
= copy_to_mode_reg (mode1
, op1
);
13082 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
13083 pat
= GEN_FCN (d
->icode
) (target
, op0
, op1
, op2
);
13090 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
13093 ix86_expand_sse_comi (const struct builtin_description
*d
, tree arglist
,
13097 tree arg0
= TREE_VALUE (arglist
);
13098 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13099 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13100 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13102 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[0].mode
;
13103 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[1].mode
;
13104 enum rtx_code comparison
= d
->comparison
;
13106 if (VECTOR_MODE_P (mode0
))
13107 op0
= safe_vector_operand (op0
, mode0
);
13108 if (VECTOR_MODE_P (mode1
))
13109 op1
= safe_vector_operand (op1
, mode1
);
13111 /* Swap operands if we have a comparison that isn't available in
13120 target
= gen_reg_rtx (SImode
);
13121 emit_move_insn (target
, const0_rtx
);
13122 target
= gen_rtx_SUBREG (QImode
, target
, 0);
13124 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
13125 op0
= copy_to_mode_reg (mode0
, op0
);
13126 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
13127 op1
= copy_to_mode_reg (mode1
, op1
);
13129 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
13130 pat
= GEN_FCN (d
->icode
) (op0
, op1
);
13134 emit_insn (gen_rtx_SET (VOIDmode
,
13135 gen_rtx_STRICT_LOW_PART (VOIDmode
, target
),
13136 gen_rtx_fmt_ee (comparison
, QImode
,
13140 return SUBREG_REG (target
);
13143 /* Expand an expression EXP that calls a built-in function,
13144 with result going to TARGET if that's convenient
13145 (and in mode MODE if that's convenient).
13146 SUBTARGET may be used as the target for computing one of EXP's operands.
13147 IGNORE is nonzero if the value is to be ignored. */
13150 ix86_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13151 enum machine_mode mode ATTRIBUTE_UNUSED
,
13152 int ignore ATTRIBUTE_UNUSED
)
13154 const struct builtin_description
*d
;
13156 enum insn_code icode
;
13157 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
13158 tree arglist
= TREE_OPERAND (exp
, 1);
13159 tree arg0
, arg1
, arg2
;
13160 rtx op0
, op1
, op2
, pat
;
13161 enum machine_mode tmode
, mode0
, mode1
, mode2
;
13162 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13166 case IX86_BUILTIN_EMMS
:
13167 emit_insn (gen_emms ());
13170 case IX86_BUILTIN_SFENCE
:
13171 emit_insn (gen_sfence ());
13174 case IX86_BUILTIN_PEXTRW
:
13175 case IX86_BUILTIN_PEXTRW128
:
13176 icode
= (fcode
== IX86_BUILTIN_PEXTRW
13177 ? CODE_FOR_mmx_pextrw
13178 : CODE_FOR_sse2_pextrw
);
13179 arg0
= TREE_VALUE (arglist
);
13180 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13181 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13182 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13183 tmode
= insn_data
[icode
].operand
[0].mode
;
13184 mode0
= insn_data
[icode
].operand
[1].mode
;
13185 mode1
= insn_data
[icode
].operand
[2].mode
;
13187 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13188 op0
= copy_to_mode_reg (mode0
, op0
);
13189 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13191 error ("selector must be an integer constant in the range 0..%i",
13192 fcode
== IX86_BUILTIN_PEXTRW
? 3:7);
13193 return gen_reg_rtx (tmode
);
13196 || GET_MODE (target
) != tmode
13197 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13198 target
= gen_reg_rtx (tmode
);
13199 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13205 case IX86_BUILTIN_PINSRW
:
13206 case IX86_BUILTIN_PINSRW128
:
13207 icode
= (fcode
== IX86_BUILTIN_PINSRW
13208 ? CODE_FOR_mmx_pinsrw
13209 : CODE_FOR_sse2_pinsrw
);
13210 arg0
= TREE_VALUE (arglist
);
13211 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13212 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13213 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13214 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13215 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13216 tmode
= insn_data
[icode
].operand
[0].mode
;
13217 mode0
= insn_data
[icode
].operand
[1].mode
;
13218 mode1
= insn_data
[icode
].operand
[2].mode
;
13219 mode2
= insn_data
[icode
].operand
[3].mode
;
13221 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13222 op0
= copy_to_mode_reg (mode0
, op0
);
13223 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13224 op1
= copy_to_mode_reg (mode1
, op1
);
13225 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13227 error ("selector must be an integer constant in the range 0..%i",
13228 fcode
== IX86_BUILTIN_PINSRW
? 15:255);
13232 || GET_MODE (target
) != tmode
13233 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13234 target
= gen_reg_rtx (tmode
);
13235 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13241 case IX86_BUILTIN_MASKMOVQ
:
13242 case IX86_BUILTIN_MASKMOVDQU
:
13243 icode
= (fcode
== IX86_BUILTIN_MASKMOVQ
13244 ? (TARGET_64BIT
? CODE_FOR_mmx_maskmovq_rex
: CODE_FOR_mmx_maskmovq
)
13245 : (TARGET_64BIT
? CODE_FOR_sse2_maskmovdqu_rex64
13246 : CODE_FOR_sse2_maskmovdqu
));
13247 /* Note the arg order is different from the operand order. */
13248 arg1
= TREE_VALUE (arglist
);
13249 arg2
= TREE_VALUE (TREE_CHAIN (arglist
));
13250 arg0
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13251 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13252 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13253 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13254 mode0
= insn_data
[icode
].operand
[0].mode
;
13255 mode1
= insn_data
[icode
].operand
[1].mode
;
13256 mode2
= insn_data
[icode
].operand
[2].mode
;
13258 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13259 op0
= copy_to_mode_reg (mode0
, op0
);
13260 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13261 op1
= copy_to_mode_reg (mode1
, op1
);
13262 if (! (*insn_data
[icode
].operand
[2].predicate
) (op2
, mode2
))
13263 op2
= copy_to_mode_reg (mode2
, op2
);
13264 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
13270 case IX86_BUILTIN_SQRTSS
:
13271 return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv4sf2
, arglist
, target
);
13272 case IX86_BUILTIN_RSQRTSS
:
13273 return ix86_expand_unop1_builtin (CODE_FOR_vmrsqrtv4sf2
, arglist
, target
);
13274 case IX86_BUILTIN_RCPSS
:
13275 return ix86_expand_unop1_builtin (CODE_FOR_vmrcpv4sf2
, arglist
, target
);
13277 case IX86_BUILTIN_LOADAPS
:
13278 return ix86_expand_unop_builtin (CODE_FOR_sse_movaps
, arglist
, target
, 1);
13280 case IX86_BUILTIN_LOADUPS
:
13281 return ix86_expand_unop_builtin (CODE_FOR_sse_movups
, arglist
, target
, 1);
13283 case IX86_BUILTIN_STOREAPS
:
13284 return ix86_expand_store_builtin (CODE_FOR_sse_movaps
, arglist
);
13286 case IX86_BUILTIN_STOREUPS
:
13287 return ix86_expand_store_builtin (CODE_FOR_sse_movups
, arglist
);
13289 case IX86_BUILTIN_LOADSS
:
13290 return ix86_expand_unop_builtin (CODE_FOR_sse_loadss
, arglist
, target
, 1);
13292 case IX86_BUILTIN_STORESS
:
13293 return ix86_expand_store_builtin (CODE_FOR_sse_storess
, arglist
);
13295 case IX86_BUILTIN_LOADHPS
:
13296 case IX86_BUILTIN_LOADLPS
:
13297 case IX86_BUILTIN_LOADHPD
:
13298 case IX86_BUILTIN_LOADLPD
:
13299 icode
= (fcode
== IX86_BUILTIN_LOADHPS
? CODE_FOR_sse_movhps
13300 : fcode
== IX86_BUILTIN_LOADLPS
? CODE_FOR_sse_movlps
13301 : fcode
== IX86_BUILTIN_LOADHPD
? CODE_FOR_sse2_movhpd
13302 : CODE_FOR_sse2_movsd
);
13303 arg0
= TREE_VALUE (arglist
);
13304 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13305 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13306 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13307 tmode
= insn_data
[icode
].operand
[0].mode
;
13308 mode0
= insn_data
[icode
].operand
[1].mode
;
13309 mode1
= insn_data
[icode
].operand
[2].mode
;
13311 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13312 op0
= copy_to_mode_reg (mode0
, op0
);
13313 op1
= gen_rtx_MEM (mode1
, copy_to_mode_reg (Pmode
, op1
));
13315 || GET_MODE (target
) != tmode
13316 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13317 target
= gen_reg_rtx (tmode
);
13318 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13324 case IX86_BUILTIN_STOREHPS
:
13325 case IX86_BUILTIN_STORELPS
:
13326 case IX86_BUILTIN_STOREHPD
:
13327 case IX86_BUILTIN_STORELPD
:
13328 icode
= (fcode
== IX86_BUILTIN_STOREHPS
? CODE_FOR_sse_movhps
13329 : fcode
== IX86_BUILTIN_STORELPS
? CODE_FOR_sse_movlps
13330 : fcode
== IX86_BUILTIN_STOREHPD
? CODE_FOR_sse2_movhpd
13331 : CODE_FOR_sse2_movsd
);
13332 arg0
= TREE_VALUE (arglist
);
13333 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13334 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13335 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13336 mode0
= insn_data
[icode
].operand
[1].mode
;
13337 mode1
= insn_data
[icode
].operand
[2].mode
;
13339 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13340 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13341 op1
= copy_to_mode_reg (mode1
, op1
);
13343 pat
= GEN_FCN (icode
) (op0
, op0
, op1
);
13349 case IX86_BUILTIN_MOVNTPS
:
13350 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf
, arglist
);
13351 case IX86_BUILTIN_MOVNTQ
:
13352 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi
, arglist
);
13354 case IX86_BUILTIN_LDMXCSR
:
13355 op0
= expand_expr (TREE_VALUE (arglist
), NULL_RTX
, VOIDmode
, 0);
13356 target
= assign_386_stack_local (SImode
, 0);
13357 emit_move_insn (target
, op0
);
13358 emit_insn (gen_ldmxcsr (target
));
13361 case IX86_BUILTIN_STMXCSR
:
13362 target
= assign_386_stack_local (SImode
, 0);
13363 emit_insn (gen_stmxcsr (target
));
13364 return copy_to_mode_reg (SImode
, target
);
13366 case IX86_BUILTIN_SHUFPS
:
13367 case IX86_BUILTIN_SHUFPD
:
13368 icode
= (fcode
== IX86_BUILTIN_SHUFPS
13369 ? CODE_FOR_sse_shufps
13370 : CODE_FOR_sse2_shufpd
);
13371 arg0
= TREE_VALUE (arglist
);
13372 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13373 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13374 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13375 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13376 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13377 tmode
= insn_data
[icode
].operand
[0].mode
;
13378 mode0
= insn_data
[icode
].operand
[1].mode
;
13379 mode1
= insn_data
[icode
].operand
[2].mode
;
13380 mode2
= insn_data
[icode
].operand
[3].mode
;
13382 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13383 op0
= copy_to_mode_reg (mode0
, op0
);
13384 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13385 op1
= copy_to_mode_reg (mode1
, op1
);
13386 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13388 /* @@@ better error message */
13389 error ("mask must be an immediate");
13390 return gen_reg_rtx (tmode
);
13393 || GET_MODE (target
) != tmode
13394 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13395 target
= gen_reg_rtx (tmode
);
13396 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13402 case IX86_BUILTIN_PSHUFW
:
13403 case IX86_BUILTIN_PSHUFD
:
13404 case IX86_BUILTIN_PSHUFHW
:
13405 case IX86_BUILTIN_PSHUFLW
:
13406 icode
= ( fcode
== IX86_BUILTIN_PSHUFHW
? CODE_FOR_sse2_pshufhw
13407 : fcode
== IX86_BUILTIN_PSHUFLW
? CODE_FOR_sse2_pshuflw
13408 : fcode
== IX86_BUILTIN_PSHUFD
? CODE_FOR_sse2_pshufd
13409 : CODE_FOR_mmx_pshufw
);
13410 arg0
= TREE_VALUE (arglist
);
13411 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13412 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13413 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13414 tmode
= insn_data
[icode
].operand
[0].mode
;
13415 mode1
= insn_data
[icode
].operand
[1].mode
;
13416 mode2
= insn_data
[icode
].operand
[2].mode
;
13418 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
13419 op0
= copy_to_mode_reg (mode1
, op0
);
13420 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
13422 /* @@@ better error message */
13423 error ("mask must be an immediate");
13427 || GET_MODE (target
) != tmode
13428 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13429 target
= gen_reg_rtx (tmode
);
13430 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13436 case IX86_BUILTIN_PSLLDQI128
:
13437 case IX86_BUILTIN_PSRLDQI128
:
13438 icode
= ( fcode
== IX86_BUILTIN_PSLLDQI128
? CODE_FOR_sse2_ashlti3
13439 : CODE_FOR_sse2_lshrti3
);
13440 arg0
= TREE_VALUE (arglist
);
13441 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13442 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13443 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13444 tmode
= insn_data
[icode
].operand
[0].mode
;
13445 mode1
= insn_data
[icode
].operand
[1].mode
;
13446 mode2
= insn_data
[icode
].operand
[2].mode
;
13448 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
13450 op0
= copy_to_reg (op0
);
13451 op0
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
), 0);
13453 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
13455 error ("shift must be an immediate");
13458 target
= gen_reg_rtx (V2DImode
);
13459 pat
= GEN_FCN (icode
) (simplify_gen_subreg (tmode
, target
, V2DImode
, 0), op0
, op1
);
13465 case IX86_BUILTIN_FEMMS
:
13466 emit_insn (gen_femms ());
13469 case IX86_BUILTIN_PAVGUSB
:
13470 return ix86_expand_binop_builtin (CODE_FOR_pavgusb
, arglist
, target
);
13472 case IX86_BUILTIN_PF2ID
:
13473 return ix86_expand_unop_builtin (CODE_FOR_pf2id
, arglist
, target
, 0);
13475 case IX86_BUILTIN_PFACC
:
13476 return ix86_expand_binop_builtin (CODE_FOR_pfacc
, arglist
, target
);
13478 case IX86_BUILTIN_PFADD
:
13479 return ix86_expand_binop_builtin (CODE_FOR_addv2sf3
, arglist
, target
);
13481 case IX86_BUILTIN_PFCMPEQ
:
13482 return ix86_expand_binop_builtin (CODE_FOR_eqv2sf3
, arglist
, target
);
13484 case IX86_BUILTIN_PFCMPGE
:
13485 return ix86_expand_binop_builtin (CODE_FOR_gev2sf3
, arglist
, target
);
13487 case IX86_BUILTIN_PFCMPGT
:
13488 return ix86_expand_binop_builtin (CODE_FOR_gtv2sf3
, arglist
, target
);
13490 case IX86_BUILTIN_PFMAX
:
13491 return ix86_expand_binop_builtin (CODE_FOR_pfmaxv2sf3
, arglist
, target
);
13493 case IX86_BUILTIN_PFMIN
:
13494 return ix86_expand_binop_builtin (CODE_FOR_pfminv2sf3
, arglist
, target
);
13496 case IX86_BUILTIN_PFMUL
:
13497 return ix86_expand_binop_builtin (CODE_FOR_mulv2sf3
, arglist
, target
);
13499 case IX86_BUILTIN_PFRCP
:
13500 return ix86_expand_unop_builtin (CODE_FOR_pfrcpv2sf2
, arglist
, target
, 0);
13502 case IX86_BUILTIN_PFRCPIT1
:
13503 return ix86_expand_binop_builtin (CODE_FOR_pfrcpit1v2sf3
, arglist
, target
);
13505 case IX86_BUILTIN_PFRCPIT2
:
13506 return ix86_expand_binop_builtin (CODE_FOR_pfrcpit2v2sf3
, arglist
, target
);
13508 case IX86_BUILTIN_PFRSQIT1
:
13509 return ix86_expand_binop_builtin (CODE_FOR_pfrsqit1v2sf3
, arglist
, target
);
13511 case IX86_BUILTIN_PFRSQRT
:
13512 return ix86_expand_unop_builtin (CODE_FOR_pfrsqrtv2sf2
, arglist
, target
, 0);
13514 case IX86_BUILTIN_PFSUB
:
13515 return ix86_expand_binop_builtin (CODE_FOR_subv2sf3
, arglist
, target
);
13517 case IX86_BUILTIN_PFSUBR
:
13518 return ix86_expand_binop_builtin (CODE_FOR_subrv2sf3
, arglist
, target
);
13520 case IX86_BUILTIN_PI2FD
:
13521 return ix86_expand_unop_builtin (CODE_FOR_floatv2si2
, arglist
, target
, 0);
13523 case IX86_BUILTIN_PMULHRW
:
13524 return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3
, arglist
, target
);
13526 case IX86_BUILTIN_PF2IW
:
13527 return ix86_expand_unop_builtin (CODE_FOR_pf2iw
, arglist
, target
, 0);
13529 case IX86_BUILTIN_PFNACC
:
13530 return ix86_expand_binop_builtin (CODE_FOR_pfnacc
, arglist
, target
);
13532 case IX86_BUILTIN_PFPNACC
:
13533 return ix86_expand_binop_builtin (CODE_FOR_pfpnacc
, arglist
, target
);
13535 case IX86_BUILTIN_PI2FW
:
13536 return ix86_expand_unop_builtin (CODE_FOR_pi2fw
, arglist
, target
, 0);
13538 case IX86_BUILTIN_PSWAPDSI
:
13539 return ix86_expand_unop_builtin (CODE_FOR_pswapdv2si2
, arglist
, target
, 0);
13541 case IX86_BUILTIN_PSWAPDSF
:
13542 return ix86_expand_unop_builtin (CODE_FOR_pswapdv2sf2
, arglist
, target
, 0);
13544 case IX86_BUILTIN_SSE_ZERO
:
13545 target
= gen_reg_rtx (V4SFmode
);
13546 emit_insn (gen_sse_clrv4sf (target
, CONST0_RTX (V4SFmode
)));
13549 case IX86_BUILTIN_MMX_ZERO
:
13550 target
= gen_reg_rtx (DImode
);
13551 emit_insn (gen_mmx_clrdi (target
));
13554 case IX86_BUILTIN_CLRTI
:
13555 target
= gen_reg_rtx (V2DImode
);
13556 emit_insn (gen_sse2_clrti (simplify_gen_subreg (TImode
, target
, V2DImode
, 0)));
13560 case IX86_BUILTIN_SQRTSD
:
13561 return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv2df2
, arglist
, target
);
13562 case IX86_BUILTIN_LOADAPD
:
13563 return ix86_expand_unop_builtin (CODE_FOR_sse2_movapd
, arglist
, target
, 1);
13564 case IX86_BUILTIN_LOADUPD
:
13565 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd
, arglist
, target
, 1);
13567 case IX86_BUILTIN_STOREAPD
:
13568 return ix86_expand_store_builtin (CODE_FOR_sse2_movapd
, arglist
);
13569 case IX86_BUILTIN_STOREUPD
:
13570 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd
, arglist
);
13572 case IX86_BUILTIN_LOADSD
:
13573 return ix86_expand_unop_builtin (CODE_FOR_sse2_loadsd
, arglist
, target
, 1);
13575 case IX86_BUILTIN_STORESD
:
13576 return ix86_expand_store_builtin (CODE_FOR_sse2_storesd
, arglist
);
13578 case IX86_BUILTIN_SETPD1
:
13579 target
= assign_386_stack_local (DFmode
, 0);
13580 arg0
= TREE_VALUE (arglist
);
13581 emit_move_insn (adjust_address (target
, DFmode
, 0),
13582 expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
13583 op0
= gen_reg_rtx (V2DFmode
);
13584 emit_insn (gen_sse2_loadsd (op0
, adjust_address (target
, V2DFmode
, 0)));
13585 emit_insn (gen_sse2_shufpd (op0
, op0
, op0
, const0_rtx
));
13588 case IX86_BUILTIN_SETPD
:
13589 target
= assign_386_stack_local (V2DFmode
, 0);
13590 arg0
= TREE_VALUE (arglist
);
13591 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13592 emit_move_insn (adjust_address (target
, DFmode
, 0),
13593 expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
13594 emit_move_insn (adjust_address (target
, DFmode
, 8),
13595 expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0));
13596 op0
= gen_reg_rtx (V2DFmode
);
13597 emit_insn (gen_sse2_movapd (op0
, target
));
13600 case IX86_BUILTIN_LOADRPD
:
13601 target
= ix86_expand_unop_builtin (CODE_FOR_sse2_movapd
, arglist
,
13602 gen_reg_rtx (V2DFmode
), 1);
13603 emit_insn (gen_sse2_shufpd (target
, target
, target
, const1_rtx
));
13606 case IX86_BUILTIN_LOADPD1
:
13607 target
= ix86_expand_unop_builtin (CODE_FOR_sse2_loadsd
, arglist
,
13608 gen_reg_rtx (V2DFmode
), 1);
13609 emit_insn (gen_sse2_shufpd (target
, target
, target
, const0_rtx
));
13612 case IX86_BUILTIN_STOREPD1
:
13613 return ix86_expand_store_builtin (CODE_FOR_sse2_movapd
, arglist
);
13614 case IX86_BUILTIN_STORERPD
:
13615 return ix86_expand_store_builtin (CODE_FOR_sse2_movapd
, arglist
);
13617 case IX86_BUILTIN_CLRPD
:
13618 target
= gen_reg_rtx (V2DFmode
);
13619 emit_insn (gen_sse_clrv2df (target
));
13622 case IX86_BUILTIN_MFENCE
:
13623 emit_insn (gen_sse2_mfence ());
13625 case IX86_BUILTIN_LFENCE
:
13626 emit_insn (gen_sse2_lfence ());
13629 case IX86_BUILTIN_CLFLUSH
:
13630 arg0
= TREE_VALUE (arglist
);
13631 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13632 icode
= CODE_FOR_sse2_clflush
;
13633 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, Pmode
))
13634 op0
= copy_to_mode_reg (Pmode
, op0
);
13636 emit_insn (gen_sse2_clflush (op0
));
13639 case IX86_BUILTIN_MOVNTPD
:
13640 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df
, arglist
);
13641 case IX86_BUILTIN_MOVNTDQ
:
13642 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di
, arglist
);
13643 case IX86_BUILTIN_MOVNTI
:
13644 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi
, arglist
);
13646 case IX86_BUILTIN_LOADDQA
:
13647 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqa
, arglist
, target
, 1);
13648 case IX86_BUILTIN_LOADDQU
:
13649 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu
, arglist
, target
, 1);
13650 case IX86_BUILTIN_LOADD
:
13651 return ix86_expand_unop_builtin (CODE_FOR_sse2_loadd
, arglist
, target
, 1);
13653 case IX86_BUILTIN_STOREDQA
:
13654 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqa
, arglist
);
13655 case IX86_BUILTIN_STOREDQU
:
13656 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu
, arglist
);
13657 case IX86_BUILTIN_STORED
:
13658 return ix86_expand_store_builtin (CODE_FOR_sse2_stored
, arglist
);
13660 case IX86_BUILTIN_MONITOR
:
13661 arg0
= TREE_VALUE (arglist
);
13662 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13663 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13664 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13665 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13666 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13668 op0
= copy_to_mode_reg (SImode
, op0
);
13670 op1
= copy_to_mode_reg (SImode
, op1
);
13672 op2
= copy_to_mode_reg (SImode
, op2
);
13673 emit_insn (gen_monitor (op0
, op1
, op2
));
13676 case IX86_BUILTIN_MWAIT
:
13677 arg0
= TREE_VALUE (arglist
);
13678 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13679 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13680 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13682 op0
= copy_to_mode_reg (SImode
, op0
);
13684 op1
= copy_to_mode_reg (SImode
, op1
);
13685 emit_insn (gen_mwait (op0
, op1
));
13688 case IX86_BUILTIN_LOADDDUP
:
13689 return ix86_expand_unop_builtin (CODE_FOR_loadddup
, arglist
, target
, 1);
13691 case IX86_BUILTIN_LDDQU
:
13692 return ix86_expand_unop_builtin (CODE_FOR_lddqu
, arglist
, target
,
13699 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13700 if (d
->code
== fcode
)
13702 /* Compares are treated specially. */
13703 if (d
->icode
== CODE_FOR_maskcmpv4sf3
13704 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
13705 || d
->icode
== CODE_FOR_maskncmpv4sf3
13706 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
13707 || d
->icode
== CODE_FOR_maskcmpv2df3
13708 || d
->icode
== CODE_FOR_vmmaskcmpv2df3
13709 || d
->icode
== CODE_FOR_maskncmpv2df3
13710 || d
->icode
== CODE_FOR_vmmaskncmpv2df3
)
13711 return ix86_expand_sse_compare (d
, arglist
, target
);
13713 return ix86_expand_binop_builtin (d
->icode
, arglist
, target
);
13716 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13717 if (d
->code
== fcode
)
13718 return ix86_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
13720 for (i
= 0, d
= bdesc_comi
; i
< ARRAY_SIZE (bdesc_comi
); i
++, d
++)
13721 if (d
->code
== fcode
)
13722 return ix86_expand_sse_comi (d
, arglist
, target
);
13724 /* @@@ Should really do something sensible here. */
13728 /* Store OPERAND to the memory after reload is completed. This means
13729 that we can't easily use assign_stack_local. */
13731 ix86_force_to_memory (enum machine_mode mode
, rtx operand
)
13734 if (!reload_completed
)
13736 if (TARGET_RED_ZONE
)
13738 result
= gen_rtx_MEM (mode
,
13739 gen_rtx_PLUS (Pmode
,
13741 GEN_INT (-RED_ZONE_SIZE
)));
13742 emit_move_insn (result
, operand
);
13744 else if (!TARGET_RED_ZONE
&& TARGET_64BIT
)
13750 operand
= gen_lowpart (DImode
, operand
);
13754 gen_rtx_SET (VOIDmode
,
13755 gen_rtx_MEM (DImode
,
13756 gen_rtx_PRE_DEC (DImode
,
13757 stack_pointer_rtx
)),
13763 result
= gen_rtx_MEM (mode
, stack_pointer_rtx
);
13772 split_di (&operand
, 1, operands
, operands
+ 1);
13774 gen_rtx_SET (VOIDmode
,
13775 gen_rtx_MEM (SImode
,
13776 gen_rtx_PRE_DEC (Pmode
,
13777 stack_pointer_rtx
)),
13780 gen_rtx_SET (VOIDmode
,
13781 gen_rtx_MEM (SImode
,
13782 gen_rtx_PRE_DEC (Pmode
,
13783 stack_pointer_rtx
)),
13788 /* It is better to store HImodes as SImodes. */
13789 if (!TARGET_PARTIAL_REG_STALL
)
13790 operand
= gen_lowpart (SImode
, operand
);
13794 gen_rtx_SET (VOIDmode
,
13795 gen_rtx_MEM (GET_MODE (operand
),
13796 gen_rtx_PRE_DEC (SImode
,
13797 stack_pointer_rtx
)),
13803 result
= gen_rtx_MEM (mode
, stack_pointer_rtx
);
13808 /* Free operand from the memory. */
13810 ix86_free_from_memory (enum machine_mode mode
)
13812 if (!TARGET_RED_ZONE
)
13816 if (mode
== DImode
|| TARGET_64BIT
)
13818 else if (mode
== HImode
&& TARGET_PARTIAL_REG_STALL
)
13822 /* Use LEA to deallocate stack space. In peephole2 it will be converted
13823 to pop or add instruction if registers are available. */
13824 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13825 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
13830 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
13831 QImode must go into class Q_REGS.
13832 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
13833 movdf to do mem-to-mem moves through integer regs. */
13835 ix86_preferred_reload_class (rtx x
, enum reg_class
class)
13837 if (GET_CODE (x
) == CONST_VECTOR
&& x
!= CONST0_RTX (GET_MODE (x
)))
13839 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != VOIDmode
)
13841 /* SSE can't load any constant directly yet. */
13842 if (SSE_CLASS_P (class))
13844 /* Floats can load 0 and 1. */
13845 if (MAYBE_FLOAT_CLASS_P (class) && standard_80387_constant_p (x
))
13847 /* Limit class to non-SSE. Use GENERAL_REGS if possible. */
13848 if (MAYBE_SSE_CLASS_P (class))
13849 return (reg_class_subset_p (class, GENERAL_REGS
)
13850 ? GENERAL_REGS
: FLOAT_REGS
);
13854 /* General regs can load everything. */
13855 if (reg_class_subset_p (class, GENERAL_REGS
))
13856 return GENERAL_REGS
;
13857 /* In case we haven't resolved FLOAT or SSE yet, give up. */
13858 if (MAYBE_FLOAT_CLASS_P (class) || MAYBE_SSE_CLASS_P (class))
13861 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x
))
13863 if (GET_MODE (x
) == QImode
&& ! reg_class_subset_p (class, Q_REGS
))
13868 /* If we are copying between general and FP registers, we need a memory
13869 location. The same is true for SSE and MMX registers.
13871 The macro can't work reliably when one of the CLASSES is class containing
13872 registers from multiple units (SSE, MMX, integer). We avoid this by never
13873 combining those units in single alternative in the machine description.
13874 Ensure that this constraint holds to avoid unexpected surprises.
13876 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
13877 enforce these sanity checks. */
13879 ix86_secondary_memory_needed (enum reg_class class1
, enum reg_class class2
,
13880 enum machine_mode mode
, int strict
)
13882 if (MAYBE_FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class1
)
13883 || MAYBE_FLOAT_CLASS_P (class2
) != FLOAT_CLASS_P (class2
)
13884 || MAYBE_SSE_CLASS_P (class1
) != SSE_CLASS_P (class1
)
13885 || MAYBE_SSE_CLASS_P (class2
) != SSE_CLASS_P (class2
)
13886 || MAYBE_MMX_CLASS_P (class1
) != MMX_CLASS_P (class1
)
13887 || MAYBE_MMX_CLASS_P (class2
) != MMX_CLASS_P (class2
))
13894 return (FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class2
)
13895 || ((SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
)
13896 || MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
))
13897 && ((mode
!= SImode
&& (mode
!= DImode
|| !TARGET_64BIT
))
13898 || (!TARGET_INTER_UNIT_MOVES
&& !optimize_size
))));
13900 /* Return the cost of moving data from a register in class CLASS1 to
13901 one in class CLASS2.
13903 It is not required that the cost always equal 2 when FROM is the same as TO;
13904 on some machines it is expensive to move between registers if they are not
13905 general registers. */
13907 ix86_register_move_cost (enum machine_mode mode
, enum reg_class class1
,
13908 enum reg_class class2
)
13910 /* In case we require secondary memory, compute cost of the store followed
13911 by load. In order to avoid bad register allocation choices, we need
13912 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
13914 if (ix86_secondary_memory_needed (class1
, class2
, mode
, 0))
13918 cost
+= MAX (MEMORY_MOVE_COST (mode
, class1
, 0),
13919 MEMORY_MOVE_COST (mode
, class1
, 1));
13920 cost
+= MAX (MEMORY_MOVE_COST (mode
, class2
, 0),
13921 MEMORY_MOVE_COST (mode
, class2
, 1));
13923 /* In case of copying from general_purpose_register we may emit multiple
13924 stores followed by single load causing memory size mismatch stall.
13925 Count this as arbitrarily high cost of 20. */
13926 if (CLASS_MAX_NREGS (class1
, mode
) > CLASS_MAX_NREGS (class2
, mode
))
13929 /* In the case of FP/MMX moves, the registers actually overlap, and we
13930 have to switch modes in order to treat them differently. */
13931 if ((MMX_CLASS_P (class1
) && MAYBE_FLOAT_CLASS_P (class2
))
13932 || (MMX_CLASS_P (class2
) && MAYBE_FLOAT_CLASS_P (class1
)))
13938 /* Moves between SSE/MMX and integer unit are expensive. */
13939 if (MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
)
13940 || SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
))
13941 return ix86_cost
->mmxsse_to_integer
;
13942 if (MAYBE_FLOAT_CLASS_P (class1
))
13943 return ix86_cost
->fp_move
;
13944 if (MAYBE_SSE_CLASS_P (class1
))
13945 return ix86_cost
->sse_move
;
13946 if (MAYBE_MMX_CLASS_P (class1
))
13947 return ix86_cost
->mmx_move
;
13951 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
13953 ix86_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
13955 /* Flags and only flags can only hold CCmode values. */
13956 if (CC_REGNO_P (regno
))
13957 return GET_MODE_CLASS (mode
) == MODE_CC
;
13958 if (GET_MODE_CLASS (mode
) == MODE_CC
13959 || GET_MODE_CLASS (mode
) == MODE_RANDOM
13960 || GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
13962 if (FP_REGNO_P (regno
))
13963 return VALID_FP_MODE_P (mode
);
13964 if (SSE_REGNO_P (regno
))
13965 return (TARGET_SSE
? VALID_SSE_REG_MODE (mode
) : 0);
13966 if (MMX_REGNO_P (regno
))
13968 ? VALID_MMX_REG_MODE (mode
) || VALID_MMX_REG_MODE_3DNOW (mode
) : 0);
13969 /* We handle both integer and floats in the general purpose registers.
13970 In future we should be able to handle vector modes as well. */
13971 if (!VALID_INT_MODE_P (mode
) && !VALID_FP_MODE_P (mode
))
13973 /* Take care for QImode values - they can be in non-QI regs, but then
13974 they do cause partial register stalls. */
13975 if (regno
< 4 || mode
!= QImode
|| TARGET_64BIT
)
13977 return reload_in_progress
|| reload_completed
|| !TARGET_PARTIAL_REG_STALL
;
13980 /* Return the cost of moving data of mode M between a
13981 register and memory. A value of 2 is the default; this cost is
13982 relative to those in `REGISTER_MOVE_COST'.
13984 If moving between registers and memory is more expensive than
13985 between two registers, you should define this macro to express the
13988 Model also increased moving costs of QImode registers in non
13992 ix86_memory_move_cost (enum machine_mode mode
, enum reg_class
class, int in
)
13994 if (FLOAT_CLASS_P (class))
14011 return in
? ix86_cost
->fp_load
[index
] : ix86_cost
->fp_store
[index
];
14013 if (SSE_CLASS_P (class))
14016 switch (GET_MODE_SIZE (mode
))
14030 return in
? ix86_cost
->sse_load
[index
] : ix86_cost
->sse_store
[index
];
14032 if (MMX_CLASS_P (class))
14035 switch (GET_MODE_SIZE (mode
))
14046 return in
? ix86_cost
->mmx_load
[index
] : ix86_cost
->mmx_store
[index
];
14048 switch (GET_MODE_SIZE (mode
))
14052 return (Q_CLASS_P (class) ? ix86_cost
->int_load
[0]
14053 : ix86_cost
->movzbl_load
);
14055 return (Q_CLASS_P (class) ? ix86_cost
->int_store
[0]
14056 : ix86_cost
->int_store
[0] + 4);
14059 return in
? ix86_cost
->int_load
[1] : ix86_cost
->int_store
[1];
14061 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
14062 if (mode
== TFmode
)
14064 return ((in
? ix86_cost
->int_load
[2] : ix86_cost
->int_store
[2])
14065 * (((int) GET_MODE_SIZE (mode
)
14066 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
));
14070 /* Compute a (partial) cost for rtx X. Return true if the complete
14071 cost has been computed, and false if subexpressions should be
14072 scanned. In either case, *TOTAL contains the cost result. */
14075 ix86_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
14077 enum machine_mode mode
= GET_MODE (x
);
14085 if (TARGET_64BIT
&& !x86_64_immediate_operand (x
, VOIDmode
))
14087 else if (TARGET_64BIT
&& !x86_64_zext_immediate_operand (x
, VOIDmode
))
14089 else if (flag_pic
&& SYMBOLIC_CONST (x
)
14091 || (!GET_CODE (x
) != LABEL_REF
14092 && (GET_CODE (x
) != SYMBOL_REF
14093 || !SYMBOL_REF_LOCAL_P (x
)))))
14100 if (mode
== VOIDmode
)
14103 switch (standard_80387_constant_p (x
))
14108 default: /* Other constants */
14113 /* Start with (MEM (SYMBOL_REF)), since that's where
14114 it'll probably end up. Add a penalty for size. */
14115 *total
= (COSTS_N_INSNS (1)
14116 + (flag_pic
!= 0 && !TARGET_64BIT
)
14117 + (mode
== SFmode
? 0 : mode
== DFmode
? 1 : 2));
14123 /* The zero extensions is often completely free on x86_64, so make
14124 it as cheap as possible. */
14125 if (TARGET_64BIT
&& mode
== DImode
14126 && GET_MODE (XEXP (x
, 0)) == SImode
)
14128 else if (TARGET_ZERO_EXTEND_WITH_AND
)
14129 *total
= COSTS_N_INSNS (ix86_cost
->add
);
14131 *total
= COSTS_N_INSNS (ix86_cost
->movzx
);
14135 *total
= COSTS_N_INSNS (ix86_cost
->movsx
);
14139 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
14140 && (GET_MODE (XEXP (x
, 0)) != DImode
|| TARGET_64BIT
))
14142 HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
14145 *total
= COSTS_N_INSNS (ix86_cost
->add
);
14148 if ((value
== 2 || value
== 3)
14149 && ix86_cost
->lea
<= ix86_cost
->shift_const
)
14151 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14161 if (!TARGET_64BIT
&& GET_MODE (XEXP (x
, 0)) == DImode
)
14163 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
14165 if (INTVAL (XEXP (x
, 1)) > 32)
14166 *total
= COSTS_N_INSNS(ix86_cost
->shift_const
+ 2);
14168 *total
= COSTS_N_INSNS(ix86_cost
->shift_const
* 2);
14172 if (GET_CODE (XEXP (x
, 1)) == AND
)
14173 *total
= COSTS_N_INSNS(ix86_cost
->shift_var
* 2);
14175 *total
= COSTS_N_INSNS(ix86_cost
->shift_var
* 6 + 2);
14180 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
14181 *total
= COSTS_N_INSNS (ix86_cost
->shift_const
);
14183 *total
= COSTS_N_INSNS (ix86_cost
->shift_var
);
14188 if (FLOAT_MODE_P (mode
))
14190 *total
= COSTS_N_INSNS (ix86_cost
->fmul
);
14195 rtx op0
= XEXP (x
, 0);
14196 rtx op1
= XEXP (x
, 1);
14198 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
14200 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
14201 for (nbits
= 0; value
!= 0; value
&= value
- 1)
14205 /* This is arbitrary. */
14208 /* Compute costs correctly for widening multiplication. */
14209 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op1
) == ZERO_EXTEND
)
14210 && GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0))) * 2
14211 == GET_MODE_SIZE (mode
))
14213 int is_mulwiden
= 0;
14214 enum machine_mode inner_mode
= GET_MODE (op0
);
14216 if (GET_CODE (op0
) == GET_CODE (op1
))
14217 is_mulwiden
= 1, op1
= XEXP (op1
, 0);
14218 else if (GET_CODE (op1
) == CONST_INT
)
14220 if (GET_CODE (op0
) == SIGN_EXTEND
)
14221 is_mulwiden
= trunc_int_for_mode (INTVAL (op1
), inner_mode
)
14224 is_mulwiden
= !(INTVAL (op1
) & ~GET_MODE_MASK (inner_mode
));
14228 op0
= XEXP (op0
, 0), mode
= GET_MODE (op0
);
14231 *total
= COSTS_N_INSNS (ix86_cost
->mult_init
[MODE_INDEX (mode
)]
14232 + nbits
* ix86_cost
->mult_bit
)
14233 + rtx_cost (op0
, outer_code
) + rtx_cost (op1
, outer_code
);
14242 if (FLOAT_MODE_P (mode
))
14243 *total
= COSTS_N_INSNS (ix86_cost
->fdiv
);
14245 *total
= COSTS_N_INSNS (ix86_cost
->divide
[MODE_INDEX (mode
)]);
14249 if (FLOAT_MODE_P (mode
))
14250 *total
= COSTS_N_INSNS (ix86_cost
->fadd
);
14251 else if (GET_MODE_CLASS (mode
) == MODE_INT
14252 && GET_MODE_BITSIZE (mode
) <= GET_MODE_BITSIZE (Pmode
))
14254 if (GET_CODE (XEXP (x
, 0)) == PLUS
14255 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
14256 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
14257 && CONSTANT_P (XEXP (x
, 1)))
14259 HOST_WIDE_INT val
= INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1));
14260 if (val
== 2 || val
== 4 || val
== 8)
14262 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14263 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 1), outer_code
);
14264 *total
+= rtx_cost (XEXP (XEXP (XEXP (x
, 0), 0), 0),
14266 *total
+= rtx_cost (XEXP (x
, 1), outer_code
);
14270 else if (GET_CODE (XEXP (x
, 0)) == MULT
14271 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
14273 HOST_WIDE_INT val
= INTVAL (XEXP (XEXP (x
, 0), 1));
14274 if (val
== 2 || val
== 4 || val
== 8)
14276 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14277 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
);
14278 *total
+= rtx_cost (XEXP (x
, 1), outer_code
);
14282 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
14284 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14285 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
);
14286 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 1), outer_code
);
14287 *total
+= rtx_cost (XEXP (x
, 1), outer_code
);
14294 if (FLOAT_MODE_P (mode
))
14296 *total
= COSTS_N_INSNS (ix86_cost
->fadd
);
14304 if (!TARGET_64BIT
&& mode
== DImode
)
14306 *total
= (COSTS_N_INSNS (ix86_cost
->add
) * 2
14307 + (rtx_cost (XEXP (x
, 0), outer_code
)
14308 << (GET_MODE (XEXP (x
, 0)) != DImode
))
14309 + (rtx_cost (XEXP (x
, 1), outer_code
)
14310 << (GET_MODE (XEXP (x
, 1)) != DImode
)));
14316 if (FLOAT_MODE_P (mode
))
14318 *total
= COSTS_N_INSNS (ix86_cost
->fchs
);
14324 if (!TARGET_64BIT
&& mode
== DImode
)
14325 *total
= COSTS_N_INSNS (ix86_cost
->add
* 2);
14327 *total
= COSTS_N_INSNS (ix86_cost
->add
);
14331 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTRACT
14332 && XEXP (XEXP (x
, 0), 1) == const1_rtx
14333 && GET_CODE (XEXP (XEXP (x
, 0), 2)) == CONST_INT
14334 && XEXP (x
, 1) == const0_rtx
)
14336 /* This kind of construct is implemented using test[bwl].
14337 Treat it as if we had an AND. */
14338 *total
= (COSTS_N_INSNS (ix86_cost
->add
)
14339 + rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
14340 + rtx_cost (const1_rtx
, outer_code
));
14346 if (!TARGET_SSE_MATH
|| !VALID_SSE_REG_MODE (mode
))
14351 if (FLOAT_MODE_P (mode
))
14352 *total
= COSTS_N_INSNS (ix86_cost
->fabs
);
14356 if (FLOAT_MODE_P (mode
))
14357 *total
= COSTS_N_INSNS (ix86_cost
->fsqrt
);
14361 if (XINT (x
, 1) == UNSPEC_TP
)
14370 #if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION)
14372 ix86_svr3_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
14375 fputs ("\tpushl $", asm_out_file
);
14376 assemble_name (asm_out_file
, XSTR (symbol
, 0));
14377 fputc ('\n', asm_out_file
);
14383 static int current_machopic_label_num
;
14385 /* Given a symbol name and its associated stub, write out the
14386 definition of the stub. */
14389 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
14391 unsigned int length
;
14392 char *binder_name
, *symbol_name
, lazy_ptr_name
[32];
14393 int label
= ++current_machopic_label_num
;
14395 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
14396 symb
= (*targetm
.strip_name_encoding
) (symb
);
14398 length
= strlen (stub
);
14399 binder_name
= alloca (length
+ 32);
14400 GEN_BINDER_NAME_FOR_STUB (binder_name
, stub
, length
);
14402 length
= strlen (symb
);
14403 symbol_name
= alloca (length
+ 32);
14404 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
14406 sprintf (lazy_ptr_name
, "L%d$lz", label
);
14409 machopic_picsymbol_stub_section ();
14411 machopic_symbol_stub_section ();
14413 fprintf (file
, "%s:\n", stub
);
14414 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
14418 fprintf (file
, "\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n", label
, label
);
14419 fprintf (file
, "\tmovl %s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name
, label
);
14420 fprintf (file
, "\tjmp %%edx\n");
14423 fprintf (file
, "\tjmp *%s\n", lazy_ptr_name
);
14425 fprintf (file
, "%s:\n", binder_name
);
14429 fprintf (file
, "\tlea %s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name
, label
);
14430 fprintf (file
, "\tpushl %%eax\n");
14433 fprintf (file
, "\t pushl $%s\n", lazy_ptr_name
);
14435 fprintf (file
, "\tjmp dyld_stub_binding_helper\n");
14437 machopic_lazy_symbol_ptr_section ();
14438 fprintf (file
, "%s:\n", lazy_ptr_name
);
14439 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
14440 fprintf (file
, "\t.long %s\n", binder_name
);
14442 #endif /* TARGET_MACHO */
14444 /* Order the registers for register allocator. */
14447 x86_order_regs_for_local_alloc (void)
14452 /* First allocate the local general purpose registers. */
14453 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
14454 if (GENERAL_REGNO_P (i
) && call_used_regs
[i
])
14455 reg_alloc_order
[pos
++] = i
;
14457 /* Global general purpose registers. */
14458 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
14459 if (GENERAL_REGNO_P (i
) && !call_used_regs
[i
])
14460 reg_alloc_order
[pos
++] = i
;
14462 /* x87 registers come first in case we are doing FP math
14464 if (!TARGET_SSE_MATH
)
14465 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
14466 reg_alloc_order
[pos
++] = i
;
14468 /* SSE registers. */
14469 for (i
= FIRST_SSE_REG
; i
<= LAST_SSE_REG
; i
++)
14470 reg_alloc_order
[pos
++] = i
;
14471 for (i
= FIRST_REX_SSE_REG
; i
<= LAST_REX_SSE_REG
; i
++)
14472 reg_alloc_order
[pos
++] = i
;
14474 /* x87 registers. */
14475 if (TARGET_SSE_MATH
)
14476 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
14477 reg_alloc_order
[pos
++] = i
;
14479 for (i
= FIRST_MMX_REG
; i
<= LAST_MMX_REG
; i
++)
14480 reg_alloc_order
[pos
++] = i
;
14482 /* Initialize the rest of array as we do not allocate some registers
14484 while (pos
< FIRST_PSEUDO_REGISTER
)
14485 reg_alloc_order
[pos
++] = 0;
14488 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
14489 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
14492 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
14493 struct attribute_spec.handler. */
14495 ix86_handle_struct_attribute (tree
*node
, tree name
,
14496 tree args ATTRIBUTE_UNUSED
,
14497 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
14500 if (DECL_P (*node
))
14502 if (TREE_CODE (*node
) == TYPE_DECL
)
14503 type
= &TREE_TYPE (*node
);
14508 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
14509 || TREE_CODE (*type
) == UNION_TYPE
)))
14511 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
14512 *no_add_attrs
= true;
14515 else if ((is_attribute_p ("ms_struct", name
)
14516 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
14517 || ((is_attribute_p ("gcc_struct", name
)
14518 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
14520 warning ("%qs incompatible attribute ignored",
14521 IDENTIFIER_POINTER (name
));
14522 *no_add_attrs
= true;
14529 ix86_ms_bitfield_layout_p (tree record_type
)
14531 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
14532 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
14533 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
14536 /* Returns an expression indicating where the this parameter is
14537 located on entry to the FUNCTION. */
14540 x86_this_parameter (tree function
)
14542 tree type
= TREE_TYPE (function
);
14546 int n
= aggregate_value_p (TREE_TYPE (type
), type
) != 0;
14547 return gen_rtx_REG (DImode
, x86_64_int_parameter_registers
[n
]);
14550 if (ix86_function_regparm (type
, function
) > 0)
14554 parm
= TYPE_ARG_TYPES (type
);
14555 /* Figure out whether or not the function has a variable number of
14557 for (; parm
; parm
= TREE_CHAIN (parm
))
14558 if (TREE_VALUE (parm
) == void_type_node
)
14560 /* If not, the this parameter is in the first argument. */
14564 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type
)))
14566 return gen_rtx_REG (SImode
, regno
);
14570 if (aggregate_value_p (TREE_TYPE (type
), type
))
14571 return gen_rtx_MEM (SImode
, plus_constant (stack_pointer_rtx
, 8));
14573 return gen_rtx_MEM (SImode
, plus_constant (stack_pointer_rtx
, 4));
14576 /* Determine whether x86_output_mi_thunk can succeed. */
14579 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED
,
14580 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
14581 HOST_WIDE_INT vcall_offset
, tree function
)
14583 /* 64-bit can handle anything. */
14587 /* For 32-bit, everything's fine if we have one free register. */
14588 if (ix86_function_regparm (TREE_TYPE (function
), function
) < 3)
14591 /* Need a free register for vcall_offset. */
14595 /* Need a free register for GOT references. */
14596 if (flag_pic
&& !(*targetm
.binds_local_p
) (function
))
14599 /* Otherwise ok. */
14603 /* Output the assembler code for a thunk function. THUNK_DECL is the
14604 declaration for the thunk function itself, FUNCTION is the decl for
14605 the target function. DELTA is an immediate constant offset to be
14606 added to THIS. If VCALL_OFFSET is nonzero, the word at
14607 *(*this + vcall_offset) should be added to THIS. */
14610 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
14611 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
14612 HOST_WIDE_INT vcall_offset
, tree function
)
14615 rtx
this = x86_this_parameter (function
);
14618 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
14619 pull it in now and let DELTA benefit. */
14622 else if (vcall_offset
)
14624 /* Put the this parameter into %eax. */
14626 xops
[1] = this_reg
= gen_rtx_REG (Pmode
, 0);
14627 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops
);
14630 this_reg
= NULL_RTX
;
14632 /* Adjust the this parameter by a fixed constant. */
14635 xops
[0] = GEN_INT (delta
);
14636 xops
[1] = this_reg
? this_reg
: this;
14639 if (!x86_64_general_operand (xops
[0], DImode
))
14641 tmp
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 2 /* R10 */);
14643 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops
);
14647 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops
);
14650 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops
);
14653 /* Adjust the this parameter by a value stored in the vtable. */
14657 tmp
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 2 /* R10 */);
14660 int tmp_regno
= 2 /* ECX */;
14661 if (lookup_attribute ("fastcall",
14662 TYPE_ATTRIBUTES (TREE_TYPE (function
))))
14663 tmp_regno
= 0 /* EAX */;
14664 tmp
= gen_rtx_REG (SImode
, tmp_regno
);
14667 xops
[0] = gen_rtx_MEM (Pmode
, this_reg
);
14670 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops
);
14672 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops
);
14674 /* Adjust the this parameter. */
14675 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (tmp
, vcall_offset
));
14676 if (TARGET_64BIT
&& !memory_operand (xops
[0], Pmode
))
14678 rtx tmp2
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
14679 xops
[0] = GEN_INT (vcall_offset
);
14681 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops
);
14682 xops
[0] = gen_rtx_MEM (Pmode
, gen_rtx_PLUS (Pmode
, tmp
, tmp2
));
14684 xops
[1] = this_reg
;
14686 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops
);
14688 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops
);
14691 /* If necessary, drop THIS back to its stack slot. */
14692 if (this_reg
&& this_reg
!= this)
14694 xops
[0] = this_reg
;
14696 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops
);
14699 xops
[0] = XEXP (DECL_RTL (function
), 0);
14702 if (!flag_pic
|| (*targetm
.binds_local_p
) (function
))
14703 output_asm_insn ("jmp\t%P0", xops
);
14706 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, xops
[0]), UNSPEC_GOTPCREL
);
14707 tmp
= gen_rtx_CONST (Pmode
, tmp
);
14708 tmp
= gen_rtx_MEM (QImode
, tmp
);
14710 output_asm_insn ("jmp\t%A0", xops
);
14715 if (!flag_pic
|| (*targetm
.binds_local_p
) (function
))
14716 output_asm_insn ("jmp\t%P0", xops
);
14721 rtx sym_ref
= XEXP (DECL_RTL (function
), 0);
14722 tmp
= (gen_rtx_SYMBOL_REF
14724 machopic_indirection_name (sym_ref
, /*stub_p=*/true)));
14725 tmp
= gen_rtx_MEM (QImode
, tmp
);
14727 output_asm_insn ("jmp\t%0", xops
);
14730 #endif /* TARGET_MACHO */
14732 tmp
= gen_rtx_REG (SImode
, 2 /* ECX */);
14733 output_set_got (tmp
);
14736 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops
);
14737 output_asm_insn ("jmp\t{*}%1", xops
);
14743 x86_file_start (void)
14745 default_file_start ();
14746 if (X86_FILE_START_VERSION_DIRECTIVE
)
14747 fputs ("\t.version\t\"01.01\"\n", asm_out_file
);
14748 if (X86_FILE_START_FLTUSED
)
14749 fputs ("\t.global\t__fltused\n", asm_out_file
);
14750 if (ix86_asm_dialect
== ASM_INTEL
)
14751 fputs ("\t.intel_syntax\n", asm_out_file
);
14755 x86_field_alignment (tree field
, int computed
)
14757 enum machine_mode mode
;
14758 tree type
= TREE_TYPE (field
);
14760 if (TARGET_64BIT
|| TARGET_ALIGN_DOUBLE
)
14762 mode
= TYPE_MODE (TREE_CODE (type
) == ARRAY_TYPE
14763 ? get_inner_array_type (type
) : type
);
14764 if (mode
== DFmode
|| mode
== DCmode
14765 || GET_MODE_CLASS (mode
) == MODE_INT
14766 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
14767 return MIN (32, computed
);
14771 /* Output assembler code to FILE to increment profiler label # LABELNO
14772 for profiling a function entry. */
14774 x86_function_profiler (FILE *file
, int labelno ATTRIBUTE_UNUSED
)
14779 #ifndef NO_PROFILE_COUNTERS
14780 fprintf (file
, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX
, labelno
);
14782 fprintf (file
, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME
);
14786 #ifndef NO_PROFILE_COUNTERS
14787 fprintf (file
, "\tmovq\t$%sP%d,%%r11\n", LPREFIX
, labelno
);
14789 fprintf (file
, "\tcall\t%s\n", MCOUNT_NAME
);
14793 #ifndef NO_PROFILE_COUNTERS
14794 fprintf (file
, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
14795 LPREFIX
, labelno
, PROFILE_COUNT_REGISTER
);
14797 fprintf (file
, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME
);
14801 #ifndef NO_PROFILE_COUNTERS
14802 fprintf (file
, "\tmovl\t$%sP%d,%%%s\n", LPREFIX
, labelno
,
14803 PROFILE_COUNT_REGISTER
);
14805 fprintf (file
, "\tcall\t%s\n", MCOUNT_NAME
);
14809 /* We don't have exact information about the insn sizes, but we may assume
14810 quite safely that we are informed about all 1 byte insns and memory
14811 address sizes. This is enough to eliminate unnecessary padding in
14815 min_insn_size (rtx insn
)
14819 if (!INSN_P (insn
) || !active_insn_p (insn
))
14822 /* Discard alignments we've emit and jump instructions. */
14823 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
14824 && XINT (PATTERN (insn
), 1) == UNSPECV_ALIGN
)
14826 if (GET_CODE (insn
) == JUMP_INSN
14827 && (GET_CODE (PATTERN (insn
)) == ADDR_VEC
14828 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
))
14831 /* Important case - calls are always 5 bytes.
14832 It is common to have many calls in the row. */
14833 if (GET_CODE (insn
) == CALL_INSN
14834 && symbolic_reference_mentioned_p (PATTERN (insn
))
14835 && !SIBLING_CALL_P (insn
))
14837 if (get_attr_length (insn
) <= 1)
14840 /* For normal instructions we may rely on the sizes of addresses
14841 and the presence of symbol to require 4 bytes of encoding.
14842 This is not the case for jumps where references are PC relative. */
14843 if (GET_CODE (insn
) != JUMP_INSN
)
14845 l
= get_attr_length_address (insn
);
14846 if (l
< 4 && symbolic_reference_mentioned_p (PATTERN (insn
)))
14855 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
14859 ix86_avoid_jump_misspredicts (void)
14861 rtx insn
, start
= get_insns ();
14862 int nbytes
= 0, njumps
= 0;
14865 /* Look for all minimal intervals of instructions containing 4 jumps.
14866 The intervals are bounded by START and INSN. NBYTES is the total
14867 size of instructions in the interval including INSN and not including
14868 START. When the NBYTES is smaller than 16 bytes, it is possible
14869 that the end of START and INSN ends up in the same 16byte page.
14871 The smallest offset in the page INSN can start is the case where START
14872 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
14873 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
14875 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14878 nbytes
+= min_insn_size (insn
);
14880 fprintf(dump_file
, "Insn %i estimated to %i bytes\n",
14881 INSN_UID (insn
), min_insn_size (insn
));
14882 if ((GET_CODE (insn
) == JUMP_INSN
14883 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
14884 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
14885 || GET_CODE (insn
) == CALL_INSN
)
14892 start
= NEXT_INSN (start
);
14893 if ((GET_CODE (start
) == JUMP_INSN
14894 && GET_CODE (PATTERN (start
)) != ADDR_VEC
14895 && GET_CODE (PATTERN (start
)) != ADDR_DIFF_VEC
)
14896 || GET_CODE (start
) == CALL_INSN
)
14897 njumps
--, isjump
= 1;
14900 nbytes
-= min_insn_size (start
);
14905 fprintf (dump_file
, "Interval %i to %i has %i bytes\n",
14906 INSN_UID (start
), INSN_UID (insn
), nbytes
);
14908 if (njumps
== 3 && isjump
&& nbytes
< 16)
14910 int padsize
= 15 - nbytes
+ min_insn_size (insn
);
14913 fprintf (dump_file
, "Padding insn %i by %i bytes!\n",
14914 INSN_UID (insn
), padsize
);
14915 emit_insn_before (gen_align (GEN_INT (padsize
)), insn
);
14920 /* AMD Athlon works faster
14921 when RET is not destination of conditional jump or directly preceded
14922 by other jump instruction. We avoid the penalty by inserting NOP just
14923 before the RET instructions in such cases. */
14925 ix86_pad_returns (void)
14930 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
14932 basic_block bb
= e
->src
;
14933 rtx ret
= BB_END (bb
);
14935 bool replace
= false;
14937 if (GET_CODE (ret
) != JUMP_INSN
|| GET_CODE (PATTERN (ret
)) != RETURN
14938 || !maybe_hot_bb_p (bb
))
14940 for (prev
= PREV_INSN (ret
); prev
; prev
= PREV_INSN (prev
))
14941 if (active_insn_p (prev
) || GET_CODE (prev
) == CODE_LABEL
)
14943 if (prev
&& GET_CODE (prev
) == CODE_LABEL
)
14948 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14949 if (EDGE_FREQUENCY (e
) && e
->src
->index
>= 0
14950 && !(e
->flags
& EDGE_FALLTHRU
))
14955 prev
= prev_active_insn (ret
);
14957 && ((GET_CODE (prev
) == JUMP_INSN
&& any_condjump_p (prev
))
14958 || GET_CODE (prev
) == CALL_INSN
))
14960 /* Empty functions get branch mispredict even when the jump destination
14961 is not visible to us. */
14962 if (!prev
&& cfun
->function_frequency
> FUNCTION_FREQUENCY_UNLIKELY_EXECUTED
)
14967 emit_insn_before (gen_return_internal_long (), ret
);
14973 /* Implement machine specific optimizations. We implement padding of returns
14974 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
14978 if (TARGET_ATHLON_K8
&& optimize
&& !optimize_size
)
14979 ix86_pad_returns ();
14980 if (TARGET_FOUR_JUMP_LIMIT
&& optimize
&& !optimize_size
)
14981 ix86_avoid_jump_misspredicts ();
14984 /* Return nonzero when QImode register that must be represented via REX prefix
14987 x86_extended_QIreg_mentioned_p (rtx insn
)
14990 extract_insn_cached (insn
);
14991 for (i
= 0; i
< recog_data
.n_operands
; i
++)
14992 if (REG_P (recog_data
.operand
[i
])
14993 && REGNO (recog_data
.operand
[i
]) >= 4)
14998 /* Return nonzero when P points to register encoded via REX prefix.
14999 Called via for_each_rtx. */
15001 extended_reg_mentioned_1 (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
15003 unsigned int regno
;
15006 regno
= REGNO (*p
);
15007 return REX_INT_REGNO_P (regno
) || REX_SSE_REGNO_P (regno
);
15010 /* Return true when INSN mentions register that must be encoded using REX
15013 x86_extended_reg_mentioned_p (rtx insn
)
15015 return for_each_rtx (&PATTERN (insn
), extended_reg_mentioned_1
, NULL
);
15018 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
15019 optabs would emit if we didn't have TFmode patterns. */
15022 x86_emit_floatuns (rtx operands
[2])
15024 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
15025 enum machine_mode mode
, inmode
;
15027 inmode
= GET_MODE (operands
[1]);
15028 if (inmode
!= SImode
15029 && inmode
!= DImode
)
15033 in
= force_reg (inmode
, operands
[1]);
15034 mode
= GET_MODE (out
);
15035 neglab
= gen_label_rtx ();
15036 donelab
= gen_label_rtx ();
15037 i1
= gen_reg_rtx (Pmode
);
15038 f0
= gen_reg_rtx (mode
);
15040 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, Pmode
, 0, neglab
);
15042 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
15043 emit_jump_insn (gen_jump (donelab
));
15046 emit_label (neglab
);
15048 i0
= expand_simple_binop (Pmode
, LSHIFTRT
, in
, const1_rtx
, NULL
, 1, OPTAB_DIRECT
);
15049 i1
= expand_simple_binop (Pmode
, AND
, in
, const1_rtx
, NULL
, 1, OPTAB_DIRECT
);
15050 i0
= expand_simple_binop (Pmode
, IOR
, i0
, i1
, i0
, 1, OPTAB_DIRECT
);
15051 expand_float (f0
, i0
, 0);
15052 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
15054 emit_label (donelab
);
15057 /* Initialize vector TARGET via VALS. */
15059 ix86_expand_vector_init (rtx target
, rtx vals
)
15061 enum machine_mode mode
= GET_MODE (target
);
15062 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
15063 int n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
15066 for (i
= n_elts
- 1; i
>= 0; i
--)
15067 if (GET_CODE (XVECEXP (vals
, 0, i
)) != CONST_INT
15068 && GET_CODE (XVECEXP (vals
, 0, i
)) != CONST_DOUBLE
)
15071 /* Few special cases first...
15072 ... constants are best loaded from constant pool. */
15075 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
15079 /* ... values where only first field is non-constant are best loaded
15080 from the pool and overwritten via move later. */
15083 rtx op
= simplify_gen_subreg (mode
, XVECEXP (vals
, 0, 0),
15084 GET_MODE_INNER (mode
), 0);
15086 op
= force_reg (mode
, op
);
15087 XVECEXP (vals
, 0, 0) = CONST0_RTX (GET_MODE_INNER (mode
));
15088 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
15089 switch (GET_MODE (target
))
15092 emit_insn (gen_sse2_movsd (target
, target
, op
));
15095 emit_insn (gen_sse_movss (target
, target
, op
));
15103 /* And the busy sequence doing rotations. */
15104 switch (GET_MODE (target
))
15109 simplify_gen_subreg (V2DFmode
, XVECEXP (vals
, 0, 0), DFmode
, 0);
15111 simplify_gen_subreg (V2DFmode
, XVECEXP (vals
, 0, 1), DFmode
, 0);
15113 vecop0
= force_reg (V2DFmode
, vecop0
);
15114 vecop1
= force_reg (V2DFmode
, vecop1
);
15115 emit_insn (gen_sse2_unpcklpd (target
, vecop0
, vecop1
));
15121 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 0), SFmode
, 0);
15123 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 1), SFmode
, 0);
15125 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 2), SFmode
, 0);
15127 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 3), SFmode
, 0);
15128 rtx tmp1
= gen_reg_rtx (V4SFmode
);
15129 rtx tmp2
= gen_reg_rtx (V4SFmode
);
15131 vecop0
= force_reg (V4SFmode
, vecop0
);
15132 vecop1
= force_reg (V4SFmode
, vecop1
);
15133 vecop2
= force_reg (V4SFmode
, vecop2
);
15134 vecop3
= force_reg (V4SFmode
, vecop3
);
15135 emit_insn (gen_sse_unpcklps (tmp1
, vecop1
, vecop3
));
15136 emit_insn (gen_sse_unpcklps (tmp2
, vecop0
, vecop2
));
15137 emit_insn (gen_sse_unpcklps (target
, tmp2
, tmp1
));
15145 /* Implements target hook vector_mode_supported_p. */
15147 ix86_vector_mode_supported_p (enum machine_mode mode
)
15150 && VALID_SSE_REG_MODE (mode
))
15153 else if (TARGET_MMX
15154 && VALID_MMX_REG_MODE (mode
))
15157 else if (TARGET_3DNOW
15158 && VALID_MMX_REG_MODE_3DNOW (mode
))
15165 /* Worker function for TARGET_MD_ASM_CLOBBERS.
15167 We do this in the new i386 backend to maintain source compatibility
15168 with the old cc0-based compiler. */
15171 ix86_md_asm_clobbers (tree clobbers
)
15173 clobbers
= tree_cons (NULL_TREE
, build_string (5, "flags"),
15175 clobbers
= tree_cons (NULL_TREE
, build_string (4, "fpsr"),
15177 clobbers
= tree_cons (NULL_TREE
, build_string (7, "dirflag"),
15182 /* Worker function for REVERSE_CONDITION. */
15185 ix86_reverse_condition (enum rtx_code code
, enum machine_mode mode
)
15187 return (mode
!= CCFPmode
&& mode
!= CCFPUmode
15188 ? reverse_condition (code
)
15189 : reverse_condition_maybe_unordered (code
));
15192 /* Output code to perform an x87 FP register move, from OPERANDS[1]
15196 output_387_reg_move (rtx insn
, rtx
*operands
)
15198 if (REG_P (operands
[1])
15199 && find_regno_note (insn
, REG_DEAD
, REGNO (operands
[1])))
15201 if (REGNO (operands
[0]) == FIRST_STACK_REG
15202 && TARGET_USE_FFREEP
)
15203 return "ffreep\t%y0";
15204 return "fstp\t%y0";
15206 if (STACK_TOP_P (operands
[0]))
15207 return "fld%z1\t%y1";
15211 /* Output code to perform a conditional jump to LABEL, if C2 flag in
15212 FP status register is set. */
15215 ix86_emit_fp_unordered_jump (rtx label
)
15217 rtx reg
= gen_reg_rtx (HImode
);
15220 emit_insn (gen_x86_fnstsw_1 (reg
));
15222 if (TARGET_USE_SAHF
)
15224 emit_insn (gen_x86_sahf_1 (reg
));
15226 temp
= gen_rtx_REG (CCmode
, FLAGS_REG
);
15227 temp
= gen_rtx_UNORDERED (VOIDmode
, temp
, const0_rtx
);
15231 emit_insn (gen_testqi_ext_ccno_0 (reg
, GEN_INT (0x04)));
15233 temp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
15234 temp
= gen_rtx_NE (VOIDmode
, temp
, const0_rtx
);
15237 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
15238 gen_rtx_LABEL_REF (VOIDmode
, label
),
15240 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
15241 emit_jump_insn (temp
);
15244 /* Output code to perform a log1p XFmode calculation. */
15246 void ix86_emit_i387_log1p (rtx op0
, rtx op1
)
15248 rtx label1
= gen_label_rtx ();
15249 rtx label2
= gen_label_rtx ();
15251 rtx tmp
= gen_reg_rtx (XFmode
);
15252 rtx tmp2
= gen_reg_rtx (XFmode
);
15254 emit_insn (gen_absxf2 (tmp
, op1
));
15255 emit_insn (gen_cmpxf (tmp
,
15256 CONST_DOUBLE_FROM_REAL_VALUE (
15257 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode
),
15259 emit_jump_insn (gen_bge (label1
));
15261 emit_move_insn (tmp2
, standard_80387_constant_rtx (4)); /* fldln2 */
15262 emit_insn (gen_fyl2xp1_xf3 (op0
, tmp2
, op1
));
15263 emit_jump (label2
);
15265 emit_label (label1
);
15266 emit_move_insn (tmp
, CONST1_RTX (XFmode
));
15267 emit_insn (gen_addxf3 (tmp
, op1
, tmp
));
15268 emit_move_insn (tmp2
, standard_80387_constant_rtx (4)); /* fldln2 */
15269 emit_insn (gen_fyl2x_xf3 (op0
, tmp2
, tmp
));
15271 emit_label (label2
);
15274 /* Solaris named-section hook. Parameters are as for
15275 named_section_real. */
15278 i386_solaris_elf_named_section (const char *name
, unsigned int flags
,
15281 /* With Binutils 2.15, the "@unwind" marker must be specified on
15282 every occurrence of the ".eh_frame" section, not just the first
15285 && strcmp (name
, ".eh_frame") == 0)
15287 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",@unwind\n", name
,
15288 flags
& SECTION_WRITE
? "aw" : "a");
15291 default_elf_asm_named_section (name
, flags
, decl
);
15294 #include "gt-i386.h"