1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
42 #include "basic-block.h"
45 #ifndef CHECK_STACK_LIMIT
46 #define CHECK_STACK_LIMIT -1
49 /* Processor costs (relative to an add) */
50 struct processor_costs i386_cost
= { /* 386 specific costs */
51 1, /* cost of an add instruction */
52 1, /* cost of a lea instruction */
53 3, /* variable shift costs */
54 2, /* constant shift costs */
55 6, /* cost of starting a multiply */
56 1, /* cost of multiply per each bit set */
57 23, /* cost of a divide/mod */
58 15, /* "large" insn */
60 4, /* cost for loading QImode using movzbl */
61 {2, 4, 2}, /* cost of loading integer registers
62 in QImode, HImode and SImode.
63 Relative to reg-reg move (2). */
64 {2, 4, 2}, /* cost of storing integer registers */
65 2, /* cost of reg,reg fld/fst */
66 {8, 8, 8}, /* cost of loading fp registers
67 in SFmode, DFmode and XFmode */
68 {8, 8, 8}, /* cost of loading integer registers */
69 2, /* cost of moving MMX register */
70 {4, 8}, /* cost of loading MMX registers
71 in SImode and DImode */
72 {4, 8}, /* cost of storing MMX registers
73 in SImode and DImode */
74 2, /* cost of moving SSE register */
75 {4, 8, 16}, /* cost of loading SSE registers
76 in SImode, DImode and TImode */
77 {4, 8, 16}, /* cost of storing SSE registers
78 in SImode, DImode and TImode */
79 3, /* MMX or SSE register to integer */
82 struct processor_costs i486_cost
= { /* 486 specific costs */
83 1, /* cost of an add instruction */
84 1, /* cost of a lea instruction */
85 3, /* variable shift costs */
86 2, /* constant shift costs */
87 12, /* cost of starting a multiply */
88 1, /* cost of multiply per each bit set */
89 40, /* cost of a divide/mod */
90 15, /* "large" insn */
92 4, /* cost for loading QImode using movzbl */
93 {2, 4, 2}, /* cost of loading integer registers
94 in QImode, HImode and SImode.
95 Relative to reg-reg move (2). */
96 {2, 4, 2}, /* cost of storing integer registers */
97 2, /* cost of reg,reg fld/fst */
98 {8, 8, 8}, /* cost of loading fp registers
99 in SFmode, DFmode and XFmode */
100 {8, 8, 8}, /* cost of loading integer registers */
101 2, /* cost of moving MMX register */
102 {4, 8}, /* cost of loading MMX registers
103 in SImode and DImode */
104 {4, 8}, /* cost of storing MMX registers
105 in SImode and DImode */
106 2, /* cost of moving SSE register */
107 {4, 8, 16}, /* cost of loading SSE registers
108 in SImode, DImode and TImode */
109 {4, 8, 16}, /* cost of storing SSE registers
110 in SImode, DImode and TImode */
111 3 /* MMX or SSE register to integer */
114 struct processor_costs pentium_cost
= {
115 1, /* cost of an add instruction */
116 1, /* cost of a lea instruction */
117 4, /* variable shift costs */
118 1, /* constant shift costs */
119 11, /* cost of starting a multiply */
120 0, /* cost of multiply per each bit set */
121 25, /* cost of a divide/mod */
122 8, /* "large" insn */
124 6, /* cost for loading QImode using movzbl */
125 {2, 4, 2}, /* cost of loading integer registers
126 in QImode, HImode and SImode.
127 Relative to reg-reg move (2). */
128 {2, 4, 2}, /* cost of storing integer registers */
129 2, /* cost of reg,reg fld/fst */
130 {2, 2, 6}, /* cost of loading fp registers
131 in SFmode, DFmode and XFmode */
132 {4, 4, 6}, /* cost of loading integer registers */
133 8, /* cost of moving MMX register */
134 {8, 8}, /* cost of loading MMX registers
135 in SImode and DImode */
136 {8, 8}, /* cost of storing MMX registers
137 in SImode and DImode */
138 2, /* cost of moving SSE register */
139 {4, 8, 16}, /* cost of loading SSE registers
140 in SImode, DImode and TImode */
141 {4, 8, 16}, /* cost of storing SSE registers
142 in SImode, DImode and TImode */
143 3 /* MMX or SSE register to integer */
146 struct processor_costs pentiumpro_cost
= {
147 1, /* cost of an add instruction */
148 1, /* cost of a lea instruction */
149 1, /* variable shift costs */
150 1, /* constant shift costs */
151 4, /* cost of starting a multiply */
152 0, /* cost of multiply per each bit set */
153 17, /* cost of a divide/mod */
154 8, /* "large" insn */
156 2, /* cost for loading QImode using movzbl */
157 {4, 4, 4}, /* cost of loading integer registers
158 in QImode, HImode and SImode.
159 Relative to reg-reg move (2). */
160 {2, 2, 2}, /* cost of storing integer registers */
161 2, /* cost of reg,reg fld/fst */
162 {2, 2, 6}, /* cost of loading fp registers
163 in SFmode, DFmode and XFmode */
164 {4, 4, 6}, /* cost of loading integer registers */
165 2, /* cost of moving MMX register */
166 {2, 2}, /* cost of loading MMX registers
167 in SImode and DImode */
168 {2, 2}, /* cost of storing MMX registers
169 in SImode and DImode */
170 2, /* cost of moving SSE register */
171 {2, 2, 8}, /* cost of loading SSE registers
172 in SImode, DImode and TImode */
173 {2, 2, 8}, /* cost of storing SSE registers
174 in SImode, DImode and TImode */
175 3 /* MMX or SSE register to integer */
178 struct processor_costs k6_cost
= {
179 1, /* cost of an add instruction */
180 2, /* cost of a lea instruction */
181 1, /* variable shift costs */
182 1, /* constant shift costs */
183 3, /* cost of starting a multiply */
184 0, /* cost of multiply per each bit set */
185 18, /* cost of a divide/mod */
186 8, /* "large" insn */
188 3, /* cost for loading QImode using movzbl */
189 {4, 5, 4}, /* cost of loading integer registers
190 in QImode, HImode and SImode.
191 Relative to reg-reg move (2). */
192 {2, 3, 2}, /* cost of storing integer registers */
193 4, /* cost of reg,reg fld/fst */
194 {6, 6, 6}, /* cost of loading fp registers
195 in SFmode, DFmode and XFmode */
196 {4, 4, 4}, /* cost of loading integer registers */
197 2, /* cost of moving MMX register */
198 {2, 2}, /* cost of loading MMX registers
199 in SImode and DImode */
200 {2, 2}, /* cost of storing MMX registers
201 in SImode and DImode */
202 2, /* cost of moving SSE register */
203 {2, 2, 8}, /* cost of loading SSE registers
204 in SImode, DImode and TImode */
205 {2, 2, 8}, /* cost of storing SSE registers
206 in SImode, DImode and TImode */
207 6 /* MMX or SSE register to integer */
210 struct processor_costs athlon_cost
= {
211 1, /* cost of an add instruction */
212 2, /* cost of a lea instruction */
213 1, /* variable shift costs */
214 1, /* constant shift costs */
215 5, /* cost of starting a multiply */
216 0, /* cost of multiply per each bit set */
217 42, /* cost of a divide/mod */
218 8, /* "large" insn */
220 4, /* cost for loading QImode using movzbl */
221 {4, 5, 4}, /* cost of loading integer registers
222 in QImode, HImode and SImode.
223 Relative to reg-reg move (2). */
224 {2, 3, 2}, /* cost of storing integer registers */
225 4, /* cost of reg,reg fld/fst */
226 {6, 6, 20}, /* cost of loading fp registers
227 in SFmode, DFmode and XFmode */
228 {4, 4, 16}, /* cost of loading integer registers */
229 2, /* cost of moving MMX register */
230 {2, 2}, /* cost of loading MMX registers
231 in SImode and DImode */
232 {2, 2}, /* cost of storing MMX registers
233 in SImode and DImode */
234 2, /* cost of moving SSE register */
235 {2, 2, 8}, /* cost of loading SSE registers
236 in SImode, DImode and TImode */
237 {2, 2, 8}, /* cost of storing SSE registers
238 in SImode, DImode and TImode */
239 6 /* MMX or SSE register to integer */
242 struct processor_costs pentium4_cost
= {
243 1, /* cost of an add instruction */
244 1, /* cost of a lea instruction */
245 8, /* variable shift costs */
246 8, /* constant shift costs */
247 30, /* cost of starting a multiply */
248 0, /* cost of multiply per each bit set */
249 112, /* cost of a divide/mod */
250 16, /* "large" insn */
252 2, /* cost for loading QImode using movzbl */
253 {4, 5, 4}, /* cost of loading integer registers
254 in QImode, HImode and SImode.
255 Relative to reg-reg move (2). */
256 {2, 3, 2}, /* cost of storing integer registers */
257 2, /* cost of reg,reg fld/fst */
258 {2, 2, 6}, /* cost of loading fp registers
259 in SFmode, DFmode and XFmode */
260 {4, 4, 6}, /* cost of loading integer registers */
261 2, /* cost of moving MMX register */
262 {2, 2}, /* cost of loading MMX registers
263 in SImode and DImode */
264 {2, 2}, /* cost of storing MMX registers
265 in SImode and DImode */
266 12, /* cost of moving SSE register */
267 {12, 12, 12}, /* cost of loading SSE registers
268 in SImode, DImode and TImode */
269 {2, 2, 8}, /* cost of storing SSE registers
270 in SImode, DImode and TImode */
271 10, /* MMX or SSE register to integer */
274 struct processor_costs
*ix86_cost
= &pentium_cost
;
276 /* Processor feature/optimization bitmasks. */
277 #define m_386 (1<<PROCESSOR_I386)
278 #define m_486 (1<<PROCESSOR_I486)
279 #define m_PENT (1<<PROCESSOR_PENTIUM)
280 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
281 #define m_K6 (1<<PROCESSOR_K6)
282 #define m_ATHLON (1<<PROCESSOR_ATHLON)
283 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
285 const int x86_use_leave
= m_386
| m_K6
| m_ATHLON
;
286 const int x86_push_memory
= m_386
| m_K6
| m_ATHLON
| m_PENT4
;
287 const int x86_zero_extend_with_and
= m_486
| m_PENT
;
288 const int x86_movx
= m_ATHLON
| m_PPRO
| m_PENT4
/* m_386 | m_K6 */;
289 const int x86_double_with_add
= ~m_386
;
290 const int x86_use_bit_test
= m_386
;
291 const int x86_unroll_strlen
= m_486
| m_PENT
| m_PPRO
| m_ATHLON
| m_K6
;
292 const int x86_cmove
= m_PPRO
| m_ATHLON
| m_PENT4
;
293 const int x86_deep_branch
= m_PPRO
| m_K6
| m_ATHLON
| m_PENT4
;
294 const int x86_use_sahf
= m_PPRO
| m_K6
| m_PENT4
;
295 const int x86_partial_reg_stall
= m_PPRO
;
296 const int x86_use_loop
= m_K6
;
297 const int x86_use_fiop
= ~(m_PPRO
| m_ATHLON
| m_PENT
);
298 const int x86_use_mov0
= m_K6
;
299 const int x86_use_cltd
= ~(m_PENT
| m_K6
);
300 const int x86_read_modify_write
= ~m_PENT
;
301 const int x86_read_modify
= ~(m_PENT
| m_PPRO
);
302 const int x86_split_long_moves
= m_PPRO
;
303 const int x86_promote_QImode
= m_K6
| m_PENT
| m_386
| m_486
;
304 const int x86_single_stringop
= m_386
| m_PENT4
;
305 const int x86_qimode_math
= ~(0);
306 const int x86_promote_qi_regs
= 0;
307 const int x86_himode_math
= ~(m_PPRO
);
308 const int x86_promote_hi_regs
= m_PPRO
;
309 const int x86_sub_esp_4
= m_ATHLON
| m_PPRO
| m_PENT4
;
310 const int x86_sub_esp_8
= m_ATHLON
| m_PPRO
| m_386
| m_486
| m_PENT4
;
311 const int x86_add_esp_4
= m_ATHLON
| m_K6
| m_PENT4
;
312 const int x86_add_esp_8
= m_ATHLON
| m_PPRO
| m_K6
| m_386
| m_486
| m_PENT4
;
313 const int x86_integer_DFmode_moves
= ~(m_ATHLON
| m_PENT4
);
314 const int x86_partial_reg_dependency
= m_ATHLON
| m_PENT4
;
315 const int x86_memory_mismatch_stall
= m_ATHLON
| m_PENT4
;
317 #define AT_BP(mode) (gen_rtx_MEM ((mode), hard_frame_pointer_rtx))
319 const char * const hi_reg_name
[] = HI_REGISTER_NAMES
;
320 const char * const qi_reg_name
[] = QI_REGISTER_NAMES
;
321 const char * const qi_high_reg_name
[] = QI_HIGH_REGISTER_NAMES
;
323 /* Array of the smallest class containing reg number REGNO, indexed by
324 REGNO. Used by REGNO_REG_CLASS in i386.h. */
326 enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
] =
329 AREG
, DREG
, CREG
, BREG
,
331 SIREG
, DIREG
, NON_Q_REGS
, NON_Q_REGS
,
333 FP_TOP_REG
, FP_SECOND_REG
, FLOAT_REGS
, FLOAT_REGS
,
334 FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
,
337 /* flags, fpsr, dirflag, frame */
338 NO_REGS
, NO_REGS
, NO_REGS
, NON_Q_REGS
,
339 SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
,
341 MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
,
345 /* The "default" register map. */
347 int const dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
349 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
350 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
351 -1, -1, -1, -1, /* arg, flags, fpsr, dir */
352 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
353 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
356 /* The "default" register map used in 64bit mode. */
357 int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
] =
359 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
360 33, 34, 35, 36, 37, 38, 39, 40 /* fp regs */
361 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
362 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
363 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
364 8,9,10,11,12,13,14,15, /* extended integer registers */
365 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
368 /* Define the register numbers to be used in Dwarf debugging information.
369 The SVR4 reference port C compiler uses the following register numbers
370 in its Dwarf output code:
371 0 for %eax (gcc regno = 0)
372 1 for %ecx (gcc regno = 2)
373 2 for %edx (gcc regno = 1)
374 3 for %ebx (gcc regno = 3)
375 4 for %esp (gcc regno = 7)
376 5 for %ebp (gcc regno = 6)
377 6 for %esi (gcc regno = 4)
378 7 for %edi (gcc regno = 5)
379 The following three DWARF register numbers are never generated by
380 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
381 believes these numbers have these meanings.
382 8 for %eip (no gcc equivalent)
383 9 for %eflags (gcc regno = 17)
384 10 for %trapno (no gcc equivalent)
385 It is not at all clear how we should number the FP stack registers
386 for the x86 architecture. If the version of SDB on x86/svr4 were
387 a bit less brain dead with respect to floating-point then we would
388 have a precedent to follow with respect to DWARF register numbers
389 for x86 FP registers, but the SDB on x86/svr4 is so completely
390 broken with respect to FP registers that it is hardly worth thinking
391 of it as something to strive for compatibility with.
392 The version of x86/svr4 SDB I have at the moment does (partially)
393 seem to believe that DWARF register number 11 is associated with
394 the x86 register %st(0), but that's about all. Higher DWARF
395 register numbers don't seem to be associated with anything in
396 particular, and even for DWARF regno 11, SDB only seems to under-
397 stand that it should say that a variable lives in %st(0) (when
398 asked via an `=' command) if we said it was in DWARF regno 11,
399 but SDB still prints garbage when asked for the value of the
400 variable in question (via a `/' command).
401 (Also note that the labels SDB prints for various FP stack regs
402 when doing an `x' command are all wrong.)
403 Note that these problems generally don't affect the native SVR4
404 C compiler because it doesn't allow the use of -O with -g and
405 because when it is *not* optimizing, it allocates a memory
406 location for each floating-point variable, and the memory
407 location is what gets described in the DWARF AT_location
408 attribute for the variable in question.
409 Regardless of the severe mental illness of the x86/svr4 SDB, we
410 do something sensible here and we use the following DWARF
411 register numbers. Note that these are all stack-top-relative
413 11 for %st(0) (gcc regno = 8)
414 12 for %st(1) (gcc regno = 9)
415 13 for %st(2) (gcc regno = 10)
416 14 for %st(3) (gcc regno = 11)
417 15 for %st(4) (gcc regno = 12)
418 16 for %st(5) (gcc regno = 13)
419 17 for %st(6) (gcc regno = 14)
420 18 for %st(7) (gcc regno = 15)
422 int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
424 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
425 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
426 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
427 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
428 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
429 -1, -1, -1, -1, -1, -1, -1, -1, /* extemded integer registers */
430 -1, -1, -1, -1, -1, -1, -1, -1, /* extemded SSE registers */
433 /* Test and compare insns in i386.md store the information needed to
434 generate branch and scc insns here. */
436 struct rtx_def
*ix86_compare_op0
= NULL_RTX
;
437 struct rtx_def
*ix86_compare_op1
= NULL_RTX
;
439 #define MAX_386_STACK_LOCALS 2
441 /* Define the structure for the machine field in struct function. */
442 struct machine_function
444 rtx stack_locals
[(int) MAX_MACHINE_MODE
][MAX_386_STACK_LOCALS
];
445 int accesses_prev_frame
;
448 #define ix86_stack_locals (cfun->machine->stack_locals)
450 /* Structure describing stack frame layout.
451 Stack grows downward:
457 saved frame pointer if frame_pointer_needed
458 <- HARD_FRAME_POINTER
464 > to_allocate <- FRAME_POINTER
475 int outgoing_arguments_size
;
477 HOST_WIDE_INT to_allocate
;
478 /* The offsets relative to ARG_POINTER. */
479 HOST_WIDE_INT frame_pointer_offset
;
480 HOST_WIDE_INT hard_frame_pointer_offset
;
481 HOST_WIDE_INT stack_pointer_offset
;
484 /* which cpu are we scheduling for */
485 enum processor_type ix86_cpu
;
487 /* which instruction set architecture to use. */
490 /* Strings to hold which cpu and instruction set architecture to use. */
491 const char *ix86_cpu_string
; /* for -mcpu=<xxx> */
492 const char *ix86_arch_string
; /* for -march=<xxx> */
494 /* # of registers to use to pass arguments. */
495 const char *ix86_regparm_string
;
497 /* ix86_regparm_string as a number */
500 /* Alignment to use for loops and jumps: */
502 /* Power of two alignment for loops. */
503 const char *ix86_align_loops_string
;
505 /* Power of two alignment for non-loop jumps. */
506 const char *ix86_align_jumps_string
;
508 /* Power of two alignment for stack boundary in bytes. */
509 const char *ix86_preferred_stack_boundary_string
;
511 /* Preferred alignment for stack boundary in bits. */
512 int ix86_preferred_stack_boundary
;
514 /* Values 1-5: see jump.c */
515 int ix86_branch_cost
;
516 const char *ix86_branch_cost_string
;
518 /* Power of two alignment for functions. */
519 int ix86_align_funcs
;
520 const char *ix86_align_funcs_string
;
522 /* Power of two alignment for loops. */
523 int ix86_align_loops
;
525 /* Power of two alignment for non-loop jumps. */
526 int ix86_align_jumps
;
528 static void output_pic_addr_const
PARAMS ((FILE *, rtx
, int));
529 static void put_condition_code
PARAMS ((enum rtx_code
, enum machine_mode
,
531 static rtx ix86_expand_int_compare
PARAMS ((enum rtx_code
, rtx
, rtx
));
532 static enum rtx_code ix86_prepare_fp_compare_args
PARAMS ((enum rtx_code
,
534 static rtx gen_push
PARAMS ((rtx
));
535 static int memory_address_length
PARAMS ((rtx addr
));
536 static int ix86_flags_dependant
PARAMS ((rtx
, rtx
, enum attr_type
));
537 static int ix86_agi_dependant
PARAMS ((rtx
, rtx
, enum attr_type
));
538 static int ix86_safe_length
PARAMS ((rtx
));
539 static enum attr_memory ix86_safe_memory
PARAMS ((rtx
));
540 static enum attr_pent_pair ix86_safe_pent_pair
PARAMS ((rtx
));
541 static enum attr_ppro_uops ix86_safe_ppro_uops
PARAMS ((rtx
));
542 static void ix86_dump_ppro_packet
PARAMS ((FILE *));
543 static void ix86_reorder_insn
PARAMS ((rtx
*, rtx
*));
544 static rtx
* ix86_pent_find_pair
PARAMS ((rtx
*, rtx
*, enum attr_pent_pair
,
546 static void ix86_init_machine_status
PARAMS ((struct function
*));
547 static void ix86_mark_machine_status
PARAMS ((struct function
*));
548 static void ix86_free_machine_status
PARAMS ((struct function
*));
549 static int ix86_split_to_parts
PARAMS ((rtx
, rtx
*, enum machine_mode
));
550 static int ix86_safe_length_prefix
PARAMS ((rtx
));
551 static int ix86_nsaved_regs
PARAMS((void));
552 static void ix86_emit_save_regs
PARAMS((void));
553 static void ix86_emit_restore_regs_using_mov
PARAMS ((rtx
, int));
554 static void ix86_emit_epilogue_esp_adjustment
PARAMS((int));
555 static void ix86_set_move_mem_attrs_1
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
));
556 static void ix86_sched_reorder_pentium
PARAMS((rtx
*, rtx
*));
557 static void ix86_sched_reorder_ppro
PARAMS((rtx
*, rtx
*));
558 static HOST_WIDE_INT ix86_GOT_alias_set
PARAMS ((void));
562 rtx base
, index
, disp
;
566 static int ix86_decompose_address
PARAMS ((rtx
, struct ix86_address
*));
568 struct builtin_description
;
569 static rtx ix86_expand_sse_comi
PARAMS ((struct builtin_description
*, tree
,
571 static rtx ix86_expand_sse_compare
PARAMS ((struct builtin_description
*, tree
,
573 static rtx ix86_expand_unop1_builtin
PARAMS ((enum insn_code
, tree
, rtx
));
574 static rtx ix86_expand_unop_builtin
PARAMS ((enum insn_code
, tree
, rtx
, int));
575 static rtx ix86_expand_binop_builtin
PARAMS ((enum insn_code
, tree
, rtx
));
576 static rtx ix86_expand_store_builtin
PARAMS ((enum insn_code
, tree
, int));
577 static rtx safe_vector_operand
PARAMS ((rtx
, enum machine_mode
));
578 static enum rtx_code ix86_fp_compare_code_to_integer
PARAMS ((enum rtx_code
));
579 static void ix86_fp_comparison_codes
PARAMS ((enum rtx_code code
,
583 static rtx ix86_expand_fp_compare
PARAMS ((enum rtx_code
, rtx
, rtx
, rtx
,
585 static int ix86_fp_comparison_arithmetics_cost
PARAMS ((enum rtx_code code
));
586 static int ix86_fp_comparison_fcomi_cost
PARAMS ((enum rtx_code code
));
587 static int ix86_fp_comparison_sahf_cost
PARAMS ((enum rtx_code code
));
588 static int ix86_fp_comparison_cost
PARAMS ((enum rtx_code code
));
589 static int ix86_save_reg
PARAMS ((int));
590 static void ix86_compute_frame_layout
PARAMS ((struct ix86_frame
*));
592 /* Sometimes certain combinations of command options do not make
593 sense on a particular target machine. You can define a macro
594 `OVERRIDE_OPTIONS' to take account of this. This macro, if
595 defined, is executed once just after all the command options have
598 Don't use this macro to turn on various extra optimizations for
599 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
605 /* Comes from final.c -- no real reason to change it. */
606 #define MAX_CODE_ALIGN 16
610 struct processor_costs
*cost
; /* Processor costs */
611 int target_enable
; /* Target flags to enable. */
612 int target_disable
; /* Target flags to disable. */
613 int align_loop
; /* Default alignments. */
618 const processor_target_table
[PROCESSOR_max
] =
620 {&i386_cost
, 0, 0, 2, 2, 2, 1},
621 {&i486_cost
, 0, 0, 4, 4, 4, 1},
622 {&pentium_cost
, 0, 0, -4, -4, -4, 1},
623 {&pentiumpro_cost
, 0, 0, 4, -4, 4, 1},
624 {&k6_cost
, 0, 0, -5, -5, 4, 1},
625 {&athlon_cost
, 0, 0, 4, -4, 4, 1},
626 {&pentium4_cost
, 0, 0, 2, 2, 2, 1}
631 const char *name
; /* processor name or nickname. */
632 enum processor_type processor
;
634 const processor_alias_table
[] =
636 {"i386", PROCESSOR_I386
},
637 {"i486", PROCESSOR_I486
},
638 {"i586", PROCESSOR_PENTIUM
},
639 {"pentium", PROCESSOR_PENTIUM
},
640 {"i686", PROCESSOR_PENTIUMPRO
},
641 {"pentiumpro", PROCESSOR_PENTIUMPRO
},
642 {"k6", PROCESSOR_K6
},
643 {"athlon", PROCESSOR_ATHLON
},
644 {"pentium4", PROCESSOR_PENTIUM4
},
647 int const pta_size
= sizeof (processor_alias_table
) / sizeof (struct pta
);
649 #ifdef SUBTARGET_OVERRIDE_OPTIONS
650 SUBTARGET_OVERRIDE_OPTIONS
;
653 ix86_arch
= PROCESSOR_I386
;
654 ix86_cpu
= (enum processor_type
) TARGET_CPU_DEFAULT
;
656 if (ix86_arch_string
!= 0)
658 for (i
= 0; i
< pta_size
; i
++)
659 if (! strcmp (ix86_arch_string
, processor_alias_table
[i
].name
))
661 ix86_arch
= processor_alias_table
[i
].processor
;
662 /* Default cpu tuning to the architecture. */
663 ix86_cpu
= ix86_arch
;
668 error ("bad value (%s) for -march= switch", ix86_arch_string
);
671 if (ix86_cpu_string
!= 0)
673 for (i
= 0; i
< pta_size
; i
++)
674 if (! strcmp (ix86_cpu_string
, processor_alias_table
[i
].name
))
676 ix86_cpu
= processor_alias_table
[i
].processor
;
680 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string
);
683 ix86_cost
= processor_target_table
[ix86_cpu
].cost
;
684 target_flags
|= processor_target_table
[ix86_cpu
].target_enable
;
685 target_flags
&= ~processor_target_table
[ix86_cpu
].target_disable
;
687 /* Arrange to set up i386_stack_locals for all functions. */
688 init_machine_status
= ix86_init_machine_status
;
689 mark_machine_status
= ix86_mark_machine_status
;
690 free_machine_status
= ix86_free_machine_status
;
692 /* Validate -mregparm= value. */
693 if (ix86_regparm_string
)
695 i
= atoi (ix86_regparm_string
);
696 if (i
< 0 || i
> REGPARM_MAX
)
697 error ("-mregparm=%d is not between 0 and %d", i
, REGPARM_MAX
);
702 /* Validate -malign-loops= value, or provide default. */
703 ix86_align_loops
= processor_target_table
[ix86_cpu
].align_loop
;
704 if (ix86_align_loops_string
)
706 i
= atoi (ix86_align_loops_string
);
707 if (i
< 0 || i
> MAX_CODE_ALIGN
)
708 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
710 ix86_align_loops
= i
;
713 /* Validate -malign-jumps= value, or provide default. */
714 ix86_align_jumps
= processor_target_table
[ix86_cpu
].align_jump
;
715 if (ix86_align_jumps_string
)
717 i
= atoi (ix86_align_jumps_string
);
718 if (i
< 0 || i
> MAX_CODE_ALIGN
)
719 error ("-malign-jumps=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
721 ix86_align_jumps
= i
;
724 /* Validate -malign-functions= value, or provide default. */
725 ix86_align_funcs
= processor_target_table
[ix86_cpu
].align_func
;
726 if (ix86_align_funcs_string
)
728 i
= atoi (ix86_align_funcs_string
);
729 if (i
< 0 || i
> MAX_CODE_ALIGN
)
730 error ("-malign-functions=%d is not between 0 and %d",
733 ix86_align_funcs
= i
;
736 /* Validate -mpreferred-stack-boundary= value, or provide default.
737 The default of 128 bits is for Pentium III's SSE __m128. */
738 ix86_preferred_stack_boundary
= 128;
739 if (ix86_preferred_stack_boundary_string
)
741 i
= atoi (ix86_preferred_stack_boundary_string
);
743 error ("-mpreferred-stack-boundary=%d is not between 2 and 31", i
);
745 ix86_preferred_stack_boundary
= (1 << i
) * BITS_PER_UNIT
;
748 /* Validate -mbranch-cost= value, or provide default. */
749 ix86_branch_cost
= processor_target_table
[ix86_cpu
].branch_cost
;
750 if (ix86_branch_cost_string
)
752 i
= atoi (ix86_branch_cost_string
);
754 error ("-mbranch-cost=%d is not between 0 and 5", i
);
756 ix86_branch_cost
= i
;
759 /* Keep nonleaf frame pointers. */
760 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
761 flag_omit_frame_pointer
= 1;
763 /* If we're doing fast math, we don't care about comparison order
764 wrt NaNs. This lets us use a shorter comparison sequence. */
765 if (flag_unsafe_math_optimizations
)
766 target_flags
&= ~MASK_IEEE_FP
;
768 /* It makes no sense to ask for just SSE builtins, so MMX is also turned
771 target_flags
|= MASK_MMX
;
775 optimization_options (level
, size
)
777 int size ATTRIBUTE_UNUSED
;
779 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
780 make the problem with not enough registers even worse. */
781 #ifdef INSN_SCHEDULING
783 flag_schedule_insns
= 0;
787 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
788 attribute for DECL. The attributes in ATTRIBUTES have previously been
792 ix86_valid_decl_attribute_p (decl
, attributes
, identifier
, args
)
793 tree decl ATTRIBUTE_UNUSED
;
794 tree attributes ATTRIBUTE_UNUSED
;
795 tree identifier ATTRIBUTE_UNUSED
;
796 tree args ATTRIBUTE_UNUSED
;
801 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
802 attribute for TYPE. The attributes in ATTRIBUTES have previously been
806 ix86_valid_type_attribute_p (type
, attributes
, identifier
, args
)
808 tree attributes ATTRIBUTE_UNUSED
;
812 if (TREE_CODE (type
) != FUNCTION_TYPE
813 && TREE_CODE (type
) != METHOD_TYPE
814 && TREE_CODE (type
) != FIELD_DECL
815 && TREE_CODE (type
) != TYPE_DECL
)
818 /* Stdcall attribute says callee is responsible for popping arguments
819 if they are not variable. */
820 if (is_attribute_p ("stdcall", identifier
))
821 return (args
== NULL_TREE
);
823 /* Cdecl attribute says the callee is a normal C declaration. */
824 if (is_attribute_p ("cdecl", identifier
))
825 return (args
== NULL_TREE
);
827 /* Regparm attribute specifies how many integer arguments are to be
828 passed in registers. */
829 if (is_attribute_p ("regparm", identifier
))
833 if (! args
|| TREE_CODE (args
) != TREE_LIST
834 || TREE_CHAIN (args
) != NULL_TREE
835 || TREE_VALUE (args
) == NULL_TREE
)
838 cst
= TREE_VALUE (args
);
839 if (TREE_CODE (cst
) != INTEGER_CST
)
842 if (compare_tree_int (cst
, REGPARM_MAX
) > 0)
851 /* Return 0 if the attributes for two types are incompatible, 1 if they
852 are compatible, and 2 if they are nearly compatible (which causes a
853 warning to be generated). */
856 ix86_comp_type_attributes (type1
, type2
)
860 /* Check for mismatch of non-default calling convention. */
861 const char *rtdstr
= TARGET_RTD
? "cdecl" : "stdcall";
863 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
866 /* Check for mismatched return types (cdecl vs stdcall). */
867 if (!lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type1
))
868 != !lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type2
)))
873 /* Value is the number of bytes of arguments automatically
874 popped when returning from a subroutine call.
875 FUNDECL is the declaration node of the function (as a tree),
876 FUNTYPE is the data type of the function (as a tree),
877 or for a library call it is an identifier node for the subroutine name.
878 SIZE is the number of bytes of arguments passed on the stack.
880 On the 80386, the RTD insn may be used to pop them if the number
881 of args is fixed, but if the number is variable then the caller
882 must pop them all. RTD can't be used for library calls now
883 because the library is compiled with the Unix compiler.
884 Use of RTD is a selectable option, since it is incompatible with
885 standard Unix calling sequences. If the option is not selected,
886 the caller must always pop the args.
888 The attribute stdcall is equivalent to RTD on a per module basis. */
891 ix86_return_pops_args (fundecl
, funtype
, size
)
896 int rtd
= TARGET_RTD
&& (!fundecl
|| TREE_CODE (fundecl
) != IDENTIFIER_NODE
);
898 /* Cdecl functions override -mrtd, and never pop the stack. */
899 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype
))) {
901 /* Stdcall functions will pop the stack if not variable args. */
902 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype
)))
906 && (TYPE_ARG_TYPES (funtype
) == NULL_TREE
907 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype
)))
912 /* Lose any fake structure return argument. */
913 if (aggregate_value_p (TREE_TYPE (funtype
)))
914 return GET_MODE_SIZE (Pmode
);
919 /* Argument support functions. */
921 /* Initialize a variable CUM of type CUMULATIVE_ARGS
922 for a call to a function whose data type is FNTYPE.
923 For a library call, FNTYPE is 0. */
926 init_cumulative_args (cum
, fntype
, libname
)
927 CUMULATIVE_ARGS
*cum
; /* Argument info to initialize */
928 tree fntype
; /* tree ptr for function decl */
929 rtx libname
; /* SYMBOL_REF of library name or 0 */
931 static CUMULATIVE_ARGS zero_cum
;
932 tree param
, next_param
;
934 if (TARGET_DEBUG_ARG
)
936 fprintf (stderr
, "\ninit_cumulative_args (");
938 fprintf (stderr
, "fntype code = %s, ret code = %s",
939 tree_code_name
[(int) TREE_CODE (fntype
)],
940 tree_code_name
[(int) TREE_CODE (TREE_TYPE (fntype
))]);
942 fprintf (stderr
, "no fntype");
945 fprintf (stderr
, ", libname = %s", XSTR (libname
, 0));
950 /* Set up the number of registers to use for passing arguments. */
951 cum
->nregs
= ix86_regparm
;
954 tree attr
= lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype
));
957 cum
->nregs
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr
)));
960 /* Determine if this function has variable arguments. This is
961 indicated by the last argument being 'void_type_mode' if there
962 are no variable arguments. If there are variable arguments, then
963 we won't pass anything in registers */
967 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
968 param
!= 0; param
= next_param
)
970 next_param
= TREE_CHAIN (param
);
971 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
976 if (TARGET_DEBUG_ARG
)
977 fprintf (stderr
, ", nregs=%d )\n", cum
->nregs
);
982 /* Update the data in CUM to advance over an argument
983 of mode MODE and data type TYPE.
984 (TYPE is null for libcalls where that information may not be available.) */
987 function_arg_advance (cum
, mode
, type
, named
)
988 CUMULATIVE_ARGS
*cum
; /* current arg information */
989 enum machine_mode mode
; /* current arg mode */
990 tree type
; /* type of the argument or 0 if lib support */
991 int named
; /* whether or not the argument was named */
994 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
995 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
997 if (TARGET_DEBUG_ARG
)
999 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
1000 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
1001 if (TARGET_SSE
&& mode
== TImode
)
1003 cum
->sse_words
+= words
;
1004 cum
->sse_nregs
-= 1;
1005 cum
->sse_regno
+= 1;
1006 if (cum
->sse_nregs
<= 0)
1014 cum
->words
+= words
;
1015 cum
->nregs
-= words
;
1016 cum
->regno
+= words
;
1018 if (cum
->nregs
<= 0)
1027 /* Define where to put the arguments to a function.
1028 Value is zero to push the argument on the stack,
1029 or a hard register in which to store the argument.
1031 MODE is the argument's machine mode.
1032 TYPE is the data type of the argument (as a tree).
1033 This is null for libcalls where that information may
1035 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1036 the preceding args and about the function being called.
1037 NAMED is nonzero if this argument is a named parameter
1038 (otherwise it is an extra parameter matching an ellipsis). */
1041 function_arg (cum
, mode
, type
, named
)
1042 CUMULATIVE_ARGS
*cum
; /* current arg information */
1043 enum machine_mode mode
; /* current arg mode */
1044 tree type
; /* type of the argument or 0 if lib support */
1045 int named
; /* != 0 for normal args, == 0 for ... args */
1049 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
1050 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1054 /* For now, pass fp/complex values on the stack. */
1063 if (words
<= cum
->nregs
)
1064 ret
= gen_rtx_REG (mode
, cum
->regno
);
1068 ret
= gen_rtx_REG (mode
, cum
->sse_regno
);
1072 if (TARGET_DEBUG_ARG
)
1075 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
1076 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
1079 fprintf (stderr
, ", reg=%%e%s", reg_names
[ REGNO(ret
) ]);
1081 fprintf (stderr
, ", stack");
1083 fprintf (stderr
, " )\n");
1090 /* Return nonzero if OP is (const_int 1), else return zero. */
1093 const_int_1_operand (op
, mode
)
1095 enum machine_mode mode ATTRIBUTE_UNUSED
;
1097 return (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 1);
1100 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1101 reference and a constant. */
1104 symbolic_operand (op
, mode
)
1106 enum machine_mode mode ATTRIBUTE_UNUSED
;
1108 switch (GET_CODE (op
))
1116 if (GET_CODE (op
) == SYMBOL_REF
1117 || GET_CODE (op
) == LABEL_REF
1118 || (GET_CODE (op
) == UNSPEC
1119 && XINT (op
, 1) >= 6
1120 && XINT (op
, 1) <= 7))
1122 if (GET_CODE (op
) != PLUS
1123 || GET_CODE (XEXP (op
, 1)) != CONST_INT
)
1127 if (GET_CODE (op
) == SYMBOL_REF
1128 || GET_CODE (op
) == LABEL_REF
)
1130 /* Only @GOTOFF gets offsets. */
1131 if (GET_CODE (op
) != UNSPEC
1132 || XINT (op
, 1) != 7)
1135 op
= XVECEXP (op
, 0, 0);
1136 if (GET_CODE (op
) == SYMBOL_REF
1137 || GET_CODE (op
) == LABEL_REF
)
1146 /* Return true if the operand contains a @GOT or @GOTOFF reference. */
1149 pic_symbolic_operand (op
, mode
)
1151 enum machine_mode mode ATTRIBUTE_UNUSED
;
1153 if (GET_CODE (op
) == CONST
)
1156 if (GET_CODE (op
) == UNSPEC
)
1158 if (GET_CODE (op
) != PLUS
1159 || GET_CODE (XEXP (op
, 1)) != CONST_INT
)
1162 if (GET_CODE (op
) == UNSPEC
)
1168 /* Test for a valid operand for a call instruction. Don't allow the
1169 arg pointer register or virtual regs since they may decay into
1170 reg + const, which the patterns can't handle. */
1173 call_insn_operand (op
, mode
)
1175 enum machine_mode mode ATTRIBUTE_UNUSED
;
1177 /* Disallow indirect through a virtual register. This leads to
1178 compiler aborts when trying to eliminate them. */
1179 if (GET_CODE (op
) == REG
1180 && (op
== arg_pointer_rtx
1181 || op
== frame_pointer_rtx
1182 || (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1183 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
1186 /* Disallow `call 1234'. Due to varying assembler lameness this
1187 gets either rejected or translated to `call .+1234'. */
1188 if (GET_CODE (op
) == CONST_INT
)
1191 /* Explicitly allow SYMBOL_REF even if pic. */
1192 if (GET_CODE (op
) == SYMBOL_REF
)
1195 /* Half-pic doesn't allow anything but registers and constants.
1196 We've just taken care of the later. */
1198 return register_operand (op
, Pmode
);
1200 /* Otherwise we can allow any general_operand in the address. */
1201 return general_operand (op
, Pmode
);
1205 constant_call_address_operand (op
, mode
)
1207 enum machine_mode mode ATTRIBUTE_UNUSED
;
1209 if (GET_CODE (op
) == CONST
1210 && GET_CODE (XEXP (op
, 0)) == PLUS
1211 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
1212 op
= XEXP (XEXP (op
, 0), 0);
1213 return GET_CODE (op
) == SYMBOL_REF
;
1216 /* Match exactly zero and one. */
1219 const0_operand (op
, mode
)
1221 enum machine_mode mode
;
1223 return op
== CONST0_RTX (mode
);
1227 const1_operand (op
, mode
)
1229 enum machine_mode mode ATTRIBUTE_UNUSED
;
1231 return op
== const1_rtx
;
1234 /* Match 2, 4, or 8. Used for leal multiplicands. */
1237 const248_operand (op
, mode
)
1239 enum machine_mode mode ATTRIBUTE_UNUSED
;
1241 return (GET_CODE (op
) == CONST_INT
1242 && (INTVAL (op
) == 2 || INTVAL (op
) == 4 || INTVAL (op
) == 8));
1245 /* True if this is a constant appropriate for an increment or decremenmt. */
1248 incdec_operand (op
, mode
)
1250 enum machine_mode mode
;
1252 /* On Pentium4, the inc and dec operations causes extra dependancy on flag
1253 registers, since carry flag is not set. */
1254 if (TARGET_PENTIUM4
&& !optimize_size
)
1256 if (op
== const1_rtx
|| op
== constm1_rtx
)
1258 if (GET_CODE (op
) != CONST_INT
)
1260 if (mode
== SImode
&& INTVAL (op
) == (HOST_WIDE_INT
) 0xffffffff)
1262 if (mode
== HImode
&& INTVAL (op
) == (HOST_WIDE_INT
) 0xffff)
1264 if (mode
== QImode
&& INTVAL (op
) == (HOST_WIDE_INT
) 0xff)
1269 /* Return false if this is the stack pointer, or any other fake
1270 register eliminable to the stack pointer. Otherwise, this is
1273 This is used to prevent esp from being used as an index reg.
1274 Which would only happen in pathological cases. */
1277 reg_no_sp_operand (op
, mode
)
1279 enum machine_mode mode
;
1282 if (GET_CODE (t
) == SUBREG
)
1284 if (t
== stack_pointer_rtx
|| t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
)
1287 return register_operand (op
, mode
);
1291 mmx_reg_operand (op
, mode
)
1293 enum machine_mode mode ATTRIBUTE_UNUSED
;
1295 return MMX_REG_P (op
);
1298 /* Return false if this is any eliminable register. Otherwise
1302 general_no_elim_operand (op
, mode
)
1304 enum machine_mode mode
;
1307 if (GET_CODE (t
) == SUBREG
)
1309 if (t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
1310 || t
== virtual_incoming_args_rtx
|| t
== virtual_stack_vars_rtx
1311 || t
== virtual_stack_dynamic_rtx
)
1314 return general_operand (op
, mode
);
1317 /* Return false if this is any eliminable register. Otherwise
1318 register_operand or const_int. */
1321 nonmemory_no_elim_operand (op
, mode
)
1323 enum machine_mode mode
;
1326 if (GET_CODE (t
) == SUBREG
)
1328 if (t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
1329 || t
== virtual_incoming_args_rtx
|| t
== virtual_stack_vars_rtx
1330 || t
== virtual_stack_dynamic_rtx
)
1333 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
1336 /* Return true if op is a Q_REGS class register. */
1339 q_regs_operand (op
, mode
)
1341 enum machine_mode mode
;
1343 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1345 if (GET_CODE (op
) == SUBREG
)
1346 op
= SUBREG_REG (op
);
1347 return QI_REG_P (op
);
1350 /* Return true if op is a NON_Q_REGS class register. */
1353 non_q_regs_operand (op
, mode
)
1355 enum machine_mode mode
;
1357 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1359 if (GET_CODE (op
) == SUBREG
)
1360 op
= SUBREG_REG (op
);
1361 return NON_QI_REG_P (op
);
1364 /* Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS
1367 sse_comparison_operator (op
, mode
)
1369 enum machine_mode mode ATTRIBUTE_UNUSED
;
1371 enum rtx_code code
= GET_CODE (op
);
1374 /* Operations supported directly. */
1384 /* These are equivalent to ones above in non-IEEE comparisons. */
1391 return !TARGET_IEEE_FP
;
1396 /* Return 1 if OP is a valid comparison operator in valid mode. */
1398 ix86_comparison_operator (op
, mode
)
1400 enum machine_mode mode
;
1402 enum machine_mode inmode
;
1403 enum rtx_code code
= GET_CODE (op
);
1404 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1406 if (GET_RTX_CLASS (code
) != '<')
1408 inmode
= GET_MODE (XEXP (op
, 0));
1410 if (inmode
== CCFPmode
|| inmode
== CCFPUmode
)
1412 enum rtx_code second_code
, bypass_code
;
1413 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
1414 return (bypass_code
== NIL
&& second_code
== NIL
);
1421 if (inmode
== CCmode
|| inmode
== CCGCmode
1422 || inmode
== CCGOCmode
|| inmode
== CCNOmode
)
1425 case LTU
: case GTU
: case LEU
: case ORDERED
: case UNORDERED
: case GEU
:
1426 if (inmode
== CCmode
)
1430 if (inmode
== CCmode
|| inmode
== CCGCmode
|| inmode
== CCNOmode
)
1438 /* Return 1 if OP is a comparison operator that can be issued by fcmov. */
1441 fcmov_comparison_operator (op
, mode
)
1443 enum machine_mode mode
;
1445 enum machine_mode inmode
;
1446 enum rtx_code code
= GET_CODE (op
);
1447 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1449 if (GET_RTX_CLASS (code
) != '<')
1451 inmode
= GET_MODE (XEXP (op
, 0));
1452 if (inmode
== CCFPmode
|| inmode
== CCFPUmode
)
1454 enum rtx_code second_code
, bypass_code
;
1455 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
1456 if (bypass_code
!= NIL
|| second_code
!= NIL
)
1458 code
= ix86_fp_compare_code_to_integer (code
);
1460 /* i387 supports just limited amount of conditional codes. */
1463 case LTU
: case GTU
: case LEU
: case GEU
:
1464 if (inmode
== CCmode
|| inmode
== CCFPmode
|| inmode
== CCFPUmode
)
1467 case ORDERED
: case UNORDERED
:
1475 /* Return 1 if OP is a binary operator that can be promoted to wider mode. */
1478 promotable_binary_operator (op
, mode
)
1480 enum machine_mode mode ATTRIBUTE_UNUSED
;
1482 switch (GET_CODE (op
))
1485 /* Modern CPUs have same latency for HImode and SImode multiply,
1486 but 386 and 486 do HImode multiply faster. */
1487 return ix86_cpu
> PROCESSOR_I486
;
1499 /* Nearly general operand, but accept any const_double, since we wish
1500 to be able to drop them into memory rather than have them get pulled
1504 cmp_fp_expander_operand (op
, mode
)
1506 enum machine_mode mode
;
1508 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
1510 if (GET_CODE (op
) == CONST_DOUBLE
)
1512 return general_operand (op
, mode
);
1515 /* Match an SI or HImode register for a zero_extract. */
1518 ext_register_operand (op
, mode
)
1520 enum machine_mode mode ATTRIBUTE_UNUSED
;
1522 if (GET_MODE (op
) != SImode
&& GET_MODE (op
) != HImode
)
1524 return register_operand (op
, VOIDmode
);
1527 /* Return 1 if this is a valid binary floating-point operation.
1528 OP is the expression matched, and MODE is its mode. */
1531 binary_fp_operator (op
, mode
)
1533 enum machine_mode mode
;
1535 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
1538 switch (GET_CODE (op
))
1544 return GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
;
1552 mult_operator(op
, mode
)
1554 enum machine_mode mode ATTRIBUTE_UNUSED
;
1556 return GET_CODE (op
) == MULT
;
1560 div_operator(op
, mode
)
1562 enum machine_mode mode ATTRIBUTE_UNUSED
;
1564 return GET_CODE (op
) == DIV
;
1568 arith_or_logical_operator (op
, mode
)
1570 enum machine_mode mode
;
1572 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1573 && (GET_RTX_CLASS (GET_CODE (op
)) == 'c'
1574 || GET_RTX_CLASS (GET_CODE (op
)) == '2'));
1577 /* Returns 1 if OP is memory operand with a displacement. */
1580 memory_displacement_operand (op
, mode
)
1582 enum machine_mode mode
;
1584 struct ix86_address parts
;
1586 if (! memory_operand (op
, mode
))
1589 if (! ix86_decompose_address (XEXP (op
, 0), &parts
))
1592 return parts
.disp
!= NULL_RTX
;
1595 /* To avoid problems when jump re-emits comparisons like testqi_ext_ccno_0,
1596 re-recognize the operand to avoid a copy_to_mode_reg that will fail.
1598 ??? It seems likely that this will only work because cmpsi is an
1599 expander, and no actual insns use this. */
1602 cmpsi_operand (op
, mode
)
1604 enum machine_mode mode
;
1606 if (general_operand (op
, mode
))
1609 if (GET_CODE (op
) == AND
1610 && GET_MODE (op
) == SImode
1611 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTRACT
1612 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
1613 && GET_CODE (XEXP (XEXP (op
, 0), 2)) == CONST_INT
1614 && INTVAL (XEXP (XEXP (op
, 0), 1)) == 8
1615 && INTVAL (XEXP (XEXP (op
, 0), 2)) == 8
1616 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
1622 /* Returns 1 if OP is memory operand that can not be represented by the
1626 long_memory_operand (op
, mode
)
1628 enum machine_mode mode
;
1630 if (! memory_operand (op
, mode
))
1633 return memory_address_length (op
) != 0;
1636 /* Return nonzero if the rtx is known aligned. */
1639 aligned_operand (op
, mode
)
1641 enum machine_mode mode
;
1643 struct ix86_address parts
;
1645 if (!general_operand (op
, mode
))
1648 /* Registers and immediate operands are always "aligned". */
1649 if (GET_CODE (op
) != MEM
)
1652 /* Don't even try to do any aligned optimizations with volatiles. */
1653 if (MEM_VOLATILE_P (op
))
1658 /* Pushes and pops are only valid on the stack pointer. */
1659 if (GET_CODE (op
) == PRE_DEC
1660 || GET_CODE (op
) == POST_INC
)
1663 /* Decode the address. */
1664 if (! ix86_decompose_address (op
, &parts
))
1667 /* Look for some component that isn't known to be aligned. */
1671 && REGNO_POINTER_ALIGN (REGNO (parts
.index
)) < 32)
1676 if (REGNO_POINTER_ALIGN (REGNO (parts
.base
)) < 32)
1681 if (GET_CODE (parts
.disp
) != CONST_INT
1682 || (INTVAL (parts
.disp
) & 3) != 0)
1686 /* Didn't find one -- this must be an aligned address. */
1690 /* Return true if the constant is something that can be loaded with
1691 a special instruction. Only handle 0.0 and 1.0; others are less
1695 standard_80387_constant_p (x
)
1698 if (GET_CODE (x
) != CONST_DOUBLE
|| !FLOAT_MODE_P (GET_MODE (x
)))
1700 /* Note that on the 80387, other constants, such as pi, that we should support
1701 too. On some machines, these are much slower to load as standard constant,
1702 than to load from doubles in memory. */
1703 if (x
== CONST0_RTX (GET_MODE (x
)))
1705 if (x
== CONST1_RTX (GET_MODE (x
)))
1710 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
1713 standard_sse_constant_p (x
)
1716 if (GET_CODE (x
) != CONST_DOUBLE
)
1718 return (x
== CONST0_RTX (GET_MODE (x
)));
1721 /* Returns 1 if OP contains a symbol reference */
1724 symbolic_reference_mentioned_p (op
)
1727 register const char *fmt
;
1730 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1733 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
1734 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
1740 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
1741 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
1745 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
1752 /* Return 1 if it is appropriate to emit `ret' instructions in the
1753 body of a function. Do this only if the epilogue is simple, needing a
1754 couple of insns. Prior to reloading, we can't tell how many registers
1755 must be saved, so return 0 then. Return 0 if there is no frame
1756 marker to de-allocate.
1758 If NON_SAVING_SETJMP is defined and true, then it is not possible
1759 for the epilogue to be simple, so return 0. This is a special case
1760 since NON_SAVING_SETJMP will not cause regs_ever_live to change
1761 until final, but jump_optimize may need to know sooner if a
1765 ix86_can_use_return_insn_p ()
1767 struct ix86_frame frame
;
1769 #ifdef NON_SAVING_SETJMP
1770 if (NON_SAVING_SETJMP
&& current_function_calls_setjmp
)
1773 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
1774 if (profile_block_flag
== 2)
1778 if (! reload_completed
|| frame_pointer_needed
)
1781 /* Don't allow more than 32 pop, since that's all we can do
1782 with one instruction. */
1783 if (current_function_pops_args
1784 && current_function_args_size
>= 32768)
1787 ix86_compute_frame_layout (&frame
);
1788 return frame
.to_allocate
== 0 && frame
.nregs
== 0;
1791 /* Value should be nonzero if functions must have frame pointers.
1792 Zero means the frame pointer need not be set up (and parms may
1793 be accessed via the stack pointer) in functions that seem suitable. */
1796 ix86_frame_pointer_required ()
1798 /* If we accessed previous frames, then the generated code expects
1799 to be able to access the saved ebp value in our frame. */
1800 if (cfun
->machine
->accesses_prev_frame
)
1803 /* Several x86 os'es need a frame pointer for other reasons,
1804 usually pertaining to setjmp. */
1805 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
1808 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
1809 the frame pointer by default. Turn it back on now if we've not
1810 got a leaf function. */
1811 if (TARGET_OMIT_LEAF_FRAME_POINTER
&& ! leaf_function_p ())
1817 /* Record that the current function accesses previous call frames. */
1820 ix86_setup_frame_addresses ()
1822 cfun
->machine
->accesses_prev_frame
= 1;
1825 static char pic_label_name
[32];
1827 /* This function generates code for -fpic that loads %ebx with
1828 the return address of the caller and then returns. */
1831 ix86_asm_file_end (file
)
1836 if (! TARGET_DEEP_BRANCH_PREDICTION
|| pic_label_name
[0] == 0)
1839 /* ??? Binutils 2.10 and earlier has a linkonce elimination bug related
1840 to updating relocations to a section being discarded such that this
1841 doesn't work. Ought to detect this at configure time. */
1842 #if 0 && defined (ASM_OUTPUT_SECTION_NAME)
1843 /* The trick here is to create a linkonce section containing the
1844 pic label thunk, but to refer to it with an internal label.
1845 Because the label is internal, we don't have inter-dso name
1846 binding issues on hosts that don't support ".hidden".
1848 In order to use these macros, however, we must create a fake
1851 tree decl
= build_decl (FUNCTION_DECL
,
1852 get_identifier ("i686.get_pc_thunk"),
1854 DECL_ONE_ONLY (decl
) = 1;
1855 UNIQUE_SECTION (decl
, 0);
1856 named_section (decl
, NULL
, 0);
1862 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
1863 internal (non-global) label that's being emitted, it didn't make
1864 sense to have .type information for local labels. This caused
1865 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
1866 me debug info for a label that you're declaring non-global?) this
1867 was changed to call ASM_OUTPUT_LABEL() instead. */
1869 ASM_OUTPUT_LABEL (file
, pic_label_name
);
1871 xops
[0] = pic_offset_table_rtx
;
1872 xops
[1] = gen_rtx_MEM (SImode
, stack_pointer_rtx
);
1873 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops
);
1874 output_asm_insn ("ret", xops
);
1878 load_pic_register ()
1882 gotsym
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1884 if (TARGET_DEEP_BRANCH_PREDICTION
)
1886 if (! pic_label_name
[0])
1887 ASM_GENERATE_INTERNAL_LABEL (pic_label_name
, "LPR", 0);
1888 pclab
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, pic_label_name
));
1892 pclab
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
1895 emit_insn (gen_prologue_get_pc (pic_offset_table_rtx
, pclab
));
1897 if (! TARGET_DEEP_BRANCH_PREDICTION
)
1898 emit_insn (gen_popsi1 (pic_offset_table_rtx
));
1900 emit_insn (gen_prologue_set_got (pic_offset_table_rtx
, gotsym
, pclab
));
1903 /* Generate an SImode "push" pattern for input ARG. */
1909 return gen_rtx_SET (VOIDmode
,
1910 gen_rtx_MEM (SImode
,
1911 gen_rtx_PRE_DEC (SImode
,
1912 stack_pointer_rtx
)),
1916 /* Return 1 if we need to save REGNO. */
1918 ix86_save_reg (regno
)
1921 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
1922 || current_function_uses_const_pool
);
1923 return ((regs_ever_live
[regno
] && !call_used_regs
[regno
]
1924 && !fixed_regs
[regno
]
1925 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
1926 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
));
1930 /* Return number of registers to be saved on the stack. */
1938 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
1939 if (ix86_save_reg (regno
))
1944 /* Return the offset between two registers, one to be eliminated, and the other
1945 its replacement, at the start of a routine. */
1948 ix86_initial_elimination_offset (from
, to
)
1952 struct ix86_frame frame
;
1953 ix86_compute_frame_layout (&frame
);
1955 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1956 return frame
.hard_frame_pointer_offset
;
1957 else if (from
== FRAME_POINTER_REGNUM
1958 && to
== HARD_FRAME_POINTER_REGNUM
)
1959 return frame
.hard_frame_pointer_offset
- frame
.frame_pointer_offset
;
1962 if (to
!= STACK_POINTER_REGNUM
)
1964 else if (from
== ARG_POINTER_REGNUM
)
1965 return frame
.stack_pointer_offset
;
1966 else if (from
!= FRAME_POINTER_REGNUM
)
1969 return frame
.stack_pointer_offset
- frame
.frame_pointer_offset
;
1973 /* Fill structure ix86_frame about frame of currently computed function. */
1976 ix86_compute_frame_layout (frame
)
1977 struct ix86_frame
*frame
;
1979 HOST_WIDE_INT total_size
;
1980 int stack_alignment_needed
= cfun
->stack_alignment_needed
/ BITS_PER_UNIT
;
1982 int preferred_alignment
= cfun
->preferred_stack_boundary
/ BITS_PER_UNIT
;
1983 HOST_WIDE_INT size
= get_frame_size ();
1985 frame
->nregs
= ix86_nsaved_regs ();
1988 /* Skip return value and save base pointer. */
1989 offset
= frame_pointer_needed
? UNITS_PER_WORD
* 2 : UNITS_PER_WORD
;
1991 frame
->hard_frame_pointer_offset
= offset
;
1993 /* Do some sanity checking of stack_alignment_needed and
1994 preferred_alignment, since i386 port is the only using those features
1995 that may break easilly. */
1997 if (size
&& !stack_alignment_needed
)
1999 if (preferred_alignment
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
2001 if (preferred_alignment
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
2003 if (stack_alignment_needed
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
2006 if (stack_alignment_needed
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
2007 stack_alignment_needed
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
2009 /* Register save area */
2010 offset
+= frame
->nregs
* UNITS_PER_WORD
;
2012 /* Align start of frame for local function. */
2013 frame
->padding1
= ((offset
+ stack_alignment_needed
- 1)
2014 & -stack_alignment_needed
) - offset
;
2016 offset
+= frame
->padding1
;
2018 /* Frame pointer points here. */
2019 frame
->frame_pointer_offset
= offset
;
2023 /* Add outgoing arguments area. */
2024 if (ACCUMULATE_OUTGOING_ARGS
)
2026 offset
+= current_function_outgoing_args_size
;
2027 frame
->outgoing_arguments_size
= current_function_outgoing_args_size
;
2030 frame
->outgoing_arguments_size
= 0;
2032 /* Align stack boundary. */
2033 frame
->padding2
= ((offset
+ preferred_alignment
- 1)
2034 & -preferred_alignment
) - offset
;
2036 offset
+= frame
->padding2
;
2038 /* We've reached end of stack frame. */
2039 frame
->stack_pointer_offset
= offset
;
2041 /* Size prologue needs to allocate. */
2042 frame
->to_allocate
=
2043 (size
+ frame
->padding1
+ frame
->padding2
2044 + frame
->outgoing_arguments_size
);
2047 fprintf (stderr
, "nregs: %i\n", frame
->nregs
);
2048 fprintf (stderr
, "size: %i\n", size
);
2049 fprintf (stderr
, "alignment1: %i\n", stack_alignment_needed
);
2050 fprintf (stderr
, "padding1: %i\n", frame
->padding1
);
2051 fprintf (stderr
, "padding2: %i\n", frame
->padding2
);
2052 fprintf (stderr
, "to_allocate: %i\n", frame
->to_allocate
);
2053 fprintf (stderr
, "frame_pointer_offset: %i\n", frame
->frame_pointer_offset
);
2054 fprintf (stderr
, "hard_frame_pointer_offset: %i\n",
2055 frame
->hard_frame_pointer_offset
);
2056 fprintf (stderr
, "stack_pointer_offset: %i\n", frame
->stack_pointer_offset
);
2060 /* Emit code to save registers in the prologue. */
2063 ix86_emit_save_regs ()
2068 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
2069 if (ix86_save_reg (regno
))
2071 insn
= emit_insn (gen_push (gen_rtx_REG (SImode
, regno
)));
2072 RTX_FRAME_RELATED_P (insn
) = 1;
2076 /* Expand the prologue into a bunch of separate insns. */
2079 ix86_expand_prologue ()
2082 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
2083 || current_function_uses_const_pool
);
2084 struct ix86_frame frame
;
2086 ix86_compute_frame_layout (&frame
);
2088 /* Note: AT&T enter does NOT have reversed args. Enter is probably
2089 slower on all targets. Also sdb doesn't like it. */
2091 if (frame_pointer_needed
)
2093 insn
= emit_insn (gen_push (hard_frame_pointer_rtx
));
2094 RTX_FRAME_RELATED_P (insn
) = 1;
2096 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2097 RTX_FRAME_RELATED_P (insn
) = 1;
2100 ix86_emit_save_regs ();
2102 if (frame
.to_allocate
== 0)
2104 else if (! TARGET_STACK_PROBE
|| frame
.to_allocate
< CHECK_STACK_LIMIT
)
2106 if (frame_pointer_needed
)
2107 insn
= emit_insn (gen_pro_epilogue_adjust_stack
2108 (stack_pointer_rtx
, stack_pointer_rtx
,
2109 GEN_INT (-frame
.to_allocate
), hard_frame_pointer_rtx
));
2111 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2112 GEN_INT (-frame
.to_allocate
)));
2113 RTX_FRAME_RELATED_P (insn
) = 1;
2117 /* ??? Is this only valid for Win32? */
2121 arg0
= gen_rtx_REG (SImode
, 0);
2122 emit_move_insn (arg0
, GEN_INT (frame
.to_allocate
));
2124 sym
= gen_rtx_MEM (FUNCTION_MODE
,
2125 gen_rtx_SYMBOL_REF (Pmode
, "_alloca"));
2126 insn
= emit_call_insn (gen_call (sym
, const0_rtx
));
2128 CALL_INSN_FUNCTION_USAGE (insn
)
2129 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, arg0
),
2130 CALL_INSN_FUNCTION_USAGE (insn
));
2133 #ifdef SUBTARGET_PROLOGUE
2138 load_pic_register ();
2140 /* If we are profiling, make sure no instructions are scheduled before
2141 the call to mcount. However, if -fpic, the above call will have
2143 if ((profile_flag
|| profile_block_flag
) && ! pic_reg_used
)
2144 emit_insn (gen_blockage ());
2147 /* Emit code to add TSIZE to esp value. Use POP instruction when
2151 ix86_emit_epilogue_esp_adjustment (tsize
)
2154 /* If a frame pointer is present, we must be sure to tie the sp
2155 to the fp so that we don't mis-schedule. */
2156 if (frame_pointer_needed
)
2157 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
2160 hard_frame_pointer_rtx
));
2162 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2166 /* Emit code to restore saved registers using MOV insns. First register
2167 is restored from POINTER + OFFSET. */
2169 ix86_emit_restore_regs_using_mov (pointer
, offset
)
2175 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2176 if (ix86_save_reg (regno
))
2178 emit_move_insn (gen_rtx_REG (Pmode
, regno
),
2179 adj_offsettable_operand (gen_rtx_MEM (Pmode
,
2182 offset
+= UNITS_PER_WORD
;
2186 /* Restore function stack, frame, and registers. */
2189 ix86_expand_epilogue (emit_return
)
2193 int sp_valid
= !frame_pointer_needed
|| current_function_sp_is_unchanging
;
2194 struct ix86_frame frame
;
2195 HOST_WIDE_INT offset
;
2197 ix86_compute_frame_layout (&frame
);
2199 /* Calculate start of saved registers relative to ebp. */
2200 offset
= -frame
.nregs
* UNITS_PER_WORD
;
2202 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
2203 if (profile_block_flag
== 2)
2205 FUNCTION_BLOCK_PROFILER_EXIT
;
2209 /* If we're only restoring one register and sp is not valid then
2210 using a move instruction to restore the register since it's
2211 less work than reloading sp and popping the register.
2213 The default code result in stack adjustment using add/lea instruction,
2214 while this code results in LEAVE instruction (or discrete equivalent),
2215 so it is profitable in some other cases as well. Especially when there
2216 are no registers to restore. We also use this code when TARGET_USE_LEAVE
2217 and there is exactly one register to pop. This heruistic may need some
2218 tuning in future. */
2219 if ((!sp_valid
&& frame
.nregs
<= 1)
2220 || (frame_pointer_needed
&& !frame
.nregs
&& frame
.to_allocate
)
2221 || (frame_pointer_needed
&& TARGET_USE_LEAVE
&& !optimize_size
2222 && frame
.nregs
== 1))
2224 /* Restore registers. We can use ebp or esp to address the memory
2225 locations. If both are available, default to ebp, since offsets
2226 are known to be small. Only exception is esp pointing directly to the
2227 end of block of saved registers, where we may simplify addressing
2230 if (!frame_pointer_needed
|| (sp_valid
&& !frame
.to_allocate
))
2231 ix86_emit_restore_regs_using_mov (stack_pointer_rtx
, frame
.to_allocate
);
2233 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx
, offset
);
2235 if (!frame_pointer_needed
)
2236 ix86_emit_epilogue_esp_adjustment (frame
.to_allocate
2237 + frame
.nregs
* UNITS_PER_WORD
);
2238 /* If not an i386, mov & pop is faster than "leave". */
2239 else if (TARGET_USE_LEAVE
|| optimize_size
)
2240 emit_insn (gen_leave ());
2243 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
2244 hard_frame_pointer_rtx
,
2246 hard_frame_pointer_rtx
));
2247 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
2252 /* First step is to deallocate the stack frame so that we can
2253 pop the registers. */
2256 if (!frame_pointer_needed
)
2258 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
2259 hard_frame_pointer_rtx
,
2261 hard_frame_pointer_rtx
));
2263 else if (frame
.to_allocate
)
2264 ix86_emit_epilogue_esp_adjustment (frame
.to_allocate
);
2266 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2267 if (ix86_save_reg (regno
))
2268 emit_insn (gen_popsi1 (gen_rtx_REG (SImode
, regno
)));
2269 if (frame_pointer_needed
)
2270 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
2273 /* Sibcall epilogues don't want a return instruction. */
2277 if (current_function_pops_args
&& current_function_args_size
)
2279 rtx popc
= GEN_INT (current_function_pops_args
);
2281 /* i386 can only pop 64K bytes. If asked to pop more, pop
2282 return address, do explicit add, and jump indirectly to the
2285 if (current_function_pops_args
>= 65536)
2287 rtx ecx
= gen_rtx_REG (SImode
, 2);
2289 emit_insn (gen_popsi1 (ecx
));
2290 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, popc
));
2291 emit_jump_insn (gen_return_indirect_internal (ecx
));
2294 emit_jump_insn (gen_return_pop_internal (popc
));
2297 emit_jump_insn (gen_return_internal ());
2300 /* Extract the parts of an RTL expression that is a valid memory address
2301 for an instruction. Return false if the structure of the address is
2305 ix86_decompose_address (addr
, out
)
2307 struct ix86_address
*out
;
2309 rtx base
= NULL_RTX
;
2310 rtx index
= NULL_RTX
;
2311 rtx disp
= NULL_RTX
;
2312 HOST_WIDE_INT scale
= 1;
2313 rtx scale_rtx
= NULL_RTX
;
2315 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == SUBREG
)
2317 else if (GET_CODE (addr
) == PLUS
)
2319 rtx op0
= XEXP (addr
, 0);
2320 rtx op1
= XEXP (addr
, 1);
2321 enum rtx_code code0
= GET_CODE (op0
);
2322 enum rtx_code code1
= GET_CODE (op1
);
2324 if (code0
== REG
|| code0
== SUBREG
)
2326 if (code1
== REG
|| code1
== SUBREG
)
2327 index
= op0
, base
= op1
; /* index + base */
2329 base
= op0
, disp
= op1
; /* base + displacement */
2331 else if (code0
== MULT
)
2333 index
= XEXP (op0
, 0);
2334 scale_rtx
= XEXP (op0
, 1);
2335 if (code1
== REG
|| code1
== SUBREG
)
2336 base
= op1
; /* index*scale + base */
2338 disp
= op1
; /* index*scale + disp */
2340 else if (code0
== PLUS
&& GET_CODE (XEXP (op0
, 0)) == MULT
)
2342 index
= XEXP (XEXP (op0
, 0), 0); /* index*scale + base + disp */
2343 scale_rtx
= XEXP (XEXP (op0
, 0), 1);
2344 base
= XEXP (op0
, 1);
2347 else if (code0
== PLUS
)
2349 index
= XEXP (op0
, 0); /* index + base + disp */
2350 base
= XEXP (op0
, 1);
2356 else if (GET_CODE (addr
) == MULT
)
2358 index
= XEXP (addr
, 0); /* index*scale */
2359 scale_rtx
= XEXP (addr
, 1);
2361 else if (GET_CODE (addr
) == ASHIFT
)
2365 /* We're called for lea too, which implements ashift on occasion. */
2366 index
= XEXP (addr
, 0);
2367 tmp
= XEXP (addr
, 1);
2368 if (GET_CODE (tmp
) != CONST_INT
)
2370 scale
= INTVAL (tmp
);
2371 if ((unsigned HOST_WIDE_INT
) scale
> 3)
2376 disp
= addr
; /* displacement */
2378 /* Extract the integral value of scale. */
2381 if (GET_CODE (scale_rtx
) != CONST_INT
)
2383 scale
= INTVAL (scale_rtx
);
2386 /* Allow arg pointer and stack pointer as index if there is not scaling */
2387 if (base
&& index
&& scale
== 1
2388 && (index
== arg_pointer_rtx
|| index
== frame_pointer_rtx
2389 || index
== stack_pointer_rtx
))
2396 /* Special case: %ebp cannot be encoded as a base without a displacement. */
2397 if ((base
== hard_frame_pointer_rtx
2398 || base
== frame_pointer_rtx
2399 || base
== arg_pointer_rtx
) && !disp
)
2402 /* Special case: on K6, [%esi] makes the instruction vector decoded.
2403 Avoid this by transforming to [%esi+0]. */
2404 if (ix86_cpu
== PROCESSOR_K6
&& !optimize_size
2405 && base
&& !index
&& !disp
2407 && REGNO_REG_CLASS (REGNO (base
)) == SIREG
)
2410 /* Special case: encode reg+reg instead of reg*2. */
2411 if (!base
&& index
&& scale
&& scale
== 2)
2412 base
= index
, scale
= 1;
2414 /* Special case: scaling cannot be encoded without base or displacement. */
2415 if (!base
&& !disp
&& index
&& scale
!= 1)
2426 /* Return cost of the memory address x.
2427 For i386, it is better to use a complex address than let gcc copy
2428 the address into a reg and make a new pseudo. But not if the address
2429 requires to two regs - that would mean more pseudos with longer
2432 ix86_address_cost (x
)
2435 struct ix86_address parts
;
2438 if (!ix86_decompose_address (x
, &parts
))
2441 /* More complex memory references are better. */
2442 if (parts
.disp
&& parts
.disp
!= const0_rtx
)
2445 /* Attempt to minimize number of registers in the address. */
2447 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
))
2449 && (!REG_P (parts
.index
)
2450 || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)))
2454 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
)
2456 && (!REG_P (parts
.index
) || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)
2457 && parts
.base
!= parts
.index
)
2460 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
2461 since it's predecode logic can't detect the length of instructions
2462 and it degenerates to vector decoded. Increase cost of such
2463 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
2464 to split such addresses or even refuse such addresses at all.
2466 Following addressing modes are affected:
2471 The first and last case may be avoidable by explicitly coding the zero in
2472 memory address, but I don't have AMD-K6 machine handy to check this
2476 && ((!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
!= 1)
2477 || (parts
.disp
&& !parts
.base
&& parts
.index
&& parts
.scale
!= 1)
2478 || (!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
== 1)))
2484 /* If X is a machine specific address (i.e. a symbol or label being
2485 referenced as a displacement from the GOT implemented using an
2486 UNSPEC), then return the base term. Otherwise return X. */
2489 ix86_find_base_term (x
)
2494 if (GET_CODE (x
) != PLUS
2495 || XEXP (x
, 0) != pic_offset_table_rtx
2496 || GET_CODE (XEXP (x
, 1)) != CONST
)
2499 term
= XEXP (XEXP (x
, 1), 0);
2501 if (GET_CODE (term
) == PLUS
&& GET_CODE (XEXP (term
, 1)) == CONST_INT
)
2502 term
= XEXP (term
, 0);
2504 if (GET_CODE (term
) != UNSPEC
2505 || XVECLEN (term
, 0) != 1
2506 || XINT (term
, 1) != 7)
2509 term
= XVECEXP (term
, 0, 0);
2511 if (GET_CODE (term
) != SYMBOL_REF
2512 && GET_CODE (term
) != LABEL_REF
)
2518 /* Determine if a given CONST RTX is a valid memory displacement
2522 legitimate_pic_address_disp_p (disp
)
2525 if (GET_CODE (disp
) != CONST
)
2527 disp
= XEXP (disp
, 0);
2529 if (GET_CODE (disp
) == PLUS
)
2531 if (GET_CODE (XEXP (disp
, 1)) != CONST_INT
)
2533 disp
= XEXP (disp
, 0);
2536 if (GET_CODE (disp
) != UNSPEC
2537 || XVECLEN (disp
, 0) != 1)
2540 /* Must be @GOT or @GOTOFF. */
2541 if (XINT (disp
, 1) != 6
2542 && XINT (disp
, 1) != 7)
2545 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2546 && GET_CODE (XVECEXP (disp
, 0, 0)) != LABEL_REF
)
2552 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
2553 memory address for an instruction. The MODE argument is the machine mode
2554 for the MEM expression that wants to use this address.
2556 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2557 convert common non-canonical forms to canonical form so that they will
2561 legitimate_address_p (mode
, addr
, strict
)
2562 enum machine_mode mode
;
2566 struct ix86_address parts
;
2567 rtx base
, index
, disp
;
2568 HOST_WIDE_INT scale
;
2569 const char *reason
= NULL
;
2570 rtx reason_rtx
= NULL_RTX
;
2572 if (TARGET_DEBUG_ADDR
)
2575 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
2576 GET_MODE_NAME (mode
), strict
);
2580 if (! ix86_decompose_address (addr
, &parts
))
2582 reason
= "decomposition failed";
2587 index
= parts
.index
;
2589 scale
= parts
.scale
;
2591 /* Validate base register.
2593 Don't allow SUBREG's here, it can lead to spill failures when the base
2594 is one word out of a two word structure, which is represented internally
2601 if (GET_CODE (base
) != REG
)
2603 reason
= "base is not a register";
2607 if (GET_MODE (base
) != Pmode
)
2609 reason
= "base is not in Pmode";
2613 if ((strict
&& ! REG_OK_FOR_BASE_STRICT_P (base
))
2614 || (! strict
&& ! REG_OK_FOR_BASE_NONSTRICT_P (base
)))
2616 reason
= "base is not valid";
2621 /* Validate index register.
2623 Don't allow SUBREG's here, it can lead to spill failures when the index
2624 is one word out of a two word structure, which is represented internally
2631 if (GET_CODE (index
) != REG
)
2633 reason
= "index is not a register";
2637 if (GET_MODE (index
) != Pmode
)
2639 reason
= "index is not in Pmode";
2643 if ((strict
&& ! REG_OK_FOR_INDEX_STRICT_P (index
))
2644 || (! strict
&& ! REG_OK_FOR_INDEX_NONSTRICT_P (index
)))
2646 reason
= "index is not valid";
2651 /* Validate scale factor. */
2654 reason_rtx
= GEN_INT (scale
);
2657 reason
= "scale without index";
2661 if (scale
!= 2 && scale
!= 4 && scale
!= 8)
2663 reason
= "scale is not a valid multiplier";
2668 /* Validate displacement. */
2673 if (!CONSTANT_ADDRESS_P (disp
))
2675 reason
= "displacement is not constant";
2679 if (GET_CODE (disp
) == CONST_DOUBLE
)
2681 reason
= "displacement is a const_double";
2685 if (flag_pic
&& SYMBOLIC_CONST (disp
))
2687 if (! legitimate_pic_address_disp_p (disp
))
2689 reason
= "displacement is an invalid pic construct";
2693 /* This code used to verify that a symbolic pic displacement
2694 includes the pic_offset_table_rtx register.
2696 While this is good idea, unfortunately these constructs may
2697 be created by "adds using lea" optimization for incorrect
2706 This code is nonsensical, but results in addressing
2707 GOT table with pic_offset_table_rtx base. We can't
2708 just refuse it easilly, since it gets matched by
2709 "addsi3" pattern, that later gets split to lea in the
2710 case output register differs from input. While this
2711 can be handled by separate addsi pattern for this case
2712 that never results in lea, this seems to be easier and
2713 correct fix for crash to disable this test. */
2715 else if (HALF_PIC_P ())
2717 if (! HALF_PIC_ADDRESS_P (disp
)
2718 || (base
!= NULL_RTX
|| index
!= NULL_RTX
))
2720 reason
= "displacement is an invalid half-pic reference";
2726 /* Everything looks valid. */
2727 if (TARGET_DEBUG_ADDR
)
2728 fprintf (stderr
, "Success.\n");
2732 if (TARGET_DEBUG_ADDR
)
2734 fprintf (stderr
, "Error: %s\n", reason
);
2735 debug_rtx (reason_rtx
);
2740 /* Return an unique alias set for the GOT. */
2742 static HOST_WIDE_INT
2743 ix86_GOT_alias_set ()
2745 static HOST_WIDE_INT set
= -1;
2747 set
= new_alias_set ();
2751 /* Return a legitimate reference for ORIG (an address) using the
2752 register REG. If REG is 0, a new pseudo is generated.
2754 There are two types of references that must be handled:
2756 1. Global data references must load the address from the GOT, via
2757 the PIC reg. An insn is emitted to do this load, and the reg is
2760 2. Static data references, constant pool addresses, and code labels
2761 compute the address as an offset from the GOT, whose base is in
2762 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to
2763 differentiate them from global data objects. The returned
2764 address is the PIC reg + an unspec constant.
2766 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2767 reg also appears in the address. */
2770 legitimize_pic_address (orig
, reg
)
2778 if (GET_CODE (addr
) == LABEL_REF
2779 || (GET_CODE (addr
) == SYMBOL_REF
2780 && (CONSTANT_POOL_ADDRESS_P (addr
)
2781 || SYMBOL_REF_FLAG (addr
))))
2783 /* This symbol may be referenced via a displacement from the PIC
2784 base address (@GOTOFF). */
2786 current_function_uses_pic_offset_table
= 1;
2787 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), 7);
2788 new = gen_rtx_CONST (Pmode
, new);
2789 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2793 emit_move_insn (reg
, new);
2797 else if (GET_CODE (addr
) == SYMBOL_REF
)
2799 /* This symbol must be referenced via a load from the
2800 Global Offset Table (@GOT). */
2802 current_function_uses_pic_offset_table
= 1;
2803 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), 6);
2804 new = gen_rtx_CONST (Pmode
, new);
2805 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2806 new = gen_rtx_MEM (Pmode
, new);
2807 RTX_UNCHANGING_P (new) = 1;
2808 MEM_ALIAS_SET (new) = ix86_GOT_alias_set ();
2811 reg
= gen_reg_rtx (Pmode
);
2812 emit_move_insn (reg
, new);
2817 if (GET_CODE (addr
) == CONST
)
2819 addr
= XEXP (addr
, 0);
2820 if (GET_CODE (addr
) == UNSPEC
)
2822 /* Check that the unspec is one of the ones we generate? */
2824 else if (GET_CODE (addr
) != PLUS
)
2827 if (GET_CODE (addr
) == PLUS
)
2829 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
2831 /* Check first to see if this is a constant offset from a @GOTOFF
2832 symbol reference. */
2833 if ((GET_CODE (op0
) == LABEL_REF
2834 || (GET_CODE (op0
) == SYMBOL_REF
2835 && (CONSTANT_POOL_ADDRESS_P (op0
)
2836 || SYMBOL_REF_FLAG (op0
))))
2837 && GET_CODE (op1
) == CONST_INT
)
2839 current_function_uses_pic_offset_table
= 1;
2840 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
), 7);
2841 new = gen_rtx_PLUS (Pmode
, new, op1
);
2842 new = gen_rtx_CONST (Pmode
, new);
2843 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2847 emit_move_insn (reg
, new);
2853 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
2854 new = legitimize_pic_address (XEXP (addr
, 1),
2855 base
== reg
? NULL_RTX
: reg
);
2857 if (GET_CODE (new) == CONST_INT
)
2858 new = plus_constant (base
, INTVAL (new));
2861 if (GET_CODE (new) == PLUS
&& CONSTANT_P (XEXP (new, 1)))
2863 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new, 0));
2864 new = XEXP (new, 1);
2866 new = gen_rtx_PLUS (Pmode
, base
, new);
2874 /* Try machine-dependent ways of modifying an illegitimate address
2875 to be legitimate. If we find one, return the new, valid address.
2876 This macro is used in only one place: `memory_address' in explow.c.
2878 OLDX is the address as it was before break_out_memory_refs was called.
2879 In some cases it is useful to look at this to decide what needs to be done.
2881 MODE and WIN are passed so that this macro can use
2882 GO_IF_LEGITIMATE_ADDRESS.
2884 It is always safe for this macro to do nothing. It exists to recognize
2885 opportunities to optimize the output.
2887 For the 80386, we handle X+REG by loading X into a register R and
2888 using R+REG. R will go in a general reg and indexing will be used.
2889 However, if REG is a broken-out memory address or multiplication,
2890 nothing needs to be done because REG can certainly go in a general reg.
2892 When -fpic is used, special handling is needed for symbolic references.
2893 See comments by legitimize_pic_address in i386.c for details. */
2896 legitimize_address (x
, oldx
, mode
)
2898 register rtx oldx ATTRIBUTE_UNUSED
;
2899 enum machine_mode mode
;
2904 if (TARGET_DEBUG_ADDR
)
2906 fprintf (stderr
, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
2907 GET_MODE_NAME (mode
));
2911 if (flag_pic
&& SYMBOLIC_CONST (x
))
2912 return legitimize_pic_address (x
, 0);
2914 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
2915 if (GET_CODE (x
) == ASHIFT
2916 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2917 && (log
= (unsigned)exact_log2 (INTVAL (XEXP (x
, 1)))) < 4)
2920 x
= gen_rtx_MULT (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
2921 GEN_INT (1 << log
));
2924 if (GET_CODE (x
) == PLUS
)
2926 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
2928 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
2929 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2930 && (log
= (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) < 4)
2933 XEXP (x
, 0) = gen_rtx_MULT (Pmode
,
2934 force_reg (Pmode
, XEXP (XEXP (x
, 0), 0)),
2935 GEN_INT (1 << log
));
2938 if (GET_CODE (XEXP (x
, 1)) == ASHIFT
2939 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2940 && (log
= (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1)))) < 4)
2943 XEXP (x
, 1) = gen_rtx_MULT (Pmode
,
2944 force_reg (Pmode
, XEXP (XEXP (x
, 1), 0)),
2945 GEN_INT (1 << log
));
2948 /* Put multiply first if it isn't already. */
2949 if (GET_CODE (XEXP (x
, 1)) == MULT
)
2951 rtx tmp
= XEXP (x
, 0);
2952 XEXP (x
, 0) = XEXP (x
, 1);
2957 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2958 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2959 created by virtual register instantiation, register elimination, and
2960 similar optimizations. */
2961 if (GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
2964 x
= gen_rtx_PLUS (Pmode
,
2965 gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
2966 XEXP (XEXP (x
, 1), 0)),
2967 XEXP (XEXP (x
, 1), 1));
2971 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2972 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2973 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2974 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2975 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2976 && CONSTANT_P (XEXP (x
, 1)))
2979 rtx other
= NULL_RTX
;
2981 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2983 constant
= XEXP (x
, 1);
2984 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2986 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2988 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2989 other
= XEXP (x
, 1);
2997 x
= gen_rtx_PLUS (Pmode
,
2998 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
2999 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
3000 plus_constant (other
, INTVAL (constant
)));
3004 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
3007 if (GET_CODE (XEXP (x
, 0)) == MULT
)
3010 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
3013 if (GET_CODE (XEXP (x
, 1)) == MULT
)
3016 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
3020 && GET_CODE (XEXP (x
, 1)) == REG
3021 && GET_CODE (XEXP (x
, 0)) == REG
)
3024 if (flag_pic
&& SYMBOLIC_CONST (XEXP (x
, 1)))
3027 x
= legitimize_pic_address (x
, 0);
3030 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
3033 if (GET_CODE (XEXP (x
, 0)) == REG
)
3035 register rtx temp
= gen_reg_rtx (Pmode
);
3036 register rtx val
= force_operand (XEXP (x
, 1), temp
);
3038 emit_move_insn (temp
, val
);
3044 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3046 register rtx temp
= gen_reg_rtx (Pmode
);
3047 register rtx val
= force_operand (XEXP (x
, 0), temp
);
3049 emit_move_insn (temp
, val
);
3059 /* Print an integer constant expression in assembler syntax. Addition
3060 and subtraction are the only arithmetic that may appear in these
3061 expressions. FILE is the stdio stream to write to, X is the rtx, and
3062 CODE is the operand print code from the output string. */
3065 output_pic_addr_const (file
, x
, code
)
3072 switch (GET_CODE (x
))
3082 assemble_name (file
, XSTR (x
, 0));
3083 if (code
== 'P' && ! SYMBOL_REF_FLAG (x
))
3084 fputs ("@PLT", file
);
3091 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
3092 assemble_name (asm_out_file
, buf
);
3096 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
3100 /* This used to output parentheses around the expression,
3101 but that does not work on the 386 (either ATT or BSD assembler). */
3102 output_pic_addr_const (file
, XEXP (x
, 0), code
);
3106 if (GET_MODE (x
) == VOIDmode
)
3108 /* We can use %d if the number is <32 bits and positive. */
3109 if (CONST_DOUBLE_HIGH (x
) || CONST_DOUBLE_LOW (x
) < 0)
3110 fprintf (file
, "0x%lx%08lx",
3111 (unsigned long) CONST_DOUBLE_HIGH (x
),
3112 (unsigned long) CONST_DOUBLE_LOW (x
));
3114 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
3117 /* We can't handle floating point constants;
3118 PRINT_OPERAND must handle them. */
3119 output_operand_lossage ("floating constant misused");
3123 /* Some assemblers need integer constants to appear first. */
3124 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
3126 output_pic_addr_const (file
, XEXP (x
, 0), code
);
3128 output_pic_addr_const (file
, XEXP (x
, 1), code
);
3130 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3132 output_pic_addr_const (file
, XEXP (x
, 1), code
);
3134 output_pic_addr_const (file
, XEXP (x
, 0), code
);
3141 putc (ASSEMBLER_DIALECT
? '(' : '[', file
);
3142 output_pic_addr_const (file
, XEXP (x
, 0), code
);
3144 output_pic_addr_const (file
, XEXP (x
, 1), code
);
3145 putc (ASSEMBLER_DIALECT
? ')' : ']', file
);
3149 if (XVECLEN (x
, 0) != 1)
3151 output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
3152 switch (XINT (x
, 1))
3155 fputs ("@GOT", file
);
3158 fputs ("@GOTOFF", file
);
3161 fputs ("@PLT", file
);
3164 output_operand_lossage ("invalid UNSPEC as operand");
3170 output_operand_lossage ("invalid expression as operand");
3174 /* This is called from dwarfout.c via ASM_OUTPUT_DWARF_ADDR_CONST.
3175 We need to handle our special PIC relocations. */
3178 i386_dwarf_output_addr_const (file
, x
)
3182 fprintf (file
, "%s", INT_ASM_OP
);
3184 output_pic_addr_const (file
, x
, '\0');
3186 output_addr_const (file
, x
);
3190 /* In the name of slightly smaller debug output, and to cater to
3191 general assembler losage, recognize PIC+GOTOFF and turn it back
3192 into a direct symbol reference. */
3195 i386_simplify_dwarf_addr (orig_x
)
3200 if (GET_CODE (x
) != PLUS
3201 || GET_CODE (XEXP (x
, 0)) != REG
3202 || GET_CODE (XEXP (x
, 1)) != CONST
)
3205 x
= XEXP (XEXP (x
, 1), 0);
3206 if (GET_CODE (x
) == UNSPEC
3207 && (XINT (x
, 1) == 6
3208 || XINT (x
, 1) == 7))
3209 return XVECEXP (x
, 0, 0);
3211 if (GET_CODE (x
) == PLUS
3212 && GET_CODE (XEXP (x
, 0)) == UNSPEC
3213 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3214 && (XINT (XEXP (x
, 0), 1) == 6
3215 || XINT (XEXP (x
, 0), 1) == 7))
3216 return gen_rtx_PLUS (VOIDmode
, XVECEXP (XEXP (x
, 0), 0, 0), XEXP (x
, 1));
3222 put_condition_code (code
, mode
, reverse
, fp
, file
)
3224 enum machine_mode mode
;
3230 if (mode
== CCFPmode
|| mode
== CCFPUmode
)
3232 enum rtx_code second_code
, bypass_code
;
3233 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
3234 if (bypass_code
!= NIL
|| second_code
!= NIL
)
3236 code
= ix86_fp_compare_code_to_integer (code
);
3240 code
= reverse_condition (code
);
3251 if (mode
!= CCmode
&& mode
!= CCNOmode
&& mode
!= CCGCmode
)
3256 /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers.
3257 Those same assemblers have the same but opposite losage on cmov. */
3260 suffix
= fp
? "nbe" : "a";
3263 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
3265 else if (mode
== CCmode
|| mode
== CCGCmode
)
3276 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
3278 else if (mode
== CCmode
|| mode
== CCGCmode
)
3287 suffix
= fp
? "nb" : "ae";
3290 if (mode
!= CCmode
&& mode
!= CCGCmode
&& mode
!= CCNOmode
)
3300 suffix
= fp
? "u" : "p";
3303 suffix
= fp
? "nu" : "np";
3308 fputs (suffix
, file
);
3312 print_reg (x
, code
, file
)
3317 if (REGNO (x
) == ARG_POINTER_REGNUM
3318 || REGNO (x
) == FRAME_POINTER_REGNUM
3319 || REGNO (x
) == FLAGS_REG
3320 || REGNO (x
) == FPSR_REG
)
3323 if (ASSEMBLER_DIALECT
== 0 || USER_LABEL_PREFIX
[0] == 0)
3328 else if (code
== 'b')
3330 else if (code
== 'k')
3332 else if (code
== 'q')
3334 else if (code
== 'y')
3336 else if (code
== 'h')
3338 else if (code
== 'm' || MMX_REG_P (x
))
3341 code
= GET_MODE_SIZE (GET_MODE (x
));
3343 /* Irritatingly, AMD extended registers use different naming convention
3344 from the normal registers. */
3345 if (REX_INT_REG_P (x
))
3350 error ("Extended registers have no high halves\n");
3353 fprintf (file
, "r%ib", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
3356 fprintf (file
, "r%iw", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
3359 fprintf (file
, "r%id", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
3362 fprintf (file
, "r%i", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
3365 error ("Unsupported operand size for extended register.\n");
3373 fputs (hi_reg_name
[REGNO (x
)], file
);
3376 if (STACK_TOP_P (x
))
3378 fputs ("st(0)", file
);
3385 if (! ANY_FP_REG_P (x
))
3386 putc (code
== 8 ? 'r' : 'e', file
);
3390 fputs (hi_reg_name
[REGNO (x
)], file
);
3393 fputs (qi_reg_name
[REGNO (x
)], file
);
3396 fputs (qi_high_reg_name
[REGNO (x
)], file
);
3404 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
3405 C -- print opcode suffix for set/cmov insn.
3406 c -- like C, but print reversed condition
3407 R -- print the prefix for register names.
3408 z -- print the opcode suffix for the size of the current operand.
3409 * -- print a star (in certain assembler syntax)
3410 A -- print an absolute memory reference.
3411 w -- print the operand as if it's a "word" (HImode) even if it isn't.
3412 s -- print a shift double count, followed by the assemblers argument
3414 b -- print the QImode name of the register for the indicated operand.
3415 %b0 would print %al if operands[0] is reg 0.
3416 w -- likewise, print the HImode name of the register.
3417 k -- likewise, print the SImode name of the register.
3418 q -- likewise, print the DImode name of the register.
3419 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
3420 y -- print "st(0)" instead of "st" as a register.
3421 m -- print "st(n)" as an mmx register.
3422 D -- print condition for SSE cmp instruction.
3426 print_operand (file
, x
, code
)
3436 if (ASSEMBLER_DIALECT
== 0)
3441 if (ASSEMBLER_DIALECT
== 0)
3443 else if (ASSEMBLER_DIALECT
== 1)
3445 /* Intel syntax. For absolute addresses, registers should not
3446 be surrounded by braces. */
3447 if (GET_CODE (x
) != REG
)
3450 PRINT_OPERAND (file
, x
, 0);
3456 PRINT_OPERAND (file
, x
, 0);
3461 if (ASSEMBLER_DIALECT
== 0)
3466 if (ASSEMBLER_DIALECT
== 0)
3471 if (ASSEMBLER_DIALECT
== 0)
3476 if (ASSEMBLER_DIALECT
== 0)
3481 if (ASSEMBLER_DIALECT
== 0)
3486 if (ASSEMBLER_DIALECT
== 0)
3491 /* 387 opcodes don't get size suffixes if the operands are
3494 if (STACK_REG_P (x
))
3497 /* this is the size of op from size of operand */
3498 switch (GET_MODE_SIZE (GET_MODE (x
)))
3501 #ifdef HAVE_GAS_FILDS_FISTS
3507 if (GET_MODE (x
) == SFmode
)
3522 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
3524 #ifdef GAS_MNEMONICS
3551 if (GET_CODE (x
) == CONST_INT
|| ! SHIFT_DOUBLE_OMITS_COUNT
)
3553 PRINT_OPERAND (file
, x
, 0);
3559 /* Little bit of braindamage here. The SSE compare instructions
3560 does use completely different names for the comparisons that the
3561 fp conditional moves. */
3562 switch (GET_CODE (x
))
3577 fputs ("unord", file
);
3581 fputs ("neq", file
);
3585 fputs ("nlt", file
);
3589 fputs ("nle", file
);
3592 fputs ("ord", file
);
3600 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 0, file
);
3603 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 1, file
);
3606 /* Like above, but reverse condition */
3608 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 0, file
);
3611 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 1, file
);
3617 sprintf (str
, "invalid operand code `%c'", code
);
3618 output_operand_lossage (str
);
3623 if (GET_CODE (x
) == REG
)
3625 PRINT_REG (x
, code
, file
);
3628 else if (GET_CODE (x
) == MEM
)
3630 /* No `byte ptr' prefix for call instructions. */
3631 if (ASSEMBLER_DIALECT
!= 0 && code
!= 'X' && code
!= 'P')
3634 switch (GET_MODE_SIZE (GET_MODE (x
)))
3636 case 1: size
= "BYTE"; break;
3637 case 2: size
= "WORD"; break;
3638 case 4: size
= "DWORD"; break;
3639 case 8: size
= "QWORD"; break;
3640 case 12: size
= "XWORD"; break;
3641 case 16: size
= "XMMWORD"; break;
3646 /* Check for explicit size override (codes 'b', 'w' and 'k') */
3649 else if (code
== 'w')
3651 else if (code
== 'k')
3655 fputs (" PTR ", file
);
3659 if (flag_pic
&& CONSTANT_ADDRESS_P (x
))
3660 output_pic_addr_const (file
, x
, code
);
3665 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
3670 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3671 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
3673 if (ASSEMBLER_DIALECT
== 0)
3675 fprintf (file
, "0x%lx", l
);
3678 /* These float cases don't actually occur as immediate operands. */
3679 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
3684 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3685 REAL_VALUE_TO_DECIMAL (r
, "%.22e", dstr
);
3686 fprintf (file
, "%s", dstr
);
3689 else if (GET_CODE (x
) == CONST_DOUBLE
3690 && (GET_MODE (x
) == XFmode
|| GET_MODE (x
) == TFmode
))
3695 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3696 REAL_VALUE_TO_DECIMAL (r
, "%.22e", dstr
);
3697 fprintf (file
, "%s", dstr
);
3703 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3705 if (ASSEMBLER_DIALECT
== 0)
3708 else if (GET_CODE (x
) == CONST
|| GET_CODE (x
) == SYMBOL_REF
3709 || GET_CODE (x
) == LABEL_REF
)
3711 if (ASSEMBLER_DIALECT
== 0)
3714 fputs ("OFFSET FLAT:", file
);
3717 if (GET_CODE (x
) == CONST_INT
)
3718 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
3720 output_pic_addr_const (file
, x
, code
);
3722 output_addr_const (file
, x
);
3726 /* Print a memory operand whose address is ADDR. */
3729 print_operand_address (file
, addr
)
3733 struct ix86_address parts
;
3734 rtx base
, index
, disp
;
3737 if (! ix86_decompose_address (addr
, &parts
))
3741 index
= parts
.index
;
3743 scale
= parts
.scale
;
3745 if (!base
&& !index
)
3747 /* Displacement only requires special attention. */
3749 if (GET_CODE (disp
) == CONST_INT
)
3751 if (ASSEMBLER_DIALECT
!= 0)
3753 if (USER_LABEL_PREFIX
[0] == 0)
3755 fputs ("ds:", file
);
3757 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
3760 output_pic_addr_const (file
, addr
, 0);
3762 output_addr_const (file
, addr
);
3766 if (ASSEMBLER_DIALECT
== 0)
3771 output_pic_addr_const (file
, disp
, 0);
3772 else if (GET_CODE (disp
) == LABEL_REF
)
3773 output_asm_label (disp
);
3775 output_addr_const (file
, disp
);
3780 PRINT_REG (base
, 0, file
);
3784 PRINT_REG (index
, 0, file
);
3786 fprintf (file
, ",%d", scale
);
3792 rtx offset
= NULL_RTX
;
3796 /* Pull out the offset of a symbol; print any symbol itself. */
3797 if (GET_CODE (disp
) == CONST
3798 && GET_CODE (XEXP (disp
, 0)) == PLUS
3799 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
3801 offset
= XEXP (XEXP (disp
, 0), 1);
3802 disp
= gen_rtx_CONST (VOIDmode
,
3803 XEXP (XEXP (disp
, 0), 0));
3807 output_pic_addr_const (file
, disp
, 0);
3808 else if (GET_CODE (disp
) == LABEL_REF
)
3809 output_asm_label (disp
);
3810 else if (GET_CODE (disp
) == CONST_INT
)
3813 output_addr_const (file
, disp
);
3819 PRINT_REG (base
, 0, file
);
3822 if (INTVAL (offset
) >= 0)
3824 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
3828 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
3835 PRINT_REG (index
, 0, file
);
3837 fprintf (file
, "*%d", scale
);
3844 /* Split one or more DImode RTL references into pairs of SImode
3845 references. The RTL can be REG, offsettable MEM, integer constant, or
3846 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3847 split and "num" is its length. lo_half and hi_half are output arrays
3848 that parallel "operands". */
3851 split_di (operands
, num
, lo_half
, hi_half
)
3854 rtx lo_half
[], hi_half
[];
3858 rtx op
= operands
[num
];
3859 if (CONSTANT_P (op
))
3860 split_double (op
, &lo_half
[num
], &hi_half
[num
]);
3861 else if (! reload_completed
)
3863 lo_half
[num
] = gen_lowpart (SImode
, op
);
3864 hi_half
[num
] = gen_highpart (SImode
, op
);
3866 else if (GET_CODE (op
) == REG
)
3868 lo_half
[num
] = gen_rtx_REG (SImode
, REGNO (op
));
3869 hi_half
[num
] = gen_rtx_REG (SImode
, REGNO (op
) + 1);
3871 else if (offsettable_memref_p (op
))
3873 rtx lo_addr
= XEXP (op
, 0);
3874 rtx hi_addr
= XEXP (adj_offsettable_operand (op
, 4), 0);
3875 lo_half
[num
] = change_address (op
, SImode
, lo_addr
);
3876 hi_half
[num
] = change_address (op
, SImode
, hi_addr
);
3883 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
3884 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
3885 is the expression of the binary operation. The output may either be
3886 emitted here, or returned to the caller, like all output_* functions.
3888 There is no guarantee that the operands are the same mode, as they
3889 might be within FLOAT or FLOAT_EXTEND expressions. */
3891 #ifndef SYSV386_COMPAT
3892 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
3893 wants to fix the assemblers because that causes incompatibility
3894 with gcc. No-one wants to fix gcc because that causes
3895 incompatibility with assemblers... You can use the option of
3896 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
3897 #define SYSV386_COMPAT 1
3901 output_387_binary_op (insn
, operands
)
3905 static char buf
[30];
3908 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]) | SSE_REG_P (operands
[2]);
3910 #ifdef ENABLE_CHECKING
3911 /* Even if we do not want to check the inputs, this documents input
3912 constraints. Which helps in understanding the following code. */
3913 if (STACK_REG_P (operands
[0])
3914 && ((REG_P (operands
[1])
3915 && REGNO (operands
[0]) == REGNO (operands
[1])
3916 && (STACK_REG_P (operands
[2]) || GET_CODE (operands
[2]) == MEM
))
3917 || (REG_P (operands
[2])
3918 && REGNO (operands
[0]) == REGNO (operands
[2])
3919 && (STACK_REG_P (operands
[1]) || GET_CODE (operands
[1]) == MEM
)))
3920 && (STACK_TOP_P (operands
[1]) || STACK_TOP_P (operands
[2])))
3926 switch (GET_CODE (operands
[3]))
3929 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3930 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3938 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3939 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3947 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3948 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3956 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
3957 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
3971 if (GET_MODE (operands
[0]) == SFmode
)
3972 strcat (buf
, "ss\t{%2, %0|%0, %2}");
3974 strcat (buf
, "sd\t{%2, %0|%0, %2}");
3979 switch (GET_CODE (operands
[3]))
3983 if (REG_P (operands
[2]) && REGNO (operands
[0]) == REGNO (operands
[2]))
3985 rtx temp
= operands
[2];
3986 operands
[2] = operands
[1];
3990 /* know operands[0] == operands[1]. */
3992 if (GET_CODE (operands
[2]) == MEM
)
3998 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
4000 if (STACK_TOP_P (operands
[0]))
4001 /* How is it that we are storing to a dead operand[2]?
4002 Well, presumably operands[1] is dead too. We can't
4003 store the result to st(0) as st(0) gets popped on this
4004 instruction. Instead store to operands[2] (which I
4005 think has to be st(1)). st(1) will be popped later.
4006 gcc <= 2.8.1 didn't have this check and generated
4007 assembly code that the Unixware assembler rejected. */
4008 p
= "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
4010 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
4014 if (STACK_TOP_P (operands
[0]))
4015 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
4017 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
4022 if (GET_CODE (operands
[1]) == MEM
)
4028 if (GET_CODE (operands
[2]) == MEM
)
4034 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
4037 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
4038 derived assemblers, confusingly reverse the direction of
4039 the operation for fsub{r} and fdiv{r} when the
4040 destination register is not st(0). The Intel assembler
4041 doesn't have this brain damage. Read !SYSV386_COMPAT to
4042 figure out what the hardware really does. */
4043 if (STACK_TOP_P (operands
[0]))
4044 p
= "{p\t%0, %2|rp\t%2, %0}";
4046 p
= "{rp\t%2, %0|p\t%0, %2}";
4048 if (STACK_TOP_P (operands
[0]))
4049 /* As above for fmul/fadd, we can't store to st(0). */
4050 p
= "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
4052 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
4057 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[1])))
4060 if (STACK_TOP_P (operands
[0]))
4061 p
= "{rp\t%0, %1|p\t%1, %0}";
4063 p
= "{p\t%1, %0|rp\t%0, %1}";
4065 if (STACK_TOP_P (operands
[0]))
4066 p
= "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
4068 p
= "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
4073 if (STACK_TOP_P (operands
[0]))
4075 if (STACK_TOP_P (operands
[1]))
4076 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
4078 p
= "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
4081 else if (STACK_TOP_P (operands
[1]))
4084 p
= "{\t%1, %0|r\t%0, %1}";
4086 p
= "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
4092 p
= "{r\t%2, %0|\t%0, %2}";
4094 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
4107 /* Output code for INSN to convert a float to a signed int. OPERANDS
4108 are the insn operands. The output may be [HSD]Imode and the input
4109 operand may be [SDX]Fmode. */
4112 output_fix_trunc (insn
, operands
)
4116 int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
4117 int dimode_p
= GET_MODE (operands
[0]) == DImode
;
4120 /* Jump through a hoop or two for DImode, since the hardware has no
4121 non-popping instruction. We used to do this a different way, but
4122 that was somewhat fragile and broke with post-reload splitters. */
4123 if (dimode_p
&& !stack_top_dies
)
4124 output_asm_insn ("fld\t%y1", operands
);
4126 if (! STACK_TOP_P (operands
[1]))
4129 xops
[0] = GEN_INT (12);
4130 xops
[1] = adj_offsettable_operand (operands
[2], 1);
4131 xops
[1] = change_address (xops
[1], QImode
, NULL_RTX
);
4133 xops
[2] = operands
[0];
4134 if (GET_CODE (operands
[0]) != MEM
)
4135 xops
[2] = operands
[3];
4137 output_asm_insn ("fnstcw\t%2", operands
);
4138 output_asm_insn ("mov{l}\t{%2, %4|%4, %2}", operands
);
4139 output_asm_insn ("mov{b}\t{%0, %1|%1, %0}", xops
);
4140 output_asm_insn ("fldcw\t%2", operands
);
4141 output_asm_insn ("mov{l}\t{%4, %2|%2, %4}", operands
);
4143 if (stack_top_dies
|| dimode_p
)
4144 output_asm_insn ("fistp%z2\t%2", xops
);
4146 output_asm_insn ("fist%z2\t%2", xops
);
4148 output_asm_insn ("fldcw\t%2", operands
);
4150 if (GET_CODE (operands
[0]) != MEM
)
4154 split_di (operands
+0, 1, xops
+0, xops
+1);
4155 split_di (operands
+3, 1, xops
+2, xops
+3);
4156 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops
);
4157 output_asm_insn ("mov{l}\t{%3, %1|%1, %3}", xops
);
4159 else if (GET_MODE (operands
[0]) == SImode
)
4160 output_asm_insn ("mov{l}\t{%3, %0|%0, %3}", operands
);
4162 output_asm_insn ("mov{w}\t{%3, %0|%0, %3}", operands
);
4168 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
4169 should be used and 2 when fnstsw should be used. UNORDERED_P is true
4170 when fucom should be used. */
4173 output_fp_compare (insn
, operands
, eflags_p
, unordered_p
)
4176 int eflags_p
, unordered_p
;
4179 rtx cmp_op0
= operands
[0];
4180 rtx cmp_op1
= operands
[1];
4181 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]);
4186 cmp_op1
= operands
[2];
4190 if (GET_MODE (operands
[0]) == SFmode
)
4192 return "ucomiss\t{%1, %0|%0, %1}";
4194 return "comiss\t{%1, %0|%0, %y}";
4197 return "ucomisd\t{%1, %0|%0, %1}";
4199 return "comisd\t{%1, %0|%0, %y}";
4202 if (! STACK_TOP_P (cmp_op0
))
4205 stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
4207 if (STACK_REG_P (cmp_op1
)
4209 && find_regno_note (insn
, REG_DEAD
, REGNO (cmp_op1
))
4210 && REGNO (cmp_op1
) != FIRST_STACK_REG
)
4212 /* If both the top of the 387 stack dies, and the other operand
4213 is also a stack register that dies, then this must be a
4214 `fcompp' float compare */
4218 /* There is no double popping fcomi variant. Fortunately,
4219 eflags is immune from the fstp's cc clobbering. */
4221 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands
);
4223 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands
);
4231 return "fucompp\n\tfnstsw\t%0";
4233 return "fcompp\n\tfnstsw\t%0";
4246 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
4248 static const char * const alt
[24] =
4260 "fcomi\t{%y1, %0|%0, %y1}",
4261 "fcomip\t{%y1, %0|%0, %y1}",
4262 "fucomi\t{%y1, %0|%0, %y1}",
4263 "fucomip\t{%y1, %0|%0, %y1}",
4270 "fcom%z2\t%y2\n\tfnstsw\t%0",
4271 "fcomp%z2\t%y2\n\tfnstsw\t%0",
4272 "fucom%z2\t%y2\n\tfnstsw\t%0",
4273 "fucomp%z2\t%y2\n\tfnstsw\t%0",
4275 "ficom%z2\t%y2\n\tfnstsw\t%0",
4276 "ficomp%z2\t%y2\n\tfnstsw\t%0",
4284 mask
= eflags_p
<< 3;
4285 mask
|= (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
) << 2;
4286 mask
|= unordered_p
<< 1;
4287 mask
|= stack_top_dies
;
4299 /* Output assembler code to FILE to initialize basic-block profiling.
4301 If profile_block_flag == 2
4303 Output code to call the subroutine `__bb_init_trace_func'
4304 and pass two parameters to it. The first parameter is
4305 the address of a block allocated in the object module.
4306 The second parameter is the number of the first basic block
4309 The name of the block is a local symbol made with this statement:
4311 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
4313 Of course, since you are writing the definition of
4314 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
4315 can take a short cut in the definition of this macro and use the
4316 name that you know will result.
4318 The number of the first basic block of the function is
4319 passed to the macro in BLOCK_OR_LABEL.
4321 If described in a virtual assembler language the code to be
4325 parameter2 <- BLOCK_OR_LABEL
4326 call __bb_init_trace_func
4328 else if profile_block_flag != 0
4330 Output code to call the subroutine `__bb_init_func'
4331 and pass one single parameter to it, which is the same
4332 as the first parameter to `__bb_init_trace_func'.
4334 The first word of this parameter is a flag which will be nonzero if
4335 the object module has already been initialized. So test this word
4336 first, and do not call `__bb_init_func' if the flag is nonzero.
4337 Note: When profile_block_flag == 2 the test need not be done
4338 but `__bb_init_trace_func' *must* be called.
4340 BLOCK_OR_LABEL may be used to generate a label number as a
4341 branch destination in case `__bb_init_func' will not be called.
4343 If described in a virtual assembler language the code to be
4354 ix86_output_function_block_profiler (file
, block_or_label
)
4358 static int num_func
= 0;
4360 char block_table
[80], false_label
[80];
4362 ASM_GENERATE_INTERNAL_LABEL (block_table
, "LPBX", 0);
4364 xops
[1] = gen_rtx_SYMBOL_REF (VOIDmode
, block_table
);
4365 xops
[5] = stack_pointer_rtx
;
4366 xops
[7] = gen_rtx_REG (Pmode
, 0); /* eax */
4368 CONSTANT_POOL_ADDRESS_P (xops
[1]) = TRUE
;
4370 switch (profile_block_flag
)
4373 xops
[2] = GEN_INT (block_or_label
);
4374 xops
[3] = gen_rtx_MEM (Pmode
,
4375 gen_rtx_SYMBOL_REF (VOIDmode
, "__bb_init_trace_func"));
4376 xops
[6] = GEN_INT (8);
4378 output_asm_insn ("push{l}\t%2", xops
);
4380 output_asm_insn ("push{l}\t%1", xops
);
4383 output_asm_insn ("lea{l}\t{%a1, %7|%7, %a1}", xops
);
4384 output_asm_insn ("push{l}\t%7", xops
);
4386 output_asm_insn ("call\t%P3", xops
);
4387 output_asm_insn ("add{l}\t{%6, %5|%5, %6}", xops
);
4391 ASM_GENERATE_INTERNAL_LABEL (false_label
, "LPBZ", num_func
);
4393 xops
[0] = const0_rtx
;
4394 xops
[2] = gen_rtx_MEM (Pmode
,
4395 gen_rtx_SYMBOL_REF (VOIDmode
, false_label
));
4396 xops
[3] = gen_rtx_MEM (Pmode
,
4397 gen_rtx_SYMBOL_REF (VOIDmode
, "__bb_init_func"));
4398 xops
[4] = gen_rtx_MEM (Pmode
, xops
[1]);
4399 xops
[6] = GEN_INT (4);
4401 CONSTANT_POOL_ADDRESS_P (xops
[2]) = TRUE
;
4403 output_asm_insn ("cmp{l}\t{%0, %4|%4, %0}", xops
);
4404 output_asm_insn ("jne\t%2", xops
);
4407 output_asm_insn ("push{l}\t%1", xops
);
4410 output_asm_insn ("lea{l}\t{%a1, %7|%7, %a2}", xops
);
4411 output_asm_insn ("push{l}\t%7", xops
);
4413 output_asm_insn ("call\t%P3", xops
);
4414 output_asm_insn ("add{l}\t{%6, %5|%5, %6}", xops
);
4415 ASM_OUTPUT_INTERNAL_LABEL (file
, "LPBZ", num_func
);
4421 /* Output assembler code to FILE to increment a counter associated
4422 with basic block number BLOCKNO.
4424 If profile_block_flag == 2
4426 Output code to initialize the global structure `__bb' and
4427 call the function `__bb_trace_func' which will increment the
4430 `__bb' consists of two words. In the first word the number
4431 of the basic block has to be stored. In the second word
4432 the address of a block allocated in the object module
4435 The basic block number is given by BLOCKNO.
4437 The address of the block is given by the label created with
4439 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0);
4441 by FUNCTION_BLOCK_PROFILER.
4443 Of course, since you are writing the definition of
4444 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
4445 can take a short cut in the definition of this macro and use the
4446 name that you know will result.
4448 If described in a virtual assembler language the code to be
4451 move BLOCKNO -> (__bb)
4452 move LPBX0 -> (__bb+4)
4453 call __bb_trace_func
4455 Note that function `__bb_trace_func' must not change the
4456 machine state, especially the flag register. To grant
4457 this, you must output code to save and restore registers
4458 either in this macro or in the macros MACHINE_STATE_SAVE
4459 and MACHINE_STATE_RESTORE. The last two macros will be
4460 used in the function `__bb_trace_func', so you must make
4461 sure that the function prologue does not change any
4462 register prior to saving it with MACHINE_STATE_SAVE.
4464 else if profile_block_flag != 0
4466 Output code to increment the counter directly.
4467 Basic blocks are numbered separately from zero within each
4468 compiled object module. The count associated with block number
4469 BLOCKNO is at index BLOCKNO in an array of words; the name of
4470 this array is a local symbol made with this statement:
4472 ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2);
4474 Of course, since you are writing the definition of
4475 `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you
4476 can take a short cut in the definition of this macro and use the
4477 name that you know will result.
4479 If described in a virtual assembler language the code to be
4482 inc (LPBX2+4*BLOCKNO)
4486 ix86_output_block_profiler (file
, blockno
)
4487 FILE *file ATTRIBUTE_UNUSED
;
4490 rtx xops
[8], cnt_rtx
;
4492 char *block_table
= counts
;
4494 switch (profile_block_flag
)
4497 ASM_GENERATE_INTERNAL_LABEL (block_table
, "LPBX", 0);
4499 xops
[1] = gen_rtx_SYMBOL_REF (VOIDmode
, block_table
);
4500 xops
[2] = GEN_INT (blockno
);
4501 xops
[3] = gen_rtx_MEM (Pmode
,
4502 gen_rtx_SYMBOL_REF (VOIDmode
, "__bb_trace_func"));
4503 xops
[4] = gen_rtx_SYMBOL_REF (VOIDmode
, "__bb");
4504 xops
[5] = plus_constant (xops
[4], 4);
4505 xops
[0] = gen_rtx_MEM (SImode
, xops
[4]);
4506 xops
[6] = gen_rtx_MEM (SImode
, xops
[5]);
4508 CONSTANT_POOL_ADDRESS_P (xops
[1]) = TRUE
;
4510 output_asm_insn ("pushf", xops
);
4511 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops
);
4514 xops
[7] = gen_rtx_REG (Pmode
, 0); /* eax */
4515 output_asm_insn ("push{l}\t%7", xops
);
4516 output_asm_insn ("lea{l}\t{%a1, %7|%7, %a1}", xops
);
4517 output_asm_insn ("mov{l}\t{%7, %6|%6, %7}", xops
);
4518 output_asm_insn ("pop{l}\t%7", xops
);
4521 output_asm_insn ("mov{l}\t{%1, %6|%6, %1}", xops
);
4522 output_asm_insn ("call\t%P3", xops
);
4523 output_asm_insn ("popf", xops
);
4528 ASM_GENERATE_INTERNAL_LABEL (counts
, "LPBX", 2);
4529 cnt_rtx
= gen_rtx_SYMBOL_REF (VOIDmode
, counts
);
4530 SYMBOL_REF_FLAG (cnt_rtx
) = TRUE
;
4533 cnt_rtx
= plus_constant (cnt_rtx
, blockno
*4);
4536 cnt_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, cnt_rtx
);
4538 xops
[0] = gen_rtx_MEM (SImode
, cnt_rtx
);
4539 output_asm_insn ("inc{l}\t%0", xops
);
4546 ix86_expand_move (mode
, operands
)
4547 enum machine_mode mode
;
4550 int strict
= (reload_in_progress
|| reload_completed
);
4553 if (flag_pic
&& mode
== Pmode
&& symbolic_operand (operands
[1], Pmode
))
4555 /* Emit insns to move operands[1] into operands[0]. */
4557 if (GET_CODE (operands
[0]) == MEM
)
4558 operands
[1] = force_reg (Pmode
, operands
[1]);
4561 rtx temp
= operands
[0];
4562 if (GET_CODE (temp
) != REG
)
4563 temp
= gen_reg_rtx (Pmode
);
4564 temp
= legitimize_pic_address (operands
[1], temp
);
4565 if (temp
== operands
[0])
4572 if (GET_CODE (operands
[0]) == MEM
4573 && (GET_MODE (operands
[0]) == QImode
4574 || !push_operand (operands
[0], mode
))
4575 && GET_CODE (operands
[1]) == MEM
)
4576 operands
[1] = force_reg (mode
, operands
[1]);
4578 if (push_operand (operands
[0], mode
)
4579 && ! general_no_elim_operand (operands
[1], mode
))
4580 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
4582 if (FLOAT_MODE_P (mode
))
4584 /* If we are loading a floating point constant to a register,
4585 force the value to memory now, since we'll get better code
4586 out the back end. */
4590 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
4591 && register_operand (operands
[0], mode
))
4592 operands
[1] = validize_mem (force_const_mem (mode
, operands
[1]));
4596 insn
= gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
4601 /* Attempt to expand a binary operator. Make the expansion closer to the
4602 actual machine, then just general_operand, which will allow 3 separate
4603 memory references (one output, two input) in a single insn. */
4606 ix86_expand_binary_operator (code
, mode
, operands
)
4608 enum machine_mode mode
;
4611 int matching_memory
;
4612 rtx src1
, src2
, dst
, op
, clob
;
4618 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
4619 if (GET_RTX_CLASS (code
) == 'c'
4620 && (rtx_equal_p (dst
, src2
)
4621 || immediate_operand (src1
, mode
)))
4628 /* If the destination is memory, and we do not have matching source
4629 operands, do things in registers. */
4630 matching_memory
= 0;
4631 if (GET_CODE (dst
) == MEM
)
4633 if (rtx_equal_p (dst
, src1
))
4634 matching_memory
= 1;
4635 else if (GET_RTX_CLASS (code
) == 'c'
4636 && rtx_equal_p (dst
, src2
))
4637 matching_memory
= 2;
4639 dst
= gen_reg_rtx (mode
);
4642 /* Both source operands cannot be in memory. */
4643 if (GET_CODE (src1
) == MEM
&& GET_CODE (src2
) == MEM
)
4645 if (matching_memory
!= 2)
4646 src2
= force_reg (mode
, src2
);
4648 src1
= force_reg (mode
, src1
);
4651 /* If the operation is not commutable, source 1 cannot be a constant
4652 or non-matching memory. */
4653 if ((CONSTANT_P (src1
)
4654 || (!matching_memory
&& GET_CODE (src1
) == MEM
))
4655 && GET_RTX_CLASS (code
) != 'c')
4656 src1
= force_reg (mode
, src1
);
4658 /* If optimizing, copy to regs to improve CSE */
4659 if (optimize
&& ! no_new_pseudos
)
4661 if (GET_CODE (dst
) == MEM
)
4662 dst
= gen_reg_rtx (mode
);
4663 if (GET_CODE (src1
) == MEM
)
4664 src1
= force_reg (mode
, src1
);
4665 if (GET_CODE (src2
) == MEM
)
4666 src2
= force_reg (mode
, src2
);
4669 /* Emit the instruction. */
4671 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, mode
, src1
, src2
));
4672 if (reload_in_progress
)
4674 /* Reload doesn't know about the flags register, and doesn't know that
4675 it doesn't want to clobber it. We can only do this with PLUS. */
4682 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
4683 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
4686 /* Fix up the destination if needed. */
4687 if (dst
!= operands
[0])
4688 emit_move_insn (operands
[0], dst
);
4691 /* Return TRUE or FALSE depending on whether the binary operator meets the
4692 appropriate constraints. */
4695 ix86_binary_operator_ok (code
, mode
, operands
)
4697 enum machine_mode mode ATTRIBUTE_UNUSED
;
4700 /* Both source operands cannot be in memory. */
4701 if (GET_CODE (operands
[1]) == MEM
&& GET_CODE (operands
[2]) == MEM
)
4703 /* If the operation is not commutable, source 1 cannot be a constant. */
4704 if (CONSTANT_P (operands
[1]) && GET_RTX_CLASS (code
) != 'c')
4706 /* If the destination is memory, we must have a matching source operand. */
4707 if (GET_CODE (operands
[0]) == MEM
4708 && ! (rtx_equal_p (operands
[0], operands
[1])
4709 || (GET_RTX_CLASS (code
) == 'c'
4710 && rtx_equal_p (operands
[0], operands
[2]))))
4712 /* If the operation is not commutable and the source 1 is memory, we must
4713 have a matching destionation. */
4714 if (GET_CODE (operands
[1]) == MEM
4715 && GET_RTX_CLASS (code
) != 'c'
4716 && ! rtx_equal_p (operands
[0], operands
[1]))
4721 /* Attempt to expand a unary operator. Make the expansion closer to the
4722 actual machine, then just general_operand, which will allow 2 separate
4723 memory references (one output, one input) in a single insn. */
4726 ix86_expand_unary_operator (code
, mode
, operands
)
4728 enum machine_mode mode
;
4731 int matching_memory
;
4732 rtx src
, dst
, op
, clob
;
4737 /* If the destination is memory, and we do not have matching source
4738 operands, do things in registers. */
4739 matching_memory
= 0;
4740 if (GET_CODE (dst
) == MEM
)
4742 if (rtx_equal_p (dst
, src
))
4743 matching_memory
= 1;
4745 dst
= gen_reg_rtx (mode
);
4748 /* When source operand is memory, destination must match. */
4749 if (!matching_memory
&& GET_CODE (src
) == MEM
)
4750 src
= force_reg (mode
, src
);
4752 /* If optimizing, copy to regs to improve CSE */
4753 if (optimize
&& ! no_new_pseudos
)
4755 if (GET_CODE (dst
) == MEM
)
4756 dst
= gen_reg_rtx (mode
);
4757 if (GET_CODE (src
) == MEM
)
4758 src
= force_reg (mode
, src
);
4761 /* Emit the instruction. */
4763 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_e (code
, mode
, src
));
4764 if (reload_in_progress
|| code
== NOT
)
4766 /* Reload doesn't know about the flags register, and doesn't know that
4767 it doesn't want to clobber it. */
4774 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
4775 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
4778 /* Fix up the destination if needed. */
4779 if (dst
!= operands
[0])
4780 emit_move_insn (operands
[0], dst
);
4783 /* Return TRUE or FALSE depending on whether the unary operator meets the
4784 appropriate constraints. */
4787 ix86_unary_operator_ok (code
, mode
, operands
)
4788 enum rtx_code code ATTRIBUTE_UNUSED
;
4789 enum machine_mode mode ATTRIBUTE_UNUSED
;
4790 rtx operands
[2] ATTRIBUTE_UNUSED
;
4792 /* If one of operands is memory, source and destination must match. */
4793 if ((GET_CODE (operands
[0]) == MEM
4794 || GET_CODE (operands
[1]) == MEM
)
4795 && ! rtx_equal_p (operands
[0], operands
[1]))
4800 /* Return TRUE or FALSE depending on whether the first SET in INSN
4801 has source and destination with matching CC modes, and that the
4802 CC mode is at least as constrained as REQ_MODE. */
4805 ix86_match_ccmode (insn
, req_mode
)
4807 enum machine_mode req_mode
;
4810 enum machine_mode set_mode
;
4812 set
= PATTERN (insn
);
4813 if (GET_CODE (set
) == PARALLEL
)
4814 set
= XVECEXP (set
, 0, 0);
4815 if (GET_CODE (set
) != SET
)
4817 if (GET_CODE (SET_SRC (set
)) != COMPARE
)
4820 set_mode
= GET_MODE (SET_DEST (set
));
4824 if (req_mode
!= CCNOmode
4825 && (req_mode
!= CCmode
4826 || XEXP (SET_SRC (set
), 1) != const0_rtx
))
4830 if (req_mode
== CCGCmode
)
4834 if (req_mode
== CCGOCmode
|| req_mode
== CCNOmode
)
4838 if (req_mode
== CCZmode
)
4848 return (GET_MODE (SET_SRC (set
)) == set_mode
);
4851 /* Generate insn patterns to do an integer compare of OPERANDS. */
4854 ix86_expand_int_compare (code
, op0
, op1
)
4858 enum machine_mode cmpmode
;
4861 cmpmode
= SELECT_CC_MODE (code
, op0
, op1
);
4862 flags
= gen_rtx_REG (cmpmode
, FLAGS_REG
);
4864 /* This is very simple, but making the interface the same as in the
4865 FP case makes the rest of the code easier. */
4866 tmp
= gen_rtx_COMPARE (cmpmode
, op0
, op1
);
4867 emit_insn (gen_rtx_SET (VOIDmode
, flags
, tmp
));
4869 /* Return the test that should be put into the flags user, i.e.
4870 the bcc, scc, or cmov instruction. */
4871 return gen_rtx_fmt_ee (code
, VOIDmode
, flags
, const0_rtx
);
4874 /* Figure out whether to use ordered or unordered fp comparisons.
4875 Return the appropriate mode to use. */
4878 ix86_fp_compare_mode (code
)
4879 enum rtx_code code ATTRIBUTE_UNUSED
;
4881 /* ??? In order to make all comparisons reversible, we do all comparisons
4882 non-trapping when compiling for IEEE. Once gcc is able to distinguish
4883 all forms trapping and nontrapping comparisons, we can make inequality
4884 comparisons trapping again, since it results in better code when using
4885 FCOM based compares. */
4886 return TARGET_IEEE_FP
? CCFPUmode
: CCFPmode
;
4890 ix86_cc_mode (code
, op0
, op1
)
4894 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
4895 return ix86_fp_compare_mode (code
);
4898 /* Only zero flag is needed. */
4900 case NE
: /* ZF!=0 */
4902 /* Codes needing carry flag. */
4903 case GEU
: /* CF=0 */
4904 case GTU
: /* CF=0 & ZF=0 */
4905 case LTU
: /* CF=1 */
4906 case LEU
: /* CF=1 | ZF=1 */
4908 /* Codes possibly doable only with sign flag when
4909 comparing against zero. */
4910 case GE
: /* SF=OF or SF=0 */
4911 case LT
: /* SF<>OF or SF=1 */
4912 if (op1
== const0_rtx
)
4915 /* For other cases Carry flag is not required. */
4917 /* Codes doable only with sign flag when comparing
4918 against zero, but we miss jump instruction for it
4919 so we need to use relational tests agains overflow
4920 that thus needs to be zero. */
4921 case GT
: /* ZF=0 & SF=OF */
4922 case LE
: /* ZF=1 | SF<>OF */
4923 if (op1
== const0_rtx
)
4932 /* Return true if we should use an FCOMI instruction for this fp comparison. */
4935 ix86_use_fcomi_compare (code
)
4936 enum rtx_code code ATTRIBUTE_UNUSED
;
4938 enum rtx_code swapped_code
= swap_condition (code
);
4939 return ((ix86_fp_comparison_cost (code
) == ix86_fp_comparison_fcomi_cost (code
))
4940 || (ix86_fp_comparison_cost (swapped_code
)
4941 == ix86_fp_comparison_fcomi_cost (swapped_code
)));
4944 /* Swap, force into registers, or otherwise massage the two operands
4945 to a fp comparison. The operands are updated in place; the new
4946 comparsion code is returned. */
4948 static enum rtx_code
4949 ix86_prepare_fp_compare_args (code
, pop0
, pop1
)
4953 enum machine_mode fpcmp_mode
= ix86_fp_compare_mode (code
);
4954 rtx op0
= *pop0
, op1
= *pop1
;
4955 enum machine_mode op_mode
= GET_MODE (op0
);
4956 int is_sse
= SSE_REG_P (op0
) | SSE_REG_P (op1
);
4958 /* All of the unordered compare instructions only work on registers.
4959 The same is true of the XFmode compare instructions. The same is
4960 true of the fcomi compare instructions. */
4963 && (fpcmp_mode
== CCFPUmode
4964 || op_mode
== XFmode
4965 || op_mode
== TFmode
4966 || ix86_use_fcomi_compare (code
)))
4968 op0
= force_reg (op_mode
, op0
);
4969 op1
= force_reg (op_mode
, op1
);
4973 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
4974 things around if they appear profitable, otherwise force op0
4977 if (standard_80387_constant_p (op0
) == 0
4978 || (GET_CODE (op0
) == MEM
4979 && ! (standard_80387_constant_p (op1
) == 0
4980 || GET_CODE (op1
) == MEM
)))
4983 tmp
= op0
, op0
= op1
, op1
= tmp
;
4984 code
= swap_condition (code
);
4987 if (GET_CODE (op0
) != REG
)
4988 op0
= force_reg (op_mode
, op0
);
4990 if (CONSTANT_P (op1
))
4992 if (standard_80387_constant_p (op1
))
4993 op1
= force_reg (op_mode
, op1
);
4995 op1
= validize_mem (force_const_mem (op_mode
, op1
));
4999 /* Try to rearrange the comparison to make it cheaper. */
5000 if (ix86_fp_comparison_cost (code
)
5001 > ix86_fp_comparison_cost (swap_condition (code
))
5002 && (GET_CODE (op0
) == REG
|| !reload_completed
))
5005 tmp
= op0
, op0
= op1
, op1
= tmp
;
5006 code
= swap_condition (code
);
5007 if (GET_CODE (op0
) != REG
)
5008 op0
= force_reg (op_mode
, op0
);
5016 /* Convert comparison codes we use to represent FP comparison to integer
5017 code that will result in proper branch. Return UNKNOWN if no such code
5019 static enum rtx_code
5020 ix86_fp_compare_code_to_integer (code
)
5050 /* Split comparison code CODE into comparisons we can do using branch
5051 instructions. BYPASS_CODE is comparison code for branch that will
5052 branch around FIRST_CODE and SECOND_CODE. If some of branches
5053 is not required, set value to NIL.
5054 We never require more than two branches. */
5056 ix86_fp_comparison_codes (code
, bypass_code
, first_code
, second_code
)
5057 enum rtx_code code
, *bypass_code
, *first_code
, *second_code
;
5063 /* The fcomi comparison sets flags as follows:
5073 case GT
: /* GTU - CF=0 & ZF=0 */
5074 case GE
: /* GEU - CF=0 */
5075 case ORDERED
: /* PF=0 */
5076 case UNORDERED
: /* PF=1 */
5077 case UNEQ
: /* EQ - ZF=1 */
5078 case UNLT
: /* LTU - CF=1 */
5079 case UNLE
: /* LEU - CF=1 | ZF=1 */
5080 case LTGT
: /* EQ - ZF=0 */
5082 case LT
: /* LTU - CF=1 - fails on unordered */
5084 *bypass_code
= UNORDERED
;
5086 case LE
: /* LEU - CF=1 | ZF=1 - fails on unordered */
5088 *bypass_code
= UNORDERED
;
5090 case EQ
: /* EQ - ZF=1 - fails on unordered */
5092 *bypass_code
= UNORDERED
;
5094 case NE
: /* NE - ZF=0 - fails on unordered */
5096 *second_code
= UNORDERED
;
5098 case UNGE
: /* GEU - CF=0 - fails on unordered */
5100 *second_code
= UNORDERED
;
5102 case UNGT
: /* GTU - CF=0 & ZF=0 - fails on unordered */
5104 *second_code
= UNORDERED
;
5109 if (!TARGET_IEEE_FP
)
5116 /* Return cost of comparison done fcom + arithmetics operations on AX.
5117 All following functions do use number of instructions as an cost metrics.
5118 In future this should be tweaked to compute bytes for optimize_size and
5119 take into account performance of various instructions on various CPUs. */
5121 ix86_fp_comparison_arithmetics_cost (code
)
5124 if (!TARGET_IEEE_FP
)
5126 /* The cost of code output by ix86_expand_fp_compare. */
5154 /* Return cost of comparison done using fcomi operation.
5155 See ix86_fp_comparison_arithmetics_cost for the metrics. */
5157 ix86_fp_comparison_fcomi_cost (code
)
5160 enum rtx_code bypass_code
, first_code
, second_code
;
5161 /* Return arbitarily high cost when instruction is not supported - this
5162 prevents gcc from using it. */
5165 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
5166 return (bypass_code
!= NIL
|| second_code
!= NIL
) + 2;
5169 /* Return cost of comparison done using sahf operation.
5170 See ix86_fp_comparison_arithmetics_cost for the metrics. */
5172 ix86_fp_comparison_sahf_cost (code
)
5175 enum rtx_code bypass_code
, first_code
, second_code
;
5176 /* Return arbitarily high cost when instruction is not preferred - this
5177 avoids gcc from using it. */
5178 if (!TARGET_USE_SAHF
&& !optimize_size
)
5180 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
5181 return (bypass_code
!= NIL
|| second_code
!= NIL
) + 3;
5184 /* Compute cost of the comparison done using any method.
5185 See ix86_fp_comparison_arithmetics_cost for the metrics. */
5187 ix86_fp_comparison_cost (code
)
5190 int fcomi_cost
, sahf_cost
, arithmetics_cost
= 1024;
5193 fcomi_cost
= ix86_fp_comparison_fcomi_cost (code
);
5194 sahf_cost
= ix86_fp_comparison_sahf_cost (code
);
5196 min
= arithmetics_cost
= ix86_fp_comparison_arithmetics_cost (code
);
5197 if (min
> sahf_cost
)
5199 if (min
> fcomi_cost
)
5204 /* Generate insn patterns to do a floating point compare of OPERANDS. */
5207 ix86_expand_fp_compare (code
, op0
, op1
, scratch
, second_test
, bypass_test
)
5209 rtx op0
, op1
, scratch
;
5213 enum machine_mode fpcmp_mode
, intcmp_mode
;
5215 int cost
= ix86_fp_comparison_cost (code
);
5216 enum rtx_code bypass_code
, first_code
, second_code
;
5218 fpcmp_mode
= ix86_fp_compare_mode (code
);
5219 code
= ix86_prepare_fp_compare_args (code
, &op0
, &op1
);
5222 *second_test
= NULL_RTX
;
5224 *bypass_test
= NULL_RTX
;
5226 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
5228 /* Do fcomi/sahf based test when profitable. */
5229 if ((bypass_code
== NIL
|| bypass_test
)
5230 && (second_code
== NIL
|| second_test
)
5231 && ix86_fp_comparison_arithmetics_cost (code
) > cost
)
5235 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
5236 tmp
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (fpcmp_mode
, FLAGS_REG
),
5242 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
5243 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), 9);
5245 scratch
= gen_reg_rtx (HImode
);
5246 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
5247 emit_insn (gen_x86_sahf_1 (scratch
));
5250 /* The FP codes work out to act like unsigned. */
5251 intcmp_mode
= fpcmp_mode
;
5253 if (bypass_code
!= NIL
)
5254 *bypass_test
= gen_rtx_fmt_ee (bypass_code
, VOIDmode
,
5255 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
5257 if (second_code
!= NIL
)
5258 *second_test
= gen_rtx_fmt_ee (second_code
, VOIDmode
,
5259 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
5264 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
5265 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
5266 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), 9);
5268 scratch
= gen_reg_rtx (HImode
);
5269 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
5271 /* In the unordered case, we have to check C2 for NaN's, which
5272 doesn't happen to work out to anything nice combination-wise.
5273 So do some bit twiddling on the value we've got in AH to come
5274 up with an appropriate set of condition codes. */
5276 intcmp_mode
= CCNOmode
;
5281 if (code
== GT
|| !TARGET_IEEE_FP
)
5283 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
5288 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
5289 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
5290 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x44)));
5291 intcmp_mode
= CCmode
;
5297 if (code
== LT
&& TARGET_IEEE_FP
)
5299 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
5300 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x01)));
5301 intcmp_mode
= CCmode
;
5306 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x01)));
5312 if (code
== GE
|| !TARGET_IEEE_FP
)
5314 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x05)));
5319 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
5320 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
5327 if (code
== LE
&& TARGET_IEEE_FP
)
5329 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
5330 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
5331 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
5332 intcmp_mode
= CCmode
;
5337 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
5343 if (code
== EQ
&& TARGET_IEEE_FP
)
5345 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
5346 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
5347 intcmp_mode
= CCmode
;
5352 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
5359 if (code
== NE
&& TARGET_IEEE_FP
)
5361 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
5362 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
5368 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
5374 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
5378 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
5387 /* Return the test that should be put into the flags user, i.e.
5388 the bcc, scc, or cmov instruction. */
5389 return gen_rtx_fmt_ee (code
, VOIDmode
,
5390 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
5395 ix86_expand_compare (code
, second_test
, bypass_test
)
5397 rtx
*second_test
, *bypass_test
;
5400 op0
= ix86_compare_op0
;
5401 op1
= ix86_compare_op1
;
5404 *second_test
= NULL_RTX
;
5406 *bypass_test
= NULL_RTX
;
5408 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
5409 ret
= ix86_expand_fp_compare (code
, op0
, op1
, NULL_RTX
,
5410 second_test
, bypass_test
);
5412 ret
= ix86_expand_int_compare (code
, op0
, op1
);
5418 ix86_expand_branch (code
, label
)
5424 switch (GET_MODE (ix86_compare_op0
))
5429 tmp
= ix86_expand_compare (code
, NULL
, NULL
);
5430 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5431 gen_rtx_LABEL_REF (VOIDmode
, label
),
5433 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
5440 /* Don't expand the comparison early, so that we get better code
5441 when jump or whoever decides to reverse the comparison. */
5446 code
= ix86_prepare_fp_compare_args (code
, &ix86_compare_op0
,
5449 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
,
5450 ix86_compare_op0
, ix86_compare_op1
);
5451 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
5452 gen_rtx_LABEL_REF (VOIDmode
, label
),
5454 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
5456 use_fcomi
= ix86_use_fcomi_compare (code
);
5457 vec
= rtvec_alloc (3 + !use_fcomi
);
5458 RTVEC_ELT (vec
, 0) = tmp
;
5460 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
5462 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
5465 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
5467 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
5472 /* Expand DImode branch into multiple compare+branch. */
5474 rtx lo
[2], hi
[2], label2
;
5475 enum rtx_code code1
, code2
, code3
;
5477 if (CONSTANT_P (ix86_compare_op0
) && ! CONSTANT_P (ix86_compare_op1
))
5479 tmp
= ix86_compare_op0
;
5480 ix86_compare_op0
= ix86_compare_op1
;
5481 ix86_compare_op1
= tmp
;
5482 code
= swap_condition (code
);
5484 split_di (&ix86_compare_op0
, 1, lo
+0, hi
+0);
5485 split_di (&ix86_compare_op1
, 1, lo
+1, hi
+1);
5487 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
5488 avoid two branches. This costs one extra insn, so disable when
5489 optimizing for size. */
5491 if ((code
== EQ
|| code
== NE
)
5493 || hi
[1] == const0_rtx
|| lo
[1] == const0_rtx
))
5498 if (hi
[1] != const0_rtx
)
5499 xor1
= expand_binop (SImode
, xor_optab
, xor1
, hi
[1],
5500 NULL_RTX
, 0, OPTAB_WIDEN
);
5503 if (lo
[1] != const0_rtx
)
5504 xor0
= expand_binop (SImode
, xor_optab
, xor0
, lo
[1],
5505 NULL_RTX
, 0, OPTAB_WIDEN
);
5507 tmp
= expand_binop (SImode
, ior_optab
, xor1
, xor0
,
5508 NULL_RTX
, 0, OPTAB_WIDEN
);
5510 ix86_compare_op0
= tmp
;
5511 ix86_compare_op1
= const0_rtx
;
5512 ix86_expand_branch (code
, label
);
5516 /* Otherwise, if we are doing less-than or greater-or-equal-than,
5517 op1 is a constant and the low word is zero, then we can just
5518 examine the high word. */
5520 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
)
5523 case LT
: case LTU
: case GE
: case GEU
:
5524 ix86_compare_op0
= hi
[0];
5525 ix86_compare_op1
= hi
[1];
5526 ix86_expand_branch (code
, label
);
5532 /* Otherwise, we need two or three jumps. */
5534 label2
= gen_label_rtx ();
5537 code2
= swap_condition (code
);
5538 code3
= unsigned_condition (code
);
5542 case LT
: case GT
: case LTU
: case GTU
:
5545 case LE
: code1
= LT
; code2
= GT
; break;
5546 case GE
: code1
= GT
; code2
= LT
; break;
5547 case LEU
: code1
= LTU
; code2
= GTU
; break;
5548 case GEU
: code1
= GTU
; code2
= LTU
; break;
5550 case EQ
: code1
= NIL
; code2
= NE
; break;
5551 case NE
: code2
= NIL
; break;
5559 * if (hi(a) < hi(b)) goto true;
5560 * if (hi(a) > hi(b)) goto false;
5561 * if (lo(a) < lo(b)) goto true;
5565 ix86_compare_op0
= hi
[0];
5566 ix86_compare_op1
= hi
[1];
5569 ix86_expand_branch (code1
, label
);
5571 ix86_expand_branch (code2
, label2
);
5573 ix86_compare_op0
= lo
[0];
5574 ix86_compare_op1
= lo
[1];
5575 ix86_expand_branch (code3
, label
);
5578 emit_label (label2
);
5587 /* Split branch based on floating point condition. */
5589 ix86_split_fp_branch (condition
, op1
, op2
, target1
, target2
, tmp
)
5590 rtx condition
, op1
, op2
, target1
, target2
, tmp
;
5593 rtx label
= NULL_RTX
;
5594 enum rtx_code code
= GET_CODE (condition
);
5596 if (target2
!= pc_rtx
)
5599 code
= reverse_condition_maybe_unordered (code
);
5604 condition
= ix86_expand_fp_compare (code
, op1
, op2
,
5605 tmp
, &second
, &bypass
);
5606 if (bypass
!= NULL_RTX
)
5608 label
= gen_label_rtx ();
5609 emit_jump_insn (gen_rtx_SET
5611 gen_rtx_IF_THEN_ELSE (VOIDmode
,
5613 gen_rtx_LABEL_REF (VOIDmode
,
5617 /* AMD Athlon and probably other CPUs too have fast bypass path between the
5618 comparison and first branch. The second branch takes longer to execute
5619 so place first branch the worse predicable one if possible. */
5620 if (second
!= NULL_RTX
5621 && (GET_CODE (second
) == UNORDERED
|| GET_CODE (second
) == ORDERED
))
5623 rtx tmp
= condition
;
5627 emit_jump_insn (gen_rtx_SET
5629 gen_rtx_IF_THEN_ELSE (VOIDmode
,
5630 condition
, target1
, target2
)));
5631 if (second
!= NULL_RTX
)
5632 emit_jump_insn (gen_rtx_SET
5634 gen_rtx_IF_THEN_ELSE (VOIDmode
, second
, target1
, target2
)));
5635 if (label
!= NULL_RTX
)
5640 ix86_expand_setcc (code
, dest
)
5644 rtx ret
, tmp
, tmpreg
;
5645 rtx second_test
, bypass_test
;
5648 if (GET_MODE (ix86_compare_op0
) == DImode
)
5649 return 0; /* FAIL */
5651 /* Three modes of generation:
5652 0 -- destination does not overlap compare sources:
5653 clear dest first, emit strict_low_part setcc.
5654 1 -- destination does overlap compare sources:
5655 emit subreg setcc, zero extend.
5656 2 -- destination is in QImode:
5662 if (GET_MODE (dest
) == QImode
)
5664 else if (reg_overlap_mentioned_p (dest
, ix86_compare_op0
)
5665 || reg_overlap_mentioned_p (dest
, ix86_compare_op1
))
5669 emit_move_insn (dest
, const0_rtx
);
5671 ret
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
5672 PUT_MODE (ret
, QImode
);
5678 tmp
= gen_lowpart (QImode
, dest
);
5680 tmp
= gen_rtx_STRICT_LOW_PART (VOIDmode
, tmp
);
5684 if (!cse_not_expected
)
5685 tmp
= gen_reg_rtx (QImode
);
5687 tmp
= gen_lowpart (QImode
, dest
);
5691 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, ret
));
5692 if (bypass_test
|| second_test
)
5694 rtx test
= second_test
;
5696 rtx tmp2
= gen_reg_rtx (QImode
);
5703 PUT_CODE (test
, reverse_condition_maybe_unordered (GET_CODE (test
)));
5705 PUT_MODE (test
, QImode
);
5706 emit_insn (gen_rtx_SET (VOIDmode
, tmp2
, test
));
5709 emit_insn (gen_andqi3 (tmp
, tmpreg
, tmp2
));
5711 emit_insn (gen_iorqi3 (tmp
, tmpreg
, tmp2
));
5718 tmp
= gen_rtx_ZERO_EXTEND (GET_MODE (dest
), tmp
);
5719 tmp
= gen_rtx_SET (VOIDmode
, dest
, tmp
);
5720 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
5721 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
5725 return 1; /* DONE */
5729 ix86_expand_int_movcc (operands
)
5732 enum rtx_code code
= GET_CODE (operands
[1]), compare_code
;
5733 rtx compare_seq
, compare_op
;
5734 rtx second_test
, bypass_test
;
5736 /* When the compare code is not LTU or GEU, we can not use sbbl case.
5737 In case comparsion is done with immediate, we can convert it to LTU or
5738 GEU by altering the integer. */
5740 if ((code
== LEU
|| code
== GTU
)
5741 && GET_CODE (ix86_compare_op1
) == CONST_INT
5742 && GET_MODE (operands
[0]) != HImode
5743 && (unsigned int)INTVAL (ix86_compare_op1
) != 0xffffffff
5744 && GET_CODE (operands
[2]) == CONST_INT
5745 && GET_CODE (operands
[3]) == CONST_INT
)
5751 ix86_compare_op1
= GEN_INT (INTVAL (ix86_compare_op1
) + 1);
5755 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
5756 compare_seq
= gen_sequence ();
5759 compare_code
= GET_CODE (compare_op
);
5761 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
5762 HImode insns, we'd be swallowed in word prefix ops. */
5764 if (GET_MODE (operands
[0]) != HImode
5765 && GET_CODE (operands
[2]) == CONST_INT
5766 && GET_CODE (operands
[3]) == CONST_INT
)
5768 rtx out
= operands
[0];
5769 HOST_WIDE_INT ct
= INTVAL (operands
[2]);
5770 HOST_WIDE_INT cf
= INTVAL (operands
[3]);
5773 if ((compare_code
== LTU
|| compare_code
== GEU
)
5774 && !second_test
&& !bypass_test
)
5777 /* Detect overlap between destination and compare sources. */
5780 /* To simplify rest of code, restrict to the GEU case. */
5781 if (compare_code
== LTU
)
5786 compare_code
= reverse_condition (compare_code
);
5787 code
= reverse_condition (code
);
5791 if (reg_overlap_mentioned_p (out
, ix86_compare_op0
)
5792 || reg_overlap_mentioned_p (out
, ix86_compare_op1
))
5793 tmp
= gen_reg_rtx (SImode
);
5795 emit_insn (compare_seq
);
5796 emit_insn (gen_x86_movsicc_0_m1 (tmp
));
5808 emit_insn (gen_addsi3 (out
, out
, GEN_INT (ct
)));
5819 emit_insn (gen_iorsi3 (out
, out
, GEN_INT (ct
)));
5821 else if (diff
== -1 && ct
)
5831 emit_insn (gen_one_cmplsi2 (tmp
, tmp
));
5833 emit_insn (gen_addsi3 (out
, out
, GEN_INT (cf
)));
5840 * andl cf - ct, dest
5845 emit_insn (gen_andsi3 (out
, out
, GEN_INT (cf
- ct
)));
5847 emit_insn (gen_addsi3 (out
, out
, GEN_INT (ct
)));
5851 emit_move_insn (out
, tmp
);
5853 return 1; /* DONE */
5860 tmp
= ct
, ct
= cf
, cf
= tmp
;
5862 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
5864 /* We may be reversing unordered compare to normal compare, that
5865 is not valid in general (we may convert non-trapping condition
5866 to trapping one), however on i386 we currently emit all
5867 comparisons unordered. */
5868 compare_code
= reverse_condition_maybe_unordered (compare_code
);
5869 code
= reverse_condition_maybe_unordered (code
);
5873 compare_code
= reverse_condition (compare_code
);
5874 code
= reverse_condition (code
);
5877 if (diff
== 1 || diff
== 2 || diff
== 4 || diff
== 8
5878 || diff
== 3 || diff
== 5 || diff
== 9)
5884 * lea cf(dest*(ct-cf)),dest
5888 * This also catches the degenerate setcc-only case.
5894 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
5895 ix86_compare_op1
, VOIDmode
, 0, 1);
5902 tmp
= gen_rtx_MULT (SImode
, out
, GEN_INT (diff
& ~1));
5906 tmp
= gen_rtx_PLUS (SImode
, tmp
, out
);
5912 tmp
= gen_rtx_PLUS (SImode
, tmp
, GEN_INT (cf
));
5918 emit_move_insn (out
, tmp
);
5923 clob
= gen_rtx_REG (CCmode
, FLAGS_REG
);
5924 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
5926 tmp
= gen_rtx_SET (VOIDmode
, out
, tmp
);
5927 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
5931 emit_insn (gen_rtx_SET (VOIDmode
, out
, tmp
));
5933 if (out
!= operands
[0])
5934 emit_move_insn (operands
[0], out
);
5936 return 1; /* DONE */
5940 * General case: Jumpful:
5941 * xorl dest,dest cmpl op1, op2
5942 * cmpl op1, op2 movl ct, dest
5944 * decl dest movl cf, dest
5945 * andl (cf-ct),dest 1:
5950 * This is reasonably steep, but branch mispredict costs are
5951 * high on modern cpus, so consider failing only if optimizing
5954 * %%% Parameterize branch_cost on the tuning architecture, then
5955 * use that. The 80386 couldn't care less about mispredicts.
5958 if (!optimize_size
&& !TARGET_CMOVE
)
5964 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
5966 /* We may be reversing unordered compare to normal compare,
5967 that is not valid in general (we may convert non-trapping
5968 condition to trapping one), however on i386 we currently
5969 emit all comparisons unordered. */
5970 compare_code
= reverse_condition_maybe_unordered (compare_code
);
5971 code
= reverse_condition_maybe_unordered (code
);
5975 compare_code
= reverse_condition (compare_code
);
5976 code
= reverse_condition (code
);
5980 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
5981 ix86_compare_op1
, VOIDmode
, 0, 1);
5983 emit_insn (gen_addsi3 (out
, out
, constm1_rtx
));
5984 emit_insn (gen_andsi3 (out
, out
, GEN_INT (cf
-ct
)));
5986 emit_insn (gen_addsi3 (out
, out
, GEN_INT (ct
)));
5987 if (out
!= operands
[0])
5988 emit_move_insn (operands
[0], out
);
5990 return 1; /* DONE */
5996 /* Try a few things more with specific constants and a variable. */
5999 rtx var
, orig_out
, out
, tmp
;
6002 return 0; /* FAIL */
6004 /* If one of the two operands is an interesting constant, load a
6005 constant with the above and mask it in with a logical operation. */
6007 if (GET_CODE (operands
[2]) == CONST_INT
)
6010 if (INTVAL (operands
[2]) == 0)
6011 operands
[3] = constm1_rtx
, op
= and_optab
;
6012 else if (INTVAL (operands
[2]) == -1)
6013 operands
[3] = const0_rtx
, op
= ior_optab
;
6015 return 0; /* FAIL */
6017 else if (GET_CODE (operands
[3]) == CONST_INT
)
6020 if (INTVAL (operands
[3]) == 0)
6021 operands
[2] = constm1_rtx
, op
= and_optab
;
6022 else if (INTVAL (operands
[3]) == -1)
6023 operands
[2] = const0_rtx
, op
= ior_optab
;
6025 return 0; /* FAIL */
6028 return 0; /* FAIL */
6030 orig_out
= operands
[0];
6031 tmp
= gen_reg_rtx (GET_MODE (orig_out
));
6034 /* Recurse to get the constant loaded. */
6035 if (ix86_expand_int_movcc (operands
) == 0)
6036 return 0; /* FAIL */
6038 /* Mask in the interesting variable. */
6039 out
= expand_binop (GET_MODE (orig_out
), op
, var
, tmp
, orig_out
, 0,
6041 if (out
!= orig_out
)
6042 emit_move_insn (orig_out
, out
);
6044 return 1; /* DONE */
6048 * For comparison with above,
6058 if (! nonimmediate_operand (operands
[2], GET_MODE (operands
[0])))
6059 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
6060 if (! nonimmediate_operand (operands
[3], GET_MODE (operands
[0])))
6061 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
6063 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
6065 rtx tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
6066 emit_move_insn (tmp
, operands
[3]);
6069 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
6071 rtx tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
6072 emit_move_insn (tmp
, operands
[2]);
6076 emit_insn (compare_seq
);
6077 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
6078 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
6079 compare_op
, operands
[2],
6082 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
6083 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
6088 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
6089 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
6094 return 1; /* DONE */
6098 ix86_expand_fp_movcc (operands
)
6103 rtx compare_op
, second_test
, bypass_test
;
6105 /* For SF/DFmode conditional moves based on comparisons
6106 in same mode, we may want to use SSE min/max instructions. */
6107 if (((TARGET_SSE
&& GET_MODE (operands
[0]) == SFmode
)
6108 || (TARGET_SSE2
&& GET_MODE (operands
[0]) == DFmode
))
6109 && GET_MODE (ix86_compare_op0
) == GET_MODE (operands
[0])
6110 /* We may be called from the post-reload splitter. */
6111 && (!REG_P (operands
[0])
6112 || SSE_REG_P (operands
[0])
6113 || REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
6115 rtx op0
= ix86_compare_op0
, op1
= ix86_compare_op1
;
6116 code
= GET_CODE (operands
[1]);
6118 /* See if we have (cross) match between comparison operands and
6119 conditional move operands. */
6120 if (rtx_equal_p (operands
[2], op1
))
6125 code
= reverse_condition_maybe_unordered (code
);
6127 if (rtx_equal_p (operands
[2], op0
) && rtx_equal_p (operands
[3], op1
))
6129 /* Check for min operation. */
6132 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
6133 if (memory_operand (op0
, VOIDmode
))
6134 op0
= force_reg (GET_MODE (operands
[0]), op0
);
6135 if (GET_MODE (operands
[0]) == SFmode
)
6136 emit_insn (gen_minsf3 (operands
[0], op0
, op1
));
6138 emit_insn (gen_mindf3 (operands
[0], op0
, op1
));
6141 /* Check for max operation. */
6144 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
6145 if (memory_operand (op0
, VOIDmode
))
6146 op0
= force_reg (GET_MODE (operands
[0]), op0
);
6147 if (GET_MODE (operands
[0]) == SFmode
)
6148 emit_insn (gen_maxsf3 (operands
[0], op0
, op1
));
6150 emit_insn (gen_maxdf3 (operands
[0], op0
, op1
));
6154 /* Manage condition to be sse_comparison_operator. In case we are
6155 in non-ieee mode, try to canonicalize the destination operand
6156 to be first in the comparison - this helps reload to avoid extra
6158 if (!sse_comparison_operator (operands
[1], VOIDmode
)
6159 || (rtx_equal_p (operands
[0], ix86_compare_op1
) && !TARGET_IEEE_FP
))
6161 rtx tmp
= ix86_compare_op0
;
6162 ix86_compare_op0
= ix86_compare_op1
;
6163 ix86_compare_op1
= tmp
;
6164 operands
[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands
[1])),
6165 VOIDmode
, ix86_compare_op0
,
6168 /* Similary try to manage result to be first operand of conditional
6170 if (rtx_equal_p (operands
[0], operands
[3]))
6172 rtx tmp
= operands
[2];
6173 operands
[2] = operands
[3];
6175 operands
[1] = gen_rtx_fmt_ee (reverse_condition_maybe_unordered
6176 (GET_CODE (operands
[1])),
6177 VOIDmode
, ix86_compare_op0
,
6180 if (GET_MODE (operands
[0]) == SFmode
)
6181 emit_insn (gen_sse_movsfcc (operands
[0], operands
[1],
6182 operands
[2], operands
[3],
6183 ix86_compare_op0
, ix86_compare_op1
));
6185 emit_insn (gen_sse_movdfcc (operands
[0], operands
[1],
6186 operands
[2], operands
[3],
6187 ix86_compare_op0
, ix86_compare_op1
));
6191 /* The floating point conditional move instructions don't directly
6192 support conditions resulting from a signed integer comparison. */
6194 code
= GET_CODE (operands
[1]);
6195 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
6197 /* The floating point conditional move instructions don't directly
6198 support signed integer comparisons. */
6200 if (!fcmov_comparison_operator (compare_op
, VOIDmode
))
6202 if (second_test
!= NULL
|| bypass_test
!= NULL
)
6204 tmp
= gen_reg_rtx (QImode
);
6205 ix86_expand_setcc (code
, tmp
);
6207 ix86_compare_op0
= tmp
;
6208 ix86_compare_op1
= const0_rtx
;
6209 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
6211 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
6213 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
6214 emit_move_insn (tmp
, operands
[3]);
6217 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
6219 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
6220 emit_move_insn (tmp
, operands
[2]);
6224 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
6225 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
6230 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
6231 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
6236 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
6237 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
6245 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
6246 works for floating pointer parameters and nonoffsetable memories.
6247 For pushes, it returns just stack offsets; the values will be saved
6248 in the right order. Maximally three parts are generated. */
6251 ix86_split_to_parts (operand
, parts
, mode
)
6254 enum machine_mode mode
;
6256 int size
= mode
== TFmode
? 3 : GET_MODE_SIZE (mode
) / 4;
6258 if (GET_CODE (operand
) == REG
&& MMX_REGNO_P (REGNO (operand
)))
6260 if (size
< 2 || size
> 3)
6263 /* Optimize constant pool reference to immediates. This is used by fp moves,
6264 that force all constants to memory to allow combining. */
6266 if (GET_CODE (operand
) == MEM
6267 && GET_CODE (XEXP (operand
, 0)) == SYMBOL_REF
6268 && CONSTANT_POOL_ADDRESS_P (XEXP (operand
, 0)))
6269 operand
= get_pool_constant (XEXP (operand
, 0));
6271 if (GET_CODE (operand
) == MEM
&& !offsettable_memref_p (operand
))
6273 /* The only non-offsetable memories we handle are pushes. */
6274 if (! push_operand (operand
, VOIDmode
))
6277 PUT_MODE (operand
, SImode
);
6278 parts
[0] = parts
[1] = parts
[2] = operand
;
6283 split_di (&operand
, 1, &parts
[0], &parts
[1]);
6286 if (REG_P (operand
))
6288 if (!reload_completed
)
6290 parts
[0] = gen_rtx_REG (SImode
, REGNO (operand
) + 0);
6291 parts
[1] = gen_rtx_REG (SImode
, REGNO (operand
) + 1);
6293 parts
[2] = gen_rtx_REG (SImode
, REGNO (operand
) + 2);
6295 else if (offsettable_memref_p (operand
))
6297 PUT_MODE (operand
, SImode
);
6299 parts
[1] = adj_offsettable_operand (operand
, 4);
6301 parts
[2] = adj_offsettable_operand (operand
, 8);
6303 else if (GET_CODE (operand
) == CONST_DOUBLE
)
6308 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
6313 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
6314 parts
[2] = GEN_INT (l
[2]);
6317 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
6322 parts
[1] = GEN_INT (l
[1]);
6323 parts
[0] = GEN_INT (l
[0]);
6333 /* Emit insns to perform a move or push of DI, DF, and XF values.
6334 Return false when normal moves are needed; true when all required
6335 insns have been emitted. Operands 2-4 contain the input values
6336 int the correct order; operands 5-7 contain the output values. */
6339 ix86_split_long_move (operands1
)
6348 /* Make our own copy to avoid clobbering the operands. */
6349 operands
[0] = copy_rtx (operands1
[0]);
6350 operands
[1] = copy_rtx (operands1
[1]);
6352 /* The only non-offsettable memory we handle is push. */
6353 if (push_operand (operands
[0], VOIDmode
))
6355 else if (GET_CODE (operands
[0]) == MEM
6356 && ! offsettable_memref_p (operands
[0]))
6359 size
= ix86_split_to_parts (operands
[0], part
[0], GET_MODE (operands1
[0]));
6360 ix86_split_to_parts (operands
[1], part
[1], GET_MODE (operands1
[0]));
6362 /* When emitting push, take care for source operands on the stack. */
6363 if (push
&& GET_CODE (operands
[1]) == MEM
6364 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
6367 part
[1][1] = part
[1][2];
6368 part
[1][0] = part
[1][1];
6371 /* We need to do copy in the right order in case an address register
6372 of the source overlaps the destination. */
6373 if (REG_P (part
[0][0]) && GET_CODE (part
[1][0]) == MEM
)
6375 if (reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0)))
6377 if (reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
6380 && reg_overlap_mentioned_p (part
[0][2], XEXP (part
[1][0], 0)))
6383 /* Collision in the middle part can be handled by reordering. */
6384 if (collisions
== 1 && size
== 3
6385 && reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
6388 tmp
= part
[0][1]; part
[0][1] = part
[0][2]; part
[0][2] = tmp
;
6389 tmp
= part
[1][1]; part
[1][1] = part
[1][2]; part
[1][2] = tmp
;
6392 /* If there are more collisions, we can't handle it by reordering.
6393 Do an lea to the last part and use only one colliding move. */
6394 else if (collisions
> 1)
6397 emit_insn (gen_rtx_SET (VOIDmode
, part
[0][size
- 1],
6398 XEXP (part
[1][0], 0)));
6399 part
[1][0] = change_address (part
[1][0], SImode
, part
[0][size
- 1]);
6400 part
[1][1] = adj_offsettable_operand (part
[1][0], 4);
6402 part
[1][2] = adj_offsettable_operand (part
[1][0], 8);
6410 /* We use only first 12 bytes of TFmode value, but for pushing we
6411 are required to adjust stack as if we were pushing real 16byte
6413 if (GET_MODE (operands1
[0]) == TFmode
)
6414 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
6416 emit_insn (gen_push (part
[1][2]));
6418 emit_insn (gen_push (part
[1][1]));
6419 emit_insn (gen_push (part
[1][0]));
6423 /* Choose correct order to not overwrite the source before it is copied. */
6424 if ((REG_P (part
[0][0])
6425 && REG_P (part
[1][1])
6426 && (REGNO (part
[0][0]) == REGNO (part
[1][1])
6428 && REGNO (part
[0][0]) == REGNO (part
[1][2]))))
6430 && reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0))))
6434 operands1
[2] = part
[0][2];
6435 operands1
[3] = part
[0][1];
6436 operands1
[4] = part
[0][0];
6437 operands1
[5] = part
[1][2];
6438 operands1
[6] = part
[1][1];
6439 operands1
[7] = part
[1][0];
6443 operands1
[2] = part
[0][1];
6444 operands1
[3] = part
[0][0];
6445 operands1
[5] = part
[1][1];
6446 operands1
[6] = part
[1][0];
6453 operands1
[2] = part
[0][0];
6454 operands1
[3] = part
[0][1];
6455 operands1
[4] = part
[0][2];
6456 operands1
[5] = part
[1][0];
6457 operands1
[6] = part
[1][1];
6458 operands1
[7] = part
[1][2];
6462 operands1
[2] = part
[0][0];
6463 operands1
[3] = part
[0][1];
6464 operands1
[5] = part
[1][0];
6465 operands1
[6] = part
[1][1];
6473 ix86_split_ashldi (operands
, scratch
)
6474 rtx
*operands
, scratch
;
6476 rtx low
[2], high
[2];
6479 if (GET_CODE (operands
[2]) == CONST_INT
)
6481 split_di (operands
, 2, low
, high
);
6482 count
= INTVAL (operands
[2]) & 63;
6486 emit_move_insn (high
[0], low
[1]);
6487 emit_move_insn (low
[0], const0_rtx
);
6490 emit_insn (gen_ashlsi3 (high
[0], high
[0], GEN_INT (count
- 32)));
6494 if (!rtx_equal_p (operands
[0], operands
[1]))
6495 emit_move_insn (operands
[0], operands
[1]);
6496 emit_insn (gen_x86_shld_1 (high
[0], low
[0], GEN_INT (count
)));
6497 emit_insn (gen_ashlsi3 (low
[0], low
[0], GEN_INT (count
)));
6502 if (!rtx_equal_p (operands
[0], operands
[1]))
6503 emit_move_insn (operands
[0], operands
[1]);
6505 split_di (operands
, 1, low
, high
);
6507 emit_insn (gen_x86_shld_1 (high
[0], low
[0], operands
[2]));
6508 emit_insn (gen_ashlsi3 (low
[0], low
[0], operands
[2]));
6510 if (TARGET_CMOVE
&& (! no_new_pseudos
|| scratch
))
6512 if (! no_new_pseudos
)
6513 scratch
= force_reg (SImode
, const0_rtx
);
6515 emit_move_insn (scratch
, const0_rtx
);
6517 emit_insn (gen_x86_shift_adj_1 (high
[0], low
[0], operands
[2],
6521 emit_insn (gen_x86_shift_adj_2 (high
[0], low
[0], operands
[2]));
6526 ix86_split_ashrdi (operands
, scratch
)
6527 rtx
*operands
, scratch
;
6529 rtx low
[2], high
[2];
6532 if (GET_CODE (operands
[2]) == CONST_INT
)
6534 split_di (operands
, 2, low
, high
);
6535 count
= INTVAL (operands
[2]) & 63;
6539 emit_move_insn (low
[0], high
[1]);
6541 if (! reload_completed
)
6542 emit_insn (gen_ashrsi3 (high
[0], low
[0], GEN_INT (31)));
6545 emit_move_insn (high
[0], low
[0]);
6546 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (31)));
6550 emit_insn (gen_ashrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
6554 if (!rtx_equal_p (operands
[0], operands
[1]))
6555 emit_move_insn (operands
[0], operands
[1]);
6556 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
6557 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (count
)));
6562 if (!rtx_equal_p (operands
[0], operands
[1]))
6563 emit_move_insn (operands
[0], operands
[1]);
6565 split_di (operands
, 1, low
, high
);
6567 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
6568 emit_insn (gen_ashrsi3 (high
[0], high
[0], operands
[2]));
6570 if (TARGET_CMOVE
&& (! no_new_pseudos
|| scratch
))
6572 if (! no_new_pseudos
)
6573 scratch
= gen_reg_rtx (SImode
);
6574 emit_move_insn (scratch
, high
[0]);
6575 emit_insn (gen_ashrsi3 (scratch
, scratch
, GEN_INT (31)));
6576 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
6580 emit_insn (gen_x86_shift_adj_3 (low
[0], high
[0], operands
[2]));
6585 ix86_split_lshrdi (operands
, scratch
)
6586 rtx
*operands
, scratch
;
6588 rtx low
[2], high
[2];
6591 if (GET_CODE (operands
[2]) == CONST_INT
)
6593 split_di (operands
, 2, low
, high
);
6594 count
= INTVAL (operands
[2]) & 63;
6598 emit_move_insn (low
[0], high
[1]);
6599 emit_move_insn (high
[0], const0_rtx
);
6602 emit_insn (gen_lshrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
6606 if (!rtx_equal_p (operands
[0], operands
[1]))
6607 emit_move_insn (operands
[0], operands
[1]);
6608 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
6609 emit_insn (gen_lshrsi3 (high
[0], high
[0], GEN_INT (count
)));
6614 if (!rtx_equal_p (operands
[0], operands
[1]))
6615 emit_move_insn (operands
[0], operands
[1]);
6617 split_di (operands
, 1, low
, high
);
6619 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
6620 emit_insn (gen_lshrsi3 (high
[0], high
[0], operands
[2]));
6622 /* Heh. By reversing the arguments, we can reuse this pattern. */
6623 if (TARGET_CMOVE
&& (! no_new_pseudos
|| scratch
))
6625 if (! no_new_pseudos
)
6626 scratch
= force_reg (SImode
, const0_rtx
);
6628 emit_move_insn (scratch
, const0_rtx
);
6630 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
6634 emit_insn (gen_x86_shift_adj_2 (low
[0], high
[0], operands
[2]));
6638 /* Expand the appropriate insns for doing strlen if not just doing
6641 out = result, initialized with the start address
6642 align_rtx = alignment of the address.
6643 scratch = scratch register, initialized with the startaddress when
6644 not aligned, otherwise undefined
6646 This is just the body. It needs the initialisations mentioned above and
6647 some address computing at the end. These things are done in i386.md. */
6650 ix86_expand_strlensi_unroll_1 (out
, align_rtx
, scratch
)
6651 rtx out
, align_rtx
, scratch
;
6655 rtx align_2_label
= NULL_RTX
;
6656 rtx align_3_label
= NULL_RTX
;
6657 rtx align_4_label
= gen_label_rtx ();
6658 rtx end_0_label
= gen_label_rtx ();
6660 rtx tmpreg
= gen_reg_rtx (SImode
);
6663 if (GET_CODE (align_rtx
) == CONST_INT
)
6664 align
= INTVAL (align_rtx
);
6666 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
6668 /* Is there a known alignment and is it less than 4? */
6671 /* Is there a known alignment and is it not 2? */
6674 align_3_label
= gen_label_rtx (); /* Label when aligned to 3-byte */
6675 align_2_label
= gen_label_rtx (); /* Label when aligned to 2-byte */
6677 /* Leave just the 3 lower bits. */
6678 align_rtx
= expand_binop (SImode
, and_optab
, scratch
, GEN_INT (3),
6679 NULL_RTX
, 0, OPTAB_WIDEN
);
6681 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
6682 SImode
, 1, 0, align_4_label
);
6683 emit_cmp_and_jump_insns (align_rtx
, GEN_INT (2), EQ
, NULL
,
6684 SImode
, 1, 0, align_2_label
);
6685 emit_cmp_and_jump_insns (align_rtx
, GEN_INT (2), GTU
, NULL
,
6686 SImode
, 1, 0, align_3_label
);
6690 /* Since the alignment is 2, we have to check 2 or 0 bytes;
6691 check if is aligned to 4 - byte. */
6693 align_rtx
= expand_binop (SImode
, and_optab
, scratch
, GEN_INT (2),
6694 NULL_RTX
, 0, OPTAB_WIDEN
);
6696 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
6697 SImode
, 1, 0, align_4_label
);
6700 mem
= gen_rtx_MEM (QImode
, out
);
6702 /* Now compare the bytes. */
6704 /* Compare the first n unaligned byte on a byte per byte basis. */
6705 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
,
6706 QImode
, 1, 0, end_0_label
);
6708 /* Increment the address. */
6709 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
6711 /* Not needed with an alignment of 2 */
6714 emit_label (align_2_label
);
6716 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
,
6717 QImode
, 1, 0, end_0_label
);
6719 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
6721 emit_label (align_3_label
);
6724 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
,
6725 QImode
, 1, 0, end_0_label
);
6727 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
6730 /* Generate loop to check 4 bytes at a time. It is not a good idea to
6731 align this loop. It gives only huge programs, but does not help to
6733 emit_label (align_4_label
);
6735 mem
= gen_rtx_MEM (SImode
, out
);
6736 emit_move_insn (scratch
, mem
);
6737 emit_insn (gen_addsi3 (out
, out
, GEN_INT (4)));
6739 /* This formula yields a nonzero result iff one of the bytes is zero.
6740 This saves three branches inside loop and many cycles. */
6742 emit_insn (gen_addsi3 (tmpreg
, scratch
, GEN_INT (-0x01010101)));
6743 emit_insn (gen_one_cmplsi2 (scratch
, scratch
));
6744 emit_insn (gen_andsi3 (tmpreg
, tmpreg
, scratch
));
6745 emit_insn (gen_andsi3 (tmpreg
, tmpreg
, GEN_INT (0x80808080)));
6746 emit_cmp_and_jump_insns (tmpreg
, const0_rtx
, EQ
, 0,
6747 SImode
, 1, 0, align_4_label
);
6751 rtx reg
= gen_reg_rtx (SImode
);
6752 emit_move_insn (reg
, tmpreg
);
6753 emit_insn (gen_lshrsi3 (reg
, reg
, GEN_INT (16)));
6755 /* If zero is not in the first two bytes, move two bytes forward. */
6756 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
6757 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
6758 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
6759 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
,
6760 gen_rtx_IF_THEN_ELSE (SImode
, tmp
,
6763 /* Emit lea manually to avoid clobbering of flags. */
6764 emit_insn (gen_rtx_SET (SImode
, reg
,
6765 gen_rtx_PLUS (SImode
, out
, GEN_INT (2))));
6767 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
6768 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
6769 emit_insn (gen_rtx_SET (VOIDmode
, out
,
6770 gen_rtx_IF_THEN_ELSE (SImode
, tmp
,
6777 rtx end_2_label
= gen_label_rtx ();
6778 /* Is zero in the first two bytes? */
6780 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
6781 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
6782 tmp
= gen_rtx_NE (VOIDmode
, tmp
, const0_rtx
);
6783 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
6784 gen_rtx_LABEL_REF (VOIDmode
, end_2_label
),
6786 tmp
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
6787 JUMP_LABEL (tmp
) = end_2_label
;
6789 /* Not in the first two. Move two bytes forward. */
6790 emit_insn (gen_lshrsi3 (tmpreg
, tmpreg
, GEN_INT (16)));
6791 emit_insn (gen_addsi3 (out
, out
, GEN_INT (2)));
6793 emit_label (end_2_label
);
6797 /* Avoid branch in fixing the byte. */
6798 tmpreg
= gen_lowpart (QImode
, tmpreg
);
6799 emit_insn (gen_addqi3_cc (tmpreg
, tmpreg
, tmpreg
));
6800 emit_insn (gen_subsi3_carry (out
, out
, GEN_INT (3)));
6802 emit_label (end_0_label
);
6805 /* Clear stack slot assignments remembered from previous functions.
6806 This is called from INIT_EXPANDERS once before RTL is emitted for each
6810 ix86_init_machine_status (p
)
6813 p
->machine
= (struct machine_function
*)
6814 xcalloc (1, sizeof (struct machine_function
));
6817 /* Mark machine specific bits of P for GC. */
6819 ix86_mark_machine_status (p
)
6822 struct machine_function
*machine
= p
->machine
;
6823 enum machine_mode mode
;
6829 for (mode
= VOIDmode
; (int) mode
< (int) MAX_MACHINE_MODE
;
6830 mode
= (enum machine_mode
) ((int) mode
+ 1))
6831 for (n
= 0; n
< MAX_386_STACK_LOCALS
; n
++)
6832 ggc_mark_rtx (machine
->stack_locals
[(int) mode
][n
]);
6836 ix86_free_machine_status (p
)
6843 /* Return a MEM corresponding to a stack slot with mode MODE.
6844 Allocate a new slot if necessary.
6846 The RTL for a function can have several slots available: N is
6847 which slot to use. */
6850 assign_386_stack_local (mode
, n
)
6851 enum machine_mode mode
;
6854 if (n
< 0 || n
>= MAX_386_STACK_LOCALS
)
6857 if (ix86_stack_locals
[(int) mode
][n
] == NULL_RTX
)
6858 ix86_stack_locals
[(int) mode
][n
]
6859 = assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
6861 return ix86_stack_locals
[(int) mode
][n
];
6864 /* Calculate the length of the memory address in the instruction
6865 encoding. Does not include the one-byte modrm, opcode, or prefix. */
6868 memory_address_length (addr
)
6871 struct ix86_address parts
;
6872 rtx base
, index
, disp
;
6875 if (GET_CODE (addr
) == PRE_DEC
6876 || GET_CODE (addr
) == POST_INC
)
6879 if (! ix86_decompose_address (addr
, &parts
))
6883 index
= parts
.index
;
6887 /* Register Indirect. */
6888 if (base
&& !index
&& !disp
)
6890 /* Special cases: ebp and esp need the two-byte modrm form. */
6891 if (addr
== stack_pointer_rtx
6892 || addr
== arg_pointer_rtx
6893 || addr
== frame_pointer_rtx
6894 || addr
== hard_frame_pointer_rtx
)
6898 /* Direct Addressing. */
6899 else if (disp
&& !base
&& !index
)
6904 /* Find the length of the displacement constant. */
6907 if (GET_CODE (disp
) == CONST_INT
6908 && CONST_OK_FOR_LETTER_P (INTVAL (disp
), 'K'))
6914 /* An index requires the two-byte modrm form. */
6922 /* Compute default value for "length_immediate" attribute. When SHORTFORM is set
6923 expect that insn have 8bit immediate alternative. */
6925 ix86_attr_length_immediate_default (insn
, shortform
)
6931 extract_insn_cached (insn
);
6932 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
6933 if (CONSTANT_P (recog_data
.operand
[i
]))
6938 && GET_CODE (recog_data
.operand
[i
]) == CONST_INT
6939 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data
.operand
[i
]), 'K'))
6943 switch (get_attr_mode (insn
))
6955 fatal_insn ("Unknown insn mode", insn
);
6961 /* Compute default value for "length_address" attribute. */
6963 ix86_attr_length_address_default (insn
)
6967 extract_insn_cached (insn
);
6968 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
6969 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
6971 return memory_address_length (XEXP (recog_data
.operand
[i
], 0));
6977 /* Return the maximum number of instructions a cpu can issue. */
6984 case PROCESSOR_PENTIUM
:
6988 case PROCESSOR_PENTIUMPRO
:
6989 case PROCESSOR_PENTIUM4
:
6990 case PROCESSOR_ATHLON
:
6998 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
6999 by DEP_INSN and nothing set by DEP_INSN. */
7002 ix86_flags_dependant (insn
, dep_insn
, insn_type
)
7004 enum attr_type insn_type
;
7008 /* Simplify the test for uninteresting insns. */
7009 if (insn_type
!= TYPE_SETCC
7010 && insn_type
!= TYPE_ICMOV
7011 && insn_type
!= TYPE_FCMOV
7012 && insn_type
!= TYPE_IBR
)
7015 if ((set
= single_set (dep_insn
)) != 0)
7017 set
= SET_DEST (set
);
7020 else if (GET_CODE (PATTERN (dep_insn
)) == PARALLEL
7021 && XVECLEN (PATTERN (dep_insn
), 0) == 2
7022 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 0)) == SET
7023 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 1)) == SET
)
7025 set
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
7026 set2
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
7031 if (GET_CODE (set
) != REG
|| REGNO (set
) != FLAGS_REG
)
7034 /* This test is true if the dependant insn reads the flags but
7035 not any other potentially set register. */
7036 if (!reg_overlap_mentioned_p (set
, PATTERN (insn
)))
7039 if (set2
&& reg_overlap_mentioned_p (set2
, PATTERN (insn
)))
7045 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
7046 address with operands set by DEP_INSN. */
7049 ix86_agi_dependant (insn
, dep_insn
, insn_type
)
7051 enum attr_type insn_type
;
7055 if (insn_type
== TYPE_LEA
)
7057 addr
= PATTERN (insn
);
7058 if (GET_CODE (addr
) == SET
)
7060 else if (GET_CODE (addr
) == PARALLEL
7061 && GET_CODE (XVECEXP (addr
, 0, 0)) == SET
)
7062 addr
= XVECEXP (addr
, 0, 0);
7065 addr
= SET_SRC (addr
);
7070 extract_insn_cached (insn
);
7071 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
7072 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
7074 addr
= XEXP (recog_data
.operand
[i
], 0);
7081 return modified_in_p (addr
, dep_insn
);
7085 ix86_adjust_cost (insn
, link
, dep_insn
, cost
)
7086 rtx insn
, link
, dep_insn
;
7089 enum attr_type insn_type
, dep_insn_type
;
7090 enum attr_memory memory
;
7092 int dep_insn_code_number
;
7094 /* Anti and output depenancies have zero cost on all CPUs. */
7095 if (REG_NOTE_KIND (link
) != 0)
7098 dep_insn_code_number
= recog_memoized (dep_insn
);
7100 /* If we can't recognize the insns, we can't really do anything. */
7101 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
7104 insn_type
= get_attr_type (insn
);
7105 dep_insn_type
= get_attr_type (dep_insn
);
7107 /* Prologue and epilogue allocators can have a false dependency on ebp.
7108 This results in one cycle extra stall on Pentium prologue scheduling,
7109 so handle this important case manually. */
7110 if (dep_insn_code_number
== CODE_FOR_pro_epilogue_adjust_stack
7111 && dep_insn_type
== TYPE_ALU
7112 && !reg_mentioned_p (stack_pointer_rtx
, insn
))
7117 case PROCESSOR_PENTIUM
:
7118 /* Address Generation Interlock adds a cycle of latency. */
7119 if (ix86_agi_dependant (insn
, dep_insn
, insn_type
))
7122 /* ??? Compares pair with jump/setcc. */
7123 if (ix86_flags_dependant (insn
, dep_insn
, insn_type
))
7126 /* Floating point stores require value to be ready one cycle ealier. */
7127 if (insn_type
== TYPE_FMOV
7128 && get_attr_memory (insn
) == MEMORY_STORE
7129 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
7133 case PROCESSOR_PENTIUMPRO
:
7134 /* Since we can't represent delayed latencies of load+operation,
7135 increase the cost here for non-imov insns. */
7136 if (dep_insn_type
!= TYPE_IMOV
7137 && dep_insn_type
!= TYPE_FMOV
7138 && ((memory
= get_attr_memory (dep_insn
) == MEMORY_LOAD
)
7139 || memory
== MEMORY_BOTH
))
7142 /* INT->FP conversion is expensive. */
7143 if (get_attr_fp_int_src (dep_insn
))
7146 /* There is one cycle extra latency between an FP op and a store. */
7147 if (insn_type
== TYPE_FMOV
7148 && (set
= single_set (dep_insn
)) != NULL_RTX
7149 && (set2
= single_set (insn
)) != NULL_RTX
7150 && rtx_equal_p (SET_DEST (set
), SET_SRC (set2
))
7151 && GET_CODE (SET_DEST (set2
)) == MEM
)
7156 /* The esp dependency is resolved before the instruction is really
7158 if ((insn_type
== TYPE_PUSH
|| insn_type
== TYPE_POP
)
7159 && (dep_insn_type
== TYPE_PUSH
|| dep_insn_type
== TYPE_POP
))
7162 /* Since we can't represent delayed latencies of load+operation,
7163 increase the cost here for non-imov insns. */
7164 if ((memory
= get_attr_memory (dep_insn
) == MEMORY_LOAD
)
7165 || memory
== MEMORY_BOTH
)
7166 cost
+= (dep_insn_type
!= TYPE_IMOV
) ? 2 : 1;
7168 /* INT->FP conversion is expensive. */
7169 if (get_attr_fp_int_src (dep_insn
))
7173 case PROCESSOR_ATHLON
:
7174 if ((memory
= get_attr_memory (dep_insn
)) == MEMORY_LOAD
7175 || memory
== MEMORY_BOTH
)
7177 if (dep_insn_type
== TYPE_IMOV
|| dep_insn_type
== TYPE_FMOV
)
7192 struct ppro_sched_data
7195 int issued_this_cycle
;
7200 ix86_safe_length (insn
)
7203 if (recog_memoized (insn
) >= 0)
7204 return get_attr_length(insn
);
7210 ix86_safe_length_prefix (insn
)
7213 if (recog_memoized (insn
) >= 0)
7214 return get_attr_length(insn
);
7219 static enum attr_memory
7220 ix86_safe_memory (insn
)
7223 if (recog_memoized (insn
) >= 0)
7224 return get_attr_memory(insn
);
7226 return MEMORY_UNKNOWN
;
7229 static enum attr_pent_pair
7230 ix86_safe_pent_pair (insn
)
7233 if (recog_memoized (insn
) >= 0)
7234 return get_attr_pent_pair(insn
);
7236 return PENT_PAIR_NP
;
7239 static enum attr_ppro_uops
7240 ix86_safe_ppro_uops (insn
)
7243 if (recog_memoized (insn
) >= 0)
7244 return get_attr_ppro_uops (insn
);
7246 return PPRO_UOPS_MANY
;
7250 ix86_dump_ppro_packet (dump
)
7253 if (ix86_sched_data
.ppro
.decode
[0])
7255 fprintf (dump
, "PPRO packet: %d",
7256 INSN_UID (ix86_sched_data
.ppro
.decode
[0]));
7257 if (ix86_sched_data
.ppro
.decode
[1])
7258 fprintf (dump
, " %d", INSN_UID (ix86_sched_data
.ppro
.decode
[1]));
7259 if (ix86_sched_data
.ppro
.decode
[2])
7260 fprintf (dump
, " %d", INSN_UID (ix86_sched_data
.ppro
.decode
[2]));
7265 /* We're beginning a new block. Initialize data structures as necessary. */
7268 ix86_sched_init (dump
, sched_verbose
)
7269 FILE *dump ATTRIBUTE_UNUSED
;
7270 int sched_verbose ATTRIBUTE_UNUSED
;
7272 memset (&ix86_sched_data
, 0, sizeof (ix86_sched_data
));
7275 /* Shift INSN to SLOT, and shift everything else down. */
7278 ix86_reorder_insn (insnp
, slot
)
7285 insnp
[0] = insnp
[1];
7286 while (++insnp
!= slot
);
7291 /* Find an instruction with given pairability and minimal amount of cycles
7292 lost by the fact that the CPU waits for both pipelines to finish before
7293 reading next instructions. Also take care that both instructions together
7294 can not exceed 7 bytes. */
7297 ix86_pent_find_pair (e_ready
, ready
, type
, first
)
7300 enum attr_pent_pair type
;
7303 int mincycles
, cycles
;
7304 enum attr_pent_pair tmp
;
7305 enum attr_memory memory
;
7306 rtx
*insnp
, *bestinsnp
= NULL
;
7308 if (ix86_safe_length (first
) > 7 + ix86_safe_length_prefix (first
))
7311 memory
= ix86_safe_memory (first
);
7312 cycles
= result_ready_cost (first
);
7313 mincycles
= INT_MAX
;
7315 for (insnp
= e_ready
; insnp
>= ready
&& mincycles
; --insnp
)
7316 if ((tmp
= ix86_safe_pent_pair (*insnp
)) == type
7317 && ix86_safe_length (*insnp
) <= 7 + ix86_safe_length_prefix (*insnp
))
7319 enum attr_memory second_memory
;
7320 int secondcycles
, currentcycles
;
7322 second_memory
= ix86_safe_memory (*insnp
);
7323 secondcycles
= result_ready_cost (*insnp
);
7324 currentcycles
= abs (cycles
- secondcycles
);
7326 if (secondcycles
>= 1 && cycles
>= 1)
7328 /* Two read/modify/write instructions together takes two
7330 if (memory
== MEMORY_BOTH
&& second_memory
== MEMORY_BOTH
)
7333 /* Read modify/write instruction followed by read/modify
7334 takes one cycle longer. */
7335 if (memory
== MEMORY_BOTH
&& second_memory
== MEMORY_LOAD
7336 && tmp
!= PENT_PAIR_UV
7337 && ix86_safe_pent_pair (first
) != PENT_PAIR_UV
)
7340 if (currentcycles
< mincycles
)
7341 bestinsnp
= insnp
, mincycles
= currentcycles
;
7347 /* Subroutines of ix86_sched_reorder. */
7350 ix86_sched_reorder_pentium (ready
, e_ready
)
7354 enum attr_pent_pair pair1
, pair2
;
7357 /* This wouldn't be necessary if Haifa knew that static insn ordering
7358 is important to which pipe an insn is issued to. So we have to make
7359 some minor rearrangements. */
7361 pair1
= ix86_safe_pent_pair (*e_ready
);
7363 /* If the first insn is non-pairable, let it be. */
7364 if (pair1
== PENT_PAIR_NP
)
7367 pair2
= PENT_PAIR_NP
;
7370 /* If the first insn is UV or PV pairable, search for a PU
7372 if (pair1
== PENT_PAIR_UV
|| pair1
== PENT_PAIR_PV
)
7374 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
7375 PENT_PAIR_PU
, *e_ready
);
7377 pair2
= PENT_PAIR_PU
;
7380 /* If the first insn is PU or UV pairable, search for a PV
7382 if (pair2
== PENT_PAIR_NP
7383 && (pair1
== PENT_PAIR_PU
|| pair1
== PENT_PAIR_UV
))
7385 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
7386 PENT_PAIR_PV
, *e_ready
);
7388 pair2
= PENT_PAIR_PV
;
7391 /* If the first insn is pairable, search for a UV
7393 if (pair2
== PENT_PAIR_NP
)
7395 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
7396 PENT_PAIR_UV
, *e_ready
);
7398 pair2
= PENT_PAIR_UV
;
7401 if (pair2
== PENT_PAIR_NP
)
7404 /* Found something! Decide if we need to swap the order. */
7405 if (pair1
== PENT_PAIR_PV
|| pair2
== PENT_PAIR_PU
7406 || (pair1
== PENT_PAIR_UV
&& pair2
== PENT_PAIR_UV
7407 && ix86_safe_memory (*e_ready
) == MEMORY_BOTH
7408 && ix86_safe_memory (*insnp
) == MEMORY_LOAD
))
7409 ix86_reorder_insn (insnp
, e_ready
);
7411 ix86_reorder_insn (insnp
, e_ready
- 1);
7415 ix86_sched_reorder_ppro (ready
, e_ready
)
7420 enum attr_ppro_uops cur_uops
;
7421 int issued_this_cycle
;
7425 /* At this point .ppro.decode contains the state of the three
7426 decoders from last "cycle". That is, those insns that were
7427 actually independent. But here we're scheduling for the
7428 decoder, and we may find things that are decodable in the
7431 memcpy (decode
, ix86_sched_data
.ppro
.decode
, sizeof (decode
));
7432 issued_this_cycle
= 0;
7435 cur_uops
= ix86_safe_ppro_uops (*insnp
);
7437 /* If the decoders are empty, and we've a complex insn at the
7438 head of the priority queue, let it issue without complaint. */
7439 if (decode
[0] == NULL
)
7441 if (cur_uops
== PPRO_UOPS_MANY
)
7447 /* Otherwise, search for a 2-4 uop unsn to issue. */
7448 while (cur_uops
!= PPRO_UOPS_FEW
)
7452 cur_uops
= ix86_safe_ppro_uops (*--insnp
);
7455 /* If so, move it to the head of the line. */
7456 if (cur_uops
== PPRO_UOPS_FEW
)
7457 ix86_reorder_insn (insnp
, e_ready
);
7459 /* Issue the head of the queue. */
7460 issued_this_cycle
= 1;
7461 decode
[0] = *e_ready
--;
7464 /* Look for simple insns to fill in the other two slots. */
7465 for (i
= 1; i
< 3; ++i
)
7466 if (decode
[i
] == NULL
)
7468 if (ready
>= e_ready
)
7472 cur_uops
= ix86_safe_ppro_uops (*insnp
);
7473 while (cur_uops
!= PPRO_UOPS_ONE
)
7477 cur_uops
= ix86_safe_ppro_uops (*--insnp
);
7480 /* Found one. Move it to the head of the queue and issue it. */
7481 if (cur_uops
== PPRO_UOPS_ONE
)
7483 ix86_reorder_insn (insnp
, e_ready
);
7484 decode
[i
] = *e_ready
--;
7485 issued_this_cycle
++;
7489 /* ??? Didn't find one. Ideally, here we would do a lazy split
7490 of 2-uop insns, issue one and queue the other. */
7494 if (issued_this_cycle
== 0)
7495 issued_this_cycle
= 1;
7496 ix86_sched_data
.ppro
.issued_this_cycle
= issued_this_cycle
;
7499 /* We are about to being issuing insns for this clock cycle.
7500 Override the default sort algorithm to better slot instructions. */
7502 ix86_sched_reorder (dump
, sched_verbose
, ready
, n_ready
, clock_var
)
7503 FILE *dump ATTRIBUTE_UNUSED
;
7504 int sched_verbose ATTRIBUTE_UNUSED
;
7507 int clock_var ATTRIBUTE_UNUSED
;
7509 rtx
*e_ready
= ready
+ n_ready
- 1;
7519 case PROCESSOR_PENTIUM
:
7520 ix86_sched_reorder_pentium (ready
, e_ready
);
7523 case PROCESSOR_PENTIUMPRO
:
7524 ix86_sched_reorder_ppro (ready
, e_ready
);
7529 return ix86_issue_rate ();
7532 /* We are about to issue INSN. Return the number of insns left on the
7533 ready queue that can be issued this cycle. */
7536 ix86_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
)
7546 return can_issue_more
- 1;
7548 case PROCESSOR_PENTIUMPRO
:
7550 enum attr_ppro_uops uops
= ix86_safe_ppro_uops (insn
);
7552 if (uops
== PPRO_UOPS_MANY
)
7555 ix86_dump_ppro_packet (dump
);
7556 ix86_sched_data
.ppro
.decode
[0] = insn
;
7557 ix86_sched_data
.ppro
.decode
[1] = NULL
;
7558 ix86_sched_data
.ppro
.decode
[2] = NULL
;
7560 ix86_dump_ppro_packet (dump
);
7561 ix86_sched_data
.ppro
.decode
[0] = NULL
;
7563 else if (uops
== PPRO_UOPS_FEW
)
7566 ix86_dump_ppro_packet (dump
);
7567 ix86_sched_data
.ppro
.decode
[0] = insn
;
7568 ix86_sched_data
.ppro
.decode
[1] = NULL
;
7569 ix86_sched_data
.ppro
.decode
[2] = NULL
;
7573 for (i
= 0; i
< 3; ++i
)
7574 if (ix86_sched_data
.ppro
.decode
[i
] == NULL
)
7576 ix86_sched_data
.ppro
.decode
[i
] = insn
;
7584 ix86_dump_ppro_packet (dump
);
7585 ix86_sched_data
.ppro
.decode
[0] = NULL
;
7586 ix86_sched_data
.ppro
.decode
[1] = NULL
;
7587 ix86_sched_data
.ppro
.decode
[2] = NULL
;
7591 return --ix86_sched_data
.ppro
.issued_this_cycle
;
7595 /* Walk through INSNS and look for MEM references whose address is DSTREG or
7596 SRCREG and set the memory attribute to those of DSTREF and SRCREF, as
7600 ix86_set_move_mem_attrs (insns
, dstref
, srcref
, dstreg
, srcreg
)
7602 rtx dstref
, srcref
, dstreg
, srcreg
;
7606 for (insn
= insns
; insn
!= 0 ; insn
= NEXT_INSN (insn
))
7608 ix86_set_move_mem_attrs_1 (PATTERN (insn
), dstref
, srcref
,
7612 /* Subroutine of above to actually do the updating by recursively walking
7616 ix86_set_move_mem_attrs_1 (x
, dstref
, srcref
, dstreg
, srcreg
)
7618 rtx dstref
, srcref
, dstreg
, srcreg
;
7620 enum rtx_code code
= GET_CODE (x
);
7621 const char *format_ptr
= GET_RTX_FORMAT (code
);
7624 if (code
== MEM
&& XEXP (x
, 0) == dstreg
)
7625 MEM_COPY_ATTRIBUTES (x
, dstref
);
7626 else if (code
== MEM
&& XEXP (x
, 0) == srcreg
)
7627 MEM_COPY_ATTRIBUTES (x
, srcref
);
7629 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, format_ptr
++)
7631 if (*format_ptr
== 'e')
7632 ix86_set_move_mem_attrs_1 (XEXP (x
, i
), dstref
, srcref
,
7634 else if (*format_ptr
== 'E')
7635 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7636 ix86_set_move_mem_attrs_1 (XVECEXP (x
, i
, j
), dstref
, srcref
,
7641 /* Compute the alignment given to a constant that is being placed in memory.
7642 EXP is the constant and ALIGN is the alignment that the object would
7644 The value of this function is used instead of that alignment to align
7648 ix86_constant_alignment (exp
, align
)
7652 if (TREE_CODE (exp
) == REAL_CST
)
7654 if (TYPE_MODE (TREE_TYPE (exp
)) == DFmode
&& align
< 64)
7656 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp
))) && align
< 128)
7659 else if (TREE_CODE (exp
) == STRING_CST
&& TREE_STRING_LENGTH (exp
) >= 31
7666 /* Compute the alignment for a static variable.
7667 TYPE is the data type, and ALIGN is the alignment that
7668 the object would ordinarily have. The value of this function is used
7669 instead of that alignment to align the object. */
7672 ix86_data_alignment (type
, align
)
7676 if (AGGREGATE_TYPE_P (type
)
7678 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
7679 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 256
7680 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 256)
7683 if (TREE_CODE (type
) == ARRAY_TYPE
)
7685 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
7687 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
7690 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
7693 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
7695 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
7698 else if ((TREE_CODE (type
) == RECORD_TYPE
7699 || TREE_CODE (type
) == UNION_TYPE
7700 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
7701 && TYPE_FIELDS (type
))
7703 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
7705 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
7708 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
7709 || TREE_CODE (type
) == INTEGER_TYPE
)
7711 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
7713 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
7720 /* Compute the alignment for a local variable.
7721 TYPE is the data type, and ALIGN is the alignment that
7722 the object would ordinarily have. The value of this macro is used
7723 instead of that alignment to align the object. */
7726 ix86_local_alignment (type
, align
)
7730 if (TREE_CODE (type
) == ARRAY_TYPE
)
7732 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
7734 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
7737 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
7739 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
7741 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
7744 else if ((TREE_CODE (type
) == RECORD_TYPE
7745 || TREE_CODE (type
) == UNION_TYPE
7746 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
7747 && TYPE_FIELDS (type
))
7749 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
7751 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
7754 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
7755 || TREE_CODE (type
) == INTEGER_TYPE
)
7758 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
7760 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
7766 #define def_builtin(NAME, TYPE, CODE) \
7767 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL_PTR)
7768 struct builtin_description
7770 enum insn_code icode
;
7772 enum ix86_builtins code
;
7773 enum rtx_code comparison
;
7777 static struct builtin_description bdesc_comi
[] =
7779 { CODE_FOR_sse_comi
, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS
, EQ
, 0 },
7780 { CODE_FOR_sse_comi
, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS
, LT
, 0 },
7781 { CODE_FOR_sse_comi
, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS
, LE
, 0 },
7782 { CODE_FOR_sse_comi
, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS
, LT
, 1 },
7783 { CODE_FOR_sse_comi
, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS
, LE
, 1 },
7784 { CODE_FOR_sse_comi
, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS
, NE
, 0 },
7785 { CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS
, EQ
, 0 },
7786 { CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS
, LT
, 0 },
7787 { CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS
, LE
, 0 },
7788 { CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS
, LT
, 1 },
7789 { CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS
, LE
, 1 },
7790 { CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS
, NE
, 0 }
7793 static struct builtin_description bdesc_2arg
[] =
7796 { CODE_FOR_addv4sf3
, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS
, 0, 0 },
7797 { CODE_FOR_subv4sf3
, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS
, 0, 0 },
7798 { CODE_FOR_mulv4sf3
, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS
, 0, 0 },
7799 { CODE_FOR_divv4sf3
, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS
, 0, 0 },
7800 { CODE_FOR_vmaddv4sf3
, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS
, 0, 0 },
7801 { CODE_FOR_vmsubv4sf3
, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS
, 0, 0 },
7802 { CODE_FOR_vmmulv4sf3
, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS
, 0, 0 },
7803 { CODE_FOR_vmdivv4sf3
, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS
, 0, 0 },
7805 { CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS
, EQ
, 0 },
7806 { CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS
, LT
, 0 },
7807 { CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS
, LE
, 0 },
7808 { CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS
, LT
, 1 },
7809 { CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS
, LE
, 1 },
7810 { CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS
, UNORDERED
, 0 },
7811 { CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS
, EQ
, 0 },
7812 { CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS
, LT
, 0 },
7813 { CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS
, LE
, 0 },
7814 { CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS
, LT
, 1 },
7815 { CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS
, LE
, 1 },
7816 { CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS
, UNORDERED
, 0 },
7817 { CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS
, EQ
, 0 },
7818 { CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS
, LT
, 0 },
7819 { CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS
, LE
, 0 },
7820 { CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpgtss", IX86_BUILTIN_CMPGTSS
, LT
, 1 },
7821 { CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpgess", IX86_BUILTIN_CMPGESS
, LE
, 1 },
7822 { CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS
, UNORDERED
, 0 },
7823 { CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS
, EQ
, 0 },
7824 { CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS
, LT
, 0 },
7825 { CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS
, LE
, 0 },
7826 { CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS
, LT
, 1 },
7827 { CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS
, LE
, 1 },
7828 { CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS
, UNORDERED
, 0 },
7830 { CODE_FOR_sminv4sf3
, "__builtin_ia32_minps", IX86_BUILTIN_MINPS
, 0, 0 },
7831 { CODE_FOR_smaxv4sf3
, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS
, 0, 0 },
7832 { CODE_FOR_vmsminv4sf3
, "__builtin_ia32_minss", IX86_BUILTIN_MINSS
, 0, 0 },
7833 { CODE_FOR_vmsmaxv4sf3
, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS
, 0, 0 },
7835 { CODE_FOR_sse_andti3
, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS
, 0, 0 },
7836 { CODE_FOR_sse_nandti3
, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS
, 0, 0 },
7837 { CODE_FOR_sse_iorti3
, "__builtin_ia32_orps", IX86_BUILTIN_ORPS
, 0, 0 },
7838 { CODE_FOR_sse_xorti3
, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS
, 0, 0 },
7840 { CODE_FOR_sse_movss
, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS
, 0, 0 },
7841 { CODE_FOR_sse_movhlps
, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS
, 0, 0 },
7842 { CODE_FOR_sse_movlhps
, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS
, 0, 0 },
7843 { CODE_FOR_sse_unpckhps
, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS
, 0, 0 },
7844 { CODE_FOR_sse_unpcklps
, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS
, 0, 0 },
7847 { CODE_FOR_addv8qi3
, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB
, 0, 0 },
7848 { CODE_FOR_addv4hi3
, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW
, 0, 0 },
7849 { CODE_FOR_addv2si3
, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD
, 0, 0 },
7850 { CODE_FOR_subv8qi3
, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB
, 0, 0 },
7851 { CODE_FOR_subv4hi3
, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW
, 0, 0 },
7852 { CODE_FOR_subv2si3
, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD
, 0, 0 },
7854 { CODE_FOR_ssaddv8qi3
, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB
, 0, 0 },
7855 { CODE_FOR_ssaddv4hi3
, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW
, 0, 0 },
7856 { CODE_FOR_sssubv8qi3
, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB
, 0, 0 },
7857 { CODE_FOR_sssubv4hi3
, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW
, 0, 0 },
7858 { CODE_FOR_usaddv8qi3
, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB
, 0, 0 },
7859 { CODE_FOR_usaddv4hi3
, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW
, 0, 0 },
7860 { CODE_FOR_ussubv8qi3
, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB
, 0, 0 },
7861 { CODE_FOR_ussubv4hi3
, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW
, 0, 0 },
7863 { CODE_FOR_mulv4hi3
, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW
, 0, 0 },
7864 { CODE_FOR_smulv4hi3_highpart
, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW
, 0, 0 },
7865 { CODE_FOR_umulv4hi3_highpart
, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW
, 0, 0 },
7867 { CODE_FOR_mmx_anddi3
, "__builtin_ia32_pand", IX86_BUILTIN_PAND
, 0, 0 },
7868 { CODE_FOR_mmx_nanddi3
, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN
, 0, 0 },
7869 { CODE_FOR_mmx_iordi3
, "__builtin_ia32_por", IX86_BUILTIN_POR
, 0, 0 },
7870 { CODE_FOR_mmx_xordi3
, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR
, 0, 0 },
7872 { CODE_FOR_mmx_uavgv8qi3
, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB
, 0, 0 },
7873 { CODE_FOR_mmx_uavgv4hi3
, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW
, 0, 0 },
7875 { CODE_FOR_eqv8qi3
, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB
, 0, 0 },
7876 { CODE_FOR_eqv4hi3
, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW
, 0, 0 },
7877 { CODE_FOR_eqv2si3
, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD
, 0, 0 },
7878 { CODE_FOR_gtv8qi3
, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB
, 0, 0 },
7879 { CODE_FOR_gtv4hi3
, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW
, 0, 0 },
7880 { CODE_FOR_gtv2si3
, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD
, 0, 0 },
7882 { CODE_FOR_umaxv8qi3
, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB
, 0, 0 },
7883 { CODE_FOR_smaxv4hi3
, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW
, 0, 0 },
7884 { CODE_FOR_uminv8qi3
, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB
, 0, 0 },
7885 { CODE_FOR_sminv4hi3
, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW
, 0, 0 },
7887 { CODE_FOR_mmx_punpckhbw
, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW
, 0, 0 },
7888 { CODE_FOR_mmx_punpckhwd
, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD
, 0, 0 },
7889 { CODE_FOR_mmx_punpckhdq
, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ
, 0, 0 },
7890 { CODE_FOR_mmx_punpcklbw
, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW
, 0, 0 },
7891 { CODE_FOR_mmx_punpcklwd
, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD
, 0, 0 },
7892 { CODE_FOR_mmx_punpckldq
, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ
, 0, 0 },
7895 { CODE_FOR_mmx_packsswb
, 0, IX86_BUILTIN_PACKSSWB
, 0, 0 },
7896 { CODE_FOR_mmx_packssdw
, 0, IX86_BUILTIN_PACKSSDW
, 0, 0 },
7897 { CODE_FOR_mmx_packuswb
, 0, IX86_BUILTIN_PACKUSWB
, 0, 0 },
7899 { CODE_FOR_cvtpi2ps
, 0, IX86_BUILTIN_CVTPI2PS
, 0, 0 },
7900 { CODE_FOR_cvtsi2ss
, 0, IX86_BUILTIN_CVTSI2SS
, 0, 0 },
7902 { CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLW
, 0, 0 },
7903 { CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLWI
, 0, 0 },
7904 { CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLD
, 0, 0 },
7905 { CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLDI
, 0, 0 },
7906 { CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQ
, 0, 0 },
7907 { CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQI
, 0, 0 },
7909 { CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLW
, 0, 0 },
7910 { CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLWI
, 0, 0 },
7911 { CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLD
, 0, 0 },
7912 { CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLDI
, 0, 0 },
7913 { CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQ
, 0, 0 },
7914 { CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQI
, 0, 0 },
7916 { CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAW
, 0, 0 },
7917 { CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAWI
, 0, 0 },
7918 { CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRAD
, 0, 0 },
7919 { CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRADI
, 0, 0 },
7921 { CODE_FOR_mmx_psadbw
, 0, IX86_BUILTIN_PSADBW
, 0, 0 },
7922 { CODE_FOR_mmx_pmaddwd
, 0, IX86_BUILTIN_PMADDWD
, 0, 0 }
7926 static struct builtin_description bdesc_1arg
[] =
7928 { CODE_FOR_mmx_pmovmskb
, 0, IX86_BUILTIN_PMOVMSKB
, 0, 0 },
7929 { CODE_FOR_sse_movmskps
, 0, IX86_BUILTIN_MOVMSKPS
, 0, 0 },
7931 { CODE_FOR_sqrtv4sf2
, 0, IX86_BUILTIN_SQRTPS
, 0, 0 },
7932 { CODE_FOR_rsqrtv4sf2
, 0, IX86_BUILTIN_RSQRTPS
, 0, 0 },
7933 { CODE_FOR_rcpv4sf2
, 0, IX86_BUILTIN_RCPPS
, 0, 0 },
7935 { CODE_FOR_cvtps2pi
, 0, IX86_BUILTIN_CVTPS2PI
, 0, 0 },
7936 { CODE_FOR_cvtss2si
, 0, IX86_BUILTIN_CVTSS2SI
, 0, 0 },
7937 { CODE_FOR_cvttps2pi
, 0, IX86_BUILTIN_CVTTPS2PI
, 0, 0 },
7938 { CODE_FOR_cvttss2si
, 0, IX86_BUILTIN_CVTTSS2SI
, 0, 0 }
7942 /* Expand all the target specific builtins. This is not called if TARGET_MMX
7943 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
7946 ix86_init_builtins ()
7948 struct builtin_description
* d
;
7950 tree endlink
= void_list_node
;
7952 tree pchar_type_node
= build_pointer_type (char_type_node
);
7953 tree pfloat_type_node
= build_pointer_type (float_type_node
);
7954 tree pv2si_type_node
= build_pointer_type (V2SI_type_node
);
7955 tree pdi_type_node
= build_pointer_type (long_long_unsigned_type_node
);
7958 tree int_ftype_v4sf_v4sf
7959 = build_function_type (integer_type_node
,
7960 tree_cons (NULL_TREE
, V4SF_type_node
,
7961 tree_cons (NULL_TREE
,
7964 tree v4si_ftype_v4sf_v4sf
7965 = build_function_type (V4SI_type_node
,
7966 tree_cons (NULL_TREE
, V4SF_type_node
,
7967 tree_cons (NULL_TREE
,
7970 /* MMX/SSE/integer conversions. */
7971 tree int_ftype_v4sf_int
7972 = build_function_type (integer_type_node
,
7973 tree_cons (NULL_TREE
, V4SF_type_node
,
7974 tree_cons (NULL_TREE
,
7978 = build_function_type (integer_type_node
,
7979 tree_cons (NULL_TREE
, V4SF_type_node
,
7982 = build_function_type (integer_type_node
,
7983 tree_cons (NULL_TREE
, V8QI_type_node
,
7986 = build_function_type (integer_type_node
,
7987 tree_cons (NULL_TREE
, V2SI_type_node
,
7990 = build_function_type (V2SI_type_node
,
7991 tree_cons (NULL_TREE
, integer_type_node
,
7993 tree v4sf_ftype_v4sf_int
7994 = build_function_type (integer_type_node
,
7995 tree_cons (NULL_TREE
, V4SF_type_node
,
7996 tree_cons (NULL_TREE
, integer_type_node
,
7998 tree v4sf_ftype_v4sf_v2si
7999 = build_function_type (V4SF_type_node
,
8000 tree_cons (NULL_TREE
, V4SF_type_node
,
8001 tree_cons (NULL_TREE
, V2SI_type_node
,
8003 tree int_ftype_v4hi_int
8004 = build_function_type (integer_type_node
,
8005 tree_cons (NULL_TREE
, V4HI_type_node
,
8006 tree_cons (NULL_TREE
, integer_type_node
,
8008 tree v4hi_ftype_v4hi_int_int
8009 = build_function_type (V4HI_type_node
,
8010 tree_cons (NULL_TREE
, V4HI_type_node
,
8011 tree_cons (NULL_TREE
, integer_type_node
,
8012 tree_cons (NULL_TREE
,
8015 /* Miscellaneous. */
8016 tree v8qi_ftype_v4hi_v4hi
8017 = build_function_type (V8QI_type_node
,
8018 tree_cons (NULL_TREE
, V4HI_type_node
,
8019 tree_cons (NULL_TREE
, V4HI_type_node
,
8021 tree v4hi_ftype_v2si_v2si
8022 = build_function_type (V4HI_type_node
,
8023 tree_cons (NULL_TREE
, V2SI_type_node
,
8024 tree_cons (NULL_TREE
, V2SI_type_node
,
8026 tree v4sf_ftype_v4sf_v4sf_int
8027 = build_function_type (V4SF_type_node
,
8028 tree_cons (NULL_TREE
, V4SF_type_node
,
8029 tree_cons (NULL_TREE
, V4SF_type_node
,
8030 tree_cons (NULL_TREE
,
8033 tree v4hi_ftype_v8qi_v8qi
8034 = build_function_type (V4HI_type_node
,
8035 tree_cons (NULL_TREE
, V8QI_type_node
,
8036 tree_cons (NULL_TREE
, V8QI_type_node
,
8038 tree v2si_ftype_v4hi_v4hi
8039 = build_function_type (V2SI_type_node
,
8040 tree_cons (NULL_TREE
, V4HI_type_node
,
8041 tree_cons (NULL_TREE
, V4HI_type_node
,
8043 tree v4hi_ftype_v4hi_int
8044 = build_function_type (V4HI_type_node
,
8045 tree_cons (NULL_TREE
, V4HI_type_node
,
8046 tree_cons (NULL_TREE
, integer_type_node
,
8048 tree di_ftype_di_int
8049 = build_function_type (long_long_unsigned_type_node
,
8050 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
8051 tree_cons (NULL_TREE
, integer_type_node
,
8053 tree v8qi_ftype_v8qi_di
8054 = build_function_type (V8QI_type_node
,
8055 tree_cons (NULL_TREE
, V8QI_type_node
,
8056 tree_cons (NULL_TREE
,
8057 long_long_integer_type_node
,
8059 tree v4hi_ftype_v4hi_di
8060 = build_function_type (V4HI_type_node
,
8061 tree_cons (NULL_TREE
, V4HI_type_node
,
8062 tree_cons (NULL_TREE
,
8063 long_long_integer_type_node
,
8065 tree v2si_ftype_v2si_di
8066 = build_function_type (V2SI_type_node
,
8067 tree_cons (NULL_TREE
, V2SI_type_node
,
8068 tree_cons (NULL_TREE
,
8069 long_long_integer_type_node
,
8071 tree void_ftype_void
8072 = build_function_type (void_type_node
, endlink
);
8073 tree void_ftype_pchar_int
8074 = build_function_type (void_type_node
,
8075 tree_cons (NULL_TREE
, pchar_type_node
,
8076 tree_cons (NULL_TREE
, integer_type_node
,
8078 tree void_ftype_unsigned
8079 = build_function_type (void_type_node
,
8080 tree_cons (NULL_TREE
, unsigned_type_node
,
8082 tree unsigned_ftype_void
8083 = build_function_type (unsigned_type_node
, endlink
);
8085 = build_function_type (long_long_unsigned_type_node
, endlink
);
8087 = build_function_type (intTI_type_node
, endlink
);
8088 tree v2si_ftype_v4sf
8089 = build_function_type (V2SI_type_node
,
8090 tree_cons (NULL_TREE
, V4SF_type_node
,
8093 tree maskmovq_args
= tree_cons (NULL_TREE
, V8QI_type_node
,
8094 tree_cons (NULL_TREE
, V8QI_type_node
,
8095 tree_cons (NULL_TREE
,
8098 tree void_ftype_v8qi_v8qi_pchar
8099 = build_function_type (void_type_node
, maskmovq_args
);
8100 tree v4sf_ftype_pfloat
8101 = build_function_type (V4SF_type_node
,
8102 tree_cons (NULL_TREE
, pfloat_type_node
,
8104 tree v4sf_ftype_float
8105 = build_function_type (V4SF_type_node
,
8106 tree_cons (NULL_TREE
, float_type_node
,
8108 tree v4sf_ftype_float_float_float_float
8109 = build_function_type (V4SF_type_node
,
8110 tree_cons (NULL_TREE
, float_type_node
,
8111 tree_cons (NULL_TREE
, float_type_node
,
8112 tree_cons (NULL_TREE
,
8114 tree_cons (NULL_TREE
,
8117 /* @@@ the type is bogus */
8118 tree v4sf_ftype_v4sf_pv2si
8119 = build_function_type (V4SF_type_node
,
8120 tree_cons (NULL_TREE
, V4SF_type_node
,
8121 tree_cons (NULL_TREE
, pv2si_type_node
,
8123 tree v4sf_ftype_pv2si_v4sf
8124 = build_function_type (V4SF_type_node
,
8125 tree_cons (NULL_TREE
, V4SF_type_node
,
8126 tree_cons (NULL_TREE
, pv2si_type_node
,
8128 tree void_ftype_pfloat_v4sf
8129 = build_function_type (void_type_node
,
8130 tree_cons (NULL_TREE
, pfloat_type_node
,
8131 tree_cons (NULL_TREE
, V4SF_type_node
,
8133 tree void_ftype_pdi_di
8134 = build_function_type (void_type_node
,
8135 tree_cons (NULL_TREE
, pdi_type_node
,
8136 tree_cons (NULL_TREE
,
8137 long_long_unsigned_type_node
,
8139 /* Normal vector unops. */
8140 tree v4sf_ftype_v4sf
8141 = build_function_type (V4SF_type_node
,
8142 tree_cons (NULL_TREE
, V4SF_type_node
,
8145 /* Normal vector binops. */
8146 tree v4sf_ftype_v4sf_v4sf
8147 = build_function_type (V4SF_type_node
,
8148 tree_cons (NULL_TREE
, V4SF_type_node
,
8149 tree_cons (NULL_TREE
, V4SF_type_node
,
8151 tree v8qi_ftype_v8qi_v8qi
8152 = build_function_type (V8QI_type_node
,
8153 tree_cons (NULL_TREE
, V8QI_type_node
,
8154 tree_cons (NULL_TREE
, V8QI_type_node
,
8156 tree v4hi_ftype_v4hi_v4hi
8157 = build_function_type (V4HI_type_node
,
8158 tree_cons (NULL_TREE
, V4HI_type_node
,
8159 tree_cons (NULL_TREE
, V4HI_type_node
,
8161 tree v2si_ftype_v2si_v2si
8162 = build_function_type (V2SI_type_node
,
8163 tree_cons (NULL_TREE
, V2SI_type_node
,
8164 tree_cons (NULL_TREE
, V2SI_type_node
,
8167 = build_function_type (intTI_type_node
,
8168 tree_cons (NULL_TREE
, intTI_type_node
,
8169 tree_cons (NULL_TREE
, intTI_type_node
,
8172 = build_function_type (long_long_unsigned_type_node
,
8173 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
8174 tree_cons (NULL_TREE
,
8175 long_long_unsigned_type_node
,
8178 /* Add all builtins that are more or less simple operations on two
8180 for (i
= 0, d
= bdesc_2arg
; i
< sizeof (bdesc_2arg
) / sizeof *d
; i
++, d
++)
8182 /* Use one of the operands; the target can have a different mode for
8183 mask-generating compares. */
8184 enum machine_mode mode
;
8189 mode
= insn_data
[d
->icode
].operand
[1].mode
;
8191 if (! TARGET_SSE
&& ! VALID_MMX_REG_MODE (mode
))
8197 type
= v4sf_ftype_v4sf_v4sf
;
8200 type
= v8qi_ftype_v8qi_v8qi
;
8203 type
= v4hi_ftype_v4hi_v4hi
;
8206 type
= v2si_ftype_v2si_v2si
;
8209 type
= ti_ftype_ti_ti
;
8212 type
= di_ftype_di_di
;
8219 /* Override for comparisons. */
8220 if (d
->icode
== CODE_FOR_maskcmpv4sf3
8221 || d
->icode
== CODE_FOR_maskncmpv4sf3
8222 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
8223 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
)
8224 type
= v4si_ftype_v4sf_v4sf
;
8226 def_builtin (d
->name
, type
, d
->code
);
8229 /* Add the remaining MMX insns with somewhat more complicated types. */
8230 def_builtin ("__builtin_ia32_m_from_int", v2si_ftype_int
, IX86_BUILTIN_M_FROM_INT
);
8231 def_builtin ("__builtin_ia32_m_to_int", int_ftype_v2si
, IX86_BUILTIN_M_TO_INT
);
8232 def_builtin ("__builtin_ia32_mmx_zero", di_ftype_void
, IX86_BUILTIN_MMX_ZERO
);
8233 def_builtin ("__builtin_ia32_emms", void_ftype_void
, IX86_BUILTIN_EMMS
);
8234 def_builtin ("__builtin_ia32_ldmxcsr", void_ftype_unsigned
, IX86_BUILTIN_LDMXCSR
);
8235 def_builtin ("__builtin_ia32_stmxcsr", unsigned_ftype_void
, IX86_BUILTIN_STMXCSR
);
8236 def_builtin ("__builtin_ia32_psllw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSLLW
);
8237 def_builtin ("__builtin_ia32_pslld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSLLD
);
8238 def_builtin ("__builtin_ia32_psllq", di_ftype_di_di
, IX86_BUILTIN_PSLLQ
);
8240 def_builtin ("__builtin_ia32_psrlw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRLW
);
8241 def_builtin ("__builtin_ia32_psrld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRLD
);
8242 def_builtin ("__builtin_ia32_psrlq", di_ftype_di_di
, IX86_BUILTIN_PSRLQ
);
8244 def_builtin ("__builtin_ia32_psraw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRAW
);
8245 def_builtin ("__builtin_ia32_psrad", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRAD
);
8247 def_builtin ("__builtin_ia32_pshufw", v4hi_ftype_v4hi_int
, IX86_BUILTIN_PSHUFW
);
8248 def_builtin ("__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi
, IX86_BUILTIN_PMADDWD
);
8250 /* Everything beyond this point is SSE only. */
8254 /* comi/ucomi insns. */
8255 for (i
= 0, d
= bdesc_comi
; i
< sizeof (bdesc_comi
) / sizeof *d
; i
++, d
++)
8256 def_builtin (d
->name
, int_ftype_v4sf_v4sf
, d
->code
);
8258 def_builtin ("__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKSSWB
);
8259 def_builtin ("__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si
, IX86_BUILTIN_PACKSSDW
);
8260 def_builtin ("__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKUSWB
);
8262 def_builtin ("__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si
, IX86_BUILTIN_CVTPI2PS
);
8263 def_builtin ("__builtin_ia32_cvtps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTPS2PI
);
8264 def_builtin ("__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int
, IX86_BUILTIN_CVTSI2SS
);
8265 def_builtin ("__builtin_ia32_cvtss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTSS2SI
);
8266 def_builtin ("__builtin_ia32_cvttps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTTPS2PI
);
8267 def_builtin ("__builtin_ia32_cvttss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTTSS2SI
);
8269 def_builtin ("__builtin_ia32_pextrw", int_ftype_v4hi_int
, IX86_BUILTIN_PEXTRW
);
8270 def_builtin ("__builtin_ia32_pinsrw", v4hi_ftype_v4hi_int_int
, IX86_BUILTIN_PINSRW
);
8272 def_builtin ("__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar
, IX86_BUILTIN_MASKMOVQ
);
8274 def_builtin ("__builtin_ia32_loadaps", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADAPS
);
8275 def_builtin ("__builtin_ia32_loadups", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADUPS
);
8276 def_builtin ("__builtin_ia32_loadss", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADSS
);
8277 def_builtin ("__builtin_ia32_storeaps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREAPS
);
8278 def_builtin ("__builtin_ia32_storeups", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREUPS
);
8279 def_builtin ("__builtin_ia32_storess", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STORESS
);
8281 def_builtin ("__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADHPS
);
8282 def_builtin ("__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADLPS
);
8283 def_builtin ("__builtin_ia32_storehps", v4sf_ftype_pv2si_v4sf
, IX86_BUILTIN_STOREHPS
);
8284 def_builtin ("__builtin_ia32_storelps", v4sf_ftype_pv2si_v4sf
, IX86_BUILTIN_STORELPS
);
8286 def_builtin ("__builtin_ia32_movmskps", int_ftype_v4sf
, IX86_BUILTIN_MOVMSKPS
);
8287 def_builtin ("__builtin_ia32_pmovmskb", int_ftype_v8qi
, IX86_BUILTIN_PMOVMSKB
);
8288 def_builtin ("__builtin_ia32_movntps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_MOVNTPS
);
8289 def_builtin ("__builtin_ia32_movntq", void_ftype_pdi_di
, IX86_BUILTIN_MOVNTQ
);
8291 def_builtin ("__builtin_ia32_sfence", void_ftype_void
, IX86_BUILTIN_SFENCE
);
8292 def_builtin ("__builtin_ia32_prefetch", void_ftype_pchar_int
, IX86_BUILTIN_PREFETCH
);
8294 def_builtin ("__builtin_ia32_psadbw", v4hi_ftype_v8qi_v8qi
, IX86_BUILTIN_PSADBW
);
8296 def_builtin ("__builtin_ia32_rcpps", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPPS
);
8297 def_builtin ("__builtin_ia32_rcpss", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPSS
);
8298 def_builtin ("__builtin_ia32_rsqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTPS
);
8299 def_builtin ("__builtin_ia32_rsqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTSS
);
8300 def_builtin ("__builtin_ia32_sqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTPS
);
8301 def_builtin ("__builtin_ia32_sqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTSS
);
8303 def_builtin ("__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int
, IX86_BUILTIN_SHUFPS
);
8305 /* Composite intrinsics. */
8306 def_builtin ("__builtin_ia32_setps1", v4sf_ftype_float
, IX86_BUILTIN_SETPS1
);
8307 def_builtin ("__builtin_ia32_setps", v4sf_ftype_float_float_float_float
, IX86_BUILTIN_SETPS
);
8308 def_builtin ("__builtin_ia32_setzerops", ti_ftype_void
, IX86_BUILTIN_CLRPS
);
8309 def_builtin ("__builtin_ia32_loadps1", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADPS1
);
8310 def_builtin ("__builtin_ia32_loadrps", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADRPS
);
8311 def_builtin ("__builtin_ia32_storeps1", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREPS1
);
8312 def_builtin ("__builtin_ia32_storerps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STORERPS
);
8315 /* Errors in the source file can cause expand_expr to return const0_rtx
8316 where we expect a vector. To avoid crashing, use one of the vector
8317 clear instructions. */
8319 safe_vector_operand (x
, mode
)
8321 enum machine_mode mode
;
8323 if (x
!= const0_rtx
)
8325 x
= gen_reg_rtx (mode
);
8327 if (VALID_MMX_REG_MODE (mode
))
8328 emit_insn (gen_mmx_clrdi (mode
== DImode
? x
8329 : gen_rtx_SUBREG (DImode
, x
, 0)));
8331 emit_insn (gen_sse_clrti (mode
== TImode
? x
8332 : gen_rtx_SUBREG (TImode
, x
, 0)));
8336 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
8339 ix86_expand_binop_builtin (icode
, arglist
, target
)
8340 enum insn_code icode
;
8345 tree arg0
= TREE_VALUE (arglist
);
8346 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8347 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8348 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8349 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8350 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8351 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
8353 if (VECTOR_MODE_P (mode0
))
8354 op0
= safe_vector_operand (op0
, mode0
);
8355 if (VECTOR_MODE_P (mode1
))
8356 op1
= safe_vector_operand (op1
, mode1
);
8359 || GET_MODE (target
) != tmode
8360 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8361 target
= gen_reg_rtx (tmode
);
8363 /* In case the insn wants input operands in modes different from
8364 the result, abort. */
8365 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
8368 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8369 op0
= copy_to_mode_reg (mode0
, op0
);
8370 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8371 op1
= copy_to_mode_reg (mode1
, op1
);
8373 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8380 /* Subroutine of ix86_expand_builtin to take care of stores. */
8383 ix86_expand_store_builtin (icode
, arglist
, shuffle
)
8384 enum insn_code icode
;
8389 tree arg0
= TREE_VALUE (arglist
);
8390 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8391 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8392 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8393 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8394 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
8396 if (VECTOR_MODE_P (mode1
))
8397 op1
= safe_vector_operand (op1
, mode1
);
8399 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8400 if (shuffle
>= 0 || ! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8401 op1
= copy_to_mode_reg (mode1
, op1
);
8403 emit_insn (gen_sse_shufps (op1
, op1
, op1
, GEN_INT (shuffle
)));
8404 pat
= GEN_FCN (icode
) (op0
, op1
);
8410 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
8413 ix86_expand_unop_builtin (icode
, arglist
, target
, do_load
)
8414 enum insn_code icode
;
8420 tree arg0
= TREE_VALUE (arglist
);
8421 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8422 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8423 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8426 || GET_MODE (target
) != tmode
8427 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8428 target
= gen_reg_rtx (tmode
);
8430 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8433 if (VECTOR_MODE_P (mode0
))
8434 op0
= safe_vector_operand (op0
, mode0
);
8436 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8437 op0
= copy_to_mode_reg (mode0
, op0
);
8440 pat
= GEN_FCN (icode
) (target
, op0
);
8447 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
8448 sqrtss, rsqrtss, rcpss. */
8451 ix86_expand_unop1_builtin (icode
, arglist
, target
)
8452 enum insn_code icode
;
8457 tree arg0
= TREE_VALUE (arglist
);
8458 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8459 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8460 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
8463 || GET_MODE (target
) != tmode
8464 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8465 target
= gen_reg_rtx (tmode
);
8467 if (VECTOR_MODE_P (mode0
))
8468 op0
= safe_vector_operand (op0
, mode0
);
8470 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8471 op0
= copy_to_mode_reg (mode0
, op0
);
8473 pat
= GEN_FCN (icode
) (target
, op0
, op0
);
8480 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
8483 ix86_expand_sse_compare (d
, arglist
, target
)
8484 struct builtin_description
*d
;
8489 tree arg0
= TREE_VALUE (arglist
);
8490 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8491 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8492 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8494 enum machine_mode tmode
= insn_data
[d
->icode
].operand
[0].mode
;
8495 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[1].mode
;
8496 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[2].mode
;
8497 enum rtx_code comparison
= d
->comparison
;
8499 if (VECTOR_MODE_P (mode0
))
8500 op0
= safe_vector_operand (op0
, mode0
);
8501 if (VECTOR_MODE_P (mode1
))
8502 op1
= safe_vector_operand (op1
, mode1
);
8504 /* Swap operands if we have a comparison that isn't available in
8508 target
= gen_reg_rtx (tmode
);
8509 emit_move_insn (target
, op1
);
8512 comparison
= swap_condition (comparison
);
8515 || GET_MODE (target
) != tmode
8516 || ! (*insn_data
[d
->icode
].operand
[0].predicate
) (target
, tmode
))
8517 target
= gen_reg_rtx (tmode
);
8519 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op0
, mode0
))
8520 op0
= copy_to_mode_reg (mode0
, op0
);
8521 if (! (*insn_data
[d
->icode
].operand
[2].predicate
) (op1
, mode1
))
8522 op1
= copy_to_mode_reg (mode1
, op1
);
8524 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
8525 pat
= GEN_FCN (d
->icode
) (target
, op0
, op1
, op2
);
8532 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
8535 ix86_expand_sse_comi (d
, arglist
, target
)
8536 struct builtin_description
*d
;
8541 tree arg0
= TREE_VALUE (arglist
);
8542 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8543 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8544 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8546 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[0].mode
;
8547 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[1].mode
;
8548 enum rtx_code comparison
= d
->comparison
;
8550 if (VECTOR_MODE_P (mode0
))
8551 op0
= safe_vector_operand (op0
, mode0
);
8552 if (VECTOR_MODE_P (mode1
))
8553 op1
= safe_vector_operand (op1
, mode1
);
8555 /* Swap operands if we have a comparison that isn't available in
8562 comparison
= swap_condition (comparison
);
8565 target
= gen_reg_rtx (SImode
);
8566 emit_move_insn (target
, const0_rtx
);
8567 target
= gen_rtx_SUBREG (QImode
, target
, 0);
8569 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
8570 op0
= copy_to_mode_reg (mode0
, op0
);
8571 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
8572 op1
= copy_to_mode_reg (mode1
, op1
);
8574 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
8575 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
8579 emit_insn (gen_setcc_2 (target
, op2
));
8584 /* Expand an expression EXP that calls a built-in function,
8585 with result going to TARGET if that's convenient
8586 (and in mode MODE if that's convenient).
8587 SUBTARGET may be used as the target for computing one of EXP's operands.
8588 IGNORE is nonzero if the value is to be ignored. */
8591 ix86_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
8594 rtx subtarget ATTRIBUTE_UNUSED
;
8595 enum machine_mode mode ATTRIBUTE_UNUSED
;
8596 int ignore ATTRIBUTE_UNUSED
;
8598 struct builtin_description
*d
;
8600 enum insn_code icode
;
8601 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8602 tree arglist
= TREE_OPERAND (exp
, 1);
8603 tree arg0
, arg1
, arg2
, arg3
;
8604 rtx op0
, op1
, op2
, pat
;
8605 enum machine_mode tmode
, mode0
, mode1
, mode2
;
8606 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8610 case IX86_BUILTIN_EMMS
:
8611 emit_insn (gen_emms ());
8614 case IX86_BUILTIN_SFENCE
:
8615 emit_insn (gen_sfence ());
8618 case IX86_BUILTIN_M_FROM_INT
:
8619 target
= gen_reg_rtx (DImode
);
8620 op0
= expand_expr (TREE_VALUE (arglist
), NULL_RTX
, VOIDmode
, 0);
8621 emit_move_insn (gen_rtx_SUBREG (SImode
, target
, 0), op0
);
8624 case IX86_BUILTIN_M_TO_INT
:
8625 op0
= expand_expr (TREE_VALUE (arglist
), NULL_RTX
, VOIDmode
, 0);
8626 op0
= copy_to_mode_reg (DImode
, op0
);
8627 target
= gen_reg_rtx (SImode
);
8628 emit_move_insn (target
, gen_rtx_SUBREG (SImode
, op0
, 0));
8631 case IX86_BUILTIN_PEXTRW
:
8632 icode
= CODE_FOR_mmx_pextrw
;
8633 arg0
= TREE_VALUE (arglist
);
8634 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8635 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8636 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8637 tmode
= insn_data
[icode
].operand
[0].mode
;
8638 mode0
= insn_data
[icode
].operand
[1].mode
;
8639 mode1
= insn_data
[icode
].operand
[2].mode
;
8641 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8642 op0
= copy_to_mode_reg (mode0
, op0
);
8643 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8645 /* @@@ better error message */
8646 error ("selector must be an immediate");
8650 || GET_MODE (target
) != tmode
8651 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8652 target
= gen_reg_rtx (tmode
);
8653 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8659 case IX86_BUILTIN_PINSRW
:
8660 icode
= CODE_FOR_mmx_pinsrw
;
8661 arg0
= TREE_VALUE (arglist
);
8662 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8663 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8664 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8665 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8666 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
8667 tmode
= insn_data
[icode
].operand
[0].mode
;
8668 mode0
= insn_data
[icode
].operand
[1].mode
;
8669 mode1
= insn_data
[icode
].operand
[2].mode
;
8670 mode2
= insn_data
[icode
].operand
[3].mode
;
8672 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8673 op0
= copy_to_mode_reg (mode0
, op0
);
8674 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8675 op1
= copy_to_mode_reg (mode1
, op1
);
8676 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
8678 /* @@@ better error message */
8679 error ("selector must be an immediate");
8683 || GET_MODE (target
) != tmode
8684 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8685 target
= gen_reg_rtx (tmode
);
8686 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8692 case IX86_BUILTIN_MASKMOVQ
:
8693 icode
= CODE_FOR_mmx_maskmovq
;
8694 /* Note the arg order is different from the operand order. */
8695 arg1
= TREE_VALUE (arglist
);
8696 arg2
= TREE_VALUE (TREE_CHAIN (arglist
));
8697 arg0
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8698 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8699 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8700 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
8701 mode0
= insn_data
[icode
].operand
[0].mode
;
8702 mode1
= insn_data
[icode
].operand
[1].mode
;
8703 mode2
= insn_data
[icode
].operand
[2].mode
;
8705 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8706 op0
= copy_to_mode_reg (mode0
, op0
);
8707 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8708 op1
= copy_to_mode_reg (mode1
, op1
);
8709 if (! (*insn_data
[icode
].operand
[2].predicate
) (op2
, mode2
))
8710 op2
= copy_to_mode_reg (mode2
, op2
);
8711 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
8717 case IX86_BUILTIN_SQRTSS
:
8718 return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv4sf2
, arglist
, target
);
8719 case IX86_BUILTIN_RSQRTSS
:
8720 return ix86_expand_unop1_builtin (CODE_FOR_vmrsqrtv4sf2
, arglist
, target
);
8721 case IX86_BUILTIN_RCPSS
:
8722 return ix86_expand_unop1_builtin (CODE_FOR_vmrcpv4sf2
, arglist
, target
);
8724 case IX86_BUILTIN_LOADAPS
:
8725 return ix86_expand_unop_builtin (CODE_FOR_sse_movaps
, arglist
, target
, 1);
8727 case IX86_BUILTIN_LOADUPS
:
8728 return ix86_expand_unop_builtin (CODE_FOR_sse_movups
, arglist
, target
, 1);
8730 case IX86_BUILTIN_STOREAPS
:
8731 return ix86_expand_store_builtin (CODE_FOR_sse_movaps
, arglist
, -1);
8732 case IX86_BUILTIN_STOREUPS
:
8733 return ix86_expand_store_builtin (CODE_FOR_sse_movups
, arglist
, -1);
8735 case IX86_BUILTIN_LOADSS
:
8736 return ix86_expand_unop_builtin (CODE_FOR_sse_loadss
, arglist
, target
, 1);
8738 case IX86_BUILTIN_STORESS
:
8739 return ix86_expand_store_builtin (CODE_FOR_sse_storess
, arglist
, -1);
8741 case IX86_BUILTIN_LOADHPS
:
8742 case IX86_BUILTIN_LOADLPS
:
8743 icode
= (fcode
== IX86_BUILTIN_LOADHPS
8744 ? CODE_FOR_sse_movhps
: CODE_FOR_sse_movlps
);
8745 arg0
= TREE_VALUE (arglist
);
8746 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8747 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8748 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8749 tmode
= insn_data
[icode
].operand
[0].mode
;
8750 mode0
= insn_data
[icode
].operand
[1].mode
;
8751 mode1
= insn_data
[icode
].operand
[2].mode
;
8753 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8754 op0
= copy_to_mode_reg (mode0
, op0
);
8755 op1
= gen_rtx_MEM (mode1
, copy_to_mode_reg (Pmode
, op1
));
8757 || GET_MODE (target
) != tmode
8758 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8759 target
= gen_reg_rtx (tmode
);
8760 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8766 case IX86_BUILTIN_STOREHPS
:
8767 case IX86_BUILTIN_STORELPS
:
8768 icode
= (fcode
== IX86_BUILTIN_STOREHPS
8769 ? CODE_FOR_sse_movhps
: CODE_FOR_sse_movlps
);
8770 arg0
= TREE_VALUE (arglist
);
8771 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8772 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8773 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8774 mode0
= insn_data
[icode
].operand
[1].mode
;
8775 mode1
= insn_data
[icode
].operand
[2].mode
;
8777 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
8778 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8779 op1
= copy_to_mode_reg (mode1
, op1
);
8781 pat
= GEN_FCN (icode
) (op0
, op0
, op1
);
8787 case IX86_BUILTIN_MOVNTPS
:
8788 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf
, arglist
, -1);
8789 case IX86_BUILTIN_MOVNTQ
:
8790 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi
, arglist
, -1);
8792 case IX86_BUILTIN_LDMXCSR
:
8793 op0
= expand_expr (TREE_VALUE (arglist
), NULL_RTX
, VOIDmode
, 0);
8794 target
= assign_386_stack_local (SImode
, 0);
8795 emit_move_insn (target
, op0
);
8796 emit_insn (gen_ldmxcsr (target
));
8799 case IX86_BUILTIN_STMXCSR
:
8800 target
= assign_386_stack_local (SImode
, 0);
8801 emit_insn (gen_stmxcsr (target
));
8802 return copy_to_mode_reg (SImode
, target
);
8804 case IX86_BUILTIN_PREFETCH
:
8805 icode
= CODE_FOR_prefetch
;
8806 arg0
= TREE_VALUE (arglist
);
8807 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8808 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8809 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8810 mode0
= insn_data
[icode
].operand
[0].mode
;
8811 mode1
= insn_data
[icode
].operand
[1].mode
;
8813 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
8815 /* @@@ better error message */
8816 error ("selector must be an immediate");
8820 op0
= copy_to_mode_reg (Pmode
, op0
);
8821 pat
= GEN_FCN (icode
) (op0
, op1
);
8827 case IX86_BUILTIN_SHUFPS
:
8828 icode
= CODE_FOR_sse_shufps
;
8829 arg0
= TREE_VALUE (arglist
);
8830 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8831 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8832 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8833 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8834 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
8835 tmode
= insn_data
[icode
].operand
[0].mode
;
8836 mode0
= insn_data
[icode
].operand
[1].mode
;
8837 mode1
= insn_data
[icode
].operand
[2].mode
;
8838 mode2
= insn_data
[icode
].operand
[3].mode
;
8840 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8841 op0
= copy_to_mode_reg (mode0
, op0
);
8842 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
8843 op1
= copy_to_mode_reg (mode1
, op1
);
8844 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
8846 /* @@@ better error message */
8847 error ("mask must be an immediate");
8851 || GET_MODE (target
) != tmode
8852 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8853 target
= gen_reg_rtx (tmode
);
8854 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8860 case IX86_BUILTIN_PSHUFW
:
8861 icode
= CODE_FOR_mmx_pshufw
;
8862 arg0
= TREE_VALUE (arglist
);
8863 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8864 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
8865 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
8866 tmode
= insn_data
[icode
].operand
[0].mode
;
8867 mode0
= insn_data
[icode
].operand
[2].mode
;
8868 mode1
= insn_data
[icode
].operand
[3].mode
;
8870 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
8871 op0
= copy_to_mode_reg (mode0
, op0
);
8872 if (! (*insn_data
[icode
].operand
[3].predicate
) (op1
, mode1
))
8874 /* @@@ better error message */
8875 error ("mask must be an immediate");
8879 || GET_MODE (target
) != tmode
8880 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8881 target
= gen_reg_rtx (tmode
);
8882 pat
= GEN_FCN (icode
) (target
, target
, op0
, op1
);
8888 /* Composite intrinsics. */
8889 case IX86_BUILTIN_SETPS1
:
8890 target
= assign_386_stack_local (SFmode
, 0);
8891 arg0
= TREE_VALUE (arglist
);
8892 emit_move_insn (change_address (target
, SFmode
, XEXP (target
, 0)),
8893 expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
8894 op0
= gen_reg_rtx (V4SFmode
);
8895 emit_insn (gen_sse_loadss (op0
, change_address (target
, V4SFmode
,
8896 XEXP (target
, 0))));
8897 emit_insn (gen_sse_shufps (op0
, op0
, op0
, GEN_INT (0)));
8900 case IX86_BUILTIN_SETPS
:
8901 target
= assign_386_stack_local (V4SFmode
, 0);
8902 op0
= change_address (target
, SFmode
, XEXP (target
, 0));
8903 arg0
= TREE_VALUE (arglist
);
8904 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8905 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8906 arg3
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist
))));
8907 emit_move_insn (op0
,
8908 expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
8909 emit_move_insn (adj_offsettable_operand (op0
, 4),
8910 expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0));
8911 emit_move_insn (adj_offsettable_operand (op0
, 8),
8912 expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0));
8913 emit_move_insn (adj_offsettable_operand (op0
, 12),
8914 expand_expr (arg3
, NULL_RTX
, VOIDmode
, 0));
8915 op0
= gen_reg_rtx (V4SFmode
);
8916 emit_insn (gen_sse_movaps (op0
, target
));
8919 case IX86_BUILTIN_CLRPS
:
8920 target
= gen_reg_rtx (TImode
);
8921 emit_insn (gen_sse_clrti (target
));
8924 case IX86_BUILTIN_LOADRPS
:
8925 target
= ix86_expand_unop_builtin (CODE_FOR_sse_movaps
, arglist
,
8926 gen_reg_rtx (V4SFmode
), 1);
8927 emit_insn (gen_sse_shufps (target
, target
, target
, GEN_INT (0x1b)));
8930 case IX86_BUILTIN_LOADPS1
:
8931 target
= ix86_expand_unop_builtin (CODE_FOR_sse_loadss
, arglist
,
8932 gen_reg_rtx (V4SFmode
), 1);
8933 emit_insn (gen_sse_shufps (target
, target
, target
, const0_rtx
));
8936 case IX86_BUILTIN_STOREPS1
:
8937 return ix86_expand_store_builtin (CODE_FOR_sse_movaps
, arglist
, 0);
8938 case IX86_BUILTIN_STORERPS
:
8939 return ix86_expand_store_builtin (CODE_FOR_sse_movaps
, arglist
, 0x1B);
8941 case IX86_BUILTIN_MMX_ZERO
:
8942 target
= gen_reg_rtx (DImode
);
8943 emit_insn (gen_mmx_clrdi (target
));
8950 for (i
= 0, d
= bdesc_2arg
; i
< sizeof (bdesc_2arg
) / sizeof *d
; i
++, d
++)
8951 if (d
->code
== fcode
)
8953 /* Compares are treated specially. */
8954 if (d
->icode
== CODE_FOR_maskcmpv4sf3
8955 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
8956 || d
->icode
== CODE_FOR_maskncmpv4sf3
8957 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
)
8958 return ix86_expand_sse_compare (d
, arglist
, target
);
8960 return ix86_expand_binop_builtin (d
->icode
, arglist
, target
);
8963 for (i
= 0, d
= bdesc_1arg
; i
< sizeof (bdesc_1arg
) / sizeof *d
; i
++, d
++)
8964 if (d
->code
== fcode
)
8965 return ix86_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
8967 for (i
= 0, d
= bdesc_comi
; i
< sizeof (bdesc_comi
) / sizeof *d
; i
++, d
++)
8968 if (d
->code
== fcode
)
8969 return ix86_expand_sse_comi (d
, arglist
, target
);
8971 /* @@@ Should really do something sensible here. */
8975 /* Store OPERAND to the memory after reload is completed. This means
8976 that we can't easilly use assign_stack_local. */
8978 ix86_force_to_memory (mode
, operand
)
8979 enum machine_mode mode
;
8982 if (!reload_completed
)
8989 split_di (&operand
, 1, operands
, operands
+1);
8991 gen_rtx_SET (VOIDmode
,
8992 gen_rtx_MEM (SImode
,
8993 gen_rtx_PRE_DEC (Pmode
,
8994 stack_pointer_rtx
)),
8997 gen_rtx_SET (VOIDmode
,
8998 gen_rtx_MEM (SImode
,
8999 gen_rtx_PRE_DEC (Pmode
,
9000 stack_pointer_rtx
)),
9005 /* It is better to store HImodes as SImodes. */
9006 if (!TARGET_PARTIAL_REG_STALL
)
9007 operand
= gen_lowpart (SImode
, operand
);
9011 gen_rtx_SET (VOIDmode
,
9012 gen_rtx_MEM (GET_MODE (operand
),
9013 gen_rtx_PRE_DEC (SImode
,
9014 stack_pointer_rtx
)),
9020 return gen_rtx_MEM (mode
, stack_pointer_rtx
);
9023 /* Free operand from the memory. */
9025 ix86_free_from_memory (mode
)
9026 enum machine_mode mode
;
9028 /* Use LEA to deallocate stack space. In peephole2 it will be converted
9029 to pop or add instruction if registers are available. */
9030 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9031 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
9032 GEN_INT (mode
== DImode
9034 : mode
== HImode
&& TARGET_PARTIAL_REG_STALL
9039 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
9040 QImode must go into class Q_REGS.
9041 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
9042 movdf to do mem-to-mem moves through integer regs. */
9044 ix86_preferred_reload_class (x
, class)
9046 enum reg_class
class;
9048 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != VOIDmode
)
9050 /* SSE can't load any constant directly yet. */
9051 if (SSE_CLASS_P (class))
9053 /* Floats can load 0 and 1. */
9054 if (MAYBE_FLOAT_CLASS_P (class) && standard_80387_constant_p (x
))
9056 /* Limit class to non-SSE. Use GENERAL_REGS if possible. */
9057 if (MAYBE_SSE_CLASS_P (class))
9058 return (reg_class_subset_p (class, GENERAL_REGS
)
9059 ? GENERAL_REGS
: FLOAT_REGS
);
9063 /* General regs can load everything. */
9064 if (reg_class_subset_p (class, GENERAL_REGS
))
9065 return GENERAL_REGS
;
9066 /* In case we haven't resolved FLOAT or SSE yet, give up. */
9067 if (MAYBE_FLOAT_CLASS_P (class) || MAYBE_SSE_CLASS_P (class))
9070 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x
))
9072 if (GET_MODE (x
) == QImode
&& ! reg_class_subset_p (class, Q_REGS
))
9077 /* If we are copying between general and FP registers, we need a memory
9078 location. The same is true for SSE and MMX registers.
9080 The macro can't work reliably when one of the CLASSES is class containing
9081 registers from multiple units (SSE, MMX, integer). We avoid this by never
9082 combining those units in single alternative in the machine description.
9083 Ensure that this constraint holds to avoid unexpected surprises.
9085 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
9086 enforce these sanity checks. */
9088 ix86_secondary_memory_needed (class1
, class2
, mode
, strict
)
9089 enum reg_class class1
, class2
;
9090 enum machine_mode mode
;
9093 if (MAYBE_FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class1
)
9094 || MAYBE_FLOAT_CLASS_P (class2
) != FLOAT_CLASS_P (class2
)
9095 || MAYBE_SSE_CLASS_P (class1
) != SSE_CLASS_P (class1
)
9096 || MAYBE_SSE_CLASS_P (class2
) != SSE_CLASS_P (class2
)
9097 || MAYBE_MMX_CLASS_P (class1
) != MMX_CLASS_P (class1
)
9098 || MAYBE_MMX_CLASS_P (class2
) != MMX_CLASS_P (class2
))
9105 return (FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class2
)
9106 || (SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
)
9107 && (mode
) != SImode
)
9108 || (MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
)
9109 && (mode
) != SImode
));
9111 /* Return the cost of moving data from a register in class CLASS1 to
9112 one in class CLASS2.
9114 It is not required that the cost always equal 2 when FROM is the same as TO;
9115 on some machines it is expensive to move between registers if they are not
9116 general registers. */
9118 ix86_register_move_cost (mode
, class1
, class2
)
9119 enum machine_mode mode
;
9120 enum reg_class class1
, class2
;
9122 /* In case we require secondary memory, compute cost of the store followed
9123 by load. In case of copying from general_purpose_register we may emit
9124 multiple stores followed by single load causing memory size mismatch
9125 stall. Count this as arbitarily high cost of 20. */
9126 if (ix86_secondary_memory_needed (class1
, class2
, mode
, 0))
9128 if (CLASS_MAX_NREGS (class1
, mode
) > CLASS_MAX_NREGS (class2
, mode
))
9130 return (MEMORY_MOVE_COST (mode
, class1
, 0)
9131 + MEMORY_MOVE_COST (mode
, class2
, 1));
9133 /* Moves between SSE/MMX and integer unit are expensive.
9134 ??? We should make this cost CPU specific. */
9135 if (MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
)
9136 || SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
))
9137 return ix86_cost
->mmxsse_to_integer
;
9138 if (MAYBE_FLOAT_CLASS_P (class1
))
9139 return ix86_cost
->fp_move
;
9140 if (MAYBE_SSE_CLASS_P (class1
))
9141 return ix86_cost
->sse_move
;
9142 if (MAYBE_MMX_CLASS_P (class1
))
9143 return ix86_cost
->mmx_move
;
9147 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
9149 ix86_hard_regno_mode_ok (regno
, mode
)
9151 enum machine_mode mode
;
9153 /* Flags and only flags can only hold CCmode values. */
9154 if (CC_REGNO_P (regno
))
9155 return GET_MODE_CLASS (mode
) == MODE_CC
;
9156 if (GET_MODE_CLASS (mode
) == MODE_CC
9157 || GET_MODE_CLASS (mode
) == MODE_RANDOM
9158 || GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
9160 if (FP_REGNO_P (regno
))
9161 return VALID_FP_MODE_P (mode
);
9162 if (SSE_REGNO_P (regno
))
9163 return VALID_SSE_REG_MODE (mode
);
9164 if (MMX_REGNO_P (regno
))
9165 return VALID_MMX_REG_MODE (mode
);
9166 /* We handle both integer and floats in the general purpose registers.
9167 In future we should be able to handle vector modes as well. */
9168 if (!VALID_INT_MODE_P (mode
) && !VALID_FP_MODE_P (mode
))
9170 /* Take care for QImode values - they can be in non-QI regs, but then
9171 they do cause partial register stalls. */
9172 if (regno
< 4 || mode
!= QImode
)
9174 return reload_in_progress
|| reload_completed
|| !TARGET_PARTIAL_REG_STALL
;
9177 /* Return the cost of moving data of mode M between a
9178 register and memory. A value of 2 is the default; this cost is
9179 relative to those in `REGISTER_MOVE_COST'.
9181 If moving between registers and memory is more expensive than
9182 between two registers, you should define this macro to express the
9185 Model also increased moving costs of QImode registers in non
9189 ix86_memory_move_cost (mode
, class, in
)
9190 enum machine_mode mode
;
9191 enum reg_class
class;
9194 if (FLOAT_CLASS_P (class))
9212 return in
? ix86_cost
->fp_load
[index
] : ix86_cost
->fp_store
[index
];
9214 if (SSE_CLASS_P (class))
9217 switch (GET_MODE_SIZE (mode
))
9231 return in
? ix86_cost
->sse_load
[index
] : ix86_cost
->sse_store
[index
];
9233 if (MMX_CLASS_P (class))
9236 switch (GET_MODE_SIZE (mode
))
9247 return in
? ix86_cost
->mmx_load
[index
] : ix86_cost
->mmx_store
[index
];
9249 switch (GET_MODE_SIZE (mode
))
9253 return (Q_CLASS_P (class) ? ix86_cost
->int_load
[0]
9254 : ix86_cost
->movzbl_load
);
9256 return (Q_CLASS_P (class) ? ix86_cost
->int_store
[0]
9257 : ix86_cost
->int_store
[0] + 4);
9260 return in
? ix86_cost
->int_load
[1] : ix86_cost
->int_store
[1];
9262 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
9265 return ((in
? ix86_cost
->int_load
[2] : ix86_cost
->int_store
[2])
9266 * (int) GET_MODE_SIZE (mode
) / 4);