1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "basic-block.h"
44 #include "target-def.h"
45 #include "langhooks.h"
47 #ifndef CHECK_STACK_LIMIT
48 #define CHECK_STACK_LIMIT (-1)
51 /* Processor costs (relative to an add) */
53 struct processor_costs size_cost
= { /* costs for tunning for size */
54 2, /* cost of an add instruction */
55 3, /* cost of a lea instruction */
56 2, /* variable shift costs */
57 3, /* constant shift costs */
58 3, /* cost of starting a multiply */
59 0, /* cost of multiply per each bit set */
60 3, /* cost of a divide/mod */
61 3, /* cost of movsx */
62 3, /* cost of movzx */
65 2, /* cost for loading QImode using movzbl */
66 {2, 2, 2}, /* cost of loading integer registers
67 in QImode, HImode and SImode.
68 Relative to reg-reg move (2). */
69 {2, 2, 2}, /* cost of storing integer registers */
70 2, /* cost of reg,reg fld/fst */
71 {2, 2, 2}, /* cost of loading fp registers
72 in SFmode, DFmode and XFmode */
73 {2, 2, 2}, /* cost of loading integer registers */
74 3, /* cost of moving MMX register */
75 {3, 3}, /* cost of loading MMX registers
76 in SImode and DImode */
77 {3, 3}, /* cost of storing MMX registers
78 in SImode and DImode */
79 3, /* cost of moving SSE register */
80 {3, 3, 3}, /* cost of loading SSE registers
81 in SImode, DImode and TImode */
82 {3, 3, 3}, /* cost of storing SSE registers
83 in SImode, DImode and TImode */
84 3, /* MMX or SSE register to integer */
85 0, /* size of prefetch block */
86 0, /* number of parallel prefetches */
88 /* Processor costs (relative to an add) */
90 struct processor_costs i386_cost
= { /* 386 specific costs */
91 1, /* cost of an add instruction */
92 1, /* cost of a lea instruction */
93 3, /* variable shift costs */
94 2, /* constant shift costs */
95 6, /* cost of starting a multiply */
96 1, /* cost of multiply per each bit set */
97 23, /* cost of a divide/mod */
98 3, /* cost of movsx */
99 2, /* cost of movzx */
100 15, /* "large" insn */
102 4, /* cost for loading QImode using movzbl */
103 {2, 4, 2}, /* cost of loading integer registers
104 in QImode, HImode and SImode.
105 Relative to reg-reg move (2). */
106 {2, 4, 2}, /* cost of storing integer registers */
107 2, /* cost of reg,reg fld/fst */
108 {8, 8, 8}, /* cost of loading fp registers
109 in SFmode, DFmode and XFmode */
110 {8, 8, 8}, /* cost of loading integer registers */
111 2, /* cost of moving MMX register */
112 {4, 8}, /* cost of loading MMX registers
113 in SImode and DImode */
114 {4, 8}, /* cost of storing MMX registers
115 in SImode and DImode */
116 2, /* cost of moving SSE register */
117 {4, 8, 16}, /* cost of loading SSE registers
118 in SImode, DImode and TImode */
119 {4, 8, 16}, /* cost of storing SSE registers
120 in SImode, DImode and TImode */
121 3, /* MMX or SSE register to integer */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
127 struct processor_costs i486_cost
= { /* 486 specific costs */
128 1, /* cost of an add instruction */
129 1, /* cost of a lea instruction */
130 3, /* variable shift costs */
131 2, /* constant shift costs */
132 12, /* cost of starting a multiply */
133 1, /* cost of multiply per each bit set */
134 40, /* cost of a divide/mod */
135 3, /* cost of movsx */
136 2, /* cost of movzx */
137 15, /* "large" insn */
139 4, /* cost for loading QImode using movzbl */
140 {2, 4, 2}, /* cost of loading integer registers
141 in QImode, HImode and SImode.
142 Relative to reg-reg move (2). */
143 {2, 4, 2}, /* cost of storing integer registers */
144 2, /* cost of reg,reg fld/fst */
145 {8, 8, 8}, /* cost of loading fp registers
146 in SFmode, DFmode and XFmode */
147 {8, 8, 8}, /* cost of loading integer registers */
148 2, /* cost of moving MMX register */
149 {4, 8}, /* cost of loading MMX registers
150 in SImode and DImode */
151 {4, 8}, /* cost of storing MMX registers
152 in SImode and DImode */
153 2, /* cost of moving SSE register */
154 {4, 8, 16}, /* cost of loading SSE registers
155 in SImode, DImode and TImode */
156 {4, 8, 16}, /* cost of storing SSE registers
157 in SImode, DImode and TImode */
158 3, /* MMX or SSE register to integer */
159 0, /* size of prefetch block */
160 0, /* number of parallel prefetches */
164 struct processor_costs pentium_cost
= {
165 1, /* cost of an add instruction */
166 1, /* cost of a lea instruction */
167 4, /* variable shift costs */
168 1, /* constant shift costs */
169 11, /* cost of starting a multiply */
170 0, /* cost of multiply per each bit set */
171 25, /* cost of a divide/mod */
172 3, /* cost of movsx */
173 2, /* cost of movzx */
174 8, /* "large" insn */
176 6, /* cost for loading QImode using movzbl */
177 {2, 4, 2}, /* cost of loading integer registers
178 in QImode, HImode and SImode.
179 Relative to reg-reg move (2). */
180 {2, 4, 2}, /* cost of storing integer registers */
181 2, /* cost of reg,reg fld/fst */
182 {2, 2, 6}, /* cost of loading fp registers
183 in SFmode, DFmode and XFmode */
184 {4, 4, 6}, /* cost of loading integer registers */
185 8, /* cost of moving MMX register */
186 {8, 8}, /* cost of loading MMX registers
187 in SImode and DImode */
188 {8, 8}, /* cost of storing MMX registers
189 in SImode and DImode */
190 2, /* cost of moving SSE register */
191 {4, 8, 16}, /* cost of loading SSE registers
192 in SImode, DImode and TImode */
193 {4, 8, 16}, /* cost of storing SSE registers
194 in SImode, DImode and TImode */
195 3, /* MMX or SSE register to integer */
196 0, /* size of prefetch block */
197 0, /* number of parallel prefetches */
201 struct processor_costs pentiumpro_cost
= {
202 1, /* cost of an add instruction */
203 1, /* cost of a lea instruction */
204 1, /* variable shift costs */
205 1, /* constant shift costs */
206 4, /* cost of starting a multiply */
207 0, /* cost of multiply per each bit set */
208 17, /* cost of a divide/mod */
209 1, /* cost of movsx */
210 1, /* cost of movzx */
211 8, /* "large" insn */
213 2, /* cost for loading QImode using movzbl */
214 {4, 4, 4}, /* cost of loading integer registers
215 in QImode, HImode and SImode.
216 Relative to reg-reg move (2). */
217 {2, 2, 2}, /* cost of storing integer registers */
218 2, /* cost of reg,reg fld/fst */
219 {2, 2, 6}, /* cost of loading fp registers
220 in SFmode, DFmode and XFmode */
221 {4, 4, 6}, /* cost of loading integer registers */
222 2, /* cost of moving MMX register */
223 {2, 2}, /* cost of loading MMX registers
224 in SImode and DImode */
225 {2, 2}, /* cost of storing MMX registers
226 in SImode and DImode */
227 2, /* cost of moving SSE register */
228 {2, 2, 8}, /* cost of loading SSE registers
229 in SImode, DImode and TImode */
230 {2, 2, 8}, /* cost of storing SSE registers
231 in SImode, DImode and TImode */
232 3, /* MMX or SSE register to integer */
233 32, /* size of prefetch block */
234 6, /* number of parallel prefetches */
238 struct processor_costs k6_cost
= {
239 1, /* cost of an add instruction */
240 2, /* cost of a lea instruction */
241 1, /* variable shift costs */
242 1, /* constant shift costs */
243 3, /* cost of starting a multiply */
244 0, /* cost of multiply per each bit set */
245 18, /* cost of a divide/mod */
246 2, /* cost of movsx */
247 2, /* cost of movzx */
248 8, /* "large" insn */
250 3, /* cost for loading QImode using movzbl */
251 {4, 5, 4}, /* cost of loading integer registers
252 in QImode, HImode and SImode.
253 Relative to reg-reg move (2). */
254 {2, 3, 2}, /* cost of storing integer registers */
255 4, /* cost of reg,reg fld/fst */
256 {6, 6, 6}, /* cost of loading fp registers
257 in SFmode, DFmode and XFmode */
258 {4, 4, 4}, /* cost of loading integer registers */
259 2, /* cost of moving MMX register */
260 {2, 2}, /* cost of loading MMX registers
261 in SImode and DImode */
262 {2, 2}, /* cost of storing MMX registers
263 in SImode and DImode */
264 2, /* cost of moving SSE register */
265 {2, 2, 8}, /* cost of loading SSE registers
266 in SImode, DImode and TImode */
267 {2, 2, 8}, /* cost of storing SSE registers
268 in SImode, DImode and TImode */
269 6, /* MMX or SSE register to integer */
270 32, /* size of prefetch block */
271 1, /* number of parallel prefetches */
275 struct processor_costs athlon_cost
= {
276 1, /* cost of an add instruction */
277 2, /* cost of a lea instruction */
278 1, /* variable shift costs */
279 1, /* constant shift costs */
280 5, /* cost of starting a multiply */
281 0, /* cost of multiply per each bit set */
282 42, /* cost of a divide/mod */
283 1, /* cost of movsx */
284 1, /* cost of movzx */
285 8, /* "large" insn */
287 4, /* cost for loading QImode using movzbl */
288 {4, 5, 4}, /* cost of loading integer registers
289 in QImode, HImode and SImode.
290 Relative to reg-reg move (2). */
291 {2, 3, 2}, /* cost of storing integer registers */
292 4, /* cost of reg,reg fld/fst */
293 {6, 6, 20}, /* cost of loading fp registers
294 in SFmode, DFmode and XFmode */
295 {4, 4, 16}, /* cost of loading integer registers */
296 2, /* cost of moving MMX register */
297 {2, 2}, /* cost of loading MMX registers
298 in SImode and DImode */
299 {2, 2}, /* cost of storing MMX registers
300 in SImode and DImode */
301 2, /* cost of moving SSE register */
302 {2, 2, 8}, /* cost of loading SSE registers
303 in SImode, DImode and TImode */
304 {2, 2, 8}, /* cost of storing SSE registers
305 in SImode, DImode and TImode */
306 6, /* MMX or SSE register to integer */
307 64, /* size of prefetch block */
308 6, /* number of parallel prefetches */
312 struct processor_costs pentium4_cost
= {
313 1, /* cost of an add instruction */
314 1, /* cost of a lea instruction */
315 8, /* variable shift costs */
316 8, /* constant shift costs */
317 30, /* cost of starting a multiply */
318 0, /* cost of multiply per each bit set */
319 112, /* cost of a divide/mod */
320 1, /* cost of movsx */
321 1, /* cost of movzx */
322 16, /* "large" insn */
324 2, /* cost for loading QImode using movzbl */
325 {4, 5, 4}, /* cost of loading integer registers
326 in QImode, HImode and SImode.
327 Relative to reg-reg move (2). */
328 {2, 3, 2}, /* cost of storing integer registers */
329 2, /* cost of reg,reg fld/fst */
330 {2, 2, 6}, /* cost of loading fp registers
331 in SFmode, DFmode and XFmode */
332 {4, 4, 6}, /* cost of loading integer registers */
333 2, /* cost of moving MMX register */
334 {2, 2}, /* cost of loading MMX registers
335 in SImode and DImode */
336 {2, 2}, /* cost of storing MMX registers
337 in SImode and DImode */
338 12, /* cost of moving SSE register */
339 {12, 12, 12}, /* cost of loading SSE registers
340 in SImode, DImode and TImode */
341 {2, 2, 8}, /* cost of storing SSE registers
342 in SImode, DImode and TImode */
343 10, /* MMX or SSE register to integer */
344 64, /* size of prefetch block */
345 6, /* number of parallel prefetches */
348 const struct processor_costs
*ix86_cost
= &pentium_cost
;
350 /* Processor feature/optimization bitmasks. */
351 #define m_386 (1<<PROCESSOR_I386)
352 #define m_486 (1<<PROCESSOR_I486)
353 #define m_PENT (1<<PROCESSOR_PENTIUM)
354 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
355 #define m_K6 (1<<PROCESSOR_K6)
356 #define m_ATHLON (1<<PROCESSOR_ATHLON)
357 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
359 const int x86_use_leave
= m_386
| m_K6
| m_ATHLON
;
360 const int x86_push_memory
= m_386
| m_K6
| m_ATHLON
| m_PENT4
;
361 const int x86_zero_extend_with_and
= m_486
| m_PENT
;
362 const int x86_movx
= m_ATHLON
| m_PPRO
| m_PENT4
/* m_386 | m_K6 */;
363 const int x86_double_with_add
= ~m_386
;
364 const int x86_use_bit_test
= m_386
;
365 const int x86_unroll_strlen
= m_486
| m_PENT
| m_PPRO
| m_ATHLON
| m_K6
;
366 const int x86_cmove
= m_PPRO
| m_ATHLON
| m_PENT4
;
367 const int x86_3dnow_a
= m_ATHLON
;
368 const int x86_deep_branch
= m_PPRO
| m_K6
| m_ATHLON
| m_PENT4
;
369 const int x86_branch_hints
= m_PENT4
;
370 const int x86_use_sahf
= m_PPRO
| m_K6
| m_PENT4
;
371 const int x86_partial_reg_stall
= m_PPRO
;
372 const int x86_use_loop
= m_K6
;
373 const int x86_use_fiop
= ~(m_PPRO
| m_ATHLON
| m_PENT
);
374 const int x86_use_mov0
= m_K6
;
375 const int x86_use_cltd
= ~(m_PENT
| m_K6
);
376 const int x86_read_modify_write
= ~m_PENT
;
377 const int x86_read_modify
= ~(m_PENT
| m_PPRO
);
378 const int x86_split_long_moves
= m_PPRO
;
379 const int x86_promote_QImode
= m_K6
| m_PENT
| m_386
| m_486
;
380 const int x86_single_stringop
= m_386
| m_PENT4
;
381 const int x86_qimode_math
= ~(0);
382 const int x86_promote_qi_regs
= 0;
383 const int x86_himode_math
= ~(m_PPRO
);
384 const int x86_promote_hi_regs
= m_PPRO
;
385 const int x86_sub_esp_4
= m_ATHLON
| m_PPRO
| m_PENT4
;
386 const int x86_sub_esp_8
= m_ATHLON
| m_PPRO
| m_386
| m_486
| m_PENT4
;
387 const int x86_add_esp_4
= m_ATHLON
| m_K6
| m_PENT4
;
388 const int x86_add_esp_8
= m_ATHLON
| m_PPRO
| m_K6
| m_386
| m_486
| m_PENT4
;
389 const int x86_integer_DFmode_moves
= ~(m_ATHLON
| m_PENT4
);
390 const int x86_partial_reg_dependency
= m_ATHLON
| m_PENT4
;
391 const int x86_memory_mismatch_stall
= m_ATHLON
| m_PENT4
;
392 const int x86_accumulate_outgoing_args
= m_ATHLON
| m_PENT4
| m_PPRO
;
393 const int x86_prologue_using_move
= m_ATHLON
| m_PENT4
| m_PPRO
;
394 const int x86_epilogue_using_move
= m_ATHLON
| m_PENT4
| m_PPRO
;
395 const int x86_decompose_lea
= m_PENT4
;
396 const int x86_arch_always_fancy_math_387
= m_PENT
|m_PPRO
|m_ATHLON
|m_PENT4
;
398 /* In case the avreage insn count for single function invocation is
399 lower than this constant, emit fast (but longer) prologue and
401 #define FAST_PROLOGUE_INSN_COUNT 30
402 /* Set by prologue expander and used by epilogue expander to determine
404 static int use_fast_prologue_epilogue
;
406 #define AT_BP(MODE) (gen_rtx_MEM ((MODE), hard_frame_pointer_rtx))
408 static const char *const hi_reg_name
[] = HI_REGISTER_NAMES
; /* names for 16 bit regs */
409 static const char *const qi_reg_name
[] = QI_REGISTER_NAMES
; /* names for 8 bit regs (low) */
410 static const char *const qi_high_reg_name
[] = QI_HIGH_REGISTER_NAMES
; /* names for 8 bit regs (high) */
412 /* Array of the smallest class containing reg number REGNO, indexed by
413 REGNO. Used by REGNO_REG_CLASS in i386.h. */
415 enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
] =
418 AREG
, DREG
, CREG
, BREG
,
420 SIREG
, DIREG
, NON_Q_REGS
, NON_Q_REGS
,
422 FP_TOP_REG
, FP_SECOND_REG
, FLOAT_REGS
, FLOAT_REGS
,
423 FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
,
426 /* flags, fpsr, dirflag, frame */
427 NO_REGS
, NO_REGS
, NO_REGS
, NON_Q_REGS
,
428 SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
,
430 MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
,
432 NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
,
433 NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
,
434 SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
,
438 /* The "default" register map used in 32bit mode. */
440 int const dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
442 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
443 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
444 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
445 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
446 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
447 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
448 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
451 static int const x86_64_int_parameter_registers
[6] = {5 /*RDI*/, 4 /*RSI*/,
452 1 /*RDX*/, 2 /*RCX*/,
453 FIRST_REX_INT_REG
/*R8 */,
454 FIRST_REX_INT_REG
+ 1 /*R9 */};
455 static int const x86_64_int_return_registers
[4] = {0 /*RAX*/, 1 /*RDI*/, 5, 4};
457 /* The "default" register map used in 64bit mode. */
458 int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
] =
460 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
461 33, 34, 35, 36, 37, 38, 39, 40 /* fp regs */
462 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
463 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
464 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
465 8,9,10,11,12,13,14,15, /* extended integer registers */
466 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
469 /* Define the register numbers to be used in Dwarf debugging information.
470 The SVR4 reference port C compiler uses the following register numbers
471 in its Dwarf output code:
472 0 for %eax (gcc regno = 0)
473 1 for %ecx (gcc regno = 2)
474 2 for %edx (gcc regno = 1)
475 3 for %ebx (gcc regno = 3)
476 4 for %esp (gcc regno = 7)
477 5 for %ebp (gcc regno = 6)
478 6 for %esi (gcc regno = 4)
479 7 for %edi (gcc regno = 5)
480 The following three DWARF register numbers are never generated by
481 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
482 believes these numbers have these meanings.
483 8 for %eip (no gcc equivalent)
484 9 for %eflags (gcc regno = 17)
485 10 for %trapno (no gcc equivalent)
486 It is not at all clear how we should number the FP stack registers
487 for the x86 architecture. If the version of SDB on x86/svr4 were
488 a bit less brain dead with respect to floating-point then we would
489 have a precedent to follow with respect to DWARF register numbers
490 for x86 FP registers, but the SDB on x86/svr4 is so completely
491 broken with respect to FP registers that it is hardly worth thinking
492 of it as something to strive for compatibility with.
493 The version of x86/svr4 SDB I have at the moment does (partially)
494 seem to believe that DWARF register number 11 is associated with
495 the x86 register %st(0), but that's about all. Higher DWARF
496 register numbers don't seem to be associated with anything in
497 particular, and even for DWARF regno 11, SDB only seems to under-
498 stand that it should say that a variable lives in %st(0) (when
499 asked via an `=' command) if we said it was in DWARF regno 11,
500 but SDB still prints garbage when asked for the value of the
501 variable in question (via a `/' command).
502 (Also note that the labels SDB prints for various FP stack regs
503 when doing an `x' command are all wrong.)
504 Note that these problems generally don't affect the native SVR4
505 C compiler because it doesn't allow the use of -O with -g and
506 because when it is *not* optimizing, it allocates a memory
507 location for each floating-point variable, and the memory
508 location is what gets described in the DWARF AT_location
509 attribute for the variable in question.
510 Regardless of the severe mental illness of the x86/svr4 SDB, we
511 do something sensible here and we use the following DWARF
512 register numbers. Note that these are all stack-top-relative
514 11 for %st(0) (gcc regno = 8)
515 12 for %st(1) (gcc regno = 9)
516 13 for %st(2) (gcc regno = 10)
517 14 for %st(3) (gcc regno = 11)
518 15 for %st(4) (gcc regno = 12)
519 16 for %st(5) (gcc regno = 13)
520 17 for %st(6) (gcc regno = 14)
521 18 for %st(7) (gcc regno = 15)
523 int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
525 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
526 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
527 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
528 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
529 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
530 -1, -1, -1, -1, -1, -1, -1, -1, /* extemded integer registers */
531 -1, -1, -1, -1, -1, -1, -1, -1, /* extemded SSE registers */
534 /* Test and compare insns in i386.md store the information needed to
535 generate branch and scc insns here. */
537 rtx ix86_compare_op0
= NULL_RTX
;
538 rtx ix86_compare_op1
= NULL_RTX
;
540 #define MAX_386_STACK_LOCALS 3
541 /* Size of the register save area. */
542 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
544 /* Define the structure for the machine field in struct function. */
545 struct machine_function
547 rtx stack_locals
[(int) MAX_MACHINE_MODE
][MAX_386_STACK_LOCALS
];
548 int save_varrargs_registers
;
549 int accesses_prev_frame
;
552 #define ix86_stack_locals (cfun->machine->stack_locals)
553 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
555 /* Structure describing stack frame layout.
556 Stack grows downward:
562 saved frame pointer if frame_pointer_needed
563 <- HARD_FRAME_POINTER
569 > to_allocate <- FRAME_POINTER
581 int outgoing_arguments_size
;
584 HOST_WIDE_INT to_allocate
;
585 /* The offsets relative to ARG_POINTER. */
586 HOST_WIDE_INT frame_pointer_offset
;
587 HOST_WIDE_INT hard_frame_pointer_offset
;
588 HOST_WIDE_INT stack_pointer_offset
;
591 /* Used to enable/disable debugging features. */
592 const char *ix86_debug_arg_string
, *ix86_debug_addr_string
;
593 /* Code model option as passed by user. */
594 const char *ix86_cmodel_string
;
596 enum cmodel ix86_cmodel
;
598 const char *ix86_asm_string
;
599 enum asm_dialect ix86_asm_dialect
= ASM_ATT
;
601 /* which cpu are we scheduling for */
602 enum processor_type ix86_cpu
;
604 /* which unit we are generating floating point math for */
605 enum fpmath_unit ix86_fpmath
;
607 /* which instruction set architecture to use. */
610 /* Strings to hold which cpu and instruction set architecture to use. */
611 const char *ix86_cpu_string
; /* for -mcpu=<xxx> */
612 const char *ix86_arch_string
; /* for -march=<xxx> */
613 const char *ix86_fpmath_string
; /* for -mfpmath=<xxx> */
615 /* # of registers to use to pass arguments. */
616 const char *ix86_regparm_string
;
618 /* true if sse prefetch instruction is not NOOP. */
619 int x86_prefetch_sse
;
621 /* ix86_regparm_string as a number */
624 /* Alignment to use for loops and jumps: */
626 /* Power of two alignment for loops. */
627 const char *ix86_align_loops_string
;
629 /* Power of two alignment for non-loop jumps. */
630 const char *ix86_align_jumps_string
;
632 /* Power of two alignment for stack boundary in bytes. */
633 const char *ix86_preferred_stack_boundary_string
;
635 /* Preferred alignment for stack boundary in bits. */
636 int ix86_preferred_stack_boundary
;
638 /* Values 1-5: see jump.c */
639 int ix86_branch_cost
;
640 const char *ix86_branch_cost_string
;
642 /* Power of two alignment for functions. */
643 const char *ix86_align_funcs_string
;
645 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
646 static char internal_label_prefix
[16];
647 static int internal_label_prefix_len
;
649 static int local_symbolic_operand
PARAMS ((rtx
, enum machine_mode
));
650 static void output_pic_addr_const
PARAMS ((FILE *, rtx
, int));
651 static void put_condition_code
PARAMS ((enum rtx_code
, enum machine_mode
,
653 static rtx ix86_expand_int_compare
PARAMS ((enum rtx_code
, rtx
, rtx
));
654 static enum rtx_code ix86_prepare_fp_compare_args
PARAMS ((enum rtx_code
,
656 static rtx gen_push
PARAMS ((rtx
));
657 static int memory_address_length
PARAMS ((rtx addr
));
658 static int ix86_flags_dependant
PARAMS ((rtx
, rtx
, enum attr_type
));
659 static int ix86_agi_dependant
PARAMS ((rtx
, rtx
, enum attr_type
));
660 static int ix86_safe_length
PARAMS ((rtx
));
661 static enum attr_memory ix86_safe_memory
PARAMS ((rtx
));
662 static enum attr_pent_pair ix86_safe_pent_pair
PARAMS ((rtx
));
663 static enum attr_ppro_uops ix86_safe_ppro_uops
PARAMS ((rtx
));
664 static void ix86_dump_ppro_packet
PARAMS ((FILE *));
665 static void ix86_reorder_insn
PARAMS ((rtx
*, rtx
*));
666 static rtx
* ix86_pent_find_pair
PARAMS ((rtx
*, rtx
*, enum attr_pent_pair
,
668 static void ix86_init_machine_status
PARAMS ((struct function
*));
669 static void ix86_mark_machine_status
PARAMS ((struct function
*));
670 static void ix86_free_machine_status
PARAMS ((struct function
*));
671 static int ix86_split_to_parts
PARAMS ((rtx
, rtx
*, enum machine_mode
));
672 static int ix86_safe_length_prefix
PARAMS ((rtx
));
673 static int ix86_nsaved_regs
PARAMS ((void));
674 static void ix86_emit_save_regs
PARAMS ((void));
675 static void ix86_emit_save_regs_using_mov
PARAMS ((rtx
, HOST_WIDE_INT
));
676 static void ix86_emit_restore_regs_using_mov
PARAMS ((rtx
, int, int));
677 static void ix86_set_move_mem_attrs_1
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
));
678 static void ix86_sched_reorder_pentium
PARAMS ((rtx
*, rtx
*));
679 static void ix86_sched_reorder_ppro
PARAMS ((rtx
*, rtx
*));
680 static HOST_WIDE_INT ix86_GOT_alias_set
PARAMS ((void));
681 static void ix86_adjust_counter
PARAMS ((rtx
, HOST_WIDE_INT
));
682 static rtx ix86_expand_aligntest
PARAMS ((rtx
, int));
683 static void ix86_expand_strlensi_unroll_1
PARAMS ((rtx
, rtx
));
684 static int ix86_issue_rate
PARAMS ((void));
685 static int ix86_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
686 static void ix86_sched_init
PARAMS ((FILE *, int, int));
687 static int ix86_sched_reorder
PARAMS ((FILE *, int, rtx
*, int *, int));
688 static int ix86_variable_issue
PARAMS ((FILE *, int, rtx
, int));
689 static void ix86_init_mmx_sse_builtins
PARAMS ((void));
693 rtx base
, index
, disp
;
697 static int ix86_decompose_address
PARAMS ((rtx
, struct ix86_address
*));
699 struct builtin_description
;
700 static rtx ix86_expand_sse_comi
PARAMS ((const struct builtin_description
*,
702 static rtx ix86_expand_sse_compare
PARAMS ((const struct builtin_description
*,
704 static rtx ix86_expand_unop1_builtin
PARAMS ((enum insn_code
, tree
, rtx
));
705 static rtx ix86_expand_unop_builtin
PARAMS ((enum insn_code
, tree
, rtx
, int));
706 static rtx ix86_expand_binop_builtin
PARAMS ((enum insn_code
, tree
, rtx
));
707 static rtx ix86_expand_timode_binop_builtin
PARAMS ((enum insn_code
,
709 static rtx ix86_expand_store_builtin
PARAMS ((enum insn_code
, tree
));
710 static rtx safe_vector_operand
PARAMS ((rtx
, enum machine_mode
));
711 static enum rtx_code ix86_fp_compare_code_to_integer
PARAMS ((enum rtx_code
));
712 static void ix86_fp_comparison_codes
PARAMS ((enum rtx_code code
,
716 static rtx ix86_expand_fp_compare
PARAMS ((enum rtx_code
, rtx
, rtx
, rtx
,
718 static int ix86_fp_comparison_arithmetics_cost
PARAMS ((enum rtx_code code
));
719 static int ix86_fp_comparison_fcomi_cost
PARAMS ((enum rtx_code code
));
720 static int ix86_fp_comparison_sahf_cost
PARAMS ((enum rtx_code code
));
721 static int ix86_fp_comparison_cost
PARAMS ((enum rtx_code code
));
722 static int ix86_save_reg
PARAMS ((int, int));
723 static void ix86_compute_frame_layout
PARAMS ((struct ix86_frame
*));
724 static int ix86_comp_type_attributes
PARAMS ((tree
, tree
));
725 const struct attribute_spec ix86_attribute_table
[];
726 static tree ix86_handle_cdecl_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
727 static tree ix86_handle_regparm_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
729 #ifdef DO_GLOBAL_CTORS_BODY
730 static void ix86_svr3_asm_out_constructor
PARAMS ((rtx
, int));
733 /* Register class used for passing given 64bit part of the argument.
734 These represent classes as documented by the PS ABI, with the exception
735 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
736 use SF or DFmode move instead of DImode to avoid reformating penalties.
738 Similary we play games with INTEGERSI_CLASS to use cheaper SImode moves
739 whenever possible (upper half does contain padding).
741 enum x86_64_reg_class
744 X86_64_INTEGER_CLASS
,
745 X86_64_INTEGERSI_CLASS
,
754 static const char * const x86_64_reg_class_name
[] =
755 {"no", "integer", "integerSI", "sse", "sseSF", "sseDF", "sseup", "x87", "x87up", "no"};
757 #define MAX_CLASSES 4
758 static int classify_argument
PARAMS ((enum machine_mode
, tree
,
759 enum x86_64_reg_class
[MAX_CLASSES
],
761 static int examine_argument
PARAMS ((enum machine_mode
, tree
, int, int *,
763 static rtx construct_container
PARAMS ((enum machine_mode
, tree
, int, int, int,
765 static enum x86_64_reg_class merge_classes
PARAMS ((enum x86_64_reg_class
,
766 enum x86_64_reg_class
));
768 /* Initialize the GCC target structure. */
769 #undef TARGET_ATTRIBUTE_TABLE
770 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
771 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
772 # undef TARGET_MERGE_DECL_ATTRIBUTES
773 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
776 #undef TARGET_COMP_TYPE_ATTRIBUTES
777 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
779 #undef TARGET_INIT_BUILTINS
780 #define TARGET_INIT_BUILTINS ix86_init_builtins
782 #undef TARGET_EXPAND_BUILTIN
783 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
785 #if defined (OSF_OS) || defined (TARGET_OSF1ELF)
786 static void ix86_osf_output_function_prologue
PARAMS ((FILE *,
788 # undef TARGET_ASM_FUNCTION_PROLOGUE
789 # define TARGET_ASM_FUNCTION_PROLOGUE ix86_osf_output_function_prologue
792 #undef TARGET_ASM_OPEN_PAREN
793 #define TARGET_ASM_OPEN_PAREN ""
794 #undef TARGET_ASM_CLOSE_PAREN
795 #define TARGET_ASM_CLOSE_PAREN ""
797 #undef TARGET_ASM_ALIGNED_HI_OP
798 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
799 #undef TARGET_ASM_ALIGNED_SI_OP
800 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
802 #undef TARGET_ASM_ALIGNED_DI_OP
803 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
806 #undef TARGET_ASM_UNALIGNED_HI_OP
807 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
808 #undef TARGET_ASM_UNALIGNED_SI_OP
809 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
810 #undef TARGET_ASM_UNALIGNED_DI_OP
811 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
813 #undef TARGET_SCHED_ADJUST_COST
814 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
815 #undef TARGET_SCHED_ISSUE_RATE
816 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
817 #undef TARGET_SCHED_VARIABLE_ISSUE
818 #define TARGET_SCHED_VARIABLE_ISSUE ix86_variable_issue
819 #undef TARGET_SCHED_INIT
820 #define TARGET_SCHED_INIT ix86_sched_init
821 #undef TARGET_SCHED_REORDER
822 #define TARGET_SCHED_REORDER ix86_sched_reorder
824 struct gcc_target targetm
= TARGET_INITIALIZER
;
826 /* Sometimes certain combinations of command options do not make
827 sense on a particular target machine. You can define a macro
828 `OVERRIDE_OPTIONS' to take account of this. This macro, if
829 defined, is executed once just after all the command options have
832 Don't use this macro to turn on various extra optimizations for
833 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
839 /* Comes from final.c -- no real reason to change it. */
840 #define MAX_CODE_ALIGN 16
844 const struct processor_costs
*cost
; /* Processor costs */
845 const int target_enable
; /* Target flags to enable. */
846 const int target_disable
; /* Target flags to disable. */
847 const int align_loop
; /* Default alignments. */
848 const int align_loop_max_skip
;
849 const int align_jump
;
850 const int align_jump_max_skip
;
851 const int align_func
;
852 const int branch_cost
;
854 const processor_target_table
[PROCESSOR_max
] =
856 {&i386_cost
, 0, 0, 4, 3, 4, 3, 4, 1},
857 {&i486_cost
, 0, 0, 16, 15, 16, 15, 16, 1},
858 {&pentium_cost
, 0, 0, 16, 7, 16, 7, 16, 1},
859 {&pentiumpro_cost
, 0, 0, 16, 15, 16, 7, 16, 1},
860 {&k6_cost
, 0, 0, 32, 7, 32, 7, 32, 1},
861 {&athlon_cost
, 0, 0, 16, 7, 64, 7, 16, 1},
862 {&pentium4_cost
, 0, 0, 0, 0, 0, 0, 0, 1}
865 static const char * const cpu_names
[] = TARGET_CPU_DEFAULT_NAMES
;
868 const char *const name
; /* processor name or nickname. */
869 const enum processor_type processor
;
875 PTA_PREFETCH_SSE
= 8,
880 const processor_alias_table
[] =
882 {"i386", PROCESSOR_I386
, 0},
883 {"i486", PROCESSOR_I486
, 0},
884 {"i586", PROCESSOR_PENTIUM
, 0},
885 {"pentium", PROCESSOR_PENTIUM
, 0},
886 {"pentium-mmx", PROCESSOR_PENTIUM
, PTA_MMX
},
887 {"i686", PROCESSOR_PENTIUMPRO
, 0},
888 {"pentiumpro", PROCESSOR_PENTIUMPRO
, 0},
889 {"pentium2", PROCESSOR_PENTIUMPRO
, PTA_MMX
},
890 {"pentium3", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_SSE
| PTA_PREFETCH_SSE
},
891 {"pentium4", PROCESSOR_PENTIUM4
, PTA_SSE
| PTA_SSE2
|
892 PTA_MMX
| PTA_PREFETCH_SSE
},
893 {"k6", PROCESSOR_K6
, PTA_MMX
},
894 {"k6-2", PROCESSOR_K6
, PTA_MMX
| PTA_3DNOW
},
895 {"k6-3", PROCESSOR_K6
, PTA_MMX
| PTA_3DNOW
},
896 {"athlon", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
898 {"athlon-tbird", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
899 | PTA_3DNOW
| PTA_3DNOW_A
},
900 {"athlon-4", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
901 | PTA_3DNOW_A
| PTA_SSE
},
902 {"athlon-xp", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
903 | PTA_3DNOW_A
| PTA_SSE
},
904 {"athlon-mp", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
905 | PTA_3DNOW_A
| PTA_SSE
},
908 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
910 #ifdef SUBTARGET_OVERRIDE_OPTIONS
911 SUBTARGET_OVERRIDE_OPTIONS
;
914 if (!ix86_cpu_string
&& ix86_arch_string
)
915 ix86_cpu_string
= ix86_arch_string
;
916 if (!ix86_cpu_string
)
917 ix86_cpu_string
= cpu_names
[TARGET_CPU_DEFAULT
];
918 if (!ix86_arch_string
)
919 ix86_arch_string
= TARGET_64BIT
? "athlon-4" : "i386";
921 if (ix86_cmodel_string
!= 0)
923 if (!strcmp (ix86_cmodel_string
, "small"))
924 ix86_cmodel
= flag_pic
? CM_SMALL_PIC
: CM_SMALL
;
926 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string
);
927 else if (!strcmp (ix86_cmodel_string
, "32"))
929 else if (!strcmp (ix86_cmodel_string
, "kernel") && !flag_pic
)
930 ix86_cmodel
= CM_KERNEL
;
931 else if (!strcmp (ix86_cmodel_string
, "medium") && !flag_pic
)
932 ix86_cmodel
= CM_MEDIUM
;
933 else if (!strcmp (ix86_cmodel_string
, "large") && !flag_pic
)
934 ix86_cmodel
= CM_LARGE
;
936 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string
);
942 ix86_cmodel
= flag_pic
? CM_SMALL_PIC
: CM_SMALL
;
944 if (ix86_asm_string
!= 0)
946 if (!strcmp (ix86_asm_string
, "intel"))
947 ix86_asm_dialect
= ASM_INTEL
;
948 else if (!strcmp (ix86_asm_string
, "att"))
949 ix86_asm_dialect
= ASM_ATT
;
951 error ("bad value (%s) for -masm= switch", ix86_asm_string
);
953 if ((TARGET_64BIT
== 0) != (ix86_cmodel
== CM_32
))
954 error ("code model `%s' not supported in the %s bit mode",
955 ix86_cmodel_string
, TARGET_64BIT
? "64" : "32");
956 if (ix86_cmodel
== CM_LARGE
)
957 sorry ("code model `large' not supported yet");
958 if ((TARGET_64BIT
!= 0) != ((target_flags
& MASK_64BIT
) != 0))
959 sorry ("%i-bit mode not compiled in",
960 (target_flags
& MASK_64BIT
) ? 64 : 32);
962 for (i
= 0; i
< pta_size
; i
++)
963 if (! strcmp (ix86_arch_string
, processor_alias_table
[i
].name
))
965 ix86_arch
= processor_alias_table
[i
].processor
;
966 /* Default cpu tuning to the architecture. */
967 ix86_cpu
= ix86_arch
;
968 if (processor_alias_table
[i
].flags
& PTA_MMX
969 && !(target_flags
& MASK_MMX_SET
))
970 target_flags
|= MASK_MMX
;
971 if (processor_alias_table
[i
].flags
& PTA_3DNOW
972 && !(target_flags
& MASK_3DNOW_SET
))
973 target_flags
|= MASK_3DNOW
;
974 if (processor_alias_table
[i
].flags
& PTA_3DNOW_A
975 && !(target_flags
& MASK_3DNOW_A_SET
))
976 target_flags
|= MASK_3DNOW_A
;
977 if (processor_alias_table
[i
].flags
& PTA_SSE
978 && !(target_flags
& MASK_SSE_SET
))
979 target_flags
|= MASK_SSE
;
980 if (processor_alias_table
[i
].flags
& PTA_SSE2
981 && !(target_flags
& MASK_SSE2_SET
))
982 target_flags
|= MASK_SSE2
;
983 if (processor_alias_table
[i
].flags
& PTA_PREFETCH_SSE
)
984 x86_prefetch_sse
= true;
989 error ("bad value (%s) for -march= switch", ix86_arch_string
);
991 for (i
= 0; i
< pta_size
; i
++)
992 if (! strcmp (ix86_cpu_string
, processor_alias_table
[i
].name
))
994 ix86_cpu
= processor_alias_table
[i
].processor
;
997 if (processor_alias_table
[i
].flags
& PTA_PREFETCH_SSE
)
998 x86_prefetch_sse
= true;
1000 error ("bad value (%s) for -mcpu= switch", ix86_cpu_string
);
1003 ix86_cost
= &size_cost
;
1005 ix86_cost
= processor_target_table
[ix86_cpu
].cost
;
1006 target_flags
|= processor_target_table
[ix86_cpu
].target_enable
;
1007 target_flags
&= ~processor_target_table
[ix86_cpu
].target_disable
;
1009 /* Arrange to set up i386_stack_locals for all functions. */
1010 init_machine_status
= ix86_init_machine_status
;
1011 mark_machine_status
= ix86_mark_machine_status
;
1012 free_machine_status
= ix86_free_machine_status
;
1014 /* Validate -mregparm= value. */
1015 if (ix86_regparm_string
)
1017 i
= atoi (ix86_regparm_string
);
1018 if (i
< 0 || i
> REGPARM_MAX
)
1019 error ("-mregparm=%d is not between 0 and %d", i
, REGPARM_MAX
);
1025 ix86_regparm
= REGPARM_MAX
;
1027 /* If the user has provided any of the -malign-* options,
1028 warn and use that value only if -falign-* is not set.
1029 Remove this code in GCC 3.2 or later. */
1030 if (ix86_align_loops_string
)
1032 warning ("-malign-loops is obsolete, use -falign-loops");
1033 if (align_loops
== 0)
1035 i
= atoi (ix86_align_loops_string
);
1036 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1037 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1039 align_loops
= 1 << i
;
1043 if (ix86_align_jumps_string
)
1045 warning ("-malign-jumps is obsolete, use -falign-jumps");
1046 if (align_jumps
== 0)
1048 i
= atoi (ix86_align_jumps_string
);
1049 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1050 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1052 align_jumps
= 1 << i
;
1056 if (ix86_align_funcs_string
)
1058 warning ("-malign-functions is obsolete, use -falign-functions");
1059 if (align_functions
== 0)
1061 i
= atoi (ix86_align_funcs_string
);
1062 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1063 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1065 align_functions
= 1 << i
;
1069 /* Default align_* from the processor table. */
1070 if (align_loops
== 0)
1072 align_loops
= processor_target_table
[ix86_cpu
].align_loop
;
1073 align_loops_max_skip
= processor_target_table
[ix86_cpu
].align_loop_max_skip
;
1075 if (align_jumps
== 0)
1077 align_jumps
= processor_target_table
[ix86_cpu
].align_jump
;
1078 align_jumps_max_skip
= processor_target_table
[ix86_cpu
].align_jump_max_skip
;
1080 if (align_functions
== 0)
1082 align_functions
= processor_target_table
[ix86_cpu
].align_func
;
1085 /* Validate -mpreferred-stack-boundary= value, or provide default.
1086 The default of 128 bits is for Pentium III's SSE __m128, but we
1087 don't want additional code to keep the stack aligned when
1088 optimizing for code size. */
1089 ix86_preferred_stack_boundary
= (optimize_size
1090 ? TARGET_64BIT
? 64 : 32
1092 if (ix86_preferred_stack_boundary_string
)
1094 i
= atoi (ix86_preferred_stack_boundary_string
);
1095 if (i
< (TARGET_64BIT
? 3 : 2) || i
> 12)
1096 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i
,
1097 TARGET_64BIT
? 3 : 2);
1099 ix86_preferred_stack_boundary
= (1 << i
) * BITS_PER_UNIT
;
1102 /* Validate -mbranch-cost= value, or provide default. */
1103 ix86_branch_cost
= processor_target_table
[ix86_cpu
].branch_cost
;
1104 if (ix86_branch_cost_string
)
1106 i
= atoi (ix86_branch_cost_string
);
1108 error ("-mbranch-cost=%d is not between 0 and 5", i
);
1110 ix86_branch_cost
= i
;
1113 /* Keep nonleaf frame pointers. */
1114 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
1115 flag_omit_frame_pointer
= 1;
1117 /* If we're doing fast math, we don't care about comparison order
1118 wrt NaNs. This lets us use a shorter comparison sequence. */
1119 if (flag_unsafe_math_optimizations
)
1120 target_flags
&= ~MASK_IEEE_FP
;
1122 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1123 since the insns won't need emulation. */
1124 if (x86_arch_always_fancy_math_387
& (1 << ix86_arch
))
1125 target_flags
&= ~MASK_NO_FANCY_MATH_387
;
1129 if (TARGET_ALIGN_DOUBLE
)
1130 error ("-malign-double makes no sense in the 64bit mode");
1132 error ("-mrtd calling convention not supported in the 64bit mode");
1133 /* Enable by default the SSE and MMX builtins. */
1134 target_flags
|= (MASK_SSE2
| MASK_SSE
| MASK_MMX
| MASK_128BIT_LONG_DOUBLE
);
1135 ix86_fpmath
= FPMATH_SSE
;
1138 ix86_fpmath
= FPMATH_387
;
1140 if (ix86_fpmath_string
!= 0)
1142 if (! strcmp (ix86_fpmath_string
, "387"))
1143 ix86_fpmath
= FPMATH_387
;
1144 else if (! strcmp (ix86_fpmath_string
, "sse"))
1148 warning ("SSE instruction set disabled, using 387 arithmetics");
1149 ix86_fpmath
= FPMATH_387
;
1152 ix86_fpmath
= FPMATH_SSE
;
1154 else if (! strcmp (ix86_fpmath_string
, "387,sse")
1155 || ! strcmp (ix86_fpmath_string
, "sse,387"))
1159 warning ("SSE instruction set disabled, using 387 arithmetics");
1160 ix86_fpmath
= FPMATH_387
;
1162 else if (!TARGET_80387
)
1164 warning ("387 instruction set disabled, using SSE arithmetics");
1165 ix86_fpmath
= FPMATH_SSE
;
1168 ix86_fpmath
= FPMATH_SSE
| FPMATH_387
;
1171 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string
);
1174 /* It makes no sense to ask for just SSE builtins, so MMX is also turned
1178 target_flags
|= MASK_MMX
;
1179 x86_prefetch_sse
= true;
1182 /* If it has 3DNow! it also has MMX so MMX is also turned on by -m3dnow */
1185 target_flags
|= MASK_MMX
;
1186 /* If we are targetting the Athlon architecture, enable the 3Dnow/MMX
1187 extensions it adds. */
1188 if (x86_3dnow_a
& (1 << ix86_arch
))
1189 target_flags
|= MASK_3DNOW_A
;
1191 if ((x86_accumulate_outgoing_args
& CPUMASK
)
1192 && !(target_flags
& MASK_ACCUMULATE_OUTGOING_ARGS_SET
)
1194 target_flags
|= MASK_ACCUMULATE_OUTGOING_ARGS
;
1196 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1199 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix
, "LX", 0);
1200 p
= strchr (internal_label_prefix
, 'X');
1201 internal_label_prefix_len
= p
- internal_label_prefix
;
1207 optimization_options (level
, size
)
1209 int size ATTRIBUTE_UNUSED
;
1211 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
1212 make the problem with not enough registers even worse. */
1213 #ifdef INSN_SCHEDULING
1215 flag_schedule_insns
= 0;
1217 if (TARGET_64BIT
&& optimize
>= 1)
1218 flag_omit_frame_pointer
= 1;
1221 flag_pcc_struct_return
= 0;
1222 flag_asynchronous_unwind_tables
= 1;
1226 /* Table of valid machine attributes. */
1227 const struct attribute_spec ix86_attribute_table
[] =
1229 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1230 /* Stdcall attribute says callee is responsible for popping arguments
1231 if they are not variable. */
1232 { "stdcall", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1233 /* Cdecl attribute says the callee is a normal C declaration */
1234 { "cdecl", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1235 /* Regparm attribute specifies how many integer arguments are to be
1236 passed in registers. */
1237 { "regparm", 1, 1, false, true, true, ix86_handle_regparm_attribute
},
1238 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
1239 { "dllimport", 0, 0, false, false, false, ix86_handle_dll_attribute
},
1240 { "dllexport", 0, 0, false, false, false, ix86_handle_dll_attribute
},
1241 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute
},
1243 { NULL
, 0, 0, false, false, false, NULL
}
1246 /* Handle a "cdecl" or "stdcall" attribute;
1247 arguments as in struct attribute_spec.handler. */
1249 ix86_handle_cdecl_attribute (node
, name
, args
, flags
, no_add_attrs
)
1252 tree args ATTRIBUTE_UNUSED
;
1253 int flags ATTRIBUTE_UNUSED
;
1256 if (TREE_CODE (*node
) != FUNCTION_TYPE
1257 && TREE_CODE (*node
) != METHOD_TYPE
1258 && TREE_CODE (*node
) != FIELD_DECL
1259 && TREE_CODE (*node
) != TYPE_DECL
)
1261 warning ("`%s' attribute only applies to functions",
1262 IDENTIFIER_POINTER (name
));
1263 *no_add_attrs
= true;
1268 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
1269 *no_add_attrs
= true;
1275 /* Handle a "regparm" attribute;
1276 arguments as in struct attribute_spec.handler. */
1278 ix86_handle_regparm_attribute (node
, name
, args
, flags
, no_add_attrs
)
1282 int flags ATTRIBUTE_UNUSED
;
1285 if (TREE_CODE (*node
) != FUNCTION_TYPE
1286 && TREE_CODE (*node
) != METHOD_TYPE
1287 && TREE_CODE (*node
) != FIELD_DECL
1288 && TREE_CODE (*node
) != TYPE_DECL
)
1290 warning ("`%s' attribute only applies to functions",
1291 IDENTIFIER_POINTER (name
));
1292 *no_add_attrs
= true;
1298 cst
= TREE_VALUE (args
);
1299 if (TREE_CODE (cst
) != INTEGER_CST
)
1301 warning ("`%s' attribute requires an integer constant argument",
1302 IDENTIFIER_POINTER (name
));
1303 *no_add_attrs
= true;
1305 else if (compare_tree_int (cst
, REGPARM_MAX
) > 0)
1307 warning ("argument to `%s' attribute larger than %d",
1308 IDENTIFIER_POINTER (name
), REGPARM_MAX
);
1309 *no_add_attrs
= true;
1316 #if defined (OSF_OS) || defined (TARGET_OSF1ELF)
1318 /* Generate the assembly code for function entry. FILE is a stdio
1319 stream to output the code to. SIZE is an int: how many units of
1320 temporary storage to allocate.
1322 Refer to the array `regs_ever_live' to determine which registers to
1323 save; `regs_ever_live[I]' is nonzero if register number I is ever
1324 used in the function. This function is responsible for knowing
1325 which registers should not be saved even if used.
1327 We override it here to allow for the new profiling code to go before
1328 the prologue and the old mcount code to go after the prologue (and
1329 after %ebx has been set up for ELF shared library support). */
1332 ix86_osf_output_function_prologue (file
, size
)
1336 const char *prefix
= "";
1337 const char *const lprefix
= LPREFIX
;
1338 int labelno
= profile_label_no
;
1342 if (TARGET_UNDERSCORES
)
1345 if (current_function_profile
&& OSF_PROFILE_BEFORE_PROLOGUE
)
1347 if (!flag_pic
&& !HALF_PIC_P ())
1349 fprintf (file
, "\tmovl $%sP%d,%%edx\n", lprefix
, labelno
);
1350 fprintf (file
, "\tcall *%s_mcount_ptr\n", prefix
);
1353 else if (HALF_PIC_P ())
1357 HALF_PIC_EXTERNAL ("_mcount_ptr");
1358 symref
= HALF_PIC_PTR (gen_rtx_SYMBOL_REF (Pmode
,
1361 fprintf (file
, "\tmovl $%sP%d,%%edx\n", lprefix
, labelno
);
1362 fprintf (file
, "\tmovl %s%s,%%eax\n", prefix
,
1364 fprintf (file
, "\tcall *(%%eax)\n");
1369 static int call_no
= 0;
1371 fprintf (file
, "\tcall %sPc%d\n", lprefix
, call_no
);
1372 fprintf (file
, "%sPc%d:\tpopl %%eax\n", lprefix
, call_no
);
1373 fprintf (file
, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n",
1374 lprefix
, call_no
++);
1375 fprintf (file
, "\tleal %sP%d@GOTOFF(%%eax),%%edx\n",
1377 fprintf (file
, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n",
1379 fprintf (file
, "\tcall *(%%eax)\n");
1385 if (current_function_profile
&& OSF_PROFILE_BEFORE_PROLOGUE
)
1389 fprintf (file
, "\tmovl $%sP%d,%%edx\n", lprefix
, labelno
);
1390 fprintf (file
, "\tcall *%s_mcount_ptr\n", prefix
);
1395 static int call_no
= 0;
1397 fprintf (file
, "\tcall %sPc%d\n", lprefix
, call_no
);
1398 fprintf (file
, "%sPc%d:\tpopl %%eax\n", lprefix
, call_no
);
1399 fprintf (file
, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n",
1400 lprefix
, call_no
++);
1401 fprintf (file
, "\tleal %sP%d@GOTOFF(%%eax),%%edx\n",
1403 fprintf (file
, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n",
1405 fprintf (file
, "\tcall *(%%eax)\n");
1408 #endif /* !OSF_OS */
1410 function_prologue (file
, size
);
1413 #endif /* OSF_OS || TARGET_OSF1ELF */
1415 /* Return 0 if the attributes for two types are incompatible, 1 if they
1416 are compatible, and 2 if they are nearly compatible (which causes a
1417 warning to be generated). */
1420 ix86_comp_type_attributes (type1
, type2
)
1424 /* Check for mismatch of non-default calling convention. */
1425 const char *const rtdstr
= TARGET_RTD
? "cdecl" : "stdcall";
1427 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
1430 /* Check for mismatched return types (cdecl vs stdcall). */
1431 if (!lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type1
))
1432 != !lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type2
)))
1437 /* Value is the number of bytes of arguments automatically
1438 popped when returning from a subroutine call.
1439 FUNDECL is the declaration node of the function (as a tree),
1440 FUNTYPE is the data type of the function (as a tree),
1441 or for a library call it is an identifier node for the subroutine name.
1442 SIZE is the number of bytes of arguments passed on the stack.
1444 On the 80386, the RTD insn may be used to pop them if the number
1445 of args is fixed, but if the number is variable then the caller
1446 must pop them all. RTD can't be used for library calls now
1447 because the library is compiled with the Unix compiler.
1448 Use of RTD is a selectable option, since it is incompatible with
1449 standard Unix calling sequences. If the option is not selected,
1450 the caller must always pop the args.
1452 The attribute stdcall is equivalent to RTD on a per module basis. */
1455 ix86_return_pops_args (fundecl
, funtype
, size
)
1460 int rtd
= TARGET_RTD
&& (!fundecl
|| TREE_CODE (fundecl
) != IDENTIFIER_NODE
);
1462 /* Cdecl functions override -mrtd, and never pop the stack. */
1463 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype
))) {
1465 /* Stdcall functions will pop the stack if not variable args. */
1466 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype
)))
1470 && (TYPE_ARG_TYPES (funtype
) == NULL_TREE
1471 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype
)))
1472 == void_type_node
)))
1476 /* Lose any fake structure return argument if it is passed on the stack. */
1477 if (aggregate_value_p (TREE_TYPE (funtype
))
1480 int nregs
= ix86_regparm
;
1484 tree attr
= lookup_attribute ("regparm", TYPE_ATTRIBUTES (funtype
));
1487 nregs
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr
)));
1491 return GET_MODE_SIZE (Pmode
);
1497 /* Argument support functions. */
1499 /* Return true when register may be used to pass function parameters. */
1501 ix86_function_arg_regno_p (regno
)
1506 return (regno
< REGPARM_MAX
1507 || (TARGET_SSE
&& SSE_REGNO_P (regno
) && !fixed_regs
[regno
]));
1508 if (SSE_REGNO_P (regno
) && TARGET_SSE
)
1510 /* RAX is used as hidden argument to va_arg functions. */
1513 for (i
= 0; i
< REGPARM_MAX
; i
++)
1514 if (regno
== x86_64_int_parameter_registers
[i
])
1519 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1520 for a call to a function whose data type is FNTYPE.
1521 For a library call, FNTYPE is 0. */
1524 init_cumulative_args (cum
, fntype
, libname
)
1525 CUMULATIVE_ARGS
*cum
; /* Argument info to initialize */
1526 tree fntype
; /* tree ptr for function decl */
1527 rtx libname
; /* SYMBOL_REF of library name or 0 */
1529 static CUMULATIVE_ARGS zero_cum
;
1530 tree param
, next_param
;
1532 if (TARGET_DEBUG_ARG
)
1534 fprintf (stderr
, "\ninit_cumulative_args (");
1536 fprintf (stderr
, "fntype code = %s, ret code = %s",
1537 tree_code_name
[(int) TREE_CODE (fntype
)],
1538 tree_code_name
[(int) TREE_CODE (TREE_TYPE (fntype
))]);
1540 fprintf (stderr
, "no fntype");
1543 fprintf (stderr
, ", libname = %s", XSTR (libname
, 0));
1548 /* Set up the number of registers to use for passing arguments. */
1549 cum
->nregs
= ix86_regparm
;
1550 cum
->sse_nregs
= SSE_REGPARM_MAX
;
1551 if (fntype
&& !TARGET_64BIT
)
1553 tree attr
= lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype
));
1556 cum
->nregs
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr
)));
1558 cum
->maybe_vaarg
= false;
1560 /* Determine if this function has variable arguments. This is
1561 indicated by the last argument being 'void_type_mode' if there
1562 are no variable arguments. If there are variable arguments, then
1563 we won't pass anything in registers */
1567 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
1568 param
!= 0; param
= next_param
)
1570 next_param
= TREE_CHAIN (param
);
1571 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
1575 cum
->maybe_vaarg
= true;
1579 if ((!fntype
&& !libname
)
1580 || (fntype
&& !TYPE_ARG_TYPES (fntype
)))
1581 cum
->maybe_vaarg
= 1;
1583 if (TARGET_DEBUG_ARG
)
1584 fprintf (stderr
, ", nregs=%d )\n", cum
->nregs
);
1589 /* x86-64 register passing impleemntation. See x86-64 ABI for details. Goal
1590 of this code is to classify each 8bytes of incoming argument by the register
1591 class and assign registers accordingly. */
1593 /* Return the union class of CLASS1 and CLASS2.
1594 See the x86-64 PS ABI for details. */
1596 static enum x86_64_reg_class
1597 merge_classes (class1
, class2
)
1598 enum x86_64_reg_class class1
, class2
;
1600 /* Rule #1: If both classes are equal, this is the resulting class. */
1601 if (class1
== class2
)
1604 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
1606 if (class1
== X86_64_NO_CLASS
)
1608 if (class2
== X86_64_NO_CLASS
)
1611 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
1612 if (class1
== X86_64_MEMORY_CLASS
|| class2
== X86_64_MEMORY_CLASS
)
1613 return X86_64_MEMORY_CLASS
;
1615 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
1616 if ((class1
== X86_64_INTEGERSI_CLASS
&& class2
== X86_64_SSESF_CLASS
)
1617 || (class2
== X86_64_INTEGERSI_CLASS
&& class1
== X86_64_SSESF_CLASS
))
1618 return X86_64_INTEGERSI_CLASS
;
1619 if (class1
== X86_64_INTEGER_CLASS
|| class1
== X86_64_INTEGERSI_CLASS
1620 || class2
== X86_64_INTEGER_CLASS
|| class2
== X86_64_INTEGERSI_CLASS
)
1621 return X86_64_INTEGER_CLASS
;
1623 /* Rule #5: If one of the classes is X87 or X87UP class, MEMORY is used. */
1624 if (class1
== X86_64_X87_CLASS
|| class1
== X86_64_X87UP_CLASS
1625 || class2
== X86_64_X87_CLASS
|| class2
== X86_64_X87UP_CLASS
)
1626 return X86_64_MEMORY_CLASS
;
1628 /* Rule #6: Otherwise class SSE is used. */
1629 return X86_64_SSE_CLASS
;
1632 /* Classify the argument of type TYPE and mode MODE.
1633 CLASSES will be filled by the register class used to pass each word
1634 of the operand. The number of words is returned. In case the parameter
1635 should be passed in memory, 0 is returned. As a special case for zero
1636 sized containers, classes[0] will be NO_CLASS and 1 is returned.
1638 BIT_OFFSET is used internally for handling records and specifies offset
1639 of the offset in bits modulo 256 to avoid overflow cases.
1641 See the x86-64 PS ABI for details.
1645 classify_argument (mode
, type
, classes
, bit_offset
)
1646 enum machine_mode mode
;
1648 enum x86_64_reg_class classes
[MAX_CLASSES
];
1652 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
1653 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1655 if (type
&& AGGREGATE_TYPE_P (type
))
1659 enum x86_64_reg_class subclasses
[MAX_CLASSES
];
1661 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
1665 for (i
= 0; i
< words
; i
++)
1666 classes
[i
] = X86_64_NO_CLASS
;
1668 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
1669 signalize memory class, so handle it as special case. */
1672 classes
[0] = X86_64_NO_CLASS
;
1676 /* Classify each field of record and merge classes. */
1677 if (TREE_CODE (type
) == RECORD_TYPE
)
1679 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
1681 if (TREE_CODE (field
) == FIELD_DECL
)
1685 /* Bitfields are always classified as integer. Handle them
1686 early, since later code would consider them to be
1687 misaligned integers. */
1688 if (DECL_BIT_FIELD (field
))
1690 for (i
= int_bit_position (field
) / 8 / 8;
1691 i
< (int_bit_position (field
)
1692 + tree_low_cst (DECL_SIZE (field
), 0)
1695 merge_classes (X86_64_INTEGER_CLASS
,
1700 num
= classify_argument (TYPE_MODE (TREE_TYPE (field
)),
1701 TREE_TYPE (field
), subclasses
,
1702 (int_bit_position (field
)
1703 + bit_offset
) % 256);
1706 for (i
= 0; i
< num
; i
++)
1709 (int_bit_position (field
) + bit_offset
) / 8 / 8;
1711 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
1717 /* Arrays are handled as small records. */
1718 else if (TREE_CODE (type
) == ARRAY_TYPE
)
1721 num
= classify_argument (TYPE_MODE (TREE_TYPE (type
)),
1722 TREE_TYPE (type
), subclasses
, bit_offset
);
1726 /* The partial classes are now full classes. */
1727 if (subclasses
[0] == X86_64_SSESF_CLASS
&& bytes
!= 4)
1728 subclasses
[0] = X86_64_SSE_CLASS
;
1729 if (subclasses
[0] == X86_64_INTEGERSI_CLASS
&& bytes
!= 4)
1730 subclasses
[0] = X86_64_INTEGER_CLASS
;
1732 for (i
= 0; i
< words
; i
++)
1733 classes
[i
] = subclasses
[i
% num
];
1735 /* Unions are similar to RECORD_TYPE but offset is always 0. */
1736 else if (TREE_CODE (type
) == UNION_TYPE
1737 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
1739 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
1741 if (TREE_CODE (field
) == FIELD_DECL
)
1744 num
= classify_argument (TYPE_MODE (TREE_TYPE (field
)),
1745 TREE_TYPE (field
), subclasses
,
1749 for (i
= 0; i
< num
; i
++)
1750 classes
[i
] = merge_classes (subclasses
[i
], classes
[i
]);
1757 /* Final merger cleanup. */
1758 for (i
= 0; i
< words
; i
++)
1760 /* If one class is MEMORY, everything should be passed in
1762 if (classes
[i
] == X86_64_MEMORY_CLASS
)
1765 /* The X86_64_SSEUP_CLASS should be always preceded by
1766 X86_64_SSE_CLASS. */
1767 if (classes
[i
] == X86_64_SSEUP_CLASS
1768 && (i
== 0 || classes
[i
- 1] != X86_64_SSE_CLASS
))
1769 classes
[i
] = X86_64_SSE_CLASS
;
1771 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
1772 if (classes
[i
] == X86_64_X87UP_CLASS
1773 && (i
== 0 || classes
[i
- 1] != X86_64_X87_CLASS
))
1774 classes
[i
] = X86_64_SSE_CLASS
;
1779 /* Compute alignment needed. We align all types to natural boundaries with
1780 exception of XFmode that is aligned to 64bits. */
1781 if (mode
!= VOIDmode
&& mode
!= BLKmode
)
1783 int mode_alignment
= GET_MODE_BITSIZE (mode
);
1786 mode_alignment
= 128;
1787 else if (mode
== XCmode
)
1788 mode_alignment
= 256;
1789 /* Misaligned fields are always returned in memory. */
1790 if (bit_offset
% mode_alignment
)
1794 /* Classification of atomic types. */
1804 if (bit_offset
+ GET_MODE_BITSIZE (mode
) <= 32)
1805 classes
[0] = X86_64_INTEGERSI_CLASS
;
1807 classes
[0] = X86_64_INTEGER_CLASS
;
1811 classes
[0] = classes
[1] = X86_64_INTEGER_CLASS
;
1814 classes
[0] = classes
[1] = X86_64_INTEGER_CLASS
;
1815 classes
[2] = classes
[3] = X86_64_INTEGER_CLASS
;
1818 if (!(bit_offset
% 64))
1819 classes
[0] = X86_64_SSESF_CLASS
;
1821 classes
[0] = X86_64_SSE_CLASS
;
1824 classes
[0] = X86_64_SSEDF_CLASS
;
1827 classes
[0] = X86_64_X87_CLASS
;
1828 classes
[1] = X86_64_X87UP_CLASS
;
1831 classes
[0] = X86_64_X87_CLASS
;
1832 classes
[1] = X86_64_X87UP_CLASS
;
1833 classes
[2] = X86_64_X87_CLASS
;
1834 classes
[3] = X86_64_X87UP_CLASS
;
1837 classes
[0] = X86_64_SSEDF_CLASS
;
1838 classes
[1] = X86_64_SSEDF_CLASS
;
1841 classes
[0] = X86_64_SSE_CLASS
;
1845 classes
[0] = X86_64_SSE_CLASS
;
1846 classes
[1] = X86_64_SSEUP_CLASS
;
1852 classes
[0] = X86_64_SSE_CLASS
;
1862 /* Examine the argument and return set number of register required in each
1863 class. Return 0 iff parameter should be passed in memory. */
1865 examine_argument (mode
, type
, in_return
, int_nregs
, sse_nregs
)
1866 enum machine_mode mode
;
1868 int *int_nregs
, *sse_nregs
;
1871 enum x86_64_reg_class
class[MAX_CLASSES
];
1872 int n
= classify_argument (mode
, type
, class, 0);
1878 for (n
--; n
>= 0; n
--)
1881 case X86_64_INTEGER_CLASS
:
1882 case X86_64_INTEGERSI_CLASS
:
1885 case X86_64_SSE_CLASS
:
1886 case X86_64_SSESF_CLASS
:
1887 case X86_64_SSEDF_CLASS
:
1890 case X86_64_NO_CLASS
:
1891 case X86_64_SSEUP_CLASS
:
1893 case X86_64_X87_CLASS
:
1894 case X86_64_X87UP_CLASS
:
1898 case X86_64_MEMORY_CLASS
:
1903 /* Construct container for the argument used by GCC interface. See
1904 FUNCTION_ARG for the detailed description. */
1906 construct_container (mode
, type
, in_return
, nintregs
, nsseregs
, intreg
, sse_regno
)
1907 enum machine_mode mode
;
1910 int nintregs
, nsseregs
;
1914 enum machine_mode tmpmode
;
1916 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
1917 enum x86_64_reg_class
class[MAX_CLASSES
];
1921 int needed_sseregs
, needed_intregs
;
1922 rtx exp
[MAX_CLASSES
];
1925 n
= classify_argument (mode
, type
, class, 0);
1926 if (TARGET_DEBUG_ARG
)
1929 fprintf (stderr
, "Memory class\n");
1932 fprintf (stderr
, "Classes:");
1933 for (i
= 0; i
< n
; i
++)
1935 fprintf (stderr
, " %s", x86_64_reg_class_name
[class[i
]]);
1937 fprintf (stderr
, "\n");
1942 if (!examine_argument (mode
, type
, in_return
, &needed_intregs
, &needed_sseregs
))
1944 if (needed_intregs
> nintregs
|| needed_sseregs
> nsseregs
)
1947 /* First construct simple cases. Avoid SCmode, since we want to use
1948 single register to pass this type. */
1949 if (n
== 1 && mode
!= SCmode
)
1952 case X86_64_INTEGER_CLASS
:
1953 case X86_64_INTEGERSI_CLASS
:
1954 return gen_rtx_REG (mode
, intreg
[0]);
1955 case X86_64_SSE_CLASS
:
1956 case X86_64_SSESF_CLASS
:
1957 case X86_64_SSEDF_CLASS
:
1958 return gen_rtx_REG (mode
, SSE_REGNO (sse_regno
));
1959 case X86_64_X87_CLASS
:
1960 return gen_rtx_REG (mode
, FIRST_STACK_REG
);
1961 case X86_64_NO_CLASS
:
1962 /* Zero sized array, struct or class. */
1967 if (n
== 2 && class[0] == X86_64_SSE_CLASS
&& class[1] == X86_64_SSEUP_CLASS
)
1968 return gen_rtx_REG (mode
, SSE_REGNO (sse_regno
));
1970 && class[0] == X86_64_X87_CLASS
&& class[1] == X86_64_X87UP_CLASS
)
1971 return gen_rtx_REG (TFmode
, FIRST_STACK_REG
);
1972 if (n
== 2 && class[0] == X86_64_INTEGER_CLASS
1973 && class[1] == X86_64_INTEGER_CLASS
1974 && (mode
== CDImode
|| mode
== TImode
)
1975 && intreg
[0] + 1 == intreg
[1])
1976 return gen_rtx_REG (mode
, intreg
[0]);
1978 && class[0] == X86_64_X87_CLASS
&& class[1] == X86_64_X87UP_CLASS
1979 && class[2] == X86_64_X87_CLASS
&& class[3] == X86_64_X87UP_CLASS
)
1980 return gen_rtx_REG (TCmode
, FIRST_STACK_REG
);
1982 /* Otherwise figure out the entries of the PARALLEL. */
1983 for (i
= 0; i
< n
; i
++)
1987 case X86_64_NO_CLASS
:
1989 case X86_64_INTEGER_CLASS
:
1990 case X86_64_INTEGERSI_CLASS
:
1991 /* Merge TImodes on aligned occassions here too. */
1992 if (i
* 8 + 8 > bytes
)
1993 tmpmode
= mode_for_size ((bytes
- i
* 8) * BITS_PER_UNIT
, MODE_INT
, 0);
1994 else if (class[i
] == X86_64_INTEGERSI_CLASS
)
1998 /* We've requested 24 bytes we don't have mode for. Use DImode. */
1999 if (tmpmode
== BLKmode
)
2001 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2002 gen_rtx_REG (tmpmode
, *intreg
),
2006 case X86_64_SSESF_CLASS
:
2007 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2008 gen_rtx_REG (SFmode
,
2009 SSE_REGNO (sse_regno
)),
2013 case X86_64_SSEDF_CLASS
:
2014 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2015 gen_rtx_REG (DFmode
,
2016 SSE_REGNO (sse_regno
)),
2020 case X86_64_SSE_CLASS
:
2021 if (i
< n
&& class[i
+ 1] == X86_64_SSEUP_CLASS
)
2022 tmpmode
= TImode
, i
++;
2025 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2026 gen_rtx_REG (tmpmode
,
2027 SSE_REGNO (sse_regno
)),
2035 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nexps
));
2036 for (i
= 0; i
< nexps
; i
++)
2037 XVECEXP (ret
, 0, i
) = exp
[i
];
2041 /* Update the data in CUM to advance over an argument
2042 of mode MODE and data type TYPE.
2043 (TYPE is null for libcalls where that information may not be available.) */
2046 function_arg_advance (cum
, mode
, type
, named
)
2047 CUMULATIVE_ARGS
*cum
; /* current arg information */
2048 enum machine_mode mode
; /* current arg mode */
2049 tree type
; /* type of the argument or 0 if lib support */
2050 int named
; /* whether or not the argument was named */
2053 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2054 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2056 if (TARGET_DEBUG_ARG
)
2058 "function_adv (sz=%d, wds=%2d, nregs=%d, mode=%s, named=%d)\n\n",
2059 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
2062 int int_nregs
, sse_nregs
;
2063 if (!examine_argument (mode
, type
, 0, &int_nregs
, &sse_nregs
))
2064 cum
->words
+= words
;
2065 else if (sse_nregs
<= cum
->sse_nregs
&& int_nregs
<= cum
->nregs
)
2067 cum
->nregs
-= int_nregs
;
2068 cum
->sse_nregs
-= sse_nregs
;
2069 cum
->regno
+= int_nregs
;
2070 cum
->sse_regno
+= sse_nregs
;
2073 cum
->words
+= words
;
2077 if (TARGET_SSE
&& mode
== TImode
)
2079 cum
->sse_words
+= words
;
2080 cum
->sse_nregs
-= 1;
2081 cum
->sse_regno
+= 1;
2082 if (cum
->sse_nregs
<= 0)
2090 cum
->words
+= words
;
2091 cum
->nregs
-= words
;
2092 cum
->regno
+= words
;
2094 if (cum
->nregs
<= 0)
2104 /* Define where to put the arguments to a function.
2105 Value is zero to push the argument on the stack,
2106 or a hard register in which to store the argument.
2108 MODE is the argument's machine mode.
2109 TYPE is the data type of the argument (as a tree).
2110 This is null for libcalls where that information may
2112 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2113 the preceding args and about the function being called.
2114 NAMED is nonzero if this argument is a named parameter
2115 (otherwise it is an extra parameter matching an ellipsis). */
2118 function_arg (cum
, mode
, type
, named
)
2119 CUMULATIVE_ARGS
*cum
; /* current arg information */
2120 enum machine_mode mode
; /* current arg mode */
2121 tree type
; /* type of the argument or 0 if lib support */
2122 int named
; /* != 0 for normal args, == 0 for ... args */
2126 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2127 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2129 /* Handle an hidden AL argument containing number of registers for varargs
2130 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
2132 if (mode
== VOIDmode
)
2135 return GEN_INT (cum
->maybe_vaarg
2136 ? (cum
->sse_nregs
< 0
2144 ret
= construct_container (mode
, type
, 0, cum
->nregs
, cum
->sse_nregs
,
2145 &x86_64_int_parameter_registers
[cum
->regno
],
2150 /* For now, pass fp/complex values on the stack. */
2159 if (words
<= cum
->nregs
)
2160 ret
= gen_rtx_REG (mode
, cum
->regno
);
2164 ret
= gen_rtx_REG (mode
, cum
->sse_regno
);
2168 if (TARGET_DEBUG_ARG
)
2171 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d",
2172 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
2175 fprintf (stderr
, ", reg=%%e%s", reg_names
[ REGNO (ret
) ]);
2177 fprintf (stderr
, ", stack");
2179 fprintf (stderr
, " )\n");
2185 /* Gives the alignment boundary, in bits, of an argument with the specified mode
2189 ix86_function_arg_boundary (mode
, type
)
2190 enum machine_mode mode
;
2195 return PARM_BOUNDARY
;
2197 align
= TYPE_ALIGN (type
);
2199 align
= GET_MODE_ALIGNMENT (mode
);
2200 if (align
< PARM_BOUNDARY
)
2201 align
= PARM_BOUNDARY
;
2207 /* Return true if N is a possible register number of function value. */
2209 ix86_function_value_regno_p (regno
)
2214 return ((regno
) == 0
2215 || ((regno
) == FIRST_FLOAT_REG
&& TARGET_FLOAT_RETURNS_IN_80387
)
2216 || ((regno
) == FIRST_SSE_REG
&& TARGET_SSE
));
2218 return ((regno
) == 0 || (regno
) == FIRST_FLOAT_REG
2219 || ((regno
) == FIRST_SSE_REG
&& TARGET_SSE
)
2220 || ((regno
) == FIRST_FLOAT_REG
&& TARGET_FLOAT_RETURNS_IN_80387
));
2223 /* Define how to find the value returned by a function.
2224 VALTYPE is the data type of the value (as a tree).
2225 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2226 otherwise, FUNC is 0. */
2228 ix86_function_value (valtype
)
2233 rtx ret
= construct_container (TYPE_MODE (valtype
), valtype
, 1,
2234 REGPARM_MAX
, SSE_REGPARM_MAX
,
2235 x86_64_int_return_registers
, 0);
2236 /* For zero sized structures, construct_continer return NULL, but we need
2237 to keep rest of compiler happy by returning meaningfull value. */
2239 ret
= gen_rtx_REG (TYPE_MODE (valtype
), 0);
2243 return gen_rtx_REG (TYPE_MODE (valtype
), VALUE_REGNO (TYPE_MODE (valtype
)));
2246 /* Return false iff type is returned in memory. */
2248 ix86_return_in_memory (type
)
2251 int needed_intregs
, needed_sseregs
;
2254 return !examine_argument (TYPE_MODE (type
), type
, 1,
2255 &needed_intregs
, &needed_sseregs
);
2259 if (TYPE_MODE (type
) == BLKmode
2260 || (VECTOR_MODE_P (TYPE_MODE (type
))
2261 && int_size_in_bytes (type
) == 8)
2262 || (int_size_in_bytes (type
) > 12 && TYPE_MODE (type
) != TImode
2263 && TYPE_MODE (type
) != TFmode
2264 && !VECTOR_MODE_P (TYPE_MODE (type
))))
2270 /* Define how to find the value returned by a library function
2271 assuming the value has mode MODE. */
2273 ix86_libcall_value (mode
)
2274 enum machine_mode mode
;
2284 return gen_rtx_REG (mode
, FIRST_SSE_REG
);
2287 return gen_rtx_REG (mode
, FIRST_FLOAT_REG
);
2289 return gen_rtx_REG (mode
, 0);
2293 return gen_rtx_REG (mode
, VALUE_REGNO (mode
));
2296 /* Create the va_list data type. */
2299 ix86_build_va_list ()
2301 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
2303 /* For i386 we use plain pointer to argument area. */
2305 return build_pointer_type (char_type_node
);
2307 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
2308 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
2310 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gp_offset"),
2311 unsigned_type_node
);
2312 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fp_offset"),
2313 unsigned_type_node
);
2314 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
2316 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
2319 DECL_FIELD_CONTEXT (f_gpr
) = record
;
2320 DECL_FIELD_CONTEXT (f_fpr
) = record
;
2321 DECL_FIELD_CONTEXT (f_ovf
) = record
;
2322 DECL_FIELD_CONTEXT (f_sav
) = record
;
2324 TREE_CHAIN (record
) = type_decl
;
2325 TYPE_NAME (record
) = type_decl
;
2326 TYPE_FIELDS (record
) = f_gpr
;
2327 TREE_CHAIN (f_gpr
) = f_fpr
;
2328 TREE_CHAIN (f_fpr
) = f_ovf
;
2329 TREE_CHAIN (f_ovf
) = f_sav
;
2331 layout_type (record
);
2333 /* The correct type is an array type of one element. */
2334 return build_array_type (record
, build_index_type (size_zero_node
));
2337 /* Perform any needed actions needed for a function that is receiving a
2338 variable number of arguments.
2342 MODE and TYPE are the mode and type of the current parameter.
2344 PRETEND_SIZE is a variable that should be set to the amount of stack
2345 that must be pushed by the prolog to pretend that our caller pushed
2348 Normally, this macro will push all remaining incoming registers on the
2349 stack and set PRETEND_SIZE to the length of the registers pushed. */
2352 ix86_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2353 CUMULATIVE_ARGS
*cum
;
2354 enum machine_mode mode
;
2356 int *pretend_size ATTRIBUTE_UNUSED
;
2360 CUMULATIVE_ARGS next_cum
;
2361 rtx save_area
= NULL_RTX
, mem
;
2374 /* Indicate to allocate space on the stack for varargs save area. */
2375 ix86_save_varrargs_registers
= 1;
2377 fntype
= TREE_TYPE (current_function_decl
);
2378 stdarg_p
= (TYPE_ARG_TYPES (fntype
) != 0
2379 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
2380 != void_type_node
));
2382 /* For varargs, we do not want to skip the dummy va_dcl argument.
2383 For stdargs, we do want to skip the last named argument. */
2386 function_arg_advance (&next_cum
, mode
, type
, 1);
2389 save_area
= frame_pointer_rtx
;
2391 set
= get_varargs_alias_set ();
2393 for (i
= next_cum
.regno
; i
< ix86_regparm
; i
++)
2395 mem
= gen_rtx_MEM (Pmode
,
2396 plus_constant (save_area
, i
* UNITS_PER_WORD
));
2397 set_mem_alias_set (mem
, set
);
2398 emit_move_insn (mem
, gen_rtx_REG (Pmode
,
2399 x86_64_int_parameter_registers
[i
]));
2402 if (next_cum
.sse_nregs
)
2404 /* Now emit code to save SSE registers. The AX parameter contains number
2405 of SSE parameter regsiters used to call this function. We use
2406 sse_prologue_save insn template that produces computed jump across
2407 SSE saves. We need some preparation work to get this working. */
2409 label
= gen_label_rtx ();
2410 label_ref
= gen_rtx_LABEL_REF (Pmode
, label
);
2412 /* Compute address to jump to :
2413 label - 5*eax + nnamed_sse_arguments*5 */
2414 tmp_reg
= gen_reg_rtx (Pmode
);
2415 nsse_reg
= gen_reg_rtx (Pmode
);
2416 emit_insn (gen_zero_extendqidi2 (nsse_reg
, gen_rtx_REG (QImode
, 0)));
2417 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
,
2418 gen_rtx_MULT (Pmode
, nsse_reg
,
2420 if (next_cum
.sse_regno
)
2423 gen_rtx_CONST (DImode
,
2424 gen_rtx_PLUS (DImode
,
2426 GEN_INT (next_cum
.sse_regno
* 4))));
2428 emit_move_insn (nsse_reg
, label_ref
);
2429 emit_insn (gen_subdi3 (nsse_reg
, nsse_reg
, tmp_reg
));
2431 /* Compute address of memory block we save into. We always use pointer
2432 pointing 127 bytes after first byte to store - this is needed to keep
2433 instruction size limited by 4 bytes. */
2434 tmp_reg
= gen_reg_rtx (Pmode
);
2435 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
,
2436 plus_constant (save_area
,
2437 8 * REGPARM_MAX
+ 127)));
2438 mem
= gen_rtx_MEM (BLKmode
, plus_constant (tmp_reg
, -127));
2439 set_mem_alias_set (mem
, set
);
2440 set_mem_align (mem
, BITS_PER_WORD
);
2442 /* And finally do the dirty job! */
2443 emit_insn (gen_sse_prologue_save (mem
, nsse_reg
,
2444 GEN_INT (next_cum
.sse_regno
), label
));
2449 /* Implement va_start. */
2452 ix86_va_start (stdarg_p
, valist
, nextarg
)
2457 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
2458 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
2459 tree gpr
, fpr
, ovf
, sav
, t
;
2461 /* Only 64bit target needs something special. */
2464 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
2468 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
2469 f_fpr
= TREE_CHAIN (f_gpr
);
2470 f_ovf
= TREE_CHAIN (f_fpr
);
2471 f_sav
= TREE_CHAIN (f_ovf
);
2473 valist
= build1 (INDIRECT_REF
, TREE_TYPE (TREE_TYPE (valist
)), valist
);
2474 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
);
2475 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
);
2476 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
);
2477 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
);
2479 /* Count number of gp and fp argument registers used. */
2480 words
= current_function_args_info
.words
;
2481 n_gpr
= current_function_args_info
.regno
;
2482 n_fpr
= current_function_args_info
.sse_regno
;
2484 if (TARGET_DEBUG_ARG
)
2485 fprintf (stderr
, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
2486 (int) words
, (int) n_gpr
, (int) n_fpr
);
2488 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
2489 build_int_2 (n_gpr
* 8, 0));
2490 TREE_SIDE_EFFECTS (t
) = 1;
2491 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2493 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
2494 build_int_2 (n_fpr
* 16 + 8*REGPARM_MAX
, 0));
2495 TREE_SIDE_EFFECTS (t
) = 1;
2496 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2498 /* Find the overflow area. */
2499 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
2501 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
2502 build_int_2 (words
* UNITS_PER_WORD
, 0));
2503 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
2504 TREE_SIDE_EFFECTS (t
) = 1;
2505 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2507 /* Find the register save area.
2508 Prologue of the function save it right above stack frame. */
2509 t
= make_tree (TREE_TYPE (sav
), frame_pointer_rtx
);
2510 t
= build (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
2511 TREE_SIDE_EFFECTS (t
) = 1;
2512 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2515 /* Implement va_arg. */
2517 ix86_va_arg (valist
, type
)
2520 static const int intreg
[6] = { 0, 1, 2, 3, 4, 5 };
2521 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
2522 tree gpr
, fpr
, ovf
, sav
, t
;
2524 rtx lab_false
, lab_over
= NULL_RTX
;
2528 /* Only 64bit target needs something special. */
2531 return std_expand_builtin_va_arg (valist
, type
);
2534 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
2535 f_fpr
= TREE_CHAIN (f_gpr
);
2536 f_ovf
= TREE_CHAIN (f_fpr
);
2537 f_sav
= TREE_CHAIN (f_ovf
);
2539 valist
= build1 (INDIRECT_REF
, TREE_TYPE (TREE_TYPE (valist
)), valist
);
2540 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
);
2541 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
);
2542 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
);
2543 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
);
2545 size
= int_size_in_bytes (type
);
2546 rsize
= (size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2548 container
= construct_container (TYPE_MODE (type
), type
, 0,
2549 REGPARM_MAX
, SSE_REGPARM_MAX
, intreg
, 0);
2551 * Pull the value out of the saved registers ...
2554 addr_rtx
= gen_reg_rtx (Pmode
);
2558 rtx int_addr_rtx
, sse_addr_rtx
;
2559 int needed_intregs
, needed_sseregs
;
2562 lab_over
= gen_label_rtx ();
2563 lab_false
= gen_label_rtx ();
2565 examine_argument (TYPE_MODE (type
), type
, 0,
2566 &needed_intregs
, &needed_sseregs
);
2569 need_temp
= ((needed_intregs
&& TYPE_ALIGN (type
) > 64)
2570 || TYPE_ALIGN (type
) > 128);
2572 /* In case we are passing structure, verify that it is consetuctive block
2573 on the register save area. If not we need to do moves. */
2574 if (!need_temp
&& !REG_P (container
))
2576 /* Verify that all registers are strictly consetuctive */
2577 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container
, 0, 0), 0))))
2581 for (i
= 0; i
< XVECLEN (container
, 0) && !need_temp
; i
++)
2583 rtx slot
= XVECEXP (container
, 0, i
);
2584 if (REGNO (XEXP (slot
, 0)) != FIRST_SSE_REG
+ (unsigned int) i
2585 || INTVAL (XEXP (slot
, 1)) != i
* 16)
2593 for (i
= 0; i
< XVECLEN (container
, 0) && !need_temp
; i
++)
2595 rtx slot
= XVECEXP (container
, 0, i
);
2596 if (REGNO (XEXP (slot
, 0)) != (unsigned int) i
2597 || INTVAL (XEXP (slot
, 1)) != i
* 8)
2604 int_addr_rtx
= addr_rtx
;
2605 sse_addr_rtx
= addr_rtx
;
2609 int_addr_rtx
= gen_reg_rtx (Pmode
);
2610 sse_addr_rtx
= gen_reg_rtx (Pmode
);
2612 /* First ensure that we fit completely in registers. */
2615 emit_cmp_and_jump_insns (expand_expr
2616 (gpr
, NULL_RTX
, SImode
, EXPAND_NORMAL
),
2617 GEN_INT ((REGPARM_MAX
- needed_intregs
+
2618 1) * 8), GE
, const1_rtx
, SImode
,
2623 emit_cmp_and_jump_insns (expand_expr
2624 (fpr
, NULL_RTX
, SImode
, EXPAND_NORMAL
),
2625 GEN_INT ((SSE_REGPARM_MAX
-
2626 needed_sseregs
+ 1) * 16 +
2627 REGPARM_MAX
* 8), GE
, const1_rtx
,
2628 SImode
, 1, lab_false
);
2631 /* Compute index to start of area used for integer regs. */
2634 t
= build (PLUS_EXPR
, ptr_type_node
, sav
, gpr
);
2635 r
= expand_expr (t
, int_addr_rtx
, Pmode
, EXPAND_NORMAL
);
2636 if (r
!= int_addr_rtx
)
2637 emit_move_insn (int_addr_rtx
, r
);
2641 t
= build (PLUS_EXPR
, ptr_type_node
, sav
, fpr
);
2642 r
= expand_expr (t
, sse_addr_rtx
, Pmode
, EXPAND_NORMAL
);
2643 if (r
!= sse_addr_rtx
)
2644 emit_move_insn (sse_addr_rtx
, r
);
2651 /* Never use the memory itself, as it has the alias set. */
2652 addr_rtx
= XEXP (assign_temp (type
, 0, 1, 0), 0);
2653 mem
= gen_rtx_MEM (BLKmode
, addr_rtx
);
2654 set_mem_alias_set (mem
, get_varargs_alias_set ());
2655 set_mem_align (mem
, BITS_PER_UNIT
);
2657 for (i
= 0; i
< XVECLEN (container
, 0); i
++)
2659 rtx slot
= XVECEXP (container
, 0, i
);
2660 rtx reg
= XEXP (slot
, 0);
2661 enum machine_mode mode
= GET_MODE (reg
);
2667 if (SSE_REGNO_P (REGNO (reg
)))
2669 src_addr
= sse_addr_rtx
;
2670 src_offset
= (REGNO (reg
) - FIRST_SSE_REG
) * 16;
2674 src_addr
= int_addr_rtx
;
2675 src_offset
= REGNO (reg
) * 8;
2677 src_mem
= gen_rtx_MEM (mode
, src_addr
);
2678 set_mem_alias_set (src_mem
, get_varargs_alias_set ());
2679 src_mem
= adjust_address (src_mem
, mode
, src_offset
);
2680 dest_mem
= adjust_address (mem
, mode
, INTVAL (XEXP (slot
, 1)));
2681 emit_move_insn (dest_mem
, src_mem
);
2688 build (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
2689 build_int_2 (needed_intregs
* 8, 0));
2690 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
2691 TREE_SIDE_EFFECTS (t
) = 1;
2692 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2697 build (PLUS_EXPR
, TREE_TYPE (fpr
), fpr
,
2698 build_int_2 (needed_sseregs
* 16, 0));
2699 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
, t
);
2700 TREE_SIDE_EFFECTS (t
) = 1;
2701 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2704 emit_jump_insn (gen_jump (lab_over
));
2706 emit_label (lab_false
);
2709 /* ... otherwise out of the overflow area. */
2711 /* Care for on-stack alignment if needed. */
2712 if (FUNCTION_ARG_BOUNDARY (VOIDmode
, type
) <= 64)
2716 HOST_WIDE_INT align
= FUNCTION_ARG_BOUNDARY (VOIDmode
, type
) / 8;
2717 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), ovf
, build_int_2 (align
- 1, 0));
2718 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, build_int_2 (-align
, -1));
2722 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
2724 emit_move_insn (addr_rtx
, r
);
2727 build (PLUS_EXPR
, TREE_TYPE (t
), t
,
2728 build_int_2 (rsize
* UNITS_PER_WORD
, 0));
2729 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
2730 TREE_SIDE_EFFECTS (t
) = 1;
2731 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2734 emit_label (lab_over
);
2739 /* Return nonzero if OP is general operand representable on x86_64. */
2742 x86_64_general_operand (op
, mode
)
2744 enum machine_mode mode
;
2747 return general_operand (op
, mode
);
2748 if (nonimmediate_operand (op
, mode
))
2750 return x86_64_sign_extended_value (op
);
2753 /* Return nonzero if OP is general operand representable on x86_64
2754 as either sign extended or zero extended constant. */
2757 x86_64_szext_general_operand (op
, mode
)
2759 enum machine_mode mode
;
2762 return general_operand (op
, mode
);
2763 if (nonimmediate_operand (op
, mode
))
2765 return x86_64_sign_extended_value (op
) || x86_64_zero_extended_value (op
);
2768 /* Return nonzero if OP is nonmemory operand representable on x86_64. */
2771 x86_64_nonmemory_operand (op
, mode
)
2773 enum machine_mode mode
;
2776 return nonmemory_operand (op
, mode
);
2777 if (register_operand (op
, mode
))
2779 return x86_64_sign_extended_value (op
);
2782 /* Return nonzero if OP is nonmemory operand acceptable by movabs patterns. */
2785 x86_64_movabs_operand (op
, mode
)
2787 enum machine_mode mode
;
2789 if (!TARGET_64BIT
|| !flag_pic
)
2790 return nonmemory_operand (op
, mode
);
2791 if (register_operand (op
, mode
) || x86_64_sign_extended_value (op
))
2793 if (CONSTANT_P (op
) && !symbolic_reference_mentioned_p (op
))
2798 /* Return nonzero if OP is nonmemory operand representable on x86_64. */
2801 x86_64_szext_nonmemory_operand (op
, mode
)
2803 enum machine_mode mode
;
2806 return nonmemory_operand (op
, mode
);
2807 if (register_operand (op
, mode
))
2809 return x86_64_sign_extended_value (op
) || x86_64_zero_extended_value (op
);
2812 /* Return nonzero if OP is immediate operand representable on x86_64. */
2815 x86_64_immediate_operand (op
, mode
)
2817 enum machine_mode mode
;
2820 return immediate_operand (op
, mode
);
2821 return x86_64_sign_extended_value (op
);
2824 /* Return nonzero if OP is immediate operand representable on x86_64. */
2827 x86_64_zext_immediate_operand (op
, mode
)
2829 enum machine_mode mode ATTRIBUTE_UNUSED
;
2831 return x86_64_zero_extended_value (op
);
2834 /* Return nonzero if OP is (const_int 1), else return zero. */
2837 const_int_1_operand (op
, mode
)
2839 enum machine_mode mode ATTRIBUTE_UNUSED
;
2841 return (GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 1);
2844 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
2845 reference and a constant. */
2848 symbolic_operand (op
, mode
)
2850 enum machine_mode mode ATTRIBUTE_UNUSED
;
2852 switch (GET_CODE (op
))
2860 if (GET_CODE (op
) == SYMBOL_REF
2861 || GET_CODE (op
) == LABEL_REF
2862 || (GET_CODE (op
) == UNSPEC
2863 && (XINT (op
, 1) == 6
2864 || XINT (op
, 1) == 7
2865 || XINT (op
, 1) == 15)))
2867 if (GET_CODE (op
) != PLUS
2868 || GET_CODE (XEXP (op
, 1)) != CONST_INT
)
2872 if (GET_CODE (op
) == SYMBOL_REF
2873 || GET_CODE (op
) == LABEL_REF
)
2875 /* Only @GOTOFF gets offsets. */
2876 if (GET_CODE (op
) != UNSPEC
2877 || XINT (op
, 1) != 7)
2880 op
= XVECEXP (op
, 0, 0);
2881 if (GET_CODE (op
) == SYMBOL_REF
2882 || GET_CODE (op
) == LABEL_REF
)
2891 /* Return true if the operand contains a @GOT or @GOTOFF reference. */
2894 pic_symbolic_operand (op
, mode
)
2896 enum machine_mode mode ATTRIBUTE_UNUSED
;
2898 if (GET_CODE (op
) != CONST
)
2903 if (GET_CODE (XEXP (op
, 0)) == UNSPEC
)
2908 if (GET_CODE (op
) == UNSPEC
)
2910 if (GET_CODE (op
) != PLUS
2911 || GET_CODE (XEXP (op
, 1)) != CONST_INT
)
2914 if (GET_CODE (op
) == UNSPEC
)
2920 /* Return true if OP is a symbolic operand that resolves locally. */
2923 local_symbolic_operand (op
, mode
)
2925 enum machine_mode mode ATTRIBUTE_UNUSED
;
2927 if (GET_CODE (op
) == LABEL_REF
)
2930 if (GET_CODE (op
) == CONST
2931 && GET_CODE (XEXP (op
, 0)) == PLUS
2932 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
2933 op
= XEXP (XEXP (op
, 0), 0);
2935 if (GET_CODE (op
) != SYMBOL_REF
)
2938 /* These we've been told are local by varasm and encode_section_info
2940 if (CONSTANT_POOL_ADDRESS_P (op
) || SYMBOL_REF_FLAG (op
))
2943 /* There is, however, a not insubstantial body of code in the rest of
2944 the compiler that assumes it can just stick the results of
2945 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
2946 /* ??? This is a hack. Should update the body of the compiler to
2947 always create a DECL an invoke ENCODE_SECTION_INFO. */
2948 if (strncmp (XSTR (op
, 0), internal_label_prefix
,
2949 internal_label_prefix_len
) == 0)
2955 /* Test for a valid operand for a call instruction. Don't allow the
2956 arg pointer register or virtual regs since they may decay into
2957 reg + const, which the patterns can't handle. */
2960 call_insn_operand (op
, mode
)
2962 enum machine_mode mode ATTRIBUTE_UNUSED
;
2964 /* Disallow indirect through a virtual register. This leads to
2965 compiler aborts when trying to eliminate them. */
2966 if (GET_CODE (op
) == REG
2967 && (op
== arg_pointer_rtx
2968 || op
== frame_pointer_rtx
2969 || (REGNO (op
) >= FIRST_PSEUDO_REGISTER
2970 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)))
2973 /* Disallow `call 1234'. Due to varying assembler lameness this
2974 gets either rejected or translated to `call .+1234'. */
2975 if (GET_CODE (op
) == CONST_INT
)
2978 /* Explicitly allow SYMBOL_REF even if pic. */
2979 if (GET_CODE (op
) == SYMBOL_REF
)
2982 /* Half-pic doesn't allow anything but registers and constants.
2983 We've just taken care of the later. */
2985 return register_operand (op
, Pmode
);
2987 /* Otherwise we can allow any general_operand in the address. */
2988 return general_operand (op
, Pmode
);
2992 constant_call_address_operand (op
, mode
)
2994 enum machine_mode mode ATTRIBUTE_UNUSED
;
2996 if (GET_CODE (op
) == CONST
2997 && GET_CODE (XEXP (op
, 0)) == PLUS
2998 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
2999 op
= XEXP (XEXP (op
, 0), 0);
3000 return GET_CODE (op
) == SYMBOL_REF
;
3003 /* Match exactly zero and one. */
3006 const0_operand (op
, mode
)
3008 enum machine_mode mode
;
3010 return op
== CONST0_RTX (mode
);
3014 const1_operand (op
, mode
)
3016 enum machine_mode mode ATTRIBUTE_UNUSED
;
3018 return op
== const1_rtx
;
3021 /* Match 2, 4, or 8. Used for leal multiplicands. */
3024 const248_operand (op
, mode
)
3026 enum machine_mode mode ATTRIBUTE_UNUSED
;
3028 return (GET_CODE (op
) == CONST_INT
3029 && (INTVAL (op
) == 2 || INTVAL (op
) == 4 || INTVAL (op
) == 8));
3032 /* True if this is a constant appropriate for an increment or decremenmt. */
3035 incdec_operand (op
, mode
)
3037 enum machine_mode mode ATTRIBUTE_UNUSED
;
3039 /* On Pentium4, the inc and dec operations causes extra dependency on flag
3040 registers, since carry flag is not set. */
3041 if (TARGET_PENTIUM4
&& !optimize_size
)
3043 return op
== const1_rtx
|| op
== constm1_rtx
;
3046 /* Return nonzero if OP is acceptable as operand of DImode shift
3050 shiftdi_operand (op
, mode
)
3052 enum machine_mode mode ATTRIBUTE_UNUSED
;
3055 return nonimmediate_operand (op
, mode
);
3057 return register_operand (op
, mode
);
3060 /* Return false if this is the stack pointer, or any other fake
3061 register eliminable to the stack pointer. Otherwise, this is
3064 This is used to prevent esp from being used as an index reg.
3065 Which would only happen in pathological cases. */
3068 reg_no_sp_operand (op
, mode
)
3070 enum machine_mode mode
;
3073 if (GET_CODE (t
) == SUBREG
)
3075 if (t
== stack_pointer_rtx
|| t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
)
3078 return register_operand (op
, mode
);
3082 mmx_reg_operand (op
, mode
)
3084 enum machine_mode mode ATTRIBUTE_UNUSED
;
3086 return MMX_REG_P (op
);
3089 /* Return false if this is any eliminable register. Otherwise
3093 general_no_elim_operand (op
, mode
)
3095 enum machine_mode mode
;
3098 if (GET_CODE (t
) == SUBREG
)
3100 if (t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
3101 || t
== virtual_incoming_args_rtx
|| t
== virtual_stack_vars_rtx
3102 || t
== virtual_stack_dynamic_rtx
)
3105 && REGNO (t
) >= FIRST_VIRTUAL_REGISTER
3106 && REGNO (t
) <= LAST_VIRTUAL_REGISTER
)
3109 return general_operand (op
, mode
);
3112 /* Return false if this is any eliminable register. Otherwise
3113 register_operand or const_int. */
3116 nonmemory_no_elim_operand (op
, mode
)
3118 enum machine_mode mode
;
3121 if (GET_CODE (t
) == SUBREG
)
3123 if (t
== arg_pointer_rtx
|| t
== frame_pointer_rtx
3124 || t
== virtual_incoming_args_rtx
|| t
== virtual_stack_vars_rtx
3125 || t
== virtual_stack_dynamic_rtx
)
3128 return GET_CODE (op
) == CONST_INT
|| register_operand (op
, mode
);
3131 /* Return true if op is a Q_REGS class register. */
3134 q_regs_operand (op
, mode
)
3136 enum machine_mode mode
;
3138 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3140 if (GET_CODE (op
) == SUBREG
)
3141 op
= SUBREG_REG (op
);
3142 return QI_REG_P (op
);
3145 /* Return true if op is a NON_Q_REGS class register. */
3148 non_q_regs_operand (op
, mode
)
3150 enum machine_mode mode
;
3152 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3154 if (GET_CODE (op
) == SUBREG
)
3155 op
= SUBREG_REG (op
);
3156 return NON_QI_REG_P (op
);
3159 /* Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS
3162 sse_comparison_operator (op
, mode
)
3164 enum machine_mode mode ATTRIBUTE_UNUSED
;
3166 enum rtx_code code
= GET_CODE (op
);
3169 /* Operations supported directly. */
3179 /* These are equivalent to ones above in non-IEEE comparisons. */
3186 return !TARGET_IEEE_FP
;
3191 /* Return 1 if OP is a valid comparison operator in valid mode. */
3193 ix86_comparison_operator (op
, mode
)
3195 enum machine_mode mode
;
3197 enum machine_mode inmode
;
3198 enum rtx_code code
= GET_CODE (op
);
3199 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3201 if (GET_RTX_CLASS (code
) != '<')
3203 inmode
= GET_MODE (XEXP (op
, 0));
3205 if (inmode
== CCFPmode
|| inmode
== CCFPUmode
)
3207 enum rtx_code second_code
, bypass_code
;
3208 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
3209 return (bypass_code
== NIL
&& second_code
== NIL
);
3216 if (inmode
== CCmode
|| inmode
== CCGCmode
3217 || inmode
== CCGOCmode
|| inmode
== CCNOmode
)
3220 case LTU
: case GTU
: case LEU
: case ORDERED
: case UNORDERED
: case GEU
:
3221 if (inmode
== CCmode
)
3225 if (inmode
== CCmode
|| inmode
== CCGCmode
|| inmode
== CCNOmode
)
3233 /* Return 1 if OP is a comparison operator that can be issued by fcmov. */
3236 fcmov_comparison_operator (op
, mode
)
3238 enum machine_mode mode
;
3240 enum machine_mode inmode
;
3241 enum rtx_code code
= GET_CODE (op
);
3242 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3244 if (GET_RTX_CLASS (code
) != '<')
3246 inmode
= GET_MODE (XEXP (op
, 0));
3247 if (inmode
== CCFPmode
|| inmode
== CCFPUmode
)
3249 enum rtx_code second_code
, bypass_code
;
3250 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
3251 if (bypass_code
!= NIL
|| second_code
!= NIL
)
3253 code
= ix86_fp_compare_code_to_integer (code
);
3255 /* i387 supports just limited amount of conditional codes. */
3258 case LTU
: case GTU
: case LEU
: case GEU
:
3259 if (inmode
== CCmode
|| inmode
== CCFPmode
|| inmode
== CCFPUmode
)
3262 case ORDERED
: case UNORDERED
:
3270 /* Return 1 if OP is a binary operator that can be promoted to wider mode. */
3273 promotable_binary_operator (op
, mode
)
3275 enum machine_mode mode ATTRIBUTE_UNUSED
;
3277 switch (GET_CODE (op
))
3280 /* Modern CPUs have same latency for HImode and SImode multiply,
3281 but 386 and 486 do HImode multiply faster. */
3282 return ix86_cpu
> PROCESSOR_I486
;
3294 /* Nearly general operand, but accept any const_double, since we wish
3295 to be able to drop them into memory rather than have them get pulled
3299 cmp_fp_expander_operand (op
, mode
)
3301 enum machine_mode mode
;
3303 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
3305 if (GET_CODE (op
) == CONST_DOUBLE
)
3307 return general_operand (op
, mode
);
3310 /* Match an SI or HImode register for a zero_extract. */
3313 ext_register_operand (op
, mode
)
3315 enum machine_mode mode ATTRIBUTE_UNUSED
;
3318 if ((!TARGET_64BIT
|| GET_MODE (op
) != DImode
)
3319 && GET_MODE (op
) != SImode
&& GET_MODE (op
) != HImode
)
3322 if (!register_operand (op
, VOIDmode
))
3325 /* Be curefull to accept only registers having upper parts. */
3326 regno
= REG_P (op
) ? REGNO (op
) : REGNO (SUBREG_REG (op
));
3327 return (regno
> LAST_VIRTUAL_REGISTER
|| regno
< 4);
3330 /* Return 1 if this is a valid binary floating-point operation.
3331 OP is the expression matched, and MODE is its mode. */
3334 binary_fp_operator (op
, mode
)
3336 enum machine_mode mode
;
3338 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
3341 switch (GET_CODE (op
))
3347 return GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
;
3355 mult_operator (op
, mode
)
3357 enum machine_mode mode ATTRIBUTE_UNUSED
;
3359 return GET_CODE (op
) == MULT
;
3363 div_operator (op
, mode
)
3365 enum machine_mode mode ATTRIBUTE_UNUSED
;
3367 return GET_CODE (op
) == DIV
;
3371 arith_or_logical_operator (op
, mode
)
3373 enum machine_mode mode
;
3375 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
3376 && (GET_RTX_CLASS (GET_CODE (op
)) == 'c'
3377 || GET_RTX_CLASS (GET_CODE (op
)) == '2'));
3380 /* Returns 1 if OP is memory operand with a displacement. */
3383 memory_displacement_operand (op
, mode
)
3385 enum machine_mode mode
;
3387 struct ix86_address parts
;
3389 if (! memory_operand (op
, mode
))
3392 if (! ix86_decompose_address (XEXP (op
, 0), &parts
))
3395 return parts
.disp
!= NULL_RTX
;
3398 /* To avoid problems when jump re-emits comparisons like testqi_ext_ccno_0,
3399 re-recognize the operand to avoid a copy_to_mode_reg that will fail.
3401 ??? It seems likely that this will only work because cmpsi is an
3402 expander, and no actual insns use this. */
3405 cmpsi_operand (op
, mode
)
3407 enum machine_mode mode
;
3409 if (nonimmediate_operand (op
, mode
))
3412 if (GET_CODE (op
) == AND
3413 && GET_MODE (op
) == SImode
3414 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTRACT
3415 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
3416 && GET_CODE (XEXP (XEXP (op
, 0), 2)) == CONST_INT
3417 && INTVAL (XEXP (XEXP (op
, 0), 1)) == 8
3418 && INTVAL (XEXP (XEXP (op
, 0), 2)) == 8
3419 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
3425 /* Returns 1 if OP is memory operand that can not be represented by the
3429 long_memory_operand (op
, mode
)
3431 enum machine_mode mode
;
3433 if (! memory_operand (op
, mode
))
3436 return memory_address_length (op
) != 0;
3439 /* Return nonzero if the rtx is known aligned. */
3442 aligned_operand (op
, mode
)
3444 enum machine_mode mode
;
3446 struct ix86_address parts
;
3448 if (!general_operand (op
, mode
))
3451 /* Registers and immediate operands are always "aligned". */
3452 if (GET_CODE (op
) != MEM
)
3455 /* Don't even try to do any aligned optimizations with volatiles. */
3456 if (MEM_VOLATILE_P (op
))
3461 /* Pushes and pops are only valid on the stack pointer. */
3462 if (GET_CODE (op
) == PRE_DEC
3463 || GET_CODE (op
) == POST_INC
)
3466 /* Decode the address. */
3467 if (! ix86_decompose_address (op
, &parts
))
3470 if (parts
.base
&& GET_CODE (parts
.base
) == SUBREG
)
3471 parts
.base
= SUBREG_REG (parts
.base
);
3472 if (parts
.index
&& GET_CODE (parts
.index
) == SUBREG
)
3473 parts
.index
= SUBREG_REG (parts
.index
);
3475 /* Look for some component that isn't known to be aligned. */
3479 && REGNO_POINTER_ALIGN (REGNO (parts
.index
)) < 32)
3484 if (REGNO_POINTER_ALIGN (REGNO (parts
.base
)) < 32)
3489 if (GET_CODE (parts
.disp
) != CONST_INT
3490 || (INTVAL (parts
.disp
) & 3) != 0)
3494 /* Didn't find one -- this must be an aligned address. */
3498 /* Return true if the constant is something that can be loaded with
3499 a special instruction. Only handle 0.0 and 1.0; others are less
3503 standard_80387_constant_p (x
)
3506 if (GET_CODE (x
) != CONST_DOUBLE
|| !FLOAT_MODE_P (GET_MODE (x
)))
3508 /* Note that on the 80387, other constants, such as pi, that we should support
3509 too. On some machines, these are much slower to load as standard constant,
3510 than to load from doubles in memory. */
3511 if (x
== CONST0_RTX (GET_MODE (x
)))
3513 if (x
== CONST1_RTX (GET_MODE (x
)))
3518 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
3521 standard_sse_constant_p (x
)
3524 if (GET_CODE (x
) != CONST_DOUBLE
)
3526 return (x
== CONST0_RTX (GET_MODE (x
)));
3529 /* Returns 1 if OP contains a symbol reference */
3532 symbolic_reference_mentioned_p (op
)
3535 register const char *fmt
;
3538 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
3541 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3542 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3548 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3549 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3553 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
3560 /* Return 1 if it is appropriate to emit `ret' instructions in the
3561 body of a function. Do this only if the epilogue is simple, needing a
3562 couple of insns. Prior to reloading, we can't tell how many registers
3563 must be saved, so return 0 then. Return 0 if there is no frame
3564 marker to de-allocate.
3566 If NON_SAVING_SETJMP is defined and true, then it is not possible
3567 for the epilogue to be simple, so return 0. This is a special case
3568 since NON_SAVING_SETJMP will not cause regs_ever_live to change
3569 until final, but jump_optimize may need to know sooner if a
3573 ix86_can_use_return_insn_p ()
3575 struct ix86_frame frame
;
3577 #ifdef NON_SAVING_SETJMP
3578 if (NON_SAVING_SETJMP
&& current_function_calls_setjmp
)
3582 if (! reload_completed
|| frame_pointer_needed
)
3585 /* Don't allow more than 32 pop, since that's all we can do
3586 with one instruction. */
3587 if (current_function_pops_args
3588 && current_function_args_size
>= 32768)
3591 ix86_compute_frame_layout (&frame
);
3592 return frame
.to_allocate
== 0 && frame
.nregs
== 0;
3595 /* Return 1 if VALUE can be stored in the sign extended immediate field. */
3597 x86_64_sign_extended_value (value
)
3600 switch (GET_CODE (value
))
3602 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
3603 to be at least 32 and this all acceptable constants are
3604 represented as CONST_INT. */
3606 if (HOST_BITS_PER_WIDE_INT
== 32)
3610 HOST_WIDE_INT val
= trunc_int_for_mode (INTVAL (value
), DImode
);
3611 return trunc_int_for_mode (val
, SImode
) == val
;
3615 /* For certain code models, the symbolic references are known to fit. */
3617 return ix86_cmodel
== CM_SMALL
|| ix86_cmodel
== CM_KERNEL
;
3619 /* For certain code models, the code is near as well. */
3621 return ix86_cmodel
!= CM_LARGE
&& ix86_cmodel
!= CM_SMALL_PIC
;
3623 /* We also may accept the offsetted memory references in certain special
3626 if (GET_CODE (XEXP (value
, 0)) == UNSPEC
3627 && XVECLEN (XEXP (value
, 0), 0) == 1
3628 && XINT (XEXP (value
, 0), 1) == 15)
3630 else if (GET_CODE (XEXP (value
, 0)) == PLUS
)
3632 rtx op1
= XEXP (XEXP (value
, 0), 0);
3633 rtx op2
= XEXP (XEXP (value
, 0), 1);
3634 HOST_WIDE_INT offset
;
3636 if (ix86_cmodel
== CM_LARGE
)
3638 if (GET_CODE (op2
) != CONST_INT
)
3640 offset
= trunc_int_for_mode (INTVAL (op2
), DImode
);
3641 switch (GET_CODE (op1
))
3644 /* For CM_SMALL assume that latest object is 1MB before
3645 end of 31bits boundary. We may also accept pretty
3646 large negative constants knowing that all objects are
3647 in the positive half of address space. */
3648 if (ix86_cmodel
== CM_SMALL
3649 && offset
< 1024*1024*1024
3650 && trunc_int_for_mode (offset
, SImode
) == offset
)
3652 /* For CM_KERNEL we know that all object resist in the
3653 negative half of 32bits address space. We may not
3654 accept negative offsets, since they may be just off
3655 and we may accept pretty large positive ones. */
3656 if (ix86_cmodel
== CM_KERNEL
3658 && trunc_int_for_mode (offset
, SImode
) == offset
)
3662 /* These conditions are similar to SYMBOL_REF ones, just the
3663 constraints for code models differ. */
3664 if ((ix86_cmodel
== CM_SMALL
|| ix86_cmodel
== CM_MEDIUM
)
3665 && offset
< 1024*1024*1024
3666 && trunc_int_for_mode (offset
, SImode
) == offset
)
3668 if (ix86_cmodel
== CM_KERNEL
3670 && trunc_int_for_mode (offset
, SImode
) == offset
)
3683 /* Return 1 if VALUE can be stored in the zero extended immediate field. */
3685 x86_64_zero_extended_value (value
)
3688 switch (GET_CODE (value
))
3691 if (HOST_BITS_PER_WIDE_INT
== 32)
3692 return (GET_MODE (value
) == VOIDmode
3693 && !CONST_DOUBLE_HIGH (value
));
3697 if (HOST_BITS_PER_WIDE_INT
== 32)
3698 return INTVAL (value
) >= 0;
3700 return !(INTVAL (value
) & ~(HOST_WIDE_INT
) 0xffffffff);
3703 /* For certain code models, the symbolic references are known to fit. */
3705 return ix86_cmodel
== CM_SMALL
;
3707 /* For certain code models, the code is near as well. */
3709 return ix86_cmodel
== CM_SMALL
|| ix86_cmodel
== CM_MEDIUM
;
3711 /* We also may accept the offsetted memory references in certain special
3714 if (GET_CODE (XEXP (value
, 0)) == PLUS
)
3716 rtx op1
= XEXP (XEXP (value
, 0), 0);
3717 rtx op2
= XEXP (XEXP (value
, 0), 1);
3719 if (ix86_cmodel
== CM_LARGE
)
3721 switch (GET_CODE (op1
))
3725 /* For small code model we may accept pretty large positive
3726 offsets, since one bit is available for free. Negative
3727 offsets are limited by the size of NULL pointer area
3728 specified by the ABI. */
3729 if (ix86_cmodel
== CM_SMALL
3730 && GET_CODE (op2
) == CONST_INT
3731 && trunc_int_for_mode (INTVAL (op2
), DImode
) > -0x10000
3732 && (trunc_int_for_mode (INTVAL (op2
), SImode
)
3735 /* ??? For the kernel, we may accept adjustment of
3736 -0x10000000, since we know that it will just convert
3737 negative address space to positive, but perhaps this
3738 is not worthwhile. */
3741 /* These conditions are similar to SYMBOL_REF ones, just the
3742 constraints for code models differ. */
3743 if ((ix86_cmodel
== CM_SMALL
|| ix86_cmodel
== CM_MEDIUM
)
3744 && GET_CODE (op2
) == CONST_INT
3745 && trunc_int_for_mode (INTVAL (op2
), DImode
) > -0x10000
3746 && (trunc_int_for_mode (INTVAL (op2
), SImode
)
3760 /* Value should be nonzero if functions must have frame pointers.
3761 Zero means the frame pointer need not be set up (and parms may
3762 be accessed via the stack pointer) in functions that seem suitable. */
3765 ix86_frame_pointer_required ()
3767 /* If we accessed previous frames, then the generated code expects
3768 to be able to access the saved ebp value in our frame. */
3769 if (cfun
->machine
->accesses_prev_frame
)
3772 /* Several x86 os'es need a frame pointer for other reasons,
3773 usually pertaining to setjmp. */
3774 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
3777 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
3778 the frame pointer by default. Turn it back on now if we've not
3779 got a leaf function. */
3780 if (TARGET_OMIT_LEAF_FRAME_POINTER
&& ! leaf_function_p ())
3786 /* Record that the current function accesses previous call frames. */
3789 ix86_setup_frame_addresses ()
3791 cfun
->machine
->accesses_prev_frame
= 1;
3794 static char pic_label_name
[32];
3796 /* This function generates code for -fpic that loads %ebx with
3797 the return address of the caller and then returns. */
3800 ix86_asm_file_end (file
)
3805 if (! TARGET_DEEP_BRANCH_PREDICTION
|| pic_label_name
[0] == 0)
3808 /* ??? Binutils 2.10 and earlier has a linkonce elimination bug related
3809 to updating relocations to a section being discarded such that this
3810 doesn't work. Ought to detect this at configure time. */
3812 /* The trick here is to create a linkonce section containing the
3813 pic label thunk, but to refer to it with an internal label.
3814 Because the label is internal, we don't have inter-dso name
3815 binding issues on hosts that don't support ".hidden".
3817 In order to use these macros, however, we must create a fake
3819 if (targetm
.have_named_sections
)
3821 tree decl
= build_decl (FUNCTION_DECL
,
3822 get_identifier ("i686.get_pc_thunk"),
3824 DECL_ONE_ONLY (decl
) = 1;
3825 UNIQUE_SECTION (decl
, 0);
3826 named_section (decl
, NULL
);
3833 /* This used to call ASM_DECLARE_FUNCTION_NAME() but since it's an
3834 internal (non-global) label that's being emitted, it didn't make
3835 sense to have .type information for local labels. This caused
3836 the SCO OpenServer 5.0.4 ELF assembler grief (why are you giving
3837 me debug info for a label that you're declaring non-global?) this
3838 was changed to call ASM_OUTPUT_LABEL() instead. */
3840 ASM_OUTPUT_LABEL (file
, pic_label_name
);
3842 xops
[0] = pic_offset_table_rtx
;
3843 xops
[1] = gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3844 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops
);
3845 output_asm_insn ("ret", xops
);
3849 load_pic_register ()
3856 gotsym
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3858 if (TARGET_DEEP_BRANCH_PREDICTION
)
3860 if (! pic_label_name
[0])
3861 ASM_GENERATE_INTERNAL_LABEL (pic_label_name
, "LPR", 0);
3862 pclab
= gen_rtx_MEM (QImode
, gen_rtx_SYMBOL_REF (Pmode
, pic_label_name
));
3866 pclab
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
3869 emit_insn (gen_prologue_get_pc (pic_offset_table_rtx
, pclab
));
3871 if (! TARGET_DEEP_BRANCH_PREDICTION
)
3872 emit_insn (gen_popsi1 (pic_offset_table_rtx
));
3874 emit_insn (gen_prologue_set_got (pic_offset_table_rtx
, gotsym
, pclab
));
3877 /* Generate an "push" pattern for input ARG. */
3883 return gen_rtx_SET (VOIDmode
,
3885 gen_rtx_PRE_DEC (Pmode
,
3886 stack_pointer_rtx
)),
3890 /* Return 1 if we need to save REGNO. */
3892 ix86_save_reg (regno
, maybe_eh_return
)
3894 int maybe_eh_return
;
3896 if (regno
== PIC_OFFSET_TABLE_REGNUM
3897 && (current_function_uses_pic_offset_table
3898 || current_function_uses_const_pool
3899 || current_function_calls_eh_return
))
3902 if (current_function_calls_eh_return
&& maybe_eh_return
)
3907 unsigned test
= EH_RETURN_DATA_REGNO (i
);
3908 if (test
== INVALID_REGNUM
)
3910 if (test
== (unsigned) regno
)
3915 return (regs_ever_live
[regno
]
3916 && !call_used_regs
[regno
]
3917 && !fixed_regs
[regno
]
3918 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
));
3921 /* Return number of registers to be saved on the stack. */
3929 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
3930 if (ix86_save_reg (regno
, true))
3935 /* Return the offset between two registers, one to be eliminated, and the other
3936 its replacement, at the start of a routine. */
3939 ix86_initial_elimination_offset (from
, to
)
3943 struct ix86_frame frame
;
3944 ix86_compute_frame_layout (&frame
);
3946 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
3947 return frame
.hard_frame_pointer_offset
;
3948 else if (from
== FRAME_POINTER_REGNUM
3949 && to
== HARD_FRAME_POINTER_REGNUM
)
3950 return frame
.hard_frame_pointer_offset
- frame
.frame_pointer_offset
;
3953 if (to
!= STACK_POINTER_REGNUM
)
3955 else if (from
== ARG_POINTER_REGNUM
)
3956 return frame
.stack_pointer_offset
;
3957 else if (from
!= FRAME_POINTER_REGNUM
)
3960 return frame
.stack_pointer_offset
- frame
.frame_pointer_offset
;
3964 /* Fill structure ix86_frame about frame of currently computed function. */
3967 ix86_compute_frame_layout (frame
)
3968 struct ix86_frame
*frame
;
3970 HOST_WIDE_INT total_size
;
3971 int stack_alignment_needed
= cfun
->stack_alignment_needed
/ BITS_PER_UNIT
;
3973 int preferred_alignment
= cfun
->preferred_stack_boundary
/ BITS_PER_UNIT
;
3974 HOST_WIDE_INT size
= get_frame_size ();
3976 frame
->nregs
= ix86_nsaved_regs ();
3979 /* Skip return address and saved base pointer. */
3980 offset
= frame_pointer_needed
? UNITS_PER_WORD
* 2 : UNITS_PER_WORD
;
3982 frame
->hard_frame_pointer_offset
= offset
;
3984 /* Do some sanity checking of stack_alignment_needed and
3985 preferred_alignment, since i386 port is the only using those features
3986 that may break easily. */
3988 if (size
&& !stack_alignment_needed
)
3990 if (preferred_alignment
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
3992 if (preferred_alignment
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
3994 if (stack_alignment_needed
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
3997 if (stack_alignment_needed
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
3998 stack_alignment_needed
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4000 /* Register save area */
4001 offset
+= frame
->nregs
* UNITS_PER_WORD
;
4004 if (ix86_save_varrargs_registers
)
4006 offset
+= X86_64_VARARGS_SIZE
;
4007 frame
->va_arg_size
= X86_64_VARARGS_SIZE
;
4010 frame
->va_arg_size
= 0;
4012 /* Align start of frame for local function. */
4013 frame
->padding1
= ((offset
+ stack_alignment_needed
- 1)
4014 & -stack_alignment_needed
) - offset
;
4016 offset
+= frame
->padding1
;
4018 /* Frame pointer points here. */
4019 frame
->frame_pointer_offset
= offset
;
4023 /* Add outgoing arguments area. */
4024 if (ACCUMULATE_OUTGOING_ARGS
)
4026 offset
+= current_function_outgoing_args_size
;
4027 frame
->outgoing_arguments_size
= current_function_outgoing_args_size
;
4030 frame
->outgoing_arguments_size
= 0;
4032 /* Align stack boundary. */
4033 frame
->padding2
= ((offset
+ preferred_alignment
- 1)
4034 & -preferred_alignment
) - offset
;
4036 offset
+= frame
->padding2
;
4038 /* We've reached end of stack frame. */
4039 frame
->stack_pointer_offset
= offset
;
4041 /* Size prologue needs to allocate. */
4042 frame
->to_allocate
=
4043 (size
+ frame
->padding1
+ frame
->padding2
4044 + frame
->outgoing_arguments_size
+ frame
->va_arg_size
);
4046 if (TARGET_64BIT
&& TARGET_RED_ZONE
&& current_function_sp_is_unchanging
4047 && current_function_is_leaf
)
4049 frame
->red_zone_size
= frame
->to_allocate
;
4050 if (frame
->red_zone_size
> RED_ZONE_SIZE
- RED_ZONE_RESERVE
)
4051 frame
->red_zone_size
= RED_ZONE_SIZE
- RED_ZONE_RESERVE
;
4054 frame
->red_zone_size
= 0;
4055 frame
->to_allocate
-= frame
->red_zone_size
;
4056 frame
->stack_pointer_offset
-= frame
->red_zone_size
;
4058 fprintf (stderr
, "nregs: %i\n", frame
->nregs
);
4059 fprintf (stderr
, "size: %i\n", size
);
4060 fprintf (stderr
, "alignment1: %i\n", stack_alignment_needed
);
4061 fprintf (stderr
, "padding1: %i\n", frame
->padding1
);
4062 fprintf (stderr
, "va_arg: %i\n", frame
->va_arg_size
);
4063 fprintf (stderr
, "padding2: %i\n", frame
->padding2
);
4064 fprintf (stderr
, "to_allocate: %i\n", frame
->to_allocate
);
4065 fprintf (stderr
, "red_zone_size: %i\n", frame
->red_zone_size
);
4066 fprintf (stderr
, "frame_pointer_offset: %i\n", frame
->frame_pointer_offset
);
4067 fprintf (stderr
, "hard_frame_pointer_offset: %i\n",
4068 frame
->hard_frame_pointer_offset
);
4069 fprintf (stderr
, "stack_pointer_offset: %i\n", frame
->stack_pointer_offset
);
4073 /* Emit code to save registers in the prologue. */
4076 ix86_emit_save_regs ()
4081 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
4082 if (ix86_save_reg (regno
, true))
4084 insn
= emit_insn (gen_push (gen_rtx_REG (Pmode
, regno
)));
4085 RTX_FRAME_RELATED_P (insn
) = 1;
4089 /* Emit code to save registers using MOV insns. First register
4090 is restored from POINTER + OFFSET. */
4092 ix86_emit_save_regs_using_mov (pointer
, offset
)
4094 HOST_WIDE_INT offset
;
4099 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4100 if (ix86_save_reg (regno
, true))
4102 insn
= emit_move_insn (adjust_address (gen_rtx_MEM (Pmode
, pointer
),
4104 gen_rtx_REG (Pmode
, regno
));
4105 RTX_FRAME_RELATED_P (insn
) = 1;
4106 offset
+= UNITS_PER_WORD
;
4110 /* Expand the prologue into a bunch of separate insns. */
4113 ix86_expand_prologue ()
4116 int pic_reg_used
= (flag_pic
&& (current_function_uses_pic_offset_table
4117 || current_function_uses_const_pool
)
4119 struct ix86_frame frame
;
4121 HOST_WIDE_INT allocate
;
4125 use_fast_prologue_epilogue
4126 = !expensive_function_p (FAST_PROLOGUE_INSN_COUNT
);
4127 if (TARGET_PROLOGUE_USING_MOVE
)
4128 use_mov
= use_fast_prologue_epilogue
;
4130 ix86_compute_frame_layout (&frame
);
4132 /* Note: AT&T enter does NOT have reversed args. Enter is probably
4133 slower on all targets. Also sdb doesn't like it. */
4135 if (frame_pointer_needed
)
4137 insn
= emit_insn (gen_push (hard_frame_pointer_rtx
));
4138 RTX_FRAME_RELATED_P (insn
) = 1;
4140 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
4141 RTX_FRAME_RELATED_P (insn
) = 1;
4144 allocate
= frame
.to_allocate
;
4145 /* In case we are dealing only with single register and empty frame,
4146 push is equivalent of the mov+add sequence. */
4147 if (allocate
== 0 && frame
.nregs
<= 1)
4151 ix86_emit_save_regs ();
4153 allocate
+= frame
.nregs
* UNITS_PER_WORD
;
4157 else if (! TARGET_STACK_PROBE
|| allocate
< CHECK_STACK_LIMIT
)
4159 insn
= emit_insn (gen_pro_epilogue_adjust_stack
4160 (stack_pointer_rtx
, stack_pointer_rtx
,
4161 GEN_INT (-allocate
)));
4162 RTX_FRAME_RELATED_P (insn
) = 1;
4166 /* ??? Is this only valid for Win32? */
4173 arg0
= gen_rtx_REG (SImode
, 0);
4174 emit_move_insn (arg0
, GEN_INT (allocate
));
4176 sym
= gen_rtx_MEM (FUNCTION_MODE
,
4177 gen_rtx_SYMBOL_REF (Pmode
, "_alloca"));
4178 insn
= emit_call_insn (gen_call (sym
, const0_rtx
, constm1_rtx
));
4180 CALL_INSN_FUNCTION_USAGE (insn
)
4181 = gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_USE (VOIDmode
, arg0
),
4182 CALL_INSN_FUNCTION_USAGE (insn
));
4186 if (!frame_pointer_needed
|| !frame
.to_allocate
)
4187 ix86_emit_save_regs_using_mov (stack_pointer_rtx
, frame
.to_allocate
);
4189 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx
,
4190 -frame
.nregs
* UNITS_PER_WORD
);
4193 #ifdef SUBTARGET_PROLOGUE
4198 load_pic_register ();
4200 /* If we are profiling, make sure no instructions are scheduled before
4201 the call to mcount. However, if -fpic, the above call will have
4203 if (current_function_profile
&& ! pic_reg_used
)
4204 emit_insn (gen_blockage ());
4207 /* Emit code to restore saved registers using MOV insns. First register
4208 is restored from POINTER + OFFSET. */
4210 ix86_emit_restore_regs_using_mov (pointer
, offset
, maybe_eh_return
)
4213 int maybe_eh_return
;
4217 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4218 if (ix86_save_reg (regno
, maybe_eh_return
))
4220 emit_move_insn (gen_rtx_REG (Pmode
, regno
),
4221 adjust_address (gen_rtx_MEM (Pmode
, pointer
),
4223 offset
+= UNITS_PER_WORD
;
4227 /* Restore function stack, frame, and registers. */
4230 ix86_expand_epilogue (style
)
4234 int sp_valid
= !frame_pointer_needed
|| current_function_sp_is_unchanging
;
4235 struct ix86_frame frame
;
4236 HOST_WIDE_INT offset
;
4238 ix86_compute_frame_layout (&frame
);
4240 /* Calculate start of saved registers relative to ebp. Special care
4241 must be taken for the normal return case of a function using
4242 eh_return: the eax and edx registers are marked as saved, but not
4243 restored along this path. */
4244 offset
= frame
.nregs
;
4245 if (current_function_calls_eh_return
&& style
!= 2)
4247 offset
*= -UNITS_PER_WORD
;
4249 /* If we're only restoring one register and sp is not valid then
4250 using a move instruction to restore the register since it's
4251 less work than reloading sp and popping the register.
4253 The default code result in stack adjustment using add/lea instruction,
4254 while this code results in LEAVE instruction (or discrete equivalent),
4255 so it is profitable in some other cases as well. Especially when there
4256 are no registers to restore. We also use this code when TARGET_USE_LEAVE
4257 and there is exactly one register to pop. This heruistic may need some
4258 tuning in future. */
4259 if ((!sp_valid
&& frame
.nregs
<= 1)
4260 || (TARGET_EPILOGUE_USING_MOVE
4261 && use_fast_prologue_epilogue
4262 && (frame
.nregs
> 1 || frame
.to_allocate
))
4263 || (frame_pointer_needed
&& !frame
.nregs
&& frame
.to_allocate
)
4264 || (frame_pointer_needed
&& TARGET_USE_LEAVE
4265 && use_fast_prologue_epilogue
&& frame
.nregs
== 1)
4266 || current_function_calls_eh_return
)
4268 /* Restore registers. We can use ebp or esp to address the memory
4269 locations. If both are available, default to ebp, since offsets
4270 are known to be small. Only exception is esp pointing directly to the
4271 end of block of saved registers, where we may simplify addressing
4274 if (!frame_pointer_needed
|| (sp_valid
&& !frame
.to_allocate
))
4275 ix86_emit_restore_regs_using_mov (stack_pointer_rtx
,
4276 frame
.to_allocate
, style
== 2);
4278 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx
,
4279 offset
, style
== 2);
4281 /* eh_return epilogues need %ecx added to the stack pointer. */
4284 rtx tmp
, sa
= EH_RETURN_STACKADJ_RTX
;
4286 if (frame_pointer_needed
)
4288 tmp
= gen_rtx_PLUS (Pmode
, hard_frame_pointer_rtx
, sa
);
4289 tmp
= plus_constant (tmp
, UNITS_PER_WORD
);
4290 emit_insn (gen_rtx_SET (VOIDmode
, sa
, tmp
));
4292 tmp
= gen_rtx_MEM (Pmode
, hard_frame_pointer_rtx
);
4293 emit_move_insn (hard_frame_pointer_rtx
, tmp
);
4295 emit_insn (gen_pro_epilogue_adjust_stack
4296 (stack_pointer_rtx
, sa
, const0_rtx
));
4300 tmp
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, sa
);
4301 tmp
= plus_constant (tmp
, (frame
.to_allocate
4302 + frame
.nregs
* UNITS_PER_WORD
));
4303 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, tmp
));
4306 else if (!frame_pointer_needed
)
4307 emit_insn (gen_pro_epilogue_adjust_stack
4308 (stack_pointer_rtx
, stack_pointer_rtx
,
4309 GEN_INT (frame
.to_allocate
4310 + frame
.nregs
* UNITS_PER_WORD
)));
4311 /* If not an i386, mov & pop is faster than "leave". */
4312 else if (TARGET_USE_LEAVE
|| optimize_size
|| !use_fast_prologue_epilogue
)
4313 emit_insn (TARGET_64BIT
? gen_leave_rex64 () : gen_leave ());
4316 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
4317 hard_frame_pointer_rtx
,
4320 emit_insn (gen_popdi1 (hard_frame_pointer_rtx
));
4322 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
4327 /* First step is to deallocate the stack frame so that we can
4328 pop the registers. */
4331 if (!frame_pointer_needed
)
4333 emit_insn (gen_pro_epilogue_adjust_stack (stack_pointer_rtx
,
4334 hard_frame_pointer_rtx
,
4337 else if (frame
.to_allocate
)
4338 emit_insn (gen_pro_epilogue_adjust_stack
4339 (stack_pointer_rtx
, stack_pointer_rtx
,
4340 GEN_INT (frame
.to_allocate
)));
4342 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4343 if (ix86_save_reg (regno
, false))
4346 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode
, regno
)));
4348 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode
, regno
)));
4350 if (frame_pointer_needed
)
4352 /* Leave results in shorter dependency chains on CPUs that are
4353 able to grok it fast. */
4354 if (TARGET_USE_LEAVE
)
4355 emit_insn (TARGET_64BIT
? gen_leave_rex64 () : gen_leave ());
4356 else if (TARGET_64BIT
)
4357 emit_insn (gen_popdi1 (hard_frame_pointer_rtx
));
4359 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
4363 /* Sibcall epilogues don't want a return instruction. */
4367 if (current_function_pops_args
&& current_function_args_size
)
4369 rtx popc
= GEN_INT (current_function_pops_args
);
4371 /* i386 can only pop 64K bytes. If asked to pop more, pop
4372 return address, do explicit add, and jump indirectly to the
4375 if (current_function_pops_args
>= 65536)
4377 rtx ecx
= gen_rtx_REG (SImode
, 2);
4379 /* There are is no "pascal" calling convention in 64bit ABI. */
4383 emit_insn (gen_popsi1 (ecx
));
4384 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, popc
));
4385 emit_jump_insn (gen_return_indirect_internal (ecx
));
4388 emit_jump_insn (gen_return_pop_internal (popc
));
4391 emit_jump_insn (gen_return_internal ());
4394 /* Extract the parts of an RTL expression that is a valid memory address
4395 for an instruction. Return 0 if the structure of the address is
4396 grossly off. Return -1 if the address contains ASHIFT, so it is not
4397 strictly valid, but still used for computing length of lea instruction.
4401 ix86_decompose_address (addr
, out
)
4403 struct ix86_address
*out
;
4405 rtx base
= NULL_RTX
;
4406 rtx index
= NULL_RTX
;
4407 rtx disp
= NULL_RTX
;
4408 HOST_WIDE_INT scale
= 1;
4409 rtx scale_rtx
= NULL_RTX
;
4412 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
4414 else if (GET_CODE (addr
) == PLUS
)
4416 rtx op0
= XEXP (addr
, 0);
4417 rtx op1
= XEXP (addr
, 1);
4418 enum rtx_code code0
= GET_CODE (op0
);
4419 enum rtx_code code1
= GET_CODE (op1
);
4421 if (code0
== REG
|| code0
== SUBREG
)
4423 if (code1
== REG
|| code1
== SUBREG
)
4424 index
= op0
, base
= op1
; /* index + base */
4426 base
= op0
, disp
= op1
; /* base + displacement */
4428 else if (code0
== MULT
)
4430 index
= XEXP (op0
, 0);
4431 scale_rtx
= XEXP (op0
, 1);
4432 if (code1
== REG
|| code1
== SUBREG
)
4433 base
= op1
; /* index*scale + base */
4435 disp
= op1
; /* index*scale + disp */
4437 else if (code0
== PLUS
&& GET_CODE (XEXP (op0
, 0)) == MULT
)
4439 index
= XEXP (XEXP (op0
, 0), 0); /* index*scale + base + disp */
4440 scale_rtx
= XEXP (XEXP (op0
, 0), 1);
4441 base
= XEXP (op0
, 1);
4444 else if (code0
== PLUS
)
4446 index
= XEXP (op0
, 0); /* index + base + disp */
4447 base
= XEXP (op0
, 1);
4453 else if (GET_CODE (addr
) == MULT
)
4455 index
= XEXP (addr
, 0); /* index*scale */
4456 scale_rtx
= XEXP (addr
, 1);
4458 else if (GET_CODE (addr
) == ASHIFT
)
4462 /* We're called for lea too, which implements ashift on occasion. */
4463 index
= XEXP (addr
, 0);
4464 tmp
= XEXP (addr
, 1);
4465 if (GET_CODE (tmp
) != CONST_INT
)
4467 scale
= INTVAL (tmp
);
4468 if ((unsigned HOST_WIDE_INT
) scale
> 3)
4474 disp
= addr
; /* displacement */
4476 /* Extract the integral value of scale. */
4479 if (GET_CODE (scale_rtx
) != CONST_INT
)
4481 scale
= INTVAL (scale_rtx
);
4484 /* Allow arg pointer and stack pointer as index if there is not scaling */
4485 if (base
&& index
&& scale
== 1
4486 && (index
== arg_pointer_rtx
|| index
== frame_pointer_rtx
4487 || index
== stack_pointer_rtx
))
4494 /* Special case: %ebp cannot be encoded as a base without a displacement. */
4495 if ((base
== hard_frame_pointer_rtx
4496 || base
== frame_pointer_rtx
4497 || base
== arg_pointer_rtx
) && !disp
)
4500 /* Special case: on K6, [%esi] makes the instruction vector decoded.
4501 Avoid this by transforming to [%esi+0]. */
4502 if (ix86_cpu
== PROCESSOR_K6
&& !optimize_size
4503 && base
&& !index
&& !disp
4505 && REGNO_REG_CLASS (REGNO (base
)) == SIREG
)
4508 /* Special case: encode reg+reg instead of reg*2. */
4509 if (!base
&& index
&& scale
&& scale
== 2)
4510 base
= index
, scale
= 1;
4512 /* Special case: scaling cannot be encoded without base or displacement. */
4513 if (!base
&& !disp
&& index
&& scale
!= 1)
4524 /* Return cost of the memory address x.
4525 For i386, it is better to use a complex address than let gcc copy
4526 the address into a reg and make a new pseudo. But not if the address
4527 requires to two regs - that would mean more pseudos with longer
4530 ix86_address_cost (x
)
4533 struct ix86_address parts
;
4536 if (!ix86_decompose_address (x
, &parts
))
4539 if (parts
.base
&& GET_CODE (parts
.base
) == SUBREG
)
4540 parts
.base
= SUBREG_REG (parts
.base
);
4541 if (parts
.index
&& GET_CODE (parts
.index
) == SUBREG
)
4542 parts
.index
= SUBREG_REG (parts
.index
);
4544 /* More complex memory references are better. */
4545 if (parts
.disp
&& parts
.disp
!= const0_rtx
)
4548 /* Attempt to minimize number of registers in the address. */
4550 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
))
4552 && (!REG_P (parts
.index
)
4553 || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)))
4557 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
)
4559 && (!REG_P (parts
.index
) || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)
4560 && parts
.base
!= parts
.index
)
4563 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
4564 since it's predecode logic can't detect the length of instructions
4565 and it degenerates to vector decoded. Increase cost of such
4566 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
4567 to split such addresses or even refuse such addresses at all.
4569 Following addressing modes are affected:
4574 The first and last case may be avoidable by explicitly coding the zero in
4575 memory address, but I don't have AMD-K6 machine handy to check this
4579 && ((!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
!= 1)
4580 || (parts
.disp
&& !parts
.base
&& parts
.index
&& parts
.scale
!= 1)
4581 || (!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
== 1)))
4587 /* If X is a machine specific address (i.e. a symbol or label being
4588 referenced as a displacement from the GOT implemented using an
4589 UNSPEC), then return the base term. Otherwise return X. */
4592 ix86_find_base_term (x
)
4599 if (GET_CODE (x
) != CONST
)
4602 if (GET_CODE (term
) == PLUS
4603 && (GET_CODE (XEXP (term
, 1)) == CONST_INT
4604 || GET_CODE (XEXP (term
, 1)) == CONST_DOUBLE
))
4605 term
= XEXP (term
, 0);
4606 if (GET_CODE (term
) != UNSPEC
4607 || XVECLEN (term
, 0) != 1
4608 || XINT (term
, 1) != 15)
4611 term
= XVECEXP (term
, 0, 0);
4613 if (GET_CODE (term
) != SYMBOL_REF
4614 && GET_CODE (term
) != LABEL_REF
)
4620 if (GET_CODE (x
) != PLUS
4621 || XEXP (x
, 0) != pic_offset_table_rtx
4622 || GET_CODE (XEXP (x
, 1)) != CONST
)
4625 term
= XEXP (XEXP (x
, 1), 0);
4627 if (GET_CODE (term
) == PLUS
&& GET_CODE (XEXP (term
, 1)) == CONST_INT
)
4628 term
= XEXP (term
, 0);
4630 if (GET_CODE (term
) != UNSPEC
4631 || XVECLEN (term
, 0) != 1
4632 || XINT (term
, 1) != 7)
4635 term
= XVECEXP (term
, 0, 0);
4637 if (GET_CODE (term
) != SYMBOL_REF
4638 && GET_CODE (term
) != LABEL_REF
)
4644 /* Determine if a given CONST RTX is a valid memory displacement
4648 legitimate_pic_address_disp_p (disp
)
4651 /* In 64bit mode we can allow direct addresses of symbols and labels
4652 when they are not dynamic symbols. */
4656 if (GET_CODE (disp
) == CONST
)
4658 /* ??? Handle PIC code models */
4659 if (GET_CODE (x
) == PLUS
4660 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
4661 && ix86_cmodel
== CM_SMALL_PIC
4662 && INTVAL (XEXP (x
, 1)) < 1024*1024*1024
4663 && INTVAL (XEXP (x
, 1)) > -1024*1024*1024))
4665 if (local_symbolic_operand (x
, Pmode
))
4668 if (GET_CODE (disp
) != CONST
)
4670 disp
= XEXP (disp
, 0);
4674 /* We are unsafe to allow PLUS expressions. This limit allowed distance
4675 of GOT tables. We should not need these anyway. */
4676 if (GET_CODE (disp
) != UNSPEC
4677 || XVECLEN (disp
, 0) != 1
4678 || XINT (disp
, 1) != 15)
4681 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
4682 && GET_CODE (XVECEXP (disp
, 0, 0)) != LABEL_REF
)
4687 if (GET_CODE (disp
) == PLUS
)
4689 if (GET_CODE (XEXP (disp
, 1)) != CONST_INT
)
4691 disp
= XEXP (disp
, 0);
4694 if (GET_CODE (disp
) != UNSPEC
4695 || XVECLEN (disp
, 0) != 1)
4698 /* Must be @GOT or @GOTOFF. */
4699 switch (XINT (disp
, 1))
4702 return GET_CODE (XVECEXP (disp
, 0, 0)) == SYMBOL_REF
;
4704 case 7: /* @GOTOFF */
4705 return local_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
4711 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
4712 memory address for an instruction. The MODE argument is the machine mode
4713 for the MEM expression that wants to use this address.
4715 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
4716 convert common non-canonical forms to canonical form so that they will
4720 legitimate_address_p (mode
, addr
, strict
)
4721 enum machine_mode mode
;
4725 struct ix86_address parts
;
4726 rtx base
, index
, disp
;
4727 HOST_WIDE_INT scale
;
4728 const char *reason
= NULL
;
4729 rtx reason_rtx
= NULL_RTX
;
4731 if (TARGET_DEBUG_ADDR
)
4734 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
4735 GET_MODE_NAME (mode
), strict
);
4739 if (ix86_decompose_address (addr
, &parts
) <= 0)
4741 reason
= "decomposition failed";
4746 index
= parts
.index
;
4748 scale
= parts
.scale
;
4750 /* Validate base register.
4752 Don't allow SUBREG's here, it can lead to spill failures when the base
4753 is one word out of a two word structure, which is represented internally
4761 if (GET_CODE (base
) == SUBREG
)
4762 reg
= SUBREG_REG (base
);
4766 if (GET_CODE (reg
) != REG
)
4768 reason
= "base is not a register";
4772 if (GET_MODE (base
) != Pmode
)
4774 reason
= "base is not in Pmode";
4778 if ((strict
&& ! REG_OK_FOR_BASE_STRICT_P (reg
))
4779 || (! strict
&& ! REG_OK_FOR_BASE_NONSTRICT_P (reg
)))
4781 reason
= "base is not valid";
4786 /* Validate index register.
4788 Don't allow SUBREG's here, it can lead to spill failures when the index
4789 is one word out of a two word structure, which is represented internally
4797 if (GET_CODE (index
) == SUBREG
)
4798 reg
= SUBREG_REG (index
);
4802 if (GET_CODE (reg
) != REG
)
4804 reason
= "index is not a register";
4808 if (GET_MODE (index
) != Pmode
)
4810 reason
= "index is not in Pmode";
4814 if ((strict
&& ! REG_OK_FOR_INDEX_STRICT_P (reg
))
4815 || (! strict
&& ! REG_OK_FOR_INDEX_NONSTRICT_P (reg
)))
4817 reason
= "index is not valid";
4822 /* Validate scale factor. */
4825 reason_rtx
= GEN_INT (scale
);
4828 reason
= "scale without index";
4832 if (scale
!= 2 && scale
!= 4 && scale
!= 8)
4834 reason
= "scale is not a valid multiplier";
4839 /* Validate displacement. */
4844 if (!CONSTANT_ADDRESS_P (disp
))
4846 reason
= "displacement is not constant";
4852 if (!x86_64_sign_extended_value (disp
))
4854 reason
= "displacement is out of range";
4860 if (GET_CODE (disp
) == CONST_DOUBLE
)
4862 reason
= "displacement is a const_double";
4867 if (flag_pic
&& SYMBOLIC_CONST (disp
))
4869 if (TARGET_64BIT
&& (index
|| base
))
4871 reason
= "non-constant pic memory reference";
4874 if (! legitimate_pic_address_disp_p (disp
))
4876 reason
= "displacement is an invalid pic construct";
4880 /* This code used to verify that a symbolic pic displacement
4881 includes the pic_offset_table_rtx register.
4883 While this is good idea, unfortunately these constructs may
4884 be created by "adds using lea" optimization for incorrect
4893 This code is nonsensical, but results in addressing
4894 GOT table with pic_offset_table_rtx base. We can't
4895 just refuse it easily, since it gets matched by
4896 "addsi3" pattern, that later gets split to lea in the
4897 case output register differs from input. While this
4898 can be handled by separate addsi pattern for this case
4899 that never results in lea, this seems to be easier and
4900 correct fix for crash to disable this test. */
4902 else if (HALF_PIC_P ())
4904 if (! HALF_PIC_ADDRESS_P (disp
)
4905 || (base
!= NULL_RTX
|| index
!= NULL_RTX
))
4907 reason
= "displacement is an invalid half-pic reference";
4913 /* Everything looks valid. */
4914 if (TARGET_DEBUG_ADDR
)
4915 fprintf (stderr
, "Success.\n");
4919 if (TARGET_DEBUG_ADDR
)
4921 fprintf (stderr
, "Error: %s\n", reason
);
4922 debug_rtx (reason_rtx
);
4927 /* Return an unique alias set for the GOT. */
4929 static HOST_WIDE_INT
4930 ix86_GOT_alias_set ()
4932 static HOST_WIDE_INT set
= -1;
4934 set
= new_alias_set ();
4938 /* Return a legitimate reference for ORIG (an address) using the
4939 register REG. If REG is 0, a new pseudo is generated.
4941 There are two types of references that must be handled:
4943 1. Global data references must load the address from the GOT, via
4944 the PIC reg. An insn is emitted to do this load, and the reg is
4947 2. Static data references, constant pool addresses, and code labels
4948 compute the address as an offset from the GOT, whose base is in
4949 the PIC reg. Static data objects have SYMBOL_REF_FLAG set to
4950 differentiate them from global data objects. The returned
4951 address is the PIC reg + an unspec constant.
4953 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
4954 reg also appears in the address. */
4957 legitimize_pic_address (orig
, reg
)
4965 if (local_symbolic_operand (addr
, Pmode
))
4967 /* In 64bit mode we can address such objects directly. */
4972 /* This symbol may be referenced via a displacement from the PIC
4973 base address (@GOTOFF). */
4975 current_function_uses_pic_offset_table
= 1;
4976 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), 7);
4977 new = gen_rtx_CONST (Pmode
, new);
4978 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
4982 emit_move_insn (reg
, new);
4987 else if (GET_CODE (addr
) == SYMBOL_REF
)
4991 current_function_uses_pic_offset_table
= 1;
4992 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), 15);
4993 new = gen_rtx_CONST (Pmode
, new);
4994 new = gen_rtx_MEM (Pmode
, new);
4995 RTX_UNCHANGING_P (new) = 1;
4996 set_mem_alias_set (new, ix86_GOT_alias_set ());
4999 reg
= gen_reg_rtx (Pmode
);
5000 /* Use directly gen_movsi, otherwise the address is loaded
5001 into register for CSE. We don't want to CSE this addresses,
5002 instead we CSE addresses from the GOT table, so skip this. */
5003 emit_insn (gen_movsi (reg
, new));
5008 /* This symbol must be referenced via a load from the
5009 Global Offset Table (@GOT). */
5011 current_function_uses_pic_offset_table
= 1;
5012 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), 6);
5013 new = gen_rtx_CONST (Pmode
, new);
5014 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5015 new = gen_rtx_MEM (Pmode
, new);
5016 RTX_UNCHANGING_P (new) = 1;
5017 set_mem_alias_set (new, ix86_GOT_alias_set ());
5020 reg
= gen_reg_rtx (Pmode
);
5021 emit_move_insn (reg
, new);
5027 if (GET_CODE (addr
) == CONST
)
5029 addr
= XEXP (addr
, 0);
5031 /* We must match stuff we generate before. Assume the only
5032 unspecs that can get here are ours. Not that we could do
5033 anything with them anyway... */
5034 if (GET_CODE (addr
) == UNSPEC
5035 || (GET_CODE (addr
) == PLUS
5036 && GET_CODE (XEXP (addr
, 0)) == UNSPEC
))
5038 if (GET_CODE (addr
) != PLUS
)
5041 if (GET_CODE (addr
) == PLUS
)
5043 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
5045 /* Check first to see if this is a constant offset from a @GOTOFF
5046 symbol reference. */
5047 if (local_symbolic_operand (op0
, Pmode
)
5048 && GET_CODE (op1
) == CONST_INT
)
5052 current_function_uses_pic_offset_table
= 1;
5053 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
), 7);
5054 new = gen_rtx_PLUS (Pmode
, new, op1
);
5055 new = gen_rtx_CONST (Pmode
, new);
5056 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5060 emit_move_insn (reg
, new);
5066 /* ??? We need to limit offsets here. */
5071 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
5072 new = legitimize_pic_address (XEXP (addr
, 1),
5073 base
== reg
? NULL_RTX
: reg
);
5075 if (GET_CODE (new) == CONST_INT
)
5076 new = plus_constant (base
, INTVAL (new));
5079 if (GET_CODE (new) == PLUS
&& CONSTANT_P (XEXP (new, 1)))
5081 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new, 0));
5082 new = XEXP (new, 1);
5084 new = gen_rtx_PLUS (Pmode
, base
, new);
5092 /* Try machine-dependent ways of modifying an illegitimate address
5093 to be legitimate. If we find one, return the new, valid address.
5094 This macro is used in only one place: `memory_address' in explow.c.
5096 OLDX is the address as it was before break_out_memory_refs was called.
5097 In some cases it is useful to look at this to decide what needs to be done.
5099 MODE and WIN are passed so that this macro can use
5100 GO_IF_LEGITIMATE_ADDRESS.
5102 It is always safe for this macro to do nothing. It exists to recognize
5103 opportunities to optimize the output.
5105 For the 80386, we handle X+REG by loading X into a register R and
5106 using R+REG. R will go in a general reg and indexing will be used.
5107 However, if REG is a broken-out memory address or multiplication,
5108 nothing needs to be done because REG can certainly go in a general reg.
5110 When -fpic is used, special handling is needed for symbolic references.
5111 See comments by legitimize_pic_address in i386.c for details. */
5114 legitimize_address (x
, oldx
, mode
)
5116 register rtx oldx ATTRIBUTE_UNUSED
;
5117 enum machine_mode mode
;
5122 if (TARGET_DEBUG_ADDR
)
5124 fprintf (stderr
, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
5125 GET_MODE_NAME (mode
));
5129 if (flag_pic
&& SYMBOLIC_CONST (x
))
5130 return legitimize_pic_address (x
, 0);
5132 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
5133 if (GET_CODE (x
) == ASHIFT
5134 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5135 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (x
, 1)))) < 4)
5138 x
= gen_rtx_MULT (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
5139 GEN_INT (1 << log
));
5142 if (GET_CODE (x
) == PLUS
)
5144 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
5146 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
5147 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5148 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) < 4)
5151 XEXP (x
, 0) = gen_rtx_MULT (Pmode
,
5152 force_reg (Pmode
, XEXP (XEXP (x
, 0), 0)),
5153 GEN_INT (1 << log
));
5156 if (GET_CODE (XEXP (x
, 1)) == ASHIFT
5157 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5158 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1)))) < 4)
5161 XEXP (x
, 1) = gen_rtx_MULT (Pmode
,
5162 force_reg (Pmode
, XEXP (XEXP (x
, 1), 0)),
5163 GEN_INT (1 << log
));
5166 /* Put multiply first if it isn't already. */
5167 if (GET_CODE (XEXP (x
, 1)) == MULT
)
5169 rtx tmp
= XEXP (x
, 0);
5170 XEXP (x
, 0) = XEXP (x
, 1);
5175 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
5176 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
5177 created by virtual register instantiation, register elimination, and
5178 similar optimizations. */
5179 if (GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
5182 x
= gen_rtx_PLUS (Pmode
,
5183 gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5184 XEXP (XEXP (x
, 1), 0)),
5185 XEXP (XEXP (x
, 1), 1));
5189 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
5190 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
5191 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
5192 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
5193 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
5194 && CONSTANT_P (XEXP (x
, 1)))
5197 rtx other
= NULL_RTX
;
5199 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5201 constant
= XEXP (x
, 1);
5202 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5204 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
5206 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5207 other
= XEXP (x
, 1);
5215 x
= gen_rtx_PLUS (Pmode
,
5216 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
5217 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
5218 plus_constant (other
, INTVAL (constant
)));
5222 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
5225 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5228 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
5231 if (GET_CODE (XEXP (x
, 1)) == MULT
)
5234 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
5238 && GET_CODE (XEXP (x
, 1)) == REG
5239 && GET_CODE (XEXP (x
, 0)) == REG
)
5242 if (flag_pic
&& SYMBOLIC_CONST (XEXP (x
, 1)))
5245 x
= legitimize_pic_address (x
, 0);
5248 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
5251 if (GET_CODE (XEXP (x
, 0)) == REG
)
5253 register rtx temp
= gen_reg_rtx (Pmode
);
5254 register rtx val
= force_operand (XEXP (x
, 1), temp
);
5256 emit_move_insn (temp
, val
);
5262 else if (GET_CODE (XEXP (x
, 1)) == REG
)
5264 register rtx temp
= gen_reg_rtx (Pmode
);
5265 register rtx val
= force_operand (XEXP (x
, 0), temp
);
5267 emit_move_insn (temp
, val
);
5277 /* Print an integer constant expression in assembler syntax. Addition
5278 and subtraction are the only arithmetic that may appear in these
5279 expressions. FILE is the stdio stream to write to, X is the rtx, and
5280 CODE is the operand print code from the output string. */
5283 output_pic_addr_const (file
, x
, code
)
5290 switch (GET_CODE (x
))
5300 assemble_name (file
, XSTR (x
, 0));
5301 if (code
== 'P' && ! SYMBOL_REF_FLAG (x
))
5302 fputs ("@PLT", file
);
5309 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
5310 assemble_name (asm_out_file
, buf
);
5314 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5318 /* This used to output parentheses around the expression,
5319 but that does not work on the 386 (either ATT or BSD assembler). */
5320 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5324 if (GET_MODE (x
) == VOIDmode
)
5326 /* We can use %d if the number is <32 bits and positive. */
5327 if (CONST_DOUBLE_HIGH (x
) || CONST_DOUBLE_LOW (x
) < 0)
5328 fprintf (file
, "0x%lx%08lx",
5329 (unsigned long) CONST_DOUBLE_HIGH (x
),
5330 (unsigned long) CONST_DOUBLE_LOW (x
));
5332 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
5335 /* We can't handle floating point constants;
5336 PRINT_OPERAND must handle them. */
5337 output_operand_lossage ("floating constant misused");
5341 /* Some assemblers need integer constants to appear first. */
5342 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5344 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5346 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5348 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5350 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5352 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5359 putc (ASSEMBLER_DIALECT
== ASM_INTEL
? '(' : '[', file
);
5360 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5362 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5363 putc (ASSEMBLER_DIALECT
== ASM_INTEL
? ')' : ']', file
);
5367 if (XVECLEN (x
, 0) != 1)
5369 output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
5370 switch (XINT (x
, 1))
5373 fputs ("@GOT", file
);
5376 fputs ("@GOTOFF", file
);
5379 fputs ("@PLT", file
);
5382 fputs ("@GOTPCREL(%RIP)", file
);
5385 output_operand_lossage ("invalid UNSPEC as operand");
5391 output_operand_lossage ("invalid expression as operand");
5395 /* This is called from dwarfout.c via ASM_OUTPUT_DWARF_ADDR_CONST.
5396 We need to handle our special PIC relocations. */
5399 i386_dwarf_output_addr_const (file
, x
)
5404 fprintf (file
, "%s", TARGET_64BIT
? ASM_QUAD
: ASM_LONG
);
5408 fprintf (file
, "%s", ASM_LONG
);
5411 output_pic_addr_const (file
, x
, '\0');
5413 output_addr_const (file
, x
);
5417 /* In the name of slightly smaller debug output, and to cater to
5418 general assembler losage, recognize PIC+GOTOFF and turn it back
5419 into a direct symbol reference. */
5422 i386_simplify_dwarf_addr (orig_x
)
5427 if (GET_CODE (x
) == MEM
)
5432 if (GET_CODE (x
) != CONST
5433 || GET_CODE (XEXP (x
, 0)) != UNSPEC
5434 || XINT (XEXP (x
, 0), 1) != 15
5435 || GET_CODE (orig_x
) != MEM
)
5437 return XVECEXP (XEXP (x
, 0), 0, 0);
5440 if (GET_CODE (x
) != PLUS
5441 || GET_CODE (XEXP (x
, 1)) != CONST
)
5444 if (GET_CODE (XEXP (x
, 0)) == REG
5445 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5446 /* %ebx + GOT/GOTOFF */
5448 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5450 /* %ebx + %reg * scale + GOT/GOTOFF */
5452 if (GET_CODE (XEXP (y
, 0)) == REG
5453 && REGNO (XEXP (y
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5455 else if (GET_CODE (XEXP (y
, 1)) == REG
5456 && REGNO (XEXP (y
, 1)) == PIC_OFFSET_TABLE_REGNUM
)
5460 if (GET_CODE (y
) != REG
5461 && GET_CODE (y
) != MULT
5462 && GET_CODE (y
) != ASHIFT
)
5468 x
= XEXP (XEXP (x
, 1), 0);
5469 if (GET_CODE (x
) == UNSPEC
5470 && ((XINT (x
, 1) == 6 && GET_CODE (orig_x
) == MEM
)
5471 || (XINT (x
, 1) == 7 && GET_CODE (orig_x
) != MEM
)))
5474 return gen_rtx_PLUS (Pmode
, y
, XVECEXP (x
, 0, 0));
5475 return XVECEXP (x
, 0, 0);
5478 if (GET_CODE (x
) == PLUS
5479 && GET_CODE (XEXP (x
, 0)) == UNSPEC
5480 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5481 && ((XINT (XEXP (x
, 0), 1) == 6 && GET_CODE (orig_x
) == MEM
)
5482 || (XINT (XEXP (x
, 0), 1) == 7 && GET_CODE (orig_x
) != MEM
)))
5484 x
= gen_rtx_PLUS (VOIDmode
, XVECEXP (XEXP (x
, 0), 0, 0), XEXP (x
, 1));
5486 return gen_rtx_PLUS (Pmode
, y
, x
);
5494 put_condition_code (code
, mode
, reverse
, fp
, file
)
5496 enum machine_mode mode
;
5502 if (mode
== CCFPmode
|| mode
== CCFPUmode
)
5504 enum rtx_code second_code
, bypass_code
;
5505 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
5506 if (bypass_code
!= NIL
|| second_code
!= NIL
)
5508 code
= ix86_fp_compare_code_to_integer (code
);
5512 code
= reverse_condition (code
);
5523 if (mode
!= CCmode
&& mode
!= CCNOmode
&& mode
!= CCGCmode
)
5528 /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers.
5529 Those same assemblers have the same but opposite losage on cmov. */
5532 suffix
= fp
? "nbe" : "a";
5535 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
5537 else if (mode
== CCmode
|| mode
== CCGCmode
)
5548 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
5550 else if (mode
== CCmode
|| mode
== CCGCmode
)
5559 suffix
= fp
? "nb" : "ae";
5562 if (mode
!= CCmode
&& mode
!= CCGCmode
&& mode
!= CCNOmode
)
5572 suffix
= fp
? "u" : "p";
5575 suffix
= fp
? "nu" : "np";
5580 fputs (suffix
, file
);
5584 print_reg (x
, code
, file
)
5589 if (REGNO (x
) == ARG_POINTER_REGNUM
5590 || REGNO (x
) == FRAME_POINTER_REGNUM
5591 || REGNO (x
) == FLAGS_REG
5592 || REGNO (x
) == FPSR_REG
)
5595 if (ASSEMBLER_DIALECT
== ASM_ATT
|| USER_LABEL_PREFIX
[0] == 0)
5598 if (code
== 'w' || MMX_REG_P (x
))
5600 else if (code
== 'b')
5602 else if (code
== 'k')
5604 else if (code
== 'q')
5606 else if (code
== 'y')
5608 else if (code
== 'h')
5611 code
= GET_MODE_SIZE (GET_MODE (x
));
5613 /* Irritatingly, AMD extended registers use different naming convention
5614 from the normal registers. */
5615 if (REX_INT_REG_P (x
))
5622 error ("extended registers have no high halves");
5625 fprintf (file
, "r%ib", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
5628 fprintf (file
, "r%iw", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
5631 fprintf (file
, "r%id", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
5634 fprintf (file
, "r%i", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
5637 error ("unsupported operand size for extended register");
5645 if (STACK_TOP_P (x
))
5647 fputs ("st(0)", file
);
5654 if (! ANY_FP_REG_P (x
))
5655 putc (code
== 8 && TARGET_64BIT
? 'r' : 'e', file
);
5659 fputs (hi_reg_name
[REGNO (x
)], file
);
5662 fputs (qi_reg_name
[REGNO (x
)], file
);
5665 fputs (qi_high_reg_name
[REGNO (x
)], file
);
5673 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
5674 C -- print opcode suffix for set/cmov insn.
5675 c -- like C, but print reversed condition
5676 F,f -- likewise, but for floating-point.
5677 O -- if CMOV_SUN_AS_SYNTAX, expand to "w.", "l." or "q.", otherwise
5679 R -- print the prefix for register names.
5680 z -- print the opcode suffix for the size of the current operand.
5681 * -- print a star (in certain assembler syntax)
5682 A -- print an absolute memory reference.
5683 w -- print the operand as if it's a "word" (HImode) even if it isn't.
5684 s -- print a shift double count, followed by the assemblers argument
5686 b -- print the QImode name of the register for the indicated operand.
5687 %b0 would print %al if operands[0] is reg 0.
5688 w -- likewise, print the HImode name of the register.
5689 k -- likewise, print the SImode name of the register.
5690 q -- likewise, print the DImode name of the register.
5691 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
5692 y -- print "st(0)" instead of "st" as a register.
5693 D -- print condition for SSE cmp instruction.
5694 P -- if PIC, print an @PLT suffix.
5695 X -- don't print any sort of PIC '@' suffix for a symbol.
5699 print_operand (file
, x
, code
)
5709 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5714 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5716 else if (ASSEMBLER_DIALECT
== ASM_INTEL
)
5718 /* Intel syntax. For absolute addresses, registers should not
5719 be surrounded by braces. */
5720 if (GET_CODE (x
) != REG
)
5723 PRINT_OPERAND (file
, x
, 0);
5731 PRINT_OPERAND (file
, x
, 0);
5736 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5741 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5746 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5751 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5756 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5761 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5766 /* 387 opcodes don't get size suffixes if the operands are
5768 if (STACK_REG_P (x
))
5771 /* Likewise if using Intel opcodes. */
5772 if (ASSEMBLER_DIALECT
== ASM_INTEL
)
5775 /* This is the size of op from size of operand. */
5776 switch (GET_MODE_SIZE (GET_MODE (x
)))
5779 #ifdef HAVE_GAS_FILDS_FISTS
5785 if (GET_MODE (x
) == SFmode
)
5800 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
5802 #ifdef GAS_MNEMONICS
5828 if (GET_CODE (x
) == CONST_INT
|| ! SHIFT_DOUBLE_OMITS_COUNT
)
5830 PRINT_OPERAND (file
, x
, 0);
5836 /* Little bit of braindamage here. The SSE compare instructions
5837 does use completely different names for the comparisons that the
5838 fp conditional moves. */
5839 switch (GET_CODE (x
))
5854 fputs ("unord", file
);
5858 fputs ("neq", file
);
5862 fputs ("nlt", file
);
5866 fputs ("nle", file
);
5869 fputs ("ord", file
);
5877 #ifdef CMOV_SUN_AS_SYNTAX
5878 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5880 switch (GET_MODE (x
))
5882 case HImode
: putc ('w', file
); break;
5884 case SFmode
: putc ('l', file
); break;
5886 case DFmode
: putc ('q', file
); break;
5894 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 0, file
);
5897 #ifdef CMOV_SUN_AS_SYNTAX
5898 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5901 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 1, file
);
5904 /* Like above, but reverse condition */
5906 /* Check to see if argument to %c is really a constant
5907 and not a condition code which needs to be reversed. */
5908 if (GET_RTX_CLASS (GET_CODE (x
)) != '<')
5910 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
5913 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 0, file
);
5916 #ifdef CMOV_SUN_AS_SYNTAX
5917 if (ASSEMBLER_DIALECT
== ASM_ATT
)
5920 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 1, file
);
5926 if (!optimize
|| optimize_size
|| !TARGET_BRANCH_PREDICTION_HINTS
)
5929 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
5932 int pred_val
= INTVAL (XEXP (x
, 0));
5934 if (pred_val
< REG_BR_PROB_BASE
* 45 / 100
5935 || pred_val
> REG_BR_PROB_BASE
* 55 / 100)
5937 int taken
= pred_val
> REG_BR_PROB_BASE
/ 2;
5938 int cputaken
= final_forward_branch_p (current_output_insn
) == 0;
5940 /* Emit hints only in the case default branch prediction
5941 heruistics would fail. */
5942 if (taken
!= cputaken
)
5944 /* We use 3e (DS) prefix for taken branches and
5945 2e (CS) prefix for not taken branches. */
5947 fputs ("ds ; ", file
);
5949 fputs ("cs ; ", file
);
5956 output_operand_lossage ("invalid operand code `%c'", code
);
5960 if (GET_CODE (x
) == REG
)
5962 PRINT_REG (x
, code
, file
);
5965 else if (GET_CODE (x
) == MEM
)
5967 /* No `byte ptr' prefix for call instructions. */
5968 if (ASSEMBLER_DIALECT
== ASM_INTEL
&& code
!= 'X' && code
!= 'P')
5971 switch (GET_MODE_SIZE (GET_MODE (x
)))
5973 case 1: size
= "BYTE"; break;
5974 case 2: size
= "WORD"; break;
5975 case 4: size
= "DWORD"; break;
5976 case 8: size
= "QWORD"; break;
5977 case 12: size
= "XWORD"; break;
5978 case 16: size
= "XMMWORD"; break;
5983 /* Check for explicit size override (codes 'b', 'w' and 'k') */
5986 else if (code
== 'w')
5988 else if (code
== 'k')
5992 fputs (" PTR ", file
);
5996 if (flag_pic
&& CONSTANT_ADDRESS_P (x
))
5997 output_pic_addr_const (file
, x
, code
);
5998 /* Avoid (%rip) for call operands. */
5999 else if (CONSTANT_ADDRESS_P (x
) && code
=='P'
6000 && GET_CODE (x
) != CONST_INT
)
6001 output_addr_const (file
, x
);
6002 else if (this_is_asm_operands
&& ! address_operand (x
, VOIDmode
))
6003 output_operand_lossage ("invalid constraints for operand");
6008 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
6013 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6014 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
6016 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6018 fprintf (file
, "0x%lx", l
);
6021 /* These float cases don't actually occur as immediate operands. */
6022 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
6027 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6028 REAL_VALUE_TO_DECIMAL (r
, "%.22e", dstr
);
6029 fprintf (file
, "%s", dstr
);
6032 else if (GET_CODE (x
) == CONST_DOUBLE
6033 && (GET_MODE (x
) == XFmode
|| GET_MODE (x
) == TFmode
))
6038 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6039 REAL_VALUE_TO_DECIMAL (r
, "%.22e", dstr
);
6040 fprintf (file
, "%s", dstr
);
6046 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
6048 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6051 else if (GET_CODE (x
) == CONST
|| GET_CODE (x
) == SYMBOL_REF
6052 || GET_CODE (x
) == LABEL_REF
)
6054 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6057 fputs ("OFFSET FLAT:", file
);
6060 if (GET_CODE (x
) == CONST_INT
)
6061 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
6063 output_pic_addr_const (file
, x
, code
);
6065 output_addr_const (file
, x
);
6069 /* Print a memory operand whose address is ADDR. */
6072 print_operand_address (file
, addr
)
6076 struct ix86_address parts
;
6077 rtx base
, index
, disp
;
6080 if (! ix86_decompose_address (addr
, &parts
))
6084 index
= parts
.index
;
6086 scale
= parts
.scale
;
6088 if (!base
&& !index
)
6090 /* Displacement only requires special attention. */
6092 if (GET_CODE (disp
) == CONST_INT
)
6094 if (ASSEMBLER_DIALECT
== ASM_INTEL
)
6096 if (USER_LABEL_PREFIX
[0] == 0)
6098 fputs ("ds:", file
);
6100 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
6103 output_pic_addr_const (file
, addr
, 0);
6105 output_addr_const (file
, addr
);
6107 /* Use one byte shorter RIP relative addressing for 64bit mode. */
6108 if (GET_CODE (disp
) != CONST_INT
&& TARGET_64BIT
)
6109 fputs ("(%rip)", file
);
6113 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6118 output_pic_addr_const (file
, disp
, 0);
6119 else if (GET_CODE (disp
) == LABEL_REF
)
6120 output_asm_label (disp
);
6122 output_addr_const (file
, disp
);
6127 PRINT_REG (base
, 0, file
);
6131 PRINT_REG (index
, 0, file
);
6133 fprintf (file
, ",%d", scale
);
6139 rtx offset
= NULL_RTX
;
6143 /* Pull out the offset of a symbol; print any symbol itself. */
6144 if (GET_CODE (disp
) == CONST
6145 && GET_CODE (XEXP (disp
, 0)) == PLUS
6146 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
6148 offset
= XEXP (XEXP (disp
, 0), 1);
6149 disp
= gen_rtx_CONST (VOIDmode
,
6150 XEXP (XEXP (disp
, 0), 0));
6154 output_pic_addr_const (file
, disp
, 0);
6155 else if (GET_CODE (disp
) == LABEL_REF
)
6156 output_asm_label (disp
);
6157 else if (GET_CODE (disp
) == CONST_INT
)
6160 output_addr_const (file
, disp
);
6166 PRINT_REG (base
, 0, file
);
6169 if (INTVAL (offset
) >= 0)
6171 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
6175 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
6182 PRINT_REG (index
, 0, file
);
6184 fprintf (file
, "*%d", scale
);
6191 /* Split one or more DImode RTL references into pairs of SImode
6192 references. The RTL can be REG, offsettable MEM, integer constant, or
6193 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
6194 split and "num" is its length. lo_half and hi_half are output arrays
6195 that parallel "operands". */
6198 split_di (operands
, num
, lo_half
, hi_half
)
6201 rtx lo_half
[], hi_half
[];
6205 rtx op
= operands
[num
];
6207 /* simplify_subreg refuse to split volatile memory addresses,
6208 but we still have to handle it. */
6209 if (GET_CODE (op
) == MEM
)
6211 lo_half
[num
] = adjust_address (op
, SImode
, 0);
6212 hi_half
[num
] = adjust_address (op
, SImode
, 4);
6216 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
6217 GET_MODE (op
) == VOIDmode
6218 ? DImode
: GET_MODE (op
), 0);
6219 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
6220 GET_MODE (op
) == VOIDmode
6221 ? DImode
: GET_MODE (op
), 4);
6225 /* Split one or more TImode RTL references into pairs of SImode
6226 references. The RTL can be REG, offsettable MEM, integer constant, or
6227 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
6228 split and "num" is its length. lo_half and hi_half are output arrays
6229 that parallel "operands". */
6232 split_ti (operands
, num
, lo_half
, hi_half
)
6235 rtx lo_half
[], hi_half
[];
6239 rtx op
= operands
[num
];
6241 /* simplify_subreg refuse to split volatile memory addresses, but we
6242 still have to handle it. */
6243 if (GET_CODE (op
) == MEM
)
6245 lo_half
[num
] = adjust_address (op
, DImode
, 0);
6246 hi_half
[num
] = adjust_address (op
, DImode
, 8);
6250 lo_half
[num
] = simplify_gen_subreg (DImode
, op
, TImode
, 0);
6251 hi_half
[num
] = simplify_gen_subreg (DImode
, op
, TImode
, 8);
6256 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
6257 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
6258 is the expression of the binary operation. The output may either be
6259 emitted here, or returned to the caller, like all output_* functions.
6261 There is no guarantee that the operands are the same mode, as they
6262 might be within FLOAT or FLOAT_EXTEND expressions. */
6264 #ifndef SYSV386_COMPAT
6265 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
6266 wants to fix the assemblers because that causes incompatibility
6267 with gcc. No-one wants to fix gcc because that causes
6268 incompatibility with assemblers... You can use the option of
6269 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
6270 #define SYSV386_COMPAT 1
6274 output_387_binary_op (insn
, operands
)
6278 static char buf
[30];
6281 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]) | SSE_REG_P (operands
[2]);
6283 #ifdef ENABLE_CHECKING
6284 /* Even if we do not want to check the inputs, this documents input
6285 constraints. Which helps in understanding the following code. */
6286 if (STACK_REG_P (operands
[0])
6287 && ((REG_P (operands
[1])
6288 && REGNO (operands
[0]) == REGNO (operands
[1])
6289 && (STACK_REG_P (operands
[2]) || GET_CODE (operands
[2]) == MEM
))
6290 || (REG_P (operands
[2])
6291 && REGNO (operands
[0]) == REGNO (operands
[2])
6292 && (STACK_REG_P (operands
[1]) || GET_CODE (operands
[1]) == MEM
)))
6293 && (STACK_TOP_P (operands
[1]) || STACK_TOP_P (operands
[2])))
6299 switch (GET_CODE (operands
[3]))
6302 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6303 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6311 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6312 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6320 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6321 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6329 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6330 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6344 if (GET_MODE (operands
[0]) == SFmode
)
6345 strcat (buf
, "ss\t{%2, %0|%0, %2}");
6347 strcat (buf
, "sd\t{%2, %0|%0, %2}");
6352 switch (GET_CODE (operands
[3]))
6356 if (REG_P (operands
[2]) && REGNO (operands
[0]) == REGNO (operands
[2]))
6358 rtx temp
= operands
[2];
6359 operands
[2] = operands
[1];
6363 /* know operands[0] == operands[1]. */
6365 if (GET_CODE (operands
[2]) == MEM
)
6371 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
6373 if (STACK_TOP_P (operands
[0]))
6374 /* How is it that we are storing to a dead operand[2]?
6375 Well, presumably operands[1] is dead too. We can't
6376 store the result to st(0) as st(0) gets popped on this
6377 instruction. Instead store to operands[2] (which I
6378 think has to be st(1)). st(1) will be popped later.
6379 gcc <= 2.8.1 didn't have this check and generated
6380 assembly code that the Unixware assembler rejected. */
6381 p
= "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
6383 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
6387 if (STACK_TOP_P (operands
[0]))
6388 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
6390 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
6395 if (GET_CODE (operands
[1]) == MEM
)
6401 if (GET_CODE (operands
[2]) == MEM
)
6407 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
6410 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
6411 derived assemblers, confusingly reverse the direction of
6412 the operation for fsub{r} and fdiv{r} when the
6413 destination register is not st(0). The Intel assembler
6414 doesn't have this brain damage. Read !SYSV386_COMPAT to
6415 figure out what the hardware really does. */
6416 if (STACK_TOP_P (operands
[0]))
6417 p
= "{p\t%0, %2|rp\t%2, %0}";
6419 p
= "{rp\t%2, %0|p\t%0, %2}";
6421 if (STACK_TOP_P (operands
[0]))
6422 /* As above for fmul/fadd, we can't store to st(0). */
6423 p
= "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
6425 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
6430 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[1])))
6433 if (STACK_TOP_P (operands
[0]))
6434 p
= "{rp\t%0, %1|p\t%1, %0}";
6436 p
= "{p\t%1, %0|rp\t%0, %1}";
6438 if (STACK_TOP_P (operands
[0]))
6439 p
= "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
6441 p
= "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
6446 if (STACK_TOP_P (operands
[0]))
6448 if (STACK_TOP_P (operands
[1]))
6449 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
6451 p
= "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
6454 else if (STACK_TOP_P (operands
[1]))
6457 p
= "{\t%1, %0|r\t%0, %1}";
6459 p
= "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
6465 p
= "{r\t%2, %0|\t%0, %2}";
6467 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
6480 /* Output code to initialize control word copies used by
6481 trunc?f?i patterns. NORMAL is set to current control word, while ROUND_DOWN
6482 is set to control word rounding downwards. */
6484 emit_i387_cw_initialization (normal
, round_down
)
6485 rtx normal
, round_down
;
6487 rtx reg
= gen_reg_rtx (HImode
);
6489 emit_insn (gen_x86_fnstcw_1 (normal
));
6490 emit_move_insn (reg
, normal
);
6491 if (!TARGET_PARTIAL_REG_STALL
&& !optimize_size
6493 emit_insn (gen_movsi_insv_1 (reg
, GEN_INT (0xc)));
6495 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0xc00)));
6496 emit_move_insn (round_down
, reg
);
6499 /* Output code for INSN to convert a float to a signed int. OPERANDS
6500 are the insn operands. The output may be [HSD]Imode and the input
6501 operand may be [SDX]Fmode. */
6504 output_fix_trunc (insn
, operands
)
6508 int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
6509 int dimode_p
= GET_MODE (operands
[0]) == DImode
;
6511 /* Jump through a hoop or two for DImode, since the hardware has no
6512 non-popping instruction. We used to do this a different way, but
6513 that was somewhat fragile and broke with post-reload splitters. */
6514 if (dimode_p
&& !stack_top_dies
)
6515 output_asm_insn ("fld\t%y1", operands
);
6517 if (!STACK_TOP_P (operands
[1]))
6520 if (GET_CODE (operands
[0]) != MEM
)
6523 output_asm_insn ("fldcw\t%3", operands
);
6524 if (stack_top_dies
|| dimode_p
)
6525 output_asm_insn ("fistp%z0\t%0", operands
);
6527 output_asm_insn ("fist%z0\t%0", operands
);
6528 output_asm_insn ("fldcw\t%2", operands
);
6533 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
6534 should be used and 2 when fnstsw should be used. UNORDERED_P is true
6535 when fucom should be used. */
6538 output_fp_compare (insn
, operands
, eflags_p
, unordered_p
)
6541 int eflags_p
, unordered_p
;
6544 rtx cmp_op0
= operands
[0];
6545 rtx cmp_op1
= operands
[1];
6546 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]);
6551 cmp_op1
= operands
[2];
6555 if (GET_MODE (operands
[0]) == SFmode
)
6557 return "ucomiss\t{%1, %0|%0, %1}";
6559 return "comiss\t{%1, %0|%0, %y}";
6562 return "ucomisd\t{%1, %0|%0, %1}";
6564 return "comisd\t{%1, %0|%0, %y}";
6567 if (! STACK_TOP_P (cmp_op0
))
6570 stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
6572 if (STACK_REG_P (cmp_op1
)
6574 && find_regno_note (insn
, REG_DEAD
, REGNO (cmp_op1
))
6575 && REGNO (cmp_op1
) != FIRST_STACK_REG
)
6577 /* If both the top of the 387 stack dies, and the other operand
6578 is also a stack register that dies, then this must be a
6579 `fcompp' float compare */
6583 /* There is no double popping fcomi variant. Fortunately,
6584 eflags is immune from the fstp's cc clobbering. */
6586 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands
);
6588 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands
);
6596 return "fucompp\n\tfnstsw\t%0";
6598 return "fcompp\n\tfnstsw\t%0";
6611 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
6613 static const char * const alt
[24] =
6625 "fcomi\t{%y1, %0|%0, %y1}",
6626 "fcomip\t{%y1, %0|%0, %y1}",
6627 "fucomi\t{%y1, %0|%0, %y1}",
6628 "fucomip\t{%y1, %0|%0, %y1}",
6635 "fcom%z2\t%y2\n\tfnstsw\t%0",
6636 "fcomp%z2\t%y2\n\tfnstsw\t%0",
6637 "fucom%z2\t%y2\n\tfnstsw\t%0",
6638 "fucomp%z2\t%y2\n\tfnstsw\t%0",
6640 "ficom%z2\t%y2\n\tfnstsw\t%0",
6641 "ficomp%z2\t%y2\n\tfnstsw\t%0",
6649 mask
= eflags_p
<< 3;
6650 mask
|= (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
) << 2;
6651 mask
|= unordered_p
<< 1;
6652 mask
|= stack_top_dies
;
6665 ix86_output_addr_vec_elt (file
, value
)
6669 const char *directive
= ASM_LONG
;
6674 directive
= ASM_QUAD
;
6680 fprintf (file
, "%s%s%d\n", directive
, LPREFIX
, value
);
6684 ix86_output_addr_diff_elt (file
, value
, rel
)
6689 fprintf (file
, "%s%s%d-.+(.-%s%d)\n",
6690 ASM_LONG
, LPREFIX
, value
, LPREFIX
, rel
);
6691 else if (HAVE_AS_GOTOFF_IN_DATA
)
6692 fprintf (file
, "%s%s%d@GOTOFF\n", ASM_LONG
, LPREFIX
, value
);
6694 asm_fprintf (file
, "%s%U_GLOBAL_OFFSET_TABLE_+[.-%s%d]\n",
6695 ASM_LONG
, LPREFIX
, value
);
6698 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
6702 ix86_expand_clear (dest
)
6707 /* We play register width games, which are only valid after reload. */
6708 if (!reload_completed
)
6711 /* Avoid HImode and its attendant prefix byte. */
6712 if (GET_MODE_SIZE (GET_MODE (dest
)) < 4)
6713 dest
= gen_rtx_REG (SImode
, REGNO (dest
));
6715 tmp
= gen_rtx_SET (VOIDmode
, dest
, const0_rtx
);
6717 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
6718 if (reload_completed
&& (!TARGET_USE_MOV0
|| optimize_size
))
6720 rtx clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, 17));
6721 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
6728 ix86_expand_move (mode
, operands
)
6729 enum machine_mode mode
;
6732 int strict
= (reload_in_progress
|| reload_completed
);
6735 if (flag_pic
&& mode
== Pmode
&& symbolic_operand (operands
[1], Pmode
))
6737 /* Emit insns to move operands[1] into operands[0]. */
6739 if (GET_CODE (operands
[0]) == MEM
)
6740 operands
[1] = force_reg (Pmode
, operands
[1]);
6743 rtx temp
= operands
[0];
6744 if (GET_CODE (temp
) != REG
)
6745 temp
= gen_reg_rtx (Pmode
);
6746 temp
= legitimize_pic_address (operands
[1], temp
);
6747 if (temp
== operands
[0])
6754 if (GET_CODE (operands
[0]) == MEM
6755 && (PUSH_ROUNDING (GET_MODE_SIZE (mode
)) != GET_MODE_SIZE (mode
)
6756 || !push_operand (operands
[0], mode
))
6757 && GET_CODE (operands
[1]) == MEM
)
6758 operands
[1] = force_reg (mode
, operands
[1]);
6760 if (push_operand (operands
[0], mode
)
6761 && ! general_no_elim_operand (operands
[1], mode
))
6762 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
6764 /* Force large constants in 64bit compilation into register
6765 to get them CSEed. */
6766 if (TARGET_64BIT
&& mode
== DImode
6767 && immediate_operand (operands
[1], mode
)
6768 && !x86_64_zero_extended_value (operands
[1])
6769 && !register_operand (operands
[0], mode
)
6770 && optimize
&& !reload_completed
&& !reload_in_progress
)
6771 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
6773 if (FLOAT_MODE_P (mode
))
6775 /* If we are loading a floating point constant to a register,
6776 force the value to memory now, since we'll get better code
6777 out the back end. */
6781 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
6782 && register_operand (operands
[0], mode
))
6783 operands
[1] = validize_mem (force_const_mem (mode
, operands
[1]));
6787 insn
= gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
6793 ix86_expand_vector_move (mode
, operands
)
6794 enum machine_mode mode
;
6797 /* Force constants other than zero into memory. We do not know how
6798 the instructions used to build constants modify the upper 64 bits
6799 of the register, once we have that information we may be able
6800 to handle some of them more efficiently. */
6801 if ((reload_in_progress
| reload_completed
) == 0
6802 && register_operand (operands
[0], mode
)
6803 && CONSTANT_P (operands
[1]))
6805 rtx addr
= gen_reg_rtx (Pmode
);
6806 emit_move_insn (addr
, XEXP (force_const_mem (mode
, operands
[1]), 0));
6807 operands
[1] = gen_rtx_MEM (mode
, addr
);
6810 /* Make operand1 a register if it isn't already. */
6811 if ((reload_in_progress
| reload_completed
) == 0
6812 && !register_operand (operands
[0], mode
)
6813 && !register_operand (operands
[1], mode
)
6814 && operands
[1] != CONST0_RTX (mode
))
6816 rtx temp
= force_reg (GET_MODE (operands
[1]), operands
[1]);
6817 emit_move_insn (operands
[0], temp
);
6821 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
6824 /* Attempt to expand a binary operator. Make the expansion closer to the
6825 actual machine, then just general_operand, which will allow 3 separate
6826 memory references (one output, two input) in a single insn. */
6829 ix86_expand_binary_operator (code
, mode
, operands
)
6831 enum machine_mode mode
;
6834 int matching_memory
;
6835 rtx src1
, src2
, dst
, op
, clob
;
6841 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
6842 if (GET_RTX_CLASS (code
) == 'c'
6843 && (rtx_equal_p (dst
, src2
)
6844 || immediate_operand (src1
, mode
)))
6851 /* If the destination is memory, and we do not have matching source
6852 operands, do things in registers. */
6853 matching_memory
= 0;
6854 if (GET_CODE (dst
) == MEM
)
6856 if (rtx_equal_p (dst
, src1
))
6857 matching_memory
= 1;
6858 else if (GET_RTX_CLASS (code
) == 'c'
6859 && rtx_equal_p (dst
, src2
))
6860 matching_memory
= 2;
6862 dst
= gen_reg_rtx (mode
);
6865 /* Both source operands cannot be in memory. */
6866 if (GET_CODE (src1
) == MEM
&& GET_CODE (src2
) == MEM
)
6868 if (matching_memory
!= 2)
6869 src2
= force_reg (mode
, src2
);
6871 src1
= force_reg (mode
, src1
);
6874 /* If the operation is not commutable, source 1 cannot be a constant
6875 or non-matching memory. */
6876 if ((CONSTANT_P (src1
)
6877 || (!matching_memory
&& GET_CODE (src1
) == MEM
))
6878 && GET_RTX_CLASS (code
) != 'c')
6879 src1
= force_reg (mode
, src1
);
6881 /* If optimizing, copy to regs to improve CSE */
6882 if (optimize
&& ! no_new_pseudos
)
6884 if (GET_CODE (dst
) == MEM
)
6885 dst
= gen_reg_rtx (mode
);
6886 if (GET_CODE (src1
) == MEM
)
6887 src1
= force_reg (mode
, src1
);
6888 if (GET_CODE (src2
) == MEM
)
6889 src2
= force_reg (mode
, src2
);
6892 /* Emit the instruction. */
6894 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, mode
, src1
, src2
));
6895 if (reload_in_progress
)
6897 /* Reload doesn't know about the flags register, and doesn't know that
6898 it doesn't want to clobber it. We can only do this with PLUS. */
6905 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
6906 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
6909 /* Fix up the destination if needed. */
6910 if (dst
!= operands
[0])
6911 emit_move_insn (operands
[0], dst
);
6914 /* Return TRUE or FALSE depending on whether the binary operator meets the
6915 appropriate constraints. */
6918 ix86_binary_operator_ok (code
, mode
, operands
)
6920 enum machine_mode mode ATTRIBUTE_UNUSED
;
6923 /* Both source operands cannot be in memory. */
6924 if (GET_CODE (operands
[1]) == MEM
&& GET_CODE (operands
[2]) == MEM
)
6926 /* If the operation is not commutable, source 1 cannot be a constant. */
6927 if (CONSTANT_P (operands
[1]) && GET_RTX_CLASS (code
) != 'c')
6929 /* If the destination is memory, we must have a matching source operand. */
6930 if (GET_CODE (operands
[0]) == MEM
6931 && ! (rtx_equal_p (operands
[0], operands
[1])
6932 || (GET_RTX_CLASS (code
) == 'c'
6933 && rtx_equal_p (operands
[0], operands
[2]))))
6935 /* If the operation is not commutable and the source 1 is memory, we must
6936 have a matching destination. */
6937 if (GET_CODE (operands
[1]) == MEM
6938 && GET_RTX_CLASS (code
) != 'c'
6939 && ! rtx_equal_p (operands
[0], operands
[1]))
6944 /* Attempt to expand a unary operator. Make the expansion closer to the
6945 actual machine, then just general_operand, which will allow 2 separate
6946 memory references (one output, one input) in a single insn. */
6949 ix86_expand_unary_operator (code
, mode
, operands
)
6951 enum machine_mode mode
;
6954 int matching_memory
;
6955 rtx src
, dst
, op
, clob
;
6960 /* If the destination is memory, and we do not have matching source
6961 operands, do things in registers. */
6962 matching_memory
= 0;
6963 if (GET_CODE (dst
) == MEM
)
6965 if (rtx_equal_p (dst
, src
))
6966 matching_memory
= 1;
6968 dst
= gen_reg_rtx (mode
);
6971 /* When source operand is memory, destination must match. */
6972 if (!matching_memory
&& GET_CODE (src
) == MEM
)
6973 src
= force_reg (mode
, src
);
6975 /* If optimizing, copy to regs to improve CSE */
6976 if (optimize
&& ! no_new_pseudos
)
6978 if (GET_CODE (dst
) == MEM
)
6979 dst
= gen_reg_rtx (mode
);
6980 if (GET_CODE (src
) == MEM
)
6981 src
= force_reg (mode
, src
);
6984 /* Emit the instruction. */
6986 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_e (code
, mode
, src
));
6987 if (reload_in_progress
|| code
== NOT
)
6989 /* Reload doesn't know about the flags register, and doesn't know that
6990 it doesn't want to clobber it. */
6997 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
6998 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
7001 /* Fix up the destination if needed. */
7002 if (dst
!= operands
[0])
7003 emit_move_insn (operands
[0], dst
);
7006 /* Return TRUE or FALSE depending on whether the unary operator meets the
7007 appropriate constraints. */
7010 ix86_unary_operator_ok (code
, mode
, operands
)
7011 enum rtx_code code ATTRIBUTE_UNUSED
;
7012 enum machine_mode mode ATTRIBUTE_UNUSED
;
7013 rtx operands
[2] ATTRIBUTE_UNUSED
;
7015 /* If one of operands is memory, source and destination must match. */
7016 if ((GET_CODE (operands
[0]) == MEM
7017 || GET_CODE (operands
[1]) == MEM
)
7018 && ! rtx_equal_p (operands
[0], operands
[1]))
7023 /* Return TRUE or FALSE depending on whether the first SET in INSN
7024 has source and destination with matching CC modes, and that the
7025 CC mode is at least as constrained as REQ_MODE. */
7028 ix86_match_ccmode (insn
, req_mode
)
7030 enum machine_mode req_mode
;
7033 enum machine_mode set_mode
;
7035 set
= PATTERN (insn
);
7036 if (GET_CODE (set
) == PARALLEL
)
7037 set
= XVECEXP (set
, 0, 0);
7038 if (GET_CODE (set
) != SET
)
7040 if (GET_CODE (SET_SRC (set
)) != COMPARE
)
7043 set_mode
= GET_MODE (SET_DEST (set
));
7047 if (req_mode
!= CCNOmode
7048 && (req_mode
!= CCmode
7049 || XEXP (SET_SRC (set
), 1) != const0_rtx
))
7053 if (req_mode
== CCGCmode
)
7057 if (req_mode
== CCGOCmode
|| req_mode
== CCNOmode
)
7061 if (req_mode
== CCZmode
)
7071 return (GET_MODE (SET_SRC (set
)) == set_mode
);
7074 /* Generate insn patterns to do an integer compare of OPERANDS. */
7077 ix86_expand_int_compare (code
, op0
, op1
)
7081 enum machine_mode cmpmode
;
7084 cmpmode
= SELECT_CC_MODE (code
, op0
, op1
);
7085 flags
= gen_rtx_REG (cmpmode
, FLAGS_REG
);
7087 /* This is very simple, but making the interface the same as in the
7088 FP case makes the rest of the code easier. */
7089 tmp
= gen_rtx_COMPARE (cmpmode
, op0
, op1
);
7090 emit_insn (gen_rtx_SET (VOIDmode
, flags
, tmp
));
7092 /* Return the test that should be put into the flags user, i.e.
7093 the bcc, scc, or cmov instruction. */
7094 return gen_rtx_fmt_ee (code
, VOIDmode
, flags
, const0_rtx
);
7097 /* Figure out whether to use ordered or unordered fp comparisons.
7098 Return the appropriate mode to use. */
7101 ix86_fp_compare_mode (code
)
7102 enum rtx_code code ATTRIBUTE_UNUSED
;
7104 /* ??? In order to make all comparisons reversible, we do all comparisons
7105 non-trapping when compiling for IEEE. Once gcc is able to distinguish
7106 all forms trapping and nontrapping comparisons, we can make inequality
7107 comparisons trapping again, since it results in better code when using
7108 FCOM based compares. */
7109 return TARGET_IEEE_FP
? CCFPUmode
: CCFPmode
;
7113 ix86_cc_mode (code
, op0
, op1
)
7117 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
7118 return ix86_fp_compare_mode (code
);
7121 /* Only zero flag is needed. */
7123 case NE
: /* ZF!=0 */
7125 /* Codes needing carry flag. */
7126 case GEU
: /* CF=0 */
7127 case GTU
: /* CF=0 & ZF=0 */
7128 case LTU
: /* CF=1 */
7129 case LEU
: /* CF=1 | ZF=1 */
7131 /* Codes possibly doable only with sign flag when
7132 comparing against zero. */
7133 case GE
: /* SF=OF or SF=0 */
7134 case LT
: /* SF<>OF or SF=1 */
7135 if (op1
== const0_rtx
)
7138 /* For other cases Carry flag is not required. */
7140 /* Codes doable only with sign flag when comparing
7141 against zero, but we miss jump instruction for it
7142 so we need to use relational tests agains overflow
7143 that thus needs to be zero. */
7144 case GT
: /* ZF=0 & SF=OF */
7145 case LE
: /* ZF=1 | SF<>OF */
7146 if (op1
== const0_rtx
)
7150 /* strcmp pattern do (use flags) and combine may ask us for proper
7159 /* Return true if we should use an FCOMI instruction for this fp comparison. */
7162 ix86_use_fcomi_compare (code
)
7163 enum rtx_code code ATTRIBUTE_UNUSED
;
7165 enum rtx_code swapped_code
= swap_condition (code
);
7166 return ((ix86_fp_comparison_cost (code
) == ix86_fp_comparison_fcomi_cost (code
))
7167 || (ix86_fp_comparison_cost (swapped_code
)
7168 == ix86_fp_comparison_fcomi_cost (swapped_code
)));
7171 /* Swap, force into registers, or otherwise massage the two operands
7172 to a fp comparison. The operands are updated in place; the new
7173 comparsion code is returned. */
7175 static enum rtx_code
7176 ix86_prepare_fp_compare_args (code
, pop0
, pop1
)
7180 enum machine_mode fpcmp_mode
= ix86_fp_compare_mode (code
);
7181 rtx op0
= *pop0
, op1
= *pop1
;
7182 enum machine_mode op_mode
= GET_MODE (op0
);
7183 int is_sse
= SSE_REG_P (op0
) | SSE_REG_P (op1
);
7185 /* All of the unordered compare instructions only work on registers.
7186 The same is true of the XFmode compare instructions. The same is
7187 true of the fcomi compare instructions. */
7190 && (fpcmp_mode
== CCFPUmode
7191 || op_mode
== XFmode
7192 || op_mode
== TFmode
7193 || ix86_use_fcomi_compare (code
)))
7195 op0
= force_reg (op_mode
, op0
);
7196 op1
= force_reg (op_mode
, op1
);
7200 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
7201 things around if they appear profitable, otherwise force op0
7204 if (standard_80387_constant_p (op0
) == 0
7205 || (GET_CODE (op0
) == MEM
7206 && ! (standard_80387_constant_p (op1
) == 0
7207 || GET_CODE (op1
) == MEM
)))
7210 tmp
= op0
, op0
= op1
, op1
= tmp
;
7211 code
= swap_condition (code
);
7214 if (GET_CODE (op0
) != REG
)
7215 op0
= force_reg (op_mode
, op0
);
7217 if (CONSTANT_P (op1
))
7219 if (standard_80387_constant_p (op1
))
7220 op1
= force_reg (op_mode
, op1
);
7222 op1
= validize_mem (force_const_mem (op_mode
, op1
));
7226 /* Try to rearrange the comparison to make it cheaper. */
7227 if (ix86_fp_comparison_cost (code
)
7228 > ix86_fp_comparison_cost (swap_condition (code
))
7229 && (GET_CODE (op1
) == REG
|| !no_new_pseudos
))
7232 tmp
= op0
, op0
= op1
, op1
= tmp
;
7233 code
= swap_condition (code
);
7234 if (GET_CODE (op0
) != REG
)
7235 op0
= force_reg (op_mode
, op0
);
7243 /* Convert comparison codes we use to represent FP comparison to integer
7244 code that will result in proper branch. Return UNKNOWN if no such code
7246 static enum rtx_code
7247 ix86_fp_compare_code_to_integer (code
)
7277 /* Split comparison code CODE into comparisons we can do using branch
7278 instructions. BYPASS_CODE is comparison code for branch that will
7279 branch around FIRST_CODE and SECOND_CODE. If some of branches
7280 is not required, set value to NIL.
7281 We never require more than two branches. */
7283 ix86_fp_comparison_codes (code
, bypass_code
, first_code
, second_code
)
7284 enum rtx_code code
, *bypass_code
, *first_code
, *second_code
;
7290 /* The fcomi comparison sets flags as follows:
7300 case GT
: /* GTU - CF=0 & ZF=0 */
7301 case GE
: /* GEU - CF=0 */
7302 case ORDERED
: /* PF=0 */
7303 case UNORDERED
: /* PF=1 */
7304 case UNEQ
: /* EQ - ZF=1 */
7305 case UNLT
: /* LTU - CF=1 */
7306 case UNLE
: /* LEU - CF=1 | ZF=1 */
7307 case LTGT
: /* EQ - ZF=0 */
7309 case LT
: /* LTU - CF=1 - fails on unordered */
7311 *bypass_code
= UNORDERED
;
7313 case LE
: /* LEU - CF=1 | ZF=1 - fails on unordered */
7315 *bypass_code
= UNORDERED
;
7317 case EQ
: /* EQ - ZF=1 - fails on unordered */
7319 *bypass_code
= UNORDERED
;
7321 case NE
: /* NE - ZF=0 - fails on unordered */
7323 *second_code
= UNORDERED
;
7325 case UNGE
: /* GEU - CF=0 - fails on unordered */
7327 *second_code
= UNORDERED
;
7329 case UNGT
: /* GTU - CF=0 & ZF=0 - fails on unordered */
7331 *second_code
= UNORDERED
;
7336 if (!TARGET_IEEE_FP
)
7343 /* Return cost of comparison done fcom + arithmetics operations on AX.
7344 All following functions do use number of instructions as an cost metrics.
7345 In future this should be tweaked to compute bytes for optimize_size and
7346 take into account performance of various instructions on various CPUs. */
7348 ix86_fp_comparison_arithmetics_cost (code
)
7351 if (!TARGET_IEEE_FP
)
7353 /* The cost of code output by ix86_expand_fp_compare. */
7381 /* Return cost of comparison done using fcomi operation.
7382 See ix86_fp_comparison_arithmetics_cost for the metrics. */
7384 ix86_fp_comparison_fcomi_cost (code
)
7387 enum rtx_code bypass_code
, first_code
, second_code
;
7388 /* Return arbitarily high cost when instruction is not supported - this
7389 prevents gcc from using it. */
7392 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
7393 return (bypass_code
!= NIL
|| second_code
!= NIL
) + 2;
7396 /* Return cost of comparison done using sahf operation.
7397 See ix86_fp_comparison_arithmetics_cost for the metrics. */
7399 ix86_fp_comparison_sahf_cost (code
)
7402 enum rtx_code bypass_code
, first_code
, second_code
;
7403 /* Return arbitarily high cost when instruction is not preferred - this
7404 avoids gcc from using it. */
7405 if (!TARGET_USE_SAHF
&& !optimize_size
)
7407 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
7408 return (bypass_code
!= NIL
|| second_code
!= NIL
) + 3;
7411 /* Compute cost of the comparison done using any method.
7412 See ix86_fp_comparison_arithmetics_cost for the metrics. */
7414 ix86_fp_comparison_cost (code
)
7417 int fcomi_cost
, sahf_cost
, arithmetics_cost
= 1024;
7420 fcomi_cost
= ix86_fp_comparison_fcomi_cost (code
);
7421 sahf_cost
= ix86_fp_comparison_sahf_cost (code
);
7423 min
= arithmetics_cost
= ix86_fp_comparison_arithmetics_cost (code
);
7424 if (min
> sahf_cost
)
7426 if (min
> fcomi_cost
)
7431 /* Generate insn patterns to do a floating point compare of OPERANDS. */
7434 ix86_expand_fp_compare (code
, op0
, op1
, scratch
, second_test
, bypass_test
)
7436 rtx op0
, op1
, scratch
;
7440 enum machine_mode fpcmp_mode
, intcmp_mode
;
7442 int cost
= ix86_fp_comparison_cost (code
);
7443 enum rtx_code bypass_code
, first_code
, second_code
;
7445 fpcmp_mode
= ix86_fp_compare_mode (code
);
7446 code
= ix86_prepare_fp_compare_args (code
, &op0
, &op1
);
7449 *second_test
= NULL_RTX
;
7451 *bypass_test
= NULL_RTX
;
7453 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
7455 /* Do fcomi/sahf based test when profitable. */
7456 if ((bypass_code
== NIL
|| bypass_test
)
7457 && (second_code
== NIL
|| second_test
)
7458 && ix86_fp_comparison_arithmetics_cost (code
) > cost
)
7462 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
7463 tmp
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (fpcmp_mode
, FLAGS_REG
),
7469 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
7470 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), 9);
7472 scratch
= gen_reg_rtx (HImode
);
7473 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
7474 emit_insn (gen_x86_sahf_1 (scratch
));
7477 /* The FP codes work out to act like unsigned. */
7478 intcmp_mode
= fpcmp_mode
;
7480 if (bypass_code
!= NIL
)
7481 *bypass_test
= gen_rtx_fmt_ee (bypass_code
, VOIDmode
,
7482 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
7484 if (second_code
!= NIL
)
7485 *second_test
= gen_rtx_fmt_ee (second_code
, VOIDmode
,
7486 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
7491 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
7492 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
7493 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), 9);
7495 scratch
= gen_reg_rtx (HImode
);
7496 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
7498 /* In the unordered case, we have to check C2 for NaN's, which
7499 doesn't happen to work out to anything nice combination-wise.
7500 So do some bit twiddling on the value we've got in AH to come
7501 up with an appropriate set of condition codes. */
7503 intcmp_mode
= CCNOmode
;
7508 if (code
== GT
|| !TARGET_IEEE_FP
)
7510 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
7515 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
7516 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
7517 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x44)));
7518 intcmp_mode
= CCmode
;
7524 if (code
== LT
&& TARGET_IEEE_FP
)
7526 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
7527 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x01)));
7528 intcmp_mode
= CCmode
;
7533 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x01)));
7539 if (code
== GE
|| !TARGET_IEEE_FP
)
7541 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x05)));
7546 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
7547 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
7554 if (code
== LE
&& TARGET_IEEE_FP
)
7556 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
7557 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
7558 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
7559 intcmp_mode
= CCmode
;
7564 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
7570 if (code
== EQ
&& TARGET_IEEE_FP
)
7572 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
7573 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
7574 intcmp_mode
= CCmode
;
7579 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
7586 if (code
== NE
&& TARGET_IEEE_FP
)
7588 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
7589 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
7595 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
7601 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
7605 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
7614 /* Return the test that should be put into the flags user, i.e.
7615 the bcc, scc, or cmov instruction. */
7616 return gen_rtx_fmt_ee (code
, VOIDmode
,
7617 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
7622 ix86_expand_compare (code
, second_test
, bypass_test
)
7624 rtx
*second_test
, *bypass_test
;
7627 op0
= ix86_compare_op0
;
7628 op1
= ix86_compare_op1
;
7631 *second_test
= NULL_RTX
;
7633 *bypass_test
= NULL_RTX
;
7635 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
7636 ret
= ix86_expand_fp_compare (code
, op0
, op1
, NULL_RTX
,
7637 second_test
, bypass_test
);
7639 ret
= ix86_expand_int_compare (code
, op0
, op1
);
7644 /* Return true if the CODE will result in nontrivial jump sequence. */
7646 ix86_fp_jump_nontrivial_p (code
)
7649 enum rtx_code bypass_code
, first_code
, second_code
;
7652 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
7653 return bypass_code
!= NIL
|| second_code
!= NIL
;
7657 ix86_expand_branch (code
, label
)
7663 switch (GET_MODE (ix86_compare_op0
))
7669 tmp
= ix86_expand_compare (code
, NULL
, NULL
);
7670 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
7671 gen_rtx_LABEL_REF (VOIDmode
, label
),
7673 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
7683 enum rtx_code bypass_code
, first_code
, second_code
;
7685 code
= ix86_prepare_fp_compare_args (code
, &ix86_compare_op0
,
7688 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
7690 /* Check whether we will use the natural sequence with one jump. If
7691 so, we can expand jump early. Otherwise delay expansion by
7692 creating compound insn to not confuse optimizers. */
7693 if (bypass_code
== NIL
&& second_code
== NIL
7696 ix86_split_fp_branch (code
, ix86_compare_op0
, ix86_compare_op1
,
7697 gen_rtx_LABEL_REF (VOIDmode
, label
),
7702 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
,
7703 ix86_compare_op0
, ix86_compare_op1
);
7704 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
7705 gen_rtx_LABEL_REF (VOIDmode
, label
),
7707 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
7709 use_fcomi
= ix86_use_fcomi_compare (code
);
7710 vec
= rtvec_alloc (3 + !use_fcomi
);
7711 RTVEC_ELT (vec
, 0) = tmp
;
7713 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
7715 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
7718 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
7720 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
7728 /* Expand DImode branch into multiple compare+branch. */
7730 rtx lo
[2], hi
[2], label2
;
7731 enum rtx_code code1
, code2
, code3
;
7733 if (CONSTANT_P (ix86_compare_op0
) && ! CONSTANT_P (ix86_compare_op1
))
7735 tmp
= ix86_compare_op0
;
7736 ix86_compare_op0
= ix86_compare_op1
;
7737 ix86_compare_op1
= tmp
;
7738 code
= swap_condition (code
);
7740 split_di (&ix86_compare_op0
, 1, lo
+0, hi
+0);
7741 split_di (&ix86_compare_op1
, 1, lo
+1, hi
+1);
7743 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
7744 avoid two branches. This costs one extra insn, so disable when
7745 optimizing for size. */
7747 if ((code
== EQ
|| code
== NE
)
7749 || hi
[1] == const0_rtx
|| lo
[1] == const0_rtx
))
7754 if (hi
[1] != const0_rtx
)
7755 xor1
= expand_binop (SImode
, xor_optab
, xor1
, hi
[1],
7756 NULL_RTX
, 0, OPTAB_WIDEN
);
7759 if (lo
[1] != const0_rtx
)
7760 xor0
= expand_binop (SImode
, xor_optab
, xor0
, lo
[1],
7761 NULL_RTX
, 0, OPTAB_WIDEN
);
7763 tmp
= expand_binop (SImode
, ior_optab
, xor1
, xor0
,
7764 NULL_RTX
, 0, OPTAB_WIDEN
);
7766 ix86_compare_op0
= tmp
;
7767 ix86_compare_op1
= const0_rtx
;
7768 ix86_expand_branch (code
, label
);
7772 /* Otherwise, if we are doing less-than or greater-or-equal-than,
7773 op1 is a constant and the low word is zero, then we can just
7774 examine the high word. */
7776 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
)
7779 case LT
: case LTU
: case GE
: case GEU
:
7780 ix86_compare_op0
= hi
[0];
7781 ix86_compare_op1
= hi
[1];
7782 ix86_expand_branch (code
, label
);
7788 /* Otherwise, we need two or three jumps. */
7790 label2
= gen_label_rtx ();
7793 code2
= swap_condition (code
);
7794 code3
= unsigned_condition (code
);
7798 case LT
: case GT
: case LTU
: case GTU
:
7801 case LE
: code1
= LT
; code2
= GT
; break;
7802 case GE
: code1
= GT
; code2
= LT
; break;
7803 case LEU
: code1
= LTU
; code2
= GTU
; break;
7804 case GEU
: code1
= GTU
; code2
= LTU
; break;
7806 case EQ
: code1
= NIL
; code2
= NE
; break;
7807 case NE
: code2
= NIL
; break;
7815 * if (hi(a) < hi(b)) goto true;
7816 * if (hi(a) > hi(b)) goto false;
7817 * if (lo(a) < lo(b)) goto true;
7821 ix86_compare_op0
= hi
[0];
7822 ix86_compare_op1
= hi
[1];
7825 ix86_expand_branch (code1
, label
);
7827 ix86_expand_branch (code2
, label2
);
7829 ix86_compare_op0
= lo
[0];
7830 ix86_compare_op1
= lo
[1];
7831 ix86_expand_branch (code3
, label
);
7834 emit_label (label2
);
7843 /* Split branch based on floating point condition. */
7845 ix86_split_fp_branch (code
, op1
, op2
, target1
, target2
, tmp
)
7847 rtx op1
, op2
, target1
, target2
, tmp
;
7850 rtx label
= NULL_RTX
;
7852 int bypass_probability
= -1, second_probability
= -1, probability
= -1;
7855 if (target2
!= pc_rtx
)
7858 code
= reverse_condition_maybe_unordered (code
);
7863 condition
= ix86_expand_fp_compare (code
, op1
, op2
,
7864 tmp
, &second
, &bypass
);
7866 if (split_branch_probability
>= 0)
7868 /* Distribute the probabilities across the jumps.
7869 Assume the BYPASS and SECOND to be always test
7871 probability
= split_branch_probability
;
7873 /* Value of 1 is low enough to make no need for probability
7874 to be updated. Later we may run some experiments and see
7875 if unordered values are more frequent in practice. */
7877 bypass_probability
= 1;
7879 second_probability
= 1;
7881 if (bypass
!= NULL_RTX
)
7883 label
= gen_label_rtx ();
7884 i
= emit_jump_insn (gen_rtx_SET
7886 gen_rtx_IF_THEN_ELSE (VOIDmode
,
7888 gen_rtx_LABEL_REF (VOIDmode
,
7891 if (bypass_probability
>= 0)
7893 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
7894 GEN_INT (bypass_probability
),
7897 i
= emit_jump_insn (gen_rtx_SET
7899 gen_rtx_IF_THEN_ELSE (VOIDmode
,
7900 condition
, target1
, target2
)));
7901 if (probability
>= 0)
7903 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
7904 GEN_INT (probability
),
7906 if (second
!= NULL_RTX
)
7908 i
= emit_jump_insn (gen_rtx_SET
7910 gen_rtx_IF_THEN_ELSE (VOIDmode
, second
, target1
,
7912 if (second_probability
>= 0)
7914 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
7915 GEN_INT (second_probability
),
7918 if (label
!= NULL_RTX
)
7923 ix86_expand_setcc (code
, dest
)
7927 rtx ret
, tmp
, tmpreg
;
7928 rtx second_test
, bypass_test
;
7930 if (GET_MODE (ix86_compare_op0
) == DImode
7932 return 0; /* FAIL */
7934 if (GET_MODE (dest
) != QImode
)
7937 ret
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
7938 PUT_MODE (ret
, QImode
);
7943 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, ret
));
7944 if (bypass_test
|| second_test
)
7946 rtx test
= second_test
;
7948 rtx tmp2
= gen_reg_rtx (QImode
);
7955 PUT_CODE (test
, reverse_condition_maybe_unordered (GET_CODE (test
)));
7957 PUT_MODE (test
, QImode
);
7958 emit_insn (gen_rtx_SET (VOIDmode
, tmp2
, test
));
7961 emit_insn (gen_andqi3 (tmp
, tmpreg
, tmp2
));
7963 emit_insn (gen_iorqi3 (tmp
, tmpreg
, tmp2
));
7966 return 1; /* DONE */
7970 ix86_expand_int_movcc (operands
)
7973 enum rtx_code code
= GET_CODE (operands
[1]), compare_code
;
7974 rtx compare_seq
, compare_op
;
7975 rtx second_test
, bypass_test
;
7976 enum machine_mode mode
= GET_MODE (operands
[0]);
7978 /* When the compare code is not LTU or GEU, we can not use sbbl case.
7979 In case comparsion is done with immediate, we can convert it to LTU or
7980 GEU by altering the integer. */
7982 if ((code
== LEU
|| code
== GTU
)
7983 && GET_CODE (ix86_compare_op1
) == CONST_INT
7985 && (unsigned int) INTVAL (ix86_compare_op1
) != 0xffffffff
7986 && GET_CODE (operands
[2]) == CONST_INT
7987 && GET_CODE (operands
[3]) == CONST_INT
)
7993 ix86_compare_op1
= GEN_INT (INTVAL (ix86_compare_op1
) + 1);
7997 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
7998 compare_seq
= gen_sequence ();
8001 compare_code
= GET_CODE (compare_op
);
8003 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
8004 HImode insns, we'd be swallowed in word prefix ops. */
8007 && (mode
!= DImode
|| TARGET_64BIT
)
8008 && GET_CODE (operands
[2]) == CONST_INT
8009 && GET_CODE (operands
[3]) == CONST_INT
)
8011 rtx out
= operands
[0];
8012 HOST_WIDE_INT ct
= INTVAL (operands
[2]);
8013 HOST_WIDE_INT cf
= INTVAL (operands
[3]);
8016 if ((compare_code
== LTU
|| compare_code
== GEU
)
8017 && !second_test
&& !bypass_test
)
8020 /* Detect overlap between destination and compare sources. */
8023 /* To simplify rest of code, restrict to the GEU case. */
8024 if (compare_code
== LTU
)
8029 compare_code
= reverse_condition (compare_code
);
8030 code
= reverse_condition (code
);
8034 if (reg_overlap_mentioned_p (out
, ix86_compare_op0
)
8035 || reg_overlap_mentioned_p (out
, ix86_compare_op1
))
8036 tmp
= gen_reg_rtx (mode
);
8038 emit_insn (compare_seq
);
8040 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp
));
8042 emit_insn (gen_x86_movsicc_0_m1 (tmp
));
8054 tmp
= expand_simple_binop (mode
, PLUS
,
8056 tmp
, 1, OPTAB_DIRECT
);
8067 tmp
= expand_simple_binop (mode
, IOR
,
8069 tmp
, 1, OPTAB_DIRECT
);
8071 else if (diff
== -1 && ct
)
8081 tmp
= expand_simple_unop (mode
, NOT
, tmp
, tmp
, 1);
8083 tmp
= expand_simple_binop (mode
, PLUS
,
8085 tmp
, 1, OPTAB_DIRECT
);
8092 * andl cf - ct, dest
8097 tmp
= expand_simple_binop (mode
, AND
,
8099 gen_int_mode (cf
- ct
, mode
),
8100 tmp
, 1, OPTAB_DIRECT
);
8102 tmp
= expand_simple_binop (mode
, PLUS
,
8104 tmp
, 1, OPTAB_DIRECT
);
8108 emit_move_insn (out
, tmp
);
8110 return 1; /* DONE */
8117 tmp
= ct
, ct
= cf
, cf
= tmp
;
8119 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
8121 /* We may be reversing unordered compare to normal compare, that
8122 is not valid in general (we may convert non-trapping condition
8123 to trapping one), however on i386 we currently emit all
8124 comparisons unordered. */
8125 compare_code
= reverse_condition_maybe_unordered (compare_code
);
8126 code
= reverse_condition_maybe_unordered (code
);
8130 compare_code
= reverse_condition (compare_code
);
8131 code
= reverse_condition (code
);
8134 if ((diff
== 1 || diff
== 2 || diff
== 4 || diff
== 8
8135 || diff
== 3 || diff
== 5 || diff
== 9)
8136 && (mode
!= DImode
|| x86_64_sign_extended_value (GEN_INT (cf
))))
8142 * lea cf(dest*(ct-cf)),dest
8146 * This also catches the degenerate setcc-only case.
8152 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
8153 ix86_compare_op1
, VOIDmode
, 0, 1);
8156 /* On x86_64 the lea instruction operates on Pmode, so we need to get arithmetics
8157 done in proper mode to match. */
8164 tmp
= gen_rtx_MULT (mode
, out1
, GEN_INT (diff
& ~1));
8168 tmp
= gen_rtx_PLUS (mode
, tmp
, out1
);
8174 tmp
= gen_rtx_PLUS (mode
, tmp
, GEN_INT (cf
));
8178 && (GET_CODE (tmp
) != SUBREG
|| SUBREG_REG (tmp
) != out
))
8184 clob
= gen_rtx_REG (CCmode
, FLAGS_REG
);
8185 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
8187 tmp
= gen_rtx_SET (VOIDmode
, out
, tmp
);
8188 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
8192 emit_insn (gen_rtx_SET (VOIDmode
, out
, tmp
));
8194 if (out
!= operands
[0])
8195 emit_move_insn (operands
[0], out
);
8197 return 1; /* DONE */
8201 * General case: Jumpful:
8202 * xorl dest,dest cmpl op1, op2
8203 * cmpl op1, op2 movl ct, dest
8205 * decl dest movl cf, dest
8206 * andl (cf-ct),dest 1:
8211 * This is reasonably steep, but branch mispredict costs are
8212 * high on modern cpus, so consider failing only if optimizing
8215 * %%% Parameterize branch_cost on the tuning architecture, then
8216 * use that. The 80386 couldn't care less about mispredicts.
8219 if (!optimize_size
&& !TARGET_CMOVE
)
8225 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
8227 /* We may be reversing unordered compare to normal compare,
8228 that is not valid in general (we may convert non-trapping
8229 condition to trapping one), however on i386 we currently
8230 emit all comparisons unordered. */
8231 compare_code
= reverse_condition_maybe_unordered (compare_code
);
8232 code
= reverse_condition_maybe_unordered (code
);
8236 compare_code
= reverse_condition (compare_code
);
8237 code
= reverse_condition (code
);
8241 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
8242 ix86_compare_op1
, VOIDmode
, 0, 1);
8244 out
= expand_simple_binop (mode
, PLUS
,
8246 out
, 1, OPTAB_DIRECT
);
8247 out
= expand_simple_binop (mode
, AND
,
8249 gen_int_mode (cf
- ct
, mode
),
8250 out
, 1, OPTAB_DIRECT
);
8251 out
= expand_simple_binop (mode
, PLUS
,
8253 out
, 1, OPTAB_DIRECT
);
8254 if (out
!= operands
[0])
8255 emit_move_insn (operands
[0], out
);
8257 return 1; /* DONE */
8263 /* Try a few things more with specific constants and a variable. */
8266 rtx var
, orig_out
, out
, tmp
;
8269 return 0; /* FAIL */
8271 /* If one of the two operands is an interesting constant, load a
8272 constant with the above and mask it in with a logical operation. */
8274 if (GET_CODE (operands
[2]) == CONST_INT
)
8277 if (INTVAL (operands
[2]) == 0)
8278 operands
[3] = constm1_rtx
, op
= and_optab
;
8279 else if (INTVAL (operands
[2]) == -1)
8280 operands
[3] = const0_rtx
, op
= ior_optab
;
8282 return 0; /* FAIL */
8284 else if (GET_CODE (operands
[3]) == CONST_INT
)
8287 if (INTVAL (operands
[3]) == 0)
8288 operands
[2] = constm1_rtx
, op
= and_optab
;
8289 else if (INTVAL (operands
[3]) == -1)
8290 operands
[2] = const0_rtx
, op
= ior_optab
;
8292 return 0; /* FAIL */
8295 return 0; /* FAIL */
8297 orig_out
= operands
[0];
8298 tmp
= gen_reg_rtx (mode
);
8301 /* Recurse to get the constant loaded. */
8302 if (ix86_expand_int_movcc (operands
) == 0)
8303 return 0; /* FAIL */
8305 /* Mask in the interesting variable. */
8306 out
= expand_binop (mode
, op
, var
, tmp
, orig_out
, 0,
8308 if (out
!= orig_out
)
8309 emit_move_insn (orig_out
, out
);
8311 return 1; /* DONE */
8315 * For comparison with above,
8325 if (! nonimmediate_operand (operands
[2], mode
))
8326 operands
[2] = force_reg (mode
, operands
[2]);
8327 if (! nonimmediate_operand (operands
[3], mode
))
8328 operands
[3] = force_reg (mode
, operands
[3]);
8330 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
8332 rtx tmp
= gen_reg_rtx (mode
);
8333 emit_move_insn (tmp
, operands
[3]);
8336 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
8338 rtx tmp
= gen_reg_rtx (mode
);
8339 emit_move_insn (tmp
, operands
[2]);
8342 if (! register_operand (operands
[2], VOIDmode
)
8343 && ! register_operand (operands
[3], VOIDmode
))
8344 operands
[2] = force_reg (mode
, operands
[2]);
8346 emit_insn (compare_seq
);
8347 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
8348 gen_rtx_IF_THEN_ELSE (mode
,
8349 compare_op
, operands
[2],
8352 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
8353 gen_rtx_IF_THEN_ELSE (mode
,
8358 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
8359 gen_rtx_IF_THEN_ELSE (mode
,
8364 return 1; /* DONE */
8368 ix86_expand_fp_movcc (operands
)
8373 rtx compare_op
, second_test
, bypass_test
;
8375 /* For SF/DFmode conditional moves based on comparisons
8376 in same mode, we may want to use SSE min/max instructions. */
8377 if (((TARGET_SSE_MATH
&& GET_MODE (operands
[0]) == SFmode
)
8378 || (TARGET_SSE2
&& TARGET_SSE_MATH
&& GET_MODE (operands
[0]) == DFmode
))
8379 && GET_MODE (ix86_compare_op0
) == GET_MODE (operands
[0])
8380 /* The SSE comparisons does not support the LTGT/UNEQ pair. */
8382 || (GET_CODE (operands
[1]) != LTGT
&& GET_CODE (operands
[1]) != UNEQ
))
8383 /* We may be called from the post-reload splitter. */
8384 && (!REG_P (operands
[0])
8385 || SSE_REG_P (operands
[0])
8386 || REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
8388 rtx op0
= ix86_compare_op0
, op1
= ix86_compare_op1
;
8389 code
= GET_CODE (operands
[1]);
8391 /* See if we have (cross) match between comparison operands and
8392 conditional move operands. */
8393 if (rtx_equal_p (operands
[2], op1
))
8398 code
= reverse_condition_maybe_unordered (code
);
8400 if (rtx_equal_p (operands
[2], op0
) && rtx_equal_p (operands
[3], op1
))
8402 /* Check for min operation. */
8405 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
8406 if (memory_operand (op0
, VOIDmode
))
8407 op0
= force_reg (GET_MODE (operands
[0]), op0
);
8408 if (GET_MODE (operands
[0]) == SFmode
)
8409 emit_insn (gen_minsf3 (operands
[0], op0
, op1
));
8411 emit_insn (gen_mindf3 (operands
[0], op0
, op1
));
8414 /* Check for max operation. */
8417 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
8418 if (memory_operand (op0
, VOIDmode
))
8419 op0
= force_reg (GET_MODE (operands
[0]), op0
);
8420 if (GET_MODE (operands
[0]) == SFmode
)
8421 emit_insn (gen_maxsf3 (operands
[0], op0
, op1
));
8423 emit_insn (gen_maxdf3 (operands
[0], op0
, op1
));
8427 /* Manage condition to be sse_comparison_operator. In case we are
8428 in non-ieee mode, try to canonicalize the destination operand
8429 to be first in the comparison - this helps reload to avoid extra
8431 if (!sse_comparison_operator (operands
[1], VOIDmode
)
8432 || (rtx_equal_p (operands
[0], ix86_compare_op1
) && !TARGET_IEEE_FP
))
8434 rtx tmp
= ix86_compare_op0
;
8435 ix86_compare_op0
= ix86_compare_op1
;
8436 ix86_compare_op1
= tmp
;
8437 operands
[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands
[1])),
8438 VOIDmode
, ix86_compare_op0
,
8441 /* Similary try to manage result to be first operand of conditional
8442 move. We also don't support the NE comparison on SSE, so try to
8444 if ((rtx_equal_p (operands
[0], operands
[3])
8445 && (!TARGET_IEEE_FP
|| GET_CODE (operands
[1]) != EQ
))
8446 || (GET_CODE (operands
[1]) == NE
&& TARGET_IEEE_FP
))
8448 rtx tmp
= operands
[2];
8449 operands
[2] = operands
[3];
8451 operands
[1] = gen_rtx_fmt_ee (reverse_condition_maybe_unordered
8452 (GET_CODE (operands
[1])),
8453 VOIDmode
, ix86_compare_op0
,
8456 if (GET_MODE (operands
[0]) == SFmode
)
8457 emit_insn (gen_sse_movsfcc (operands
[0], operands
[1],
8458 operands
[2], operands
[3],
8459 ix86_compare_op0
, ix86_compare_op1
));
8461 emit_insn (gen_sse_movdfcc (operands
[0], operands
[1],
8462 operands
[2], operands
[3],
8463 ix86_compare_op0
, ix86_compare_op1
));
8467 /* The floating point conditional move instructions don't directly
8468 support conditions resulting from a signed integer comparison. */
8470 code
= GET_CODE (operands
[1]);
8471 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
8473 /* The floating point conditional move instructions don't directly
8474 support signed integer comparisons. */
8476 if (!fcmov_comparison_operator (compare_op
, VOIDmode
))
8478 if (second_test
!= NULL
|| bypass_test
!= NULL
)
8480 tmp
= gen_reg_rtx (QImode
);
8481 ix86_expand_setcc (code
, tmp
);
8483 ix86_compare_op0
= tmp
;
8484 ix86_compare_op1
= const0_rtx
;
8485 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
8487 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
8489 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
8490 emit_move_insn (tmp
, operands
[3]);
8493 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
8495 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
8496 emit_move_insn (tmp
, operands
[2]);
8500 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
8501 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
8506 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
8507 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
8512 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
8513 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
8521 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
8522 works for floating pointer parameters and nonoffsetable memories.
8523 For pushes, it returns just stack offsets; the values will be saved
8524 in the right order. Maximally three parts are generated. */
8527 ix86_split_to_parts (operand
, parts
, mode
)
8530 enum machine_mode mode
;
8535 size
= mode
== TFmode
? 3 : (GET_MODE_SIZE (mode
) / 4);
8537 size
= (GET_MODE_SIZE (mode
) + 4) / 8;
8539 if (GET_CODE (operand
) == REG
&& MMX_REGNO_P (REGNO (operand
)))
8541 if (size
< 2 || size
> 3)
8544 /* Optimize constant pool reference to immediates. This is used by fp moves,
8545 that force all constants to memory to allow combining. */
8547 if (GET_CODE (operand
) == MEM
8548 && GET_CODE (XEXP (operand
, 0)) == SYMBOL_REF
8549 && CONSTANT_POOL_ADDRESS_P (XEXP (operand
, 0)))
8550 operand
= get_pool_constant (XEXP (operand
, 0));
8552 if (GET_CODE (operand
) == MEM
&& !offsettable_memref_p (operand
))
8554 /* The only non-offsetable memories we handle are pushes. */
8555 if (! push_operand (operand
, VOIDmode
))
8558 operand
= copy_rtx (operand
);
8559 PUT_MODE (operand
, Pmode
);
8560 parts
[0] = parts
[1] = parts
[2] = operand
;
8562 else if (!TARGET_64BIT
)
8565 split_di (&operand
, 1, &parts
[0], &parts
[1]);
8568 if (REG_P (operand
))
8570 if (!reload_completed
)
8572 parts
[0] = gen_rtx_REG (SImode
, REGNO (operand
) + 0);
8573 parts
[1] = gen_rtx_REG (SImode
, REGNO (operand
) + 1);
8575 parts
[2] = gen_rtx_REG (SImode
, REGNO (operand
) + 2);
8577 else if (offsettable_memref_p (operand
))
8579 operand
= adjust_address (operand
, SImode
, 0);
8581 parts
[1] = adjust_address (operand
, SImode
, 4);
8583 parts
[2] = adjust_address (operand
, SImode
, 8);
8585 else if (GET_CODE (operand
) == CONST_DOUBLE
)
8590 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
8595 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
8596 parts
[2] = gen_int_mode (l
[2], SImode
);
8599 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
8604 parts
[1] = gen_int_mode (l
[1], SImode
);
8605 parts
[0] = gen_int_mode (l
[0], SImode
);
8614 split_ti (&operand
, 1, &parts
[0], &parts
[1]);
8615 if (mode
== XFmode
|| mode
== TFmode
)
8617 if (REG_P (operand
))
8619 if (!reload_completed
)
8621 parts
[0] = gen_rtx_REG (DImode
, REGNO (operand
) + 0);
8622 parts
[1] = gen_rtx_REG (SImode
, REGNO (operand
) + 1);
8624 else if (offsettable_memref_p (operand
))
8626 operand
= adjust_address (operand
, DImode
, 0);
8628 parts
[1] = adjust_address (operand
, SImode
, 8);
8630 else if (GET_CODE (operand
) == CONST_DOUBLE
)
8635 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
8636 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
8637 /* Do not use shift by 32 to avoid warning on 32bit systems. */
8638 if (HOST_BITS_PER_WIDE_INT
>= 64)
8641 ((l
[0] & (((HOST_WIDE_INT
) 2 << 31) - 1))
8642 + ((((HOST_WIDE_INT
) l
[1]) << 31) << 1),
8645 parts
[0] = immed_double_const (l
[0], l
[1], DImode
);
8646 parts
[1] = gen_int_mode (l
[2], SImode
);
8656 /* Emit insns to perform a move or push of DI, DF, and XF values.
8657 Return false when normal moves are needed; true when all required
8658 insns have been emitted. Operands 2-4 contain the input values
8659 int the correct order; operands 5-7 contain the output values. */
8662 ix86_split_long_move (operands
)
8669 enum machine_mode mode
= GET_MODE (operands
[0]);
8671 /* The DFmode expanders may ask us to move double.
8672 For 64bit target this is single move. By hiding the fact
8673 here we simplify i386.md splitters. */
8674 if (GET_MODE_SIZE (GET_MODE (operands
[0])) == 8 && TARGET_64BIT
)
8676 /* Optimize constant pool reference to immediates. This is used by
8677 fp moves, that force all constants to memory to allow combining. */
8679 if (GET_CODE (operands
[1]) == MEM
8680 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8681 && CONSTANT_POOL_ADDRESS_P (XEXP (operands
[1], 0)))
8682 operands
[1] = get_pool_constant (XEXP (operands
[1], 0));
8683 if (push_operand (operands
[0], VOIDmode
))
8685 operands
[0] = copy_rtx (operands
[0]);
8686 PUT_MODE (operands
[0], Pmode
);
8689 operands
[0] = gen_lowpart (DImode
, operands
[0]);
8690 operands
[1] = gen_lowpart (DImode
, operands
[1]);
8691 emit_move_insn (operands
[0], operands
[1]);
8695 /* The only non-offsettable memory we handle is push. */
8696 if (push_operand (operands
[0], VOIDmode
))
8698 else if (GET_CODE (operands
[0]) == MEM
8699 && ! offsettable_memref_p (operands
[0]))
8702 nparts
= ix86_split_to_parts (operands
[1], part
[1], GET_MODE (operands
[0]));
8703 ix86_split_to_parts (operands
[0], part
[0], GET_MODE (operands
[0]));
8705 /* When emitting push, take care for source operands on the stack. */
8706 if (push
&& GET_CODE (operands
[1]) == MEM
8707 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
8710 part
[1][1] = change_address (part
[1][1], GET_MODE (part
[1][1]),
8711 XEXP (part
[1][2], 0));
8712 part
[1][0] = change_address (part
[1][0], GET_MODE (part
[1][0]),
8713 XEXP (part
[1][1], 0));
8716 /* We need to do copy in the right order in case an address register
8717 of the source overlaps the destination. */
8718 if (REG_P (part
[0][0]) && GET_CODE (part
[1][0]) == MEM
)
8720 if (reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0)))
8722 if (reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
8725 && reg_overlap_mentioned_p (part
[0][2], XEXP (part
[1][0], 0)))
8728 /* Collision in the middle part can be handled by reordering. */
8729 if (collisions
== 1 && nparts
== 3
8730 && reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
8733 tmp
= part
[0][1]; part
[0][1] = part
[0][2]; part
[0][2] = tmp
;
8734 tmp
= part
[1][1]; part
[1][1] = part
[1][2]; part
[1][2] = tmp
;
8737 /* If there are more collisions, we can't handle it by reordering.
8738 Do an lea to the last part and use only one colliding move. */
8739 else if (collisions
> 1)
8742 emit_insn (gen_rtx_SET (VOIDmode
, part
[0][nparts
- 1],
8743 XEXP (part
[1][0], 0)));
8744 part
[1][0] = change_address (part
[1][0],
8745 TARGET_64BIT
? DImode
: SImode
,
8746 part
[0][nparts
- 1]);
8747 part
[1][1] = adjust_address (part
[1][0], VOIDmode
, UNITS_PER_WORD
);
8749 part
[1][2] = adjust_address (part
[1][0], VOIDmode
, 8);
8759 /* We use only first 12 bytes of TFmode value, but for pushing we
8760 are required to adjust stack as if we were pushing real 16byte
8762 if (mode
== TFmode
&& !TARGET_64BIT
)
8763 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8765 emit_move_insn (part
[0][2], part
[1][2]);
8770 /* In 64bit mode we don't have 32bit push available. In case this is
8771 register, it is OK - we will just use larger counterpart. We also
8772 retype memory - these comes from attempt to avoid REX prefix on
8773 moving of second half of TFmode value. */
8774 if (GET_MODE (part
[1][1]) == SImode
)
8776 if (GET_CODE (part
[1][1]) == MEM
)
8777 part
[1][1] = adjust_address (part
[1][1], DImode
, 0);
8778 else if (REG_P (part
[1][1]))
8779 part
[1][1] = gen_rtx_REG (DImode
, REGNO (part
[1][1]));
8782 if (GET_MODE (part
[1][0]) == SImode
)
8783 part
[1][0] = part
[1][1];
8786 emit_move_insn (part
[0][1], part
[1][1]);
8787 emit_move_insn (part
[0][0], part
[1][0]);
8791 /* Choose correct order to not overwrite the source before it is copied. */
8792 if ((REG_P (part
[0][0])
8793 && REG_P (part
[1][1])
8794 && (REGNO (part
[0][0]) == REGNO (part
[1][1])
8796 && REGNO (part
[0][0]) == REGNO (part
[1][2]))))
8798 && reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0))))
8802 operands
[2] = part
[0][2];
8803 operands
[3] = part
[0][1];
8804 operands
[4] = part
[0][0];
8805 operands
[5] = part
[1][2];
8806 operands
[6] = part
[1][1];
8807 operands
[7] = part
[1][0];
8811 operands
[2] = part
[0][1];
8812 operands
[3] = part
[0][0];
8813 operands
[5] = part
[1][1];
8814 operands
[6] = part
[1][0];
8821 operands
[2] = part
[0][0];
8822 operands
[3] = part
[0][1];
8823 operands
[4] = part
[0][2];
8824 operands
[5] = part
[1][0];
8825 operands
[6] = part
[1][1];
8826 operands
[7] = part
[1][2];
8830 operands
[2] = part
[0][0];
8831 operands
[3] = part
[0][1];
8832 operands
[5] = part
[1][0];
8833 operands
[6] = part
[1][1];
8836 emit_move_insn (operands
[2], operands
[5]);
8837 emit_move_insn (operands
[3], operands
[6]);
8839 emit_move_insn (operands
[4], operands
[7]);
8845 ix86_split_ashldi (operands
, scratch
)
8846 rtx
*operands
, scratch
;
8848 rtx low
[2], high
[2];
8851 if (GET_CODE (operands
[2]) == CONST_INT
)
8853 split_di (operands
, 2, low
, high
);
8854 count
= INTVAL (operands
[2]) & 63;
8858 emit_move_insn (high
[0], low
[1]);
8859 emit_move_insn (low
[0], const0_rtx
);
8862 emit_insn (gen_ashlsi3 (high
[0], high
[0], GEN_INT (count
- 32)));
8866 if (!rtx_equal_p (operands
[0], operands
[1]))
8867 emit_move_insn (operands
[0], operands
[1]);
8868 emit_insn (gen_x86_shld_1 (high
[0], low
[0], GEN_INT (count
)));
8869 emit_insn (gen_ashlsi3 (low
[0], low
[0], GEN_INT (count
)));
8874 if (!rtx_equal_p (operands
[0], operands
[1]))
8875 emit_move_insn (operands
[0], operands
[1]);
8877 split_di (operands
, 1, low
, high
);
8879 emit_insn (gen_x86_shld_1 (high
[0], low
[0], operands
[2]));
8880 emit_insn (gen_ashlsi3 (low
[0], low
[0], operands
[2]));
8882 if (TARGET_CMOVE
&& (! no_new_pseudos
|| scratch
))
8884 if (! no_new_pseudos
)
8885 scratch
= force_reg (SImode
, const0_rtx
);
8887 emit_move_insn (scratch
, const0_rtx
);
8889 emit_insn (gen_x86_shift_adj_1 (high
[0], low
[0], operands
[2],
8893 emit_insn (gen_x86_shift_adj_2 (high
[0], low
[0], operands
[2]));
8898 ix86_split_ashrdi (operands
, scratch
)
8899 rtx
*operands
, scratch
;
8901 rtx low
[2], high
[2];
8904 if (GET_CODE (operands
[2]) == CONST_INT
)
8906 split_di (operands
, 2, low
, high
);
8907 count
= INTVAL (operands
[2]) & 63;
8911 emit_move_insn (low
[0], high
[1]);
8913 if (! reload_completed
)
8914 emit_insn (gen_ashrsi3 (high
[0], low
[0], GEN_INT (31)));
8917 emit_move_insn (high
[0], low
[0]);
8918 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (31)));
8922 emit_insn (gen_ashrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
8926 if (!rtx_equal_p (operands
[0], operands
[1]))
8927 emit_move_insn (operands
[0], operands
[1]);
8928 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
8929 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (count
)));
8934 if (!rtx_equal_p (operands
[0], operands
[1]))
8935 emit_move_insn (operands
[0], operands
[1]);
8937 split_di (operands
, 1, low
, high
);
8939 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
8940 emit_insn (gen_ashrsi3 (high
[0], high
[0], operands
[2]));
8942 if (TARGET_CMOVE
&& (! no_new_pseudos
|| scratch
))
8944 if (! no_new_pseudos
)
8945 scratch
= gen_reg_rtx (SImode
);
8946 emit_move_insn (scratch
, high
[0]);
8947 emit_insn (gen_ashrsi3 (scratch
, scratch
, GEN_INT (31)));
8948 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
8952 emit_insn (gen_x86_shift_adj_3 (low
[0], high
[0], operands
[2]));
8957 ix86_split_lshrdi (operands
, scratch
)
8958 rtx
*operands
, scratch
;
8960 rtx low
[2], high
[2];
8963 if (GET_CODE (operands
[2]) == CONST_INT
)
8965 split_di (operands
, 2, low
, high
);
8966 count
= INTVAL (operands
[2]) & 63;
8970 emit_move_insn (low
[0], high
[1]);
8971 emit_move_insn (high
[0], const0_rtx
);
8974 emit_insn (gen_lshrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
8978 if (!rtx_equal_p (operands
[0], operands
[1]))
8979 emit_move_insn (operands
[0], operands
[1]);
8980 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
8981 emit_insn (gen_lshrsi3 (high
[0], high
[0], GEN_INT (count
)));
8986 if (!rtx_equal_p (operands
[0], operands
[1]))
8987 emit_move_insn (operands
[0], operands
[1]);
8989 split_di (operands
, 1, low
, high
);
8991 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
8992 emit_insn (gen_lshrsi3 (high
[0], high
[0], operands
[2]));
8994 /* Heh. By reversing the arguments, we can reuse this pattern. */
8995 if (TARGET_CMOVE
&& (! no_new_pseudos
|| scratch
))
8997 if (! no_new_pseudos
)
8998 scratch
= force_reg (SImode
, const0_rtx
);
9000 emit_move_insn (scratch
, const0_rtx
);
9002 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
9006 emit_insn (gen_x86_shift_adj_2 (low
[0], high
[0], operands
[2]));
9010 /* Helper function for the string operations below. Dest VARIABLE whether
9011 it is aligned to VALUE bytes. If true, jump to the label. */
9013 ix86_expand_aligntest (variable
, value
)
9017 rtx label
= gen_label_rtx ();
9018 rtx tmpcount
= gen_reg_rtx (GET_MODE (variable
));
9019 if (GET_MODE (variable
) == DImode
)
9020 emit_insn (gen_anddi3 (tmpcount
, variable
, GEN_INT (value
)));
9022 emit_insn (gen_andsi3 (tmpcount
, variable
, GEN_INT (value
)));
9023 emit_cmp_and_jump_insns (tmpcount
, const0_rtx
, EQ
, 0, GET_MODE (variable
),
9028 /* Adjust COUNTER by the VALUE. */
9030 ix86_adjust_counter (countreg
, value
)
9032 HOST_WIDE_INT value
;
9034 if (GET_MODE (countreg
) == DImode
)
9035 emit_insn (gen_adddi3 (countreg
, countreg
, GEN_INT (-value
)));
9037 emit_insn (gen_addsi3 (countreg
, countreg
, GEN_INT (-value
)));
9040 /* Zero extend possibly SImode EXP to Pmode register. */
9042 ix86_zero_extend_to_Pmode (exp
)
9046 if (GET_MODE (exp
) == VOIDmode
)
9047 return force_reg (Pmode
, exp
);
9048 if (GET_MODE (exp
) == Pmode
)
9049 return copy_to_mode_reg (Pmode
, exp
);
9050 r
= gen_reg_rtx (Pmode
);
9051 emit_insn (gen_zero_extendsidi2 (r
, exp
));
9055 /* Expand string move (memcpy) operation. Use i386 string operations when
9056 profitable. expand_clrstr contains similar code. */
9058 ix86_expand_movstr (dst
, src
, count_exp
, align_exp
)
9059 rtx dst
, src
, count_exp
, align_exp
;
9061 rtx srcreg
, destreg
, countreg
;
9062 enum machine_mode counter_mode
;
9063 HOST_WIDE_INT align
= 0;
9064 unsigned HOST_WIDE_INT count
= 0;
9069 if (GET_CODE (align_exp
) == CONST_INT
)
9070 align
= INTVAL (align_exp
);
9072 /* This simple hack avoids all inlining code and simplifies code below. */
9073 if (!TARGET_ALIGN_STRINGOPS
)
9076 if (GET_CODE (count_exp
) == CONST_INT
)
9077 count
= INTVAL (count_exp
);
9079 /* Figure out proper mode for counter. For 32bits it is always SImode,
9080 for 64bits use SImode when possible, otherwise DImode.
9081 Set count to number of bytes copied when known at compile time. */
9082 if (!TARGET_64BIT
|| GET_MODE (count_exp
) == SImode
9083 || x86_64_zero_extended_value (count_exp
))
9084 counter_mode
= SImode
;
9086 counter_mode
= DImode
;
9088 if (counter_mode
!= SImode
&& counter_mode
!= DImode
)
9091 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
9092 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
9094 emit_insn (gen_cld ());
9096 /* When optimizing for size emit simple rep ; movsb instruction for
9097 counts not divisible by 4. */
9099 if ((!optimize
|| optimize_size
) && (count
== 0 || (count
& 0x03)))
9101 countreg
= ix86_zero_extend_to_Pmode (count_exp
);
9103 emit_insn (gen_rep_movqi_rex64 (destreg
, srcreg
, countreg
,
9104 destreg
, srcreg
, countreg
));
9106 emit_insn (gen_rep_movqi (destreg
, srcreg
, countreg
,
9107 destreg
, srcreg
, countreg
));
9110 /* For constant aligned (or small unaligned) copies use rep movsl
9111 followed by code copying the rest. For PentiumPro ensure 8 byte
9112 alignment to allow rep movsl acceleration. */
9116 || (!TARGET_PENTIUMPRO
&& !TARGET_64BIT
&& align
>= 4)
9117 || optimize_size
|| count
< (unsigned int) 64))
9119 int size
= TARGET_64BIT
&& !optimize_size
? 8 : 4;
9120 if (count
& ~(size
- 1))
9122 countreg
= copy_to_mode_reg (counter_mode
,
9123 GEN_INT ((count
>> (size
== 4 ? 2 : 3))
9124 & (TARGET_64BIT
? -1 : 0x3fffffff)));
9125 countreg
= ix86_zero_extend_to_Pmode (countreg
);
9129 emit_insn (gen_rep_movsi_rex64 (destreg
, srcreg
, countreg
,
9130 destreg
, srcreg
, countreg
));
9132 emit_insn (gen_rep_movsi (destreg
, srcreg
, countreg
,
9133 destreg
, srcreg
, countreg
));
9136 emit_insn (gen_rep_movdi_rex64 (destreg
, srcreg
, countreg
,
9137 destreg
, srcreg
, countreg
));
9139 if (size
== 8 && (count
& 0x04))
9140 emit_insn (gen_strmovsi (destreg
, srcreg
));
9142 emit_insn (gen_strmovhi (destreg
, srcreg
));
9144 emit_insn (gen_strmovqi (destreg
, srcreg
));
9146 /* The generic code based on the glibc implementation:
9147 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
9148 allowing accelerated copying there)
9149 - copy the data using rep movsl
9156 /* In case we don't know anything about the alignment, default to
9157 library version, since it is usually equally fast and result in
9159 if (!TARGET_INLINE_ALL_STRINGOPS
&& align
< UNITS_PER_WORD
)
9165 if (TARGET_SINGLE_STRINGOP
)
9166 emit_insn (gen_cld ());
9168 countreg2
= gen_reg_rtx (Pmode
);
9169 countreg
= copy_to_mode_reg (counter_mode
, count_exp
);
9171 /* We don't use loops to align destination and to copy parts smaller
9172 than 4 bytes, because gcc is able to optimize such code better (in
9173 the case the destination or the count really is aligned, gcc is often
9174 able to predict the branches) and also it is friendlier to the
9175 hardware branch prediction.
9177 Using loops is benefical for generic case, because we can
9178 handle small counts using the loops. Many CPUs (such as Athlon)
9179 have large REP prefix setup costs.
9181 This is quite costy. Maybe we can revisit this decision later or
9182 add some customizability to this code. */
9185 && align
< (TARGET_PENTIUMPRO
&& (count
== 0
9186 || count
>= (unsigned int) 260)
9187 ? 8 : UNITS_PER_WORD
))
9189 label
= gen_label_rtx ();
9190 emit_cmp_and_jump_insns (countreg
, GEN_INT (UNITS_PER_WORD
- 1),
9191 LEU
, 0, counter_mode
, 1, label
);
9195 rtx label
= ix86_expand_aligntest (destreg
, 1);
9196 emit_insn (gen_strmovqi (destreg
, srcreg
));
9197 ix86_adjust_counter (countreg
, 1);
9199 LABEL_NUSES (label
) = 1;
9203 rtx label
= ix86_expand_aligntest (destreg
, 2);
9204 emit_insn (gen_strmovhi (destreg
, srcreg
));
9205 ix86_adjust_counter (countreg
, 2);
9207 LABEL_NUSES (label
) = 1;
9210 && ((TARGET_PENTIUMPRO
&& (count
== 0
9211 || count
>= (unsigned int) 260))
9214 rtx label
= ix86_expand_aligntest (destreg
, 4);
9215 emit_insn (gen_strmovsi (destreg
, srcreg
));
9216 ix86_adjust_counter (countreg
, 4);
9218 LABEL_NUSES (label
) = 1;
9221 if (!TARGET_SINGLE_STRINGOP
)
9222 emit_insn (gen_cld ());
9225 emit_insn (gen_lshrdi3 (countreg2
, ix86_zero_extend_to_Pmode (countreg
),
9227 emit_insn (gen_rep_movdi_rex64 (destreg
, srcreg
, countreg2
,
9228 destreg
, srcreg
, countreg2
));
9232 emit_insn (gen_lshrsi3 (countreg2
, countreg
, GEN_INT (2)));
9233 emit_insn (gen_rep_movsi (destreg
, srcreg
, countreg2
,
9234 destreg
, srcreg
, countreg2
));
9240 LABEL_NUSES (label
) = 1;
9242 if (TARGET_64BIT
&& align
> 4 && count
!= 0 && (count
& 4))
9243 emit_insn (gen_strmovsi (destreg
, srcreg
));
9244 if ((align
<= 4 || count
== 0) && TARGET_64BIT
)
9246 rtx label
= ix86_expand_aligntest (countreg
, 4);
9247 emit_insn (gen_strmovsi (destreg
, srcreg
));
9249 LABEL_NUSES (label
) = 1;
9251 if (align
> 2 && count
!= 0 && (count
& 2))
9252 emit_insn (gen_strmovhi (destreg
, srcreg
));
9253 if (align
<= 2 || count
== 0)
9255 rtx label
= ix86_expand_aligntest (countreg
, 2);
9256 emit_insn (gen_strmovhi (destreg
, srcreg
));
9258 LABEL_NUSES (label
) = 1;
9260 if (align
> 1 && count
!= 0 && (count
& 1))
9261 emit_insn (gen_strmovqi (destreg
, srcreg
));
9262 if (align
<= 1 || count
== 0)
9264 rtx label
= ix86_expand_aligntest (countreg
, 1);
9265 emit_insn (gen_strmovqi (destreg
, srcreg
));
9267 LABEL_NUSES (label
) = 1;
9271 insns
= get_insns ();
9274 ix86_set_move_mem_attrs (insns
, dst
, src
, destreg
, srcreg
);
9279 /* Expand string clear operation (bzero). Use i386 string operations when
9280 profitable. expand_movstr contains similar code. */
9282 ix86_expand_clrstr (src
, count_exp
, align_exp
)
9283 rtx src
, count_exp
, align_exp
;
9285 rtx destreg
, zeroreg
, countreg
;
9286 enum machine_mode counter_mode
;
9287 HOST_WIDE_INT align
= 0;
9288 unsigned HOST_WIDE_INT count
= 0;
9290 if (GET_CODE (align_exp
) == CONST_INT
)
9291 align
= INTVAL (align_exp
);
9293 /* This simple hack avoids all inlining code and simplifies code below. */
9294 if (!TARGET_ALIGN_STRINGOPS
)
9297 if (GET_CODE (count_exp
) == CONST_INT
)
9298 count
= INTVAL (count_exp
);
9299 /* Figure out proper mode for counter. For 32bits it is always SImode,
9300 for 64bits use SImode when possible, otherwise DImode.
9301 Set count to number of bytes copied when known at compile time. */
9302 if (!TARGET_64BIT
|| GET_MODE (count_exp
) == SImode
9303 || x86_64_zero_extended_value (count_exp
))
9304 counter_mode
= SImode
;
9306 counter_mode
= DImode
;
9308 destreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
9310 emit_insn (gen_cld ());
9312 /* When optimizing for size emit simple rep ; movsb instruction for
9313 counts not divisible by 4. */
9315 if ((!optimize
|| optimize_size
) && (count
== 0 || (count
& 0x03)))
9317 countreg
= ix86_zero_extend_to_Pmode (count_exp
);
9318 zeroreg
= copy_to_mode_reg (QImode
, const0_rtx
);
9320 emit_insn (gen_rep_stosqi_rex64 (destreg
, countreg
, zeroreg
,
9321 destreg
, countreg
));
9323 emit_insn (gen_rep_stosqi (destreg
, countreg
, zeroreg
,
9324 destreg
, countreg
));
9328 || (!TARGET_PENTIUMPRO
&& !TARGET_64BIT
&& align
>= 4)
9329 || optimize_size
|| count
< (unsigned int) 64))
9331 int size
= TARGET_64BIT
&& !optimize_size
? 8 : 4;
9332 zeroreg
= copy_to_mode_reg (size
== 4 ? SImode
: DImode
, const0_rtx
);
9333 if (count
& ~(size
- 1))
9335 countreg
= copy_to_mode_reg (counter_mode
,
9336 GEN_INT ((count
>> (size
== 4 ? 2 : 3))
9337 & (TARGET_64BIT
? -1 : 0x3fffffff)));
9338 countreg
= ix86_zero_extend_to_Pmode (countreg
);
9342 emit_insn (gen_rep_stossi_rex64 (destreg
, countreg
, zeroreg
,
9343 destreg
, countreg
));
9345 emit_insn (gen_rep_stossi (destreg
, countreg
, zeroreg
,
9346 destreg
, countreg
));
9349 emit_insn (gen_rep_stosdi_rex64 (destreg
, countreg
, zeroreg
,
9350 destreg
, countreg
));
9352 if (size
== 8 && (count
& 0x04))
9353 emit_insn (gen_strsetsi (destreg
,
9354 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
9356 emit_insn (gen_strsethi (destreg
,
9357 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
9359 emit_insn (gen_strsetqi (destreg
,
9360 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
9367 /* In case we don't know anything about the alignment, default to
9368 library version, since it is usually equally fast and result in
9370 if (!TARGET_INLINE_ALL_STRINGOPS
&& align
< UNITS_PER_WORD
)
9373 if (TARGET_SINGLE_STRINGOP
)
9374 emit_insn (gen_cld ());
9376 countreg2
= gen_reg_rtx (Pmode
);
9377 countreg
= copy_to_mode_reg (counter_mode
, count_exp
);
9378 zeroreg
= copy_to_mode_reg (Pmode
, const0_rtx
);
9381 && align
< (TARGET_PENTIUMPRO
&& (count
== 0
9382 || count
>= (unsigned int) 260)
9383 ? 8 : UNITS_PER_WORD
))
9385 label
= gen_label_rtx ();
9386 emit_cmp_and_jump_insns (countreg
, GEN_INT (UNITS_PER_WORD
- 1),
9387 LEU
, 0, counter_mode
, 1, label
);
9391 rtx label
= ix86_expand_aligntest (destreg
, 1);
9392 emit_insn (gen_strsetqi (destreg
,
9393 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
9394 ix86_adjust_counter (countreg
, 1);
9396 LABEL_NUSES (label
) = 1;
9400 rtx label
= ix86_expand_aligntest (destreg
, 2);
9401 emit_insn (gen_strsethi (destreg
,
9402 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
9403 ix86_adjust_counter (countreg
, 2);
9405 LABEL_NUSES (label
) = 1;
9407 if (align
<= 4 && TARGET_PENTIUMPRO
&& (count
== 0
9408 || count
>= (unsigned int) 260))
9410 rtx label
= ix86_expand_aligntest (destreg
, 4);
9411 emit_insn (gen_strsetsi (destreg
, (TARGET_64BIT
9412 ? gen_rtx_SUBREG (SImode
, zeroreg
, 0)
9414 ix86_adjust_counter (countreg
, 4);
9416 LABEL_NUSES (label
) = 1;
9419 if (!TARGET_SINGLE_STRINGOP
)
9420 emit_insn (gen_cld ());
9423 emit_insn (gen_lshrdi3 (countreg2
, ix86_zero_extend_to_Pmode (countreg
),
9425 emit_insn (gen_rep_stosdi_rex64 (destreg
, countreg2
, zeroreg
,
9426 destreg
, countreg2
));
9430 emit_insn (gen_lshrsi3 (countreg2
, countreg
, GEN_INT (2)));
9431 emit_insn (gen_rep_stossi (destreg
, countreg2
, zeroreg
,
9432 destreg
, countreg2
));
9438 LABEL_NUSES (label
) = 1;
9440 if (TARGET_64BIT
&& align
> 4 && count
!= 0 && (count
& 4))
9441 emit_insn (gen_strsetsi (destreg
,
9442 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
9443 if (TARGET_64BIT
&& (align
<= 4 || count
== 0))
9445 rtx label
= ix86_expand_aligntest (destreg
, 2);
9446 emit_insn (gen_strsetsi (destreg
,
9447 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
9449 LABEL_NUSES (label
) = 1;
9451 if (align
> 2 && count
!= 0 && (count
& 2))
9452 emit_insn (gen_strsethi (destreg
,
9453 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
9454 if (align
<= 2 || count
== 0)
9456 rtx label
= ix86_expand_aligntest (destreg
, 2);
9457 emit_insn (gen_strsethi (destreg
,
9458 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
9460 LABEL_NUSES (label
) = 1;
9462 if (align
> 1 && count
!= 0 && (count
& 1))
9463 emit_insn (gen_strsetqi (destreg
,
9464 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
9465 if (align
<= 1 || count
== 0)
9467 rtx label
= ix86_expand_aligntest (destreg
, 1);
9468 emit_insn (gen_strsetqi (destreg
,
9469 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
9471 LABEL_NUSES (label
) = 1;
9476 /* Expand strlen. */
9478 ix86_expand_strlen (out
, src
, eoschar
, align
)
9479 rtx out
, src
, eoschar
, align
;
9481 rtx addr
, scratch1
, scratch2
, scratch3
, scratch4
;
9483 /* The generic case of strlen expander is long. Avoid it's
9484 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
9486 if (TARGET_UNROLL_STRLEN
&& eoschar
== const0_rtx
&& optimize
> 1
9487 && !TARGET_INLINE_ALL_STRINGOPS
9489 && (GET_CODE (align
) != CONST_INT
|| INTVAL (align
) < 4))
9492 addr
= force_reg (Pmode
, XEXP (src
, 0));
9493 scratch1
= gen_reg_rtx (Pmode
);
9495 if (TARGET_UNROLL_STRLEN
&& eoschar
== const0_rtx
&& optimize
> 1
9498 /* Well it seems that some optimizer does not combine a call like
9499 foo(strlen(bar), strlen(bar));
9500 when the move and the subtraction is done here. It does calculate
9501 the length just once when these instructions are done inside of
9502 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
9503 often used and I use one fewer register for the lifetime of
9504 output_strlen_unroll() this is better. */
9506 emit_move_insn (out
, addr
);
9508 ix86_expand_strlensi_unroll_1 (out
, align
);
9510 /* strlensi_unroll_1 returns the address of the zero at the end of
9511 the string, like memchr(), so compute the length by subtracting
9512 the start address. */
9514 emit_insn (gen_subdi3 (out
, out
, addr
));
9516 emit_insn (gen_subsi3 (out
, out
, addr
));
9520 scratch2
= gen_reg_rtx (Pmode
);
9521 scratch3
= gen_reg_rtx (Pmode
);
9522 scratch4
= force_reg (Pmode
, constm1_rtx
);
9524 emit_move_insn (scratch3
, addr
);
9525 eoschar
= force_reg (QImode
, eoschar
);
9527 emit_insn (gen_cld ());
9530 emit_insn (gen_strlenqi_rex_1 (scratch1
, scratch3
, eoschar
,
9531 align
, scratch4
, scratch3
));
9532 emit_insn (gen_one_cmpldi2 (scratch2
, scratch1
));
9533 emit_insn (gen_adddi3 (out
, scratch2
, constm1_rtx
));
9537 emit_insn (gen_strlenqi_1 (scratch1
, scratch3
, eoschar
,
9538 align
, scratch4
, scratch3
));
9539 emit_insn (gen_one_cmplsi2 (scratch2
, scratch1
));
9540 emit_insn (gen_addsi3 (out
, scratch2
, constm1_rtx
));
9546 /* Expand the appropriate insns for doing strlen if not just doing
9549 out = result, initialized with the start address
9550 align_rtx = alignment of the address.
9551 scratch = scratch register, initialized with the startaddress when
9552 not aligned, otherwise undefined
9554 This is just the body. It needs the initialisations mentioned above and
9555 some address computing at the end. These things are done in i386.md. */
9558 ix86_expand_strlensi_unroll_1 (out
, align_rtx
)
9563 rtx align_2_label
= NULL_RTX
;
9564 rtx align_3_label
= NULL_RTX
;
9565 rtx align_4_label
= gen_label_rtx ();
9566 rtx end_0_label
= gen_label_rtx ();
9568 rtx tmpreg
= gen_reg_rtx (SImode
);
9569 rtx scratch
= gen_reg_rtx (SImode
);
9572 if (GET_CODE (align_rtx
) == CONST_INT
)
9573 align
= INTVAL (align_rtx
);
9575 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
9577 /* Is there a known alignment and is it less than 4? */
9580 rtx scratch1
= gen_reg_rtx (Pmode
);
9581 emit_move_insn (scratch1
, out
);
9582 /* Is there a known alignment and is it not 2? */
9585 align_3_label
= gen_label_rtx (); /* Label when aligned to 3-byte */
9586 align_2_label
= gen_label_rtx (); /* Label when aligned to 2-byte */
9588 /* Leave just the 3 lower bits. */
9589 align_rtx
= expand_binop (Pmode
, and_optab
, scratch1
, GEN_INT (3),
9590 NULL_RTX
, 0, OPTAB_WIDEN
);
9592 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
9593 Pmode
, 1, align_4_label
);
9594 emit_cmp_and_jump_insns (align_rtx
, GEN_INT (2), EQ
, NULL
,
9595 Pmode
, 1, align_2_label
);
9596 emit_cmp_and_jump_insns (align_rtx
, GEN_INT (2), GTU
, NULL
,
9597 Pmode
, 1, align_3_label
);
9601 /* Since the alignment is 2, we have to check 2 or 0 bytes;
9602 check if is aligned to 4 - byte. */
9604 align_rtx
= expand_binop (Pmode
, and_optab
, scratch1
, GEN_INT (2),
9605 NULL_RTX
, 0, OPTAB_WIDEN
);
9607 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
9608 Pmode
, 1, align_4_label
);
9611 mem
= gen_rtx_MEM (QImode
, out
);
9613 /* Now compare the bytes. */
9615 /* Compare the first n unaligned byte on a byte per byte basis. */
9616 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
,
9617 QImode
, 1, end_0_label
);
9619 /* Increment the address. */
9621 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
9623 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
9625 /* Not needed with an alignment of 2 */
9628 emit_label (align_2_label
);
9630 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
, QImode
, 1,
9634 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
9636 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
9638 emit_label (align_3_label
);
9641 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
, QImode
, 1,
9645 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
9647 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
9650 /* Generate loop to check 4 bytes at a time. It is not a good idea to
9651 align this loop. It gives only huge programs, but does not help to
9653 emit_label (align_4_label
);
9655 mem
= gen_rtx_MEM (SImode
, out
);
9656 emit_move_insn (scratch
, mem
);
9658 emit_insn (gen_adddi3 (out
, out
, GEN_INT (4)));
9660 emit_insn (gen_addsi3 (out
, out
, GEN_INT (4)));
9662 /* This formula yields a nonzero result iff one of the bytes is zero.
9663 This saves three branches inside loop and many cycles. */
9665 emit_insn (gen_addsi3 (tmpreg
, scratch
, GEN_INT (-0x01010101)));
9666 emit_insn (gen_one_cmplsi2 (scratch
, scratch
));
9667 emit_insn (gen_andsi3 (tmpreg
, tmpreg
, scratch
));
9668 emit_insn (gen_andsi3 (tmpreg
, tmpreg
,
9669 gen_int_mode (0x80808080, SImode
)));
9670 emit_cmp_and_jump_insns (tmpreg
, const0_rtx
, EQ
, 0, SImode
, 1,
9675 rtx reg
= gen_reg_rtx (SImode
);
9676 rtx reg2
= gen_reg_rtx (Pmode
);
9677 emit_move_insn (reg
, tmpreg
);
9678 emit_insn (gen_lshrsi3 (reg
, reg
, GEN_INT (16)));
9680 /* If zero is not in the first two bytes, move two bytes forward. */
9681 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
9682 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
9683 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
9684 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
,
9685 gen_rtx_IF_THEN_ELSE (SImode
, tmp
,
9688 /* Emit lea manually to avoid clobbering of flags. */
9689 emit_insn (gen_rtx_SET (SImode
, reg2
,
9690 gen_rtx_PLUS (Pmode
, out
, GEN_INT (2))));
9692 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
9693 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
9694 emit_insn (gen_rtx_SET (VOIDmode
, out
,
9695 gen_rtx_IF_THEN_ELSE (Pmode
, tmp
,
9702 rtx end_2_label
= gen_label_rtx ();
9703 /* Is zero in the first two bytes? */
9705 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
9706 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
9707 tmp
= gen_rtx_NE (VOIDmode
, tmp
, const0_rtx
);
9708 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
9709 gen_rtx_LABEL_REF (VOIDmode
, end_2_label
),
9711 tmp
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
9712 JUMP_LABEL (tmp
) = end_2_label
;
9714 /* Not in the first two. Move two bytes forward. */
9715 emit_insn (gen_lshrsi3 (tmpreg
, tmpreg
, GEN_INT (16)));
9717 emit_insn (gen_adddi3 (out
, out
, GEN_INT (2)));
9719 emit_insn (gen_addsi3 (out
, out
, GEN_INT (2)));
9721 emit_label (end_2_label
);
9725 /* Avoid branch in fixing the byte. */
9726 tmpreg
= gen_lowpart (QImode
, tmpreg
);
9727 emit_insn (gen_addqi3_cc (tmpreg
, tmpreg
, tmpreg
));
9729 emit_insn (gen_subdi3_carry_rex64 (out
, out
, GEN_INT (3)));
9731 emit_insn (gen_subsi3_carry (out
, out
, GEN_INT (3)));
9733 emit_label (end_0_label
);
9736 /* Clear stack slot assignments remembered from previous functions.
9737 This is called from INIT_EXPANDERS once before RTL is emitted for each
9741 ix86_init_machine_status (p
)
9744 p
->machine
= (struct machine_function
*)
9745 xcalloc (1, sizeof (struct machine_function
));
9748 /* Mark machine specific bits of P for GC. */
9750 ix86_mark_machine_status (p
)
9753 struct machine_function
*machine
= p
->machine
;
9754 enum machine_mode mode
;
9760 for (mode
= VOIDmode
; (int) mode
< (int) MAX_MACHINE_MODE
;
9761 mode
= (enum machine_mode
) ((int) mode
+ 1))
9762 for (n
= 0; n
< MAX_386_STACK_LOCALS
; n
++)
9763 ggc_mark_rtx (machine
->stack_locals
[(int) mode
][n
]);
9767 ix86_free_machine_status (p
)
9774 /* Return a MEM corresponding to a stack slot with mode MODE.
9775 Allocate a new slot if necessary.
9777 The RTL for a function can have several slots available: N is
9778 which slot to use. */
9781 assign_386_stack_local (mode
, n
)
9782 enum machine_mode mode
;
9785 if (n
< 0 || n
>= MAX_386_STACK_LOCALS
)
9788 if (ix86_stack_locals
[(int) mode
][n
] == NULL_RTX
)
9789 ix86_stack_locals
[(int) mode
][n
]
9790 = assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
9792 return ix86_stack_locals
[(int) mode
][n
];
9795 /* Calculate the length of the memory address in the instruction
9796 encoding. Does not include the one-byte modrm, opcode, or prefix. */
9799 memory_address_length (addr
)
9802 struct ix86_address parts
;
9803 rtx base
, index
, disp
;
9806 if (GET_CODE (addr
) == PRE_DEC
9807 || GET_CODE (addr
) == POST_INC
9808 || GET_CODE (addr
) == PRE_MODIFY
9809 || GET_CODE (addr
) == POST_MODIFY
)
9812 if (! ix86_decompose_address (addr
, &parts
))
9816 index
= parts
.index
;
9820 /* Register Indirect. */
9821 if (base
&& !index
&& !disp
)
9823 /* Special cases: ebp and esp need the two-byte modrm form. */
9824 if (addr
== stack_pointer_rtx
9825 || addr
== arg_pointer_rtx
9826 || addr
== frame_pointer_rtx
9827 || addr
== hard_frame_pointer_rtx
)
9831 /* Direct Addressing. */
9832 else if (disp
&& !base
&& !index
)
9837 /* Find the length of the displacement constant. */
9840 if (GET_CODE (disp
) == CONST_INT
9841 && CONST_OK_FOR_LETTER_P (INTVAL (disp
), 'K'))
9847 /* An index requires the two-byte modrm form. */
9855 /* Compute default value for "length_immediate" attribute. When SHORTFORM is set
9856 expect that insn have 8bit immediate alternative. */
9858 ix86_attr_length_immediate_default (insn
, shortform
)
9864 extract_insn_cached (insn
);
9865 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
9866 if (CONSTANT_P (recog_data
.operand
[i
]))
9871 && GET_CODE (recog_data
.operand
[i
]) == CONST_INT
9872 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data
.operand
[i
]), 'K'))
9876 switch (get_attr_mode (insn
))
9887 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
9892 fatal_insn ("unknown insn mode", insn
);
9898 /* Compute default value for "length_address" attribute. */
9900 ix86_attr_length_address_default (insn
)
9904 extract_insn_cached (insn
);
9905 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
9906 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
9908 return memory_address_length (XEXP (recog_data
.operand
[i
], 0));
9914 /* Return the maximum number of instructions a cpu can issue. */
9921 case PROCESSOR_PENTIUM
:
9925 case PROCESSOR_PENTIUMPRO
:
9926 case PROCESSOR_PENTIUM4
:
9927 case PROCESSOR_ATHLON
:
9935 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
9936 by DEP_INSN and nothing set by DEP_INSN. */
9939 ix86_flags_dependant (insn
, dep_insn
, insn_type
)
9941 enum attr_type insn_type
;
9945 /* Simplify the test for uninteresting insns. */
9946 if (insn_type
!= TYPE_SETCC
9947 && insn_type
!= TYPE_ICMOV
9948 && insn_type
!= TYPE_FCMOV
9949 && insn_type
!= TYPE_IBR
)
9952 if ((set
= single_set (dep_insn
)) != 0)
9954 set
= SET_DEST (set
);
9957 else if (GET_CODE (PATTERN (dep_insn
)) == PARALLEL
9958 && XVECLEN (PATTERN (dep_insn
), 0) == 2
9959 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 0)) == SET
9960 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 1)) == SET
)
9962 set
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
9963 set2
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
9968 if (GET_CODE (set
) != REG
|| REGNO (set
) != FLAGS_REG
)
9971 /* This test is true if the dependent insn reads the flags but
9972 not any other potentially set register. */
9973 if (!reg_overlap_mentioned_p (set
, PATTERN (insn
)))
9976 if (set2
&& reg_overlap_mentioned_p (set2
, PATTERN (insn
)))
9982 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
9983 address with operands set by DEP_INSN. */
9986 ix86_agi_dependant (insn
, dep_insn
, insn_type
)
9988 enum attr_type insn_type
;
9992 if (insn_type
== TYPE_LEA
9995 addr
= PATTERN (insn
);
9996 if (GET_CODE (addr
) == SET
)
9998 else if (GET_CODE (addr
) == PARALLEL
9999 && GET_CODE (XVECEXP (addr
, 0, 0)) == SET
)
10000 addr
= XVECEXP (addr
, 0, 0);
10003 addr
= SET_SRC (addr
);
10008 extract_insn_cached (insn
);
10009 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
10010 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
10012 addr
= XEXP (recog_data
.operand
[i
], 0);
10019 return modified_in_p (addr
, dep_insn
);
10023 ix86_adjust_cost (insn
, link
, dep_insn
, cost
)
10024 rtx insn
, link
, dep_insn
;
10027 enum attr_type insn_type
, dep_insn_type
;
10028 enum attr_memory memory
, dep_memory
;
10030 int dep_insn_code_number
;
10032 /* Anti and output depenancies have zero cost on all CPUs. */
10033 if (REG_NOTE_KIND (link
) != 0)
10036 dep_insn_code_number
= recog_memoized (dep_insn
);
10038 /* If we can't recognize the insns, we can't really do anything. */
10039 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
10042 insn_type
= get_attr_type (insn
);
10043 dep_insn_type
= get_attr_type (dep_insn
);
10047 case PROCESSOR_PENTIUM
:
10048 /* Address Generation Interlock adds a cycle of latency. */
10049 if (ix86_agi_dependant (insn
, dep_insn
, insn_type
))
10052 /* ??? Compares pair with jump/setcc. */
10053 if (ix86_flags_dependant (insn
, dep_insn
, insn_type
))
10056 /* Floating point stores require value to be ready one cycle ealier. */
10057 if (insn_type
== TYPE_FMOV
10058 && get_attr_memory (insn
) == MEMORY_STORE
10059 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
10063 case PROCESSOR_PENTIUMPRO
:
10064 memory
= get_attr_memory (insn
);
10065 dep_memory
= get_attr_memory (dep_insn
);
10067 /* Since we can't represent delayed latencies of load+operation,
10068 increase the cost here for non-imov insns. */
10069 if (dep_insn_type
!= TYPE_IMOV
10070 && dep_insn_type
!= TYPE_FMOV
10071 && (dep_memory
== MEMORY_LOAD
|| dep_memory
== MEMORY_BOTH
))
10074 /* INT->FP conversion is expensive. */
10075 if (get_attr_fp_int_src (dep_insn
))
10078 /* There is one cycle extra latency between an FP op and a store. */
10079 if (insn_type
== TYPE_FMOV
10080 && (set
= single_set (dep_insn
)) != NULL_RTX
10081 && (set2
= single_set (insn
)) != NULL_RTX
10082 && rtx_equal_p (SET_DEST (set
), SET_SRC (set2
))
10083 && GET_CODE (SET_DEST (set2
)) == MEM
)
10086 /* Show ability of reorder buffer to hide latency of load by executing
10087 in parallel with previous instruction in case
10088 previous instruction is not needed to compute the address. */
10089 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
10090 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
10092 /* Claim moves to take one cycle, as core can issue one load
10093 at time and the next load can start cycle later. */
10094 if (dep_insn_type
== TYPE_IMOV
10095 || dep_insn_type
== TYPE_FMOV
)
10103 memory
= get_attr_memory (insn
);
10104 dep_memory
= get_attr_memory (dep_insn
);
10105 /* The esp dependency is resolved before the instruction is really
10107 if ((insn_type
== TYPE_PUSH
|| insn_type
== TYPE_POP
)
10108 && (dep_insn_type
== TYPE_PUSH
|| dep_insn_type
== TYPE_POP
))
10111 /* Since we can't represent delayed latencies of load+operation,
10112 increase the cost here for non-imov insns. */
10113 if (dep_memory
== MEMORY_LOAD
|| dep_memory
== MEMORY_BOTH
)
10114 cost
+= (dep_insn_type
!= TYPE_IMOV
) ? 2 : 1;
10116 /* INT->FP conversion is expensive. */
10117 if (get_attr_fp_int_src (dep_insn
))
10120 /* Show ability of reorder buffer to hide latency of load by executing
10121 in parallel with previous instruction in case
10122 previous instruction is not needed to compute the address. */
10123 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
10124 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
10126 /* Claim moves to take one cycle, as core can issue one load
10127 at time and the next load can start cycle later. */
10128 if (dep_insn_type
== TYPE_IMOV
10129 || dep_insn_type
== TYPE_FMOV
)
10138 case PROCESSOR_ATHLON
:
10139 memory
= get_attr_memory (insn
);
10140 dep_memory
= get_attr_memory (dep_insn
);
10142 if (dep_memory
== MEMORY_LOAD
|| dep_memory
== MEMORY_BOTH
)
10144 if (dep_insn_type
== TYPE_IMOV
|| dep_insn_type
== TYPE_FMOV
)
10149 /* Show ability of reorder buffer to hide latency of load by executing
10150 in parallel with previous instruction in case
10151 previous instruction is not needed to compute the address. */
10152 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
10153 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
10155 /* Claim moves to take one cycle, as core can issue one load
10156 at time and the next load can start cycle later. */
10157 if (dep_insn_type
== TYPE_IMOV
10158 || dep_insn_type
== TYPE_FMOV
)
10160 else if (cost
>= 3)
10175 struct ppro_sched_data
10178 int issued_this_cycle
;
10183 ix86_safe_length (insn
)
10186 if (recog_memoized (insn
) >= 0)
10187 return get_attr_length (insn
);
10193 ix86_safe_length_prefix (insn
)
10196 if (recog_memoized (insn
) >= 0)
10197 return get_attr_length (insn
);
10202 static enum attr_memory
10203 ix86_safe_memory (insn
)
10206 if (recog_memoized (insn
) >= 0)
10207 return get_attr_memory (insn
);
10209 return MEMORY_UNKNOWN
;
10212 static enum attr_pent_pair
10213 ix86_safe_pent_pair (insn
)
10216 if (recog_memoized (insn
) >= 0)
10217 return get_attr_pent_pair (insn
);
10219 return PENT_PAIR_NP
;
10222 static enum attr_ppro_uops
10223 ix86_safe_ppro_uops (insn
)
10226 if (recog_memoized (insn
) >= 0)
10227 return get_attr_ppro_uops (insn
);
10229 return PPRO_UOPS_MANY
;
10233 ix86_dump_ppro_packet (dump
)
10236 if (ix86_sched_data
.ppro
.decode
[0])
10238 fprintf (dump
, "PPRO packet: %d",
10239 INSN_UID (ix86_sched_data
.ppro
.decode
[0]));
10240 if (ix86_sched_data
.ppro
.decode
[1])
10241 fprintf (dump
, " %d", INSN_UID (ix86_sched_data
.ppro
.decode
[1]));
10242 if (ix86_sched_data
.ppro
.decode
[2])
10243 fprintf (dump
, " %d", INSN_UID (ix86_sched_data
.ppro
.decode
[2]));
10244 fputc ('\n', dump
);
10248 /* We're beginning a new block. Initialize data structures as necessary. */
10251 ix86_sched_init (dump
, sched_verbose
, veclen
)
10252 FILE *dump ATTRIBUTE_UNUSED
;
10253 int sched_verbose ATTRIBUTE_UNUSED
;
10254 int veclen ATTRIBUTE_UNUSED
;
10256 memset (&ix86_sched_data
, 0, sizeof (ix86_sched_data
));
10259 /* Shift INSN to SLOT, and shift everything else down. */
10262 ix86_reorder_insn (insnp
, slot
)
10269 insnp
[0] = insnp
[1];
10270 while (++insnp
!= slot
);
10275 /* Find an instruction with given pairability and minimal amount of cycles
10276 lost by the fact that the CPU waits for both pipelines to finish before
10277 reading next instructions. Also take care that both instructions together
10278 can not exceed 7 bytes. */
10281 ix86_pent_find_pair (e_ready
, ready
, type
, first
)
10284 enum attr_pent_pair type
;
10287 int mincycles
, cycles
;
10288 enum attr_pent_pair tmp
;
10289 enum attr_memory memory
;
10290 rtx
*insnp
, *bestinsnp
= NULL
;
10292 if (ix86_safe_length (first
) > 7 + ix86_safe_length_prefix (first
))
10295 memory
= ix86_safe_memory (first
);
10296 cycles
= result_ready_cost (first
);
10297 mincycles
= INT_MAX
;
10299 for (insnp
= e_ready
; insnp
>= ready
&& mincycles
; --insnp
)
10300 if ((tmp
= ix86_safe_pent_pair (*insnp
)) == type
10301 && ix86_safe_length (*insnp
) <= 7 + ix86_safe_length_prefix (*insnp
))
10303 enum attr_memory second_memory
;
10304 int secondcycles
, currentcycles
;
10306 second_memory
= ix86_safe_memory (*insnp
);
10307 secondcycles
= result_ready_cost (*insnp
);
10308 currentcycles
= abs (cycles
- secondcycles
);
10310 if (secondcycles
>= 1 && cycles
>= 1)
10312 /* Two read/modify/write instructions together takes two
10314 if (memory
== MEMORY_BOTH
&& second_memory
== MEMORY_BOTH
)
10315 currentcycles
+= 2;
10317 /* Read modify/write instruction followed by read/modify
10318 takes one cycle longer. */
10319 if (memory
== MEMORY_BOTH
&& second_memory
== MEMORY_LOAD
10320 && tmp
!= PENT_PAIR_UV
10321 && ix86_safe_pent_pair (first
) != PENT_PAIR_UV
)
10322 currentcycles
+= 1;
10324 if (currentcycles
< mincycles
)
10325 bestinsnp
= insnp
, mincycles
= currentcycles
;
10331 /* Subroutines of ix86_sched_reorder. */
10334 ix86_sched_reorder_pentium (ready
, e_ready
)
10338 enum attr_pent_pair pair1
, pair2
;
10341 /* This wouldn't be necessary if Haifa knew that static insn ordering
10342 is important to which pipe an insn is issued to. So we have to make
10343 some minor rearrangements. */
10345 pair1
= ix86_safe_pent_pair (*e_ready
);
10347 /* If the first insn is non-pairable, let it be. */
10348 if (pair1
== PENT_PAIR_NP
)
10351 pair2
= PENT_PAIR_NP
;
10354 /* If the first insn is UV or PV pairable, search for a PU
10355 insn to go with. */
10356 if (pair1
== PENT_PAIR_UV
|| pair1
== PENT_PAIR_PV
)
10358 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
10359 PENT_PAIR_PU
, *e_ready
);
10361 pair2
= PENT_PAIR_PU
;
10364 /* If the first insn is PU or UV pairable, search for a PV
10365 insn to go with. */
10366 if (pair2
== PENT_PAIR_NP
10367 && (pair1
== PENT_PAIR_PU
|| pair1
== PENT_PAIR_UV
))
10369 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
10370 PENT_PAIR_PV
, *e_ready
);
10372 pair2
= PENT_PAIR_PV
;
10375 /* If the first insn is pairable, search for a UV
10376 insn to go with. */
10377 if (pair2
== PENT_PAIR_NP
)
10379 insnp
= ix86_pent_find_pair (e_ready
-1, ready
,
10380 PENT_PAIR_UV
, *e_ready
);
10382 pair2
= PENT_PAIR_UV
;
10385 if (pair2
== PENT_PAIR_NP
)
10388 /* Found something! Decide if we need to swap the order. */
10389 if (pair1
== PENT_PAIR_PV
|| pair2
== PENT_PAIR_PU
10390 || (pair1
== PENT_PAIR_UV
&& pair2
== PENT_PAIR_UV
10391 && ix86_safe_memory (*e_ready
) == MEMORY_BOTH
10392 && ix86_safe_memory (*insnp
) == MEMORY_LOAD
))
10393 ix86_reorder_insn (insnp
, e_ready
);
10395 ix86_reorder_insn (insnp
, e_ready
- 1);
10399 ix86_sched_reorder_ppro (ready
, e_ready
)
10404 enum attr_ppro_uops cur_uops
;
10405 int issued_this_cycle
;
10409 /* At this point .ppro.decode contains the state of the three
10410 decoders from last "cycle". That is, those insns that were
10411 actually independent. But here we're scheduling for the
10412 decoder, and we may find things that are decodable in the
10415 memcpy (decode
, ix86_sched_data
.ppro
.decode
, sizeof (decode
));
10416 issued_this_cycle
= 0;
10419 cur_uops
= ix86_safe_ppro_uops (*insnp
);
10421 /* If the decoders are empty, and we've a complex insn at the
10422 head of the priority queue, let it issue without complaint. */
10423 if (decode
[0] == NULL
)
10425 if (cur_uops
== PPRO_UOPS_MANY
)
10427 decode
[0] = *insnp
;
10431 /* Otherwise, search for a 2-4 uop unsn to issue. */
10432 while (cur_uops
!= PPRO_UOPS_FEW
)
10434 if (insnp
== ready
)
10436 cur_uops
= ix86_safe_ppro_uops (*--insnp
);
10439 /* If so, move it to the head of the line. */
10440 if (cur_uops
== PPRO_UOPS_FEW
)
10441 ix86_reorder_insn (insnp
, e_ready
);
10443 /* Issue the head of the queue. */
10444 issued_this_cycle
= 1;
10445 decode
[0] = *e_ready
--;
10448 /* Look for simple insns to fill in the other two slots. */
10449 for (i
= 1; i
< 3; ++i
)
10450 if (decode
[i
] == NULL
)
10452 if (ready
>= e_ready
)
10456 cur_uops
= ix86_safe_ppro_uops (*insnp
);
10457 while (cur_uops
!= PPRO_UOPS_ONE
)
10459 if (insnp
== ready
)
10461 cur_uops
= ix86_safe_ppro_uops (*--insnp
);
10464 /* Found one. Move it to the head of the queue and issue it. */
10465 if (cur_uops
== PPRO_UOPS_ONE
)
10467 ix86_reorder_insn (insnp
, e_ready
);
10468 decode
[i
] = *e_ready
--;
10469 issued_this_cycle
++;
10473 /* ??? Didn't find one. Ideally, here we would do a lazy split
10474 of 2-uop insns, issue one and queue the other. */
10478 if (issued_this_cycle
== 0)
10479 issued_this_cycle
= 1;
10480 ix86_sched_data
.ppro
.issued_this_cycle
= issued_this_cycle
;
10483 /* We are about to being issuing insns for this clock cycle.
10484 Override the default sort algorithm to better slot instructions. */
10486 ix86_sched_reorder (dump
, sched_verbose
, ready
, n_readyp
, clock_var
)
10487 FILE *dump ATTRIBUTE_UNUSED
;
10488 int sched_verbose ATTRIBUTE_UNUSED
;
10491 int clock_var ATTRIBUTE_UNUSED
;
10493 int n_ready
= *n_readyp
;
10494 rtx
*e_ready
= ready
+ n_ready
- 1;
10504 case PROCESSOR_PENTIUM
:
10505 ix86_sched_reorder_pentium (ready
, e_ready
);
10508 case PROCESSOR_PENTIUMPRO
:
10509 ix86_sched_reorder_ppro (ready
, e_ready
);
10514 return ix86_issue_rate ();
10517 /* We are about to issue INSN. Return the number of insns left on the
10518 ready queue that can be issued this cycle. */
10521 ix86_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
)
10525 int can_issue_more
;
10531 return can_issue_more
- 1;
10533 case PROCESSOR_PENTIUMPRO
:
10535 enum attr_ppro_uops uops
= ix86_safe_ppro_uops (insn
);
10537 if (uops
== PPRO_UOPS_MANY
)
10540 ix86_dump_ppro_packet (dump
);
10541 ix86_sched_data
.ppro
.decode
[0] = insn
;
10542 ix86_sched_data
.ppro
.decode
[1] = NULL
;
10543 ix86_sched_data
.ppro
.decode
[2] = NULL
;
10545 ix86_dump_ppro_packet (dump
);
10546 ix86_sched_data
.ppro
.decode
[0] = NULL
;
10548 else if (uops
== PPRO_UOPS_FEW
)
10551 ix86_dump_ppro_packet (dump
);
10552 ix86_sched_data
.ppro
.decode
[0] = insn
;
10553 ix86_sched_data
.ppro
.decode
[1] = NULL
;
10554 ix86_sched_data
.ppro
.decode
[2] = NULL
;
10558 for (i
= 0; i
< 3; ++i
)
10559 if (ix86_sched_data
.ppro
.decode
[i
] == NULL
)
10561 ix86_sched_data
.ppro
.decode
[i
] = insn
;
10569 ix86_dump_ppro_packet (dump
);
10570 ix86_sched_data
.ppro
.decode
[0] = NULL
;
10571 ix86_sched_data
.ppro
.decode
[1] = NULL
;
10572 ix86_sched_data
.ppro
.decode
[2] = NULL
;
10576 return --ix86_sched_data
.ppro
.issued_this_cycle
;
10580 /* Walk through INSNS and look for MEM references whose address is DSTREG or
10581 SRCREG and set the memory attribute to those of DSTREF and SRCREF, as
10585 ix86_set_move_mem_attrs (insns
, dstref
, srcref
, dstreg
, srcreg
)
10587 rtx dstref
, srcref
, dstreg
, srcreg
;
10591 for (insn
= insns
; insn
!= 0 ; insn
= NEXT_INSN (insn
))
10593 ix86_set_move_mem_attrs_1 (PATTERN (insn
), dstref
, srcref
,
10597 /* Subroutine of above to actually do the updating by recursively walking
10601 ix86_set_move_mem_attrs_1 (x
, dstref
, srcref
, dstreg
, srcreg
)
10603 rtx dstref
, srcref
, dstreg
, srcreg
;
10605 enum rtx_code code
= GET_CODE (x
);
10606 const char *format_ptr
= GET_RTX_FORMAT (code
);
10609 if (code
== MEM
&& XEXP (x
, 0) == dstreg
)
10610 MEM_COPY_ATTRIBUTES (x
, dstref
);
10611 else if (code
== MEM
&& XEXP (x
, 0) == srcreg
)
10612 MEM_COPY_ATTRIBUTES (x
, srcref
);
10614 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, format_ptr
++)
10616 if (*format_ptr
== 'e')
10617 ix86_set_move_mem_attrs_1 (XEXP (x
, i
), dstref
, srcref
,
10619 else if (*format_ptr
== 'E')
10620 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10621 ix86_set_move_mem_attrs_1 (XVECEXP (x
, i
, j
), dstref
, srcref
,
10626 /* Compute the alignment given to a constant that is being placed in memory.
10627 EXP is the constant and ALIGN is the alignment that the object would
10629 The value of this function is used instead of that alignment to align
10633 ix86_constant_alignment (exp
, align
)
10637 if (TREE_CODE (exp
) == REAL_CST
)
10639 if (TYPE_MODE (TREE_TYPE (exp
)) == DFmode
&& align
< 64)
10641 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp
))) && align
< 128)
10644 else if (TREE_CODE (exp
) == STRING_CST
&& TREE_STRING_LENGTH (exp
) >= 31
10651 /* Compute the alignment for a static variable.
10652 TYPE is the data type, and ALIGN is the alignment that
10653 the object would ordinarily have. The value of this function is used
10654 instead of that alignment to align the object. */
10657 ix86_data_alignment (type
, align
)
10661 if (AGGREGATE_TYPE_P (type
)
10662 && TYPE_SIZE (type
)
10663 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
10664 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 256
10665 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 256)
10668 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
10669 to 16byte boundary. */
10672 if (AGGREGATE_TYPE_P (type
)
10673 && TYPE_SIZE (type
)
10674 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
10675 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 128
10676 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 128)
10680 if (TREE_CODE (type
) == ARRAY_TYPE
)
10682 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
10684 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
10687 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
10690 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
10692 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
10695 else if ((TREE_CODE (type
) == RECORD_TYPE
10696 || TREE_CODE (type
) == UNION_TYPE
10697 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
10698 && TYPE_FIELDS (type
))
10700 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
10702 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
10705 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
10706 || TREE_CODE (type
) == INTEGER_TYPE
)
10708 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
10710 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
10717 /* Compute the alignment for a local variable.
10718 TYPE is the data type, and ALIGN is the alignment that
10719 the object would ordinarily have. The value of this macro is used
10720 instead of that alignment to align the object. */
10723 ix86_local_alignment (type
, align
)
10727 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
10728 to 16byte boundary. */
10731 if (AGGREGATE_TYPE_P (type
)
10732 && TYPE_SIZE (type
)
10733 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
10734 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 16
10735 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 128)
10738 if (TREE_CODE (type
) == ARRAY_TYPE
)
10740 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
10742 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
10745 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
10747 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
10749 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
10752 else if ((TREE_CODE (type
) == RECORD_TYPE
10753 || TREE_CODE (type
) == UNION_TYPE
10754 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
10755 && TYPE_FIELDS (type
))
10757 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
10759 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
10762 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
10763 || TREE_CODE (type
) == INTEGER_TYPE
)
10766 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
10768 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
10774 /* Emit RTL insns to initialize the variable parts of a trampoline.
10775 FNADDR is an RTX for the address of the function's pure code.
10776 CXT is an RTX for the static chain value for the function. */
10778 x86_initialize_trampoline (tramp
, fnaddr
, cxt
)
10779 rtx tramp
, fnaddr
, cxt
;
10783 /* Compute offset from the end of the jmp to the target function. */
10784 rtx disp
= expand_binop (SImode
, sub_optab
, fnaddr
,
10785 plus_constant (tramp
, 10),
10786 NULL_RTX
, 1, OPTAB_DIRECT
);
10787 emit_move_insn (gen_rtx_MEM (QImode
, tramp
),
10788 gen_int_mode (0xb9, QImode
));
10789 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 1)), cxt
);
10790 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 5)),
10791 gen_int_mode (0xe9, QImode
));
10792 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 6)), disp
);
10797 /* Try to load address using shorter movl instead of movabs.
10798 We may want to support movq for kernel mode, but kernel does not use
10799 trampolines at the moment. */
10800 if (x86_64_zero_extended_value (fnaddr
))
10802 fnaddr
= copy_to_mode_reg (DImode
, fnaddr
);
10803 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
10804 gen_int_mode (0xbb41, HImode
));
10805 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, offset
+ 2)),
10806 gen_lowpart (SImode
, fnaddr
));
10811 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
10812 gen_int_mode (0xbb49, HImode
));
10813 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, offset
+ 2)),
10817 /* Load static chain using movabs to r10. */
10818 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
10819 gen_int_mode (0xba49, HImode
));
10820 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, offset
+ 2)),
10823 /* Jump to the r11 */
10824 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
10825 gen_int_mode (0xff49, HImode
));
10826 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, offset
+2)),
10827 gen_int_mode (0xe3, QImode
));
10829 if (offset
> TRAMPOLINE_SIZE
)
10834 #define def_builtin(MASK, NAME, TYPE, CODE) \
10836 if ((MASK) & target_flags) \
10837 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \
10840 struct builtin_description
10842 const unsigned int mask
;
10843 const enum insn_code icode
;
10844 const char *const name
;
10845 const enum ix86_builtins code
;
10846 const enum rtx_code comparison
;
10847 const unsigned int flag
;
10850 static const struct builtin_description bdesc_comi
[] =
10852 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS
, EQ
, 0 },
10853 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS
, LT
, 0 },
10854 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS
, LE
, 0 },
10855 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS
, LT
, 1 },
10856 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS
, LE
, 1 },
10857 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS
, NE
, 0 },
10858 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS
, EQ
, 0 },
10859 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS
, LT
, 0 },
10860 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS
, LE
, 0 },
10861 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS
, LT
, 1 },
10862 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS
, LE
, 1 },
10863 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS
, NE
, 0 }
10866 static const struct builtin_description bdesc_2arg
[] =
10869 { MASK_SSE
, CODE_FOR_addv4sf3
, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS
, 0, 0 },
10870 { MASK_SSE
, CODE_FOR_subv4sf3
, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS
, 0, 0 },
10871 { MASK_SSE
, CODE_FOR_mulv4sf3
, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS
, 0, 0 },
10872 { MASK_SSE
, CODE_FOR_divv4sf3
, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS
, 0, 0 },
10873 { MASK_SSE
, CODE_FOR_vmaddv4sf3
, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS
, 0, 0 },
10874 { MASK_SSE
, CODE_FOR_vmsubv4sf3
, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS
, 0, 0 },
10875 { MASK_SSE
, CODE_FOR_vmmulv4sf3
, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS
, 0, 0 },
10876 { MASK_SSE
, CODE_FOR_vmdivv4sf3
, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS
, 0, 0 },
10878 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS
, EQ
, 0 },
10879 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS
, LT
, 0 },
10880 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS
, LE
, 0 },
10881 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS
, LT
, 1 },
10882 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS
, LE
, 1 },
10883 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS
, UNORDERED
, 0 },
10884 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS
, EQ
, 0 },
10885 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS
, LT
, 0 },
10886 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS
, LE
, 0 },
10887 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS
, LT
, 1 },
10888 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS
, LE
, 1 },
10889 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS
, UNORDERED
, 0 },
10890 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS
, EQ
, 0 },
10891 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS
, LT
, 0 },
10892 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS
, LE
, 0 },
10893 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpgtss", IX86_BUILTIN_CMPGTSS
, LT
, 1 },
10894 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpgess", IX86_BUILTIN_CMPGESS
, LE
, 1 },
10895 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS
, UNORDERED
, 0 },
10896 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS
, EQ
, 0 },
10897 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS
, LT
, 0 },
10898 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS
, LE
, 0 },
10899 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS
, LT
, 1 },
10900 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS
, LE
, 1 },
10901 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS
, UNORDERED
, 0 },
10903 { MASK_SSE
, CODE_FOR_sminv4sf3
, "__builtin_ia32_minps", IX86_BUILTIN_MINPS
, 0, 0 },
10904 { MASK_SSE
, CODE_FOR_smaxv4sf3
, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS
, 0, 0 },
10905 { MASK_SSE
, CODE_FOR_vmsminv4sf3
, "__builtin_ia32_minss", IX86_BUILTIN_MINSS
, 0, 0 },
10906 { MASK_SSE
, CODE_FOR_vmsmaxv4sf3
, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS
, 0, 0 },
10908 { MASK_SSE
, CODE_FOR_sse_movss
, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS
, 0, 0 },
10909 { MASK_SSE
, CODE_FOR_sse_movhlps
, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS
, 0, 0 },
10910 { MASK_SSE
, CODE_FOR_sse_movlhps
, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS
, 0, 0 },
10911 { MASK_SSE
, CODE_FOR_sse_unpckhps
, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS
, 0, 0 },
10912 { MASK_SSE
, CODE_FOR_sse_unpcklps
, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS
, 0, 0 },
10915 { MASK_MMX
, CODE_FOR_addv8qi3
, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB
, 0, 0 },
10916 { MASK_MMX
, CODE_FOR_addv4hi3
, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW
, 0, 0 },
10917 { MASK_MMX
, CODE_FOR_addv2si3
, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD
, 0, 0 },
10918 { MASK_MMX
, CODE_FOR_subv8qi3
, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB
, 0, 0 },
10919 { MASK_MMX
, CODE_FOR_subv4hi3
, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW
, 0, 0 },
10920 { MASK_MMX
, CODE_FOR_subv2si3
, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD
, 0, 0 },
10922 { MASK_MMX
, CODE_FOR_ssaddv8qi3
, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB
, 0, 0 },
10923 { MASK_MMX
, CODE_FOR_ssaddv4hi3
, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW
, 0, 0 },
10924 { MASK_MMX
, CODE_FOR_sssubv8qi3
, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB
, 0, 0 },
10925 { MASK_MMX
, CODE_FOR_sssubv4hi3
, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW
, 0, 0 },
10926 { MASK_MMX
, CODE_FOR_usaddv8qi3
, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB
, 0, 0 },
10927 { MASK_MMX
, CODE_FOR_usaddv4hi3
, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW
, 0, 0 },
10928 { MASK_MMX
, CODE_FOR_ussubv8qi3
, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB
, 0, 0 },
10929 { MASK_MMX
, CODE_FOR_ussubv4hi3
, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW
, 0, 0 },
10931 { MASK_MMX
, CODE_FOR_mulv4hi3
, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW
, 0, 0 },
10932 { MASK_MMX
, CODE_FOR_smulv4hi3_highpart
, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW
, 0, 0 },
10933 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_umulv4hi3_highpart
, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW
, 0, 0 },
10935 { MASK_MMX
, CODE_FOR_mmx_anddi3
, "__builtin_ia32_pand", IX86_BUILTIN_PAND
, 0, 0 },
10936 { MASK_MMX
, CODE_FOR_mmx_nanddi3
, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN
, 0, 0 },
10937 { MASK_MMX
, CODE_FOR_mmx_iordi3
, "__builtin_ia32_por", IX86_BUILTIN_POR
, 0, 0 },
10938 { MASK_MMX
, CODE_FOR_mmx_xordi3
, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR
, 0, 0 },
10940 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_uavgv8qi3
, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB
, 0, 0 },
10941 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_uavgv4hi3
, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW
, 0, 0 },
10943 { MASK_MMX
, CODE_FOR_eqv8qi3
, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB
, 0, 0 },
10944 { MASK_MMX
, CODE_FOR_eqv4hi3
, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW
, 0, 0 },
10945 { MASK_MMX
, CODE_FOR_eqv2si3
, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD
, 0, 0 },
10946 { MASK_MMX
, CODE_FOR_gtv8qi3
, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB
, 0, 0 },
10947 { MASK_MMX
, CODE_FOR_gtv4hi3
, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW
, 0, 0 },
10948 { MASK_MMX
, CODE_FOR_gtv2si3
, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD
, 0, 0 },
10950 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_umaxv8qi3
, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB
, 0, 0 },
10951 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_smaxv4hi3
, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW
, 0, 0 },
10952 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_uminv8qi3
, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB
, 0, 0 },
10953 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_sminv4hi3
, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW
, 0, 0 },
10955 { MASK_MMX
, CODE_FOR_mmx_punpckhbw
, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW
, 0, 0 },
10956 { MASK_MMX
, CODE_FOR_mmx_punpckhwd
, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD
, 0, 0 },
10957 { MASK_MMX
, CODE_FOR_mmx_punpckhdq
, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ
, 0, 0 },
10958 { MASK_MMX
, CODE_FOR_mmx_punpcklbw
, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW
, 0, 0 },
10959 { MASK_MMX
, CODE_FOR_mmx_punpcklwd
, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD
, 0, 0 },
10960 { MASK_MMX
, CODE_FOR_mmx_punpckldq
, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ
, 0, 0 },
10963 { MASK_MMX
, CODE_FOR_mmx_packsswb
, 0, IX86_BUILTIN_PACKSSWB
, 0, 0 },
10964 { MASK_MMX
, CODE_FOR_mmx_packssdw
, 0, IX86_BUILTIN_PACKSSDW
, 0, 0 },
10965 { MASK_MMX
, CODE_FOR_mmx_packuswb
, 0, IX86_BUILTIN_PACKUSWB
, 0, 0 },
10967 { MASK_SSE
, CODE_FOR_cvtpi2ps
, 0, IX86_BUILTIN_CVTPI2PS
, 0, 0 },
10968 { MASK_SSE
, CODE_FOR_cvtsi2ss
, 0, IX86_BUILTIN_CVTSI2SS
, 0, 0 },
10970 { MASK_MMX
, CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLW
, 0, 0 },
10971 { MASK_MMX
, CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLWI
, 0, 0 },
10972 { MASK_MMX
, CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLD
, 0, 0 },
10973 { MASK_MMX
, CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLDI
, 0, 0 },
10974 { MASK_MMX
, CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQ
, 0, 0 },
10975 { MASK_MMX
, CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQI
, 0, 0 },
10977 { MASK_MMX
, CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLW
, 0, 0 },
10978 { MASK_MMX
, CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLWI
, 0, 0 },
10979 { MASK_MMX
, CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLD
, 0, 0 },
10980 { MASK_MMX
, CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLDI
, 0, 0 },
10981 { MASK_MMX
, CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQ
, 0, 0 },
10982 { MASK_MMX
, CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQI
, 0, 0 },
10984 { MASK_MMX
, CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAW
, 0, 0 },
10985 { MASK_MMX
, CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAWI
, 0, 0 },
10986 { MASK_MMX
, CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRAD
, 0, 0 },
10987 { MASK_MMX
, CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRADI
, 0, 0 },
10989 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_psadbw
, 0, IX86_BUILTIN_PSADBW
, 0, 0 },
10990 { MASK_MMX
, CODE_FOR_mmx_pmaddwd
, 0, IX86_BUILTIN_PMADDWD
, 0, 0 }
10994 static const struct builtin_description bdesc_1arg
[] =
10996 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_pmovmskb
, 0, IX86_BUILTIN_PMOVMSKB
, 0, 0 },
10997 { MASK_SSE
, CODE_FOR_sse_movmskps
, 0, IX86_BUILTIN_MOVMSKPS
, 0, 0 },
10999 { MASK_SSE
, CODE_FOR_sqrtv4sf2
, 0, IX86_BUILTIN_SQRTPS
, 0, 0 },
11000 { MASK_SSE
, CODE_FOR_rsqrtv4sf2
, 0, IX86_BUILTIN_RSQRTPS
, 0, 0 },
11001 { MASK_SSE
, CODE_FOR_rcpv4sf2
, 0, IX86_BUILTIN_RCPPS
, 0, 0 },
11003 { MASK_SSE
, CODE_FOR_cvtps2pi
, 0, IX86_BUILTIN_CVTPS2PI
, 0, 0 },
11004 { MASK_SSE
, CODE_FOR_cvtss2si
, 0, IX86_BUILTIN_CVTSS2SI
, 0, 0 },
11005 { MASK_SSE
, CODE_FOR_cvttps2pi
, 0, IX86_BUILTIN_CVTTPS2PI
, 0, 0 },
11006 { MASK_SSE
, CODE_FOR_cvttss2si
, 0, IX86_BUILTIN_CVTTSS2SI
, 0, 0 }
11011 ix86_init_builtins ()
11014 ix86_init_mmx_sse_builtins ();
11017 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
11018 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
11021 ix86_init_mmx_sse_builtins ()
11023 const struct builtin_description
* d
;
11025 tree endlink
= void_list_node
;
11027 tree pchar_type_node
= build_pointer_type (char_type_node
);
11028 tree pfloat_type_node
= build_pointer_type (float_type_node
);
11029 tree pv2si_type_node
= build_pointer_type (V2SI_type_node
);
11030 tree pdi_type_node
= build_pointer_type (long_long_unsigned_type_node
);
11033 tree int_ftype_v4sf_v4sf
11034 = build_function_type (integer_type_node
,
11035 tree_cons (NULL_TREE
, V4SF_type_node
,
11036 tree_cons (NULL_TREE
,
11039 tree v4si_ftype_v4sf_v4sf
11040 = build_function_type (V4SI_type_node
,
11041 tree_cons (NULL_TREE
, V4SF_type_node
,
11042 tree_cons (NULL_TREE
,
11045 /* MMX/SSE/integer conversions. */
11046 tree int_ftype_v4sf
11047 = build_function_type (integer_type_node
,
11048 tree_cons (NULL_TREE
, V4SF_type_node
,
11050 tree int_ftype_v8qi
11051 = build_function_type (integer_type_node
,
11052 tree_cons (NULL_TREE
, V8QI_type_node
,
11054 tree v4sf_ftype_v4sf_int
11055 = build_function_type (V4SF_type_node
,
11056 tree_cons (NULL_TREE
, V4SF_type_node
,
11057 tree_cons (NULL_TREE
, integer_type_node
,
11059 tree v4sf_ftype_v4sf_v2si
11060 = build_function_type (V4SF_type_node
,
11061 tree_cons (NULL_TREE
, V4SF_type_node
,
11062 tree_cons (NULL_TREE
, V2SI_type_node
,
11064 tree int_ftype_v4hi_int
11065 = build_function_type (integer_type_node
,
11066 tree_cons (NULL_TREE
, V4HI_type_node
,
11067 tree_cons (NULL_TREE
, integer_type_node
,
11069 tree v4hi_ftype_v4hi_int_int
11070 = build_function_type (V4HI_type_node
,
11071 tree_cons (NULL_TREE
, V4HI_type_node
,
11072 tree_cons (NULL_TREE
, integer_type_node
,
11073 tree_cons (NULL_TREE
,
11076 /* Miscellaneous. */
11077 tree v8qi_ftype_v4hi_v4hi
11078 = build_function_type (V8QI_type_node
,
11079 tree_cons (NULL_TREE
, V4HI_type_node
,
11080 tree_cons (NULL_TREE
, V4HI_type_node
,
11082 tree v4hi_ftype_v2si_v2si
11083 = build_function_type (V4HI_type_node
,
11084 tree_cons (NULL_TREE
, V2SI_type_node
,
11085 tree_cons (NULL_TREE
, V2SI_type_node
,
11087 tree v4sf_ftype_v4sf_v4sf_int
11088 = build_function_type (V4SF_type_node
,
11089 tree_cons (NULL_TREE
, V4SF_type_node
,
11090 tree_cons (NULL_TREE
, V4SF_type_node
,
11091 tree_cons (NULL_TREE
,
11094 tree v4hi_ftype_v8qi_v8qi
11095 = build_function_type (V4HI_type_node
,
11096 tree_cons (NULL_TREE
, V8QI_type_node
,
11097 tree_cons (NULL_TREE
, V8QI_type_node
,
11099 tree v2si_ftype_v4hi_v4hi
11100 = build_function_type (V2SI_type_node
,
11101 tree_cons (NULL_TREE
, V4HI_type_node
,
11102 tree_cons (NULL_TREE
, V4HI_type_node
,
11104 tree v4hi_ftype_v4hi_int
11105 = build_function_type (V4HI_type_node
,
11106 tree_cons (NULL_TREE
, V4HI_type_node
,
11107 tree_cons (NULL_TREE
, integer_type_node
,
11109 tree v4hi_ftype_v4hi_di
11110 = build_function_type (V4HI_type_node
,
11111 tree_cons (NULL_TREE
, V4HI_type_node
,
11112 tree_cons (NULL_TREE
,
11113 long_long_integer_type_node
,
11115 tree v2si_ftype_v2si_di
11116 = build_function_type (V2SI_type_node
,
11117 tree_cons (NULL_TREE
, V2SI_type_node
,
11118 tree_cons (NULL_TREE
,
11119 long_long_integer_type_node
,
11121 tree void_ftype_void
11122 = build_function_type (void_type_node
, endlink
);
11123 tree void_ftype_unsigned
11124 = build_function_type (void_type_node
,
11125 tree_cons (NULL_TREE
, unsigned_type_node
,
11127 tree unsigned_ftype_void
11128 = build_function_type (unsigned_type_node
, endlink
);
11130 = build_function_type (long_long_unsigned_type_node
, endlink
);
11131 tree v4sf_ftype_void
11132 = build_function_type (V4SF_type_node
, endlink
);
11133 tree v2si_ftype_v4sf
11134 = build_function_type (V2SI_type_node
,
11135 tree_cons (NULL_TREE
, V4SF_type_node
,
11137 /* Loads/stores. */
11138 tree maskmovq_args
= tree_cons (NULL_TREE
, V8QI_type_node
,
11139 tree_cons (NULL_TREE
, V8QI_type_node
,
11140 tree_cons (NULL_TREE
,
11143 tree void_ftype_v8qi_v8qi_pchar
11144 = build_function_type (void_type_node
, maskmovq_args
);
11145 tree v4sf_ftype_pfloat
11146 = build_function_type (V4SF_type_node
,
11147 tree_cons (NULL_TREE
, pfloat_type_node
,
11149 /* @@@ the type is bogus */
11150 tree v4sf_ftype_v4sf_pv2si
11151 = build_function_type (V4SF_type_node
,
11152 tree_cons (NULL_TREE
, V4SF_type_node
,
11153 tree_cons (NULL_TREE
, pv2si_type_node
,
11155 tree void_ftype_pv2si_v4sf
11156 = build_function_type (void_type_node
,
11157 tree_cons (NULL_TREE
, pv2si_type_node
,
11158 tree_cons (NULL_TREE
, V4SF_type_node
,
11160 tree void_ftype_pfloat_v4sf
11161 = build_function_type (void_type_node
,
11162 tree_cons (NULL_TREE
, pfloat_type_node
,
11163 tree_cons (NULL_TREE
, V4SF_type_node
,
11165 tree void_ftype_pdi_di
11166 = build_function_type (void_type_node
,
11167 tree_cons (NULL_TREE
, pdi_type_node
,
11168 tree_cons (NULL_TREE
,
11169 long_long_unsigned_type_node
,
11171 /* Normal vector unops. */
11172 tree v4sf_ftype_v4sf
11173 = build_function_type (V4SF_type_node
,
11174 tree_cons (NULL_TREE
, V4SF_type_node
,
11177 /* Normal vector binops. */
11178 tree v4sf_ftype_v4sf_v4sf
11179 = build_function_type (V4SF_type_node
,
11180 tree_cons (NULL_TREE
, V4SF_type_node
,
11181 tree_cons (NULL_TREE
, V4SF_type_node
,
11183 tree v8qi_ftype_v8qi_v8qi
11184 = build_function_type (V8QI_type_node
,
11185 tree_cons (NULL_TREE
, V8QI_type_node
,
11186 tree_cons (NULL_TREE
, V8QI_type_node
,
11188 tree v4hi_ftype_v4hi_v4hi
11189 = build_function_type (V4HI_type_node
,
11190 tree_cons (NULL_TREE
, V4HI_type_node
,
11191 tree_cons (NULL_TREE
, V4HI_type_node
,
11193 tree v2si_ftype_v2si_v2si
11194 = build_function_type (V2SI_type_node
,
11195 tree_cons (NULL_TREE
, V2SI_type_node
,
11196 tree_cons (NULL_TREE
, V2SI_type_node
,
11198 tree di_ftype_di_di
11199 = build_function_type (long_long_unsigned_type_node
,
11200 tree_cons (NULL_TREE
, long_long_unsigned_type_node
,
11201 tree_cons (NULL_TREE
,
11202 long_long_unsigned_type_node
,
11205 tree v2si_ftype_v2sf
11206 = build_function_type (V2SI_type_node
,
11207 tree_cons (NULL_TREE
, V2SF_type_node
,
11209 tree v2sf_ftype_v2si
11210 = build_function_type (V2SF_type_node
,
11211 tree_cons (NULL_TREE
, V2SI_type_node
,
11213 tree v2si_ftype_v2si
11214 = build_function_type (V2SI_type_node
,
11215 tree_cons (NULL_TREE
, V2SI_type_node
,
11217 tree v2sf_ftype_v2sf
11218 = build_function_type (V2SF_type_node
,
11219 tree_cons (NULL_TREE
, V2SF_type_node
,
11221 tree v2sf_ftype_v2sf_v2sf
11222 = build_function_type (V2SF_type_node
,
11223 tree_cons (NULL_TREE
, V2SF_type_node
,
11224 tree_cons (NULL_TREE
,
11227 tree v2si_ftype_v2sf_v2sf
11228 = build_function_type (V2SI_type_node
,
11229 tree_cons (NULL_TREE
, V2SF_type_node
,
11230 tree_cons (NULL_TREE
,
11234 /* Add all builtins that are more or less simple operations on two
11236 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
11238 /* Use one of the operands; the target can have a different mode for
11239 mask-generating compares. */
11240 enum machine_mode mode
;
11245 mode
= insn_data
[d
->icode
].operand
[1].mode
;
11250 type
= v4sf_ftype_v4sf_v4sf
;
11253 type
= v8qi_ftype_v8qi_v8qi
;
11256 type
= v4hi_ftype_v4hi_v4hi
;
11259 type
= v2si_ftype_v2si_v2si
;
11262 type
= di_ftype_di_di
;
11269 /* Override for comparisons. */
11270 if (d
->icode
== CODE_FOR_maskcmpv4sf3
11271 || d
->icode
== CODE_FOR_maskncmpv4sf3
11272 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
11273 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
)
11274 type
= v4si_ftype_v4sf_v4sf
;
11276 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
11279 /* Add the remaining MMX insns with somewhat more complicated types. */
11280 def_builtin (MASK_MMX
, "__builtin_ia32_mmx_zero", di_ftype_void
, IX86_BUILTIN_MMX_ZERO
);
11281 def_builtin (MASK_MMX
, "__builtin_ia32_emms", void_ftype_void
, IX86_BUILTIN_EMMS
);
11282 def_builtin (MASK_MMX
, "__builtin_ia32_ldmxcsr", void_ftype_unsigned
, IX86_BUILTIN_LDMXCSR
);
11283 def_builtin (MASK_MMX
, "__builtin_ia32_stmxcsr", unsigned_ftype_void
, IX86_BUILTIN_STMXCSR
);
11284 def_builtin (MASK_MMX
, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSLLW
);
11285 def_builtin (MASK_MMX
, "__builtin_ia32_pslld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSLLD
);
11286 def_builtin (MASK_MMX
, "__builtin_ia32_psllq", di_ftype_di_di
, IX86_BUILTIN_PSLLQ
);
11288 def_builtin (MASK_MMX
, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRLW
);
11289 def_builtin (MASK_MMX
, "__builtin_ia32_psrld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRLD
);
11290 def_builtin (MASK_MMX
, "__builtin_ia32_psrlq", di_ftype_di_di
, IX86_BUILTIN_PSRLQ
);
11292 def_builtin (MASK_MMX
, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRAW
);
11293 def_builtin (MASK_MMX
, "__builtin_ia32_psrad", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRAD
);
11295 def_builtin (MASK_MMX
, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int
, IX86_BUILTIN_PSHUFW
);
11296 def_builtin (MASK_MMX
, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi
, IX86_BUILTIN_PMADDWD
);
11298 /* comi/ucomi insns. */
11299 for (i
= 0, d
= bdesc_comi
; i
< ARRAY_SIZE (bdesc_comi
); i
++, d
++)
11300 def_builtin (d
->mask
, d
->name
, int_ftype_v4sf_v4sf
, d
->code
);
11302 def_builtin (MASK_MMX
, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKSSWB
);
11303 def_builtin (MASK_MMX
, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si
, IX86_BUILTIN_PACKSSDW
);
11304 def_builtin (MASK_MMX
, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKUSWB
);
11306 def_builtin (MASK_SSE
, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si
, IX86_BUILTIN_CVTPI2PS
);
11307 def_builtin (MASK_SSE
, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTPS2PI
);
11308 def_builtin (MASK_SSE
, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int
, IX86_BUILTIN_CVTSI2SS
);
11309 def_builtin (MASK_SSE
, "__builtin_ia32_cvtss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTSS2SI
);
11310 def_builtin (MASK_SSE
, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTTPS2PI
);
11311 def_builtin (MASK_SSE
, "__builtin_ia32_cvttss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTTSS2SI
);
11313 def_builtin (MASK_SSE
, "__builtin_ia32_andps", v4sf_ftype_v4sf_v4sf
, IX86_BUILTIN_ANDPS
);
11314 def_builtin (MASK_SSE
, "__builtin_ia32_andnps", v4sf_ftype_v4sf_v4sf
, IX86_BUILTIN_ANDNPS
);
11315 def_builtin (MASK_SSE
, "__builtin_ia32_orps", v4sf_ftype_v4sf_v4sf
, IX86_BUILTIN_ORPS
);
11316 def_builtin (MASK_SSE
, "__builtin_ia32_xorps", v4sf_ftype_v4sf_v4sf
, IX86_BUILTIN_XORPS
);
11318 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pextrw", int_ftype_v4hi_int
, IX86_BUILTIN_PEXTRW
);
11319 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pinsrw", v4hi_ftype_v4hi_int_int
, IX86_BUILTIN_PINSRW
);
11321 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar
, IX86_BUILTIN_MASKMOVQ
);
11323 def_builtin (MASK_SSE
, "__builtin_ia32_loadaps", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADAPS
);
11324 def_builtin (MASK_SSE
, "__builtin_ia32_loadups", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADUPS
);
11325 def_builtin (MASK_SSE
, "__builtin_ia32_loadss", v4sf_ftype_pfloat
, IX86_BUILTIN_LOADSS
);
11326 def_builtin (MASK_SSE
, "__builtin_ia32_storeaps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREAPS
);
11327 def_builtin (MASK_SSE
, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREUPS
);
11328 def_builtin (MASK_SSE
, "__builtin_ia32_storess", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STORESS
);
11330 def_builtin (MASK_SSE
, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADHPS
);
11331 def_builtin (MASK_SSE
, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADLPS
);
11332 def_builtin (MASK_SSE
, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf
, IX86_BUILTIN_STOREHPS
);
11333 def_builtin (MASK_SSE
, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf
, IX86_BUILTIN_STORELPS
);
11335 def_builtin (MASK_SSE
, "__builtin_ia32_movmskps", int_ftype_v4sf
, IX86_BUILTIN_MOVMSKPS
);
11336 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pmovmskb", int_ftype_v8qi
, IX86_BUILTIN_PMOVMSKB
);
11337 def_builtin (MASK_SSE
, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_MOVNTPS
);
11338 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_movntq", void_ftype_pdi_di
, IX86_BUILTIN_MOVNTQ
);
11340 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_sfence", void_ftype_void
, IX86_BUILTIN_SFENCE
);
11342 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_psadbw", v4hi_ftype_v8qi_v8qi
, IX86_BUILTIN_PSADBW
);
11344 def_builtin (MASK_SSE
, "__builtin_ia32_rcpps", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPPS
);
11345 def_builtin (MASK_SSE
, "__builtin_ia32_rcpss", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPSS
);
11346 def_builtin (MASK_SSE
, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTPS
);
11347 def_builtin (MASK_SSE
, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTSS
);
11348 def_builtin (MASK_SSE
, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTPS
);
11349 def_builtin (MASK_SSE
, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTSS
);
11351 def_builtin (MASK_SSE
, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int
, IX86_BUILTIN_SHUFPS
);
11353 /* Original 3DNow! */
11354 def_builtin (MASK_3DNOW
, "__builtin_ia32_femms", void_ftype_void
, IX86_BUILTIN_FEMMS
);
11355 def_builtin (MASK_3DNOW
, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi
, IX86_BUILTIN_PAVGUSB
);
11356 def_builtin (MASK_3DNOW
, "__builtin_ia32_pf2id", v2si_ftype_v2sf
, IX86_BUILTIN_PF2ID
);
11357 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFACC
);
11358 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFADD
);
11359 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPEQ
);
11360 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPGE
);
11361 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPGT
);
11362 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMAX
);
11363 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMIN
);
11364 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMUL
);
11365 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf
, IX86_BUILTIN_PFRCP
);
11366 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRCPIT1
);
11367 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRCPIT2
);
11368 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf
, IX86_BUILTIN_PFRSQRT
);
11369 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRSQIT1
);
11370 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFSUB
);
11371 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFSUBR
);
11372 def_builtin (MASK_3DNOW
, "__builtin_ia32_pi2fd", v2sf_ftype_v2si
, IX86_BUILTIN_PI2FD
);
11373 def_builtin (MASK_3DNOW
, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi
, IX86_BUILTIN_PMULHRW
);
11375 /* 3DNow! extension as used in the Athlon CPU. */
11376 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pf2iw", v2si_ftype_v2sf
, IX86_BUILTIN_PF2IW
);
11377 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFNACC
);
11378 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFPNACC
);
11379 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pi2fw", v2sf_ftype_v2si
, IX86_BUILTIN_PI2FW
);
11380 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf
, IX86_BUILTIN_PSWAPDSF
);
11381 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pswapdsi", v2si_ftype_v2si
, IX86_BUILTIN_PSWAPDSI
);
11383 def_builtin (MASK_SSE
, "__builtin_ia32_setzerops", v4sf_ftype_void
, IX86_BUILTIN_SSE_ZERO
);
11386 /* Errors in the source file can cause expand_expr to return const0_rtx
11387 where we expect a vector. To avoid crashing, use one of the vector
11388 clear instructions. */
11390 safe_vector_operand (x
, mode
)
11392 enum machine_mode mode
;
11394 if (x
!= const0_rtx
)
11396 x
= gen_reg_rtx (mode
);
11398 if (VALID_MMX_REG_MODE (mode
) || VALID_MMX_REG_MODE_3DNOW (mode
))
11399 emit_insn (gen_mmx_clrdi (mode
== DImode
? x
11400 : gen_rtx_SUBREG (DImode
, x
, 0)));
11402 emit_insn (gen_sse_clrv4sf (mode
== V4SFmode
? x
11403 : gen_rtx_SUBREG (V4SFmode
, x
, 0)));
11407 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
11410 ix86_expand_binop_builtin (icode
, arglist
, target
)
11411 enum insn_code icode
;
11416 tree arg0
= TREE_VALUE (arglist
);
11417 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11418 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11419 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11420 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11421 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11422 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11424 if (VECTOR_MODE_P (mode0
))
11425 op0
= safe_vector_operand (op0
, mode0
);
11426 if (VECTOR_MODE_P (mode1
))
11427 op1
= safe_vector_operand (op1
, mode1
);
11430 || GET_MODE (target
) != tmode
11431 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11432 target
= gen_reg_rtx (tmode
);
11434 /* In case the insn wants input operands in modes different from
11435 the result, abort. */
11436 if (GET_MODE (op0
) != mode0
|| GET_MODE (op1
) != mode1
)
11439 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11440 op0
= copy_to_mode_reg (mode0
, op0
);
11441 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11442 op1
= copy_to_mode_reg (mode1
, op1
);
11444 /* In the commutative cases, both op0 and op1 are nonimmediate_operand,
11445 yet one of the two must not be a memory. This is normally enforced
11446 by expanders, but we didn't bother to create one here. */
11447 if (GET_CODE (op0
) == MEM
&& GET_CODE (op1
) == MEM
)
11448 op0
= copy_to_mode_reg (mode0
, op0
);
11450 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11457 /* In type_for_mode we restrict the ability to create TImode types
11458 to hosts with 64-bit H_W_I. So we've defined the SSE logicals
11459 to have a V4SFmode signature. Convert them in-place to TImode. */
11462 ix86_expand_timode_binop_builtin (icode
, arglist
, target
)
11463 enum insn_code icode
;
11468 tree arg0
= TREE_VALUE (arglist
);
11469 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11470 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11471 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11473 op0
= gen_lowpart (TImode
, op0
);
11474 op1
= gen_lowpart (TImode
, op1
);
11475 target
= gen_reg_rtx (TImode
);
11477 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, TImode
))
11478 op0
= copy_to_mode_reg (TImode
, op0
);
11479 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, TImode
))
11480 op1
= copy_to_mode_reg (TImode
, op1
);
11482 /* In the commutative cases, both op0 and op1 are nonimmediate_operand,
11483 yet one of the two must not be a memory. This is normally enforced
11484 by expanders, but we didn't bother to create one here. */
11485 if (GET_CODE (op0
) == MEM
&& GET_CODE (op1
) == MEM
)
11486 op0
= copy_to_mode_reg (TImode
, op0
);
11488 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11493 return gen_lowpart (V4SFmode
, target
);
11496 /* Subroutine of ix86_expand_builtin to take care of stores. */
11499 ix86_expand_store_builtin (icode
, arglist
)
11500 enum insn_code icode
;
11504 tree arg0
= TREE_VALUE (arglist
);
11505 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11506 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11507 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11508 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11509 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11511 if (VECTOR_MODE_P (mode1
))
11512 op1
= safe_vector_operand (op1
, mode1
);
11514 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11516 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11517 op1
= copy_to_mode_reg (mode1
, op1
);
11519 pat
= GEN_FCN (icode
) (op0
, op1
);
11525 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
11528 ix86_expand_unop_builtin (icode
, arglist
, target
, do_load
)
11529 enum insn_code icode
;
11535 tree arg0
= TREE_VALUE (arglist
);
11536 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11537 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11538 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11541 || GET_MODE (target
) != tmode
11542 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11543 target
= gen_reg_rtx (tmode
);
11545 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11548 if (VECTOR_MODE_P (mode0
))
11549 op0
= safe_vector_operand (op0
, mode0
);
11551 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11552 op0
= copy_to_mode_reg (mode0
, op0
);
11555 pat
= GEN_FCN (icode
) (target
, op0
);
11562 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
11563 sqrtss, rsqrtss, rcpss. */
11566 ix86_expand_unop1_builtin (icode
, arglist
, target
)
11567 enum insn_code icode
;
11572 tree arg0
= TREE_VALUE (arglist
);
11573 rtx op1
, op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11574 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11575 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11578 || GET_MODE (target
) != tmode
11579 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11580 target
= gen_reg_rtx (tmode
);
11582 if (VECTOR_MODE_P (mode0
))
11583 op0
= safe_vector_operand (op0
, mode0
);
11585 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11586 op0
= copy_to_mode_reg (mode0
, op0
);
11589 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode0
))
11590 op1
= copy_to_mode_reg (mode0
, op1
);
11592 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11599 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
11602 ix86_expand_sse_compare (d
, arglist
, target
)
11603 const struct builtin_description
*d
;
11608 tree arg0
= TREE_VALUE (arglist
);
11609 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11610 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11611 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11613 enum machine_mode tmode
= insn_data
[d
->icode
].operand
[0].mode
;
11614 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[1].mode
;
11615 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[2].mode
;
11616 enum rtx_code comparison
= d
->comparison
;
11618 if (VECTOR_MODE_P (mode0
))
11619 op0
= safe_vector_operand (op0
, mode0
);
11620 if (VECTOR_MODE_P (mode1
))
11621 op1
= safe_vector_operand (op1
, mode1
);
11623 /* Swap operands if we have a comparison that isn't available in
11627 rtx tmp
= gen_reg_rtx (mode1
);
11628 emit_move_insn (tmp
, op1
);
11634 || GET_MODE (target
) != tmode
11635 || ! (*insn_data
[d
->icode
].operand
[0].predicate
) (target
, tmode
))
11636 target
= gen_reg_rtx (tmode
);
11638 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op0
, mode0
))
11639 op0
= copy_to_mode_reg (mode0
, op0
);
11640 if (! (*insn_data
[d
->icode
].operand
[2].predicate
) (op1
, mode1
))
11641 op1
= copy_to_mode_reg (mode1
, op1
);
11643 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
11644 pat
= GEN_FCN (d
->icode
) (target
, op0
, op1
, op2
);
11651 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
11654 ix86_expand_sse_comi (d
, arglist
, target
)
11655 const struct builtin_description
*d
;
11660 tree arg0
= TREE_VALUE (arglist
);
11661 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11662 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11663 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11665 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[0].mode
;
11666 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[1].mode
;
11667 enum rtx_code comparison
= d
->comparison
;
11669 if (VECTOR_MODE_P (mode0
))
11670 op0
= safe_vector_operand (op0
, mode0
);
11671 if (VECTOR_MODE_P (mode1
))
11672 op1
= safe_vector_operand (op1
, mode1
);
11674 /* Swap operands if we have a comparison that isn't available in
11683 target
= gen_reg_rtx (SImode
);
11684 emit_move_insn (target
, const0_rtx
);
11685 target
= gen_rtx_SUBREG (QImode
, target
, 0);
11687 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
11688 op0
= copy_to_mode_reg (mode0
, op0
);
11689 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
11690 op1
= copy_to_mode_reg (mode1
, op1
);
11692 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
11693 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
11697 emit_insn (gen_rtx_SET (VOIDmode
,
11698 gen_rtx_STRICT_LOW_PART (VOIDmode
, target
),
11699 gen_rtx_fmt_ee (comparison
, QImode
,
11700 gen_rtx_REG (CCmode
, FLAGS_REG
),
11703 return SUBREG_REG (target
);
11706 /* Expand an expression EXP that calls a built-in function,
11707 with result going to TARGET if that's convenient
11708 (and in mode MODE if that's convenient).
11709 SUBTARGET may be used as the target for computing one of EXP's operands.
11710 IGNORE is nonzero if the value is to be ignored. */
11713 ix86_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
11716 rtx subtarget ATTRIBUTE_UNUSED
;
11717 enum machine_mode mode ATTRIBUTE_UNUSED
;
11718 int ignore ATTRIBUTE_UNUSED
;
11720 const struct builtin_description
*d
;
11722 enum insn_code icode
;
11723 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
11724 tree arglist
= TREE_OPERAND (exp
, 1);
11725 tree arg0
, arg1
, arg2
;
11726 rtx op0
, op1
, op2
, pat
;
11727 enum machine_mode tmode
, mode0
, mode1
, mode2
;
11728 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
11732 case IX86_BUILTIN_EMMS
:
11733 emit_insn (gen_emms ());
11736 case IX86_BUILTIN_SFENCE
:
11737 emit_insn (gen_sfence ());
11740 case IX86_BUILTIN_PEXTRW
:
11741 icode
= CODE_FOR_mmx_pextrw
;
11742 arg0
= TREE_VALUE (arglist
);
11743 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11744 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11745 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11746 tmode
= insn_data
[icode
].operand
[0].mode
;
11747 mode0
= insn_data
[icode
].operand
[1].mode
;
11748 mode1
= insn_data
[icode
].operand
[2].mode
;
11750 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11751 op0
= copy_to_mode_reg (mode0
, op0
);
11752 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11754 /* @@@ better error message */
11755 error ("selector must be an immediate");
11756 return gen_reg_rtx (tmode
);
11759 || GET_MODE (target
) != tmode
11760 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11761 target
= gen_reg_rtx (tmode
);
11762 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11768 case IX86_BUILTIN_PINSRW
:
11769 icode
= CODE_FOR_mmx_pinsrw
;
11770 arg0
= TREE_VALUE (arglist
);
11771 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11772 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11773 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11774 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11775 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11776 tmode
= insn_data
[icode
].operand
[0].mode
;
11777 mode0
= insn_data
[icode
].operand
[1].mode
;
11778 mode1
= insn_data
[icode
].operand
[2].mode
;
11779 mode2
= insn_data
[icode
].operand
[3].mode
;
11781 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11782 op0
= copy_to_mode_reg (mode0
, op0
);
11783 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11784 op1
= copy_to_mode_reg (mode1
, op1
);
11785 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11787 /* @@@ better error message */
11788 error ("selector must be an immediate");
11792 || GET_MODE (target
) != tmode
11793 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11794 target
= gen_reg_rtx (tmode
);
11795 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11801 case IX86_BUILTIN_MASKMOVQ
:
11802 icode
= TARGET_64BIT
? CODE_FOR_mmx_maskmovq_rex
: CODE_FOR_mmx_maskmovq
;
11803 /* Note the arg order is different from the operand order. */
11804 arg1
= TREE_VALUE (arglist
);
11805 arg2
= TREE_VALUE (TREE_CHAIN (arglist
));
11806 arg0
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11807 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11808 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11809 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11810 mode0
= insn_data
[icode
].operand
[0].mode
;
11811 mode1
= insn_data
[icode
].operand
[1].mode
;
11812 mode2
= insn_data
[icode
].operand
[2].mode
;
11814 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
11815 op0
= copy_to_mode_reg (mode0
, op0
);
11816 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
11817 op1
= copy_to_mode_reg (mode1
, op1
);
11818 if (! (*insn_data
[icode
].operand
[2].predicate
) (op2
, mode2
))
11819 op2
= copy_to_mode_reg (mode2
, op2
);
11820 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
11826 case IX86_BUILTIN_SQRTSS
:
11827 return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv4sf2
, arglist
, target
);
11828 case IX86_BUILTIN_RSQRTSS
:
11829 return ix86_expand_unop1_builtin (CODE_FOR_vmrsqrtv4sf2
, arglist
, target
);
11830 case IX86_BUILTIN_RCPSS
:
11831 return ix86_expand_unop1_builtin (CODE_FOR_vmrcpv4sf2
, arglist
, target
);
11833 case IX86_BUILTIN_ANDPS
:
11834 return ix86_expand_timode_binop_builtin (CODE_FOR_sse_andti3
,
11836 case IX86_BUILTIN_ANDNPS
:
11837 return ix86_expand_timode_binop_builtin (CODE_FOR_sse_nandti3
,
11839 case IX86_BUILTIN_ORPS
:
11840 return ix86_expand_timode_binop_builtin (CODE_FOR_sse_iorti3
,
11842 case IX86_BUILTIN_XORPS
:
11843 return ix86_expand_timode_binop_builtin (CODE_FOR_sse_xorti3
,
11846 case IX86_BUILTIN_LOADAPS
:
11847 return ix86_expand_unop_builtin (CODE_FOR_sse_movaps
, arglist
, target
, 1);
11849 case IX86_BUILTIN_LOADUPS
:
11850 return ix86_expand_unop_builtin (CODE_FOR_sse_movups
, arglist
, target
, 1);
11852 case IX86_BUILTIN_STOREAPS
:
11853 return ix86_expand_store_builtin (CODE_FOR_sse_movaps
, arglist
);
11854 case IX86_BUILTIN_STOREUPS
:
11855 return ix86_expand_store_builtin (CODE_FOR_sse_movups
, arglist
);
11857 case IX86_BUILTIN_LOADSS
:
11858 return ix86_expand_unop_builtin (CODE_FOR_sse_loadss
, arglist
, target
, 1);
11860 case IX86_BUILTIN_STORESS
:
11861 return ix86_expand_store_builtin (CODE_FOR_sse_storess
, arglist
);
11863 case IX86_BUILTIN_LOADHPS
:
11864 case IX86_BUILTIN_LOADLPS
:
11865 icode
= (fcode
== IX86_BUILTIN_LOADHPS
11866 ? CODE_FOR_sse_movhps
: CODE_FOR_sse_movlps
);
11867 arg0
= TREE_VALUE (arglist
);
11868 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11869 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11870 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11871 tmode
= insn_data
[icode
].operand
[0].mode
;
11872 mode0
= insn_data
[icode
].operand
[1].mode
;
11873 mode1
= insn_data
[icode
].operand
[2].mode
;
11875 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11876 op0
= copy_to_mode_reg (mode0
, op0
);
11877 op1
= gen_rtx_MEM (mode1
, copy_to_mode_reg (Pmode
, op1
));
11879 || GET_MODE (target
) != tmode
11880 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11881 target
= gen_reg_rtx (tmode
);
11882 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11888 case IX86_BUILTIN_STOREHPS
:
11889 case IX86_BUILTIN_STORELPS
:
11890 icode
= (fcode
== IX86_BUILTIN_STOREHPS
11891 ? CODE_FOR_sse_movhps
: CODE_FOR_sse_movlps
);
11892 arg0
= TREE_VALUE (arglist
);
11893 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11894 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11895 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11896 mode0
= insn_data
[icode
].operand
[1].mode
;
11897 mode1
= insn_data
[icode
].operand
[2].mode
;
11899 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
11900 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11901 op1
= copy_to_mode_reg (mode1
, op1
);
11903 pat
= GEN_FCN (icode
) (op0
, op0
, op1
);
11909 case IX86_BUILTIN_MOVNTPS
:
11910 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf
, arglist
);
11911 case IX86_BUILTIN_MOVNTQ
:
11912 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi
, arglist
);
11914 case IX86_BUILTIN_LDMXCSR
:
11915 op0
= expand_expr (TREE_VALUE (arglist
), NULL_RTX
, VOIDmode
, 0);
11916 target
= assign_386_stack_local (SImode
, 0);
11917 emit_move_insn (target
, op0
);
11918 emit_insn (gen_ldmxcsr (target
));
11921 case IX86_BUILTIN_STMXCSR
:
11922 target
= assign_386_stack_local (SImode
, 0);
11923 emit_insn (gen_stmxcsr (target
));
11924 return copy_to_mode_reg (SImode
, target
);
11926 case IX86_BUILTIN_SHUFPS
:
11927 icode
= CODE_FOR_sse_shufps
;
11928 arg0
= TREE_VALUE (arglist
);
11929 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11930 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
11931 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11932 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11933 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
11934 tmode
= insn_data
[icode
].operand
[0].mode
;
11935 mode0
= insn_data
[icode
].operand
[1].mode
;
11936 mode1
= insn_data
[icode
].operand
[2].mode
;
11937 mode2
= insn_data
[icode
].operand
[3].mode
;
11939 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11940 op0
= copy_to_mode_reg (mode0
, op0
);
11941 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11942 op1
= copy_to_mode_reg (mode1
, op1
);
11943 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
11945 /* @@@ better error message */
11946 error ("mask must be an immediate");
11947 return gen_reg_rtx (tmode
);
11950 || GET_MODE (target
) != tmode
11951 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11952 target
= gen_reg_rtx (tmode
);
11953 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
11959 case IX86_BUILTIN_PSHUFW
:
11960 icode
= CODE_FOR_mmx_pshufw
;
11961 arg0
= TREE_VALUE (arglist
);
11962 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
11963 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
11964 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
11965 tmode
= insn_data
[icode
].operand
[0].mode
;
11966 mode1
= insn_data
[icode
].operand
[1].mode
;
11967 mode2
= insn_data
[icode
].operand
[2].mode
;
11969 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
11970 op0
= copy_to_mode_reg (mode1
, op0
);
11971 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
11973 /* @@@ better error message */
11974 error ("mask must be an immediate");
11978 || GET_MODE (target
) != tmode
11979 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11980 target
= gen_reg_rtx (tmode
);
11981 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11987 case IX86_BUILTIN_FEMMS
:
11988 emit_insn (gen_femms ());
11991 case IX86_BUILTIN_PAVGUSB
:
11992 return ix86_expand_binop_builtin (CODE_FOR_pavgusb
, arglist
, target
);
11994 case IX86_BUILTIN_PF2ID
:
11995 return ix86_expand_unop_builtin (CODE_FOR_pf2id
, arglist
, target
, 0);
11997 case IX86_BUILTIN_PFACC
:
11998 return ix86_expand_binop_builtin (CODE_FOR_pfacc
, arglist
, target
);
12000 case IX86_BUILTIN_PFADD
:
12001 return ix86_expand_binop_builtin (CODE_FOR_addv2sf3
, arglist
, target
);
12003 case IX86_BUILTIN_PFCMPEQ
:
12004 return ix86_expand_binop_builtin (CODE_FOR_eqv2sf3
, arglist
, target
);
12006 case IX86_BUILTIN_PFCMPGE
:
12007 return ix86_expand_binop_builtin (CODE_FOR_gev2sf3
, arglist
, target
);
12009 case IX86_BUILTIN_PFCMPGT
:
12010 return ix86_expand_binop_builtin (CODE_FOR_gtv2sf3
, arglist
, target
);
12012 case IX86_BUILTIN_PFMAX
:
12013 return ix86_expand_binop_builtin (CODE_FOR_pfmaxv2sf3
, arglist
, target
);
12015 case IX86_BUILTIN_PFMIN
:
12016 return ix86_expand_binop_builtin (CODE_FOR_pfminv2sf3
, arglist
, target
);
12018 case IX86_BUILTIN_PFMUL
:
12019 return ix86_expand_binop_builtin (CODE_FOR_mulv2sf3
, arglist
, target
);
12021 case IX86_BUILTIN_PFRCP
:
12022 return ix86_expand_unop_builtin (CODE_FOR_pfrcpv2sf2
, arglist
, target
, 0);
12024 case IX86_BUILTIN_PFRCPIT1
:
12025 return ix86_expand_binop_builtin (CODE_FOR_pfrcpit1v2sf3
, arglist
, target
);
12027 case IX86_BUILTIN_PFRCPIT2
:
12028 return ix86_expand_binop_builtin (CODE_FOR_pfrcpit2v2sf3
, arglist
, target
);
12030 case IX86_BUILTIN_PFRSQIT1
:
12031 return ix86_expand_binop_builtin (CODE_FOR_pfrsqit1v2sf3
, arglist
, target
);
12033 case IX86_BUILTIN_PFRSQRT
:
12034 return ix86_expand_unop_builtin (CODE_FOR_pfrsqrtv2sf2
, arglist
, target
, 0);
12036 case IX86_BUILTIN_PFSUB
:
12037 return ix86_expand_binop_builtin (CODE_FOR_subv2sf3
, arglist
, target
);
12039 case IX86_BUILTIN_PFSUBR
:
12040 return ix86_expand_binop_builtin (CODE_FOR_subrv2sf3
, arglist
, target
);
12042 case IX86_BUILTIN_PI2FD
:
12043 return ix86_expand_unop_builtin (CODE_FOR_floatv2si2
, arglist
, target
, 0);
12045 case IX86_BUILTIN_PMULHRW
:
12046 return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3
, arglist
, target
);
12048 case IX86_BUILTIN_PF2IW
:
12049 return ix86_expand_unop_builtin (CODE_FOR_pf2iw
, arglist
, target
, 0);
12051 case IX86_BUILTIN_PFNACC
:
12052 return ix86_expand_binop_builtin (CODE_FOR_pfnacc
, arglist
, target
);
12054 case IX86_BUILTIN_PFPNACC
:
12055 return ix86_expand_binop_builtin (CODE_FOR_pfpnacc
, arglist
, target
);
12057 case IX86_BUILTIN_PI2FW
:
12058 return ix86_expand_unop_builtin (CODE_FOR_pi2fw
, arglist
, target
, 0);
12060 case IX86_BUILTIN_PSWAPDSI
:
12061 return ix86_expand_unop_builtin (CODE_FOR_pswapdv2si2
, arglist
, target
, 0);
12063 case IX86_BUILTIN_PSWAPDSF
:
12064 return ix86_expand_unop_builtin (CODE_FOR_pswapdv2sf2
, arglist
, target
, 0);
12066 case IX86_BUILTIN_SSE_ZERO
:
12067 target
= gen_reg_rtx (V4SFmode
);
12068 emit_insn (gen_sse_clrv4sf (target
));
12071 case IX86_BUILTIN_MMX_ZERO
:
12072 target
= gen_reg_rtx (DImode
);
12073 emit_insn (gen_mmx_clrdi (target
));
12080 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12081 if (d
->code
== fcode
)
12083 /* Compares are treated specially. */
12084 if (d
->icode
== CODE_FOR_maskcmpv4sf3
12085 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
12086 || d
->icode
== CODE_FOR_maskncmpv4sf3
12087 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
)
12088 return ix86_expand_sse_compare (d
, arglist
, target
);
12090 return ix86_expand_binop_builtin (d
->icode
, arglist
, target
);
12093 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
12094 if (d
->code
== fcode
)
12095 return ix86_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
12097 for (i
= 0, d
= bdesc_comi
; i
< ARRAY_SIZE (bdesc_comi
); i
++, d
++)
12098 if (d
->code
== fcode
)
12099 return ix86_expand_sse_comi (d
, arglist
, target
);
12101 /* @@@ Should really do something sensible here. */
12105 /* Store OPERAND to the memory after reload is completed. This means
12106 that we can't easily use assign_stack_local. */
12108 ix86_force_to_memory (mode
, operand
)
12109 enum machine_mode mode
;
12113 if (!reload_completed
)
12115 if (TARGET_64BIT
&& TARGET_RED_ZONE
)
12117 result
= gen_rtx_MEM (mode
,
12118 gen_rtx_PLUS (Pmode
,
12120 GEN_INT (-RED_ZONE_SIZE
)));
12121 emit_move_insn (result
, operand
);
12123 else if (TARGET_64BIT
&& !TARGET_RED_ZONE
)
12129 operand
= gen_lowpart (DImode
, operand
);
12133 gen_rtx_SET (VOIDmode
,
12134 gen_rtx_MEM (DImode
,
12135 gen_rtx_PRE_DEC (DImode
,
12136 stack_pointer_rtx
)),
12142 result
= gen_rtx_MEM (mode
, stack_pointer_rtx
);
12151 split_di (&operand
, 1, operands
, operands
+ 1);
12153 gen_rtx_SET (VOIDmode
,
12154 gen_rtx_MEM (SImode
,
12155 gen_rtx_PRE_DEC (Pmode
,
12156 stack_pointer_rtx
)),
12159 gen_rtx_SET (VOIDmode
,
12160 gen_rtx_MEM (SImode
,
12161 gen_rtx_PRE_DEC (Pmode
,
12162 stack_pointer_rtx
)),
12167 /* It is better to store HImodes as SImodes. */
12168 if (!TARGET_PARTIAL_REG_STALL
)
12169 operand
= gen_lowpart (SImode
, operand
);
12173 gen_rtx_SET (VOIDmode
,
12174 gen_rtx_MEM (GET_MODE (operand
),
12175 gen_rtx_PRE_DEC (SImode
,
12176 stack_pointer_rtx
)),
12182 result
= gen_rtx_MEM (mode
, stack_pointer_rtx
);
12187 /* Free operand from the memory. */
12189 ix86_free_from_memory (mode
)
12190 enum machine_mode mode
;
12192 if (!TARGET_64BIT
|| !TARGET_RED_ZONE
)
12196 if (mode
== DImode
|| TARGET_64BIT
)
12198 else if (mode
== HImode
&& TARGET_PARTIAL_REG_STALL
)
12202 /* Use LEA to deallocate stack space. In peephole2 it will be converted
12203 to pop or add instruction if registers are available. */
12204 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
12205 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
12210 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
12211 QImode must go into class Q_REGS.
12212 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
12213 movdf to do mem-to-mem moves through integer regs. */
12215 ix86_preferred_reload_class (x
, class)
12217 enum reg_class
class;
12219 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != VOIDmode
)
12221 /* SSE can't load any constant directly yet. */
12222 if (SSE_CLASS_P (class))
12224 /* Floats can load 0 and 1. */
12225 if (MAYBE_FLOAT_CLASS_P (class) && standard_80387_constant_p (x
))
12227 /* Limit class to non-SSE. Use GENERAL_REGS if possible. */
12228 if (MAYBE_SSE_CLASS_P (class))
12229 return (reg_class_subset_p (class, GENERAL_REGS
)
12230 ? GENERAL_REGS
: FLOAT_REGS
);
12234 /* General regs can load everything. */
12235 if (reg_class_subset_p (class, GENERAL_REGS
))
12236 return GENERAL_REGS
;
12237 /* In case we haven't resolved FLOAT or SSE yet, give up. */
12238 if (MAYBE_FLOAT_CLASS_P (class) || MAYBE_SSE_CLASS_P (class))
12241 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x
))
12243 if (GET_MODE (x
) == QImode
&& ! reg_class_subset_p (class, Q_REGS
))
12248 /* If we are copying between general and FP registers, we need a memory
12249 location. The same is true for SSE and MMX registers.
12251 The macro can't work reliably when one of the CLASSES is class containing
12252 registers from multiple units (SSE, MMX, integer). We avoid this by never
12253 combining those units in single alternative in the machine description.
12254 Ensure that this constraint holds to avoid unexpected surprises.
12256 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
12257 enforce these sanity checks. */
12259 ix86_secondary_memory_needed (class1
, class2
, mode
, strict
)
12260 enum reg_class class1
, class2
;
12261 enum machine_mode mode
;
12264 if (MAYBE_FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class1
)
12265 || MAYBE_FLOAT_CLASS_P (class2
) != FLOAT_CLASS_P (class2
)
12266 || MAYBE_SSE_CLASS_P (class1
) != SSE_CLASS_P (class1
)
12267 || MAYBE_SSE_CLASS_P (class2
) != SSE_CLASS_P (class2
)
12268 || MAYBE_MMX_CLASS_P (class1
) != MMX_CLASS_P (class1
)
12269 || MAYBE_MMX_CLASS_P (class2
) != MMX_CLASS_P (class2
))
12276 return (FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class2
)
12277 || (SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
)
12278 && (mode
) != SImode
)
12279 || (MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
)
12280 && (mode
) != SImode
));
12282 /* Return the cost of moving data from a register in class CLASS1 to
12283 one in class CLASS2.
12285 It is not required that the cost always equal 2 when FROM is the same as TO;
12286 on some machines it is expensive to move between registers if they are not
12287 general registers. */
12289 ix86_register_move_cost (mode
, class1
, class2
)
12290 enum machine_mode mode
;
12291 enum reg_class class1
, class2
;
12293 /* In case we require secondary memory, compute cost of the store followed
12294 by load. In case of copying from general_purpose_register we may emit
12295 multiple stores followed by single load causing memory size mismatch
12296 stall. Count this as arbitarily high cost of 20. */
12297 if (ix86_secondary_memory_needed (class1
, class2
, mode
, 0))
12300 if (CLASS_MAX_NREGS (class1
, mode
) > CLASS_MAX_NREGS (class2
, mode
))
12302 return (MEMORY_MOVE_COST (mode
, class1
, 0)
12303 + MEMORY_MOVE_COST (mode
, class2
, 1) + add_cost
);
12305 /* Moves between SSE/MMX and integer unit are expensive. */
12306 if (MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
)
12307 || SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
))
12308 return ix86_cost
->mmxsse_to_integer
;
12309 if (MAYBE_FLOAT_CLASS_P (class1
))
12310 return ix86_cost
->fp_move
;
12311 if (MAYBE_SSE_CLASS_P (class1
))
12312 return ix86_cost
->sse_move
;
12313 if (MAYBE_MMX_CLASS_P (class1
))
12314 return ix86_cost
->mmx_move
;
12318 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
12320 ix86_hard_regno_mode_ok (regno
, mode
)
12322 enum machine_mode mode
;
12324 /* Flags and only flags can only hold CCmode values. */
12325 if (CC_REGNO_P (regno
))
12326 return GET_MODE_CLASS (mode
) == MODE_CC
;
12327 if (GET_MODE_CLASS (mode
) == MODE_CC
12328 || GET_MODE_CLASS (mode
) == MODE_RANDOM
12329 || GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
12331 if (FP_REGNO_P (regno
))
12332 return VALID_FP_MODE_P (mode
);
12333 if (SSE_REGNO_P (regno
))
12334 return VALID_SSE_REG_MODE (mode
);
12335 if (MMX_REGNO_P (regno
))
12336 return VALID_MMX_REG_MODE (mode
) || VALID_MMX_REG_MODE_3DNOW (mode
);
12337 /* We handle both integer and floats in the general purpose registers.
12338 In future we should be able to handle vector modes as well. */
12339 if (!VALID_INT_MODE_P (mode
) && !VALID_FP_MODE_P (mode
))
12341 /* Take care for QImode values - they can be in non-QI regs, but then
12342 they do cause partial register stalls. */
12343 if (regno
< 4 || mode
!= QImode
|| TARGET_64BIT
)
12345 return reload_in_progress
|| reload_completed
|| !TARGET_PARTIAL_REG_STALL
;
12348 /* Return the cost of moving data of mode M between a
12349 register and memory. A value of 2 is the default; this cost is
12350 relative to those in `REGISTER_MOVE_COST'.
12352 If moving between registers and memory is more expensive than
12353 between two registers, you should define this macro to express the
12356 Model also increased moving costs of QImode registers in non
12360 ix86_memory_move_cost (mode
, class, in
)
12361 enum machine_mode mode
;
12362 enum reg_class
class;
12365 if (FLOAT_CLASS_P (class))
12383 return in
? ix86_cost
->fp_load
[index
] : ix86_cost
->fp_store
[index
];
12385 if (SSE_CLASS_P (class))
12388 switch (GET_MODE_SIZE (mode
))
12402 return in
? ix86_cost
->sse_load
[index
] : ix86_cost
->sse_store
[index
];
12404 if (MMX_CLASS_P (class))
12407 switch (GET_MODE_SIZE (mode
))
12418 return in
? ix86_cost
->mmx_load
[index
] : ix86_cost
->mmx_store
[index
];
12420 switch (GET_MODE_SIZE (mode
))
12424 return (Q_CLASS_P (class) ? ix86_cost
->int_load
[0]
12425 : ix86_cost
->movzbl_load
);
12427 return (Q_CLASS_P (class) ? ix86_cost
->int_store
[0]
12428 : ix86_cost
->int_store
[0] + 4);
12431 return in
? ix86_cost
->int_load
[1] : ix86_cost
->int_store
[1];
12433 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
12434 if (mode
== TFmode
)
12436 return ((in
? ix86_cost
->int_load
[2] : ix86_cost
->int_store
[2])
12437 * (int) GET_MODE_SIZE (mode
) / 4);
12441 #ifdef DO_GLOBAL_CTORS_BODY
12443 ix86_svr3_asm_out_constructor (symbol
, priority
)
12445 int priority ATTRIBUTE_UNUSED
;
12448 fputs ("\tpushl $", asm_out_file
);
12449 assemble_name (asm_out_file
, XSTR (symbol
, 0));
12450 fputc ('\n', asm_out_file
);
12454 /* Order the registers for register allocator. */
12457 x86_order_regs_for_local_alloc ()
12462 /* First allocate the local general purpose registers. */
12463 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12464 if (GENERAL_REGNO_P (i
) && call_used_regs
[i
])
12465 reg_alloc_order
[pos
++] = i
;
12467 /* Global general purpose registers. */
12468 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12469 if (GENERAL_REGNO_P (i
) && !call_used_regs
[i
])
12470 reg_alloc_order
[pos
++] = i
;
12472 /* x87 registers come first in case we are doing FP math
12474 if (!TARGET_SSE_MATH
)
12475 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
12476 reg_alloc_order
[pos
++] = i
;
12478 /* SSE registers. */
12479 for (i
= FIRST_SSE_REG
; i
<= LAST_SSE_REG
; i
++)
12480 reg_alloc_order
[pos
++] = i
;
12481 for (i
= FIRST_REX_SSE_REG
; i
<= LAST_REX_SSE_REG
; i
++)
12482 reg_alloc_order
[pos
++] = i
;
12484 /* x87 registerts. */
12485 if (TARGET_SSE_MATH
)
12486 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
12487 reg_alloc_order
[pos
++] = i
;
12489 for (i
= FIRST_MMX_REG
; i
<= LAST_MMX_REG
; i
++)
12490 reg_alloc_order
[pos
++] = i
;
12492 /* Initialize the rest of array as we do not allocate some registers
12494 while (pos
< FIRST_PSEUDO_REGISTER
)
12495 reg_alloc_order
[pos
++] = 0;