1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
52 #ifndef CHECK_STACK_LIMIT
53 #define CHECK_STACK_LIMIT (-1)
56 /* Return index of given mode in mult and division cost tables. */
57 #define MODE_INDEX(mode) \
58 ((mode) == QImode ? 0 \
59 : (mode) == HImode ? 1 \
60 : (mode) == SImode ? 2 \
61 : (mode) == DImode ? 3 \
64 /* Processor costs (relative to an add) */
66 struct processor_costs size_cost
= { /* costs for tunning for size */
67 2, /* cost of an add instruction */
68 3, /* cost of a lea instruction */
69 2, /* variable shift costs */
70 3, /* constant shift costs */
71 {3, 3, 3, 3, 5}, /* cost of starting a multiply */
72 0, /* cost of multiply per each bit set */
73 {3, 3, 3, 3, 5}, /* cost of a divide/mod */
74 3, /* cost of movsx */
75 3, /* cost of movzx */
78 2, /* cost for loading QImode using movzbl */
79 {2, 2, 2}, /* cost of loading integer registers
80 in QImode, HImode and SImode.
81 Relative to reg-reg move (2). */
82 {2, 2, 2}, /* cost of storing integer registers */
83 2, /* cost of reg,reg fld/fst */
84 {2, 2, 2}, /* cost of loading fp registers
85 in SFmode, DFmode and XFmode */
86 {2, 2, 2}, /* cost of loading integer registers */
87 3, /* cost of moving MMX register */
88 {3, 3}, /* cost of loading MMX registers
89 in SImode and DImode */
90 {3, 3}, /* cost of storing MMX registers
91 in SImode and DImode */
92 3, /* cost of moving SSE register */
93 {3, 3, 3}, /* cost of loading SSE registers
94 in SImode, DImode and TImode */
95 {3, 3, 3}, /* cost of storing SSE registers
96 in SImode, DImode and TImode */
97 3, /* MMX or SSE register to integer */
98 0, /* size of prefetch block */
99 0, /* number of parallel prefetches */
101 2, /* cost of FADD and FSUB insns. */
102 2, /* cost of FMUL instruction. */
103 2, /* cost of FDIV instruction. */
104 2, /* cost of FABS instruction. */
105 2, /* cost of FCHS instruction. */
106 2, /* cost of FSQRT instruction. */
109 /* Processor costs (relative to an add) */
111 struct processor_costs i386_cost
= { /* 386 specific costs */
112 1, /* cost of an add instruction */
113 1, /* cost of a lea instruction */
114 3, /* variable shift costs */
115 2, /* constant shift costs */
116 {6, 6, 6, 6, 6}, /* cost of starting a multiply */
117 1, /* cost of multiply per each bit set */
118 {23, 23, 23, 23, 23}, /* cost of a divide/mod */
119 3, /* cost of movsx */
120 2, /* cost of movzx */
121 15, /* "large" insn */
123 4, /* cost for loading QImode using movzbl */
124 {2, 4, 2}, /* cost of loading integer registers
125 in QImode, HImode and SImode.
126 Relative to reg-reg move (2). */
127 {2, 4, 2}, /* cost of storing integer registers */
128 2, /* cost of reg,reg fld/fst */
129 {8, 8, 8}, /* cost of loading fp registers
130 in SFmode, DFmode and XFmode */
131 {8, 8, 8}, /* cost of loading integer registers */
132 2, /* cost of moving MMX register */
133 {4, 8}, /* cost of loading MMX registers
134 in SImode and DImode */
135 {4, 8}, /* cost of storing MMX registers
136 in SImode and DImode */
137 2, /* cost of moving SSE register */
138 {4, 8, 16}, /* cost of loading SSE registers
139 in SImode, DImode and TImode */
140 {4, 8, 16}, /* cost of storing SSE registers
141 in SImode, DImode and TImode */
142 3, /* MMX or SSE register to integer */
143 0, /* size of prefetch block */
144 0, /* number of parallel prefetches */
146 23, /* cost of FADD and FSUB insns. */
147 27, /* cost of FMUL instruction. */
148 88, /* cost of FDIV instruction. */
149 22, /* cost of FABS instruction. */
150 24, /* cost of FCHS instruction. */
151 122, /* cost of FSQRT instruction. */
155 struct processor_costs i486_cost
= { /* 486 specific costs */
156 1, /* cost of an add instruction */
157 1, /* cost of a lea instruction */
158 3, /* variable shift costs */
159 2, /* constant shift costs */
160 {12, 12, 12, 12, 12}, /* cost of starting a multiply */
161 1, /* cost of multiply per each bit set */
162 {40, 40, 40, 40, 40}, /* cost of a divide/mod */
163 3, /* cost of movsx */
164 2, /* cost of movzx */
165 15, /* "large" insn */
167 4, /* cost for loading QImode using movzbl */
168 {2, 4, 2}, /* cost of loading integer registers
169 in QImode, HImode and SImode.
170 Relative to reg-reg move (2). */
171 {2, 4, 2}, /* cost of storing integer registers */
172 2, /* cost of reg,reg fld/fst */
173 {8, 8, 8}, /* cost of loading fp registers
174 in SFmode, DFmode and XFmode */
175 {8, 8, 8}, /* cost of loading integer registers */
176 2, /* cost of moving MMX register */
177 {4, 8}, /* cost of loading MMX registers
178 in SImode and DImode */
179 {4, 8}, /* cost of storing MMX registers
180 in SImode and DImode */
181 2, /* cost of moving SSE register */
182 {4, 8, 16}, /* cost of loading SSE registers
183 in SImode, DImode and TImode */
184 {4, 8, 16}, /* cost of storing SSE registers
185 in SImode, DImode and TImode */
186 3, /* MMX or SSE register to integer */
187 0, /* size of prefetch block */
188 0, /* number of parallel prefetches */
190 8, /* cost of FADD and FSUB insns. */
191 16, /* cost of FMUL instruction. */
192 73, /* cost of FDIV instruction. */
193 3, /* cost of FABS instruction. */
194 3, /* cost of FCHS instruction. */
195 83, /* cost of FSQRT instruction. */
199 struct processor_costs pentium_cost
= {
200 1, /* cost of an add instruction */
201 1, /* cost of a lea instruction */
202 4, /* variable shift costs */
203 1, /* constant shift costs */
204 {11, 11, 11, 11, 11}, /* cost of starting a multiply */
205 0, /* cost of multiply per each bit set */
206 {25, 25, 25, 25, 25}, /* cost of a divide/mod */
207 3, /* cost of movsx */
208 2, /* cost of movzx */
209 8, /* "large" insn */
211 6, /* cost for loading QImode using movzbl */
212 {2, 4, 2}, /* cost of loading integer registers
213 in QImode, HImode and SImode.
214 Relative to reg-reg move (2). */
215 {2, 4, 2}, /* cost of storing integer registers */
216 2, /* cost of reg,reg fld/fst */
217 {2, 2, 6}, /* cost of loading fp registers
218 in SFmode, DFmode and XFmode */
219 {4, 4, 6}, /* cost of loading integer registers */
220 8, /* cost of moving MMX register */
221 {8, 8}, /* cost of loading MMX registers
222 in SImode and DImode */
223 {8, 8}, /* cost of storing MMX registers
224 in SImode and DImode */
225 2, /* cost of moving SSE register */
226 {4, 8, 16}, /* cost of loading SSE registers
227 in SImode, DImode and TImode */
228 {4, 8, 16}, /* cost of storing SSE registers
229 in SImode, DImode and TImode */
230 3, /* MMX or SSE register to integer */
231 0, /* size of prefetch block */
232 0, /* number of parallel prefetches */
234 3, /* cost of FADD and FSUB insns. */
235 3, /* cost of FMUL instruction. */
236 39, /* cost of FDIV instruction. */
237 1, /* cost of FABS instruction. */
238 1, /* cost of FCHS instruction. */
239 70, /* cost of FSQRT instruction. */
243 struct processor_costs pentiumpro_cost
= {
244 1, /* cost of an add instruction */
245 1, /* cost of a lea instruction */
246 1, /* variable shift costs */
247 1, /* constant shift costs */
248 {4, 4, 4, 4, 4}, /* cost of starting a multiply */
249 0, /* cost of multiply per each bit set */
250 {17, 17, 17, 17, 17}, /* cost of a divide/mod */
251 1, /* cost of movsx */
252 1, /* cost of movzx */
253 8, /* "large" insn */
255 2, /* cost for loading QImode using movzbl */
256 {4, 4, 4}, /* cost of loading integer registers
257 in QImode, HImode and SImode.
258 Relative to reg-reg move (2). */
259 {2, 2, 2}, /* cost of storing integer registers */
260 2, /* cost of reg,reg fld/fst */
261 {2, 2, 6}, /* cost of loading fp registers
262 in SFmode, DFmode and XFmode */
263 {4, 4, 6}, /* cost of loading integer registers */
264 2, /* cost of moving MMX register */
265 {2, 2}, /* cost of loading MMX registers
266 in SImode and DImode */
267 {2, 2}, /* cost of storing MMX registers
268 in SImode and DImode */
269 2, /* cost of moving SSE register */
270 {2, 2, 8}, /* cost of loading SSE registers
271 in SImode, DImode and TImode */
272 {2, 2, 8}, /* cost of storing SSE registers
273 in SImode, DImode and TImode */
274 3, /* MMX or SSE register to integer */
275 32, /* size of prefetch block */
276 6, /* number of parallel prefetches */
278 3, /* cost of FADD and FSUB insns. */
279 5, /* cost of FMUL instruction. */
280 56, /* cost of FDIV instruction. */
281 2, /* cost of FABS instruction. */
282 2, /* cost of FCHS instruction. */
283 56, /* cost of FSQRT instruction. */
287 struct processor_costs k6_cost
= {
288 1, /* cost of an add instruction */
289 2, /* cost of a lea instruction */
290 1, /* variable shift costs */
291 1, /* constant shift costs */
292 {3, 3, 3, 3, 3}, /* cost of starting a multiply */
293 0, /* cost of multiply per each bit set */
294 {18, 18, 18, 18, 18}, /* cost of a divide/mod */
295 2, /* cost of movsx */
296 2, /* cost of movzx */
297 8, /* "large" insn */
299 3, /* cost for loading QImode using movzbl */
300 {4, 5, 4}, /* cost of loading integer registers
301 in QImode, HImode and SImode.
302 Relative to reg-reg move (2). */
303 {2, 3, 2}, /* cost of storing integer registers */
304 4, /* cost of reg,reg fld/fst */
305 {6, 6, 6}, /* cost of loading fp registers
306 in SFmode, DFmode and XFmode */
307 {4, 4, 4}, /* cost of loading integer registers */
308 2, /* cost of moving MMX register */
309 {2, 2}, /* cost of loading MMX registers
310 in SImode and DImode */
311 {2, 2}, /* cost of storing MMX registers
312 in SImode and DImode */
313 2, /* cost of moving SSE register */
314 {2, 2, 8}, /* cost of loading SSE registers
315 in SImode, DImode and TImode */
316 {2, 2, 8}, /* cost of storing SSE registers
317 in SImode, DImode and TImode */
318 6, /* MMX or SSE register to integer */
319 32, /* size of prefetch block */
320 1, /* number of parallel prefetches */
322 2, /* cost of FADD and FSUB insns. */
323 2, /* cost of FMUL instruction. */
324 56, /* cost of FDIV instruction. */
325 2, /* cost of FABS instruction. */
326 2, /* cost of FCHS instruction. */
327 56, /* cost of FSQRT instruction. */
331 struct processor_costs athlon_cost
= {
332 1, /* cost of an add instruction */
333 2, /* cost of a lea instruction */
334 1, /* variable shift costs */
335 1, /* constant shift costs */
336 {5, 5, 5, 5, 5}, /* cost of starting a multiply */
337 0, /* cost of multiply per each bit set */
338 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
339 1, /* cost of movsx */
340 1, /* cost of movzx */
341 8, /* "large" insn */
343 4, /* cost for loading QImode using movzbl */
344 {3, 4, 3}, /* cost of loading integer registers
345 in QImode, HImode and SImode.
346 Relative to reg-reg move (2). */
347 {3, 4, 3}, /* cost of storing integer registers */
348 4, /* cost of reg,reg fld/fst */
349 {4, 4, 12}, /* cost of loading fp registers
350 in SFmode, DFmode and XFmode */
351 {6, 6, 8}, /* cost of loading integer registers */
352 2, /* cost of moving MMX register */
353 {4, 4}, /* cost of loading MMX registers
354 in SImode and DImode */
355 {4, 4}, /* cost of storing MMX registers
356 in SImode and DImode */
357 2, /* cost of moving SSE register */
358 {4, 4, 6}, /* cost of loading SSE registers
359 in SImode, DImode and TImode */
360 {4, 4, 5}, /* cost of storing SSE registers
361 in SImode, DImode and TImode */
362 5, /* MMX or SSE register to integer */
363 64, /* size of prefetch block */
364 6, /* number of parallel prefetches */
366 4, /* cost of FADD and FSUB insns. */
367 4, /* cost of FMUL instruction. */
368 24, /* cost of FDIV instruction. */
369 2, /* cost of FABS instruction. */
370 2, /* cost of FCHS instruction. */
371 35, /* cost of FSQRT instruction. */
375 struct processor_costs k8_cost
= {
376 1, /* cost of an add instruction */
377 2, /* cost of a lea instruction */
378 1, /* variable shift costs */
379 1, /* constant shift costs */
380 {3, 4, 3, 4, 5}, /* cost of starting a multiply */
381 0, /* cost of multiply per each bit set */
382 {18, 26, 42, 74, 74}, /* cost of a divide/mod */
383 1, /* cost of movsx */
384 1, /* cost of movzx */
385 8, /* "large" insn */
387 4, /* cost for loading QImode using movzbl */
388 {3, 4, 3}, /* cost of loading integer registers
389 in QImode, HImode and SImode.
390 Relative to reg-reg move (2). */
391 {3, 4, 3}, /* cost of storing integer registers */
392 4, /* cost of reg,reg fld/fst */
393 {4, 4, 12}, /* cost of loading fp registers
394 in SFmode, DFmode and XFmode */
395 {6, 6, 8}, /* cost of loading integer registers */
396 2, /* cost of moving MMX register */
397 {3, 3}, /* cost of loading MMX registers
398 in SImode and DImode */
399 {4, 4}, /* cost of storing MMX registers
400 in SImode and DImode */
401 2, /* cost of moving SSE register */
402 {4, 3, 6}, /* cost of loading SSE registers
403 in SImode, DImode and TImode */
404 {4, 4, 5}, /* cost of storing SSE registers
405 in SImode, DImode and TImode */
406 5, /* MMX or SSE register to integer */
407 64, /* size of prefetch block */
408 6, /* number of parallel prefetches */
410 4, /* cost of FADD and FSUB insns. */
411 4, /* cost of FMUL instruction. */
412 19, /* cost of FDIV instruction. */
413 2, /* cost of FABS instruction. */
414 2, /* cost of FCHS instruction. */
415 35, /* cost of FSQRT instruction. */
419 struct processor_costs pentium4_cost
= {
420 1, /* cost of an add instruction */
421 3, /* cost of a lea instruction */
422 4, /* variable shift costs */
423 4, /* constant shift costs */
424 {15, 15, 15, 15, 15}, /* cost of starting a multiply */
425 0, /* cost of multiply per each bit set */
426 {56, 56, 56, 56, 56}, /* cost of a divide/mod */
427 1, /* cost of movsx */
428 1, /* cost of movzx */
429 16, /* "large" insn */
431 2, /* cost for loading QImode using movzbl */
432 {4, 5, 4}, /* cost of loading integer registers
433 in QImode, HImode and SImode.
434 Relative to reg-reg move (2). */
435 {2, 3, 2}, /* cost of storing integer registers */
436 2, /* cost of reg,reg fld/fst */
437 {2, 2, 6}, /* cost of loading fp registers
438 in SFmode, DFmode and XFmode */
439 {4, 4, 6}, /* cost of loading integer registers */
440 2, /* cost of moving MMX register */
441 {2, 2}, /* cost of loading MMX registers
442 in SImode and DImode */
443 {2, 2}, /* cost of storing MMX registers
444 in SImode and DImode */
445 12, /* cost of moving SSE register */
446 {12, 12, 12}, /* cost of loading SSE registers
447 in SImode, DImode and TImode */
448 {2, 2, 8}, /* cost of storing SSE registers
449 in SImode, DImode and TImode */
450 10, /* MMX or SSE register to integer */
451 64, /* size of prefetch block */
452 6, /* number of parallel prefetches */
454 5, /* cost of FADD and FSUB insns. */
455 7, /* cost of FMUL instruction. */
456 43, /* cost of FDIV instruction. */
457 2, /* cost of FABS instruction. */
458 2, /* cost of FCHS instruction. */
459 43, /* cost of FSQRT instruction. */
463 struct processor_costs nocona_cost
= {
464 1, /* cost of an add instruction */
465 1, /* cost of a lea instruction */
466 1, /* variable shift costs */
467 1, /* constant shift costs */
468 {10, 10, 10, 10, 10}, /* cost of starting a multiply */
469 0, /* cost of multiply per each bit set */
470 {66, 66, 66, 66, 66}, /* cost of a divide/mod */
471 1, /* cost of movsx */
472 1, /* cost of movzx */
473 16, /* "large" insn */
475 4, /* cost for loading QImode using movzbl */
476 {4, 4, 4}, /* cost of loading integer registers
477 in QImode, HImode and SImode.
478 Relative to reg-reg move (2). */
479 {4, 4, 4}, /* cost of storing integer registers */
480 3, /* cost of reg,reg fld/fst */
481 {12, 12, 12}, /* cost of loading fp registers
482 in SFmode, DFmode and XFmode */
483 {4, 4, 4}, /* cost of loading integer registers */
484 6, /* cost of moving MMX register */
485 {12, 12}, /* cost of loading MMX registers
486 in SImode and DImode */
487 {12, 12}, /* cost of storing MMX registers
488 in SImode and DImode */
489 6, /* cost of moving SSE register */
490 {12, 12, 12}, /* cost of loading SSE registers
491 in SImode, DImode and TImode */
492 {12, 12, 12}, /* cost of storing SSE registers
493 in SImode, DImode and TImode */
494 8, /* MMX or SSE register to integer */
495 128, /* size of prefetch block */
496 8, /* number of parallel prefetches */
498 6, /* cost of FADD and FSUB insns. */
499 8, /* cost of FMUL instruction. */
500 40, /* cost of FDIV instruction. */
501 3, /* cost of FABS instruction. */
502 3, /* cost of FCHS instruction. */
503 44, /* cost of FSQRT instruction. */
506 const struct processor_costs
*ix86_cost
= &pentium_cost
;
508 /* Processor feature/optimization bitmasks. */
509 #define m_386 (1<<PROCESSOR_I386)
510 #define m_486 (1<<PROCESSOR_I486)
511 #define m_PENT (1<<PROCESSOR_PENTIUM)
512 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
513 #define m_K6 (1<<PROCESSOR_K6)
514 #define m_ATHLON (1<<PROCESSOR_ATHLON)
515 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
516 #define m_K8 (1<<PROCESSOR_K8)
517 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
518 #define m_NOCONA (1<<PROCESSOR_NOCONA)
520 const int x86_use_leave
= m_386
| m_K6
| m_ATHLON_K8
;
521 const int x86_push_memory
= m_386
| m_K6
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
522 const int x86_zero_extend_with_and
= m_486
| m_PENT
;
523 const int x86_movx
= m_ATHLON_K8
| m_PPRO
| m_PENT4
| m_NOCONA
/* m_386 | m_K6 */;
524 const int x86_double_with_add
= ~m_386
;
525 const int x86_use_bit_test
= m_386
;
526 const int x86_unroll_strlen
= m_486
| m_PENT
| m_PPRO
| m_ATHLON_K8
| m_K6
;
527 const int x86_cmove
= m_PPRO
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
528 const int x86_3dnow_a
= m_ATHLON_K8
;
529 const int x86_deep_branch
= m_PPRO
| m_K6
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
530 /* Branch hints were put in P4 based on simulation result. But
531 after P4 was made, no performance benefit was observed with
532 branch hints. It also increases the code size. As the result,
533 icc never generates branch hints. */
534 const int x86_branch_hints
= 0;
535 const int x86_use_sahf
= m_PPRO
| m_K6
| m_PENT4
| m_NOCONA
;
536 const int x86_partial_reg_stall
= m_PPRO
;
537 const int x86_use_loop
= m_K6
;
538 const int x86_use_fiop
= ~(m_PPRO
| m_ATHLON_K8
| m_PENT
);
539 const int x86_use_mov0
= m_K6
;
540 const int x86_use_cltd
= ~(m_PENT
| m_K6
);
541 const int x86_read_modify_write
= ~m_PENT
;
542 const int x86_read_modify
= ~(m_PENT
| m_PPRO
);
543 const int x86_split_long_moves
= m_PPRO
;
544 const int x86_promote_QImode
= m_K6
| m_PENT
| m_386
| m_486
| m_ATHLON_K8
;
545 const int x86_fast_prefix
= ~(m_PENT
| m_486
| m_386
);
546 const int x86_single_stringop
= m_386
| m_PENT4
| m_NOCONA
;
547 const int x86_qimode_math
= ~(0);
548 const int x86_promote_qi_regs
= 0;
549 const int x86_himode_math
= ~(m_PPRO
);
550 const int x86_promote_hi_regs
= m_PPRO
;
551 const int x86_sub_esp_4
= m_ATHLON_K8
| m_PPRO
| m_PENT4
| m_NOCONA
;
552 const int x86_sub_esp_8
= m_ATHLON_K8
| m_PPRO
| m_386
| m_486
| m_PENT4
| m_NOCONA
;
553 const int x86_add_esp_4
= m_ATHLON_K8
| m_K6
| m_PENT4
| m_NOCONA
;
554 const int x86_add_esp_8
= m_ATHLON_K8
| m_PPRO
| m_K6
| m_386
| m_486
| m_PENT4
| m_NOCONA
;
555 const int x86_integer_DFmode_moves
= ~(m_ATHLON_K8
| m_PENT4
| m_NOCONA
| m_PPRO
);
556 const int x86_partial_reg_dependency
= m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
557 const int x86_memory_mismatch_stall
= m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
558 const int x86_accumulate_outgoing_args
= m_ATHLON_K8
| m_PENT4
| m_NOCONA
| m_PPRO
;
559 const int x86_prologue_using_move
= m_ATHLON_K8
| m_PPRO
;
560 const int x86_epilogue_using_move
= m_ATHLON_K8
| m_PPRO
;
561 const int x86_decompose_lea
= m_PENT4
| m_NOCONA
;
562 const int x86_shift1
= ~m_486
;
563 const int x86_arch_always_fancy_math_387
= m_PENT
| m_PPRO
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
564 const int x86_sse_partial_reg_dependency
= m_PENT4
| m_NOCONA
| m_PPRO
;
565 /* Set for machines where the type and dependencies are resolved on SSE register
566 parts instead of whole registers, so we may maintain just lower part of
567 scalar values in proper format leaving the upper part undefined. */
568 const int x86_sse_partial_regs
= m_ATHLON_K8
;
569 /* Athlon optimizes partial-register FPS special case, thus avoiding the
570 need for extra instructions beforehand */
571 const int x86_sse_partial_regs_for_cvtsd2ss
= 0;
572 const int x86_sse_typeless_stores
= m_ATHLON_K8
;
573 const int x86_sse_load0_by_pxor
= m_PPRO
| m_PENT4
| m_NOCONA
;
574 const int x86_use_ffreep
= m_ATHLON_K8
;
575 const int x86_rep_movl_optimal
= m_386
| m_PENT
| m_PPRO
| m_K6
;
576 const int x86_inter_unit_moves
= ~(m_ATHLON_K8
);
577 const int x86_ext_80387_constants
= m_K6
| m_ATHLON
| m_PENT4
| m_NOCONA
| m_PPRO
;
578 /* Some CPU cores are not able to predict more than 4 branch instructions in
579 the 16 byte window. */
580 const int x86_four_jump_limit
= m_PPRO
| m_ATHLON_K8
| m_PENT4
| m_NOCONA
;
581 const int x86_schedule
= m_PPRO
| m_ATHLON_K8
| m_K6
| m_PENT
;
583 /* In case the average insn count for single function invocation is
584 lower than this constant, emit fast (but longer) prologue and
586 #define FAST_PROLOGUE_INSN_COUNT 20
588 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
589 static const char *const qi_reg_name
[] = QI_REGISTER_NAMES
;
590 static const char *const qi_high_reg_name
[] = QI_HIGH_REGISTER_NAMES
;
591 static const char *const hi_reg_name
[] = HI_REGISTER_NAMES
;
593 /* Array of the smallest class containing reg number REGNO, indexed by
594 REGNO. Used by REGNO_REG_CLASS in i386.h. */
596 enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
] =
599 AREG
, DREG
, CREG
, BREG
,
601 SIREG
, DIREG
, NON_Q_REGS
, NON_Q_REGS
,
603 FP_TOP_REG
, FP_SECOND_REG
, FLOAT_REGS
, FLOAT_REGS
,
604 FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
, FLOAT_REGS
,
607 /* flags, fpsr, dirflag, frame */
608 NO_REGS
, NO_REGS
, NO_REGS
, NON_Q_REGS
,
609 SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
,
611 MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
, MMX_REGS
,
613 NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
,
614 NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
, NON_Q_REGS
,
615 SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
, SSE_REGS
,
619 /* The "default" register map used in 32bit mode. */
621 int const dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
623 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
624 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
625 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
626 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
627 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
628 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
629 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
632 static int const x86_64_int_parameter_registers
[6] =
634 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
635 FIRST_REX_INT_REG
/*R8 */, FIRST_REX_INT_REG
+ 1 /*R9 */
638 static int const x86_64_int_return_registers
[4] =
640 0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
643 /* The "default" register map used in 64bit mode. */
644 int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
] =
646 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
647 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
648 -1, -1, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
649 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
650 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
651 8,9,10,11,12,13,14,15, /* extended integer registers */
652 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
655 /* Define the register numbers to be used in Dwarf debugging information.
656 The SVR4 reference port C compiler uses the following register numbers
657 in its Dwarf output code:
658 0 for %eax (gcc regno = 0)
659 1 for %ecx (gcc regno = 2)
660 2 for %edx (gcc regno = 1)
661 3 for %ebx (gcc regno = 3)
662 4 for %esp (gcc regno = 7)
663 5 for %ebp (gcc regno = 6)
664 6 for %esi (gcc regno = 4)
665 7 for %edi (gcc regno = 5)
666 The following three DWARF register numbers are never generated by
667 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
668 believes these numbers have these meanings.
669 8 for %eip (no gcc equivalent)
670 9 for %eflags (gcc regno = 17)
671 10 for %trapno (no gcc equivalent)
672 It is not at all clear how we should number the FP stack registers
673 for the x86 architecture. If the version of SDB on x86/svr4 were
674 a bit less brain dead with respect to floating-point then we would
675 have a precedent to follow with respect to DWARF register numbers
676 for x86 FP registers, but the SDB on x86/svr4 is so completely
677 broken with respect to FP registers that it is hardly worth thinking
678 of it as something to strive for compatibility with.
679 The version of x86/svr4 SDB I have at the moment does (partially)
680 seem to believe that DWARF register number 11 is associated with
681 the x86 register %st(0), but that's about all. Higher DWARF
682 register numbers don't seem to be associated with anything in
683 particular, and even for DWARF regno 11, SDB only seems to under-
684 stand that it should say that a variable lives in %st(0) (when
685 asked via an `=' command) if we said it was in DWARF regno 11,
686 but SDB still prints garbage when asked for the value of the
687 variable in question (via a `/' command).
688 (Also note that the labels SDB prints for various FP stack regs
689 when doing an `x' command are all wrong.)
690 Note that these problems generally don't affect the native SVR4
691 C compiler because it doesn't allow the use of -O with -g and
692 because when it is *not* optimizing, it allocates a memory
693 location for each floating-point variable, and the memory
694 location is what gets described in the DWARF AT_location
695 attribute for the variable in question.
696 Regardless of the severe mental illness of the x86/svr4 SDB, we
697 do something sensible here and we use the following DWARF
698 register numbers. Note that these are all stack-top-relative
700 11 for %st(0) (gcc regno = 8)
701 12 for %st(1) (gcc regno = 9)
702 13 for %st(2) (gcc regno = 10)
703 14 for %st(3) (gcc regno = 11)
704 15 for %st(4) (gcc regno = 12)
705 16 for %st(5) (gcc regno = 13)
706 17 for %st(6) (gcc regno = 14)
707 18 for %st(7) (gcc regno = 15)
709 int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
] =
711 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
712 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
713 -1, 9, -1, -1, -1, /* arg, flags, fpsr, dir, frame */
714 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
715 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
716 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
717 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
720 /* Test and compare insns in i386.md store the information needed to
721 generate branch and scc insns here. */
723 rtx ix86_compare_op0
= NULL_RTX
;
724 rtx ix86_compare_op1
= NULL_RTX
;
726 #define MAX_386_STACK_LOCALS 3
727 /* Size of the register save area. */
728 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
730 /* Define the structure for the machine field in struct function. */
732 struct stack_local_entry
GTY(())
737 struct stack_local_entry
*next
;
740 /* Structure describing stack frame layout.
741 Stack grows downward:
747 saved frame pointer if frame_pointer_needed
748 <- HARD_FRAME_POINTER
754 > to_allocate <- FRAME_POINTER
766 int outgoing_arguments_size
;
769 HOST_WIDE_INT to_allocate
;
770 /* The offsets relative to ARG_POINTER. */
771 HOST_WIDE_INT frame_pointer_offset
;
772 HOST_WIDE_INT hard_frame_pointer_offset
;
773 HOST_WIDE_INT stack_pointer_offset
;
775 /* When save_regs_using_mov is set, emit prologue using
776 move instead of push instructions. */
777 bool save_regs_using_mov
;
780 /* Used to enable/disable debugging features. */
781 const char *ix86_debug_arg_string
, *ix86_debug_addr_string
;
782 /* Code model option as passed by user. */
783 const char *ix86_cmodel_string
;
785 enum cmodel ix86_cmodel
;
787 const char *ix86_asm_string
;
788 enum asm_dialect ix86_asm_dialect
= ASM_ATT
;
790 const char *ix86_tls_dialect_string
;
791 enum tls_dialect ix86_tls_dialect
= TLS_DIALECT_GNU
;
793 /* Which unit we are generating floating point math for. */
794 enum fpmath_unit ix86_fpmath
;
796 /* Which cpu are we scheduling for. */
797 enum processor_type ix86_tune
;
798 /* Which instruction set architecture to use. */
799 enum processor_type ix86_arch
;
801 /* Strings to hold which cpu and instruction set architecture to use. */
802 const char *ix86_tune_string
; /* for -mtune=<xxx> */
803 const char *ix86_arch_string
; /* for -march=<xxx> */
804 const char *ix86_fpmath_string
; /* for -mfpmath=<xxx> */
806 /* # of registers to use to pass arguments. */
807 const char *ix86_regparm_string
;
809 /* true if sse prefetch instruction is not NOOP. */
810 int x86_prefetch_sse
;
812 /* ix86_regparm_string as a number */
815 /* Alignment to use for loops and jumps: */
817 /* Power of two alignment for loops. */
818 const char *ix86_align_loops_string
;
820 /* Power of two alignment for non-loop jumps. */
821 const char *ix86_align_jumps_string
;
823 /* Power of two alignment for stack boundary in bytes. */
824 const char *ix86_preferred_stack_boundary_string
;
826 /* Preferred alignment for stack boundary in bits. */
827 unsigned int ix86_preferred_stack_boundary
;
829 /* Values 1-5: see jump.c */
830 int ix86_branch_cost
;
831 const char *ix86_branch_cost_string
;
833 /* Power of two alignment for functions. */
834 const char *ix86_align_funcs_string
;
836 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
837 char internal_label_prefix
[16];
838 int internal_label_prefix_len
;
840 static void output_pic_addr_const (FILE *, rtx
, int);
841 static void put_condition_code (enum rtx_code
, enum machine_mode
,
843 static const char *get_some_local_dynamic_name (void);
844 static int get_some_local_dynamic_name_1 (rtx
*, void *);
845 static rtx
ix86_expand_int_compare (enum rtx_code
, rtx
, rtx
);
846 static enum rtx_code
ix86_prepare_fp_compare_args (enum rtx_code
, rtx
*,
848 static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
849 static enum machine_mode
ix86_cc_modes_compatible (enum machine_mode
,
851 static rtx
get_thread_pointer (int);
852 static rtx
legitimize_tls_address (rtx
, enum tls_model
, int);
853 static void get_pc_thunk_name (char [32], unsigned int);
854 static rtx
gen_push (rtx
);
855 static int ix86_flags_dependant (rtx
, rtx
, enum attr_type
);
856 static int ix86_agi_dependant (rtx
, rtx
, enum attr_type
);
857 static struct machine_function
* ix86_init_machine_status (void);
858 static int ix86_split_to_parts (rtx
, rtx
*, enum machine_mode
);
859 static int ix86_nsaved_regs (void);
860 static void ix86_emit_save_regs (void);
861 static void ix86_emit_save_regs_using_mov (rtx
, HOST_WIDE_INT
);
862 static void ix86_emit_restore_regs_using_mov (rtx
, HOST_WIDE_INT
, int);
863 static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT
);
864 static HOST_WIDE_INT
ix86_GOT_alias_set (void);
865 static void ix86_adjust_counter (rtx
, HOST_WIDE_INT
);
866 static rtx
ix86_expand_aligntest (rtx
, int);
867 static void ix86_expand_strlensi_unroll_1 (rtx
, rtx
, rtx
);
868 static int ix86_issue_rate (void);
869 static int ix86_adjust_cost (rtx
, rtx
, rtx
, int);
870 static int ia32_multipass_dfa_lookahead (void);
871 static bool ix86_misaligned_mem_ok (enum machine_mode
);
872 static void ix86_init_mmx_sse_builtins (void);
873 static rtx
x86_this_parameter (tree
);
874 static void x86_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
875 HOST_WIDE_INT
, tree
);
876 static bool x86_can_output_mi_thunk (tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
877 static void x86_file_start (void);
878 static void ix86_reorg (void);
879 static bool ix86_expand_carry_flag_compare (enum rtx_code
, rtx
, rtx
, rtx
*);
880 static tree
ix86_build_builtin_va_list (void);
881 static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
883 static tree
ix86_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
884 static bool ix86_vector_mode_supported_p (enum machine_mode
);
886 static int ix86_address_cost (rtx
);
887 static bool ix86_cannot_force_const_mem (rtx
);
888 static rtx
ix86_delegitimize_address (rtx
);
890 struct builtin_description
;
891 static rtx
ix86_expand_sse_comi (const struct builtin_description
*,
893 static rtx
ix86_expand_sse_compare (const struct builtin_description
*,
895 static rtx
ix86_expand_unop1_builtin (enum insn_code
, tree
, rtx
);
896 static rtx
ix86_expand_unop_builtin (enum insn_code
, tree
, rtx
, int);
897 static rtx
ix86_expand_binop_builtin (enum insn_code
, tree
, rtx
);
898 static rtx
ix86_expand_store_builtin (enum insn_code
, tree
);
899 static rtx
safe_vector_operand (rtx
, enum machine_mode
);
900 static rtx
ix86_expand_fp_compare (enum rtx_code
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
901 static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code
);
902 static int ix86_fp_comparison_fcomi_cost (enum rtx_code code
);
903 static int ix86_fp_comparison_sahf_cost (enum rtx_code code
);
904 static int ix86_fp_comparison_cost (enum rtx_code code
);
905 static unsigned int ix86_select_alt_pic_regnum (void);
906 static int ix86_save_reg (unsigned int, int);
907 static void ix86_compute_frame_layout (struct ix86_frame
*);
908 static int ix86_comp_type_attributes (tree
, tree
);
909 static int ix86_function_regparm (tree
, tree
);
910 const struct attribute_spec ix86_attribute_table
[];
911 static bool ix86_function_ok_for_sibcall (tree
, tree
);
912 static tree
ix86_handle_cdecl_attribute (tree
*, tree
, tree
, int, bool *);
913 static tree
ix86_handle_regparm_attribute (tree
*, tree
, tree
, int, bool *);
914 static int ix86_value_regno (enum machine_mode
);
915 static bool contains_128bit_aligned_vector_p (tree
);
916 static rtx
ix86_struct_value_rtx (tree
, int);
917 static bool ix86_ms_bitfield_layout_p (tree
);
918 static tree
ix86_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
919 static int extended_reg_mentioned_1 (rtx
*, void *);
920 static bool ix86_rtx_costs (rtx
, int, int, int *);
921 static int min_insn_size (rtx
);
922 static tree
ix86_md_asm_clobbers (tree clobbers
);
923 static bool ix86_must_pass_in_stack (enum machine_mode mode
, tree type
);
924 static bool ix86_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
927 #if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION)
928 static void ix86_svr3_asm_out_constructor (rtx
, int);
930 /* This function is only used on Solaris. */
931 static void i386_solaris_elf_named_section (const char *, unsigned int, tree
)
934 /* Register class used for passing given 64bit part of the argument.
935 These represent classes as documented by the PS ABI, with the exception
936 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
937 use SF or DFmode move instead of DImode to avoid reformatting penalties.
939 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
940 whenever possible (upper half does contain padding).
942 enum x86_64_reg_class
945 X86_64_INTEGER_CLASS
,
946 X86_64_INTEGERSI_CLASS
,
955 static const char * const x86_64_reg_class_name
[] =
956 {"no", "integer", "integerSI", "sse", "sseSF", "sseDF", "sseup", "x87", "x87up", "no"};
958 #define MAX_CLASSES 4
959 static int classify_argument (enum machine_mode
, tree
,
960 enum x86_64_reg_class
[MAX_CLASSES
], int);
961 static int examine_argument (enum machine_mode
, tree
, int, int *, int *);
962 static rtx
construct_container (enum machine_mode
, tree
, int, int, int,
964 static enum x86_64_reg_class
merge_classes (enum x86_64_reg_class
,
965 enum x86_64_reg_class
);
967 /* Table of constants used by fldpi, fldln2, etc.... */
968 static REAL_VALUE_TYPE ext_80387_constants_table
[5];
969 static bool ext_80387_constants_init
= 0;
970 static void init_ext_80387_constants (void);
972 /* Initialize the GCC target structure. */
973 #undef TARGET_ATTRIBUTE_TABLE
974 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
975 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
976 # undef TARGET_MERGE_DECL_ATTRIBUTES
977 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
980 #undef TARGET_COMP_TYPE_ATTRIBUTES
981 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
983 #undef TARGET_INIT_BUILTINS
984 #define TARGET_INIT_BUILTINS ix86_init_builtins
986 #undef TARGET_EXPAND_BUILTIN
987 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
989 #undef TARGET_ASM_FUNCTION_EPILOGUE
990 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
992 #undef TARGET_ASM_OPEN_PAREN
993 #define TARGET_ASM_OPEN_PAREN ""
994 #undef TARGET_ASM_CLOSE_PAREN
995 #define TARGET_ASM_CLOSE_PAREN ""
997 #undef TARGET_ASM_ALIGNED_HI_OP
998 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
999 #undef TARGET_ASM_ALIGNED_SI_OP
1000 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
1002 #undef TARGET_ASM_ALIGNED_DI_OP
1003 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
1006 #undef TARGET_ASM_UNALIGNED_HI_OP
1007 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
1008 #undef TARGET_ASM_UNALIGNED_SI_OP
1009 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
1010 #undef TARGET_ASM_UNALIGNED_DI_OP
1011 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
1013 #undef TARGET_SCHED_ADJUST_COST
1014 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
1015 #undef TARGET_SCHED_ISSUE_RATE
1016 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
1017 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1018 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1019 ia32_multipass_dfa_lookahead
1021 #undef TARGET_VECTORIZE_MISALIGNED_MEM_OK
1022 #define TARGET_VECTORIZE_MISALIGNED_MEM_OK ix86_misaligned_mem_ok
1024 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1025 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
1028 #undef TARGET_HAVE_TLS
1029 #define TARGET_HAVE_TLS true
1031 #undef TARGET_CANNOT_FORCE_CONST_MEM
1032 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
1034 #undef TARGET_DELEGITIMIZE_ADDRESS
1035 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
1037 #undef TARGET_MS_BITFIELD_LAYOUT_P
1038 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
1040 #undef TARGET_ASM_OUTPUT_MI_THUNK
1041 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
1042 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1043 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
1045 #undef TARGET_ASM_FILE_START
1046 #define TARGET_ASM_FILE_START x86_file_start
1048 #undef TARGET_RTX_COSTS
1049 #define TARGET_RTX_COSTS ix86_rtx_costs
1050 #undef TARGET_ADDRESS_COST
1051 #define TARGET_ADDRESS_COST ix86_address_cost
1053 #undef TARGET_FIXED_CONDITION_CODE_REGS
1054 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
1055 #undef TARGET_CC_MODES_COMPATIBLE
1056 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
1058 #undef TARGET_MACHINE_DEPENDENT_REORG
1059 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
1061 #undef TARGET_BUILD_BUILTIN_VA_LIST
1062 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
1064 #undef TARGET_MD_ASM_CLOBBERS
1065 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
1067 #undef TARGET_PROMOTE_PROTOTYPES
1068 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1069 #undef TARGET_STRUCT_VALUE_RTX
1070 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
1071 #undef TARGET_SETUP_INCOMING_VARARGS
1072 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
1073 #undef TARGET_MUST_PASS_IN_STACK
1074 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
1075 #undef TARGET_PASS_BY_REFERENCE
1076 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
1078 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1079 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
1081 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1082 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
1084 #ifdef SUBTARGET_INSERT_ATTRIBUTES
1085 #undef TARGET_INSERT_ATTRIBUTES
1086 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
1089 struct gcc_target targetm
= TARGET_INITIALIZER
;
1092 /* The svr4 ABI for the i386 says that records and unions are returned
1094 #ifndef DEFAULT_PCC_STRUCT_RETURN
1095 #define DEFAULT_PCC_STRUCT_RETURN 1
1098 /* Sometimes certain combinations of command options do not make
1099 sense on a particular target machine. You can define a macro
1100 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1101 defined, is executed once just after all the command options have
1104 Don't use this macro to turn on various extra optimizations for
1105 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1108 override_options (void)
1111 int ix86_tune_defaulted
= 0;
1113 /* Comes from final.c -- no real reason to change it. */
1114 #define MAX_CODE_ALIGN 16
1118 const struct processor_costs
*cost
; /* Processor costs */
1119 const int target_enable
; /* Target flags to enable. */
1120 const int target_disable
; /* Target flags to disable. */
1121 const int align_loop
; /* Default alignments. */
1122 const int align_loop_max_skip
;
1123 const int align_jump
;
1124 const int align_jump_max_skip
;
1125 const int align_func
;
1127 const processor_target_table
[PROCESSOR_max
] =
1129 {&i386_cost
, 0, 0, 4, 3, 4, 3, 4},
1130 {&i486_cost
, 0, 0, 16, 15, 16, 15, 16},
1131 {&pentium_cost
, 0, 0, 16, 7, 16, 7, 16},
1132 {&pentiumpro_cost
, 0, 0, 16, 15, 16, 7, 16},
1133 {&k6_cost
, 0, 0, 32, 7, 32, 7, 32},
1134 {&athlon_cost
, 0, 0, 16, 7, 16, 7, 16},
1135 {&pentium4_cost
, 0, 0, 0, 0, 0, 0, 0},
1136 {&k8_cost
, 0, 0, 16, 7, 16, 7, 16},
1137 {&nocona_cost
, 0, 0, 0, 0, 0, 0, 0}
1140 static const char * const cpu_names
[] = TARGET_CPU_DEFAULT_NAMES
;
1143 const char *const name
; /* processor name or nickname. */
1144 const enum processor_type processor
;
1145 const enum pta_flags
1151 PTA_PREFETCH_SSE
= 16,
1157 const processor_alias_table
[] =
1159 {"i386", PROCESSOR_I386
, 0},
1160 {"i486", PROCESSOR_I486
, 0},
1161 {"i586", PROCESSOR_PENTIUM
, 0},
1162 {"pentium", PROCESSOR_PENTIUM
, 0},
1163 {"pentium-mmx", PROCESSOR_PENTIUM
, PTA_MMX
},
1164 {"winchip-c6", PROCESSOR_I486
, PTA_MMX
},
1165 {"winchip2", PROCESSOR_I486
, PTA_MMX
| PTA_3DNOW
},
1166 {"c3", PROCESSOR_I486
, PTA_MMX
| PTA_3DNOW
},
1167 {"c3-2", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_SSE
},
1168 {"i686", PROCESSOR_PENTIUMPRO
, 0},
1169 {"pentiumpro", PROCESSOR_PENTIUMPRO
, 0},
1170 {"pentium2", PROCESSOR_PENTIUMPRO
, PTA_MMX
},
1171 {"pentium3", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_SSE
| PTA_PREFETCH_SSE
},
1172 {"pentium3m", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_SSE
| PTA_PREFETCH_SSE
},
1173 {"pentium-m", PROCESSOR_PENTIUMPRO
, PTA_MMX
| PTA_SSE
| PTA_PREFETCH_SSE
| PTA_SSE2
},
1174 {"pentium4", PROCESSOR_PENTIUM4
, PTA_SSE
| PTA_SSE2
1175 | PTA_MMX
| PTA_PREFETCH_SSE
},
1176 {"pentium4m", PROCESSOR_PENTIUM4
, PTA_SSE
| PTA_SSE2
1177 | PTA_MMX
| PTA_PREFETCH_SSE
},
1178 {"prescott", PROCESSOR_NOCONA
, PTA_SSE
| PTA_SSE2
| PTA_SSE3
1179 | PTA_MMX
| PTA_PREFETCH_SSE
},
1180 {"nocona", PROCESSOR_NOCONA
, PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_64BIT
1181 | PTA_MMX
| PTA_PREFETCH_SSE
},
1182 {"k6", PROCESSOR_K6
, PTA_MMX
},
1183 {"k6-2", PROCESSOR_K6
, PTA_MMX
| PTA_3DNOW
},
1184 {"k6-3", PROCESSOR_K6
, PTA_MMX
| PTA_3DNOW
},
1185 {"athlon", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1187 {"athlon-tbird", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
1188 | PTA_3DNOW
| PTA_3DNOW_A
},
1189 {"athlon-4", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1190 | PTA_3DNOW_A
| PTA_SSE
},
1191 {"athlon-xp", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1192 | PTA_3DNOW_A
| PTA_SSE
},
1193 {"athlon-mp", PROCESSOR_ATHLON
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
1194 | PTA_3DNOW_A
| PTA_SSE
},
1195 {"x86-64", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_64BIT
1196 | PTA_SSE
| PTA_SSE2
},
1197 {"k8", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1198 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1199 {"opteron", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1200 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1201 {"athlon64", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1202 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1203 {"athlon-fx", PROCESSOR_K8
, PTA_MMX
| PTA_PREFETCH_SSE
| PTA_3DNOW
| PTA_64BIT
1204 | PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
},
1207 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
1209 /* Set the default values for switches whose default depends on TARGET_64BIT
1210 in case they weren't overwritten by command line options. */
1213 if (flag_omit_frame_pointer
== 2)
1214 flag_omit_frame_pointer
= 1;
1215 if (flag_asynchronous_unwind_tables
== 2)
1216 flag_asynchronous_unwind_tables
= 1;
1217 if (flag_pcc_struct_return
== 2)
1218 flag_pcc_struct_return
= 0;
1222 if (flag_omit_frame_pointer
== 2)
1223 flag_omit_frame_pointer
= 0;
1224 if (flag_asynchronous_unwind_tables
== 2)
1225 flag_asynchronous_unwind_tables
= 0;
1226 if (flag_pcc_struct_return
== 2)
1227 flag_pcc_struct_return
= DEFAULT_PCC_STRUCT_RETURN
;
1230 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1231 SUBTARGET_OVERRIDE_OPTIONS
;
1234 if (!ix86_tune_string
&& ix86_arch_string
)
1235 ix86_tune_string
= ix86_arch_string
;
1236 if (!ix86_tune_string
)
1238 ix86_tune_string
= cpu_names
[TARGET_CPU_DEFAULT
];
1239 ix86_tune_defaulted
= 1;
1241 if (!ix86_arch_string
)
1242 ix86_arch_string
= TARGET_64BIT
? "x86-64" : "i386";
1244 if (ix86_cmodel_string
!= 0)
1246 if (!strcmp (ix86_cmodel_string
, "small"))
1247 ix86_cmodel
= flag_pic
? CM_SMALL_PIC
: CM_SMALL
;
1249 sorry ("code model %s not supported in PIC mode", ix86_cmodel_string
);
1250 else if (!strcmp (ix86_cmodel_string
, "32"))
1251 ix86_cmodel
= CM_32
;
1252 else if (!strcmp (ix86_cmodel_string
, "kernel") && !flag_pic
)
1253 ix86_cmodel
= CM_KERNEL
;
1254 else if (!strcmp (ix86_cmodel_string
, "medium") && !flag_pic
)
1255 ix86_cmodel
= CM_MEDIUM
;
1256 else if (!strcmp (ix86_cmodel_string
, "large") && !flag_pic
)
1257 ix86_cmodel
= CM_LARGE
;
1259 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string
);
1263 ix86_cmodel
= CM_32
;
1265 ix86_cmodel
= flag_pic
? CM_SMALL_PIC
: CM_SMALL
;
1267 if (ix86_asm_string
!= 0)
1269 if (!strcmp (ix86_asm_string
, "intel"))
1270 ix86_asm_dialect
= ASM_INTEL
;
1271 else if (!strcmp (ix86_asm_string
, "att"))
1272 ix86_asm_dialect
= ASM_ATT
;
1274 error ("bad value (%s) for -masm= switch", ix86_asm_string
);
1276 if ((TARGET_64BIT
== 0) != (ix86_cmodel
== CM_32
))
1277 error ("code model %qs not supported in the %s bit mode",
1278 ix86_cmodel_string
, TARGET_64BIT
? "64" : "32");
1279 if (ix86_cmodel
== CM_LARGE
)
1280 sorry ("code model %<large%> not supported yet");
1281 if ((TARGET_64BIT
!= 0) != ((target_flags
& MASK_64BIT
) != 0))
1282 sorry ("%i-bit mode not compiled in",
1283 (target_flags
& MASK_64BIT
) ? 64 : 32);
1285 for (i
= 0; i
< pta_size
; i
++)
1286 if (! strcmp (ix86_arch_string
, processor_alias_table
[i
].name
))
1288 ix86_arch
= processor_alias_table
[i
].processor
;
1289 /* Default cpu tuning to the architecture. */
1290 ix86_tune
= ix86_arch
;
1291 if (processor_alias_table
[i
].flags
& PTA_MMX
1292 && !(target_flags_explicit
& MASK_MMX
))
1293 target_flags
|= MASK_MMX
;
1294 if (processor_alias_table
[i
].flags
& PTA_3DNOW
1295 && !(target_flags_explicit
& MASK_3DNOW
))
1296 target_flags
|= MASK_3DNOW
;
1297 if (processor_alias_table
[i
].flags
& PTA_3DNOW_A
1298 && !(target_flags_explicit
& MASK_3DNOW_A
))
1299 target_flags
|= MASK_3DNOW_A
;
1300 if (processor_alias_table
[i
].flags
& PTA_SSE
1301 && !(target_flags_explicit
& MASK_SSE
))
1302 target_flags
|= MASK_SSE
;
1303 if (processor_alias_table
[i
].flags
& PTA_SSE2
1304 && !(target_flags_explicit
& MASK_SSE2
))
1305 target_flags
|= MASK_SSE2
;
1306 if (processor_alias_table
[i
].flags
& PTA_SSE3
1307 && !(target_flags_explicit
& MASK_SSE3
))
1308 target_flags
|= MASK_SSE3
;
1309 if (processor_alias_table
[i
].flags
& PTA_PREFETCH_SSE
)
1310 x86_prefetch_sse
= true;
1311 if (TARGET_64BIT
&& !(processor_alias_table
[i
].flags
& PTA_64BIT
))
1312 error ("CPU you selected does not support x86-64 "
1318 error ("bad value (%s) for -march= switch", ix86_arch_string
);
1320 for (i
= 0; i
< pta_size
; i
++)
1321 if (! strcmp (ix86_tune_string
, processor_alias_table
[i
].name
))
1323 ix86_tune
= processor_alias_table
[i
].processor
;
1324 if (TARGET_64BIT
&& !(processor_alias_table
[i
].flags
& PTA_64BIT
))
1326 if (ix86_tune_defaulted
)
1328 ix86_tune_string
= "x86-64";
1329 for (i
= 0; i
< pta_size
; i
++)
1330 if (! strcmp (ix86_tune_string
,
1331 processor_alias_table
[i
].name
))
1333 ix86_tune
= processor_alias_table
[i
].processor
;
1336 error ("CPU you selected does not support x86-64 "
1339 /* Intel CPUs have always interpreted SSE prefetch instructions as
1340 NOPs; so, we can enable SSE prefetch instructions even when
1341 -mtune (rather than -march) points us to a processor that has them.
1342 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
1343 higher processors. */
1344 if (TARGET_CMOVE
&& (processor_alias_table
[i
].flags
& PTA_PREFETCH_SSE
))
1345 x86_prefetch_sse
= true;
1349 error ("bad value (%s) for -mtune= switch", ix86_tune_string
);
1352 ix86_cost
= &size_cost
;
1354 ix86_cost
= processor_target_table
[ix86_tune
].cost
;
1355 target_flags
|= processor_target_table
[ix86_tune
].target_enable
;
1356 target_flags
&= ~processor_target_table
[ix86_tune
].target_disable
;
1358 /* Arrange to set up i386_stack_locals for all functions. */
1359 init_machine_status
= ix86_init_machine_status
;
1361 /* Validate -mregparm= value. */
1362 if (ix86_regparm_string
)
1364 i
= atoi (ix86_regparm_string
);
1365 if (i
< 0 || i
> REGPARM_MAX
)
1366 error ("-mregparm=%d is not between 0 and %d", i
, REGPARM_MAX
);
1372 ix86_regparm
= REGPARM_MAX
;
1374 /* If the user has provided any of the -malign-* options,
1375 warn and use that value only if -falign-* is not set.
1376 Remove this code in GCC 3.2 or later. */
1377 if (ix86_align_loops_string
)
1379 warning ("-malign-loops is obsolete, use -falign-loops");
1380 if (align_loops
== 0)
1382 i
= atoi (ix86_align_loops_string
);
1383 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1384 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1386 align_loops
= 1 << i
;
1390 if (ix86_align_jumps_string
)
1392 warning ("-malign-jumps is obsolete, use -falign-jumps");
1393 if (align_jumps
== 0)
1395 i
= atoi (ix86_align_jumps_string
);
1396 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1397 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1399 align_jumps
= 1 << i
;
1403 if (ix86_align_funcs_string
)
1405 warning ("-malign-functions is obsolete, use -falign-functions");
1406 if (align_functions
== 0)
1408 i
= atoi (ix86_align_funcs_string
);
1409 if (i
< 0 || i
> MAX_CODE_ALIGN
)
1410 error ("-malign-loops=%d is not between 0 and %d", i
, MAX_CODE_ALIGN
);
1412 align_functions
= 1 << i
;
1416 /* Default align_* from the processor table. */
1417 if (align_loops
== 0)
1419 align_loops
= processor_target_table
[ix86_tune
].align_loop
;
1420 align_loops_max_skip
= processor_target_table
[ix86_tune
].align_loop_max_skip
;
1422 if (align_jumps
== 0)
1424 align_jumps
= processor_target_table
[ix86_tune
].align_jump
;
1425 align_jumps_max_skip
= processor_target_table
[ix86_tune
].align_jump_max_skip
;
1427 if (align_functions
== 0)
1429 align_functions
= processor_target_table
[ix86_tune
].align_func
;
1432 /* Validate -mpreferred-stack-boundary= value, or provide default.
1433 The default of 128 bits is for Pentium III's SSE __m128, but we
1434 don't want additional code to keep the stack aligned when
1435 optimizing for code size. */
1436 ix86_preferred_stack_boundary
= (optimize_size
1437 ? TARGET_64BIT
? 128 : 32
1439 if (ix86_preferred_stack_boundary_string
)
1441 i
= atoi (ix86_preferred_stack_boundary_string
);
1442 if (i
< (TARGET_64BIT
? 4 : 2) || i
> 12)
1443 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i
,
1444 TARGET_64BIT
? 4 : 2);
1446 ix86_preferred_stack_boundary
= (1 << i
) * BITS_PER_UNIT
;
1449 /* Validate -mbranch-cost= value, or provide default. */
1450 ix86_branch_cost
= processor_target_table
[ix86_tune
].cost
->branch_cost
;
1451 if (ix86_branch_cost_string
)
1453 i
= atoi (ix86_branch_cost_string
);
1455 error ("-mbranch-cost=%d is not between 0 and 5", i
);
1457 ix86_branch_cost
= i
;
1460 if (ix86_tls_dialect_string
)
1462 if (strcmp (ix86_tls_dialect_string
, "gnu") == 0)
1463 ix86_tls_dialect
= TLS_DIALECT_GNU
;
1464 else if (strcmp (ix86_tls_dialect_string
, "sun") == 0)
1465 ix86_tls_dialect
= TLS_DIALECT_SUN
;
1467 error ("bad value (%s) for -mtls-dialect= switch",
1468 ix86_tls_dialect_string
);
1471 /* Keep nonleaf frame pointers. */
1472 if (TARGET_OMIT_LEAF_FRAME_POINTER
)
1473 flag_omit_frame_pointer
= 1;
1475 /* If we're doing fast math, we don't care about comparison order
1476 wrt NaNs. This lets us use a shorter comparison sequence. */
1477 if (flag_unsafe_math_optimizations
)
1478 target_flags
&= ~MASK_IEEE_FP
;
1480 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
1481 since the insns won't need emulation. */
1482 if (x86_arch_always_fancy_math_387
& (1 << ix86_arch
))
1483 target_flags
&= ~MASK_NO_FANCY_MATH_387
;
1485 /* Turn on SSE2 builtins for -msse3. */
1487 target_flags
|= MASK_SSE2
;
1489 /* Turn on SSE builtins for -msse2. */
1491 target_flags
|= MASK_SSE
;
1495 if (TARGET_ALIGN_DOUBLE
)
1496 error ("-malign-double makes no sense in the 64bit mode");
1498 error ("-mrtd calling convention not supported in the 64bit mode");
1499 /* Enable by default the SSE and MMX builtins. */
1500 target_flags
|= (MASK_SSE2
| MASK_SSE
| MASK_MMX
| MASK_128BIT_LONG_DOUBLE
);
1501 ix86_fpmath
= FPMATH_SSE
;
1505 ix86_fpmath
= FPMATH_387
;
1506 /* i386 ABI does not specify red zone. It still makes sense to use it
1507 when programmer takes care to stack from being destroyed. */
1508 if (!(target_flags_explicit
& MASK_NO_RED_ZONE
))
1509 target_flags
|= MASK_NO_RED_ZONE
;
1512 if (ix86_fpmath_string
!= 0)
1514 if (! strcmp (ix86_fpmath_string
, "387"))
1515 ix86_fpmath
= FPMATH_387
;
1516 else if (! strcmp (ix86_fpmath_string
, "sse"))
1520 warning ("SSE instruction set disabled, using 387 arithmetics");
1521 ix86_fpmath
= FPMATH_387
;
1524 ix86_fpmath
= FPMATH_SSE
;
1526 else if (! strcmp (ix86_fpmath_string
, "387,sse")
1527 || ! strcmp (ix86_fpmath_string
, "sse,387"))
1531 warning ("SSE instruction set disabled, using 387 arithmetics");
1532 ix86_fpmath
= FPMATH_387
;
1534 else if (!TARGET_80387
)
1536 warning ("387 instruction set disabled, using SSE arithmetics");
1537 ix86_fpmath
= FPMATH_SSE
;
1540 ix86_fpmath
= FPMATH_SSE
| FPMATH_387
;
1543 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string
);
1546 /* It makes no sense to ask for just SSE builtins, so MMX is also turned
1550 target_flags
|= MASK_MMX
;
1551 x86_prefetch_sse
= true;
1554 /* If it has 3DNow! it also has MMX so MMX is also turned on by -m3dnow */
1557 target_flags
|= MASK_MMX
;
1558 /* If we are targeting the Athlon architecture, enable the 3Dnow/MMX
1559 extensions it adds. */
1560 if (x86_3dnow_a
& (1 << ix86_arch
))
1561 target_flags
|= MASK_3DNOW_A
;
1563 if ((x86_accumulate_outgoing_args
& TUNEMASK
)
1564 && !(target_flags_explicit
& MASK_ACCUMULATE_OUTGOING_ARGS
)
1566 target_flags
|= MASK_ACCUMULATE_OUTGOING_ARGS
;
1568 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
1571 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix
, "LX", 0);
1572 p
= strchr (internal_label_prefix
, 'X');
1573 internal_label_prefix_len
= p
- internal_label_prefix
;
1576 /* When scheduling description is not available, disable scheduler pass so it
1577 won't slow down the compilation and make x87 code slower. */
1578 if (!TARGET_SCHEDULE
)
1579 flag_schedule_insns_after_reload
= flag_schedule_insns
= 0;
1583 optimization_options (int level
, int size ATTRIBUTE_UNUSED
)
1585 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
1586 make the problem with not enough registers even worse. */
1587 #ifdef INSN_SCHEDULING
1589 flag_schedule_insns
= 0;
1592 /* The default values of these switches depend on the TARGET_64BIT
1593 that is not known at this moment. Mark these values with 2 and
1594 let user the to override these. In case there is no command line option
1595 specifying them, we will set the defaults in override_options. */
1597 flag_omit_frame_pointer
= 2;
1598 flag_pcc_struct_return
= 2;
1599 flag_asynchronous_unwind_tables
= 2;
1602 /* Table of valid machine attributes. */
1603 const struct attribute_spec ix86_attribute_table
[] =
1605 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1606 /* Stdcall attribute says callee is responsible for popping arguments
1607 if they are not variable. */
1608 { "stdcall", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1609 /* Fastcall attribute says callee is responsible for popping arguments
1610 if they are not variable. */
1611 { "fastcall", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1612 /* Cdecl attribute says the callee is a normal C declaration */
1613 { "cdecl", 0, 0, false, true, true, ix86_handle_cdecl_attribute
},
1614 /* Regparm attribute specifies how many integer arguments are to be
1615 passed in registers. */
1616 { "regparm", 1, 1, false, true, true, ix86_handle_regparm_attribute
},
1617 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1618 { "dllimport", 0, 0, false, false, false, handle_dll_attribute
},
1619 { "dllexport", 0, 0, false, false, false, handle_dll_attribute
},
1620 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute
},
1622 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute
},
1623 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute
},
1624 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1625 SUBTARGET_ATTRIBUTE_TABLE
,
1627 { NULL
, 0, 0, false, false, false, NULL
}
1630 /* Decide whether we can make a sibling call to a function. DECL is the
1631 declaration of the function being targeted by the call and EXP is the
1632 CALL_EXPR representing the call. */
1635 ix86_function_ok_for_sibcall (tree decl
, tree exp
)
1637 /* If we are generating position-independent code, we cannot sibcall
1638 optimize any indirect call, or a direct call to a global function,
1639 as the PLT requires %ebx be live. */
1640 if (!TARGET_64BIT
&& flag_pic
&& (!decl
|| TREE_PUBLIC (decl
)))
1643 /* If we are returning floats on the 80387 register stack, we cannot
1644 make a sibcall from a function that doesn't return a float to a
1645 function that does or, conversely, from a function that does return
1646 a float to a function that doesn't; the necessary stack adjustment
1647 would not be executed. */
1648 if (STACK_REG_P (ix86_function_value (TREE_TYPE (exp
)))
1649 != STACK_REG_P (ix86_function_value (TREE_TYPE (DECL_RESULT (cfun
->decl
)))))
1652 /* If this call is indirect, we'll need to be able to use a call-clobbered
1653 register for the address of the target function. Make sure that all
1654 such registers are not used for passing parameters. */
1655 if (!decl
&& !TARGET_64BIT
)
1659 /* We're looking at the CALL_EXPR, we need the type of the function. */
1660 type
= TREE_OPERAND (exp
, 0); /* pointer expression */
1661 type
= TREE_TYPE (type
); /* pointer type */
1662 type
= TREE_TYPE (type
); /* function type */
1664 if (ix86_function_regparm (type
, NULL
) >= 3)
1666 /* ??? Need to count the actual number of registers to be used,
1667 not the possible number of registers. Fix later. */
1672 /* Otherwise okay. That also includes certain types of indirect calls. */
1676 /* Handle a "cdecl", "stdcall", or "fastcall" attribute;
1677 arguments as in struct attribute_spec.handler. */
1679 ix86_handle_cdecl_attribute (tree
*node
, tree name
,
1680 tree args ATTRIBUTE_UNUSED
,
1681 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1683 if (TREE_CODE (*node
) != FUNCTION_TYPE
1684 && TREE_CODE (*node
) != METHOD_TYPE
1685 && TREE_CODE (*node
) != FIELD_DECL
1686 && TREE_CODE (*node
) != TYPE_DECL
)
1688 warning ("%qs attribute only applies to functions",
1689 IDENTIFIER_POINTER (name
));
1690 *no_add_attrs
= true;
1694 if (is_attribute_p ("fastcall", name
))
1696 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node
)))
1698 error ("fastcall and stdcall attributes are not compatible");
1700 else if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node
)))
1702 error ("fastcall and regparm attributes are not compatible");
1705 else if (is_attribute_p ("stdcall", name
))
1707 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node
)))
1709 error ("fastcall and stdcall attributes are not compatible");
1716 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
1717 *no_add_attrs
= true;
1723 /* Handle a "regparm" attribute;
1724 arguments as in struct attribute_spec.handler. */
1726 ix86_handle_regparm_attribute (tree
*node
, tree name
, tree args
,
1727 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1729 if (TREE_CODE (*node
) != FUNCTION_TYPE
1730 && TREE_CODE (*node
) != METHOD_TYPE
1731 && TREE_CODE (*node
) != FIELD_DECL
1732 && TREE_CODE (*node
) != TYPE_DECL
)
1734 warning ("%qs attribute only applies to functions",
1735 IDENTIFIER_POINTER (name
));
1736 *no_add_attrs
= true;
1742 cst
= TREE_VALUE (args
);
1743 if (TREE_CODE (cst
) != INTEGER_CST
)
1745 warning ("%qs attribute requires an integer constant argument",
1746 IDENTIFIER_POINTER (name
));
1747 *no_add_attrs
= true;
1749 else if (compare_tree_int (cst
, REGPARM_MAX
) > 0)
1751 warning ("argument to %qs attribute larger than %d",
1752 IDENTIFIER_POINTER (name
), REGPARM_MAX
);
1753 *no_add_attrs
= true;
1756 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node
)))
1758 error ("fastcall and regparm attributes are not compatible");
1765 /* Return 0 if the attributes for two types are incompatible, 1 if they
1766 are compatible, and 2 if they are nearly compatible (which causes a
1767 warning to be generated). */
1770 ix86_comp_type_attributes (tree type1
, tree type2
)
1772 /* Check for mismatch of non-default calling convention. */
1773 const char *const rtdstr
= TARGET_RTD
? "cdecl" : "stdcall";
1775 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
1778 /* Check for mismatched fastcall types */
1779 if (!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1
))
1780 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2
)))
1783 /* Check for mismatched return types (cdecl vs stdcall). */
1784 if (!lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type1
))
1785 != !lookup_attribute (rtdstr
, TYPE_ATTRIBUTES (type2
)))
1787 if (ix86_function_regparm (type1
, NULL
)
1788 != ix86_function_regparm (type2
, NULL
))
1793 /* Return the regparm value for a fuctio with the indicated TYPE and DECL.
1794 DECL may be NULL when calling function indirectly
1795 or considering a libcall. */
1798 ix86_function_regparm (tree type
, tree decl
)
1801 int regparm
= ix86_regparm
;
1802 bool user_convention
= false;
1806 attr
= lookup_attribute ("regparm", TYPE_ATTRIBUTES (type
));
1809 regparm
= TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr
)));
1810 user_convention
= true;
1813 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type
)))
1816 user_convention
= true;
1819 /* Use register calling convention for local functions when possible. */
1820 if (!TARGET_64BIT
&& !user_convention
&& decl
1821 && flag_unit_at_a_time
&& !profile_flag
)
1823 struct cgraph_local_info
*i
= cgraph_local_info (decl
);
1826 /* We can't use regparm(3) for nested functions as these use
1827 static chain pointer in third argument. */
1828 if (DECL_CONTEXT (decl
) && !DECL_NO_STATIC_CHAIN (decl
))
1838 /* Return true if EAX is live at the start of the function. Used by
1839 ix86_expand_prologue to determine if we need special help before
1840 calling allocate_stack_worker. */
1843 ix86_eax_live_at_start_p (void)
1845 /* Cheat. Don't bother working forward from ix86_function_regparm
1846 to the function type to whether an actual argument is located in
1847 eax. Instead just look at cfg info, which is still close enough
1848 to correct at this point. This gives false positives for broken
1849 functions that might use uninitialized data that happens to be
1850 allocated in eax, but who cares? */
1851 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->global_live_at_end
, 0);
1854 /* Value is the number of bytes of arguments automatically
1855 popped when returning from a subroutine call.
1856 FUNDECL is the declaration node of the function (as a tree),
1857 FUNTYPE is the data type of the function (as a tree),
1858 or for a library call it is an identifier node for the subroutine name.
1859 SIZE is the number of bytes of arguments passed on the stack.
1861 On the 80386, the RTD insn may be used to pop them if the number
1862 of args is fixed, but if the number is variable then the caller
1863 must pop them all. RTD can't be used for library calls now
1864 because the library is compiled with the Unix compiler.
1865 Use of RTD is a selectable option, since it is incompatible with
1866 standard Unix calling sequences. If the option is not selected,
1867 the caller must always pop the args.
1869 The attribute stdcall is equivalent to RTD on a per module basis. */
1872 ix86_return_pops_args (tree fundecl
, tree funtype
, int size
)
1874 int rtd
= TARGET_RTD
&& (!fundecl
|| TREE_CODE (fundecl
) != IDENTIFIER_NODE
);
1876 /* Cdecl functions override -mrtd, and never pop the stack. */
1877 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype
))) {
1879 /* Stdcall and fastcall functions will pop the stack if not
1881 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype
))
1882 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype
)))
1886 && (TYPE_ARG_TYPES (funtype
) == NULL_TREE
1887 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype
)))
1888 == void_type_node
)))
1892 /* Lose any fake structure return argument if it is passed on the stack. */
1893 if (aggregate_value_p (TREE_TYPE (funtype
), fundecl
)
1895 && !KEEP_AGGREGATE_RETURN_POINTER
)
1897 int nregs
= ix86_function_regparm (funtype
, fundecl
);
1900 return GET_MODE_SIZE (Pmode
);
1906 /* Argument support functions. */
1908 /* Return true when register may be used to pass function parameters. */
1910 ix86_function_arg_regno_p (int regno
)
1914 return (regno
< REGPARM_MAX
1915 || (TARGET_SSE
&& SSE_REGNO_P (regno
) && !fixed_regs
[regno
]));
1916 if (SSE_REGNO_P (regno
) && TARGET_SSE
)
1918 /* RAX is used as hidden argument to va_arg functions. */
1921 for (i
= 0; i
< REGPARM_MAX
; i
++)
1922 if (regno
== x86_64_int_parameter_registers
[i
])
1927 /* Return if we do not know how to pass TYPE solely in registers. */
1930 ix86_must_pass_in_stack (enum machine_mode mode
, tree type
)
1932 if (must_pass_in_stack_var_size_or_pad (mode
, type
))
1934 return (!TARGET_64BIT
&& type
&& mode
== TImode
);
1937 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1938 for a call to a function whose data type is FNTYPE.
1939 For a library call, FNTYPE is 0. */
1942 init_cumulative_args (CUMULATIVE_ARGS
*cum
, /* Argument info to initialize */
1943 tree fntype
, /* tree ptr for function decl */
1944 rtx libname
, /* SYMBOL_REF of library name or 0 */
1947 static CUMULATIVE_ARGS zero_cum
;
1948 tree param
, next_param
;
1950 if (TARGET_DEBUG_ARG
)
1952 fprintf (stderr
, "\ninit_cumulative_args (");
1954 fprintf (stderr
, "fntype code = %s, ret code = %s",
1955 tree_code_name
[(int) TREE_CODE (fntype
)],
1956 tree_code_name
[(int) TREE_CODE (TREE_TYPE (fntype
))]);
1958 fprintf (stderr
, "no fntype");
1961 fprintf (stderr
, ", libname = %s", XSTR (libname
, 0));
1966 /* Set up the number of registers to use for passing arguments. */
1968 cum
->nregs
= ix86_function_regparm (fntype
, fndecl
);
1970 cum
->nregs
= ix86_regparm
;
1972 cum
->sse_nregs
= SSE_REGPARM_MAX
;
1974 cum
->mmx_nregs
= MMX_REGPARM_MAX
;
1975 cum
->warn_sse
= true;
1976 cum
->warn_mmx
= true;
1977 cum
->maybe_vaarg
= false;
1979 /* Use ecx and edx registers if function has fastcall attribute */
1980 if (fntype
&& !TARGET_64BIT
)
1982 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype
)))
1989 /* Determine if this function has variable arguments. This is
1990 indicated by the last argument being 'void_type_mode' if there
1991 are no variable arguments. If there are variable arguments, then
1992 we won't pass anything in registers in 32-bit mode. */
1994 if (cum
->nregs
|| cum
->mmx_nregs
|| cum
->sse_nregs
)
1996 for (param
= (fntype
) ? TYPE_ARG_TYPES (fntype
) : 0;
1997 param
!= 0; param
= next_param
)
1999 next_param
= TREE_CHAIN (param
);
2000 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
2011 cum
->maybe_vaarg
= true;
2015 if ((!fntype
&& !libname
)
2016 || (fntype
&& !TYPE_ARG_TYPES (fntype
)))
2017 cum
->maybe_vaarg
= 1;
2019 if (TARGET_DEBUG_ARG
)
2020 fprintf (stderr
, ", nregs=%d )\n", cum
->nregs
);
2025 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
2026 of this code is to classify each 8bytes of incoming argument by the register
2027 class and assign registers accordingly. */
2029 /* Return the union class of CLASS1 and CLASS2.
2030 See the x86-64 PS ABI for details. */
2032 static enum x86_64_reg_class
2033 merge_classes (enum x86_64_reg_class class1
, enum x86_64_reg_class class2
)
2035 /* Rule #1: If both classes are equal, this is the resulting class. */
2036 if (class1
== class2
)
2039 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
2041 if (class1
== X86_64_NO_CLASS
)
2043 if (class2
== X86_64_NO_CLASS
)
2046 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
2047 if (class1
== X86_64_MEMORY_CLASS
|| class2
== X86_64_MEMORY_CLASS
)
2048 return X86_64_MEMORY_CLASS
;
2050 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
2051 if ((class1
== X86_64_INTEGERSI_CLASS
&& class2
== X86_64_SSESF_CLASS
)
2052 || (class2
== X86_64_INTEGERSI_CLASS
&& class1
== X86_64_SSESF_CLASS
))
2053 return X86_64_INTEGERSI_CLASS
;
2054 if (class1
== X86_64_INTEGER_CLASS
|| class1
== X86_64_INTEGERSI_CLASS
2055 || class2
== X86_64_INTEGER_CLASS
|| class2
== X86_64_INTEGERSI_CLASS
)
2056 return X86_64_INTEGER_CLASS
;
2058 /* Rule #5: If one of the classes is X87 or X87UP class, MEMORY is used. */
2059 if (class1
== X86_64_X87_CLASS
|| class1
== X86_64_X87UP_CLASS
2060 || class2
== X86_64_X87_CLASS
|| class2
== X86_64_X87UP_CLASS
)
2061 return X86_64_MEMORY_CLASS
;
2063 /* Rule #6: Otherwise class SSE is used. */
2064 return X86_64_SSE_CLASS
;
2067 /* Classify the argument of type TYPE and mode MODE.
2068 CLASSES will be filled by the register class used to pass each word
2069 of the operand. The number of words is returned. In case the parameter
2070 should be passed in memory, 0 is returned. As a special case for zero
2071 sized containers, classes[0] will be NO_CLASS and 1 is returned.
2073 BIT_OFFSET is used internally for handling records and specifies offset
2074 of the offset in bits modulo 256 to avoid overflow cases.
2076 See the x86-64 PS ABI for details.
2080 classify_argument (enum machine_mode mode
, tree type
,
2081 enum x86_64_reg_class classes
[MAX_CLASSES
], int bit_offset
)
2083 HOST_WIDE_INT bytes
=
2084 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2085 int words
= (bytes
+ (bit_offset
% 64) / 8 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2087 /* Variable sized entities are always passed/returned in memory. */
2091 if (mode
!= VOIDmode
2092 && targetm
.calls
.must_pass_in_stack (mode
, type
))
2095 if (type
&& AGGREGATE_TYPE_P (type
))
2099 enum x86_64_reg_class subclasses
[MAX_CLASSES
];
2101 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
2105 for (i
= 0; i
< words
; i
++)
2106 classes
[i
] = X86_64_NO_CLASS
;
2108 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
2109 signalize memory class, so handle it as special case. */
2112 classes
[0] = X86_64_NO_CLASS
;
2116 /* Classify each field of record and merge classes. */
2117 if (TREE_CODE (type
) == RECORD_TYPE
)
2119 /* For classes first merge in the field of the subclasses. */
2120 if (TYPE_BINFO (type
))
2122 tree binfo
, base_binfo
;
2125 for (binfo
= TYPE_BINFO (type
), basenum
= 0;
2126 BINFO_BASE_ITERATE (binfo
, basenum
, base_binfo
); basenum
++)
2129 int offset
= tree_low_cst (BINFO_OFFSET (base_binfo
), 0) * 8;
2130 tree type
= BINFO_TYPE (base_binfo
);
2132 num
= classify_argument (TYPE_MODE (type
),
2134 (offset
+ bit_offset
) % 256);
2137 for (i
= 0; i
< num
; i
++)
2139 int pos
= (offset
+ (bit_offset
% 64)) / 8 / 8;
2141 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
2145 /* And now merge the fields of structure. */
2146 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
2148 if (TREE_CODE (field
) == FIELD_DECL
)
2152 /* Bitfields are always classified as integer. Handle them
2153 early, since later code would consider them to be
2154 misaligned integers. */
2155 if (DECL_BIT_FIELD (field
))
2157 for (i
= int_bit_position (field
) / 8 / 8;
2158 i
< (int_bit_position (field
)
2159 + tree_low_cst (DECL_SIZE (field
), 0)
2162 merge_classes (X86_64_INTEGER_CLASS
,
2167 num
= classify_argument (TYPE_MODE (TREE_TYPE (field
)),
2168 TREE_TYPE (field
), subclasses
,
2169 (int_bit_position (field
)
2170 + bit_offset
) % 256);
2173 for (i
= 0; i
< num
; i
++)
2176 (int_bit_position (field
) + (bit_offset
% 64)) / 8 / 8;
2178 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
2184 /* Arrays are handled as small records. */
2185 else if (TREE_CODE (type
) == ARRAY_TYPE
)
2188 num
= classify_argument (TYPE_MODE (TREE_TYPE (type
)),
2189 TREE_TYPE (type
), subclasses
, bit_offset
);
2193 /* The partial classes are now full classes. */
2194 if (subclasses
[0] == X86_64_SSESF_CLASS
&& bytes
!= 4)
2195 subclasses
[0] = X86_64_SSE_CLASS
;
2196 if (subclasses
[0] == X86_64_INTEGERSI_CLASS
&& bytes
!= 4)
2197 subclasses
[0] = X86_64_INTEGER_CLASS
;
2199 for (i
= 0; i
< words
; i
++)
2200 classes
[i
] = subclasses
[i
% num
];
2202 /* Unions are similar to RECORD_TYPE but offset is always 0. */
2203 else if (TREE_CODE (type
) == UNION_TYPE
2204 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
2206 /* For classes first merge in the field of the subclasses. */
2207 if (TYPE_BINFO (type
))
2209 tree binfo
, base_binfo
;
2212 for (binfo
= TYPE_BINFO (type
), basenum
= 0;
2213 BINFO_BASE_ITERATE (binfo
, basenum
, base_binfo
); basenum
++)
2216 int offset
= tree_low_cst (BINFO_OFFSET (base_binfo
), 0) * 8;
2217 tree type
= BINFO_TYPE (base_binfo
);
2219 num
= classify_argument (TYPE_MODE (type
),
2221 (offset
+ (bit_offset
% 64)) % 256);
2224 for (i
= 0; i
< num
; i
++)
2226 int pos
= (offset
+ (bit_offset
% 64)) / 8 / 8;
2228 merge_classes (subclasses
[i
], classes
[i
+ pos
]);
2232 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
2234 if (TREE_CODE (field
) == FIELD_DECL
)
2237 num
= classify_argument (TYPE_MODE (TREE_TYPE (field
)),
2238 TREE_TYPE (field
), subclasses
,
2242 for (i
= 0; i
< num
; i
++)
2243 classes
[i
] = merge_classes (subclasses
[i
], classes
[i
]);
2247 else if (TREE_CODE (type
) == SET_TYPE
)
2251 classes
[0] = X86_64_INTEGERSI_CLASS
;
2254 else if (bytes
<= 8)
2256 classes
[0] = X86_64_INTEGER_CLASS
;
2259 else if (bytes
<= 12)
2261 classes
[0] = X86_64_INTEGER_CLASS
;
2262 classes
[1] = X86_64_INTEGERSI_CLASS
;
2267 classes
[0] = X86_64_INTEGER_CLASS
;
2268 classes
[1] = X86_64_INTEGER_CLASS
;
2275 /* Final merger cleanup. */
2276 for (i
= 0; i
< words
; i
++)
2278 /* If one class is MEMORY, everything should be passed in
2280 if (classes
[i
] == X86_64_MEMORY_CLASS
)
2283 /* The X86_64_SSEUP_CLASS should be always preceded by
2284 X86_64_SSE_CLASS. */
2285 if (classes
[i
] == X86_64_SSEUP_CLASS
2286 && (i
== 0 || classes
[i
- 1] != X86_64_SSE_CLASS
))
2287 classes
[i
] = X86_64_SSE_CLASS
;
2289 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
2290 if (classes
[i
] == X86_64_X87UP_CLASS
2291 && (i
== 0 || classes
[i
- 1] != X86_64_X87_CLASS
))
2292 classes
[i
] = X86_64_SSE_CLASS
;
2297 /* Compute alignment needed. We align all types to natural boundaries with
2298 exception of XFmode that is aligned to 64bits. */
2299 if (mode
!= VOIDmode
&& mode
!= BLKmode
)
2301 int mode_alignment
= GET_MODE_BITSIZE (mode
);
2304 mode_alignment
= 128;
2305 else if (mode
== XCmode
)
2306 mode_alignment
= 256;
2307 if (COMPLEX_MODE_P (mode
))
2308 mode_alignment
/= 2;
2309 /* Misaligned fields are always returned in memory. */
2310 if (bit_offset
% mode_alignment
)
2314 /* for V1xx modes, just use the base mode */
2315 if (VECTOR_MODE_P (mode
)
2316 && GET_MODE_SIZE (GET_MODE_INNER (mode
)) == bytes
)
2317 mode
= GET_MODE_INNER (mode
);
2319 /* Classification of atomic types. */
2329 if (bit_offset
+ GET_MODE_BITSIZE (mode
) <= 32)
2330 classes
[0] = X86_64_INTEGERSI_CLASS
;
2332 classes
[0] = X86_64_INTEGER_CLASS
;
2336 classes
[0] = classes
[1] = X86_64_INTEGER_CLASS
;
2341 if (!(bit_offset
% 64))
2342 classes
[0] = X86_64_SSESF_CLASS
;
2344 classes
[0] = X86_64_SSE_CLASS
;
2347 classes
[0] = X86_64_SSEDF_CLASS
;
2350 classes
[0] = X86_64_X87_CLASS
;
2351 classes
[1] = X86_64_X87UP_CLASS
;
2354 classes
[0] = X86_64_SSE_CLASS
;
2355 classes
[1] = X86_64_SSEUP_CLASS
;
2358 classes
[0] = X86_64_SSE_CLASS
;
2361 classes
[0] = X86_64_SSEDF_CLASS
;
2362 classes
[1] = X86_64_SSEDF_CLASS
;
2366 /* These modes are larger than 16 bytes. */
2374 classes
[0] = X86_64_SSE_CLASS
;
2375 classes
[1] = X86_64_SSEUP_CLASS
;
2381 classes
[0] = X86_64_SSE_CLASS
;
2387 if (VECTOR_MODE_P (mode
))
2391 if (GET_MODE_CLASS (GET_MODE_INNER (mode
)) == MODE_INT
)
2393 if (bit_offset
+ GET_MODE_BITSIZE (mode
) <= 32)
2394 classes
[0] = X86_64_INTEGERSI_CLASS
;
2396 classes
[0] = X86_64_INTEGER_CLASS
;
2397 classes
[1] = X86_64_INTEGER_CLASS
;
2398 return 1 + (bytes
> 8);
2405 /* Examine the argument and return set number of register required in each
2406 class. Return 0 iff parameter should be passed in memory. */
2408 examine_argument (enum machine_mode mode
, tree type
, int in_return
,
2409 int *int_nregs
, int *sse_nregs
)
2411 enum x86_64_reg_class
class[MAX_CLASSES
];
2412 int n
= classify_argument (mode
, type
, class, 0);
2418 for (n
--; n
>= 0; n
--)
2421 case X86_64_INTEGER_CLASS
:
2422 case X86_64_INTEGERSI_CLASS
:
2425 case X86_64_SSE_CLASS
:
2426 case X86_64_SSESF_CLASS
:
2427 case X86_64_SSEDF_CLASS
:
2430 case X86_64_NO_CLASS
:
2431 case X86_64_SSEUP_CLASS
:
2433 case X86_64_X87_CLASS
:
2434 case X86_64_X87UP_CLASS
:
2438 case X86_64_MEMORY_CLASS
:
2443 /* Construct container for the argument used by GCC interface. See
2444 FUNCTION_ARG for the detailed description. */
2446 construct_container (enum machine_mode mode
, tree type
, int in_return
,
2447 int nintregs
, int nsseregs
, const int * intreg
,
2450 enum machine_mode tmpmode
;
2452 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2453 enum x86_64_reg_class
class[MAX_CLASSES
];
2457 int needed_sseregs
, needed_intregs
;
2458 rtx exp
[MAX_CLASSES
];
2461 n
= classify_argument (mode
, type
, class, 0);
2462 if (TARGET_DEBUG_ARG
)
2465 fprintf (stderr
, "Memory class\n");
2468 fprintf (stderr
, "Classes:");
2469 for (i
= 0; i
< n
; i
++)
2471 fprintf (stderr
, " %s", x86_64_reg_class_name
[class[i
]]);
2473 fprintf (stderr
, "\n");
2478 if (!examine_argument (mode
, type
, in_return
, &needed_intregs
, &needed_sseregs
))
2480 if (needed_intregs
> nintregs
|| needed_sseregs
> nsseregs
)
2483 /* First construct simple cases. Avoid SCmode, since we want to use
2484 single register to pass this type. */
2485 if (n
== 1 && mode
!= SCmode
)
2488 case X86_64_INTEGER_CLASS
:
2489 case X86_64_INTEGERSI_CLASS
:
2490 return gen_rtx_REG (mode
, intreg
[0]);
2491 case X86_64_SSE_CLASS
:
2492 case X86_64_SSESF_CLASS
:
2493 case X86_64_SSEDF_CLASS
:
2494 return gen_rtx_REG (mode
, SSE_REGNO (sse_regno
));
2495 case X86_64_X87_CLASS
:
2496 return gen_rtx_REG (mode
, FIRST_STACK_REG
);
2497 case X86_64_NO_CLASS
:
2498 /* Zero sized array, struct or class. */
2503 if (n
== 2 && class[0] == X86_64_SSE_CLASS
&& class[1] == X86_64_SSEUP_CLASS
2505 return gen_rtx_REG (mode
, SSE_REGNO (sse_regno
));
2507 && class[0] == X86_64_X87_CLASS
&& class[1] == X86_64_X87UP_CLASS
)
2508 return gen_rtx_REG (XFmode
, FIRST_STACK_REG
);
2509 if (n
== 2 && class[0] == X86_64_INTEGER_CLASS
2510 && class[1] == X86_64_INTEGER_CLASS
2511 && (mode
== CDImode
|| mode
== TImode
|| mode
== TFmode
)
2512 && intreg
[0] + 1 == intreg
[1])
2513 return gen_rtx_REG (mode
, intreg
[0]);
2515 && class[0] == X86_64_X87_CLASS
&& class[1] == X86_64_X87UP_CLASS
2516 && class[2] == X86_64_X87_CLASS
&& class[3] == X86_64_X87UP_CLASS
2518 return gen_rtx_REG (XCmode
, FIRST_STACK_REG
);
2520 /* Otherwise figure out the entries of the PARALLEL. */
2521 for (i
= 0; i
< n
; i
++)
2525 case X86_64_NO_CLASS
:
2527 case X86_64_INTEGER_CLASS
:
2528 case X86_64_INTEGERSI_CLASS
:
2529 /* Merge TImodes on aligned occasions here too. */
2530 if (i
* 8 + 8 > bytes
)
2531 tmpmode
= mode_for_size ((bytes
- i
* 8) * BITS_PER_UNIT
, MODE_INT
, 0);
2532 else if (class[i
] == X86_64_INTEGERSI_CLASS
)
2536 /* We've requested 24 bytes we don't have mode for. Use DImode. */
2537 if (tmpmode
== BLKmode
)
2539 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2540 gen_rtx_REG (tmpmode
, *intreg
),
2544 case X86_64_SSESF_CLASS
:
2545 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2546 gen_rtx_REG (SFmode
,
2547 SSE_REGNO (sse_regno
)),
2551 case X86_64_SSEDF_CLASS
:
2552 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2553 gen_rtx_REG (DFmode
,
2554 SSE_REGNO (sse_regno
)),
2558 case X86_64_SSE_CLASS
:
2559 if (i
< n
- 1 && class[i
+ 1] == X86_64_SSEUP_CLASS
)
2563 exp
[nexps
++] = gen_rtx_EXPR_LIST (VOIDmode
,
2564 gen_rtx_REG (tmpmode
,
2565 SSE_REGNO (sse_regno
)),
2567 if (tmpmode
== TImode
)
2575 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nexps
));
2576 for (i
= 0; i
< nexps
; i
++)
2577 XVECEXP (ret
, 0, i
) = exp
[i
];
2581 /* Update the data in CUM to advance over an argument
2582 of mode MODE and data type TYPE.
2583 (TYPE is null for libcalls where that information may not be available.) */
2586 function_arg_advance (CUMULATIVE_ARGS
*cum
, /* current arg information */
2587 enum machine_mode mode
, /* current arg mode */
2588 tree type
, /* type of the argument or 0 if lib support */
2589 int named
) /* whether or not the argument was named */
2592 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2593 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2595 if (TARGET_DEBUG_ARG
)
2597 "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, mode=%s, named=%d)\n\n",
2598 words
, cum
->words
, cum
->nregs
, cum
->sse_nregs
, GET_MODE_NAME (mode
), named
);
2601 int int_nregs
, sse_nregs
;
2602 if (!examine_argument (mode
, type
, 0, &int_nregs
, &sse_nregs
))
2603 cum
->words
+= words
;
2604 else if (sse_nregs
<= cum
->sse_nregs
&& int_nregs
<= cum
->nregs
)
2606 cum
->nregs
-= int_nregs
;
2607 cum
->sse_nregs
-= sse_nregs
;
2608 cum
->regno
+= int_nregs
;
2609 cum
->sse_regno
+= sse_nregs
;
2612 cum
->words
+= words
;
2616 if (TARGET_SSE
&& SSE_REG_MODE_P (mode
)
2617 && (!type
|| !AGGREGATE_TYPE_P (type
)))
2619 cum
->sse_words
+= words
;
2620 cum
->sse_nregs
-= 1;
2621 cum
->sse_regno
+= 1;
2622 if (cum
->sse_nregs
<= 0)
2628 else if (TARGET_MMX
&& MMX_REG_MODE_P (mode
)
2629 && (!type
|| !AGGREGATE_TYPE_P (type
)))
2631 cum
->mmx_words
+= words
;
2632 cum
->mmx_nregs
-= 1;
2633 cum
->mmx_regno
+= 1;
2634 if (cum
->mmx_nregs
<= 0)
2642 cum
->words
+= words
;
2643 cum
->nregs
-= words
;
2644 cum
->regno
+= words
;
2646 if (cum
->nregs
<= 0)
2656 /* Define where to put the arguments to a function.
2657 Value is zero to push the argument on the stack,
2658 or a hard register in which to store the argument.
2660 MODE is the argument's machine mode.
2661 TYPE is the data type of the argument (as a tree).
2662 This is null for libcalls where that information may
2664 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2665 the preceding args and about the function being called.
2666 NAMED is nonzero if this argument is a named parameter
2667 (otherwise it is an extra parameter matching an ellipsis). */
2670 function_arg (CUMULATIVE_ARGS
*cum
, /* current arg information */
2671 enum machine_mode mode
, /* current arg mode */
2672 tree type
, /* type of the argument or 0 if lib support */
2673 int named
) /* != 0 for normal args, == 0 for ... args */
2677 (mode
== BLKmode
) ? int_size_in_bytes (type
) : (int) GET_MODE_SIZE (mode
);
2678 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2679 static bool warnedsse
, warnedmmx
;
2681 /* To simplify the code below, represent vector types with a vector mode
2682 even if MMX/SSE are not active. */
2684 && TREE_CODE (type
) == VECTOR_TYPE
2685 && (bytes
== 8 || bytes
== 16)
2686 && GET_MODE_CLASS (TYPE_MODE (type
)) != MODE_VECTOR_INT
2687 && GET_MODE_CLASS (TYPE_MODE (type
)) != MODE_VECTOR_FLOAT
)
2689 enum machine_mode innermode
= TYPE_MODE (TREE_TYPE (type
));
2690 enum machine_mode newmode
2691 = TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
2692 ? MIN_MODE_VECTOR_FLOAT
: MIN_MODE_VECTOR_INT
;
2694 /* Get the mode which has this inner mode and number of units. */
2695 for (; newmode
!= VOIDmode
; newmode
= GET_MODE_WIDER_MODE (newmode
))
2696 if (GET_MODE_NUNITS (newmode
) == TYPE_VECTOR_SUBPARTS (type
)
2697 && GET_MODE_INNER (newmode
) == innermode
)
2704 /* Handle a hidden AL argument containing number of registers for varargs
2705 x86-64 functions. For i386 ABI just return constm1_rtx to avoid
2707 if (mode
== VOIDmode
)
2710 return GEN_INT (cum
->maybe_vaarg
2711 ? (cum
->sse_nregs
< 0
2719 ret
= construct_container (mode
, type
, 0, cum
->nregs
, cum
->sse_nregs
,
2720 &x86_64_int_parameter_registers
[cum
->regno
],
2725 /* For now, pass fp/complex values on the stack. */
2737 if (words
<= cum
->nregs
)
2739 int regno
= cum
->regno
;
2741 /* Fastcall allocates the first two DWORD (SImode) or
2742 smaller arguments to ECX and EDX. */
2745 if (mode
== BLKmode
|| mode
== DImode
)
2748 /* ECX not EAX is the first allocated register. */
2752 ret
= gen_rtx_REG (mode
, regno
);
2762 if (!type
|| !AGGREGATE_TYPE_P (type
))
2764 if (!TARGET_SSE
&& !warnedsse
&& cum
->warn_sse
)
2767 warning ("SSE vector argument without SSE enabled "
2771 ret
= gen_rtx_REG (mode
, cum
->sse_regno
+ FIRST_SSE_REG
);
2778 if (!type
|| !AGGREGATE_TYPE_P (type
))
2780 if (!TARGET_MMX
&& !warnedmmx
&& cum
->warn_mmx
)
2783 warning ("MMX vector argument without MMX enabled "
2787 ret
= gen_rtx_REG (mode
, cum
->mmx_regno
+ FIRST_MMX_REG
);
2792 if (TARGET_DEBUG_ARG
)
2795 "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
2796 words
, cum
->words
, cum
->nregs
, GET_MODE_NAME (mode
), named
);
2799 print_simple_rtl (stderr
, ret
);
2801 fprintf (stderr
, ", stack");
2803 fprintf (stderr
, " )\n");
2809 /* A C expression that indicates when an argument must be passed by
2810 reference. If nonzero for an argument, a copy of that argument is
2811 made in memory and a pointer to the argument is passed instead of
2812 the argument itself. The pointer is passed in whatever way is
2813 appropriate for passing a pointer to that type. */
2816 ix86_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
2817 enum machine_mode mode ATTRIBUTE_UNUSED
,
2818 tree type
, bool named ATTRIBUTE_UNUSED
)
2823 if (type
&& int_size_in_bytes (type
) == -1)
2825 if (TARGET_DEBUG_ARG
)
2826 fprintf (stderr
, "function_arg_pass_by_reference\n");
2833 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
2834 ABI. Only called if TARGET_SSE. */
2836 contains_128bit_aligned_vector_p (tree type
)
2838 enum machine_mode mode
= TYPE_MODE (type
);
2839 if (SSE_REG_MODE_P (mode
)
2840 && (!TYPE_USER_ALIGN (type
) || TYPE_ALIGN (type
) > 128))
2842 if (TYPE_ALIGN (type
) < 128)
2845 if (AGGREGATE_TYPE_P (type
))
2847 /* Walk the aggregates recursively. */
2848 if (TREE_CODE (type
) == RECORD_TYPE
2849 || TREE_CODE (type
) == UNION_TYPE
2850 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
2854 if (TYPE_BINFO (type
))
2856 tree binfo
, base_binfo
;
2859 for (binfo
= TYPE_BINFO (type
), i
= 0;
2860 BINFO_BASE_ITERATE (binfo
, i
, base_binfo
); i
++)
2861 if (contains_128bit_aligned_vector_p (BINFO_TYPE (base_binfo
)))
2864 /* And now merge the fields of structure. */
2865 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
2867 if (TREE_CODE (field
) == FIELD_DECL
2868 && contains_128bit_aligned_vector_p (TREE_TYPE (field
)))
2872 /* Just for use if some languages passes arrays by value. */
2873 else if (TREE_CODE (type
) == ARRAY_TYPE
)
2875 if (contains_128bit_aligned_vector_p (TREE_TYPE (type
)))
2884 /* Gives the alignment boundary, in bits, of an argument with the
2885 specified mode and type. */
2888 ix86_function_arg_boundary (enum machine_mode mode
, tree type
)
2892 align
= TYPE_ALIGN (type
);
2894 align
= GET_MODE_ALIGNMENT (mode
);
2895 if (align
< PARM_BOUNDARY
)
2896 align
= PARM_BOUNDARY
;
2899 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
2900 make an exception for SSE modes since these require 128bit
2903 The handling here differs from field_alignment. ICC aligns MMX
2904 arguments to 4 byte boundaries, while structure fields are aligned
2905 to 8 byte boundaries. */
2907 align
= PARM_BOUNDARY
;
2910 if (!SSE_REG_MODE_P (mode
))
2911 align
= PARM_BOUNDARY
;
2915 if (!contains_128bit_aligned_vector_p (type
))
2916 align
= PARM_BOUNDARY
;
2924 /* Return true if N is a possible register number of function value. */
2926 ix86_function_value_regno_p (int regno
)
2930 return ((regno
) == 0
2931 || ((regno
) == FIRST_FLOAT_REG
&& TARGET_FLOAT_RETURNS_IN_80387
)
2932 || ((regno
) == FIRST_SSE_REG
&& TARGET_SSE
));
2934 return ((regno
) == 0 || (regno
) == FIRST_FLOAT_REG
2935 || ((regno
) == FIRST_SSE_REG
&& TARGET_SSE
)
2936 || ((regno
) == FIRST_FLOAT_REG
&& TARGET_FLOAT_RETURNS_IN_80387
));
2939 /* Define how to find the value returned by a function.
2940 VALTYPE is the data type of the value (as a tree).
2941 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2942 otherwise, FUNC is 0. */
2944 ix86_function_value (tree valtype
)
2948 rtx ret
= construct_container (TYPE_MODE (valtype
), valtype
, 1,
2949 REGPARM_MAX
, SSE_REGPARM_MAX
,
2950 x86_64_int_return_registers
, 0);
2951 /* For zero sized structures, construct_container return NULL, but we need
2952 to keep rest of compiler happy by returning meaningful value. */
2954 ret
= gen_rtx_REG (TYPE_MODE (valtype
), 0);
2958 return gen_rtx_REG (TYPE_MODE (valtype
),
2959 ix86_value_regno (TYPE_MODE (valtype
)));
2962 /* Return false iff type is returned in memory. */
2964 ix86_return_in_memory (tree type
)
2966 int needed_intregs
, needed_sseregs
, size
;
2967 enum machine_mode mode
= TYPE_MODE (type
);
2970 return !examine_argument (mode
, type
, 1, &needed_intregs
, &needed_sseregs
);
2972 if (mode
== BLKmode
)
2975 size
= int_size_in_bytes (type
);
2977 if (MS_AGGREGATE_RETURN
&& AGGREGATE_TYPE_P (type
) && size
<= 8)
2980 if (VECTOR_MODE_P (mode
) || mode
== TImode
)
2982 /* User-created vectors small enough to fit in EAX. */
2986 /* MMX/3dNow values are returned on the stack, since we've
2987 got to EMMS/FEMMS before returning. */
2991 /* SSE values are returned in XMM0, except when it doesn't exist. */
2993 return (TARGET_SSE
? 0 : 1);
3004 /* When returning SSE vector types, we have a choice of either
3005 (1) being abi incompatible with a -march switch, or
3006 (2) generating an error.
3007 Given no good solution, I think the safest thing is one warning.
3008 The user won't be able to use -Werror, but....
3010 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
3011 called in response to actually generating a caller or callee that
3012 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
3013 via aggregate_value_p for general type probing from tree-ssa. */
3016 ix86_struct_value_rtx (tree type
, int incoming ATTRIBUTE_UNUSED
)
3020 if (!TARGET_SSE
&& type
&& !warned
)
3022 /* Look at the return type of the function, not the function type. */
3023 enum machine_mode mode
= TYPE_MODE (TREE_TYPE (type
));
3026 || (VECTOR_MODE_P (mode
) && GET_MODE_SIZE (mode
) == 16))
3029 warning ("SSE vector return without SSE enabled changes the ABI");
3036 /* Define how to find the value returned by a library function
3037 assuming the value has mode MODE. */
3039 ix86_libcall_value (enum machine_mode mode
)
3050 return gen_rtx_REG (mode
, FIRST_SSE_REG
);
3052 return gen_rtx_REG (mode
, FIRST_FLOAT_REG
);
3057 return gen_rtx_REG (mode
, 0);
3061 return gen_rtx_REG (mode
, ix86_value_regno (mode
));
3064 /* Given a mode, return the register to use for a return value. */
3067 ix86_value_regno (enum machine_mode mode
)
3069 /* Floating point return values in %st(0). */
3070 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& TARGET_FLOAT_RETURNS_IN_80387
)
3071 return FIRST_FLOAT_REG
;
3072 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
3073 we prevent this case when sse is not available. */
3074 if (mode
== TImode
|| (VECTOR_MODE_P (mode
) && GET_MODE_SIZE (mode
) == 16))
3075 return FIRST_SSE_REG
;
3076 /* Everything else in %eax. */
3080 /* Create the va_list data type. */
3083 ix86_build_builtin_va_list (void)
3085 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
3087 /* For i386 we use plain pointer to argument area. */
3089 return build_pointer_type (char_type_node
);
3091 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
3092 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
3094 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("gp_offset"),
3095 unsigned_type_node
);
3096 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("fp_offset"),
3097 unsigned_type_node
);
3098 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("overflow_arg_area"),
3100 f_sav
= build_decl (FIELD_DECL
, get_identifier ("reg_save_area"),
3103 DECL_FIELD_CONTEXT (f_gpr
) = record
;
3104 DECL_FIELD_CONTEXT (f_fpr
) = record
;
3105 DECL_FIELD_CONTEXT (f_ovf
) = record
;
3106 DECL_FIELD_CONTEXT (f_sav
) = record
;
3108 TREE_CHAIN (record
) = type_decl
;
3109 TYPE_NAME (record
) = type_decl
;
3110 TYPE_FIELDS (record
) = f_gpr
;
3111 TREE_CHAIN (f_gpr
) = f_fpr
;
3112 TREE_CHAIN (f_fpr
) = f_ovf
;
3113 TREE_CHAIN (f_ovf
) = f_sav
;
3115 layout_type (record
);
3117 /* The correct type is an array type of one element. */
3118 return build_array_type (record
, build_index_type (size_zero_node
));
3121 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
3124 ix86_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3125 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
3128 CUMULATIVE_ARGS next_cum
;
3129 rtx save_area
= NULL_RTX
, mem
;
3142 /* Indicate to allocate space on the stack for varargs save area. */
3143 ix86_save_varrargs_registers
= 1;
3145 cfun
->stack_alignment_needed
= 128;
3147 fntype
= TREE_TYPE (current_function_decl
);
3148 stdarg_p
= (TYPE_ARG_TYPES (fntype
) != 0
3149 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
3150 != void_type_node
));
3152 /* For varargs, we do not want to skip the dummy va_dcl argument.
3153 For stdargs, we do want to skip the last named argument. */
3156 function_arg_advance (&next_cum
, mode
, type
, 1);
3159 save_area
= frame_pointer_rtx
;
3161 set
= get_varargs_alias_set ();
3163 for (i
= next_cum
.regno
; i
< ix86_regparm
; i
++)
3165 mem
= gen_rtx_MEM (Pmode
,
3166 plus_constant (save_area
, i
* UNITS_PER_WORD
));
3167 set_mem_alias_set (mem
, set
);
3168 emit_move_insn (mem
, gen_rtx_REG (Pmode
,
3169 x86_64_int_parameter_registers
[i
]));
3172 if (next_cum
.sse_nregs
)
3174 /* Now emit code to save SSE registers. The AX parameter contains number
3175 of SSE parameter registers used to call this function. We use
3176 sse_prologue_save insn template that produces computed jump across
3177 SSE saves. We need some preparation work to get this working. */
3179 label
= gen_label_rtx ();
3180 label_ref
= gen_rtx_LABEL_REF (Pmode
, label
);
3182 /* Compute address to jump to :
3183 label - 5*eax + nnamed_sse_arguments*5 */
3184 tmp_reg
= gen_reg_rtx (Pmode
);
3185 nsse_reg
= gen_reg_rtx (Pmode
);
3186 emit_insn (gen_zero_extendqidi2 (nsse_reg
, gen_rtx_REG (QImode
, 0)));
3187 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
,
3188 gen_rtx_MULT (Pmode
, nsse_reg
,
3190 if (next_cum
.sse_regno
)
3193 gen_rtx_CONST (DImode
,
3194 gen_rtx_PLUS (DImode
,
3196 GEN_INT (next_cum
.sse_regno
* 4))));
3198 emit_move_insn (nsse_reg
, label_ref
);
3199 emit_insn (gen_subdi3 (nsse_reg
, nsse_reg
, tmp_reg
));
3201 /* Compute address of memory block we save into. We always use pointer
3202 pointing 127 bytes after first byte to store - this is needed to keep
3203 instruction size limited by 4 bytes. */
3204 tmp_reg
= gen_reg_rtx (Pmode
);
3205 emit_insn (gen_rtx_SET (VOIDmode
, tmp_reg
,
3206 plus_constant (save_area
,
3207 8 * REGPARM_MAX
+ 127)));
3208 mem
= gen_rtx_MEM (BLKmode
, plus_constant (tmp_reg
, -127));
3209 set_mem_alias_set (mem
, set
);
3210 set_mem_align (mem
, BITS_PER_WORD
);
3212 /* And finally do the dirty job! */
3213 emit_insn (gen_sse_prologue_save (mem
, nsse_reg
,
3214 GEN_INT (next_cum
.sse_regno
), label
));
3219 /* Implement va_start. */
3222 ix86_va_start (tree valist
, rtx nextarg
)
3224 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
3225 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
3226 tree gpr
, fpr
, ovf
, sav
, t
;
3228 /* Only 64bit target needs something special. */
3231 std_expand_builtin_va_start (valist
, nextarg
);
3235 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
3236 f_fpr
= TREE_CHAIN (f_gpr
);
3237 f_ovf
= TREE_CHAIN (f_fpr
);
3238 f_sav
= TREE_CHAIN (f_ovf
);
3240 valist
= build1 (INDIRECT_REF
, TREE_TYPE (TREE_TYPE (valist
)), valist
);
3241 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
3242 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
3243 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
3244 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
3246 /* Count number of gp and fp argument registers used. */
3247 words
= current_function_args_info
.words
;
3248 n_gpr
= current_function_args_info
.regno
;
3249 n_fpr
= current_function_args_info
.sse_regno
;
3251 if (TARGET_DEBUG_ARG
)
3252 fprintf (stderr
, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
3253 (int) words
, (int) n_gpr
, (int) n_fpr
);
3255 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
3256 build_int_cst (NULL_TREE
, n_gpr
* 8));
3257 TREE_SIDE_EFFECTS (t
) = 1;
3258 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3260 t
= build (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
3261 build_int_cst (NULL_TREE
, n_fpr
* 16 + 8*REGPARM_MAX
));
3262 TREE_SIDE_EFFECTS (t
) = 1;
3263 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3265 /* Find the overflow area. */
3266 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
3268 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), t
,
3269 build_int_cst (NULL_TREE
, words
* UNITS_PER_WORD
));
3270 t
= build (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
3271 TREE_SIDE_EFFECTS (t
) = 1;
3272 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3274 /* Find the register save area.
3275 Prologue of the function save it right above stack frame. */
3276 t
= make_tree (TREE_TYPE (sav
), frame_pointer_rtx
);
3277 t
= build (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
3278 TREE_SIDE_EFFECTS (t
) = 1;
3279 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3282 /* Implement va_arg. */
3285 ix86_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
3287 static const int intreg
[6] = { 0, 1, 2, 3, 4, 5 };
3288 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
3289 tree gpr
, fpr
, ovf
, sav
, t
;
3291 tree lab_false
, lab_over
= NULL_TREE
;
3297 /* Only 64bit target needs something special. */
3299 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
3301 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
3302 f_fpr
= TREE_CHAIN (f_gpr
);
3303 f_ovf
= TREE_CHAIN (f_fpr
);
3304 f_sav
= TREE_CHAIN (f_ovf
);
3306 valist
= build_va_arg_indirect_ref (valist
);
3307 gpr
= build (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
3308 fpr
= build (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
3309 ovf
= build (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
3310 sav
= build (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
3312 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
3314 type
= build_pointer_type (type
);
3315 size
= int_size_in_bytes (type
);
3316 rsize
= (size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3318 container
= construct_container (TYPE_MODE (type
), type
, 0,
3319 REGPARM_MAX
, SSE_REGPARM_MAX
, intreg
, 0);
3321 * Pull the value out of the saved registers ...
3324 addr
= create_tmp_var (ptr_type_node
, "addr");
3325 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
3329 int needed_intregs
, needed_sseregs
;
3331 tree int_addr
, sse_addr
;
3333 lab_false
= create_artificial_label ();
3334 lab_over
= create_artificial_label ();
3336 examine_argument (TYPE_MODE (type
), type
, 0,
3337 &needed_intregs
, &needed_sseregs
);
3339 need_temp
= (!REG_P (container
)
3340 && ((needed_intregs
&& TYPE_ALIGN (type
) > 64)
3341 || TYPE_ALIGN (type
) > 128));
3343 /* In case we are passing structure, verify that it is consecutive block
3344 on the register save area. If not we need to do moves. */
3345 if (!need_temp
&& !REG_P (container
))
3347 /* Verify that all registers are strictly consecutive */
3348 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container
, 0, 0), 0))))
3352 for (i
= 0; i
< XVECLEN (container
, 0) && !need_temp
; i
++)
3354 rtx slot
= XVECEXP (container
, 0, i
);
3355 if (REGNO (XEXP (slot
, 0)) != FIRST_SSE_REG
+ (unsigned int) i
3356 || INTVAL (XEXP (slot
, 1)) != i
* 16)
3364 for (i
= 0; i
< XVECLEN (container
, 0) && !need_temp
; i
++)
3366 rtx slot
= XVECEXP (container
, 0, i
);
3367 if (REGNO (XEXP (slot
, 0)) != (unsigned int) i
3368 || INTVAL (XEXP (slot
, 1)) != i
* 8)
3380 int_addr
= create_tmp_var (ptr_type_node
, "int_addr");
3381 DECL_POINTER_ALIAS_SET (int_addr
) = get_varargs_alias_set ();
3382 sse_addr
= create_tmp_var (ptr_type_node
, "sse_addr");
3383 DECL_POINTER_ALIAS_SET (sse_addr
) = get_varargs_alias_set ();
3385 /* First ensure that we fit completely in registers. */
3388 t
= build_int_cst (TREE_TYPE (gpr
),
3389 (REGPARM_MAX
- needed_intregs
+ 1) * 8);
3390 t
= build2 (GE_EXPR
, boolean_type_node
, gpr
, t
);
3391 t2
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
3392 t
= build (COND_EXPR
, void_type_node
, t
, t2
, NULL_TREE
);
3393 gimplify_and_add (t
, pre_p
);
3397 t
= build_int_cst (TREE_TYPE (fpr
),
3398 (SSE_REGPARM_MAX
- needed_sseregs
+ 1) * 16
3400 t
= build2 (GE_EXPR
, boolean_type_node
, fpr
, t
);
3401 t2
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
3402 t
= build (COND_EXPR
, void_type_node
, t
, t2
, NULL_TREE
);
3403 gimplify_and_add (t
, pre_p
);
3406 /* Compute index to start of area used for integer regs. */
3409 /* int_addr = gpr + sav; */
3410 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, gpr
);
3411 t
= build2 (MODIFY_EXPR
, void_type_node
, int_addr
, t
);
3412 gimplify_and_add (t
, pre_p
);
3416 /* sse_addr = fpr + sav; */
3417 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
, fpr
);
3418 t
= build2 (MODIFY_EXPR
, void_type_node
, sse_addr
, t
);
3419 gimplify_and_add (t
, pre_p
);
3424 tree temp
= create_tmp_var (type
, "va_arg_tmp");
3427 t
= build1 (ADDR_EXPR
, build_pointer_type (type
), temp
);
3428 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
3429 gimplify_and_add (t
, pre_p
);
3431 for (i
= 0; i
< XVECLEN (container
, 0); i
++)
3433 rtx slot
= XVECEXP (container
, 0, i
);
3434 rtx reg
= XEXP (slot
, 0);
3435 enum machine_mode mode
= GET_MODE (reg
);
3436 tree piece_type
= lang_hooks
.types
.type_for_mode (mode
, 1);
3437 tree addr_type
= build_pointer_type (piece_type
);
3440 tree dest_addr
, dest
;
3442 if (SSE_REGNO_P (REGNO (reg
)))
3444 src_addr
= sse_addr
;
3445 src_offset
= (REGNO (reg
) - FIRST_SSE_REG
) * 16;
3449 src_addr
= int_addr
;
3450 src_offset
= REGNO (reg
) * 8;
3452 src_addr
= fold_convert (addr_type
, src_addr
);
3453 src_addr
= fold (build2 (PLUS_EXPR
, addr_type
, src_addr
,
3454 size_int (src_offset
)));
3455 src
= build_va_arg_indirect_ref (src_addr
);
3457 dest_addr
= fold_convert (addr_type
, addr
);
3458 dest_addr
= fold (build2 (PLUS_EXPR
, addr_type
, dest_addr
,
3459 size_int (INTVAL (XEXP (slot
, 1)))));
3460 dest
= build_va_arg_indirect_ref (dest_addr
);
3462 t
= build2 (MODIFY_EXPR
, void_type_node
, dest
, src
);
3463 gimplify_and_add (t
, pre_p
);
3469 t
= build2 (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
3470 build_int_cst (NULL_TREE
, needed_intregs
* 8));
3471 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
3472 gimplify_and_add (t
, pre_p
);
3476 t
= build2 (PLUS_EXPR
, TREE_TYPE (fpr
), fpr
,
3477 build_int_cst (NULL_TREE
, needed_sseregs
* 16));
3478 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
, t
);
3479 gimplify_and_add (t
, pre_p
);
3482 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
3483 gimplify_and_add (t
, pre_p
);
3485 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
3486 append_to_statement_list (t
, pre_p
);
3489 /* ... otherwise out of the overflow area. */
3491 /* Care for on-stack alignment if needed. */
3492 if (FUNCTION_ARG_BOUNDARY (VOIDmode
, type
) <= 64)
3496 HOST_WIDE_INT align
= FUNCTION_ARG_BOUNDARY (VOIDmode
, type
) / 8;
3497 t
= build (PLUS_EXPR
, TREE_TYPE (ovf
), ovf
,
3498 build_int_cst (NULL_TREE
, align
- 1));
3499 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
3500 build_int_cst (NULL_TREE
, -align
));
3502 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
3504 t2
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
3505 gimplify_and_add (t2
, pre_p
);
3507 t
= build2 (PLUS_EXPR
, TREE_TYPE (t
), t
,
3508 build_int_cst (NULL_TREE
, rsize
* UNITS_PER_WORD
));
3509 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
3510 gimplify_and_add (t
, pre_p
);
3514 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
3515 append_to_statement_list (t
, pre_p
);
3518 ptrtype
= build_pointer_type (type
);
3519 addr
= fold_convert (ptrtype
, addr
);
3522 addr
= build_va_arg_indirect_ref (addr
);
3523 return build_va_arg_indirect_ref (addr
);
3526 /* Return nonzero if OPNUM's MEM should be matched
3527 in movabs* patterns. */
3530 ix86_check_movabs (rtx insn
, int opnum
)
3534 set
= PATTERN (insn
);
3535 if (GET_CODE (set
) == PARALLEL
)
3536 set
= XVECEXP (set
, 0, 0);
3537 if (GET_CODE (set
) != SET
)
3539 mem
= XEXP (set
, opnum
);
3540 while (GET_CODE (mem
) == SUBREG
)
3541 mem
= SUBREG_REG (mem
);
3542 if (GET_CODE (mem
) != MEM
)
3544 return (volatile_ok
|| !MEM_VOLATILE_P (mem
));
3547 /* Initialize the table of extra 80387 mathematical constants. */
3550 init_ext_80387_constants (void)
3552 static const char * cst
[5] =
3554 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
3555 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
3556 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
3557 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
3558 "3.1415926535897932385128089594061862044", /* 4: fldpi */
3562 for (i
= 0; i
< 5; i
++)
3564 real_from_string (&ext_80387_constants_table
[i
], cst
[i
]);
3565 /* Ensure each constant is rounded to XFmode precision. */
3566 real_convert (&ext_80387_constants_table
[i
],
3567 XFmode
, &ext_80387_constants_table
[i
]);
3570 ext_80387_constants_init
= 1;
3573 /* Return true if the constant is something that can be loaded with
3574 a special instruction. */
3577 standard_80387_constant_p (rtx x
)
3579 if (GET_CODE (x
) != CONST_DOUBLE
|| !FLOAT_MODE_P (GET_MODE (x
)))
3582 if (x
== CONST0_RTX (GET_MODE (x
)))
3584 if (x
== CONST1_RTX (GET_MODE (x
)))
3587 /* For XFmode constants, try to find a special 80387 instruction when
3588 optimizing for size or on those CPUs that benefit from them. */
3589 if (GET_MODE (x
) == XFmode
3590 && (optimize_size
|| x86_ext_80387_constants
& TUNEMASK
))
3595 if (! ext_80387_constants_init
)
3596 init_ext_80387_constants ();
3598 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3599 for (i
= 0; i
< 5; i
++)
3600 if (real_identical (&r
, &ext_80387_constants_table
[i
]))
3607 /* Return the opcode of the special instruction to be used to load
3611 standard_80387_constant_opcode (rtx x
)
3613 switch (standard_80387_constant_p (x
))
3633 /* Return the CONST_DOUBLE representing the 80387 constant that is
3634 loaded by the specified special instruction. The argument IDX
3635 matches the return value from standard_80387_constant_p. */
3638 standard_80387_constant_rtx (int idx
)
3642 if (! ext_80387_constants_init
)
3643 init_ext_80387_constants ();
3659 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table
[i
],
3663 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
3666 standard_sse_constant_p (rtx x
)
3668 if (x
== const0_rtx
)
3670 return (x
== CONST0_RTX (GET_MODE (x
)));
3673 /* Returns 1 if OP contains a symbol reference */
3676 symbolic_reference_mentioned_p (rtx op
)
3681 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
3684 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3685 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3691 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3692 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3696 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
3703 /* Return 1 if it is appropriate to emit `ret' instructions in the
3704 body of a function. Do this only if the epilogue is simple, needing a
3705 couple of insns. Prior to reloading, we can't tell how many registers
3706 must be saved, so return 0 then. Return 0 if there is no frame
3707 marker to de-allocate.
3709 If NON_SAVING_SETJMP is defined and true, then it is not possible
3710 for the epilogue to be simple, so return 0. This is a special case
3711 since NON_SAVING_SETJMP will not cause regs_ever_live to change
3712 until final, but jump_optimize may need to know sooner if a
3716 ix86_can_use_return_insn_p (void)
3718 struct ix86_frame frame
;
3720 #ifdef NON_SAVING_SETJMP
3721 if (NON_SAVING_SETJMP
&& current_function_calls_setjmp
)
3725 if (! reload_completed
|| frame_pointer_needed
)
3728 /* Don't allow more than 32 pop, since that's all we can do
3729 with one instruction. */
3730 if (current_function_pops_args
3731 && current_function_args_size
>= 32768)
3734 ix86_compute_frame_layout (&frame
);
3735 return frame
.to_allocate
== 0 && frame
.nregs
== 0;
3738 /* Value should be nonzero if functions must have frame pointers.
3739 Zero means the frame pointer need not be set up (and parms may
3740 be accessed via the stack pointer) in functions that seem suitable. */
3743 ix86_frame_pointer_required (void)
3745 /* If we accessed previous frames, then the generated code expects
3746 to be able to access the saved ebp value in our frame. */
3747 if (cfun
->machine
->accesses_prev_frame
)
3750 /* Several x86 os'es need a frame pointer for other reasons,
3751 usually pertaining to setjmp. */
3752 if (SUBTARGET_FRAME_POINTER_REQUIRED
)
3755 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
3756 the frame pointer by default. Turn it back on now if we've not
3757 got a leaf function. */
3758 if (TARGET_OMIT_LEAF_FRAME_POINTER
3759 && (!current_function_is_leaf
))
3762 if (current_function_profile
)
3768 /* Record that the current function accesses previous call frames. */
3771 ix86_setup_frame_addresses (void)
3773 cfun
->machine
->accesses_prev_frame
= 1;
3776 #if defined(HAVE_GAS_HIDDEN) && defined(SUPPORTS_ONE_ONLY)
3777 # define USE_HIDDEN_LINKONCE 1
3779 # define USE_HIDDEN_LINKONCE 0
3782 static int pic_labels_used
;
3784 /* Fills in the label name that should be used for a pc thunk for
3785 the given register. */
3788 get_pc_thunk_name (char name
[32], unsigned int regno
)
3790 if (USE_HIDDEN_LINKONCE
)
3791 sprintf (name
, "__i686.get_pc_thunk.%s", reg_names
[regno
]);
3793 ASM_GENERATE_INTERNAL_LABEL (name
, "LPR", regno
);
3797 /* This function generates code for -fpic that loads %ebx with
3798 the return address of the caller and then returns. */
3801 ix86_file_end (void)
3806 for (regno
= 0; regno
< 8; ++regno
)
3810 if (! ((pic_labels_used
>> regno
) & 1))
3813 get_pc_thunk_name (name
, regno
);
3815 if (USE_HIDDEN_LINKONCE
)
3819 decl
= build_decl (FUNCTION_DECL
, get_identifier (name
),
3821 TREE_PUBLIC (decl
) = 1;
3822 TREE_STATIC (decl
) = 1;
3823 DECL_ONE_ONLY (decl
) = 1;
3825 (*targetm
.asm_out
.unique_section
) (decl
, 0);
3826 named_section (decl
, NULL
, 0);
3828 (*targetm
.asm_out
.globalize_label
) (asm_out_file
, name
);
3829 fputs ("\t.hidden\t", asm_out_file
);
3830 assemble_name (asm_out_file
, name
);
3831 fputc ('\n', asm_out_file
);
3832 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
3837 ASM_OUTPUT_LABEL (asm_out_file
, name
);
3840 xops
[0] = gen_rtx_REG (SImode
, regno
);
3841 xops
[1] = gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3842 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops
);
3843 output_asm_insn ("ret", xops
);
3846 if (NEED_INDICATE_EXEC_STACK
)
3847 file_end_indicate_exec_stack ();
3850 /* Emit code for the SET_GOT patterns. */
3853 output_set_got (rtx dest
)
3858 xops
[1] = gen_rtx_SYMBOL_REF (Pmode
, GOT_SYMBOL_NAME
);
3860 if (! TARGET_DEEP_BRANCH_PREDICTION
|| !flag_pic
)
3862 xops
[2] = gen_rtx_LABEL_REF (Pmode
, gen_label_rtx ());
3865 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops
);
3867 output_asm_insn ("call\t%a2", xops
);
3870 /* Output the "canonical" label name ("Lxx$pb") here too. This
3871 is what will be referred to by the Mach-O PIC subsystem. */
3872 ASM_OUTPUT_LABEL (asm_out_file
, machopic_function_base_name ());
3874 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
3875 CODE_LABEL_NUMBER (XEXP (xops
[2], 0)));
3878 output_asm_insn ("pop{l}\t%0", xops
);
3883 get_pc_thunk_name (name
, REGNO (dest
));
3884 pic_labels_used
|= 1 << REGNO (dest
);
3886 xops
[2] = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3887 xops
[2] = gen_rtx_MEM (QImode
, xops
[2]);
3888 output_asm_insn ("call\t%X2", xops
);
3891 if (!flag_pic
|| TARGET_DEEP_BRANCH_PREDICTION
)
3892 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops
);
3893 else if (!TARGET_MACHO
)
3894 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %a1+(.-%a2)}", xops
);
3899 /* Generate an "push" pattern for input ARG. */
3904 return gen_rtx_SET (VOIDmode
,
3906 gen_rtx_PRE_DEC (Pmode
,
3907 stack_pointer_rtx
)),
3911 /* Return >= 0 if there is an unused call-clobbered register available
3912 for the entire function. */
3915 ix86_select_alt_pic_regnum (void)
3917 if (current_function_is_leaf
&& !current_function_profile
)
3920 for (i
= 2; i
>= 0; --i
)
3921 if (!regs_ever_live
[i
])
3925 return INVALID_REGNUM
;
3928 /* Return 1 if we need to save REGNO. */
3930 ix86_save_reg (unsigned int regno
, int maybe_eh_return
)
3932 if (pic_offset_table_rtx
3933 && regno
== REAL_PIC_OFFSET_TABLE_REGNUM
3934 && (regs_ever_live
[REAL_PIC_OFFSET_TABLE_REGNUM
]
3935 || current_function_profile
3936 || current_function_calls_eh_return
3937 || current_function_uses_const_pool
))
3939 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM
)
3944 if (current_function_calls_eh_return
&& maybe_eh_return
)
3949 unsigned test
= EH_RETURN_DATA_REGNO (i
);
3950 if (test
== INVALID_REGNUM
)
3957 return (regs_ever_live
[regno
]
3958 && !call_used_regs
[regno
]
3959 && !fixed_regs
[regno
]
3960 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
));
3963 /* Return number of registers to be saved on the stack. */
3966 ix86_nsaved_regs (void)
3971 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
3972 if (ix86_save_reg (regno
, true))
3977 /* Return the offset between two registers, one to be eliminated, and the other
3978 its replacement, at the start of a routine. */
3981 ix86_initial_elimination_offset (int from
, int to
)
3983 struct ix86_frame frame
;
3984 ix86_compute_frame_layout (&frame
);
3986 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
3987 return frame
.hard_frame_pointer_offset
;
3988 else if (from
== FRAME_POINTER_REGNUM
3989 && to
== HARD_FRAME_POINTER_REGNUM
)
3990 return frame
.hard_frame_pointer_offset
- frame
.frame_pointer_offset
;
3993 if (to
!= STACK_POINTER_REGNUM
)
3995 else if (from
== ARG_POINTER_REGNUM
)
3996 return frame
.stack_pointer_offset
;
3997 else if (from
!= FRAME_POINTER_REGNUM
)
4000 return frame
.stack_pointer_offset
- frame
.frame_pointer_offset
;
4004 /* Fill structure ix86_frame about frame of currently computed function. */
4007 ix86_compute_frame_layout (struct ix86_frame
*frame
)
4009 HOST_WIDE_INT total_size
;
4010 unsigned int stack_alignment_needed
;
4011 HOST_WIDE_INT offset
;
4012 unsigned int preferred_alignment
;
4013 HOST_WIDE_INT size
= get_frame_size ();
4015 frame
->nregs
= ix86_nsaved_regs ();
4018 stack_alignment_needed
= cfun
->stack_alignment_needed
/ BITS_PER_UNIT
;
4019 preferred_alignment
= cfun
->preferred_stack_boundary
/ BITS_PER_UNIT
;
4021 /* During reload iteration the amount of registers saved can change.
4022 Recompute the value as needed. Do not recompute when amount of registers
4023 didn't change as reload does mutiple calls to the function and does not
4024 expect the decision to change within single iteration. */
4026 && cfun
->machine
->use_fast_prologue_epilogue_nregs
!= frame
->nregs
)
4028 int count
= frame
->nregs
;
4030 cfun
->machine
->use_fast_prologue_epilogue_nregs
= count
;
4031 /* The fast prologue uses move instead of push to save registers. This
4032 is significantly longer, but also executes faster as modern hardware
4033 can execute the moves in parallel, but can't do that for push/pop.
4035 Be careful about choosing what prologue to emit: When function takes
4036 many instructions to execute we may use slow version as well as in
4037 case function is known to be outside hot spot (this is known with
4038 feedback only). Weight the size of function by number of registers
4039 to save as it is cheap to use one or two push instructions but very
4040 slow to use many of them. */
4042 count
= (count
- 1) * FAST_PROLOGUE_INSN_COUNT
;
4043 if (cfun
->function_frequency
< FUNCTION_FREQUENCY_NORMAL
4044 || (flag_branch_probabilities
4045 && cfun
->function_frequency
< FUNCTION_FREQUENCY_HOT
))
4046 cfun
->machine
->use_fast_prologue_epilogue
= false;
4048 cfun
->machine
->use_fast_prologue_epilogue
4049 = !expensive_function_p (count
);
4051 if (TARGET_PROLOGUE_USING_MOVE
4052 && cfun
->machine
->use_fast_prologue_epilogue
)
4053 frame
->save_regs_using_mov
= true;
4055 frame
->save_regs_using_mov
= false;
4058 /* Skip return address and saved base pointer. */
4059 offset
= frame_pointer_needed
? UNITS_PER_WORD
* 2 : UNITS_PER_WORD
;
4061 frame
->hard_frame_pointer_offset
= offset
;
4063 /* Do some sanity checking of stack_alignment_needed and
4064 preferred_alignment, since i386 port is the only using those features
4065 that may break easily. */
4067 if (size
&& !stack_alignment_needed
)
4069 if (preferred_alignment
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
4071 if (preferred_alignment
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
4073 if (stack_alignment_needed
> PREFERRED_STACK_BOUNDARY
/ BITS_PER_UNIT
)
4076 if (stack_alignment_needed
< STACK_BOUNDARY
/ BITS_PER_UNIT
)
4077 stack_alignment_needed
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4079 /* Register save area */
4080 offset
+= frame
->nregs
* UNITS_PER_WORD
;
4083 if (ix86_save_varrargs_registers
)
4085 offset
+= X86_64_VARARGS_SIZE
;
4086 frame
->va_arg_size
= X86_64_VARARGS_SIZE
;
4089 frame
->va_arg_size
= 0;
4091 /* Align start of frame for local function. */
4092 frame
->padding1
= ((offset
+ stack_alignment_needed
- 1)
4093 & -stack_alignment_needed
) - offset
;
4095 offset
+= frame
->padding1
;
4097 /* Frame pointer points here. */
4098 frame
->frame_pointer_offset
= offset
;
4102 /* Add outgoing arguments area. Can be skipped if we eliminated
4103 all the function calls as dead code.
4104 Skipping is however impossible when function calls alloca. Alloca
4105 expander assumes that last current_function_outgoing_args_size
4106 of stack frame are unused. */
4107 if (ACCUMULATE_OUTGOING_ARGS
4108 && (!current_function_is_leaf
|| current_function_calls_alloca
))
4110 offset
+= current_function_outgoing_args_size
;
4111 frame
->outgoing_arguments_size
= current_function_outgoing_args_size
;
4114 frame
->outgoing_arguments_size
= 0;
4116 /* Align stack boundary. Only needed if we're calling another function
4118 if (!current_function_is_leaf
|| current_function_calls_alloca
)
4119 frame
->padding2
= ((offset
+ preferred_alignment
- 1)
4120 & -preferred_alignment
) - offset
;
4122 frame
->padding2
= 0;
4124 offset
+= frame
->padding2
;
4126 /* We've reached end of stack frame. */
4127 frame
->stack_pointer_offset
= offset
;
4129 /* Size prologue needs to allocate. */
4130 frame
->to_allocate
=
4131 (size
+ frame
->padding1
+ frame
->padding2
4132 + frame
->outgoing_arguments_size
+ frame
->va_arg_size
);
4134 if ((!frame
->to_allocate
&& frame
->nregs
<= 1)
4135 || (TARGET_64BIT
&& frame
->to_allocate
>= (HOST_WIDE_INT
) 0x80000000))
4136 frame
->save_regs_using_mov
= false;
4138 if (TARGET_RED_ZONE
&& current_function_sp_is_unchanging
4139 && current_function_is_leaf
)
4141 frame
->red_zone_size
= frame
->to_allocate
;
4142 if (frame
->save_regs_using_mov
)
4143 frame
->red_zone_size
+= frame
->nregs
* UNITS_PER_WORD
;
4144 if (frame
->red_zone_size
> RED_ZONE_SIZE
- RED_ZONE_RESERVE
)
4145 frame
->red_zone_size
= RED_ZONE_SIZE
- RED_ZONE_RESERVE
;
4148 frame
->red_zone_size
= 0;
4149 frame
->to_allocate
-= frame
->red_zone_size
;
4150 frame
->stack_pointer_offset
-= frame
->red_zone_size
;
4152 fprintf (stderr
, "nregs: %i\n", frame
->nregs
);
4153 fprintf (stderr
, "size: %i\n", size
);
4154 fprintf (stderr
, "alignment1: %i\n", stack_alignment_needed
);
4155 fprintf (stderr
, "padding1: %i\n", frame
->padding1
);
4156 fprintf (stderr
, "va_arg: %i\n", frame
->va_arg_size
);
4157 fprintf (stderr
, "padding2: %i\n", frame
->padding2
);
4158 fprintf (stderr
, "to_allocate: %i\n", frame
->to_allocate
);
4159 fprintf (stderr
, "red_zone_size: %i\n", frame
->red_zone_size
);
4160 fprintf (stderr
, "frame_pointer_offset: %i\n", frame
->frame_pointer_offset
);
4161 fprintf (stderr
, "hard_frame_pointer_offset: %i\n",
4162 frame
->hard_frame_pointer_offset
);
4163 fprintf (stderr
, "stack_pointer_offset: %i\n", frame
->stack_pointer_offset
);
4167 /* Emit code to save registers in the prologue. */
4170 ix86_emit_save_regs (void)
4175 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
--)
4176 if (ix86_save_reg (regno
, true))
4178 insn
= emit_insn (gen_push (gen_rtx_REG (Pmode
, regno
)));
4179 RTX_FRAME_RELATED_P (insn
) = 1;
4183 /* Emit code to save registers using MOV insns. First register
4184 is restored from POINTER + OFFSET. */
4186 ix86_emit_save_regs_using_mov (rtx pointer
, HOST_WIDE_INT offset
)
4191 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4192 if (ix86_save_reg (regno
, true))
4194 insn
= emit_move_insn (adjust_address (gen_rtx_MEM (Pmode
, pointer
),
4196 gen_rtx_REG (Pmode
, regno
));
4197 RTX_FRAME_RELATED_P (insn
) = 1;
4198 offset
+= UNITS_PER_WORD
;
4202 /* Expand prologue or epilogue stack adjustment.
4203 The pattern exist to put a dependency on all ebp-based memory accesses.
4204 STYLE should be negative if instructions should be marked as frame related,
4205 zero if %r11 register is live and cannot be freely used and positive
4209 pro_epilogue_adjust_stack (rtx dest
, rtx src
, rtx offset
, int style
)
4214 insn
= emit_insn (gen_pro_epilogue_adjust_stack_1 (dest
, src
, offset
));
4215 else if (x86_64_immediate_operand (offset
, DImode
))
4216 insn
= emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest
, src
, offset
));
4220 /* r11 is used by indirect sibcall return as well, set before the
4221 epilogue and used after the epilogue. ATM indirect sibcall
4222 shouldn't be used together with huge frame sizes in one
4223 function because of the frame_size check in sibcall.c. */
4226 r11
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
4227 insn
= emit_insn (gen_rtx_SET (DImode
, r11
, offset
));
4229 RTX_FRAME_RELATED_P (insn
) = 1;
4230 insn
= emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest
, src
, r11
,
4234 RTX_FRAME_RELATED_P (insn
) = 1;
4237 /* Expand the prologue into a bunch of separate insns. */
4240 ix86_expand_prologue (void)
4244 struct ix86_frame frame
;
4245 HOST_WIDE_INT allocate
;
4247 ix86_compute_frame_layout (&frame
);
4249 /* Note: AT&T enter does NOT have reversed args. Enter is probably
4250 slower on all targets. Also sdb doesn't like it. */
4252 if (frame_pointer_needed
)
4254 insn
= emit_insn (gen_push (hard_frame_pointer_rtx
));
4255 RTX_FRAME_RELATED_P (insn
) = 1;
4257 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
4258 RTX_FRAME_RELATED_P (insn
) = 1;
4261 allocate
= frame
.to_allocate
;
4263 if (!frame
.save_regs_using_mov
)
4264 ix86_emit_save_regs ();
4266 allocate
+= frame
.nregs
* UNITS_PER_WORD
;
4268 /* When using red zone we may start register saving before allocating
4269 the stack frame saving one cycle of the prologue. */
4270 if (TARGET_RED_ZONE
&& frame
.save_regs_using_mov
)
4271 ix86_emit_save_regs_using_mov (frame_pointer_needed
? hard_frame_pointer_rtx
4272 : stack_pointer_rtx
,
4273 -frame
.nregs
* UNITS_PER_WORD
);
4277 else if (! TARGET_STACK_PROBE
|| allocate
< CHECK_STACK_LIMIT
)
4278 pro_epilogue_adjust_stack (stack_pointer_rtx
, stack_pointer_rtx
,
4279 GEN_INT (-allocate
), -1);
4282 /* Only valid for Win32. */
4283 rtx eax
= gen_rtx_REG (SImode
, 0);
4284 bool eax_live
= ix86_eax_live_at_start_p ();
4291 emit_insn (gen_push (eax
));
4295 insn
= emit_move_insn (eax
, GEN_INT (allocate
));
4296 RTX_FRAME_RELATED_P (insn
) = 1;
4298 insn
= emit_insn (gen_allocate_stack_worker (eax
));
4299 RTX_FRAME_RELATED_P (insn
) = 1;
4304 if (frame_pointer_needed
)
4305 t
= plus_constant (hard_frame_pointer_rtx
,
4308 - frame
.nregs
* UNITS_PER_WORD
);
4310 t
= plus_constant (stack_pointer_rtx
, allocate
);
4311 emit_move_insn (eax
, gen_rtx_MEM (SImode
, t
));
4315 if (frame
.save_regs_using_mov
&& !TARGET_RED_ZONE
)
4317 if (!frame_pointer_needed
|| !frame
.to_allocate
)
4318 ix86_emit_save_regs_using_mov (stack_pointer_rtx
, frame
.to_allocate
);
4320 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx
,
4321 -frame
.nregs
* UNITS_PER_WORD
);
4324 pic_reg_used
= false;
4325 if (pic_offset_table_rtx
4326 && (regs_ever_live
[REAL_PIC_OFFSET_TABLE_REGNUM
]
4327 || current_function_profile
))
4329 unsigned int alt_pic_reg_used
= ix86_select_alt_pic_regnum ();
4331 if (alt_pic_reg_used
!= INVALID_REGNUM
)
4332 REGNO (pic_offset_table_rtx
) = alt_pic_reg_used
;
4334 pic_reg_used
= true;
4339 insn
= emit_insn (gen_set_got (pic_offset_table_rtx
));
4341 /* Even with accurate pre-reload life analysis, we can wind up
4342 deleting all references to the pic register after reload.
4343 Consider if cross-jumping unifies two sides of a branch
4344 controlled by a comparison vs the only read from a global.
4345 In which case, allow the set_got to be deleted, though we're
4346 too late to do anything about the ebx save in the prologue. */
4347 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, NULL
);
4350 /* Prevent function calls from be scheduled before the call to mcount.
4351 In the pic_reg_used case, make sure that the got load isn't deleted. */
4352 if (current_function_profile
)
4353 emit_insn (gen_blockage (pic_reg_used
? pic_offset_table_rtx
: const0_rtx
));
4356 /* Emit code to restore saved registers using MOV insns. First register
4357 is restored from POINTER + OFFSET. */
4359 ix86_emit_restore_regs_using_mov (rtx pointer
, HOST_WIDE_INT offset
,
4360 int maybe_eh_return
)
4363 rtx base_address
= gen_rtx_MEM (Pmode
, pointer
);
4365 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4366 if (ix86_save_reg (regno
, maybe_eh_return
))
4368 /* Ensure that adjust_address won't be forced to produce pointer
4369 out of range allowed by x86-64 instruction set. */
4370 if (TARGET_64BIT
&& offset
!= trunc_int_for_mode (offset
, SImode
))
4374 r11
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
4375 emit_move_insn (r11
, GEN_INT (offset
));
4376 emit_insn (gen_adddi3 (r11
, r11
, pointer
));
4377 base_address
= gen_rtx_MEM (Pmode
, r11
);
4380 emit_move_insn (gen_rtx_REG (Pmode
, regno
),
4381 adjust_address (base_address
, Pmode
, offset
));
4382 offset
+= UNITS_PER_WORD
;
4386 /* Restore function stack, frame, and registers. */
4389 ix86_expand_epilogue (int style
)
4392 int sp_valid
= !frame_pointer_needed
|| current_function_sp_is_unchanging
;
4393 struct ix86_frame frame
;
4394 HOST_WIDE_INT offset
;
4396 ix86_compute_frame_layout (&frame
);
4398 /* Calculate start of saved registers relative to ebp. Special care
4399 must be taken for the normal return case of a function using
4400 eh_return: the eax and edx registers are marked as saved, but not
4401 restored along this path. */
4402 offset
= frame
.nregs
;
4403 if (current_function_calls_eh_return
&& style
!= 2)
4405 offset
*= -UNITS_PER_WORD
;
4407 /* If we're only restoring one register and sp is not valid then
4408 using a move instruction to restore the register since it's
4409 less work than reloading sp and popping the register.
4411 The default code result in stack adjustment using add/lea instruction,
4412 while this code results in LEAVE instruction (or discrete equivalent),
4413 so it is profitable in some other cases as well. Especially when there
4414 are no registers to restore. We also use this code when TARGET_USE_LEAVE
4415 and there is exactly one register to pop. This heuristic may need some
4416 tuning in future. */
4417 if ((!sp_valid
&& frame
.nregs
<= 1)
4418 || (TARGET_EPILOGUE_USING_MOVE
4419 && cfun
->machine
->use_fast_prologue_epilogue
4420 && (frame
.nregs
> 1 || frame
.to_allocate
))
4421 || (frame_pointer_needed
&& !frame
.nregs
&& frame
.to_allocate
)
4422 || (frame_pointer_needed
&& TARGET_USE_LEAVE
4423 && cfun
->machine
->use_fast_prologue_epilogue
4424 && frame
.nregs
== 1)
4425 || current_function_calls_eh_return
)
4427 /* Restore registers. We can use ebp or esp to address the memory
4428 locations. If both are available, default to ebp, since offsets
4429 are known to be small. Only exception is esp pointing directly to the
4430 end of block of saved registers, where we may simplify addressing
4433 if (!frame_pointer_needed
|| (sp_valid
&& !frame
.to_allocate
))
4434 ix86_emit_restore_regs_using_mov (stack_pointer_rtx
,
4435 frame
.to_allocate
, style
== 2);
4437 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx
,
4438 offset
, style
== 2);
4440 /* eh_return epilogues need %ecx added to the stack pointer. */
4443 rtx tmp
, sa
= EH_RETURN_STACKADJ_RTX
;
4445 if (frame_pointer_needed
)
4447 tmp
= gen_rtx_PLUS (Pmode
, hard_frame_pointer_rtx
, sa
);
4448 tmp
= plus_constant (tmp
, UNITS_PER_WORD
);
4449 emit_insn (gen_rtx_SET (VOIDmode
, sa
, tmp
));
4451 tmp
= gen_rtx_MEM (Pmode
, hard_frame_pointer_rtx
);
4452 emit_move_insn (hard_frame_pointer_rtx
, tmp
);
4454 pro_epilogue_adjust_stack (stack_pointer_rtx
, sa
,
4459 tmp
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, sa
);
4460 tmp
= plus_constant (tmp
, (frame
.to_allocate
4461 + frame
.nregs
* UNITS_PER_WORD
));
4462 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, tmp
));
4465 else if (!frame_pointer_needed
)
4466 pro_epilogue_adjust_stack (stack_pointer_rtx
, stack_pointer_rtx
,
4467 GEN_INT (frame
.to_allocate
4468 + frame
.nregs
* UNITS_PER_WORD
),
4470 /* If not an i386, mov & pop is faster than "leave". */
4471 else if (TARGET_USE_LEAVE
|| optimize_size
4472 || !cfun
->machine
->use_fast_prologue_epilogue
)
4473 emit_insn (TARGET_64BIT
? gen_leave_rex64 () : gen_leave ());
4476 pro_epilogue_adjust_stack (stack_pointer_rtx
,
4477 hard_frame_pointer_rtx
,
4480 emit_insn (gen_popdi1 (hard_frame_pointer_rtx
));
4482 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
4487 /* First step is to deallocate the stack frame so that we can
4488 pop the registers. */
4491 if (!frame_pointer_needed
)
4493 pro_epilogue_adjust_stack (stack_pointer_rtx
,
4494 hard_frame_pointer_rtx
,
4495 GEN_INT (offset
), style
);
4497 else if (frame
.to_allocate
)
4498 pro_epilogue_adjust_stack (stack_pointer_rtx
, stack_pointer_rtx
,
4499 GEN_INT (frame
.to_allocate
), style
);
4501 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
4502 if (ix86_save_reg (regno
, false))
4505 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode
, regno
)));
4507 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode
, regno
)));
4509 if (frame_pointer_needed
)
4511 /* Leave results in shorter dependency chains on CPUs that are
4512 able to grok it fast. */
4513 if (TARGET_USE_LEAVE
)
4514 emit_insn (TARGET_64BIT
? gen_leave_rex64 () : gen_leave ());
4515 else if (TARGET_64BIT
)
4516 emit_insn (gen_popdi1 (hard_frame_pointer_rtx
));
4518 emit_insn (gen_popsi1 (hard_frame_pointer_rtx
));
4522 /* Sibcall epilogues don't want a return instruction. */
4526 if (current_function_pops_args
&& current_function_args_size
)
4528 rtx popc
= GEN_INT (current_function_pops_args
);
4530 /* i386 can only pop 64K bytes. If asked to pop more, pop
4531 return address, do explicit add, and jump indirectly to the
4534 if (current_function_pops_args
>= 65536)
4536 rtx ecx
= gen_rtx_REG (SImode
, 2);
4538 /* There is no "pascal" calling convention in 64bit ABI. */
4542 emit_insn (gen_popsi1 (ecx
));
4543 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, popc
));
4544 emit_jump_insn (gen_return_indirect_internal (ecx
));
4547 emit_jump_insn (gen_return_pop_internal (popc
));
4550 emit_jump_insn (gen_return_internal ());
4553 /* Reset from the function's potential modifications. */
4556 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
4557 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4559 if (pic_offset_table_rtx
)
4560 REGNO (pic_offset_table_rtx
) = REAL_PIC_OFFSET_TABLE_REGNUM
;
4563 /* Extract the parts of an RTL expression that is a valid memory address
4564 for an instruction. Return 0 if the structure of the address is
4565 grossly off. Return -1 if the address contains ASHIFT, so it is not
4566 strictly valid, but still used for computing length of lea instruction. */
4569 ix86_decompose_address (rtx addr
, struct ix86_address
*out
)
4571 rtx base
= NULL_RTX
;
4572 rtx index
= NULL_RTX
;
4573 rtx disp
= NULL_RTX
;
4574 HOST_WIDE_INT scale
= 1;
4575 rtx scale_rtx
= NULL_RTX
;
4577 enum ix86_address_seg seg
= SEG_DEFAULT
;
4579 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == SUBREG
)
4581 else if (GET_CODE (addr
) == PLUS
)
4591 addends
[n
++] = XEXP (op
, 1);
4594 while (GET_CODE (op
) == PLUS
);
4599 for (i
= n
; i
>= 0; --i
)
4602 switch (GET_CODE (op
))
4607 index
= XEXP (op
, 0);
4608 scale_rtx
= XEXP (op
, 1);
4612 if (XINT (op
, 1) == UNSPEC_TP
4613 && TARGET_TLS_DIRECT_SEG_REFS
4614 && seg
== SEG_DEFAULT
)
4615 seg
= TARGET_64BIT
? SEG_FS
: SEG_GS
;
4644 else if (GET_CODE (addr
) == MULT
)
4646 index
= XEXP (addr
, 0); /* index*scale */
4647 scale_rtx
= XEXP (addr
, 1);
4649 else if (GET_CODE (addr
) == ASHIFT
)
4653 /* We're called for lea too, which implements ashift on occasion. */
4654 index
= XEXP (addr
, 0);
4655 tmp
= XEXP (addr
, 1);
4656 if (GET_CODE (tmp
) != CONST_INT
)
4658 scale
= INTVAL (tmp
);
4659 if ((unsigned HOST_WIDE_INT
) scale
> 3)
4665 disp
= addr
; /* displacement */
4667 /* Extract the integral value of scale. */
4670 if (GET_CODE (scale_rtx
) != CONST_INT
)
4672 scale
= INTVAL (scale_rtx
);
4675 /* Allow arg pointer and stack pointer as index if there is not scaling. */
4676 if (base
&& index
&& scale
== 1
4677 && (index
== arg_pointer_rtx
4678 || index
== frame_pointer_rtx
4679 || (REG_P (index
) && REGNO (index
) == STACK_POINTER_REGNUM
)))
4686 /* Special case: %ebp cannot be encoded as a base without a displacement. */
4687 if ((base
== hard_frame_pointer_rtx
4688 || base
== frame_pointer_rtx
4689 || base
== arg_pointer_rtx
) && !disp
)
4692 /* Special case: on K6, [%esi] makes the instruction vector decoded.
4693 Avoid this by transforming to [%esi+0]. */
4694 if (ix86_tune
== PROCESSOR_K6
&& !optimize_size
4695 && base
&& !index
&& !disp
4697 && REGNO_REG_CLASS (REGNO (base
)) == SIREG
)
4700 /* Special case: encode reg+reg instead of reg*2. */
4701 if (!base
&& index
&& scale
&& scale
== 2)
4702 base
= index
, scale
= 1;
4704 /* Special case: scaling cannot be encoded without base or displacement. */
4705 if (!base
&& !disp
&& index
&& scale
!= 1)
4717 /* Return cost of the memory address x.
4718 For i386, it is better to use a complex address than let gcc copy
4719 the address into a reg and make a new pseudo. But not if the address
4720 requires to two regs - that would mean more pseudos with longer
4723 ix86_address_cost (rtx x
)
4725 struct ix86_address parts
;
4728 if (!ix86_decompose_address (x
, &parts
))
4731 /* More complex memory references are better. */
4732 if (parts
.disp
&& parts
.disp
!= const0_rtx
)
4734 if (parts
.seg
!= SEG_DEFAULT
)
4737 /* Attempt to minimize number of registers in the address. */
4739 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
))
4741 && (!REG_P (parts
.index
)
4742 || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)))
4746 && (!REG_P (parts
.base
) || REGNO (parts
.base
) >= FIRST_PSEUDO_REGISTER
)
4748 && (!REG_P (parts
.index
) || REGNO (parts
.index
) >= FIRST_PSEUDO_REGISTER
)
4749 && parts
.base
!= parts
.index
)
4752 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
4753 since it's predecode logic can't detect the length of instructions
4754 and it degenerates to vector decoded. Increase cost of such
4755 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
4756 to split such addresses or even refuse such addresses at all.
4758 Following addressing modes are affected:
4763 The first and last case may be avoidable by explicitly coding the zero in
4764 memory address, but I don't have AMD-K6 machine handy to check this
4768 && ((!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
!= 1)
4769 || (parts
.disp
&& !parts
.base
&& parts
.index
&& parts
.scale
!= 1)
4770 || (!parts
.disp
&& parts
.base
&& parts
.index
&& parts
.scale
== 1)))
4776 /* If X is a machine specific address (i.e. a symbol or label being
4777 referenced as a displacement from the GOT implemented using an
4778 UNSPEC), then return the base term. Otherwise return X. */
4781 ix86_find_base_term (rtx x
)
4787 if (GET_CODE (x
) != CONST
)
4790 if (GET_CODE (term
) == PLUS
4791 && (GET_CODE (XEXP (term
, 1)) == CONST_INT
4792 || GET_CODE (XEXP (term
, 1)) == CONST_DOUBLE
))
4793 term
= XEXP (term
, 0);
4794 if (GET_CODE (term
) != UNSPEC
4795 || XINT (term
, 1) != UNSPEC_GOTPCREL
)
4798 term
= XVECEXP (term
, 0, 0);
4800 if (GET_CODE (term
) != SYMBOL_REF
4801 && GET_CODE (term
) != LABEL_REF
)
4807 term
= ix86_delegitimize_address (x
);
4809 if (GET_CODE (term
) != SYMBOL_REF
4810 && GET_CODE (term
) != LABEL_REF
)
4816 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
4817 this is used for to form addresses to local data when -fPIC is in
4821 darwin_local_data_pic (rtx disp
)
4823 if (GET_CODE (disp
) == MINUS
)
4825 if (GET_CODE (XEXP (disp
, 0)) == LABEL_REF
4826 || GET_CODE (XEXP (disp
, 0)) == SYMBOL_REF
)
4827 if (GET_CODE (XEXP (disp
, 1)) == SYMBOL_REF
)
4829 const char *sym_name
= XSTR (XEXP (disp
, 1), 0);
4830 if (! strcmp (sym_name
, "<pic base>"))
4838 /* Determine if a given RTX is a valid constant. We already know this
4839 satisfies CONSTANT_P. */
4842 legitimate_constant_p (rtx x
)
4844 switch (GET_CODE (x
))
4849 if (GET_CODE (x
) == PLUS
)
4851 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
4856 if (TARGET_MACHO
&& darwin_local_data_pic (x
))
4859 /* Only some unspecs are valid as "constants". */
4860 if (GET_CODE (x
) == UNSPEC
)
4861 switch (XINT (x
, 1))
4865 return local_exec_symbolic_operand (XVECEXP (x
, 0, 0), Pmode
);
4867 return local_dynamic_symbolic_operand (XVECEXP (x
, 0, 0), Pmode
);
4872 /* We must have drilled down to a symbol. */
4873 if (!symbolic_operand (x
, Pmode
))
4878 /* TLS symbols are never valid. */
4879 if (tls_symbolic_operand (x
, Pmode
))
4887 /* Otherwise we handle everything else in the move patterns. */
4891 /* Determine if it's legal to put X into the constant pool. This
4892 is not possible for the address of thread-local symbols, which
4893 is checked above. */
4896 ix86_cannot_force_const_mem (rtx x
)
4898 return !legitimate_constant_p (x
);
4901 /* Determine if a given RTX is a valid constant address. */
4904 constant_address_p (rtx x
)
4906 return CONSTANT_P (x
) && legitimate_address_p (Pmode
, x
, 1);
4909 /* Nonzero if the constant value X is a legitimate general operand
4910 when generating PIC code. It is given that flag_pic is on and
4911 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
4914 legitimate_pic_operand_p (rtx x
)
4918 switch (GET_CODE (x
))
4921 inner
= XEXP (x
, 0);
4923 /* Only some unspecs are valid as "constants". */
4924 if (GET_CODE (inner
) == UNSPEC
)
4925 switch (XINT (inner
, 1))
4928 return local_exec_symbolic_operand (XVECEXP (inner
, 0, 0), Pmode
);
4936 return legitimate_pic_address_disp_p (x
);
4943 /* Determine if a given CONST RTX is a valid memory displacement
4947 legitimate_pic_address_disp_p (rtx disp
)
4951 /* In 64bit mode we can allow direct addresses of symbols and labels
4952 when they are not dynamic symbols. */
4955 /* TLS references should always be enclosed in UNSPEC. */
4956 if (tls_symbolic_operand (disp
, GET_MODE (disp
)))
4958 if (GET_CODE (disp
) == SYMBOL_REF
4959 && ix86_cmodel
== CM_SMALL_PIC
4960 && SYMBOL_REF_LOCAL_P (disp
))
4962 if (GET_CODE (disp
) == LABEL_REF
)
4964 if (GET_CODE (disp
) == CONST
4965 && GET_CODE (XEXP (disp
, 0)) == PLUS
)
4967 rtx op0
= XEXP (XEXP (disp
, 0), 0);
4968 rtx op1
= XEXP (XEXP (disp
, 0), 1);
4970 /* TLS references should always be enclosed in UNSPEC. */
4971 if (tls_symbolic_operand (op0
, GET_MODE (op0
)))
4973 if (((GET_CODE (op0
) == SYMBOL_REF
4974 && ix86_cmodel
== CM_SMALL_PIC
4975 && SYMBOL_REF_LOCAL_P (op0
))
4976 || GET_CODE (op0
) == LABEL_REF
)
4977 && GET_CODE (op1
) == CONST_INT
4978 && INTVAL (op1
) < 16*1024*1024
4979 && INTVAL (op1
) >= -16*1024*1024)
4983 if (GET_CODE (disp
) != CONST
)
4985 disp
= XEXP (disp
, 0);
4989 /* We are unsafe to allow PLUS expressions. This limit allowed distance
4990 of GOT tables. We should not need these anyway. */
4991 if (GET_CODE (disp
) != UNSPEC
4992 || XINT (disp
, 1) != UNSPEC_GOTPCREL
)
4995 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
4996 && GET_CODE (XVECEXP (disp
, 0, 0)) != LABEL_REF
)
5002 if (GET_CODE (disp
) == PLUS
)
5004 if (GET_CODE (XEXP (disp
, 1)) != CONST_INT
)
5006 disp
= XEXP (disp
, 0);
5010 if (TARGET_MACHO
&& darwin_local_data_pic (disp
))
5013 if (GET_CODE (disp
) != UNSPEC
)
5016 switch (XINT (disp
, 1))
5021 return GET_CODE (XVECEXP (disp
, 0, 0)) == SYMBOL_REF
;
5023 if (GET_CODE (XVECEXP (disp
, 0, 0)) == SYMBOL_REF
5024 || GET_CODE (XVECEXP (disp
, 0, 0)) == LABEL_REF
)
5025 return local_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5027 case UNSPEC_GOTTPOFF
:
5028 case UNSPEC_GOTNTPOFF
:
5029 case UNSPEC_INDNTPOFF
:
5032 return initial_exec_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5034 return local_exec_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5036 return local_dynamic_symbolic_operand (XVECEXP (disp
, 0, 0), Pmode
);
5042 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
5043 memory address for an instruction. The MODE argument is the machine mode
5044 for the MEM expression that wants to use this address.
5046 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
5047 convert common non-canonical forms to canonical form so that they will
5051 legitimate_address_p (enum machine_mode mode
, rtx addr
, int strict
)
5053 struct ix86_address parts
;
5054 rtx base
, index
, disp
;
5055 HOST_WIDE_INT scale
;
5056 const char *reason
= NULL
;
5057 rtx reason_rtx
= NULL_RTX
;
5059 if (TARGET_DEBUG_ADDR
)
5062 "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
5063 GET_MODE_NAME (mode
), strict
);
5067 if (ix86_decompose_address (addr
, &parts
) <= 0)
5069 reason
= "decomposition failed";
5074 index
= parts
.index
;
5076 scale
= parts
.scale
;
5078 /* Validate base register.
5080 Don't allow SUBREG's here, it can lead to spill failures when the base
5081 is one word out of a two word structure, which is represented internally
5088 if (GET_CODE (base
) != REG
)
5090 reason
= "base is not a register";
5094 if (GET_MODE (base
) != Pmode
)
5096 reason
= "base is not in Pmode";
5100 if ((strict
&& ! REG_OK_FOR_BASE_STRICT_P (base
))
5101 || (! strict
&& ! REG_OK_FOR_BASE_NONSTRICT_P (base
)))
5103 reason
= "base is not valid";
5108 /* Validate index register.
5110 Don't allow SUBREG's here, it can lead to spill failures when the index
5111 is one word out of a two word structure, which is represented internally
5118 if (GET_CODE (index
) != REG
)
5120 reason
= "index is not a register";
5124 if (GET_MODE (index
) != Pmode
)
5126 reason
= "index is not in Pmode";
5130 if ((strict
&& ! REG_OK_FOR_INDEX_STRICT_P (index
))
5131 || (! strict
&& ! REG_OK_FOR_INDEX_NONSTRICT_P (index
)))
5133 reason
= "index is not valid";
5138 /* Validate scale factor. */
5141 reason_rtx
= GEN_INT (scale
);
5144 reason
= "scale without index";
5148 if (scale
!= 2 && scale
!= 4 && scale
!= 8)
5150 reason
= "scale is not a valid multiplier";
5155 /* Validate displacement. */
5160 if (GET_CODE (disp
) == CONST
5161 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
)
5162 switch (XINT (XEXP (disp
, 0), 1))
5166 case UNSPEC_GOTPCREL
:
5169 goto is_legitimate_pic
;
5171 case UNSPEC_GOTTPOFF
:
5172 case UNSPEC_GOTNTPOFF
:
5173 case UNSPEC_INDNTPOFF
:
5179 reason
= "invalid address unspec";
5183 else if (flag_pic
&& (SYMBOLIC_CONST (disp
)
5185 && !machopic_operand_p (disp
)
5190 if (TARGET_64BIT
&& (index
|| base
))
5192 /* foo@dtpoff(%rX) is ok. */
5193 if (GET_CODE (disp
) != CONST
5194 || GET_CODE (XEXP (disp
, 0)) != PLUS
5195 || GET_CODE (XEXP (XEXP (disp
, 0), 0)) != UNSPEC
5196 || GET_CODE (XEXP (XEXP (disp
, 0), 1)) != CONST_INT
5197 || (XINT (XEXP (XEXP (disp
, 0), 0), 1) != UNSPEC_DTPOFF
5198 && XINT (XEXP (XEXP (disp
, 0), 0), 1) != UNSPEC_NTPOFF
))
5200 reason
= "non-constant pic memory reference";
5204 else if (! legitimate_pic_address_disp_p (disp
))
5206 reason
= "displacement is an invalid pic construct";
5210 /* This code used to verify that a symbolic pic displacement
5211 includes the pic_offset_table_rtx register.
5213 While this is good idea, unfortunately these constructs may
5214 be created by "adds using lea" optimization for incorrect
5223 This code is nonsensical, but results in addressing
5224 GOT table with pic_offset_table_rtx base. We can't
5225 just refuse it easily, since it gets matched by
5226 "addsi3" pattern, that later gets split to lea in the
5227 case output register differs from input. While this
5228 can be handled by separate addsi pattern for this case
5229 that never results in lea, this seems to be easier and
5230 correct fix for crash to disable this test. */
5232 else if (GET_CODE (disp
) != LABEL_REF
5233 && GET_CODE (disp
) != CONST_INT
5234 && (GET_CODE (disp
) != CONST
5235 || !legitimate_constant_p (disp
))
5236 && (GET_CODE (disp
) != SYMBOL_REF
5237 || !legitimate_constant_p (disp
)))
5239 reason
= "displacement is not constant";
5242 else if (TARGET_64BIT
5243 && !x86_64_immediate_operand (disp
, VOIDmode
))
5245 reason
= "displacement is out of range";
5250 /* Everything looks valid. */
5251 if (TARGET_DEBUG_ADDR
)
5252 fprintf (stderr
, "Success.\n");
5256 if (TARGET_DEBUG_ADDR
)
5258 fprintf (stderr
, "Error: %s\n", reason
);
5259 debug_rtx (reason_rtx
);
5264 /* Return an unique alias set for the GOT. */
5266 static HOST_WIDE_INT
5267 ix86_GOT_alias_set (void)
5269 static HOST_WIDE_INT set
= -1;
5271 set
= new_alias_set ();
5275 /* Return a legitimate reference for ORIG (an address) using the
5276 register REG. If REG is 0, a new pseudo is generated.
5278 There are two types of references that must be handled:
5280 1. Global data references must load the address from the GOT, via
5281 the PIC reg. An insn is emitted to do this load, and the reg is
5284 2. Static data references, constant pool addresses, and code labels
5285 compute the address as an offset from the GOT, whose base is in
5286 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
5287 differentiate them from global data objects. The returned
5288 address is the PIC reg + an unspec constant.
5290 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
5291 reg also appears in the address. */
5294 legitimize_pic_address (rtx orig
, rtx reg
)
5302 reg
= gen_reg_rtx (Pmode
);
5303 /* Use the generic Mach-O PIC machinery. */
5304 return machopic_legitimize_pic_address (orig
, GET_MODE (orig
), reg
);
5307 if (TARGET_64BIT
&& legitimate_pic_address_disp_p (addr
))
5309 else if (!TARGET_64BIT
&& local_symbolic_operand (addr
, Pmode
))
5311 /* This symbol may be referenced via a displacement from the PIC
5312 base address (@GOTOFF). */
5314 if (reload_in_progress
)
5315 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5316 if (GET_CODE (addr
) == CONST
)
5317 addr
= XEXP (addr
, 0);
5318 if (GET_CODE (addr
) == PLUS
)
5320 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (addr
, 0)), UNSPEC_GOTOFF
);
5321 new = gen_rtx_PLUS (Pmode
, new, XEXP (addr
, 1));
5324 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
5325 new = gen_rtx_CONST (Pmode
, new);
5326 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5330 emit_move_insn (reg
, new);
5334 else if (GET_CODE (addr
) == SYMBOL_REF
)
5338 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTPCREL
);
5339 new = gen_rtx_CONST (Pmode
, new);
5340 new = gen_const_mem (Pmode
, new);
5341 set_mem_alias_set (new, ix86_GOT_alias_set ());
5344 reg
= gen_reg_rtx (Pmode
);
5345 /* Use directly gen_movsi, otherwise the address is loaded
5346 into register for CSE. We don't want to CSE this addresses,
5347 instead we CSE addresses from the GOT table, so skip this. */
5348 emit_insn (gen_movsi (reg
, new));
5353 /* This symbol must be referenced via a load from the
5354 Global Offset Table (@GOT). */
5356 if (reload_in_progress
)
5357 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5358 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
5359 new = gen_rtx_CONST (Pmode
, new);
5360 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5361 new = gen_const_mem (Pmode
, new);
5362 set_mem_alias_set (new, ix86_GOT_alias_set ());
5365 reg
= gen_reg_rtx (Pmode
);
5366 emit_move_insn (reg
, new);
5372 if (GET_CODE (addr
) == CONST
)
5374 addr
= XEXP (addr
, 0);
5376 /* We must match stuff we generate before. Assume the only
5377 unspecs that can get here are ours. Not that we could do
5378 anything with them anyway.... */
5379 if (GET_CODE (addr
) == UNSPEC
5380 || (GET_CODE (addr
) == PLUS
5381 && GET_CODE (XEXP (addr
, 0)) == UNSPEC
))
5383 if (GET_CODE (addr
) != PLUS
)
5386 if (GET_CODE (addr
) == PLUS
)
5388 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
5390 /* Check first to see if this is a constant offset from a @GOTOFF
5391 symbol reference. */
5392 if (local_symbolic_operand (op0
, Pmode
)
5393 && GET_CODE (op1
) == CONST_INT
)
5397 if (reload_in_progress
)
5398 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5399 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
5401 new = gen_rtx_PLUS (Pmode
, new, op1
);
5402 new = gen_rtx_CONST (Pmode
, new);
5403 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
5407 emit_move_insn (reg
, new);
5413 if (INTVAL (op1
) < -16*1024*1024
5414 || INTVAL (op1
) >= 16*1024*1024)
5415 new = gen_rtx_PLUS (Pmode
, force_reg (Pmode
, op0
), op1
);
5420 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
5421 new = legitimize_pic_address (XEXP (addr
, 1),
5422 base
== reg
? NULL_RTX
: reg
);
5424 if (GET_CODE (new) == CONST_INT
)
5425 new = plus_constant (base
, INTVAL (new));
5428 if (GET_CODE (new) == PLUS
&& CONSTANT_P (XEXP (new, 1)))
5430 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new, 0));
5431 new = XEXP (new, 1);
5433 new = gen_rtx_PLUS (Pmode
, base
, new);
5441 /* Load the thread pointer. If TO_REG is true, force it into a register. */
5444 get_thread_pointer (int to_reg
)
5448 tp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TP
);
5452 reg
= gen_reg_rtx (Pmode
);
5453 insn
= gen_rtx_SET (VOIDmode
, reg
, tp
);
5454 insn
= emit_insn (insn
);
5459 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
5460 false if we expect this to be used for a memory address and true if
5461 we expect to load the address into a register. */
5464 legitimize_tls_address (rtx x
, enum tls_model model
, int for_mov
)
5466 rtx dest
, base
, off
, pic
;
5471 case TLS_MODEL_GLOBAL_DYNAMIC
:
5472 dest
= gen_reg_rtx (Pmode
);
5475 rtx rax
= gen_rtx_REG (Pmode
, 0), insns
;
5478 emit_call_insn (gen_tls_global_dynamic_64 (rax
, x
));
5479 insns
= get_insns ();
5482 emit_libcall_block (insns
, dest
, rax
, x
);
5485 emit_insn (gen_tls_global_dynamic_32 (dest
, x
));
5488 case TLS_MODEL_LOCAL_DYNAMIC
:
5489 base
= gen_reg_rtx (Pmode
);
5492 rtx rax
= gen_rtx_REG (Pmode
, 0), insns
, note
;
5495 emit_call_insn (gen_tls_local_dynamic_base_64 (rax
));
5496 insns
= get_insns ();
5499 note
= gen_rtx_EXPR_LIST (VOIDmode
, const0_rtx
, NULL
);
5500 note
= gen_rtx_EXPR_LIST (VOIDmode
, ix86_tls_get_addr (), note
);
5501 emit_libcall_block (insns
, base
, rax
, note
);
5504 emit_insn (gen_tls_local_dynamic_base_32 (base
));
5506 off
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), UNSPEC_DTPOFF
);
5507 off
= gen_rtx_CONST (Pmode
, off
);
5509 return gen_rtx_PLUS (Pmode
, base
, off
);
5511 case TLS_MODEL_INITIAL_EXEC
:
5515 type
= UNSPEC_GOTNTPOFF
;
5519 if (reload_in_progress
)
5520 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5521 pic
= pic_offset_table_rtx
;
5522 type
= TARGET_GNU_TLS
? UNSPEC_GOTNTPOFF
: UNSPEC_GOTTPOFF
;
5524 else if (!TARGET_GNU_TLS
)
5526 pic
= gen_reg_rtx (Pmode
);
5527 emit_insn (gen_set_got (pic
));
5528 type
= UNSPEC_GOTTPOFF
;
5533 type
= UNSPEC_INDNTPOFF
;
5536 off
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
), type
);
5537 off
= gen_rtx_CONST (Pmode
, off
);
5539 off
= gen_rtx_PLUS (Pmode
, pic
, off
);
5540 off
= gen_const_mem (Pmode
, off
);
5541 set_mem_alias_set (off
, ix86_GOT_alias_set ());
5543 if (TARGET_64BIT
|| TARGET_GNU_TLS
)
5545 base
= get_thread_pointer (for_mov
|| !TARGET_TLS_DIRECT_SEG_REFS
);
5546 off
= force_reg (Pmode
, off
);
5547 return gen_rtx_PLUS (Pmode
, base
, off
);
5551 base
= get_thread_pointer (true);
5552 dest
= gen_reg_rtx (Pmode
);
5553 emit_insn (gen_subsi3 (dest
, base
, off
));
5557 case TLS_MODEL_LOCAL_EXEC
:
5558 off
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, x
),
5559 (TARGET_64BIT
|| TARGET_GNU_TLS
)
5560 ? UNSPEC_NTPOFF
: UNSPEC_TPOFF
);
5561 off
= gen_rtx_CONST (Pmode
, off
);
5563 if (TARGET_64BIT
|| TARGET_GNU_TLS
)
5565 base
= get_thread_pointer (for_mov
|| !TARGET_TLS_DIRECT_SEG_REFS
);
5566 return gen_rtx_PLUS (Pmode
, base
, off
);
5570 base
= get_thread_pointer (true);
5571 dest
= gen_reg_rtx (Pmode
);
5572 emit_insn (gen_subsi3 (dest
, base
, off
));
5583 /* Try machine-dependent ways of modifying an illegitimate address
5584 to be legitimate. If we find one, return the new, valid address.
5585 This macro is used in only one place: `memory_address' in explow.c.
5587 OLDX is the address as it was before break_out_memory_refs was called.
5588 In some cases it is useful to look at this to decide what needs to be done.
5590 MODE and WIN are passed so that this macro can use
5591 GO_IF_LEGITIMATE_ADDRESS.
5593 It is always safe for this macro to do nothing. It exists to recognize
5594 opportunities to optimize the output.
5596 For the 80386, we handle X+REG by loading X into a register R and
5597 using R+REG. R will go in a general reg and indexing will be used.
5598 However, if REG is a broken-out memory address or multiplication,
5599 nothing needs to be done because REG can certainly go in a general reg.
5601 When -fpic is used, special handling is needed for symbolic references.
5602 See comments by legitimize_pic_address in i386.c for details. */
5605 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
, enum machine_mode mode
)
5610 if (TARGET_DEBUG_ADDR
)
5612 fprintf (stderr
, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
5613 GET_MODE_NAME (mode
));
5617 log
= GET_CODE (x
) == SYMBOL_REF
? SYMBOL_REF_TLS_MODEL (x
) : 0;
5619 return legitimize_tls_address (x
, log
, false);
5620 if (GET_CODE (x
) == CONST
5621 && GET_CODE (XEXP (x
, 0)) == PLUS
5622 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5623 && (log
= SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0))))
5625 rtx t
= legitimize_tls_address (XEXP (XEXP (x
, 0), 0), log
, false);
5626 return gen_rtx_PLUS (Pmode
, t
, XEXP (XEXP (x
, 0), 1));
5629 if (flag_pic
&& SYMBOLIC_CONST (x
))
5630 return legitimize_pic_address (x
, 0);
5632 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
5633 if (GET_CODE (x
) == ASHIFT
5634 && GET_CODE (XEXP (x
, 1)) == CONST_INT
5635 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (x
, 1)))) < 4)
5638 x
= gen_rtx_MULT (Pmode
, force_reg (Pmode
, XEXP (x
, 0)),
5639 GEN_INT (1 << log
));
5642 if (GET_CODE (x
) == PLUS
)
5644 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
5646 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
5647 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
5648 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) < 4)
5651 XEXP (x
, 0) = gen_rtx_MULT (Pmode
,
5652 force_reg (Pmode
, XEXP (XEXP (x
, 0), 0)),
5653 GEN_INT (1 << log
));
5656 if (GET_CODE (XEXP (x
, 1)) == ASHIFT
5657 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5658 && (log
= (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1)))) < 4)
5661 XEXP (x
, 1) = gen_rtx_MULT (Pmode
,
5662 force_reg (Pmode
, XEXP (XEXP (x
, 1), 0)),
5663 GEN_INT (1 << log
));
5666 /* Put multiply first if it isn't already. */
5667 if (GET_CODE (XEXP (x
, 1)) == MULT
)
5669 rtx tmp
= XEXP (x
, 0);
5670 XEXP (x
, 0) = XEXP (x
, 1);
5675 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
5676 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
5677 created by virtual register instantiation, register elimination, and
5678 similar optimizations. */
5679 if (GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
5682 x
= gen_rtx_PLUS (Pmode
,
5683 gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
5684 XEXP (XEXP (x
, 1), 0)),
5685 XEXP (XEXP (x
, 1), 1));
5689 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
5690 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
5691 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
5692 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
5693 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
5694 && CONSTANT_P (XEXP (x
, 1)))
5697 rtx other
= NULL_RTX
;
5699 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5701 constant
= XEXP (x
, 1);
5702 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5704 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
5706 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
5707 other
= XEXP (x
, 1);
5715 x
= gen_rtx_PLUS (Pmode
,
5716 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
5717 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
5718 plus_constant (other
, INTVAL (constant
)));
5722 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
5725 if (GET_CODE (XEXP (x
, 0)) == MULT
)
5728 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
5731 if (GET_CODE (XEXP (x
, 1)) == MULT
)
5734 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
5738 && GET_CODE (XEXP (x
, 1)) == REG
5739 && GET_CODE (XEXP (x
, 0)) == REG
)
5742 if (flag_pic
&& SYMBOLIC_CONST (XEXP (x
, 1)))
5745 x
= legitimize_pic_address (x
, 0);
5748 if (changed
&& legitimate_address_p (mode
, x
, FALSE
))
5751 if (GET_CODE (XEXP (x
, 0)) == REG
)
5753 rtx temp
= gen_reg_rtx (Pmode
);
5754 rtx val
= force_operand (XEXP (x
, 1), temp
);
5756 emit_move_insn (temp
, val
);
5762 else if (GET_CODE (XEXP (x
, 1)) == REG
)
5764 rtx temp
= gen_reg_rtx (Pmode
);
5765 rtx val
= force_operand (XEXP (x
, 0), temp
);
5767 emit_move_insn (temp
, val
);
5777 /* Print an integer constant expression in assembler syntax. Addition
5778 and subtraction are the only arithmetic that may appear in these
5779 expressions. FILE is the stdio stream to write to, X is the rtx, and
5780 CODE is the operand print code from the output string. */
5783 output_pic_addr_const (FILE *file
, rtx x
, int code
)
5787 switch (GET_CODE (x
))
5797 /* Mark the decl as referenced so that cgraph will output the function. */
5798 if (SYMBOL_REF_DECL (x
))
5799 mark_decl_referenced (SYMBOL_REF_DECL (x
));
5801 assemble_name (file
, XSTR (x
, 0));
5802 if (!TARGET_MACHO
&& code
== 'P' && ! SYMBOL_REF_LOCAL_P (x
))
5803 fputs ("@PLT", file
);
5810 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
5811 assemble_name (asm_out_file
, buf
);
5815 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5819 /* This used to output parentheses around the expression,
5820 but that does not work on the 386 (either ATT or BSD assembler). */
5821 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5825 if (GET_MODE (x
) == VOIDmode
)
5827 /* We can use %d if the number is <32 bits and positive. */
5828 if (CONST_DOUBLE_HIGH (x
) || CONST_DOUBLE_LOW (x
) < 0)
5829 fprintf (file
, "0x%lx%08lx",
5830 (unsigned long) CONST_DOUBLE_HIGH (x
),
5831 (unsigned long) CONST_DOUBLE_LOW (x
));
5833 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
));
5836 /* We can't handle floating point constants;
5837 PRINT_OPERAND must handle them. */
5838 output_operand_lossage ("floating constant misused");
5842 /* Some assemblers need integer constants to appear first. */
5843 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5845 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5847 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5849 else if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5851 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5853 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5861 putc (ASSEMBLER_DIALECT
== ASM_INTEL
? '(' : '[', file
);
5862 output_pic_addr_const (file
, XEXP (x
, 0), code
);
5864 output_pic_addr_const (file
, XEXP (x
, 1), code
);
5866 putc (ASSEMBLER_DIALECT
== ASM_INTEL
? ')' : ']', file
);
5870 if (XVECLEN (x
, 0) != 1)
5872 output_pic_addr_const (file
, XVECEXP (x
, 0, 0), code
);
5873 switch (XINT (x
, 1))
5876 fputs ("@GOT", file
);
5879 fputs ("@GOTOFF", file
);
5881 case UNSPEC_GOTPCREL
:
5882 fputs ("@GOTPCREL(%rip)", file
);
5884 case UNSPEC_GOTTPOFF
:
5885 /* FIXME: This might be @TPOFF in Sun ld too. */
5886 fputs ("@GOTTPOFF", file
);
5889 fputs ("@TPOFF", file
);
5893 fputs ("@TPOFF", file
);
5895 fputs ("@NTPOFF", file
);
5898 fputs ("@DTPOFF", file
);
5900 case UNSPEC_GOTNTPOFF
:
5902 fputs ("@GOTTPOFF(%rip)", file
);
5904 fputs ("@GOTNTPOFF", file
);
5906 case UNSPEC_INDNTPOFF
:
5907 fputs ("@INDNTPOFF", file
);
5910 output_operand_lossage ("invalid UNSPEC as operand");
5916 output_operand_lossage ("invalid expression as operand");
5920 /* This is called from dwarfout.c via ASM_OUTPUT_DWARF_ADDR_CONST.
5921 We need to handle our special PIC relocations. */
5924 i386_dwarf_output_addr_const (FILE *file
, rtx x
)
5927 fprintf (file
, "%s", TARGET_64BIT
? ASM_QUAD
: ASM_LONG
);
5931 fprintf (file
, "%s", ASM_LONG
);
5934 output_pic_addr_const (file
, x
, '\0');
5936 output_addr_const (file
, x
);
5940 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
5941 We need to emit DTP-relative relocations. */
5944 i386_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
5946 fputs (ASM_LONG
, file
);
5947 output_addr_const (file
, x
);
5948 fputs ("@DTPOFF", file
);
5954 fputs (", 0", file
);
5961 /* In the name of slightly smaller debug output, and to cater to
5962 general assembler losage, recognize PIC+GOTOFF and turn it back
5963 into a direct symbol reference. */
5966 ix86_delegitimize_address (rtx orig_x
)
5970 if (GET_CODE (x
) == MEM
)
5975 if (GET_CODE (x
) != CONST
5976 || GET_CODE (XEXP (x
, 0)) != UNSPEC
5977 || XINT (XEXP (x
, 0), 1) != UNSPEC_GOTPCREL
5978 || GET_CODE (orig_x
) != MEM
)
5980 return XVECEXP (XEXP (x
, 0), 0, 0);
5983 if (GET_CODE (x
) != PLUS
5984 || GET_CODE (XEXP (x
, 1)) != CONST
)
5987 if (GET_CODE (XEXP (x
, 0)) == REG
5988 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5989 /* %ebx + GOT/GOTOFF */
5991 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5993 /* %ebx + %reg * scale + GOT/GOTOFF */
5995 if (GET_CODE (XEXP (y
, 0)) == REG
5996 && REGNO (XEXP (y
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5998 else if (GET_CODE (XEXP (y
, 1)) == REG
5999 && REGNO (XEXP (y
, 1)) == PIC_OFFSET_TABLE_REGNUM
)
6003 if (GET_CODE (y
) != REG
6004 && GET_CODE (y
) != MULT
6005 && GET_CODE (y
) != ASHIFT
)
6011 x
= XEXP (XEXP (x
, 1), 0);
6012 if (GET_CODE (x
) == UNSPEC
6013 && ((XINT (x
, 1) == UNSPEC_GOT
&& GET_CODE (orig_x
) == MEM
)
6014 || (XINT (x
, 1) == UNSPEC_GOTOFF
&& GET_CODE (orig_x
) != MEM
)))
6017 return gen_rtx_PLUS (Pmode
, y
, XVECEXP (x
, 0, 0));
6018 return XVECEXP (x
, 0, 0);
6021 if (GET_CODE (x
) == PLUS
6022 && GET_CODE (XEXP (x
, 0)) == UNSPEC
6023 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6024 && ((XINT (XEXP (x
, 0), 1) == UNSPEC_GOT
&& GET_CODE (orig_x
) == MEM
)
6025 || (XINT (XEXP (x
, 0), 1) == UNSPEC_GOTOFF
6026 && GET_CODE (orig_x
) != MEM
)))
6028 x
= gen_rtx_PLUS (VOIDmode
, XVECEXP (XEXP (x
, 0), 0, 0), XEXP (x
, 1));
6030 return gen_rtx_PLUS (Pmode
, y
, x
);
6038 put_condition_code (enum rtx_code code
, enum machine_mode mode
, int reverse
,
6043 if (mode
== CCFPmode
|| mode
== CCFPUmode
)
6045 enum rtx_code second_code
, bypass_code
;
6046 ix86_fp_comparison_codes (code
, &bypass_code
, &code
, &second_code
);
6047 if (bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
)
6049 code
= ix86_fp_compare_code_to_integer (code
);
6053 code
= reverse_condition (code
);
6064 if (mode
!= CCmode
&& mode
!= CCNOmode
&& mode
!= CCGCmode
)
6069 /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers.
6070 Those same assemblers have the same but opposite losage on cmov. */
6073 suffix
= fp
? "nbe" : "a";
6076 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
6078 else if (mode
== CCmode
|| mode
== CCGCmode
)
6089 if (mode
== CCNOmode
|| mode
== CCGOCmode
)
6091 else if (mode
== CCmode
|| mode
== CCGCmode
)
6100 suffix
= fp
? "nb" : "ae";
6103 if (mode
!= CCmode
&& mode
!= CCGCmode
&& mode
!= CCNOmode
)
6113 suffix
= fp
? "u" : "p";
6116 suffix
= fp
? "nu" : "np";
6121 fputs (suffix
, file
);
6124 /* Print the name of register X to FILE based on its machine mode and number.
6125 If CODE is 'w', pretend the mode is HImode.
6126 If CODE is 'b', pretend the mode is QImode.
6127 If CODE is 'k', pretend the mode is SImode.
6128 If CODE is 'q', pretend the mode is DImode.
6129 If CODE is 'h', pretend the reg is the `high' byte register.
6130 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
6133 print_reg (rtx x
, int code
, FILE *file
)
6135 if (REGNO (x
) == ARG_POINTER_REGNUM
6136 || REGNO (x
) == FRAME_POINTER_REGNUM
6137 || REGNO (x
) == FLAGS_REG
6138 || REGNO (x
) == FPSR_REG
)
6141 if (ASSEMBLER_DIALECT
== ASM_ATT
|| USER_LABEL_PREFIX
[0] == 0)
6144 if (code
== 'w' || MMX_REG_P (x
))
6146 else if (code
== 'b')
6148 else if (code
== 'k')
6150 else if (code
== 'q')
6152 else if (code
== 'y')
6154 else if (code
== 'h')
6157 code
= GET_MODE_SIZE (GET_MODE (x
));
6159 /* Irritatingly, AMD extended registers use different naming convention
6160 from the normal registers. */
6161 if (REX_INT_REG_P (x
))
6168 error ("extended registers have no high halves");
6171 fprintf (file
, "r%ib", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6174 fprintf (file
, "r%iw", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6177 fprintf (file
, "r%id", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6180 fprintf (file
, "r%i", REGNO (x
) - FIRST_REX_INT_REG
+ 8);
6183 error ("unsupported operand size for extended register");
6191 if (STACK_TOP_P (x
))
6193 fputs ("st(0)", file
);
6200 if (! ANY_FP_REG_P (x
))
6201 putc (code
== 8 && TARGET_64BIT
? 'r' : 'e', file
);
6206 fputs (hi_reg_name
[REGNO (x
)], file
);
6209 if (REGNO (x
) >= ARRAY_SIZE (qi_reg_name
))
6211 fputs (qi_reg_name
[REGNO (x
)], file
);
6214 if (REGNO (x
) >= ARRAY_SIZE (qi_high_reg_name
))
6216 fputs (qi_high_reg_name
[REGNO (x
)], file
);
6223 /* Locate some local-dynamic symbol still in use by this function
6224 so that we can print its name in some tls_local_dynamic_base
6228 get_some_local_dynamic_name (void)
6232 if (cfun
->machine
->some_ld_name
)
6233 return cfun
->machine
->some_ld_name
;
6235 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6237 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
6238 return cfun
->machine
->some_ld_name
;
6244 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
6248 if (GET_CODE (x
) == SYMBOL_REF
6249 && local_dynamic_symbolic_operand (x
, Pmode
))
6251 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
6259 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
6260 C -- print opcode suffix for set/cmov insn.
6261 c -- like C, but print reversed condition
6262 F,f -- likewise, but for floating-point.
6263 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
6265 R -- print the prefix for register names.
6266 z -- print the opcode suffix for the size of the current operand.
6267 * -- print a star (in certain assembler syntax)
6268 A -- print an absolute memory reference.
6269 w -- print the operand as if it's a "word" (HImode) even if it isn't.
6270 s -- print a shift double count, followed by the assemblers argument
6272 b -- print the QImode name of the register for the indicated operand.
6273 %b0 would print %al if operands[0] is reg 0.
6274 w -- likewise, print the HImode name of the register.
6275 k -- likewise, print the SImode name of the register.
6276 q -- likewise, print the DImode name of the register.
6277 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
6278 y -- print "st(0)" instead of "st" as a register.
6279 D -- print condition for SSE cmp instruction.
6280 P -- if PIC, print an @PLT suffix.
6281 X -- don't print any sort of PIC '@' suffix for a symbol.
6282 & -- print some in-use local-dynamic symbol name.
6286 print_operand (FILE *file
, rtx x
, int code
)
6293 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6298 assemble_name (file
, get_some_local_dynamic_name ());
6302 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6304 else if (ASSEMBLER_DIALECT
== ASM_INTEL
)
6306 /* Intel syntax. For absolute addresses, registers should not
6307 be surrounded by braces. */
6308 if (GET_CODE (x
) != REG
)
6311 PRINT_OPERAND (file
, x
, 0);
6319 PRINT_OPERAND (file
, x
, 0);
6324 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6329 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6334 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6339 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6344 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6349 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6354 /* 387 opcodes don't get size suffixes if the operands are
6356 if (STACK_REG_P (x
))
6359 /* Likewise if using Intel opcodes. */
6360 if (ASSEMBLER_DIALECT
== ASM_INTEL
)
6363 /* This is the size of op from size of operand. */
6364 switch (GET_MODE_SIZE (GET_MODE (x
)))
6367 #ifdef HAVE_GAS_FILDS_FISTS
6373 if (GET_MODE (x
) == SFmode
)
6388 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
6390 #ifdef GAS_MNEMONICS
6416 if (GET_CODE (x
) == CONST_INT
|| ! SHIFT_DOUBLE_OMITS_COUNT
)
6418 PRINT_OPERAND (file
, x
, 0);
6424 /* Little bit of braindamage here. The SSE compare instructions
6425 does use completely different names for the comparisons that the
6426 fp conditional moves. */
6427 switch (GET_CODE (x
))
6442 fputs ("unord", file
);
6446 fputs ("neq", file
);
6450 fputs ("nlt", file
);
6454 fputs ("nle", file
);
6457 fputs ("ord", file
);
6465 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
6466 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6468 switch (GET_MODE (x
))
6470 case HImode
: putc ('w', file
); break;
6472 case SFmode
: putc ('l', file
); break;
6474 case DFmode
: putc ('q', file
); break;
6482 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 0, file
);
6485 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
6486 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6489 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 0, 1, file
);
6492 /* Like above, but reverse condition */
6494 /* Check to see if argument to %c is really a constant
6495 and not a condition code which needs to be reversed. */
6496 if (!COMPARISON_P (x
))
6498 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
6501 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 0, file
);
6504 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
6505 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6508 put_condition_code (GET_CODE (x
), GET_MODE (XEXP (x
, 0)), 1, 1, file
);
6514 if (!optimize
|| optimize_size
|| !TARGET_BRANCH_PREDICTION_HINTS
)
6517 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
6520 int pred_val
= INTVAL (XEXP (x
, 0));
6522 if (pred_val
< REG_BR_PROB_BASE
* 45 / 100
6523 || pred_val
> REG_BR_PROB_BASE
* 55 / 100)
6525 int taken
= pred_val
> REG_BR_PROB_BASE
/ 2;
6526 int cputaken
= final_forward_branch_p (current_output_insn
) == 0;
6528 /* Emit hints only in the case default branch prediction
6529 heuristics would fail. */
6530 if (taken
!= cputaken
)
6532 /* We use 3e (DS) prefix for taken branches and
6533 2e (CS) prefix for not taken branches. */
6535 fputs ("ds ; ", file
);
6537 fputs ("cs ; ", file
);
6544 output_operand_lossage ("invalid operand code '%c'", code
);
6548 if (GET_CODE (x
) == REG
)
6549 print_reg (x
, code
, file
);
6551 else if (GET_CODE (x
) == MEM
)
6553 /* No `byte ptr' prefix for call instructions. */
6554 if (ASSEMBLER_DIALECT
== ASM_INTEL
&& code
!= 'X' && code
!= 'P')
6557 switch (GET_MODE_SIZE (GET_MODE (x
)))
6559 case 1: size
= "BYTE"; break;
6560 case 2: size
= "WORD"; break;
6561 case 4: size
= "DWORD"; break;
6562 case 8: size
= "QWORD"; break;
6563 case 12: size
= "XWORD"; break;
6564 case 16: size
= "XMMWORD"; break;
6569 /* Check for explicit size override (codes 'b', 'w' and 'k') */
6572 else if (code
== 'w')
6574 else if (code
== 'k')
6578 fputs (" PTR ", file
);
6582 /* Avoid (%rip) for call operands. */
6583 if (CONSTANT_ADDRESS_P (x
) && code
== 'P'
6584 && GET_CODE (x
) != CONST_INT
)
6585 output_addr_const (file
, x
);
6586 else if (this_is_asm_operands
&& ! address_operand (x
, VOIDmode
))
6587 output_operand_lossage ("invalid constraints for operand");
6592 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
6597 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6598 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
6600 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6602 fprintf (file
, "0x%08lx", l
);
6605 /* These float cases don't actually occur as immediate operands. */
6606 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
6610 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (dstr
), 0, 1);
6611 fprintf (file
, "%s", dstr
);
6614 else if (GET_CODE (x
) == CONST_DOUBLE
6615 && GET_MODE (x
) == XFmode
)
6619 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (dstr
), 0, 1);
6620 fprintf (file
, "%s", dstr
);
6627 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
6629 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6632 else if (GET_CODE (x
) == CONST
|| GET_CODE (x
) == SYMBOL_REF
6633 || GET_CODE (x
) == LABEL_REF
)
6635 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6638 fputs ("OFFSET FLAT:", file
);
6641 if (GET_CODE (x
) == CONST_INT
)
6642 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
6644 output_pic_addr_const (file
, x
, code
);
6646 output_addr_const (file
, x
);
6650 /* Print a memory operand whose address is ADDR. */
6653 print_operand_address (FILE *file
, rtx addr
)
6655 struct ix86_address parts
;
6656 rtx base
, index
, disp
;
6659 if (! ix86_decompose_address (addr
, &parts
))
6663 index
= parts
.index
;
6665 scale
= parts
.scale
;
6673 if (USER_LABEL_PREFIX
[0] == 0)
6675 fputs ((parts
.seg
== SEG_FS
? "fs:" : "gs:"), file
);
6681 if (!base
&& !index
)
6683 /* Displacement only requires special attention. */
6685 if (GET_CODE (disp
) == CONST_INT
)
6687 if (ASSEMBLER_DIALECT
== ASM_INTEL
&& parts
.seg
== SEG_DEFAULT
)
6689 if (USER_LABEL_PREFIX
[0] == 0)
6691 fputs ("ds:", file
);
6693 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (disp
));
6696 output_pic_addr_const (file
, disp
, 0);
6698 output_addr_const (file
, disp
);
6700 /* Use one byte shorter RIP relative addressing for 64bit mode. */
6702 && ((GET_CODE (disp
) == SYMBOL_REF
6703 && ! tls_symbolic_operand (disp
, GET_MODE (disp
)))
6704 || GET_CODE (disp
) == LABEL_REF
6705 || (GET_CODE (disp
) == CONST
6706 && GET_CODE (XEXP (disp
, 0)) == PLUS
6707 && (GET_CODE (XEXP (XEXP (disp
, 0), 0)) == SYMBOL_REF
6708 || GET_CODE (XEXP (XEXP (disp
, 0), 0)) == LABEL_REF
)
6709 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)))
6710 fputs ("(%rip)", file
);
6714 if (ASSEMBLER_DIALECT
== ASM_ATT
)
6719 output_pic_addr_const (file
, disp
, 0);
6720 else if (GET_CODE (disp
) == LABEL_REF
)
6721 output_asm_label (disp
);
6723 output_addr_const (file
, disp
);
6728 print_reg (base
, 0, file
);
6732 print_reg (index
, 0, file
);
6734 fprintf (file
, ",%d", scale
);
6740 rtx offset
= NULL_RTX
;
6744 /* Pull out the offset of a symbol; print any symbol itself. */
6745 if (GET_CODE (disp
) == CONST
6746 && GET_CODE (XEXP (disp
, 0)) == PLUS
6747 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
6749 offset
= XEXP (XEXP (disp
, 0), 1);
6750 disp
= gen_rtx_CONST (VOIDmode
,
6751 XEXP (XEXP (disp
, 0), 0));
6755 output_pic_addr_const (file
, disp
, 0);
6756 else if (GET_CODE (disp
) == LABEL_REF
)
6757 output_asm_label (disp
);
6758 else if (GET_CODE (disp
) == CONST_INT
)
6761 output_addr_const (file
, disp
);
6767 print_reg (base
, 0, file
);
6770 if (INTVAL (offset
) >= 0)
6772 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
6776 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (offset
));
6783 print_reg (index
, 0, file
);
6785 fprintf (file
, "*%d", scale
);
6793 output_addr_const_extra (FILE *file
, rtx x
)
6797 if (GET_CODE (x
) != UNSPEC
)
6800 op
= XVECEXP (x
, 0, 0);
6801 switch (XINT (x
, 1))
6803 case UNSPEC_GOTTPOFF
:
6804 output_addr_const (file
, op
);
6805 /* FIXME: This might be @TPOFF in Sun ld. */
6806 fputs ("@GOTTPOFF", file
);
6809 output_addr_const (file
, op
);
6810 fputs ("@TPOFF", file
);
6813 output_addr_const (file
, op
);
6815 fputs ("@TPOFF", file
);
6817 fputs ("@NTPOFF", file
);
6820 output_addr_const (file
, op
);
6821 fputs ("@DTPOFF", file
);
6823 case UNSPEC_GOTNTPOFF
:
6824 output_addr_const (file
, op
);
6826 fputs ("@GOTTPOFF(%rip)", file
);
6828 fputs ("@GOTNTPOFF", file
);
6830 case UNSPEC_INDNTPOFF
:
6831 output_addr_const (file
, op
);
6832 fputs ("@INDNTPOFF", file
);
6842 /* Split one or more DImode RTL references into pairs of SImode
6843 references. The RTL can be REG, offsettable MEM, integer constant, or
6844 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
6845 split and "num" is its length. lo_half and hi_half are output arrays
6846 that parallel "operands". */
6849 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
6853 rtx op
= operands
[num
];
6855 /* simplify_subreg refuse to split volatile memory addresses,
6856 but we still have to handle it. */
6857 if (GET_CODE (op
) == MEM
)
6859 lo_half
[num
] = adjust_address (op
, SImode
, 0);
6860 hi_half
[num
] = adjust_address (op
, SImode
, 4);
6864 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
6865 GET_MODE (op
) == VOIDmode
6866 ? DImode
: GET_MODE (op
), 0);
6867 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
6868 GET_MODE (op
) == VOIDmode
6869 ? DImode
: GET_MODE (op
), 4);
6873 /* Split one or more TImode RTL references into pairs of SImode
6874 references. The RTL can be REG, offsettable MEM, integer constant, or
6875 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
6876 split and "num" is its length. lo_half and hi_half are output arrays
6877 that parallel "operands". */
6880 split_ti (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
6884 rtx op
= operands
[num
];
6886 /* simplify_subreg refuse to split volatile memory addresses, but we
6887 still have to handle it. */
6888 if (GET_CODE (op
) == MEM
)
6890 lo_half
[num
] = adjust_address (op
, DImode
, 0);
6891 hi_half
[num
] = adjust_address (op
, DImode
, 8);
6895 lo_half
[num
] = simplify_gen_subreg (DImode
, op
, TImode
, 0);
6896 hi_half
[num
] = simplify_gen_subreg (DImode
, op
, TImode
, 8);
6901 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
6902 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
6903 is the expression of the binary operation. The output may either be
6904 emitted here, or returned to the caller, like all output_* functions.
6906 There is no guarantee that the operands are the same mode, as they
6907 might be within FLOAT or FLOAT_EXTEND expressions. */
6909 #ifndef SYSV386_COMPAT
6910 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
6911 wants to fix the assemblers because that causes incompatibility
6912 with gcc. No-one wants to fix gcc because that causes
6913 incompatibility with assemblers... You can use the option of
6914 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
6915 #define SYSV386_COMPAT 1
6919 output_387_binary_op (rtx insn
, rtx
*operands
)
6921 static char buf
[30];
6924 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]) | SSE_REG_P (operands
[2]);
6926 #ifdef ENABLE_CHECKING
6927 /* Even if we do not want to check the inputs, this documents input
6928 constraints. Which helps in understanding the following code. */
6929 if (STACK_REG_P (operands
[0])
6930 && ((REG_P (operands
[1])
6931 && REGNO (operands
[0]) == REGNO (operands
[1])
6932 && (STACK_REG_P (operands
[2]) || GET_CODE (operands
[2]) == MEM
))
6933 || (REG_P (operands
[2])
6934 && REGNO (operands
[0]) == REGNO (operands
[2])
6935 && (STACK_REG_P (operands
[1]) || GET_CODE (operands
[1]) == MEM
)))
6936 && (STACK_TOP_P (operands
[1]) || STACK_TOP_P (operands
[2])))
6942 switch (GET_CODE (operands
[3]))
6945 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6946 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6954 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6955 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6963 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6964 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6972 if (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
6973 || GET_MODE_CLASS (GET_MODE (operands
[2])) == MODE_INT
)
6987 if (GET_MODE (operands
[0]) == SFmode
)
6988 strcat (buf
, "ss\t{%2, %0|%0, %2}");
6990 strcat (buf
, "sd\t{%2, %0|%0, %2}");
6995 switch (GET_CODE (operands
[3]))
6999 if (REG_P (operands
[2]) && REGNO (operands
[0]) == REGNO (operands
[2]))
7001 rtx temp
= operands
[2];
7002 operands
[2] = operands
[1];
7006 /* know operands[0] == operands[1]. */
7008 if (GET_CODE (operands
[2]) == MEM
)
7014 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
7016 if (STACK_TOP_P (operands
[0]))
7017 /* How is it that we are storing to a dead operand[2]?
7018 Well, presumably operands[1] is dead too. We can't
7019 store the result to st(0) as st(0) gets popped on this
7020 instruction. Instead store to operands[2] (which I
7021 think has to be st(1)). st(1) will be popped later.
7022 gcc <= 2.8.1 didn't have this check and generated
7023 assembly code that the Unixware assembler rejected. */
7024 p
= "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7026 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7030 if (STACK_TOP_P (operands
[0]))
7031 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7033 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7038 if (GET_CODE (operands
[1]) == MEM
)
7044 if (GET_CODE (operands
[2]) == MEM
)
7050 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[2])))
7053 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
7054 derived assemblers, confusingly reverse the direction of
7055 the operation for fsub{r} and fdiv{r} when the
7056 destination register is not st(0). The Intel assembler
7057 doesn't have this brain damage. Read !SYSV386_COMPAT to
7058 figure out what the hardware really does. */
7059 if (STACK_TOP_P (operands
[0]))
7060 p
= "{p\t%0, %2|rp\t%2, %0}";
7062 p
= "{rp\t%2, %0|p\t%0, %2}";
7064 if (STACK_TOP_P (operands
[0]))
7065 /* As above for fmul/fadd, we can't store to st(0). */
7066 p
= "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
7068 p
= "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
7073 if (find_regno_note (insn
, REG_DEAD
, REGNO (operands
[1])))
7076 if (STACK_TOP_P (operands
[0]))
7077 p
= "{rp\t%0, %1|p\t%1, %0}";
7079 p
= "{p\t%1, %0|rp\t%0, %1}";
7081 if (STACK_TOP_P (operands
[0]))
7082 p
= "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
7084 p
= "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
7089 if (STACK_TOP_P (operands
[0]))
7091 if (STACK_TOP_P (operands
[1]))
7092 p
= "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
7094 p
= "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
7097 else if (STACK_TOP_P (operands
[1]))
7100 p
= "{\t%1, %0|r\t%0, %1}";
7102 p
= "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
7108 p
= "{r\t%2, %0|\t%0, %2}";
7110 p
= "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
7123 /* Output code to initialize control word copies used by trunc?f?i and
7124 rounding patterns. CURRENT_MODE is set to current control word,
7125 while NEW_MODE is set to new control word. */
7128 emit_i387_cw_initialization (rtx current_mode
, rtx new_mode
, int mode
)
7130 rtx reg
= gen_reg_rtx (HImode
);
7132 emit_insn (gen_x86_fnstcw_1 (current_mode
));
7133 emit_move_insn (reg
, current_mode
);
7135 if (!TARGET_PARTIAL_REG_STALL
&& !optimize_size
7141 /* round down toward -oo */
7142 emit_insn (gen_movsi_insv_1 (reg
, GEN_INT (0x4)));
7146 /* round up toward +oo */
7147 emit_insn (gen_movsi_insv_1 (reg
, GEN_INT (0x8)));
7151 /* round toward zero (truncate) */
7152 emit_insn (gen_movsi_insv_1 (reg
, GEN_INT (0xc)));
7155 case I387_CW_MASK_PM
:
7156 /* mask precision exception for nearbyint() */
7157 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0020)));
7169 /* round down toward -oo */
7170 emit_insn (gen_andhi3 (reg
, reg
, GEN_INT (~0x0c00)));
7171 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0400)));
7175 /* round up toward +oo */
7176 emit_insn (gen_andhi3 (reg
, reg
, GEN_INT (~0x0c00)));
7177 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0800)));
7181 /* round toward zero (truncate) */
7182 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0c00)));
7185 case I387_CW_MASK_PM
:
7186 /* mask precision exception for nearbyint() */
7187 emit_insn (gen_iorhi3 (reg
, reg
, GEN_INT (0x0020)));
7195 emit_move_insn (new_mode
, reg
);
7198 /* Output code for INSN to convert a float to a signed int. OPERANDS
7199 are the insn operands. The output may be [HSD]Imode and the input
7200 operand may be [SDX]Fmode. */
7203 output_fix_trunc (rtx insn
, rtx
*operands
)
7205 int stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
7206 int dimode_p
= GET_MODE (operands
[0]) == DImode
;
7208 /* Jump through a hoop or two for DImode, since the hardware has no
7209 non-popping instruction. We used to do this a different way, but
7210 that was somewhat fragile and broke with post-reload splitters. */
7211 if (dimode_p
&& !stack_top_dies
)
7212 output_asm_insn ("fld\t%y1", operands
);
7214 if (!STACK_TOP_P (operands
[1]))
7217 if (GET_CODE (operands
[0]) != MEM
)
7220 output_asm_insn ("fldcw\t%3", operands
);
7221 if (stack_top_dies
|| dimode_p
)
7222 output_asm_insn ("fistp%z0\t%0", operands
);
7224 output_asm_insn ("fist%z0\t%0", operands
);
7225 output_asm_insn ("fldcw\t%2", operands
);
7230 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
7231 should be used and 2 when fnstsw should be used. UNORDERED_P is true
7232 when fucom should be used. */
7235 output_fp_compare (rtx insn
, rtx
*operands
, int eflags_p
, int unordered_p
)
7238 rtx cmp_op0
, cmp_op1
;
7239 int is_sse
= SSE_REG_P (operands
[0]) | SSE_REG_P (operands
[1]);
7243 cmp_op0
= operands
[1];
7244 cmp_op1
= operands
[2];
7248 cmp_op0
= operands
[0];
7249 cmp_op1
= operands
[1];
7254 if (GET_MODE (operands
[0]) == SFmode
)
7256 return "ucomiss\t{%1, %0|%0, %1}";
7258 return "comiss\t{%1, %0|%0, %1}";
7261 return "ucomisd\t{%1, %0|%0, %1}";
7263 return "comisd\t{%1, %0|%0, %1}";
7266 if (! STACK_TOP_P (cmp_op0
))
7269 stack_top_dies
= find_regno_note (insn
, REG_DEAD
, FIRST_STACK_REG
) != 0;
7271 if (cmp_op1
== CONST0_RTX (GET_MODE (cmp_op1
)))
7275 output_asm_insn ("ftst\n\tfnstsw\t%0", operands
);
7276 return TARGET_USE_FFREEP
? "ffreep\t%y1" : "fstp\t%y1";
7279 return "ftst\n\tfnstsw\t%0";
7282 if (STACK_REG_P (cmp_op1
)
7284 && find_regno_note (insn
, REG_DEAD
, REGNO (cmp_op1
))
7285 && REGNO (cmp_op1
) != FIRST_STACK_REG
)
7287 /* If both the top of the 387 stack dies, and the other operand
7288 is also a stack register that dies, then this must be a
7289 `fcompp' float compare */
7293 /* There is no double popping fcomi variant. Fortunately,
7294 eflags is immune from the fstp's cc clobbering. */
7296 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands
);
7298 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands
);
7299 return TARGET_USE_FFREEP
? "ffreep\t%y0" : "fstp\t%y0";
7306 return "fucompp\n\tfnstsw\t%0";
7308 return "fcompp\n\tfnstsw\t%0";
7321 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
7323 static const char * const alt
[24] =
7335 "fcomi\t{%y1, %0|%0, %y1}",
7336 "fcomip\t{%y1, %0|%0, %y1}",
7337 "fucomi\t{%y1, %0|%0, %y1}",
7338 "fucomip\t{%y1, %0|%0, %y1}",
7345 "fcom%z2\t%y2\n\tfnstsw\t%0",
7346 "fcomp%z2\t%y2\n\tfnstsw\t%0",
7347 "fucom%z2\t%y2\n\tfnstsw\t%0",
7348 "fucomp%z2\t%y2\n\tfnstsw\t%0",
7350 "ficom%z2\t%y2\n\tfnstsw\t%0",
7351 "ficomp%z2\t%y2\n\tfnstsw\t%0",
7359 mask
= eflags_p
<< 3;
7360 mask
|= (GET_MODE_CLASS (GET_MODE (operands
[1])) == MODE_INT
) << 2;
7361 mask
|= unordered_p
<< 1;
7362 mask
|= stack_top_dies
;
7375 ix86_output_addr_vec_elt (FILE *file
, int value
)
7377 const char *directive
= ASM_LONG
;
7382 directive
= ASM_QUAD
;
7388 fprintf (file
, "%s%s%d\n", directive
, LPREFIX
, value
);
7392 ix86_output_addr_diff_elt (FILE *file
, int value
, int rel
)
7395 fprintf (file
, "%s%s%d-%s%d\n",
7396 ASM_LONG
, LPREFIX
, value
, LPREFIX
, rel
);
7397 else if (HAVE_AS_GOTOFF_IN_DATA
)
7398 fprintf (file
, "%s%s%d@GOTOFF\n", ASM_LONG
, LPREFIX
, value
);
7400 else if (TARGET_MACHO
)
7402 fprintf (file
, "%s%s%d-", ASM_LONG
, LPREFIX
, value
);
7403 machopic_output_function_base_name (file
);
7404 fprintf(file
, "\n");
7408 asm_fprintf (file
, "%s%U%s+[.-%s%d]\n",
7409 ASM_LONG
, GOT_SYMBOL_NAME
, LPREFIX
, value
);
7412 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
7416 ix86_expand_clear (rtx dest
)
7420 /* We play register width games, which are only valid after reload. */
7421 if (!reload_completed
)
7424 /* Avoid HImode and its attendant prefix byte. */
7425 if (GET_MODE_SIZE (GET_MODE (dest
)) < 4)
7426 dest
= gen_rtx_REG (SImode
, REGNO (dest
));
7428 tmp
= gen_rtx_SET (VOIDmode
, dest
, const0_rtx
);
7430 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
7431 if (reload_completed
&& (!TARGET_USE_MOV0
|| optimize_size
))
7433 rtx clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, 17));
7434 tmp
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, tmp
, clob
));
7440 /* X is an unchanging MEM. If it is a constant pool reference, return
7441 the constant pool rtx, else NULL. */
7444 maybe_get_pool_constant (rtx x
)
7446 x
= ix86_delegitimize_address (XEXP (x
, 0));
7448 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
7449 return get_pool_constant (x
);
7455 ix86_expand_move (enum machine_mode mode
, rtx operands
[])
7457 int strict
= (reload_in_progress
|| reload_completed
);
7459 enum tls_model model
;
7464 model
= GET_CODE (op1
) == SYMBOL_REF
? SYMBOL_REF_TLS_MODEL (op1
) : 0;
7467 op1
= legitimize_tls_address (op1
, model
, true);
7468 op1
= force_operand (op1
, op0
);
7473 if (flag_pic
&& mode
== Pmode
&& symbolic_operand (op1
, Pmode
))
7478 rtx temp
= ((reload_in_progress
7479 || ((op0
&& GET_CODE (op0
) == REG
)
7481 ? op0
: gen_reg_rtx (Pmode
));
7482 op1
= machopic_indirect_data_reference (op1
, temp
);
7483 op1
= machopic_legitimize_pic_address (op1
, mode
,
7484 temp
== op1
? 0 : temp
);
7486 else if (MACHOPIC_INDIRECT
)
7487 op1
= machopic_indirect_data_reference (op1
, 0);
7491 if (GET_CODE (op0
) == MEM
)
7492 op1
= force_reg (Pmode
, op1
);
7494 op1
= legitimize_address (op1
, op1
, Pmode
);
7495 #endif /* TARGET_MACHO */
7499 if (GET_CODE (op0
) == MEM
7500 && (PUSH_ROUNDING (GET_MODE_SIZE (mode
)) != GET_MODE_SIZE (mode
)
7501 || !push_operand (op0
, mode
))
7502 && GET_CODE (op1
) == MEM
)
7503 op1
= force_reg (mode
, op1
);
7505 if (push_operand (op0
, mode
)
7506 && ! general_no_elim_operand (op1
, mode
))
7507 op1
= copy_to_mode_reg (mode
, op1
);
7509 /* Force large constants in 64bit compilation into register
7510 to get them CSEed. */
7511 if (TARGET_64BIT
&& mode
== DImode
7512 && immediate_operand (op1
, mode
)
7513 && !x86_64_zext_immediate_operand (op1
, VOIDmode
)
7514 && !register_operand (op0
, mode
)
7515 && optimize
&& !reload_completed
&& !reload_in_progress
)
7516 op1
= copy_to_mode_reg (mode
, op1
);
7518 if (FLOAT_MODE_P (mode
))
7520 /* If we are loading a floating point constant to a register,
7521 force the value to memory now, since we'll get better code
7522 out the back end. */
7526 else if (GET_CODE (op1
) == CONST_DOUBLE
)
7528 op1
= validize_mem (force_const_mem (mode
, op1
));
7529 if (!register_operand (op0
, mode
))
7531 rtx temp
= gen_reg_rtx (mode
);
7532 emit_insn (gen_rtx_SET (VOIDmode
, temp
, op1
));
7533 emit_move_insn (op0
, temp
);
7540 emit_insn (gen_rtx_SET (VOIDmode
, op0
, op1
));
7544 ix86_expand_vector_move (enum machine_mode mode
, rtx operands
[])
7546 /* Force constants other than zero into memory. We do not know how
7547 the instructions used to build constants modify the upper 64 bits
7548 of the register, once we have that information we may be able
7549 to handle some of them more efficiently. */
7550 if ((reload_in_progress
| reload_completed
) == 0
7551 && register_operand (operands
[0], mode
)
7552 && CONSTANT_P (operands
[1]) && operands
[1] != CONST0_RTX (mode
))
7553 operands
[1] = validize_mem (force_const_mem (mode
, operands
[1]));
7555 /* Make operand1 a register if it isn't already. */
7557 && !register_operand (operands
[0], mode
)
7558 && !register_operand (operands
[1], mode
))
7560 rtx temp
= force_reg (GET_MODE (operands
[1]), operands
[1]);
7561 emit_move_insn (operands
[0], temp
);
7565 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
7568 /* Attempt to expand a binary operator. Make the expansion closer to the
7569 actual machine, then just general_operand, which will allow 3 separate
7570 memory references (one output, two input) in a single insn. */
7573 ix86_expand_binary_operator (enum rtx_code code
, enum machine_mode mode
,
7576 int matching_memory
;
7577 rtx src1
, src2
, dst
, op
, clob
;
7583 /* Recognize <var1> = <value> <op> <var1> for commutative operators */
7584 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
7585 && (rtx_equal_p (dst
, src2
)
7586 || immediate_operand (src1
, mode
)))
7593 /* If the destination is memory, and we do not have matching source
7594 operands, do things in registers. */
7595 matching_memory
= 0;
7596 if (GET_CODE (dst
) == MEM
)
7598 if (rtx_equal_p (dst
, src1
))
7599 matching_memory
= 1;
7600 else if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
7601 && rtx_equal_p (dst
, src2
))
7602 matching_memory
= 2;
7604 dst
= gen_reg_rtx (mode
);
7607 /* Both source operands cannot be in memory. */
7608 if (GET_CODE (src1
) == MEM
&& GET_CODE (src2
) == MEM
)
7610 if (matching_memory
!= 2)
7611 src2
= force_reg (mode
, src2
);
7613 src1
= force_reg (mode
, src1
);
7616 /* If the operation is not commutable, source 1 cannot be a constant
7617 or non-matching memory. */
7618 if ((CONSTANT_P (src1
)
7619 || (!matching_memory
&& GET_CODE (src1
) == MEM
))
7620 && GET_RTX_CLASS (code
) != RTX_COMM_ARITH
)
7621 src1
= force_reg (mode
, src1
);
7623 /* If optimizing, copy to regs to improve CSE */
7624 if (optimize
&& ! no_new_pseudos
)
7626 if (GET_CODE (dst
) == MEM
)
7627 dst
= gen_reg_rtx (mode
);
7628 if (GET_CODE (src1
) == MEM
)
7629 src1
= force_reg (mode
, src1
);
7630 if (GET_CODE (src2
) == MEM
)
7631 src2
= force_reg (mode
, src2
);
7634 /* Emit the instruction. */
7636 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, mode
, src1
, src2
));
7637 if (reload_in_progress
)
7639 /* Reload doesn't know about the flags register, and doesn't know that
7640 it doesn't want to clobber it. We can only do this with PLUS. */
7647 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
7648 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
7651 /* Fix up the destination if needed. */
7652 if (dst
!= operands
[0])
7653 emit_move_insn (operands
[0], dst
);
7656 /* Return TRUE or FALSE depending on whether the binary operator meets the
7657 appropriate constraints. */
7660 ix86_binary_operator_ok (enum rtx_code code
,
7661 enum machine_mode mode ATTRIBUTE_UNUSED
,
7664 /* Both source operands cannot be in memory. */
7665 if (GET_CODE (operands
[1]) == MEM
&& GET_CODE (operands
[2]) == MEM
)
7667 /* If the operation is not commutable, source 1 cannot be a constant. */
7668 if (CONSTANT_P (operands
[1]) && GET_RTX_CLASS (code
) != RTX_COMM_ARITH
)
7670 /* If the destination is memory, we must have a matching source operand. */
7671 if (GET_CODE (operands
[0]) == MEM
7672 && ! (rtx_equal_p (operands
[0], operands
[1])
7673 || (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
7674 && rtx_equal_p (operands
[0], operands
[2]))))
7676 /* If the operation is not commutable and the source 1 is memory, we must
7677 have a matching destination. */
7678 if (GET_CODE (operands
[1]) == MEM
7679 && GET_RTX_CLASS (code
) != RTX_COMM_ARITH
7680 && ! rtx_equal_p (operands
[0], operands
[1]))
7685 /* Attempt to expand a unary operator. Make the expansion closer to the
7686 actual machine, then just general_operand, which will allow 2 separate
7687 memory references (one output, one input) in a single insn. */
7690 ix86_expand_unary_operator (enum rtx_code code
, enum machine_mode mode
,
7693 int matching_memory
;
7694 rtx src
, dst
, op
, clob
;
7699 /* If the destination is memory, and we do not have matching source
7700 operands, do things in registers. */
7701 matching_memory
= 0;
7702 if (GET_CODE (dst
) == MEM
)
7704 if (rtx_equal_p (dst
, src
))
7705 matching_memory
= 1;
7707 dst
= gen_reg_rtx (mode
);
7710 /* When source operand is memory, destination must match. */
7711 if (!matching_memory
&& GET_CODE (src
) == MEM
)
7712 src
= force_reg (mode
, src
);
7714 /* If optimizing, copy to regs to improve CSE */
7715 if (optimize
&& ! no_new_pseudos
)
7717 if (GET_CODE (dst
) == MEM
)
7718 dst
= gen_reg_rtx (mode
);
7719 if (GET_CODE (src
) == MEM
)
7720 src
= force_reg (mode
, src
);
7723 /* Emit the instruction. */
7725 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_e (code
, mode
, src
));
7726 if (reload_in_progress
|| code
== NOT
)
7728 /* Reload doesn't know about the flags register, and doesn't know that
7729 it doesn't want to clobber it. */
7736 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, FLAGS_REG
));
7737 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
7740 /* Fix up the destination if needed. */
7741 if (dst
!= operands
[0])
7742 emit_move_insn (operands
[0], dst
);
7745 /* Return TRUE or FALSE depending on whether the unary operator meets the
7746 appropriate constraints. */
7749 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED
,
7750 enum machine_mode mode ATTRIBUTE_UNUSED
,
7751 rtx operands
[2] ATTRIBUTE_UNUSED
)
7753 /* If one of operands is memory, source and destination must match. */
7754 if ((GET_CODE (operands
[0]) == MEM
7755 || GET_CODE (operands
[1]) == MEM
)
7756 && ! rtx_equal_p (operands
[0], operands
[1]))
7761 /* Return TRUE or FALSE depending on whether the first SET in INSN
7762 has source and destination with matching CC modes, and that the
7763 CC mode is at least as constrained as REQ_MODE. */
7766 ix86_match_ccmode (rtx insn
, enum machine_mode req_mode
)
7769 enum machine_mode set_mode
;
7771 set
= PATTERN (insn
);
7772 if (GET_CODE (set
) == PARALLEL
)
7773 set
= XVECEXP (set
, 0, 0);
7774 if (GET_CODE (set
) != SET
)
7776 if (GET_CODE (SET_SRC (set
)) != COMPARE
)
7779 set_mode
= GET_MODE (SET_DEST (set
));
7783 if (req_mode
!= CCNOmode
7784 && (req_mode
!= CCmode
7785 || XEXP (SET_SRC (set
), 1) != const0_rtx
))
7789 if (req_mode
== CCGCmode
)
7793 if (req_mode
== CCGOCmode
|| req_mode
== CCNOmode
)
7797 if (req_mode
== CCZmode
)
7807 return (GET_MODE (SET_SRC (set
)) == set_mode
);
7810 /* Generate insn patterns to do an integer compare of OPERANDS. */
7813 ix86_expand_int_compare (enum rtx_code code
, rtx op0
, rtx op1
)
7815 enum machine_mode cmpmode
;
7818 cmpmode
= SELECT_CC_MODE (code
, op0
, op1
);
7819 flags
= gen_rtx_REG (cmpmode
, FLAGS_REG
);
7821 /* This is very simple, but making the interface the same as in the
7822 FP case makes the rest of the code easier. */
7823 tmp
= gen_rtx_COMPARE (cmpmode
, op0
, op1
);
7824 emit_insn (gen_rtx_SET (VOIDmode
, flags
, tmp
));
7826 /* Return the test that should be put into the flags user, i.e.
7827 the bcc, scc, or cmov instruction. */
7828 return gen_rtx_fmt_ee (code
, VOIDmode
, flags
, const0_rtx
);
7831 /* Figure out whether to use ordered or unordered fp comparisons.
7832 Return the appropriate mode to use. */
7835 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED
)
7837 /* ??? In order to make all comparisons reversible, we do all comparisons
7838 non-trapping when compiling for IEEE. Once gcc is able to distinguish
7839 all forms trapping and nontrapping comparisons, we can make inequality
7840 comparisons trapping again, since it results in better code when using
7841 FCOM based compares. */
7842 return TARGET_IEEE_FP
? CCFPUmode
: CCFPmode
;
7846 ix86_cc_mode (enum rtx_code code
, rtx op0
, rtx op1
)
7848 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
7849 return ix86_fp_compare_mode (code
);
7852 /* Only zero flag is needed. */
7854 case NE
: /* ZF!=0 */
7856 /* Codes needing carry flag. */
7857 case GEU
: /* CF=0 */
7858 case GTU
: /* CF=0 & ZF=0 */
7859 case LTU
: /* CF=1 */
7860 case LEU
: /* CF=1 | ZF=1 */
7862 /* Codes possibly doable only with sign flag when
7863 comparing against zero. */
7864 case GE
: /* SF=OF or SF=0 */
7865 case LT
: /* SF<>OF or SF=1 */
7866 if (op1
== const0_rtx
)
7869 /* For other cases Carry flag is not required. */
7871 /* Codes doable only with sign flag when comparing
7872 against zero, but we miss jump instruction for it
7873 so we need to use relational tests against overflow
7874 that thus needs to be zero. */
7875 case GT
: /* ZF=0 & SF=OF */
7876 case LE
: /* ZF=1 | SF<>OF */
7877 if (op1
== const0_rtx
)
7881 /* strcmp pattern do (use flags) and combine may ask us for proper
7890 /* Return the fixed registers used for condition codes. */
7893 ix86_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
7900 /* If two condition code modes are compatible, return a condition code
7901 mode which is compatible with both. Otherwise, return
7904 static enum machine_mode
7905 ix86_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
7910 if (GET_MODE_CLASS (m1
) != MODE_CC
|| GET_MODE_CLASS (m2
) != MODE_CC
)
7913 if ((m1
== CCGCmode
&& m2
== CCGOCmode
)
7914 || (m1
== CCGOCmode
&& m2
== CCGCmode
))
7942 /* These are only compatible with themselves, which we already
7948 /* Return true if we should use an FCOMI instruction for this fp comparison. */
7951 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED
)
7953 enum rtx_code swapped_code
= swap_condition (code
);
7954 return ((ix86_fp_comparison_cost (code
) == ix86_fp_comparison_fcomi_cost (code
))
7955 || (ix86_fp_comparison_cost (swapped_code
)
7956 == ix86_fp_comparison_fcomi_cost (swapped_code
)));
7959 /* Swap, force into registers, or otherwise massage the two operands
7960 to a fp comparison. The operands are updated in place; the new
7961 comparison code is returned. */
7963 static enum rtx_code
7964 ix86_prepare_fp_compare_args (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
7966 enum machine_mode fpcmp_mode
= ix86_fp_compare_mode (code
);
7967 rtx op0
= *pop0
, op1
= *pop1
;
7968 enum machine_mode op_mode
= GET_MODE (op0
);
7969 int is_sse
= SSE_REG_P (op0
) | SSE_REG_P (op1
);
7971 /* All of the unordered compare instructions only work on registers.
7972 The same is true of the fcomi compare instructions. The same is
7973 true of the XFmode compare instructions if not comparing with
7974 zero (ftst insn is used in this case). */
7977 && (fpcmp_mode
== CCFPUmode
7978 || (op_mode
== XFmode
7979 && ! (standard_80387_constant_p (op0
) == 1
7980 || standard_80387_constant_p (op1
) == 1))
7981 || ix86_use_fcomi_compare (code
)))
7983 op0
= force_reg (op_mode
, op0
);
7984 op1
= force_reg (op_mode
, op1
);
7988 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
7989 things around if they appear profitable, otherwise force op0
7992 if (standard_80387_constant_p (op0
) == 0
7993 || (GET_CODE (op0
) == MEM
7994 && ! (standard_80387_constant_p (op1
) == 0
7995 || GET_CODE (op1
) == MEM
)))
7998 tmp
= op0
, op0
= op1
, op1
= tmp
;
7999 code
= swap_condition (code
);
8002 if (GET_CODE (op0
) != REG
)
8003 op0
= force_reg (op_mode
, op0
);
8005 if (CONSTANT_P (op1
))
8007 int tmp
= standard_80387_constant_p (op1
);
8009 op1
= validize_mem (force_const_mem (op_mode
, op1
));
8013 op1
= force_reg (op_mode
, op1
);
8016 op1
= force_reg (op_mode
, op1
);
8020 /* Try to rearrange the comparison to make it cheaper. */
8021 if (ix86_fp_comparison_cost (code
)
8022 > ix86_fp_comparison_cost (swap_condition (code
))
8023 && (GET_CODE (op1
) == REG
|| !no_new_pseudos
))
8026 tmp
= op0
, op0
= op1
, op1
= tmp
;
8027 code
= swap_condition (code
);
8028 if (GET_CODE (op0
) != REG
)
8029 op0
= force_reg (op_mode
, op0
);
8037 /* Convert comparison codes we use to represent FP comparison to integer
8038 code that will result in proper branch. Return UNKNOWN if no such code
8042 ix86_fp_compare_code_to_integer (enum rtx_code code
)
8071 /* Split comparison code CODE into comparisons we can do using branch
8072 instructions. BYPASS_CODE is comparison code for branch that will
8073 branch around FIRST_CODE and SECOND_CODE. If some of branches
8074 is not required, set value to UNKNOWN.
8075 We never require more than two branches. */
8078 ix86_fp_comparison_codes (enum rtx_code code
, enum rtx_code
*bypass_code
,
8079 enum rtx_code
*first_code
,
8080 enum rtx_code
*second_code
)
8083 *bypass_code
= UNKNOWN
;
8084 *second_code
= UNKNOWN
;
8086 /* The fcomi comparison sets flags as follows:
8096 case GT
: /* GTU - CF=0 & ZF=0 */
8097 case GE
: /* GEU - CF=0 */
8098 case ORDERED
: /* PF=0 */
8099 case UNORDERED
: /* PF=1 */
8100 case UNEQ
: /* EQ - ZF=1 */
8101 case UNLT
: /* LTU - CF=1 */
8102 case UNLE
: /* LEU - CF=1 | ZF=1 */
8103 case LTGT
: /* EQ - ZF=0 */
8105 case LT
: /* LTU - CF=1 - fails on unordered */
8107 *bypass_code
= UNORDERED
;
8109 case LE
: /* LEU - CF=1 | ZF=1 - fails on unordered */
8111 *bypass_code
= UNORDERED
;
8113 case EQ
: /* EQ - ZF=1 - fails on unordered */
8115 *bypass_code
= UNORDERED
;
8117 case NE
: /* NE - ZF=0 - fails on unordered */
8119 *second_code
= UNORDERED
;
8121 case UNGE
: /* GEU - CF=0 - fails on unordered */
8123 *second_code
= UNORDERED
;
8125 case UNGT
: /* GTU - CF=0 & ZF=0 - fails on unordered */
8127 *second_code
= UNORDERED
;
8132 if (!TARGET_IEEE_FP
)
8134 *second_code
= UNKNOWN
;
8135 *bypass_code
= UNKNOWN
;
8139 /* Return cost of comparison done fcom + arithmetics operations on AX.
8140 All following functions do use number of instructions as a cost metrics.
8141 In future this should be tweaked to compute bytes for optimize_size and
8142 take into account performance of various instructions on various CPUs. */
8144 ix86_fp_comparison_arithmetics_cost (enum rtx_code code
)
8146 if (!TARGET_IEEE_FP
)
8148 /* The cost of code output by ix86_expand_fp_compare. */
8176 /* Return cost of comparison done using fcomi operation.
8177 See ix86_fp_comparison_arithmetics_cost for the metrics. */
8179 ix86_fp_comparison_fcomi_cost (enum rtx_code code
)
8181 enum rtx_code bypass_code
, first_code
, second_code
;
8182 /* Return arbitrarily high cost when instruction is not supported - this
8183 prevents gcc from using it. */
8186 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8187 return (bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
) + 2;
8190 /* Return cost of comparison done using sahf operation.
8191 See ix86_fp_comparison_arithmetics_cost for the metrics. */
8193 ix86_fp_comparison_sahf_cost (enum rtx_code code
)
8195 enum rtx_code bypass_code
, first_code
, second_code
;
8196 /* Return arbitrarily high cost when instruction is not preferred - this
8197 avoids gcc from using it. */
8198 if (!TARGET_USE_SAHF
&& !optimize_size
)
8200 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8201 return (bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
) + 3;
8204 /* Compute cost of the comparison done using any method.
8205 See ix86_fp_comparison_arithmetics_cost for the metrics. */
8207 ix86_fp_comparison_cost (enum rtx_code code
)
8209 int fcomi_cost
, sahf_cost
, arithmetics_cost
= 1024;
8212 fcomi_cost
= ix86_fp_comparison_fcomi_cost (code
);
8213 sahf_cost
= ix86_fp_comparison_sahf_cost (code
);
8215 min
= arithmetics_cost
= ix86_fp_comparison_arithmetics_cost (code
);
8216 if (min
> sahf_cost
)
8218 if (min
> fcomi_cost
)
8223 /* Generate insn patterns to do a floating point compare of OPERANDS. */
8226 ix86_expand_fp_compare (enum rtx_code code
, rtx op0
, rtx op1
, rtx scratch
,
8227 rtx
*second_test
, rtx
*bypass_test
)
8229 enum machine_mode fpcmp_mode
, intcmp_mode
;
8231 int cost
= ix86_fp_comparison_cost (code
);
8232 enum rtx_code bypass_code
, first_code
, second_code
;
8234 fpcmp_mode
= ix86_fp_compare_mode (code
);
8235 code
= ix86_prepare_fp_compare_args (code
, &op0
, &op1
);
8238 *second_test
= NULL_RTX
;
8240 *bypass_test
= NULL_RTX
;
8242 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8244 /* Do fcomi/sahf based test when profitable. */
8245 if ((bypass_code
== UNKNOWN
|| bypass_test
)
8246 && (second_code
== UNKNOWN
|| second_test
)
8247 && ix86_fp_comparison_arithmetics_cost (code
) > cost
)
8251 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
8252 tmp
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (fpcmp_mode
, FLAGS_REG
),
8258 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
8259 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), UNSPEC_FNSTSW
);
8261 scratch
= gen_reg_rtx (HImode
);
8262 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
8263 emit_insn (gen_x86_sahf_1 (scratch
));
8266 /* The FP codes work out to act like unsigned. */
8267 intcmp_mode
= fpcmp_mode
;
8269 if (bypass_code
!= UNKNOWN
)
8270 *bypass_test
= gen_rtx_fmt_ee (bypass_code
, VOIDmode
,
8271 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
8273 if (second_code
!= UNKNOWN
)
8274 *second_test
= gen_rtx_fmt_ee (second_code
, VOIDmode
,
8275 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
8280 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
8281 tmp
= gen_rtx_COMPARE (fpcmp_mode
, op0
, op1
);
8282 tmp2
= gen_rtx_UNSPEC (HImode
, gen_rtvec (1, tmp
), UNSPEC_FNSTSW
);
8284 scratch
= gen_reg_rtx (HImode
);
8285 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, tmp2
));
8287 /* In the unordered case, we have to check C2 for NaN's, which
8288 doesn't happen to work out to anything nice combination-wise.
8289 So do some bit twiddling on the value we've got in AH to come
8290 up with an appropriate set of condition codes. */
8292 intcmp_mode
= CCNOmode
;
8297 if (code
== GT
|| !TARGET_IEEE_FP
)
8299 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
8304 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8305 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
8306 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x44)));
8307 intcmp_mode
= CCmode
;
8313 if (code
== LT
&& TARGET_IEEE_FP
)
8315 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8316 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x01)));
8317 intcmp_mode
= CCmode
;
8322 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x01)));
8328 if (code
== GE
|| !TARGET_IEEE_FP
)
8330 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x05)));
8335 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8336 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
8343 if (code
== LE
&& TARGET_IEEE_FP
)
8345 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8346 emit_insn (gen_addqi_ext_1 (scratch
, scratch
, constm1_rtx
));
8347 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
8348 intcmp_mode
= CCmode
;
8353 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x45)));
8359 if (code
== EQ
&& TARGET_IEEE_FP
)
8361 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8362 emit_insn (gen_cmpqi_ext_3 (scratch
, GEN_INT (0x40)));
8363 intcmp_mode
= CCmode
;
8368 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
8375 if (code
== NE
&& TARGET_IEEE_FP
)
8377 emit_insn (gen_andqi_ext_0 (scratch
, scratch
, GEN_INT (0x45)));
8378 emit_insn (gen_xorqi_cc_ext_1 (scratch
, scratch
,
8384 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x40)));
8390 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
8394 emit_insn (gen_testqi_ext_ccno_0 (scratch
, GEN_INT (0x04)));
8403 /* Return the test that should be put into the flags user, i.e.
8404 the bcc, scc, or cmov instruction. */
8405 return gen_rtx_fmt_ee (code
, VOIDmode
,
8406 gen_rtx_REG (intcmp_mode
, FLAGS_REG
),
8411 ix86_expand_compare (enum rtx_code code
, rtx
*second_test
, rtx
*bypass_test
)
8414 op0
= ix86_compare_op0
;
8415 op1
= ix86_compare_op1
;
8418 *second_test
= NULL_RTX
;
8420 *bypass_test
= NULL_RTX
;
8422 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
8423 ret
= ix86_expand_fp_compare (code
, op0
, op1
, NULL_RTX
,
8424 second_test
, bypass_test
);
8426 ret
= ix86_expand_int_compare (code
, op0
, op1
);
8431 /* Return true if the CODE will result in nontrivial jump sequence. */
8433 ix86_fp_jump_nontrivial_p (enum rtx_code code
)
8435 enum rtx_code bypass_code
, first_code
, second_code
;
8438 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8439 return bypass_code
!= UNKNOWN
|| second_code
!= UNKNOWN
;
8443 ix86_expand_branch (enum rtx_code code
, rtx label
)
8447 switch (GET_MODE (ix86_compare_op0
))
8453 tmp
= ix86_expand_compare (code
, NULL
, NULL
);
8454 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
8455 gen_rtx_LABEL_REF (VOIDmode
, label
),
8457 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
8466 enum rtx_code bypass_code
, first_code
, second_code
;
8468 code
= ix86_prepare_fp_compare_args (code
, &ix86_compare_op0
,
8471 ix86_fp_comparison_codes (code
, &bypass_code
, &first_code
, &second_code
);
8473 /* Check whether we will use the natural sequence with one jump. If
8474 so, we can expand jump early. Otherwise delay expansion by
8475 creating compound insn to not confuse optimizers. */
8476 if (bypass_code
== UNKNOWN
&& second_code
== UNKNOWN
8479 ix86_split_fp_branch (code
, ix86_compare_op0
, ix86_compare_op1
,
8480 gen_rtx_LABEL_REF (VOIDmode
, label
),
8485 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
,
8486 ix86_compare_op0
, ix86_compare_op1
);
8487 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
8488 gen_rtx_LABEL_REF (VOIDmode
, label
),
8490 tmp
= gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
);
8492 use_fcomi
= ix86_use_fcomi_compare (code
);
8493 vec
= rtvec_alloc (3 + !use_fcomi
);
8494 RTVEC_ELT (vec
, 0) = tmp
;
8496 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 18));
8498 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCFPmode
, 17));
8501 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (HImode
));
8503 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
8511 /* Expand DImode branch into multiple compare+branch. */
8513 rtx lo
[2], hi
[2], label2
;
8514 enum rtx_code code1
, code2
, code3
;
8516 if (CONSTANT_P (ix86_compare_op0
) && ! CONSTANT_P (ix86_compare_op1
))
8518 tmp
= ix86_compare_op0
;
8519 ix86_compare_op0
= ix86_compare_op1
;
8520 ix86_compare_op1
= tmp
;
8521 code
= swap_condition (code
);
8523 split_di (&ix86_compare_op0
, 1, lo
+0, hi
+0);
8524 split_di (&ix86_compare_op1
, 1, lo
+1, hi
+1);
8526 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
8527 avoid two branches. This costs one extra insn, so disable when
8528 optimizing for size. */
8530 if ((code
== EQ
|| code
== NE
)
8532 || hi
[1] == const0_rtx
|| lo
[1] == const0_rtx
))
8537 if (hi
[1] != const0_rtx
)
8538 xor1
= expand_binop (SImode
, xor_optab
, xor1
, hi
[1],
8539 NULL_RTX
, 0, OPTAB_WIDEN
);
8542 if (lo
[1] != const0_rtx
)
8543 xor0
= expand_binop (SImode
, xor_optab
, xor0
, lo
[1],
8544 NULL_RTX
, 0, OPTAB_WIDEN
);
8546 tmp
= expand_binop (SImode
, ior_optab
, xor1
, xor0
,
8547 NULL_RTX
, 0, OPTAB_WIDEN
);
8549 ix86_compare_op0
= tmp
;
8550 ix86_compare_op1
= const0_rtx
;
8551 ix86_expand_branch (code
, label
);
8555 /* Otherwise, if we are doing less-than or greater-or-equal-than,
8556 op1 is a constant and the low word is zero, then we can just
8557 examine the high word. */
8559 if (GET_CODE (hi
[1]) == CONST_INT
&& lo
[1] == const0_rtx
)
8562 case LT
: case LTU
: case GE
: case GEU
:
8563 ix86_compare_op0
= hi
[0];
8564 ix86_compare_op1
= hi
[1];
8565 ix86_expand_branch (code
, label
);
8571 /* Otherwise, we need two or three jumps. */
8573 label2
= gen_label_rtx ();
8576 code2
= swap_condition (code
);
8577 code3
= unsigned_condition (code
);
8581 case LT
: case GT
: case LTU
: case GTU
:
8584 case LE
: code1
= LT
; code2
= GT
; break;
8585 case GE
: code1
= GT
; code2
= LT
; break;
8586 case LEU
: code1
= LTU
; code2
= GTU
; break;
8587 case GEU
: code1
= GTU
; code2
= LTU
; break;
8589 case EQ
: code1
= UNKNOWN
; code2
= NE
; break;
8590 case NE
: code2
= UNKNOWN
; break;
8598 * if (hi(a) < hi(b)) goto true;
8599 * if (hi(a) > hi(b)) goto false;
8600 * if (lo(a) < lo(b)) goto true;
8604 ix86_compare_op0
= hi
[0];
8605 ix86_compare_op1
= hi
[1];
8607 if (code1
!= UNKNOWN
)
8608 ix86_expand_branch (code1
, label
);
8609 if (code2
!= UNKNOWN
)
8610 ix86_expand_branch (code2
, label2
);
8612 ix86_compare_op0
= lo
[0];
8613 ix86_compare_op1
= lo
[1];
8614 ix86_expand_branch (code3
, label
);
8616 if (code2
!= UNKNOWN
)
8617 emit_label (label2
);
8626 /* Split branch based on floating point condition. */
8628 ix86_split_fp_branch (enum rtx_code code
, rtx op1
, rtx op2
,
8629 rtx target1
, rtx target2
, rtx tmp
)
8632 rtx label
= NULL_RTX
;
8634 int bypass_probability
= -1, second_probability
= -1, probability
= -1;
8637 if (target2
!= pc_rtx
)
8640 code
= reverse_condition_maybe_unordered (code
);
8645 condition
= ix86_expand_fp_compare (code
, op1
, op2
,
8646 tmp
, &second
, &bypass
);
8648 if (split_branch_probability
>= 0)
8650 /* Distribute the probabilities across the jumps.
8651 Assume the BYPASS and SECOND to be always test
8653 probability
= split_branch_probability
;
8655 /* Value of 1 is low enough to make no need for probability
8656 to be updated. Later we may run some experiments and see
8657 if unordered values are more frequent in practice. */
8659 bypass_probability
= 1;
8661 second_probability
= 1;
8663 if (bypass
!= NULL_RTX
)
8665 label
= gen_label_rtx ();
8666 i
= emit_jump_insn (gen_rtx_SET
8668 gen_rtx_IF_THEN_ELSE (VOIDmode
,
8670 gen_rtx_LABEL_REF (VOIDmode
,
8673 if (bypass_probability
>= 0)
8675 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
8676 GEN_INT (bypass_probability
),
8679 i
= emit_jump_insn (gen_rtx_SET
8681 gen_rtx_IF_THEN_ELSE (VOIDmode
,
8682 condition
, target1
, target2
)));
8683 if (probability
>= 0)
8685 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
8686 GEN_INT (probability
),
8688 if (second
!= NULL_RTX
)
8690 i
= emit_jump_insn (gen_rtx_SET
8692 gen_rtx_IF_THEN_ELSE (VOIDmode
, second
, target1
,
8694 if (second_probability
>= 0)
8696 = gen_rtx_EXPR_LIST (REG_BR_PROB
,
8697 GEN_INT (second_probability
),
8700 if (label
!= NULL_RTX
)
8705 ix86_expand_setcc (enum rtx_code code
, rtx dest
)
8707 rtx ret
, tmp
, tmpreg
, equiv
;
8708 rtx second_test
, bypass_test
;
8710 if (GET_MODE (ix86_compare_op0
) == DImode
8712 return 0; /* FAIL */
8714 if (GET_MODE (dest
) != QImode
)
8717 ret
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
8718 PUT_MODE (ret
, QImode
);
8723 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, ret
));
8724 if (bypass_test
|| second_test
)
8726 rtx test
= second_test
;
8728 rtx tmp2
= gen_reg_rtx (QImode
);
8735 PUT_CODE (test
, reverse_condition_maybe_unordered (GET_CODE (test
)));
8737 PUT_MODE (test
, QImode
);
8738 emit_insn (gen_rtx_SET (VOIDmode
, tmp2
, test
));
8741 emit_insn (gen_andqi3 (tmp
, tmpreg
, tmp2
));
8743 emit_insn (gen_iorqi3 (tmp
, tmpreg
, tmp2
));
8746 /* Attach a REG_EQUAL note describing the comparison result. */
8747 equiv
= simplify_gen_relational (code
, QImode
,
8748 GET_MODE (ix86_compare_op0
),
8749 ix86_compare_op0
, ix86_compare_op1
);
8750 set_unique_reg_note (get_last_insn (), REG_EQUAL
, equiv
);
8752 return 1; /* DONE */
8755 /* Expand comparison setting or clearing carry flag. Return true when
8756 successful and set pop for the operation. */
8758 ix86_expand_carry_flag_compare (enum rtx_code code
, rtx op0
, rtx op1
, rtx
*pop
)
8760 enum machine_mode mode
=
8761 GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
8763 /* Do not handle DImode compares that go trought special path. Also we can't
8764 deal with FP compares yet. This is possible to add. */
8765 if ((mode
== DImode
&& !TARGET_64BIT
))
8767 if (FLOAT_MODE_P (mode
))
8769 rtx second_test
= NULL
, bypass_test
= NULL
;
8770 rtx compare_op
, compare_seq
;
8772 /* Shortcut: following common codes never translate into carry flag compares. */
8773 if (code
== EQ
|| code
== NE
|| code
== UNEQ
|| code
== LTGT
8774 || code
== ORDERED
|| code
== UNORDERED
)
8777 /* These comparisons require zero flag; swap operands so they won't. */
8778 if ((code
== GT
|| code
== UNLE
|| code
== LE
|| code
== UNGT
)
8784 code
= swap_condition (code
);
8787 /* Try to expand the comparison and verify that we end up with carry flag
8788 based comparison. This is fails to be true only when we decide to expand
8789 comparison using arithmetic that is not too common scenario. */
8791 compare_op
= ix86_expand_fp_compare (code
, op0
, op1
, NULL_RTX
,
8792 &second_test
, &bypass_test
);
8793 compare_seq
= get_insns ();
8796 if (second_test
|| bypass_test
)
8798 if (GET_MODE (XEXP (compare_op
, 0)) == CCFPmode
8799 || GET_MODE (XEXP (compare_op
, 0)) == CCFPUmode
)
8800 code
= ix86_fp_compare_code_to_integer (GET_CODE (compare_op
));
8802 code
= GET_CODE (compare_op
);
8803 if (code
!= LTU
&& code
!= GEU
)
8805 emit_insn (compare_seq
);
8809 if (!INTEGRAL_MODE_P (mode
))
8817 /* Convert a==0 into (unsigned)a<1. */
8820 if (op1
!= const0_rtx
)
8823 code
= (code
== EQ
? LTU
: GEU
);
8826 /* Convert a>b into b<a or a>=b-1. */
8829 if (GET_CODE (op1
) == CONST_INT
)
8831 op1
= gen_int_mode (INTVAL (op1
) + 1, GET_MODE (op0
));
8832 /* Bail out on overflow. We still can swap operands but that
8833 would force loading of the constant into register. */
8834 if (op1
== const0_rtx
8835 || !x86_64_immediate_operand (op1
, GET_MODE (op1
)))
8837 code
= (code
== GTU
? GEU
: LTU
);
8844 code
= (code
== GTU
? LTU
: GEU
);
8848 /* Convert a>=0 into (unsigned)a<0x80000000. */
8851 if (mode
== DImode
|| op1
!= const0_rtx
)
8853 op1
= gen_int_mode (1 << (GET_MODE_BITSIZE (mode
) - 1), mode
);
8854 code
= (code
== LT
? GEU
: LTU
);
8858 if (mode
== DImode
|| op1
!= constm1_rtx
)
8860 op1
= gen_int_mode (1 << (GET_MODE_BITSIZE (mode
) - 1), mode
);
8861 code
= (code
== LE
? GEU
: LTU
);
8867 /* Swapping operands may cause constant to appear as first operand. */
8868 if (!nonimmediate_operand (op0
, VOIDmode
))
8872 op0
= force_reg (mode
, op0
);
8874 ix86_compare_op0
= op0
;
8875 ix86_compare_op1
= op1
;
8876 *pop
= ix86_expand_compare (code
, NULL
, NULL
);
8877 if (GET_CODE (*pop
) != LTU
&& GET_CODE (*pop
) != GEU
)
8883 ix86_expand_int_movcc (rtx operands
[])
8885 enum rtx_code code
= GET_CODE (operands
[1]), compare_code
;
8886 rtx compare_seq
, compare_op
;
8887 rtx second_test
, bypass_test
;
8888 enum machine_mode mode
= GET_MODE (operands
[0]);
8889 bool sign_bit_compare_p
= false;;
8892 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
8893 compare_seq
= get_insns ();
8896 compare_code
= GET_CODE (compare_op
);
8898 if ((ix86_compare_op1
== const0_rtx
&& (code
== GE
|| code
== LT
))
8899 || (ix86_compare_op1
== constm1_rtx
&& (code
== GT
|| code
== LE
)))
8900 sign_bit_compare_p
= true;
8902 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
8903 HImode insns, we'd be swallowed in word prefix ops. */
8905 if ((mode
!= HImode
|| TARGET_FAST_PREFIX
)
8906 && (mode
!= DImode
|| TARGET_64BIT
)
8907 && GET_CODE (operands
[2]) == CONST_INT
8908 && GET_CODE (operands
[3]) == CONST_INT
)
8910 rtx out
= operands
[0];
8911 HOST_WIDE_INT ct
= INTVAL (operands
[2]);
8912 HOST_WIDE_INT cf
= INTVAL (operands
[3]);
8916 /* Sign bit compares are better done using shifts than we do by using
8918 if (sign_bit_compare_p
8919 || ix86_expand_carry_flag_compare (code
, ix86_compare_op0
,
8920 ix86_compare_op1
, &compare_op
))
8922 /* Detect overlap between destination and compare sources. */
8925 if (!sign_bit_compare_p
)
8929 compare_code
= GET_CODE (compare_op
);
8931 if (GET_MODE (XEXP (compare_op
, 0)) == CCFPmode
8932 || GET_MODE (XEXP (compare_op
, 0)) == CCFPUmode
)
8935 compare_code
= ix86_fp_compare_code_to_integer (compare_code
);
8938 /* To simplify rest of code, restrict to the GEU case. */
8939 if (compare_code
== LTU
)
8941 HOST_WIDE_INT tmp
= ct
;
8944 compare_code
= reverse_condition (compare_code
);
8945 code
= reverse_condition (code
);
8950 PUT_CODE (compare_op
,
8951 reverse_condition_maybe_unordered
8952 (GET_CODE (compare_op
)));
8954 PUT_CODE (compare_op
, reverse_condition (GET_CODE (compare_op
)));
8958 if (reg_overlap_mentioned_p (out
, ix86_compare_op0
)
8959 || reg_overlap_mentioned_p (out
, ix86_compare_op1
))
8960 tmp
= gen_reg_rtx (mode
);
8963 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp
, compare_op
));
8965 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode
, tmp
), compare_op
));
8969 if (code
== GT
|| code
== GE
)
8970 code
= reverse_condition (code
);
8973 HOST_WIDE_INT tmp
= ct
;
8978 tmp
= emit_store_flag (tmp
, code
, ix86_compare_op0
,
8979 ix86_compare_op1
, VOIDmode
, 0, -1);
8992 tmp
= expand_simple_binop (mode
, PLUS
,
8994 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9005 tmp
= expand_simple_binop (mode
, IOR
,
9007 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9009 else if (diff
== -1 && ct
)
9019 tmp
= expand_simple_unop (mode
, NOT
, tmp
, copy_rtx (tmp
), 1);
9021 tmp
= expand_simple_binop (mode
, PLUS
,
9022 copy_rtx (tmp
), GEN_INT (cf
),
9023 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9031 * andl cf - ct, dest
9041 tmp
= expand_simple_unop (mode
, NOT
, tmp
, copy_rtx (tmp
), 1);
9044 tmp
= expand_simple_binop (mode
, AND
,
9046 gen_int_mode (cf
- ct
, mode
),
9047 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9049 tmp
= expand_simple_binop (mode
, PLUS
,
9050 copy_rtx (tmp
), GEN_INT (ct
),
9051 copy_rtx (tmp
), 1, OPTAB_DIRECT
);
9054 if (!rtx_equal_p (tmp
, out
))
9055 emit_move_insn (copy_rtx (out
), copy_rtx (tmp
));
9057 return 1; /* DONE */
9063 tmp
= ct
, ct
= cf
, cf
= tmp
;
9065 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
9067 /* We may be reversing unordered compare to normal compare, that
9068 is not valid in general (we may convert non-trapping condition
9069 to trapping one), however on i386 we currently emit all
9070 comparisons unordered. */
9071 compare_code
= reverse_condition_maybe_unordered (compare_code
);
9072 code
= reverse_condition_maybe_unordered (code
);
9076 compare_code
= reverse_condition (compare_code
);
9077 code
= reverse_condition (code
);
9081 compare_code
= UNKNOWN
;
9082 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0
)) == MODE_INT
9083 && GET_CODE (ix86_compare_op1
) == CONST_INT
)
9085 if (ix86_compare_op1
== const0_rtx
9086 && (code
== LT
|| code
== GE
))
9087 compare_code
= code
;
9088 else if (ix86_compare_op1
== constm1_rtx
)
9092 else if (code
== GT
)
9097 /* Optimize dest = (op0 < 0) ? -1 : cf. */
9098 if (compare_code
!= UNKNOWN
9099 && GET_MODE (ix86_compare_op0
) == GET_MODE (out
)
9100 && (cf
== -1 || ct
== -1))
9102 /* If lea code below could be used, only optimize
9103 if it results in a 2 insn sequence. */
9105 if (! (diff
== 1 || diff
== 2 || diff
== 4 || diff
== 8
9106 || diff
== 3 || diff
== 5 || diff
== 9)
9107 || (compare_code
== LT
&& ct
== -1)
9108 || (compare_code
== GE
&& cf
== -1))
9111 * notl op1 (if necessary)
9119 code
= reverse_condition (code
);
9122 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9123 ix86_compare_op1
, VOIDmode
, 0, -1);
9125 out
= expand_simple_binop (mode
, IOR
,
9127 out
, 1, OPTAB_DIRECT
);
9128 if (out
!= operands
[0])
9129 emit_move_insn (operands
[0], out
);
9131 return 1; /* DONE */
9136 if ((diff
== 1 || diff
== 2 || diff
== 4 || diff
== 8
9137 || diff
== 3 || diff
== 5 || diff
== 9)
9138 && ((mode
!= QImode
&& mode
!= HImode
) || !TARGET_PARTIAL_REG_STALL
)
9140 || x86_64_immediate_operand (GEN_INT (cf
), VOIDmode
)))
9146 * lea cf(dest*(ct-cf)),dest
9150 * This also catches the degenerate setcc-only case.
9156 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9157 ix86_compare_op1
, VOIDmode
, 0, 1);
9160 /* On x86_64 the lea instruction operates on Pmode, so we need
9161 to get arithmetics done in proper mode to match. */
9163 tmp
= copy_rtx (out
);
9167 out1
= copy_rtx (out
);
9168 tmp
= gen_rtx_MULT (mode
, out1
, GEN_INT (diff
& ~1));
9172 tmp
= gen_rtx_PLUS (mode
, tmp
, out1
);
9178 tmp
= gen_rtx_PLUS (mode
, tmp
, GEN_INT (cf
));
9181 if (!rtx_equal_p (tmp
, out
))
9184 out
= force_operand (tmp
, copy_rtx (out
));
9186 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (out
), copy_rtx (tmp
)));
9188 if (!rtx_equal_p (out
, operands
[0]))
9189 emit_move_insn (operands
[0], copy_rtx (out
));
9191 return 1; /* DONE */
9195 * General case: Jumpful:
9196 * xorl dest,dest cmpl op1, op2
9197 * cmpl op1, op2 movl ct, dest
9199 * decl dest movl cf, dest
9200 * andl (cf-ct),dest 1:
9205 * This is reasonably steep, but branch mispredict costs are
9206 * high on modern cpus, so consider failing only if optimizing
9210 if ((!TARGET_CMOVE
|| (mode
== QImode
&& TARGET_PARTIAL_REG_STALL
))
9211 && BRANCH_COST
>= 2)
9217 if (FLOAT_MODE_P (GET_MODE (ix86_compare_op0
)))
9218 /* We may be reversing unordered compare to normal compare,
9219 that is not valid in general (we may convert non-trapping
9220 condition to trapping one), however on i386 we currently
9221 emit all comparisons unordered. */
9222 code
= reverse_condition_maybe_unordered (code
);
9225 code
= reverse_condition (code
);
9226 if (compare_code
!= UNKNOWN
)
9227 compare_code
= reverse_condition (compare_code
);
9231 if (compare_code
!= UNKNOWN
)
9233 /* notl op1 (if needed)
9238 For x < 0 (resp. x <= -1) there will be no notl,
9239 so if possible swap the constants to get rid of the
9241 True/false will be -1/0 while code below (store flag
9242 followed by decrement) is 0/-1, so the constants need
9243 to be exchanged once more. */
9245 if (compare_code
== GE
|| !cf
)
9247 code
= reverse_condition (code
);
9252 HOST_WIDE_INT tmp
= cf
;
9257 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9258 ix86_compare_op1
, VOIDmode
, 0, -1);
9262 out
= emit_store_flag (out
, code
, ix86_compare_op0
,
9263 ix86_compare_op1
, VOIDmode
, 0, 1);
9265 out
= expand_simple_binop (mode
, PLUS
, copy_rtx (out
), constm1_rtx
,
9266 copy_rtx (out
), 1, OPTAB_DIRECT
);
9269 out
= expand_simple_binop (mode
, AND
, copy_rtx (out
),
9270 gen_int_mode (cf
- ct
, mode
),
9271 copy_rtx (out
), 1, OPTAB_DIRECT
);
9273 out
= expand_simple_binop (mode
, PLUS
, copy_rtx (out
), GEN_INT (ct
),
9274 copy_rtx (out
), 1, OPTAB_DIRECT
);
9275 if (!rtx_equal_p (out
, operands
[0]))
9276 emit_move_insn (operands
[0], copy_rtx (out
));
9278 return 1; /* DONE */
9282 if (!TARGET_CMOVE
|| (mode
== QImode
&& TARGET_PARTIAL_REG_STALL
))
9284 /* Try a few things more with specific constants and a variable. */
9287 rtx var
, orig_out
, out
, tmp
;
9289 if (BRANCH_COST
<= 2)
9290 return 0; /* FAIL */
9292 /* If one of the two operands is an interesting constant, load a
9293 constant with the above and mask it in with a logical operation. */
9295 if (GET_CODE (operands
[2]) == CONST_INT
)
9298 if (INTVAL (operands
[2]) == 0 && operands
[3] != constm1_rtx
)
9299 operands
[3] = constm1_rtx
, op
= and_optab
;
9300 else if (INTVAL (operands
[2]) == -1 && operands
[3] != const0_rtx
)
9301 operands
[3] = const0_rtx
, op
= ior_optab
;
9303 return 0; /* FAIL */
9305 else if (GET_CODE (operands
[3]) == CONST_INT
)
9308 if (INTVAL (operands
[3]) == 0 && operands
[2] != constm1_rtx
)
9309 operands
[2] = constm1_rtx
, op
= and_optab
;
9310 else if (INTVAL (operands
[3]) == -1 && operands
[3] != const0_rtx
)
9311 operands
[2] = const0_rtx
, op
= ior_optab
;
9313 return 0; /* FAIL */
9316 return 0; /* FAIL */
9318 orig_out
= operands
[0];
9319 tmp
= gen_reg_rtx (mode
);
9322 /* Recurse to get the constant loaded. */
9323 if (ix86_expand_int_movcc (operands
) == 0)
9324 return 0; /* FAIL */
9326 /* Mask in the interesting variable. */
9327 out
= expand_binop (mode
, op
, var
, tmp
, orig_out
, 0,
9329 if (!rtx_equal_p (out
, orig_out
))
9330 emit_move_insn (copy_rtx (orig_out
), copy_rtx (out
));
9332 return 1; /* DONE */
9336 * For comparison with above,
9346 if (! nonimmediate_operand (operands
[2], mode
))
9347 operands
[2] = force_reg (mode
, operands
[2]);
9348 if (! nonimmediate_operand (operands
[3], mode
))
9349 operands
[3] = force_reg (mode
, operands
[3]);
9351 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
9353 rtx tmp
= gen_reg_rtx (mode
);
9354 emit_move_insn (tmp
, operands
[3]);
9357 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
9359 rtx tmp
= gen_reg_rtx (mode
);
9360 emit_move_insn (tmp
, operands
[2]);
9364 if (! register_operand (operands
[2], VOIDmode
)
9366 || ! register_operand (operands
[3], VOIDmode
)))
9367 operands
[2] = force_reg (mode
, operands
[2]);
9370 && ! register_operand (operands
[3], VOIDmode
))
9371 operands
[3] = force_reg (mode
, operands
[3]);
9373 emit_insn (compare_seq
);
9374 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9375 gen_rtx_IF_THEN_ELSE (mode
,
9376 compare_op
, operands
[2],
9379 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
9380 gen_rtx_IF_THEN_ELSE (mode
,
9382 copy_rtx (operands
[3]),
9383 copy_rtx (operands
[0]))));
9385 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (operands
[0]),
9386 gen_rtx_IF_THEN_ELSE (mode
,
9388 copy_rtx (operands
[2]),
9389 copy_rtx (operands
[0]))));
9391 return 1; /* DONE */
9395 ix86_expand_fp_movcc (rtx operands
[])
9399 rtx compare_op
, second_test
, bypass_test
;
9401 /* For SF/DFmode conditional moves based on comparisons
9402 in same mode, we may want to use SSE min/max instructions. */
9403 if (((TARGET_SSE_MATH
&& GET_MODE (operands
[0]) == SFmode
)
9404 || (TARGET_SSE2
&& TARGET_SSE_MATH
&& GET_MODE (operands
[0]) == DFmode
))
9405 && GET_MODE (ix86_compare_op0
) == GET_MODE (operands
[0])
9406 /* The SSE comparisons does not support the LTGT/UNEQ pair. */
9408 || (GET_CODE (operands
[1]) != LTGT
&& GET_CODE (operands
[1]) != UNEQ
))
9409 /* We may be called from the post-reload splitter. */
9410 && (!REG_P (operands
[0])
9411 || SSE_REG_P (operands
[0])
9412 || REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
9414 rtx op0
= ix86_compare_op0
, op1
= ix86_compare_op1
;
9415 code
= GET_CODE (operands
[1]);
9417 /* See if we have (cross) match between comparison operands and
9418 conditional move operands. */
9419 if (rtx_equal_p (operands
[2], op1
))
9424 code
= reverse_condition_maybe_unordered (code
);
9426 if (rtx_equal_p (operands
[2], op0
) && rtx_equal_p (operands
[3], op1
))
9428 /* Check for min operation. */
9429 if (code
== LT
|| code
== UNLE
)
9437 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
9438 if (memory_operand (op0
, VOIDmode
))
9439 op0
= force_reg (GET_MODE (operands
[0]), op0
);
9440 if (GET_MODE (operands
[0]) == SFmode
)
9441 emit_insn (gen_minsf3 (operands
[0], op0
, op1
));
9443 emit_insn (gen_mindf3 (operands
[0], op0
, op1
));
9446 /* Check for max operation. */
9447 if (code
== GT
|| code
== UNGE
)
9455 operands
[0] = force_reg (GET_MODE (operands
[0]), operands
[0]);
9456 if (memory_operand (op0
, VOIDmode
))
9457 op0
= force_reg (GET_MODE (operands
[0]), op0
);
9458 if (GET_MODE (operands
[0]) == SFmode
)
9459 emit_insn (gen_maxsf3 (operands
[0], op0
, op1
));
9461 emit_insn (gen_maxdf3 (operands
[0], op0
, op1
));
9465 /* Manage condition to be sse_comparison_operator. In case we are
9466 in non-ieee mode, try to canonicalize the destination operand
9467 to be first in the comparison - this helps reload to avoid extra
9469 if (!sse_comparison_operator (operands
[1], VOIDmode
)
9470 || (rtx_equal_p (operands
[0], ix86_compare_op1
) && !TARGET_IEEE_FP
))
9472 rtx tmp
= ix86_compare_op0
;
9473 ix86_compare_op0
= ix86_compare_op1
;
9474 ix86_compare_op1
= tmp
;
9475 operands
[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands
[1])),
9476 VOIDmode
, ix86_compare_op0
,
9479 /* Similarly try to manage result to be first operand of conditional
9480 move. We also don't support the NE comparison on SSE, so try to
9482 if ((rtx_equal_p (operands
[0], operands
[3])
9483 && (!TARGET_IEEE_FP
|| GET_CODE (operands
[1]) != EQ
))
9484 || (GET_CODE (operands
[1]) == NE
&& TARGET_IEEE_FP
))
9486 rtx tmp
= operands
[2];
9487 operands
[2] = operands
[3];
9489 operands
[1] = gen_rtx_fmt_ee (reverse_condition_maybe_unordered
9490 (GET_CODE (operands
[1])),
9491 VOIDmode
, ix86_compare_op0
,
9494 if (GET_MODE (operands
[0]) == SFmode
)
9495 emit_insn (gen_sse_movsfcc (operands
[0], operands
[1],
9496 operands
[2], operands
[3],
9497 ix86_compare_op0
, ix86_compare_op1
));
9499 emit_insn (gen_sse_movdfcc (operands
[0], operands
[1],
9500 operands
[2], operands
[3],
9501 ix86_compare_op0
, ix86_compare_op1
));
9505 /* The floating point conditional move instructions don't directly
9506 support conditions resulting from a signed integer comparison. */
9508 code
= GET_CODE (operands
[1]);
9509 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
9511 /* The floating point conditional move instructions don't directly
9512 support signed integer comparisons. */
9514 if (!fcmov_comparison_operator (compare_op
, VOIDmode
))
9516 if (second_test
!= NULL
|| bypass_test
!= NULL
)
9518 tmp
= gen_reg_rtx (QImode
);
9519 ix86_expand_setcc (code
, tmp
);
9521 ix86_compare_op0
= tmp
;
9522 ix86_compare_op1
= const0_rtx
;
9523 compare_op
= ix86_expand_compare (code
, &second_test
, &bypass_test
);
9525 if (bypass_test
&& reg_overlap_mentioned_p (operands
[0], operands
[3]))
9527 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
9528 emit_move_insn (tmp
, operands
[3]);
9531 if (second_test
&& reg_overlap_mentioned_p (operands
[0], operands
[2]))
9533 tmp
= gen_reg_rtx (GET_MODE (operands
[0]));
9534 emit_move_insn (tmp
, operands
[2]);
9538 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9539 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
9544 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9545 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
9550 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
9551 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
9559 /* Expand conditional increment or decrement using adb/sbb instructions.
9560 The default case using setcc followed by the conditional move can be
9561 done by generic code. */
9563 ix86_expand_int_addcc (rtx operands
[])
9565 enum rtx_code code
= GET_CODE (operands
[1]);
9567 rtx val
= const0_rtx
;
9569 enum machine_mode mode
= GET_MODE (operands
[0]);
9571 if (operands
[3] != const1_rtx
9572 && operands
[3] != constm1_rtx
)
9574 if (!ix86_expand_carry_flag_compare (code
, ix86_compare_op0
,
9575 ix86_compare_op1
, &compare_op
))
9577 code
= GET_CODE (compare_op
);
9579 if (GET_MODE (XEXP (compare_op
, 0)) == CCFPmode
9580 || GET_MODE (XEXP (compare_op
, 0)) == CCFPUmode
)
9583 code
= ix86_fp_compare_code_to_integer (code
);
9590 PUT_CODE (compare_op
,
9591 reverse_condition_maybe_unordered
9592 (GET_CODE (compare_op
)));
9594 PUT_CODE (compare_op
, reverse_condition (GET_CODE (compare_op
)));
9596 PUT_MODE (compare_op
, mode
);
9598 /* Construct either adc or sbb insn. */
9599 if ((code
== LTU
) == (operands
[3] == constm1_rtx
))
9601 switch (GET_MODE (operands
[0]))
9604 emit_insn (gen_subqi3_carry (operands
[0], operands
[2], val
, compare_op
));
9607 emit_insn (gen_subhi3_carry (operands
[0], operands
[2], val
, compare_op
));
9610 emit_insn (gen_subsi3_carry (operands
[0], operands
[2], val
, compare_op
));
9613 emit_insn (gen_subdi3_carry_rex64 (operands
[0], operands
[2], val
, compare_op
));
9621 switch (GET_MODE (operands
[0]))
9624 emit_insn (gen_addqi3_carry (operands
[0], operands
[2], val
, compare_op
));
9627 emit_insn (gen_addhi3_carry (operands
[0], operands
[2], val
, compare_op
));
9630 emit_insn (gen_addsi3_carry (operands
[0], operands
[2], val
, compare_op
));
9633 emit_insn (gen_adddi3_carry_rex64 (operands
[0], operands
[2], val
, compare_op
));
9639 return 1; /* DONE */
9643 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
9644 works for floating pointer parameters and nonoffsetable memories.
9645 For pushes, it returns just stack offsets; the values will be saved
9646 in the right order. Maximally three parts are generated. */
9649 ix86_split_to_parts (rtx operand
, rtx
*parts
, enum machine_mode mode
)
9654 size
= mode
==XFmode
? 3 : GET_MODE_SIZE (mode
) / 4;
9656 size
= (GET_MODE_SIZE (mode
) + 4) / 8;
9658 if (GET_CODE (operand
) == REG
&& MMX_REGNO_P (REGNO (operand
)))
9660 if (size
< 2 || size
> 3)
9663 /* Optimize constant pool reference to immediates. This is used by fp
9664 moves, that force all constants to memory to allow combining. */
9665 if (GET_CODE (operand
) == MEM
&& MEM_READONLY_P (operand
))
9667 rtx tmp
= maybe_get_pool_constant (operand
);
9672 if (GET_CODE (operand
) == MEM
&& !offsettable_memref_p (operand
))
9674 /* The only non-offsetable memories we handle are pushes. */
9675 if (! push_operand (operand
, VOIDmode
))
9678 operand
= copy_rtx (operand
);
9679 PUT_MODE (operand
, Pmode
);
9680 parts
[0] = parts
[1] = parts
[2] = operand
;
9682 else if (!TARGET_64BIT
)
9685 split_di (&operand
, 1, &parts
[0], &parts
[1]);
9688 if (REG_P (operand
))
9690 if (!reload_completed
)
9692 parts
[0] = gen_rtx_REG (SImode
, REGNO (operand
) + 0);
9693 parts
[1] = gen_rtx_REG (SImode
, REGNO (operand
) + 1);
9695 parts
[2] = gen_rtx_REG (SImode
, REGNO (operand
) + 2);
9697 else if (offsettable_memref_p (operand
))
9699 operand
= adjust_address (operand
, SImode
, 0);
9701 parts
[1] = adjust_address (operand
, SImode
, 4);
9703 parts
[2] = adjust_address (operand
, SImode
, 8);
9705 else if (GET_CODE (operand
) == CONST_DOUBLE
)
9710 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
9714 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
9715 parts
[2] = gen_int_mode (l
[2], SImode
);
9718 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
9723 parts
[1] = gen_int_mode (l
[1], SImode
);
9724 parts
[0] = gen_int_mode (l
[0], SImode
);
9733 split_ti (&operand
, 1, &parts
[0], &parts
[1]);
9734 if (mode
== XFmode
|| mode
== TFmode
)
9736 enum machine_mode upper_mode
= mode
==XFmode
? SImode
: DImode
;
9737 if (REG_P (operand
))
9739 if (!reload_completed
)
9741 parts
[0] = gen_rtx_REG (DImode
, REGNO (operand
) + 0);
9742 parts
[1] = gen_rtx_REG (upper_mode
, REGNO (operand
) + 1);
9744 else if (offsettable_memref_p (operand
))
9746 operand
= adjust_address (operand
, DImode
, 0);
9748 parts
[1] = adjust_address (operand
, upper_mode
, 8);
9750 else if (GET_CODE (operand
) == CONST_DOUBLE
)
9755 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
9756 real_to_target (l
, &r
, mode
);
9757 /* Do not use shift by 32 to avoid warning on 32bit systems. */
9758 if (HOST_BITS_PER_WIDE_INT
>= 64)
9761 ((l
[0] & (((HOST_WIDE_INT
) 2 << 31) - 1))
9762 + ((((HOST_WIDE_INT
) l
[1]) << 31) << 1),
9765 parts
[0] = immed_double_const (l
[0], l
[1], DImode
);
9766 if (upper_mode
== SImode
)
9767 parts
[1] = gen_int_mode (l
[2], SImode
);
9768 else if (HOST_BITS_PER_WIDE_INT
>= 64)
9771 ((l
[2] & (((HOST_WIDE_INT
) 2 << 31) - 1))
9772 + ((((HOST_WIDE_INT
) l
[3]) << 31) << 1),
9775 parts
[1] = immed_double_const (l
[2], l
[3], DImode
);
9785 /* Emit insns to perform a move or push of DI, DF, and XF values.
9786 Return false when normal moves are needed; true when all required
9787 insns have been emitted. Operands 2-4 contain the input values
9788 int the correct order; operands 5-7 contain the output values. */
9791 ix86_split_long_move (rtx operands
[])
9797 enum machine_mode mode
= GET_MODE (operands
[0]);
9799 /* The DFmode expanders may ask us to move double.
9800 For 64bit target this is single move. By hiding the fact
9801 here we simplify i386.md splitters. */
9802 if (GET_MODE_SIZE (GET_MODE (operands
[0])) == 8 && TARGET_64BIT
)
9804 /* Optimize constant pool reference to immediates. This is used by
9805 fp moves, that force all constants to memory to allow combining. */
9807 if (GET_CODE (operands
[1]) == MEM
9808 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
9809 && CONSTANT_POOL_ADDRESS_P (XEXP (operands
[1], 0)))
9810 operands
[1] = get_pool_constant (XEXP (operands
[1], 0));
9811 if (push_operand (operands
[0], VOIDmode
))
9813 operands
[0] = copy_rtx (operands
[0]);
9814 PUT_MODE (operands
[0], Pmode
);
9817 operands
[0] = gen_lowpart (DImode
, operands
[0]);
9818 operands
[1] = gen_lowpart (DImode
, operands
[1]);
9819 emit_move_insn (operands
[0], operands
[1]);
9823 /* The only non-offsettable memory we handle is push. */
9824 if (push_operand (operands
[0], VOIDmode
))
9826 else if (GET_CODE (operands
[0]) == MEM
9827 && ! offsettable_memref_p (operands
[0]))
9830 nparts
= ix86_split_to_parts (operands
[1], part
[1], GET_MODE (operands
[0]));
9831 ix86_split_to_parts (operands
[0], part
[0], GET_MODE (operands
[0]));
9833 /* When emitting push, take care for source operands on the stack. */
9834 if (push
&& GET_CODE (operands
[1]) == MEM
9835 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
9838 part
[1][1] = change_address (part
[1][1], GET_MODE (part
[1][1]),
9839 XEXP (part
[1][2], 0));
9840 part
[1][0] = change_address (part
[1][0], GET_MODE (part
[1][0]),
9841 XEXP (part
[1][1], 0));
9844 /* We need to do copy in the right order in case an address register
9845 of the source overlaps the destination. */
9846 if (REG_P (part
[0][0]) && GET_CODE (part
[1][0]) == MEM
)
9848 if (reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0)))
9850 if (reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
9853 && reg_overlap_mentioned_p (part
[0][2], XEXP (part
[1][0], 0)))
9856 /* Collision in the middle part can be handled by reordering. */
9857 if (collisions
== 1 && nparts
== 3
9858 && reg_overlap_mentioned_p (part
[0][1], XEXP (part
[1][0], 0)))
9861 tmp
= part
[0][1]; part
[0][1] = part
[0][2]; part
[0][2] = tmp
;
9862 tmp
= part
[1][1]; part
[1][1] = part
[1][2]; part
[1][2] = tmp
;
9865 /* If there are more collisions, we can't handle it by reordering.
9866 Do an lea to the last part and use only one colliding move. */
9867 else if (collisions
> 1)
9873 base
= part
[0][nparts
- 1];
9875 /* Handle the case when the last part isn't valid for lea.
9876 Happens in 64-bit mode storing the 12-byte XFmode. */
9877 if (GET_MODE (base
) != Pmode
)
9878 base
= gen_rtx_REG (Pmode
, REGNO (base
));
9880 emit_insn (gen_rtx_SET (VOIDmode
, base
, XEXP (part
[1][0], 0)));
9881 part
[1][0] = replace_equiv_address (part
[1][0], base
);
9882 part
[1][1] = replace_equiv_address (part
[1][1],
9883 plus_constant (base
, UNITS_PER_WORD
));
9885 part
[1][2] = replace_equiv_address (part
[1][2],
9886 plus_constant (base
, 8));
9896 if (TARGET_128BIT_LONG_DOUBLE
&& mode
== XFmode
)
9897 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, GEN_INT (-4)));
9898 emit_move_insn (part
[0][2], part
[1][2]);
9903 /* In 64bit mode we don't have 32bit push available. In case this is
9904 register, it is OK - we will just use larger counterpart. We also
9905 retype memory - these comes from attempt to avoid REX prefix on
9906 moving of second half of TFmode value. */
9907 if (GET_MODE (part
[1][1]) == SImode
)
9909 if (GET_CODE (part
[1][1]) == MEM
)
9910 part
[1][1] = adjust_address (part
[1][1], DImode
, 0);
9911 else if (REG_P (part
[1][1]))
9912 part
[1][1] = gen_rtx_REG (DImode
, REGNO (part
[1][1]));
9915 if (GET_MODE (part
[1][0]) == SImode
)
9916 part
[1][0] = part
[1][1];
9919 emit_move_insn (part
[0][1], part
[1][1]);
9920 emit_move_insn (part
[0][0], part
[1][0]);
9924 /* Choose correct order to not overwrite the source before it is copied. */
9925 if ((REG_P (part
[0][0])
9926 && REG_P (part
[1][1])
9927 && (REGNO (part
[0][0]) == REGNO (part
[1][1])
9929 && REGNO (part
[0][0]) == REGNO (part
[1][2]))))
9931 && reg_overlap_mentioned_p (part
[0][0], XEXP (part
[1][0], 0))))
9935 operands
[2] = part
[0][2];
9936 operands
[3] = part
[0][1];
9937 operands
[4] = part
[0][0];
9938 operands
[5] = part
[1][2];
9939 operands
[6] = part
[1][1];
9940 operands
[7] = part
[1][0];
9944 operands
[2] = part
[0][1];
9945 operands
[3] = part
[0][0];
9946 operands
[5] = part
[1][1];
9947 operands
[6] = part
[1][0];
9954 operands
[2] = part
[0][0];
9955 operands
[3] = part
[0][1];
9956 operands
[4] = part
[0][2];
9957 operands
[5] = part
[1][0];
9958 operands
[6] = part
[1][1];
9959 operands
[7] = part
[1][2];
9963 operands
[2] = part
[0][0];
9964 operands
[3] = part
[0][1];
9965 operands
[5] = part
[1][0];
9966 operands
[6] = part
[1][1];
9970 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
9973 if (GET_CODE (operands
[5]) == CONST_INT
9974 && operands
[5] != const0_rtx
9975 && REG_P (operands
[2]))
9977 if (GET_CODE (operands
[6]) == CONST_INT
9978 && INTVAL (operands
[6]) == INTVAL (operands
[5]))
9979 operands
[6] = operands
[2];
9982 && GET_CODE (operands
[7]) == CONST_INT
9983 && INTVAL (operands
[7]) == INTVAL (operands
[5]))
9984 operands
[7] = operands
[2];
9988 && GET_CODE (operands
[6]) == CONST_INT
9989 && operands
[6] != const0_rtx
9990 && REG_P (operands
[3])
9991 && GET_CODE (operands
[7]) == CONST_INT
9992 && INTVAL (operands
[7]) == INTVAL (operands
[6]))
9993 operands
[7] = operands
[3];
9996 emit_move_insn (operands
[2], operands
[5]);
9997 emit_move_insn (operands
[3], operands
[6]);
9999 emit_move_insn (operands
[4], operands
[7]);
10004 /* Helper function of ix86_split_ashldi used to generate an SImode
10005 left shift by a constant, either using a single shift or
10006 a sequence of add instructions. */
10009 ix86_expand_ashlsi3_const (rtx operand
, int count
)
10012 emit_insn (gen_addsi3 (operand
, operand
, operand
));
10013 else if (!optimize_size
10014 && count
* ix86_cost
->add
<= ix86_cost
->shift_const
)
10017 for (i
=0; i
<count
; i
++)
10018 emit_insn (gen_addsi3 (operand
, operand
, operand
));
10021 emit_insn (gen_ashlsi3 (operand
, operand
, GEN_INT (count
)));
10025 ix86_split_ashldi (rtx
*operands
, rtx scratch
)
10027 rtx low
[2], high
[2];
10030 if (GET_CODE (operands
[2]) == CONST_INT
)
10032 split_di (operands
, 2, low
, high
);
10033 count
= INTVAL (operands
[2]) & 63;
10037 emit_move_insn (high
[0], low
[1]);
10038 emit_move_insn (low
[0], const0_rtx
);
10041 ix86_expand_ashlsi3_const (high
[0], count
- 32);
10045 if (!rtx_equal_p (operands
[0], operands
[1]))
10046 emit_move_insn (operands
[0], operands
[1]);
10047 emit_insn (gen_x86_shld_1 (high
[0], low
[0], GEN_INT (count
)));
10048 ix86_expand_ashlsi3_const (low
[0], count
);
10053 split_di (operands
, 1, low
, high
);
10055 if (operands
[1] == const1_rtx
)
10057 /* Assuming we've chosen a QImode capable registers, then 1LL << N
10058 can be done with two 32-bit shifts, no branches, no cmoves. */
10059 if (ANY_QI_REG_P (low
[0]) && ANY_QI_REG_P (high
[0]))
10061 rtx s
, d
, flags
= gen_rtx_REG (CCZmode
, FLAGS_REG
);
10063 ix86_expand_clear (low
[0]);
10064 ix86_expand_clear (high
[0]);
10065 emit_insn (gen_testqi_ccz_1 (operands
[2], GEN_INT (32)));
10067 d
= gen_lowpart (QImode
, low
[0]);
10068 d
= gen_rtx_STRICT_LOW_PART (VOIDmode
, d
);
10069 s
= gen_rtx_EQ (QImode
, flags
, const0_rtx
);
10070 emit_insn (gen_rtx_SET (VOIDmode
, d
, s
));
10072 d
= gen_lowpart (QImode
, high
[0]);
10073 d
= gen_rtx_STRICT_LOW_PART (VOIDmode
, d
);
10074 s
= gen_rtx_NE (QImode
, flags
, const0_rtx
);
10075 emit_insn (gen_rtx_SET (VOIDmode
, d
, s
));
10078 /* Otherwise, we can get the same results by manually performing
10079 a bit extract operation on bit 5, and then performing the two
10080 shifts. The two methods of getting 0/1 into low/high are exactly
10081 the same size. Avoiding the shift in the bit extract case helps
10082 pentium4 a bit; no one else seems to care much either way. */
10087 if (TARGET_PARTIAL_REG_STALL
&& !optimize_size
)
10088 x
= gen_rtx_ZERO_EXTEND (SImode
, operands
[2]);
10090 x
= gen_lowpart (SImode
, operands
[2]);
10091 emit_insn (gen_rtx_SET (VOIDmode
, high
[0], x
));
10093 emit_insn (gen_lshrsi3 (high
[0], high
[0], GEN_INT (5)));
10094 emit_insn (gen_andsi3 (high
[0], high
[0], GEN_INT (1)));
10095 emit_move_insn (low
[0], high
[0]);
10096 emit_insn (gen_xorsi3 (low
[0], low
[0], GEN_INT (1)));
10099 emit_insn (gen_ashlsi3 (low
[0], low
[0], operands
[2]));
10100 emit_insn (gen_ashlsi3 (high
[0], high
[0], operands
[2]));
10104 if (operands
[1] == constm1_rtx
)
10106 /* For -1LL << N, we can avoid the shld instruction, because we
10107 know that we're shifting 0...31 ones into a -1. */
10108 emit_move_insn (low
[0], constm1_rtx
);
10110 emit_move_insn (high
[0], low
[0]);
10112 emit_move_insn (high
[0], constm1_rtx
);
10116 if (!rtx_equal_p (operands
[0], operands
[1]))
10117 emit_move_insn (operands
[0], operands
[1]);
10119 split_di (operands
, 1, low
, high
);
10120 emit_insn (gen_x86_shld_1 (high
[0], low
[0], operands
[2]));
10123 emit_insn (gen_ashlsi3 (low
[0], low
[0], operands
[2]));
10125 if (TARGET_CMOVE
&& scratch
)
10127 ix86_expand_clear (scratch
);
10128 emit_insn (gen_x86_shift_adj_1 (high
[0], low
[0], operands
[2], scratch
));
10131 emit_insn (gen_x86_shift_adj_2 (high
[0], low
[0], operands
[2]));
10135 ix86_split_ashrdi (rtx
*operands
, rtx scratch
)
10137 rtx low
[2], high
[2];
10140 if (GET_CODE (operands
[2]) == CONST_INT
)
10142 split_di (operands
, 2, low
, high
);
10143 count
= INTVAL (operands
[2]) & 63;
10147 emit_move_insn (high
[0], high
[1]);
10148 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (31)));
10149 emit_move_insn (low
[0], high
[0]);
10152 else if (count
>= 32)
10154 emit_move_insn (low
[0], high
[1]);
10155 emit_move_insn (high
[0], low
[0]);
10156 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (31)));
10158 emit_insn (gen_ashrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
10162 if (!rtx_equal_p (operands
[0], operands
[1]))
10163 emit_move_insn (operands
[0], operands
[1]);
10164 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
10165 emit_insn (gen_ashrsi3 (high
[0], high
[0], GEN_INT (count
)));
10170 if (!rtx_equal_p (operands
[0], operands
[1]))
10171 emit_move_insn (operands
[0], operands
[1]);
10173 split_di (operands
, 1, low
, high
);
10175 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
10176 emit_insn (gen_ashrsi3 (high
[0], high
[0], operands
[2]));
10178 if (TARGET_CMOVE
&& scratch
)
10180 emit_move_insn (scratch
, high
[0]);
10181 emit_insn (gen_ashrsi3 (scratch
, scratch
, GEN_INT (31)));
10182 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
10186 emit_insn (gen_x86_shift_adj_3 (low
[0], high
[0], operands
[2]));
10191 ix86_split_lshrdi (rtx
*operands
, rtx scratch
)
10193 rtx low
[2], high
[2];
10196 if (GET_CODE (operands
[2]) == CONST_INT
)
10198 split_di (operands
, 2, low
, high
);
10199 count
= INTVAL (operands
[2]) & 63;
10203 emit_move_insn (low
[0], high
[1]);
10204 ix86_expand_clear (high
[0]);
10207 emit_insn (gen_lshrsi3 (low
[0], low
[0], GEN_INT (count
- 32)));
10211 if (!rtx_equal_p (operands
[0], operands
[1]))
10212 emit_move_insn (operands
[0], operands
[1]);
10213 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], GEN_INT (count
)));
10214 emit_insn (gen_lshrsi3 (high
[0], high
[0], GEN_INT (count
)));
10219 if (!rtx_equal_p (operands
[0], operands
[1]))
10220 emit_move_insn (operands
[0], operands
[1]);
10222 split_di (operands
, 1, low
, high
);
10224 emit_insn (gen_x86_shrd_1 (low
[0], high
[0], operands
[2]));
10225 emit_insn (gen_lshrsi3 (high
[0], high
[0], operands
[2]));
10227 /* Heh. By reversing the arguments, we can reuse this pattern. */
10228 if (TARGET_CMOVE
&& scratch
)
10230 ix86_expand_clear (scratch
);
10231 emit_insn (gen_x86_shift_adj_1 (low
[0], high
[0], operands
[2],
10235 emit_insn (gen_x86_shift_adj_2 (low
[0], high
[0], operands
[2]));
10239 /* Helper function for the string operations below. Dest VARIABLE whether
10240 it is aligned to VALUE bytes. If true, jump to the label. */
10242 ix86_expand_aligntest (rtx variable
, int value
)
10244 rtx label
= gen_label_rtx ();
10245 rtx tmpcount
= gen_reg_rtx (GET_MODE (variable
));
10246 if (GET_MODE (variable
) == DImode
)
10247 emit_insn (gen_anddi3 (tmpcount
, variable
, GEN_INT (value
)));
10249 emit_insn (gen_andsi3 (tmpcount
, variable
, GEN_INT (value
)));
10250 emit_cmp_and_jump_insns (tmpcount
, const0_rtx
, EQ
, 0, GET_MODE (variable
),
10255 /* Adjust COUNTER by the VALUE. */
10257 ix86_adjust_counter (rtx countreg
, HOST_WIDE_INT value
)
10259 if (GET_MODE (countreg
) == DImode
)
10260 emit_insn (gen_adddi3 (countreg
, countreg
, GEN_INT (-value
)));
10262 emit_insn (gen_addsi3 (countreg
, countreg
, GEN_INT (-value
)));
10265 /* Zero extend possibly SImode EXP to Pmode register. */
10267 ix86_zero_extend_to_Pmode (rtx exp
)
10270 if (GET_MODE (exp
) == VOIDmode
)
10271 return force_reg (Pmode
, exp
);
10272 if (GET_MODE (exp
) == Pmode
)
10273 return copy_to_mode_reg (Pmode
, exp
);
10274 r
= gen_reg_rtx (Pmode
);
10275 emit_insn (gen_zero_extendsidi2 (r
, exp
));
10279 /* Expand string move (memcpy) operation. Use i386 string operations when
10280 profitable. expand_clrmem contains similar code. */
10282 ix86_expand_movmem (rtx dst
, rtx src
, rtx count_exp
, rtx align_exp
)
10284 rtx srcreg
, destreg
, countreg
, srcexp
, destexp
;
10285 enum machine_mode counter_mode
;
10286 HOST_WIDE_INT align
= 0;
10287 unsigned HOST_WIDE_INT count
= 0;
10289 if (GET_CODE (align_exp
) == CONST_INT
)
10290 align
= INTVAL (align_exp
);
10292 /* Can't use any of this if the user has appropriated esi or edi. */
10293 if (global_regs
[4] || global_regs
[5])
10296 /* This simple hack avoids all inlining code and simplifies code below. */
10297 if (!TARGET_ALIGN_STRINGOPS
)
10300 if (GET_CODE (count_exp
) == CONST_INT
)
10302 count
= INTVAL (count_exp
);
10303 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
10307 /* Figure out proper mode for counter. For 32bits it is always SImode,
10308 for 64bits use SImode when possible, otherwise DImode.
10309 Set count to number of bytes copied when known at compile time. */
10311 || GET_MODE (count_exp
) == SImode
10312 || x86_64_zext_immediate_operand (count_exp
, VOIDmode
))
10313 counter_mode
= SImode
;
10315 counter_mode
= DImode
;
10317 if (counter_mode
!= SImode
&& counter_mode
!= DImode
)
10320 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
10321 if (destreg
!= XEXP (dst
, 0))
10322 dst
= replace_equiv_address_nv (dst
, destreg
);
10323 srcreg
= copy_to_mode_reg (Pmode
, XEXP (src
, 0));
10324 if (srcreg
!= XEXP (src
, 0))
10325 src
= replace_equiv_address_nv (src
, srcreg
);
10327 /* When optimizing for size emit simple rep ; movsb instruction for
10328 counts not divisible by 4. */
10330 if ((!optimize
|| optimize_size
) && (count
== 0 || (count
& 0x03)))
10332 emit_insn (gen_cld ());
10333 countreg
= ix86_zero_extend_to_Pmode (count_exp
);
10334 destexp
= gen_rtx_PLUS (Pmode
, destreg
, countreg
);
10335 srcexp
= gen_rtx_PLUS (Pmode
, srcreg
, countreg
);
10336 emit_insn (gen_rep_mov (destreg
, dst
, srcreg
, src
, countreg
,
10340 /* For constant aligned (or small unaligned) copies use rep movsl
10341 followed by code copying the rest. For PentiumPro ensure 8 byte
10342 alignment to allow rep movsl acceleration. */
10344 else if (count
!= 0
10346 || (!TARGET_PENTIUMPRO
&& !TARGET_64BIT
&& align
>= 4)
10347 || optimize_size
|| count
< (unsigned int) 64))
10349 unsigned HOST_WIDE_INT offset
= 0;
10350 int size
= TARGET_64BIT
&& !optimize_size
? 8 : 4;
10351 rtx srcmem
, dstmem
;
10353 emit_insn (gen_cld ());
10354 if (count
& ~(size
- 1))
10356 countreg
= copy_to_mode_reg (counter_mode
,
10357 GEN_INT ((count
>> (size
== 4 ? 2 : 3))
10358 & (TARGET_64BIT
? -1 : 0x3fffffff)));
10359 countreg
= ix86_zero_extend_to_Pmode (countreg
);
10361 destexp
= gen_rtx_ASHIFT (Pmode
, countreg
,
10362 GEN_INT (size
== 4 ? 2 : 3));
10363 srcexp
= gen_rtx_PLUS (Pmode
, destexp
, srcreg
);
10364 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10366 emit_insn (gen_rep_mov (destreg
, dst
, srcreg
, src
,
10367 countreg
, destexp
, srcexp
));
10368 offset
= count
& ~(size
- 1);
10370 if (size
== 8 && (count
& 0x04))
10372 srcmem
= adjust_automodify_address_nv (src
, SImode
, srcreg
,
10374 dstmem
= adjust_automodify_address_nv (dst
, SImode
, destreg
,
10376 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10381 srcmem
= adjust_automodify_address_nv (src
, HImode
, srcreg
,
10383 dstmem
= adjust_automodify_address_nv (dst
, HImode
, destreg
,
10385 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10390 srcmem
= adjust_automodify_address_nv (src
, QImode
, srcreg
,
10392 dstmem
= adjust_automodify_address_nv (dst
, QImode
, destreg
,
10394 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10397 /* The generic code based on the glibc implementation:
10398 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
10399 allowing accelerated copying there)
10400 - copy the data using rep movsl
10401 - copy the rest. */
10406 rtx srcmem
, dstmem
;
10407 int desired_alignment
= (TARGET_PENTIUMPRO
10408 && (count
== 0 || count
>= (unsigned int) 260)
10409 ? 8 : UNITS_PER_WORD
);
10410 /* Get rid of MEM_OFFSETs, they won't be accurate. */
10411 dst
= change_address (dst
, BLKmode
, destreg
);
10412 src
= change_address (src
, BLKmode
, srcreg
);
10414 /* In case we don't know anything about the alignment, default to
10415 library version, since it is usually equally fast and result in
10418 Also emit call when we know that the count is large and call overhead
10419 will not be important. */
10420 if (!TARGET_INLINE_ALL_STRINGOPS
10421 && (align
< UNITS_PER_WORD
|| !TARGET_REP_MOVL_OPTIMAL
))
10424 if (TARGET_SINGLE_STRINGOP
)
10425 emit_insn (gen_cld ());
10427 countreg2
= gen_reg_rtx (Pmode
);
10428 countreg
= copy_to_mode_reg (counter_mode
, count_exp
);
10430 /* We don't use loops to align destination and to copy parts smaller
10431 than 4 bytes, because gcc is able to optimize such code better (in
10432 the case the destination or the count really is aligned, gcc is often
10433 able to predict the branches) and also it is friendlier to the
10434 hardware branch prediction.
10436 Using loops is beneficial for generic case, because we can
10437 handle small counts using the loops. Many CPUs (such as Athlon)
10438 have large REP prefix setup costs.
10440 This is quite costly. Maybe we can revisit this decision later or
10441 add some customizability to this code. */
10443 if (count
== 0 && align
< desired_alignment
)
10445 label
= gen_label_rtx ();
10446 emit_cmp_and_jump_insns (countreg
, GEN_INT (desired_alignment
- 1),
10447 LEU
, 0, counter_mode
, 1, label
);
10451 rtx label
= ix86_expand_aligntest (destreg
, 1);
10452 srcmem
= change_address (src
, QImode
, srcreg
);
10453 dstmem
= change_address (dst
, QImode
, destreg
);
10454 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10455 ix86_adjust_counter (countreg
, 1);
10456 emit_label (label
);
10457 LABEL_NUSES (label
) = 1;
10461 rtx label
= ix86_expand_aligntest (destreg
, 2);
10462 srcmem
= change_address (src
, HImode
, srcreg
);
10463 dstmem
= change_address (dst
, HImode
, destreg
);
10464 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10465 ix86_adjust_counter (countreg
, 2);
10466 emit_label (label
);
10467 LABEL_NUSES (label
) = 1;
10469 if (align
<= 4 && desired_alignment
> 4)
10471 rtx label
= ix86_expand_aligntest (destreg
, 4);
10472 srcmem
= change_address (src
, SImode
, srcreg
);
10473 dstmem
= change_address (dst
, SImode
, destreg
);
10474 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10475 ix86_adjust_counter (countreg
, 4);
10476 emit_label (label
);
10477 LABEL_NUSES (label
) = 1;
10480 if (label
&& desired_alignment
> 4 && !TARGET_64BIT
)
10482 emit_label (label
);
10483 LABEL_NUSES (label
) = 1;
10486 if (!TARGET_SINGLE_STRINGOP
)
10487 emit_insn (gen_cld ());
10490 emit_insn (gen_lshrdi3 (countreg2
, ix86_zero_extend_to_Pmode (countreg
),
10492 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, GEN_INT (3));
10496 emit_insn (gen_lshrsi3 (countreg2
, countreg
, const2_rtx
));
10497 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, const2_rtx
);
10499 srcexp
= gen_rtx_PLUS (Pmode
, destexp
, srcreg
);
10500 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10501 emit_insn (gen_rep_mov (destreg
, dst
, srcreg
, src
,
10502 countreg2
, destexp
, srcexp
));
10506 emit_label (label
);
10507 LABEL_NUSES (label
) = 1;
10509 if (TARGET_64BIT
&& align
> 4 && count
!= 0 && (count
& 4))
10511 srcmem
= change_address (src
, SImode
, srcreg
);
10512 dstmem
= change_address (dst
, SImode
, destreg
);
10513 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10515 if ((align
<= 4 || count
== 0) && TARGET_64BIT
)
10517 rtx label
= ix86_expand_aligntest (countreg
, 4);
10518 srcmem
= change_address (src
, SImode
, srcreg
);
10519 dstmem
= change_address (dst
, SImode
, destreg
);
10520 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10521 emit_label (label
);
10522 LABEL_NUSES (label
) = 1;
10524 if (align
> 2 && count
!= 0 && (count
& 2))
10526 srcmem
= change_address (src
, HImode
, srcreg
);
10527 dstmem
= change_address (dst
, HImode
, destreg
);
10528 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10530 if (align
<= 2 || count
== 0)
10532 rtx label
= ix86_expand_aligntest (countreg
, 2);
10533 srcmem
= change_address (src
, HImode
, srcreg
);
10534 dstmem
= change_address (dst
, HImode
, destreg
);
10535 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10536 emit_label (label
);
10537 LABEL_NUSES (label
) = 1;
10539 if (align
> 1 && count
!= 0 && (count
& 1))
10541 srcmem
= change_address (src
, QImode
, srcreg
);
10542 dstmem
= change_address (dst
, QImode
, destreg
);
10543 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10545 if (align
<= 1 || count
== 0)
10547 rtx label
= ix86_expand_aligntest (countreg
, 1);
10548 srcmem
= change_address (src
, QImode
, srcreg
);
10549 dstmem
= change_address (dst
, QImode
, destreg
);
10550 emit_insn (gen_strmov (destreg
, dstmem
, srcreg
, srcmem
));
10551 emit_label (label
);
10552 LABEL_NUSES (label
) = 1;
10559 /* Expand string clear operation (bzero). Use i386 string operations when
10560 profitable. expand_movmem contains similar code. */
10562 ix86_expand_clrmem (rtx dst
, rtx count_exp
, rtx align_exp
)
10564 rtx destreg
, zeroreg
, countreg
, destexp
;
10565 enum machine_mode counter_mode
;
10566 HOST_WIDE_INT align
= 0;
10567 unsigned HOST_WIDE_INT count
= 0;
10569 if (GET_CODE (align_exp
) == CONST_INT
)
10570 align
= INTVAL (align_exp
);
10572 /* Can't use any of this if the user has appropriated esi. */
10573 if (global_regs
[4])
10576 /* This simple hack avoids all inlining code and simplifies code below. */
10577 if (!TARGET_ALIGN_STRINGOPS
)
10580 if (GET_CODE (count_exp
) == CONST_INT
)
10582 count
= INTVAL (count_exp
);
10583 if (!TARGET_INLINE_ALL_STRINGOPS
&& count
> 64)
10586 /* Figure out proper mode for counter. For 32bits it is always SImode,
10587 for 64bits use SImode when possible, otherwise DImode.
10588 Set count to number of bytes copied when known at compile time. */
10590 || GET_MODE (count_exp
) == SImode
10591 || x86_64_zext_immediate_operand (count_exp
, VOIDmode
))
10592 counter_mode
= SImode
;
10594 counter_mode
= DImode
;
10596 destreg
= copy_to_mode_reg (Pmode
, XEXP (dst
, 0));
10597 if (destreg
!= XEXP (dst
, 0))
10598 dst
= replace_equiv_address_nv (dst
, destreg
);
10601 /* When optimizing for size emit simple rep ; movsb instruction for
10602 counts not divisible by 4. The movl $N, %ecx; rep; stosb
10603 sequence is 7 bytes long, so if optimizing for size and count is
10604 small enough that some stosl, stosw and stosb instructions without
10605 rep are shorter, fall back into the next if. */
10607 if ((!optimize
|| optimize_size
)
10610 && (!optimize_size
|| (count
& 0x03) + (count
>> 2) > 7))))
10612 emit_insn (gen_cld ());
10614 countreg
= ix86_zero_extend_to_Pmode (count_exp
);
10615 zeroreg
= copy_to_mode_reg (QImode
, const0_rtx
);
10616 destexp
= gen_rtx_PLUS (Pmode
, destreg
, countreg
);
10617 emit_insn (gen_rep_stos (destreg
, countreg
, dst
, zeroreg
, destexp
));
10619 else if (count
!= 0
10621 || (!TARGET_PENTIUMPRO
&& !TARGET_64BIT
&& align
>= 4)
10622 || optimize_size
|| count
< (unsigned int) 64))
10624 int size
= TARGET_64BIT
&& !optimize_size
? 8 : 4;
10625 unsigned HOST_WIDE_INT offset
= 0;
10627 emit_insn (gen_cld ());
10629 zeroreg
= copy_to_mode_reg (size
== 4 ? SImode
: DImode
, const0_rtx
);
10630 if (count
& ~(size
- 1))
10632 unsigned HOST_WIDE_INT repcount
;
10633 unsigned int max_nonrep
;
10635 repcount
= count
>> (size
== 4 ? 2 : 3);
10637 repcount
&= 0x3fffffff;
10639 /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes.
10640 movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN
10641 bytes. In both cases the latter seems to be faster for small
10643 max_nonrep
= size
== 4 ? 7 : 4;
10644 if (!optimize_size
)
10647 case PROCESSOR_PENTIUM4
:
10648 case PROCESSOR_NOCONA
:
10655 if (repcount
<= max_nonrep
)
10656 while (repcount
-- > 0)
10658 rtx mem
= adjust_automodify_address_nv (dst
,
10659 GET_MODE (zeroreg
),
10661 emit_insn (gen_strset (destreg
, mem
, zeroreg
));
10666 countreg
= copy_to_mode_reg (counter_mode
, GEN_INT (repcount
));
10667 countreg
= ix86_zero_extend_to_Pmode (countreg
);
10668 destexp
= gen_rtx_ASHIFT (Pmode
, countreg
,
10669 GEN_INT (size
== 4 ? 2 : 3));
10670 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10671 emit_insn (gen_rep_stos (destreg
, countreg
, dst
, zeroreg
,
10673 offset
= count
& ~(size
- 1);
10676 if (size
== 8 && (count
& 0x04))
10678 rtx mem
= adjust_automodify_address_nv (dst
, SImode
, destreg
,
10680 emit_insn (gen_strset (destreg
, mem
,
10681 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
10686 rtx mem
= adjust_automodify_address_nv (dst
, HImode
, destreg
,
10688 emit_insn (gen_strset (destreg
, mem
,
10689 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10694 rtx mem
= adjust_automodify_address_nv (dst
, QImode
, destreg
,
10696 emit_insn (gen_strset (destreg
, mem
,
10697 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10704 /* Compute desired alignment of the string operation. */
10705 int desired_alignment
= (TARGET_PENTIUMPRO
10706 && (count
== 0 || count
>= (unsigned int) 260)
10707 ? 8 : UNITS_PER_WORD
);
10709 /* In case we don't know anything about the alignment, default to
10710 library version, since it is usually equally fast and result in
10713 Also emit call when we know that the count is large and call overhead
10714 will not be important. */
10715 if (!TARGET_INLINE_ALL_STRINGOPS
10716 && (align
< UNITS_PER_WORD
|| !TARGET_REP_MOVL_OPTIMAL
))
10719 if (TARGET_SINGLE_STRINGOP
)
10720 emit_insn (gen_cld ());
10722 countreg2
= gen_reg_rtx (Pmode
);
10723 countreg
= copy_to_mode_reg (counter_mode
, count_exp
);
10724 zeroreg
= copy_to_mode_reg (Pmode
, const0_rtx
);
10725 /* Get rid of MEM_OFFSET, it won't be accurate. */
10726 dst
= change_address (dst
, BLKmode
, destreg
);
10728 if (count
== 0 && align
< desired_alignment
)
10730 label
= gen_label_rtx ();
10731 emit_cmp_and_jump_insns (countreg
, GEN_INT (desired_alignment
- 1),
10732 LEU
, 0, counter_mode
, 1, label
);
10736 rtx label
= ix86_expand_aligntest (destreg
, 1);
10737 emit_insn (gen_strset (destreg
, dst
,
10738 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10739 ix86_adjust_counter (countreg
, 1);
10740 emit_label (label
);
10741 LABEL_NUSES (label
) = 1;
10745 rtx label
= ix86_expand_aligntest (destreg
, 2);
10746 emit_insn (gen_strset (destreg
, dst
,
10747 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10748 ix86_adjust_counter (countreg
, 2);
10749 emit_label (label
);
10750 LABEL_NUSES (label
) = 1;
10752 if (align
<= 4 && desired_alignment
> 4)
10754 rtx label
= ix86_expand_aligntest (destreg
, 4);
10755 emit_insn (gen_strset (destreg
, dst
,
10757 ? gen_rtx_SUBREG (SImode
, zeroreg
, 0)
10759 ix86_adjust_counter (countreg
, 4);
10760 emit_label (label
);
10761 LABEL_NUSES (label
) = 1;
10764 if (label
&& desired_alignment
> 4 && !TARGET_64BIT
)
10766 emit_label (label
);
10767 LABEL_NUSES (label
) = 1;
10771 if (!TARGET_SINGLE_STRINGOP
)
10772 emit_insn (gen_cld ());
10775 emit_insn (gen_lshrdi3 (countreg2
, ix86_zero_extend_to_Pmode (countreg
),
10777 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, GEN_INT (3));
10781 emit_insn (gen_lshrsi3 (countreg2
, countreg
, const2_rtx
));
10782 destexp
= gen_rtx_ASHIFT (Pmode
, countreg2
, const2_rtx
);
10784 destexp
= gen_rtx_PLUS (Pmode
, destexp
, destreg
);
10785 emit_insn (gen_rep_stos (destreg
, countreg2
, dst
, zeroreg
, destexp
));
10789 emit_label (label
);
10790 LABEL_NUSES (label
) = 1;
10793 if (TARGET_64BIT
&& align
> 4 && count
!= 0 && (count
& 4))
10794 emit_insn (gen_strset (destreg
, dst
,
10795 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
10796 if (TARGET_64BIT
&& (align
<= 4 || count
== 0))
10798 rtx label
= ix86_expand_aligntest (countreg
, 4);
10799 emit_insn (gen_strset (destreg
, dst
,
10800 gen_rtx_SUBREG (SImode
, zeroreg
, 0)));
10801 emit_label (label
);
10802 LABEL_NUSES (label
) = 1;
10804 if (align
> 2 && count
!= 0 && (count
& 2))
10805 emit_insn (gen_strset (destreg
, dst
,
10806 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10807 if (align
<= 2 || count
== 0)
10809 rtx label
= ix86_expand_aligntest (countreg
, 2);
10810 emit_insn (gen_strset (destreg
, dst
,
10811 gen_rtx_SUBREG (HImode
, zeroreg
, 0)));
10812 emit_label (label
);
10813 LABEL_NUSES (label
) = 1;
10815 if (align
> 1 && count
!= 0 && (count
& 1))
10816 emit_insn (gen_strset (destreg
, dst
,
10817 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10818 if (align
<= 1 || count
== 0)
10820 rtx label
= ix86_expand_aligntest (countreg
, 1);
10821 emit_insn (gen_strset (destreg
, dst
,
10822 gen_rtx_SUBREG (QImode
, zeroreg
, 0)));
10823 emit_label (label
);
10824 LABEL_NUSES (label
) = 1;
10830 /* Expand strlen. */
10832 ix86_expand_strlen (rtx out
, rtx src
, rtx eoschar
, rtx align
)
10834 rtx addr
, scratch1
, scratch2
, scratch3
, scratch4
;
10836 /* The generic case of strlen expander is long. Avoid it's
10837 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
10839 if (TARGET_UNROLL_STRLEN
&& eoschar
== const0_rtx
&& optimize
> 1
10840 && !TARGET_INLINE_ALL_STRINGOPS
10842 && (GET_CODE (align
) != CONST_INT
|| INTVAL (align
) < 4))
10845 addr
= force_reg (Pmode
, XEXP (src
, 0));
10846 scratch1
= gen_reg_rtx (Pmode
);
10848 if (TARGET_UNROLL_STRLEN
&& eoschar
== const0_rtx
&& optimize
> 1
10851 /* Well it seems that some optimizer does not combine a call like
10852 foo(strlen(bar), strlen(bar));
10853 when the move and the subtraction is done here. It does calculate
10854 the length just once when these instructions are done inside of
10855 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
10856 often used and I use one fewer register for the lifetime of
10857 output_strlen_unroll() this is better. */
10859 emit_move_insn (out
, addr
);
10861 ix86_expand_strlensi_unroll_1 (out
, src
, align
);
10863 /* strlensi_unroll_1 returns the address of the zero at the end of
10864 the string, like memchr(), so compute the length by subtracting
10865 the start address. */
10867 emit_insn (gen_subdi3 (out
, out
, addr
));
10869 emit_insn (gen_subsi3 (out
, out
, addr
));
10874 scratch2
= gen_reg_rtx (Pmode
);
10875 scratch3
= gen_reg_rtx (Pmode
);
10876 scratch4
= force_reg (Pmode
, constm1_rtx
);
10878 emit_move_insn (scratch3
, addr
);
10879 eoschar
= force_reg (QImode
, eoschar
);
10881 emit_insn (gen_cld ());
10882 src
= replace_equiv_address_nv (src
, scratch3
);
10884 /* If .md starts supporting :P, this can be done in .md. */
10885 unspec
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (4, src
, eoschar
, align
,
10886 scratch4
), UNSPEC_SCAS
);
10887 emit_insn (gen_strlenqi_1 (scratch1
, scratch3
, unspec
));
10890 emit_insn (gen_one_cmpldi2 (scratch2
, scratch1
));
10891 emit_insn (gen_adddi3 (out
, scratch2
, constm1_rtx
));
10895 emit_insn (gen_one_cmplsi2 (scratch2
, scratch1
));
10896 emit_insn (gen_addsi3 (out
, scratch2
, constm1_rtx
));
10902 /* Expand the appropriate insns for doing strlen if not just doing
10905 out = result, initialized with the start address
10906 align_rtx = alignment of the address.
10907 scratch = scratch register, initialized with the startaddress when
10908 not aligned, otherwise undefined
10910 This is just the body. It needs the initializations mentioned above and
10911 some address computing at the end. These things are done in i386.md. */
10914 ix86_expand_strlensi_unroll_1 (rtx out
, rtx src
, rtx align_rtx
)
10918 rtx align_2_label
= NULL_RTX
;
10919 rtx align_3_label
= NULL_RTX
;
10920 rtx align_4_label
= gen_label_rtx ();
10921 rtx end_0_label
= gen_label_rtx ();
10923 rtx tmpreg
= gen_reg_rtx (SImode
);
10924 rtx scratch
= gen_reg_rtx (SImode
);
10928 if (GET_CODE (align_rtx
) == CONST_INT
)
10929 align
= INTVAL (align_rtx
);
10931 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
10933 /* Is there a known alignment and is it less than 4? */
10936 rtx scratch1
= gen_reg_rtx (Pmode
);
10937 emit_move_insn (scratch1
, out
);
10938 /* Is there a known alignment and is it not 2? */
10941 align_3_label
= gen_label_rtx (); /* Label when aligned to 3-byte */
10942 align_2_label
= gen_label_rtx (); /* Label when aligned to 2-byte */
10944 /* Leave just the 3 lower bits. */
10945 align_rtx
= expand_binop (Pmode
, and_optab
, scratch1
, GEN_INT (3),
10946 NULL_RTX
, 0, OPTAB_WIDEN
);
10948 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
10949 Pmode
, 1, align_4_label
);
10950 emit_cmp_and_jump_insns (align_rtx
, const2_rtx
, EQ
, NULL
,
10951 Pmode
, 1, align_2_label
);
10952 emit_cmp_and_jump_insns (align_rtx
, const2_rtx
, GTU
, NULL
,
10953 Pmode
, 1, align_3_label
);
10957 /* Since the alignment is 2, we have to check 2 or 0 bytes;
10958 check if is aligned to 4 - byte. */
10960 align_rtx
= expand_binop (Pmode
, and_optab
, scratch1
, const2_rtx
,
10961 NULL_RTX
, 0, OPTAB_WIDEN
);
10963 emit_cmp_and_jump_insns (align_rtx
, const0_rtx
, EQ
, NULL
,
10964 Pmode
, 1, align_4_label
);
10967 mem
= change_address (src
, QImode
, out
);
10969 /* Now compare the bytes. */
10971 /* Compare the first n unaligned byte on a byte per byte basis. */
10972 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
,
10973 QImode
, 1, end_0_label
);
10975 /* Increment the address. */
10977 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
10979 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
10981 /* Not needed with an alignment of 2 */
10984 emit_label (align_2_label
);
10986 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
, QImode
, 1,
10990 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
10992 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
10994 emit_label (align_3_label
);
10997 emit_cmp_and_jump_insns (mem
, const0_rtx
, EQ
, NULL
, QImode
, 1,
11001 emit_insn (gen_adddi3 (out
, out
, const1_rtx
));
11003 emit_insn (gen_addsi3 (out
, out
, const1_rtx
));
11006 /* Generate loop to check 4 bytes at a time. It is not a good idea to
11007 align this loop. It gives only huge programs, but does not help to
11009 emit_label (align_4_label
);
11011 mem
= change_address (src
, SImode
, out
);
11012 emit_move_insn (scratch
, mem
);
11014 emit_insn (gen_adddi3 (out
, out
, GEN_INT (4)));
11016 emit_insn (gen_addsi3 (out
, out
, GEN_INT (4)));
11018 /* This formula yields a nonzero result iff one of the bytes is zero.
11019 This saves three branches inside loop and many cycles. */
11021 emit_insn (gen_addsi3 (tmpreg
, scratch
, GEN_INT (-0x01010101)));
11022 emit_insn (gen_one_cmplsi2 (scratch
, scratch
));
11023 emit_insn (gen_andsi3 (tmpreg
, tmpreg
, scratch
));
11024 emit_insn (gen_andsi3 (tmpreg
, tmpreg
,
11025 gen_int_mode (0x80808080, SImode
)));
11026 emit_cmp_and_jump_insns (tmpreg
, const0_rtx
, EQ
, 0, SImode
, 1,
11031 rtx reg
= gen_reg_rtx (SImode
);
11032 rtx reg2
= gen_reg_rtx (Pmode
);
11033 emit_move_insn (reg
, tmpreg
);
11034 emit_insn (gen_lshrsi3 (reg
, reg
, GEN_INT (16)));
11036 /* If zero is not in the first two bytes, move two bytes forward. */
11037 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
11038 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
11039 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
11040 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
,
11041 gen_rtx_IF_THEN_ELSE (SImode
, tmp
,
11044 /* Emit lea manually to avoid clobbering of flags. */
11045 emit_insn (gen_rtx_SET (SImode
, reg2
,
11046 gen_rtx_PLUS (Pmode
, out
, const2_rtx
)));
11048 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
11049 tmp
= gen_rtx_EQ (VOIDmode
, tmp
, const0_rtx
);
11050 emit_insn (gen_rtx_SET (VOIDmode
, out
,
11051 gen_rtx_IF_THEN_ELSE (Pmode
, tmp
,
11058 rtx end_2_label
= gen_label_rtx ();
11059 /* Is zero in the first two bytes? */
11061 emit_insn (gen_testsi_ccno_1 (tmpreg
, GEN_INT (0x8080)));
11062 tmp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
11063 tmp
= gen_rtx_NE (VOIDmode
, tmp
, const0_rtx
);
11064 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
11065 gen_rtx_LABEL_REF (VOIDmode
, end_2_label
),
11067 tmp
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
11068 JUMP_LABEL (tmp
) = end_2_label
;
11070 /* Not in the first two. Move two bytes forward. */
11071 emit_insn (gen_lshrsi3 (tmpreg
, tmpreg
, GEN_INT (16)));
11073 emit_insn (gen_adddi3 (out
, out
, const2_rtx
));
11075 emit_insn (gen_addsi3 (out
, out
, const2_rtx
));
11077 emit_label (end_2_label
);
11081 /* Avoid branch in fixing the byte. */
11082 tmpreg
= gen_lowpart (QImode
, tmpreg
);
11083 emit_insn (gen_addqi3_cc (tmpreg
, tmpreg
, tmpreg
));
11084 cmp
= gen_rtx_LTU (Pmode
, gen_rtx_REG (CCmode
, 17), const0_rtx
);
11086 emit_insn (gen_subdi3_carry_rex64 (out
, out
, GEN_INT (3), cmp
));
11088 emit_insn (gen_subsi3_carry (out
, out
, GEN_INT (3), cmp
));
11090 emit_label (end_0_label
);
11094 ix86_expand_call (rtx retval
, rtx fnaddr
, rtx callarg1
,
11095 rtx callarg2 ATTRIBUTE_UNUSED
,
11096 rtx pop
, int sibcall
)
11098 rtx use
= NULL
, call
;
11100 if (pop
== const0_rtx
)
11102 if (TARGET_64BIT
&& pop
)
11106 if (flag_pic
&& GET_CODE (XEXP (fnaddr
, 0)) == SYMBOL_REF
)
11107 fnaddr
= machopic_indirect_call_target (fnaddr
);
11109 /* Static functions and indirect calls don't need the pic register. */
11110 if (! TARGET_64BIT
&& flag_pic
11111 && GET_CODE (XEXP (fnaddr
, 0)) == SYMBOL_REF
11112 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr
, 0)))
11113 use_reg (&use
, pic_offset_table_rtx
);
11115 if (TARGET_64BIT
&& INTVAL (callarg2
) >= 0)
11117 rtx al
= gen_rtx_REG (QImode
, 0);
11118 emit_move_insn (al
, callarg2
);
11119 use_reg (&use
, al
);
11121 #endif /* TARGET_MACHO */
11123 if (! call_insn_operand (XEXP (fnaddr
, 0), Pmode
))
11125 fnaddr
= copy_to_mode_reg (Pmode
, XEXP (fnaddr
, 0));
11126 fnaddr
= gen_rtx_MEM (QImode
, fnaddr
);
11128 if (sibcall
&& TARGET_64BIT
11129 && !constant_call_address_operand (XEXP (fnaddr
, 0), Pmode
))
11132 addr
= copy_to_mode_reg (Pmode
, XEXP (fnaddr
, 0));
11133 fnaddr
= gen_rtx_REG (Pmode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
11134 emit_move_insn (fnaddr
, addr
);
11135 fnaddr
= gen_rtx_MEM (QImode
, fnaddr
);
11138 call
= gen_rtx_CALL (VOIDmode
, fnaddr
, callarg1
);
11140 call
= gen_rtx_SET (VOIDmode
, retval
, call
);
11143 pop
= gen_rtx_PLUS (Pmode
, stack_pointer_rtx
, pop
);
11144 pop
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, pop
);
11145 call
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, call
, pop
));
11148 call
= emit_call_insn (call
);
11150 CALL_INSN_FUNCTION_USAGE (call
) = use
;
11154 /* Clear stack slot assignments remembered from previous functions.
11155 This is called from INIT_EXPANDERS once before RTL is emitted for each
11158 static struct machine_function
*
11159 ix86_init_machine_status (void)
11161 struct machine_function
*f
;
11163 f
= ggc_alloc_cleared (sizeof (struct machine_function
));
11164 f
->use_fast_prologue_epilogue_nregs
= -1;
11169 /* Return a MEM corresponding to a stack slot with mode MODE.
11170 Allocate a new slot if necessary.
11172 The RTL for a function can have several slots available: N is
11173 which slot to use. */
11176 assign_386_stack_local (enum machine_mode mode
, int n
)
11178 struct stack_local_entry
*s
;
11180 if (n
< 0 || n
>= MAX_386_STACK_LOCALS
)
11183 for (s
= ix86_stack_locals
; s
; s
= s
->next
)
11184 if (s
->mode
== mode
&& s
->n
== n
)
11187 s
= (struct stack_local_entry
*)
11188 ggc_alloc (sizeof (struct stack_local_entry
));
11191 s
->rtl
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
11193 s
->next
= ix86_stack_locals
;
11194 ix86_stack_locals
= s
;
11198 /* Construct the SYMBOL_REF for the tls_get_addr function. */
11200 static GTY(()) rtx ix86_tls_symbol
;
11202 ix86_tls_get_addr (void)
11205 if (!ix86_tls_symbol
)
11207 ix86_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
,
11208 (TARGET_GNU_TLS
&& !TARGET_64BIT
)
11209 ? "___tls_get_addr"
11210 : "__tls_get_addr");
11213 return ix86_tls_symbol
;
11216 /* Calculate the length of the memory address in the instruction
11217 encoding. Does not include the one-byte modrm, opcode, or prefix. */
11220 memory_address_length (rtx addr
)
11222 struct ix86_address parts
;
11223 rtx base
, index
, disp
;
11226 if (GET_CODE (addr
) == PRE_DEC
11227 || GET_CODE (addr
) == POST_INC
11228 || GET_CODE (addr
) == PRE_MODIFY
11229 || GET_CODE (addr
) == POST_MODIFY
)
11232 if (! ix86_decompose_address (addr
, &parts
))
11236 index
= parts
.index
;
11241 - esp as the base always wants an index,
11242 - ebp as the base always wants a displacement. */
11244 /* Register Indirect. */
11245 if (base
&& !index
&& !disp
)
11247 /* esp (for its index) and ebp (for its displacement) need
11248 the two-byte modrm form. */
11249 if (addr
== stack_pointer_rtx
11250 || addr
== arg_pointer_rtx
11251 || addr
== frame_pointer_rtx
11252 || addr
== hard_frame_pointer_rtx
)
11256 /* Direct Addressing. */
11257 else if (disp
&& !base
&& !index
)
11262 /* Find the length of the displacement constant. */
11265 if (GET_CODE (disp
) == CONST_INT
11266 && CONST_OK_FOR_LETTER_P (INTVAL (disp
), 'K')
11272 /* ebp always wants a displacement. */
11273 else if (base
== hard_frame_pointer_rtx
)
11276 /* An index requires the two-byte modrm form.... */
11278 /* ...like esp, which always wants an index. */
11279 || base
== stack_pointer_rtx
11280 || base
== arg_pointer_rtx
11281 || base
== frame_pointer_rtx
)
11288 /* Compute default value for "length_immediate" attribute. When SHORTFORM
11289 is set, expect that insn have 8bit immediate alternative. */
11291 ix86_attr_length_immediate_default (rtx insn
, int shortform
)
11295 extract_insn_cached (insn
);
11296 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
11297 if (CONSTANT_P (recog_data
.operand
[i
]))
11302 && GET_CODE (recog_data
.operand
[i
]) == CONST_INT
11303 && CONST_OK_FOR_LETTER_P (INTVAL (recog_data
.operand
[i
]), 'K'))
11307 switch (get_attr_mode (insn
))
11318 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
11323 fatal_insn ("unknown insn mode", insn
);
11329 /* Compute default value for "length_address" attribute. */
11331 ix86_attr_length_address_default (rtx insn
)
11335 if (get_attr_type (insn
) == TYPE_LEA
)
11337 rtx set
= PATTERN (insn
);
11338 if (GET_CODE (set
) == SET
)
11340 else if (GET_CODE (set
) == PARALLEL
11341 && GET_CODE (XVECEXP (set
, 0, 0)) == SET
)
11342 set
= XVECEXP (set
, 0, 0);
11345 #ifdef ENABLE_CHECKING
11351 return memory_address_length (SET_SRC (set
));
11354 extract_insn_cached (insn
);
11355 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
11356 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
11358 return memory_address_length (XEXP (recog_data
.operand
[i
], 0));
11364 /* Return the maximum number of instructions a cpu can issue. */
11367 ix86_issue_rate (void)
11371 case PROCESSOR_PENTIUM
:
11375 case PROCESSOR_PENTIUMPRO
:
11376 case PROCESSOR_PENTIUM4
:
11377 case PROCESSOR_ATHLON
:
11379 case PROCESSOR_NOCONA
:
11387 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
11388 by DEP_INSN and nothing set by DEP_INSN. */
11391 ix86_flags_dependant (rtx insn
, rtx dep_insn
, enum attr_type insn_type
)
11395 /* Simplify the test for uninteresting insns. */
11396 if (insn_type
!= TYPE_SETCC
11397 && insn_type
!= TYPE_ICMOV
11398 && insn_type
!= TYPE_FCMOV
11399 && insn_type
!= TYPE_IBR
)
11402 if ((set
= single_set (dep_insn
)) != 0)
11404 set
= SET_DEST (set
);
11407 else if (GET_CODE (PATTERN (dep_insn
)) == PARALLEL
11408 && XVECLEN (PATTERN (dep_insn
), 0) == 2
11409 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 0)) == SET
11410 && GET_CODE (XVECEXP (PATTERN (dep_insn
), 0, 1)) == SET
)
11412 set
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
11413 set2
= SET_DEST (XVECEXP (PATTERN (dep_insn
), 0, 0));
11418 if (GET_CODE (set
) != REG
|| REGNO (set
) != FLAGS_REG
)
11421 /* This test is true if the dependent insn reads the flags but
11422 not any other potentially set register. */
11423 if (!reg_overlap_mentioned_p (set
, PATTERN (insn
)))
11426 if (set2
&& reg_overlap_mentioned_p (set2
, PATTERN (insn
)))
11432 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
11433 address with operands set by DEP_INSN. */
11436 ix86_agi_dependant (rtx insn
, rtx dep_insn
, enum attr_type insn_type
)
11440 if (insn_type
== TYPE_LEA
11443 addr
= PATTERN (insn
);
11444 if (GET_CODE (addr
) == SET
)
11446 else if (GET_CODE (addr
) == PARALLEL
11447 && GET_CODE (XVECEXP (addr
, 0, 0)) == SET
)
11448 addr
= XVECEXP (addr
, 0, 0);
11451 addr
= SET_SRC (addr
);
11456 extract_insn_cached (insn
);
11457 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
11458 if (GET_CODE (recog_data
.operand
[i
]) == MEM
)
11460 addr
= XEXP (recog_data
.operand
[i
], 0);
11467 return modified_in_p (addr
, dep_insn
);
11471 ix86_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
11473 enum attr_type insn_type
, dep_insn_type
;
11474 enum attr_memory memory
;
11476 int dep_insn_code_number
;
11478 /* Anti and output dependencies have zero cost on all CPUs. */
11479 if (REG_NOTE_KIND (link
) != 0)
11482 dep_insn_code_number
= recog_memoized (dep_insn
);
11484 /* If we can't recognize the insns, we can't really do anything. */
11485 if (dep_insn_code_number
< 0 || recog_memoized (insn
) < 0)
11488 insn_type
= get_attr_type (insn
);
11489 dep_insn_type
= get_attr_type (dep_insn
);
11493 case PROCESSOR_PENTIUM
:
11494 /* Address Generation Interlock adds a cycle of latency. */
11495 if (ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11498 /* ??? Compares pair with jump/setcc. */
11499 if (ix86_flags_dependant (insn
, dep_insn
, insn_type
))
11502 /* Floating point stores require value to be ready one cycle earlier. */
11503 if (insn_type
== TYPE_FMOV
11504 && get_attr_memory (insn
) == MEMORY_STORE
11505 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11509 case PROCESSOR_PENTIUMPRO
:
11510 memory
= get_attr_memory (insn
);
11512 /* INT->FP conversion is expensive. */
11513 if (get_attr_fp_int_src (dep_insn
))
11516 /* There is one cycle extra latency between an FP op and a store. */
11517 if (insn_type
== TYPE_FMOV
11518 && (set
= single_set (dep_insn
)) != NULL_RTX
11519 && (set2
= single_set (insn
)) != NULL_RTX
11520 && rtx_equal_p (SET_DEST (set
), SET_SRC (set2
))
11521 && GET_CODE (SET_DEST (set2
)) == MEM
)
11524 /* Show ability of reorder buffer to hide latency of load by executing
11525 in parallel with previous instruction in case
11526 previous instruction is not needed to compute the address. */
11527 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
11528 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11530 /* Claim moves to take one cycle, as core can issue one load
11531 at time and the next load can start cycle later. */
11532 if (dep_insn_type
== TYPE_IMOV
11533 || dep_insn_type
== TYPE_FMOV
)
11541 memory
= get_attr_memory (insn
);
11543 /* The esp dependency is resolved before the instruction is really
11545 if ((insn_type
== TYPE_PUSH
|| insn_type
== TYPE_POP
)
11546 && (dep_insn_type
== TYPE_PUSH
|| dep_insn_type
== TYPE_POP
))
11549 /* INT->FP conversion is expensive. */
11550 if (get_attr_fp_int_src (dep_insn
))
11553 /* Show ability of reorder buffer to hide latency of load by executing
11554 in parallel with previous instruction in case
11555 previous instruction is not needed to compute the address. */
11556 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
11557 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11559 /* Claim moves to take one cycle, as core can issue one load
11560 at time and the next load can start cycle later. */
11561 if (dep_insn_type
== TYPE_IMOV
11562 || dep_insn_type
== TYPE_FMOV
)
11571 case PROCESSOR_ATHLON
:
11573 memory
= get_attr_memory (insn
);
11575 /* Show ability of reorder buffer to hide latency of load by executing
11576 in parallel with previous instruction in case
11577 previous instruction is not needed to compute the address. */
11578 if ((memory
== MEMORY_LOAD
|| memory
== MEMORY_BOTH
)
11579 && !ix86_agi_dependant (insn
, dep_insn
, insn_type
))
11581 enum attr_unit unit
= get_attr_unit (insn
);
11584 /* Because of the difference between the length of integer and
11585 floating unit pipeline preparation stages, the memory operands
11586 for floating point are cheaper.
11588 ??? For Athlon it the difference is most probably 2. */
11589 if (unit
== UNIT_INTEGER
|| unit
== UNIT_UNKNOWN
)
11592 loadcost
= TARGET_ATHLON
? 2 : 0;
11594 if (cost
>= loadcost
)
11607 /* How many alternative schedules to try. This should be as wide as the
11608 scheduling freedom in the DFA, but no wider. Making this value too
11609 large results extra work for the scheduler. */
11612 ia32_multipass_dfa_lookahead (void)
11614 if (ix86_tune
== PROCESSOR_PENTIUM
)
11617 if (ix86_tune
== PROCESSOR_PENTIUMPRO
11618 || ix86_tune
== PROCESSOR_K6
)
11626 /* Implement the target hook targetm.vectorize.misaligned_mem_ok. */
11629 ix86_misaligned_mem_ok (enum machine_mode mode
)
11631 if (TARGET_MMX
&& VALID_MMX_REG_MODE (mode
))
11637 /* Compute the alignment given to a constant that is being placed in memory.
11638 EXP is the constant and ALIGN is the alignment that the object would
11640 The value of this function is used instead of that alignment to align
11644 ix86_constant_alignment (tree exp
, int align
)
11646 if (TREE_CODE (exp
) == REAL_CST
)
11648 if (TYPE_MODE (TREE_TYPE (exp
)) == DFmode
&& align
< 64)
11650 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp
))) && align
< 128)
11653 else if (!optimize_size
&& TREE_CODE (exp
) == STRING_CST
11654 && TREE_STRING_LENGTH (exp
) >= 31 && align
< BITS_PER_WORD
)
11655 return BITS_PER_WORD
;
11660 /* Compute the alignment for a static variable.
11661 TYPE is the data type, and ALIGN is the alignment that
11662 the object would ordinarily have. The value of this function is used
11663 instead of that alignment to align the object. */
11666 ix86_data_alignment (tree type
, int align
)
11668 if (AGGREGATE_TYPE_P (type
)
11669 && TYPE_SIZE (type
)
11670 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
11671 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 256
11672 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 256)
11675 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
11676 to 16byte boundary. */
11679 if (AGGREGATE_TYPE_P (type
)
11680 && TYPE_SIZE (type
)
11681 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
11682 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 128
11683 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 128)
11687 if (TREE_CODE (type
) == ARRAY_TYPE
)
11689 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
11691 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
11694 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
11697 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
11699 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
11702 else if ((TREE_CODE (type
) == RECORD_TYPE
11703 || TREE_CODE (type
) == UNION_TYPE
11704 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
11705 && TYPE_FIELDS (type
))
11707 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
11709 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
11712 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
11713 || TREE_CODE (type
) == INTEGER_TYPE
)
11715 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
11717 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
11724 /* Compute the alignment for a local variable.
11725 TYPE is the data type, and ALIGN is the alignment that
11726 the object would ordinarily have. The value of this macro is used
11727 instead of that alignment to align the object. */
11730 ix86_local_alignment (tree type
, int align
)
11732 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
11733 to 16byte boundary. */
11736 if (AGGREGATE_TYPE_P (type
)
11737 && TYPE_SIZE (type
)
11738 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
11739 && (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 16
11740 || TREE_INT_CST_HIGH (TYPE_SIZE (type
))) && align
< 128)
11743 if (TREE_CODE (type
) == ARRAY_TYPE
)
11745 if (TYPE_MODE (TREE_TYPE (type
)) == DFmode
&& align
< 64)
11747 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type
))) && align
< 128)
11750 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
11752 if (TYPE_MODE (type
) == DCmode
&& align
< 64)
11754 if (TYPE_MODE (type
) == XCmode
&& align
< 128)
11757 else if ((TREE_CODE (type
) == RECORD_TYPE
11758 || TREE_CODE (type
) == UNION_TYPE
11759 || TREE_CODE (type
) == QUAL_UNION_TYPE
)
11760 && TYPE_FIELDS (type
))
11762 if (DECL_MODE (TYPE_FIELDS (type
)) == DFmode
&& align
< 64)
11764 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type
))) && align
< 128)
11767 else if (TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == VECTOR_TYPE
11768 || TREE_CODE (type
) == INTEGER_TYPE
)
11771 if (TYPE_MODE (type
) == DFmode
&& align
< 64)
11773 if (ALIGN_MODE_128 (TYPE_MODE (type
)) && align
< 128)
11779 /* Emit RTL insns to initialize the variable parts of a trampoline.
11780 FNADDR is an RTX for the address of the function's pure code.
11781 CXT is an RTX for the static chain value for the function. */
11783 x86_initialize_trampoline (rtx tramp
, rtx fnaddr
, rtx cxt
)
11787 /* Compute offset from the end of the jmp to the target function. */
11788 rtx disp
= expand_binop (SImode
, sub_optab
, fnaddr
,
11789 plus_constant (tramp
, 10),
11790 NULL_RTX
, 1, OPTAB_DIRECT
);
11791 emit_move_insn (gen_rtx_MEM (QImode
, tramp
),
11792 gen_int_mode (0xb9, QImode
));
11793 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 1)), cxt
);
11794 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, 5)),
11795 gen_int_mode (0xe9, QImode
));
11796 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 6)), disp
);
11801 /* Try to load address using shorter movl instead of movabs.
11802 We may want to support movq for kernel mode, but kernel does not use
11803 trampolines at the moment. */
11804 if (x86_64_zext_immediate_operand (fnaddr
, VOIDmode
))
11806 fnaddr
= copy_to_mode_reg (DImode
, fnaddr
);
11807 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11808 gen_int_mode (0xbb41, HImode
));
11809 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, offset
+ 2)),
11810 gen_lowpart (SImode
, fnaddr
));
11815 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11816 gen_int_mode (0xbb49, HImode
));
11817 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, offset
+ 2)),
11821 /* Load static chain using movabs to r10. */
11822 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11823 gen_int_mode (0xba49, HImode
));
11824 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, offset
+ 2)),
11827 /* Jump to the r11 */
11828 emit_move_insn (gen_rtx_MEM (HImode
, plus_constant (tramp
, offset
)),
11829 gen_int_mode (0xff49, HImode
));
11830 emit_move_insn (gen_rtx_MEM (QImode
, plus_constant (tramp
, offset
+2)),
11831 gen_int_mode (0xe3, QImode
));
11833 if (offset
> TRAMPOLINE_SIZE
)
11837 #ifdef ENABLE_EXECUTE_STACK
11838 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
11839 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
11843 #define def_builtin(MASK, NAME, TYPE, CODE) \
11845 if ((MASK) & target_flags \
11846 && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \
11847 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
11848 NULL, NULL_TREE); \
11851 struct builtin_description
11853 const unsigned int mask
;
11854 const enum insn_code icode
;
11855 const char *const name
;
11856 const enum ix86_builtins code
;
11857 const enum rtx_code comparison
;
11858 const unsigned int flag
;
11861 static const struct builtin_description bdesc_comi
[] =
11863 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS
, UNEQ
, 0 },
11864 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS
, UNLT
, 0 },
11865 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS
, UNLE
, 0 },
11866 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS
, GT
, 0 },
11867 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS
, GE
, 0 },
11868 { MASK_SSE
, CODE_FOR_sse_comi
, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS
, LTGT
, 0 },
11869 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS
, UNEQ
, 0 },
11870 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS
, UNLT
, 0 },
11871 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS
, UNLE
, 0 },
11872 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS
, GT
, 0 },
11873 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS
, GE
, 0 },
11874 { MASK_SSE
, CODE_FOR_sse_ucomi
, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS
, LTGT
, 0 },
11875 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD
, UNEQ
, 0 },
11876 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD
, UNLT
, 0 },
11877 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD
, UNLE
, 0 },
11878 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD
, GT
, 0 },
11879 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD
, GE
, 0 },
11880 { MASK_SSE2
, CODE_FOR_sse2_comi
, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD
, LTGT
, 0 },
11881 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD
, UNEQ
, 0 },
11882 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD
, UNLT
, 0 },
11883 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD
, UNLE
, 0 },
11884 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD
, GT
, 0 },
11885 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD
, GE
, 0 },
11886 { MASK_SSE2
, CODE_FOR_sse2_ucomi
, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD
, LTGT
, 0 },
11889 static const struct builtin_description bdesc_2arg
[] =
11892 { MASK_SSE
, CODE_FOR_addv4sf3
, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS
, 0, 0 },
11893 { MASK_SSE
, CODE_FOR_subv4sf3
, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS
, 0, 0 },
11894 { MASK_SSE
, CODE_FOR_mulv4sf3
, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS
, 0, 0 },
11895 { MASK_SSE
, CODE_FOR_divv4sf3
, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS
, 0, 0 },
11896 { MASK_SSE
, CODE_FOR_vmaddv4sf3
, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS
, 0, 0 },
11897 { MASK_SSE
, CODE_FOR_vmsubv4sf3
, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS
, 0, 0 },
11898 { MASK_SSE
, CODE_FOR_vmmulv4sf3
, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS
, 0, 0 },
11899 { MASK_SSE
, CODE_FOR_vmdivv4sf3
, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS
, 0, 0 },
11901 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS
, EQ
, 0 },
11902 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS
, LT
, 0 },
11903 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS
, LE
, 0 },
11904 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS
, LT
, 1 },
11905 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS
, LE
, 1 },
11906 { MASK_SSE
, CODE_FOR_maskcmpv4sf3
, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS
, UNORDERED
, 0 },
11907 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS
, EQ
, 0 },
11908 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS
, LT
, 0 },
11909 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS
, LE
, 0 },
11910 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS
, LT
, 1 },
11911 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS
, LE
, 1 },
11912 { MASK_SSE
, CODE_FOR_maskncmpv4sf3
, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS
, UNORDERED
, 0 },
11913 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS
, EQ
, 0 },
11914 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS
, LT
, 0 },
11915 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS
, LE
, 0 },
11916 { MASK_SSE
, CODE_FOR_vmmaskcmpv4sf3
, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS
, UNORDERED
, 0 },
11917 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS
, EQ
, 0 },
11918 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS
, LT
, 0 },
11919 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS
, LE
, 0 },
11920 { MASK_SSE
, CODE_FOR_vmmaskncmpv4sf3
, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS
, UNORDERED
, 0 },
11922 { MASK_SSE
, CODE_FOR_sminv4sf3
, "__builtin_ia32_minps", IX86_BUILTIN_MINPS
, 0, 0 },
11923 { MASK_SSE
, CODE_FOR_smaxv4sf3
, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS
, 0, 0 },
11924 { MASK_SSE
, CODE_FOR_vmsminv4sf3
, "__builtin_ia32_minss", IX86_BUILTIN_MINSS
, 0, 0 },
11925 { MASK_SSE
, CODE_FOR_vmsmaxv4sf3
, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS
, 0, 0 },
11927 { MASK_SSE
, CODE_FOR_sse_andv4sf3
, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS
, 0, 0 },
11928 { MASK_SSE
, CODE_FOR_sse_nandv4sf3
, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS
, 0, 0 },
11929 { MASK_SSE
, CODE_FOR_sse_iorv4sf3
, "__builtin_ia32_orps", IX86_BUILTIN_ORPS
, 0, 0 },
11930 { MASK_SSE
, CODE_FOR_sse_xorv4sf3
, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS
, 0, 0 },
11932 { MASK_SSE
, CODE_FOR_sse_movss
, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS
, 0, 0 },
11933 { MASK_SSE
, CODE_FOR_sse_movhlps
, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS
, 0, 0 },
11934 { MASK_SSE
, CODE_FOR_sse_movlhps
, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS
, 0, 0 },
11935 { MASK_SSE
, CODE_FOR_sse_unpckhps
, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS
, 0, 0 },
11936 { MASK_SSE
, CODE_FOR_sse_unpcklps
, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS
, 0, 0 },
11939 { MASK_MMX
, CODE_FOR_addv8qi3
, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB
, 0, 0 },
11940 { MASK_MMX
, CODE_FOR_addv4hi3
, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW
, 0, 0 },
11941 { MASK_MMX
, CODE_FOR_addv2si3
, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD
, 0, 0 },
11942 { MASK_MMX
, CODE_FOR_mmx_adddi3
, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ
, 0, 0 },
11943 { MASK_MMX
, CODE_FOR_subv8qi3
, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB
, 0, 0 },
11944 { MASK_MMX
, CODE_FOR_subv4hi3
, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW
, 0, 0 },
11945 { MASK_MMX
, CODE_FOR_subv2si3
, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD
, 0, 0 },
11946 { MASK_MMX
, CODE_FOR_mmx_subdi3
, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ
, 0, 0 },
11948 { MASK_MMX
, CODE_FOR_ssaddv8qi3
, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB
, 0, 0 },
11949 { MASK_MMX
, CODE_FOR_ssaddv4hi3
, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW
, 0, 0 },
11950 { MASK_MMX
, CODE_FOR_sssubv8qi3
, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB
, 0, 0 },
11951 { MASK_MMX
, CODE_FOR_sssubv4hi3
, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW
, 0, 0 },
11952 { MASK_MMX
, CODE_FOR_usaddv8qi3
, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB
, 0, 0 },
11953 { MASK_MMX
, CODE_FOR_usaddv4hi3
, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW
, 0, 0 },
11954 { MASK_MMX
, CODE_FOR_ussubv8qi3
, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB
, 0, 0 },
11955 { MASK_MMX
, CODE_FOR_ussubv4hi3
, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW
, 0, 0 },
11957 { MASK_MMX
, CODE_FOR_mulv4hi3
, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW
, 0, 0 },
11958 { MASK_MMX
, CODE_FOR_smulv4hi3_highpart
, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW
, 0, 0 },
11959 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_umulv4hi3_highpart
, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW
, 0, 0 },
11961 { MASK_MMX
, CODE_FOR_mmx_anddi3
, "__builtin_ia32_pand", IX86_BUILTIN_PAND
, 0, 0 },
11962 { MASK_MMX
, CODE_FOR_mmx_nanddi3
, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN
, 0, 0 },
11963 { MASK_MMX
, CODE_FOR_mmx_iordi3
, "__builtin_ia32_por", IX86_BUILTIN_POR
, 0, 0 },
11964 { MASK_MMX
, CODE_FOR_mmx_xordi3
, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR
, 0, 0 },
11966 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_uavgv8qi3
, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB
, 0, 0 },
11967 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_uavgv4hi3
, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW
, 0, 0 },
11969 { MASK_MMX
, CODE_FOR_eqv8qi3
, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB
, 0, 0 },
11970 { MASK_MMX
, CODE_FOR_eqv4hi3
, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW
, 0, 0 },
11971 { MASK_MMX
, CODE_FOR_eqv2si3
, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD
, 0, 0 },
11972 { MASK_MMX
, CODE_FOR_gtv8qi3
, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB
, 0, 0 },
11973 { MASK_MMX
, CODE_FOR_gtv4hi3
, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW
, 0, 0 },
11974 { MASK_MMX
, CODE_FOR_gtv2si3
, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD
, 0, 0 },
11976 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_umaxv8qi3
, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB
, 0, 0 },
11977 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_smaxv4hi3
, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW
, 0, 0 },
11978 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_uminv8qi3
, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB
, 0, 0 },
11979 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_sminv4hi3
, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW
, 0, 0 },
11981 { MASK_MMX
, CODE_FOR_mmx_punpckhbw
, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW
, 0, 0 },
11982 { MASK_MMX
, CODE_FOR_mmx_punpckhwd
, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD
, 0, 0 },
11983 { MASK_MMX
, CODE_FOR_mmx_punpckhdq
, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ
, 0, 0 },
11984 { MASK_MMX
, CODE_FOR_mmx_punpcklbw
, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW
, 0, 0 },
11985 { MASK_MMX
, CODE_FOR_mmx_punpcklwd
, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD
, 0, 0 },
11986 { MASK_MMX
, CODE_FOR_mmx_punpckldq
, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ
, 0, 0 },
11989 { MASK_MMX
, CODE_FOR_mmx_packsswb
, 0, IX86_BUILTIN_PACKSSWB
, 0, 0 },
11990 { MASK_MMX
, CODE_FOR_mmx_packssdw
, 0, IX86_BUILTIN_PACKSSDW
, 0, 0 },
11991 { MASK_MMX
, CODE_FOR_mmx_packuswb
, 0, IX86_BUILTIN_PACKUSWB
, 0, 0 },
11993 { MASK_SSE
, CODE_FOR_cvtpi2ps
, 0, IX86_BUILTIN_CVTPI2PS
, 0, 0 },
11994 { MASK_SSE
, CODE_FOR_cvtsi2ss
, 0, IX86_BUILTIN_CVTSI2SS
, 0, 0 },
11995 { MASK_SSE
| MASK_64BIT
, CODE_FOR_cvtsi2ssq
, 0, IX86_BUILTIN_CVTSI642SS
, 0, 0 },
11997 { MASK_MMX
, CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLW
, 0, 0 },
11998 { MASK_MMX
, CODE_FOR_ashlv4hi3
, 0, IX86_BUILTIN_PSLLWI
, 0, 0 },
11999 { MASK_MMX
, CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLD
, 0, 0 },
12000 { MASK_MMX
, CODE_FOR_ashlv2si3
, 0, IX86_BUILTIN_PSLLDI
, 0, 0 },
12001 { MASK_MMX
, CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQ
, 0, 0 },
12002 { MASK_MMX
, CODE_FOR_mmx_ashldi3
, 0, IX86_BUILTIN_PSLLQI
, 0, 0 },
12004 { MASK_MMX
, CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLW
, 0, 0 },
12005 { MASK_MMX
, CODE_FOR_lshrv4hi3
, 0, IX86_BUILTIN_PSRLWI
, 0, 0 },
12006 { MASK_MMX
, CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLD
, 0, 0 },
12007 { MASK_MMX
, CODE_FOR_lshrv2si3
, 0, IX86_BUILTIN_PSRLDI
, 0, 0 },
12008 { MASK_MMX
, CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQ
, 0, 0 },
12009 { MASK_MMX
, CODE_FOR_mmx_lshrdi3
, 0, IX86_BUILTIN_PSRLQI
, 0, 0 },
12011 { MASK_MMX
, CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAW
, 0, 0 },
12012 { MASK_MMX
, CODE_FOR_ashrv4hi3
, 0, IX86_BUILTIN_PSRAWI
, 0, 0 },
12013 { MASK_MMX
, CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRAD
, 0, 0 },
12014 { MASK_MMX
, CODE_FOR_ashrv2si3
, 0, IX86_BUILTIN_PSRADI
, 0, 0 },
12016 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_psadbw
, 0, IX86_BUILTIN_PSADBW
, 0, 0 },
12017 { MASK_MMX
, CODE_FOR_mmx_pmaddwd
, 0, IX86_BUILTIN_PMADDWD
, 0, 0 },
12020 { MASK_SSE2
, CODE_FOR_addv2df3
, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD
, 0, 0 },
12021 { MASK_SSE2
, CODE_FOR_subv2df3
, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD
, 0, 0 },
12022 { MASK_SSE2
, CODE_FOR_mulv2df3
, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD
, 0, 0 },
12023 { MASK_SSE2
, CODE_FOR_divv2df3
, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD
, 0, 0 },
12024 { MASK_SSE2
, CODE_FOR_vmaddv2df3
, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD
, 0, 0 },
12025 { MASK_SSE2
, CODE_FOR_vmsubv2df3
, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD
, 0, 0 },
12026 { MASK_SSE2
, CODE_FOR_vmmulv2df3
, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD
, 0, 0 },
12027 { MASK_SSE2
, CODE_FOR_vmdivv2df3
, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD
, 0, 0 },
12029 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD
, EQ
, 0 },
12030 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD
, LT
, 0 },
12031 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD
, LE
, 0 },
12032 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD
, LT
, 1 },
12033 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD
, LE
, 1 },
12034 { MASK_SSE2
, CODE_FOR_maskcmpv2df3
, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD
, UNORDERED
, 0 },
12035 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD
, EQ
, 0 },
12036 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD
, LT
, 0 },
12037 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD
, LE
, 0 },
12038 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD
, LT
, 1 },
12039 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD
, LE
, 1 },
12040 { MASK_SSE2
, CODE_FOR_maskncmpv2df3
, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD
, UNORDERED
, 0 },
12041 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD
, EQ
, 0 },
12042 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD
, LT
, 0 },
12043 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD
, LE
, 0 },
12044 { MASK_SSE2
, CODE_FOR_vmmaskcmpv2df3
, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD
, UNORDERED
, 0 },
12045 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD
, EQ
, 0 },
12046 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD
, LT
, 0 },
12047 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD
, LE
, 0 },
12048 { MASK_SSE2
, CODE_FOR_vmmaskncmpv2df3
, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD
, UNORDERED
, 0 },
12050 { MASK_SSE2
, CODE_FOR_sminv2df3
, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD
, 0, 0 },
12051 { MASK_SSE2
, CODE_FOR_smaxv2df3
, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD
, 0, 0 },
12052 { MASK_SSE2
, CODE_FOR_vmsminv2df3
, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD
, 0, 0 },
12053 { MASK_SSE2
, CODE_FOR_vmsmaxv2df3
, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD
, 0, 0 },
12055 { MASK_SSE2
, CODE_FOR_sse2_andv2df3
, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD
, 0, 0 },
12056 { MASK_SSE2
, CODE_FOR_sse2_nandv2df3
, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD
, 0, 0 },
12057 { MASK_SSE2
, CODE_FOR_sse2_iorv2df3
, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD
, 0, 0 },
12058 { MASK_SSE2
, CODE_FOR_sse2_xorv2df3
, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD
, 0, 0 },
12060 { MASK_SSE2
, CODE_FOR_sse2_movsd
, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD
, 0, 0 },
12061 { MASK_SSE2
, CODE_FOR_sse2_unpckhpd
, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD
, 0, 0 },
12062 { MASK_SSE2
, CODE_FOR_sse2_unpcklpd
, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD
, 0, 0 },
12065 { MASK_SSE2
, CODE_FOR_addv16qi3
, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128
, 0, 0 },
12066 { MASK_SSE2
, CODE_FOR_addv8hi3
, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128
, 0, 0 },
12067 { MASK_SSE2
, CODE_FOR_addv4si3
, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128
, 0, 0 },
12068 { MASK_SSE2
, CODE_FOR_addv2di3
, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128
, 0, 0 },
12069 { MASK_SSE2
, CODE_FOR_subv16qi3
, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128
, 0, 0 },
12070 { MASK_SSE2
, CODE_FOR_subv8hi3
, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128
, 0, 0 },
12071 { MASK_SSE2
, CODE_FOR_subv4si3
, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128
, 0, 0 },
12072 { MASK_SSE2
, CODE_FOR_subv2di3
, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128
, 0, 0 },
12074 { MASK_MMX
, CODE_FOR_ssaddv16qi3
, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128
, 0, 0 },
12075 { MASK_MMX
, CODE_FOR_ssaddv8hi3
, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128
, 0, 0 },
12076 { MASK_MMX
, CODE_FOR_sssubv16qi3
, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128
, 0, 0 },
12077 { MASK_MMX
, CODE_FOR_sssubv8hi3
, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128
, 0, 0 },
12078 { MASK_MMX
, CODE_FOR_usaddv16qi3
, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128
, 0, 0 },
12079 { MASK_MMX
, CODE_FOR_usaddv8hi3
, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128
, 0, 0 },
12080 { MASK_MMX
, CODE_FOR_ussubv16qi3
, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128
, 0, 0 },
12081 { MASK_MMX
, CODE_FOR_ussubv8hi3
, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128
, 0, 0 },
12083 { MASK_SSE2
, CODE_FOR_mulv8hi3
, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128
, 0, 0 },
12084 { MASK_SSE2
, CODE_FOR_smulv8hi3_highpart
, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128
, 0, 0 },
12086 { MASK_SSE2
, CODE_FOR_sse2_andv2di3
, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128
, 0, 0 },
12087 { MASK_SSE2
, CODE_FOR_sse2_nandv2di3
, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128
, 0, 0 },
12088 { MASK_SSE2
, CODE_FOR_sse2_iorv2di3
, "__builtin_ia32_por128", IX86_BUILTIN_POR128
, 0, 0 },
12089 { MASK_SSE2
, CODE_FOR_sse2_xorv2di3
, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128
, 0, 0 },
12091 { MASK_SSE2
, CODE_FOR_sse2_uavgv16qi3
, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128
, 0, 0 },
12092 { MASK_SSE2
, CODE_FOR_sse2_uavgv8hi3
, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128
, 0, 0 },
12094 { MASK_SSE2
, CODE_FOR_eqv16qi3
, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128
, 0, 0 },
12095 { MASK_SSE2
, CODE_FOR_eqv8hi3
, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128
, 0, 0 },
12096 { MASK_SSE2
, CODE_FOR_eqv4si3
, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128
, 0, 0 },
12097 { MASK_SSE2
, CODE_FOR_gtv16qi3
, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128
, 0, 0 },
12098 { MASK_SSE2
, CODE_FOR_gtv8hi3
, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128
, 0, 0 },
12099 { MASK_SSE2
, CODE_FOR_gtv4si3
, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128
, 0, 0 },
12101 { MASK_SSE2
, CODE_FOR_umaxv16qi3
, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128
, 0, 0 },
12102 { MASK_SSE2
, CODE_FOR_smaxv8hi3
, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128
, 0, 0 },
12103 { MASK_SSE2
, CODE_FOR_uminv16qi3
, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128
, 0, 0 },
12104 { MASK_SSE2
, CODE_FOR_sminv8hi3
, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128
, 0, 0 },
12106 { MASK_SSE2
, CODE_FOR_sse2_punpckhbw
, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128
, 0, 0 },
12107 { MASK_SSE2
, CODE_FOR_sse2_punpckhwd
, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128
, 0, 0 },
12108 { MASK_SSE2
, CODE_FOR_sse2_punpckhdq
, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128
, 0, 0 },
12109 { MASK_SSE2
, CODE_FOR_sse2_punpckhqdq
, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128
, 0, 0 },
12110 { MASK_SSE2
, CODE_FOR_sse2_punpcklbw
, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128
, 0, 0 },
12111 { MASK_SSE2
, CODE_FOR_sse2_punpcklwd
, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128
, 0, 0 },
12112 { MASK_SSE2
, CODE_FOR_sse2_punpckldq
, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128
, 0, 0 },
12113 { MASK_SSE2
, CODE_FOR_sse2_punpcklqdq
, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128
, 0, 0 },
12115 { MASK_SSE2
, CODE_FOR_sse2_packsswb
, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128
, 0, 0 },
12116 { MASK_SSE2
, CODE_FOR_sse2_packssdw
, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128
, 0, 0 },
12117 { MASK_SSE2
, CODE_FOR_sse2_packuswb
, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128
, 0, 0 },
12119 { MASK_SSE2
, CODE_FOR_umulv8hi3_highpart
, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128
, 0, 0 },
12120 { MASK_SSE2
, CODE_FOR_sse2_psadbw
, 0, IX86_BUILTIN_PSADBW128
, 0, 0 },
12122 { MASK_SSE2
, CODE_FOR_sse2_umulsidi3
, 0, IX86_BUILTIN_PMULUDQ
, 0, 0 },
12123 { MASK_SSE2
, CODE_FOR_sse2_umulv2siv2di3
, 0, IX86_BUILTIN_PMULUDQ128
, 0, 0 },
12125 { MASK_SSE2
, CODE_FOR_ashlv8hi3_ti
, 0, IX86_BUILTIN_PSLLW128
, 0, 0 },
12126 { MASK_SSE2
, CODE_FOR_ashlv8hi3
, 0, IX86_BUILTIN_PSLLWI128
, 0, 0 },
12127 { MASK_SSE2
, CODE_FOR_ashlv4si3_ti
, 0, IX86_BUILTIN_PSLLD128
, 0, 0 },
12128 { MASK_SSE2
, CODE_FOR_ashlv4si3
, 0, IX86_BUILTIN_PSLLDI128
, 0, 0 },
12129 { MASK_SSE2
, CODE_FOR_ashlv2di3_ti
, 0, IX86_BUILTIN_PSLLQ128
, 0, 0 },
12130 { MASK_SSE2
, CODE_FOR_ashlv2di3
, 0, IX86_BUILTIN_PSLLQI128
, 0, 0 },
12132 { MASK_SSE2
, CODE_FOR_lshrv8hi3_ti
, 0, IX86_BUILTIN_PSRLW128
, 0, 0 },
12133 { MASK_SSE2
, CODE_FOR_lshrv8hi3
, 0, IX86_BUILTIN_PSRLWI128
, 0, 0 },
12134 { MASK_SSE2
, CODE_FOR_lshrv4si3_ti
, 0, IX86_BUILTIN_PSRLD128
, 0, 0 },
12135 { MASK_SSE2
, CODE_FOR_lshrv4si3
, 0, IX86_BUILTIN_PSRLDI128
, 0, 0 },
12136 { MASK_SSE2
, CODE_FOR_lshrv2di3_ti
, 0, IX86_BUILTIN_PSRLQ128
, 0, 0 },
12137 { MASK_SSE2
, CODE_FOR_lshrv2di3
, 0, IX86_BUILTIN_PSRLQI128
, 0, 0 },
12139 { MASK_SSE2
, CODE_FOR_ashrv8hi3_ti
, 0, IX86_BUILTIN_PSRAW128
, 0, 0 },
12140 { MASK_SSE2
, CODE_FOR_ashrv8hi3
, 0, IX86_BUILTIN_PSRAWI128
, 0, 0 },
12141 { MASK_SSE2
, CODE_FOR_ashrv4si3_ti
, 0, IX86_BUILTIN_PSRAD128
, 0, 0 },
12142 { MASK_SSE2
, CODE_FOR_ashrv4si3
, 0, IX86_BUILTIN_PSRADI128
, 0, 0 },
12144 { MASK_SSE2
, CODE_FOR_sse2_pmaddwd
, 0, IX86_BUILTIN_PMADDWD128
, 0, 0 },
12146 { MASK_SSE2
, CODE_FOR_cvtsi2sd
, 0, IX86_BUILTIN_CVTSI2SD
, 0, 0 },
12147 { MASK_SSE2
| MASK_64BIT
, CODE_FOR_cvtsi2sdq
, 0, IX86_BUILTIN_CVTSI642SD
, 0, 0 },
12148 { MASK_SSE2
, CODE_FOR_cvtsd2ss
, 0, IX86_BUILTIN_CVTSD2SS
, 0, 0 },
12149 { MASK_SSE2
, CODE_FOR_cvtss2sd
, 0, IX86_BUILTIN_CVTSS2SD
, 0, 0 },
12152 { MASK_SSE3
, CODE_FOR_addsubv4sf3
, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS
, 0, 0 },
12153 { MASK_SSE3
, CODE_FOR_addsubv2df3
, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD
, 0, 0 },
12154 { MASK_SSE3
, CODE_FOR_haddv4sf3
, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS
, 0, 0 },
12155 { MASK_SSE3
, CODE_FOR_haddv2df3
, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD
, 0, 0 },
12156 { MASK_SSE3
, CODE_FOR_hsubv4sf3
, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS
, 0, 0 },
12157 { MASK_SSE3
, CODE_FOR_hsubv2df3
, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD
, 0, 0 }
12160 static const struct builtin_description bdesc_1arg
[] =
12162 { MASK_SSE
| MASK_3DNOW_A
, CODE_FOR_mmx_pmovmskb
, 0, IX86_BUILTIN_PMOVMSKB
, 0, 0 },
12163 { MASK_SSE
, CODE_FOR_sse_movmskps
, 0, IX86_BUILTIN_MOVMSKPS
, 0, 0 },
12165 { MASK_SSE
, CODE_FOR_sqrtv4sf2
, 0, IX86_BUILTIN_SQRTPS
, 0, 0 },
12166 { MASK_SSE
, CODE_FOR_rsqrtv4sf2
, 0, IX86_BUILTIN_RSQRTPS
, 0, 0 },
12167 { MASK_SSE
, CODE_FOR_rcpv4sf2
, 0, IX86_BUILTIN_RCPPS
, 0, 0 },
12169 { MASK_SSE
, CODE_FOR_cvtps2pi
, 0, IX86_BUILTIN_CVTPS2PI
, 0, 0 },
12170 { MASK_SSE
, CODE_FOR_cvtss2si
, 0, IX86_BUILTIN_CVTSS2SI
, 0, 0 },
12171 { MASK_SSE
| MASK_64BIT
, CODE_FOR_cvtss2siq
, 0, IX86_BUILTIN_CVTSS2SI64
, 0, 0 },
12172 { MASK_SSE
, CODE_FOR_cvttps2pi
, 0, IX86_BUILTIN_CVTTPS2PI
, 0, 0 },
12173 { MASK_SSE
, CODE_FOR_cvttss2si
, 0, IX86_BUILTIN_CVTTSS2SI
, 0, 0 },
12174 { MASK_SSE
| MASK_64BIT
, CODE_FOR_cvttss2siq
, 0, IX86_BUILTIN_CVTTSS2SI64
, 0, 0 },
12176 { MASK_SSE2
, CODE_FOR_sse2_pmovmskb
, 0, IX86_BUILTIN_PMOVMSKB128
, 0, 0 },
12177 { MASK_SSE2
, CODE_FOR_sse2_movmskpd
, 0, IX86_BUILTIN_MOVMSKPD
, 0, 0 },
12178 { MASK_SSE2
, CODE_FOR_sse2_movq2dq
, 0, IX86_BUILTIN_MOVQ2DQ
, 0, 0 },
12179 { MASK_SSE2
, CODE_FOR_sse2_movdq2q
, 0, IX86_BUILTIN_MOVDQ2Q
, 0, 0 },
12181 { MASK_SSE2
, CODE_FOR_sqrtv2df2
, 0, IX86_BUILTIN_SQRTPD
, 0, 0 },
12183 { MASK_SSE2
, CODE_FOR_cvtdq2pd
, 0, IX86_BUILTIN_CVTDQ2PD
, 0, 0 },
12184 { MASK_SSE2
, CODE_FOR_cvtdq2ps
, 0, IX86_BUILTIN_CVTDQ2PS
, 0, 0 },
12186 { MASK_SSE2
, CODE_FOR_cvtpd2dq
, 0, IX86_BUILTIN_CVTPD2DQ
, 0, 0 },
12187 { MASK_SSE2
, CODE_FOR_cvtpd2pi
, 0, IX86_BUILTIN_CVTPD2PI
, 0, 0 },
12188 { MASK_SSE2
, CODE_FOR_cvtpd2ps
, 0, IX86_BUILTIN_CVTPD2PS
, 0, 0 },
12189 { MASK_SSE2
, CODE_FOR_cvttpd2dq
, 0, IX86_BUILTIN_CVTTPD2DQ
, 0, 0 },
12190 { MASK_SSE2
, CODE_FOR_cvttpd2pi
, 0, IX86_BUILTIN_CVTTPD2PI
, 0, 0 },
12192 { MASK_SSE2
, CODE_FOR_cvtpi2pd
, 0, IX86_BUILTIN_CVTPI2PD
, 0, 0 },
12194 { MASK_SSE2
, CODE_FOR_cvtsd2si
, 0, IX86_BUILTIN_CVTSD2SI
, 0, 0 },
12195 { MASK_SSE2
, CODE_FOR_cvttsd2si
, 0, IX86_BUILTIN_CVTTSD2SI
, 0, 0 },
12196 { MASK_SSE2
| MASK_64BIT
, CODE_FOR_cvtsd2siq
, 0, IX86_BUILTIN_CVTSD2SI64
, 0, 0 },
12197 { MASK_SSE2
| MASK_64BIT
, CODE_FOR_cvttsd2siq
, 0, IX86_BUILTIN_CVTTSD2SI64
, 0, 0 },
12199 { MASK_SSE2
, CODE_FOR_cvtps2dq
, 0, IX86_BUILTIN_CVTPS2DQ
, 0, 0 },
12200 { MASK_SSE2
, CODE_FOR_cvtps2pd
, 0, IX86_BUILTIN_CVTPS2PD
, 0, 0 },
12201 { MASK_SSE2
, CODE_FOR_cvttps2dq
, 0, IX86_BUILTIN_CVTTPS2DQ
, 0, 0 },
12203 { MASK_SSE2
, CODE_FOR_sse2_movq
, 0, IX86_BUILTIN_MOVQ
, 0, 0 },
12206 { MASK_SSE3
, CODE_FOR_movshdup
, 0, IX86_BUILTIN_MOVSHDUP
, 0, 0 },
12207 { MASK_SSE3
, CODE_FOR_movsldup
, 0, IX86_BUILTIN_MOVSLDUP
, 0, 0 },
12208 { MASK_SSE3
, CODE_FOR_movddup
, 0, IX86_BUILTIN_MOVDDUP
, 0, 0 }
12212 ix86_init_builtins (void)
12215 ix86_init_mmx_sse_builtins ();
12218 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
12219 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
12222 ix86_init_mmx_sse_builtins (void)
12224 const struct builtin_description
* d
;
12227 tree V16QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V16QImode
);
12228 tree V2SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V2SImode
);
12229 tree V2SF_type_node
= build_vector_type_for_mode (float_type_node
, V2SFmode
);
12230 tree V2DI_type_node
= build_vector_type_for_mode (intDI_type_node
, V2DImode
);
12231 tree V2DF_type_node
= build_vector_type_for_mode (double_type_node
, V2DFmode
);
12232 tree V4SF_type_node
= build_vector_type_for_mode (float_type_node
, V4SFmode
);
12233 tree V4SI_type_node
= build_vector_type_for_mode (intSI_type_node
, V4SImode
);
12234 tree V4HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V4HImode
);
12235 tree V8QI_type_node
= build_vector_type_for_mode (intQI_type_node
, V8QImode
);
12236 tree V8HI_type_node
= build_vector_type_for_mode (intHI_type_node
, V8HImode
);
12238 tree pchar_type_node
= build_pointer_type (char_type_node
);
12239 tree pcchar_type_node
= build_pointer_type (
12240 build_type_variant (char_type_node
, 1, 0));
12241 tree pfloat_type_node
= build_pointer_type (float_type_node
);
12242 tree pcfloat_type_node
= build_pointer_type (
12243 build_type_variant (float_type_node
, 1, 0));
12244 tree pv2si_type_node
= build_pointer_type (V2SI_type_node
);
12245 tree pv2di_type_node
= build_pointer_type (V2DI_type_node
);
12246 tree pdi_type_node
= build_pointer_type (long_long_unsigned_type_node
);
12249 tree int_ftype_v4sf_v4sf
12250 = build_function_type_list (integer_type_node
,
12251 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12252 tree v4si_ftype_v4sf_v4sf
12253 = build_function_type_list (V4SI_type_node
,
12254 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12255 /* MMX/SSE/integer conversions. */
12256 tree int_ftype_v4sf
12257 = build_function_type_list (integer_type_node
,
12258 V4SF_type_node
, NULL_TREE
);
12259 tree int64_ftype_v4sf
12260 = build_function_type_list (long_long_integer_type_node
,
12261 V4SF_type_node
, NULL_TREE
);
12262 tree int_ftype_v8qi
12263 = build_function_type_list (integer_type_node
, V8QI_type_node
, NULL_TREE
);
12264 tree v4sf_ftype_v4sf_int
12265 = build_function_type_list (V4SF_type_node
,
12266 V4SF_type_node
, integer_type_node
, NULL_TREE
);
12267 tree v4sf_ftype_v4sf_int64
12268 = build_function_type_list (V4SF_type_node
,
12269 V4SF_type_node
, long_long_integer_type_node
,
12271 tree v4sf_ftype_v4sf_v2si
12272 = build_function_type_list (V4SF_type_node
,
12273 V4SF_type_node
, V2SI_type_node
, NULL_TREE
);
12274 tree int_ftype_v4hi_int
12275 = build_function_type_list (integer_type_node
,
12276 V4HI_type_node
, integer_type_node
, NULL_TREE
);
12277 tree v4hi_ftype_v4hi_int_int
12278 = build_function_type_list (V4HI_type_node
, V4HI_type_node
,
12279 integer_type_node
, integer_type_node
,
12281 /* Miscellaneous. */
12282 tree v8qi_ftype_v4hi_v4hi
12283 = build_function_type_list (V8QI_type_node
,
12284 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
12285 tree v4hi_ftype_v2si_v2si
12286 = build_function_type_list (V4HI_type_node
,
12287 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12288 tree v4sf_ftype_v4sf_v4sf_int
12289 = build_function_type_list (V4SF_type_node
,
12290 V4SF_type_node
, V4SF_type_node
,
12291 integer_type_node
, NULL_TREE
);
12292 tree v2si_ftype_v4hi_v4hi
12293 = build_function_type_list (V2SI_type_node
,
12294 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
12295 tree v4hi_ftype_v4hi_int
12296 = build_function_type_list (V4HI_type_node
,
12297 V4HI_type_node
, integer_type_node
, NULL_TREE
);
12298 tree v4hi_ftype_v4hi_di
12299 = build_function_type_list (V4HI_type_node
,
12300 V4HI_type_node
, long_long_unsigned_type_node
,
12302 tree v2si_ftype_v2si_di
12303 = build_function_type_list (V2SI_type_node
,
12304 V2SI_type_node
, long_long_unsigned_type_node
,
12306 tree void_ftype_void
12307 = build_function_type (void_type_node
, void_list_node
);
12308 tree void_ftype_unsigned
12309 = build_function_type_list (void_type_node
, unsigned_type_node
, NULL_TREE
);
12310 tree void_ftype_unsigned_unsigned
12311 = build_function_type_list (void_type_node
, unsigned_type_node
,
12312 unsigned_type_node
, NULL_TREE
);
12313 tree void_ftype_pcvoid_unsigned_unsigned
12314 = build_function_type_list (void_type_node
, const_ptr_type_node
,
12315 unsigned_type_node
, unsigned_type_node
,
12317 tree unsigned_ftype_void
12318 = build_function_type (unsigned_type_node
, void_list_node
);
12320 = build_function_type (long_long_unsigned_type_node
, void_list_node
);
12321 tree v4sf_ftype_void
12322 = build_function_type (V4SF_type_node
, void_list_node
);
12323 tree v2si_ftype_v4sf
12324 = build_function_type_list (V2SI_type_node
, V4SF_type_node
, NULL_TREE
);
12325 /* Loads/stores. */
12326 tree void_ftype_v8qi_v8qi_pchar
12327 = build_function_type_list (void_type_node
,
12328 V8QI_type_node
, V8QI_type_node
,
12329 pchar_type_node
, NULL_TREE
);
12330 tree v4sf_ftype_pcfloat
12331 = build_function_type_list (V4SF_type_node
, pcfloat_type_node
, NULL_TREE
);
12332 /* @@@ the type is bogus */
12333 tree v4sf_ftype_v4sf_pv2si
12334 = build_function_type_list (V4SF_type_node
,
12335 V4SF_type_node
, pv2si_type_node
, NULL_TREE
);
12336 tree void_ftype_pv2si_v4sf
12337 = build_function_type_list (void_type_node
,
12338 pv2si_type_node
, V4SF_type_node
, NULL_TREE
);
12339 tree void_ftype_pfloat_v4sf
12340 = build_function_type_list (void_type_node
,
12341 pfloat_type_node
, V4SF_type_node
, NULL_TREE
);
12342 tree void_ftype_pdi_di
12343 = build_function_type_list (void_type_node
,
12344 pdi_type_node
, long_long_unsigned_type_node
,
12346 tree void_ftype_pv2di_v2di
12347 = build_function_type_list (void_type_node
,
12348 pv2di_type_node
, V2DI_type_node
, NULL_TREE
);
12349 /* Normal vector unops. */
12350 tree v4sf_ftype_v4sf
12351 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12353 /* Normal vector binops. */
12354 tree v4sf_ftype_v4sf_v4sf
12355 = build_function_type_list (V4SF_type_node
,
12356 V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
12357 tree v8qi_ftype_v8qi_v8qi
12358 = build_function_type_list (V8QI_type_node
,
12359 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
12360 tree v4hi_ftype_v4hi_v4hi
12361 = build_function_type_list (V4HI_type_node
,
12362 V4HI_type_node
, V4HI_type_node
, NULL_TREE
);
12363 tree v2si_ftype_v2si_v2si
12364 = build_function_type_list (V2SI_type_node
,
12365 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12366 tree di_ftype_di_di
12367 = build_function_type_list (long_long_unsigned_type_node
,
12368 long_long_unsigned_type_node
,
12369 long_long_unsigned_type_node
, NULL_TREE
);
12371 tree v2si_ftype_v2sf
12372 = build_function_type_list (V2SI_type_node
, V2SF_type_node
, NULL_TREE
);
12373 tree v2sf_ftype_v2si
12374 = build_function_type_list (V2SF_type_node
, V2SI_type_node
, NULL_TREE
);
12375 tree v2si_ftype_v2si
12376 = build_function_type_list (V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12377 tree v2sf_ftype_v2sf
12378 = build_function_type_list (V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
12379 tree v2sf_ftype_v2sf_v2sf
12380 = build_function_type_list (V2SF_type_node
,
12381 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
12382 tree v2si_ftype_v2sf_v2sf
12383 = build_function_type_list (V2SI_type_node
,
12384 V2SF_type_node
, V2SF_type_node
, NULL_TREE
);
12385 tree pint_type_node
= build_pointer_type (integer_type_node
);
12386 tree pcint_type_node
= build_pointer_type (
12387 build_type_variant (integer_type_node
, 1, 0));
12388 tree pdouble_type_node
= build_pointer_type (double_type_node
);
12389 tree pcdouble_type_node
= build_pointer_type (
12390 build_type_variant (double_type_node
, 1, 0));
12391 tree int_ftype_v2df_v2df
12392 = build_function_type_list (integer_type_node
,
12393 V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12396 = build_function_type (intTI_type_node
, void_list_node
);
12397 tree v2di_ftype_void
12398 = build_function_type (V2DI_type_node
, void_list_node
);
12399 tree ti_ftype_ti_ti
12400 = build_function_type_list (intTI_type_node
,
12401 intTI_type_node
, intTI_type_node
, NULL_TREE
);
12402 tree void_ftype_pcvoid
12403 = build_function_type_list (void_type_node
, const_ptr_type_node
, NULL_TREE
);
12405 = build_function_type_list (V2DI_type_node
,
12406 long_long_unsigned_type_node
, NULL_TREE
);
12408 = build_function_type_list (long_long_unsigned_type_node
,
12409 V2DI_type_node
, NULL_TREE
);
12410 tree v4sf_ftype_v4si
12411 = build_function_type_list (V4SF_type_node
, V4SI_type_node
, NULL_TREE
);
12412 tree v4si_ftype_v4sf
12413 = build_function_type_list (V4SI_type_node
, V4SF_type_node
, NULL_TREE
);
12414 tree v2df_ftype_v4si
12415 = build_function_type_list (V2DF_type_node
, V4SI_type_node
, NULL_TREE
);
12416 tree v4si_ftype_v2df
12417 = build_function_type_list (V4SI_type_node
, V2DF_type_node
, NULL_TREE
);
12418 tree v2si_ftype_v2df
12419 = build_function_type_list (V2SI_type_node
, V2DF_type_node
, NULL_TREE
);
12420 tree v4sf_ftype_v2df
12421 = build_function_type_list (V4SF_type_node
, V2DF_type_node
, NULL_TREE
);
12422 tree v2df_ftype_v2si
12423 = build_function_type_list (V2DF_type_node
, V2SI_type_node
, NULL_TREE
);
12424 tree v2df_ftype_v4sf
12425 = build_function_type_list (V2DF_type_node
, V4SF_type_node
, NULL_TREE
);
12426 tree int_ftype_v2df
12427 = build_function_type_list (integer_type_node
, V2DF_type_node
, NULL_TREE
);
12428 tree int64_ftype_v2df
12429 = build_function_type_list (long_long_integer_type_node
,
12430 V2DF_type_node
, NULL_TREE
);
12431 tree v2df_ftype_v2df_int
12432 = build_function_type_list (V2DF_type_node
,
12433 V2DF_type_node
, integer_type_node
, NULL_TREE
);
12434 tree v2df_ftype_v2df_int64
12435 = build_function_type_list (V2DF_type_node
,
12436 V2DF_type_node
, long_long_integer_type_node
,
12438 tree v4sf_ftype_v4sf_v2df
12439 = build_function_type_list (V4SF_type_node
,
12440 V4SF_type_node
, V2DF_type_node
, NULL_TREE
);
12441 tree v2df_ftype_v2df_v4sf
12442 = build_function_type_list (V2DF_type_node
,
12443 V2DF_type_node
, V4SF_type_node
, NULL_TREE
);
12444 tree v2df_ftype_v2df_v2df_int
12445 = build_function_type_list (V2DF_type_node
,
12446 V2DF_type_node
, V2DF_type_node
,
12449 tree v2df_ftype_v2df_pv2si
12450 = build_function_type_list (V2DF_type_node
,
12451 V2DF_type_node
, pv2si_type_node
, NULL_TREE
);
12452 tree void_ftype_pv2si_v2df
12453 = build_function_type_list (void_type_node
,
12454 pv2si_type_node
, V2DF_type_node
, NULL_TREE
);
12455 tree void_ftype_pdouble_v2df
12456 = build_function_type_list (void_type_node
,
12457 pdouble_type_node
, V2DF_type_node
, NULL_TREE
);
12458 tree void_ftype_pint_int
12459 = build_function_type_list (void_type_node
,
12460 pint_type_node
, integer_type_node
, NULL_TREE
);
12461 tree void_ftype_v16qi_v16qi_pchar
12462 = build_function_type_list (void_type_node
,
12463 V16QI_type_node
, V16QI_type_node
,
12464 pchar_type_node
, NULL_TREE
);
12465 tree v2df_ftype_pcdouble
12466 = build_function_type_list (V2DF_type_node
, pcdouble_type_node
, NULL_TREE
);
12467 tree v2df_ftype_v2df_v2df
12468 = build_function_type_list (V2DF_type_node
,
12469 V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12470 tree v16qi_ftype_v16qi_v16qi
12471 = build_function_type_list (V16QI_type_node
,
12472 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12473 tree v8hi_ftype_v8hi_v8hi
12474 = build_function_type_list (V8HI_type_node
,
12475 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12476 tree v4si_ftype_v4si_v4si
12477 = build_function_type_list (V4SI_type_node
,
12478 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12479 tree v2di_ftype_v2di_v2di
12480 = build_function_type_list (V2DI_type_node
,
12481 V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
12482 tree v2di_ftype_v2df_v2df
12483 = build_function_type_list (V2DI_type_node
,
12484 V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12485 tree v2df_ftype_v2df
12486 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
12487 tree v2df_ftype_double
12488 = build_function_type_list (V2DF_type_node
, double_type_node
, NULL_TREE
);
12489 tree v2df_ftype_double_double
12490 = build_function_type_list (V2DF_type_node
,
12491 double_type_node
, double_type_node
, NULL_TREE
);
12492 tree int_ftype_v8hi_int
12493 = build_function_type_list (integer_type_node
,
12494 V8HI_type_node
, integer_type_node
, NULL_TREE
);
12495 tree v8hi_ftype_v8hi_int_int
12496 = build_function_type_list (V8HI_type_node
,
12497 V8HI_type_node
, integer_type_node
,
12498 integer_type_node
, NULL_TREE
);
12499 tree v2di_ftype_v2di_int
12500 = build_function_type_list (V2DI_type_node
,
12501 V2DI_type_node
, integer_type_node
, NULL_TREE
);
12502 tree v4si_ftype_v4si_int
12503 = build_function_type_list (V4SI_type_node
,
12504 V4SI_type_node
, integer_type_node
, NULL_TREE
);
12505 tree v8hi_ftype_v8hi_int
12506 = build_function_type_list (V8HI_type_node
,
12507 V8HI_type_node
, integer_type_node
, NULL_TREE
);
12508 tree v8hi_ftype_v8hi_v2di
12509 = build_function_type_list (V8HI_type_node
,
12510 V8HI_type_node
, V2DI_type_node
, NULL_TREE
);
12511 tree v4si_ftype_v4si_v2di
12512 = build_function_type_list (V4SI_type_node
,
12513 V4SI_type_node
, V2DI_type_node
, NULL_TREE
);
12514 tree v4si_ftype_v8hi_v8hi
12515 = build_function_type_list (V4SI_type_node
,
12516 V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
12517 tree di_ftype_v8qi_v8qi
12518 = build_function_type_list (long_long_unsigned_type_node
,
12519 V8QI_type_node
, V8QI_type_node
, NULL_TREE
);
12520 tree di_ftype_v2si_v2si
12521 = build_function_type_list (long_long_unsigned_type_node
,
12522 V2SI_type_node
, V2SI_type_node
, NULL_TREE
);
12523 tree v2di_ftype_v16qi_v16qi
12524 = build_function_type_list (V2DI_type_node
,
12525 V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
12526 tree v2di_ftype_v4si_v4si
12527 = build_function_type_list (V2DI_type_node
,
12528 V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
12529 tree int_ftype_v16qi
12530 = build_function_type_list (integer_type_node
, V16QI_type_node
, NULL_TREE
);
12531 tree v16qi_ftype_pcchar
12532 = build_function_type_list (V16QI_type_node
, pcchar_type_node
, NULL_TREE
);
12533 tree void_ftype_pchar_v16qi
12534 = build_function_type_list (void_type_node
,
12535 pchar_type_node
, V16QI_type_node
, NULL_TREE
);
12536 tree v4si_ftype_pcint
12537 = build_function_type_list (V4SI_type_node
, pcint_type_node
, NULL_TREE
);
12538 tree void_ftype_pcint_v4si
12539 = build_function_type_list (void_type_node
,
12540 pcint_type_node
, V4SI_type_node
, NULL_TREE
);
12541 tree v2di_ftype_v2di
12542 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
12545 tree float128_type
;
12547 /* The __float80 type. */
12548 if (TYPE_MODE (long_double_type_node
) == XFmode
)
12549 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
12553 /* The __float80 type. */
12554 float80_type
= make_node (REAL_TYPE
);
12555 TYPE_PRECISION (float80_type
) = 80;
12556 layout_type (float80_type
);
12557 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
12560 float128_type
= make_node (REAL_TYPE
);
12561 TYPE_PRECISION (float128_type
) = 128;
12562 layout_type (float128_type
);
12563 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
12565 /* Add all builtins that are more or less simple operations on two
12567 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
12569 /* Use one of the operands; the target can have a different mode for
12570 mask-generating compares. */
12571 enum machine_mode mode
;
12576 mode
= insn_data
[d
->icode
].operand
[1].mode
;
12581 type
= v16qi_ftype_v16qi_v16qi
;
12584 type
= v8hi_ftype_v8hi_v8hi
;
12587 type
= v4si_ftype_v4si_v4si
;
12590 type
= v2di_ftype_v2di_v2di
;
12593 type
= v2df_ftype_v2df_v2df
;
12596 type
= ti_ftype_ti_ti
;
12599 type
= v4sf_ftype_v4sf_v4sf
;
12602 type
= v8qi_ftype_v8qi_v8qi
;
12605 type
= v4hi_ftype_v4hi_v4hi
;
12608 type
= v2si_ftype_v2si_v2si
;
12611 type
= di_ftype_di_di
;
12618 /* Override for comparisons. */
12619 if (d
->icode
== CODE_FOR_maskcmpv4sf3
12620 || d
->icode
== CODE_FOR_maskncmpv4sf3
12621 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
12622 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
)
12623 type
= v4si_ftype_v4sf_v4sf
;
12625 if (d
->icode
== CODE_FOR_maskcmpv2df3
12626 || d
->icode
== CODE_FOR_maskncmpv2df3
12627 || d
->icode
== CODE_FOR_vmmaskcmpv2df3
12628 || d
->icode
== CODE_FOR_vmmaskncmpv2df3
)
12629 type
= v2di_ftype_v2df_v2df
;
12631 def_builtin (d
->mask
, d
->name
, type
, d
->code
);
12634 /* Add the remaining MMX insns with somewhat more complicated types. */
12635 def_builtin (MASK_MMX
, "__builtin_ia32_mmx_zero", di_ftype_void
, IX86_BUILTIN_MMX_ZERO
);
12636 def_builtin (MASK_MMX
, "__builtin_ia32_emms", void_ftype_void
, IX86_BUILTIN_EMMS
);
12637 def_builtin (MASK_MMX
, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSLLW
);
12638 def_builtin (MASK_MMX
, "__builtin_ia32_pslld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSLLD
);
12639 def_builtin (MASK_MMX
, "__builtin_ia32_psllq", di_ftype_di_di
, IX86_BUILTIN_PSLLQ
);
12641 def_builtin (MASK_MMX
, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRLW
);
12642 def_builtin (MASK_MMX
, "__builtin_ia32_psrld", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRLD
);
12643 def_builtin (MASK_MMX
, "__builtin_ia32_psrlq", di_ftype_di_di
, IX86_BUILTIN_PSRLQ
);
12645 def_builtin (MASK_MMX
, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di
, IX86_BUILTIN_PSRAW
);
12646 def_builtin (MASK_MMX
, "__builtin_ia32_psrad", v2si_ftype_v2si_di
, IX86_BUILTIN_PSRAD
);
12648 def_builtin (MASK_MMX
, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int
, IX86_BUILTIN_PSHUFW
);
12649 def_builtin (MASK_MMX
, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi
, IX86_BUILTIN_PMADDWD
);
12651 /* comi/ucomi insns. */
12652 for (i
= 0, d
= bdesc_comi
; i
< ARRAY_SIZE (bdesc_comi
); i
++, d
++)
12653 if (d
->mask
== MASK_SSE2
)
12654 def_builtin (d
->mask
, d
->name
, int_ftype_v2df_v2df
, d
->code
);
12656 def_builtin (d
->mask
, d
->name
, int_ftype_v4sf_v4sf
, d
->code
);
12658 def_builtin (MASK_MMX
, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKSSWB
);
12659 def_builtin (MASK_MMX
, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si
, IX86_BUILTIN_PACKSSDW
);
12660 def_builtin (MASK_MMX
, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi
, IX86_BUILTIN_PACKUSWB
);
12662 def_builtin (MASK_SSE
, "__builtin_ia32_ldmxcsr", void_ftype_unsigned
, IX86_BUILTIN_LDMXCSR
);
12663 def_builtin (MASK_SSE
, "__builtin_ia32_stmxcsr", unsigned_ftype_void
, IX86_BUILTIN_STMXCSR
);
12664 def_builtin (MASK_SSE
, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si
, IX86_BUILTIN_CVTPI2PS
);
12665 def_builtin (MASK_SSE
, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTPS2PI
);
12666 def_builtin (MASK_SSE
, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int
, IX86_BUILTIN_CVTSI2SS
);
12667 def_builtin (MASK_SSE
| MASK_64BIT
, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64
, IX86_BUILTIN_CVTSI642SS
);
12668 def_builtin (MASK_SSE
, "__builtin_ia32_cvtss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTSS2SI
);
12669 def_builtin (MASK_SSE
| MASK_64BIT
, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf
, IX86_BUILTIN_CVTSS2SI64
);
12670 def_builtin (MASK_SSE
, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf
, IX86_BUILTIN_CVTTPS2PI
);
12671 def_builtin (MASK_SSE
, "__builtin_ia32_cvttss2si", int_ftype_v4sf
, IX86_BUILTIN_CVTTSS2SI
);
12672 def_builtin (MASK_SSE
| MASK_64BIT
, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf
, IX86_BUILTIN_CVTTSS2SI64
);
12674 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pextrw", int_ftype_v4hi_int
, IX86_BUILTIN_PEXTRW
);
12675 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pinsrw", v4hi_ftype_v4hi_int_int
, IX86_BUILTIN_PINSRW
);
12677 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar
, IX86_BUILTIN_MASKMOVQ
);
12679 def_builtin (MASK_SSE
, "__builtin_ia32_loadaps", v4sf_ftype_pcfloat
, IX86_BUILTIN_LOADAPS
);
12680 def_builtin (MASK_SSE
, "__builtin_ia32_loadups", v4sf_ftype_pcfloat
, IX86_BUILTIN_LOADUPS
);
12681 def_builtin (MASK_SSE
, "__builtin_ia32_loadss", v4sf_ftype_pcfloat
, IX86_BUILTIN_LOADSS
);
12682 def_builtin (MASK_SSE
, "__builtin_ia32_storeaps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREAPS
);
12683 def_builtin (MASK_SSE
, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STOREUPS
);
12684 def_builtin (MASK_SSE
, "__builtin_ia32_storess", void_ftype_pfloat_v4sf
, IX86_BUILTIN_STORESS
);
12686 def_builtin (MASK_SSE
, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADHPS
);
12687 def_builtin (MASK_SSE
, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si
, IX86_BUILTIN_LOADLPS
);
12688 def_builtin (MASK_SSE
, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf
, IX86_BUILTIN_STOREHPS
);
12689 def_builtin (MASK_SSE
, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf
, IX86_BUILTIN_STORELPS
);
12691 def_builtin (MASK_SSE
, "__builtin_ia32_movmskps", int_ftype_v4sf
, IX86_BUILTIN_MOVMSKPS
);
12692 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_pmovmskb", int_ftype_v8qi
, IX86_BUILTIN_PMOVMSKB
);
12693 def_builtin (MASK_SSE
, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf
, IX86_BUILTIN_MOVNTPS
);
12694 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_movntq", void_ftype_pdi_di
, IX86_BUILTIN_MOVNTQ
);
12696 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_sfence", void_ftype_void
, IX86_BUILTIN_SFENCE
);
12698 def_builtin (MASK_SSE
| MASK_3DNOW_A
, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi
, IX86_BUILTIN_PSADBW
);
12700 def_builtin (MASK_SSE
, "__builtin_ia32_rcpps", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPPS
);
12701 def_builtin (MASK_SSE
, "__builtin_ia32_rcpss", v4sf_ftype_v4sf
, IX86_BUILTIN_RCPSS
);
12702 def_builtin (MASK_SSE
, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTPS
);
12703 def_builtin (MASK_SSE
, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_RSQRTSS
);
12704 def_builtin (MASK_SSE
, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTPS
);
12705 def_builtin (MASK_SSE
, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf
, IX86_BUILTIN_SQRTSS
);
12707 def_builtin (MASK_SSE
, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int
, IX86_BUILTIN_SHUFPS
);
12709 /* Original 3DNow! */
12710 def_builtin (MASK_3DNOW
, "__builtin_ia32_femms", void_ftype_void
, IX86_BUILTIN_FEMMS
);
12711 def_builtin (MASK_3DNOW
, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi
, IX86_BUILTIN_PAVGUSB
);
12712 def_builtin (MASK_3DNOW
, "__builtin_ia32_pf2id", v2si_ftype_v2sf
, IX86_BUILTIN_PF2ID
);
12713 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFACC
);
12714 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFADD
);
12715 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPEQ
);
12716 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPGE
);
12717 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf
, IX86_BUILTIN_PFCMPGT
);
12718 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMAX
);
12719 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMIN
);
12720 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFMUL
);
12721 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf
, IX86_BUILTIN_PFRCP
);
12722 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRCPIT1
);
12723 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRCPIT2
);
12724 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf
, IX86_BUILTIN_PFRSQRT
);
12725 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFRSQIT1
);
12726 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFSUB
);
12727 def_builtin (MASK_3DNOW
, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFSUBR
);
12728 def_builtin (MASK_3DNOW
, "__builtin_ia32_pi2fd", v2sf_ftype_v2si
, IX86_BUILTIN_PI2FD
);
12729 def_builtin (MASK_3DNOW
, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi
, IX86_BUILTIN_PMULHRW
);
12731 /* 3DNow! extension as used in the Athlon CPU. */
12732 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pf2iw", v2si_ftype_v2sf
, IX86_BUILTIN_PF2IW
);
12733 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFNACC
);
12734 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf
, IX86_BUILTIN_PFPNACC
);
12735 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pi2fw", v2sf_ftype_v2si
, IX86_BUILTIN_PI2FW
);
12736 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf
, IX86_BUILTIN_PSWAPDSF
);
12737 def_builtin (MASK_3DNOW_A
, "__builtin_ia32_pswapdsi", v2si_ftype_v2si
, IX86_BUILTIN_PSWAPDSI
);
12739 def_builtin (MASK_SSE
, "__builtin_ia32_setzerops", v4sf_ftype_void
, IX86_BUILTIN_SSE_ZERO
);
12742 def_builtin (MASK_SSE2
, "__builtin_ia32_pextrw128", int_ftype_v8hi_int
, IX86_BUILTIN_PEXTRW128
);
12743 def_builtin (MASK_SSE2
, "__builtin_ia32_pinsrw128", v8hi_ftype_v8hi_int_int
, IX86_BUILTIN_PINSRW128
);
12745 def_builtin (MASK_SSE2
, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar
, IX86_BUILTIN_MASKMOVDQU
);
12746 def_builtin (MASK_SSE2
, "__builtin_ia32_movq2dq", v2di_ftype_di
, IX86_BUILTIN_MOVQ2DQ
);
12747 def_builtin (MASK_SSE2
, "__builtin_ia32_movdq2q", di_ftype_v2di
, IX86_BUILTIN_MOVDQ2Q
);
12749 def_builtin (MASK_SSE2
, "__builtin_ia32_loadapd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADAPD
);
12750 def_builtin (MASK_SSE2
, "__builtin_ia32_loadupd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADUPD
);
12751 def_builtin (MASK_SSE2
, "__builtin_ia32_loadsd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADSD
);
12752 def_builtin (MASK_SSE2
, "__builtin_ia32_storeapd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STOREAPD
);
12753 def_builtin (MASK_SSE2
, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STOREUPD
);
12754 def_builtin (MASK_SSE2
, "__builtin_ia32_storesd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STORESD
);
12756 def_builtin (MASK_SSE2
, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pv2si
, IX86_BUILTIN_LOADHPD
);
12757 def_builtin (MASK_SSE2
, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pv2si
, IX86_BUILTIN_LOADLPD
);
12758 def_builtin (MASK_SSE2
, "__builtin_ia32_storehpd", void_ftype_pv2si_v2df
, IX86_BUILTIN_STOREHPD
);
12759 def_builtin (MASK_SSE2
, "__builtin_ia32_storelpd", void_ftype_pv2si_v2df
, IX86_BUILTIN_STORELPD
);
12761 def_builtin (MASK_SSE2
, "__builtin_ia32_movmskpd", int_ftype_v2df
, IX86_BUILTIN_MOVMSKPD
);
12762 def_builtin (MASK_SSE2
, "__builtin_ia32_pmovmskb128", int_ftype_v16qi
, IX86_BUILTIN_PMOVMSKB128
);
12763 def_builtin (MASK_SSE2
, "__builtin_ia32_movnti", void_ftype_pint_int
, IX86_BUILTIN_MOVNTI
);
12764 def_builtin (MASK_SSE2
, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df
, IX86_BUILTIN_MOVNTPD
);
12765 def_builtin (MASK_SSE2
, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di
, IX86_BUILTIN_MOVNTDQ
);
12767 def_builtin (MASK_SSE2
, "__builtin_ia32_pshufd", v4si_ftype_v4si_int
, IX86_BUILTIN_PSHUFD
);
12768 def_builtin (MASK_SSE2
, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSHUFLW
);
12769 def_builtin (MASK_SSE2
, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSHUFHW
);
12770 def_builtin (MASK_SSE2
, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi
, IX86_BUILTIN_PSADBW128
);
12772 def_builtin (MASK_SSE2
, "__builtin_ia32_sqrtpd", v2df_ftype_v2df
, IX86_BUILTIN_SQRTPD
);
12773 def_builtin (MASK_SSE2
, "__builtin_ia32_sqrtsd", v2df_ftype_v2df
, IX86_BUILTIN_SQRTSD
);
12775 def_builtin (MASK_SSE2
, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int
, IX86_BUILTIN_SHUFPD
);
12777 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si
, IX86_BUILTIN_CVTDQ2PD
);
12778 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si
, IX86_BUILTIN_CVTDQ2PS
);
12780 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df
, IX86_BUILTIN_CVTPD2DQ
);
12781 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df
, IX86_BUILTIN_CVTPD2PI
);
12782 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df
, IX86_BUILTIN_CVTPD2PS
);
12783 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df
, IX86_BUILTIN_CVTTPD2DQ
);
12784 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df
, IX86_BUILTIN_CVTTPD2PI
);
12786 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si
, IX86_BUILTIN_CVTPI2PD
);
12788 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtsd2si", int_ftype_v2df
, IX86_BUILTIN_CVTSD2SI
);
12789 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttsd2si", int_ftype_v2df
, IX86_BUILTIN_CVTTSD2SI
);
12790 def_builtin (MASK_SSE2
| MASK_64BIT
, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df
, IX86_BUILTIN_CVTSD2SI64
);
12791 def_builtin (MASK_SSE2
| MASK_64BIT
, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df
, IX86_BUILTIN_CVTTSD2SI64
);
12793 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf
, IX86_BUILTIN_CVTPS2DQ
);
12794 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf
, IX86_BUILTIN_CVTPS2PD
);
12795 def_builtin (MASK_SSE2
, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf
, IX86_BUILTIN_CVTTPS2DQ
);
12797 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int
, IX86_BUILTIN_CVTSI2SD
);
12798 def_builtin (MASK_SSE2
| MASK_64BIT
, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64
, IX86_BUILTIN_CVTSI642SD
);
12799 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df
, IX86_BUILTIN_CVTSD2SS
);
12800 def_builtin (MASK_SSE2
, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf
, IX86_BUILTIN_CVTSS2SD
);
12802 def_builtin (MASK_SSE2
, "__builtin_ia32_setpd1", v2df_ftype_double
, IX86_BUILTIN_SETPD1
);
12803 def_builtin (MASK_SSE2
, "__builtin_ia32_setpd", v2df_ftype_double_double
, IX86_BUILTIN_SETPD
);
12804 def_builtin (MASK_SSE2
, "__builtin_ia32_setzeropd", ti_ftype_void
, IX86_BUILTIN_CLRPD
);
12805 def_builtin (MASK_SSE2
, "__builtin_ia32_loadpd1", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADPD1
);
12806 def_builtin (MASK_SSE2
, "__builtin_ia32_loadrpd", v2df_ftype_pcdouble
, IX86_BUILTIN_LOADRPD
);
12807 def_builtin (MASK_SSE2
, "__builtin_ia32_storepd1", void_ftype_pdouble_v2df
, IX86_BUILTIN_STOREPD1
);
12808 def_builtin (MASK_SSE2
, "__builtin_ia32_storerpd", void_ftype_pdouble_v2df
, IX86_BUILTIN_STORERPD
);
12810 def_builtin (MASK_SSE2
, "__builtin_ia32_clflush", void_ftype_pcvoid
, IX86_BUILTIN_CLFLUSH
);
12811 def_builtin (MASK_SSE2
, "__builtin_ia32_lfence", void_ftype_void
, IX86_BUILTIN_LFENCE
);
12812 def_builtin (MASK_SSE2
, "__builtin_ia32_mfence", void_ftype_void
, IX86_BUILTIN_MFENCE
);
12814 def_builtin (MASK_SSE2
, "__builtin_ia32_loaddqa", v16qi_ftype_pcchar
, IX86_BUILTIN_LOADDQA
);
12815 def_builtin (MASK_SSE2
, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar
, IX86_BUILTIN_LOADDQU
);
12816 def_builtin (MASK_SSE2
, "__builtin_ia32_loadd", v4si_ftype_pcint
, IX86_BUILTIN_LOADD
);
12817 def_builtin (MASK_SSE2
, "__builtin_ia32_storedqa", void_ftype_pchar_v16qi
, IX86_BUILTIN_STOREDQA
);
12818 def_builtin (MASK_SSE2
, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi
, IX86_BUILTIN_STOREDQU
);
12819 def_builtin (MASK_SSE2
, "__builtin_ia32_stored", void_ftype_pcint_v4si
, IX86_BUILTIN_STORED
);
12820 def_builtin (MASK_SSE2
, "__builtin_ia32_movq", v2di_ftype_v2di
, IX86_BUILTIN_MOVQ
);
12822 def_builtin (MASK_SSE
, "__builtin_ia32_setzero128", v2di_ftype_void
, IX86_BUILTIN_CLRTI
);
12824 def_builtin (MASK_SSE2
, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si
, IX86_BUILTIN_PMULUDQ
);
12825 def_builtin (MASK_SSE2
, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si
, IX86_BUILTIN_PMULUDQ128
);
12827 def_builtin (MASK_SSE2
, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di
, IX86_BUILTIN_PSLLW128
);
12828 def_builtin (MASK_SSE2
, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di
, IX86_BUILTIN_PSLLD128
);
12829 def_builtin (MASK_SSE2
, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di
, IX86_BUILTIN_PSLLQ128
);
12831 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di
, IX86_BUILTIN_PSRLW128
);
12832 def_builtin (MASK_SSE2
, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di
, IX86_BUILTIN_PSRLD128
);
12833 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di
, IX86_BUILTIN_PSRLQ128
);
12835 def_builtin (MASK_SSE2
, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di
, IX86_BUILTIN_PSRAW128
);
12836 def_builtin (MASK_SSE2
, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di
, IX86_BUILTIN_PSRAD128
);
12838 def_builtin (MASK_SSE2
, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSLLDQI128
);
12839 def_builtin (MASK_SSE2
, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSLLWI128
);
12840 def_builtin (MASK_SSE2
, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int
, IX86_BUILTIN_PSLLDI128
);
12841 def_builtin (MASK_SSE2
, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSLLQI128
);
12843 def_builtin (MASK_SSE2
, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSRLDQI128
);
12844 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSRLWI128
);
12845 def_builtin (MASK_SSE2
, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int
, IX86_BUILTIN_PSRLDI128
);
12846 def_builtin (MASK_SSE2
, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int
, IX86_BUILTIN_PSRLQI128
);
12848 def_builtin (MASK_SSE2
, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int
, IX86_BUILTIN_PSRAWI128
);
12849 def_builtin (MASK_SSE2
, "__builtin_ia32_psradi128", v4si_ftype_v4si_int
, IX86_BUILTIN_PSRADI128
);
12851 def_builtin (MASK_SSE2
, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi
, IX86_BUILTIN_PMADDWD128
);
12853 /* Prescott New Instructions. */
12854 def_builtin (MASK_SSE3
, "__builtin_ia32_monitor",
12855 void_ftype_pcvoid_unsigned_unsigned
,
12856 IX86_BUILTIN_MONITOR
);
12857 def_builtin (MASK_SSE3
, "__builtin_ia32_mwait",
12858 void_ftype_unsigned_unsigned
,
12859 IX86_BUILTIN_MWAIT
);
12860 def_builtin (MASK_SSE3
, "__builtin_ia32_movshdup",
12862 IX86_BUILTIN_MOVSHDUP
);
12863 def_builtin (MASK_SSE3
, "__builtin_ia32_movsldup",
12865 IX86_BUILTIN_MOVSLDUP
);
12866 def_builtin (MASK_SSE3
, "__builtin_ia32_lddqu",
12867 v16qi_ftype_pcchar
, IX86_BUILTIN_LDDQU
);
12868 def_builtin (MASK_SSE3
, "__builtin_ia32_loadddup",
12869 v2df_ftype_pcdouble
, IX86_BUILTIN_LOADDDUP
);
12870 def_builtin (MASK_SSE3
, "__builtin_ia32_movddup",
12871 v2df_ftype_v2df
, IX86_BUILTIN_MOVDDUP
);
12874 /* Errors in the source file can cause expand_expr to return const0_rtx
12875 where we expect a vector. To avoid crashing, use one of the vector
12876 clear instructions. */
12878 safe_vector_operand (rtx x
, enum machine_mode mode
)
12880 if (x
!= const0_rtx
)
12882 x
= gen_reg_rtx (mode
);
12884 if (VALID_MMX_REG_MODE (mode
) || VALID_MMX_REG_MODE_3DNOW (mode
))
12885 emit_insn (gen_mmx_clrdi (mode
== DImode
? x
12886 : gen_rtx_SUBREG (DImode
, x
, 0)));
12888 emit_insn (gen_sse_clrv4sf (mode
== V4SFmode
? x
12889 : gen_rtx_SUBREG (V4SFmode
, x
, 0),
12890 CONST0_RTX (V4SFmode
)));
12894 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
12897 ix86_expand_binop_builtin (enum insn_code icode
, tree arglist
, rtx target
)
12900 tree arg0
= TREE_VALUE (arglist
);
12901 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12902 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12903 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12904 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12905 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12906 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12908 if (VECTOR_MODE_P (mode0
))
12909 op0
= safe_vector_operand (op0
, mode0
);
12910 if (VECTOR_MODE_P (mode1
))
12911 op1
= safe_vector_operand (op1
, mode1
);
12914 || GET_MODE (target
) != tmode
12915 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12916 target
= gen_reg_rtx (tmode
);
12918 if (GET_MODE (op1
) == SImode
&& mode1
== TImode
)
12920 rtx x
= gen_reg_rtx (V4SImode
);
12921 emit_insn (gen_sse2_loadd (x
, op1
));
12922 op1
= gen_lowpart (TImode
, x
);
12925 /* In case the insn wants input operands in modes different from
12926 the result, abort. */
12927 if ((GET_MODE (op0
) != mode0
&& GET_MODE (op0
) != VOIDmode
)
12928 || (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
))
12931 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12932 op0
= copy_to_mode_reg (mode0
, op0
);
12933 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12934 op1
= copy_to_mode_reg (mode1
, op1
);
12936 /* In the commutative cases, both op0 and op1 are nonimmediate_operand,
12937 yet one of the two must not be a memory. This is normally enforced
12938 by expanders, but we didn't bother to create one here. */
12939 if (GET_CODE (op0
) == MEM
&& GET_CODE (op1
) == MEM
)
12940 op0
= copy_to_mode_reg (mode0
, op0
);
12942 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
12949 /* Subroutine of ix86_expand_builtin to take care of stores. */
12952 ix86_expand_store_builtin (enum insn_code icode
, tree arglist
)
12955 tree arg0
= TREE_VALUE (arglist
);
12956 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
12957 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12958 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
12959 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
12960 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
12962 if (VECTOR_MODE_P (mode1
))
12963 op1
= safe_vector_operand (op1
, mode1
);
12965 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12966 op1
= copy_to_mode_reg (mode1
, op1
);
12968 pat
= GEN_FCN (icode
) (op0
, op1
);
12974 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
12977 ix86_expand_unop_builtin (enum insn_code icode
, tree arglist
,
12978 rtx target
, int do_load
)
12981 tree arg0
= TREE_VALUE (arglist
);
12982 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
12983 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12984 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12987 || GET_MODE (target
) != tmode
12988 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12989 target
= gen_reg_rtx (tmode
);
12991 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12994 if (VECTOR_MODE_P (mode0
))
12995 op0
= safe_vector_operand (op0
, mode0
);
12997 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12998 op0
= copy_to_mode_reg (mode0
, op0
);
13001 pat
= GEN_FCN (icode
) (target
, op0
);
13008 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
13009 sqrtss, rsqrtss, rcpss. */
13012 ix86_expand_unop1_builtin (enum insn_code icode
, tree arglist
, rtx target
)
13015 tree arg0
= TREE_VALUE (arglist
);
13016 rtx op1
, op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13017 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13018 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13021 || GET_MODE (target
) != tmode
13022 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13023 target
= gen_reg_rtx (tmode
);
13025 if (VECTOR_MODE_P (mode0
))
13026 op0
= safe_vector_operand (op0
, mode0
);
13028 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13029 op0
= copy_to_mode_reg (mode0
, op0
);
13032 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode0
))
13033 op1
= copy_to_mode_reg (mode0
, op1
);
13035 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13042 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
13045 ix86_expand_sse_compare (const struct builtin_description
*d
, tree arglist
,
13049 tree arg0
= TREE_VALUE (arglist
);
13050 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13051 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13052 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13054 enum machine_mode tmode
= insn_data
[d
->icode
].operand
[0].mode
;
13055 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[1].mode
;
13056 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[2].mode
;
13057 enum rtx_code comparison
= d
->comparison
;
13059 if (VECTOR_MODE_P (mode0
))
13060 op0
= safe_vector_operand (op0
, mode0
);
13061 if (VECTOR_MODE_P (mode1
))
13062 op1
= safe_vector_operand (op1
, mode1
);
13064 /* Swap operands if we have a comparison that isn't available in
13068 rtx tmp
= gen_reg_rtx (mode1
);
13069 emit_move_insn (tmp
, op1
);
13075 || GET_MODE (target
) != tmode
13076 || ! (*insn_data
[d
->icode
].operand
[0].predicate
) (target
, tmode
))
13077 target
= gen_reg_rtx (tmode
);
13079 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op0
, mode0
))
13080 op0
= copy_to_mode_reg (mode0
, op0
);
13081 if (! (*insn_data
[d
->icode
].operand
[2].predicate
) (op1
, mode1
))
13082 op1
= copy_to_mode_reg (mode1
, op1
);
13084 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
13085 pat
= GEN_FCN (d
->icode
) (target
, op0
, op1
, op2
);
13092 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
13095 ix86_expand_sse_comi (const struct builtin_description
*d
, tree arglist
,
13099 tree arg0
= TREE_VALUE (arglist
);
13100 tree arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13101 rtx op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13102 rtx op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13104 enum machine_mode mode0
= insn_data
[d
->icode
].operand
[0].mode
;
13105 enum machine_mode mode1
= insn_data
[d
->icode
].operand
[1].mode
;
13106 enum rtx_code comparison
= d
->comparison
;
13108 if (VECTOR_MODE_P (mode0
))
13109 op0
= safe_vector_operand (op0
, mode0
);
13110 if (VECTOR_MODE_P (mode1
))
13111 op1
= safe_vector_operand (op1
, mode1
);
13113 /* Swap operands if we have a comparison that isn't available in
13122 target
= gen_reg_rtx (SImode
);
13123 emit_move_insn (target
, const0_rtx
);
13124 target
= gen_rtx_SUBREG (QImode
, target
, 0);
13126 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
13127 op0
= copy_to_mode_reg (mode0
, op0
);
13128 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
13129 op1
= copy_to_mode_reg (mode1
, op1
);
13131 op2
= gen_rtx_fmt_ee (comparison
, mode0
, op0
, op1
);
13132 pat
= GEN_FCN (d
->icode
) (op0
, op1
);
13136 emit_insn (gen_rtx_SET (VOIDmode
,
13137 gen_rtx_STRICT_LOW_PART (VOIDmode
, target
),
13138 gen_rtx_fmt_ee (comparison
, QImode
,
13142 return SUBREG_REG (target
);
13145 /* Expand an expression EXP that calls a built-in function,
13146 with result going to TARGET if that's convenient
13147 (and in mode MODE if that's convenient).
13148 SUBTARGET may be used as the target for computing one of EXP's operands.
13149 IGNORE is nonzero if the value is to be ignored. */
13152 ix86_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13153 enum machine_mode mode ATTRIBUTE_UNUSED
,
13154 int ignore ATTRIBUTE_UNUSED
)
13156 const struct builtin_description
*d
;
13158 enum insn_code icode
;
13159 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
13160 tree arglist
= TREE_OPERAND (exp
, 1);
13161 tree arg0
, arg1
, arg2
;
13162 rtx op0
, op1
, op2
, pat
;
13163 enum machine_mode tmode
, mode0
, mode1
, mode2
;
13164 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
13168 case IX86_BUILTIN_EMMS
:
13169 emit_insn (gen_emms ());
13172 case IX86_BUILTIN_SFENCE
:
13173 emit_insn (gen_sfence ());
13176 case IX86_BUILTIN_PEXTRW
:
13177 case IX86_BUILTIN_PEXTRW128
:
13178 icode
= (fcode
== IX86_BUILTIN_PEXTRW
13179 ? CODE_FOR_mmx_pextrw
13180 : CODE_FOR_sse2_pextrw
);
13181 arg0
= TREE_VALUE (arglist
);
13182 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13183 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13184 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13185 tmode
= insn_data
[icode
].operand
[0].mode
;
13186 mode0
= insn_data
[icode
].operand
[1].mode
;
13187 mode1
= insn_data
[icode
].operand
[2].mode
;
13189 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13190 op0
= copy_to_mode_reg (mode0
, op0
);
13191 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13193 error ("selector must be an integer constant in the range 0..%i",
13194 fcode
== IX86_BUILTIN_PEXTRW
? 3:7);
13195 return gen_reg_rtx (tmode
);
13198 || GET_MODE (target
) != tmode
13199 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13200 target
= gen_reg_rtx (tmode
);
13201 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13207 case IX86_BUILTIN_PINSRW
:
13208 case IX86_BUILTIN_PINSRW128
:
13209 icode
= (fcode
== IX86_BUILTIN_PINSRW
13210 ? CODE_FOR_mmx_pinsrw
13211 : CODE_FOR_sse2_pinsrw
);
13212 arg0
= TREE_VALUE (arglist
);
13213 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13214 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13215 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13216 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13217 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13218 tmode
= insn_data
[icode
].operand
[0].mode
;
13219 mode0
= insn_data
[icode
].operand
[1].mode
;
13220 mode1
= insn_data
[icode
].operand
[2].mode
;
13221 mode2
= insn_data
[icode
].operand
[3].mode
;
13223 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13224 op0
= copy_to_mode_reg (mode0
, op0
);
13225 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13226 op1
= copy_to_mode_reg (mode1
, op1
);
13227 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13229 error ("selector must be an integer constant in the range 0..%i",
13230 fcode
== IX86_BUILTIN_PINSRW
? 15:255);
13234 || GET_MODE (target
) != tmode
13235 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13236 target
= gen_reg_rtx (tmode
);
13237 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13243 case IX86_BUILTIN_MASKMOVQ
:
13244 case IX86_BUILTIN_MASKMOVDQU
:
13245 icode
= (fcode
== IX86_BUILTIN_MASKMOVQ
13246 ? (TARGET_64BIT
? CODE_FOR_mmx_maskmovq_rex
: CODE_FOR_mmx_maskmovq
)
13247 : (TARGET_64BIT
? CODE_FOR_sse2_maskmovdqu_rex64
13248 : CODE_FOR_sse2_maskmovdqu
));
13249 /* Note the arg order is different from the operand order. */
13250 arg1
= TREE_VALUE (arglist
);
13251 arg2
= TREE_VALUE (TREE_CHAIN (arglist
));
13252 arg0
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13253 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13254 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13255 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13256 mode0
= insn_data
[icode
].operand
[0].mode
;
13257 mode1
= insn_data
[icode
].operand
[1].mode
;
13258 mode2
= insn_data
[icode
].operand
[2].mode
;
13260 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13261 op0
= copy_to_mode_reg (mode0
, op0
);
13262 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13263 op1
= copy_to_mode_reg (mode1
, op1
);
13264 if (! (*insn_data
[icode
].operand
[2].predicate
) (op2
, mode2
))
13265 op2
= copy_to_mode_reg (mode2
, op2
);
13266 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
13272 case IX86_BUILTIN_SQRTSS
:
13273 return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv4sf2
, arglist
, target
);
13274 case IX86_BUILTIN_RSQRTSS
:
13275 return ix86_expand_unop1_builtin (CODE_FOR_vmrsqrtv4sf2
, arglist
, target
);
13276 case IX86_BUILTIN_RCPSS
:
13277 return ix86_expand_unop1_builtin (CODE_FOR_vmrcpv4sf2
, arglist
, target
);
13279 case IX86_BUILTIN_LOADAPS
:
13280 return ix86_expand_unop_builtin (CODE_FOR_sse_movaps
, arglist
, target
, 1);
13282 case IX86_BUILTIN_LOADUPS
:
13283 return ix86_expand_unop_builtin (CODE_FOR_sse_movups
, arglist
, target
, 1);
13285 case IX86_BUILTIN_STOREAPS
:
13286 return ix86_expand_store_builtin (CODE_FOR_sse_movaps
, arglist
);
13288 case IX86_BUILTIN_STOREUPS
:
13289 return ix86_expand_store_builtin (CODE_FOR_sse_movups
, arglist
);
13291 case IX86_BUILTIN_LOADSS
:
13292 return ix86_expand_unop_builtin (CODE_FOR_sse_loadss
, arglist
, target
, 1);
13294 case IX86_BUILTIN_STORESS
:
13295 return ix86_expand_store_builtin (CODE_FOR_sse_storess
, arglist
);
13297 case IX86_BUILTIN_LOADHPS
:
13298 case IX86_BUILTIN_LOADLPS
:
13299 case IX86_BUILTIN_LOADHPD
:
13300 case IX86_BUILTIN_LOADLPD
:
13301 icode
= (fcode
== IX86_BUILTIN_LOADHPS
? CODE_FOR_sse_movhps
13302 : fcode
== IX86_BUILTIN_LOADLPS
? CODE_FOR_sse_movlps
13303 : fcode
== IX86_BUILTIN_LOADHPD
? CODE_FOR_sse2_movhpd
13304 : CODE_FOR_sse2_movsd
);
13305 arg0
= TREE_VALUE (arglist
);
13306 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13307 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13308 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13309 tmode
= insn_data
[icode
].operand
[0].mode
;
13310 mode0
= insn_data
[icode
].operand
[1].mode
;
13311 mode1
= insn_data
[icode
].operand
[2].mode
;
13313 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13314 op0
= copy_to_mode_reg (mode0
, op0
);
13315 op1
= gen_rtx_MEM (mode1
, copy_to_mode_reg (Pmode
, op1
));
13317 || GET_MODE (target
) != tmode
13318 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13319 target
= gen_reg_rtx (tmode
);
13320 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13326 case IX86_BUILTIN_STOREHPS
:
13327 case IX86_BUILTIN_STORELPS
:
13328 case IX86_BUILTIN_STOREHPD
:
13329 case IX86_BUILTIN_STORELPD
:
13330 icode
= (fcode
== IX86_BUILTIN_STOREHPS
? CODE_FOR_sse_movhps
13331 : fcode
== IX86_BUILTIN_STORELPS
? CODE_FOR_sse_movlps
13332 : fcode
== IX86_BUILTIN_STOREHPD
? CODE_FOR_sse2_movhpd
13333 : CODE_FOR_sse2_movsd
);
13334 arg0
= TREE_VALUE (arglist
);
13335 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13336 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13337 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13338 mode0
= insn_data
[icode
].operand
[1].mode
;
13339 mode1
= insn_data
[icode
].operand
[2].mode
;
13341 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
13342 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13343 op1
= copy_to_mode_reg (mode1
, op1
);
13345 pat
= GEN_FCN (icode
) (op0
, op0
, op1
);
13351 case IX86_BUILTIN_MOVNTPS
:
13352 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf
, arglist
);
13353 case IX86_BUILTIN_MOVNTQ
:
13354 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi
, arglist
);
13356 case IX86_BUILTIN_LDMXCSR
:
13357 op0
= expand_expr (TREE_VALUE (arglist
), NULL_RTX
, VOIDmode
, 0);
13358 target
= assign_386_stack_local (SImode
, 0);
13359 emit_move_insn (target
, op0
);
13360 emit_insn (gen_ldmxcsr (target
));
13363 case IX86_BUILTIN_STMXCSR
:
13364 target
= assign_386_stack_local (SImode
, 0);
13365 emit_insn (gen_stmxcsr (target
));
13366 return copy_to_mode_reg (SImode
, target
);
13368 case IX86_BUILTIN_SHUFPS
:
13369 case IX86_BUILTIN_SHUFPD
:
13370 icode
= (fcode
== IX86_BUILTIN_SHUFPS
13371 ? CODE_FOR_sse_shufps
13372 : CODE_FOR_sse2_shufpd
);
13373 arg0
= TREE_VALUE (arglist
);
13374 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13375 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13376 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13377 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13378 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13379 tmode
= insn_data
[icode
].operand
[0].mode
;
13380 mode0
= insn_data
[icode
].operand
[1].mode
;
13381 mode1
= insn_data
[icode
].operand
[2].mode
;
13382 mode2
= insn_data
[icode
].operand
[3].mode
;
13384 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13385 op0
= copy_to_mode_reg (mode0
, op0
);
13386 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13387 op1
= copy_to_mode_reg (mode1
, op1
);
13388 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
13390 /* @@@ better error message */
13391 error ("mask must be an immediate");
13392 return gen_reg_rtx (tmode
);
13395 || GET_MODE (target
) != tmode
13396 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13397 target
= gen_reg_rtx (tmode
);
13398 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
13404 case IX86_BUILTIN_PSHUFW
:
13405 case IX86_BUILTIN_PSHUFD
:
13406 case IX86_BUILTIN_PSHUFHW
:
13407 case IX86_BUILTIN_PSHUFLW
:
13408 icode
= ( fcode
== IX86_BUILTIN_PSHUFHW
? CODE_FOR_sse2_pshufhw
13409 : fcode
== IX86_BUILTIN_PSHUFLW
? CODE_FOR_sse2_pshuflw
13410 : fcode
== IX86_BUILTIN_PSHUFD
? CODE_FOR_sse2_pshufd
13411 : CODE_FOR_mmx_pshufw
);
13412 arg0
= TREE_VALUE (arglist
);
13413 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13414 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13415 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13416 tmode
= insn_data
[icode
].operand
[0].mode
;
13417 mode1
= insn_data
[icode
].operand
[1].mode
;
13418 mode2
= insn_data
[icode
].operand
[2].mode
;
13420 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
13421 op0
= copy_to_mode_reg (mode1
, op0
);
13422 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
13424 /* @@@ better error message */
13425 error ("mask must be an immediate");
13429 || GET_MODE (target
) != tmode
13430 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13431 target
= gen_reg_rtx (tmode
);
13432 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
13438 case IX86_BUILTIN_PSLLDQI128
:
13439 case IX86_BUILTIN_PSRLDQI128
:
13440 icode
= ( fcode
== IX86_BUILTIN_PSLLDQI128
? CODE_FOR_sse2_ashlti3
13441 : CODE_FOR_sse2_lshrti3
);
13442 arg0
= TREE_VALUE (arglist
);
13443 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13444 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13445 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13446 tmode
= insn_data
[icode
].operand
[0].mode
;
13447 mode1
= insn_data
[icode
].operand
[1].mode
;
13448 mode2
= insn_data
[icode
].operand
[2].mode
;
13450 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode1
))
13452 op0
= copy_to_reg (op0
);
13453 op0
= simplify_gen_subreg (mode1
, op0
, GET_MODE (op0
), 0);
13455 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode2
))
13457 error ("shift must be an immediate");
13460 target
= gen_reg_rtx (V2DImode
);
13461 pat
= GEN_FCN (icode
) (simplify_gen_subreg (tmode
, target
, V2DImode
, 0), op0
, op1
);
13467 case IX86_BUILTIN_FEMMS
:
13468 emit_insn (gen_femms ());
13471 case IX86_BUILTIN_PAVGUSB
:
13472 return ix86_expand_binop_builtin (CODE_FOR_pavgusb
, arglist
, target
);
13474 case IX86_BUILTIN_PF2ID
:
13475 return ix86_expand_unop_builtin (CODE_FOR_pf2id
, arglist
, target
, 0);
13477 case IX86_BUILTIN_PFACC
:
13478 return ix86_expand_binop_builtin (CODE_FOR_pfacc
, arglist
, target
);
13480 case IX86_BUILTIN_PFADD
:
13481 return ix86_expand_binop_builtin (CODE_FOR_addv2sf3
, arglist
, target
);
13483 case IX86_BUILTIN_PFCMPEQ
:
13484 return ix86_expand_binop_builtin (CODE_FOR_eqv2sf3
, arglist
, target
);
13486 case IX86_BUILTIN_PFCMPGE
:
13487 return ix86_expand_binop_builtin (CODE_FOR_gev2sf3
, arglist
, target
);
13489 case IX86_BUILTIN_PFCMPGT
:
13490 return ix86_expand_binop_builtin (CODE_FOR_gtv2sf3
, arglist
, target
);
13492 case IX86_BUILTIN_PFMAX
:
13493 return ix86_expand_binop_builtin (CODE_FOR_pfmaxv2sf3
, arglist
, target
);
13495 case IX86_BUILTIN_PFMIN
:
13496 return ix86_expand_binop_builtin (CODE_FOR_pfminv2sf3
, arglist
, target
);
13498 case IX86_BUILTIN_PFMUL
:
13499 return ix86_expand_binop_builtin (CODE_FOR_mulv2sf3
, arglist
, target
);
13501 case IX86_BUILTIN_PFRCP
:
13502 return ix86_expand_unop_builtin (CODE_FOR_pfrcpv2sf2
, arglist
, target
, 0);
13504 case IX86_BUILTIN_PFRCPIT1
:
13505 return ix86_expand_binop_builtin (CODE_FOR_pfrcpit1v2sf3
, arglist
, target
);
13507 case IX86_BUILTIN_PFRCPIT2
:
13508 return ix86_expand_binop_builtin (CODE_FOR_pfrcpit2v2sf3
, arglist
, target
);
13510 case IX86_BUILTIN_PFRSQIT1
:
13511 return ix86_expand_binop_builtin (CODE_FOR_pfrsqit1v2sf3
, arglist
, target
);
13513 case IX86_BUILTIN_PFRSQRT
:
13514 return ix86_expand_unop_builtin (CODE_FOR_pfrsqrtv2sf2
, arglist
, target
, 0);
13516 case IX86_BUILTIN_PFSUB
:
13517 return ix86_expand_binop_builtin (CODE_FOR_subv2sf3
, arglist
, target
);
13519 case IX86_BUILTIN_PFSUBR
:
13520 return ix86_expand_binop_builtin (CODE_FOR_subrv2sf3
, arglist
, target
);
13522 case IX86_BUILTIN_PI2FD
:
13523 return ix86_expand_unop_builtin (CODE_FOR_floatv2si2
, arglist
, target
, 0);
13525 case IX86_BUILTIN_PMULHRW
:
13526 return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3
, arglist
, target
);
13528 case IX86_BUILTIN_PF2IW
:
13529 return ix86_expand_unop_builtin (CODE_FOR_pf2iw
, arglist
, target
, 0);
13531 case IX86_BUILTIN_PFNACC
:
13532 return ix86_expand_binop_builtin (CODE_FOR_pfnacc
, arglist
, target
);
13534 case IX86_BUILTIN_PFPNACC
:
13535 return ix86_expand_binop_builtin (CODE_FOR_pfpnacc
, arglist
, target
);
13537 case IX86_BUILTIN_PI2FW
:
13538 return ix86_expand_unop_builtin (CODE_FOR_pi2fw
, arglist
, target
, 0);
13540 case IX86_BUILTIN_PSWAPDSI
:
13541 return ix86_expand_unop_builtin (CODE_FOR_pswapdv2si2
, arglist
, target
, 0);
13543 case IX86_BUILTIN_PSWAPDSF
:
13544 return ix86_expand_unop_builtin (CODE_FOR_pswapdv2sf2
, arglist
, target
, 0);
13546 case IX86_BUILTIN_SSE_ZERO
:
13547 target
= gen_reg_rtx (V4SFmode
);
13548 emit_insn (gen_sse_clrv4sf (target
, CONST0_RTX (V4SFmode
)));
13551 case IX86_BUILTIN_MMX_ZERO
:
13552 target
= gen_reg_rtx (DImode
);
13553 emit_insn (gen_mmx_clrdi (target
));
13556 case IX86_BUILTIN_CLRTI
:
13557 target
= gen_reg_rtx (V2DImode
);
13558 emit_insn (gen_sse2_clrti (simplify_gen_subreg (TImode
, target
, V2DImode
, 0)));
13562 case IX86_BUILTIN_SQRTSD
:
13563 return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv2df2
, arglist
, target
);
13564 case IX86_BUILTIN_LOADAPD
:
13565 return ix86_expand_unop_builtin (CODE_FOR_sse2_movapd
, arglist
, target
, 1);
13566 case IX86_BUILTIN_LOADUPD
:
13567 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd
, arglist
, target
, 1);
13569 case IX86_BUILTIN_STOREAPD
:
13570 return ix86_expand_store_builtin (CODE_FOR_sse2_movapd
, arglist
);
13571 case IX86_BUILTIN_STOREUPD
:
13572 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd
, arglist
);
13574 case IX86_BUILTIN_LOADSD
:
13575 return ix86_expand_unop_builtin (CODE_FOR_sse2_loadsd
, arglist
, target
, 1);
13577 case IX86_BUILTIN_STORESD
:
13578 return ix86_expand_store_builtin (CODE_FOR_sse2_storesd
, arglist
);
13580 case IX86_BUILTIN_SETPD1
:
13581 target
= assign_386_stack_local (DFmode
, 0);
13582 arg0
= TREE_VALUE (arglist
);
13583 emit_move_insn (adjust_address (target
, DFmode
, 0),
13584 expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
13585 op0
= gen_reg_rtx (V2DFmode
);
13586 emit_insn (gen_sse2_loadsd (op0
, adjust_address (target
, V2DFmode
, 0)));
13587 emit_insn (gen_sse2_shufpd (op0
, op0
, op0
, const0_rtx
));
13590 case IX86_BUILTIN_SETPD
:
13591 target
= assign_386_stack_local (V2DFmode
, 0);
13592 arg0
= TREE_VALUE (arglist
);
13593 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13594 emit_move_insn (adjust_address (target
, DFmode
, 0),
13595 expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0));
13596 emit_move_insn (adjust_address (target
, DFmode
, 8),
13597 expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0));
13598 op0
= gen_reg_rtx (V2DFmode
);
13599 emit_insn (gen_sse2_movapd (op0
, target
));
13602 case IX86_BUILTIN_LOADRPD
:
13603 target
= ix86_expand_unop_builtin (CODE_FOR_sse2_movapd
, arglist
,
13604 gen_reg_rtx (V2DFmode
), 1);
13605 emit_insn (gen_sse2_shufpd (target
, target
, target
, const1_rtx
));
13608 case IX86_BUILTIN_LOADPD1
:
13609 target
= ix86_expand_unop_builtin (CODE_FOR_sse2_loadsd
, arglist
,
13610 gen_reg_rtx (V2DFmode
), 1);
13611 emit_insn (gen_sse2_shufpd (target
, target
, target
, const0_rtx
));
13614 case IX86_BUILTIN_STOREPD1
:
13615 return ix86_expand_store_builtin (CODE_FOR_sse2_movapd
, arglist
);
13616 case IX86_BUILTIN_STORERPD
:
13617 return ix86_expand_store_builtin (CODE_FOR_sse2_movapd
, arglist
);
13619 case IX86_BUILTIN_CLRPD
:
13620 target
= gen_reg_rtx (V2DFmode
);
13621 emit_insn (gen_sse_clrv2df (target
));
13624 case IX86_BUILTIN_MFENCE
:
13625 emit_insn (gen_sse2_mfence ());
13627 case IX86_BUILTIN_LFENCE
:
13628 emit_insn (gen_sse2_lfence ());
13631 case IX86_BUILTIN_CLFLUSH
:
13632 arg0
= TREE_VALUE (arglist
);
13633 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13634 icode
= CODE_FOR_sse2_clflush
;
13635 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, Pmode
))
13636 op0
= copy_to_mode_reg (Pmode
, op0
);
13638 emit_insn (gen_sse2_clflush (op0
));
13641 case IX86_BUILTIN_MOVNTPD
:
13642 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df
, arglist
);
13643 case IX86_BUILTIN_MOVNTDQ
:
13644 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di
, arglist
);
13645 case IX86_BUILTIN_MOVNTI
:
13646 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi
, arglist
);
13648 case IX86_BUILTIN_LOADDQA
:
13649 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqa
, arglist
, target
, 1);
13650 case IX86_BUILTIN_LOADDQU
:
13651 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu
, arglist
, target
, 1);
13652 case IX86_BUILTIN_LOADD
:
13653 return ix86_expand_unop_builtin (CODE_FOR_sse2_loadd
, arglist
, target
, 1);
13655 case IX86_BUILTIN_STOREDQA
:
13656 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqa
, arglist
);
13657 case IX86_BUILTIN_STOREDQU
:
13658 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu
, arglist
);
13659 case IX86_BUILTIN_STORED
:
13660 return ix86_expand_store_builtin (CODE_FOR_sse2_stored
, arglist
);
13662 case IX86_BUILTIN_MONITOR
:
13663 arg0
= TREE_VALUE (arglist
);
13664 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13665 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
13666 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13667 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13668 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, 0);
13670 op0
= copy_to_mode_reg (SImode
, op0
);
13672 op1
= copy_to_mode_reg (SImode
, op1
);
13674 op2
= copy_to_mode_reg (SImode
, op2
);
13675 emit_insn (gen_monitor (op0
, op1
, op2
));
13678 case IX86_BUILTIN_MWAIT
:
13679 arg0
= TREE_VALUE (arglist
);
13680 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
13681 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
13682 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, 0);
13684 op0
= copy_to_mode_reg (SImode
, op0
);
13686 op1
= copy_to_mode_reg (SImode
, op1
);
13687 emit_insn (gen_mwait (op0
, op1
));
13690 case IX86_BUILTIN_LOADDDUP
:
13691 return ix86_expand_unop_builtin (CODE_FOR_loadddup
, arglist
, target
, 1);
13693 case IX86_BUILTIN_LDDQU
:
13694 return ix86_expand_unop_builtin (CODE_FOR_lddqu
, arglist
, target
,
13701 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13702 if (d
->code
== fcode
)
13704 /* Compares are treated specially. */
13705 if (d
->icode
== CODE_FOR_maskcmpv4sf3
13706 || d
->icode
== CODE_FOR_vmmaskcmpv4sf3
13707 || d
->icode
== CODE_FOR_maskncmpv4sf3
13708 || d
->icode
== CODE_FOR_vmmaskncmpv4sf3
13709 || d
->icode
== CODE_FOR_maskcmpv2df3
13710 || d
->icode
== CODE_FOR_vmmaskcmpv2df3
13711 || d
->icode
== CODE_FOR_maskncmpv2df3
13712 || d
->icode
== CODE_FOR_vmmaskncmpv2df3
)
13713 return ix86_expand_sse_compare (d
, arglist
, target
);
13715 return ix86_expand_binop_builtin (d
->icode
, arglist
, target
);
13718 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13719 if (d
->code
== fcode
)
13720 return ix86_expand_unop_builtin (d
->icode
, arglist
, target
, 0);
13722 for (i
= 0, d
= bdesc_comi
; i
< ARRAY_SIZE (bdesc_comi
); i
++, d
++)
13723 if (d
->code
== fcode
)
13724 return ix86_expand_sse_comi (d
, arglist
, target
);
13726 /* @@@ Should really do something sensible here. */
13730 /* Store OPERAND to the memory after reload is completed. This means
13731 that we can't easily use assign_stack_local. */
13733 ix86_force_to_memory (enum machine_mode mode
, rtx operand
)
13736 if (!reload_completed
)
13738 if (TARGET_RED_ZONE
)
13740 result
= gen_rtx_MEM (mode
,
13741 gen_rtx_PLUS (Pmode
,
13743 GEN_INT (-RED_ZONE_SIZE
)));
13744 emit_move_insn (result
, operand
);
13746 else if (!TARGET_RED_ZONE
&& TARGET_64BIT
)
13752 operand
= gen_lowpart (DImode
, operand
);
13756 gen_rtx_SET (VOIDmode
,
13757 gen_rtx_MEM (DImode
,
13758 gen_rtx_PRE_DEC (DImode
,
13759 stack_pointer_rtx
)),
13765 result
= gen_rtx_MEM (mode
, stack_pointer_rtx
);
13774 split_di (&operand
, 1, operands
, operands
+ 1);
13776 gen_rtx_SET (VOIDmode
,
13777 gen_rtx_MEM (SImode
,
13778 gen_rtx_PRE_DEC (Pmode
,
13779 stack_pointer_rtx
)),
13782 gen_rtx_SET (VOIDmode
,
13783 gen_rtx_MEM (SImode
,
13784 gen_rtx_PRE_DEC (Pmode
,
13785 stack_pointer_rtx
)),
13790 /* It is better to store HImodes as SImodes. */
13791 if (!TARGET_PARTIAL_REG_STALL
)
13792 operand
= gen_lowpart (SImode
, operand
);
13796 gen_rtx_SET (VOIDmode
,
13797 gen_rtx_MEM (GET_MODE (operand
),
13798 gen_rtx_PRE_DEC (SImode
,
13799 stack_pointer_rtx
)),
13805 result
= gen_rtx_MEM (mode
, stack_pointer_rtx
);
13810 /* Free operand from the memory. */
13812 ix86_free_from_memory (enum machine_mode mode
)
13814 if (!TARGET_RED_ZONE
)
13818 if (mode
== DImode
|| TARGET_64BIT
)
13820 else if (mode
== HImode
&& TARGET_PARTIAL_REG_STALL
)
13824 /* Use LEA to deallocate stack space. In peephole2 it will be converted
13825 to pop or add instruction if registers are available. */
13826 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
13827 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
13832 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
13833 QImode must go into class Q_REGS.
13834 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
13835 movdf to do mem-to-mem moves through integer regs. */
13837 ix86_preferred_reload_class (rtx x
, enum reg_class
class)
13839 if (GET_CODE (x
) == CONST_VECTOR
&& x
!= CONST0_RTX (GET_MODE (x
)))
13841 if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != VOIDmode
)
13843 /* SSE can't load any constant directly yet. */
13844 if (SSE_CLASS_P (class))
13846 /* Floats can load 0 and 1. */
13847 if (MAYBE_FLOAT_CLASS_P (class) && standard_80387_constant_p (x
))
13849 /* Limit class to non-SSE. Use GENERAL_REGS if possible. */
13850 if (MAYBE_SSE_CLASS_P (class))
13851 return (reg_class_subset_p (class, GENERAL_REGS
)
13852 ? GENERAL_REGS
: FLOAT_REGS
);
13856 /* General regs can load everything. */
13857 if (reg_class_subset_p (class, GENERAL_REGS
))
13858 return GENERAL_REGS
;
13859 /* In case we haven't resolved FLOAT or SSE yet, give up. */
13860 if (MAYBE_FLOAT_CLASS_P (class) || MAYBE_SSE_CLASS_P (class))
13863 if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x
))
13865 if (GET_MODE (x
) == QImode
&& ! reg_class_subset_p (class, Q_REGS
))
13870 /* If we are copying between general and FP registers, we need a memory
13871 location. The same is true for SSE and MMX registers.
13873 The macro can't work reliably when one of the CLASSES is class containing
13874 registers from multiple units (SSE, MMX, integer). We avoid this by never
13875 combining those units in single alternative in the machine description.
13876 Ensure that this constraint holds to avoid unexpected surprises.
13878 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
13879 enforce these sanity checks. */
13881 ix86_secondary_memory_needed (enum reg_class class1
, enum reg_class class2
,
13882 enum machine_mode mode
, int strict
)
13884 if (MAYBE_FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class1
)
13885 || MAYBE_FLOAT_CLASS_P (class2
) != FLOAT_CLASS_P (class2
)
13886 || MAYBE_SSE_CLASS_P (class1
) != SSE_CLASS_P (class1
)
13887 || MAYBE_SSE_CLASS_P (class2
) != SSE_CLASS_P (class2
)
13888 || MAYBE_MMX_CLASS_P (class1
) != MMX_CLASS_P (class1
)
13889 || MAYBE_MMX_CLASS_P (class2
) != MMX_CLASS_P (class2
))
13896 return (FLOAT_CLASS_P (class1
) != FLOAT_CLASS_P (class2
)
13897 || ((SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
)
13898 || MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
))
13899 && ((mode
!= SImode
&& (mode
!= DImode
|| !TARGET_64BIT
))
13900 || (!TARGET_INTER_UNIT_MOVES
&& !optimize_size
))));
13902 /* Return the cost of moving data from a register in class CLASS1 to
13903 one in class CLASS2.
13905 It is not required that the cost always equal 2 when FROM is the same as TO;
13906 on some machines it is expensive to move between registers if they are not
13907 general registers. */
13909 ix86_register_move_cost (enum machine_mode mode
, enum reg_class class1
,
13910 enum reg_class class2
)
13912 /* In case we require secondary memory, compute cost of the store followed
13913 by load. In order to avoid bad register allocation choices, we need
13914 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
13916 if (ix86_secondary_memory_needed (class1
, class2
, mode
, 0))
13920 cost
+= MAX (MEMORY_MOVE_COST (mode
, class1
, 0),
13921 MEMORY_MOVE_COST (mode
, class1
, 1));
13922 cost
+= MAX (MEMORY_MOVE_COST (mode
, class2
, 0),
13923 MEMORY_MOVE_COST (mode
, class2
, 1));
13925 /* In case of copying from general_purpose_register we may emit multiple
13926 stores followed by single load causing memory size mismatch stall.
13927 Count this as arbitrarily high cost of 20. */
13928 if (CLASS_MAX_NREGS (class1
, mode
) > CLASS_MAX_NREGS (class2
, mode
))
13931 /* In the case of FP/MMX moves, the registers actually overlap, and we
13932 have to switch modes in order to treat them differently. */
13933 if ((MMX_CLASS_P (class1
) && MAYBE_FLOAT_CLASS_P (class2
))
13934 || (MMX_CLASS_P (class2
) && MAYBE_FLOAT_CLASS_P (class1
)))
13940 /* Moves between SSE/MMX and integer unit are expensive. */
13941 if (MMX_CLASS_P (class1
) != MMX_CLASS_P (class2
)
13942 || SSE_CLASS_P (class1
) != SSE_CLASS_P (class2
))
13943 return ix86_cost
->mmxsse_to_integer
;
13944 if (MAYBE_FLOAT_CLASS_P (class1
))
13945 return ix86_cost
->fp_move
;
13946 if (MAYBE_SSE_CLASS_P (class1
))
13947 return ix86_cost
->sse_move
;
13948 if (MAYBE_MMX_CLASS_P (class1
))
13949 return ix86_cost
->mmx_move
;
13953 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
13955 ix86_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
13957 /* Flags and only flags can only hold CCmode values. */
13958 if (CC_REGNO_P (regno
))
13959 return GET_MODE_CLASS (mode
) == MODE_CC
;
13960 if (GET_MODE_CLASS (mode
) == MODE_CC
13961 || GET_MODE_CLASS (mode
) == MODE_RANDOM
13962 || GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
13964 if (FP_REGNO_P (regno
))
13965 return VALID_FP_MODE_P (mode
);
13966 if (SSE_REGNO_P (regno
))
13967 return (TARGET_SSE
? VALID_SSE_REG_MODE (mode
) : 0);
13968 if (MMX_REGNO_P (regno
))
13970 ? VALID_MMX_REG_MODE (mode
) || VALID_MMX_REG_MODE_3DNOW (mode
) : 0);
13971 /* We handle both integer and floats in the general purpose registers.
13972 In future we should be able to handle vector modes as well. */
13973 if (!VALID_INT_MODE_P (mode
) && !VALID_FP_MODE_P (mode
))
13975 /* Take care for QImode values - they can be in non-QI regs, but then
13976 they do cause partial register stalls. */
13977 if (regno
< 4 || mode
!= QImode
|| TARGET_64BIT
)
13979 return reload_in_progress
|| reload_completed
|| !TARGET_PARTIAL_REG_STALL
;
13982 /* Return the cost of moving data of mode M between a
13983 register and memory. A value of 2 is the default; this cost is
13984 relative to those in `REGISTER_MOVE_COST'.
13986 If moving between registers and memory is more expensive than
13987 between two registers, you should define this macro to express the
13990 Model also increased moving costs of QImode registers in non
13994 ix86_memory_move_cost (enum machine_mode mode
, enum reg_class
class, int in
)
13996 if (FLOAT_CLASS_P (class))
14013 return in
? ix86_cost
->fp_load
[index
] : ix86_cost
->fp_store
[index
];
14015 if (SSE_CLASS_P (class))
14018 switch (GET_MODE_SIZE (mode
))
14032 return in
? ix86_cost
->sse_load
[index
] : ix86_cost
->sse_store
[index
];
14034 if (MMX_CLASS_P (class))
14037 switch (GET_MODE_SIZE (mode
))
14048 return in
? ix86_cost
->mmx_load
[index
] : ix86_cost
->mmx_store
[index
];
14050 switch (GET_MODE_SIZE (mode
))
14054 return (Q_CLASS_P (class) ? ix86_cost
->int_load
[0]
14055 : ix86_cost
->movzbl_load
);
14057 return (Q_CLASS_P (class) ? ix86_cost
->int_store
[0]
14058 : ix86_cost
->int_store
[0] + 4);
14061 return in
? ix86_cost
->int_load
[1] : ix86_cost
->int_store
[1];
14063 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
14064 if (mode
== TFmode
)
14066 return ((in
? ix86_cost
->int_load
[2] : ix86_cost
->int_store
[2])
14067 * (((int) GET_MODE_SIZE (mode
)
14068 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
));
14072 /* Compute a (partial) cost for rtx X. Return true if the complete
14073 cost has been computed, and false if subexpressions should be
14074 scanned. In either case, *TOTAL contains the cost result. */
14077 ix86_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
14079 enum machine_mode mode
= GET_MODE (x
);
14087 if (TARGET_64BIT
&& !x86_64_immediate_operand (x
, VOIDmode
))
14089 else if (TARGET_64BIT
&& !x86_64_zext_immediate_operand (x
, VOIDmode
))
14091 else if (flag_pic
&& SYMBOLIC_CONST (x
)
14093 || (!GET_CODE (x
) != LABEL_REF
14094 && (GET_CODE (x
) != SYMBOL_REF
14095 || !SYMBOL_REF_LOCAL_P (x
)))))
14102 if (mode
== VOIDmode
)
14105 switch (standard_80387_constant_p (x
))
14110 default: /* Other constants */
14115 /* Start with (MEM (SYMBOL_REF)), since that's where
14116 it'll probably end up. Add a penalty for size. */
14117 *total
= (COSTS_N_INSNS (1)
14118 + (flag_pic
!= 0 && !TARGET_64BIT
)
14119 + (mode
== SFmode
? 0 : mode
== DFmode
? 1 : 2));
14125 /* The zero extensions is often completely free on x86_64, so make
14126 it as cheap as possible. */
14127 if (TARGET_64BIT
&& mode
== DImode
14128 && GET_MODE (XEXP (x
, 0)) == SImode
)
14130 else if (TARGET_ZERO_EXTEND_WITH_AND
)
14131 *total
= COSTS_N_INSNS (ix86_cost
->add
);
14133 *total
= COSTS_N_INSNS (ix86_cost
->movzx
);
14137 *total
= COSTS_N_INSNS (ix86_cost
->movsx
);
14141 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
14142 && (GET_MODE (XEXP (x
, 0)) != DImode
|| TARGET_64BIT
))
14144 HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
14147 *total
= COSTS_N_INSNS (ix86_cost
->add
);
14150 if ((value
== 2 || value
== 3)
14151 && ix86_cost
->lea
<= ix86_cost
->shift_const
)
14153 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14163 if (!TARGET_64BIT
&& GET_MODE (XEXP (x
, 0)) == DImode
)
14165 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
14167 if (INTVAL (XEXP (x
, 1)) > 32)
14168 *total
= COSTS_N_INSNS(ix86_cost
->shift_const
+ 2);
14170 *total
= COSTS_N_INSNS(ix86_cost
->shift_const
* 2);
14174 if (GET_CODE (XEXP (x
, 1)) == AND
)
14175 *total
= COSTS_N_INSNS(ix86_cost
->shift_var
* 2);
14177 *total
= COSTS_N_INSNS(ix86_cost
->shift_var
* 6 + 2);
14182 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
14183 *total
= COSTS_N_INSNS (ix86_cost
->shift_const
);
14185 *total
= COSTS_N_INSNS (ix86_cost
->shift_var
);
14190 if (FLOAT_MODE_P (mode
))
14192 *total
= COSTS_N_INSNS (ix86_cost
->fmul
);
14197 rtx op0
= XEXP (x
, 0);
14198 rtx op1
= XEXP (x
, 1);
14200 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
14202 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
14203 for (nbits
= 0; value
!= 0; value
&= value
- 1)
14207 /* This is arbitrary. */
14210 /* Compute costs correctly for widening multiplication. */
14211 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op1
) == ZERO_EXTEND
)
14212 && GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0))) * 2
14213 == GET_MODE_SIZE (mode
))
14215 int is_mulwiden
= 0;
14216 enum machine_mode inner_mode
= GET_MODE (op0
);
14218 if (GET_CODE (op0
) == GET_CODE (op1
))
14219 is_mulwiden
= 1, op1
= XEXP (op1
, 0);
14220 else if (GET_CODE (op1
) == CONST_INT
)
14222 if (GET_CODE (op0
) == SIGN_EXTEND
)
14223 is_mulwiden
= trunc_int_for_mode (INTVAL (op1
), inner_mode
)
14226 is_mulwiden
= !(INTVAL (op1
) & ~GET_MODE_MASK (inner_mode
));
14230 op0
= XEXP (op0
, 0), mode
= GET_MODE (op0
);
14233 *total
= COSTS_N_INSNS (ix86_cost
->mult_init
[MODE_INDEX (mode
)]
14234 + nbits
* ix86_cost
->mult_bit
)
14235 + rtx_cost (op0
, outer_code
) + rtx_cost (op1
, outer_code
);
14244 if (FLOAT_MODE_P (mode
))
14245 *total
= COSTS_N_INSNS (ix86_cost
->fdiv
);
14247 *total
= COSTS_N_INSNS (ix86_cost
->divide
[MODE_INDEX (mode
)]);
14251 if (FLOAT_MODE_P (mode
))
14252 *total
= COSTS_N_INSNS (ix86_cost
->fadd
);
14253 else if (GET_MODE_CLASS (mode
) == MODE_INT
14254 && GET_MODE_BITSIZE (mode
) <= GET_MODE_BITSIZE (Pmode
))
14256 if (GET_CODE (XEXP (x
, 0)) == PLUS
14257 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
14258 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
14259 && CONSTANT_P (XEXP (x
, 1)))
14261 HOST_WIDE_INT val
= INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1));
14262 if (val
== 2 || val
== 4 || val
== 8)
14264 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14265 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 1), outer_code
);
14266 *total
+= rtx_cost (XEXP (XEXP (XEXP (x
, 0), 0), 0),
14268 *total
+= rtx_cost (XEXP (x
, 1), outer_code
);
14272 else if (GET_CODE (XEXP (x
, 0)) == MULT
14273 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
14275 HOST_WIDE_INT val
= INTVAL (XEXP (XEXP (x
, 0), 1));
14276 if (val
== 2 || val
== 4 || val
== 8)
14278 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14279 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
);
14280 *total
+= rtx_cost (XEXP (x
, 1), outer_code
);
14284 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
14286 *total
= COSTS_N_INSNS (ix86_cost
->lea
);
14287 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
);
14288 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 1), outer_code
);
14289 *total
+= rtx_cost (XEXP (x
, 1), outer_code
);
14296 if (FLOAT_MODE_P (mode
))
14298 *total
= COSTS_N_INSNS (ix86_cost
->fadd
);
14306 if (!TARGET_64BIT
&& mode
== DImode
)
14308 *total
= (COSTS_N_INSNS (ix86_cost
->add
) * 2
14309 + (rtx_cost (XEXP (x
, 0), outer_code
)
14310 << (GET_MODE (XEXP (x
, 0)) != DImode
))
14311 + (rtx_cost (XEXP (x
, 1), outer_code
)
14312 << (GET_MODE (XEXP (x
, 1)) != DImode
)));
14318 if (FLOAT_MODE_P (mode
))
14320 *total
= COSTS_N_INSNS (ix86_cost
->fchs
);
14326 if (!TARGET_64BIT
&& mode
== DImode
)
14327 *total
= COSTS_N_INSNS (ix86_cost
->add
* 2);
14329 *total
= COSTS_N_INSNS (ix86_cost
->add
);
14333 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTRACT
14334 && XEXP (XEXP (x
, 0), 1) == const1_rtx
14335 && GET_CODE (XEXP (XEXP (x
, 0), 2)) == CONST_INT
14336 && XEXP (x
, 1) == const0_rtx
)
14338 /* This kind of construct is implemented using test[bwl].
14339 Treat it as if we had an AND. */
14340 *total
= (COSTS_N_INSNS (ix86_cost
->add
)
14341 + rtx_cost (XEXP (XEXP (x
, 0), 0), outer_code
)
14342 + rtx_cost (const1_rtx
, outer_code
));
14348 if (!TARGET_SSE_MATH
|| !VALID_SSE_REG_MODE (mode
))
14353 if (FLOAT_MODE_P (mode
))
14354 *total
= COSTS_N_INSNS (ix86_cost
->fabs
);
14358 if (FLOAT_MODE_P (mode
))
14359 *total
= COSTS_N_INSNS (ix86_cost
->fsqrt
);
14363 if (XINT (x
, 1) == UNSPEC_TP
)
14372 #if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION)
14374 ix86_svr3_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
14377 fputs ("\tpushl $", asm_out_file
);
14378 assemble_name (asm_out_file
, XSTR (symbol
, 0));
14379 fputc ('\n', asm_out_file
);
14385 static int current_machopic_label_num
;
14387 /* Given a symbol name and its associated stub, write out the
14388 definition of the stub. */
14391 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
14393 unsigned int length
;
14394 char *binder_name
, *symbol_name
, lazy_ptr_name
[32];
14395 int label
= ++current_machopic_label_num
;
14397 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
14398 symb
= (*targetm
.strip_name_encoding
) (symb
);
14400 length
= strlen (stub
);
14401 binder_name
= alloca (length
+ 32);
14402 GEN_BINDER_NAME_FOR_STUB (binder_name
, stub
, length
);
14404 length
= strlen (symb
);
14405 symbol_name
= alloca (length
+ 32);
14406 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
14408 sprintf (lazy_ptr_name
, "L%d$lz", label
);
14411 machopic_picsymbol_stub_section ();
14413 machopic_symbol_stub_section ();
14415 fprintf (file
, "%s:\n", stub
);
14416 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
14420 fprintf (file
, "\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n", label
, label
);
14421 fprintf (file
, "\tmovl %s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name
, label
);
14422 fprintf (file
, "\tjmp %%edx\n");
14425 fprintf (file
, "\tjmp *%s\n", lazy_ptr_name
);
14427 fprintf (file
, "%s:\n", binder_name
);
14431 fprintf (file
, "\tlea %s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name
, label
);
14432 fprintf (file
, "\tpushl %%eax\n");
14435 fprintf (file
, "\t pushl $%s\n", lazy_ptr_name
);
14437 fprintf (file
, "\tjmp dyld_stub_binding_helper\n");
14439 machopic_lazy_symbol_ptr_section ();
14440 fprintf (file
, "%s:\n", lazy_ptr_name
);
14441 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
14442 fprintf (file
, "\t.long %s\n", binder_name
);
14444 #endif /* TARGET_MACHO */
14446 /* Order the registers for register allocator. */
14449 x86_order_regs_for_local_alloc (void)
14454 /* First allocate the local general purpose registers. */
14455 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
14456 if (GENERAL_REGNO_P (i
) && call_used_regs
[i
])
14457 reg_alloc_order
[pos
++] = i
;
14459 /* Global general purpose registers. */
14460 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
14461 if (GENERAL_REGNO_P (i
) && !call_used_regs
[i
])
14462 reg_alloc_order
[pos
++] = i
;
14464 /* x87 registers come first in case we are doing FP math
14466 if (!TARGET_SSE_MATH
)
14467 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
14468 reg_alloc_order
[pos
++] = i
;
14470 /* SSE registers. */
14471 for (i
= FIRST_SSE_REG
; i
<= LAST_SSE_REG
; i
++)
14472 reg_alloc_order
[pos
++] = i
;
14473 for (i
= FIRST_REX_SSE_REG
; i
<= LAST_REX_SSE_REG
; i
++)
14474 reg_alloc_order
[pos
++] = i
;
14476 /* x87 registers. */
14477 if (TARGET_SSE_MATH
)
14478 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
14479 reg_alloc_order
[pos
++] = i
;
14481 for (i
= FIRST_MMX_REG
; i
<= LAST_MMX_REG
; i
++)
14482 reg_alloc_order
[pos
++] = i
;
14484 /* Initialize the rest of array as we do not allocate some registers
14486 while (pos
< FIRST_PSEUDO_REGISTER
)
14487 reg_alloc_order
[pos
++] = 0;
14490 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
14491 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
14494 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
14495 struct attribute_spec.handler. */
14497 ix86_handle_struct_attribute (tree
*node
, tree name
,
14498 tree args ATTRIBUTE_UNUSED
,
14499 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
14502 if (DECL_P (*node
))
14504 if (TREE_CODE (*node
) == TYPE_DECL
)
14505 type
= &TREE_TYPE (*node
);
14510 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
14511 || TREE_CODE (*type
) == UNION_TYPE
)))
14513 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
14514 *no_add_attrs
= true;
14517 else if ((is_attribute_p ("ms_struct", name
)
14518 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
14519 || ((is_attribute_p ("gcc_struct", name
)
14520 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
14522 warning ("%qs incompatible attribute ignored",
14523 IDENTIFIER_POINTER (name
));
14524 *no_add_attrs
= true;
14531 ix86_ms_bitfield_layout_p (tree record_type
)
14533 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
14534 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
14535 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
14538 /* Returns an expression indicating where the this parameter is
14539 located on entry to the FUNCTION. */
14542 x86_this_parameter (tree function
)
14544 tree type
= TREE_TYPE (function
);
14548 int n
= aggregate_value_p (TREE_TYPE (type
), type
) != 0;
14549 return gen_rtx_REG (DImode
, x86_64_int_parameter_registers
[n
]);
14552 if (ix86_function_regparm (type
, function
) > 0)
14556 parm
= TYPE_ARG_TYPES (type
);
14557 /* Figure out whether or not the function has a variable number of
14559 for (; parm
; parm
= TREE_CHAIN (parm
))
14560 if (TREE_VALUE (parm
) == void_type_node
)
14562 /* If not, the this parameter is in the first argument. */
14566 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type
)))
14568 return gen_rtx_REG (SImode
, regno
);
14572 if (aggregate_value_p (TREE_TYPE (type
), type
))
14573 return gen_rtx_MEM (SImode
, plus_constant (stack_pointer_rtx
, 8));
14575 return gen_rtx_MEM (SImode
, plus_constant (stack_pointer_rtx
, 4));
14578 /* Determine whether x86_output_mi_thunk can succeed. */
14581 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED
,
14582 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
14583 HOST_WIDE_INT vcall_offset
, tree function
)
14585 /* 64-bit can handle anything. */
14589 /* For 32-bit, everything's fine if we have one free register. */
14590 if (ix86_function_regparm (TREE_TYPE (function
), function
) < 3)
14593 /* Need a free register for vcall_offset. */
14597 /* Need a free register for GOT references. */
14598 if (flag_pic
&& !(*targetm
.binds_local_p
) (function
))
14601 /* Otherwise ok. */
14605 /* Output the assembler code for a thunk function. THUNK_DECL is the
14606 declaration for the thunk function itself, FUNCTION is the decl for
14607 the target function. DELTA is an immediate constant offset to be
14608 added to THIS. If VCALL_OFFSET is nonzero, the word at
14609 *(*this + vcall_offset) should be added to THIS. */
14612 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED
,
14613 tree thunk ATTRIBUTE_UNUSED
, HOST_WIDE_INT delta
,
14614 HOST_WIDE_INT vcall_offset
, tree function
)
14617 rtx
this = x86_this_parameter (function
);
14620 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
14621 pull it in now and let DELTA benefit. */
14624 else if (vcall_offset
)
14626 /* Put the this parameter into %eax. */
14628 xops
[1] = this_reg
= gen_rtx_REG (Pmode
, 0);
14629 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops
);
14632 this_reg
= NULL_RTX
;
14634 /* Adjust the this parameter by a fixed constant. */
14637 xops
[0] = GEN_INT (delta
);
14638 xops
[1] = this_reg
? this_reg
: this;
14641 if (!x86_64_general_operand (xops
[0], DImode
))
14643 tmp
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 2 /* R10 */);
14645 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops
);
14649 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops
);
14652 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops
);
14655 /* Adjust the this parameter by a value stored in the vtable. */
14659 tmp
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 2 /* R10 */);
14662 int tmp_regno
= 2 /* ECX */;
14663 if (lookup_attribute ("fastcall",
14664 TYPE_ATTRIBUTES (TREE_TYPE (function
))))
14665 tmp_regno
= 0 /* EAX */;
14666 tmp
= gen_rtx_REG (SImode
, tmp_regno
);
14669 xops
[0] = gen_rtx_MEM (Pmode
, this_reg
);
14672 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops
);
14674 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops
);
14676 /* Adjust the this parameter. */
14677 xops
[0] = gen_rtx_MEM (Pmode
, plus_constant (tmp
, vcall_offset
));
14678 if (TARGET_64BIT
&& !memory_operand (xops
[0], Pmode
))
14680 rtx tmp2
= gen_rtx_REG (DImode
, FIRST_REX_INT_REG
+ 3 /* R11 */);
14681 xops
[0] = GEN_INT (vcall_offset
);
14683 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops
);
14684 xops
[0] = gen_rtx_MEM (Pmode
, gen_rtx_PLUS (Pmode
, tmp
, tmp2
));
14686 xops
[1] = this_reg
;
14688 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops
);
14690 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops
);
14693 /* If necessary, drop THIS back to its stack slot. */
14694 if (this_reg
&& this_reg
!= this)
14696 xops
[0] = this_reg
;
14698 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops
);
14701 xops
[0] = XEXP (DECL_RTL (function
), 0);
14704 if (!flag_pic
|| (*targetm
.binds_local_p
) (function
))
14705 output_asm_insn ("jmp\t%P0", xops
);
14708 tmp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, xops
[0]), UNSPEC_GOTPCREL
);
14709 tmp
= gen_rtx_CONST (Pmode
, tmp
);
14710 tmp
= gen_rtx_MEM (QImode
, tmp
);
14712 output_asm_insn ("jmp\t%A0", xops
);
14717 if (!flag_pic
|| (*targetm
.binds_local_p
) (function
))
14718 output_asm_insn ("jmp\t%P0", xops
);
14723 rtx sym_ref
= XEXP (DECL_RTL (function
), 0);
14724 tmp
= (gen_rtx_SYMBOL_REF
14726 machopic_indirection_name (sym_ref
, /*stub_p=*/true)));
14727 tmp
= gen_rtx_MEM (QImode
, tmp
);
14729 output_asm_insn ("jmp\t%0", xops
);
14732 #endif /* TARGET_MACHO */
14734 tmp
= gen_rtx_REG (SImode
, 2 /* ECX */);
14735 output_set_got (tmp
);
14738 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops
);
14739 output_asm_insn ("jmp\t{*}%1", xops
);
14745 x86_file_start (void)
14747 default_file_start ();
14748 if (X86_FILE_START_VERSION_DIRECTIVE
)
14749 fputs ("\t.version\t\"01.01\"\n", asm_out_file
);
14750 if (X86_FILE_START_FLTUSED
)
14751 fputs ("\t.global\t__fltused\n", asm_out_file
);
14752 if (ix86_asm_dialect
== ASM_INTEL
)
14753 fputs ("\t.intel_syntax\n", asm_out_file
);
14757 x86_field_alignment (tree field
, int computed
)
14759 enum machine_mode mode
;
14760 tree type
= TREE_TYPE (field
);
14762 if (TARGET_64BIT
|| TARGET_ALIGN_DOUBLE
)
14764 mode
= TYPE_MODE (TREE_CODE (type
) == ARRAY_TYPE
14765 ? get_inner_array_type (type
) : type
);
14766 if (mode
== DFmode
|| mode
== DCmode
14767 || GET_MODE_CLASS (mode
) == MODE_INT
14768 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
14769 return MIN (32, computed
);
14773 /* Output assembler code to FILE to increment profiler label # LABELNO
14774 for profiling a function entry. */
14776 x86_function_profiler (FILE *file
, int labelno ATTRIBUTE_UNUSED
)
14781 #ifndef NO_PROFILE_COUNTERS
14782 fprintf (file
, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX
, labelno
);
14784 fprintf (file
, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME
);
14788 #ifndef NO_PROFILE_COUNTERS
14789 fprintf (file
, "\tmovq\t$%sP%d,%%r11\n", LPREFIX
, labelno
);
14791 fprintf (file
, "\tcall\t%s\n", MCOUNT_NAME
);
14795 #ifndef NO_PROFILE_COUNTERS
14796 fprintf (file
, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
14797 LPREFIX
, labelno
, PROFILE_COUNT_REGISTER
);
14799 fprintf (file
, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME
);
14803 #ifndef NO_PROFILE_COUNTERS
14804 fprintf (file
, "\tmovl\t$%sP%d,%%%s\n", LPREFIX
, labelno
,
14805 PROFILE_COUNT_REGISTER
);
14807 fprintf (file
, "\tcall\t%s\n", MCOUNT_NAME
);
14811 /* We don't have exact information about the insn sizes, but we may assume
14812 quite safely that we are informed about all 1 byte insns and memory
14813 address sizes. This is enough to eliminate unnecessary padding in
14817 min_insn_size (rtx insn
)
14821 if (!INSN_P (insn
) || !active_insn_p (insn
))
14824 /* Discard alignments we've emit and jump instructions. */
14825 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
14826 && XINT (PATTERN (insn
), 1) == UNSPECV_ALIGN
)
14828 if (GET_CODE (insn
) == JUMP_INSN
14829 && (GET_CODE (PATTERN (insn
)) == ADDR_VEC
14830 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
))
14833 /* Important case - calls are always 5 bytes.
14834 It is common to have many calls in the row. */
14835 if (GET_CODE (insn
) == CALL_INSN
14836 && symbolic_reference_mentioned_p (PATTERN (insn
))
14837 && !SIBLING_CALL_P (insn
))
14839 if (get_attr_length (insn
) <= 1)
14842 /* For normal instructions we may rely on the sizes of addresses
14843 and the presence of symbol to require 4 bytes of encoding.
14844 This is not the case for jumps where references are PC relative. */
14845 if (GET_CODE (insn
) != JUMP_INSN
)
14847 l
= get_attr_length_address (insn
);
14848 if (l
< 4 && symbolic_reference_mentioned_p (PATTERN (insn
)))
14857 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
14861 ix86_avoid_jump_misspredicts (void)
14863 rtx insn
, start
= get_insns ();
14864 int nbytes
= 0, njumps
= 0;
14867 /* Look for all minimal intervals of instructions containing 4 jumps.
14868 The intervals are bounded by START and INSN. NBYTES is the total
14869 size of instructions in the interval including INSN and not including
14870 START. When the NBYTES is smaller than 16 bytes, it is possible
14871 that the end of START and INSN ends up in the same 16byte page.
14873 The smallest offset in the page INSN can start is the case where START
14874 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
14875 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
14877 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14880 nbytes
+= min_insn_size (insn
);
14882 fprintf(dump_file
, "Insn %i estimated to %i bytes\n",
14883 INSN_UID (insn
), min_insn_size (insn
));
14884 if ((GET_CODE (insn
) == JUMP_INSN
14885 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
14886 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
14887 || GET_CODE (insn
) == CALL_INSN
)
14894 start
= NEXT_INSN (start
);
14895 if ((GET_CODE (start
) == JUMP_INSN
14896 && GET_CODE (PATTERN (start
)) != ADDR_VEC
14897 && GET_CODE (PATTERN (start
)) != ADDR_DIFF_VEC
)
14898 || GET_CODE (start
) == CALL_INSN
)
14899 njumps
--, isjump
= 1;
14902 nbytes
-= min_insn_size (start
);
14907 fprintf (dump_file
, "Interval %i to %i has %i bytes\n",
14908 INSN_UID (start
), INSN_UID (insn
), nbytes
);
14910 if (njumps
== 3 && isjump
&& nbytes
< 16)
14912 int padsize
= 15 - nbytes
+ min_insn_size (insn
);
14915 fprintf (dump_file
, "Padding insn %i by %i bytes!\n",
14916 INSN_UID (insn
), padsize
);
14917 emit_insn_before (gen_align (GEN_INT (padsize
)), insn
);
14922 /* AMD Athlon works faster
14923 when RET is not destination of conditional jump or directly preceded
14924 by other jump instruction. We avoid the penalty by inserting NOP just
14925 before the RET instructions in such cases. */
14927 ix86_pad_returns (void)
14932 FOR_EACH_EDGE (e
, ei
, EXIT_BLOCK_PTR
->preds
)
14934 basic_block bb
= e
->src
;
14935 rtx ret
= BB_END (bb
);
14937 bool replace
= false;
14939 if (GET_CODE (ret
) != JUMP_INSN
|| GET_CODE (PATTERN (ret
)) != RETURN
14940 || !maybe_hot_bb_p (bb
))
14942 for (prev
= PREV_INSN (ret
); prev
; prev
= PREV_INSN (prev
))
14943 if (active_insn_p (prev
) || GET_CODE (prev
) == CODE_LABEL
)
14945 if (prev
&& GET_CODE (prev
) == CODE_LABEL
)
14950 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14951 if (EDGE_FREQUENCY (e
) && e
->src
->index
>= 0
14952 && !(e
->flags
& EDGE_FALLTHRU
))
14957 prev
= prev_active_insn (ret
);
14959 && ((GET_CODE (prev
) == JUMP_INSN
&& any_condjump_p (prev
))
14960 || GET_CODE (prev
) == CALL_INSN
))
14962 /* Empty functions get branch mispredict even when the jump destination
14963 is not visible to us. */
14964 if (!prev
&& cfun
->function_frequency
> FUNCTION_FREQUENCY_UNLIKELY_EXECUTED
)
14969 emit_insn_before (gen_return_internal_long (), ret
);
14975 /* Implement machine specific optimizations. We implement padding of returns
14976 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
14980 if (TARGET_ATHLON_K8
&& optimize
&& !optimize_size
)
14981 ix86_pad_returns ();
14982 if (TARGET_FOUR_JUMP_LIMIT
&& optimize
&& !optimize_size
)
14983 ix86_avoid_jump_misspredicts ();
14986 /* Return nonzero when QImode register that must be represented via REX prefix
14989 x86_extended_QIreg_mentioned_p (rtx insn
)
14992 extract_insn_cached (insn
);
14993 for (i
= 0; i
< recog_data
.n_operands
; i
++)
14994 if (REG_P (recog_data
.operand
[i
])
14995 && REGNO (recog_data
.operand
[i
]) >= 4)
15000 /* Return nonzero when P points to register encoded via REX prefix.
15001 Called via for_each_rtx. */
15003 extended_reg_mentioned_1 (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
15005 unsigned int regno
;
15008 regno
= REGNO (*p
);
15009 return REX_INT_REGNO_P (regno
) || REX_SSE_REGNO_P (regno
);
15012 /* Return true when INSN mentions register that must be encoded using REX
15015 x86_extended_reg_mentioned_p (rtx insn
)
15017 return for_each_rtx (&PATTERN (insn
), extended_reg_mentioned_1
, NULL
);
15020 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
15021 optabs would emit if we didn't have TFmode patterns. */
15024 x86_emit_floatuns (rtx operands
[2])
15026 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
15027 enum machine_mode mode
, inmode
;
15029 inmode
= GET_MODE (operands
[1]);
15030 if (inmode
!= SImode
15031 && inmode
!= DImode
)
15035 in
= force_reg (inmode
, operands
[1]);
15036 mode
= GET_MODE (out
);
15037 neglab
= gen_label_rtx ();
15038 donelab
= gen_label_rtx ();
15039 i1
= gen_reg_rtx (Pmode
);
15040 f0
= gen_reg_rtx (mode
);
15042 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, Pmode
, 0, neglab
);
15044 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
15045 emit_jump_insn (gen_jump (donelab
));
15048 emit_label (neglab
);
15050 i0
= expand_simple_binop (Pmode
, LSHIFTRT
, in
, const1_rtx
, NULL
, 1, OPTAB_DIRECT
);
15051 i1
= expand_simple_binop (Pmode
, AND
, in
, const1_rtx
, NULL
, 1, OPTAB_DIRECT
);
15052 i0
= expand_simple_binop (Pmode
, IOR
, i0
, i1
, i0
, 1, OPTAB_DIRECT
);
15053 expand_float (f0
, i0
, 0);
15054 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
15056 emit_label (donelab
);
15059 /* Initialize vector TARGET via VALS. */
15061 ix86_expand_vector_init (rtx target
, rtx vals
)
15063 enum machine_mode mode
= GET_MODE (target
);
15064 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
15065 int n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
15068 for (i
= n_elts
- 1; i
>= 0; i
--)
15069 if (GET_CODE (XVECEXP (vals
, 0, i
)) != CONST_INT
15070 && GET_CODE (XVECEXP (vals
, 0, i
)) != CONST_DOUBLE
)
15073 /* Few special cases first...
15074 ... constants are best loaded from constant pool. */
15077 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
15081 /* ... values where only first field is non-constant are best loaded
15082 from the pool and overwritten via move later. */
15085 rtx op
= simplify_gen_subreg (mode
, XVECEXP (vals
, 0, 0),
15086 GET_MODE_INNER (mode
), 0);
15088 op
= force_reg (mode
, op
);
15089 XVECEXP (vals
, 0, 0) = CONST0_RTX (GET_MODE_INNER (mode
));
15090 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
15091 switch (GET_MODE (target
))
15094 emit_insn (gen_sse2_movsd (target
, target
, op
));
15097 emit_insn (gen_sse_movss (target
, target
, op
));
15105 /* And the busy sequence doing rotations. */
15106 switch (GET_MODE (target
))
15111 simplify_gen_subreg (V2DFmode
, XVECEXP (vals
, 0, 0), DFmode
, 0);
15113 simplify_gen_subreg (V2DFmode
, XVECEXP (vals
, 0, 1), DFmode
, 0);
15115 vecop0
= force_reg (V2DFmode
, vecop0
);
15116 vecop1
= force_reg (V2DFmode
, vecop1
);
15117 emit_insn (gen_sse2_unpcklpd (target
, vecop0
, vecop1
));
15123 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 0), SFmode
, 0);
15125 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 1), SFmode
, 0);
15127 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 2), SFmode
, 0);
15129 simplify_gen_subreg (V4SFmode
, XVECEXP (vals
, 0, 3), SFmode
, 0);
15130 rtx tmp1
= gen_reg_rtx (V4SFmode
);
15131 rtx tmp2
= gen_reg_rtx (V4SFmode
);
15133 vecop0
= force_reg (V4SFmode
, vecop0
);
15134 vecop1
= force_reg (V4SFmode
, vecop1
);
15135 vecop2
= force_reg (V4SFmode
, vecop2
);
15136 vecop3
= force_reg (V4SFmode
, vecop3
);
15137 emit_insn (gen_sse_unpcklps (tmp1
, vecop1
, vecop3
));
15138 emit_insn (gen_sse_unpcklps (tmp2
, vecop0
, vecop2
));
15139 emit_insn (gen_sse_unpcklps (target
, tmp2
, tmp1
));
15147 /* Implements target hook vector_mode_supported_p. */
15149 ix86_vector_mode_supported_p (enum machine_mode mode
)
15152 && VALID_SSE_REG_MODE (mode
))
15155 else if (TARGET_MMX
15156 && VALID_MMX_REG_MODE (mode
))
15159 else if (TARGET_3DNOW
15160 && VALID_MMX_REG_MODE_3DNOW (mode
))
15167 /* Worker function for TARGET_MD_ASM_CLOBBERS.
15169 We do this in the new i386 backend to maintain source compatibility
15170 with the old cc0-based compiler. */
15173 ix86_md_asm_clobbers (tree clobbers
)
15175 clobbers
= tree_cons (NULL_TREE
, build_string (5, "flags"),
15177 clobbers
= tree_cons (NULL_TREE
, build_string (4, "fpsr"),
15179 clobbers
= tree_cons (NULL_TREE
, build_string (7, "dirflag"),
15184 /* Worker function for REVERSE_CONDITION. */
15187 ix86_reverse_condition (enum rtx_code code
, enum machine_mode mode
)
15189 return (mode
!= CCFPmode
&& mode
!= CCFPUmode
15190 ? reverse_condition (code
)
15191 : reverse_condition_maybe_unordered (code
));
15194 /* Output code to perform an x87 FP register move, from OPERANDS[1]
15198 output_387_reg_move (rtx insn
, rtx
*operands
)
15200 if (REG_P (operands
[1])
15201 && find_regno_note (insn
, REG_DEAD
, REGNO (operands
[1])))
15203 if (REGNO (operands
[0]) == FIRST_STACK_REG
15204 && TARGET_USE_FFREEP
)
15205 return "ffreep\t%y0";
15206 return "fstp\t%y0";
15208 if (STACK_TOP_P (operands
[0]))
15209 return "fld%z1\t%y1";
15213 /* Output code to perform a conditional jump to LABEL, if C2 flag in
15214 FP status register is set. */
15217 ix86_emit_fp_unordered_jump (rtx label
)
15219 rtx reg
= gen_reg_rtx (HImode
);
15222 emit_insn (gen_x86_fnstsw_1 (reg
));
15224 if (TARGET_USE_SAHF
)
15226 emit_insn (gen_x86_sahf_1 (reg
));
15228 temp
= gen_rtx_REG (CCmode
, FLAGS_REG
);
15229 temp
= gen_rtx_UNORDERED (VOIDmode
, temp
, const0_rtx
);
15233 emit_insn (gen_testqi_ext_ccno_0 (reg
, GEN_INT (0x04)));
15235 temp
= gen_rtx_REG (CCNOmode
, FLAGS_REG
);
15236 temp
= gen_rtx_NE (VOIDmode
, temp
, const0_rtx
);
15239 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
15240 gen_rtx_LABEL_REF (VOIDmode
, label
),
15242 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
15243 emit_jump_insn (temp
);
15246 /* Output code to perform a log1p XFmode calculation. */
15248 void ix86_emit_i387_log1p (rtx op0
, rtx op1
)
15250 rtx label1
= gen_label_rtx ();
15251 rtx label2
= gen_label_rtx ();
15253 rtx tmp
= gen_reg_rtx (XFmode
);
15254 rtx tmp2
= gen_reg_rtx (XFmode
);
15256 emit_insn (gen_absxf2 (tmp
, op1
));
15257 emit_insn (gen_cmpxf (tmp
,
15258 CONST_DOUBLE_FROM_REAL_VALUE (
15259 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode
),
15261 emit_jump_insn (gen_bge (label1
));
15263 emit_move_insn (tmp2
, standard_80387_constant_rtx (4)); /* fldln2 */
15264 emit_insn (gen_fyl2xp1_xf3 (op0
, tmp2
, op1
));
15265 emit_jump (label2
);
15267 emit_label (label1
);
15268 emit_move_insn (tmp
, CONST1_RTX (XFmode
));
15269 emit_insn (gen_addxf3 (tmp
, op1
, tmp
));
15270 emit_move_insn (tmp2
, standard_80387_constant_rtx (4)); /* fldln2 */
15271 emit_insn (gen_fyl2x_xf3 (op0
, tmp2
, tmp
));
15273 emit_label (label2
);
15276 /* Solaris named-section hook. Parameters are as for
15277 named_section_real. */
15280 i386_solaris_elf_named_section (const char *name
, unsigned int flags
,
15283 /* With Binutils 2.15, the "@unwind" marker must be specified on
15284 every occurrence of the ".eh_frame" section, not just the first
15287 && strcmp (name
, ".eh_frame") == 0)
15289 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",@unwind\n", name
,
15290 flags
& SECTION_WRITE
? "aw" : "a");
15293 default_elf_asm_named_section (name
, flags
, decl
);
15296 #include "gt-i386.h"