1 ;;- Machine description for GNU compiler -- System/
370 version.
2 ;; Copyright (C)
1989,
1993,
1994 Free Software Foundation, Inc.
3 ;; Contributed by Jan Stein (jan@cd.chalmers.se).
4 ;; Modifed for MVS C/
370 by Dave Pitts (pitts@mcdata.com)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version
2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation,
675 Mass Ave, Cambridge, MA
02139, USA.
22 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
23 ;;- updates for most instructions.
26 ;; Special constraints for
370 machine description:
28 ;; a -- Any address register from
1 to
15.
29 ;; d -- Any register from
0 to
15.
30 ;; I -- An
8-bit constant (
0.
.255).
31 ;; J -- A
12-bit constant (
0.
.4095).
32 ;; K -- A
16-bit constant (-
32768.
.32767).
34 ;; Special formats used for outputting
370 instructions.
36 ;; %B -- Print a constant byte integer.
37 ;; %H -- Print a signed
16-bit constant.
38 ;; %L -- Print least significant word of a CONST_DOUBLE.
39 ;; %M -- Print most significant word of a CONST_DOUBLE.
40 ;; %N -- Print next register (second word of a DImode reg).
41 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
43 ;; %X -- Print a constant byte integer in hex.
45 ;; We have a special contraint for pattern matching.
47 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
49 ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI
50 ;; or SS type instruction or a register
52 ;; For MVS C/
370 we use the following stack locations for:
54 ;;
136 - internal function result buffer
55 ;;
140 - numeric conversion buffer
56 ;;
144 - pointer to internal function result buffer
57 ;;
148 - start of automatic variables and function arguments
59 ;; To support programs larger than a page,
4096 bytes, PAGE_REGISTER points
60 ;; to a page origin table, all internal labels are generated to reload the
61 ;; BASE_REGISTER knowing what page it is on and all branch instructions go
62 ;; directly to the target if it is known that the target is on the current
63 ;; page (essentially backward references). All forward references and off
64 ;; page references are handled by loading the address of target into a
65 ;; register and branching indirectly.
67 ;; Some *di patterns have been commented out per advice from RMS, as gcc
68 ;; will generate the right things to do.
72 ;;- Test instructions.
76 ; tstdi instruction pattern(s).
81 (match_operand:DI
0 "register_operand" "d"))]
86 mvs_check_page (
0,
4,
0);
91 ; tstsi instruction pattern(s).
96 (match_operand:SI
0 "register_operand" "d"))]
101 mvs_check_page (
0,
2,
0);
102 return
\"LTR %
0,%
0\";
106 ; tsthi instruction pattern(s).
111 (match_operand:HI
0 "register_operand" "d"))]
116 mvs_check_page (
0,
4,
2);
117 return
\"CH %
0,=H'
0'
\";
121 ; tstqi instruction pattern(s).
126 (match_operand:QI
0 "r_or_s_operand" "dm"))]
127 "unsigned_jump_follows_p (insn)"
131 if (REG_P (operands[
0]))
133 mvs_check_page (
0,
4,
4);
134 return
\"N %
0,=X'
000000FF'
\";
136 mvs_check_page (
0,
4,
0);
142 (match_operand:QI
0 "register_operand" "d"))]
147 if (unsigned_jump_follows_p (insn))
149 mvs_check_page (
0,
4,
4);
150 return
\"N %
0,=X'
000000FF'
\";
152 mvs_check_page (
0,
8,
0);
153 return
\"SLL %
0,
24\;SRA %
0,
24\";
157 ; tstdf instruction pattern(s).
162 (match_operand:DF
0 "general_operand" "f"))]
167 mvs_check_page (
0,
2,
0);
168 return
\"LTDR %
0,%
0\";
172 ; tstsf instruction pattern(s).
177 (match_operand:SF
0 "general_operand" "f"))]
182 mvs_check_page (
0,
2,
0);
183 return
\"LTER %
0,%
0\";
187 ;;- Compare instructions.
191 ; cmpdi instruction pattern(s).
194 ;(define_insn "cmpdi"
196 ; (compare (match_operand:DI
0 "register_operand" "d")
197 ; (match_operand:DI
1 "general_operand" "")))]
201 ; check_label_emit ();
202 ; if (REG_P (operands[
1]))
204 ; mvs_check_page (
0,
8,
0);
205 ; if (unsigned_jump_follows_p (insn))
206 ; return
\"CLR %
0,%
1\;BNE *+
6\;CLR %N0,%N1
\";
207 ; return
\"CR %
0,%
1\;BNE *+
6\;CLR %N0,%N1
\";
209 ; mvs_check_page (
0,
12,
0);
210 ; if (unsigned_jump_follows_p (insn))
211 ; return
\"CL %
0,%M1\;BNE *+
8\;CL %N0,%L1
\";
212 ; return
\"C %
0,%M1\;BNE *+
8\;CL %N0,%L1
\";
216 ; cmpsi instruction pattern(s).
221 (compare (match_operand:SI
0 "register_operand" "d")
222 (match_operand:SI
1 "general_operand" "")))]
227 if (REG_P (operands[
1]))
229 mvs_check_page (
0,
2,
0);
230 if (unsigned_jump_follows_p (insn))
231 return
\"CLR %
0,%
1\";
234 if (GET_CODE (operands[
1]) == CONST_INT)
236 mvs_check_page (
0,
4,
4);
237 if (unsigned_jump_follows_p (insn))
238 return
\"CL %
0,=F'%c1'
\";
239 return
\"C %
0,=F'%c1'
\";
241 mvs_check_page (
0,
4,
0);
242 if (unsigned_jump_follows_p (insn))
248 ; cmphi instruction pattern(s).
253 (compare (match_operand:HI
0 "register_operand" "d")
254 (match_operand:HI
1 "general_operand" "")))]
259 if (REG_P (operands[
1]))
261 mvs_check_page (
0,
8,
0);
262 if (unsigned_jump_follows_p (insn))
263 return
\"STH %
1,
140(,
13)\;CLM %
0,
3,
140(
13)
\";
264 return
\"STH %
1,
140(,
13)\;CH %
0,
140(,
13)
\";
266 if (GET_CODE (operands[
1]) == CONST_INT)
268 mvs_check_page (
0,
4,
2);
269 return
\"CH %
0,=H'%h1'
\";
271 mvs_check_page (
0,
4,
0);
276 ; cmpqi instruction pattern(s).
281 (compare (match_operand:QI
0 "r_or_s_operand" "g")
282 (match_operand:QI
1 "r_or_s_operand" "g")))]
283 "unsigned_jump_follows_p (insn)"
287 if (REG_P (operands[
0]))
289 if (REG_P (operands[
1]))
291 mvs_check_page (
0,
8,
0);
292 return
\"STC %
1,
140(,
13)\;CLM %
0,
1,
140(
13)
\";
294 if (GET_CODE (operands[
1]) == CONST_INT)
296 mvs_check_page (
0,
4,
1);
297 return
\"CLM %
0,
1,=X'%X1'
\";
299 mvs_check_page (
0,
4,
0);
300 return
\"CLM %
0,
1,%
1\";
302 else if (GET_CODE (operands[
0]) == CONST_INT)
304 cc_status.flags |= CC_REVERSED;
305 if (REG_P (operands[
1]))
307 mvs_check_page (
0,
4,
1);
308 return
\"CLM %
1,
1,=X'%X0'
\";
310 mvs_check_page (
0,
4,
0);
311 return
\"CLI %
1,%B0
\";
313 if (GET_CODE (operands[
1]) == CONST_INT)
315 mvs_check_page (
0,
4,
0);
316 return
\"CLI %
0,%B1
\";
318 if (GET_CODE (operands[
1]) == MEM)
320 mvs_check_page (
0,
6,
0);
321 return
\"CLC %O0(
1,%R0),%
1\";
323 cc_status.flags |= CC_REVERSED;
324 mvs_check_page (
0,
4,
0);
325 return
\"CLM %
1,
1,%
0\";
330 (compare (match_operand:QI
0 "register_operand" "d")
331 (match_operand:QI
1 "general_operand" "di")))]
336 if (unsigned_jump_follows_p (insn))
338 if (REG_P (operands[
1]))
340 mvs_check_page (
0,
4,
0);
341 return
\"CLM %
0,
1,%
1\";
343 if (GET_CODE (operands[
1]) == CONST_INT)
345 mvs_check_page (
0,
4,
1);
346 return
\"CLM %
0,
1,=X'%X1'
\";
348 mvs_check_page (
0,
8,
0);
349 return
\"STC %
1,
140(,
13)\;CLM %
0,
1,
140(
13)
\";
351 if (REG_P (operands[
1]))
353 mvs_check_page (
0,
18,
0);
354 return
\"SLL %
0,
24\;SRA %
0,
24\;SLL %
1,
24\;SRA %
1,
24\;CR %
0,%
1\";
356 mvs_check_page (
0,
12,
0);
357 return
\"SLL %
0,
24\;SRA %
0,
24\;C %
0,%
1\";
361 ; cmpdf instruction pattern(s).
366 (compare (match_operand:DF
0 "general_operand" "f,mF")
367 (match_operand:DF
1 "general_operand" "fmF,f")))]
372 if (FP_REG_P (operands[
0]))
374 if (FP_REG_P (operands[
1]))
376 mvs_check_page (
0,
2,
0);
377 return
\"CDR %
0,%
1\";
379 mvs_check_page (
0,
4,
0);
382 cc_status.flags |= CC_REVERSED;
383 mvs_check_page (
0,
4,
0);
388 ; cmpsf instruction pattern(s).
393 (compare (match_operand:SF
0 "general_operand" "f,mF")
394 (match_operand:SF
1 "general_operand" "fmF,f")))]
399 if (FP_REG_P (operands[
0]))
401 if (FP_REG_P (operands[
1]))
403 mvs_check_page (
0,
2,
0);
404 return
\"CER %
0,%
1\";
406 mvs_check_page (
0,
4,
0);
409 cc_status.flags |= CC_REVERSED;
410 mvs_check_page (
0,
4,
0);
415 ; cmpstrsi instruction pattern(s).
418 (define_expand "cmpstrsi"
419 [(set (match_operand:SI
0 "general_operand" "")
420 (compare (match_operand:BLK
1 "general_operand" "")
421 (match_operand:BLK
2 "general_operand" "")))
422 (use (match_operand:SI
3 "general_operand" ""))
423 (use (match_operand:SI
4 "" ""))]
429 op1 = XEXP (operands[
1],
0);
430 if (GET_CODE (op1) == REG
431 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1,
0)) == REG
432 && GET_CODE (XEXP (op1,
1)) == CONST_INT
433 && (unsigned) INTVAL (XEXP (op1,
1)) <
4096))
439 op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1));
442 op2 = XEXP (operands[
2],
0);
443 if (GET_CODE (op2) == REG
444 || (GET_CODE (op2) == PLUS && GET_CODE (XEXP (op2,
0)) == REG
445 && GET_CODE (XEXP (op2,
1)) == CONST_INT
446 && (unsigned) INTVAL (XEXP (op2,
1)) <
4096))
452 op2 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op2));
455 if (GET_CODE (operands[
3]) == CONST_INT && INTVAL (operands[
3]) <
256)
457 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (
2,
458 gen_rtx (SET, VOIDmode, operands[
0],
459 gen_rtx (COMPARE, VOIDmode, op1, op2)),
460 gen_rtx (USE, VOIDmode, operands[
3]))));
464 rtx reg1 = gen_reg_rtx (DImode);
465 rtx reg2 = gen_reg_rtx (DImode);
466 rtx subreg = gen_rtx (SUBREG, SImode, reg1,
1);
468 emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[
3]));
469 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2,
1),
471 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (
5,
472 gen_rtx (SET, VOIDmode, operands[
0],
473 gen_rtx (COMPARE, VOIDmode, op1, op2)),
474 gen_rtx (USE, VOIDmode, reg1),
475 gen_rtx (USE, VOIDmode, reg2),
476 gen_rtx (CLOBBER, VOIDmode, reg1),
477 gen_rtx (CLOBBER, VOIDmode, reg2))));
482 ; Compare a block that is less than
256 bytes in length.
485 [(set (match_operand:SI
0 "register_operand" "d")
486 (compare (match_operand:BLK
1 "s_operand" "m")
487 (match_operand:BLK
2 "s_operand" "m")))
488 (use (match_operand:QI
3 "immediate_operand" "I"))]
489 "((unsigned) INTVAL (operands[
3]) <
256)"
493 mvs_check_page (
0,
22,
0);
494 return
\"LA %
0,
1\;CLC %O1(%c3,%R1),%
2\;BH *+
12\;BL *+
6\;SLR %
0,%
0\;LNR %
0,%
0\";
497 ; Compare a block that is larger than
255 bytes in length.
500 [(set (match_operand:SI
0 "register_operand" "d")
501 (compare (match_operand:BLK
1 "general_operand" "m")
502 (match_operand:BLK
2 "general_operand" "m")))
503 (use (match_operand:DI
3 "register_operand" "d"))
504 (use (match_operand:DI
4 "register_operand" "d"))
505 (clobber (match_dup
3))
506 (clobber (match_dup
4))]
511 mvs_check_page (
0,
26,
0);
512 return
\"LA %
3,%
1\;LA %
4,%
2\;LA %
0,
1\;CLCL %
3,%
4\;BH *+
12\;BL *+
6\;SLR %
0,%
0\;LNR %
0,%
0\";
516 ;;- Move instructions.
520 ; movdi instruction pattern(s).
524 [(set (match_operand:DI
0 "r_or_s_operand" "=dm")
525 (match_operand:DI
1 "r_or_s_operand" "dim*fF"))]
526 "TARGET_CHAR_INSTRUCTIONS"
530 if (REG_P (operands[
0]))
532 if (FP_REG_P (operands[
1]))
534 mvs_check_page (
0,
8,
0);
535 return
\"STD %
1,
140(,
13)\;LM %
0,%N0,
140(
13)
\";
537 if (REG_P (operands[
1]))
539 mvs_check_page (
0,
4,
0);
540 return
\"LR %
0,%
1\;LR %N0,%N1
\";
542 if (operands[
1] == const0_rtx)
545 mvs_check_page (
0,
4,
0);
546 return
\"SLR %
0,%
0\;SLR %N0,%N0
\";
548 if (GET_CODE (operands[
1]) == CONST_INT
549 && (unsigned) INTVAL (operands[
1]) <
4096)
552 mvs_check_page (
0,
6,
0);
553 return
\"SLR %
0,%
0\;LA %N0,%c1
\";
555 if (GET_CODE (operands[
1]) == CONST_INT)
557 CC_STATUS_SET (operands[
0], operands[
1]);
558 mvs_check_page (
0,
8,
0);
559 return
\"L %
0,%
1\;SRDA %
0,
32\";
561 mvs_check_page (
0,
4,
0);
562 return
\"LM %
0,%N0,%
1\";
564 else if (FP_REG_P (operands[
1]))
566 mvs_check_page (
0,
4,
0);
567 return
\"STD %
1,%
0\";
569 else if (REG_P (operands[
1]))
571 mvs_check_page (
0,
4,
0);
572 return
\"STM %
1,%N1,%
0\";
574 mvs_check_page (
0,
6,
0);
575 return
\"MVC %O0(
8,%R0),%
1\";
579 [(set (match_operand:DI
0 "general_operand" "=dm")
580 (match_operand:DI
1 "general_operand" "dim*fF"))]
585 if (REG_P (operands[
0]))
587 if (FP_REG_P (operands[
1]))
589 mvs_check_page (
0,
8,
0);
590 return
\"STD %
1,
140(,
13)\;LM %
0,%N0,
140(
13)
\";
592 if (REG_P (operands[
1]))
594 mvs_check_page (
0,
4,
0);
595 return
\"LR %
0,%
1\;LR %N0,%N1
\";
597 if (operands[
1] == const0_rtx)
600 mvs_check_page (
0,
4,
0);
601 return
\"SLR %
0,%
0\;SLR %N0,%N0
\";
603 if (GET_CODE (operands[
1]) == CONST_INT
604 && (unsigned) INTVAL (operands[
1]) <
4096)
607 mvs_check_page (
0,
6,
0);
608 return
\"SLR %
0,%
0\;LA %N0,%c1
\";
610 if (GET_CODE (operands[
1]) == CONST_INT)
612 CC_STATUS_SET (operands[
0], operands[
1]);
613 mvs_check_page (
0,
8,
0);
614 return
\"L %
0,%
1\;SRDA %
0,
32\";
616 mvs_check_page (
0,
4,
0);
617 return
\"LM %
0,%N0,%
1\";
619 else if (FP_REG_P (operands[
1]))
621 mvs_check_page (
0,
4,
0);
622 return
\"STD %
1,%
0\";
624 mvs_check_page (
0,
4,
0);
625 return
\"STM %
1,%N1,%
0\";
629 ; movsi instruction pattern(s).
633 [(set (match_operand:SI
0 "r_or_s_operand" "=dm,dm")
634 (match_operand:SI
1 "r_or_s_operand" "dim,*fF"))]
635 "TARGET_CHAR_INSTRUCTIONS"
639 if (REG_P (operands[
0]))
641 if (FP_REG_P (operands[
1]))
643 mvs_check_page (
0,
8,
0);
644 return
\"STE %
1,
140(,
13)\;L %
0,
140(,
13)
\";
646 if (REG_P (operands[
1]))
648 mvs_check_page (
0,
2,
0);
651 if (operands[
1] == const0_rtx)
654 mvs_check_page (
0,
2,
0);
655 return
\"SLR %
0,%
0\";
657 if (GET_CODE (operands[
1]) == CONST_INT
658 && (unsigned) INTVAL (operands[
1]) <
4096)
660 mvs_check_page (
0,
4,
0);
661 return
\"LA %
0,%c1
\";
663 mvs_check_page (
0,
4,
0);
666 else if (FP_REG_P (operands[
1]))
668 mvs_check_page (
0,
4,
0);
669 return
\"STE %
1,%
0\";
671 else if (REG_P (operands[
1]))
673 mvs_check_page (
0,
4,
0);
676 mvs_check_page (
0,
6,
0);
677 return
\"MVC %O0(
4,%R0),%
1\";
681 [(set (match_operand:SI
0 "general_operand" "=d,dm")
682 (match_operand:SI
1 "general_operand" "dimF,*fd"))]
687 if (REG_P (operands[
0]))
689 if (FP_REG_P (operands[
1]))
691 mvs_check_page (
0,
8,
0);
692 return
\"STE %
1,
140(,
13)\;L %
0,
140(,
13)
\";
694 if (REG_P (operands[
1]))
696 mvs_check_page (
0,
2,
0);
699 if (operands[
1] == const0_rtx)
702 mvs_check_page (
0,
2,
0);
703 return
\"SLR %
0,%
0\";
705 if (GET_CODE (operands[
1]) == CONST_INT
706 && (unsigned) INTVAL (operands[
1]) <
4096)
708 mvs_check_page (
0,
4,
0);
709 return
\"LA %
0,%c1
\";
711 mvs_check_page (
0,
4,
0);
714 else if (FP_REG_P (operands[
1]))
716 mvs_check_page (
0,
4,
0);
717 return
\"STE %
1,%
0\";
719 mvs_check_page (
0,
4,
0);
723 ;(define_expand "movsi"
724 ; [(set (match_operand:SI
0 "general_operand" "=d,dm")
725 ; (match_operand:SI
1 "general_operand" "dimF,*fd"))]
732 ; if (GET_CODE (op0) == CONST
733 ; && GET_CODE (XEXP (XEXP (op0,
0),
0)) == SYMBOL_REF
734 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op0,
0),
0)))
736 ; op0 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op0,
0)));
740 ; if (GET_CODE (op1) == CONST
741 ; && GET_CODE (XEXP (XEXP (op1,
0),
0)) == SYMBOL_REF
742 ; && SYMBOL_REF_FLAG (XEXP (XEXP (op1,
0),
0)))
744 ; op1 = gen_rtx (MEM, SImode, copy_to_mode_reg (SImode, XEXP (op1,
0)));
747 ; emit_insn (gen_rtx (SET, VOIDmode, op0, op1));
752 ; movhi instruction pattern(s).
756 [(set (match_operand:HI
0 "r_or_s_operand" "=g")
757 (match_operand:HI
1 "r_or_s_operand" "g"))]
758 "TARGET_CHAR_INSTRUCTIONS"
762 if (REG_P (operands[
0]))
764 if (REG_P (operands[
1]))
766 mvs_check_page (
0,
2,
0);
769 if (operands[
1] == const0_rtx)
772 mvs_check_page (
0,
2,
0);
773 return
\"SLR %
0,%
0\";
775 if (GET_CODE (operands[
1]) == CONST_INT
776 && (unsigned) INTVAL (operands[
1]) <
4096)
778 mvs_check_page (
0,
4,
0);
779 return
\"LA %
0,%c1
\";
781 if (GET_CODE (operands[
1]) == CONST_INT)
783 mvs_check_page (
0,
4,
2);
784 return
\"LH %
0,=H'%h1'
\";
786 mvs_check_page (
0,
4,
0);
789 else if (REG_P (operands[
1]))
791 mvs_check_page (
0,
4,
0);
792 return
\"STH %
1,%
0\";
794 if (GET_CODE (operands[
1]) == CONST_INT)
796 mvs_check_page (
0,
6,
0);
797 return
\"MVC %O0(
2,%R0),=H'%h1'
\";
799 mvs_check_page (
0,
6,
0);
800 return
\"MVC %O0(
2,%R0),%
1\";
804 [(set (match_operand:HI
0 "general_operand" "=d,m")
805 (match_operand:HI
1 "general_operand" "g,d"))]
810 if (REG_P (operands[
0]))
812 if (REG_P (operands[
1]))
814 mvs_check_page (
0,
2,
0);
817 if (operands[
1] == const0_rtx)
820 mvs_check_page (
0,
2,
0);
821 return
\"SLR %
0,%
0\";
823 if (GET_CODE (operands[
1]) == CONST_INT
824 && (unsigned) INTVAL (operands[
1]) <
4096)
826 mvs_check_page (
0,
4,
0);
827 return
\"LA %
0,%c1
\";
829 if (GET_CODE (operands[
1]) == CONST_INT)
831 mvs_check_page (
0,
4,
2);
832 return
\"LH %
0,=H'%h1'
\";
834 mvs_check_page (
0,
4,
0);
837 mvs_check_page (
0,
4,
0);
838 return
\"STH %
1,%
0\";
842 ; movqi instruction pattern(s).
846 [(set (match_operand:QI
0 "r_or_s_operand" "=g")
847 (match_operand:QI
1 "r_or_s_operand" "g"))]
848 "TARGET_CHAR_INSTRUCTIONS"
852 if (REG_P (operands[
0]))
854 if (REG_P (operands[
1]))
856 mvs_check_page (
0,
2,
0);
859 if (operands[
1] == const0_rtx)
862 mvs_check_page (
0,
2,
0);
863 return
\"SLR %
0,%
0\";
865 if (GET_CODE (operands[
1]) == CONST_INT)
867 if (INTVAL (operands[
1]) >=
0)
869 mvs_check_page (
0,
4,
0);
870 return
\"LA %
0,%c1
\";
872 mvs_check_page (
0,
4,
0);
873 return
\"L %
0,=F'%c1'
\";
875 mvs_check_page (
0,
4,
0);
878 else if (REG_P (operands[
1]))
880 mvs_check_page (
0,
4,
0);
881 return
\"STC %
1,%
0\";
883 else if (GET_CODE (operands[
1]) == CONST_INT)
885 mvs_check_page (
0,
4,
0);
886 return
\"MVI %
0,%B1
\";
888 mvs_check_page (
0,
6,
0);
889 return
\"MVC %O0(
1,%R0),%
1\";
893 [(set (match_operand:QI
0 "general_operand" "=d,m")
894 (match_operand:QI
1 "general_operand" "g,d"))]
899 if (REG_P (operands[
0]))
901 if (REG_P (operands[
1]))
903 mvs_check_page (
0,
2,
0);
906 if (operands[
1] == const0_rtx)
909 mvs_check_page (
0,
2,
0);
910 return
\"SLR %
0,%
0\";
912 if (GET_CODE (operands[
1]) == CONST_INT)
914 if (INTVAL (operands[
1]) >=
0)
916 mvs_check_page (
0,
4,
0);
917 return
\"LA %
0,%c1
\";
919 mvs_check_page (
0,
4,
0);
920 return
\"L %
0,=F'%c1'
\";
922 mvs_check_page (
0,
4,
0);
925 mvs_check_page (
0,
4,
0);
926 return
\"STC %
1,%
0\";
930 ; movestrictqi instruction pattern(s).
933 (define_insn "movestrictqi"
934 [(set (strict_low_part (match_operand:QI
0 "general_operand" "=d"))
935 (match_operand:QI
1 "general_operand" "g"))]
940 if (REG_P (operands[
1]))
942 mvs_check_page (
0,
8,
0);
943 return
\"STC %
1,
140(,
13)\;IC %
0,
140(,
13)
\";
945 mvs_check_page (
0,
4,
0);
950 ; movstricthi instruction pattern(s).
954 [(set (strict_low_part (match_operand:HI
0 "register_operand" "=d"))
955 (match_operand:HI
1 "r_or_s_operand" "g"))]
960 if (REG_P (operands[
1]))
962 mvs_check_page (
0,
8,
0);
963 return
\"STH %
1,
140(,
13)\;ICM %
0,
3,
140(
13)
\";
965 else if (GET_CODE (operands[
1]) == CONST_INT)
967 mvs_check_page (
0,
4,
2);
968 return
\"ICM %
0,
3,=H'%h1'
\";
970 mvs_check_page (
0,
4,
0);
971 return
\"ICM %
0,
3,%
1\";
974 (define_insn "movestricthi"
975 [(set (strict_low_part (match_operand:HI
0 "general_operand" "=dm"))
976 (match_operand:HI
1 "general_operand" "d"))]
981 if (REG_P (operands[
0]))
983 mvs_check_page (
0,
8,
0);
984 return
\"STH %
1,
140(,
13)\;ICM %
0,
3,
140(
13)
\";
986 mvs_check_page (
0,
4,
0);
987 return
\"STH %
1,%
0\";
991 ; movdf instruction pattern(s).
995 [(set (match_operand:DF
0 "r_or_s_operand" "=fm,fm,*dm")
996 (match_operand:DF
1 "r_or_s_operand" "fmF,*dm,fmF"))]
997 "TARGET_CHAR_INSTRUCTIONS"
1000 check_label_emit ();
1001 if (FP_REG_P (operands[
0]))
1003 if (FP_REG_P (operands[
1]))
1005 mvs_check_page (
0,
2,
0);
1006 return
\"LDR %
0,%
1\";
1008 if (REG_P (operands[
1]))
1010 mvs_check_page (
0,
8,
0);
1011 return
\"STM %
1,%N1,
140(
13)\;LD %
0,
140(,
13)
\";
1013 if (operands[
1] == const0_rtx)
1015 CC_STATUS_SET (operands[
0], operands[
1]);
1016 mvs_check_page (
0,
2,
0);
1017 return
\"SDR %
0,%
0\";
1019 mvs_check_page (
0,
4,
0);
1020 return
\"LD %
0,%
1\";
1022 if (REG_P (operands[
0]))
1024 if (FP_REG_P (operands[
1]))
1026 mvs_check_page (
0,
12,
0);
1027 return
\"STD %
1,
140(,
13)\;LM %
0,%N0,
140(
13)
\";
1029 mvs_check_page (
0,
4,
0);
1030 return
\"LM %
0,%N0,%
1\";
1032 else if (FP_REG_P (operands[
1]))
1034 mvs_check_page (
0,
4,
0);
1035 return
\"STD %
1,%
0\";
1037 else if (REG_P (operands[
1]))
1039 mvs_check_page (
0,
4,
0);
1040 return
\"STM %
1,%N1,%
0\";
1042 mvs_check_page (
0,
6,
0);
1043 return
\"MVC %O0(
8,%R0),%
1\";
1046 (define_insn "movdf"
1047 [(set (match_operand:DF
0 "general_operand" "=f,fm,m,*d")
1048 (match_operand:DF
1 "general_operand" "fmF,*d,f,fmF"))]
1052 check_label_emit ();
1053 if (FP_REG_P (operands[
0]))
1055 if (FP_REG_P (operands[
1]))
1057 mvs_check_page (
0,
2,
0);
1058 return
\"LDR %
0,%
1\";
1060 if (REG_P (operands[
1]))
1062 mvs_check_page (
0,
8,
0);
1063 return
\"STM %
1,%N1,
140(
13)\;LD %
0,
140(,
13)
\";
1065 if (operands[
1] == const0_rtx)
1067 CC_STATUS_SET (operands[
0], operands[
1]);
1068 mvs_check_page (
0,
2,
0);
1069 return
\"SDR %
0,%
0\";
1071 mvs_check_page (
0,
4,
0);
1072 return
\"LD %
0,%
1\";
1074 else if (REG_P (operands[
0]))
1076 if (FP_REG_P (operands[
1]))
1078 mvs_check_page (
0,
12,
0);
1079 return
\"STD %
1,
140(,
13)\;LM %
0,%N0,
140(
13)
\";
1081 mvs_check_page (
0,
4,
0);
1082 return
\"LM %
0,%N0,%
1\";
1084 else if (FP_REG_P (operands[
1]))
1086 mvs_check_page (
0,
4,
0);
1087 return
\"STD %
1,%
0\";
1089 mvs_check_page (
0,
4,
0);
1090 return
\"STM %
1,%N1,%
0\";
1094 ; movsf instruction pattern(s).
1098 [(set (match_operand:SF
0 "r_or_s_operand" "=fm,fm,*dm")
1099 (match_operand:SF
1 "r_or_s_operand" "fmF,*dm,fmF"))]
1100 "TARGET_CHAR_INSTRUCTIONS"
1103 check_label_emit ();
1104 if (FP_REG_P (operands[
0]))
1106 if (FP_REG_P (operands[
1]))
1108 mvs_check_page (
0,
2,
0);
1109 return
\"LER %
0,%
1\";
1111 if (REG_P (operands[
1]))
1113 mvs_check_page (
0,
8,
0);
1114 return
\"ST %
1,
140(,
13)\;LE %
0,
140(,
13)
\";
1116 if (operands[
1] == const0_rtx)
1118 CC_STATUS_SET (operands[
0], operands[
1]);
1119 mvs_check_page (
0,
2,
0);
1120 return
\"SER %
0,%
0\";
1122 mvs_check_page (
0,
4,
0);
1123 return
\"LE %
0,%
1\";
1125 else if (REG_P (operands[
0]))
1127 if (FP_REG_P (operands[
1]))
1129 mvs_check_page (
0,
8,
0);
1130 return
\"STE %
1,
140(,
13)\;L %
0,
140(,
13)
\";
1132 mvs_check_page (
0,
4,
0);
1135 else if (FP_REG_P (operands[
1]))
1137 mvs_check_page (
0,
4,
0);
1138 return
\"STE %
1,%
0\";
1140 else if (REG_P (operands[
1]))
1142 mvs_check_page (
0,
4,
0);
1143 return
\"ST %
1,%
0\";
1145 mvs_check_page (
0,
6,
0);
1146 return
\"MVC %O0(
4,%R0),%
1\";
1149 (define_insn "movsf"
1150 [(set (match_operand:SF
0 "general_operand" "=f,fm,m,*d")
1151 (match_operand:SF
1 "general_operand" "fmF,*d,f,fmF"))]
1155 check_label_emit ();
1156 if (FP_REG_P (operands[
0]))
1158 if (FP_REG_P (operands[
1]))
1160 mvs_check_page (
0,
2,
0);
1161 return
\"LER %
0,%
1\";
1163 if (REG_P (operands[
1]))
1165 mvs_check_page (
0,
8,
0);
1166 return
\"ST %
1,
140(,
13)\;LE %
0,
140(,
13)
\";
1168 if (operands[
1] == const0_rtx)
1170 CC_STATUS_SET (operands[
0], operands[
1]);
1171 mvs_check_page (
0,
2,
0);
1172 return
\"SER %
0,%
0\";
1174 mvs_check_page (
0,
4,
0);
1175 return
\"LE %
0,%
1\";
1177 else if (REG_P (operands[
0]))
1179 if (FP_REG_P (operands[
1]))
1181 mvs_check_page (
0,
8,
0);
1182 return
\"STE %
1,
140(,
13)\;L %
0,
140(,
13)
\";
1184 mvs_check_page (
0,
4,
0);
1187 else if (FP_REG_P (operands[
1]))
1189 mvs_check_page (
0,
4,
0);
1190 return
\"STE %
1,%
0\";
1192 mvs_check_page (
0,
4,
0);
1193 return
\"ST %
1,%
0\";
1197 ; movstrsi instruction pattern(s).
1200 (define_expand "movstrsi"
1201 [(set (match_operand:BLK
0 "general_operand" "")
1202 (match_operand:BLK
1 "general_operand" ""))
1203 (use (match_operand:SI
2 "general_operand" ""))
1204 (match_operand
3 "" "")]
1210 op0 = XEXP (operands[
0],
0);
1211 if (GET_CODE (op0) == REG
1212 || (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0,
0)) == REG
1213 && GET_CODE (XEXP (op0,
1)) == CONST_INT
1214 && (unsigned) INTVAL (XEXP (op0,
1)) <
4096))
1220 op0 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op0));
1223 op1 = XEXP (operands[
1],
0);
1224 if (GET_CODE (op1) == REG
1225 || (GET_CODE (op1) == PLUS && GET_CODE (XEXP (op1,
0)) == REG
1226 && GET_CODE (XEXP (op1,
1)) == CONST_INT
1227 && (unsigned) INTVAL (XEXP (op1,
1)) <
4096))
1233 op1 = gen_rtx (MEM, BLKmode, copy_to_mode_reg (SImode, op1));
1236 if (GET_CODE (operands[
2]) == CONST_INT && INTVAL (operands[
2]) <
256)
1238 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (
2,
1239 gen_rtx (SET, VOIDmode, op0, op1),
1240 gen_rtx (USE, VOIDmode, operands[
2]))));
1244 rtx reg1 = gen_reg_rtx (DImode);
1245 rtx reg2 = gen_reg_rtx (DImode);
1246 rtx subreg = gen_rtx (SUBREG, SImode, reg1,
1);
1248 emit_insn (gen_rtx (SET, VOIDmode, subreg, operands[
2]));
1249 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (SUBREG, SImode, reg2,
1),
1251 emit_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (
5,
1252 gen_rtx (SET, VOIDmode, op0, op1),
1253 gen_rtx (USE, VOIDmode, reg1),
1254 gen_rtx (USE, VOIDmode, reg2),
1255 gen_rtx (CLOBBER, VOIDmode, reg1),
1256 gen_rtx (CLOBBER, VOIDmode, reg2))));
1261 ; Move a block that is less than
256 bytes in length.
1264 [(set (match_operand:BLK
0 "s_operand" "=m")
1265 (match_operand:BLK
1 "s_operand" "m"))
1266 (use (match_operand
2 "immediate_operand" "I"))]
1267 "((unsigned) INTVAL (operands[
2]) <
256)"
1270 check_label_emit ();
1271 mvs_check_page (
0,
6,
0);
1272 return
\"MVC %O0(%c2,%R0),%
1\";
1275 ; Move a block that is larger than
255 bytes in length.
1278 [(set (match_operand:BLK
0 "general_operand" "=m")
1279 (match_operand:BLK
1 "general_operand" "m"))
1280 (use (match_operand:DI
2 "register_operand" "d"))
1281 (use (match_operand:DI
3 "register_operand" "d"))
1282 (clobber (match_dup
2))
1283 (clobber (match_dup
3))]
1287 check_label_emit ();
1288 mvs_check_page (
0,
10,
0);
1289 return
\"LA %
2,%
0\;LA %
3,%
1\;MVCL %
2,%
3\";
1293 ;;- Conversion instructions.
1297 ; extendsidi2 instruction pattern(s).
1300 (define_expand "extendsidi2"
1301 [(set (match_operand:DI
0 "general_operand" "")
1302 (sign_extend:DI (match_operand:SI
1 "general_operand" "")))]
1306 if (GET_CODE (operands[
1]) != CONST_INT)
1308 emit_insn (gen_rtx (SET, VOIDmode,
1309 operand_subword (operands[
0],
0,
1, DImode), operands[
1]));
1310 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
1311 gen_rtx (ASHIFTRT, DImode, operands[
0],
1312 gen_rtx (CONST_INT, SImode,
32))));
1316 if (INTVAL (operands[
1]) <
0)
1318 emit_insn (gen_rtx (SET, VOIDmode,
1319 operand_subword (operands[
0],
0,
1, DImode),
1320 gen_rtx (CONST_INT, SImode, -
1)));
1324 emit_insn (gen_rtx (SET, VOIDmode,
1325 operand_subword (operands[
0],
0,
1, DImode),
1326 gen_rtx (CONST_INT, SImode,
0)));
1328 emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (SImode, operands[
0]),
1335 ; extendhisi2 instruction pattern(s).
1338 (define_insn "extendhisi2"
1339 [(set (match_operand:SI
0 "general_operand" "=d,m")
1340 (sign_extend:SI (match_operand:HI
1 "general_operand" "g,d")))]
1344 check_label_emit ();
1345 if (REG_P (operands[
0]))
1347 if (REG_P (operands[
1]))
1348 if (REGNO (operands[
0]) != REGNO (operands[
1]))
1350 mvs_check_page (
0,
2,
0);
1351 return
\"LR %
0,%
1\;SLL %
0,
16\;SRA %
0,
16\";
1354 return
\"\"; /* Should be empty.
16-bits regs are always
32-bits. */
1355 if (operands[
1] == const0_rtx)
1358 mvs_check_page (
0,
2,
0);
1359 return
\"SLR %
0,%
0\";
1361 if (GET_CODE (operands[
1]) == CONST_INT
1362 && (unsigned) INTVAL (operands[
1]) <
4096)
1364 mvs_check_page (
0,
4,
0);
1365 return
\"LA %
0,%c1
\";
1367 if (GET_CODE (operands[
1]) == CONST_INT)
1369 mvs_check_page (
0,
4,
2);
1370 return
\"LH %
0,=H'%h1'
\";
1372 mvs_check_page (
0,
4,
0);
1373 return
\"LH %
0,%
1\";
1375 mvs_check_page (
0,
4,
0);
1376 return
\"SLL %
0,
16\;SRA %
0,
16\;ST %
1,%
0\";
1380 ; extendqisi2 instruction pattern(s).
1383 (define_insn "extendqisi2"
1384 [(set (match_operand:SI
0 "general_operand" "=d")
1385 (sign_extend:SI (match_operand:QI
1 "general_operand" "
0mi")))]
1389 check_label_emit ();
1390 CC_STATUS_SET (operands[
0], operands[
1]);
1391 if (REG_P (operands[
1]))
1393 mvs_check_page (
0,
8,
0);
1394 return
\"SLL %
0,
24\;SRA %
0,
24\";
1396 if (s_operand (operands[
1]))
1398 mvs_check_page (
0,
8,
0);
1399 return
\"ICM %
0,
8,%
1\;SRA %
0,
24\";
1401 mvs_check_page (
0,
12,
0);
1402 return
\"IC %
0,%
1\;SLL %
0,
24\;SRA %
0,
24\";
1406 ; extendqihi2 instruction pattern(s).
1409 (define_insn "extendqihi2"
1410 [(set (match_operand:HI
0 "general_operand" "=d")
1411 (sign_extend:HI (match_operand:QI
1 "general_operand" "
0m")))]
1415 check_label_emit ();
1416 CC_STATUS_SET (operands[
0], operands[
1]);
1417 if (REG_P (operands[
1]))
1419 mvs_check_page (
0,
8,
0);
1420 return
\"SLL %
0,
24\;SRA %
0,
24\";
1422 if (s_operand (operands[
1]))
1424 mvs_check_page (
0,
8,
0);
1425 return
\"ICM %
0,
8,%
1\;SRA %
0,
24\";
1427 mvs_check_page (
0,
12,
0);
1428 return
\"IC %
0,%
1\;SLL %
0,
24\;SRA %
0,
24\";
1432 ; zero_extendsidi2 instruction pattern(s).
1435 (define_expand "zero_extendsidi2"
1436 [(set (match_operand:DI
0 "general_operand" "")
1437 (zero_extend:DI (match_operand:SI
1 "general_operand" "")))]
1441 emit_insn (gen_rtx (SET, VOIDmode,
1442 operand_subword (operands[
0],
0,
1, DImode), operands[
1]));
1443 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
1444 gen_rtx (LSHIFTRT, DImode, operands[
0],
1445 gen_rtx (CONST_INT, SImode,
32))));
1450 ; zero_extendhisi2 instruction pattern(s).
1453 (define_insn "zero_extendhisi2"
1454 [(set (match_operand:SI
0 "general_operand" "=d")
1455 (zero_extend:SI (match_operand:HI
1 "general_operand" "
0")))]
1459 check_label_emit ();
1460 CC_STATUS_SET (operands[
0], operands[
1]);
1461 mvs_check_page (
0,
4,
4);
1462 return
\"N %
1,=X'
0000FFFF'
\";
1466 ; zero_extendqisi2 instruction pattern(s).
1469 (define_insn "zero_extendqisi2"
1470 [(set (match_operand:SI
0 "general_operand" "=d,&d")
1471 (zero_extend:SI (match_operand:QI
1 "general_operand" "
0i,m")))]
1475 check_label_emit ();
1476 if (REG_P (operands[
1]))
1478 CC_STATUS_SET (operands[
0], operands[
1]);
1479 mvs_check_page (
0,
4,
4);
1480 return
\"N %
0,=X'
000000FF'
\";
1482 if (GET_CODE (operands[
1]) == CONST_INT)
1484 mvs_check_page (
0,
4,
0);
1485 return
\"LA %
0,%c1
\";
1488 mvs_check_page (
0,
8,
0);
1489 return
\"SLR %
0,%
0\;IC %
0,%
1\";
1493 ; zero_extendqihi2 instruction pattern(s).
1496 (define_insn "zero_extendqihi2"
1497 [(set (match_operand:HI
0 "general_operand" "=d,&d")
1498 (zero_extend:HI (match_operand:QI
1 "general_operand" "
0i,m")))]
1502 check_label_emit ();
1503 if (REG_P (operands[
1]))
1505 CC_STATUS_SET (operands[
0], operands[
1]);
1506 mvs_check_page (
0,
4,
4);
1507 return
\"N %
0,=X'
000000FF'
\";
1509 if (GET_CODE (operands[
1]) == CONST_INT)
1511 mvs_check_page (
0,
4,
0);
1512 return
\"LA %
0,%c1
\";
1515 mvs_check_page (
0,
8,
0);
1516 return
\"SLR %
0,%
0\;IC %
0,%
1\";
1520 ; truncsihi2 instruction pattern(s).
1523 (define_insn "truncsihi2"
1524 [(set (match_operand:HI
0 "general_operand" "=d,m")
1525 (truncate:HI (match_operand:SI
1 "general_operand" "
0,d")))]
1529 check_label_emit ();
1530 if (REG_P (operands[
0]))
1532 CC_STATUS_SET (operands[
0], operands[
1]);
1533 mvs_check_page (
0,
8,
0);
1534 return
\"SLL %
0,
16\;SRA %
0,
16\";
1536 mvs_check_page (
0,
4,
0);
1537 return
\"STH %
1,%
0\";
1541 ; fix_truncdfsi2 instruction pattern(s).
1544 (define_insn "fix_truncdfsi2"
1545 [(set (match_operand:SI
0 "general_operand" "=d")
1546 (fix:SI (truncate:DF (match_operand:DF
1 "general_operand" "f"))))
1547 (clobber (reg:DF
16))]
1551 check_label_emit ();
1553 if (REGNO (operands[
1]) ==
16)
1555 mvs_check_page (
0,
12,
8);
1556 return
\"AD
0,=XL8'
4F08000000000000'\;STD
0,
140(,
13)\;L %
0,
144(,
13)
\";
1558 mvs_check_page (
0,
14,
8);
1559 return
\"LDR
0,%
1\;AD
0,=XL8'
4F08000000000000'\;STD
0,
140(,
13)\;L %
0,
144(,
13)
\";
1563 ; floatsidf2 instruction pattern(s).
1565 ; Uses the float field of the TCA.
1568 (define_insn "floatsidf2"
1569 [(set (match_operand:DF
0 "general_operand" "=f")
1570 (float:DF (match_operand:SI
1 "general_operand" "d")))]
1574 check_label_emit ();
1576 mvs_check_page (
0,
16,
8);
1577 return
\"ST %
1,
508(,
12)\;XI
508(
12),
128\;LD %
0,
504(,
12)\;SD %
0,=XL8'
4E00000080000000'
\";
1581 ; truncdfsf2 instruction pattern(s).
1584 (define_insn "truncdfsf2"
1585 [(set (match_operand:SF
0 "general_operand" "=f")
1586 (float_truncate:SF (match_operand:DF
1 "general_operand" "f")))]
1590 check_label_emit ();
1591 mvs_check_page (
0,
2,
0);
1592 return
\"LRER %
0,%
1\";
1596 ; extendsfdf2 instruction pattern(s).
1599 (define_insn "extendsfdf2"
1600 [(set (match_operand:DF
0 "general_operand" "=f")
1601 (float_extend:DF (match_operand:SF
1 "general_operand" "fmF")))]
1605 check_label_emit ();
1606 CC_STATUS_SET (
0, const0_rtx);
1607 if (FP_REG_P (operands[
1]))
1609 if (REGNO (operands[
0]) == REGNO (operands[
1]))
1611 mvs_check_page (
0,
10,
0);
1612 return
\"STE %
1,
140(,
13)\;SDR %
0,%
0\;LE %
0,
140(,
13)
\";
1614 mvs_check_page (
0,
4,
0);
1615 return
\"SDR %
0,%
0\;LER %
0,%
1\";
1617 mvs_check_page (
0,
6,
0);
1618 return
\"SDR %
0,%
0\;LE %
0,%
1\";
1622 ;;- Add instructions.
1626 ; adddi3 instruction pattern(s).
1629 (define_expand "adddi3"
1630 [(set (match_operand:DI
0 "general_operand" "")
1631 (plus:DI (match_operand:DI
1 "general_operand" "")
1632 (match_operand:DI
2 "general_operand" "")))]
1636 rtx label = gen_label_rtx ();
1637 rtx op0_high = operand_subword (operands[
0],
0,
1, DImode);
1638 rtx op0_low = gen_lowpart (SImode, operands[
0]);
1640 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1641 gen_rtx (PLUS, SImode,
1642 operand_subword (operands[
1],
0,
1, DImode),
1643 operand_subword (operands[
2],
0,
1, DImode))));
1644 emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (
2,
1645 gen_rtx (SET, VOIDmode, op0_low,
1646 gen_rtx (PLUS, SImode, gen_lowpart (SImode, operands[
1]),
1647 gen_lowpart (SImode, operands[
2]))),
1648 gen_rtx (USE, VOIDmode, gen_rtx (LABEL_REF, VOIDmode, label)))));
1649 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1650 gen_rtx (PLUS, SImode, op0_high,
1651 gen_rtx (CONST_INT, SImode,
1))));
1657 [(set (match_operand:SI
0 "general_operand" "=d")
1658 (plus:SI (match_operand:SI
1 "general_operand" "%
0")
1659 (match_operand:SI
2 "general_operand" "g")))
1660 (use (label_ref (match_operand
3 "" "")))]
1666 check_label_emit ();
1667 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[
3]));
1668 if (REG_P (operands[
2]))
1672 mvs_check_page (
0,
8,
4);
1673 return
\"ALR %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1675 if (mvs_check_page (
0,
6,
0))
1677 mvs_check_page (
0,
2,
4);
1678 return
\"ALR %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1680 return
\"ALR %
0,%
2\;BC
12,%l3
\";
1684 mvs_check_page (
0,
10,
4);
1685 return
\"AL %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1687 if (mvs_check_page (
0,
8 ,
0))
1689 mvs_check_page (
0,
2,
4);
1690 return
\"AL %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1692 return
\"AL %
0,%
2\;BC
12,%l3
\";
1696 ; addsi3 instruction pattern(s).
1698 ; The following insn is used when it is known that operand one is an address,
1699 ; frame, stack or argument pointer, and operand two is a constant that is
1700 ; small enough to fit in the displacement field.
1701 ; Notice that we can't allow the frame pointer to used as a normal register
1702 ; because of this insn.
1706 [(set (match_operand:SI
0 "register_operand" "=d")
1707 (plus:SI (match_operand:SI
1 "general_operand" "%a")
1708 (match_operand:SI
2 "immediate_operand" "J")))]
1709 "((REGNO (operands[
1]) == FRAME_POINTER_REGNUM || REGNO (operands[
1]) == ARG_POINTER_REGNUM || REGNO (operands[
1]) == STACK_POINTER_REGNUM) && (unsigned) INTVAL (operands[
2]) <
4096)"
1712 check_label_emit ();
1714 mvs_check_page (
0,
4,
0);
1715 return
\"LA %
0,%c2(,%
1)
\";
1718 ; This insn handles additions that are relative to the frame pointer.
1721 [(set (match_operand:SI
0 "register_operand" "=d")
1722 (plus:SI (match_operand:SI
1 "register_operand" "%a")
1723 (match_operand:SI
2 "immediate_operand" "i")))]
1724 "REGNO (operands[
1]) == FRAME_POINTER_REGNUM"
1727 check_label_emit ();
1728 if ((unsigned) INTVAL (operands[
2]) <
4096)
1730 mvs_check_page (
0,
4,
0);
1731 return
\"LA %
0,%c2(,%
1)
\";
1733 if (REGNO (operands[
1]) == REGNO (operands[
0]))
1735 mvs_check_page (
0,
4,
0);
1738 mvs_check_page (
0,
6,
0);
1739 return
\"L %
0,%
2\;AR %
0,%
1\";
1742 (define_insn "addsi3"
1743 [(set (match_operand:SI
0 "general_operand" "=d")
1744 (plus:SI (match_operand:SI
1 "general_operand" "%
0")
1745 (match_operand:SI
2 "general_operand" "g")))]
1749 check_label_emit ();
1750 if (REG_P (operands[
2]))
1752 mvs_check_page (
0,
2,
0);
1753 return
\"AR %
0,%
2\";
1755 if (GET_CODE (operands[
2]) == CONST_INT)
1757 if (INTVAL (operands[
2]) == -
1)
1760 mvs_check_page (
0,
2,
0);
1761 return
\"BCTR %
0,
0\";
1764 mvs_check_page (
0,
4,
0);
1769 ; addhi3 instruction pattern(s).
1772 (define_insn "addhi3"
1773 [(set (match_operand:HI
0 "general_operand" "=d")
1774 (plus:HI (match_operand:HI
1 "general_operand" "%
0")
1775 (match_operand:HI
2 "general_operand" "dmi")))]
1779 check_label_emit ();
1780 if (REG_P (operands[
2]))
1782 mvs_check_page (
0,
2,
0);
1783 return
\"STH %
2,
140(,
13)\;AH %
0,
140(,
13)
\";
1785 if (GET_CODE (operands[
2]) == CONST_INT)
1787 if (INTVAL (operands[
2]) == -
1)
1790 mvs_check_page (
0,
2,
0);
1791 return
\"BCTR %
0,
0\";
1793 mvs_check_page (
0,
4,
2);
1794 return
\"AH %
0,=H'%h2'
\";
1796 mvs_check_page (
0,
4,
0);
1797 return
\"AH %
0,%
2\";
1801 ; addqi3 instruction pattern(s).
1804 (define_insn "addqi3"
1805 [(set (match_operand:QI
0 "general_operand" "=d")
1806 (plus:QI (match_operand:QI
1 "general_operand" "%a")
1807 (match_operand:QI
2 "general_operand" "ai")))]
1811 check_label_emit ();
1813 mvs_check_page (
0,
4,
0);
1814 if (REG_P (operands[
2]))
1815 return
\"LA %
0,
0(%
1,%
2)
\";
1816 return
\"LA %
0,%B2(,%
1)
\";
1820 ; adddf3 instruction pattern(s).
1823 (define_insn "adddf3"
1824 [(set (match_operand:DF
0 "general_operand" "=f")
1825 (plus:DF (match_operand:DF
1 "general_operand" "%
0")
1826 (match_operand:DF
2 "general_operand" "fmF")))]
1830 check_label_emit ();
1831 if (FP_REG_P (operands[
2]))
1833 mvs_check_page (
0,
2,
0);
1834 return
\"ADR %
0,%
2\";
1836 mvs_check_page (
0,
4,
0);
1837 return
\"AD %
0,%
2\";
1841 ; addsf3 instruction pattern(s).
1844 (define_insn "addsf3"
1845 [(set (match_operand:SF
0 "general_operand" "=f")
1846 (plus:SF (match_operand:SF
1 "general_operand" "%
0")
1847 (match_operand:SF
2 "general_operand" "fmF")))]
1851 check_label_emit ();
1852 if (FP_REG_P (operands[
2]))
1854 mvs_check_page (
0,
2,
0);
1855 return
\"AER %
0,%
2\";
1857 mvs_check_page (
0,
4,
0);
1858 return
\"AE %
0,%
2\";
1862 ;;- Subtract instructions.
1866 ; subdi3 instruction pattern(s).
1869 (define_expand "subdi3"
1870 [(set (match_operand:DI
0 "general_operand" "")
1871 (minus:DI (match_operand:DI
1 "general_operand" "")
1872 (match_operand:DI
2 "general_operand" "")))]
1876 rtx label = gen_label_rtx ();
1877 rtx op0_high = operand_subword (operands[
0],
0,
1, DImode);
1878 rtx op0_low = gen_lowpart (SImode, operands[
0]);
1880 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1881 gen_rtx (MINUS, SImode,
1882 operand_subword (operands[
1],
0,
1, DImode),
1883 operand_subword (operands[
2],
0,
1, DImode))));
1884 emit_jump_insn (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (
2,
1885 gen_rtx (SET, VOIDmode, op0_low,
1886 gen_rtx (MINUS, SImode,
1887 gen_lowpart (SImode, operands[
1]),
1888 gen_lowpart (SImode, operands[
2]))),
1889 gen_rtx (USE, VOIDmode,
1890 gen_rtx (LABEL_REF, VOIDmode, label)))));
1891 emit_insn (gen_rtx (SET, VOIDmode, op0_high,
1892 gen_rtx (MINUS, SImode, op0_high,
1893 gen_rtx (CONST_INT, SImode,
1))));
1899 [(set (match_operand:SI
0 "general_operand" "=d")
1900 (minus:SI (match_operand:SI
1 "general_operand" "
0")
1901 (match_operand:SI
2 "general_operand" "g")))
1902 (use (label_ref (match_operand
3 "" "")))]
1908 check_label_emit ();
1910 onpage = mvs_check_label (CODE_LABEL_NUMBER (operands[
3]));
1911 if (REG_P (operands[
2]))
1915 mvs_check_page (
0,
8,
4);
1916 return
\"SLR %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1918 if (mvs_check_page (
0,
6,
0))
1920 mvs_check_page (
0,
2,
4);
1921 return
\"SLR %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1923 return
\"SLR %
0,%
2\;BC
12,%l3
\";
1927 mvs_check_page (
0,
10,
4);
1928 return
\"SL %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1930 if (mvs_check_page (
0,
8,
0))
1932 mvs_check_page (
0,
2,
4);
1933 return
\"SL %
0,%
2\;L
14,=A(%l3)\;BCR
12,
14\";
1935 return
\"SL %
0,%
2\;BC
12,%l3
\";
1939 ; subsi3 instruction pattern(s).
1942 (define_insn "subsi3"
1943 [(set (match_operand:SI
0 "general_operand" "=d")
1944 (minus:SI (match_operand:SI
1 "general_operand" "
0")
1945 (match_operand:SI
2 "general_operand" "g")))]
1949 check_label_emit ();
1950 if (REG_P (operands[
2]))
1952 mvs_check_page (
0,
2,
0);
1953 return
\"SR %
0,%
2\";
1955 if (operands[
2] == const1_rtx)
1958 mvs_check_page (
0,
2,
0);
1959 return
\"BCTR %
0,
0\";
1961 mvs_check_page (
0,
4,
0);
1966 ; subhi3 instruction pattern(s).
1969 (define_insn "subhi3"
1970 [(set (match_operand:HI
0 "general_operand" "=d")
1971 (minus:HI (match_operand:HI
1 "general_operand" "
0")
1972 (match_operand:HI
2 "general_operand" "g")))]
1976 check_label_emit ();
1977 if (REG_P (operands[
2]))
1979 mvs_check_page (
0,
2,
0);
1980 return
\"STH %
2,
140(,
13)\;SH %
0,
140(,
13)
\";
1982 if (operands[
2] == const1_rtx)
1985 mvs_check_page (
0,
2,
0);
1986 return
\"BCTR %
0,
0\";
1988 if (GET_CODE (operands[
2]) == CONST_INT)
1990 mvs_check_page (
0,
4,
2);
1991 return
\"SH %
0,=H'%h2'
\";
1993 mvs_check_page (
0,
4,
0);
1994 return
\"SH %
0,%
2\";
1998 ; subqi3 instruction pattern(s).
2001 (define_expand "subqi3"
2002 [(set (match_operand:QI
0 "general_operand" "=d")
2003 (minus:QI (match_operand:QI
1 "general_operand" "
0")
2004 (match_operand:QI
2 "general_operand" "di")))]
2008 if (REG_P (operands[
2]))
2010 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
2011 gen_rtx (MINUS, QImode, operands[
1], operands[
2])));
2015 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
2016 gen_rtx (PLUS, QImode, operands[
1],
2017 negate_rtx (QImode, operands[
2]))));
2023 [(set (match_operand:QI
0 "register_operand" "=d")
2024 (minus:QI (match_operand:QI
1 "register_operand" "
0")
2025 (match_operand:QI
2 "register_operand" "d")))]
2029 check_label_emit ();
2031 mvs_check_page (
0,
2,
0);
2032 return
\"SR %
0,%
2\";
2036 ; subdf3 instruction pattern(s).
2039 (define_insn "subdf3"
2040 [(set (match_operand:DF
0 "general_operand" "=f")
2041 (minus:DF (match_operand:DF
1 "general_operand" "
0")
2042 (match_operand:DF
2 "general_operand" "fmF")))]
2046 check_label_emit ();
2047 if (FP_REG_P (operands[
2]))
2049 mvs_check_page (
0,
2,
0);
2050 return
\"SDR %
0,%
2\";
2052 mvs_check_page (
0,
4,
0);
2053 return
\"SD %
0,%
2\";
2057 ; subsf3 instruction pattern(s).
2060 (define_insn "subsf3"
2061 [(set (match_operand:SF
0 "general_operand" "=f")
2062 (minus:SF (match_operand:SF
1 "general_operand" "
0")
2063 (match_operand:SF
2 "general_operand" "fmF")))]
2067 check_label_emit ();
2068 if (FP_REG_P (operands[
2]))
2070 mvs_check_page (
0,
2,
0);
2071 return
\"SER %
0,%
2\";
2073 mvs_check_page (
0,
4,
0);
2074 return
\"SE %
0,%
2\";
2078 ;;- Multiply instructions.
2082 ; mulsi3 instruction pattern(s).
2085 (define_expand "mulsi3"
2086 [(set (match_operand:SI
0 "general_operand" "")
2087 (mult:SI (match_operand:SI
1 "general_operand" "")
2088 (match_operand:SI
2 "general_operand" "")))]
2092 if (GET_CODE (operands[
1]) == CONST_INT
2093 && CONST_OK_FOR_LETTER_P (INTVAL (operands[
1]), 'K'))
2095 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
2096 gen_rtx (MULT, SImode, operands[
2], operands[
1])));
2098 else if (GET_CODE (operands[
2]) == CONST_INT
2099 && CONST_OK_FOR_LETTER_P (INTVAL (operands[
2]), 'K'))
2101 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
2102 gen_rtx (MULT, SImode, operands[
1], operands[
2])));
2106 rtx r = gen_reg_rtx (DImode);
2108 emit_insn (gen_rtx (SET, VOIDmode,
2109 gen_rtx (SUBREG, SImode, r,
1), operands[
1]));
2110 emit_insn (gen_rtx (SET, VOIDmode, r,
2111 gen_rtx (MULT, SImode, r, operands[
2])));
2112 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
2113 gen_rtx (SUBREG, SImode, r,
1)));
2119 [(set (match_operand:SI
0 "register_operand" "=d")
2120 (mult:SI (match_operand:SI
1 "general_operand" "%
0")
2121 (match_operand:SI
2 "immediate_operand" "K")))]
2125 check_label_emit ();
2126 mvs_check_page (
0,
4,
0);
2127 return
\"MH %
0,%
2\";
2131 [(set (match_operand:DI
0 "register_operand" "=d")
2132 (mult:SI (match_operand:DI
1 "general_operand" "%
0")
2133 (match_operand:SI
2 "general_operand" "g")))]
2137 check_label_emit ();
2138 if (REG_P (operands[
2]))
2140 mvs_check_page (
0,
2,
0);
2141 return
\"MR %
0,%
2\";
2143 mvs_check_page (
0,
4,
0);
2148 ; muldf3 instruction pattern(s).
2151 (define_insn "muldf3"
2152 [(set (match_operand:DF
0 "general_operand" "=f")
2153 (mult:DF (match_operand:DF
1 "general_operand" "%
0")
2154 (match_operand:DF
2 "general_operand" "fmF")))]
2158 check_label_emit ();
2159 if (FP_REG_P (operands[
2]))
2161 mvs_check_page (
0,
2,
0);
2162 return
\"MDR %
0,%
2\";
2164 mvs_check_page (
0,
4,
0);
2165 return
\"MD %
0,%
2\";
2169 ; mulsf3 instruction pattern(s).
2172 (define_insn "mulsf3"
2173 [(set (match_operand:SF
0 "general_operand" "=f")
2174 (mult:SF (match_operand:SF
1 "general_operand" "%
0")
2175 (match_operand:SF
2 "general_operand" "fmF")))]
2179 check_label_emit ();
2180 if (FP_REG_P (operands[
2]))
2182 mvs_check_page (
0,
2,
0);
2183 return
\"MER %
0,%
2\";
2185 mvs_check_page (
0,
4,
0);
2186 return
\"ME %
0,%
2\";
2190 ;;- Divide instructions.
2194 ; divsi3 instruction pattern(s).
2197 (define_expand "divsi3"
2198 [(set (match_operand:SI
0 "general_operand" "")
2199 (div:SI (match_operand:SI
1 "general_operand" "")
2200 (match_operand:SI
2 "general_operand" "")))]
2204 rtx r = gen_reg_rtx (DImode);
2206 emit_insn (gen_extendsidi2 (r, operands[
1]));
2207 emit_insn (gen_rtx (SET, VOIDmode, r,
2208 gen_rtx (DIV, SImode, r, operands[
2])));
2209 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
2210 gen_rtx (SUBREG, SImode, r,
1)));
2216 ; udivsi3 instruction pattern(s).
2219 (define_expand "udivsi3"
2220 [(set (match_operand:SI
0 "general_operand" "")
2221 (udiv:SI (match_operand:SI
1 "general_operand" "")
2222 (match_operand:SI
2 "general_operand" "")))]
2226 rtx dr = gen_reg_rtx (DImode);
2227 rtx dr_0 = gen_rtx (SUBREG, SImode, dr,
0);
2228 rtx dr_1 = gen_rtx (SUBREG, SImode, dr,
1);
2231 if (GET_CODE (operands[
2]) == CONST_INT)
2233 if (INTVAL (operands[
2]) >
0)
2235 emit_insn (gen_zero_extendsidi2 (dr, operands[
1]));
2236 emit_insn (gen_rtx (SET, VOIDmode, dr,
2237 gen_rtx (DIV, SImode, dr, operands[
2])));
2241 rtx label1 = gen_label_rtx ();
2243 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[
1]));
2244 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx));
2245 emit_insn (gen_cmpsi (dr_0, operands[
2]));
2246 emit_jump_insn (gen_bltu (label1));
2247 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx));
2248 emit_label (label1);
2253 rtx label1 = gen_label_rtx ();
2254 rtx label2 = gen_label_rtx ();
2255 rtx label3 = gen_label_rtx ();
2256 rtx sr = gen_reg_rtx (SImode);
2258 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[
1]));
2259 emit_insn (gen_rtx (SET, VOIDmode, sr, operands[
2]));
2260 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const0_rtx));
2261 emit_insn (gen_cmpsi (sr, dr_0));
2262 emit_jump_insn (gen_bgtu (label3));
2263 emit_insn (gen_cmpsi (sr, const1_rtx));
2264 emit_jump_insn (gen_blt (label2));
2265 emit_jump_insn (gen_beq (label1));
2266 emit_insn (gen_rtx (SET, VOIDmode, dr,
2267 gen_rtx (LSHIFTRT, DImode, dr,
2268 gen_rtx (CONST_INT, SImode,
32))));
2269 emit_insn (gen_rtx (SET, VOIDmode, dr,
2270 gen_rtx (DIV, SImode, dr, sr)));
2271 emit_jump_insn (gen_jump (label3));
2272 emit_label (label1);
2273 emit_insn (gen_rtx (SET, VOIDmode, dr_1, dr_0));
2274 emit_jump_insn (gen_jump (label3));
2275 emit_label (label2);
2276 emit_insn (gen_rtx (SET, VOIDmode, dr_1, const1_rtx));
2277 emit_label (label3);
2279 emit_insn (gen_rtx (SET, VOIDmode, operands[
0], dr_1));
2284 ; This is used by divsi3 & udivsi3.
2287 [(set (match_operand:DI
0 "register_operand" "=d")
2288 (div:SI (match_operand:DI
1 "register_operand" "
0")
2289 (match_operand:SI
2 "general_operand" "")))]
2293 check_label_emit ();
2294 if (REG_P (operands[
2]))
2296 mvs_check_page (
0,
2,
0);
2297 return
\"DR %
0,%
2\";
2299 mvs_check_page (
0,
4,
0);
2304 ; divdf3 instruction pattern(s).
2307 (define_insn "divdf3"
2308 [(set (match_operand:DF
0 "general_operand" "=f")
2309 (div:DF (match_operand:DF
1 "general_operand" "
0")
2310 (match_operand:DF
2 "general_operand" "fmF")))]
2314 check_label_emit ();
2315 if (FP_REG_P (operands[
2]))
2317 mvs_check_page (
0,
2,
0);
2318 return
\"DDR %
0,%
2\";
2320 mvs_check_page (
0,
4,
0);
2321 return
\"DD %
0,%
2\";
2325 ; divsf3 instruction pattern(s).
2328 (define_insn "divsf3"
2329 [(set (match_operand:SF
0 "general_operand" "=f")
2330 (div:SF (match_operand:SF
1 "general_operand" "
0")
2331 (match_operand:SF
2 "general_operand" "fmF")))]
2335 check_label_emit ();
2336 if (FP_REG_P (operands[
2]))
2338 mvs_check_page (
0,
2,
0);
2339 return
\"DER %
0,%
2\";
2341 mvs_check_page (
0,
4,
0);
2342 return
\"DE %
0,%
2\";
2346 ;;- Modulo instructions.
2350 ; modsi3 instruction pattern(s).
2353 (define_expand "modsi3"
2354 [(set (match_operand:SI
0 "general_operand" "")
2355 (mod:SI (match_operand:SI
1 "general_operand" "")
2356 (match_operand:SI
2 "general_operand" "")))]
2360 rtx r = gen_reg_rtx (DImode);
2362 emit_insn (gen_extendsidi2 (r, operands[
1]));
2363 emit_insn (gen_rtx (SET, VOIDmode, r,
2364 gen_rtx (MOD, SImode, r, operands[
2])));
2365 emit_insn (gen_rtx (SET, VOIDmode, operands[
0],
2366 gen_rtx (SUBREG, SImode, r,
0)));
2371 ; umodsi3 instruction pattern(s).
2374 (define_expand "umodsi3"
2375 [(set (match_operand:SI
0 "general_operand" "")
2376 (umod:SI (match_operand:SI
1 "general_operand" "")
2377 (match_operand:SI
2 "general_operand" "")))]
2381 rtx dr = gen_reg_rtx (DImode);
2382 rtx dr_0 = gen_rtx (SUBREG, SImode, dr,
0);
2383 rtx dr_1 = gen_rtx (SUBREG, SImode, dr,
1);
2385 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[
1]));
2387 if (GET_CODE (operands[
2]) == CONST_INT)
2389 if (INTVAL (operands[
2]) >
0)
2391 emit_insn (gen_rtx (SET, VOIDmode, dr,
2392 gen_rtx (LSHIFTRT, DImode, dr,
2393 gen_rtx (CONST_INT, SImode,
32))));
2394 emit_insn (gen_rtx (SET, VOIDmode, dr,
2395 gen_rtx (MOD, SImode, dr, operands[
2])));
2399 rtx label1 = gen_label_rtx ();
2400 rtx sr = gen_reg_rtx (SImode);
2402 emit_insn (gen_rtx (SET, VOIDmode, sr, operands[
2]));
2403 emit_insn (gen_cmpsi (dr_0, sr));
2404 emit_jump_insn (gen_bltu (label1));
2405 emit_insn (gen_rtx (SET, VOIDmode, sr, gen_rtx (ABS, SImode, sr)));
2406 emit_insn (gen_rtx (SET, VOIDmode, dr_0,
2407 gen_rtx (PLUS, SImode, dr_0, sr)));
2408 emit_label (label1);
2413 rtx label1 = gen_label_rtx ();
2414 rtx label2 = gen_label_rtx ();
2415 rtx label3 = gen_label_rtx ();
2416 rtx sr = gen_reg_rtx (SImode);
2418 emit_insn (gen_rtx (SET, VOIDmode, dr_0, operands[
1]));
2419 emit_insn (gen_rtx (SET, VOIDmode, sr, operands[
2]));
2420 emit_insn (gen_cmpsi (sr, dr_0));
2421 emit_jump_insn (gen_bgtu (label3));
2422 emit_insn (gen_cmpsi (sr, const1_rtx));
2423 emit_jump_insn (gen_blt (label2));
2424 emit_jump_insn (gen_beq (label1));
2425 emit_insn (gen_rtx (SET, VOIDmode, dr,
2426 gen_rtx (LSHIFTRT, DImode, dr,
2427 gen_rtx (CONST_INT, SImode,
32))));
2428 emit_insn (gen_rtx (SET, VOIDmode, dr, gen_rtx (MOD, SImode, dr, sr)));
2429 emit_jump_insn (gen_jump (label3));
2430 emit_label (label1);
2431 emit_insn (gen_rtx (SET, VOIDmode, dr_0, const0_rtx));
2432 emit_jump_insn (gen_jump (label3));
2433 emit_label (label2);
2434 emit_insn (gen_rtx (SET, VOIDmode, dr_0,
2435 gen_rtx (MINUS, SImode, dr_0, sr)));
2436 emit_label (label3);
2439 emit_insn (gen_rtx (SET, VOIDmode, operands[
0], dr_0));
2444 ; This is used by modsi3 & umodsi3.
2447 [(set (match_operand:DI
0 "register_operand" "=d")
2448 (mod:SI (match_operand:DI
1 "register_operand" "
0")
2449 (match_operand:SI
2 "general_operand" "")))]
2453 check_label_emit ();
2454 if (REG_P (operands[
2]))
2456 mvs_check_page (
0,
2,
0);
2457 return
\"DR %
0,%
2\";
2459 mvs_check_page (
0,
4,
0);
2464 ;;- And instructions.
2468 ; anddi3 instruction pattern(s).
2471 ;(define_expand "anddi3"
2472 ; [(set (match_operand:DI
0 "general_operand" "")
2473 ; (and:DI (match_operand:DI
1 "general_operand" "")
2474 ; (match_operand:DI
2 "general_operand" "")))]
2480 ; emit_insn (gen_andsi3 (operand_subword (operands[
0],
0,
1, DImode),
2481 ; operand_subword (operands[
1],
0,
1, DImode),
2482 ; operand_subword (operands[
2],
0,
1, DImode)));
2483 ; emit_insn (gen_andsi3 (gen_lowpart (SImode, operands[
0]),
2484 ; gen_lowpart (SImode, operands[
1]),
2485 ; gen_lowpart (SImode, operands[
2])));
2490 ; andsi3 instruction pattern(s).
2494 [(set (match_operand:SI
0 "r_or_s_operand" "=d,m")
2495 (and:SI (match_operand:SI
1 "r_or_s_operand" "%
0,
0")
2496 (match_operand:SI
2 "r_or_s_operand" "g,mi")))]
2497 "TARGET_CHAR_INSTRUCTIONS"
2500 check_label_emit ();
2501 if (REG_P (operands[
2]))
2503 mvs_check_page (
0,
2,
0);
2504 return
\"NR %
0,%
2\";
2506 if (REG_P (operands[
0]))
2508 mvs_check_page (
0,
4,
0);
2512 mvs_check_page (
0,
6,
0);
2513 return
\"NC %O0(
4,%R0),%
2\";
2516 (define_insn "andsi3"
2517 [(set (match_operand:SI
0 "general_operand" "=d")
2518 (and:SI (match_operand:SI
1 "general_operand" "%
0")
2519 (match_operand:SI
2 "general_operand" "g")))]
2523 check_label_emit ();
2524 if (REG_P (operands[
2]))
2526 mvs_check_page (
0,
2,
0);
2527 return
\"NR %
0,%
2\";
2529 mvs_check_page (
0,
4,
0);
2534 ; andhi3 instruction pattern(s).
2538 [(set (match_operand:HI
0 "r_or_s_operand" "=d,m")
2539 (and:HI (match_operand:HI
1 "r_or_s_operand" "%
0,
0")
2540 (match_operand:HI
2 "r_or_s_operand" "di,mi")))]
2541 "TARGET_CHAR_INSTRUCTIONS"
2544 check_label_emit ();
2545 if (REG_P (operands[
2]))
2547 mvs_check_page (
0,
2,
0);
2548 return
\"NR %
0,%
2\";
2550 if (REG_P (operands[
0]))
2552 mvs_check_page (
0,
4,
0);
2553 return
\"N %
0,%H2
\";
2556 if (GET_CODE (operands[
2]) == CONST_INT)
2558 mvs_check_page (
0,
6,
2);
2559 return
\"NC %O0(
2,%R0),=H'%h2'
\";
2561 mvs_check_page (
0,
6,
0);
2562 return
\"NC %O0(
2,%R0),%
2\";
2565 (define_insn "andhi3"
2566 [(set (match_operand:HI
0 "general_operand" "=d")
2567 (and:HI (match_operand:HI
1 "general_operand" "%
0")
2568 (match_operand:HI
2 "general_operand" "di")))]
2572 check_label_emit ();
2573 if (GET_CODE (operands[
2]) == CONST_INT)
2575 mvs_check_page (
0,
4,
0);
2576 return
\"N %
0,%H2
\";
2578 mvs_check_page (
0,
2,
0);
2579 return
\"NR %
0,%
2\";
2583 ; andqi3 instruction pattern(s).
2587 [(set (match_operand:QI
0 "r_or_s_operand" "=d,m")
2588 (and:QI (match_operand:QI
1 "r_or_s_operand" "%
0,
0")
2589 (match_operand:QI
2 "r_or_s_operand" "di,mi")))]
2590 "TARGET_CHAR_INSTRUCTIONS"
2593 check_label_emit ();
2595 if (REG_P (operands[
2]))
2597 mvs_check_page (
0,
2,
0);
2598 return
\"NR %
0,%
2\";
2600 if (REG_P (operands[
0]))
2602 mvs_check_page (
0,
4,
0);
2605 if (GET_CODE (operands[
2]) == CONST_INT)
2607 mvs_check_page (
0,
4,
0);
2608 return
\"NI %
0,%B2
\";
2610 mvs_check_page (
0,
6,
0);
2611 return
\"NC %O0(
1,%R0),%
2\";
2614 (define_insn "andqi3"
2615 [(set (match_operand:QI
0 "general_operand" "=d")
2616 (and:QI (match_operand:QI
1 "general_operand" "%
0")
2617 (match_operand:QI
2 "general_operand" "di")))]
2621 check_label_emit ();
2623 if (GET_CODE (operands[
2]) == CONST_INT)
2625 mvs_check_page (
0,
4,
0);
2628 mvs_check_page (
0,
2,
0);
2629 return
\"NR %
0,%
2\";
2633 ;;- Bit set (inclusive or) instructions.
2637 ; iordi3 instruction pattern(s).
2640 ;(define_expand "iordi3"
2641 ; [(set (match_operand:DI
0 "general_operand" "")
2642 ; (ior:DI (match_operand:DI
1 "general_operand" "")
2643 ; (match_operand:DI
2 "general_operand" "")))]
2649 ; emit_insn (gen_iorsi3 (operand_subword (operands[
0],
0,
1, DImode),
2650 ; operand_subword (operands[
1],
0,
1, DImode),
2651 ; operand_subword (operands[
2],
0,
1, DImode)));
2652 ; emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[
0]),
2653 ; gen_lowpart (SImode, operands[
1]),
2654 ; gen_lowpart (SImode, operands[
2])));
2659 ; iorsi3 instruction pattern(s).
2663 [(set (match_operand:SI
0 "r_or_s_operand" "=d,m")
2664 (ior:SI (match_operand:SI
1 "r_or_s_operand" "%
0,
0")
2665 (match_operand:SI
2 "r_or_s_operand" "g,mi")))]
2666 "TARGET_CHAR_INSTRUCTIONS"
2669 check_label_emit ();
2670 if (REG_P (operands[
2]))
2672 mvs_check_page (
0,
2,
0);
2673 return
\"OR %
0,%
2\";
2675 if (REG_P (operands[
0]))
2677 mvs_check_page (
0,
4,
0);
2681 mvs_check_page (
0,
6,
0);
2682 return
\"OC %O0(
4,%R0),%
2\";
2685 (define_insn "iorsi3"
2686 [(set (match_operand:SI
0 "general_operand" "=d")
2687 (ior:SI (match_operand:SI
1 "general_operand" "%
0")
2688 (match_operand:SI
2 "general_operand" "g")))]
2692 check_label_emit ();
2693 if (REG_P (operands[
2]))
2695 mvs_check_page (
0,
2,
0);
2696 return
\"OR %
0,%
2\";
2698 mvs_check_page (
0,
4,
0);
2703 ; iorhi3 instruction pattern(s).
2707 [(set (match_operand:HI
0 "r_or_s_operand" "=d,m")
2708 (ior:HI (match_operand:HI
1 "r_or_s_operand" "%
0,
0")
2709 (match_operand:HI
2 "r_or_s_operand" "di,mi")))]
2710 "TARGET_CHAR_INSTRUCTIONS"
2713 check_label_emit ();
2714 if (REG_P (operands[
2]))
2716 mvs_check_page (
0,
2,
0);
2717 return
\"OR %
0,%
2\";
2719 if (REG_P (operands[
0]))
2721 mvs_check_page (
0,
4,
0);
2722 return
\"O %
0,%H2
\";
2725 if (GET_CODE (operands[
2]) == CONST_INT)
2727 mvs_check_page (
0,
6,
2);
2728 return
\"OC %O0(
2,%R0),=H'%h2'
\";
2730 mvs_check_page (
0,
6,
0);
2731 return
\"OC %O0(
2,%R0),%
2\";
2734 (define_insn "iorhi3"
2735 [(set (match_operand:HI
0 "general_operand" "=d")
2736 (ior:HI (match_operand:HI
1 "general_operand" "%
0")
2737 (match_operand:HI
2 "general_operand" "di")))]
2741 check_label_emit ();
2742 if (GET_CODE (operands[
2]) == CONST_INT)
2744 mvs_check_page (
0,
4,
0);
2745 return
\"O %
0,%H2
\";
2747 mvs_check_page (
0,
2,
0);
2748 return
\"OR %
0,%
2\";
2752 ; iorqi3 instruction pattern(s).
2756 [(set (match_operand:QI
0 "r_or_s_operand" "=d,m")
2757 (ior:QI (match_operand:QI
1 "r_or_s_operand" "%
0,
0")
2758 (match_operand:QI
2 "r_or_s_operand" "di,mi")))]
2759 "TARGET_CHAR_INSTRUCTIONS"
2762 check_label_emit ();
2764 if (REG_P (operands[
2]))
2766 mvs_check_page (
0,
2,
0);
2767 return
\"OR %
0,%
2\";
2769 if (REG_P (operands[
0]))
2771 mvs_check_page (
0,
4,
0);
2775 if (GET_CODE (operands[
2]) == CONST_INT)
2777 mvs_check_page (
0,
4,
0);
2778 return
\"OI %
0,%B2
\";
2780 mvs_check_page (
0,
6,
0);
2781 return
\"OC %O0(
1,%R0),%
2\";
2784 (define_insn "iorqi3"
2785 [(set (match_operand:QI
0 "general_operand" "=d")
2786 (ior:QI (match_operand:QI
1 "general_operand" "%
0")
2787 (match_operand:QI
2 "general_operand" "di")))]
2791 check_label_emit ();
2793 if (GET_CODE (operands[
2]) == CONST_INT)
2795 mvs_check_page (
0,
4,
0);
2798 mvs_check_page (
0,
2,
0);
2799 return
\"OR %
0,%
2\";
2803 ;;- Xor instructions.
2807 ; xordi3 instruction pattern(s).
2810 ;(define_expand "xordi3"
2811 ; [(set (match_operand:DI
0 "general_operand" "")
2812 ; (xor:DI (match_operand:DI
1 "general_operand" "")
2813 ; (match_operand:DI
2 "general_operand" "")))]
2819 ; emit_insn (gen_xorsi3 (operand_subword (operands[
0],
0,
1, DImode),
2820 ; operand_subword (operands[
1],
0,
1, DImode),
2821 ; operand_subword (operands[
2],
0,
1, DImode)));
2822 ; emit_insn (gen_xorsi3 (gen_lowpart (SImode, operands[
0]),
2823 ; gen_lowpart (SImode, operands[
1]),
2824 ; gen_lowpart (SImode, operands[
2])));
2829 ; xorsi3 instruction pattern(s).
2833 [(set (match_operand:SI
0 "r_or_s_operand" "=d,m")
2834 (xor:SI (match_operand:SI
1 "r_or_s_operand" "%
0,
0")
2835 (match_operand:SI
2 "r_or_s_operand" "g,mi")))]
2836 "TARGET_CHAR_INSTRUCTIONS"
2839 check_label_emit ();
2840 if (REG_P (operands[
2]))
2842 mvs_check_page (
0,
2,
0);
2843 return
\"XR %
0,%
2\";
2845 if (REG_P (operands[
0]))
2847 mvs_check_page (
0,
4,
0);
2851 mvs_check_page (
0,
6,
0);
2852 return
\"XC %O0(
4,%R0),%
2\";
2855 (define_insn "xorsi3"
2856 [(set (match_operand:SI
0 "general_operand" "=d")
2857 (xor:SI (match_operand:SI
1 "general_operand" "%
0")
2858 (match_operand:SI
2 "general_operand" "g")))]
2862 check_label_emit ();
2863 if (REG_P (operands[
2]))
2865 mvs_check_page (
0,
2,
0);
2866 return
\"XR %
0,%
2\";
2868 mvs_check_page (
0,
4,
0);
2873 ; xorhi3 instruction pattern(s).
2877 [(set (match_operand:HI
0 "r_or_s_operand" "=d,m")
2878 (xor:HI (match_operand:HI
1 "r_or_s_operand" "%
0,
0")
2879 (match_operand:HI
2 "r_or_s_operand" "di,mi")))]
2880 "TARGET_CHAR_INSTRUCTIONS"
2883 check_label_emit ();
2884 if (REG_P (operands[
2]))
2886 mvs_check_page (
0,
2,
0);
2887 return
\"XR %
0,%
2\";
2889 if (REG_P (operands[
0]))
2891 mvs_check_page (
0,
4,
0);
2892 return
\"X %
0,%H2
\";
2895 if (GET_CODE (operands[
2]) == CONST_INT)
2897 mvs_check_page (
0,
6,
2);
2898 return
\"XC %O0(
2,%R0),=H'%h2'
\";
2900 mvs_check_page (
0,
6,
0);
2901 return
\"XC %O0(
2,%R0),%
2\";
2904 (define_insn "xorhi3"
2905 [(set (match_operand:HI
0 "general_operand" "=d")
2906 (xor:HI (match_operand:HI
1 "general_operand" "%
0")
2907 (match_operand:HI
2 "general_operand" "di")))]
2911 check_label_emit ();
2912 if (GET_CODE (operands[
2]) == CONST_INT)
2914 mvs_check_page (
0,
4,
0);
2917 mvs_check_page (
0,
2,
0);
2918 return
\"XR %
0,%
2\";
2922 ; xorqi3 instruction pattern(s).
2926 [(set (match_operand:QI
0 "r_or_s_operand" "=d,m")
2927 (xor:QI (match_operand:QI
1 "r_or_s_operand" "%
0,
0")
2928 (match_operand:QI
2 "r_or_s_operand" "di,mi")))]
2929 "TARGET_CHAR_INSTRUCTIONS"
2932 check_label_emit ();
2934 if (REG_P (operands[
2]))
2936 mvs_check_page (
0,
2,
0);
2937 return
\"XR %
0,%
2\";
2939 if (REG_P (operands[
0]))
2941 mvs_check_page (
0,
4,
0);
2944 if (GET_CODE (operands[
2]) == CONST_INT)
2946 mvs_check_page (
0,
4,
0);
2947 return
\"XI %
0,%B2
\";
2949 mvs_check_page (
0,
6,
0);
2950 return
\"XC %O0(
1,%R0),%
2\";
2953 (define_insn "xorqi3"
2954 [(set (match_operand:QI
0 "general_operand" "=d")
2955 (xor:QI (match_operand:QI
1 "general_operand" "%
0")
2956 (match_operand:QI
2 "general_operand" "di")))]
2960 check_label_emit ();
2962 if (GET_CODE (operands[
2]) == CONST_INT)
2964 mvs_check_page (
0,
4,
0);
2967 mvs_check_page (
0,
2,
0);
2968 return
\"XR %
0,%
2\";
2972 ;;- Negate instructions.
2976 ; negsi2 instruction pattern(s).
2979 (define_insn "negsi2"
2980 [(set (match_operand:SI
0 "general_operand" "=d")
2981 (neg:SI (match_operand:SI
1 "general_operand" "d")))]
2985 check_label_emit ();
2986 mvs_check_page (
0,
2,
0);
2987 return
\"LCR %
0,%
1\";
2991 ; neghi2 instruction pattern(s).
2994 (define_insn "neghi2"
2995 [(set (match_operand:HI
0 "general_operand" "=d")
2996 (neg:HI (match_operand:HI
1 "general_operand" "d")))]
3000 check_label_emit ();
3001 mvs_check_page (
0,
10,
0);
3002 return
\"SLL %
1,
16\;SRA %
1,
16\;LCR %
0,%
1\";
3006 ; negdf2 instruction pattern(s).
3009 (define_insn "negdf2"
3010 [(set (match_operand:DF
0 "general_operand" "=f")
3011 (neg:DF (match_operand:DF
1 "general_operand" "f")))]
3015 check_label_emit ();
3016 mvs_check_page (
0,
2,
0);
3017 return
\"LCDR %
0,%
1\";
3021 ; negsf2 instruction pattern(s).
3024 (define_insn "negsf2"
3025 [(set (match_operand:SF
0 "general_operand" "=f")
3026 (neg:SF (match_operand:SF
1 "general_operand" "f")))]
3030 check_label_emit ();
3031 mvs_check_page (
0,
2,
0);
3032 return
\"LCER %
0,%
1\";
3036 ;;- Absolute value instructions.
3040 ; abssi2 instruction pattern(s).
3043 (define_insn "abssi2"
3044 [(set (match_operand:SI
0 "general_operand" "=d")
3045 (abs:SI (match_operand:SI
1 "general_operand" "d")))]
3049 check_label_emit ();
3050 mvs_check_page (
0,
2,
0);
3051 return
\"LPR %
0,%
1\";
3055 ; abshi2 instruction pattern(s).
3058 (define_insn "abshi2"
3059 [(set (match_operand:HI
0 "general_operand" "=d")
3060 (abs:HI (match_operand:HI
1 "general_operand" "d")))]
3064 check_label_emit ();
3065 mvs_check_page (
0,
10,
0);
3066 return
\"SLL %
1,
16\;SRA %
1,
16\;LPR %
0,%
1\";
3070 ; absdf2 instruction pattern(s).
3073 (define_insn "absdf2"
3074 [(set (match_operand:DF
0 "general_operand" "=f")
3075 (abs:DF (match_operand:DF
1 "general_operand" "f")))]
3079 check_label_emit ();
3080 mvs_check_page (
0,
2,
0);
3081 return
\"LPDR %
0,%
1\";
3085 ; abssf2 instruction pattern(s).
3088 (define_insn "abssf2"
3089 [(set (match_operand:SF
0 "general_operand" "=f")
3090 (abs:SF (match_operand:SF
1 "general_operand" "f")))]
3094 check_label_emit ();
3095 mvs_check_page (
0,
2,
0);
3096 return
\"LPER %
0,%
1\";
3100 ;;- One complement instructions.
3104 ; one_cmpldi2 instruction pattern(s).
3107 ;(define_expand "one_cmpldi2"
3108 ; [(set (match_operand:DI
0 "general_operand" "")
3109 ; (not:DI (match_operand:DI
1 "general_operand" "")))]
3113 ; rtx gen_one_cmplsi2();
3115 ; emit_insn (gen_one_cmplsi2 (operand_subword (operands[
0],
0,
1, DImode),
3116 ; operand_subword (operands[
1],
0,
1, DImode)));
3117 ; emit_insn (gen_one_cmplsi2 (gen_lowpart (SImode, operands[
0]),
3118 ; gen_lowpart (SImode, operands[
1])));
3123 ; one_cmplsi2 instruction pattern(s).
3127 [(set (match_operand:SI
0 "r_or_s_operand" "=dm")
3128 (not:SI (match_operand:SI
1 "r_or_s_operand" "
0")))]
3129 "TARGET_CHAR_INSTRUCTIONS"
3132 check_label_emit ();
3133 if (REG_P (operands[
0]))
3135 mvs_check_page (
0,
4,
4);
3136 return
\"X %
0,=F'-
1'
\";
3139 mvs_check_page (
0,
6,
4);
3140 return
\"XC %O0(
4,%R0),=F'-
1'
\";
3143 (define_insn "one_cmplsi2"
3144 [(set (match_operand:SI
0 "general_operand" "=d")
3145 (not:SI (match_operand:SI
1 "general_operand" "
0")))]
3149 check_label_emit ();
3150 mvs_check_page (
0,
4,
4);
3151 return
\"X %
0,=F'-
1'
\";
3155 ; one_cmplhi2 instruction pattern(s).
3159 [(set (match_operand:HI
0 "r_or_s_operand" "=dm")
3160 (not:HI (match_operand:HI
1 "r_or_s_operand" "
0")))]
3161 "TARGET_CHAR_INSTRUCTIONS"
3164 check_label_emit ();
3165 if (REG_P (operands[
0]))
3167 mvs_check_page (
0,
4,
4);
3168 return
\"X %
0,=F'-
1'
\";
3171 mvs_check_page (
0,
6,
4);
3172 return
\"XC %O0(
2,%R0),=X'FFFF'
\";
3175 (define_insn "one_cmplhi2"
3176 [(set (match_operand:HI
0 "general_operand" "=d")
3177 (not:HI (match_operand:HI
1 "general_operand" "
0")))]
3181 check_label_emit ();
3182 mvs_check_page (
0,
4,
4);
3183 return
\"X %
0,=F'-
1'
\";
3187 ; one_cmplqi2 instruction pattern(s).
3191 [(set (match_operand:QI
0 "r_or_s_operand" "=dm")
3192 (not:QI (match_operand:QI
1 "r_or_s_operand" "
0")))]
3193 "TARGET_CHAR_INSTRUCTIONS"
3196 check_label_emit ();
3198 if (REG_P (operands[
0]))
3200 mvs_check_page (
0,
4,
4);
3201 return
\"X %
0,=F'-
1'
\";
3203 mvs_check_page (
0,
4,
0);
3204 return
\"XI %
0,
255\";
3207 (define_insn "one_cmplqi2"
3208 [(set (match_operand:QI
0 "general_operand" "=d")
3209 (not:QI (match_operand:QI
1 "general_operand" "
0")))]
3213 check_label_emit ();
3215 mvs_check_page (
0,
4,
4);
3216 return
\"X %
0,=F'-
1'
\";
3220 ;;- Arithmetic shift instructions.
3224 ; ashldi3 instruction pattern(s).
3227 (define_insn "ashldi3"
3228 [(set (match_operand:DI
0 "general_operand" "=d")
3229 (ashift:DI (match_operand:DI
1 "general_operand" "
0")
3230 (match_operand:SI
2 "general_operand" "Ja")))]
3234 check_label_emit ();
3236 mvs_check_page (
0,
4,
0);
3237 if (REG_P (operands[
2]))
3238 return
\"SLDA %
0,
0(%
2)
\";
3239 return
\"SLDA %
0,%c2
\";
3243 ; ashrdi3 instruction pattern(s).
3246 (define_insn "ashrdi3"
3247 [(set (match_operand:DI
0 "register_operand" "=d")
3248 (ashiftrt:DI (match_operand:DI
1 "general_operand" "
0")
3249 (match_operand:SI
2 "general_operand" "Ja")))]
3253 check_label_emit ();
3254 mvs_check_page (
0,
4,
0);
3255 if (REG_P (operands[
2]))
3256 return
\"SRDA %
0,
0(%
2)
\";
3257 return
\"SRDA %
0,%c2
\";
3261 ; ashlsi3 instruction pattern(s).
3264 (define_insn "ashlsi3"
3265 [(set (match_operand:SI
0 "general_operand" "=d")
3266 (ashift:SI (match_operand:SI
1 "general_operand" "
0")
3267 (match_operand:SI
2 "general_operand" "Ja")))]
3271 check_label_emit ();
3273 mvs_check_page (
0,
4,
0);
3274 if (REG_P (operands[
2]))
3275 return
\"SLL %
0,
0(%
2)
\";
3276 return
\"SLL %
0,%c2
\";
3280 ; ashrsi3 instruction pattern(s).
3283 (define_insn "ashrsi3"
3284 [(set (match_operand:SI
0 "general_operand" "=d")
3285 (ashiftrt:SI (match_operand:SI
1 "general_operand" "
0")
3286 (match_operand:SI
2 "general_operand" "Ja")))]
3290 check_label_emit ();
3291 mvs_check_page (
0,
4,
0);
3292 if (REG_P (operands[
2]))
3293 return
\"SRA %
0,
0(%
2)
\";
3294 return
\"SRA %
0,%c2
\";
3298 ; ashlhi3 instruction pattern(s).
3301 (define_insn "ashlhi3"
3302 [(set (match_operand:HI
0 "general_operand" "=d")
3303 (ashift:HI (match_operand:HI
1 "general_operand" "
0")
3304 (match_operand:SI
2 "general_operand" "Ja")))]
3308 check_label_emit ();
3309 mvs_check_page (
0,
8,
0);
3310 if (REG_P (operands[
2]))
3311 return
\"SLL %
0,
16(%
2)\;SRA %
0,
16\";
3312 return
\"SLL %
0,
16+%c2\;SRA %
0,
16\";
3316 ; ashrhi3 instruction pattern(s).
3319 (define_insn "ashrhi3"
3320 [(set (match_operand:HI
0 "general_operand" "=d")
3321 (ashiftrt:HI (match_operand:HI
1 "general_operand" "
0")
3322 (match_operand:SI
2 "general_operand" "Ja")))]
3326 check_label_emit ();
3327 mvs_check_page (
0,
4,
0);
3328 if (REG_P (operands[
2]))
3329 return
\"SLL %
0,
16\;SRA %
0,
16(%
2)
\";
3330 return
\"SLL %
0,
16\;SRA %
0,
16+%c2
\";
3334 ; ashlqi3 instruction pattern(s).
3337 (define_insn "ashlqi3"
3338 [(set (match_operand:QI
0 "general_operand" "=d")
3339 (ashift:QI (match_operand:QI
1 "general_operand" "
0")
3340 (match_operand:SI
2 "general_operand" "Ja")))]
3344 check_label_emit ();
3346 mvs_check_page (
0,
4,
0);
3347 if (REG_P (operands[
2]))
3348 return
\"SLL %
0,
0(%
2)
\";
3349 return
\"SLL %
0,%c2
\";
3353 ; ashrqi3 instruction pattern(s).
3356 (define_insn "ashrqi3"
3357 [(set (match_operand:QI
0 "general_operand" "=d")
3358 (ashiftrt:QI (match_operand:QI
1 "general_operand" "
0")
3359 (match_operand:SI
2 "general_operand" "Ja")))]
3363 check_label_emit ();
3364 mvs_check_page (
0,
8,
0);
3365 if (REG_P (operands[
2]))
3366 return
\"SLL %
0,
24\;SRA %
0,
24(%
2)
\";
3367 return
\"SLL %
0,
24\;SRA %
0,
24+%c2
\";
3371 ;;- Logical shift instructions.
3375 ; lshrdi3 instruction pattern(s).
3378 (define_insn "lshrdi3"
3379 [(set (match_operand:DI
0 "general_operand" "=d")
3380 (lshiftrt:DI (match_operand:DI
1 "general_operand" "
0")
3381 (match_operand:SI
2 "general_operand" "Ja")))]
3385 check_label_emit ();
3386 mvs_check_page (
0,
4,
0);
3387 if (REG_P (operands[
2]))
3388 return
\"SRDL %
0,
0(%
2)
\";
3389 return
\"SRDL %
0,%c2
\";
3394 ; lshrsi3 instruction pattern(s).
3397 (define_insn "lshrsi3"
3398 [(set (match_operand:SI
0 "general_operand" "=d")
3399 (lshiftrt:SI (match_operand:SI
1 "general_operand" "
0")
3400 (match_operand:SI
2 "general_operand" "Ja")))]
3404 check_label_emit ();
3405 mvs_check_page (
0,
4,
0);
3406 if (REG_P (operands[
2]))
3407 return
\"SRL %
0,
0(%
2)
\";
3408 return
\"SRL %
0,%c2
\";
3412 ; lshrhi3 instruction pattern(s).
3415 (define_insn "lshrhi3"
3416 [(set (match_operand:HI
0 "general_operand" "=d")
3417 (lshiftrt:HI (match_operand:HI
1 "general_operand" "
0")
3418 (match_operand:SI
2 "general_operand" "Ja")))]
3422 check_label_emit ();
3424 if (REG_P (operands[
2]))
3426 mvs_check_page (
0,
8,
4);
3427 return
\"N %
0,=X'
0000FFFF'\;SRL %
0,
0(%
2)
\";
3429 mvs_check_page (
0,
8,
4);
3430 return
\"N %
0,=X'
0000FFFF'\;SRL %
0,%c2
\";
3434 ; lshrqi3 instruction pattern(s).
3437 (define_insn "lshrqi3"
3438 [(set (match_operand:QI
0 "general_operand" "=d")
3439 (lshiftrt:QI (match_operand:QI
1 "general_operand" "
0")
3440 (match_operand:SI
2 "general_operand" "Ja")))]
3444 check_label_emit ();
3446 mvs_check_page (
0,
8,
4);
3447 if (REG_P (operands[
2]))
3448 return
\"N %
0,=X'
000000FF'\;SRL %
0,
0(%
2)
\";
3449 return
\"N %
0,=X'
000000FF'\;SRL %
0,%c2
\";
3453 ;;- Conditional jump instructions.
3457 ; beq instruction pattern(s).
3462 (if_then_else (eq (cc0)
3464 (label_ref (match_operand
0 "" ""))
3469 check_label_emit ();
3470 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3472 mvs_check_page (
0,
6,
4);
3473 return
\"L
14,=A(%l0)\;BER
14\";
3475 if (mvs_check_page (
0,
4,
0))
3477 mvs_check_page (
0,
2,
4);
3478 return
\"L
14,=A(%l0)\;BER
14\";
3484 ; bne instruction pattern(s).
3489 (if_then_else (ne (cc0)
3491 (label_ref (match_operand
0 "" ""))
3496 check_label_emit ();
3497 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3499 mvs_check_page (
0,
6,
4);
3500 return
\"L
14,=A(%l0)\;BNER
14\";
3502 if (mvs_check_page (
0,
4,
0))
3504 mvs_check_page (
0,
2,
4);
3505 return
\"L
14,=A(%l0)\;BNER
14\";
3511 ; bgt instruction pattern(s).
3516 (if_then_else (gt (cc0)
3518 (label_ref (match_operand
0 "" ""))
3523 check_label_emit ();
3524 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3526 mvs_check_page (
0,
6,
4);
3527 return
\"L
14,=A(%l0)\;BHR
14\";
3529 if (mvs_check_page (
0,
4,
0))
3531 mvs_check_page (
0,
2,
4);
3532 return
\"L
14,=A(%l0)\;BHR
14\";
3538 ; bgtu instruction pattern(s).
3543 (if_then_else (gtu (cc0)
3545 (label_ref (match_operand
0 "" ""))
3550 check_label_emit ();
3551 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3553 mvs_check_page (
0,
6,
4);
3554 return
\"L
14,=A(%l0)\;BHR
14\";
3556 if (mvs_check_page (
0,
4,
0))
3558 mvs_check_page (
0,
2,
4);
3559 return
\"L
14,=A(%l0)\;BHR
14\";
3565 ; blt instruction pattern(s).
3570 (if_then_else (lt (cc0)
3572 (label_ref (match_operand
0 "" ""))
3577 check_label_emit ();
3578 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3580 mvs_check_page (
0,
6,
4);
3581 return
\"L
14,=A(%l0)\;BLR
14\";
3583 if (mvs_check_page (
0,
4,
0))
3585 mvs_check_page (
0,
2,
4);
3586 return
\"L
14,=A(%l0)\;BLR
14\";
3592 ; bltu instruction pattern(s).
3597 (if_then_else (ltu (cc0)
3599 (label_ref (match_operand
0 "" ""))
3604 check_label_emit ();
3605 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3607 mvs_check_page (
0,
6,
4);
3608 return
\"L
14,=A(%l0)\;BLR
14\";
3610 if (mvs_check_page (
0,
4,
0))
3612 mvs_check_page (
0,
2,
4);
3613 return
\"L
14,=A(%l0)\;BLR
14\";
3619 ; bge instruction pattern(s).
3624 (if_then_else (ge (cc0)
3626 (label_ref (match_operand
0 "" ""))
3631 check_label_emit ();
3632 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3634 mvs_check_page (
0,
6,
4);
3635 return
\"L
14,=A(%l0)\;BNLR
14\";
3637 if (mvs_check_page (
0,
4,
0))
3639 mvs_check_page (
0,
2,
4);
3640 return
\"L
14,=A(%l0)\;BNLR
14\";
3646 ; bgeu instruction pattern(s).
3651 (if_then_else (geu (cc0)
3653 (label_ref (match_operand
0 "" ""))
3658 check_label_emit ();
3659 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3661 mvs_check_page (
0,
6,
4);
3662 return
\"L
14,=A(%l0)\;BNLR
14\";
3664 if (mvs_check_page (
0,
4,
0))
3666 mvs_check_page (
0,
2,
4);
3667 return
\"L
14,=A(%l0)\;BNLR
14\";
3673 ; ble instruction pattern(s).
3678 (if_then_else (le (cc0)
3680 (label_ref (match_operand
0 "" ""))
3685 check_label_emit ();
3686 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3688 mvs_check_page (
0,
6,
4);
3689 return
\"L
14,=A(%l0)\;BNHR
14\";
3691 if (mvs_check_page (
0,
4,
0))
3693 mvs_check_page (
0,
2,
4);
3694 return
\"L
14,=A(%l0)\;BNHR
14\";
3700 ; bleu instruction pattern(s).
3705 (if_then_else (leu (cc0)
3707 (label_ref (match_operand
0 "" ""))
3712 check_label_emit ();
3713 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3715 mvs_check_page (
0,
6,
4);
3716 return
\"L
14,=A(%l0)\;BNHR
14\";
3718 if (mvs_check_page (
0,
4,
0))
3720 mvs_check_page (
0,
2,
4);
3721 return
\"L
14,=A(%l0)\;BNHR
14\";
3727 ;;- Negated conditional jump instructions.
3732 (if_then_else (eq (cc0)
3735 (label_ref (match_operand
0 "" ""))))]
3739 check_label_emit ();
3740 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3742 mvs_check_page (
0,
6,
4);
3743 return
\"L
14,=A(%l0)\;BNER
14\";
3745 if (mvs_check_page (
0,
4,
0))
3747 mvs_check_page (
0,
2,
4);
3748 return
\"L
14,=A(%l0)\;BNER
14\";
3755 (if_then_else (ne (cc0)
3758 (label_ref (match_operand
0 "" ""))))]
3762 check_label_emit ();
3763 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3765 mvs_check_page (
0,
6,
4);
3766 return
\"L
14,=A(%l0)\;BER
14\";
3768 if (mvs_check_page (
0,
4,
0))
3770 mvs_check_page (
0,
2,
4);
3771 return
\"L
14,=A(%l0)\;BER
14\";
3778 (if_then_else (gt (cc0)
3781 (label_ref (match_operand
0 "" ""))))]
3785 check_label_emit ();
3786 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3788 mvs_check_page (
0,
6,
4);
3789 return
\"L
14,=A(%l0)\;BNHR
14\";
3791 if (mvs_check_page (
0,
4,
0))
3793 mvs_check_page (
0,
2,
4);
3794 return
\"L
14,=A(%l0)\;BNHR
14\";
3801 (if_then_else (gtu (cc0)
3804 (label_ref (match_operand
0 "" ""))))]
3808 check_label_emit ();
3809 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3811 mvs_check_page (
0,
6,
4);
3812 return
\"L
14,=A(%l0)\;BNHR
14\";
3814 if (mvs_check_page (
0,
4,
0))
3816 mvs_check_page (
0,
2,
4);
3817 return
\"L
14,=A(%l0)\;BNHR
14\";
3824 (if_then_else (lt (cc0)
3827 (label_ref (match_operand
0 "" ""))))]
3831 check_label_emit ();
3832 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3834 mvs_check_page (
0,
6,
4);
3835 return
\"L
14,=A(%l0)\;BNLR
14\";
3837 if (mvs_check_page (
0,
4,
0))
3839 mvs_check_page (
0,
2,
4);
3840 return
\"L
14,=A(%l0)\;BNLR
14\";
3847 (if_then_else (ltu (cc0)
3850 (label_ref (match_operand
0 "" ""))))]
3854 check_label_emit ();
3855 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3857 mvs_check_page (
0,
6,
4);
3858 return
\"L
14,=A(%l0)\;BNLR
14\";
3860 if (mvs_check_page (
0,
4,
0))
3862 mvs_check_page (
0,
2,
4);
3863 return
\"L
14,=A(%l0)\;BNLR
14\";
3870 (if_then_else (ge (cc0)
3873 (label_ref (match_operand
0 "" ""))))]
3877 check_label_emit ();
3878 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3880 mvs_check_page (
0,
6,
4);
3881 return
\"L
14,=A(%l0)\;BLR
14\";
3883 if (mvs_check_page (
0,
4,
0))
3885 mvs_check_page (
0,
2,
4);
3886 return
\"L
14,=A(%l0)\;BLR
14\";
3893 (if_then_else (geu (cc0)
3896 (label_ref (match_operand
0 "" ""))))]
3900 check_label_emit ();
3901 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3903 mvs_check_page (
0,
6,
4);
3904 return
\"L
14,=A(%l0)\;BLR
14\";
3906 if (mvs_check_page (
0,
4,
0))
3908 mvs_check_page (
0,
2,
4);
3909 return
\"L
14,=A(%l0)\;BLR
14\";
3916 (if_then_else (le (cc0)
3919 (label_ref (match_operand
0 "" ""))))]
3923 check_label_emit ();
3924 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3926 mvs_check_page (
0,
6,
4);
3927 return
\"L
14,=A(%l0)\;BHR
14\";
3929 if (mvs_check_page (
0,
4,
0))
3931 mvs_check_page (
0,
2,
4);
3932 return
\"L
14,=A(%l0)\;BHR
14\";
3939 (if_then_else (leu (cc0)
3942 (label_ref (match_operand
0 "" ""))))]
3946 check_label_emit ();
3947 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
3949 mvs_check_page (
0,
6,
4);
3950 return
\"L
14,=A(%l0)\;BHR
14\";
3952 if (mvs_check_page (
0,
4,
0))
3954 mvs_check_page (
0,
2,
4);
3955 return
\"L
14,=A(%l0)\;BHR
14\";
3961 ;;- Subtract one and jump if not zero.
3967 (ne (plus:SI (match_operand:SI
0 "register_operand" "+d")
3970 (label_ref (match_operand
1 "" ""))
3973 (plus:SI (match_dup
0)
3978 check_label_emit ();
3979 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
1])))
3981 mvs_check_page (
0,
6,
4);
3982 return
\"L
14,=A(%l1)\;BCTR %
0,
14\";
3984 if (mvs_check_page (
0,
4,
0))
3986 mvs_check_page (
0,
2,
4);
3987 return
\"L
14,=A(%l1)\;BCTR %
0,
14\";
3989 return
\"BCT %
0,%l1
\";
3995 (eq (plus:SI (match_operand:SI
0 "register_operand" "+d")
3999 (label_ref (match_operand
1 "" ""))))
4001 (plus:SI (match_dup
0)
4006 check_label_emit ();
4007 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
1])))
4009 mvs_check_page (
0,
6,
4);
4010 return
\"L
14,=A(%l1)\;BCTR %
0,
14\";
4012 if (mvs_check_page (
0,
4,
0))
4014 mvs_check_page (
0,
2,
4);
4015 return
\"L
14,=A(%l1)\;BCTR %
0,
14\";
4017 return
\"BCT %
0,%l1
\";
4021 ;;- Unconditional jump instructions.
4025 ; jump instruction pattern(s).
4030 (label_ref (match_operand
0 "" "")))]
4034 check_label_emit ();
4035 if (!mvs_check_label (CODE_LABEL_NUMBER (operands[
0])))
4037 mvs_check_page (
0,
6,
4);
4038 return
\"L
14,=A(%l0)\;BR
14\";
4040 if (mvs_check_page (
0,
4,
0))
4042 mvs_check_page (
0,
2,
4);
4043 return
\"L
14,=A(%l0)\;BR
14\";
4049 ; indirect-jump instruction pattern(s).
4052 (define_insn "indirect_jump"
4053 [(set (pc) (match_operand:SI
0 "general_operand" "r"))]
4054 "(GET_CODE (operands[
0]) != MEM )"
4057 check_label_emit ();
4058 mvs_check_page (
0,
2,
0);
4063 ; tablejump instruction pattern(s).
4066 (define_insn "tablejump"
4068 (match_operand:SI
0 "general_operand" "am"))
4069 (use (label_ref (match_operand
1 "" "")))]
4073 check_label_emit ();
4074 if (REG_P (operands[
0]))
4076 mvs_check_page (
0,
6,
0);
4077 return
\"BR %
0\;DS
0F
\";
4079 mvs_check_page (
0,
10,
0);
4080 return
\"L
14,%
0\;BR
14\;DS
0F
\";
4084 ;;- Jump to subroutine.
4086 ;; For the C/
370 environment the internal functions, ie. sqrt, are called with
4087 ;; a non-standard form. So, we must fix it here. There's no BM like IBM.
4091 ; call instruction pattern(s).
4095 [(call (match_operand:QI
0 "memory_operand" "m")
4096 (match_operand:SI
1 "immediate_operand" "i"))]
4100 static char temp[
128];
4101 int i = STACK_POINTER_OFFSET;
4103 check_label_emit ();
4104 if (mvs_function_check (XSTR (operands[
0],
0)))
4106 mvs_check_page (
0,
22,
4);
4107 sprintf ( temp,
\"LA
1,
136(,
13)\;ST
1,%d(,
13)\;LA
1,%d(,
13)\;L
15,%%
0\;BALR
14,
15\;LD
0,
136(,
13)
\",
4112 mvs_check_page (
0,
10,
4);
4113 sprintf ( temp,
\"LA
1,%d(,
13)\;L
15,%%
0\;BALR
14,
15\", i );
4119 ; call_value instruction pattern(s).
4122 (define_insn "call_value"
4123 [(set (match_operand
0 "" "rf")
4124 (call (match_operand:QI
1 "memory_operand" "m")
4125 (match_operand:SI
2 "general_operand" "i")))]
4129 static char temp[
128];
4130 int i = STACK_POINTER_OFFSET;
4132 check_label_emit ();
4133 if (mvs_function_check (XSTR (operands[
1],
0)))
4135 mvs_check_page (
0,
22,
4);
4136 sprintf ( temp,
\"LA
1,
136(,
13)\;ST
1,%d(,
13)\;LA
1,%d(,
13)\;L
15,%%
1\;BALR
14,
15\;LD
0,
136(,
13)
\",
4141 mvs_check_page (
0,
10,
4);
4142 sprintf ( temp,
\"LA
1,%d(,
13)\;L
15,%%
1\;BALR
14,
15\", i );
4148 [(call (mem:QI (match_operand:SI
0 "" "i"))
4149 (match_operand:SI
1 "general_operand" "g"))]
4150 "GET_CODE (operands[
0]) == SYMBOL_REF"
4153 static char temp[
128];
4154 int i = STACK_POINTER_OFFSET;
4156 check_label_emit ();
4157 if (mvs_function_check (XSTR (operands[
0],
0)))
4159 mvs_check_page (
0,
22,
4);
4160 sprintf ( temp,
\"LA
1,
136(,
13)\;ST
1,%d(,
13)\;LA
1,%d(,
13)\;L
15,%%
0\;BALR
14,
15\;LD
0,
136(,
13)
\",
4165 mvs_check_page (
0,
10,
4);
4166 sprintf ( temp,
\"LA
1,%d(,
13)\;L
15,%%
0\;BALR
14,
15\", i );
4172 [(set (match_operand
0 "" "rf")
4173 (call (mem:QI (match_operand:SI
1 "" "i"))
4174 (match_operand:SI
2 "general_operand" "g")))]
4175 "GET_CODE (operands[
1]) == SYMBOL_REF"
4178 static char temp[
128];
4179 int i = STACK_POINTER_OFFSET;
4181 check_label_emit ();
4182 if (mvs_function_check (XSTR (operands[
1],
0)))
4184 mvs_check_page (
0,
22,
4);
4185 sprintf ( temp,
\"LA
1,
136(,
13)\;ST
1,%d(,
13)\;LA
1,%d(,
13)\;L
15,%%
1\;BALR
14,
15\;LD
0,
136(,
13)
\",
4190 mvs_check_page (
0,
10,
4);
4191 sprintf ( temp,
\"LA
1,%d(,
13)\;L
15,%%
1\;BALR
14,
15\", i );
4198 ;;- Miscellaneous instructions.
4202 ; nop instruction pattern(s).
4210 check_label_emit ();
4211 mvs_check_page (
0,
2,
0);