1 ;; GCC machine description for Hitachi H8/
300
2 ;; Copyright (C)
1992,
1993,
1994,
1995,
1996,
1997,
1998,
1999,
2000,
3 ;;
2001,
2002,
2003 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version
2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
23 ;; Boston, MA
02111-
1307, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/
300H and H8S, adds/subs operate on the
32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us
8
33 ;; more
16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/
300H
37 ;; because word_mode is different for the H8/
300 and H8/
300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
63 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
67 (define_attr "cpu" "h8300,h8300h"
68 (const (symbol_ref "cpu_type")))
70 (define_attr "type" "branch,arith"
71 (const_string "arith"))
73 ;; The size of instructions in bytes.
75 (define_attr "length" ""
76 (cond [(eq_attr "type" "branch")
77 (if_then_else (and (ge (minus (match_dup
0) (pc))
79 (le (minus (match_dup
0) (pc))
82 (if_then_else (and (eq_attr "cpu" "h8300h")
83 (and (ge (minus (pc) (match_dup
0))
85 (le (minus (pc) (match_dup
0))
91 ;; Condition code settings.
93 ;; none - insn does not affect cc
94 ;; none_0hit - insn does not affect cc but it does modify operand
0
95 ;; This attribute is used to keep track of when operand
0 changes.
96 ;; See the description of NOTICE_UPDATE_CC for more info.
97 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
98 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
99 ;; compare - compare instruction
100 ;; clobber - value of cc is unknown
102 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
103 (const_string "clobber"))
105 ;; Provide the maximum length of an assembly instruction in an asm
106 ;; statement. The maximum length of
14 bytes is achieved on H8SX.
108 (define_asm_attributes
109 [(set (attr "length")
110 (cond [(ne (symbol_ref "TARGET_H8300") (const_int
0)) (const_int
4)
111 (ne (symbol_ref "TARGET_H8300H") (const_int
0)) (const_int
10)
112 (ne (symbol_ref "TARGET_H8300S") (const_int
0)) (const_int
10)]
115 ;; ----------------------------------------------------------------------
117 ;; ----------------------------------------------------------------------
121 (define_insn "pushqi1_h8300"
122 [(parallel [(set (reg:HI SP_REG)
123 (plus:HI (reg:HI SP_REG) (const_int -
2)))
124 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -
1)))
125 (match_operand:QI
0 "register_operand" "r"))])]
127 && operands[
0] != stack_pointer_rtx"
129 [(set_attr "length" "
2")
130 (set_attr "cc" "clobber")])
132 (define_insn "pushqi1_h8300hs"
133 [(parallel [(set (reg:SI SP_REG)
134 (plus:SI (reg:SI SP_REG) (const_int -
4)))
135 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -
3)))
136 (match_operand:QI
0 "register_operand" "r"))])]
137 "(TARGET_H8300H || TARGET_H8300S)
138 && operands[
0] != stack_pointer_rtx"
140 [(set_attr "length" "
4")
141 (set_attr "cc" "clobber")])
143 (define_insn "pushqi1_h8300hs_normal"
144 [(parallel [(set (reg:HI SP_REG)
145 (plus:HI (reg:HI SP_REG) (const_int -
4)))
146 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -
3)))
147 (match_operand:QI
0 "register_operand" "r"))])]
148 "(TARGET_H8300H || TARGET_H8300S)
149 && operands[
0] != stack_pointer_rtx"
151 [(set_attr "length" "
4")
152 (set_attr "cc" "clobber")])
154 (define_expand "pushqi1"
155 [(use (match_operand:QI
0 "register_operand" ""))]
160 emit_insn (gen_pushqi1_h8300 (operands[
0]));
161 else if (!TARGET_NORMAL_MODE)
162 emit_insn (gen_pushqi1_h8300hs (operands[
0]));
164 emit_insn (gen_pushqi1_h8300hs_normal (operands[
0]));
168 (define_insn "*movqi_h8300"
169 [(set (match_operand:QI
0 "general_operand_dst" "=r,r ,<,r,r,m")
170 (match_operand:QI
1 "general_operand_src" " I,r>,r,n,m,r"))]
172 && (register_operand (operands[
0], QImode)
173 || register_operand (operands[
1], QImode))"
181 [(set_attr "length" "
2,
2,
2,
2,
4,
4")
182 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
184 (define_insn "*movqi_h8300hs"
185 [(set (match_operand:QI
0 "general_operand_dst" "=r,r ,<,r,r,m")
186 (match_operand:QI
1 "general_operand_src" " I,r>,r,n,m,r"))]
187 "(TARGET_H8300H || TARGET_H8300S)
188 && (register_operand (operands[
0], QImode)
189 || register_operand (operands[
1], QImode))"
197 [(set (attr "length")
198 (symbol_ref "compute_mov_length (operands)"))
199 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
201 (define_expand "movqi"
202 [(set (match_operand:QI
0 "general_operand_dst" "")
203 (match_operand:QI
1 "general_operand_src" ""))]
207 /* One of the ops has to be in a register. */
208 if (!register_operand (operand0, QImode)
209 && !register_operand (operand1, QImode))
211 operands[
1] = copy_to_mode_reg (QImode, operand1);
215 (define_insn "movstrictqi"
216 [(set (strict_low_part (match_operand:QI
0 "general_operand_dst" "+r,r,r,r"))
217 (match_operand:QI
1 "general_operand_src" "I,r,n,m"))]
224 [(set (attr "length")
225 (symbol_ref "compute_mov_length (operands)"))
226 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
230 (define_expand "pushhi1_h8300"
231 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
232 (match_operand:HI
0 "register_operand" ""))]
234 && operands[
0] != stack_pointer_rtx"
237 (define_insn "pushhi1_h8300hs"
238 [(parallel [(set (reg:SI SP_REG)
239 (plus:SI (reg:SI SP_REG) (const_int -
4)))
240 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -
2)))
241 (match_operand:HI
0 "register_operand" "r"))])]
242 "(TARGET_H8300H || TARGET_H8300S)
243 && operands[
0] != stack_pointer_rtx"
245 [(set_attr "length" "
4")
246 (set_attr "cc" "clobber")])
248 (define_insn "pushhi1_h8300hs_normal"
249 [(parallel [(set (reg:HI SP_REG)
250 (plus:HI (reg:HI SP_REG) (const_int -
4)))
251 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -
2)))
252 (match_operand:HI
0 "register_operand" "r"))])]
253 "(TARGET_H8300H || TARGET_H8300S)
254 && operands[
0] != stack_pointer_rtx"
256 [(set_attr "length" "
4")
257 (set_attr "cc" "clobber")])
259 (define_expand "pushhi1"
260 [(use (match_operand:HI
0 "register_operand" ""))]
265 emit_insn (gen_pushhi1_h8300 (operands[
0]));
266 else if (!TARGET_NORMAL_MODE)
267 emit_insn (gen_pushhi1_h8300hs (operands[
0]));
269 emit_insn (gen_pushhi1_h8300hs_normal (operands[
0]));
273 (define_insn "*movhi_h8300"
274 [(set (match_operand:HI
0 "general_operand_dst" "=r,r,<,r,r,m")
275 (match_operand:HI
1 "general_operand_src" "I,r>,r,i,m,r"))]
277 && (register_operand (operands[
0], HImode)
278 || register_operand (operands[
1], HImode))
279 && !(GET_CODE (operands[
0]) == MEM
280 && GET_CODE (XEXP (operands[
0],
0)) == PRE_DEC
281 && GET_CODE (XEXP (XEXP (operands[
0],
0),
0)) == REG
282 && GET_CODE (operands[
1]) == REG
283 && REGNO (XEXP (XEXP (operands[
0],
0),
0)) == REGNO (operands[
1]))"
291 [(set (attr "length")
292 (symbol_ref "compute_mov_length (operands)"))
293 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
295 (define_insn "*movhi_h8300hs"
296 [(set (match_operand:HI
0 "general_operand_dst" "=r,r,<,r,r,m")
297 (match_operand:HI
1 "general_operand_src" "I,r>,r,i,m,r"))]
298 "(TARGET_H8300H || TARGET_H8300S)
299 && (register_operand (operands[
0], HImode)
300 || register_operand (operands[
1], HImode))"
308 [(set (attr "length")
309 (symbol_ref "compute_mov_length (operands)"))
310 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
312 (define_expand "movhi"
313 [(set (match_operand:HI
0 "general_operand_dst" "")
314 (match_operand:HI
1 "general_operand_src" ""))]
318 /* One of the ops has to be in a register. */
319 if (!register_operand (operand1, HImode)
320 && !register_operand (operand0, HImode))
322 operands[
1] = copy_to_mode_reg (HImode, operand1);
326 (define_insn "movstricthi"
327 [(set (strict_low_part (match_operand:HI
0 "general_operand_dst" "+r,r,r,r"))
328 (match_operand:HI
1 "general_operand_src" "I,r,i,m"))]
335 [(set (attr "length")
336 (symbol_ref "compute_mov_length (operands)"))
337 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
341 (define_expand "movsi"
342 [(set (match_operand:SI
0 "general_operand_dst" "")
343 (match_operand:SI
1 "general_operand_src" ""))]
349 if (do_movsi (operands))
354 /* One of the ops has to be in a register. */
355 if (!register_operand (operand1, SImode)
356 && !register_operand (operand0, SImode))
358 operands[
1] = copy_to_mode_reg (SImode, operand1);
363 (define_expand "movsf"
364 [(set (match_operand:SF
0 "general_operand_dst" "")
365 (match_operand:SF
1 "general_operand_src" ""))]
371 if (do_movsi (operands))
376 /* One of the ops has to be in a register. */
377 if (!register_operand (operand1, SFmode)
378 && !register_operand (operand0, SFmode))
380 operands[
1] = copy_to_mode_reg (SFmode, operand1);
385 (define_insn "*movsi_h8300"
386 [(set (match_operand:SI
0 "general_operand_dst" "=r,r,r,o,<,r")
387 (match_operand:SI
1 "general_operand_src" "I,r,io,r,r,>"))]
389 && (register_operand (operands[
0], SImode)
390 || register_operand (operands[
1], SImode))"
393 unsigned int rn = -
1;
394 switch (which_alternative)
397 return
\"sub.w %e0,%e0\;sub.w %f0,%f0
\";
399 if (REGNO (operands[
0]) < REGNO (operands[
1]))
400 return
\"mov.w %e1,%e0\;mov.w %f1,%f0
\";
402 return
\"mov.w %f1,%f0\;mov.w %e1,%e0
\";
404 /* Make sure we don't trample the register we index with. */
405 if (GET_CODE (operands[
1]) == MEM)
407 rtx inside = XEXP (operands[
1],
0);
412 else if (GET_CODE (inside) == PLUS)
414 rtx lhs = XEXP (inside,
0);
415 rtx rhs = XEXP (inside,
1);
416 if (REG_P (lhs)) rn = REGNO (lhs);
417 if (REG_P (rhs)) rn = REGNO (rhs);
420 if (rn == REGNO (operands[
0]))
422 /* Move the second word first. */
423 return
\"mov.w %f1,%f0\;mov.w %e1,%e0
\";
427 if (GET_CODE (operands[
1]) == CONST_INT)
429 /* If either half is zero, use sub.w to clear that
431 if ((INTVAL (operands[
1]) &
0xffff) ==
0)
432 return
\"mov.w %e1,%e0\;sub.w %f0,%f0
\";
433 if (((INTVAL (operands[
1]) >>
16) &
0xffff) ==
0)
434 return
\"sub.w %e0,%e0\;mov.w %f1,%f0
\";
435 /* If the upper half and the lower half are the same,
436 copy one half to the other. */
437 if ((INTVAL (operands[
1]) &
0xffff)
438 == ((INTVAL (operands[
1]) >>
16) &
0xffff))
439 return
\"mov.w
\\t%e1,%e0\;mov.w
\\t%e0,%f0
\";
441 return
\"mov.w %e1,%e0\;mov.w %f1,%f0
\";
444 return
\"mov.w %e1,%e0\;mov.w %f1,%f0
\";
446 return
\"mov.w %f1,%T0\;mov.w %e1,%T0
\";
448 return
\"mov.w %T1,%e0\;mov.w %T1,%f0
\";
453 [(set (attr "length")
454 (symbol_ref "compute_mov_length (operands)"))
455 (set_attr "cc" "clobber")])
457 (define_insn "*movsf_h8300"
458 [(set (match_operand:SF
0 "general_operand_dst" "=r,r,r,o,<,r")
459 (match_operand:SF
1 "general_operand_src" "G,r,io,r,r,>"))]
461 && (register_operand (operands[
0], SFmode)
462 || register_operand (operands[
1], SFmode))"
465 /* Copy of the movsi stuff. */
466 unsigned int rn = -
1;
467 switch (which_alternative)
470 return
\"sub.w %e0,%e0\;sub.w %f0,%f0
\";
472 if (REGNO (operands[
0]) < REGNO (operands[
1]))
473 return
\"mov.w %e1,%e0\;mov.w %f1,%f0
\";
475 return
\"mov.w %f1,%f0\;mov.w %e1,%e0
\";
477 /* Make sure we don't trample the register we index with. */
478 if (GET_CODE (operands[
1]) == MEM)
480 rtx inside = XEXP (operands[
1],
0);
485 else if (GET_CODE (inside) == PLUS)
487 rtx lhs = XEXP (inside,
0);
488 rtx rhs = XEXP (inside,
1);
489 if (REG_P (lhs)) rn = REGNO (lhs);
490 if (REG_P (rhs)) rn = REGNO (rhs);
493 if (rn == REGNO (operands[
0]))
494 /* Move the second word first. */
495 return
\"mov.w %f1,%f0\;mov.w %e1,%e0
\";
497 /* Move the first word first. */
498 return
\"mov.w %e1,%e0\;mov.w %f1,%f0
\";
501 return
\"mov.w %e1,%e0\;mov.w %f1,%f0
\";
503 return
\"mov.w %f1,%T0\;mov.w %e1,%T0
\";
505 return
\"mov.w %T1,%e0\;mov.w %T1,%f0
\";
510 [(set (attr "length")
511 (symbol_ref "compute_mov_length (operands)"))
512 (set_attr "cc" "clobber")])
514 (define_insn "*movsi_h8300hs"
515 [(set (match_operand:SI
0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
516 (match_operand:SI
1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
517 "(TARGET_H8300S || TARGET_H8300H)
518 && (register_operand (operands[
0], SImode)
519 || register_operand (operands[
1], SImode))
520 && !(GET_CODE (operands[
0]) == MEM
521 && GET_CODE (XEXP (operands[
0],
0)) == PRE_DEC
522 && GET_CODE (XEXP (XEXP (operands[
0],
0),
0)) == REG
523 && GET_CODE (operands[
1]) == REG
524 && REGNO (XEXP (XEXP (operands[
0],
0),
0)) == REGNO (operands[
1]))"
527 switch (which_alternative)
530 return
\"sub.l %S0,%S0
\";
534 return
\"clrmac\;ldmac %
1,macl
\";
536 return
\"stmac macl,%
0\";
538 if (GET_CODE (operands[
1]) == CONST_INT)
540 int val = INTVAL (operands[
1]);
542 /* Look for constants which can be made by adding an
8-bit
543 number to zero in one of the two low bytes. */
544 if (val == (val &
0xff))
546 operands[
1] = GEN_INT ((char) val &
0xff);
547 return
\"sub.l
\\t%S0,%S0\;add.b
\\t%
1,%w0
\";
550 if (val == (val &
0xff00))
552 operands[
1] = GEN_INT ((char) (val >>
8) &
0xff);
553 return
\"sub.l
\\t%S0,%S0\;add.b
\\t%
1,%x0
\";
556 /* Look for constants that can be obtained by subs, inc, and
558 switch (val &
0xffffffff)
561 return
\"sub.l
\\t%S0,%S0\;subs
\\t#
1,%S0
\";
563 return
\"sub.l
\\t%S0,%S0\;subs
\\t#
2,%S0
\";
565 return
\"sub.l
\\t%S0,%S0\;subs
\\t#
4,%S0
\";
568 return
\"sub.l
\\t%S0,%S0\;dec.w
\\t#
1,%f0
\";
570 return
\"sub.l
\\t%S0,%S0\;dec.w
\\t#
2,%f0
\";
573 return
\"sub.l
\\t%S0,%S0\;dec.w
\\t#
1,%e0
\";
575 return
\"sub.l
\\t%S0,%S0\;dec.w
\\t#
2,%e0
\";
578 return
\"sub.l
\\t%S0,%S0\;inc.w
\\t#
1,%e0
\";
580 return
\"sub.l
\\t%S0,%S0\;inc.w
\\t#
2,%e0
\";
584 return
\"mov.l %S1,%S0
\";
586 [(set (attr "length")
587 (symbol_ref "compute_mov_length (operands)"))
588 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
590 (define_insn "*movsf_h8300h"
591 [(set (match_operand:SF
0 "general_operand_dst" "=r,r,r,m,<,r")
592 (match_operand:SF
1 "general_operand_src" "G,r,im,r,r,>"))]
593 "(TARGET_H8300H || TARGET_H8300S)
594 && (register_operand (operands[
0], SFmode)
595 || register_operand (operands[
1], SFmode))"
603 [(set (attr "length")
604 (symbol_ref "compute_mov_length (operands)"))
605 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
607 ;; ----------------------------------------------------------------------
609 ;; ----------------------------------------------------------------------
612 [(set (cc0) (zero_extract:HI (match_operand:QI
0 "bit_memory_operand" "r,U")
614 (match_operand
1 "const_int_operand" "n,n")))]
617 [(set_attr "length" "
2,
4")
618 (set_attr "cc" "set_zn,set_zn")])
621 [(set (cc0) (zero_extract:HI (match_operand:HI
0 "register_operand" "r")
623 (match_operand
1 "const_int_operand" "n")))]
626 [(set_attr "length" "
2")
627 (set_attr "cc" "set_zn")])
629 (define_insn_and_split "*tst_extzv_1_n"
631 (zero_extract:SI (match_operand:QI
0 "general_operand_src" "r,U,mn>")
633 (match_operand
1 "const_int_operand" "n,n,n")))
634 (clobber (match_scratch:QI
2 "=X,X,&r"))]
635 "(TARGET_H8300H || TARGET_H8300S)"
641 && !EXTRA_CONSTRAINT (operands[
0], 'U')"
644 (parallel [(set (cc0) (zero_extract:SI (match_dup
2)
647 (clobber (scratch:QI))])]
649 [(set_attr "length" "
2,
8,
10")
650 (set_attr "cc" "set_zn,set_zn,set_zn")])
653 [(set (cc0) (zero_extract:SI (match_operand:SI
0 "register_operand" "r")
655 (match_operand
1 "const_int_operand" "n")))]
656 "(TARGET_H8300H || TARGET_H8300S)
657 && INTVAL (operands[
1]) <=
15"
659 [(set_attr "length" "
2")
660 (set_attr "cc" "set_zn")])
662 (define_insn_and_split "*tstsi_upper_bit"
664 (zero_extract:SI (match_operand:SI
0 "register_operand" "r")
666 (match_operand
1 "const_int_operand" "n")))
667 (clobber (match_scratch:SI
2 "=&r"))]
668 "(TARGET_H8300H || TARGET_H8300S)
669 && INTVAL (operands[
1]) >=
16"
671 "&& reload_completed"
673 (ior:SI (and:SI (match_dup
2)
675 (lshiftrt:SI (match_dup
0)
678 (zero_extract:SI (match_dup
2)
681 "operands[
3] = GEN_INT (INTVAL (operands[
1]) -
16);")
683 (define_insn "*tstsi_variable_bit"
685 (zero_extract:SI (match_operand:SI
0 "register_operand" "r")
687 (and:SI (match_operand:SI
1 "register_operand" "r")
689 "TARGET_H8300H || TARGET_H8300S"
691 [(set_attr "length" "
2")
692 (set_attr "cc" "set_zn")])
694 (define_insn_and_split "*tstsi_variable_bit_qi"
696 (zero_extract:SI (zero_extend:SI (match_operand:QI
0 "general_operand_src" "r,U,mn>"))
698 (and:SI (match_operand:SI
1 "register_operand" "r,r,r")
700 (clobber (match_scratch:QI
2 "=X,X,&r"))]
701 "(TARGET_H8300H || TARGET_H8300S)"
707 && !EXTRA_CONSTRAINT (operands[
0], 'U')"
710 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup
2))
712 (and:SI (match_dup
1)
714 (clobber (scratch:QI))])]
716 [(set_attr "length" "
2,
8,
10")
717 (set_attr "cc" "set_zn,set_zn,set_zn")])
720 [(set (cc0) (match_operand:QI
0 "register_operand" "r"))]
723 [(set_attr "length" "
2")
724 (set_attr "cc" "set_znv")])
727 [(set (cc0) (match_operand:HI
0 "register_operand" "r"))]
730 [(set_attr "length" "
2")
731 (set_attr "cc" "set_znv")])
733 (define_insn "*tsthi_upper"
735 (and:HI (match_operand:HI
0 "register_operand" "r")
739 [(set_attr "length" "
2")
740 (set_attr "cc" "set_znv")])
743 [(set (cc0) (match_operand:SI
0 "register_operand" "r"))]
744 "TARGET_H8300H || TARGET_H8300S"
746 [(set_attr "length" "
2")
747 (set_attr "cc" "set_znv")])
749 (define_insn "*tstsi_upper"
751 (and:SI (match_operand:SI
0 "register_operand" "r")
752 (const_int -
65536)))]
755 [(set_attr "length" "
2")
756 (set_attr "cc" "set_znv")])
760 (compare (match_operand:QI
0 "register_operand" "r")
761 (match_operand:QI
1 "nonmemory_operand" "rn")))]
764 [(set_attr "length" "
2")
765 (set_attr "cc" "compare")])
767 (define_expand "cmphi"
769 (compare (match_operand:HI
0 "register_operand" "")
770 (match_operand:HI
1 "nonmemory_operand" "")))]
774 /* Force operand1 into a register if we're compiling
776 if (GET_CODE (operands[
1]) != REG && TARGET_H8300)
777 operands[
1] = force_reg (HImode, operands[
1]);
780 (define_insn "*cmphi_h8300"
782 (compare (match_operand:HI
0 "register_operand" "r")
783 (match_operand:HI
1 "register_operand" "r")))]
786 [(set_attr "length" "
2")
787 (set_attr "cc" "compare")])
789 (define_insn "*cmphi_h8300hs"
791 (compare (match_operand:HI
0 "register_operand" "r,r")
792 (match_operand:HI
1 "nonmemory_operand" "r,n")))]
793 "TARGET_H8300H || TARGET_H8300S"
795 [(set_attr "length" "
2,
4")
796 (set_attr "cc" "compare,compare")])
800 (compare (match_operand:SI
0 "register_operand" "r,r")
801 (match_operand:SI
1 "nonmemory_operand" "r,i")))]
802 "TARGET_H8300H || TARGET_H8300S"
804 [(set_attr "length" "
2,
6")
805 (set_attr "cc" "compare,compare")])
807 ;; ----------------------------------------------------------------------
809 ;; ----------------------------------------------------------------------
811 (define_insn "addqi3"
812 [(set (match_operand:QI
0 "register_operand" "=r")
813 (plus:QI (match_operand:QI
1 "register_operand" "%
0")
814 (match_operand:QI
2 "nonmemory_operand" "rn")))]
817 [(set_attr "length" "
2")
818 (set_attr "cc" "set_zn")])
820 (define_expand "addhi3"
821 [(set (match_operand:HI
0 "register_operand" "")
822 (plus:HI (match_operand:HI
1 "register_operand" "")
823 (match_operand:HI
2 "nonmemory_operand" "")))]
827 (define_insn "*addhi3_h8300"
828 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r,r")
829 (plus:HI (match_operand:HI
1 "register_operand" "%
0,
0,
0,
0,
0")
830 (match_operand:HI
2 "nonmemory_operand" "L,N,J,n,r")))]
836 add.b %s2,%s0\;addx %t2,%t0
838 [(set_attr "length" "
2,
2,
2,
4,
2")
839 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
841 ;; This splitter is very important to make the stack adjustment
842 ;; interrupt-safe. The combination of add.b and addx is unsafe!
844 ;; We apply this split after the peephole2 pass so that we won't end
845 ;; up creating too many adds/subs when a scratch register is
846 ;; available, which is actually a common case because stack unrolling
847 ;; tends to happen immediately after a function call.
850 [(set (match_operand:HI
0 "stack_pointer_operand" "")
851 (plus:HI (match_dup
0)
852 (match_operand
1 "const_int_gt_2_operand" "")))]
853 "TARGET_H8300 && flow2_completed"
855 "split_adds_subs (HImode, operands); DONE;")
858 [(match_scratch:HI
2 "r")
859 (set (match_operand:HI
0 "stack_pointer_operand" "")
860 (plus:HI (match_dup
0)
861 (match_operand:HI
1 "const_int_ge_8_operand" "")))]
866 (plus:HI (match_dup
0)
870 (define_insn "*addhi3_h8300hs"
871 [(set (match_operand:HI
0 "register_operand" "=r,r,r,r,r")
872 (plus:HI (match_operand:HI
1 "register_operand" "%
0,
0,
0,
0,
0")
873 (match_operand:HI
2 "nonmemory_operand" "L,N,J,n,r")))]
874 "TARGET_H8300H || TARGET_H8300S"
881 [(set_attr "length" "
2,
2,
2,
4,
2")
882 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
884 (define_insn "*addhi3_incdec"
885 [(set (match_operand:HI
0 "register_operand" "=r,r")
886 (unspec:HI [(match_operand:HI
1 "register_operand" "
0,
0")
887 (match_operand:HI
2 "incdec_operand" "M,O")]
889 "TARGET_H8300H || TARGET_H8300S"
893 [(set_attr "length" "
2,
2")
894 (set_attr "cc" "set_zn,set_zn")])
897 [(set (match_operand:HI
0 "register_operand" "")
898 (plus:HI (match_dup
0)
899 (match_operand:HI
1 "two_insn_adds_subs_operand" "")))]
902 "split_adds_subs (HImode, operands); DONE;")
904 (define_expand "addsi3"
905 [(set (match_operand:SI
0 "register_operand" "")
906 (plus:SI (match_operand:SI
1 "register_operand" "")
907 (match_operand:SI
2 "nonmemory_operand" "")))]
911 (define_insn "addsi_h8300"
912 [(set (match_operand:SI
0 "register_operand" "=r,r")
913 (plus:SI (match_operand:SI
1 "register_operand" "%
0,
0")
914 (match_operand:SI
2 "nonmemory_operand" "n,r")))]
916 "* return output_plussi (operands);"
917 [(set (attr "length")
918 (symbol_ref "compute_plussi_length (operands)"))
920 (symbol_ref "compute_plussi_cc (operands)"))])
922 (define_insn "addsi_h8300h"
923 [(set (match_operand:SI
0 "register_operand" "=r,r")
924 (plus:SI (match_operand:SI
1 "register_operand" "%
0,
0")
925 (match_operand:SI
2 "nonmemory_operand" "i,r")))]
926 "TARGET_H8300H || TARGET_H8300S"
927 "* return output_plussi (operands);"
928 [(set (attr "length")
929 (symbol_ref "compute_plussi_length (operands)"))
931 (symbol_ref "compute_plussi_cc (operands)"))])
933 (define_insn "*addsi3_incdec"
934 [(set (match_operand:SI
0 "register_operand" "=r,r")
935 (unspec:SI [(match_operand:SI
1 "register_operand" "
0,
0")
936 (match_operand:SI
2 "incdec_operand" "M,O")]
938 "TARGET_H8300H || TARGET_H8300S"
942 [(set_attr "length" "
2,
2")
943 (set_attr "cc" "set_zn,set_zn")])
946 [(set (match_operand:SI
0 "register_operand" "")
947 (plus:SI (match_dup
0)
948 (match_operand:SI
1 "two_insn_adds_subs_operand" "")))]
949 "TARGET_H8300H || TARGET_H8300S"
951 "split_adds_subs (SImode, operands); DONE;")
953 ;; ----------------------------------------------------------------------
954 ;; SUBTRACT INSTRUCTIONS
955 ;; ----------------------------------------------------------------------
957 (define_insn "subqi3"
958 [(set (match_operand:QI
0 "register_operand" "=r")
959 (minus:QI (match_operand:QI
1 "register_operand" "
0")
960 (match_operand:QI
2 "register_operand" "r")))]
963 [(set_attr "length" "
2")
964 (set_attr "cc" "set_zn")])
966 (define_expand "subhi3"
967 [(set (match_operand:HI
0 "register_operand" "")
968 (minus:HI (match_operand:HI
1 "general_operand" "")
969 (match_operand:HI
2 "nonmemory_operand" "")))]
973 (define_insn "*subhi3_h8300"
974 [(set (match_operand:HI
0 "register_operand" "=r,&r")
975 (minus:HI (match_operand:HI
1 "general_operand" "
0,
0")
976 (match_operand:HI
2 "nonmemory_operand" "r,n")))]
980 add.b %E2,%s0\;addx %F2,%t0"
981 [(set_attr "length" "
2,
4")
982 (set_attr "cc" "set_zn,clobber")])
984 (define_insn "*subhi3_h8300hs"
985 [(set (match_operand:HI
0 "register_operand" "=r,&r")
986 (minus:HI (match_operand:HI
1 "general_operand" "
0,
0")
987 (match_operand:HI
2 "nonmemory_operand" "r,n")))]
988 "TARGET_H8300H || TARGET_H8300S"
992 [(set_attr "length" "
2,
4")
993 (set_attr "cc" "set_zn,set_zn")])
995 (define_expand "subsi3"
996 [(set (match_operand:SI
0 "register_operand" "")
997 (minus:SI (match_operand:SI
1 "register_operand" "")
998 (match_operand:SI
2 "nonmemory_operand" "")))]
1002 (define_insn "subsi3_h8300"
1003 [(set (match_operand:SI
0 "register_operand" "=r")
1004 (minus:SI (match_operand:SI
1 "register_operand" "
0")
1005 (match_operand:SI
2 "register_operand" "r")))]
1007 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1008 [(set_attr "length" "
6")
1009 (set_attr "cc" "clobber")])
1011 (define_insn "subsi3_h8300h"
1012 [(set (match_operand:SI
0 "register_operand" "=r,r")
1013 (minus:SI (match_operand:SI
1 "general_operand" "
0,
0")
1014 (match_operand:SI
2 "nonmemory_operand" "r,i")))]
1015 "TARGET_H8300H || TARGET_H8300S"
1019 [(set_attr "length" "
2,
6")
1020 (set_attr "cc" "set_zn,set_zn")])
1022 ;; ----------------------------------------------------------------------
1023 ;; MULTIPLY INSTRUCTIONS
1024 ;; ----------------------------------------------------------------------
1026 ;; Note that the H8/
300 can only handle umulqihi3.
1028 (define_insn "mulqihi3"
1029 [(set (match_operand:HI
0 "register_operand" "=r")
1030 (mult:HI (sign_extend:HI (match_operand:QI
1 "register_operand" "%
0"))
1031 (sign_extend:HI (match_operand:QI
2 "register_operand" "r"))))]
1032 "TARGET_H8300H || TARGET_H8300S"
1034 [(set_attr "length" "
4")
1035 (set_attr "cc" "set_zn")])
1037 (define_insn "mulhisi3"
1038 [(set (match_operand:SI
0 "register_operand" "=r")
1039 (mult:SI (sign_extend:SI (match_operand:HI
1 "register_operand" "%
0"))
1040 (sign_extend:SI (match_operand:HI
2 "register_operand" "r"))))]
1041 "TARGET_H8300H || TARGET_H8300S"
1043 [(set_attr "length" "
4")
1044 (set_attr "cc" "set_zn")])
1046 (define_insn "umulqihi3"
1047 [(set (match_operand:HI
0 "register_operand" "=r")
1048 (mult:HI (zero_extend:HI (match_operand:QI
1 "register_operand" "%
0"))
1049 (zero_extend:HI (match_operand:QI
2 "register_operand" "r"))))]
1052 [(set_attr "length" "
2")
1053 (set_attr "cc" "none_0hit")])
1055 (define_insn "umulhisi3"
1056 [(set (match_operand:SI
0 "register_operand" "=r")
1057 (mult:SI (zero_extend:SI (match_operand:HI
1 "register_operand" "%
0"))
1058 (zero_extend:SI (match_operand:HI
2 "register_operand" "r"))))]
1059 "TARGET_H8300H || TARGET_H8300S"
1061 [(set_attr "length" "
2")
1062 (set_attr "cc" "none_0hit")])
1064 ;; This is a "bridge" instruction. Combine can't cram enough insns
1065 ;; together to crate a MAC instruction directly, but it can create
1066 ;; this instruction, which then allows combine to create the real
1069 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1070 ;; insn must generate reasonably correct code. Egad.
1072 [(set (match_operand:SI
0 "register_operand" "=a")
1075 (mem:HI (post_inc:SI (match_operand:SI
1 "register_operand" "r"))))
1077 (mem:HI (post_inc:SI (match_operand:SI
2 "register_operand" "r"))))))]
1079 "clrmac\;mac @%
2+,@%
1+"
1080 [(set_attr "length" "
6")
1081 (set_attr "cc" "none_0hit")])
1084 [(set (match_operand:SI
0 "register_operand" "=a")
1086 (sign_extend:SI (mem:HI
1087 (post_inc:SI (match_operand:SI
1 "register_operand" "r"))))
1088 (sign_extend:SI (mem:HI
1089 (post_inc:SI (match_operand:SI
2 "register_operand" "r")))))
1090 (match_operand:SI
3 "register_operand" "
0")))]
1093 [(set_attr "length" "
4")
1094 (set_attr "cc" "none_0hit")])
1096 ;; ----------------------------------------------------------------------
1097 ;; DIVIDE/MOD INSTRUCTIONS
1098 ;; ----------------------------------------------------------------------
1100 (define_insn "udivmodqi4"
1101 [(set (match_operand:QI
0 "register_operand" "=r")
1104 (match_operand:HI
1 "register_operand" "
0")
1105 (zero_extend:HI (match_operand:QI
2 "register_operand" "r")))))
1106 (set (match_operand:QI
3 "register_operand" "=r")
1110 (zero_extend:HI (match_dup
2)))))]
1114 if (find_reg_note (insn, REG_UNUSED, operands[
3]))
1115 return
\"divxu.b
\\t%X2,%T0
\";
1117 return
\"divxu.b
\\t%X2,%T0\;mov.b
\\t%t0,%s3
\";
1119 [(set_attr "length" "
4")
1120 (set_attr "cc" "clobber")])
1122 (define_insn "divmodqi4"
1123 [(set (match_operand:QI
0 "register_operand" "=r")
1126 (match_operand:HI
1 "register_operand" "
0")
1127 (sign_extend:HI (match_operand:QI
2 "register_operand" "r")))))
1128 (set (match_operand:QI
3 "register_operand" "=r")
1132 (sign_extend:HI (match_dup
2)))))]
1133 "TARGET_H8300H || TARGET_H8300S"
1136 if (find_reg_note (insn, REG_UNUSED, operands[
3]))
1137 return
\"divxs.b
\\t%X2,%T0
\";
1139 return
\"divxs.b
\\t%X2,%T0\;mov.b
\\t%t0,%s3
\";
1141 [(set_attr "length" "
6")
1142 (set_attr "cc" "clobber")])
1144 (define_insn "udivmodhi4"
1145 [(set (match_operand:HI
0 "register_operand" "=r")
1148 (match_operand:SI
1 "register_operand" "
0")
1149 (zero_extend:SI (match_operand:HI
2 "register_operand" "r")))))
1150 (set (match_operand:HI
3 "register_operand" "=r")
1154 (zero_extend:SI (match_dup
2)))))]
1155 "TARGET_H8300H || TARGET_H8300S"
1158 if (find_reg_note (insn, REG_UNUSED, operands[
3]))
1159 return
\"divxu.w
\\t%T2,%S0
\";
1161 return
\"divxu.w
\\t%T2,%S0\;mov.w
\\t%e0,%f3
\";
1163 [(set_attr "length" "
4")
1164 (set_attr "cc" "clobber")])
1166 (define_insn "divmodhi4"
1167 [(set (match_operand:HI
0 "register_operand" "=r")
1170 (match_operand:SI
1 "register_operand" "
0")
1171 (sign_extend:SI (match_operand:HI
2 "register_operand" "r")))))
1172 (set (match_operand:HI
3 "register_operand" "=r")
1176 (sign_extend:SI (match_dup
2)))))]
1177 "TARGET_H8300H || TARGET_H8300S"
1180 if (find_reg_note (insn, REG_UNUSED, operands[
3]))
1181 return
\"divxs.w
\\t%T2,%S0
\";
1183 return
\"divxs.w
\\t%T2,%S0\;mov.w
\\t%e0,%f3
\";
1185 [(set_attr "length" "
6")
1186 (set_attr "cc" "clobber")])
1188 ;; ----------------------------------------------------------------------
1190 ;; ----------------------------------------------------------------------
1192 (define_insn "*andqi3_1"
1193 [(set (match_operand:QI
0 "bit_operand" "=r,U")
1194 (and:QI (match_operand:QI
1 "bit_operand" "%
0,
0")
1195 (match_operand:QI
2 "nonmemory_operand" "rn,n")))]
1196 "register_operand (operands[
0], QImode)
1197 || single_zero_operand (operands[
2], QImode)"
1201 [(set_attr "length" "
2,
8")
1202 (set_attr "cc" "set_znv,none_0hit")])
1204 (define_expand "andqi3"
1205 [(set (match_operand:QI
0 "bit_operand" "")
1206 (and:QI (match_operand:QI
1 "bit_operand" "")
1207 (match_operand:QI
2 "nonmemory_operand" "")))]
1211 if (fix_bit_operand (operands,
0, AND))
1215 (define_expand "andhi3"
1216 [(set (match_operand:HI
0 "register_operand" "")
1217 (and:HI (match_operand:HI
1 "register_operand" "")
1218 (match_operand:HI
2 "nonmemory_operand" "")))]
1222 (define_insn "*andorqi3"
1223 [(set (match_operand:QI
0 "register_operand" "=r")
1224 (ior:QI (and:QI (match_operand:QI
2 "register_operand" "r")
1225 (match_operand:QI
3 "single_one_operand" "n"))
1226 (match_operand:QI
1 "register_operand" "
0")))]
1228 "bld
\\t%V3,%X2\;bor
\\t%V3,%X0\;bst
\\t%V3,%X0"
1229 [(set_attr "length" "
6")
1230 (set_attr "cc" "clobber")])
1232 (define_insn "*andorhi3"
1233 [(set (match_operand:HI
0 "register_operand" "=r")
1234 (ior:HI (and:HI (match_operand:HI
2 "register_operand" "r")
1235 (match_operand:HI
3 "single_one_operand" "n"))
1236 (match_operand:HI
1 "register_operand" "
0")))]
1240 operands[
3] = GEN_INT (INTVAL (operands[
3]) &
0xffff);
1241 if (INTVAL (operands[
3]) >
128)
1243 operands[
3] = GEN_INT (INTVAL (operands[
3]) >>
8);
1244 return
\"bld
\\t%V3,%t2\;bor
\\t%V3,%t0\;bst
\\t%V3,%t0
\";
1246 return
\"bld
\\t%V3,%s2\;bor
\\t%V3,%s0\;bst
\\t%V3,%s0
\";
1248 [(set_attr "length" "
6")
1249 (set_attr "cc" "clobber")])
1251 (define_insn "*andorsi3"
1252 [(set (match_operand:SI
0 "register_operand" "=r")
1253 (ior:SI (and:SI (match_operand:SI
2 "register_operand" "r")
1254 (match_operand:SI
3 "single_one_operand" "n"))
1255 (match_operand:SI
1 "register_operand" "
0")))]
1256 "(INTVAL (operands[
3]) &
0xffff) !=
0"
1259 operands[
3] = GEN_INT (INTVAL (operands[
3]) &
0xffff);
1260 if (INTVAL (operands[
3]) >
128)
1262 operands[
3] = GEN_INT (INTVAL (operands[
3]) >>
8);
1263 return
\"bld
\\t%V3,%x2\;bor
\\t%V3,%x0\;bst
\\t%V3,%x0
\";
1265 return
\"bld
\\t%V3,%w2\;bor
\\t%V3,%w0\;bst
\\t%V3,%w0
\";
1267 [(set_attr "length" "
6")
1268 (set_attr "cc" "clobber")])
1270 (define_insn "*andorsi3_shift_8"
1271 [(set (match_operand:SI
0 "register_operand" "=r")
1272 (ior:SI (and:SI (ashift:SI (match_operand:SI
2 "register_operand" "r")
1275 (match_operand:SI
1 "register_operand" "
0")))]
1278 [(set_attr "length" "
2")
1279 (set_attr "cc" "clobber")])
1281 (define_expand "andsi3"
1282 [(set (match_operand:SI
0 "register_operand" "")
1283 (and:SI (match_operand:SI
1 "register_operand" "")
1284 (match_operand:SI
2 "nonmemory_operand" "")))]
1288 ;; ----------------------------------------------------------------------
1290 ;; ----------------------------------------------------------------------
1292 (define_insn "*iorqi3_1"
1293 [(set (match_operand:QI
0 "bit_operand" "=r,U")
1294 (ior:QI (match_operand:QI
1 "bit_operand" "%
0,
0")
1295 (match_operand:QI
2 "nonmemory_operand" "rn,n")))]
1296 "register_operand (operands[
0], QImode)
1297 || single_one_operand (operands[
2], QImode)"
1301 [(set_attr "length" "
2,
8")
1302 (set_attr "cc" "set_znv,none_0hit")])
1304 (define_expand "iorqi3"
1305 [(set (match_operand:QI
0 "bit_operand" "")
1306 (ior:QI (match_operand:QI
1 "bit_operand" "")
1307 (match_operand:QI
2 "nonmemory_operand" "")))]
1311 if (fix_bit_operand (operands,
1, IOR))
1315 (define_expand "iorhi3"
1316 [(set (match_operand:HI
0 "register_operand" "")
1317 (ior:HI (match_operand:HI
1 "register_operand" "")
1318 (match_operand:HI
2 "nonmemory_operand" "")))]
1322 (define_expand "iorsi3"
1323 [(set (match_operand:SI
0 "register_operand" "")
1324 (ior:SI (match_operand:SI
1 "register_operand" "")
1325 (match_operand:SI
2 "nonmemory_operand" "")))]
1329 ;; ----------------------------------------------------------------------
1331 ;; ----------------------------------------------------------------------
1333 (define_insn "*xorqi3_1"
1334 [(set (match_operand:QI
0 "bit_operand" "=r,U")
1335 (xor:QI (match_operand:QI
1 "bit_operand" "%
0,
0")
1336 (match_operand:QI
2 "nonmemory_operand" "rn,n")))]
1337 "register_operand (operands[
0], QImode)
1338 || single_one_operand (operands[
2], QImode)"
1342 [(set_attr "length" "
2,
8")
1343 (set_attr "cc" "set_znv,none_0hit")])
1345 (define_expand "xorqi3"
1346 [(set (match_operand:QI
0 "bit_operand" "")
1347 (xor:QI (match_operand:QI
1 "bit_operand" "")
1348 (match_operand:QI
2 "nonmemory_operand" "")))]
1352 if (fix_bit_operand (operands,
1, XOR))
1356 (define_expand "xorhi3"
1357 [(set (match_operand:HI
0 "register_operand" "")
1358 (xor:HI (match_operand:HI
1 "register_operand" "")
1359 (match_operand:HI
2 "nonmemory_operand" "")))]
1363 (define_expand "xorsi3"
1364 [(set (match_operand:SI
0 "register_operand" "")
1365 (xor:SI (match_operand:SI
1 "register_operand" "")
1366 (match_operand:SI
2 "nonmemory_operand" "")))]
1370 ;; ----------------------------------------------------------------------
1371 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1372 ;; ----------------------------------------------------------------------
1374 (define_insn "*logicalhi3"
1375 [(set (match_operand:HI
0 "register_operand" "=r")
1376 (match_operator:HI
3 "bit_operator"
1377 [(match_operand:HI
1 "register_operand" "%
0")
1378 (match_operand:HI
2 "nonmemory_operand" "rn")]))]
1380 "* return output_logical_op (HImode, operands);"
1381 [(set (attr "length")
1382 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1384 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1386 (define_insn "*logicalsi3"
1387 [(set (match_operand:SI
0 "register_operand" "=r")
1388 (match_operator:SI
3 "bit_operator"
1389 [(match_operand:SI
1 "register_operand" "%
0")
1390 (match_operand:SI
2 "nonmemory_operand" "rn")]))]
1392 "* return output_logical_op (SImode, operands);"
1393 [(set (attr "length")
1394 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1396 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1398 ;; ----------------------------------------------------------------------
1399 ;; NEGATION INSTRUCTIONS
1400 ;; ----------------------------------------------------------------------
1402 (define_insn "negqi2"
1403 [(set (match_operand:QI
0 "register_operand" "=r")
1404 (neg:QI (match_operand:QI
1 "register_operand" "
0")))]
1407 [(set_attr "length" "
2")
1408 (set_attr "cc" "set_zn")])
1410 (define_expand "neghi2"
1411 [(set (match_operand:HI
0 "register_operand" "")
1412 (neg:HI (match_operand:HI
1 "register_operand" "")))]
1418 emit_insn (gen_neghi2_h8300 (operands[
0], operands[
1]));
1423 (define_expand "neghi2_h8300"
1425 (not:HI (match_operand:HI
1 "register_operand" "")))
1426 (set (match_dup
2) (plus:HI (match_dup
2) (const_int
1)))
1427 (set (match_operand:HI
0 "register_operand" "")
1430 "operands[
2] = gen_reg_rtx (HImode);")
1432 (define_insn "neghi2_h8300h"
1433 [(set (match_operand:HI
0 "register_operand" "=r")
1434 (neg:HI (match_operand:HI
1 "register_operand" "
0")))]
1435 "TARGET_H8300H || TARGET_H8300S"
1437 [(set_attr "length" "
2")
1438 (set_attr "cc" "set_zn")])
1440 (define_expand "negsi2"
1441 [(set (match_operand:SI
0 "register_operand" "")
1442 (neg:SI (match_operand:SI
1 "register_operand" "")))]
1448 emit_insn (gen_negsi2_h8300 (operands[
0], operands[
1]));
1453 (define_expand "negsi2_h8300"
1455 (not:SI (match_operand:SI
1 "register_operand" "")))
1456 (set (match_dup
2) (plus:SI (match_dup
2) (const_int
1)))
1457 (set (match_operand:SI
0 "register_operand" "")
1460 "operands[
2] = gen_reg_rtx (SImode);")
1462 (define_insn "negsi2_h8300h"
1463 [(set (match_operand:SI
0 "register_operand" "=r")
1464 (neg:SI (match_operand:SI
1 "register_operand" "
0")))]
1465 "TARGET_H8300H || TARGET_H8300S"
1467 [(set_attr "length" "
2")
1468 (set_attr "cc" "set_zn")])
1470 (define_expand "negsf2"
1471 [(set (match_operand:SF
0 "register_operand" "")
1472 (neg:SF (match_operand:SF
1 "register_operand" "")))]
1476 (define_insn "*negsf2_h8300"
1477 [(set (match_operand:SF
0 "register_operand" "=r")
1478 (neg:SF (match_operand:SF
1 "register_operand" "
0")))]
1481 [(set_attr "cc" "clobber")
1482 (set_attr "length" "
2")])
1484 (define_insn "*negsf2_h8300hs"
1485 [(set (match_operand:SF
0 "register_operand" "=r")
1486 (neg:SF (match_operand:SF
1 "register_operand" "
0")))]
1487 "TARGET_H8300H || TARGET_H8300S"
1488 "xor.w
\\t#
32768,%e0"
1489 [(set_attr "cc" "clobber")
1490 (set_attr "length" "
4")])
1492 ;; ----------------------------------------------------------------------
1493 ;; ABSOLUTE VALUE INSTRUCTIONS
1494 ;; ----------------------------------------------------------------------
1496 (define_expand "abssf2"
1497 [(set (match_operand:SF
0 "register_operand" "")
1498 (abs:SF (match_operand:SF
1 "register_operand" "")))]
1502 (define_insn "*abssf2_h8300"
1503 [(set (match_operand:SF
0 "register_operand" "=r")
1504 (abs:SF (match_operand:SF
1 "register_operand" "
0")))]
1507 [(set_attr "cc" "clobber")
1508 (set_attr "length" "
2")])
1510 (define_insn "*abssf2_h8300hs"
1511 [(set (match_operand:SF
0 "register_operand" "=r")
1512 (abs:SF (match_operand:SF
1 "register_operand" "
0")))]
1513 "TARGET_H8300H || TARGET_H8300S"
1514 "and.w
\\t#
32767,%e0"
1515 [(set_attr "cc" "clobber")
1516 (set_attr "length" "
4")])
1518 ;; ----------------------------------------------------------------------
1520 ;; ----------------------------------------------------------------------
1522 (define_insn "one_cmplqi2"
1523 [(set (match_operand:QI
0 "register_operand" "=r")
1524 (not:QI (match_operand:QI
1 "register_operand" "
0")))]
1527 [(set_attr "length" "
2")
1528 (set_attr "cc" "set_znv")])
1530 (define_expand "one_cmplhi2"
1531 [(set (match_operand:HI
0 "register_operand" "=r")
1532 (not:HI (match_operand:HI
1 "register_operand" "
0")))]
1536 (define_insn "*one_cmplhi2_h8300"
1537 [(set (match_operand:HI
0 "register_operand" "=r")
1538 (not:HI (match_operand:HI
1 "register_operand" "
0")))]
1541 [(set_attr "cc" "clobber")
1542 (set_attr "length" "
4")])
1544 (define_insn "*one_cmplhi2_h8300hs"
1545 [(set (match_operand:HI
0 "register_operand" "=r")
1546 (not:HI (match_operand:HI
1 "register_operand" "
0")))]
1547 "TARGET_H8300H || TARGET_H8300S"
1549 [(set_attr "cc" "set_znv")
1550 (set_attr "length" "
2")])
1552 (define_expand "one_cmplsi2"
1553 [(set (match_operand:SI
0 "register_operand" "=r")
1554 (not:SI (match_operand:SI
1 "register_operand" "
0")))]
1558 (define_insn "*one_complsi2_h8300"
1559 [(set (match_operand:SI
0 "register_operand" "=r")
1560 (not:SI (match_operand:SI
1 "register_operand" "
0")))]
1562 "not %w0\;not %x0\;not %y0\;not %z0"
1563 [(set_attr "cc" "clobber")
1564 (set_attr "length" "
8")])
1566 (define_insn "*one_complsi2_h8300hs"
1567 [(set (match_operand:SI
0 "register_operand" "=r")
1568 (not:SI (match_operand:SI
1 "register_operand" "
0")))]
1569 "TARGET_H8300H || TARGET_H8300S"
1571 [(set_attr "cc" "set_znv")
1572 (set_attr "length" "
2")])
1574 ;; ----------------------------------------------------------------------
1575 ;; JUMP INSTRUCTIONS
1576 ;; ----------------------------------------------------------------------
1578 ;; Conditional jump instructions
1580 (define_expand "ble"
1582 (if_then_else (le (cc0)
1584 (label_ref (match_operand
0 "" ""))
1589 (define_expand "bleu"
1591 (if_then_else (leu (cc0)
1593 (label_ref (match_operand
0 "" ""))
1598 (define_expand "bge"
1600 (if_then_else (ge (cc0)
1602 (label_ref (match_operand
0 "" ""))
1607 (define_expand "bgeu"
1609 (if_then_else (geu (cc0)
1611 (label_ref (match_operand
0 "" ""))
1616 (define_expand "blt"
1618 (if_then_else (lt (cc0)
1620 (label_ref (match_operand
0 "" ""))
1625 (define_expand "bltu"
1627 (if_then_else (ltu (cc0)
1629 (label_ref (match_operand
0 "" ""))
1634 (define_expand "bgt"
1636 (if_then_else (gt (cc0)
1638 (label_ref (match_operand
0 "" ""))
1643 (define_expand "bgtu"
1645 (if_then_else (gtu (cc0)
1647 (label_ref (match_operand
0 "" ""))
1652 (define_expand "beq"
1654 (if_then_else (eq (cc0)
1656 (label_ref (match_operand
0 "" ""))
1661 (define_expand "bne"
1663 (if_then_else (ne (cc0)
1665 (label_ref (match_operand
0 "" ""))
1670 (define_insn "branch_true"
1672 (if_then_else (match_operator
1 "comparison_operator"
1673 [(cc0) (const_int
0)])
1674 (label_ref (match_operand
0 "" ""))
1679 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) !=
0
1680 && (GET_CODE (operands[
1]) == GT
1681 || GET_CODE (operands[
1]) == GE
1682 || GET_CODE (operands[
1]) == LE
1683 || GET_CODE (operands[
1]) == LT))
1685 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1689 if (get_attr_length (insn) ==
2)
1690 return
\"b%j1 %l0
\";
1691 else if (get_attr_length (insn) ==
4)
1692 return
\"b%j1 %l0:
16\";
1694 return
\"b%k1 .Lh8BR%=\;jmp @%l0
\\n.Lh8BR%=:
\";
1696 [(set_attr "type" "branch")
1697 (set_attr "cc" "none")])
1699 (define_insn "branch_false"
1701 (if_then_else (match_operator
1 "comparison_operator"
1702 [(cc0) (const_int
0)])
1704 (label_ref (match_operand
0 "" ""))))]
1708 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) !=
0
1709 && (GET_CODE (operands[
1]) == GT
1710 || GET_CODE (operands[
1]) == GE
1711 || GET_CODE (operands[
1]) == LE
1712 || GET_CODE (operands[
1]) == LT))
1714 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1718 if (get_attr_length (insn) ==
2)
1719 return
\"b%k1 %l0
\";
1720 else if (get_attr_length (insn) ==
4)
1721 return
\"b%k1 %l0:
16\";
1723 return
\"b%j1 .Lh8BR%=\;jmp @%l0
\\n.Lh8BR%=:
\";
1725 [(set_attr "type" "branch")
1726 (set_attr "cc" "none")])
1728 ;; Unconditional and other jump instructions.
1732 (label_ref (match_operand
0 "" "")))]
1736 if (get_attr_length (insn) ==
2)
1738 else if (get_attr_length (insn) ==
4)
1739 return
\"bra %l0:
16\";
1741 return
\"jmp @%l0
\";
1743 [(set_attr "type" "branch")
1744 (set_attr "cc" "none")])
1746 ;; This is a define expand, because pointers may be either
16 or
32 bits.
1748 (define_expand "tablejump"
1749 [(parallel [(set (pc) (match_operand
0 "register_operand" ""))
1750 (use (label_ref (match_operand
1 "" "")))])]
1754 (define_insn "*tablejump_h8300"
1755 [(set (pc) (match_operand:HI
0 "register_operand" "r"))
1756 (use (label_ref (match_operand
1 "" "")))]
1759 [(set_attr "cc" "none")
1760 (set_attr "length" "
2")])
1762 (define_insn "*tablejump_h8300hs_advanced"
1763 [(set (pc) (match_operand:SI
0 "register_operand" "r"))
1764 (use (label_ref (match_operand
1 "" "")))]
1765 "TARGET_H8300H || TARGET_H8300S"
1767 [(set_attr "cc" "none")
1768 (set_attr "length" "
2")])
1770 (define_insn "*tablejump_h8300hs_normal"
1771 [(set (pc) (match_operand:HI
0 "register_operand" "r"))
1772 (use (label_ref (match_operand
1 "" "")))]
1773 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1775 [(set_attr "cc" "none")
1776 (set_attr "length" "
2")])
1778 ;; This is a define expand, because pointers may be either
16 or
32 bits.
1780 (define_expand "indirect_jump"
1781 [(set (pc) (match_operand
0 "jump_address_operand" ""))]
1785 (define_insn "*indirect_jump_h8300"
1786 [(set (pc) (match_operand:HI
0 "jump_address_operand" "Vr"))]
1789 [(set_attr "cc" "none")
1790 (set_attr "length" "
2")])
1792 (define_insn "*indirect_jump_h8300hs_advanced"
1793 [(set (pc) (match_operand:SI
0 "jump_address_operand" "Vr"))]
1794 "TARGET_H8300H || TARGET_H8300S"
1796 [(set_attr "cc" "none")
1797 (set_attr "length" "
2")])
1799 (define_insn "*indirect_jump_h8300hs_normal"
1800 [(set (pc) (match_operand:HI
0 "jump_address_operand" "Vr"))]
1801 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1803 [(set_attr "cc" "none")
1804 (set_attr "length" "
2")])
1806 ;; Call subroutine with no return value.
1808 ;; ??? Even though we use HImode here, this works on the H8/
300H and H8S.
1811 [(call (match_operand:QI
0 "call_insn_operand" "or")
1812 (match_operand:HI
1 "general_operand" "g"))]
1816 if (GET_CODE (XEXP (operands[
0],
0)) == SYMBOL_REF
1817 && SYMBOL_REF_FLAG (XEXP (operands[
0],
0)))
1818 return
\"jsr
\\t@%
0:
8\";
1820 return
\"jsr
\\t%
0\";
1822 [(set_attr "cc" "clobber")
1823 (set (attr "length")
1824 (if_then_else (match_operand:QI
0 "small_call_insn_operand" "")
1828 ;; Call subroutine, returning value in operand
0
1829 ;; (which must be a hard register).
1831 ;; ??? Even though we use HImode here, this works on the H8/
300H and H8S.
1833 (define_insn "call_value"
1834 [(set (match_operand
0 "" "=r")
1835 (call (match_operand:QI
1 "call_insn_operand" "or")
1836 (match_operand:HI
2 "general_operand" "g")))]
1840 if (GET_CODE (XEXP (operands[
1],
0)) == SYMBOL_REF
1841 && SYMBOL_REF_FLAG (XEXP (operands[
1],
0)))
1842 return
\"jsr
\\t@%
1:
8\";
1844 return
\"jsr
\\t%
1\";
1846 [(set_attr "cc" "clobber")
1847 (set (attr "length")
1848 (if_then_else (match_operand:QI
0 "small_call_insn_operand" "")
1856 [(set_attr "cc" "none")
1857 (set_attr "length" "
2")])
1859 ;; ----------------------------------------------------------------------
1860 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1861 ;; ----------------------------------------------------------------------
1863 (define_expand "push_h8300"
1864 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1865 (match_operand:HI
0 "register_operand" ""))]
1869 (define_expand "push_h8300hs"
1870 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1871 (match_operand:SI
0 "register_operand" ""))]
1872 "TARGET_H8300H && TARGET_H8300S"
1875 (define_expand "push_h8300hs_normal"
1876 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1877 (match_operand:SI
0 "register_operand" ""))]
1878 "TARGET_NORMAL_MODE"
1881 (define_expand "pop_h8300"
1882 [(set (match_operand:HI
0 "register_operand" "")
1883 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1887 (define_expand "pop_h8300hs"
1888 [(set (match_operand:SI
0 "register_operand" "")
1889 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1890 "TARGET_H8300H && TARGET_H8300S"
1893 (define_expand "pop_h8300hs_normal"
1894 [(set (match_operand:SI
0 "register_operand" "")
1895 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1896 "TARGET_NORMAL_MODE"
1899 (define_insn "stm_h8300s_2_advanced"
1901 [(set (reg:SI SP_REG)
1902 (plus:SI (reg:SI SP_REG) (const_int -
8)))
1903 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
4)))
1904 (match_operand:SI
0 "register_operand" ""))
1905 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
8)))
1906 (match_operand:SI
1 "register_operand" ""))])]
1907 "TARGET_H8300S && !TARGET_NORMAL_MODE
1908 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
1909 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
1910 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
1911 "stm.l
\\t%S0-%S1,@-er7"
1912 [(set_attr "cc" "none")
1913 (set_attr "length" "
4")])
1915 (define_insn "stm_h8300s_2_normal"
1917 [(set (reg:HI SP_REG)
1918 (plus:HI (reg:HI SP_REG) (const_int -
8)))
1919 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
4)))
1920 (match_operand:SI
0 "register_operand" ""))
1921 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
8)))
1922 (match_operand:SI
1 "register_operand" ""))])]
1923 "TARGET_H8300S && TARGET_NORMAL_MODE
1924 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
1925 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
1926 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
1927 "stm.l
\\t%S0-%S1,@-er7"
1928 [(set_attr "cc" "none")
1929 (set_attr "length" "
4")])
1931 (define_expand "stm_h8300s_2"
1932 [(use (match_operand:SI
0 "register_operand" ""))
1933 (use (match_operand:SI
1 "register_operand" ""))]
1935 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
1936 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
1937 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
1940 if (!TARGET_NORMAL_MODE)
1941 emit_insn (gen_stm_h8300s_2_advanced (operands[
0], operands[
1]));
1943 emit_insn (gen_stm_h8300s_2_normal (operands[
0], operands[
1]));
1947 (define_insn "stm_h8300s_3_advanced"
1949 [(set (reg:SI SP_REG)
1950 (plus:SI (reg:SI SP_REG) (const_int -
12)))
1951 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
4)))
1952 (match_operand:SI
0 "register_operand" ""))
1953 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
8)))
1954 (match_operand:SI
1 "register_operand" ""))
1955 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
12)))
1956 (match_operand:SI
2 "register_operand" ""))])]
1957 "TARGET_H8300S && !TARGET_NORMAL_MODE
1958 && ((REGNO (operands[
0]) ==
0
1959 && REGNO (operands[
1]) ==
1
1960 && REGNO (operands[
2]) ==
2)
1961 || (REGNO (operands[
0]) ==
4
1962 && REGNO (operands[
1]) ==
5
1963 && REGNO (operands[
2]) ==
6))"
1964 "stm.l
\\t%S0-%S2,@-er7"
1965 [(set_attr "cc" "none")
1966 (set_attr "length" "
4")])
1968 (define_insn "stm_h8300s_3_normal"
1970 [(set (reg:HI SP_REG)
1971 (plus:HI (reg:HI SP_REG) (const_int -
12)))
1972 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
4)))
1973 (match_operand:SI
0 "register_operand" ""))
1974 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
8)))
1975 (match_operand:SI
1 "register_operand" ""))
1976 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
12)))
1977 (match_operand:SI
2 "register_operand" ""))])]
1978 "TARGET_H8300S && TARGET_NORMAL_MODE
1979 && ((REGNO (operands[
0]) ==
0
1980 && REGNO (operands[
1]) ==
1
1981 && REGNO (operands[
2]) ==
2)
1982 || (REGNO (operands[
0]) ==
4
1983 && REGNO (operands[
1]) ==
5
1984 && REGNO (operands[
2]) ==
6))"
1985 "stm.l
\\t%S0-%S2,@-er7"
1986 [(set_attr "cc" "none")
1987 (set_attr "length" "
4")])
1989 (define_expand "stm_h8300s_3"
1990 [(use (match_operand:SI
0 "register_operand" ""))
1991 (use (match_operand:SI
1 "register_operand" ""))
1992 (use (match_operand:SI
2 "register_operand" ""))]
1994 && ((REGNO (operands[
0]) ==
0
1995 && REGNO (operands[
1]) ==
1
1996 && REGNO (operands[
2]) ==
2)
1997 || (REGNO (operands[
0]) ==
4
1998 && REGNO (operands[
1]) ==
5
1999 && REGNO (operands[
2]) ==
6))"
2002 if (!TARGET_NORMAL_MODE)
2003 emit_insn (gen_stm_h8300s_3_advanced (operands[
0], operands[
1],
2006 emit_insn (gen_stm_h8300s_3_normal (operands[
0], operands[
1],
2011 (define_insn "stm_h8300s_4_advanced"
2013 [(set (reg:SI SP_REG)
2014 (plus:SI (reg:SI SP_REG) (const_int -
16)))
2015 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
4)))
2016 (match_operand:SI
0 "register_operand" ""))
2017 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
8)))
2018 (match_operand:SI
1 "register_operand" ""))
2019 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
12)))
2020 (match_operand:SI
2 "register_operand" ""))
2021 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
16)))
2022 (match_operand:SI
3 "register_operand" ""))])]
2023 "TARGET_H8300S && !TARGET_NORMAL_MODE
2024 && REGNO (operands[
0]) ==
0
2025 && REGNO (operands[
1]) ==
1
2026 && REGNO (operands[
2]) ==
2
2027 && REGNO (operands[
3]) ==
3"
2028 "stm.l
\\t%S0-%S3,@-er7"
2029 [(set_attr "cc" "none")
2030 (set_attr "length" "
4")])
2032 (define_insn "stm_h8300s_4_normal"
2034 [(set (reg:HI SP_REG)
2035 (plus:HI (reg:HI SP_REG) (const_int -
16)))
2036 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
4)))
2037 (match_operand:SI
0 "register_operand" ""))
2038 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
8)))
2039 (match_operand:SI
1 "register_operand" ""))
2040 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
12)))
2041 (match_operand:SI
2 "register_operand" ""))
2042 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
16)))
2043 (match_operand:SI
3 "register_operand" ""))])]
2044 "TARGET_H8300S && TARGET_NORMAL_MODE
2045 && REGNO (operands[
0]) ==
0
2046 && REGNO (operands[
1]) ==
1
2047 && REGNO (operands[
2]) ==
2
2048 && REGNO (operands[
3]) ==
3"
2049 "stm.l
\\t%S0-%S3,@-er7"
2050 [(set_attr "cc" "none")
2051 (set_attr "length" "
4")])
2053 (define_expand "stm_h8300s_4"
2054 [(use (match_operand:SI
0 "register_operand" ""))
2055 (use (match_operand:SI
1 "register_operand" ""))
2056 (use (match_operand:SI
2 "register_operand" ""))
2057 (use (match_operand:SI
3 "register_operand" ""))]
2059 && REGNO (operands[
0]) ==
0
2060 && REGNO (operands[
1]) ==
1
2061 && REGNO (operands[
2]) ==
2
2062 && REGNO (operands[
3]) ==
3"
2065 if (!TARGET_NORMAL_MODE)
2066 emit_insn (gen_stm_h8300s_4_advanced (operands[
0], operands[
1],
2067 operands[
2], operands[
3]));
2069 emit_insn (gen_stm_h8300s_4_normal (operands[
0], operands[
1],
2070 operands[
2], operands[
3]));
2074 (define_insn "ldm_h8300s_2_advanced"
2076 [(set (reg:SI SP_REG)
2077 (plus:SI (reg:SI SP_REG) (const_int
8)))
2078 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int
4)))
2079 (match_operand:SI
0 "register_operand" ""))
2080 (set (mem:SI (reg:SI SP_REG))
2081 (match_operand:SI
1 "register_operand" ""))])]
2082 "TARGET_H8300S && !TARGET_NORMAL_MODE
2083 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
2084 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
2085 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
2086 "ldm.l
\\t@er7+,%S0-%S1"
2087 [(set_attr "cc" "none")
2088 (set_attr "length" "
4")])
2090 (define_insn "ldm_h8300s_2_normal"
2092 [(set (reg:SI SP_REG)
2093 (plus:SI (reg:SI SP_REG) (const_int
8)))
2094 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int
4)))
2095 (match_operand:SI
0 "register_operand" ""))
2096 (set (mem:SI (reg:SI SP_REG))
2097 (match_operand:SI
1 "register_operand" ""))])]
2098 "TARGET_H8300S && TARGET_NORMAL_MODE
2099 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
2100 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
2101 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
2102 "ldm.l
\\t@er7+,%S0-%S1"
2103 [(set_attr "cc" "none")
2104 (set_attr "length" "
4")])
2106 (define_expand "ldm_h8300s_2"
2107 [(use (match_operand:SI
0 "register_operand" ""))
2108 (use (match_operand:SI
1 "register_operand" ""))]
2110 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
2111 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
2112 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
2115 if (!TARGET_NORMAL_MODE)
2116 emit_insn (gen_ldm_h8300s_2_advanced (operands[
0], operands[
1]));
2118 emit_insn (gen_ldm_h8300s_2_normal (operands[
0], operands[
1]));
2122 (define_insn "ldm_h8300s_3_advanced"
2124 [(set (reg:SI SP_REG)
2125 (plus:SI (reg:SI SP_REG) (const_int
12)))
2126 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int
8)))
2127 (match_operand:SI
0 "register_operand" ""))
2128 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int
4)))
2129 (match_operand:SI
1 "register_operand" ""))
2130 (set (mem:SI (reg:SI SP_REG))
2131 (match_operand:SI
2 "register_operand" ""))])]
2132 "TARGET_H8300S && !TARGET_NORMAL_MODE
2133 && ((REGNO (operands[
0]) ==
0
2134 && REGNO (operands[
1]) ==
1
2135 && REGNO (operands[
2]) ==
2)
2136 || (REGNO (operands[
0]) ==
4
2137 && REGNO (operands[
1]) ==
5
2138 && REGNO (operands[
2]) ==
6))"
2139 "ldm.l
\\t@er7+,%S0-%S2"
2140 [(set_attr "cc" "none")
2141 (set_attr "length" "
4")])
2143 (define_insn "ldm_h8300s_3_normal"
2145 [(set (reg:HI SP_REG)
2146 (plus:HI (reg:HI SP_REG) (const_int
12)))
2147 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int
8)))
2148 (match_operand:SI
0 "register_operand" ""))
2149 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int
4)))
2150 (match_operand:SI
1 "register_operand" ""))
2151 (set (mem:SI (reg:HI SP_REG))
2152 (match_operand:SI
2 "register_operand" ""))])]
2153 "TARGET_H8300S && TARGET_NORMAL_MODE
2154 && ((REGNO (operands[
0]) ==
0
2155 && REGNO (operands[
1]) ==
1
2156 && REGNO (operands[
2]) ==
2)
2157 || (REGNO (operands[
0]) ==
4
2158 && REGNO (operands[
1]) ==
5
2159 && REGNO (operands[
2]) ==
6))"
2160 "ldm.l
\\t@er7+,%S0-%S2"
2161 [(set_attr "cc" "none")
2162 (set_attr "length" "
4")])
2164 (define_expand "ldm_h8300s_3"
2165 [(use (match_operand:SI
0 "register_operand" ""))
2166 (use (match_operand:SI
1 "register_operand" ""))
2167 (use (match_operand:SI
2 "register_operand" ""))]
2169 && ((REGNO (operands[
0]) ==
0
2170 && REGNO (operands[
1]) ==
1
2171 && REGNO (operands[
2]) ==
2)
2172 || (REGNO (operands[
0]) ==
4
2173 && REGNO (operands[
1]) ==
5
2174 && REGNO (operands[
2]) ==
6))"
2177 if (!TARGET_NORMAL_MODE)
2178 emit_insn (gen_ldm_h8300s_3_advanced (operands[
0], operands[
1],
2181 emit_insn (gen_ldm_h8300s_3_normal (operands[
0], operands[
1],
2186 (define_insn "ldm_h8300s_4_advanced"
2188 [(set (reg:SI SP_REG)
2189 (plus:SI (reg:SI SP_REG) (const_int
16)))
2190 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int
12)))
2191 (match_operand:SI
0 "register_operand" ""))
2192 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int
8)))
2193 (match_operand:SI
1 "register_operand" ""))
2194 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int
4)))
2195 (match_operand:SI
2 "register_operand" ""))
2196 (set (mem:SI (reg:SI SP_REG))
2197 (match_operand:SI
3 "register_operand" ""))])]
2198 "TARGET_H8300S && !TARGET_NORMAL_MODE
2199 && REGNO (operands[
0]) ==
0
2200 && REGNO (operands[
1]) ==
1
2201 && REGNO (operands[
2]) ==
2
2202 && REGNO (operands[
3]) ==
3"
2203 "ldm.l
\\t@er7+,%S0-%S3"
2204 [(set_attr "cc" "none")
2205 (set_attr "length" "
4")])
2207 (define_insn "ldm_h8300s_4_normal"
2209 [(set (reg:HI SP_REG)
2210 (plus:HI (reg:HI SP_REG) (const_int
16)))
2211 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int
12)))
2212 (match_operand:SI
0 "register_operand" ""))
2213 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int
8)))
2214 (match_operand:SI
1 "register_operand" ""))
2215 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int
4)))
2216 (match_operand:SI
2 "register_operand" ""))
2217 (set (mem:SI (reg:HI SP_REG))
2218 (match_operand:SI
3 "register_operand" ""))])]
2219 "TARGET_H8300S && !TARGET_NORMAL_MODE
2220 && REGNO (operands[
0]) ==
0
2221 && REGNO (operands[
1]) ==
1
2222 && REGNO (operands[
2]) ==
2
2223 && REGNO (operands[
3]) ==
3"
2224 "ldm.l
\\t@er7+,%S0-%S3"
2225 [(set_attr "cc" "none")
2226 (set_attr "length" "
4")])
2228 (define_expand "ldm_h8300s_4"
2229 [(use (match_operand:SI
0 "register_operand" ""))
2230 (use (match_operand:SI
1 "register_operand" ""))
2231 (use (match_operand:SI
2 "register_operand" ""))
2232 (use (match_operand:SI
3 "register_operand" ""))]
2233 "TARGET_H8300S && !TARGET_NORMAL_MODE
2234 && REGNO (operands[
0]) ==
0
2235 && REGNO (operands[
1]) ==
1
2236 && REGNO (operands[
2]) ==
2
2237 && REGNO (operands[
3]) ==
3"
2240 if (!TARGET_NORMAL_MODE)
2241 emit_insn (gen_ldm_h8300s_4_advanced (operands[
0], operands[
1],
2242 operands[
2], operands[
3]));
2244 emit_insn (gen_ldm_h8300s_4_normal (operands[
0], operands[
1],
2245 operands[
2], operands[
3]));
2249 (define_expand "return"
2251 "h8300_can_use_return_insn_p ()"
2254 (define_insn "*return_1"
2259 if (h8300_current_function_interrupt_function_p ())
2264 [(set_attr "cc" "none")
2265 (set_attr "length" "
2")])
2267 (define_expand "prologue"
2270 "h8300_expand_prologue (); DONE;")
2272 (define_expand "epilogue"
2275 "h8300_expand_epilogue ();")
2277 (define_insn "monitor_prologue"
2278 [(unspec_volatile [(const_int
0)] UNSPEC_MONITOR)]
2283 return
\"subs
\\t#
2,r7\;mov.w
\\tr0,@-r7\;stc
\\tccr,r0l\;mov.b
\tr
0l,@(
2,r7)\;mov.w
\\t@r7+,r0\;orc
\t#
128,ccr
\";
2284 else if (TARGET_H8300H)
2285 return
\"mov.l
\\ter0,@-er7\;stc
\\tccr,r0l\;mov.b
\\tr0l,@(
4,er7)\;mov.l
\\t@er7+,er0\;orc
\\t#
128,ccr
\";
2286 else if (TARGET_H8300S)
2287 return
\"stc
\texr,@-er7\;mov.l
\\ter0,@-er7\;stc
\tccr,r0l\;mov.b
\tr
0l,@(
6,er7)\;mov.l
\\t@er7+,er0\;orc
\t#
128,ccr
\";
2290 [(set_attr "length" "
20")
2291 (set_attr "cc" "clobber")])
2293 ;; ----------------------------------------------------------------------
2294 ;; EXTEND INSTRUCTIONS
2295 ;; ----------------------------------------------------------------------
2297 (define_expand "zero_extendqihi2"
2298 [(set (match_operand:HI
0 "register_operand" "")
2299 (zero_extend:HI (match_operand:QI
1 "general_operand_src" "")))]
2303 (define_insn "*zero_extendqihi2_h8300"
2304 [(set (match_operand:HI
0 "register_operand" "=r,r")
2305 (zero_extend:HI (match_operand:QI
1 "general_operand_src" "
0,g>")))]
2310 [(set_attr "length" "
2,
10")
2311 (set_attr "cc" "clobber,clobber")])
2313 (define_insn "*zero_extendqihi2_h8300hs"
2314 [(set (match_operand:HI
0 "register_operand" "=r,r")
2315 (zero_extend:HI (match_operand:QI
1 "general_operand_src" "
0,g>")))]
2316 "TARGET_H8300H || TARGET_H8300S"
2320 [(set_attr "length" "
2,
10")
2321 (set_attr "cc" "set_znv,set_znv")])
2323 ;; Split the zero extension of a general operand (actually a memory
2324 ;; operand) into a load of the operand and the actual zero extension
2325 ;; so that
1) the length will be accurate, and
2) the zero extensions
2326 ;; appearing at the end of basic blocks may be merged.
2329 [(set (match_operand:HI
0 "register_operand" "")
2330 (zero_extend:HI (match_operand:QI
1 "general_operand_src" "")))]
2335 (zero_extend:HI (match_dup
2)))]
2336 "operands[
2] = gen_rtx_REG (QImode, REGNO (operands[
0]));")
2338 (define_expand "zero_extendqisi2"
2339 [(set (match_operand:SI
0 "register_operand" "")
2340 (zero_extend:SI (match_operand:QI
1 "general_operand_src" "")))]
2344 (define_insn "*zero_extendqisi2_h8300"
2345 [(set (match_operand:SI
0 "register_operand" "=r,r")
2346 (zero_extend:SI (match_operand:QI
1 "general_operand_src" "
0,g>")))]
2349 mov.b #
0,%x0\;sub.w %e0,%e0
2350 mov.b %R1,%w0\;mov.b #
0,%x0\;sub.w %e0,%e0"
2351 [(set_attr "length" "
4,
8")
2352 (set_attr "cc" "clobber,clobber")])
2354 (define_insn "*zero_extendqisi2_h8300hs"
2355 [(set (match_operand:SI
0 "register_operand" "=r,r")
2356 (zero_extend:SI (match_operand:QI
1 "general_operand_src" "
0,g>")))]
2357 "TARGET_H8300H || TARGET_H8300S"
2361 [(set (match_operand:SI
0 "register_operand" "")
2362 (zero_extend:SI (match_operand:QI
1 "general_operand_src" "")))]
2363 "(TARGET_H8300H || TARGET_H8300S)
2364 && reg_overlap_mentioned_p (operands[
0], operands[
1])
2365 && reload_completed"
2369 (zero_extend:HI (match_dup
2)))
2371 (zero_extend:SI (match_dup
3)))]
2372 "operands[
2] = gen_lowpart (QImode, operands[
0]);
2373 operands[
3] = gen_lowpart (HImode, operands[
0]);")
2376 [(set (match_operand:SI
0 "register_operand" "")
2377 (zero_extend:SI (match_operand:QI
1 "general_operand_src" "")))]
2378 "(TARGET_H8300H || TARGET_H8300S)
2379 && !reg_overlap_mentioned_p (operands[
0], operands[
1])
2380 && reload_completed"
2383 (set (strict_low_part (match_dup
2))
2385 "operands[
2] = gen_rtx_REG (QImode, REGNO (operands[
0]));")
2387 (define_expand "zero_extendhisi2"
2388 [(set (match_operand:SI
0 "register_operand" "")
2389 (zero_extend:SI (match_operand:HI
1 "register_operand" "")))]
2393 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2394 (define_insn "*zero_extendhisi2_h8300"
2395 [(set (match_operand:SI
0 "register_operand" "=r,r,r")
2396 (zero_extend:SI (match_operand:HI
1 "general_operand_src" "
0,i,g>")))]
2400 mov.w %f1,%f0\;sub.w %e0,%e0
2401 mov.w %e1,%f0\;sub.w %e0,%e0"
2402 [(set_attr "length" "
2,
4,
6")
2403 (set_attr "cc" "clobber,clobber,clobber")])
2405 (define_insn "*zero_extendhisi2_h8300hs"
2406 [(set (match_operand:SI
0 "register_operand" "=r")
2407 (zero_extend:SI (match_operand:HI
1 "register_operand" "
0")))]
2408 "TARGET_H8300H || TARGET_H8300S"
2410 [(set_attr "length" "
2")
2411 (set_attr "cc" "set_znv")])
2413 (define_expand "extendqihi2"
2414 [(set (match_operand:HI
0 "register_operand" "")
2415 (sign_extend:HI (match_operand:QI
1 "register_operand" "")))]
2419 (define_insn "*extendqihi2_h8300"
2420 [(set (match_operand:HI
0 "register_operand" "=r,r")
2421 (sign_extend:HI (match_operand:QI
1 "general_operand_src" "
0,g>")))]
2424 bld #
7,%s0\;subx %t0,%t0
2425 mov.b %R1,%s0\;bld #
7,%s0\;subx %t0,%t0"
2426 [(set_attr "length" "
4,
8")
2427 (set_attr "cc" "clobber,clobber")])
2429 (define_insn "*extendqihi2_h8300hs"
2430 [(set (match_operand:HI
0 "register_operand" "=r")
2431 (sign_extend:HI (match_operand:QI
1 "register_operand" "
0")))]
2432 "TARGET_H8300H || TARGET_H8300S"
2434 [(set_attr "length" "
2")
2435 (set_attr "cc" "set_znv")])
2437 (define_expand "extendqisi2"
2438 [(set (match_operand:SI
0 "register_operand" "")
2439 (sign_extend:SI (match_operand:QI
1 "register_operand" "")))]
2443 (define_insn "*extendqisi2_h8300"
2444 [(set (match_operand:SI
0 "register_operand" "")
2445 (sign_extend:SI (match_operand:QI
1 "general_operand_src" "
0,g>")))]
2448 bld #
7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2449 mov.b %R1,%w0\;bld #
7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2450 [(set_attr "length" "
8,
12")
2451 (set_attr "cc" "clobber,clobber")])
2453 ;; The following pattern is needed because without the pattern, the
2454 ;; combiner would split (sign_extend:SI (reg:QI)) into into two
24-bit
2455 ;; shifts, one ashift and one ashiftrt.
2457 (define_insn_and_split "*extendqisi2_h8300hs"
2458 [(set (match_operand:SI
0 "register_operand" "=r")
2459 (sign_extend:SI (match_operand:QI
1 "register_operand" "
0")))]
2460 "(TARGET_H8300H || TARGET_H8300S)"
2462 "&& reload_completed"
2464 (sign_extend:HI (match_dup
1)))
2466 (sign_extend:SI (match_dup
2)))]
2467 "operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
0]));")
2469 (define_expand "extendhisi2"
2470 [(set (match_operand:SI
0 "register_operand" "")
2471 (sign_extend:SI (match_operand:HI
1 "register_operand" "")))]
2475 (define_insn "*extendhisi2_h8300"
2476 [(set (match_operand:SI
0 "register_operand" "=r,r")
2477 (sign_extend:SI (match_operand:HI
1 "general_operand_src" "
0,g>")))]
2480 bld #
7,%x0\;subx %y0,%y0\;subx %z0,%z0
2481 mov.w %T1,%f0\;bld #
7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2482 [(set_attr "length" "
6,
10")
2483 (set_attr "cc" "clobber,clobber")])
2485 (define_insn "*extendhisi2_h8300hs"
2486 [(set (match_operand:SI
0 "register_operand" "=r")
2487 (sign_extend:SI (match_operand:HI
1 "register_operand" "
0")))]
2488 "TARGET_H8300H || TARGET_H8300S"
2490 [(set_attr "length" "
2")
2491 (set_attr "cc" "set_znv")])
2493 ;; ----------------------------------------------------------------------
2495 ;; ----------------------------------------------------------------------
2497 ;; We make some attempt to provide real efficient shifting. One example is
2498 ;; doing an
8 bit shift of a
16 bit value by moving a byte reg into the other
2499 ;; reg and moving
0 into the former reg.
2501 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2502 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2503 ;; give the optimizer more cracks at the code. However, we wish to do things
2504 ;; like optimizing shifting the sign bit to bit
0 by rotating the other way.
2505 ;; There is rtl to handle this (rotate + and), but the H8/
300 doesn't handle
2506 ;;
16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2507 ;; to detect cases it can optimize.
2509 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2510 ;; easier "do it at insn emit time" route.
2514 (define_expand "ashlqi3"
2515 [(set (match_operand:QI
0 "register_operand" "")
2516 (ashift:QI (match_operand:QI
1 "register_operand" "")
2517 (match_operand:QI
2 "nonmemory_operand" "")))]
2519 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2521 (define_expand "ashrqi3"
2522 [(set (match_operand:QI
0 "register_operand" "")
2523 (ashiftrt:QI (match_operand:QI
1 "register_operand" "")
2524 (match_operand:QI
2 "nonmemory_operand" "")))]
2526 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2528 (define_expand "lshrqi3"
2529 [(set (match_operand:QI
0 "register_operand" "")
2530 (lshiftrt:QI (match_operand:QI
1 "register_operand" "")
2531 (match_operand:QI
2 "nonmemory_operand" "")))]
2533 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2535 (define_insn "*shiftqi"
2536 [(set (match_operand:QI
0 "register_operand" "=r,r")
2537 (match_operator:QI
3 "nshift_operator"
2538 [ (match_operand:QI
1 "register_operand" "
0,
0")
2539 (match_operand:QI
2 "nonmemory_operand" "R,rn")]))
2540 (clobber (match_scratch:QI
4 "=X,&r"))]
2542 "* return output_a_shift (operands);"
2543 [(set (attr "length")
2544 (symbol_ref "compute_a_shift_length (insn, operands)"))
2546 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2550 (define_expand "ashlhi3"
2551 [(set (match_operand:HI
0 "register_operand" "")
2552 (ashift:HI (match_operand:HI
1 "nonmemory_operand" "")
2553 (match_operand:QI
2 "nonmemory_operand" "")))]
2555 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2557 (define_expand "lshrhi3"
2558 [(set (match_operand:HI
0 "register_operand" "")
2559 (lshiftrt:HI (match_operand:HI
1 "general_operand" "")
2560 (match_operand:QI
2 "nonmemory_operand" "")))]
2562 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2564 (define_expand "ashrhi3"
2565 [(set (match_operand:HI
0 "register_operand" "")
2566 (ashiftrt:HI (match_operand:HI
1 "register_operand" "")
2567 (match_operand:QI
2 "nonmemory_operand" "")))]
2569 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2571 (define_insn "*shifthi"
2572 [(set (match_operand:HI
0 "register_operand" "=r,r")
2573 (match_operator:HI
3 "nshift_operator"
2574 [ (match_operand:HI
1 "register_operand" "
0,
0")
2575 (match_operand:QI
2 "nonmemory_operand" "S,rn")]))
2576 (clobber (match_scratch:QI
4 "=X,&r"))]
2578 "* return output_a_shift (operands);"
2579 [(set (attr "length")
2580 (symbol_ref "compute_a_shift_length (insn, operands)"))
2582 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2586 (define_expand "ashlsi3"
2587 [(set (match_operand:SI
0 "register_operand" "")
2588 (ashift:SI (match_operand:SI
1 "general_operand" "")
2589 (match_operand:QI
2 "nonmemory_operand" "")))]
2591 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2593 (define_expand "lshrsi3"
2594 [(set (match_operand:SI
0 "register_operand" "")
2595 (lshiftrt:SI (match_operand:SI
1 "general_operand" "")
2596 (match_operand:QI
2 "nonmemory_operand" "")))]
2598 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2600 (define_expand "ashrsi3"
2601 [(set (match_operand:SI
0 "register_operand" "")
2602 (ashiftrt:SI (match_operand:SI
1 "general_operand" "")
2603 (match_operand:QI
2 "nonmemory_operand" "")))]
2605 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2607 (define_insn "*shiftsi"
2608 [(set (match_operand:SI
0 "register_operand" "=r,r")
2609 (match_operator:SI
3 "nshift_operator"
2610 [ (match_operand:SI
1 "register_operand" "
0,
0")
2611 (match_operand:QI
2 "nonmemory_operand" "T,rn")]))
2612 (clobber (match_scratch:QI
4 "=X,&r"))]
2614 "* return output_a_shift (operands);"
2615 [(set (attr "length")
2616 (symbol_ref "compute_a_shift_length (insn, operands)"))
2618 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2620 ;; Split a variable shift into a loop. If the register containing
2621 ;; the shift count dies, then we just use that register.
2625 [(set (match_operand
0 "register_operand" "")
2626 (match_operator
2 "nshift_operator"
2628 (match_operand:QI
1 "register_operand" "")]))
2629 (clobber (match_operand:QI
3 "register_operand" ""))])]
2631 && find_regno_note (insn, REG_DEAD, REGNO (operands[
1]))"
2635 (if_then_else (le (cc0) (const_int
0))
2636 (label_ref (match_dup
5))
2641 (match_op_dup
2 [(match_dup
0) (const_int
1)]))
2642 (clobber (scratch:QI))])
2644 (plus:QI (match_dup
1) (const_int -
1)))
2648 (if_then_else (ne (cc0) (const_int
0))
2649 (label_ref (match_dup
4))
2652 "operands[
4] = gen_label_rtx ();
2653 operands[
5] = gen_label_rtx ();")
2657 [(set (match_operand
0 "register_operand" "")
2658 (match_operator
2 "nshift_operator"
2660 (match_operand:QI
1 "register_operand" "")]))
2661 (clobber (match_operand:QI
3 "register_operand" ""))])]
2663 && !find_regno_note (insn, REG_DEAD, REGNO (operands[
1]))"
2669 (if_then_else (le (cc0) (const_int
0))
2670 (label_ref (match_dup
5))
2675 (match_op_dup
2 [(match_dup
0) (const_int
1)]))
2676 (clobber (scratch:QI))])
2678 (plus:QI (match_dup
3) (const_int -
1)))
2682 (if_then_else (ne (cc0) (const_int
0))
2683 (label_ref (match_dup
4))
2686 "operands[
4] = gen_label_rtx ();
2687 operands[
5] = gen_label_rtx ();")
2689 ;; ----------------------------------------------------------------------
2691 ;; ----------------------------------------------------------------------
2693 (define_expand "rotlqi3"
2694 [(set (match_operand:QI
0 "register_operand" "")
2695 (rotate:QI (match_operand:QI
1 "register_operand" "")
2696 (match_operand:QI
2 "nonmemory_operand" "")))]
2698 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2700 (define_insn "*rotlqi3_1"
2701 [(set (match_operand:QI
0 "register_operand" "=r")
2702 (rotate:QI (match_operand:QI
1 "register_operand" "
0")
2703 (match_operand:QI
2 "immediate_operand" "")))]
2705 "* return output_a_rotate (ROTATE, operands);"
2706 [(set (attr "length")
2707 (symbol_ref "compute_a_rotate_length (operands)"))
2708 (set_attr "cc" "clobber")])
2710 (define_expand "rotlhi3"
2711 [(set (match_operand:HI
0 "register_operand" "")
2712 (rotate:HI (match_operand:HI
1 "register_operand" "")
2713 (match_operand:QI
2 "nonmemory_operand" "")))]
2715 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2717 (define_insn "*rotlhi3_1"
2718 [(set (match_operand:HI
0 "register_operand" "=r")
2719 (rotate:HI (match_operand:HI
1 "register_operand" "
0")
2720 (match_operand:QI
2 "immediate_operand" "")))]
2722 "* return output_a_rotate (ROTATE, operands);"
2723 [(set (attr "length")
2724 (symbol_ref "compute_a_rotate_length (operands)"))
2725 (set_attr "cc" "clobber")])
2727 (define_expand "rotlsi3"
2728 [(set (match_operand:SI
0 "register_operand" "")
2729 (rotate:SI (match_operand:SI
1 "register_operand" "")
2730 (match_operand:QI
2 "nonmemory_operand" "")))]
2731 "TARGET_H8300H || TARGET_H8300S"
2732 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2734 (define_insn "*rotlsi3_1"
2735 [(set (match_operand:SI
0 "register_operand" "=r")
2736 (rotate:SI (match_operand:SI
1 "register_operand" "
0")
2737 (match_operand:QI
2 "immediate_operand" "")))]
2738 "TARGET_H8300H || TARGET_H8300S"
2739 "* return output_a_rotate (ROTATE, operands);"
2740 [(set (attr "length")
2741 (symbol_ref "compute_a_rotate_length (operands)"))
2742 (set_attr "cc" "clobber")])
2744 ;; -----------------------------------------------------------------
2746 ;; -----------------------------------------------------------------
2747 ;; The H8/
300 has given
1/
8th of its opcode space to bitfield
2748 ;; instructions so let's use them as well as we can.
2750 ;; You'll never believe all these patterns perform one basic action --
2751 ;; load a bit from the source, optionally invert the bit, then store it
2752 ;; in the destination (which is known to be zero).
2754 ;; Combine obviously need some work to better identify this situation and
2755 ;; canonicalize the form better.
2758 ;; Normal loads with a
16bit destination.
2762 [(set (match_operand:HI
0 "register_operand" "=&r")
2763 (zero_extract:HI (match_operand:HI
1 "register_operand" "r")
2765 (match_operand:HI
2 "immediate_operand" "n")))]
2767 "sub.w %
0,%
0\;bld %Z2,%Y1\;bst #
0,%X0"
2768 [(set_attr "cc" "clobber")
2769 (set_attr "length" "
6")])
2772 ;; Inverted loads with a
16bit destination.
2776 [(set (match_operand:HI
0 "register_operand" "=&r")
2777 (zero_extract:HI (xor:HI (match_operand:HI
1 "register_operand" "r")
2778 (match_operand:HI
3 "const_int_operand" "n"))
2780 (match_operand:HI
2 "const_int_operand" "n")))]
2782 && (
1 << INTVAL (operands[
2])) == INTVAL (operands[
3])"
2783 "sub.w %
0,%
0\;bild %Z2,%Y1\;bst #
0,%X0"
2784 [(set_attr "cc" "clobber")
2785 (set_attr "length" "
8")])
2788 ;; Normal loads with a
32bit destination.
2791 (define_insn "*extzv_1_r_h8300"
2792 [(set (match_operand:SI
0 "register_operand" "=&r")
2793 (zero_extract:SI (match_operand:HI
1 "register_operand" "r")
2795 (match_operand
2 "const_int_operand" "n")))]
2797 && INTVAL (operands[
2]) <
16"
2798 "* return output_simode_bld (
0, operands);"
2799 [(set_attr "cc" "clobber")
2800 (set_attr "length" "
8")])
2802 (define_insn "*extzv_1_r_h8300hs"
2803 [(set (match_operand:SI
0 "register_operand" "=r,r")
2804 (zero_extract:SI (match_operand:SI
1 "register_operand" "?
0,r")
2806 (match_operand
2 "const_int_operand" "n,n")))]
2807 "(TARGET_H8300H || TARGET_H8300S)
2808 && INTVAL (operands[
2]) <
16"
2809 "* return output_simode_bld (
0, operands);"
2810 [(set_attr "cc" "set_znv,set_znv")
2811 (set_attr "length" "
8,
6")])
2814 ;; Inverted loads with a
32bit destination.
2817 (define_insn "*extzv_1_r_inv_h8300"
2818 [(set (match_operand:SI
0 "register_operand" "=&r")
2819 (zero_extract:SI (xor:HI (match_operand:HI
1 "register_operand" "r")
2820 (match_operand:HI
3 "const_int_operand" "n"))
2822 (match_operand
2 "const_int_operand" "n")))]
2824 && INTVAL (operands[
2]) <
16
2825 && (
1 << INTVAL (operands[
2])) == INTVAL (operands[
3])"
2826 "* return output_simode_bld (
1, operands);"
2827 [(set_attr "cc" "clobber")
2828 (set_attr "length" "
8")])
2830 (define_insn "*extzv_1_r_inv_h8300hs"
2831 [(set (match_operand:SI
0 "register_operand" "=r,r")
2832 (zero_extract:SI (xor:SI (match_operand:SI
1 "register_operand" "?
0,r")
2833 (match_operand
3 "const_int_operand" "n,n"))
2835 (match_operand
2 "const_int_operand" "n,n")))]
2836 "(TARGET_H8300H || TARGET_H8300S)
2837 && INTVAL (operands[
2]) <
16
2838 && (
1 << INTVAL (operands[
2])) == INTVAL (operands[
3])"
2839 "* return output_simode_bld (
1, operands);"
2840 [(set_attr "cc" "set_znv,set_znv")
2841 (set_attr "length" "
8,
6")])
2843 (define_expand "insv"
2844 [(set (zero_extract:HI (match_operand:HI
0 "general_operand" "")
2845 (match_operand:HI
1 "general_operand" "")
2846 (match_operand:HI
2 "general_operand" ""))
2847 (match_operand:HI
3 "general_operand" ""))]
2851 /* We only have single bit bit-field instructions. */
2852 if (INTVAL (operands[
1]) !=
1)
2855 /* For now, we don't allow memory operands. */
2856 if (GET_CODE (operands[
0]) == MEM
2857 || GET_CODE (operands[
3]) == MEM)
2862 [(set (zero_extract:HI (match_operand:HI
0 "register_operand" "+r")
2864 (match_operand:HI
1 "immediate_operand" "n"))
2865 (match_operand:HI
2 "register_operand" "r"))]
2867 "bld #
0,%R2\;bst %Z1,%Y0 ; i1"
2868 [(set_attr "cc" "clobber")
2869 (set_attr "length" "
4")])
2871 (define_expand "extzv"
2872 [(set (match_operand:HI
0 "register_operand" "")
2873 (zero_extract:HI (match_operand:HI
1 "bit_operand" "")
2874 (match_operand:HI
2 "general_operand" "")
2875 (match_operand:HI
3 "general_operand" "")))]
2879 /* We only have single bit bit-field instructions. */
2880 if (INTVAL (operands[
2]) !=
1)
2883 /* For now, we don't allow memory operands. */
2884 if (GET_CODE (operands[
1]) == MEM)
2888 ;; BAND, BOR, and BXOR patterns
2891 [(set (match_operand:HI
0 "bit_operand" "=Ur")
2892 (match_operator:HI
4 "bit_operator"
2893 [(zero_extract:HI (match_operand:HI
1 "register_operand" "r")
2895 (match_operand:HI
2 "immediate_operand" "n"))
2896 (match_operand:HI
3 "bit_operand" "
0")]))]
2898 "bld %Z2,%Y1\;b%c4 #
0,%R0\;bst #
0,%R0; bl1"
2899 [(set_attr "cc" "clobber")
2900 (set_attr "length" "
6")])
2903 [(set (match_operand:HI
0 "bit_operand" "=Ur")
2904 (match_operator:HI
5 "bit_operator"
2905 [(zero_extract:HI (match_operand:HI
1 "register_operand" "r")
2907 (match_operand:HI
2 "immediate_operand" "n"))
2908 (zero_extract:HI (match_operand:HI
3 "register_operand" "r")
2910 (match_operand:HI
4 "immediate_operand" "n"))]))]
2912 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #
0,%R0; bl3"
2913 [(set_attr "cc" "clobber")
2914 (set_attr "length" "
6")])
2916 ;; -----------------------------------------------------------------
2918 ;; -----------------------------------------------------------------
2922 (define_insn "*insv_si_1_n"
2923 [(set (zero_extract:SI (match_operand:SI
0 "register_operand" "+r")
2925 (match_operand:SI
1 "const_int_operand" "n"))
2926 (match_operand:SI
2 "register_operand" "r"))]
2927 "(TARGET_H8300H || TARGET_H8300S)
2928 && INTVAL (operands[
1]) <
16"
2929 "bld
\\t#
0,%w2\;bst
\\t%Z1,%Y0"
2930 [(set_attr "cc" "clobber")
2931 (set_attr "length" "
4")])
2933 (define_insn "*insv_si_1_n_lshiftrt"
2934 [(set (zero_extract:SI (match_operand:SI
0 "register_operand" "+r")
2936 (match_operand:SI
1 "const_int_operand" "n"))
2937 (lshiftrt:SI (match_operand:SI
2 "register_operand" "r")
2938 (match_operand:SI
3 "const_int_operand" "n")))]
2939 "(TARGET_H8300H || TARGET_H8300S)
2940 && INTVAL (operands[
1]) <
16
2941 && INTVAL (operands[
3]) <
16"
2942 "bld
\\t%Z3,%Y2\;bst
\\t%Z1,%Y0"
2943 [(set_attr "cc" "clobber")
2944 (set_attr "length" "
4")])
2946 (define_insn "*insv_si_1_n_lshiftrt_16"
2947 [(set (zero_extract:SI (match_operand:SI
0 "register_operand" "+r")
2949 (match_operand:SI
1 "const_int_operand" "n"))
2950 (lshiftrt:SI (match_operand:SI
2 "register_operand" "r")
2952 "(TARGET_H8300H || TARGET_H8300S)
2953 && INTVAL (operands[
1]) <
16"
2954 "rotr.w
\\t%e2\;rotl.w
\\t%e2\;bst
\\t%Z1,%Y0"
2955 [(set_attr "cc" "clobber")
2956 (set_attr "length" "
6")])
2958 (define_insn "*insv_si_8_8"
2959 [(set (zero_extract:SI (match_operand:SI
0 "register_operand" "+r")
2962 (match_operand:SI
1 "register_operand" "r"))]
2963 "TARGET_H8300H || TARGET_H8300S"
2965 [(set_attr "cc" "clobber")
2966 (set_attr "length" "
2")])
2968 (define_insn "*insv_si_8_8_lshiftrt_8"
2969 [(set (zero_extract:SI (match_operand:SI
0 "register_operand" "+r")
2972 (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
2974 "TARGET_H8300H || TARGET_H8300S"
2976 [(set_attr "cc" "clobber")
2977 (set_attr "length" "
2")])
2981 (define_insn "*extzv_8_8"
2982 [(set (match_operand:SI
0 "register_operand" "=r,r")
2983 (zero_extract:SI (match_operand:SI
1 "register_operand" "?
0,r")
2986 "TARGET_H8300H || TARGET_H8300S"
2988 mov.b
\\t%x1,%w0\;extu.w
\\t%f0\;extu.l
\\t%S0
2989 sub.l
\\t%S0,%S0\;mov.b
\\t%x1,%w0"
2990 [(set_attr "cc" "set_znv,clobber")
2991 (set_attr "length" "
6,
4")])
2993 (define_insn "*extzv_8_16"
2994 [(set (match_operand:SI
0 "register_operand" "=r")
2995 (zero_extract:SI (match_operand:SI
1 "register_operand" "r")
2998 "TARGET_H8300H || TARGET_H8300S"
2999 "mov.w
\\t%e1,%f0\;extu.w
\\t%f0\;extu.l
\\t%S0"
3000 [(set_attr "cc" "set_znv")
3001 (set_attr "length" "
6")])
3003 (define_insn "*extzv_16_8"
3004 [(set (match_operand:SI
0 "register_operand" "=r")
3005 (zero_extract:SI (match_operand:SI
1 "register_operand" "r")
3008 (clobber (match_scratch:SI
2 "=&r"))]
3010 "mov.w
\\t%e1,%f2\;mov.b
\\t%x1,%w0\;mov.b
\\t%w2,%x0\;extu.l
\\t%S0"
3011 [(set_attr "length" "
8")
3012 (set_attr "cc" "set_znv")])
3014 ;; Extract the exponent of a float.
3016 (define_insn_and_split "*extzv_8_23"
3017 [(set (match_operand:SI
0 "register_operand" "=r")
3018 (zero_extract:SI (match_operand:SI
1 "register_operand" "
0")
3021 "(TARGET_H8300H || TARGET_H8300S)"
3023 "&& reload_completed"
3024 [(parallel [(set (match_dup
0)
3025 (ashift:SI (match_dup
0)
3027 (clobber (scratch:QI))])
3028 (parallel [(set (match_dup
0)
3029 (lshiftrt:SI (match_dup
0)
3031 (clobber (scratch:QI))])]
3036 ;; ((SImode) HImode) <<
15
3038 (define_insn_and_split "*twoshifts_l16_r1"
3039 [(set (match_operand:SI
0 "register_operand" "=r")
3040 (and:SI (ashift:SI (match_operand:SI
1 "register_operand" "
0")
3042 (const_int
2147450880)))]
3043 "(TARGET_H8300H || TARGET_H8300S)"
3045 "&& reload_completed"
3046 [(parallel [(set (match_dup
0)
3047 (ashift:SI (match_dup
0)
3049 (clobber (scratch:QI))])
3050 (parallel [(set (match_dup
0)
3051 (lshiftrt:SI (match_dup
0)
3053 (clobber (scratch:QI))])]
3056 ;; Transform (SImode << B) &
0xffff into (SImode) (HImode << B).
3058 (define_insn_and_split "*andsi3_ashift_n_lower"
3059 [(set (match_operand:SI
0 "register_operand" "=r,r")
3060 (and:SI (ashift:SI (match_operand:SI
1 "register_operand" "
0,
0")
3061 (match_operand:QI
2 "const_int_operand" "S,n"))
3062 (match_operand:SI
3 "const_int_operand" "n,n")))
3063 (clobber (match_scratch:QI
4 "=X,&r"))]
3064 "(TARGET_H8300H || TARGET_H8300S)
3065 && INTVAL (operands[
2]) <=
15
3066 && INTVAL (operands[
3]) == ((-
1 << INTVAL (operands[
2])) &
0xffff)"
3068 "&& reload_completed"
3069 [(parallel [(set (match_dup
5)
3070 (ashift:HI (match_dup
5)
3072 (clobber (match_dup
4))])
3074 (zero_extend:SI (match_dup
5)))]
3075 "operands[
5] = gen_rtx_REG (HImode, REGNO (operands[
0]));")
3077 ;; Accept (A >>
30) &
2 and the like.
3079 (define_insn "*andsi3_lshiftrt_n_sb"
3080 [(set (match_operand:SI
0 "register_operand" "=r")
3081 (and:SI (lshiftrt:SI (match_operand:SI
1 "register_operand" "
0")
3082 (match_operand:SI
2 "const_int_operand" "n"))
3083 (match_operand:SI
3 "single_one_operand" "n")))]
3084 "(TARGET_H8300H || TARGET_H8300S)
3085 && exact_log2 (INTVAL (operands[
3])) <
16
3086 && INTVAL (operands[
2]) + exact_log2 (INTVAL (operands[
3])) ==
31"
3089 operands[
3] = GEN_INT (exact_log2 (INTVAL (operands[
3])));
3090 return
\"shll.l
\\t%S0\;xor.l
\\t%S0,%S0\;bst
\\t%Z3,%Y0
\";
3092 [(set_attr "length" "
8")
3093 (set_attr "cc" "clobber")])
3095 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3096 [(set (match_operand:SI
0 "register_operand" "=r")
3097 (and:SI (lshiftrt:SI (match_operand:SI
1 "register_operand" "
0")
3099 (const_int
4194304)))]
3100 "(TARGET_H8300H || TARGET_H8300S)"
3102 "&& reload_completed"
3104 (and:SI (lshiftrt:SI (match_dup
0)
3107 (parallel [(set (match_dup
0)
3108 (ashift:SI (match_dup
0)
3110 (clobber (scratch:QI))])]
3115 (define_insn "*addsi3_upper"
3116 [(set (match_operand:SI
0 "register_operand" "=r")
3117 (plus:SI (mult:SI (match_operand:SI
1 "register_operand" "r")
3119 (match_operand:SI
2 "register_operand" "
0")))]
3120 "TARGET_H8300H || TARGET_H8300S"
3122 [(set_attr "length" "
2")
3123 (set_attr "cc" "clobber")])
3125 (define_insn "*addsi3_lshiftrt_16_zexthi"
3126 [(set (match_operand:SI
0 "register_operand" "=r")
3127 (plus:SI (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
3129 (zero_extend:SI (match_operand:HI
2 "register_operand" "
0"))))]
3130 "TARGET_H8300H || TARGET_H8300S"
3131 "add.w
\\t%e1,%f0\;xor.w
\\t%e0,%e0\;rotxl.w
\\t%e0"
3132 [(set_attr "cc" "clobber")
3133 (set_attr "length" "
6")])
3135 (define_insn_and_split "*addsi3_and_r_1"
3136 [(set (match_operand:SI
0 "register_operand" "=r")
3137 (plus:SI (and:SI (match_operand:SI
1 "register_operand" "r")
3139 (match_operand:SI
2 "register_operand" "
0")))]
3140 "(TARGET_H8300H || TARGET_H8300S)"
3142 "&& reload_completed"
3144 (zero_extract:SI (match_dup
1)
3148 (if_then_else (eq (cc0)
3150 (label_ref (match_dup
3))
3153 (plus:SI (match_dup
2)
3156 "operands[
3] = gen_label_rtx ();")
3158 (define_insn_and_split "*addsi3_and_not_r_1"
3159 [(set (match_operand:SI
0 "register_operand" "=r")
3160 (plus:SI (and:SI (not:SI (match_operand:SI
1 "register_operand" "r"))
3162 (match_operand:SI
2 "register_operand" "
0")))]
3163 "(TARGET_H8300H || TARGET_H8300S)"
3165 "&& reload_completed"
3167 (zero_extract:SI (match_dup
1)
3171 (if_then_else (ne (cc0)
3173 (label_ref (match_dup
3))
3176 (plus:SI (match_dup
2)
3179 "operands[
3] = gen_label_rtx ();")
3183 (define_insn "*ixorhi3_zext"
3184 [(set (match_operand:HI
0 "register_operand" "=r")
3185 (match_operator:HI
1 "iorxor_operator"
3186 [(zero_extend:HI (match_operand:QI
2 "register_operand" "r"))
3187 (match_operand:HI
3 "register_operand" "
0")]))]
3190 [(set_attr "cc" "clobber")
3191 (set_attr "length" "
2")])
3195 (define_insn "*ixorsi3_zext_qi"
3196 [(set (match_operand:SI
0 "register_operand" "=r")
3197 (match_operator:SI
1 "iorxor_operator"
3198 [(zero_extend:SI (match_operand:QI
2 "register_operand" "r"))
3199 (match_operand:SI
3 "register_operand" "
0")]))]
3202 [(set_attr "cc" "clobber")
3203 (set_attr "length" "
2")])
3205 (define_insn "*ixorsi3_zext_hi"
3206 [(set (match_operand:SI
0 "register_operand" "=r")
3207 (match_operator:SI
1 "iorxor_operator"
3208 [(zero_extend:SI (match_operand:HI
2 "register_operand" "r"))
3209 (match_operand:SI
3 "register_operand" "
0")]))]
3210 "TARGET_H8300H || TARGET_H8300S"
3212 [(set_attr "cc" "clobber")
3213 (set_attr "length" "
2")])
3215 (define_insn "*ixorsi3_ashift_16"
3216 [(set (match_operand:SI
0 "register_operand" "=r")
3217 (match_operator:SI
1 "iorxor_operator"
3218 [(ashift:SI (match_operand:SI
2 "register_operand" "r")
3220 (match_operand:SI
3 "register_operand" "
0")]))]
3221 "TARGET_H8300H || TARGET_H8300S"
3223 [(set_attr "cc" "clobber")
3224 (set_attr "length" "
2")])
3226 (define_insn "*ixorsi3_lshiftrt_16"
3227 [(set (match_operand:SI
0 "register_operand" "=r")
3228 (match_operator:SI
1 "iorxor_operator"
3229 [(lshiftrt:SI (match_operand:SI
2 "register_operand" "r")
3231 (match_operand:SI
3 "register_operand" "
0")]))]
3232 "TARGET_H8300H || TARGET_H8300S"
3234 [(set_attr "cc" "clobber")
3235 (set_attr "length" "
2")])
3239 (define_insn "*iorhi3_ashift_8"
3240 [(set (match_operand:HI
0 "register_operand" "=r")
3241 (ior:HI (ashift:HI (match_operand:HI
1 "register_operand" "r")
3243 (match_operand:HI
2 "register_operand" "
0")))]
3246 [(set_attr "cc" "clobber")
3247 (set_attr "length" "
2")])
3249 (define_insn "*iorhi3_lshiftrt_8"
3250 [(set (match_operand:HI
0 "register_operand" "=r")
3251 (ior:HI (lshiftrt:HI (match_operand:HI
1 "register_operand" "r")
3253 (match_operand:HI
2 "register_operand" "
0")))]
3256 [(set_attr "cc" "clobber")
3257 (set_attr "length" "
2")])
3259 (define_insn "*iorhi3_two_qi"
3260 [(set (match_operand:HI
0 "register_operand" "=r")
3261 (ior:HI (zero_extend:HI (match_operand:QI
1 "register_operand" "
0"))
3262 (ashift:HI (match_operand:HI
2 "register_operand" "r")
3266 [(set_attr "cc" "clobber")
3267 (set_attr "length" "
2")])
3269 (define_insn "*iorhi3_two_qi_mem"
3270 [(set (match_operand:HI
0 "register_operand" "=&r")
3271 (ior:HI (zero_extend:HI (match_operand:QI
1 "memory_operand" "m"))
3272 (ashift:HI (subreg:HI (match_operand:QI
2 "memory_operand" "m")
0)
3275 "mov.b
\\t%X2,%t0\;mov.b
\\t%X1,%s0"
3276 [(set_attr "cc" "clobber")
3277 (set_attr "length" "
16")])
3280 [(set (match_operand:HI
0 "register_operand" "")
3281 (ior:HI (zero_extend:HI (match_operand:QI
1 "memory_operand" ""))
3282 (ashift:HI (subreg:HI (match_operand:QI
2 "memory_operand" "")
0)
3284 "(TARGET_H8300H || TARGET_H8300S)
3286 && byte_accesses_mergeable_p (XEXP (operands[
2],
0), XEXP (operands[
1],
0))"
3289 "operands[
3] = gen_rtx_MEM (HImode, XEXP (operands[
2],
0));")
3293 (define_insn "*iorsi3_two_hi"
3294 [(set (match_operand:SI
0 "register_operand" "=r")
3295 (ior:SI (zero_extend:SI (match_operand:HI
1 "register_operand" "
0"))
3296 (ashift:SI (match_operand:SI
2 "register_operand" "r")
3298 "TARGET_H8300H || TARGET_H8300S"
3300 [(set_attr "cc" "clobber")
3301 (set_attr "length" "
2")])
3303 (define_insn_and_split "*iorsi3_two_qi_zext"
3304 [(set (match_operand:SI
0 "register_operand" "=&r")
3305 (ior:SI (zero_extend:SI (match_operand:QI
1 "memory_operand" "m"))
3307 (and:SI (ashift:SI (subreg:SI (match_operand:QI
2 "memory_operand" "m")
0)
3309 (const_int
65280))))]
3310 "(TARGET_H8300H || TARGET_H8300S)"
3312 "&& reload_completed"
3314 (ior:HI (zero_extend:HI (match_dup
1))
3315 (ashift:HI (subreg:HI (match_dup
2)
0)
3318 (zero_extend:SI (match_dup
3)))]
3319 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
0]));")
3321 (define_insn "*iorsi3_e2f"
3322 [(set (match_operand:SI
0 "register_operand" "=r")
3323 (ior:SI (and:SI (match_operand:SI
1 "register_operand" "
0")
3325 (lshiftrt:SI (match_operand:SI
2 "register_operand" "r")
3327 "TARGET_H8300H || TARGET_H8300S"
3329 [(set_attr "length" "
2")
3330 (set_attr "cc" "clobber")])
3332 (define_insn_and_split "*iorsi3_two_qi_sext"
3333 [(set (match_operand:SI
0 "register_operand" "=r")
3334 (ior:SI (zero_extend:SI (match_operand:QI
1 "register_operand" "
0"))
3335 (ashift:SI (sign_extend:SI (match_operand:QI
2 "register_operand" "r"))
3337 "(TARGET_H8300H || TARGET_H8300S)"
3339 "&& reload_completed"
3341 (ior:HI (zero_extend:HI (match_dup
1))
3342 (ashift:HI (match_dup
4)
3345 (sign_extend:SI (match_dup
3)))]
3346 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
0]));
3347 operands[
4] = gen_rtx_REG (HImode, REGNO (operands[
2]));")
3349 (define_insn "*iorsi3_w"
3350 [(set (match_operand:SI
0 "register_operand" "=r,&r")
3351 (ior:SI (and:SI (match_operand:SI
1 "register_operand" "
0,
0")
3353 (zero_extend:SI (match_operand:QI
2 "general_operand_src" "r,g>"))))]
3354 "TARGET_H8300H || TARGET_H8300S"
3356 [(set_attr "length" "
2,
8")
3357 (set_attr "cc" "clobber,clobber")])
3359 (define_insn "*iorsi3_ashift_31"
3360 [(set (match_operand:SI
0 "register_operand" "=&r")
3361 (ior:SI (ashift:SI (match_operand:SI
1 "register_operand" "r")
3363 (match_operand:SI
2 "register_operand" "
0")))]
3364 "TARGET_H8300H || TARGET_H8300S"
3365 "rotxl.l
\\t%S0\;bor
\\t#
0,%w1\;rotxr.l
\\t%S0"
3366 [(set_attr "length" "
6")
3367 (set_attr "cc" "set_znv")])
3369 (define_insn "*iorsi3_and_ashift"
3370 [(set (match_operand:SI
0 "register_operand" "=r")
3371 (ior:SI (and:SI (ashift:SI (match_operand:SI
1 "register_operand" "r")
3372 (match_operand:SI
2 "const_int_operand" "n"))
3373 (match_operand:SI
3 "single_one_operand" "n"))
3374 (match_operand:SI
4 "register_operand" "
0")))]
3375 "(TARGET_H8300H || TARGET_H8300S)
3376 && (INTVAL (operands[
3]) & ~
0xffff) ==
0"
3379 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[
3]))
3380 - INTVAL (operands[
2]));
3381 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[
3])));
3382 operands[
2] = srcpos;
3383 operands[
3] = dstpos;
3384 return
\"bld
\\t%Z2,%Y1\;bor
\\t%Z3,%Y0\;bst
\\t%Z3,%Y0
\";
3386 [(set_attr "length" "
6")
3387 (set_attr "cc" "clobber")])
3389 (define_insn "*iorsi3_and_lshiftrt"
3390 [(set (match_operand:SI
0 "register_operand" "=r")
3391 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
3392 (match_operand:SI
2 "const_int_operand" "n"))
3393 (match_operand:SI
3 "single_one_operand" "n"))
3394 (match_operand:SI
4 "register_operand" "
0")))]
3395 "(TARGET_H8300H || TARGET_H8300S)
3396 && ((INTVAL (operands[
3]) << INTVAL (operands[
2])) & ~
0xffff) ==
0"
3399 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[
3]))
3400 + INTVAL (operands[
2]));
3401 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[
3])));
3402 operands[
2] = srcpos;
3403 operands[
3] = dstpos;
3404 return
\"bld
\\t%Z2,%Y1\;bor
\\t%Z3,%Y0\;bst
\\t%Z3,%Y0
\";
3406 [(set_attr "length" "
6")
3407 (set_attr "cc" "clobber")])
3409 (define_insn "*iorsi3_zero_extract"
3410 [(set (match_operand:SI
0 "register_operand" "=r")
3411 (ior:SI (zero_extract:SI (match_operand:SI
1 "register_operand" "r")
3413 (match_operand:SI
2 "const_int_operand" "n"))
3414 (match_operand:SI
3 "register_operand" "
0")))]
3415 "(TARGET_H8300H || TARGET_H8300S)
3416 && INTVAL (operands[
2]) <
16"
3417 "bld
\\t%Z2,%Y1\;bor
\\t#
0,%w0\;bst
\\t#
0,%w0"
3418 [(set_attr "length" "
6")
3419 (set_attr "cc" "clobber")])
3421 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3422 [(set (match_operand:SI
0 "register_operand" "=r")
3423 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
3426 (match_operand:SI
2 "register_operand" "
0")))]
3427 "(TARGET_H8300H || TARGET_H8300S)"
3428 "rotl.l
\\t%S1\;rotr.l
\\t%S1\;bor
\\t#
1,%w0\;bst
\\t#
1,%w0"
3429 [(set_attr "length" "
8")
3430 (set_attr "cc" "clobber")])
3432 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3433 [(set (match_operand:SI
0 "register_operand" "=r")
3434 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
3436 (const_int
4194304))
3437 (match_operand:SI
2 "register_operand" "
0")))
3438 (clobber (match_scratch:HI
3 "=&r"))]
3439 "(TARGET_H8300H || TARGET_H8300S)"
3442 if (find_regno_note (insn, REG_DEAD, REGNO (operands[
1])))
3443 return
\"shll.l
\\t%S1\;xor.w
\\t%T3,%T3\;bst
\\t#
6,%s3\;or.w
\\t%T3,%e0
\";
3445 return
\"rotl.l
\\t%S1\;rotr.l
\\t%S1\;xor.w
\\t%T3,%T3\;bst
\\t#
6,%s3\;or.w
\\t%T3,%e0
\";
3447 [(set_attr "length" "
10")
3448 (set_attr "cc" "clobber")])
3450 ;; Used to OR the exponent of a float.
3452 (define_insn "*iorsi3_shift"
3453 [(set (match_operand:SI
0 "register_operand" "=r")
3454 (ior:SI (ashift:SI (match_operand:SI
1 "register_operand" "r")
3456 (match_operand:SI
2 "register_operand" "
0")))
3457 (clobber (match_scratch:SI
3 "=&r"))]
3458 "TARGET_H8300H || TARGET_H8300S"
3463 [(set (match_operand:SI
0 "register_operand" "")
3464 (ior:SI (ashift:SI (match_operand:SI
1 "register_operand" "")
3467 (clobber (match_operand:SI
2 "register_operand" ""))])]
3468 "(TARGET_H8300H || TARGET_H8300S)
3470 && find_regno_note (insn, REG_DEAD, REGNO (operands[
1]))
3471 && REGNO (operands[
0]) != REGNO (operands[
1])"
3472 [(parallel [(set (match_dup
3)
3473 (ashift:HI (match_dup
3)
3475 (clobber (scratch:QI))])
3477 (ior:SI (ashift:SI (match_dup
1)
3480 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
1]));")
3484 [(set (match_operand:SI
0 "register_operand" "")
3485 (ior:SI (ashift:SI (match_operand:SI
1 "register_operand" "")
3488 (clobber (match_operand:SI
2 "register_operand" ""))])]
3489 "(TARGET_H8300H || TARGET_H8300S)
3491 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[
1]))
3492 && REGNO (operands[
0]) != REGNO (operands[
1]))"
3495 (parallel [(set (match_dup
3)
3496 (ashift:HI (match_dup
3)
3498 (clobber (scratch:QI))])
3500 (ior:SI (ashift:SI (match_dup
2)
3503 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
2]));")
3505 (define_insn "*iorsi2_and_1_lshiftrt_1"
3506 [(set (match_operand:SI
0 "register_operand" "=r")
3507 (ior:SI (and:SI (match_operand:SI
1 "register_operand" "
0")
3509 (lshiftrt:SI (match_dup
1)
3511 "TARGET_H8300H || TARGET_H8300S"
3512 "shlr.l
\\t%S0\;bor
\\t#
0,%w0\;bst
\\t#
0,%w0"
3513 [(set_attr "length" "
6")
3514 (set_attr "cc" "clobber")])
3516 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3517 [(set (match_operand:SI
0 "register_operand" "=r")
3518 (ior:SI (ashift:SI (match_operand:SI
1 "register_operand" "
0")
3520 (ashift:SI (match_operand:SI
2 "register_operand" "r")
3522 "(TARGET_H8300H || TARGET_H8300S)"
3524 "&& reload_completed"
3526 (ior:HI (ashift:HI (match_dup
4)
3529 (parallel [(set (match_dup
0)
3530 (ashift:SI (match_dup
0)
3532 (clobber (scratch:QI))])]
3533 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
0]));
3534 operands[
4] = gen_rtx_REG (HImode, REGNO (operands[
2]));")
3536 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3537 [(set (match_operand:SI
0 "register_operand" "=&r")
3538 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI
1 "memory_operand" "m")
0)
3540 (const_int
16711680))
3541 (ashift:SI (subreg:SI (match_operand:QI
2 "memory_operand" "m")
0)
3543 "(TARGET_H8300H || TARGET_H8300S)"
3545 "&& reload_completed"
3547 (ior:HI (zero_extend:HI (match_dup
1))
3548 (ashift:HI (subreg:HI (match_dup
2)
0)
3550 (parallel [(set (match_dup
0)
3551 (ashift:SI (match_dup
0)
3553 (clobber (scratch:QI))])]
3554 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
0]));")
3556 ;; Used to add the exponent of a float.
3558 (define_insn "*addsi3_shift"
3559 [(set (match_operand:SI
0 "register_operand" "=r")
3560 (plus:SI (mult:SI (match_operand:SI
1 "register_operand" "r")
3561 (const_int
8388608))
3562 (match_operand:SI
2 "register_operand" "
0")))
3563 (clobber (match_scratch:SI
3 "=&r"))]
3564 "TARGET_H8300H || TARGET_H8300S"
3569 [(set (match_operand:SI
0 "register_operand" "")
3570 (plus:SI (mult:SI (match_operand:SI
1 "register_operand" "")
3571 (const_int
8388608))
3573 (clobber (match_operand:SI
2 "register_operand" ""))])]
3574 "(TARGET_H8300H || TARGET_H8300S)
3576 && find_regno_note (insn, REG_DEAD, REGNO (operands[
1]))
3577 && REGNO (operands[
0]) != REGNO (operands[
1])"
3578 [(parallel [(set (match_dup
3)
3579 (ashift:HI (match_dup
3)
3581 (clobber (scratch:QI))])
3583 (plus:SI (mult:SI (match_dup
1)
3586 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
1]));")
3590 [(set (match_operand:SI
0 "register_operand" "")
3591 (plus:SI (mult:SI (match_operand:SI
1 "register_operand" "")
3592 (const_int
8388608))
3594 (clobber (match_operand:SI
2 "register_operand" ""))])]
3595 "(TARGET_H8300H || TARGET_H8300S)
3597 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[
1]))
3598 && REGNO (operands[
0]) != REGNO (operands[
1]))"
3601 (parallel [(set (match_dup
3)
3602 (ashift:HI (match_dup
3)
3604 (clobber (scratch:QI))])
3606 (plus:SI (mult:SI (match_dup
2)
3609 "operands[
3] = gen_rtx_REG (HImode, REGNO (operands[
2]));")
3613 (define_insn_and_split "*ashiftsi_sextqi_7"
3614 [(set (match_operand:SI
0 "register_operand" "=r")
3615 (ashift:SI (sign_extend:SI (match_operand:QI
1 "register_operand" "
0"))
3617 "(TARGET_H8300H || TARGET_H8300S)"
3619 "&& reload_completed"
3620 [(parallel [(set (match_dup
2)
3621 (ashift:HI (match_dup
2)
3623 (clobber (scratch:QI))])
3625 (sign_extend:SI (match_dup
2)))
3626 (parallel [(set (match_dup
0)
3627 (ashiftrt:SI (match_dup
0)
3629 (clobber (scratch:QI))])]
3630 "operands[
2] = gen_rtx_REG (HImode, REGNO (operands[
0]));")
3632 ;; Storing a part of HImode to QImode.
3635 [(set (match_operand:QI
0 "general_operand_dst" "=rm<")
3636 (subreg:QI (lshiftrt:HI (match_operand:HI
1 "register_operand" "r")
3640 [(set_attr "cc" "set_znv")
3641 (set_attr "length" "
8")])
3643 ;; Storing a part of SImode to QImode.
3646 [(set (match_operand:QI
0 "general_operand_dst" "=rm<")
3647 (subreg:QI (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
3651 [(set_attr "cc" "set_znv")
3652 (set_attr "length" "
8")])
3655 [(set (match_operand:QI
0 "general_operand_dst" "=rm<")
3656 (subreg:QI (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
3658 (clobber (match_scratch:SI
2 "=&r"))]
3659 "TARGET_H8300H || TARGET_H8300S"
3660 "mov.w
\\t%e1,%f2\;mov.b
\\t%w2,%R0"
3661 [(set_attr "cc" "set_znv")
3662 (set_attr "length" "
10")])
3665 [(set (match_operand:QI
0 "general_operand_dst" "=rm<")
3666 (subreg:QI (lshiftrt:SI (match_operand:SI
1 "register_operand" "r")
3668 (clobber (match_scratch:SI
2 "=&r"))]
3669 "TARGET_H8300H || TARGET_H8300S"
3670 "mov.w
\\t%e1,%f2\;mov.b
\\t%x2,%R0"
3671 [(set_attr "cc" "set_znv")
3672 (set_attr "length" "
10")])
3674 (define_insn_and_split ""
3676 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI
0 "register_operand" "")
0)
3680 (label_ref (match_operand
1 "" ""))
3688 (if_then_else (ge (cc0)
3690 (label_ref (match_dup
1))
3694 (define_insn_and_split ""
3696 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI
0 "register_operand" "")
0)
3700 (label_ref (match_operand
1 "" ""))
3708 (if_then_else (lt (cc0)
3710 (label_ref (match_dup
1))
3714 ;; -----------------------------------------------------------------
3715 ;; PEEPHOLE PATTERNS
3716 ;; -----------------------------------------------------------------
3718 ;; Convert (A >> B) & C to (A &
255) >> B if C ==
255 >> B.
3722 [(set (match_operand:HI
0 "register_operand" "")
3723 (lshiftrt:HI (match_dup
0)
3724 (match_operand:HI
1 "const_int_operand" "")))
3725 (clobber (match_operand:HI
2 "" ""))])
3727 (and:HI (match_dup
0)
3728 (match_operand:HI
3 "const_int_operand" "")))]
3729 "INTVAL (operands[
3]) == (
255 >> INTVAL (operands[
1]))"
3731 (and:HI (match_dup
0)
3735 (lshiftrt:HI (match_dup
0)
3737 (clobber (match_dup
2))])]
3740 ;; Convert (A << B) & C to (A &
255) << B if C ==
255 << B.
3744 [(set (match_operand:HI
0 "register_operand" "")
3745 (ashift:HI (match_dup
0)
3746 (match_operand:HI
1 "const_int_operand" "")))
3747 (clobber (match_operand:HI
2 "" ""))])
3749 (and:HI (match_dup
0)
3750 (match_operand:HI
3 "const_int_operand" "")))]
3751 "INTVAL (operands[
3]) == (
255 << INTVAL (operands[
1]))"
3753 (and:HI (match_dup
0)
3757 (ashift:HI (match_dup
0)
3759 (clobber (match_dup
2))])]
3762 ;; Convert (A >> B) & C to (A &
255) >> B if C ==
255 >> B.
3766 [(set (match_operand:SI
0 "register_operand" "")
3767 (lshiftrt:SI (match_dup
0)
3768 (match_operand:SI
1 "const_int_operand" "")))
3769 (clobber (match_operand:SI
2 "" ""))])
3771 (and:SI (match_dup
0)
3772 (match_operand:SI
3 "const_int_operand" "")))]
3773 "INTVAL (operands[
3]) == (
255 >> INTVAL (operands[
1]))"
3775 (and:SI (match_dup
0)
3779 (lshiftrt:SI (match_dup
0)
3781 (clobber (match_dup
2))])]
3784 ;; Convert (A << B) & C to (A &
255) << B if C ==
255 << B.
3788 [(set (match_operand:SI
0 "register_operand" "")
3789 (ashift:SI (match_dup
0)
3790 (match_operand:SI
1 "const_int_operand" "")))
3791 (clobber (match_operand:SI
2 "" ""))])
3793 (and:SI (match_dup
0)
3794 (match_operand:SI
3 "const_int_operand" "")))]
3795 "INTVAL (operands[
3]) == (
255 << INTVAL (operands[
1]))"
3797 (and:SI (match_dup
0)
3801 (ashift:SI (match_dup
0)
3803 (clobber (match_dup
2))])]
3806 ;; Convert (A >> B) & C to (A &
65535) >> B if C ==
65535 >> B.
3810 [(set (match_operand:SI
0 "register_operand" "")
3811 (lshiftrt:SI (match_dup
0)
3812 (match_operand:SI
1 "const_int_operand" "")))
3813 (clobber (match_operand:SI
2 "" ""))])
3815 (and:SI (match_dup
0)
3816 (match_operand:SI
3 "const_int_operand" "")))]
3817 "INTVAL (operands[
3]) == (
65535 >> INTVAL (operands[
1]))"
3819 (and:SI (match_dup
0)
3823 (lshiftrt:SI (match_dup
0)
3825 (clobber (match_dup
2))])]
3828 ;; Convert (A << B) & C to (A &
65535) << B if C ==
65535 << B.
3832 [(set (match_operand:SI
0 "register_operand" "")
3833 (ashift:SI (match_dup
0)
3834 (match_operand:SI
1 "const_int_operand" "")))
3835 (clobber (match_operand:SI
2 "" ""))])
3837 (and:SI (match_dup
0)
3838 (match_operand:SI
3 "const_int_operand" "")))]
3839 "INTVAL (operands[
3]) == (
65535 << INTVAL (operands[
1]))"
3841 (and:SI (match_dup
0)
3845 (ashift:SI (match_dup
0)
3847 (clobber (match_dup
2))])]
3850 ;; Convert a QImode push into an SImode push so that the
3851 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3854 [(parallel [(set (reg:SI SP_REG)
3855 (plus:SI (reg:SI SP_REG) (const_int -
4)))
3856 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -
3)))
3857 (match_operand:QI
0 "register_operand" ""))])]
3858 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3859 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3861 "operands[
0] = gen_rtx_REG (SImode, REGNO (operands[
0]));")
3864 [(parallel [(set (reg:HI SP_REG)
3865 (plus:HI (reg:HI SP_REG) (const_int -
4)))
3866 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -
3)))
3867 (match_operand:QI
0 "register_operand" ""))])]
3868 "TARGET_H8300S && TARGET_NORMAL_MODE"
3869 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3871 "operands[
0] = gen_rtx_REG (SImode, REGNO (operands[
0]));")
3873 ;; Convert a HImode push into an SImode push so that the
3874 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3877 [(parallel [(set (reg:SI SP_REG)
3878 (plus:SI (reg:SI SP_REG) (const_int -
4)))
3879 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -
2)))
3880 (match_operand:HI
0 "register_operand" ""))])]
3881 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3882 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3884 "operands[
0] = gen_rtx_REG (SImode, REGNO (operands[
0]));")
3887 [(parallel [(set (reg:HI SP_REG)
3888 (plus:HI (reg:HI SP_REG) (const_int -
4)))
3889 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -
2)))
3890 (match_operand:HI
0 "register_operand" ""))])]
3891 "TARGET_H8300S && TARGET_NORMAL_MODE"
3892 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3894 "operands[
0] = gen_rtx_REG (SImode, REGNO (operands[
0]));")
3896 ;; Cram four pushes into stm.l.
3899 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3900 (match_operand:SI
0 "register_operand" ""))
3901 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3902 (match_operand:SI
1 "register_operand" ""))
3903 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3904 (match_operand:SI
2 "register_operand" ""))
3905 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3906 (match_operand:SI
3 "register_operand" ""))]
3907 "TARGET_H8300S && !TARGET_NORMAL_MODE
3908 && REGNO (operands[
0]) ==
0
3909 && REGNO (operands[
1]) ==
1
3910 && REGNO (operands[
2]) ==
2
3911 && REGNO (operands[
3]) ==
3"
3912 [(parallel [(set (reg:SI SP_REG)
3913 (plus:SI (reg:SI SP_REG)
3915 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
4)))
3917 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
8)))
3919 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
12)))
3921 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
16)))
3926 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3927 (match_operand:SI
0 "register_operand" ""))
3928 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3929 (match_operand:SI
1 "register_operand" ""))
3930 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3931 (match_operand:SI
2 "register_operand" ""))
3932 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3933 (match_operand:SI
3 "register_operand" ""))]
3934 "TARGET_H8300S && TARGET_NORMAL_MODE
3935 && REGNO (operands[
0]) ==
0
3936 && REGNO (operands[
1]) ==
1
3937 && REGNO (operands[
2]) ==
2
3938 && REGNO (operands[
3]) ==
3"
3939 [(parallel [(set (reg:HI SP_REG)
3940 (plus:HI (reg:HI SP_REG)
3942 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
4)))
3944 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
8)))
3946 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
12)))
3948 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
16)))
3952 ;; Cram three pushes into stm.l.
3955 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3956 (match_operand:SI
0 "register_operand" ""))
3957 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3958 (match_operand:SI
1 "register_operand" ""))
3959 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3960 (match_operand:SI
2 "register_operand" ""))]
3961 "TARGET_H8300S && !TARGET_NORMAL_MODE
3962 && ((REGNO (operands[
0]) ==
0
3963 && REGNO (operands[
1]) ==
1
3964 && REGNO (operands[
2]) ==
2)
3965 || (REGNO (operands[
0]) ==
4
3966 && REGNO (operands[
1]) ==
5
3967 && REGNO (operands[
2]) ==
6))"
3968 [(parallel [(set (reg:SI SP_REG)
3969 (plus:SI (reg:SI SP_REG)
3971 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
4)))
3973 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
8)))
3975 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
12)))
3980 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3981 (match_operand:SI
0 "register_operand" ""))
3982 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3983 (match_operand:SI
1 "register_operand" ""))
3984 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3985 (match_operand:SI
2 "register_operand" ""))]
3986 "TARGET_H8300S && TARGET_NORMAL_MODE
3987 && ((REGNO (operands[
0]) ==
0
3988 && REGNO (operands[
1]) ==
1
3989 && REGNO (operands[
2]) ==
2)
3990 || (REGNO (operands[
0]) ==
4
3991 && REGNO (operands[
1]) ==
5
3992 && REGNO (operands[
2]) ==
6))"
3993 [(parallel [(set (reg:HI SP_REG)
3994 (plus:HI (reg:HI SP_REG)
3996 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
4)))
3998 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
8)))
4000 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
12)))
4004 ;; Cram two pushes into stm.l.
4007 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4008 (match_operand:SI
0 "register_operand" ""))
4009 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4010 (match_operand:SI
1 "register_operand" ""))]
4011 "TARGET_H8300S && !TARGET_NORMAL_MODE
4012 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
4013 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
4014 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
4015 [(parallel [(set (reg:SI SP_REG)
4016 (plus:SI (reg:SI SP_REG)
4018 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
4)))
4020 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -
8)))
4025 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4026 (match_operand:SI
0 "register_operand" ""))
4027 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4028 (match_operand:SI
1 "register_operand" ""))]
4029 "TARGET_H8300S && TARGET_NORMAL_MODE
4030 && ((REGNO (operands[
0]) ==
0 && REGNO (operands[
1]) ==
1)
4031 || (REGNO (operands[
0]) ==
2 && REGNO (operands[
1]) ==
3)
4032 || (REGNO (operands[
0]) ==
4 && REGNO (operands[
1]) ==
5))"
4033 [(parallel [(set (reg:HI SP_REG)
4034 (plus:HI (reg:HI SP_REG)
4036 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
4)))
4038 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -
8)))
4045 ;; add.w r7,r0 (
6 bytes)
4050 ;; adds #
2,r0 (
4 bytes)
4053 [(set (match_operand:HI
0 "register_operand" "")
4054 (match_operand:HI
1 "const_int_operand" ""))
4056 (plus:HI (match_dup
0)
4057 (match_operand:HI
2 "register_operand" "")))]
4058 "REG_P (operands[
0]) && REG_P (operands[
2])
4059 && REGNO (operands[
0]) != REGNO (operands[
2])
4060 && (CONST_OK_FOR_J (INTVAL (operands[
1]))
4061 || CONST_OK_FOR_L (INTVAL (operands[
1]))
4062 || CONST_OK_FOR_N (INTVAL (operands[
1])))"
4066 (plus:HI (match_dup
0)
4074 ;; add.l er7,er0 (
6 bytes)
4079 ;; adds #
4,er0 (
4 bytes)
4082 [(set (match_operand:SI
0 "register_operand" "")
4083 (match_operand:SI
1 "const_int_operand" ""))
4085 (plus:SI (match_dup
0)
4086 (match_operand:SI
2 "register_operand" "")))]
4087 "(TARGET_H8300H || TARGET_H8300S)
4088 && REG_P (operands[
0]) && REG_P (operands[
2])
4089 && REGNO (operands[
0]) != REGNO (operands[
2])
4090 && (CONST_OK_FOR_L (INTVAL (operands[
1]))
4091 || CONST_OK_FOR_N (INTVAL (operands[
1])))"
4095 (plus:SI (match_dup
0)
4102 ;; add.l #
10,er0 (takes
8 bytes)
4108 ;; add.l er7,er0 (takes
6 bytes)
4111 [(set (match_operand:SI
0 "register_operand" "")
4112 (match_operand:SI
1 "register_operand" ""))
4114 (plus:SI (match_dup
0)
4115 (match_operand:SI
2 "const_int_operand" "")))]
4116 "(TARGET_H8300H || TARGET_H8300S)
4117 && REG_P (operands[
0]) && REG_P (operands[
1])
4118 && REGNO (operands[
0]) != REGNO (operands[
1])
4119 && !CONST_OK_FOR_L (INTVAL (operands[
2]))
4120 && !CONST_OK_FOR_N (INTVAL (operands[
2]))
4121 && ((INTVAL (operands[
2]) &
0xff) == INTVAL (operands[
2])
4122 || (INTVAL (operands[
2]) &
0xff00) == INTVAL (operands[
2])
4123 || INTVAL (operands[
2]) ==
0xffff
4124 || INTVAL (operands[
2]) ==
0xfffe)"
4128 (plus:SI (match_dup
0)
4144 [(set (match_operand:HI
0 "register_operand" "")
4145 (plus:HI (match_dup
0)
4146 (match_operand
1 "incdec_operand" "")))
4150 (if_then_else (match_operator
3 "eqne_operator"
4151 [(cc0) (const_int
0)])
4152 (label_ref (match_operand
2 "" ""))
4154 "TARGET_H8300H || TARGET_H8300S"
4155 [(set (match_operand:HI
0 "register_operand" "")
4156 (unspec:HI [(match_dup
0)
4162 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4163 (label_ref (match_dup
2))
4167 ;; The SImode version of the previous pattern.
4170 [(set (match_operand:SI
0 "register_operand" "")
4171 (plus:SI (match_dup
0)
4172 (match_operand
1 "incdec_operand" "")))
4176 (if_then_else (match_operator
3 "eqne_operator"
4177 [(cc0) (const_int
0)])
4178 (label_ref (match_operand
2 "" ""))
4180 "TARGET_H8300H || TARGET_H8300S"
4181 [(set (match_operand:SI
0 "register_operand" "")
4182 (unspec:SI [(match_dup
0)
4188 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4189 (label_ref (match_dup
2))
4194 [(parallel [(set (cc0)
4195 (zero_extract:SI (match_operand:QI
0 "register_operand" "")
4198 (clobber (scratch:QI))])
4200 (if_then_else (match_operator
1 "eqne_operator"
4201 [(cc0) (const_int
0)])
4202 (label_ref (match_operand
2 "" ""))
4204 "(TARGET_H8300H || TARGET_H8300S)"
4208 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4209 (label_ref (match_dup
2))
4211 "operands[
3] = ((GET_CODE (operands[
1]) == EQ)
4212 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4213 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4215 ;; The next three peephole2's will try to transform
4217 ;; mov.b A,r0l (or mov.l A,er0)
4224 ;; and.b #CST,r0l (if CST is not
255)
4227 [(set (match_operand:QI
0 "register_operand" "")
4228 (match_operand:QI
1 "general_operand" ""))
4229 (set (match_operand:SI
2 "register_operand" "")
4230 (and:SI (match_dup
2)
4232 "(TARGET_H8300H || TARGET_H8300S)
4233 && !reg_overlap_mentioned_p (operands[
2], operands[
1])
4234 && REGNO (operands[
0]) == REGNO (operands[
2])"
4237 (set (strict_low_part (match_dup
0))
4242 [(set (match_operand:SI
0 "register_operand" "")
4243 (match_operand:SI
1 "general_operand" ""))
4245 (and:SI (match_dup
0)
4247 "(TARGET_H8300H || TARGET_H8300S)
4248 && !reg_overlap_mentioned_p (operands[
0], operands[
1])
4249 && !(GET_CODE (operands[
1]) == MEM && MEM_VOLATILE_P (operands[
1]))"
4252 (set (strict_low_part (match_dup
2))
4254 "operands[
2] = gen_lowpart (QImode, operands[
0]);
4255 operands[
3] = gen_lowpart (QImode, operands[
1]);")
4258 [(set (match_operand
0 "register_operand" "")
4259 (match_operand
1 "general_operand" ""))
4260 (set (match_operand:SI
2 "register_operand" "")
4261 (and:SI (match_dup
2)
4262 (match_operand:SI
3 "const_int_qi_operand" "")))]
4263 "(TARGET_H8300H || TARGET_H8300S)
4264 && (GET_MODE (operands[
0]) == QImode
4265 || GET_MODE (operands[
0]) == HImode
4266 || GET_MODE (operands[
0]) == SImode)
4267 && GET_MODE (operands[
0]) == GET_MODE (operands[
1])
4268 && REGNO (operands[
0]) == REGNO (operands[
2])
4269 && !reg_overlap_mentioned_p (operands[
2], operands[
1])
4270 && !(GET_MODE (operands[
1]) != QImode
4271 && GET_CODE (operands[
1]) == MEM
4272 && MEM_VOLATILE_P (operands[
1]))"
4275 (set (strict_low_part (match_dup
4))
4278 (and:SI (match_dup
2)
4280 "operands[
4] = gen_lowpart (QImode, operands[
0]);
4281 operands[
5] = gen_lowpart (QImode, operands[
1]);
4282 operands[
6] = GEN_INT (~
0xff | INTVAL (operands[
3]));")
4285 [(set (match_operand:SI
0 "register_operand" "")
4286 (match_operand:SI
1 "register_operand" ""))
4288 (and:SI (match_dup
0)
4289 (const_int
65280)))]
4290 "(TARGET_H8300H || TARGET_H8300S)
4291 && !reg_overlap_mentioned_p (operands[
0], operands[
1])"
4294 (set (zero_extract:SI (match_dup
0)
4297 (lshiftrt:SI (match_dup
1)
4301 ;; If a load of mem:SI is followed by an AND that turns off the upper
4302 ;; half, then we can load mem:HI instead.
4305 [(set (match_operand:SI
0 "register_operand" "")
4306 (match_operand:SI
1 "memory_operand" ""))
4308 (and:SI (match_dup
0)
4309 (match_operand:SI
2 "const_int_operand" "")))]
4310 "(TARGET_H8300H || TARGET_H8300S)
4311 && !MEM_VOLATILE_P (operands[
1])
4312 && (INTVAL (operands[
2]) & ~
0xffff) ==
0
4313 && INTVAL (operands[
2]) !=
255"
4317 (and:SI (match_dup
0)
4319 "operands[
3] = gen_lowpart (HImode, operands[
0]);
4320 operands[
4] = gen_lowpart (HImode, operands[
1]);")
4322 ;; (compare (reg:HI) (const_int)) takes
4 bytes, so we try to achieve
4323 ;; the equivalent with shorter sequences. Here is the summary. Cases
4324 ;; are grouped for each define_peephole2.
4326 ;; reg const_int use insn
4327 ;; --------------------------------------------------------
4328 ;; dead -
2 eq/ne inc.l
4329 ;; dead -
1 eq/ne inc.l
4330 ;; dead
1 eq/ne dec.l
4331 ;; dead
2 eq/ne dec.l
4333 ;; dead
1 geu/ltu shar.l
4334 ;; dead
3 (H8S) geu/ltu shar.l
4336 ;; ----
255 geu/ltu mov.b
4350 (compare (match_operand:HI
0 "register_operand" "")
4351 (match_operand:HI
1 "incdec_operand" "")))
4353 (if_then_else (match_operator
3 "eqne_operator"
4354 [(cc0) (const_int
0)])
4355 (label_ref (match_operand
2 "" ""))
4357 "(TARGET_H8300H || TARGET_H8300S)
4358 && peep2_reg_dead_p (
1, operands[
0])"
4360 (unspec:HI [(match_dup
0)
4366 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4367 (label_ref (match_dup
2))
4369 "operands[
4] = GEN_INT (- INTVAL (operands[
1]));")
4383 (compare (match_operand:HI
0 "register_operand" "")
4384 (match_operand:HI
1 "const_int_operand" "")))
4386 (if_then_else (match_operator
2 "gtle_operator"
4387 [(cc0) (const_int
0)])
4388 (label_ref (match_operand
3 "" ""))
4390 "(TARGET_H8300H || TARGET_H8300S)
4391 && peep2_reg_dead_p (
1, operands[
0])
4392 && (INTVAL (operands[
1]) ==
1
4393 || (TARGET_H8300S && INTVAL (operands[
1]) ==
3))"
4394 [(parallel [(set (match_dup
0)
4395 (ashiftrt:HI (match_dup
0)
4397 (clobber (scratch:QI))])
4401 (if_then_else (match_dup
4)
4402 (label_ref (match_dup
3))
4404 "switch (GET_CODE (operands[
2]))
4407 operands[
4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4410 operands[
4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4413 operands[
4] = operands[
2];
4416 operands[
5] = GEN_INT (exact_log2 (INTVAL (operands[
1]) +
1));")
4430 (compare (match_operand:HI
0 "register_operand" "")
4433 (if_then_else (match_operator
1 "gtle_operator"
4434 [(cc0) (const_int
0)])
4435 (label_ref (match_operand
2 "" ""))
4437 "TARGET_H8300H || TARGET_H8300S"
4439 (and:HI (match_dup
0)
4442 (if_then_else (match_dup
3)
4443 (label_ref (match_dup
2))
4445 "switch (GET_CODE (operands[
1]))
4448 operands[
3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4451 operands[
3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4454 operands[
3] = operands[
1];
4458 ;; (compare (reg:SI) (const_int)) takes
6 bytes, so we try to achieve
4459 ;; the equivalent with shorter sequences. Here is the summary. Cases
4460 ;; are grouped for each define_peephole2.
4462 ;; reg const_int use insn
4463 ;; --------------------------------------------------------
4464 ;; live -
2 eq/ne copy and inc.l
4465 ;; live -
1 eq/ne copy and inc.l
4466 ;; live
1 eq/ne copy and dec.l
4467 ;; live
2 eq/ne copy and dec.l
4469 ;; dead -
2 eq/ne inc.l
4470 ;; dead -
1 eq/ne inc.l
4471 ;; dead
1 eq/ne dec.l
4472 ;; dead
2 eq/ne dec.l
4474 ;; dead -
131072 eq/ne inc.w and test
4475 ;; dead -
65536 eq/ne inc.w and test
4476 ;; dead
65536 eq/ne dec.w and test
4477 ;; dead
131072 eq/ne dec.w and test
4479 ;; dead
0x000000?? except
1 and
2 eq/ne xor.b and test
4480 ;; dead
0x0000??
00 eq/ne xor.b and test
4481 ;; dead
0x0000ffff eq/ne not.w and test
4483 ;; dead
0xffffff?? except -
1 and -
2 eq/ne xor.b and not.l
4484 ;; dead
0xffff??ff eq/ne xor.b and not.l
4485 ;; dead
0x40000000 (H8S) eq/ne rotl.l and dec.l
4486 ;; dead
0x80000000 eq/ne rotl.l and dec.l
4488 ;; live
1 geu/ltu copy and shar.l
4489 ;; live
3 (H8S) geu/ltu copy and shar.l
4491 ;; dead
1 geu/ltu shar.l
4492 ;; dead
3 (H8S) geu/ltu shar.l
4494 ;; dead
3 (H8/
300H) geu/ltu and.b and test
4495 ;; dead
7 geu/ltu and.b and test
4496 ;; dead
15 geu/ltu and.b and test
4497 ;; dead
31 geu/ltu and.b and test
4498 ;; dead
63 geu/ltu and.b and test
4499 ;; dead
127 geu/ltu and.b and test
4500 ;; dead
255 geu/ltu and.b and test
4502 ;; dead
65535 geu/ltu mov.w
4504 ;; For a small constant, it is cheaper to actually do the subtraction
4505 ;; and then test the register.
4509 (compare (match_operand:SI
0 "register_operand" "")
4510 (match_operand:SI
1 "incdec_operand" "")))
4512 (if_then_else (match_operator
3 "eqne_operator"
4513 [(cc0) (const_int
0)])
4514 (label_ref (match_operand
2 "" ""))
4516 "(TARGET_H8300H || TARGET_H8300S)
4517 && peep2_reg_dead_p (
1, operands[
0])"
4519 (unspec:SI [(match_dup
0)
4525 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4526 (label_ref (match_dup
2))
4528 "operands[
4] = GEN_INT (- INTVAL (operands[
1]));")
4532 (compare (match_operand:SI
0 "register_operand" "")
4533 (match_operand:SI
1 "const_int_operand" "")))
4535 (if_then_else (match_operator
3 "eqne_operator"
4536 [(cc0) (const_int
0)])
4537 (label_ref (match_operand
2 "" ""))
4539 "(TARGET_H8300H || TARGET_H8300S)
4540 && peep2_reg_dead_p (
1, operands[
0])
4541 && (INTVAL (operands[
1]) == -
131072
4542 || INTVAL (operands[
1]) == -
65536
4543 || INTVAL (operands[
1]) ==
65536
4544 || INTVAL (operands[
1]) ==
131072)"
4546 (plus:SI (match_dup
0)
4551 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4552 (label_ref (match_dup
2))
4554 "operands[
4] = GEN_INT (- INTVAL (operands[
1]));")
4556 ;; For certain (in)equality comparisons against a constant, we can
4557 ;; XOR the register with the constant, and test the register against
4562 (compare (match_operand:SI
0 "register_operand" "")
4563 (match_operand:SI
1 "const_int_operand" "")))
4565 (if_then_else (match_operator
3 "eqne_operator"
4566 [(cc0) (const_int
0)])
4567 (label_ref (match_operand
2 "" ""))
4569 "(TARGET_H8300H || TARGET_H8300S)
4570 && peep2_reg_dead_p (
1, operands[
0])
4571 && ((INTVAL (operands[
1]) &
0x00ff) == INTVAL (operands[
1])
4572 || (INTVAL (operands[
1]) &
0xff00) == INTVAL (operands[
1])
4573 || INTVAL (operands[
1]) ==
0x0000ffff)
4574 && INTVAL (operands[
1]) !=
1
4575 && INTVAL (operands[
1]) !=
2"
4577 (xor:SI (match_dup
0)
4582 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4583 (label_ref (match_dup
2))
4589 (compare (match_operand:SI
0 "register_operand" "")
4590 (match_operand:SI
1 "const_int_operand" "")))
4592 (if_then_else (match_operator
3 "eqne_operator"
4593 [(cc0) (const_int
0)])
4594 (label_ref (match_operand
2 "" ""))
4596 "(TARGET_H8300H || TARGET_H8300S)
4597 && peep2_reg_dead_p (
1, operands[
0])
4598 && ((INTVAL (operands[
1]) |
0x00ff) == -
1
4599 || (INTVAL (operands[
1]) |
0xff00) == -
1)
4600 && INTVAL (operands[
1]) != -
1
4601 && INTVAL (operands[
1]) != -
2"
4603 (xor:SI (match_dup
0)
4606 (not:SI (match_dup
0)))
4610 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4611 (label_ref (match_dup
2))
4613 "operands[
4] = GEN_INT (INTVAL (operands[
1]) ^ -
1);")
4617 (compare (match_operand:SI
0 "register_operand" "")
4618 (match_operand:SI
1 "const_int_operand" "")))
4620 (if_then_else (match_operator
3 "eqne_operator"
4621 [(cc0) (const_int
0)])
4622 (label_ref (match_operand
2 "" ""))
4624 "(TARGET_H8300H || TARGET_H8300S)
4625 && peep2_reg_dead_p (
1, operands[
0])
4626 && (INTVAL (operands[
1]) == -
2147483647 -
1
4627 || (TARGET_H8300S && INTVAL (operands[
1]) ==
1073741824))"
4629 (rotate:SI (match_dup
0)
4632 (unspec:SI [(match_dup
0)
4638 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4639 (label_ref (match_dup
2))
4641 "operands[
4] = GEN_INT (INTVAL (operands[
1]) == -
2147483647 -
1 ?
1 :
2);")
4654 ;; We avoid this transformation if we see more than one copy of the
4655 ;; same compare insn immediately before this one.
4658 [(match_scratch:SI
4 "r")
4660 (compare (match_operand:SI
0 "register_operand" "")
4661 (match_operand:SI
1 "const_int_operand" "")))
4663 (if_then_else (match_operator
2 "gtle_operator"
4664 [(cc0) (const_int
0)])
4665 (label_ref (match_operand
3 "" ""))
4667 "(TARGET_H8300H || TARGET_H8300S)
4668 && !peep2_reg_dead_p (
1, operands[
0])
4669 && (INTVAL (operands[
1]) ==
1
4670 || (TARGET_H8300S && INTVAL (operands[
1]) ==
3))
4671 && !same_cmp_preceding_p (insn)"
4674 (parallel [(set (match_dup
4)
4675 (ashiftrt:SI (match_dup
4)
4677 (clobber (scratch:QI))])
4681 (if_then_else (match_dup
5)
4682 (label_ref (match_dup
3))
4684 "switch (GET_CODE (operands[
2]))
4687 operands[
5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4690 operands[
5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4693 operands[
5] = operands[
2];
4696 operands[
6] = GEN_INT (exact_log2 (INTVAL (operands[
1]) +
1));")
4710 (compare (match_operand:SI
0 "register_operand" "")
4711 (match_operand:SI
1 "const_int_operand" "")))
4713 (if_then_else (match_operator
2 "gtle_operator"
4714 [(cc0) (const_int
0)])
4715 (label_ref (match_operand
3 "" ""))
4717 "(TARGET_H8300H || TARGET_H8300S)
4718 && peep2_reg_dead_p (
1, operands[
0])
4719 && (INTVAL (operands[
1]) ==
1
4720 || (TARGET_H8300S && INTVAL (operands[
1]) ==
3))"
4721 [(parallel [(set (match_dup
0)
4722 (ashiftrt:SI (match_dup
0)
4724 (clobber (scratch:QI))])
4728 (if_then_else (match_dup
4)
4729 (label_ref (match_dup
3))
4731 "switch (GET_CODE (operands[
2]))
4734 operands[
4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4737 operands[
4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4740 operands[
4] = operands[
2];
4743 operands[
5] = GEN_INT (exact_log2 (INTVAL (operands[
1]) +
1));")
4758 (compare (match_operand:SI
0 "register_operand" "")
4759 (match_operand:SI
1 "const_int_operand" "")))
4761 (if_then_else (match_operator
2 "gtle_operator"
4762 [(cc0) (const_int
0)])
4763 (label_ref (match_operand
3 "" ""))
4765 "(TARGET_H8300H || TARGET_H8300S)
4766 && peep2_reg_dead_p (
1, operands[
0])
4767 && ((TARGET_H8300H && INTVAL (operands[
1]) ==
3)
4768 || INTVAL (operands[
1]) ==
7
4769 || INTVAL (operands[
1]) ==
15
4770 || INTVAL (operands[
1]) ==
31
4771 || INTVAL (operands[
1]) ==
63
4772 || INTVAL (operands[
1]) ==
127
4773 || INTVAL (operands[
1]) ==
255)"
4775 (and:SI (match_dup
0)
4780 (if_then_else (match_dup
4)
4781 (label_ref (match_dup
3))
4783 "switch (GET_CODE (operands[
2]))
4786 operands[
4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4789 operands[
4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4792 operands[
4] = operands[
2];
4795 operands[
5] = GEN_INT (~INTVAL (operands[
1]));")
4797 ;; Transform A <=
65535 to (A &
0xffff0000) ==
0.
4801 (compare (match_operand:SI
0 "register_operand" "")
4804 (if_then_else (match_operator
1 "gtle_operator"
4805 [(cc0) (const_int
0)])
4806 (label_ref (match_operand
2 "" ""))
4808 "TARGET_H8300H || TARGET_H8300S"
4810 (and:SI (match_dup
0)
4811 (const_int -
65536)))
4813 (if_then_else (match_dup
3)
4814 (label_ref (match_dup
2))
4816 "switch (GET_CODE (operands[
1]))
4819 operands[
3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4822 operands[
3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4825 operands[
3] = operands[
1];
4829 ;; For constants like -
1, -
2,
1,
2, it is still cheaper to make a copy
4830 ;; of the register being tested, do the subtraction on the copy, and
4831 ;; then test the copy. We avoid this transformation if we see more
4832 ;; than one copy of the same compare insn.
4835 [(match_scratch:SI
4 "r")
4837 (compare (match_operand:SI
0 "register_operand" "")
4838 (match_operand:SI
1 "incdec_operand" "")))
4840 (if_then_else (match_operator
3 "eqne_operator"
4841 [(cc0) (const_int
0)])
4842 (label_ref (match_operand
2 "" ""))
4844 "(TARGET_H8300H || TARGET_H8300S)
4845 && !peep2_reg_dead_p (
1, operands[
0])
4846 && !same_cmp_following_p (insn)"
4850 (unspec:SI [(match_dup
4)
4856 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4857 (label_ref (match_dup
2))
4859 "operands[
5] = GEN_INT (- INTVAL (operands[
1]));")
4861 ;; Narrow the mode of testing if possible.
4864 [(set (match_operand:HI
0 "register_operand" "")
4865 (and:HI (match_dup
0)
4866 (match_operand:HI
1 "const_int_qi_operand" "")))
4870 (if_then_else (match_operator
3 "eqne_operator"
4871 [(cc0) (const_int
0)])
4872 (label_ref (match_operand
2 "" ""))
4874 "peep2_reg_dead_p (
2, operands[
0])"
4876 (and:QI (match_dup
4)
4881 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4882 (label_ref (match_dup
2))
4884 "operands[
4] = gen_rtx_REG (QImode, REGNO (operands[
0]));
4885 operands[
5] = gen_int_mode (INTVAL (operands[
1]), QImode);")
4888 [(set (match_operand:SI
0 "register_operand" "")
4889 (and:SI (match_dup
0)
4890 (match_operand:SI
1 "const_int_qi_operand" "")))
4894 (if_then_else (match_operator
3 "eqne_operator"
4895 [(cc0) (const_int
0)])
4896 (label_ref (match_operand
2 "" ""))
4898 "peep2_reg_dead_p (
2, operands[
0])"
4900 (and:QI (match_dup
4)
4905 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4906 (label_ref (match_dup
2))
4908 "operands[
4] = gen_rtx_REG (QImode, REGNO (operands[
0]));
4909 operands[
5] = gen_int_mode (INTVAL (operands[
1]), QImode);")
4912 [(set (match_operand:SI
0 "register_operand" "")
4913 (and:SI (match_dup
0)
4914 (match_operand:SI
1 "const_int_hi_operand" "")))
4918 (if_then_else (match_operator
3 "eqne_operator"
4919 [(cc0) (const_int
0)])
4920 (label_ref (match_operand
2 "" ""))
4922 "peep2_reg_dead_p (
2, operands[
0])"
4924 (and:HI (match_dup
4)
4929 (if_then_else (match_op_dup
3 [(cc0) (const_int
0)])
4930 (label_ref (match_dup
2))
4932 "operands[
4] = gen_rtx_REG (HImode, REGNO (operands[
0]));
4933 operands[
5] = gen_int_mode (INTVAL (operands[
1]), HImode);")
4936 [(set (match_operand:SI
0 "register_operand" "")
4937 (and:SI (match_dup
0)
4938 (match_operand:SI
1 "const_int_qi_operand" "")))
4940 (xor:SI (match_dup
0)
4941 (match_operand:SI
2 "const_int_qi_operand" "")))
4945 (if_then_else (match_operator
4 "eqne_operator"
4946 [(cc0) (const_int
0)])
4947 (label_ref (match_operand
3 "" ""))
4949 "peep2_reg_dead_p (
3, operands[
0])
4950 && (~INTVAL (operands[
1]) & INTVAL (operands[
2])) ==
0"
4952 (and:QI (match_dup
5)
4955 (xor:QI (match_dup
5)
4960 (if_then_else (match_op_dup
4 [(cc0) (const_int
0)])
4961 (label_ref (match_dup
3))
4963 "operands[
5] = gen_rtx_REG (QImode, REGNO (operands[
0]));
4964 operands[
6] = gen_int_mode (INTVAL (operands[
1]), QImode);
4965 operands[
7] = gen_int_mode (INTVAL (operands[
2]), QImode);")