1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com),
5 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Classifies a h8300_src_operand or h8300_dst_operand.
52 A constant operand of some sort.
58 A memory reference with a constant address.
61 A memory reference with a register as its address.
64 Some other kind of memory reference. */
65 enum h8300_operand_class
75 /* Classifies an h8sx shift operation.
78 The shift cannot be done in a single instruction.
81 The shift is effectively a unary operation. The instruction will
82 allow any sort of destination operand and have a format similar
83 to neg and not. This is true of certain power-of-2 shifts.
86 The shift is a binary operation. The destination must be a
87 register and the source can be a register or a constant. */
95 /* For a general two-operand instruction, element [X][Y] gives
96 the length of the opcode fields when the first operand has class
97 (X + 1) and the second has class Y. */
98 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
100 /* Forward declarations. */
101 static const char *byte_reg (rtx
, int);
102 static int h8300_interrupt_function_p (tree
);
103 static int h8300_saveall_function_p (tree
);
104 static int h8300_monitor_function_p (tree
);
105 static int h8300_os_task_function_p (tree
);
106 static void h8300_emit_stack_adjustment (int, unsigned int);
107 static int round_frame_size (int);
108 static unsigned int compute_saved_regs (void);
109 static void push (int);
110 static void pop (int);
111 static const char *cond_string (enum rtx_code
);
112 static unsigned int h8300_asm_insn_count (const char *);
113 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
114 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
115 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
116 #ifndef OBJECT_FORMAT_ELF
117 static void h8300_asm_named_section (const char *, unsigned int, tree
);
119 static int h8300_and_costs (rtx
);
120 static int h8300_shift_costs (rtx
);
121 static void h8300_push_pop (int, int, int, int);
122 static int h8300_stack_offset_p (rtx
, int);
123 static int h8300_ldm_stm_regno (rtx
, int, int, int);
124 static int h8300_ldm_stm_parallel (rtvec
, int, int);
125 static void h8300_reorg (void);
126 static unsigned int h8300_constant_length (rtx
);
127 static unsigned int h8300_displacement_length (rtx
, int);
128 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
129 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
130 static unsigned int h8300_unary_length (rtx
);
131 static unsigned int h8300_short_immediate_length (rtx
);
132 static unsigned int h8300_bitfield_length (rtx
, rtx
);
133 static unsigned int h8300_binary_length (rtx
, const h8300_length_table
*);
134 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
135 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
136 enum h8sx_shift_type
h8sx_classify_shift (enum machine_mode
, enum rtx_code
, rtx
);
138 /* CPU_TYPE, says what cpu we're compiling for. */
141 /* True if a #pragma interrupt has been seen for the current function. */
142 static int pragma_interrupt
;
144 /* True if a #pragma saveall has been seen for the current function. */
145 static int pragma_saveall
;
147 static const char *const names_big
[] =
148 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
150 static const char *const names_extended
[] =
151 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
153 static const char *const names_upper_extended
[] =
154 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
156 /* Points to one of the above. */
157 /* ??? The above could be put in an array indexed by CPU_TYPE. */
158 const char * const *h8_reg_names
;
160 /* Various operations needed by the following, indexed by CPU_TYPE. */
162 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
164 /* Value of MOVE_RATIO. */
165 int h8300_move_ratio
;
167 /* Machine-specific symbol_ref flags. */
168 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
169 #define SYMBOL_FLAG_EIGHTBIT_DATA (SYMBOL_FLAG_MACH_DEP << 1)
170 #define SYMBOL_FLAG_TINY_DATA (SYMBOL_FLAG_MACH_DEP << 2)
172 /* See below where shifts are handled for explanation of this enum. */
182 /* Symbols of the various shifts which can be used as indices. */
186 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
189 /* Macros to keep the shift algorithm tables small. */
190 #define INL SHIFT_INLINE
191 #define ROT SHIFT_ROT_AND
192 #define LOP SHIFT_LOOP
193 #define SPC SHIFT_SPECIAL
195 /* The shift algorithms for each machine, mode, shift type, and shift
196 count are defined below. The three tables below correspond to
197 QImode, HImode, and SImode, respectively. Each table is organized
198 by, in the order of indices, machine, shift type, and shift count. */
200 static enum shift_alg shift_alg_qi
[3][3][8] = {
203 /* 0 1 2 3 4 5 6 7 */
204 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
205 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
206 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
210 /* 0 1 2 3 4 5 6 7 */
211 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
212 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
213 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
217 /* 0 1 2 3 4 5 6 7 */
218 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
219 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
220 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
224 static enum shift_alg shift_alg_hi
[3][3][16] = {
227 /* 0 1 2 3 4 5 6 7 */
228 /* 8 9 10 11 12 13 14 15 */
229 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
230 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
231 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
232 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
233 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
234 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
238 /* 0 1 2 3 4 5 6 7 */
239 /* 8 9 10 11 12 13 14 15 */
240 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
241 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
242 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
243 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
244 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
245 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
249 /* 0 1 2 3 4 5 6 7 */
250 /* 8 9 10 11 12 13 14 15 */
251 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
252 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
253 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
254 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
255 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
256 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
260 static enum shift_alg shift_alg_si
[3][3][32] = {
263 /* 0 1 2 3 4 5 6 7 */
264 /* 8 9 10 11 12 13 14 15 */
265 /* 16 17 18 19 20 21 22 23 */
266 /* 24 25 26 27 28 29 30 31 */
267 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
268 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
269 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
270 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
271 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
272 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
273 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
274 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
275 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
276 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
277 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
278 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
282 /* 0 1 2 3 4 5 6 7 */
283 /* 8 9 10 11 12 13 14 15 */
284 /* 16 17 18 19 20 21 22 23 */
285 /* 24 25 26 27 28 29 30 31 */
286 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
287 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
288 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
289 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
290 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
291 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
292 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
293 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
294 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
295 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
296 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
297 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
301 /* 0 1 2 3 4 5 6 7 */
302 /* 8 9 10 11 12 13 14 15 */
303 /* 16 17 18 19 20 21 22 23 */
304 /* 24 25 26 27 28 29 30 31 */
305 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
306 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
307 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
308 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
309 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
310 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
311 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
312 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
313 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
314 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
315 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
316 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
332 /* Initialize various cpu specific globals at start up. */
335 h8300_init_once (void)
337 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
338 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
339 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
343 cpu_type
= (int) CPU_H8300
;
344 h8_reg_names
= names_big
;
348 /* For this we treat the H8/300H and H8S the same. */
349 cpu_type
= (int) CPU_H8300H
;
350 h8_reg_names
= names_extended
;
352 h8_push_op
= h8_push_ops
[cpu_type
];
353 h8_pop_op
= h8_pop_ops
[cpu_type
];
354 h8_mov_op
= h8_mov_ops
[cpu_type
];
356 if (!TARGET_H8300S
&& TARGET_MAC
)
358 error ("-ms2600 is used without -ms");
359 target_flags
|= MASK_H8300S
;
362 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
364 error ("-mn is used without -mh or -ms");
365 target_flags
^= MASK_NORMAL_MODE
;
368 /* Some of the shifts are optimized for speed by default.
369 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
370 If optimizing for size, change shift_alg for those shift to
375 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
376 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
377 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
378 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
380 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
381 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
383 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
384 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
387 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
388 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
390 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
391 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
393 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
394 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
395 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
396 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
399 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
402 /* Work out a value for MOVE_RATIO. */
405 /* Memory-memory moves are quite expensive without the
406 h8sx instructions. */
407 h8300_move_ratio
= 3;
409 else if (flag_omit_frame_pointer
)
411 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
412 sometimes be as short as two individual memory-to-memory moves,
413 but since they use all the call-saved registers, it seems better
414 to allow up to three moves here. */
415 h8300_move_ratio
= 4;
417 else if (optimize_size
)
419 /* In this case we don't use movmd sequences since they tend
420 to be longer than calls to memcpy(). Memory-to-memory
421 moves are cheaper than for !TARGET_H8300SX, so it makes
422 sense to have a slightly higher threshold. */
423 h8300_move_ratio
= 4;
427 /* We use movmd sequences for some moves since it can be quicker
428 than calling memcpy(). The sequences will need to save and
429 restore er6 though, so bump up the cost. */
430 h8300_move_ratio
= 6;
434 /* Implement REG_CLASS_FROM_LETTER.
436 Some patterns need to use er6 as a scratch register. This is
437 difficult to arrange since er6 is the frame pointer and usually
440 Such patterns should define two alternatives, one which allows only
441 er6 and one which allows any general register. The former alternative
442 should have a 'd' constraint while the latter should be disparaged and
445 Normally, 'd' maps to DESTINATION_REGS and 'D' maps to GENERAL_REGS.
446 However, there are cases where they should be NO_REGS:
448 - 'd' should be NO_REGS when reloading a function that uses the
449 frame pointer. In this case, DESTINATION_REGS won't contain any
450 spillable registers, so the first alternative can't be used.
452 - -fno-omit-frame-pointer means that the frame pointer will
453 always be in use. It's therefore better to map 'd' to NO_REGS
454 before reload so that register allocator will pick the second
457 - we would like 'D' to be be NO_REGS when the frame pointer isn't
458 live, but we the frame pointer may turn out to be needed after
459 we start reload, and then we may have already decided we don't
460 have a choice, so we can't do that. Forcing the register
461 allocator to use er6 if possible might produce better code for
462 small functions: it's more efficient to save and restore er6 in
463 the prologue & epilogue than to do it in a define_split.
464 Hopefully disparaging 'D' will have a similar effect, without
465 forcing a reload failure if the frame pointer is found to be
469 h8300_reg_class_from_letter (int c
)
480 if (!flag_omit_frame_pointer
&& !reload_completed
)
482 if (frame_pointer_needed
&& reload_in_progress
)
484 return DESTINATION_REGS
;
487 /* The meaning of a constraint shouldn't change dynamically, so
488 we can't make this NO_REGS. */
499 /* Return the byte register name for a register rtx X. B should be 0
500 if you want a lower byte register. B should be 1 if you want an
501 upper byte register. */
504 byte_reg (rtx x
, int b
)
506 static const char *const names_small
[] = {
507 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
508 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
514 return names_small
[REGNO (x
) * 2 + b
];
517 /* REGNO must be saved/restored across calls if this macro is true. */
519 #define WORD_REG_USED(regno) \
521 /* No need to save registers if this function will not return. */ \
522 && ! TREE_THIS_VOLATILE (current_function_decl) \
523 && (h8300_saveall_function_p (current_function_decl) \
524 /* Save any call saved register that was used. */ \
525 || (regs_ever_live[regno] && !call_used_regs[regno]) \
526 /* Save the frame pointer if it was used. */ \
527 || (regno == HARD_FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
528 /* Save any register used in an interrupt handler. */ \
529 || (h8300_current_function_interrupt_function_p () \
530 && regs_ever_live[regno]) \
531 /* Save call clobbered registers in non-leaf interrupt \
533 || (h8300_current_function_interrupt_function_p () \
534 && call_used_regs[regno] \
535 && !current_function_is_leaf)))
537 /* Output assembly language to FILE for the operation OP with operand size
538 SIZE to adjust the stack pointer. */
541 h8300_emit_stack_adjustment (int sign
, unsigned int size
)
543 /* If the frame size is 0, we don't have anything to do. */
547 /* H8/300 cannot add/subtract a large constant with a single
548 instruction. If a temporary register is available, load the
549 constant to it and then do the addition. */
552 && !h8300_current_function_interrupt_function_p ()
553 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
555 rtx r3
= gen_rtx_REG (Pmode
, 3);
556 emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
)));
557 emit_insn (gen_addhi3 (stack_pointer_rtx
,
558 stack_pointer_rtx
, r3
));
562 /* The stack adjustment made here is further optimized by the
563 splitter. In case of H8/300, the splitter always splits the
564 addition emitted here to make the adjustment
567 emit_insn (gen_addhi3 (stack_pointer_rtx
,
568 stack_pointer_rtx
, GEN_INT (sign
* size
)));
570 emit_insn (gen_addsi3 (stack_pointer_rtx
,
571 stack_pointer_rtx
, GEN_INT (sign
* size
)));
575 /* Round up frame size SIZE. */
578 round_frame_size (int size
)
580 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
581 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
584 /* Compute which registers to push/pop.
585 Return a bit vector of registers. */
588 compute_saved_regs (void)
590 unsigned int saved_regs
= 0;
593 /* Construct a bit vector of registers to be pushed/popped. */
594 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
596 if (WORD_REG_USED (regno
))
597 saved_regs
|= 1 << regno
;
600 /* Don't push/pop the frame pointer as it is treated separately. */
601 if (frame_pointer_needed
)
602 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
607 /* Emit an insn to push register RN. */
612 rtx reg
= gen_rtx_REG (word_mode
, rn
);
616 x
= gen_push_h8300 (reg
);
617 else if (!TARGET_NORMAL_MODE
)
618 x
= gen_push_h8300hs_advanced (reg
);
620 x
= gen_push_h8300hs_normal (reg
);
622 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
625 /* Emit an insn to pop register RN. */
630 rtx reg
= gen_rtx_REG (word_mode
, rn
);
634 x
= gen_pop_h8300 (reg
);
635 else if (!TARGET_NORMAL_MODE
)
636 x
= gen_pop_h8300hs_advanced (reg
);
638 x
= gen_pop_h8300hs_normal (reg
);
640 REG_NOTES (x
) = gen_rtx_EXPR_LIST (REG_INC
, stack_pointer_rtx
, 0);
643 /* Emit an instruction to push or pop NREGS consecutive registers
644 starting at register REGNO. POP_P selects a pop rather than a
645 push and RETURN_P is true if the instruction should return.
647 It must be possible to do the requested operation in a single
648 instruction. If NREGS == 1 && !RETURN_P, use a normal push
649 or pop insn. Otherwise emit a parallel of the form:
652 [(return) ;; if RETURN_P
653 (save or restore REGNO)
654 (save or restore REGNO + 1)
656 (save or restore REGNO + NREGS - 1)
657 (set sp (plus sp (const_int adjust)))] */
660 h8300_push_pop (int regno
, int nregs
, int pop_p
, int return_p
)
666 /* See whether we can use a simple push or pop. */
667 if (!return_p
&& nregs
== 1)
676 /* We need one element for the return insn, if present, one for each
677 register, and one for stack adjustment. */
678 vec
= rtvec_alloc ((return_p
!= 0) + nregs
+ 1);
679 sp
= stack_pointer_rtx
;
682 /* Add the return instruction. */
685 RTVEC_ELT (vec
, i
) = gen_rtx_RETURN (VOIDmode
);
689 /* Add the register moves. */
690 for (j
= 0; j
< nregs
; j
++)
696 /* Register REGNO + NREGS - 1 is popped first. Before the
697 stack adjustment, its slot is at address @sp. */
698 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
699 rhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (nregs
- j
- 1) * 4));
703 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
704 lhs
= gen_rtx_MEM (SImode
, plus_constant (sp
, (j
+ 1) * -4));
705 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
707 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, lhs
, rhs
);
710 /* Add the stack adjustment. */
711 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
712 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (VOIDmode
, sp
,
713 gen_rtx_PLUS (Pmode
, sp
, offset
));
715 emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
718 /* Return true if X has the value sp + OFFSET. */
721 h8300_stack_offset_p (rtx x
, int offset
)
724 return x
== stack_pointer_rtx
;
726 return (GET_CODE (x
) == PLUS
727 && XEXP (x
, 0) == stack_pointer_rtx
728 && GET_CODE (XEXP (x
, 1)) == CONST_INT
729 && INTVAL (XEXP (x
, 1)) == offset
);
732 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
733 something that may be an ldm or stm instruction. If it fits
734 the required template, return the register it loads or stores,
737 LOAD_P is true if X should be a load, false if it should be a store.
738 NREGS is the number of registers that the whole instruction is expected
739 to load or store. INDEX is the index of the register that X should
740 load or store, relative to the lowest-numbered register. */
743 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
745 int regindex
, memindex
, offset
;
748 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
750 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
752 if (GET_CODE (x
) == SET
753 && GET_CODE (XEXP (x
, regindex
)) == REG
754 && GET_CODE (XEXP (x
, memindex
)) == MEM
755 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
756 return REGNO (XEXP (x
, regindex
));
761 /* Return true if the elements of VEC starting at FIRST describe an
762 ldm or stm instruction (LOAD_P says which). */
765 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
768 int nregs
, i
, regno
, adjust
;
770 /* There must be a stack adjustment, a register move, and at least one
771 other operation (a return or another register move). */
772 if (GET_NUM_ELEM (vec
) < 3)
775 /* Get the range of registers to be pushed or popped. */
776 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
777 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
779 /* Check that the call to h8300_ldm_stm_regno succeeded and
780 that we're only dealing with GPRs. */
781 if (regno
< 0 || regno
+ nregs
> 8)
784 /* 2-register h8s instructions must start with an even-numbered register.
785 3- and 4-register instructions must start with er0 or er4. */
788 if ((regno
& 1) != 0)
790 if (nregs
> 2 && (regno
& 3) != 0)
794 /* Check the other loads or stores. */
795 for (i
= 1; i
< nregs
; i
++)
796 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
800 /* Check the stack adjustment. */
801 last
= RTVEC_ELT (vec
, first
+ nregs
);
802 adjust
= (load_p
? nregs
: -nregs
) * 4;
803 return (GET_CODE (last
) == SET
804 && SET_DEST (last
) == stack_pointer_rtx
805 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
808 /* Return true if X is an ldm.l pattern. X is known to be parallel. */
811 h8300_ldm_parallel (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
813 return h8300_ldm_stm_parallel (XVEC (x
, 0), 1, 0);
816 /* Likewise stm.l. */
819 h8300_stm_parallel (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
821 return h8300_ldm_stm_parallel (XVEC (x
, 0), 0, 0);
824 /* Likewise rts/l and rte/l. Note that the .md pattern will check
825 for the return so there's no need to do that here. */
828 h8300_return_parallel (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
830 return h8300_ldm_stm_parallel (XVEC (x
, 0), 1, 1);
833 /* This is what the stack looks like after the prolog of
834 a function with a frame has been set up:
840 <saved registers> <- sp
842 This is what the stack looks like after the prolog of
843 a function which doesn't have a frame:
848 <saved registers> <- sp
851 /* Generate RTL code for the function prologue. */
854 h8300_expand_prologue (void)
860 /* If the current function has the OS_Task attribute set, then
861 we have a naked prologue. */
862 if (h8300_os_task_function_p (current_function_decl
))
865 if (h8300_monitor_function_p (current_function_decl
))
866 /* My understanding of monitor functions is they act just like
867 interrupt functions, except the prologue must mask
869 emit_insn (gen_monitor_prologue ());
871 if (frame_pointer_needed
)
874 push (HARD_FRAME_POINTER_REGNUM
);
875 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
878 /* Push the rest of the registers in ascending order. */
879 saved_regs
= compute_saved_regs ();
880 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
883 if (saved_regs
& (1 << regno
))
887 /* See how many registers we can push at the same time. */
888 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
889 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
892 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
893 && ((saved_regs
>> regno
) & 0x07) == 0x07)
896 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
897 && ((saved_regs
>> regno
) & 0x03) == 0x03)
901 h8300_push_pop (regno
, n_regs
, 0, 0);
905 /* Leave room for locals. */
906 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()));
909 /* Return nonzero if we can use "rts" for the function currently being
913 h8300_can_use_return_insn_p (void)
915 return (reload_completed
916 && !frame_pointer_needed
917 && get_frame_size () == 0
918 && compute_saved_regs () == 0);
921 /* Generate RTL code for the function epilogue. */
924 h8300_expand_epilogue (void)
929 HOST_WIDE_INT frame_size
;
932 if (h8300_os_task_function_p (current_function_decl
))
933 /* OS_Task epilogues are nearly naked -- they just have an
937 frame_size
= round_frame_size (get_frame_size ());
940 /* Deallocate locals. */
941 h8300_emit_stack_adjustment (1, frame_size
);
943 /* Pop the saved registers in descending order. */
944 saved_regs
= compute_saved_regs ();
945 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
948 if (saved_regs
& (1 << regno
))
952 /* See how many registers we can pop at the same time. */
953 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
954 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
957 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
958 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
961 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
962 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
966 /* See if this pop would be the last insn before the return.
967 If so, use rte/l or rts/l instead of pop or ldm.l. */
969 && !frame_pointer_needed
971 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
974 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, 1, returned_p
);
978 /* Pop frame pointer if we had one. */
979 if (frame_pointer_needed
)
983 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, 1, returned_p
);
987 emit_insn (gen_rtx_RETURN (VOIDmode
));
990 /* Return nonzero if the current function is an interrupt
994 h8300_current_function_interrupt_function_p (void)
996 return (h8300_interrupt_function_p (current_function_decl
)
997 || h8300_monitor_function_p (current_function_decl
));
1000 /* Output assembly code for the start of the file. */
1003 h8300_file_start (void)
1005 default_file_start ();
1008 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1009 else if (TARGET_H8300SX
)
1010 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
1011 else if (TARGET_H8300S
)
1012 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
1015 /* Output assembly language code for the end of file. */
1018 h8300_file_end (void)
1020 fputs ("\t.end\n", asm_out_file
);
1023 /* Return true if OP is a valid source operand for an integer move
1027 general_operand_src (rtx op
, enum machine_mode mode
)
1029 if (GET_MODE (op
) == mode
1030 && GET_CODE (op
) == MEM
1031 && GET_CODE (XEXP (op
, 0)) == POST_INC
)
1033 return general_operand (op
, mode
);
1036 /* Return true if OP is a valid destination operand for an integer move
1040 general_operand_dst (rtx op
, enum machine_mode mode
)
1042 if (GET_MODE (op
) == mode
1043 && GET_CODE (op
) == MEM
1044 && GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
1046 return general_operand (op
, mode
);
1049 /* Return true if OP is a suitable first operand for a general arithmetic
1050 insn such as "add". */
1053 h8300_dst_operand (rtx op
, enum machine_mode mode
)
1056 return nonimmediate_operand (op
, mode
);
1057 return register_operand (op
, mode
);
1060 /* Likewise the second operand. */
1063 h8300_src_operand (rtx op
, enum machine_mode mode
)
1066 return general_operand (op
, mode
);
1067 return nonmemory_operand (op
, mode
);
1070 /* Check that an operand is either a register or an unsigned 4-bit
1074 nibble_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1076 return (GET_CODE (op
) == CONST_INT
&& TARGET_H8300SX
1077 && INTVAL (op
) >= 0 && INTVAL (op
) <= 15);
1080 /* Check that an operand is either a register or an unsigned 4-bit
1084 reg_or_nibble_operand (rtx op
, enum machine_mode mode
)
1086 return (nibble_operand (op
, mode
) || register_operand (op
, mode
));
1089 /* Return true if OP is a constant that contains only one 1 in its
1090 binary representation. */
1093 single_one_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1095 if (GET_CODE (operand
) == CONST_INT
)
1097 /* We really need to do this masking because 0x80 in QImode is
1098 represented as -128 for example. */
1099 if (exact_log2 (INTVAL (operand
) & GET_MODE_MASK (mode
)) >= 0)
1106 /* Return true if OP is a constant that contains only one 0 in its
1107 binary representation. */
1110 single_zero_operand (rtx operand
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1112 if (GET_CODE (operand
) == CONST_INT
)
1114 /* We really need to do this masking because 0x80 in QImode is
1115 represented as -128 for example. */
1116 if (exact_log2 (~INTVAL (operand
) & GET_MODE_MASK (mode
)) >= 0)
1123 /* Return true if OP is a valid call operand. */
1126 call_insn_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1128 if (GET_CODE (op
) == MEM
)
1130 rtx inside
= XEXP (op
, 0);
1131 if (register_operand (inside
, Pmode
))
1133 if (CONSTANT_ADDRESS_P (inside
))
1139 /* Return 1 if an addition/subtraction of a constant integer can be
1140 transformed into two consecutive adds/subs that are faster than the
1141 straightforward way. Otherwise, return 0. */
1144 two_insn_adds_subs_operand (rtx op
, enum machine_mode mode
)
1149 if (GET_CODE (op
) == CONST_INT
)
1151 HOST_WIDE_INT value
= INTVAL (op
);
1153 /* Force VALUE to be positive so that we do not have to consider
1154 the negative case. */
1157 if (TARGET_H8300H
|| TARGET_H8300S
)
1159 /* A constant addition/subtraction takes 2 states in QImode,
1160 4 states in HImode, and 6 states in SImode. Thus, the
1161 only case we can win is when SImode is used, in which
1162 case, two adds/subs are used, taking 4 states. */
1172 /* We do not profit directly by splitting addition or
1173 subtraction of 3 and 4. However, since these are
1174 implemented as a sequence of adds or subs, they do not
1175 clobber (cc0) unlike a sequence of add.b and add.x. */
1186 /* Split an add of a small constant into two adds/subs insns.
1188 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1189 instead of adds/subs. */
1192 split_adds_subs (enum machine_mode mode
, rtx
*operands
)
1194 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1195 rtx reg
= operands
[0];
1196 HOST_WIDE_INT sign
= 1;
1197 HOST_WIDE_INT amount
;
1198 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1200 /* Force VAL to be positive so that we do not have to consider the
1211 gen_add
= gen_addhi3
;
1215 gen_add
= gen_addsi3
;
1222 /* Try different amounts in descending order. */
1223 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1227 for (; val
>= amount
; val
-= amount
)
1228 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1234 /* Return true if OP is a valid call operand, and OP represents
1235 an operand for a small call (4 bytes instead of 6 bytes). */
1238 small_call_insn_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1240 if (GET_CODE (op
) == MEM
)
1242 rtx inside
= XEXP (op
, 0);
1244 /* Register indirect is a small call. */
1245 if (register_operand (inside
, Pmode
))
1248 /* A call through the function vector is a small call too. */
1249 if (GET_CODE (inside
) == SYMBOL_REF
1250 && (SYMBOL_REF_FLAGS (inside
) & SYMBOL_FLAG_FUNCVEC_FUNCTION
))
1253 /* Otherwise it's a large call. */
1257 /* Return true if OP is a valid jump operand. */
1260 jump_address_operand (rtx op
, enum machine_mode mode
)
1262 if (GET_CODE (op
) == REG
)
1263 return mode
== Pmode
;
1265 if (GET_CODE (op
) == MEM
)
1267 rtx inside
= XEXP (op
, 0);
1268 if (register_operand (inside
, Pmode
))
1270 if (CONSTANT_ADDRESS_P (inside
))
1276 /* Recognize valid operands for bit-field instructions. */
1279 bit_operand (rtx op
, enum machine_mode mode
)
1281 /* We can accept any nonimmediate operand, except that MEM operands must
1282 be limited to those that use addresses valid for the 'U' constraint. */
1283 if (!nonimmediate_operand (op
, mode
))
1286 /* H8SX accepts pretty much anything here. */
1290 /* Accept any mem during RTL generation. Otherwise, the code that does
1291 insv and extzv will think that we cannot handle memory. However,
1292 to avoid reload problems, we only accept 'U' MEM operands after RTL
1293 generation. This means that any named pattern which uses this predicate
1294 must force its operands to match 'U' before emitting RTL. */
1296 if (GET_CODE (op
) == REG
)
1298 if (GET_CODE (op
) == SUBREG
)
1300 return (GET_CODE (op
) == MEM
1304 /* Return nonzero if OP is a MEM suitable for bit manipulation insns. */
1307 bit_memory_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1309 return (GET_CODE (op
) == MEM
1313 /* Handle machine specific pragmas for compatibility with existing
1314 compilers for the H8/300.
1316 pragma saveall generates prologue/epilogue code which saves and
1317 restores all the registers on function entry.
1319 pragma interrupt saves and restores all registers, and exits with
1320 an rte instruction rather than an rts. A pointer to a function
1321 with this attribute may be safely used in an interrupt vector. */
1324 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1326 pragma_interrupt
= 1;
1330 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1335 /* If the next function argument with MODE and TYPE is to be passed in
1336 a register, return a reg RTX for the hard register in which to pass
1337 the argument. CUM represents the state after the last argument.
1338 If the argument is to be pushed, NULL_RTX is returned. */
1341 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1342 tree type
, int named
)
1344 static const char *const hand_list
[] = {
1363 rtx result
= NULL_RTX
;
1367 /* Never pass unnamed arguments in registers. */
1371 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1372 if (TARGET_QUICKCALL
)
1375 /* If calling hand written assembler, use 4 regs of args. */
1378 const char * const *p
;
1380 fname
= XSTR (cum
->libcall
, 0);
1382 /* See if this libcall is one of the hand coded ones. */
1383 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1394 if (mode
== BLKmode
)
1395 size
= int_size_in_bytes (type
);
1397 size
= GET_MODE_SIZE (mode
);
1399 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1400 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1401 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1407 /* Compute the cost of an and insn. */
1410 h8300_and_costs (rtx x
)
1414 if (GET_MODE (x
) == QImode
)
1417 if (GET_MODE (x
) != HImode
1418 && GET_MODE (x
) != SImode
)
1422 operands
[1] = XEXP (x
, 0);
1423 operands
[2] = XEXP (x
, 1);
1425 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1428 /* Compute the cost of a shift insn. */
1431 h8300_shift_costs (rtx x
)
1435 if (GET_MODE (x
) != QImode
1436 && GET_MODE (x
) != HImode
1437 && GET_MODE (x
) != SImode
)
1442 operands
[2] = XEXP (x
, 1);
1444 return compute_a_shift_length (NULL
, operands
) / 2;
1447 /* Worker function for TARGET_RTX_COSTS. */
1450 h8300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
1452 if (TARGET_H8300SX
&& outer_code
== MEM
)
1454 /* Estimate the number of execution states needed to calculate
1456 if (register_operand (x
, VOIDmode
)
1457 || GET_CODE (x
) == POST_INC
1458 || GET_CODE (x
) == POST_DEC
1462 *total
= COSTS_N_INSNS (1);
1470 HOST_WIDE_INT n
= INTVAL (x
);
1474 /* Constant operands need the same number of processor
1475 states as register operands. Although we could try to
1476 use a size-based cost for optimize_size, the lack of
1477 of a mode makes the results very unpredictable. */
1481 if (-4 <= n
|| n
<= 4)
1492 *total
= 0 + (outer_code
== SET
);
1496 if (TARGET_H8300H
|| TARGET_H8300S
)
1497 *total
= 0 + (outer_code
== SET
);
1512 /* See comment for CONST_INT. */
1524 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1525 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1527 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1530 /* We say that MOD and DIV are so expensive because otherwise we'll
1531 generate some really horrible code for division of a power of two. */
1537 switch (GET_MODE (x
))
1541 *total
= COSTS_N_INSNS (optimize_size
? 4 : 10);
1545 *total
= COSTS_N_INSNS (optimize_size
? 4 : 18);
1551 *total
= COSTS_N_INSNS (12);
1556 switch (GET_MODE (x
))
1560 *total
= COSTS_N_INSNS (2);
1564 *total
= COSTS_N_INSNS (5);
1570 *total
= COSTS_N_INSNS (4);
1576 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1578 *total
= COSTS_N_INSNS (2);
1581 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1583 *total
= COSTS_N_INSNS (1);
1586 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1591 if (GET_MODE (x
) == HImode
)
1598 *total
= COSTS_N_INSNS (1);
1603 /* Documentation for the machine specific operand escapes:
1605 'E' like s but negative.
1606 'F' like t but negative.
1607 'G' constant just the negative
1608 'R' print operand as a byte:8 address if appropriate, else fall back to
1610 'S' print operand as a long word
1611 'T' print operand as a word
1612 'V' find the set bit, and print its number.
1613 'W' find the clear bit, and print its number.
1614 'X' print operand as a byte
1615 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1616 If this operand isn't a register, fall back to 'R' handling.
1618 'c' print the opcode corresponding to rtl
1619 'e' first word of 32 bit value - if reg, then least reg. if mem
1620 then least. if const then most sig word
1621 'f' second word of 32 bit value - if reg, then biggest reg. if mem
1622 then +2. if const then least sig word
1623 'j' print operand as condition code.
1624 'k' print operand as reverse condition code.
1625 'm' convert an integer operand to a size suffix (.b, .w or .l)
1626 'o' print an integer without a leading '#'
1627 's' print as low byte of 16 bit value
1628 't' print as high byte of 16 bit value
1629 'w' print as low byte of 32 bit value
1630 'x' print as 2nd byte of 32 bit value
1631 'y' print as 3rd byte of 32 bit value
1632 'z' print as msb of 32 bit value
1635 /* Return assembly language string which identifies a comparison type. */
1638 cond_string (enum rtx_code code
)
1667 /* Print operand X using operand code CODE to assembly language output file
1671 print_operand (FILE *file
, rtx x
, int code
)
1673 /* This is used for communication between codes V,W,Z and Y. */
1679 switch (GET_CODE (x
))
1682 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1685 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1692 switch (GET_CODE (x
))
1695 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1698 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1705 if (GET_CODE (x
) != CONST_INT
)
1707 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1710 if (GET_CODE (x
) == REG
)
1711 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1716 if (GET_CODE (x
) == REG
)
1717 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1722 bitint
= exact_log2 (INTVAL (x
) & 0xff);
1725 fprintf (file
, "#%d", bitint
);
1728 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1731 fprintf (file
, "#%d", bitint
);
1735 if (GET_CODE (x
) == REG
)
1736 fprintf (file
, "%s", byte_reg (x
, 0));
1743 if (GET_CODE (x
) == REG
)
1744 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1746 print_operand (file
, x
, 'R');
1750 bitint
= INTVAL (x
);
1751 fprintf (file
, "#%d", bitint
& 7);
1754 switch (GET_CODE (x
))
1757 fprintf (file
, "or");
1760 fprintf (file
, "xor");
1763 fprintf (file
, "and");
1770 switch (GET_CODE (x
))
1774 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1776 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1779 print_operand (file
, x
, 0);
1782 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1788 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1789 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1790 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1799 switch (GET_CODE (x
))
1803 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1805 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1808 x
= adjust_address (x
, HImode
, 2);
1809 print_operand (file
, x
, 0);
1812 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1818 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1819 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1820 fprintf (file
, "#%ld", (val
& 0xffff));
1828 fputs (cond_string (GET_CODE (x
)), file
);
1831 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1834 if (GET_CODE (x
) != CONST_INT
)
1836 if (INTVAL (x
) == 1)
1838 else if (INTVAL (x
) == 2)
1840 else if (INTVAL (x
) == 4)
1846 print_operand_address (file
, x
);
1849 if (GET_CODE (x
) == CONST_INT
)
1850 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1852 fprintf (file
, "%s", byte_reg (x
, 0));
1855 if (GET_CODE (x
) == CONST_INT
)
1856 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1858 fprintf (file
, "%s", byte_reg (x
, 1));
1861 if (GET_CODE (x
) == CONST_INT
)
1862 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1864 fprintf (file
, "%s",
1865 byte_reg (x
, TARGET_H8300
? 2 : 0));
1868 if (GET_CODE (x
) == CONST_INT
)
1869 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1871 fprintf (file
, "%s",
1872 byte_reg (x
, TARGET_H8300
? 3 : 1));
1875 if (GET_CODE (x
) == CONST_INT
)
1876 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1878 fprintf (file
, "%s", byte_reg (x
, 0));
1881 if (GET_CODE (x
) == CONST_INT
)
1882 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1884 fprintf (file
, "%s", byte_reg (x
, 1));
1889 switch (GET_CODE (x
))
1892 switch (GET_MODE (x
))
1895 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1896 fprintf (file
, "%s", byte_reg (x
, 0));
1897 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1898 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1902 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1906 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1915 rtx addr
= XEXP (x
, 0);
1917 fprintf (file
, "@");
1918 output_address (addr
);
1920 /* Add a length suffix to constant addresses. Although this
1921 is often unnecessary, it helps to avoid ambiguity in the
1922 syntax of mova. If we wrote an insn like:
1924 mova/w.l @(1,@foo.b),er0
1926 then .b would be considered part of the symbol name.
1927 Adding a length after foo will avoid this. */
1928 if (CONSTANT_P (addr
))
1932 /* Used for mov.b and bit operations. */
1933 if (h8300_eightbit_constant_address_p (addr
))
1935 fprintf (file
, ":8");
1939 /* Fall through. We should not get here if we are
1940 processing bit operations on H8/300 or H8/300H
1941 because 'U' constraint does not allow bit
1942 operations on the tiny area on these machines. */
1947 if (h8300_constant_length (addr
) == 2)
1948 fprintf (file
, ":16");
1950 fprintf (file
, ":32");
1962 fprintf (file
, "#");
1963 print_operand_address (file
, x
);
1969 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
1970 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
1971 fprintf (file
, "#%ld", val
);
1980 /* Output assembly language output for the address ADDR to FILE. */
1983 print_operand_address (FILE *file
, rtx addr
)
1988 switch (GET_CODE (addr
))
1991 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1995 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1999 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
2003 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
2007 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
2011 fprintf (file
, "(");
2013 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
2014 if (GET_CODE (index
) == REG
)
2017 print_operand_address (file
, XEXP (addr
, 1));
2018 fprintf (file
, ",");
2022 print_operand_address (file
, index
);
2026 print_operand (file
, index
, 'X');
2031 print_operand (file
, index
, 'T');
2036 print_operand (file
, index
, 'S');
2040 /* print_operand_address (file, XEXP (addr, 0)); */
2045 print_operand_address (file
, XEXP (addr
, 0));
2046 fprintf (file
, "+");
2047 print_operand_address (file
, XEXP (addr
, 1));
2049 fprintf (file
, ")");
2054 /* Since the H8/300 only has 16 bit pointers, negative values are also
2055 those >= 32768. This happens for example with pointer minus a
2056 constant. We don't want to turn (char *p - 2) into
2057 (char *p + 65534) because loop unrolling can build upon this
2058 (IE: char *p + 131068). */
2059 int n
= INTVAL (addr
);
2061 n
= (int) (short) n
;
2062 fprintf (file
, "%d", n
);
2067 output_addr_const (file
, addr
);
2072 /* Output all insn addresses and their sizes into the assembly language
2073 output file. This is helpful for debugging whether the length attributes
2074 in the md file are correct. This is not meant to be a user selectable
2078 final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
2079 int num_operands ATTRIBUTE_UNUSED
)
2081 /* This holds the last insn address. */
2082 static int last_insn_address
= 0;
2084 const int uid
= INSN_UID (insn
);
2086 if (TARGET_ADDRESSES
)
2088 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
2089 INSN_ADDRESSES (uid
) - last_insn_address
);
2090 last_insn_address
= INSN_ADDRESSES (uid
);
2094 /* Prepare for an SI sized move. */
2097 h8300_expand_movsi (rtx operands
[])
2099 rtx src
= operands
[1];
2100 rtx dst
= operands
[0];
2101 if (!reload_in_progress
&& !reload_completed
)
2103 if (!register_operand (dst
, GET_MODE (dst
)))
2105 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
2106 emit_move_insn (tmp
, src
);
2113 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
2114 Define the offset between two registers, one to be eliminated, and
2115 the other its replacement, at the start of a routine. */
2118 h8300_initial_elimination_offset (int from
, int to
)
2120 /* The number of bytes that the return address takes on the stack. */
2121 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
2123 /* The number of bytes that the saved frame pointer takes on the stack. */
2124 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
2126 /* The number of bytes that the saved registers, excluding the frame
2127 pointer, take on the stack. */
2128 int saved_regs_size
= 0;
2130 /* The number of bytes that the locals takes on the stack. */
2131 int frame_size
= round_frame_size (get_frame_size ());
2135 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
2136 if (WORD_REG_USED (regno
))
2137 saved_regs_size
+= UNITS_PER_WORD
;
2139 /* Adjust saved_regs_size because the above loop took the frame
2140 pointer int account. */
2141 saved_regs_size
-= fp_size
;
2143 if (to
== HARD_FRAME_POINTER_REGNUM
)
2147 case ARG_POINTER_REGNUM
:
2148 return pc_size
+ fp_size
;
2149 case RETURN_ADDRESS_POINTER_REGNUM
:
2151 case FRAME_POINTER_REGNUM
:
2152 return -saved_regs_size
;
2157 else if (to
== STACK_POINTER_REGNUM
)
2161 case ARG_POINTER_REGNUM
:
2162 return pc_size
+ saved_regs_size
+ frame_size
;
2163 case RETURN_ADDRESS_POINTER_REGNUM
:
2164 return saved_regs_size
+ frame_size
;
2165 case FRAME_POINTER_REGNUM
:
2175 /* Worker function for RETURN_ADDR_RTX. */
2178 h8300_return_addr_rtx (int count
, rtx frame
)
2183 ret
= gen_rtx_MEM (Pmode
,
2184 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2185 else if (flag_omit_frame_pointer
)
2188 ret
= gen_rtx_MEM (Pmode
,
2189 memory_address (Pmode
,
2190 plus_constant (frame
, UNITS_PER_WORD
)));
2191 set_mem_alias_set (ret
, get_frame_alias_set ());
2195 /* Update the condition code from the insn. */
2198 notice_update_cc (rtx body
, rtx insn
)
2202 switch (get_attr_cc (insn
))
2205 /* Insn does not affect CC at all. */
2209 /* Insn does not change CC, but the 0'th operand has been changed. */
2210 if (cc_status
.value1
!= 0
2211 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2212 cc_status
.value1
= 0;
2213 if (cc_status
.value2
!= 0
2214 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2215 cc_status
.value2
= 0;
2219 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2220 The V flag is unusable. The C flag may or may not be known but
2221 that's ok because alter_cond will change tests to use EQ/NE. */
2223 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2224 set
= single_set (insn
);
2225 cc_status
.value1
= SET_SRC (set
);
2226 if (SET_DEST (set
) != cc0_rtx
)
2227 cc_status
.value2
= SET_DEST (set
);
2231 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2232 The C flag may or may not be known but that's ok because
2233 alter_cond will change tests to use EQ/NE. */
2235 cc_status
.flags
|= CC_NO_CARRY
;
2236 set
= single_set (insn
);
2237 cc_status
.value1
= SET_SRC (set
);
2238 if (SET_DEST (set
) != cc0_rtx
)
2240 /* If the destination is STRICT_LOW_PART, strip off
2242 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2243 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2245 cc_status
.value2
= SET_DEST (set
);
2250 /* The insn is a compare instruction. */
2252 cc_status
.value1
= SET_SRC (body
);
2256 /* Insn doesn't leave CC in a usable state. */
2262 /* Return nonzero if X is a stack pointer. */
2265 stack_pointer_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2267 return x
== stack_pointer_rtx
;
2270 /* Return nonzero if X is a constant whose absolute value is greater
2274 const_int_gt_2_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2276 return (GET_CODE (x
) == CONST_INT
2277 && abs (INTVAL (x
)) > 2);
2280 /* Return nonzero if X is a constant whose absolute value is no
2284 const_int_ge_8_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2286 return (GET_CODE (x
) == CONST_INT
2287 && abs (INTVAL (x
)) >= 8);
2290 /* Return nonzero if X is a constant expressible in QImode. */
2293 const_int_qi_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2295 return (GET_CODE (x
) == CONST_INT
2296 && (INTVAL (x
) & 0xff) == INTVAL (x
));
2299 /* Return nonzero if X is a constant expressible in HImode. */
2302 const_int_hi_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2304 return (GET_CODE (x
) == CONST_INT
2305 && (INTVAL (x
) & 0xffff) == INTVAL (x
));
2308 /* Return nonzero if X is a constant suitable for inc/dec. */
2311 incdec_operand (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2313 return (GET_CODE (x
) == CONST_INT
2314 && (CONST_OK_FOR_M (INTVAL (x
))
2315 || CONST_OK_FOR_O (INTVAL (x
))));
2318 /* Return nonzero if X is either EQ or NE. */
2321 eqne_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2323 enum rtx_code code
= GET_CODE (x
);
2325 return (code
== EQ
|| code
== NE
);
2328 /* Return nonzero if X is either GT or LE. */
2331 gtle_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2333 enum rtx_code code
= GET_CODE (x
);
2335 return (code
== GT
|| code
== LE
);
2338 /* Return nonzero if X is either GTU or LEU. */
2341 gtuleu_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2343 enum rtx_code code
= GET_CODE (x
);
2345 return (code
== GTU
|| code
== LEU
);
2348 /* Return nonzero if X is either IOR or XOR. */
2351 iorxor_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2353 enum rtx_code code
= GET_CODE (x
);
2355 return (code
== IOR
|| code
== XOR
);
2358 /* Recognize valid operators for bit instructions. */
2361 bit_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2363 enum rtx_code code
= GET_CODE (x
);
2370 /* Given that X occurs in an address of the form (plus X constant),
2371 return the part of X that is expected to be a register. There are
2372 four kinds of addressing mode to recognize:
2379 If SIZE is nonnull, and the address is one of the last three forms,
2380 set *SIZE to the index multiplication factor. Set it to 0 for
2381 plain @(dd,Rn) addresses.
2383 MODE is the mode of the value being accessed. It can be VOIDmode
2384 if the address is known to be valid, but its mode is unknown. */
2387 h8300_get_index (rtx x
, enum machine_mode mode
, int *size
)
2394 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2397 && (mode
== VOIDmode
2398 || GET_MODE_CLASS (mode
) == MODE_INT
2399 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2401 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2403 /* When accessing byte-sized values, the index can be
2404 a zero-extended QImode or HImode register. */
2405 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2410 /* We're looking for addresses of the form:
2413 or (mult (zero_extend X) I)
2415 where I is the size of the operand being accessed.
2416 The canonical form of the second expression is:
2418 (and (mult (subreg X) I) J)
2420 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2423 if (GET_CODE (x
) == AND
2424 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2426 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2427 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2429 index
= XEXP (x
, 0);
2430 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2438 if (GET_CODE (index
) == MULT
2439 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2440 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2441 return XEXP (index
, 0);
2448 static const h8300_length_table addb_length_table
=
2450 /* #xx Rs @aa @Rs @xx */
2451 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2452 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2453 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2454 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2457 static const h8300_length_table addw_length_table
=
2459 /* #xx Rs @aa @Rs @xx */
2460 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2461 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2462 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2463 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2466 static const h8300_length_table addl_length_table
=
2468 /* #xx Rs @aa @Rs @xx */
2469 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2470 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2471 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2472 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2475 #define logicb_length_table addb_length_table
2476 #define logicw_length_table addw_length_table
2478 static const h8300_length_table logicl_length_table
=
2480 /* #xx Rs @aa @Rs @xx */
2481 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2482 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2483 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2484 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2487 static const h8300_length_table movb_length_table
=
2489 /* #xx Rs @aa @Rs @xx */
2490 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2491 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2492 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2493 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2496 #define movw_length_table movb_length_table
2498 static const h8300_length_table movl_length_table
=
2500 /* #xx Rs @aa @Rs @xx */
2501 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2502 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2503 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2504 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2507 /* Return the size of the given address or displacement constant. */
2510 h8300_constant_length (rtx constant
)
2512 /* Check for (@d:16,Reg). */
2513 if (GET_CODE (constant
) == CONST_INT
2514 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2517 /* Check for (@d:16,Reg) in cases where the displacement is
2518 an absolute address. */
2519 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2525 /* Return the size of a displacement field in address ADDR, which should
2526 have the form (plus X constant). SIZE is the number of bytes being
2530 h8300_displacement_length (rtx addr
, int size
)
2534 offset
= XEXP (addr
, 1);
2536 /* Check for @(d:2,Reg). */
2537 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2538 && GET_CODE (offset
) == CONST_INT
2539 && (INTVAL (offset
) == size
2540 || INTVAL (offset
) == size
* 2
2541 || INTVAL (offset
) == size
* 3))
2544 return h8300_constant_length (offset
);
2547 /* Store the class of operand OP in *CLASS and return the length of any
2548 extra operand fields. SIZE is the number of bytes in OP. CLASS
2549 can be null if only the length is needed. */
2552 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*class)
2554 enum h8300_operand_class dummy
;
2559 if (CONSTANT_P (op
))
2561 *class = H8OP_IMMEDIATE
;
2563 /* Byte-sized immediates are stored in the opcode fields. */
2567 /* If this is a 32-bit instruction, see whether the constant
2568 will fit into a 16-bit immediate field. */
2571 && GET_CODE (op
) == CONST_INT
2572 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2577 else if (GET_CODE (op
) == MEM
)
2580 if (CONSTANT_P (op
))
2582 *class = H8OP_MEM_ABSOLUTE
;
2583 return h8300_constant_length (op
);
2585 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2587 *class = H8OP_MEM_COMPLEX
;
2588 return h8300_displacement_length (op
, size
);
2590 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2592 *class = H8OP_MEM_COMPLEX
;
2595 else if (register_operand (op
, VOIDmode
))
2597 *class = H8OP_MEM_BASE
;
2601 else if (register_operand (op
, VOIDmode
))
2603 *class = H8OP_REGISTER
;
2609 /* Return the length of the instruction described by TABLE given that
2610 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2611 and OP2 must be an h8300_src_operand. */
2614 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2616 enum h8300_operand_class op1_class
, op2_class
;
2617 unsigned int size
, immediate_length
;
2619 size
= GET_MODE_SIZE (GET_MODE (op1
));
2620 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2621 + h8300_classify_operand (op2
, size
, &op2_class
));
2622 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2625 /* Return the length of a unary instruction such as neg or not given that
2626 its operand is OP. */
2629 h8300_unary_length (rtx op
)
2631 enum h8300_operand_class
class;
2632 unsigned int size
, operand_length
;
2634 size
= GET_MODE_SIZE (GET_MODE (op
));
2635 operand_length
= h8300_classify_operand (op
, size
, &class);
2642 return (size
== 4 ? 6 : 4);
2644 case H8OP_MEM_ABSOLUTE
:
2645 return operand_length
+ (size
== 4 ? 6 : 4);
2647 case H8OP_MEM_COMPLEX
:
2648 return operand_length
+ 6;
2655 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2658 h8300_short_immediate_length (rtx op
)
2660 enum h8300_operand_class
class;
2661 unsigned int size
, operand_length
;
2663 size
= GET_MODE_SIZE (GET_MODE (op
));
2664 operand_length
= h8300_classify_operand (op
, size
, &class);
2672 case H8OP_MEM_ABSOLUTE
:
2673 case H8OP_MEM_COMPLEX
:
2674 return 4 + operand_length
;
2681 /* Likewise bitfield load and store instructions. */
2684 h8300_bitfield_length (rtx op
, rtx op2
)
2686 enum h8300_operand_class
class;
2687 unsigned int size
, operand_length
;
2689 if (GET_CODE (op
) == REG
)
2691 if (GET_CODE (op
) == REG
)
2694 size
= GET_MODE_SIZE (GET_MODE (op
));
2695 operand_length
= h8300_classify_operand (op
, size
, &class);
2700 case H8OP_MEM_ABSOLUTE
:
2701 case H8OP_MEM_COMPLEX
:
2702 return 4 + operand_length
;
2709 /* Calculate the length of general binary instruction INSN using TABLE. */
2712 h8300_binary_length (rtx insn
, const h8300_length_table
*table
)
2716 set
= single_set (insn
);
2720 if (BINARY_P (SET_SRC (set
)))
2721 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2722 XEXP (SET_SRC (set
), 1), table
);
2723 else if (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
)
2724 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2725 XEXP (XEXP (SET_SRC (set
), 1), 1),
2731 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2732 memory reference and either (1) it has the form @(d:16,Rn) or
2733 (2) its address has the code given by INC_CODE. */
2736 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2741 if (GET_CODE (op
) != MEM
)
2744 addr
= XEXP (op
, 0);
2745 size
= GET_MODE_SIZE (GET_MODE (op
));
2746 if (size
!= 1 && size
!= 2)
2749 return (GET_CODE (addr
) == inc_code
2750 || (GET_CODE (addr
) == PLUS
2751 && GET_CODE (XEXP (addr
, 0)) == REG
2752 && h8300_displacement_length (addr
, size
) == 2));
2755 /* Calculate the length of move instruction INSN using the given length
2756 table. Although the tables are correct for most cases, there is some
2757 irregularity in the length of mov.b and mov.w. The following forms:
2764 are two bytes shorter than most other "mov Rs, @complex" or
2765 "mov @complex,Rd" combinations. */
2768 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2772 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2773 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2775 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2780 /* Return the length of a mova instruction with the given operands.
2781 DEST is the register destination, SRC is the source address and
2782 OFFSET is the 16-bit or 32-bit displacement. */
2785 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2790 + h8300_constant_length (offset
)
2791 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2792 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2797 /* Compute the length of INSN based on its length_table attribute.
2798 OPERANDS is the array of its operands. */
2801 h8300_insn_length_from_table (rtx insn
, rtx
* operands
)
2803 switch (get_attr_length_table (insn
))
2805 case LENGTH_TABLE_NONE
:
2808 case LENGTH_TABLE_ADDB
:
2809 return h8300_binary_length (insn
, &addb_length_table
);
2811 case LENGTH_TABLE_ADDW
:
2812 return h8300_binary_length (insn
, &addw_length_table
);
2814 case LENGTH_TABLE_ADDL
:
2815 return h8300_binary_length (insn
, &addl_length_table
);
2817 case LENGTH_TABLE_LOGICB
:
2818 return h8300_binary_length (insn
, &logicb_length_table
);
2820 case LENGTH_TABLE_MOVB
:
2821 return h8300_move_length (operands
, &movb_length_table
);
2823 case LENGTH_TABLE_MOVW
:
2824 return h8300_move_length (operands
, &movw_length_table
);
2826 case LENGTH_TABLE_MOVL
:
2827 return h8300_move_length (operands
, &movl_length_table
);
2829 case LENGTH_TABLE_MOVA
:
2830 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2832 case LENGTH_TABLE_MOVA_ZERO
:
2833 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2835 case LENGTH_TABLE_UNARY
:
2836 return h8300_unary_length (operands
[0]);
2838 case LENGTH_TABLE_MOV_IMM4
:
2839 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2841 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2842 return h8300_short_immediate_length (operands
[0]);
2844 case LENGTH_TABLE_BITFIELD
:
2845 return h8300_bitfield_length (operands
[0], operands
[1]);
2847 case LENGTH_TABLE_BITBRANCH
:
2848 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2854 /* Return true if LHS and RHS are memory references that can be mapped
2855 to the same h8sx assembly operand. LHS appears as the destination of
2856 an instruction and RHS appears as a source.
2858 Three cases are allowed:
2860 - RHS is @+Rn or @-Rn, LHS is @Rn
2861 - RHS is @Rn, LHS is @Rn+ or @Rn-
2862 - RHS and LHS have the same address and neither has side effects. */
2865 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2867 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2869 rhs
= XEXP (rhs
, 0);
2870 lhs
= XEXP (lhs
, 0);
2872 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2873 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2875 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2876 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2878 if (rtx_equal_p (rhs
, lhs
))
2884 /* Return true if OPERANDS[1] can be mapped to the same assembly
2885 operand as OPERANDS[0]. */
2888 h8300_operands_match_p (rtx
*operands
)
2890 if (register_operand (operands
[0], VOIDmode
)
2891 && register_operand (operands
[1], VOIDmode
))
2894 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2900 /* Return true if OP is a binary operator in which it would be safe to
2901 replace register operands with memory operands. */
2904 h8sx_binary_memory_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2906 if (!TARGET_H8300SX
)
2909 if (GET_MODE (op
) != QImode
2910 && GET_MODE (op
) != HImode
2911 && GET_MODE (op
) != SImode
)
2914 switch (GET_CODE (op
))
2924 return h8sx_unary_shift_operator (op
, mode
);
2928 /* Like h8sx_binary_memory_operator, but applies to unary operators. */
2931 h8sx_unary_memory_operator (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2933 if (!TARGET_H8300SX
)
2936 if (GET_MODE (op
) != QImode
2937 && GET_MODE (op
) != HImode
2938 && GET_MODE (op
) != SImode
)
2941 switch (GET_CODE (op
))
2952 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2953 region DEST. The two regions do not overlap and have the common
2954 alignment given by ALIGNMENT. Return true on success.
2956 Using movmd for variable-length moves seems to involve some
2957 complex trade-offs. For instance:
2959 - Preparing for a movmd instruction is similar to preparing
2960 for a memcpy. The main difference is that the arguments
2961 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2963 - Since movmd clobbers the frame pointer, we need to save
2964 and restore it somehow when frame_pointer_needed. This can
2965 sometimes make movmd sequences longer than calls to memcpy().
2967 - The counter register is 16 bits, so the instruction is only
2968 suitable for variable-length moves when sizeof (size_t) == 2.
2969 That's only true in normal mode.
2971 - We will often lack static alignment information. Falling back
2972 on movmd.b would likely be slower than calling memcpy(), at least
2975 This function therefore only uses movmd when the length is a
2976 known constant, and only then if -fomit-frame-pointer is in
2977 effect or if we're not optimizing for size.
2979 At the moment the function uses movmd for all in-range constants,
2980 but it might be better to fall back on memcpy() for large moves
2981 if ALIGNMENT == 1. */
2984 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2985 HOST_WIDE_INT alignment
)
2987 if (!flag_omit_frame_pointer
&& optimize_size
)
2990 if (GET_CODE (length
) == CONST_INT
)
2992 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2996 /* Use movmd.l if the alignment allows it, otherwise fall back
2998 factor
= (alignment
>= 2 ? 4 : 1);
3000 /* Make sure the length is within range. We can handle counter
3001 values up to 65536, although HImode truncation will make
3002 the count appear negative in rtl dumps. */
3003 n
= INTVAL (length
);
3004 if (n
<= 0 || n
/ factor
> 65536)
3007 /* Create temporary registers for the source and destination
3008 pointers. Initialize them to the start of each region. */
3009 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
3010 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
3012 /* Create references to the movmd source and destination blocks. */
3013 first_dest
= replace_equiv_address (dest
, dest_reg
);
3014 first_src
= replace_equiv_address (src
, src_reg
);
3016 set_mem_size (first_dest
, GEN_INT (n
& -factor
));
3017 set_mem_size (first_src
, GEN_INT (n
& -factor
));
3019 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
3020 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
3022 if ((n
& -factor
) != n
)
3024 /* Move SRC and DEST past the region we just copied.
3025 This is done to update the memory attributes. */
3026 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
3027 src
= adjust_address (src
, BLKmode
, n
& -factor
);
3029 /* Replace the addresses with the source and destination
3030 registers, which movmd has left with the right values. */
3031 dest
= replace_equiv_address (dest
, dest_reg
);
3032 src
= replace_equiv_address (src
, src_reg
);
3034 /* Mop up the left-over bytes. */
3036 emit_move_insn (adjust_address (dest
, HImode
, 0),
3037 adjust_address (src
, HImode
, 0));
3039 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
3040 adjust_address (src
, QImode
, n
& 2));
3047 /* Move ADDR into er6 after pushing its old value onto the stack. */
3050 h8300_swap_into_er6 (rtx addr
)
3052 push (HARD_FRAME_POINTER_REGNUM
);
3053 emit_move_insn (hard_frame_pointer_rtx
, addr
);
3054 if (REGNO (addr
) == SP_REG
)
3055 emit_move_insn (hard_frame_pointer_rtx
,
3056 plus_constant (hard_frame_pointer_rtx
,
3057 GET_MODE_SIZE (word_mode
)));
3060 /* Move the current value of er6 into ADDR and pop its old value
3064 h8300_swap_out_of_er6 (rtx addr
)
3066 if (REGNO (addr
) != SP_REG
)
3067 emit_move_insn (addr
, hard_frame_pointer_rtx
);
3068 pop (HARD_FRAME_POINTER_REGNUM
);
3071 /* Return the length of mov instruction. */
3074 compute_mov_length (rtx
*operands
)
3076 /* If the mov instruction involves a memory operand, we compute the
3077 length, assuming the largest addressing mode is used, and then
3078 adjust later in the function. Otherwise, we compute and return
3079 the exact length in one step. */
3080 enum machine_mode mode
= GET_MODE (operands
[0]);
3081 rtx dest
= operands
[0];
3082 rtx src
= operands
[1];
3085 if (GET_CODE (src
) == MEM
)
3086 addr
= XEXP (src
, 0);
3087 else if (GET_CODE (dest
) == MEM
)
3088 addr
= XEXP (dest
, 0);
3094 unsigned int base_length
;
3099 if (addr
== NULL_RTX
)
3102 /* The eightbit addressing is available only in QImode, so
3103 go ahead and take care of it. */
3104 if (h8300_eightbit_constant_address_p (addr
))
3111 if (addr
== NULL_RTX
)
3116 if (src
== const0_rtx
)
3126 if (addr
== NULL_RTX
)
3131 if (GET_CODE (src
) == CONST_INT
)
3133 if (src
== const0_rtx
)
3136 if ((INTVAL (src
) & 0xffff) == 0)
3139 if ((INTVAL (src
) & 0xffff) == 0)
3142 if ((INTVAL (src
) & 0xffff)
3143 == ((INTVAL (src
) >> 16) & 0xffff))
3153 if (addr
== NULL_RTX
)
3158 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
3171 /* Adjust the length based on the addressing mode used.
3172 Specifically, we subtract the difference between the actual
3173 length and the longest one, which is @(d:16,Rs). For SImode
3174 and SFmode, we double the adjustment because two mov.w are
3175 used to do the job. */
3177 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
3178 if (GET_CODE (addr
) == PRE_DEC
3179 || GET_CODE (addr
) == POST_INC
)
3181 if (mode
== QImode
|| mode
== HImode
)
3182 return base_length
- 2;
3184 /* In SImode and SFmode, we use two mov.w instructions, so
3185 double the adjustment. */
3186 return base_length
- 4;
3189 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
3190 in SImode and SFmode, the second mov.w involves an address
3191 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
3193 if (GET_CODE (addr
) == REG
)
3194 return base_length
- 2;
3200 unsigned int base_length
;
3205 if (addr
== NULL_RTX
)
3208 /* The eightbit addressing is available only in QImode, so
3209 go ahead and take care of it. */
3210 if (h8300_eightbit_constant_address_p (addr
))
3217 if (addr
== NULL_RTX
)
3222 if (src
== const0_rtx
)
3232 if (addr
== NULL_RTX
)
3236 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
3242 if (GET_CODE (src
) == CONST_INT
)
3244 int val
= INTVAL (src
);
3249 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
3252 switch (val
& 0xffffffff)
3273 if (addr
== NULL_RTX
)
3278 if (CONST_DOUBLE_OK_FOR_LETTER_P (src
, 'G'))
3291 /* Adjust the length based on the addressing mode used.
3292 Specifically, we subtract the difference between the actual
3293 length and the longest one, which is @(d:24,ERs). */
3295 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3296 if (GET_CODE (addr
) == PRE_DEC
3297 || GET_CODE (addr
) == POST_INC
)
3298 return base_length
- 6;
3300 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3301 if (GET_CODE (addr
) == REG
)
3302 return base_length
- 6;
3304 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3306 if (GET_CODE (addr
) == PLUS
3307 && GET_CODE (XEXP (addr
, 0)) == REG
3308 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3309 && INTVAL (XEXP (addr
, 1)) > -32768
3310 && INTVAL (XEXP (addr
, 1)) < 32767)
3311 return base_length
- 4;
3313 /* @aa:16 is 4 bytes shorter than the longest. */
3314 if (h8300_tiny_constant_address_p (addr
))
3315 return base_length
- 4;
3317 /* @aa:24 is 2 bytes shorter than the longest. */
3318 if (CONSTANT_P (addr
))
3319 return base_length
- 2;
3325 /* Output an addition insn. */
3328 output_plussi (rtx
*operands
)
3330 enum machine_mode mode
= GET_MODE (operands
[0]);
3337 if (GET_CODE (operands
[2]) == REG
)
3338 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3340 if (GET_CODE (operands
[2]) == CONST_INT
)
3342 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3344 if ((n
& 0xffffff) == 0)
3345 return "add\t%z2,%z0";
3346 if ((n
& 0xffff) == 0)
3347 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3348 if ((n
& 0xff) == 0)
3349 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3352 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3356 if (GET_CODE (operands
[2]) == CONST_INT
3357 && register_operand (operands
[1], VOIDmode
))
3359 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3361 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3362 return "add.l\t%S2,%S0";
3363 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3364 return "sub.l\t%G2,%S0";
3366 /* See if we can finish with 2 bytes. */
3368 switch ((unsigned int) intval
& 0xffffffff)
3373 return "adds\t%2,%S0";
3378 return "subs\t%G2,%S0";
3382 operands
[2] = GEN_INT (intval
>> 16);
3383 return "inc.w\t%2,%e0";
3387 operands
[2] = GEN_INT (intval
>> 16);
3388 return "dec.w\t%G2,%e0";
3391 /* See if we can finish with 4 bytes. */
3392 if ((intval
& 0xffff) == 0)
3394 operands
[2] = GEN_INT (intval
>> 16);
3395 return "add.w\t%2,%e0";
3399 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3401 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3402 return "sub.l\t%S2,%S0";
3404 return "add.l\t%S2,%S0";
3408 /* ??? It would be much easier to add the h8sx stuff if a single function
3409 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3410 /* Compute the length of an addition insn. */
3413 compute_plussi_length (rtx
*operands
)
3415 enum machine_mode mode
= GET_MODE (operands
[0]);
3422 if (GET_CODE (operands
[2]) == REG
)
3425 if (GET_CODE (operands
[2]) == CONST_INT
)
3427 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3429 if ((n
& 0xffffff) == 0)
3431 if ((n
& 0xffff) == 0)
3433 if ((n
& 0xff) == 0)
3441 if (GET_CODE (operands
[2]) == CONST_INT
3442 && register_operand (operands
[1], VOIDmode
))
3444 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3446 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3448 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3451 /* See if we can finish with 2 bytes. */
3453 switch ((unsigned int) intval
& 0xffffffff)
3474 /* See if we can finish with 4 bytes. */
3475 if ((intval
& 0xffff) == 0)
3479 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3480 return h8300_length_from_table (operands
[0],
3481 GEN_INT (-INTVAL (operands
[2])),
3482 &addl_length_table
);
3484 return h8300_length_from_table (operands
[0], operands
[2],
3485 &addl_length_table
);
3490 /* Compute which flag bits are valid after an addition insn. */
3493 compute_plussi_cc (rtx
*operands
)
3495 enum machine_mode mode
= GET_MODE (operands
[0]);
3506 if (GET_CODE (operands
[2]) == CONST_INT
3507 && register_operand (operands
[1], VOIDmode
))
3509 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3511 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3513 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3516 /* See if we can finish with 2 bytes. */
3518 switch ((unsigned int) intval
& 0xffffffff)
3523 return CC_NONE_0HIT
;
3528 return CC_NONE_0HIT
;
3539 /* See if we can finish with 4 bytes. */
3540 if ((intval
& 0xffff) == 0)
3548 /* Output a logical insn. */
3551 output_logical_op (enum machine_mode mode
, rtx
*operands
)
3553 /* Figure out the logical op that we need to perform. */
3554 enum rtx_code code
= GET_CODE (operands
[3]);
3555 /* Pretend that every byte is affected if both operands are registers. */
3556 const unsigned HOST_WIDE_INT intval
=
3557 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3558 /* Always use the full instruction if the
3559 first operand is in memory. It is better
3560 to use define_splits to generate the shorter
3561 sequence where valid. */
3562 && register_operand (operands
[1], VOIDmode
)
3563 ? INTVAL (operands
[2]) : 0x55555555);
3564 /* The determinant of the algorithm. If we perform an AND, 0
3565 affects a bit. Otherwise, 1 affects a bit. */
3566 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3567 /* Break up DET into pieces. */
3568 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3569 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3570 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3571 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3572 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3573 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3574 int lower_half_easy_p
= 0;
3575 int upper_half_easy_p
= 0;
3576 /* The name of an insn. */
3598 /* First, see if we can finish with one insn. */
3599 if ((TARGET_H8300H
|| TARGET_H8300S
)
3603 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3604 output_asm_insn (insn_buf
, operands
);
3608 /* Take care of the lower byte. */
3611 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3612 output_asm_insn (insn_buf
, operands
);
3614 /* Take care of the upper byte. */
3617 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3618 output_asm_insn (insn_buf
, operands
);
3623 if (TARGET_H8300H
|| TARGET_H8300S
)
3625 /* Determine if the lower half can be taken care of in no more
3627 lower_half_easy_p
= (b0
== 0
3629 || (code
!= IOR
&& w0
== 0xffff));
3631 /* Determine if the upper half can be taken care of in no more
3633 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3634 || (code
== AND
&& w1
== 0xff00));
3637 /* Check if doing everything with one insn is no worse than
3638 using multiple insns. */
3639 if ((TARGET_H8300H
|| TARGET_H8300S
)
3640 && w0
!= 0 && w1
!= 0
3641 && !(lower_half_easy_p
&& upper_half_easy_p
)
3642 && !(code
== IOR
&& w1
== 0xffff
3643 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3645 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3646 output_asm_insn (insn_buf
, operands
);
3650 /* Take care of the lower and upper words individually. For
3651 each word, we try different methods in the order of
3653 1) the special insn (in case of AND or XOR),
3654 2) the word-wise insn, and
3655 3) The byte-wise insn. */
3657 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3658 output_asm_insn ((code
== AND
)
3659 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3661 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3665 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3666 output_asm_insn (insn_buf
, operands
);
3672 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3673 output_asm_insn (insn_buf
, operands
);
3677 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3678 output_asm_insn (insn_buf
, operands
);
3683 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3684 output_asm_insn ((code
== AND
)
3685 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3687 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3690 && (w0
& 0x8000) != 0)
3692 output_asm_insn ("exts.l\t%S0", operands
);
3694 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3698 output_asm_insn ("extu.w\t%e0", operands
);
3700 else if (TARGET_H8300H
|| TARGET_H8300S
)
3704 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3705 output_asm_insn (insn_buf
, operands
);
3712 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3713 output_asm_insn (insn_buf
, operands
);
3717 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3718 output_asm_insn (insn_buf
, operands
);
3729 /* Compute the length of a logical insn. */
3732 compute_logical_op_length (enum machine_mode mode
, rtx
*operands
)
3734 /* Figure out the logical op that we need to perform. */
3735 enum rtx_code code
= GET_CODE (operands
[3]);
3736 /* Pretend that every byte is affected if both operands are registers. */
3737 const unsigned HOST_WIDE_INT intval
=
3738 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3739 /* Always use the full instruction if the
3740 first operand is in memory. It is better
3741 to use define_splits to generate the shorter
3742 sequence where valid. */
3743 && register_operand (operands
[1], VOIDmode
)
3744 ? INTVAL (operands
[2]) : 0x55555555);
3745 /* The determinant of the algorithm. If we perform an AND, 0
3746 affects a bit. Otherwise, 1 affects a bit. */
3747 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3748 /* Break up DET into pieces. */
3749 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3750 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3751 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3752 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3753 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3754 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3755 int lower_half_easy_p
= 0;
3756 int upper_half_easy_p
= 0;
3758 unsigned int length
= 0;
3763 /* First, see if we can finish with one insn. */
3764 if ((TARGET_H8300H
|| TARGET_H8300S
)
3768 length
= h8300_length_from_table (operands
[1], operands
[2],
3769 &logicw_length_table
);
3773 /* Take care of the lower byte. */
3777 /* Take care of the upper byte. */
3783 if (TARGET_H8300H
|| TARGET_H8300S
)
3785 /* Determine if the lower half can be taken care of in no more
3787 lower_half_easy_p
= (b0
== 0
3789 || (code
!= IOR
&& w0
== 0xffff));
3791 /* Determine if the upper half can be taken care of in no more
3793 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3794 || (code
== AND
&& w1
== 0xff00));
3797 /* Check if doing everything with one insn is no worse than
3798 using multiple insns. */
3799 if ((TARGET_H8300H
|| TARGET_H8300S
)
3800 && w0
!= 0 && w1
!= 0
3801 && !(lower_half_easy_p
&& upper_half_easy_p
)
3802 && !(code
== IOR
&& w1
== 0xffff
3803 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3805 length
= h8300_length_from_table (operands
[1], operands
[2],
3806 &logicl_length_table
);
3810 /* Take care of the lower and upper words individually. For
3811 each word, we try different methods in the order of
3813 1) the special insn (in case of AND or XOR),
3814 2) the word-wise insn, and
3815 3) The byte-wise insn. */
3817 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3821 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3837 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3841 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3844 && (w0
& 0x8000) != 0)
3848 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3854 else if (TARGET_H8300H
|| TARGET_H8300S
)
3875 /* Compute which flag bits are valid after a logical insn. */
3878 compute_logical_op_cc (enum machine_mode mode
, rtx
*operands
)
3880 /* Figure out the logical op that we need to perform. */
3881 enum rtx_code code
= GET_CODE (operands
[3]);
3882 /* Pretend that every byte is affected if both operands are registers. */
3883 const unsigned HOST_WIDE_INT intval
=
3884 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3885 /* Always use the full instruction if the
3886 first operand is in memory. It is better
3887 to use define_splits to generate the shorter
3888 sequence where valid. */
3889 && register_operand (operands
[1], VOIDmode
)
3890 ? INTVAL (operands
[2]) : 0x55555555);
3891 /* The determinant of the algorithm. If we perform an AND, 0
3892 affects a bit. Otherwise, 1 affects a bit. */
3893 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3894 /* Break up DET into pieces. */
3895 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3896 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3897 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3898 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3899 int lower_half_easy_p
= 0;
3900 int upper_half_easy_p
= 0;
3901 /* Condition code. */
3902 enum attr_cc cc
= CC_CLOBBER
;
3907 /* First, see if we can finish with one insn. */
3908 if ((TARGET_H8300H
|| TARGET_H8300S
)
3916 if (TARGET_H8300H
|| TARGET_H8300S
)
3918 /* Determine if the lower half can be taken care of in no more
3920 lower_half_easy_p
= (b0
== 0
3922 || (code
!= IOR
&& w0
== 0xffff));
3924 /* Determine if the upper half can be taken care of in no more
3926 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3927 || (code
== AND
&& w1
== 0xff00));
3930 /* Check if doing everything with one insn is no worse than
3931 using multiple insns. */
3932 if ((TARGET_H8300H
|| TARGET_H8300S
)
3933 && w0
!= 0 && w1
!= 0
3934 && !(lower_half_easy_p
&& upper_half_easy_p
)
3935 && !(code
== IOR
&& w1
== 0xffff
3936 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3942 if ((TARGET_H8300H
|| TARGET_H8300S
)
3945 && (w0
& 0x8000) != 0)
3957 /* Expand a conditional branch. */
3960 h8300_expand_branch (enum rtx_code code
, rtx label
)
3964 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3965 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3966 gen_rtx_LABEL_REF (VOIDmode
, label
),
3968 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, tmp
));
3973 We devote a fair bit of code to getting efficient shifts since we
3974 can only shift one bit at a time on the H8/300 and H8/300H and only
3975 one or two bits at a time on the H8S.
3977 All shift code falls into one of the following ways of
3980 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3981 when a straight line shift is about the same size or smaller than
3984 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3985 off the bits we don't need. This is used when only a few of the
3986 bits in the original value will survive in the shifted value.
3988 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3989 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3990 shifts can be added if the shift count is slightly more than 8 or
3991 16. This case also includes other oddballs that are not worth
3994 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3996 For each shift count, we try to use code that has no trade-off
3997 between code size and speed whenever possible.
3999 If the trade-off is unavoidable, we try to be reasonable.
4000 Specifically, the fastest version is one instruction longer than
4001 the shortest version, we take the fastest version. We also provide
4002 the use a way to switch back to the shortest version with -Os.
4004 For the details of the shift algorithms for various shift counts,
4005 refer to shift_alg_[qhs]i. */
4007 /* Classify a shift with the given mode and code. OP is the shift amount. */
4009 enum h8sx_shift_type
4010 h8sx_classify_shift (enum machine_mode mode
, enum rtx_code code
, rtx op
)
4012 if (!TARGET_H8300SX
)
4013 return H8SX_SHIFT_NONE
;
4019 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
4020 if (GET_CODE (op
) != CONST_INT
)
4021 return H8SX_SHIFT_BINARY
;
4023 /* Reject out-of-range shift amounts. */
4024 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
4025 return H8SX_SHIFT_NONE
;
4027 /* Power-of-2 shifts are effectively unary operations. */
4028 if (exact_log2 (INTVAL (op
)) >= 0)
4029 return H8SX_SHIFT_UNARY
;
4031 return H8SX_SHIFT_BINARY
;
4034 if (op
== const1_rtx
|| op
== const2_rtx
)
4035 return H8SX_SHIFT_UNARY
;
4036 return H8SX_SHIFT_NONE
;
4039 if (GET_CODE (op
) == CONST_INT
4040 && (INTVAL (op
) == 1
4042 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
4043 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
4044 return H8SX_SHIFT_UNARY
;
4045 return H8SX_SHIFT_NONE
;
4048 return H8SX_SHIFT_NONE
;
4052 /* Return true if X is a shift operation of type H8SX_SHIFT_UNARY. */
4055 h8sx_unary_shift_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4057 return (BINARY_P (x
) && NON_COMMUTATIVE_P (x
)
4058 && (h8sx_classify_shift (GET_MODE (x
), GET_CODE (x
), XEXP (x
, 1))
4059 == H8SX_SHIFT_UNARY
));
4062 /* Likewise H8SX_SHIFT_BINARY. */
4065 h8sx_binary_shift_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4067 return (BINARY_P (x
) && NON_COMMUTATIVE_P (x
)
4068 && (h8sx_classify_shift (GET_MODE (x
), GET_CODE (x
), XEXP (x
, 1))
4069 == H8SX_SHIFT_BINARY
));
4072 /* Return the asm template for a single h8sx shift instruction.
4073 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
4074 is the source and OPERANDS[3] is the shift. SUFFIX is the
4075 size suffix ('b', 'w' or 'l') and OPTYPE is the print_operand
4076 prefix for the destination operand. */
4079 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
4081 static char buffer
[16];
4084 switch (GET_CODE (operands
[3]))
4100 if (INTVAL (operands
[2]) > 2)
4102 /* This is really a right rotate. */
4103 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
4104 - INTVAL (operands
[2]));
4112 if (operands
[2] == const1_rtx
)
4113 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
4115 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
4119 nshift_operator (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
4121 switch (GET_CODE (x
))
4133 /* Emit code to do shifts. */
4136 expand_a_shift (enum machine_mode mode
, int code
, rtx operands
[])
4138 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
4140 case H8SX_SHIFT_BINARY
:
4141 operands
[1] = force_reg (mode
, operands
[1]);
4144 case H8SX_SHIFT_UNARY
:
4147 case H8SX_SHIFT_NONE
:
4151 emit_move_insn (operands
[0], operands
[1]);
4153 /* Need a loop to get all the bits we want - we generate the
4154 code at emit time, but need to allocate a scratch reg now. */
4156 emit_insn (gen_rtx_PARALLEL
4159 gen_rtx_SET (VOIDmode
, operands
[0],
4160 gen_rtx_fmt_ee (code
, mode
,
4161 operands
[0], operands
[2])),
4162 gen_rtx_CLOBBER (VOIDmode
,
4163 gen_rtx_SCRATCH (QImode
)))));
4167 /* Symbols of the various modes which can be used as indices. */
4171 QIshift
, HIshift
, SIshift
4174 /* For single bit shift insns, record assembler and what bits of the
4175 condition code are valid afterwards (represented as various CC_FOO
4176 bits, 0 means CC isn't left in a usable state). */
4180 const char *const assembler
;
4184 /* Assembler instruction shift table.
4186 These tables are used to look up the basic shifts.
4187 They are indexed by cpu, shift_type, and mode. */
4189 static const struct shift_insn shift_one
[2][3][3] =
4195 { "shll\t%X0", CC_SET_ZNV
},
4196 { "add.w\t%T0,%T0", CC_SET_ZN
},
4197 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
4199 /* SHIFT_LSHIFTRT */
4201 { "shlr\t%X0", CC_SET_ZNV
},
4202 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
4203 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
4205 /* SHIFT_ASHIFTRT */
4207 { "shar\t%X0", CC_SET_ZNV
},
4208 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
4209 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
4216 { "shll.b\t%X0", CC_SET_ZNV
},
4217 { "shll.w\t%T0", CC_SET_ZNV
},
4218 { "shll.l\t%S0", CC_SET_ZNV
}
4220 /* SHIFT_LSHIFTRT */
4222 { "shlr.b\t%X0", CC_SET_ZNV
},
4223 { "shlr.w\t%T0", CC_SET_ZNV
},
4224 { "shlr.l\t%S0", CC_SET_ZNV
}
4226 /* SHIFT_ASHIFTRT */
4228 { "shar.b\t%X0", CC_SET_ZNV
},
4229 { "shar.w\t%T0", CC_SET_ZNV
},
4230 { "shar.l\t%S0", CC_SET_ZNV
}
4235 static const struct shift_insn shift_two
[3][3] =
4239 { "shll.b\t#2,%X0", CC_SET_ZNV
},
4240 { "shll.w\t#2,%T0", CC_SET_ZNV
},
4241 { "shll.l\t#2,%S0", CC_SET_ZNV
}
4243 /* SHIFT_LSHIFTRT */
4245 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
4246 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
4247 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
4249 /* SHIFT_ASHIFTRT */
4251 { "shar.b\t#2,%X0", CC_SET_ZNV
},
4252 { "shar.w\t#2,%T0", CC_SET_ZNV
},
4253 { "shar.l\t#2,%S0", CC_SET_ZNV
}
4257 /* Rotates are organized by which shift they'll be used in implementing.
4258 There's no need to record whether the cc is valid afterwards because
4259 it is the AND insn that will decide this. */
4261 static const char *const rotate_one
[2][3][3] =
4268 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
4271 /* SHIFT_LSHIFTRT */
4274 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
4277 /* SHIFT_ASHIFTRT */
4280 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
4292 /* SHIFT_LSHIFTRT */
4298 /* SHIFT_ASHIFTRT */
4307 static const char *const rotate_two
[3][3] =
4315 /* SHIFT_LSHIFTRT */
4321 /* SHIFT_ASHIFTRT */
4330 /* Shift algorithm. */
4333 /* The number of bits to be shifted by shift1 and shift2. Valid
4334 when ALG is SHIFT_SPECIAL. */
4335 unsigned int remainder
;
4337 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4338 const char *special
;
4340 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4341 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4344 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4345 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4348 /* CC status for SHIFT_INLINE. */
4351 /* CC status for SHIFT_SPECIAL. */
4355 static void get_shift_alg (enum shift_type
,
4356 enum shift_mode
, unsigned int,
4357 struct shift_info
*);
4359 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4360 best algorithm for doing the shift. The assembler code is stored
4361 in the pointers in INFO. We achieve the maximum efficiency in most
4362 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4363 SImode in particular have a lot of room to optimize.
4365 We first determine the strategy of the shift algorithm by a table
4366 lookup. If that tells us to use a hand crafted assembly code, we
4367 go into the big switch statement to find what that is. Otherwise,
4368 we resort to a generic way, such as inlining. In either case, the
4369 result is returned through INFO. */
4372 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4373 unsigned int count
, struct shift_info
*info
)
4377 /* Find the target CPU. */
4380 else if (TARGET_H8300H
)
4385 /* Find the shift algorithm. */
4386 info
->alg
= SHIFT_LOOP
;
4390 if (count
< GET_MODE_BITSIZE (QImode
))
4391 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4395 if (count
< GET_MODE_BITSIZE (HImode
))
4396 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4400 if (count
< GET_MODE_BITSIZE (SImode
))
4401 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4408 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4412 info
->remainder
= count
;
4416 /* It is up to the caller to know that looping clobbers cc. */
4417 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4418 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4419 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4423 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4424 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4425 info
->cc_inline
= CC_CLOBBER
;
4429 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4430 info
->remainder
= 0;
4431 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4432 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4433 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4434 info
->cc_special
= CC_CLOBBER
;
4438 /* Here we only deal with SHIFT_SPECIAL. */
4442 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4443 through the entire value. */
4444 if (shift_type
== SHIFT_ASHIFTRT
&& count
== 7)
4446 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4458 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4460 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4462 case SHIFT_LSHIFTRT
:
4464 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4466 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4468 case SHIFT_ASHIFTRT
:
4469 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4473 else if ((8 <= count
&& count
<= 13)
4474 || (TARGET_H8300S
&& count
== 14))
4476 info
->remainder
= count
- 8;
4481 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4483 case SHIFT_LSHIFTRT
:
4486 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4487 info
->shift1
= "shlr.b\t%s0";
4488 info
->cc_inline
= CC_SET_ZNV
;
4492 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4493 info
->cc_special
= CC_SET_ZNV
;
4496 case SHIFT_ASHIFTRT
:
4499 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4500 info
->shift1
= "shar.b\t%s0";
4504 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4505 info
->cc_special
= CC_SET_ZNV
;
4510 else if (count
== 14)
4516 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4518 case SHIFT_LSHIFTRT
:
4520 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4522 case SHIFT_ASHIFTRT
:
4524 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4525 else if (TARGET_H8300H
)
4527 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4528 info
->cc_special
= CC_SET_ZNV
;
4530 else /* TARGET_H8300S */
4535 else if (count
== 15)
4540 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4542 case SHIFT_LSHIFTRT
:
4543 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4545 case SHIFT_ASHIFTRT
:
4546 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4553 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4555 info
->remainder
= count
- 8;
4560 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4562 case SHIFT_LSHIFTRT
:
4563 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4564 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4566 case SHIFT_ASHIFTRT
:
4567 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4571 else if (count
== 8 && !TARGET_H8300
)
4576 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4578 case SHIFT_LSHIFTRT
:
4579 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4581 case SHIFT_ASHIFTRT
:
4582 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4586 else if (count
== 15 && TARGET_H8300
)
4592 case SHIFT_LSHIFTRT
:
4593 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4595 case SHIFT_ASHIFTRT
:
4596 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4600 else if (count
== 15 && !TARGET_H8300
)
4605 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4606 info
->cc_special
= CC_SET_ZNV
;
4608 case SHIFT_LSHIFTRT
:
4609 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4610 info
->cc_special
= CC_SET_ZNV
;
4612 case SHIFT_ASHIFTRT
:
4616 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4617 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4618 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4620 info
->remainder
= count
- 16;
4625 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4627 info
->shift1
= "add.w\t%e0,%e0";
4629 case SHIFT_LSHIFTRT
:
4632 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4633 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4637 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4638 info
->cc_special
= CC_SET_ZNV
;
4641 case SHIFT_ASHIFTRT
:
4644 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4645 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4649 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4650 info
->cc_special
= CC_SET_ZNV
;
4655 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4657 info
->remainder
= count
- 24;
4662 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4663 info
->shift1
= "shll.b\t%z0";
4664 info
->cc_inline
= CC_SET_ZNV
;
4666 case SHIFT_LSHIFTRT
:
4667 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4668 info
->shift1
= "shlr.b\t%w0";
4669 info
->cc_inline
= CC_SET_ZNV
;
4671 case SHIFT_ASHIFTRT
:
4672 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0\n\tsubx\t%x0,%x0";
4673 info
->shift1
= "shar.b\t%w0";
4674 info
->cc_inline
= CC_SET_ZNV
;
4678 else if ((TARGET_H8300H
&& count
== 24)
4679 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4681 info
->remainder
= count
- 24;
4686 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4688 case SHIFT_LSHIFTRT
:
4689 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4690 info
->cc_special
= CC_SET_ZNV
;
4692 case SHIFT_ASHIFTRT
:
4693 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4694 info
->cc_special
= CC_SET_ZNV
;
4698 else if (!TARGET_H8300
&& count
== 28)
4704 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4706 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4708 case SHIFT_LSHIFTRT
:
4711 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4712 info
->cc_special
= CC_SET_ZNV
;
4715 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4717 case SHIFT_ASHIFTRT
:
4721 else if (!TARGET_H8300
&& count
== 29)
4727 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4729 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4731 case SHIFT_LSHIFTRT
:
4734 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4735 info
->cc_special
= CC_SET_ZNV
;
4739 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4740 info
->cc_special
= CC_SET_ZNV
;
4743 case SHIFT_ASHIFTRT
:
4747 else if (!TARGET_H8300
&& count
== 30)
4753 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4755 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4757 case SHIFT_LSHIFTRT
:
4759 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4761 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4763 case SHIFT_ASHIFTRT
:
4767 else if (count
== 31)
4774 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4776 case SHIFT_LSHIFTRT
:
4777 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4779 case SHIFT_ASHIFTRT
:
4780 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4789 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4790 info
->cc_special
= CC_SET_ZNV
;
4792 case SHIFT_LSHIFTRT
:
4793 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4794 info
->cc_special
= CC_SET_ZNV
;
4796 case SHIFT_ASHIFTRT
:
4797 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4798 info
->cc_special
= CC_SET_ZNV
;
4811 info
->shift2
= NULL
;
4814 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4815 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4818 h8300_shift_needs_scratch_p (int count
, enum machine_mode mode
)
4823 if (GET_MODE_BITSIZE (mode
) <= count
)
4826 /* Find out the target CPU. */
4829 else if (TARGET_H8300H
)
4834 /* Find the shift algorithm. */
4838 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4839 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4840 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4844 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4845 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4846 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4850 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4851 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4852 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4859 /* On H8/300H, count == 8 uses a scratch register. */
4860 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4861 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4864 /* Output the assembler code for doing shifts. */
4867 output_a_shift (rtx
*operands
)
4869 static int loopend_lab
;
4870 rtx shift
= operands
[3];
4871 enum machine_mode mode
= GET_MODE (shift
);
4872 enum rtx_code code
= GET_CODE (shift
);
4873 enum shift_type shift_type
;
4874 enum shift_mode shift_mode
;
4875 struct shift_info info
;
4882 shift_mode
= QIshift
;
4885 shift_mode
= HIshift
;
4888 shift_mode
= SIshift
;
4897 shift_type
= SHIFT_ASHIFTRT
;
4900 shift_type
= SHIFT_LSHIFTRT
;
4903 shift_type
= SHIFT_ASHIFT
;
4909 if (GET_CODE (operands
[2]) != CONST_INT
)
4911 /* This case must be taken care of by one of the two splitters
4912 that convert a variable shift into a loop. */
4917 int n
= INTVAL (operands
[2]);
4919 /* If the count is negative, make it 0. */
4922 /* If the count is too big, truncate it.
4923 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4924 do the intuitive thing. */
4925 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4926 n
= GET_MODE_BITSIZE (mode
);
4928 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4933 output_asm_insn (info
.special
, operands
);
4939 /* Emit two bit shifts first. */
4940 if (info
.shift2
!= NULL
)
4942 for (; n
> 1; n
-= 2)
4943 output_asm_insn (info
.shift2
, operands
);
4946 /* Now emit one bit shifts for any residual. */
4948 output_asm_insn (info
.shift1
, operands
);
4953 int m
= GET_MODE_BITSIZE (mode
) - n
;
4954 const int mask
= (shift_type
== SHIFT_ASHIFT
4955 ? ((1 << m
) - 1) << n
4959 /* Not all possibilities of rotate are supported. They shouldn't
4960 be generated, but let's watch for 'em. */
4961 if (info
.shift1
== 0)
4964 /* Emit two bit rotates first. */
4965 if (info
.shift2
!= NULL
)
4967 for (; m
> 1; m
-= 2)
4968 output_asm_insn (info
.shift2
, operands
);
4971 /* Now single bit rotates for any residual. */
4973 output_asm_insn (info
.shift1
, operands
);
4975 /* Now mask off the high bits. */
4977 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4978 else if (mode
== HImode
&& (TARGET_H8300H
|| TARGET_H8300S
))
4979 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4983 output_asm_insn (insn_buf
, operands
);
4988 /* A loop to shift by a "large" constant value.
4989 If we have shift-by-2 insns, use them. */
4990 if (info
.shift2
!= NULL
)
4992 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4993 names_big
[REGNO (operands
[4])]);
4994 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4995 output_asm_insn (info
.shift2
, operands
);
4996 output_asm_insn ("add #0xff,%X4", operands
);
4997 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4999 output_asm_insn (info
.shift1
, operands
);
5003 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
5004 names_big
[REGNO (operands
[4])]);
5005 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
5006 output_asm_insn (info
.shift1
, operands
);
5007 output_asm_insn ("add #0xff,%X4", operands
);
5008 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
5018 /* Count the number of assembly instructions in a string TEMPLATE. */
5021 h8300_asm_insn_count (const char *template)
5023 unsigned int count
= 1;
5025 for (; *template; template++)
5026 if (*template == '\n')
5032 /* Compute the length of a shift insn. */
5035 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
5037 rtx shift
= operands
[3];
5038 enum machine_mode mode
= GET_MODE (shift
);
5039 enum rtx_code code
= GET_CODE (shift
);
5040 enum shift_type shift_type
;
5041 enum shift_mode shift_mode
;
5042 struct shift_info info
;
5043 unsigned int wlength
= 0;
5048 shift_mode
= QIshift
;
5051 shift_mode
= HIshift
;
5054 shift_mode
= SIshift
;
5063 shift_type
= SHIFT_ASHIFTRT
;
5066 shift_type
= SHIFT_LSHIFTRT
;
5069 shift_type
= SHIFT_ASHIFT
;
5075 if (GET_CODE (operands
[2]) != CONST_INT
)
5077 /* Get the assembler code to do one shift. */
5078 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
5080 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
5084 int n
= INTVAL (operands
[2]);
5086 /* If the count is negative, make it 0. */
5089 /* If the count is too big, truncate it.
5090 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
5091 do the intuitive thing. */
5092 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
5093 n
= GET_MODE_BITSIZE (mode
);
5095 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
5100 wlength
+= h8300_asm_insn_count (info
.special
);
5102 /* Every assembly instruction used in SHIFT_SPECIAL case
5103 takes 2 bytes except xor.l, which takes 4 bytes, so if we
5104 see xor.l, we just pretend that xor.l counts as two insns
5105 so that the insn length will be computed correctly. */
5106 if (strstr (info
.special
, "xor.l") != NULL
)
5114 if (info
.shift2
!= NULL
)
5116 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
5120 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
5126 int m
= GET_MODE_BITSIZE (mode
) - n
;
5128 /* Not all possibilities of rotate are supported. They shouldn't
5129 be generated, but let's watch for 'em. */
5130 if (info
.shift1
== 0)
5133 if (info
.shift2
!= NULL
)
5135 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
5139 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
5141 /* Now mask off the high bits. */
5162 /* A loop to shift by a "large" constant value.
5163 If we have shift-by-2 insns, use them. */
5164 if (info
.shift2
!= NULL
)
5166 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
5168 wlength
+= h8300_asm_insn_count (info
.shift1
);
5172 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
5182 /* Compute which flag bits are valid after a shift insn. */
5185 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
5187 rtx shift
= operands
[3];
5188 enum machine_mode mode
= GET_MODE (shift
);
5189 enum rtx_code code
= GET_CODE (shift
);
5190 enum shift_type shift_type
;
5191 enum shift_mode shift_mode
;
5192 struct shift_info info
;
5197 shift_mode
= QIshift
;
5200 shift_mode
= HIshift
;
5203 shift_mode
= SIshift
;
5212 shift_type
= SHIFT_ASHIFTRT
;
5215 shift_type
= SHIFT_LSHIFTRT
;
5218 shift_type
= SHIFT_ASHIFT
;
5224 if (GET_CODE (operands
[2]) != CONST_INT
)
5226 /* This case must be taken care of by one of the two splitters
5227 that convert a variable shift into a loop. */
5232 int n
= INTVAL (operands
[2]);
5234 /* If the count is negative, make it 0. */
5237 /* If the count is too big, truncate it.
5238 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
5239 do the intuitive thing. */
5240 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
5241 n
= GET_MODE_BITSIZE (mode
);
5243 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
5248 if (info
.remainder
== 0)
5249 return info
.cc_special
;
5254 return info
.cc_inline
;
5257 /* This case always ends with an and instruction. */
5261 /* A loop to shift by a "large" constant value.
5262 If we have shift-by-2 insns, use them. */
5263 if (info
.shift2
!= NULL
)
5266 return info
.cc_inline
;
5276 /* A rotation by a non-constant will cause a loop to be generated, in
5277 which a rotation by one bit is used. A rotation by a constant,
5278 including the one in the loop, will be taken care of by
5279 output_a_rotate () at the insn emit time. */
5282 expand_a_rotate (rtx operands
[])
5284 rtx dst
= operands
[0];
5285 rtx src
= operands
[1];
5286 rtx rotate_amount
= operands
[2];
5287 enum machine_mode mode
= GET_MODE (dst
);
5289 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
5292 /* We rotate in place. */
5293 emit_move_insn (dst
, src
);
5295 if (GET_CODE (rotate_amount
) != CONST_INT
)
5297 rtx counter
= gen_reg_rtx (QImode
);
5298 rtx start_label
= gen_label_rtx ();
5299 rtx end_label
= gen_label_rtx ();
5301 /* If the rotate amount is less than or equal to 0,
5302 we go out of the loop. */
5303 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
5304 QImode
, 0, end_label
);
5306 /* Initialize the loop counter. */
5307 emit_move_insn (counter
, rotate_amount
);
5309 emit_label (start_label
);
5311 /* Rotate by one bit. */
5315 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5318 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5321 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5327 /* Decrement the counter by 1. */
5328 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5330 /* If the loop counter is nonzero, we go back to the beginning
5332 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5335 emit_label (end_label
);
5339 /* Rotate by AMOUNT bits. */
5343 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5346 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5349 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5359 /* Output a rotate insn. */
5362 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5364 rtx dst
= operands
[0];
5365 rtx rotate_amount
= operands
[2];
5366 enum shift_mode rotate_mode
;
5367 enum shift_type rotate_type
;
5368 const char *insn_buf
;
5371 enum machine_mode mode
= GET_MODE (dst
);
5373 if (GET_CODE (rotate_amount
) != CONST_INT
)
5379 rotate_mode
= QIshift
;
5382 rotate_mode
= HIshift
;
5385 rotate_mode
= SIshift
;
5394 rotate_type
= SHIFT_ASHIFT
;
5397 rotate_type
= SHIFT_LSHIFTRT
;
5403 amount
= INTVAL (rotate_amount
);
5405 /* Clean up AMOUNT. */
5408 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5409 amount
= GET_MODE_BITSIZE (mode
);
5411 /* Determine the faster direction. After this phase, amount will be
5412 at most a half of GET_MODE_BITSIZE (mode). */
5413 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5415 /* Flip the direction. */
5416 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5418 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5421 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5422 boost up the rotation. */
5423 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5424 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5425 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5426 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5427 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5432 /* This code works on any family. */
5433 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5434 output_asm_insn (insn_buf
, operands
);
5438 /* This code works on the H8/300H and H8S. */
5439 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5440 output_asm_insn (insn_buf
, operands
);
5447 /* Adjust AMOUNT and flip the direction. */
5448 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5450 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5453 /* Output rotate insns. */
5454 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5457 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5459 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5461 for (; amount
>= bits
; amount
-= bits
)
5462 output_asm_insn (insn_buf
, operands
);
5468 /* Compute the length of a rotate insn. */
5471 compute_a_rotate_length (rtx
*operands
)
5473 rtx src
= operands
[1];
5474 rtx amount_rtx
= operands
[2];
5475 enum machine_mode mode
= GET_MODE (src
);
5477 unsigned int length
= 0;
5479 if (GET_CODE (amount_rtx
) != CONST_INT
)
5482 amount
= INTVAL (amount_rtx
);
5484 /* Clean up AMOUNT. */
5487 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5488 amount
= GET_MODE_BITSIZE (mode
);
5490 /* Determine the faster direction. After this phase, amount
5491 will be at most a half of GET_MODE_BITSIZE (mode). */
5492 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5493 /* Flip the direction. */
5494 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5496 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5497 boost up the rotation. */
5498 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5499 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5500 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5501 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5502 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5504 /* Adjust AMOUNT and flip the direction. */
5505 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5509 /* We use 2-bit rotations on the H8S. */
5511 amount
= amount
/ 2 + amount
% 2;
5513 /* The H8/300 uses three insns to rotate one bit, taking 6
5515 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5520 /* Fix the operands of a gen_xxx so that it could become a bit
5524 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5526 /* The bit_operand predicate accepts any memory during RTL generation, but
5527 only 'U' memory afterwards, so if this is a MEM operand, we must force
5528 it to be valid for 'U' by reloading the address. */
5531 ? single_zero_operand (operands
[2], QImode
)
5532 : single_one_operand (operands
[2], QImode
))
5534 /* OK to have a memory dest. */
5535 if (GET_CODE (operands
[0]) == MEM
5536 && !OK_FOR_U (operands
[0]))
5538 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5539 copy_to_mode_reg (Pmode
,
5540 XEXP (operands
[0], 0)));
5541 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5545 if (GET_CODE (operands
[1]) == MEM
5546 && !OK_FOR_U (operands
[1]))
5548 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5549 copy_to_mode_reg (Pmode
,
5550 XEXP (operands
[1], 0)));
5551 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5557 /* Dest and src op must be register. */
5559 operands
[1] = force_reg (QImode
, operands
[1]);
5561 rtx res
= gen_reg_rtx (QImode
);
5565 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5568 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5571 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5576 emit_insn (gen_movqi (operands
[0], res
));
5581 /* Return nonzero if FUNC is an interrupt function as specified
5582 by the "interrupt" attribute. */
5585 h8300_interrupt_function_p (tree func
)
5589 if (TREE_CODE (func
) != FUNCTION_DECL
)
5592 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5593 return a
!= NULL_TREE
;
5596 /* Return nonzero if FUNC is a saveall function as specified by the
5597 "saveall" attribute. */
5600 h8300_saveall_function_p (tree func
)
5604 if (TREE_CODE (func
) != FUNCTION_DECL
)
5607 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5608 return a
!= NULL_TREE
;
5611 /* Return nonzero if FUNC is an OS_Task function as specified
5612 by the "OS_Task" attribute. */
5615 h8300_os_task_function_p (tree func
)
5619 if (TREE_CODE (func
) != FUNCTION_DECL
)
5622 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5623 return a
!= NULL_TREE
;
5626 /* Return nonzero if FUNC is a monitor function as specified
5627 by the "monitor" attribute. */
5630 h8300_monitor_function_p (tree func
)
5634 if (TREE_CODE (func
) != FUNCTION_DECL
)
5637 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5638 return a
!= NULL_TREE
;
5641 /* Return nonzero if FUNC is a function that should be called
5642 through the function vector. */
5645 h8300_funcvec_function_p (tree func
)
5649 if (TREE_CODE (func
) != FUNCTION_DECL
)
5652 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5653 return a
!= NULL_TREE
;
5656 /* Return nonzero if DECL is a variable that's in the eight bit
5660 h8300_eightbit_data_p (tree decl
)
5664 if (TREE_CODE (decl
) != VAR_DECL
)
5667 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5668 return a
!= NULL_TREE
;
5671 /* Return nonzero if DECL is a variable that's in the tiny
5675 h8300_tiny_data_p (tree decl
)
5679 if (TREE_CODE (decl
) != VAR_DECL
)
5682 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5683 return a
!= NULL_TREE
;
5686 /* Generate an 'interrupt_handler' attribute for decls. We convert
5687 all the pragmas to corresponding attributes. */
5690 h8300_insert_attributes (tree node
, tree
*attributes
)
5692 if (TREE_CODE (node
) == FUNCTION_DECL
)
5694 if (pragma_interrupt
)
5696 pragma_interrupt
= 0;
5698 /* Add an 'interrupt_handler' attribute. */
5699 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5707 /* Add an 'saveall' attribute. */
5708 *attributes
= tree_cons (get_identifier ("saveall"),
5714 /* Supported attributes:
5716 interrupt_handler: output a prologue and epilogue suitable for an
5719 saveall: output a prologue and epilogue that saves and restores
5720 all registers except the stack pointer.
5722 function_vector: This function should be called through the
5725 eightbit_data: This variable lives in the 8-bit data area and can
5726 be referenced with 8-bit absolute memory addresses.
5728 tiny_data: This variable lives in the tiny data area and can be
5729 referenced with 16-bit absolute memory references. */
5731 const struct attribute_spec h8300_attribute_table
[] =
5733 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5734 { "interrupt_handler", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5735 { "saveall", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5736 { "OS_Task", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5737 { "monitor", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5738 { "function_vector", 0, 0, true, false, false, h8300_handle_fndecl_attribute
},
5739 { "eightbit_data", 0, 0, true, false, false, h8300_handle_eightbit_data_attribute
},
5740 { "tiny_data", 0, 0, true, false, false, h8300_handle_tiny_data_attribute
},
5741 { NULL
, 0, 0, false, false, false, NULL
}
5745 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5746 struct attribute_spec.handler. */
5748 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5749 tree args ATTRIBUTE_UNUSED
,
5750 int flags ATTRIBUTE_UNUSED
,
5753 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5755 warning ("%qs attribute only applies to functions",
5756 IDENTIFIER_POINTER (name
));
5757 *no_add_attrs
= true;
5763 /* Handle an "eightbit_data" attribute; arguments as in
5764 struct attribute_spec.handler. */
5766 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5767 tree args ATTRIBUTE_UNUSED
,
5768 int flags ATTRIBUTE_UNUSED
,
5773 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5775 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
5779 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
5780 *no_add_attrs
= true;
5786 /* Handle an "tiny_data" attribute; arguments as in
5787 struct attribute_spec.handler. */
5789 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5790 tree args ATTRIBUTE_UNUSED
,
5791 int flags ATTRIBUTE_UNUSED
,
5796 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5798 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
5802 warning ("%qs attribute ignored", IDENTIFIER_POINTER (name
));
5803 *no_add_attrs
= true;
5809 /* Mark function vectors, and various small data objects. */
5812 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5814 int extra_flags
= 0;
5816 default_encode_section_info (decl
, rtl
, first
);
5818 if (TREE_CODE (decl
) == FUNCTION_DECL
5819 && h8300_funcvec_function_p (decl
))
5820 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5821 else if (TREE_CODE (decl
) == VAR_DECL
5822 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5824 if (h8300_eightbit_data_p (decl
))
5825 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5826 else if (first
&& h8300_tiny_data_p (decl
))
5827 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5831 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5834 /* Output a single-bit extraction. */
5837 output_simode_bld (int bild
, rtx operands
[])
5841 /* Clear the destination register. */
5842 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5844 /* Now output the bit load or bit inverse load, and store it in
5847 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5849 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5851 output_asm_insn ("bst\t#0,%w0", operands
);
5855 /* Determine if we can clear the destination first. */
5856 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5857 && REGNO (operands
[0]) != REGNO (operands
[1]));
5860 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5862 /* Output the bit load or bit inverse load. */
5864 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5866 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5869 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5871 /* Perform the bit store. */
5872 output_asm_insn ("rotxl.l\t%S0", operands
);
5879 /* Delayed-branch scheduling is more effective if we have some idea
5880 how long each instruction will be. Use a shorten_branches pass
5881 to get an initial estimate. */
5886 if (flag_delayed_branch
)
5887 shorten_branches (get_insns ());
5890 #ifndef OBJECT_FORMAT_ELF
5892 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5895 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5896 fprintf (asm_out_file
, "\t.section %s\n", name
);
5898 #endif /* ! OBJECT_FORMAT_ELF */
5900 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5901 which is a special case of the 'R' operand. */
5904 h8300_eightbit_constant_address_p (rtx x
)
5906 /* The ranges of the 8-bit area. */
5907 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5908 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5909 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5910 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5911 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5912 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5914 unsigned HOST_WIDE_INT addr
;
5916 /* We accept symbols declared with eightbit_data. */
5917 if (GET_CODE (x
) == SYMBOL_REF
)
5918 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5920 if (GET_CODE (x
) != CONST_INT
)
5926 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5927 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5928 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5931 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5932 on H8/300H and H8S. */
5935 h8300_tiny_constant_address_p (rtx x
)
5937 /* The ranges of the 16-bit area. */
5938 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5939 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5940 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5941 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5942 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5943 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5944 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5945 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5947 unsigned HOST_WIDE_INT addr
;
5949 switch (GET_CODE (x
))
5952 /* In the normal mode, any symbol fits in the 16-bit absolute
5953 address range. We also accept symbols declared with
5955 return (TARGET_NORMAL_MODE
5956 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5960 return (TARGET_NORMAL_MODE
5962 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5964 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5967 return TARGET_NORMAL_MODE
;
5975 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5976 locations that can be accessed as a 16-bit word. */
5979 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5981 HOST_WIDE_INT offset1
, offset2
;
5989 else if (GET_CODE (addr1
) == PLUS
5990 && REG_P (XEXP (addr1
, 0))
5991 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5993 reg1
= XEXP (addr1
, 0);
5994 offset1
= INTVAL (XEXP (addr1
, 1));
6004 else if (GET_CODE (addr2
) == PLUS
6005 && REG_P (XEXP (addr2
, 0))
6006 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
6008 reg2
= XEXP (addr2
, 0);
6009 offset2
= INTVAL (XEXP (addr2
, 1));
6014 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
6015 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
6017 && offset1
+ 1 == offset2
)
6023 /* Return nonzero if we have the same comparison insn as I3 two insns
6024 before I3. I3 is assumed to be a comparison insn. */
6027 same_cmp_preceding_p (rtx i3
)
6031 /* Make sure we have a sequence of three insns. */
6032 i2
= prev_nonnote_insn (i3
);
6035 i1
= prev_nonnote_insn (i2
);
6039 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
6040 && any_condjump_p (i2
) && onlyjump_p (i2
));
6043 /* Return nonzero if we have the same comparison insn as I1 two insns
6044 after I1. I1 is assumed to be a comparison insn. */
6047 same_cmp_following_p (rtx i1
)
6051 /* Make sure we have a sequence of three insns. */
6052 i2
= next_nonnote_insn (i1
);
6055 i3
= next_nonnote_insn (i2
);
6059 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
6060 && any_condjump_p (i2
) && onlyjump_p (i2
));
6063 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
6064 (or pops) N registers. OPERANDS are assumed to be an array of
6068 h8300_regs_ok_for_stm (int n
, rtx operands
[])
6073 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
6074 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
6075 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
6077 return ((REGNO (operands
[0]) == 0
6078 && REGNO (operands
[1]) == 1
6079 && REGNO (operands
[2]) == 2)
6080 || (REGNO (operands
[0]) == 4
6081 && REGNO (operands
[1]) == 5
6082 && REGNO (operands
[2]) == 6));
6085 return (REGNO (operands
[0]) == 0
6086 && REGNO (operands
[1]) == 1
6087 && REGNO (operands
[2]) == 2
6088 && REGNO (operands
[3]) == 3);
6094 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6097 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
6098 unsigned int new_reg
)
6100 /* Interrupt functions can only use registers that have already been
6101 saved by the prologue, even if they would normally be
6104 if (h8300_current_function_interrupt_function_p ()
6105 && !regs_ever_live
[new_reg
])
6111 /* Return nonzero if X is a legitimate constant. */
6114 h8300_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
6119 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
6122 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
6124 /* Strip off SUBREG if any. */
6125 if (GET_CODE (x
) == SUBREG
)
6130 ? REG_OK_FOR_BASE_STRICT_P (x
)
6131 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
6134 /* Return nozero if X is a legitimate address. On the H8/300, a
6135 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
6136 CONSTANT_ADDRESS. */
6139 h8300_legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
6141 /* The register indirect addresses like @er0 is always valid. */
6142 if (h8300_rtx_ok_for_base_p (x
, strict
))
6145 if (CONSTANT_ADDRESS_P (x
))
6149 && ( GET_CODE (x
) == PRE_INC
6150 || GET_CODE (x
) == PRE_DEC
6151 || GET_CODE (x
) == POST_INC
6152 || GET_CODE (x
) == POST_DEC
)
6153 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
6156 if (GET_CODE (x
) == PLUS
6157 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
6158 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
6165 /* Worker function for HARD_REGNO_NREGS.
6167 We pretend the MAC register is 32bits -- we don't have any data
6168 types on the H8 series to handle more than 32bits. */
6171 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, enum machine_mode mode
)
6173 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6176 /* Worker function for HARD_REGNO_MODE_OK. */
6179 h8300_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
6182 /* If an even reg, then anything goes. Otherwise the mode must be
6184 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
6186 /* MAC register can only be of SImode. Otherwise, anything
6188 return regno
== MAC_REG
? mode
== SImode
: 1;
6191 /* Perform target dependent optabs initialization. */
6193 h8300_init_libfuncs (void)
6195 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
6196 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
6197 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
6198 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
6199 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
6202 /* Worker function for TARGET_RETURN_IN_MEMORY. */
6205 h8300_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
6207 return (TYPE_MODE (type
) == BLKmode
6208 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
6211 /* Initialize the GCC target structure. */
6212 #undef TARGET_ATTRIBUTE_TABLE
6213 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6215 #undef TARGET_ASM_ALIGNED_HI_OP
6216 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6218 #undef TARGET_ASM_FILE_START
6219 #define TARGET_ASM_FILE_START h8300_file_start
6220 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6221 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6223 #undef TARGET_ASM_FILE_END
6224 #define TARGET_ASM_FILE_END h8300_file_end
6226 #undef TARGET_ENCODE_SECTION_INFO
6227 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6229 #undef TARGET_INSERT_ATTRIBUTES
6230 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6232 #undef TARGET_RTX_COSTS
6233 #define TARGET_RTX_COSTS h8300_rtx_costs
6235 #undef TARGET_INIT_LIBFUNCS
6236 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6238 #undef TARGET_RETURN_IN_MEMORY
6239 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6241 #undef TARGET_MACHINE_DEPENDENT_REORG
6242 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6244 struct gcc_target targetm
= TARGET_INITIALIZER
;