1 /* Subroutines for insn-output.c for Hitachi H8/300.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
40 /* Forward declarations. */
41 void print_operand_address ();
44 static int h8300_interrupt_function_p
PROTO ((tree
));
45 static int h8300_monitor_function_p
PROTO ((tree
));
46 static int h8300_os_task_function_p
PROTO ((tree
));
48 /* CPU_TYPE, says what cpu we're compiling for. */
51 /* True if the current function is an interrupt handler
52 (either via #pragma or an attribute specification). */
53 int interrupt_handler
;
55 /* True if the current fucntion is an OS Task
56 (via an attribute specification). */
59 /* True if the current function is a monitor
60 (via an attribute specification). */
63 /* True if a #pragma saveall has been seen for the current function. */
66 static char *names_big
[] =
67 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7"};
69 static char *names_extended
[] =
70 {"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"};
72 static char *names_upper_extended
[] =
73 {"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"};
75 /* Points to one of the above. */
76 /* ??? The above could be put in an array indexed by CPU_TYPE. */
79 /* Various operations needed by the following, indexed by CPU_TYPE. */
81 static char *h8_push_ops
[2] =
83 static char *h8_pop_ops
[2] =
85 static char *h8_mov_ops
[2] =
88 char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
90 /* Initialize various cpu specific globals at start up. */
97 cpu_type
= (int) CPU_H8300
;
98 h8_reg_names
= names_big
;
102 cpu_type
= (int) CPU_H8300H
;
103 h8_reg_names
= names_extended
;
105 h8_push_op
= h8_push_ops
[cpu_type
];
106 h8_pop_op
= h8_pop_ops
[cpu_type
];
107 h8_mov_op
= h8_mov_ops
[cpu_type
];
115 static char *names_small
[] =
116 {"r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
117 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"};
119 return names_small
[REGNO (x
) * 2 + b
];
122 /* REGNO must be saved/restored across calls if this macro is true. */
124 #define WORD_REG_USED(regno) \
128 || (regno == FRAME_POINTER_REGNUM && regs_ever_live[regno]) \
129 || (regs_ever_live[regno] & !call_used_regs[regno])))
131 /* Output assembly language to FILE for the operation OP with operand size
132 SIZE to adjust the stack pointer. */
135 dosize (file
, op
, size
)
140 /* On the h8300h, for sizes <= 8 bytes it is as good or
141 better to use adds/subs insns rather than add.l/sub.l
142 with an immediate value. */
143 if (size
> 4 && size
<= 8 && TARGET_H8300H
)
145 /* Crank the size down to <= 4 */
146 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 4);
155 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 4);
160 fprintf (file
, "\t%ss\t#%d,sp\n", op
, 2);
162 /* Fall through... */
165 fprintf (file
, "\t%ss\t#%d,sp\n", op
, size
);
172 fprintf (file
, "\tmov.w\t#%d,r3\n\t%s.w\tr3,sp\n", size
, op
);
174 fprintf (file
, "\t%s\t#%d,sp\n", op
, size
);
180 /* Output assembly language code for the function prologue. */
181 static int push_order
[FIRST_PSEUDO_REGISTER
] =
182 {6, 5, 4, 3, 2, 1, 0, -1, -1};
183 static int pop_order
[FIRST_PSEUDO_REGISTER
] =
184 {0, 1, 2, 3, 4, 5, 6, -1, -1};
186 /* This is what the stack looks like after the prolog of
187 a function with a frame has been set up:
193 <saved registers> <- sp
195 This is what the stack looks like after the prolog of
196 a function which doesn't have a frame:
201 <saved registers> <- sp
205 function_prologue (file
, size
)
209 register int mask
= 0;
210 int fsize
= (size
+ STACK_BOUNDARY
/ 8 - 1) & -STACK_BOUNDARY
/ 8;
213 /* Note a function with the interrupt attribute and set interrupt_handler
215 if (h8300_interrupt_function_p (current_function_decl
))
216 interrupt_handler
= 1;
218 /* If the current function has the OS_Task attribute set, then
219 we have a naked prologue. */
220 if (h8300_os_task_function_p (current_function_decl
))
222 fprintf (file
, ";OS_Task prologue\n");
227 if (h8300_monitor_function_p (current_function_decl
))
229 /* My understanding of monitor functions is they act just
230 like interrupt functions, except the prologue must
232 fprintf (file
, ";monitor prologue\n");
233 interrupt_handler
= 1;
237 fprintf (file
, "\tsubs\t#2,sp\n");
238 fprintf (file
, "\tpush\tr0\n");
239 fprintf (file
, "\tstc\tccr,r0l\n");
240 fprintf (file
, "\torc\t#128,ccr\n");
241 fprintf (file
, "\tmov.b\tr0l,@(4,sp)\n");
243 else if (TARGET_H8300H
)
245 fprintf (file
, "\tpush\ter0\n");
246 fprintf (file
, "\tstc\tccr,r0l\n");
247 fprintf (file
, "\torc\t#128,ccr\n");
248 fprintf (file
, "\tmov.b\tr0l,@(4,sp)\n");
252 if (frame_pointer_needed
)
255 fprintf (file
, "\t%s\t%s\n", h8_push_op
,
256 h8_reg_names
[FRAME_POINTER_REGNUM
]);
257 fprintf (file
, "\t%s\t%s,%s\n", h8_mov_op
,
258 h8_reg_names
[STACK_POINTER_REGNUM
],
259 h8_reg_names
[FRAME_POINTER_REGNUM
]);
261 /* leave room for locals */
262 dosize (file
, "sub", fsize
);
264 /* Push the rest of the registers */
265 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
267 int regno
= push_order
[idx
];
269 if (regno
>= 0 && WORD_REG_USED (regno
) && regno
!= FRAME_POINTER_REGNUM
)
270 fprintf (file
, "\t%s\t%s\n", h8_push_op
, h8_reg_names
[regno
]);
275 dosize (file
, "sub", fsize
);
276 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
278 int regno
= push_order
[idx
];
280 if (regno
>= 0 && WORD_REG_USED (regno
))
281 fprintf (file
, "\t%s\t%s\n", h8_push_op
, h8_reg_names
[regno
]);
286 /* Output assembly language code for the function epilogue. */
289 function_epilogue (file
, size
)
294 register int mask
= 0;
295 int fsize
= (size
+ STACK_BOUNDARY
/ 8 - 1) & -STACK_BOUNDARY
/ 8;
299 rtx insn
= get_last_insn ();
303 /* OS_Task epilogues are nearly naked -- they just have an
305 fprintf (file
, ";OS_task epilogue\n");
306 fprintf (file
, "\trts\n");
310 /* monitor epilogues are the same as interrupt function epilogues.
311 Just make a note that we're in an monitor epilogue. */
313 fprintf(file
, ";monitor epilogue\n");
315 /* If the last insn was a BARRIER, we don't have to write any code. */
316 if (GET_CODE (insn
) == NOTE
)
317 insn
= prev_nonnote_insn (insn
);
318 if (insn
&& GET_CODE (insn
) == BARRIER
)
323 if (frame_pointer_needed
)
325 /* Pop saved registers */
326 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
328 regno
= pop_order
[idx
];
329 if (regno
>= 0 && regno
!= FRAME_POINTER_REGNUM
&& WORD_REG_USED (regno
))
330 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[regno
]);
332 /* deallocate locals */
333 dosize (file
, "add", fsize
);
334 /* pop frame pointer */
335 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[FRAME_POINTER_REGNUM
]);
339 /* pop saved registers */
340 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
342 regno
= pop_order
[idx
];
343 if (regno
>= 0 && WORD_REG_USED (regno
))
344 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[regno
]);
346 /* deallocate locals */
347 dosize (file
, "add", fsize
);
350 /* If this is a monitor function, there is one register still left on
353 fprintf (file
, "\t%s\t%s\n", h8_pop_op
, h8_reg_names
[0]);
355 if (interrupt_handler
)
356 fprintf (file
, "\trte\n");
358 fprintf (file
, "\trts\n");
361 interrupt_handler
= 0;
367 /* Output assembly code for the start of the file. */
369 asm_file_start (file
)
372 fprintf (file
, ";\tGCC For the Hitachi H8/300\n");
373 fprintf (file
, ";\tBy Hitachi America Ltd and Cygnus Support\n");
374 fprintf (file
, ";\trelease F-1\n");
376 fprintf (file
, "; -O%d\n", optimize
);
378 fprintf (file
, "\n\t.h8300h\n");
380 fprintf (file
, "\n\n");
381 output_file_directive (file
, main_input_filename
);
384 /* Output assembly language code for the end of file. */
390 fprintf (file
, "\t.end\n");
393 /* Return true if VALUE is a valid constant for constraint 'P'.
394 IE: VALUE is a power of two <= 2**15. */
397 small_power_of_two (value
)
423 /* Return true if VALUE is a valid constant for constraint 'O', which
424 means that the constant would be ok to use as a bit for a bclr
431 return small_power_of_two ((~value
) & 0xff);
434 /* Return true is OP is a valid source operand for an integer move
438 general_operand_src (op
, mode
)
440 enum machine_mode mode
;
442 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
444 return general_operand (op
, mode
);
447 /* Return true if OP is a valid destination operand for an integer move
451 general_operand_dst (op
, mode
)
453 enum machine_mode mode
;
455 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == PRE_DEC
)
457 return general_operand (op
, mode
);
460 /* Return true if OP is a const valid for a bit clear instruction. */
463 o_operand (operand
, mode
)
465 enum machine_mode mode
;
467 return (GET_CODE (operand
) == CONST_INT
468 && CONST_OK_FOR_O (INTVAL (operand
)));
471 /* Return true if OP is a const valid for a bit set or bit xor instruction. */
474 p_operand (operand
, mode
)
476 enum machine_mode mode
;
478 return (GET_CODE (operand
) == CONST_INT
479 && CONST_OK_FOR_P (INTVAL (operand
)));
482 /* Return true if OP is a valid call operand. */
485 call_insn_operand (op
, mode
)
487 enum machine_mode mode
;
489 if (GET_CODE (op
) == MEM
)
491 rtx inside
= XEXP (op
, 0);
492 if (register_operand (inside
, Pmode
))
494 if (CONSTANT_ADDRESS_P (inside
))
501 adds_subs_operand (op
, mode
)
503 enum machine_mode mode
;
505 if (GET_CODE (op
) == CONST_INT
)
507 if (INTVAL (op
) <= 4 && INTVAL (op
) >= 0)
509 if (INTVAL (op
) >= -4 && INTVAL (op
) <= 0)
513 && (INTVAL (op
) <= 8 && INTVAL (op
) >= 0))
517 && (INTVAL (op
) >= -8 && INTVAL (op
) <= 0))
523 /* Return nonzero if op is an adds/subs operand which only requires
524 one insn to implement. It is assumed that OP is already an adds/subs
527 one_insn_adds_subs_operand (op
, mode
)
529 enum machine_mode mode
;
531 int val
= INTVAL (op
);
533 if (val
== 1 || val
== -1
534 || val
== 2 || val
== -2
536 && (val
== 4 || val
== -4)))
542 output_adds_subs (operands
)
545 int val
= INTVAL (operands
[2]);
547 /* First get the value into the range -4..4 inclusive.
549 The only way it can be out of this range is when TARGET_H8300H
550 is true, thus it is safe to use adds #4 and subs #4. */
553 output_asm_insn ("adds #4,%A0", operands
);
559 output_asm_insn ("subs #4,%A0", operands
);
563 /* Handle case were val == 4 or val == -4 and we're compiling
564 for TARGET_H8300H. */
565 if (TARGET_H8300H
&& val
== 4)
566 return "adds #4,%A0";
568 if (TARGET_H8300H
&& val
== -4)
569 return "subs #4,%A0";
573 output_asm_insn ("adds #2,%A0", operands
);
579 output_asm_insn ("subs #2,%A0", operands
);
583 /* val should be one or two now. */
585 return "adds #2,%A0";
588 return "subs #2,%A0";
590 /* val should be one now. */
592 return "adds #1,%A0";
595 return "subs #1,%A0";
597 /* In theory, this can't happen. */
601 /* Return true if OP is a valid call operand, and OP represents
602 an operand for a small call (4 bytes instead of 6 bytes). */
605 small_call_insn_operand (op
, mode
)
607 enum machine_mode mode
;
609 if (GET_CODE (op
) == MEM
)
611 rtx inside
= XEXP (op
, 0);
613 /* Register indirect is a small call. */
614 if (register_operand (inside
, Pmode
))
617 /* A call through the function vector is a small
619 if (GET_CODE (inside
) == SYMBOL_REF
620 && SYMBOL_REF_FLAG (inside
))
623 /* Otherwise it's a large call. */
627 /* Return true if OP is a valid jump operand. */
630 jump_address_operand (op
, mode
)
632 enum machine_mode mode
;
634 if (GET_CODE (op
) == REG
)
635 return mode
== Pmode
;
637 if (GET_CODE (op
) == MEM
)
639 rtx inside
= XEXP (op
, 0);
640 if (register_operand (inside
, Pmode
))
642 if (CONSTANT_ADDRESS_P (inside
))
648 /* Recognize valid operands for bitfield instructions. */
650 extern int rtx_equal_function_value_matters
;
653 bit_operand (op
, mode
)
655 enum machine_mode mode
;
657 /* We can except any general operand, expept that MEM operands must
658 be limited to those that use addresses valid for the 'U' constraint. */
659 if (!general_operand (op
, mode
))
662 /* Accept any mem during RTL generation. Otherwise, the code that does
663 insv and extzv will think that we can not handle memory. However,
664 to avoid reload problems, we only accept 'U' MEM operands after RTL
665 generation. This means that any named pattern which uses this predicate
666 must force its operands to match 'U' before emitting RTL. */
668 if (GET_CODE (op
) == REG
)
670 if (GET_CODE (op
) == SUBREG
)
672 if (!rtx_equal_function_value_matters
)
674 /* We're building rtl */
675 return GET_CODE (op
) == MEM
;
679 return (GET_CODE (op
) == MEM
680 && EXTRA_CONSTRAINT (op
, 'U'));
685 bit_memory_operand (op
, mode
)
687 enum machine_mode mode
;
689 return (GET_CODE (op
) == MEM
690 && EXTRA_CONSTRAINT (op
, 'U'));
693 /* Recognize valid operators for bit test. */
696 eq_operator (x
, mode
)
698 enum machine_mode mode
;
700 return (GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
);
703 /* Handle machine specific pragmas for compatibility with existing
704 compilers for the H8/300.
706 pragma saveall generates prolog/epilog code which saves and
707 restores all the registers on function entry.
709 pragma interrupt saves and restores all registers, and exits with
710 an rte instruction rather than an rts. A pointer to a function
711 with this attribute may be safely used in an interrupt vector. */
714 handle_pragma (file
, t
)
719 register char *pname
;
721 if (TREE_CODE (t
) != IDENTIFIER_NODE
)
724 pname
= IDENTIFIER_POINTER (t
);
725 if (strcmp (pname
, "interrupt") == 0)
726 interrupt_handler
= retval
= 1;
727 else if (strcmp (pname
, "saveall") == 0)
728 pragma_saveall
= retval
= 1;
733 /* If the next arg with MODE and TYPE is to be passed in a register, return
734 the rtx to represent where it is passed. CUM represents the state after
735 the last argument. NAMED is not used. */
737 static char *hand_list
[] =
757 /* Return an RTX to represent where a value with mode MODE will be returned
758 from a function. If the result is 0, the argument is pushed. */
761 function_arg (cum
, mode
, type
, named
)
762 CUMULATIVE_ARGS
*cum
;
763 enum machine_mode mode
;
771 /* Never pass unnamed arguments in registers. */
775 /* Pass 3 regs worth of data in regs when user asked on the command line. */
776 if (TARGET_QUICKCALL
)
779 /* If calling hand written assembler, use 4 regs of args. */
785 fname
= XSTR (cum
->libcall
, 0);
787 /* See if this libcall is one of the hand coded ones. */
789 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
801 size
= int_size_in_bytes (type
);
803 size
= GET_MODE_SIZE (mode
);
805 if (size
+ cum
->nbytes
> regpass
* UNITS_PER_WORD
)
811 switch (cum
->nbytes
/ UNITS_PER_WORD
)
814 result
= gen_rtx (REG
, mode
, 0);
817 result
= gen_rtx (REG
, mode
, 1);
820 result
= gen_rtx (REG
, mode
, 2);
823 result
= gen_rtx (REG
, mode
, 3);
834 /* Return the cost of the rtx R with code CODE. */
875 /* Documentation for the machine specific operand escapes:
877 'A' print rn in h8/300 mode, erN in H8/300H mode
878 'C' print (operand - 2).
879 'E' like s but negative.
880 'F' like t but negative.
881 'G' constant just the negative
882 'L' fake label, changed after used twice.
883 'M' turn a 'M' constant into its negative mod 2.
884 'P' if operand is incing/decing sp, print .w, otherwise .b.
885 'R' print operand as a byte:8 address if appropriate, else fall back to
887 'S' print operand as a long word
888 'T' print operand as a word
889 'U' if operand is incing/decing sp, print l, otherwise nothing.
890 'V' find the set bit, and print its number.
891 'W' find the clear bit, and print its number.
892 'X' print operand as a byte
893 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
894 If this operand isn't a register, fall back to 'R' handling.
896 'b' print the bit opcode
897 'c' print the ibit opcode
898 'd' bcc if EQ, bcs if NE
899 'e' first word of 32 bit value - if reg, then least reg. if mem
900 then least. if const then most sig word
901 'f' second word of 32 bit value - if reg, then biggest reg. if mem
902 then +2. if const then least sig word
903 'g' bcs if EQ, bcc if NE
904 'j' print operand as condition code.
905 'k' print operand as reverse condition code.
906 's' print as low byte of 16 bit value
907 't' print as high byte of 16 bit value
908 'w' print as low byte of 32 bit value
909 'x' print as 2nd byte of 32 bit value
910 'y' print as 3rd byte of 32 bit value
911 'z' print as msb of 32 bit value
914 /* Return assembly language string which identifies a comparison type. */
947 /* Print operand X using operand code CODE to assembly language output file
951 print_operand (file
, x
, code
)
956 /* This is used to general unique labels for the 'L' code. */
957 static int lab
= 1000;
959 /* This is used for communication between the 'P' and 'U' codes. */
962 /* This is used for communication between codes V,W,Z and Y. */
968 if (GET_CODE (x
) == REG
)
969 fprintf (file
, "%s", h8_reg_names
[REGNO (x
)]);
974 fprintf (file
, "#%d", INTVAL (x
) - 2);
977 switch (GET_CODE (x
))
980 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
983 fprintf (file
, "#%d", (-INTVAL (x
)) & 0xff);
990 switch (GET_CODE (x
))
993 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
996 fprintf (file
, "#%d", ((-INTVAL (x
)) & 0xff00) >> 8);
1003 if (GET_CODE (x
) != CONST_INT
)
1005 fprintf (file
, "#%d", 0xff & (-INTVAL (x
)));
1008 /* 'L' must always be used twice in a single pattern. It generates
1009 the same label twice, and then will generate a unique label the
1010 next time it is used. */
1011 asm_fprintf (file
, "tl%d", (lab
++) / 2);
1014 /* For 3/-3 and 4/-4, the other 2 is handled separately. */
1021 fprintf (file
, "#2");
1027 fprintf (file
, "#1");
1034 if (REGNO (XEXP (XEXP (x
, 0), 0)) == STACK_POINTER_REGNUM
)
1037 fprintf (file
, ".w");
1042 fprintf (file
, ".b");
1046 if (GET_CODE (x
) == REG
)
1047 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1052 if (GET_CODE (x
) == REG
)
1053 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1058 fprintf (file
, "%s%s", names_big
[REGNO (x
)], last_p
);
1061 bitint
= exact_log2 (INTVAL (x
));
1064 fprintf (file
, "#%d", bitint
& 7);
1067 bitint
= exact_log2 ((~INTVAL (x
)) & 0xff);
1070 fprintf (file
, "#%d", bitint
& 7);
1074 if (GET_CODE (x
) == REG
)
1075 fprintf (file
, "%s", byte_reg (x
, 0));
1082 if (GET_CODE (x
) == REG
)
1083 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1085 print_operand (file
, x
, 'R');
1089 bitint
= INTVAL (x
);
1090 fprintf (file
, "#%d", bitint
& 7);
1093 switch (GET_CODE (x
))
1096 fprintf (file
, "bor");
1099 fprintf (file
, "bxor");
1102 fprintf (file
, "band");
1107 switch (GET_CODE (x
))
1110 fprintf (file
, "bior");
1113 fprintf (file
, "bixor");
1116 fprintf (file
, "biand");
1121 switch (GET_CODE (x
))
1124 fprintf (file
, "bcc");
1127 fprintf (file
, "bcs");
1134 switch (GET_CODE (x
))
1138 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1140 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1143 x
= adj_offsettable_operand (x
, 0);
1144 print_operand (file
, x
, 0);
1147 fprintf (file
, "#%d", ((INTVAL (x
) >> 16) & 0xffff));
1155 switch (GET_CODE (x
))
1159 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1161 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1164 x
= adj_offsettable_operand (x
, 2);
1165 print_operand (file
, x
, 0);
1168 fprintf (file
, "#%d", INTVAL (x
) & 0xffff);
1175 switch (GET_CODE (x
))
1178 fprintf (file
, "bcc");
1181 fprintf (file
, "bcs");
1188 asm_fprintf (file
, cond_string (GET_CODE (x
)));
1191 asm_fprintf (file
, cond_string (reverse_condition (GET_CODE (x
))));
1194 if (GET_CODE (x
) == CONST_INT
)
1195 fprintf (file
, "#%d", (INTVAL (x
)) & 0xff);
1197 fprintf (file
, "%s", byte_reg (x
, 0));
1200 if (GET_CODE (x
) == CONST_INT
)
1201 fprintf (file
, "#%d", (INTVAL (x
) >> 8) & 0xff);
1203 fprintf (file
, "%s", byte_reg (x
, 1));
1206 if (GET_CODE (x
) != CONST_INT
)
1208 fprintf (file
, "%d", INTVAL (x
));
1211 if (GET_CODE (x
) == CONST_INT
)
1212 fprintf (file
, "#%d", INTVAL (x
) & 0xff);
1214 fprintf (file
, "%s", byte_reg (x
, TARGET_H8300
? 2 : 0));
1217 if (GET_CODE (x
) == CONST_INT
)
1218 fprintf (file
, "#%d", (INTVAL (x
) >> 8) & 0xff);
1220 fprintf (file
, "%s", byte_reg (x
, TARGET_H8300
? 3 : 1));
1223 if (GET_CODE (x
) == CONST_INT
)
1224 fprintf (file
, "#%d", (INTVAL (x
) >> 16) & 0xff);
1226 fprintf (file
, "%s", byte_reg (x
, 0));
1229 if (GET_CODE (x
) == CONST_INT
)
1230 fprintf (file
, "#%d", (INTVAL (x
) >> 24) & 0xff);
1232 fprintf (file
, "%s", byte_reg (x
, 1));
1237 switch (GET_CODE (x
))
1240 switch (GET_MODE (x
))
1243 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1244 fprintf (file
, "%s", byte_reg (x
, 0));
1245 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1246 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1250 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1254 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1262 fprintf (file
, "@");
1263 output_address (XEXP (x
, 0));
1265 /* If this is an 'R' operand (reference into the 8-bit area),
1266 then specify a symbolic address as "foo:8". */
1268 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1269 && SYMBOL_REF_FLAG (XEXP (x
, 0)))
1270 fprintf (file
, ":8");
1271 if (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
1272 && TINY_DATA_NAME_P (XSTR (XEXP (x
, 0), 0)))
1273 fprintf (file
, ":16");
1280 fprintf (file
, "#");
1281 print_operand_address (file
, x
);
1287 /* Output assembly language output for the address ADDR to FILE. */
1290 print_operand_address (file
, addr
)
1294 switch (GET_CODE (addr
))
1297 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1301 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1305 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1309 fprintf (file
, "(");
1310 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1313 print_operand_address (file
, XEXP (addr
, 1));
1314 fprintf (file
, ",");
1315 print_operand_address (file
, XEXP (addr
, 0));
1320 print_operand_address (file
, XEXP (addr
, 0));
1321 fprintf (file
, "+");
1322 print_operand_address (file
, XEXP (addr
, 1));
1324 fprintf (file
, ")");
1329 /* Since the h8/300 only has 16 bit pointers, negative values are also
1330 those >= 32768. This happens for example with pointer minus a
1331 constant. We don't want to turn (char *p - 2) into
1332 (char *p + 65534) because loop unrolling can build upon this
1333 (IE: char *p + 131068). */
1334 int n
= INTVAL (addr
);
1336 n
= (int) (short) n
;
1338 /* ??? Why the special case for -ve values? */
1339 fprintf (file
, "-%d", -n
);
1341 fprintf (file
, "%d", n
);
1346 output_addr_const (file
, addr
);
1351 /* Output all insn addresses and their sizes into the assembly language
1352 output file. This is helpful for debugging whether the length attributes
1353 in the md file are correct. This is not meant to be a user selectable
1357 final_prescan_insn (insn
, operand
, num_operands
)
1361 /* This holds the last insn address. */
1362 static int last_insn_address
= 0;
1364 int uid
= INSN_UID (insn
);
1366 if (TARGET_RTL_DUMP
)
1368 fprintf (asm_out_file
, "\n****************");
1369 print_rtl (asm_out_file
, PATTERN (insn
));
1370 fprintf (asm_out_file
, "\n");
1373 if (TARGET_ADDRESSES
)
1375 fprintf (asm_out_file
, "; 0x%x %d\n", insn_addresses
[uid
],
1376 insn_addresses
[uid
] - last_insn_address
);
1377 last_insn_address
= insn_addresses
[uid
];
1381 /* Prepare for an SI sized move. */
1387 rtx src
= operands
[1];
1388 rtx dst
= operands
[0];
1389 if (!reload_in_progress
&& !reload_completed
)
1391 if (!register_operand (dst
, GET_MODE (dst
)))
1393 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1394 emit_move_insn (tmp
, src
);
1401 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1402 Define the offset between two registers, one to be eliminated, and the other
1403 its replacement, at the start of a routine. */
1406 initial_offset (from
, to
)
1410 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1411 offset
= UNITS_PER_WORD
+ frame_pointer_needed
* UNITS_PER_WORD
;
1416 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1417 if ((regs_ever_live
[regno
]
1418 && (!call_used_regs
[regno
] || regno
== FRAME_POINTER_REGNUM
)))
1419 offset
+= UNITS_PER_WORD
;
1421 /* See the comments for get_frame_size. We need to round it up to
1424 offset
+= ((get_frame_size () + STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
1425 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
1427 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1428 offset
+= UNITS_PER_WORD
; /* Skip saved PC */
1433 /* Update the condition code from the insn. */
1436 notice_update_cc (body
, insn
)
1440 switch (get_attr_cc (insn
))
1443 /* Insn does not affect CC at all. */
1447 /* Insn does not change CC, but the 0'th operand has been changed. */
1448 if (cc_status
.value1
!= 0
1449 && reg_overlap_mentioned_p (recog_operand
[0], cc_status
.value1
))
1450 cc_status
.value1
= 0;
1454 /* Insn sets the Z,N flags of CC to recog_operand[0].
1455 V is always set to 0. C may or may not be set to 0 but that's ok
1456 because alter_cond will change tests to use EQ/NE. */
1458 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
1459 cc_status
.value1
= recog_operand
[0];
1463 /* Insn sets the Z,N flags of CC to recog_operand[0].
1464 The V flag is unusable. The C flag may or may not be known but
1465 that's ok because alter_cond will change tests to use EQ/NE. */
1467 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
1468 cc_status
.value1
= recog_operand
[0];
1472 /* The insn is a compare instruction. */
1474 cc_status
.value1
= SET_SRC (body
);
1478 /* Insn doesn't leave CC in a usable state. */
1484 /* Return 1 if a previous compare needs to be re-issued. This will happen
1485 if the compare was deleted because the previous insn set it, but the
1486 branch needs CC flags not set.
1488 OP is the comparison being performed. */
1491 restore_compare_p (op
)
1494 switch (GET_CODE (op
))
1503 if (cc_status
.flags
& CC_OVERFLOW_UNUSABLE
)
1510 /* If the carry flag isn't usable, the test should have been changed
1512 if (cc_status
.flags
& CC_NO_CARRY
)
1522 /* Recognize valid operators for bit instructions */
1525 bit_operator (x
, mode
)
1527 enum machine_mode mode
;
1529 enum rtx_code code
= GET_CODE (x
);
1538 We devote a fair bit of code to getting efficient shifts since we can only
1539 shift one bit at a time. See the .md file for more comments.
1541 Here are some thoughts on what the absolutely positively best code is.
1542 "Best" here means some rational trade-off between code size and speed,
1543 where speed is more preferred but not at the expense of generating 20 insns.
1545 H8/300 QImode shifts
1546 1-4 - do them inline
1547 5-6 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1549 7 - ASHIFT | LSHIFTRT: rotate, mask off other bits
1550 ASHIFTRT: shll, subx (propagate carry bit to all bits)
1552 H8/300 HImode shifts
1553 1-4 - do them inline
1555 7 - shift other way once, move byte into place, move carry bit into place
1556 8 - move byte, zero (ASHIFT | LSHIFTRT) or sign extend other (ASHIFTRT)
1557 9 - inline shift 1-4, move byte, set other byte
1558 13-14 - ASHIFT | LSHIFTRT: rotate 3/2, mask, move byte, set other byte to 0
1560 15 - ASHIFT | LSHIFTRT: rotate 1, mask, move byte, set other byte to 0
1561 - ASHIFTRT: shll, subx, set other byte
1563 H8/300 SImode shifts
1564 1-2 - do them inline
1566 7 - shift other way once, move bytes into place,
1567 move carry into place (possibly with sign extension)
1568 8 - move bytes into place, zero or sign extend other
1570 15 - shift other way once, move word into place, move carry into place
1571 16 - move word, zero or sign extend other
1573 24 - move bytes into place, zero or sign extend other
1575 28-30 - ASHIFT | LSHIFTRT: rotate top byte, mask, move byte into place,
1578 31 - ASHIFT | LSHIFTRT: rotate top byte, mask, byte byte into place,
1580 ASHIFTRT: shll top byte, subx, copy to other bytes
1582 H8/300H QImode shifts
1585 H8/300H HImode shifts
1588 H8/300H SImode shifts
1589 (These are complicated by the fact that we don't have byte level access to
1591 A word is: bytes 3,2,1,0 (msb -> lsb), word 1,0 (msw -> lsw)
1592 1-4 - do them inline
1594 15 - shift other way once, move word into place, move carry into place
1595 (with sign extension for ASHIFTRT)
1596 16 - move word into place, zero or sign extend other
1598 24 - ASHIFT: move byte 0(msb) to byte 1, zero byte 0,
1599 move word 0 to word 1, zero word 0
1600 LSHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1601 zero word 1, zero byte 1
1602 ASHIFTRT: move word 1 to word 0, move byte 1 to byte 0,
1603 sign extend byte 0, sign extend word 0
1604 25-27 - either loop, or
1605 do 24 bit shift, inline rest
1606 28-30 - ASHIFT: rotate 4/3/2, mask
1607 LSHIFTRT: rotate 4/3/2, mask
1609 31 - shll, subx byte 0, sign extend byte 0, sign extend word 0
1613 All of these haven't been implemented. I've just documented them and
1614 provided hooks so they can be.
1618 nshift_operator (x
, mode
)
1620 enum machine_mode mode
;
1622 switch (GET_CODE (x
))
1634 /* Called from the .md file to emit code to do shifts.
1635 Returns a boolean indicating success
1636 (currently this is always TRUE). */
1639 expand_a_shift (mode
, code
, operands
)
1640 enum machine_mode mode
;
1644 emit_move_insn (operands
[0], operands
[1]);
1646 /* need a loop to get all the bits we want - we generate the
1647 code at emit time, but need to allocate a scratch reg now */
1650 (PARALLEL
, VOIDmode
,
1652 gen_rtx (SET
, VOIDmode
, operands
[0],
1653 gen_rtx (code
, mode
, operands
[0], operands
[2])),
1654 gen_rtx (CLOBBER
, VOIDmode
, gen_rtx (SCRATCH
, QImode
, 0)))));
1659 /* Shift algorithm determination.
1661 There are various ways of doing a shift:
1662 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1664 SHIFT_ROT_AND: If the amount is large but close to either end, rotate the
1665 necessary bits into position and then set the rest to zero.
1666 SHIFT_SPECIAL: Hand crafted assembler.
1667 SHIFT_LOOP: If the above methods fail, just loop. */
1678 /* Symbols of the various shifts which can be used as indices. */
1682 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
1685 /* Symbols of the various modes which can be used as indices. */
1689 QIshift
, HIshift
, SIshift
1692 /* For single bit shift insns, record assembler and what bits of the
1693 condition code are valid afterwards (represented as various CC_FOO
1694 bits, 0 means CC isn't left in a usable state). */
1702 /* Assembler instruction shift table.
1704 These tables are used to look up the basic shifts.
1705 They are indexed by cpu, shift_type, and mode.
1708 static const struct shift_insn shift_one
[2][3][3] =
1714 { "shll %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1715 { "add.w %T0,%T0\t; shal.w", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1716 { "add.w %f0,%f0\t; shal.l\n\taddx %y0,%y0\n\taddx %z0,%z0\t; end shal.l", 0 }
1718 /* SHIFT_LSHIFTRT */
1720 { "shlr %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1721 { "shlr %t0\t; shlr.w\n\trotxr %s0\t; end shlr.w", 0 },
1722 { "shlr %z0\t; shlr.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shlr.l", 0 }
1724 /* SHIFT_ASHIFTRT */
1726 { "shar %X0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1727 { "shar %t0\t; shar.w\n\trotxr %s0\t; end shar.w", 0 },
1728 { "shar %z0\t; shar.l\n\trotxr %y0\n\trotxr %x0\n\trotxr %w0\t; end shar.l", 0 }
1735 { "shll.b %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1736 { "shll.w %T0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1737 { "shll.l %S0", CC_OVERFLOW_0
| CC_NO_CARRY
}
1739 /* SHIFT_LSHIFTRT */
1741 { "shlr.b %X0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1742 { "shlr.w %T0", CC_OVERFLOW_0
| CC_NO_CARRY
},
1743 { "shlr.l %S0", CC_OVERFLOW_0
| CC_NO_CARRY
}
1745 /* SHIFT_ASHIFTRT */
1747 { "shar.b %X0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1748 { "shar.w %T0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1749 { "shar.l %S0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
}
1754 /* Rotates are organized by which shift they'll be used in implementing.
1755 There's no need to record whether the cc is valid afterwards because
1756 it is the AND insn that will decide this. */
1758 static const char *const rotate_one
[2][3][3] =
1765 "shlr %t0\t; rotr.w\n\trotxr %s0\n\tbst #7,%t0\t; end rotr.w",
1768 /* SHIFT_LSHIFTRT */
1771 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1774 /* SHIFT_ASHIFTRT */
1777 "shll %s0\t; rotl.w\n\trotxl %t0\n\tbst #0,%s0\t; end rotl.w",
1789 /* SHIFT_LSHIFTRT */
1795 /* SHIFT_ASHIFTRT */
1804 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
1805 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
1806 We don't achieve maximum efficiency in all cases, but the hooks are here
1809 For now we just use lots of switch statements. Since we don't even come
1810 close to supporting all the cases, this is simplest. If this function ever
1811 gets too big, perhaps resort to a more table based lookup. Of course,
1812 at this point you may just wish to do it all in rtl.
1814 WARNING: The constraints on insns shiftbyn_QI/HI/SI assume shifts of
1815 1,2,3,4 will be inlined (1,2 for SI). */
1817 static enum shift_alg
1818 get_shift_alg (cpu
, shift_type
, mode
, count
, assembler_p
, cc_valid_p
)
1820 enum shift_type shift_type
;
1821 enum machine_mode mode
;
1823 const char **assembler_p
;
1826 /* The default is to loop. */
1827 enum shift_alg alg
= SHIFT_LOOP
;
1828 enum shift_mode shift_mode
;
1830 /* We don't handle negative shifts or shifts greater than the word size,
1831 they should have been handled already. */
1833 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
1839 shift_mode
= QIshift
;
1842 shift_mode
= HIshift
;
1845 shift_mode
= SIshift
;
1851 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
1852 It is up to the caller to know that looping clobbers cc. */
1853 *assembler_p
= shift_one
[cpu
][shift_type
][shift_mode
].assembler
;
1854 *cc_valid_p
= shift_one
[cpu
][shift_type
][shift_mode
].cc_valid
;
1856 /* Now look for cases we want to optimize. */
1862 return SHIFT_INLINE
;
1863 else if (count
<= 6)
1865 if (shift_type
== SHIFT_ASHIFTRT
)
1871 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1873 return SHIFT_ROT_AND
;
1876 else if (count
== 7)
1878 if (shift_type
== SHIFT_ASHIFTRT
)
1880 *assembler_p
= "shll %X0\t; shar.b(7)\n\tsubx %X0,%X0\t; end shar.b(7)";
1882 return SHIFT_SPECIAL
;
1886 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1888 return SHIFT_ROT_AND
;
1894 return SHIFT_INLINE
;
1895 else if (count
== 8)
1900 *assembler_p
= "mov.b %s0,%t0\t; shal.w(8)\n\tsub.b %s0,%s0\t; end shal.w(8)";
1902 return SHIFT_SPECIAL
;
1903 case SHIFT_LSHIFTRT
:
1904 *assembler_p
= "mov.b %t0,%s0\t; shlr.w(8)\n\tsub.b %t0,%t0\t; end shlr.w(8)";
1906 return SHIFT_SPECIAL
;
1907 case SHIFT_ASHIFTRT
:
1908 if (cpu
== CPU_H8300
)
1909 *assembler_p
= "mov.b %t0,%s0\t; shar.w(8)\n\tshll %t0\n\tsubx %t0,%t0\t; end shar.w(8)";
1911 *assembler_p
= "mov.b %t0,%s0\t; shar.w(8)\n\texts.w %T0\t; end shar.w(8)";
1913 return SHIFT_SPECIAL
;
1917 else if (count
== 15)
1919 if (shift_type
== SHIFT_ASHIFTRT
)
1921 *assembler_p
= "shll %t0,%t0\t; shar.w(15)\n\tsubx %t0,%t0\n\tmov.b %t0,%s0\t; end shar.w(15)";
1923 return SHIFT_SPECIAL
;
1927 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1929 return SHIFT_ROT_AND
;
1934 if (count
<= (cpu
== CPU_H8300
? 2 : 4))
1935 return SHIFT_INLINE
;
1936 else if (count
== 8)
1938 if (cpu
== CPU_H8300
)
1943 *assembler_p
= "mov.b %y0,%z0\t; shal.l(8)\n\tmov.b %x0,%y0\n\tmov.b %w0,%x0\n\tsub.b %w0,%w0\t; end shal.l(8)";
1945 return SHIFT_SPECIAL
;
1946 case SHIFT_LSHIFTRT
:
1947 *assembler_p
= "mov.b %x0,%w0\t; shlr.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tsub.b %z0,%z0\t; end shlr.l(8)";
1949 return SHIFT_SPECIAL
;
1950 case SHIFT_ASHIFTRT
:
1951 *assembler_p
= "mov.b %x0,%w0\t; shar.l(8)\n\tmov.b %y0,%x0\n\tmov.b %z0,%y0\n\tshll %z0\n\tsubx %z0,%z0; end shar.l(8)";
1953 return SHIFT_SPECIAL
;
1956 else /* CPU_H8300H */
1957 /* We don't have byte level access to the high word so this isn't
1958 easy to do. For now, just loop. */
1961 else if (count
== 16)
1966 *assembler_p
= "mov.w %f0,%e0\t; shal.l(16)\n\tsub.w %f0,%f0\t; end shal.l(16)";
1968 return SHIFT_SPECIAL
;
1969 case SHIFT_LSHIFTRT
:
1970 *assembler_p
= "mov.w %e0,%f0\t; shlr.l(16)\n\tsub.w %e0,%e0\t; end shlr.l(16)";
1972 return SHIFT_SPECIAL
;
1973 case SHIFT_ASHIFTRT
:
1974 if (cpu
== CPU_H8300
)
1975 *assembler_p
= "mov.w %e0,%f0\t; shar.l(16)\n\tshll %z0\n\tsubx %z0,%z0\n\tmov.b %z0,%y0\t; end shar.l(16)";
1977 *assembler_p
= "mov.w %e0,%f0\t; shar.l(16)\n\texts.l %S0\t; end shar.l(16)";
1979 return SHIFT_SPECIAL
;
1982 else if (count
>= 28 && count
<= 30)
1984 if (shift_type
== SHIFT_ASHIFTRT
)
1990 if (cpu
== CPU_H8300
)
1994 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
1996 return SHIFT_ROT_AND
;
2000 else if (count
== 31)
2002 if (shift_type
== SHIFT_ASHIFTRT
)
2004 if (cpu
== CPU_H8300
)
2005 *assembler_p
= "shll %z0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
2007 *assembler_p
= "shll %e0\t; shar.l(31)\n\tsubx %w0,%w0\n\tmov.b %w0,%x0\n\tmov.w %f0,%e0\t; end shar.l(31)";
2009 return SHIFT_SPECIAL
;
2013 if (cpu
== CPU_H8300
)
2015 if (shift_type
== SHIFT_ASHIFT
)
2016 *assembler_p
= "sub.w %e0,%e0\t; shal.l(31)\n\tshlr %w0\n\tmov.w %e0,%f0\n\trotxr %z0\t; end shal.l(31)";
2018 *assembler_p
= "sub.w %f0,%f0\t; shlr.l(31)\n\tshll %z0\n\tmov.w %f0,%e0\n\trotxl %w0\t; end shlr.l(31)";
2020 return SHIFT_SPECIAL
;
2024 *assembler_p
= rotate_one
[cpu
][shift_type
][shift_mode
];
2026 return SHIFT_ROT_AND
;
2038 /* Emit the assembler code for doing shifts. */
2041 emit_a_shift (insn
, operands
)
2045 static int loopend_lab
;
2048 rtx inside
= PATTERN (insn
);
2049 rtx shift
= operands
[3];
2050 enum machine_mode mode
= GET_MODE (shift
);
2051 enum rtx_code code
= GET_CODE (shift
);
2052 enum shift_type shift_type
;
2053 enum shift_mode shift_mode
;
2060 shift_mode
= QIshift
;
2063 shift_mode
= HIshift
;
2066 shift_mode
= SIshift
;
2075 shift_type
= SHIFT_ASHIFTRT
;
2078 shift_type
= SHIFT_LSHIFTRT
;
2081 shift_type
= SHIFT_ASHIFT
;
2087 if (GET_CODE (operands
[2]) != CONST_INT
)
2089 /* Indexing by reg, so have to loop and test at top */
2090 output_asm_insn ("mov.b %X2,%X4", operands
);
2091 fprintf (asm_out_file
, "\tble .Lle%d\n", loopend_lab
);
2093 /* Get the assembler code to do one shift. */
2094 get_shift_alg (cpu_type
, shift_type
, mode
, 1, &assembler
, &cc_valid
);
2098 int n
= INTVAL (operands
[2]);
2101 /* If the count is negative, make it 0. */
2104 /* If the count is too big, truncate it.
2105 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
2106 do the intuitive thing. */
2107 else if (n
> GET_MODE_BITSIZE (mode
))
2108 n
= GET_MODE_BITSIZE (mode
);
2110 alg
= get_shift_alg (cpu_type
, shift_type
, mode
, n
, &assembler
, &cc_valid
);
2116 output_asm_insn (assembler
, operands
);
2119 cc_status
.value1
= operands
[0];
2120 cc_status
.flags
|= cc_valid
;
2125 int m
= GET_MODE_BITSIZE (mode
) - n
;
2126 int mask
= (shift_type
== SHIFT_ASHIFT
2127 ? ((1 << GET_MODE_BITSIZE (mode
) - n
) - 1) << n
2128 : (1 << GET_MODE_BITSIZE (mode
) - n
) - 1);
2130 /* Not all possibilities of rotate are supported. They shouldn't
2131 be generated, but let's watch for 'em. */
2135 output_asm_insn (assembler
, operands
);
2141 sprintf (insn_buf
, "and #%d,%%X0\t; end shift %d via rotate+and",
2143 cc_status
.value1
= operands
[0];
2144 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
2147 sprintf (insn_buf
, "and #%d,%%s0\n\tand #%d,%%t0\t; end shift %d via rotate+and",
2148 mask
& 255, mask
>> 8, n
);
2156 sprintf (insn_buf
, "and.%c #%d,%%%c0",
2157 "bwl"[shift_mode
], mask
,
2158 mode
== QImode
? 'X' : mode
== HImode
? 'T' : 'S');
2159 cc_status
.value1
= operands
[0];
2160 cc_status
.flags
|= CC_OVERFLOW_0
| CC_NO_CARRY
;
2162 output_asm_insn (insn_buf
, operands
);
2166 output_asm_insn (assembler
, operands
);
2170 /* Need a loop, move limit to tmp reg */
2171 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
, names_big
[REGNO (operands
[4])]);
2174 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
2175 output_asm_insn (assembler
, operands
);
2176 output_asm_insn ("add #0xff,%X4", operands
);
2177 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
2178 fprintf (asm_out_file
, ".Lle%d:\n", loopend_lab
);
2183 /* Fix the operands of a gen_xxx so that it could become a bit
2187 fix_bit_operand (operands
, what
, type
)
2192 /* The bit_operand predicate accepts any memory during RTL generation, but
2193 only 'U' memory afterwards, so if this is a MEM operand, we must force
2194 it to be valid for 'U' by reloading the address. */
2196 if (GET_CODE (operands
[2]) == CONST_INT
)
2198 if (CONST_OK_FOR_LETTER_P (INTVAL (operands
[2]), what
))
2200 /* Ok to have a memory dest. */
2201 if (GET_CODE (operands
[0]) == MEM
&& !EXTRA_CONSTRAINT (operands
[0], 'U'))
2204 mem
= gen_rtx (MEM
, GET_MODE (operands
[0]),
2205 copy_to_mode_reg (Pmode
, XEXP (operands
[0], 0)));
2206 RTX_UNCHANGING_P (mem
) = RTX_UNCHANGING_P (operands
[0]);
2207 MEM_IN_STRUCT_P (mem
) = MEM_IN_STRUCT_P (operands
[0]);
2208 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (operands
[0]);
2212 if (GET_CODE (operands
[1]) == MEM
&& !EXTRA_CONSTRAINT (operands
[1], 'U'))
2215 mem
= gen_rtx (MEM
, GET_MODE (operands
[1]),
2216 copy_to_mode_reg (Pmode
, XEXP (operands
[1], 0)));
2217 RTX_UNCHANGING_P (mem
) = RTX_UNCHANGING_P (operands
[1]);
2218 MEM_IN_STRUCT_P (mem
) = MEM_IN_STRUCT_P (operands
[1]);
2219 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (operands
[1]);
2226 /* Dest and src op must be register. */
2228 operands
[1] = force_reg (QImode
, operands
[1]);
2230 rtx res
= gen_reg_rtx (QImode
);
2231 emit_insn (gen_rtx (SET
, VOIDmode
, res
, gen_rtx (type
, QImode
, operands
[1], operands
[2])));
2232 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], res
));
2237 /* Return nonzero if FUNC is an interrupt function as specified
2238 by the "interrupt" attribute. */
2241 h8300_interrupt_function_p (func
)
2246 if (TREE_CODE (func
) != FUNCTION_DECL
)
2249 a
= lookup_attribute ("interrupt_handler", DECL_MACHINE_ATTRIBUTES (func
));
2250 return a
!= NULL_TREE
;
2253 /* Return nonzero if FUNC is an OS_Task function as specified
2254 by the "OS_Task" attribute. */
2257 h8300_os_task_function_p (func
)
2262 if (TREE_CODE (func
) != FUNCTION_DECL
)
2265 a
= lookup_attribute ("OS_Task", DECL_MACHINE_ATTRIBUTES (func
));
2266 return a
!= NULL_TREE
;
2269 /* Return nonzero if FUNC is a monitor function as specified
2270 by the "monitor" attribute. */
2273 h8300_monitor_function_p (func
)
2278 if (TREE_CODE (func
) != FUNCTION_DECL
)
2281 a
= lookup_attribute ("monitor", DECL_MACHINE_ATTRIBUTES (func
));
2282 return a
!= NULL_TREE
;
2285 /* Return nonzero if FUNC is a function that should be called
2286 through the function vector. */
2289 h8300_funcvec_function_p (func
)
2294 if (TREE_CODE (func
) != FUNCTION_DECL
)
2297 a
= lookup_attribute ("function_vector", DECL_MACHINE_ATTRIBUTES (func
));
2298 return a
!= NULL_TREE
;
2301 /* Return nonzero if DECL is a variable that's in the eight bit
2305 h8300_eightbit_data_p (decl
)
2310 if (TREE_CODE (decl
) != VAR_DECL
)
2313 a
= lookup_attribute ("eightbit_data", DECL_MACHINE_ATTRIBUTES (decl
));
2314 return a
!= NULL_TREE
;
2317 /* Return nonzero if DECL is a variable that's in the tiny
2321 h8300_tiny_data_p (decl
)
2326 if (TREE_CODE (decl
) != VAR_DECL
)
2329 a
= lookup_attribute ("tiny_data", DECL_MACHINE_ATTRIBUTES (decl
));
2330 return a
!= NULL_TREE
;
2333 /* Return nonzero if ATTR is a valid attribute for DECL.
2334 ATTRIBUTES are any existing attributes and ARGS are the arguments
2337 Supported attributes:
2339 interrupt_handler: output a prologue and epilogue suitable for an
2342 function_vector: This function should be called through the
2345 eightbit_data: This variable lives in the 8-bit data area and can
2346 be referenced with 8-bit absolute memory addresses.
2348 tiny_data: This variable lives in the tiny data area and can be
2349 referenced with 16-bit absolute memory references. */
2352 h8300_valid_machine_decl_attribute (decl
, attributes
, attr
, args
)
2358 if (args
!= NULL_TREE
)
2361 if (is_attribute_p ("interrupt_handler", attr
)
2362 || is_attribute_p ("OS_Task", attr
)
2363 || is_attribute_p ("monitor", attr
)
2364 || is_attribute_p ("function_vector", attr
))
2365 return TREE_CODE (decl
) == FUNCTION_DECL
;
2367 if (is_attribute_p ("eightbit_data", attr
)
2368 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
2370 if (DECL_INITIAL (decl
) == NULL_TREE
)
2372 warning ("Only initialized variables can be placed into the 8-bit area.");
2375 DECL_SECTION_NAME (decl
) = build_string (7, ".eight");
2379 if (is_attribute_p ("tiny_data", attr
)
2380 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
2382 if (DECL_INITIAL (decl
) == NULL_TREE
)
2384 warning ("Only initialized variables can be placed into the 8-bit area.");
2387 DECL_SECTION_NAME (decl
) = build_string (6, ".tiny");
2394 extern struct obstack
*saveable_obstack
;
2396 h8300_encode_label (decl
)
2399 char *str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2400 int len
= strlen (str
);
2403 newstr
= obstack_alloc (saveable_obstack
, len
+ 2);
2405 strcpy (newstr
+ 1, str
);
2407 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2411 output_simode_bld (bild
, log2
, operands
)
2416 /* Clear the destination register. */
2418 output_asm_insn ("sub.l\t%S0,%S0", operands
);
2420 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
2422 /* Get the bit number we want to load. */
2424 operands
[2] = GEN_INT (exact_log2 (INTVAL (operands
[2])));
2426 /* Now output the bit load or bit inverse load, and store it in
2429 output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands
);
2431 output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands
);
2437 /* Given INSN and it's current length LENGTH, return the adjustment
2438 (in bytes) to correctly compute INSN's length.
2440 We use this to get the lengths of various memory references correct. */
2442 h8300_adjust_insn_length (insn
, length
)
2446 rtx pat
= PATTERN (insn
);
2448 /* Adjust length for reg->mem and mem->reg copies. */
2449 if (GET_CODE (pat
) == SET
2450 && (GET_CODE (SET_SRC (pat
)) == MEM
2451 || GET_CODE (SET_DEST (pat
)) == MEM
))
2453 /* This insn might need a length adjustment. */
2456 if (GET_CODE (SET_SRC (pat
)) == MEM
)
2457 addr
= XEXP (SET_SRC (pat
), 0);
2459 addr
= XEXP (SET_DEST (pat
), 0);
2461 /* On the H8/300, only one adjustment is necessary; if the
2462 address mode is register indirect, then this insn is two
2463 bytes shorter than indicated in the machine description. */
2464 if (TARGET_H8300
&& GET_CODE (addr
) == REG
)
2467 /* On the H8/300H, register indirect is 6 bytes shorter than
2468 indicated in the machine description. */
2469 if (TARGET_H8300H
&& GET_CODE (addr
) == REG
)
2472 /* On the H8/300H, reg + d, for small displacements is 4 bytes
2473 shorter than indicated in the machine description. */
2475 && GET_CODE (addr
) == PLUS
2476 && GET_CODE (XEXP (addr
, 0)) == REG
2477 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
2478 && INTVAL (XEXP (addr
, 1)) > -32768
2479 && INTVAL (XEXP (addr
, 1)) < 32767)
2482 /* On the H8/300H, abs:16 is two bytes shorter than the
2483 more general abs:24. */
2485 && GET_CODE (addr
) == SYMBOL_REF
2486 && TINY_DATA_NAME_P (XSTR (addr
, 0)))
2490 /* Loading some constants needs adjustment. */
2491 if (GET_CODE (pat
) == SET
2492 && GET_CODE (SET_SRC (pat
)) == CONST_INT
2493 && GET_MODE (SET_DEST (pat
)) == SImode
2494 && INTVAL (SET_SRC (pat
)) != 0)
2497 && ((INTVAL (SET_SRC (pat
)) & 0xffff) == 0
2498 || ((INTVAL (SET_SRC (pat
)) >> 16) & 0xffff) == 0))
2503 int val
= INTVAL (SET_SRC (pat
));
2505 if (val
== (val
& 0xff)
2506 || val
== (val
& 0xff00))
2509 if (val
== -4 || val
== -2 || val
== -1)
2514 /* Shifts need various adjustments. */
2515 if (GET_CODE (pat
) == PARALLEL
2516 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
2517 && (GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == ASHIFTRT
2518 || GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == LSHIFTRT
2519 || GET_CODE (SET_SRC (XVECEXP (pat
, 0, 0))) == ASHIFT
))
2521 rtx src
= SET_SRC (XVECEXP (pat
, 0, 0));
2522 enum machine_mode mode
= GET_MODE (src
);
2524 if (GET_CODE (XEXP (src
, 1)) != CONST_INT
)
2527 /* QImode shifts by small constants take one insn
2528 per shift. So the adjustment is 20 (md length) -
2530 if (mode
== QImode
&& INTVAL (XEXP (src
, 1)) <= 4)
2531 return -(20 - INTVAL (XEXP (src
, 1)) * 2);
2533 /* Similarly for HImode and SImode shifts by
2534 small constants on the H8/300H. */
2536 && (mode
== HImode
|| mode
== SImode
)
2537 && INTVAL (XEXP (src
, 1)) <= 4)
2538 return -(20 - INTVAL (XEXP (src
, 1)) * 2);
2540 /* HImode shifts by small constants for the H8/300. */
2542 && INTVAL (XEXP (src
, 1)) <= 4)
2543 return -(20 - (INTVAL (XEXP (src
, 1))
2544 * (GET_CODE (src
) == ASHIFT
? 2 : 4)));
2546 /* SImode shifts by small constants for the H8/300. */
2548 && INTVAL (XEXP (src
, 1)) <= 2)
2549 return -(20 - (INTVAL (XEXP (src
, 1))
2550 * (GET_CODE (src
) == ASHIFT
? 6 : 8)));
2552 /* XXX ??? Could check for more shift/rotate cases here. */