1 /* Subroutines for insn-output.c for Renesas H8/300.
2 Copyright (C) 1992-2016 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com),
4 Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
32 #include "stringpool.h"
37 #include "diagnostic-core.h"
39 #include "stor-layout.h"
42 #include "conditions.h"
44 #include "insn-attr.h"
48 #include "tm-constrs.h"
51 /* This file should be included last. */
52 #include "target-def.h"
54 /* Classifies a h8300_src_operand or h8300_dst_operand.
57 A constant operand of some sort.
63 A memory reference with a constant address.
66 A memory reference with a register as its address.
69 Some other kind of memory reference. */
70 enum h8300_operand_class
80 /* For a general two-operand instruction, element [X][Y] gives
81 the length of the opcode fields when the first operand has class
82 (X + 1) and the second has class Y. */
83 typedef unsigned char h8300_length_table
[NUM_H8OPS
- 1][NUM_H8OPS
];
85 /* Forward declarations. */
86 static const char *byte_reg (rtx
, int);
87 static int h8300_interrupt_function_p (tree
);
88 static int h8300_saveall_function_p (tree
);
89 static int h8300_monitor_function_p (tree
);
90 static int h8300_os_task_function_p (tree
);
91 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT
, bool);
92 static HOST_WIDE_INT
round_frame_size (HOST_WIDE_INT
);
93 static unsigned int compute_saved_regs (void);
94 static const char *cond_string (enum rtx_code
);
95 static unsigned int h8300_asm_insn_count (const char *);
96 static tree
h8300_handle_fndecl_attribute (tree
*, tree
, tree
, int, bool *);
97 static tree
h8300_handle_eightbit_data_attribute (tree
*, tree
, tree
, int, bool *);
98 static tree
h8300_handle_tiny_data_attribute (tree
*, tree
, tree
, int, bool *);
99 static void h8300_print_operand_address (FILE *, machine_mode
, rtx
);
100 static void h8300_print_operand (FILE *, rtx
, int);
101 static bool h8300_print_operand_punct_valid_p (unsigned char code
);
102 #ifndef OBJECT_FORMAT_ELF
103 static void h8300_asm_named_section (const char *, unsigned int, tree
);
105 static int h8300_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
106 static int h8300_and_costs (rtx
);
107 static int h8300_shift_costs (rtx
);
108 static void h8300_push_pop (int, int, bool, bool);
109 static int h8300_stack_offset_p (rtx
, int);
110 static int h8300_ldm_stm_regno (rtx
, int, int, int);
111 static void h8300_reorg (void);
112 static unsigned int h8300_constant_length (rtx
);
113 static unsigned int h8300_displacement_length (rtx
, int);
114 static unsigned int h8300_classify_operand (rtx
, int, enum h8300_operand_class
*);
115 static unsigned int h8300_length_from_table (rtx
, rtx
, const h8300_length_table
*);
116 static unsigned int h8300_unary_length (rtx
);
117 static unsigned int h8300_short_immediate_length (rtx
);
118 static unsigned int h8300_bitfield_length (rtx
, rtx
);
119 static unsigned int h8300_binary_length (rtx_insn
*, const h8300_length_table
*);
120 static bool h8300_short_move_mem_p (rtx
, enum rtx_code
);
121 static unsigned int h8300_move_length (rtx
*, const h8300_length_table
*);
122 static bool h8300_hard_regno_scratch_ok (unsigned int);
123 static rtx
h8300_get_index (rtx
, machine_mode mode
, int *);
125 /* CPU_TYPE, says what cpu we're compiling for. */
128 /* True if a #pragma interrupt has been seen for the current function. */
129 static int pragma_interrupt
;
131 /* True if a #pragma saveall has been seen for the current function. */
132 static int pragma_saveall
;
134 static const char *const names_big
[] =
135 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" };
137 static const char *const names_extended
[] =
138 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" };
140 static const char *const names_upper_extended
[] =
141 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" };
143 /* Points to one of the above. */
144 /* ??? The above could be put in an array indexed by CPU_TYPE. */
145 const char * const *h8_reg_names
;
147 /* Various operations needed by the following, indexed by CPU_TYPE. */
149 const char *h8_push_op
, *h8_pop_op
, *h8_mov_op
;
151 /* Value of MOVE_RATIO. */
152 int h8300_move_ratio
;
154 /* See below where shifts are handled for explanation of this enum. */
164 /* Symbols of the various shifts which can be used as indices. */
168 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
171 /* Macros to keep the shift algorithm tables small. */
172 #define INL SHIFT_INLINE
173 #define ROT SHIFT_ROT_AND
174 #define LOP SHIFT_LOOP
175 #define SPC SHIFT_SPECIAL
177 /* The shift algorithms for each machine, mode, shift type, and shift
178 count are defined below. The three tables below correspond to
179 QImode, HImode, and SImode, respectively. Each table is organized
180 by, in the order of indices, machine, shift type, and shift count. */
182 static enum shift_alg shift_alg_qi
[3][3][8] = {
185 /* 0 1 2 3 4 5 6 7 */
186 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
187 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
188 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
192 /* 0 1 2 3 4 5 6 7 */
193 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
194 { INL
, INL
, INL
, INL
, INL
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
195 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
} /* SHIFT_ASHIFTRT */
199 /* 0 1 2 3 4 5 6 7 */
200 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_ASHIFT */
201 { INL
, INL
, INL
, INL
, INL
, INL
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
202 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
} /* SHIFT_ASHIFTRT */
206 static enum shift_alg shift_alg_hi
[3][3][16] = {
209 /* 0 1 2 3 4 5 6 7 */
210 /* 8 9 10 11 12 13 14 15 */
211 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
212 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
213 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
214 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
215 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, SPC
,
216 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
220 /* 0 1 2 3 4 5 6 7 */
221 /* 8 9 10 11 12 13 14 15 */
222 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
223 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
224 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
225 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
226 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, SPC
,
227 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
231 /* 0 1 2 3 4 5 6 7 */
232 /* 8 9 10 11 12 13 14 15 */
233 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
234 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_ASHIFT */
235 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
236 SPC
, SPC
, SPC
, SPC
, SPC
, ROT
, ROT
, ROT
}, /* SHIFT_LSHIFTRT */
237 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
238 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFTRT */
242 static enum shift_alg shift_alg_si
[3][3][32] = {
245 /* 0 1 2 3 4 5 6 7 */
246 /* 8 9 10 11 12 13 14 15 */
247 /* 16 17 18 19 20 21 22 23 */
248 /* 24 25 26 27 28 29 30 31 */
249 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
250 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
251 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
,
252 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFT */
253 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
254 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
255 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
,
256 SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, SPC
}, /* SHIFT_LSHIFTRT */
257 { INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
258 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
259 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
260 SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
264 /* 0 1 2 3 4 5 6 7 */
265 /* 8 9 10 11 12 13 14 15 */
266 /* 16 17 18 19 20 21 22 23 */
267 /* 24 25 26 27 28 29 30 31 */
268 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
269 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
270 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
271 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
272 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
273 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
,
274 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
275 SPC
, LOP
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
276 { INL
, INL
, INL
, INL
, INL
, LOP
, LOP
, LOP
,
277 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
,
278 SPC
, SPC
, SPC
, SPC
, LOP
, LOP
, LOP
, LOP
,
279 SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
283 /* 0 1 2 3 4 5 6 7 */
284 /* 8 9 10 11 12 13 14 15 */
285 /* 16 17 18 19 20 21 22 23 */
286 /* 24 25 26 27 28 29 30 31 */
287 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
288 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
289 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
290 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_ASHIFT */
291 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
292 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, SPC
,
293 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
294 SPC
, SPC
, LOP
, LOP
, SPC
, SPC
, SPC
, SPC
}, /* SHIFT_LSHIFTRT */
295 { INL
, INL
, INL
, INL
, INL
, INL
, INL
, INL
,
296 INL
, INL
, INL
, LOP
, LOP
, LOP
, LOP
, LOP
,
297 SPC
, SPC
, SPC
, SPC
, SPC
, SPC
, LOP
, LOP
,
298 SPC
, SPC
, LOP
, LOP
, LOP
, LOP
, LOP
, SPC
}, /* SHIFT_ASHIFTRT */
314 /* Initialize various cpu specific globals at start up. */
317 h8300_option_override (void)
319 static const char *const h8_push_ops
[2] = { "push" , "push.l" };
320 static const char *const h8_pop_ops
[2] = { "pop" , "pop.l" };
321 static const char *const h8_mov_ops
[2] = { "mov.w", "mov.l" };
323 #ifndef OBJECT_FORMAT_ELF
326 error ("-msx is not supported in coff");
327 target_flags
|= MASK_H8300S
;
333 cpu_type
= (int) CPU_H8300
;
334 h8_reg_names
= names_big
;
338 /* For this we treat the H8/300H and H8S the same. */
339 cpu_type
= (int) CPU_H8300H
;
340 h8_reg_names
= names_extended
;
342 h8_push_op
= h8_push_ops
[cpu_type
];
343 h8_pop_op
= h8_pop_ops
[cpu_type
];
344 h8_mov_op
= h8_mov_ops
[cpu_type
];
346 if (!TARGET_H8300S
&& TARGET_MAC
)
348 error ("-ms2600 is used without -ms");
349 target_flags
|= MASK_H8300S_1
;
352 if (TARGET_H8300
&& TARGET_NORMAL_MODE
)
354 error ("-mn is used without -mh or -ms or -msx");
355 target_flags
^= MASK_NORMAL_MODE
;
358 if (! TARGET_H8300S
&& TARGET_EXR
)
360 error ("-mexr is used without -ms");
361 target_flags
|= MASK_H8300S_1
;
364 if (TARGET_H8300
&& TARGET_INT32
)
366 error ("-mint32 is not supported for H8300 and H8300L targets");
367 target_flags
^= MASK_INT32
;
370 if ((!TARGET_H8300S
&& TARGET_EXR
) && (!TARGET_H8300SX
&& TARGET_EXR
))
372 error ("-mexr is used without -ms or -msx");
373 target_flags
|= MASK_H8300S_1
;
376 if ((!TARGET_H8300S
&& TARGET_NEXR
) && (!TARGET_H8300SX
&& TARGET_NEXR
))
378 warning (OPT_mno_exr
, "-mno-exr valid only with -ms or -msx \
383 if ((TARGET_NORMAL_MODE
))
385 error ("-mn is not supported for linux targets");
386 target_flags
^= MASK_NORMAL_MODE
;
390 /* Some of the shifts are optimized for speed by default.
391 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html
392 If optimizing for size, change shift_alg for those shift to
397 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
398 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
399 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][13] = SHIFT_LOOP
;
400 shift_alg_hi
[H8_300
][SHIFT_ASHIFT
][14] = SHIFT_LOOP
;
402 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][13] = SHIFT_LOOP
;
403 shift_alg_hi
[H8_300
][SHIFT_LSHIFTRT
][14] = SHIFT_LOOP
;
405 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
406 shift_alg_hi
[H8_300
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
409 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][5] = SHIFT_LOOP
;
410 shift_alg_hi
[H8_300H
][SHIFT_ASHIFT
][6] = SHIFT_LOOP
;
412 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][5] = SHIFT_LOOP
;
413 shift_alg_hi
[H8_300H
][SHIFT_LSHIFTRT
][6] = SHIFT_LOOP
;
415 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][5] = SHIFT_LOOP
;
416 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][6] = SHIFT_LOOP
;
417 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][13] = SHIFT_LOOP
;
418 shift_alg_hi
[H8_300H
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
421 shift_alg_hi
[H8_S
][SHIFT_ASHIFTRT
][14] = SHIFT_LOOP
;
424 /* Work out a value for MOVE_RATIO. */
427 /* Memory-memory moves are quite expensive without the
428 h8sx instructions. */
429 h8300_move_ratio
= 3;
431 else if (flag_omit_frame_pointer
)
433 /* movmd sequences are fairly cheap when er6 isn't fixed. They can
434 sometimes be as short as two individual memory-to-memory moves,
435 but since they use all the call-saved registers, it seems better
436 to allow up to three moves here. */
437 h8300_move_ratio
= 4;
439 else if (optimize_size
)
441 /* In this case we don't use movmd sequences since they tend
442 to be longer than calls to memcpy(). Memory-to-memory
443 moves are cheaper than for !TARGET_H8300SX, so it makes
444 sense to have a slightly higher threshold. */
445 h8300_move_ratio
= 4;
449 /* We use movmd sequences for some moves since it can be quicker
450 than calling memcpy(). The sequences will need to save and
451 restore er6 though, so bump up the cost. */
452 h8300_move_ratio
= 6;
455 /* This target defaults to strict volatile bitfields. */
456 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
457 flag_strict_volatile_bitfields
= 1;
460 /* Return the byte register name for a register rtx X. B should be 0
461 if you want a lower byte register. B should be 1 if you want an
462 upper byte register. */
465 byte_reg (rtx x
, int b
)
467 static const char *const names_small
[] = {
468 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h",
469 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h"
472 gcc_assert (REG_P (x
));
474 return names_small
[REGNO (x
) * 2 + b
];
477 /* REGNO must be saved/restored across calls if this macro is true. */
479 #define WORD_REG_USED(regno) \
481 /* No need to save registers if this function will not return. */ \
482 && ! TREE_THIS_VOLATILE (current_function_decl) \
483 && (h8300_saveall_function_p (current_function_decl) \
484 /* Save any call saved register that was used. */ \
485 || (df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
486 /* Save the frame pointer if it was used. */ \
487 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \
488 /* Save any register used in an interrupt handler. */ \
489 || (h8300_current_function_interrupt_function_p () \
490 && df_regs_ever_live_p (regno)) \
491 /* Save call clobbered registers in non-leaf interrupt \
493 || (h8300_current_function_interrupt_function_p () \
494 && call_used_regs[regno] \
497 /* We use this to wrap all emitted insns in the prologue. */
499 F (rtx_insn
*x
, bool set_it
)
502 RTX_FRAME_RELATED_P (x
) = 1;
506 /* Mark all the subexpressions of the PARALLEL rtx PAR as
507 frame-related. Return PAR.
509 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
510 PARALLEL rtx other than the first if they do not have the
511 FRAME_RELATED flag set on them. */
515 int len
= XVECLEN (par
, 0);
518 for (i
= 0; i
< len
; i
++)
519 RTX_FRAME_RELATED_P (XVECEXP (par
, 0, i
)) = 1;
524 /* Output assembly language to FILE for the operation OP with operand size
525 SIZE to adjust the stack pointer. */
528 h8300_emit_stack_adjustment (int sign
, HOST_WIDE_INT size
, bool in_prologue
)
530 /* If the frame size is 0, we don't have anything to do. */
534 /* H8/300 cannot add/subtract a large constant with a single
535 instruction. If a temporary register is available, load the
536 constant to it and then do the addition. */
539 && !h8300_current_function_interrupt_function_p ()
540 && !(cfun
->static_chain_decl
!= NULL
&& sign
< 0))
542 rtx r3
= gen_rtx_REG (Pmode
, 3);
543 F (emit_insn (gen_movhi (r3
, GEN_INT (sign
* size
))), in_prologue
);
544 F (emit_insn (gen_addhi3 (stack_pointer_rtx
,
545 stack_pointer_rtx
, r3
)), in_prologue
);
549 /* The stack adjustment made here is further optimized by the
550 splitter. In case of H8/300, the splitter always splits the
551 addition emitted here to make the adjustment interrupt-safe.
552 FIXME: We don't always tag those, because we don't know what
553 the splitter will do. */
556 rtx_insn
*x
= emit_insn (gen_addhi3 (stack_pointer_rtx
,
558 GEN_INT (sign
* size
)));
563 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
564 stack_pointer_rtx
, GEN_INT (sign
* size
))), in_prologue
);
568 /* Round up frame size SIZE. */
571 round_frame_size (HOST_WIDE_INT size
)
573 return ((size
+ STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
574 & -STACK_BOUNDARY
/ BITS_PER_UNIT
);
577 /* Compute which registers to push/pop.
578 Return a bit vector of registers. */
581 compute_saved_regs (void)
583 unsigned int saved_regs
= 0;
586 /* Construct a bit vector of registers to be pushed/popped. */
587 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
589 if (WORD_REG_USED (regno
))
590 saved_regs
|= 1 << regno
;
593 /* Don't push/pop the frame pointer as it is treated separately. */
594 if (frame_pointer_needed
)
595 saved_regs
&= ~(1 << HARD_FRAME_POINTER_REGNUM
);
600 /* Emit an insn to push register RN. */
603 push (int rn
, bool in_prologue
)
605 rtx reg
= gen_rtx_REG (word_mode
, rn
);
609 x
= gen_push_h8300 (reg
);
610 else if (!TARGET_NORMAL_MODE
)
611 x
= gen_push_h8300hs_advanced (reg
);
613 x
= gen_push_h8300hs_normal (reg
);
614 x
= F (emit_insn (x
), in_prologue
);
615 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
619 /* Emit an insn to pop register RN. */
624 rtx reg
= gen_rtx_REG (word_mode
, rn
);
628 x
= gen_pop_h8300 (reg
);
629 else if (!TARGET_NORMAL_MODE
)
630 x
= gen_pop_h8300hs_advanced (reg
);
632 x
= gen_pop_h8300hs_normal (reg
);
634 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
638 /* Emit an instruction to push or pop NREGS consecutive registers
639 starting at register REGNO. POP_P selects a pop rather than a
640 push and RETURN_P is true if the instruction should return.
642 It must be possible to do the requested operation in a single
643 instruction. If NREGS == 1 && !RETURN_P, use a normal push
644 or pop insn. Otherwise emit a parallel of the form:
647 [(return) ;; if RETURN_P
648 (save or restore REGNO)
649 (save or restore REGNO + 1)
651 (save or restore REGNO + NREGS - 1)
652 (set sp (plus sp (const_int adjust)))] */
655 h8300_push_pop (int regno
, int nregs
, bool pop_p
, bool return_p
)
661 /* See whether we can use a simple push or pop. */
662 if (!return_p
&& nregs
== 1)
671 /* We need one element for the return insn, if present, one for each
672 register, and one for stack adjustment. */
673 vec
= rtvec_alloc ((return_p
? 1 : 0) + nregs
+ 1);
674 sp
= stack_pointer_rtx
;
677 /* Add the return instruction. */
680 RTVEC_ELT (vec
, i
) = ret_rtx
;
684 /* Add the register moves. */
685 for (j
= 0; j
< nregs
; j
++)
691 /* Register REGNO + NREGS - 1 is popped first. Before the
692 stack adjustment, its slot is at address @sp. */
693 lhs
= gen_rtx_REG (SImode
, regno
+ j
);
694 rhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
,
695 (nregs
- j
- 1) * 4));
699 /* Register REGNO is pushed first and will be stored at @(-4,sp). */
700 lhs
= gen_rtx_MEM (SImode
, plus_constant (Pmode
, sp
, (j
+ 1) * -4));
701 rhs
= gen_rtx_REG (SImode
, regno
+ j
);
703 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (lhs
, rhs
);
706 /* Add the stack adjustment. */
707 offset
= GEN_INT ((pop_p
? nregs
: -nregs
) * 4);
708 RTVEC_ELT (vec
, i
+ j
) = gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, offset
));
710 x
= gen_rtx_PARALLEL (VOIDmode
, vec
);
720 /* Return true if X has the value sp + OFFSET. */
723 h8300_stack_offset_p (rtx x
, int offset
)
726 return x
== stack_pointer_rtx
;
728 return (GET_CODE (x
) == PLUS
729 && XEXP (x
, 0) == stack_pointer_rtx
730 && GET_CODE (XEXP (x
, 1)) == CONST_INT
731 && INTVAL (XEXP (x
, 1)) == offset
);
734 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in
735 something that may be an ldm or stm instruction. If it fits
736 the required template, return the register it loads or stores,
739 LOAD_P is true if X should be a load, false if it should be a store.
740 NREGS is the number of registers that the whole instruction is expected
741 to load or store. INDEX is the index of the register that X should
742 load or store, relative to the lowest-numbered register. */
745 h8300_ldm_stm_regno (rtx x
, int load_p
, int index
, int nregs
)
747 int regindex
, memindex
, offset
;
750 regindex
= 0, memindex
= 1, offset
= (nregs
- index
- 1) * 4;
752 memindex
= 0, regindex
= 1, offset
= (index
+ 1) * -4;
754 if (GET_CODE (x
) == SET
755 && GET_CODE (XEXP (x
, regindex
)) == REG
756 && GET_CODE (XEXP (x
, memindex
)) == MEM
757 && h8300_stack_offset_p (XEXP (XEXP (x
, memindex
), 0), offset
))
758 return REGNO (XEXP (x
, regindex
));
763 /* Return true if the elements of VEC starting at FIRST describe an
764 ldm or stm instruction (LOAD_P says which). */
767 h8300_ldm_stm_parallel (rtvec vec
, int load_p
, int first
)
770 int nregs
, i
, regno
, adjust
;
772 /* There must be a stack adjustment, a register move, and at least one
773 other operation (a return or another register move). */
774 if (GET_NUM_ELEM (vec
) < 3)
777 /* Get the range of registers to be pushed or popped. */
778 nregs
= GET_NUM_ELEM (vec
) - first
- 1;
779 regno
= h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
), load_p
, 0, nregs
);
781 /* Check that the call to h8300_ldm_stm_regno succeeded and
782 that we're only dealing with GPRs. */
783 if (regno
< 0 || regno
+ nregs
> 8)
786 /* 2-register h8s instructions must start with an even-numbered register.
787 3- and 4-register instructions must start with er0 or er4. */
790 if ((regno
& 1) != 0)
792 if (nregs
> 2 && (regno
& 3) != 0)
796 /* Check the other loads or stores. */
797 for (i
= 1; i
< nregs
; i
++)
798 if (h8300_ldm_stm_regno (RTVEC_ELT (vec
, first
+ i
), load_p
, i
, nregs
)
802 /* Check the stack adjustment. */
803 last
= RTVEC_ELT (vec
, first
+ nregs
);
804 adjust
= (load_p
? nregs
: -nregs
) * 4;
805 return (GET_CODE (last
) == SET
806 && SET_DEST (last
) == stack_pointer_rtx
807 && h8300_stack_offset_p (SET_SRC (last
), adjust
));
810 /* This is what the stack looks like after the prolog of
811 a function with a frame has been set up:
817 <saved registers> <- sp
819 This is what the stack looks like after the prolog of
820 a function which doesn't have a frame:
825 <saved registers> <- sp
828 /* Generate RTL code for the function prologue. */
831 h8300_expand_prologue (void)
837 /* If the current function has the OS_Task attribute set, then
838 we have a naked prologue. */
839 if (h8300_os_task_function_p (current_function_decl
))
842 if (h8300_monitor_function_p (current_function_decl
))
843 /* The monitor function act as normal functions, which means it
844 can accept parameters and return values. In addition to this,
845 interrupts are masked in prologue and return with "rte" in epilogue. */
846 emit_insn (gen_monitor_prologue ());
848 if (frame_pointer_needed
)
851 push (HARD_FRAME_POINTER_REGNUM
, true);
852 F (emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
), true);
855 /* Push the rest of the registers in ascending order. */
856 saved_regs
= compute_saved_regs ();
857 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
+= n_regs
)
860 if (saved_regs
& (1 << regno
))
864 /* See how many registers we can push at the same time. */
865 if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
866 && ((saved_regs
>> regno
) & 0x0f) == 0x0f)
869 else if ((!TARGET_H8300SX
|| (regno
& 3) == 0)
870 && ((saved_regs
>> regno
) & 0x07) == 0x07)
873 else if ((!TARGET_H8300SX
|| (regno
& 1) == 0)
874 && ((saved_regs
>> regno
) & 0x03) == 0x03)
878 h8300_push_pop (regno
, n_regs
, false, false);
882 /* Leave room for locals. */
883 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ()), true);
885 if (flag_stack_usage_info
)
886 current_function_static_stack_size
887 = round_frame_size (get_frame_size ())
888 + (__builtin_popcount (saved_regs
) * UNITS_PER_WORD
)
889 + (frame_pointer_needed
? UNITS_PER_WORD
: 0);
892 /* Return nonzero if we can use "rts" for the function currently being
896 h8300_can_use_return_insn_p (void)
898 return (reload_completed
899 && !frame_pointer_needed
900 && get_frame_size () == 0
901 && compute_saved_regs () == 0);
904 /* Generate RTL code for the function epilogue. */
907 h8300_expand_epilogue (void)
912 HOST_WIDE_INT frame_size
;
915 if (h8300_os_task_function_p (current_function_decl
))
916 /* OS_Task epilogues are nearly naked -- they just have an
920 frame_size
= round_frame_size (get_frame_size ());
923 /* Deallocate locals. */
924 h8300_emit_stack_adjustment (1, frame_size
, false);
926 /* Pop the saved registers in descending order. */
927 saved_regs
= compute_saved_regs ();
928 for (regno
= FIRST_PSEUDO_REGISTER
- 1; regno
>= 0; regno
-= n_regs
)
931 if (saved_regs
& (1 << regno
))
935 /* See how many registers we can pop at the same time. */
936 if ((TARGET_H8300SX
|| (regno
& 3) == 3)
937 && ((saved_regs
<< 3 >> regno
) & 0x0f) == 0x0f)
940 else if ((TARGET_H8300SX
|| (regno
& 3) == 2)
941 && ((saved_regs
<< 2 >> regno
) & 0x07) == 0x07)
944 else if ((TARGET_H8300SX
|| (regno
& 1) == 1)
945 && ((saved_regs
<< 1 >> regno
) & 0x03) == 0x03)
949 /* See if this pop would be the last insn before the return.
950 If so, use rte/l or rts/l instead of pop or ldm.l. */
952 && !frame_pointer_needed
954 && (saved_regs
& ((1 << (regno
- n_regs
+ 1)) - 1)) == 0)
957 h8300_push_pop (regno
- n_regs
+ 1, n_regs
, true, returned_p
);
961 /* Pop frame pointer if we had one. */
962 if (frame_pointer_needed
)
966 h8300_push_pop (HARD_FRAME_POINTER_REGNUM
, 1, true, returned_p
);
970 emit_jump_insn (ret_rtx
);
973 /* Return nonzero if the current function is an interrupt
977 h8300_current_function_interrupt_function_p (void)
979 return (h8300_interrupt_function_p (current_function_decl
));
983 h8300_current_function_monitor_function_p ()
985 return (h8300_monitor_function_p (current_function_decl
));
988 /* Output assembly code for the start of the file. */
991 h8300_file_start (void)
993 default_file_start ();
996 fputs (TARGET_NORMAL_MODE
? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file
);
997 else if (TARGET_H8300S
)
998 fputs (TARGET_NORMAL_MODE
? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file
);
999 else if (TARGET_H8300H
)
1000 fputs (TARGET_NORMAL_MODE
? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file
);
1003 /* Output assembly language code for the end of file. */
1006 h8300_file_end (void)
1008 fputs ("\t.end\n", asm_out_file
);
1011 /* Split an add of a small constant into two adds/subs insns.
1013 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec
1014 instead of adds/subs. */
1017 split_adds_subs (machine_mode mode
, rtx
*operands
)
1019 HOST_WIDE_INT val
= INTVAL (operands
[1]);
1020 rtx reg
= operands
[0];
1021 HOST_WIDE_INT sign
= 1;
1022 HOST_WIDE_INT amount
;
1023 rtx (*gen_add
) (rtx
, rtx
, rtx
);
1025 /* Force VAL to be positive so that we do not have to consider the
1036 gen_add
= gen_addhi3
;
1040 gen_add
= gen_addsi3
;
1047 /* Try different amounts in descending order. */
1048 for (amount
= (TARGET_H8300H
|| TARGET_H8300S
) ? 4 : 2;
1052 for (; val
>= amount
; val
-= amount
)
1053 emit_insn (gen_add (reg
, reg
, GEN_INT (sign
* amount
)));
1059 /* Handle machine specific pragmas for compatibility with existing
1060 compilers for the H8/300.
1062 pragma saveall generates prologue/epilogue code which saves and
1063 restores all the registers on function entry.
1065 pragma interrupt saves and restores all registers, and exits with
1066 an rte instruction rather than an rts. A pointer to a function
1067 with this attribute may be safely used in an interrupt vector. */
1070 h8300_pr_interrupt (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1072 pragma_interrupt
= 1;
1076 h8300_pr_saveall (struct cpp_reader
*pfile ATTRIBUTE_UNUSED
)
1081 /* If the next function argument with MODE and TYPE is to be passed in
1082 a register, return a reg RTX for the hard register in which to pass
1083 the argument. CUM represents the state after the last argument.
1084 If the argument is to be pushed, NULL_RTX is returned.
1086 On the H8/300 all normal args are pushed, unless -mquickcall in which
1087 case the first 3 arguments are passed in registers. */
1090 h8300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1091 const_tree type
, bool named
)
1093 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1095 static const char *const hand_list
[] = {
1114 rtx result
= NULL_RTX
;
1118 /* Never pass unnamed arguments in registers. */
1122 /* Pass 3 regs worth of data in regs when user asked on the command line. */
1123 if (TARGET_QUICKCALL
)
1126 /* If calling hand written assembler, use 4 regs of args. */
1129 const char * const *p
;
1131 fname
= XSTR (cum
->libcall
, 0);
1133 /* See if this libcall is one of the hand coded ones. */
1134 for (p
= hand_list
; *p
&& strcmp (*p
, fname
) != 0; p
++)
1145 if (mode
== BLKmode
)
1146 size
= int_size_in_bytes (type
);
1148 size
= GET_MODE_SIZE (mode
);
1150 if (size
+ cum
->nbytes
<= regpass
* UNITS_PER_WORD
1151 && cum
->nbytes
/ UNITS_PER_WORD
<= 3)
1152 result
= gen_rtx_REG (mode
, cum
->nbytes
/ UNITS_PER_WORD
);
1158 /* Update the data in CUM to advance over an argument
1159 of mode MODE and data type TYPE.
1160 (TYPE is null for libcalls where that information may not be available.) */
1163 h8300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1164 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1166 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1168 cum
->nbytes
+= (mode
!= BLKmode
1169 ? (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
1170 : (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
);
1174 /* Implements TARGET_REGISTER_MOVE_COST.
1176 Any SI register-to-register move may need to be reloaded,
1177 so inmplement h8300_register_move_cost to return > 2 so that reload never
1181 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1182 reg_class_t from
, reg_class_t to
)
1184 if (from
== MAC_REGS
|| to
== MAC_REG
)
1190 /* Compute the cost of an and insn. */
1193 h8300_and_costs (rtx x
)
1197 if (GET_MODE (x
) == QImode
)
1200 if (GET_MODE (x
) != HImode
1201 && GET_MODE (x
) != SImode
)
1205 operands
[1] = XEXP (x
, 0);
1206 operands
[2] = XEXP (x
, 1);
1208 return compute_logical_op_length (GET_MODE (x
), operands
) / 2;
1211 /* Compute the cost of a shift insn. */
1214 h8300_shift_costs (rtx x
)
1218 if (GET_MODE (x
) != QImode
1219 && GET_MODE (x
) != HImode
1220 && GET_MODE (x
) != SImode
)
1225 operands
[2] = XEXP (x
, 1);
1227 return compute_a_shift_length (NULL
, operands
) / 2;
1230 /* Worker function for TARGET_RTX_COSTS. */
1233 h8300_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
1234 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
1236 int code
= GET_CODE (x
);
1238 if (TARGET_H8300SX
&& outer_code
== MEM
)
1240 /* Estimate the number of execution states needed to calculate
1242 if (register_operand (x
, VOIDmode
)
1243 || GET_CODE (x
) == POST_INC
1244 || GET_CODE (x
) == POST_DEC
1248 *total
= COSTS_N_INSNS (1);
1256 HOST_WIDE_INT n
= INTVAL (x
);
1260 /* Constant operands need the same number of processor
1261 states as register operands. Although we could try to
1262 use a size-based cost for !speed, the lack of
1263 of a mode makes the results very unpredictable. */
1267 if (-4 <= n
&& n
<= 4)
1278 *total
= 0 + (outer_code
== SET
);
1282 if (TARGET_H8300H
|| TARGET_H8300S
)
1283 *total
= 0 + (outer_code
== SET
);
1298 /* See comment for CONST_INT. */
1310 if (XEXP (x
, 1) == const0_rtx
)
1315 if (!h8300_dst_operand (XEXP (x
, 0), VOIDmode
)
1316 || !h8300_src_operand (XEXP (x
, 1), VOIDmode
))
1318 *total
= COSTS_N_INSNS (h8300_and_costs (x
));
1321 /* We say that MOD and DIV are so expensive because otherwise we'll
1322 generate some really horrible code for division of a power of two. */
1328 switch (GET_MODE (x
))
1332 *total
= COSTS_N_INSNS (!speed
? 4 : 10);
1336 *total
= COSTS_N_INSNS (!speed
? 4 : 18);
1342 *total
= COSTS_N_INSNS (12);
1347 switch (GET_MODE (x
))
1351 *total
= COSTS_N_INSNS (2);
1355 *total
= COSTS_N_INSNS (5);
1361 *total
= COSTS_N_INSNS (4);
1367 if (h8sx_binary_shift_operator (x
, VOIDmode
))
1369 *total
= COSTS_N_INSNS (2);
1372 else if (h8sx_unary_shift_operator (x
, VOIDmode
))
1374 *total
= COSTS_N_INSNS (1);
1377 *total
= COSTS_N_INSNS (h8300_shift_costs (x
));
1382 if (GET_MODE (x
) == HImode
)
1389 *total
= COSTS_N_INSNS (1);
1394 /* Documentation for the machine specific operand escapes:
1396 'E' like s but negative.
1397 'F' like t but negative.
1398 'G' constant just the negative
1399 'R' print operand as a byte:8 address if appropriate, else fall back to
1401 'S' print operand as a long word
1402 'T' print operand as a word
1403 'V' find the set bit, and print its number.
1404 'W' find the clear bit, and print its number.
1405 'X' print operand as a byte
1406 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8.
1407 If this operand isn't a register, fall back to 'R' handling.
1409 'c' print the opcode corresponding to rtl
1410 'e' first word of 32-bit value - if reg, then least reg. if mem
1411 then least. if const then most sig word
1412 'f' second word of 32-bit value - if reg, then biggest reg. if mem
1413 then +2. if const then least sig word
1414 'j' print operand as condition code.
1415 'k' print operand as reverse condition code.
1416 'm' convert an integer operand to a size suffix (.b, .w or .l)
1417 'o' print an integer without a leading '#'
1418 's' print as low byte of 16-bit value
1419 't' print as high byte of 16-bit value
1420 'w' print as low byte of 32-bit value
1421 'x' print as 2nd byte of 32-bit value
1422 'y' print as 3rd byte of 32-bit value
1423 'z' print as msb of 32-bit value
1426 /* Return assembly language string which identifies a comparison type. */
1429 cond_string (enum rtx_code code
)
1458 /* Print operand X using operand code CODE to assembly language output file
1462 h8300_print_operand (FILE *file
, rtx x
, int code
)
1464 /* This is used for communication between codes V,W,Z and Y. */
1470 if (h8300_constant_length (x
) == 2)
1471 fprintf (file
, ":16");
1473 fprintf (file
, ":32");
1476 switch (GET_CODE (x
))
1479 fprintf (file
, "%sl", names_big
[REGNO (x
)]);
1482 fprintf (file
, "#%ld", (-INTVAL (x
)) & 0xff);
1489 switch (GET_CODE (x
))
1492 fprintf (file
, "%sh", names_big
[REGNO (x
)]);
1495 fprintf (file
, "#%ld", ((-INTVAL (x
)) & 0xff00) >> 8);
1502 gcc_assert (GET_CODE (x
) == CONST_INT
);
1503 fprintf (file
, "#%ld", 0xff & (-INTVAL (x
)));
1506 if (GET_CODE (x
) == REG
)
1507 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1512 if (GET_CODE (x
) == REG
)
1513 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1518 bitint
= (INTVAL (x
) & 0xffff);
1519 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1)
1520 bitint
= exact_log2 (bitint
& 0xff);
1522 bitint
= exact_log2 ((bitint
>> 8) & 0xff);
1523 gcc_assert (bitint
>= 0);
1524 fprintf (file
, "#%d", bitint
);
1527 bitint
= ((~INTVAL (x
)) & 0xffff);
1528 if ((exact_log2 ((bitint
>> 8) & 0xff)) == -1 )
1529 bitint
= exact_log2 (bitint
& 0xff);
1531 bitint
= (exact_log2 ((bitint
>> 8) & 0xff));
1532 gcc_assert (bitint
>= 0);
1533 fprintf (file
, "#%d", bitint
);
1537 if (GET_CODE (x
) == REG
)
1538 fprintf (file
, "%s", byte_reg (x
, 0));
1543 gcc_assert (bitint
>= 0);
1544 if (GET_CODE (x
) == REG
)
1545 fprintf (file
, "%s%c", names_big
[REGNO (x
)], bitint
> 7 ? 'h' : 'l');
1547 h8300_print_operand (file
, x
, 'R');
1551 bitint
= INTVAL (x
);
1552 fprintf (file
, "#%d", bitint
& 7);
1555 switch (GET_CODE (x
))
1558 fprintf (file
, "or");
1561 fprintf (file
, "xor");
1564 fprintf (file
, "and");
1571 switch (GET_CODE (x
))
1575 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1577 fprintf (file
, "%s", names_upper_extended
[REGNO (x
)]);
1580 h8300_print_operand (file
, x
, 0);
1583 fprintf (file
, "#%ld", ((INTVAL (x
) >> 16) & 0xffff));
1588 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1589 fprintf (file
, "#%ld", ((val
>> 16) & 0xffff));
1598 switch (GET_CODE (x
))
1602 fprintf (file
, "%s", names_big
[REGNO (x
) + 1]);
1604 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1607 x
= adjust_address (x
, HImode
, 2);
1608 h8300_print_operand (file
, x
, 0);
1611 fprintf (file
, "#%ld", INTVAL (x
) & 0xffff);
1616 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1617 fprintf (file
, "#%ld", (val
& 0xffff));
1625 fputs (cond_string (GET_CODE (x
)), file
);
1628 fputs (cond_string (reverse_condition (GET_CODE (x
))), file
);
1631 gcc_assert (GET_CODE (x
) == CONST_INT
);
1651 h8300_print_operand_address (file
, VOIDmode
, x
);
1654 if (GET_CODE (x
) == CONST_INT
)
1655 fprintf (file
, "#%ld", (INTVAL (x
)) & 0xff);
1657 fprintf (file
, "%s", byte_reg (x
, 0));
1660 if (GET_CODE (x
) == CONST_INT
)
1661 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1663 fprintf (file
, "%s", byte_reg (x
, 1));
1666 if (GET_CODE (x
) == CONST_INT
)
1667 fprintf (file
, "#%ld", INTVAL (x
) & 0xff);
1669 fprintf (file
, "%s",
1670 byte_reg (x
, TARGET_H8300
? 2 : 0));
1673 if (GET_CODE (x
) == CONST_INT
)
1674 fprintf (file
, "#%ld", (INTVAL (x
) >> 8) & 0xff);
1676 fprintf (file
, "%s",
1677 byte_reg (x
, TARGET_H8300
? 3 : 1));
1680 if (GET_CODE (x
) == CONST_INT
)
1681 fprintf (file
, "#%ld", (INTVAL (x
) >> 16) & 0xff);
1683 fprintf (file
, "%s", byte_reg (x
, 0));
1686 if (GET_CODE (x
) == CONST_INT
)
1687 fprintf (file
, "#%ld", (INTVAL (x
) >> 24) & 0xff);
1689 fprintf (file
, "%s", byte_reg (x
, 1));
1694 switch (GET_CODE (x
))
1697 switch (GET_MODE (x
))
1700 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */
1701 fprintf (file
, "%s", byte_reg (x
, 0));
1702 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */
1703 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1707 fprintf (file
, "%s", names_big
[REGNO (x
)]);
1711 fprintf (file
, "%s", names_extended
[REGNO (x
)]);
1720 rtx addr
= XEXP (x
, 0);
1722 fprintf (file
, "@");
1723 output_address (GET_MODE (x
), addr
);
1725 /* Add a length suffix to constant addresses. Although this
1726 is often unnecessary, it helps to avoid ambiguity in the
1727 syntax of mova. If we wrote an insn like:
1729 mova/w.l @(1,@foo.b),er0
1731 then .b would be considered part of the symbol name.
1732 Adding a length after foo will avoid this. */
1733 if (CONSTANT_P (addr
))
1737 /* Used for mov.b and bit operations. */
1738 if (h8300_eightbit_constant_address_p (addr
))
1740 fprintf (file
, ":8");
1744 /* Fall through. We should not get here if we are
1745 processing bit operations on H8/300 or H8/300H
1746 because 'U' constraint does not allow bit
1747 operations on the tiny area on these machines. */
1752 if (h8300_constant_length (addr
) == 2)
1753 fprintf (file
, ":16");
1755 fprintf (file
, ":32");
1767 fprintf (file
, "#");
1768 h8300_print_operand_address (file
, VOIDmode
, x
);
1773 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), val
);
1774 fprintf (file
, "#%ld", val
);
1783 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
1786 h8300_print_operand_punct_valid_p (unsigned char code
)
1788 return (code
== '#');
1791 /* Output assembly language output for the address ADDR to FILE. */
1794 h8300_print_operand_address (FILE *file
, machine_mode mode
, rtx addr
)
1799 switch (GET_CODE (addr
))
1802 fprintf (file
, "%s", h8_reg_names
[REGNO (addr
)]);
1806 fprintf (file
, "-%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1810 fprintf (file
, "%s+", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1814 fprintf (file
, "+%s", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1818 fprintf (file
, "%s-", h8_reg_names
[REGNO (XEXP (addr
, 0))]);
1822 fprintf (file
, "(");
1824 index
= h8300_get_index (XEXP (addr
, 0), VOIDmode
, &size
);
1825 if (GET_CODE (index
) == REG
)
1828 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1829 fprintf (file
, ",");
1833 h8300_print_operand_address (file
, mode
, index
);
1837 h8300_print_operand (file
, index
, 'X');
1842 h8300_print_operand (file
, index
, 'T');
1847 h8300_print_operand (file
, index
, 'S');
1851 /* h8300_print_operand_address (file, XEXP (addr, 0)); */
1856 h8300_print_operand_address (file
, mode
, XEXP (addr
, 0));
1857 fprintf (file
, "+");
1858 h8300_print_operand_address (file
, mode
, XEXP (addr
, 1));
1860 fprintf (file
, ")");
1865 /* Since the H8/300 only has 16-bit pointers, negative values are also
1866 those >= 32768. This happens for example with pointer minus a
1867 constant. We don't want to turn (char *p - 2) into
1868 (char *p + 65534) because loop unrolling can build upon this
1869 (IE: char *p + 131068). */
1870 int n
= INTVAL (addr
);
1872 n
= (int) (short) n
;
1873 fprintf (file
, "%d", n
);
1878 output_addr_const (file
, addr
);
1883 /* Output all insn addresses and their sizes into the assembly language
1884 output file. This is helpful for debugging whether the length attributes
1885 in the md file are correct. This is not meant to be a user selectable
1889 final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
1890 int num_operands ATTRIBUTE_UNUSED
)
1892 /* This holds the last insn address. */
1893 static int last_insn_address
= 0;
1895 const int uid
= INSN_UID (insn
);
1897 if (TARGET_ADDRESSES
)
1899 fprintf (asm_out_file
, "; 0x%x %d\n", INSN_ADDRESSES (uid
),
1900 INSN_ADDRESSES (uid
) - last_insn_address
);
1901 last_insn_address
= INSN_ADDRESSES (uid
);
1905 /* Prepare for an SI sized move. */
1908 h8300_expand_movsi (rtx operands
[])
1910 rtx src
= operands
[1];
1911 rtx dst
= operands
[0];
1912 if (!reload_in_progress
&& !reload_completed
)
1914 if (!register_operand (dst
, GET_MODE (dst
)))
1916 rtx tmp
= gen_reg_rtx (GET_MODE (dst
));
1917 emit_move_insn (tmp
, src
);
1924 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1925 Frame pointer elimination is automatically handled.
1927 For the h8300, if frame pointer elimination is being done, we would like to
1928 convert ap and rp into sp, not fp.
1930 All other eliminations are valid. */
1933 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
1935 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
1938 /* Conditionally modify register usage based on target flags. */
1941 h8300_conditional_register_usage (void)
1944 fixed_regs
[MAC_REG
] = call_used_regs
[MAC_REG
] = 1;
1947 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET).
1948 Define the offset between two registers, one to be eliminated, and
1949 the other its replacement, at the start of a routine. */
1952 h8300_initial_elimination_offset (int from
, int to
)
1954 /* The number of bytes that the return address takes on the stack. */
1955 int pc_size
= POINTER_SIZE
/ BITS_PER_UNIT
;
1957 /* The number of bytes that the saved frame pointer takes on the stack. */
1958 int fp_size
= frame_pointer_needed
* UNITS_PER_WORD
;
1960 /* The number of bytes that the saved registers, excluding the frame
1961 pointer, take on the stack. */
1962 int saved_regs_size
= 0;
1964 /* The number of bytes that the locals takes on the stack. */
1965 int frame_size
= round_frame_size (get_frame_size ());
1969 for (regno
= 0; regno
<= HARD_FRAME_POINTER_REGNUM
; regno
++)
1970 if (WORD_REG_USED (regno
))
1971 saved_regs_size
+= UNITS_PER_WORD
;
1973 /* Adjust saved_regs_size because the above loop took the frame
1974 pointer int account. */
1975 saved_regs_size
-= fp_size
;
1979 case HARD_FRAME_POINTER_REGNUM
:
1982 case ARG_POINTER_REGNUM
:
1983 return pc_size
+ fp_size
;
1984 case RETURN_ADDRESS_POINTER_REGNUM
:
1986 case FRAME_POINTER_REGNUM
:
1987 return -saved_regs_size
;
1992 case STACK_POINTER_REGNUM
:
1995 case ARG_POINTER_REGNUM
:
1996 return pc_size
+ saved_regs_size
+ frame_size
;
1997 case RETURN_ADDRESS_POINTER_REGNUM
:
1998 return saved_regs_size
+ frame_size
;
1999 case FRAME_POINTER_REGNUM
:
2011 /* Worker function for RETURN_ADDR_RTX. */
2014 h8300_return_addr_rtx (int count
, rtx frame
)
2019 ret
= gen_rtx_MEM (Pmode
,
2020 gen_rtx_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
));
2021 else if (flag_omit_frame_pointer
)
2024 ret
= gen_rtx_MEM (Pmode
,
2025 memory_address (Pmode
,
2026 plus_constant (Pmode
, frame
,
2028 set_mem_alias_set (ret
, get_frame_alias_set ());
2032 /* Update the condition code from the insn. */
2035 notice_update_cc (rtx body
, rtx_insn
*insn
)
2039 switch (get_attr_cc (insn
))
2042 /* Insn does not affect CC at all. */
2046 /* Insn does not change CC, but the 0'th operand has been changed. */
2047 if (cc_status
.value1
!= 0
2048 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
2049 cc_status
.value1
= 0;
2050 if (cc_status
.value2
!= 0
2051 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value2
))
2052 cc_status
.value2
= 0;
2056 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
2057 The V flag is unusable. The C flag may or may not be known but
2058 that's ok because alter_cond will change tests to use EQ/NE. */
2060 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
2061 set
= single_set (insn
);
2062 cc_status
.value1
= SET_SRC (set
);
2063 if (SET_DEST (set
) != cc0_rtx
)
2064 cc_status
.value2
= SET_DEST (set
);
2068 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
2069 The C flag may or may not be known but that's ok because
2070 alter_cond will change tests to use EQ/NE. */
2072 cc_status
.flags
|= CC_NO_CARRY
;
2073 set
= single_set (insn
);
2074 cc_status
.value1
= SET_SRC (set
);
2075 if (SET_DEST (set
) != cc0_rtx
)
2077 /* If the destination is STRICT_LOW_PART, strip off
2079 if (GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
2080 cc_status
.value2
= XEXP (SET_DEST (set
), 0);
2082 cc_status
.value2
= SET_DEST (set
);
2087 /* The insn is a compare instruction. */
2089 cc_status
.value1
= SET_SRC (body
);
2093 /* Insn doesn't leave CC in a usable state. */
2099 /* Given that X occurs in an address of the form (plus X constant),
2100 return the part of X that is expected to be a register. There are
2101 four kinds of addressing mode to recognize:
2108 If SIZE is nonnull, and the address is one of the last three forms,
2109 set *SIZE to the index multiplication factor. Set it to 0 for
2110 plain @(dd,Rn) addresses.
2112 MODE is the mode of the value being accessed. It can be VOIDmode
2113 if the address is known to be valid, but its mode is unknown. */
2116 h8300_get_index (rtx x
, machine_mode mode
, int *size
)
2123 factor
= (mode
== VOIDmode
? 0 : GET_MODE_SIZE (mode
));
2126 && (mode
== VOIDmode
2127 || GET_MODE_CLASS (mode
) == MODE_INT
2128 || GET_MODE_CLASS (mode
) == MODE_FLOAT
))
2130 if (factor
<= 1 && GET_CODE (x
) == ZERO_EXTEND
)
2132 /* When accessing byte-sized values, the index can be
2133 a zero-extended QImode or HImode register. */
2134 *size
= GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)));
2139 /* We're looking for addresses of the form:
2142 or (mult (zero_extend X) I)
2144 where I is the size of the operand being accessed.
2145 The canonical form of the second expression is:
2147 (and (mult (subreg X) I) J)
2149 where J == GET_MODE_MASK (GET_MODE (X)) * I. */
2152 if (GET_CODE (x
) == AND
2153 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2155 || INTVAL (XEXP (x
, 1)) == 0xff * factor
2156 || INTVAL (XEXP (x
, 1)) == 0xffff * factor
))
2158 index
= XEXP (x
, 0);
2159 *size
= (INTVAL (XEXP (x
, 1)) >= 0xffff ? 2 : 1);
2167 if (GET_CODE (index
) == MULT
2168 && GET_CODE (XEXP (index
, 1)) == CONST_INT
2169 && (factor
== 0 || factor
== INTVAL (XEXP (index
, 1))))
2170 return XEXP (index
, 0);
2177 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P.
2179 On the H8/300, the predecrement and postincrement address depend thus
2180 (the amount of decrement or increment being the length of the operand). */
2183 h8300_mode_dependent_address_p (const_rtx addr
,
2184 addr_space_t as ATTRIBUTE_UNUSED
)
2186 if (GET_CODE (addr
) == PLUS
2187 && h8300_get_index (XEXP (addr
, 0), VOIDmode
, 0) != XEXP (addr
, 0))
2193 static const h8300_length_table addb_length_table
=
2195 /* #xx Rs @aa @Rs @xx */
2196 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */
2197 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */
2198 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */
2199 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */
2202 static const h8300_length_table addw_length_table
=
2204 /* #xx Rs @aa @Rs @xx */
2205 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */
2206 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */
2207 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */
2208 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */
2211 static const h8300_length_table addl_length_table
=
2213 /* #xx Rs @aa @Rs @xx */
2214 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */
2215 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */
2216 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */
2217 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */
2220 #define logicb_length_table addb_length_table
2221 #define logicw_length_table addw_length_table
2223 static const h8300_length_table logicl_length_table
=
2225 /* #xx Rs @aa @Rs @xx */
2226 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */
2227 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */
2228 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */
2229 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */
2232 static const h8300_length_table movb_length_table
=
2234 /* #xx Rs @aa @Rs @xx */
2235 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */
2236 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */
2237 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */
2238 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */
2241 #define movw_length_table movb_length_table
2243 static const h8300_length_table movl_length_table
=
2245 /* #xx Rs @aa @Rs @xx */
2246 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */
2247 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */
2248 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */
2249 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */
2252 /* Return the size of the given address or displacement constant. */
2255 h8300_constant_length (rtx constant
)
2257 /* Check for (@d:16,Reg). */
2258 if (GET_CODE (constant
) == CONST_INT
2259 && IN_RANGE (INTVAL (constant
), -0x8000, 0x7fff))
2262 /* Check for (@d:16,Reg) in cases where the displacement is
2263 an absolute address. */
2264 if (Pmode
== HImode
|| h8300_tiny_constant_address_p (constant
))
2270 /* Return the size of a displacement field in address ADDR, which should
2271 have the form (plus X constant). SIZE is the number of bytes being
2275 h8300_displacement_length (rtx addr
, int size
)
2279 offset
= XEXP (addr
, 1);
2281 /* Check for @(d:2,Reg). */
2282 if (register_operand (XEXP (addr
, 0), VOIDmode
)
2283 && GET_CODE (offset
) == CONST_INT
2284 && (INTVAL (offset
) == size
2285 || INTVAL (offset
) == size
* 2
2286 || INTVAL (offset
) == size
* 3))
2289 return h8300_constant_length (offset
);
2292 /* Store the class of operand OP in *OPCLASS and return the length of any
2293 extra operand fields. SIZE is the number of bytes in OP. OPCLASS
2294 can be null if only the length is needed. */
2297 h8300_classify_operand (rtx op
, int size
, enum h8300_operand_class
*opclass
)
2299 enum h8300_operand_class dummy
;
2304 if (CONSTANT_P (op
))
2306 *opclass
= H8OP_IMMEDIATE
;
2308 /* Byte-sized immediates are stored in the opcode fields. */
2312 /* If this is a 32-bit instruction, see whether the constant
2313 will fit into a 16-bit immediate field. */
2316 && GET_CODE (op
) == CONST_INT
2317 && IN_RANGE (INTVAL (op
), 0, 0xffff))
2322 else if (GET_CODE (op
) == MEM
)
2325 if (CONSTANT_P (op
))
2327 *opclass
= H8OP_MEM_ABSOLUTE
;
2328 return h8300_constant_length (op
);
2330 else if (GET_CODE (op
) == PLUS
&& CONSTANT_P (XEXP (op
, 1)))
2332 *opclass
= H8OP_MEM_COMPLEX
;
2333 return h8300_displacement_length (op
, size
);
2335 else if (GET_RTX_CLASS (GET_CODE (op
)) == RTX_AUTOINC
)
2337 *opclass
= H8OP_MEM_COMPLEX
;
2340 else if (register_operand (op
, VOIDmode
))
2342 *opclass
= H8OP_MEM_BASE
;
2346 gcc_assert (register_operand (op
, VOIDmode
));
2347 *opclass
= H8OP_REGISTER
;
2351 /* Return the length of the instruction described by TABLE given that
2352 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand
2353 and OP2 must be an h8300_src_operand. */
2356 h8300_length_from_table (rtx op1
, rtx op2
, const h8300_length_table
*table
)
2358 enum h8300_operand_class op1_class
, op2_class
;
2359 unsigned int size
, immediate_length
;
2361 size
= GET_MODE_SIZE (GET_MODE (op1
));
2362 immediate_length
= (h8300_classify_operand (op1
, size
, &op1_class
)
2363 + h8300_classify_operand (op2
, size
, &op2_class
));
2364 return immediate_length
+ (*table
)[op1_class
- 1][op2_class
];
2367 /* Return the length of a unary instruction such as neg or not given that
2368 its operand is OP. */
2371 h8300_unary_length (rtx op
)
2373 enum h8300_operand_class opclass
;
2374 unsigned int size
, operand_length
;
2376 size
= GET_MODE_SIZE (GET_MODE (op
));
2377 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2384 return (size
== 4 ? 6 : 4);
2386 case H8OP_MEM_ABSOLUTE
:
2387 return operand_length
+ (size
== 4 ? 6 : 4);
2389 case H8OP_MEM_COMPLEX
:
2390 return operand_length
+ 6;
2397 /* Likewise short immediate instructions such as add.w #xx:3,OP. */
2400 h8300_short_immediate_length (rtx op
)
2402 enum h8300_operand_class opclass
;
2403 unsigned int size
, operand_length
;
2405 size
= GET_MODE_SIZE (GET_MODE (op
));
2406 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2414 case H8OP_MEM_ABSOLUTE
:
2415 case H8OP_MEM_COMPLEX
:
2416 return 4 + operand_length
;
2423 /* Likewise bitfield load and store instructions. */
2426 h8300_bitfield_length (rtx op
, rtx op2
)
2428 enum h8300_operand_class opclass
;
2429 unsigned int size
, operand_length
;
2431 if (GET_CODE (op
) == REG
)
2433 gcc_assert (GET_CODE (op
) != REG
);
2435 size
= GET_MODE_SIZE (GET_MODE (op
));
2436 operand_length
= h8300_classify_operand (op
, size
, &opclass
);
2441 case H8OP_MEM_ABSOLUTE
:
2442 case H8OP_MEM_COMPLEX
:
2443 return 4 + operand_length
;
2450 /* Calculate the length of general binary instruction INSN using TABLE. */
2453 h8300_binary_length (rtx_insn
*insn
, const h8300_length_table
*table
)
2457 set
= single_set (insn
);
2460 if (BINARY_P (SET_SRC (set
)))
2461 return h8300_length_from_table (XEXP (SET_SRC (set
), 0),
2462 XEXP (SET_SRC (set
), 1), table
);
2465 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set
))) == RTX_TERNARY
);
2466 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set
), 1), 0),
2467 XEXP (XEXP (SET_SRC (set
), 1), 1),
2472 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte
2473 memory reference and either (1) it has the form @(d:16,Rn) or
2474 (2) its address has the code given by INC_CODE. */
2477 h8300_short_move_mem_p (rtx op
, enum rtx_code inc_code
)
2482 if (GET_CODE (op
) != MEM
)
2485 addr
= XEXP (op
, 0);
2486 size
= GET_MODE_SIZE (GET_MODE (op
));
2487 if (size
!= 1 && size
!= 2)
2490 return (GET_CODE (addr
) == inc_code
2491 || (GET_CODE (addr
) == PLUS
2492 && GET_CODE (XEXP (addr
, 0)) == REG
2493 && h8300_displacement_length (addr
, size
) == 2));
2496 /* Calculate the length of move instruction INSN using the given length
2497 table. Although the tables are correct for most cases, there is some
2498 irregularity in the length of mov.b and mov.w. The following forms:
2505 are two bytes shorter than most other "mov Rs, @complex" or
2506 "mov @complex,Rd" combinations. */
2509 h8300_move_length (rtx
*operands
, const h8300_length_table
*table
)
2513 size
= h8300_length_from_table (operands
[0], operands
[1], table
);
2514 if (REG_P (operands
[0]) && h8300_short_move_mem_p (operands
[1], POST_INC
))
2516 if (REG_P (operands
[1]) && h8300_short_move_mem_p (operands
[0], PRE_DEC
))
2521 /* Return the length of a mova instruction with the given operands.
2522 DEST is the register destination, SRC is the source address and
2523 OFFSET is the 16-bit or 32-bit displacement. */
2526 h8300_mova_length (rtx dest
, rtx src
, rtx offset
)
2531 + h8300_constant_length (offset
)
2532 + h8300_classify_operand (src
, GET_MODE_SIZE (GET_MODE (src
)), 0));
2533 if (!REG_P (dest
) || !REG_P (src
) || REGNO (src
) != REGNO (dest
))
2538 /* Compute the length of INSN based on its length_table attribute.
2539 OPERANDS is the array of its operands. */
2542 h8300_insn_length_from_table (rtx_insn
*insn
, rtx
* operands
)
2544 switch (get_attr_length_table (insn
))
2546 case LENGTH_TABLE_NONE
:
2549 case LENGTH_TABLE_ADDB
:
2550 return h8300_binary_length (insn
, &addb_length_table
);
2552 case LENGTH_TABLE_ADDW
:
2553 return h8300_binary_length (insn
, &addw_length_table
);
2555 case LENGTH_TABLE_ADDL
:
2556 return h8300_binary_length (insn
, &addl_length_table
);
2558 case LENGTH_TABLE_LOGICB
:
2559 return h8300_binary_length (insn
, &logicb_length_table
);
2561 case LENGTH_TABLE_MOVB
:
2562 return h8300_move_length (operands
, &movb_length_table
);
2564 case LENGTH_TABLE_MOVW
:
2565 return h8300_move_length (operands
, &movw_length_table
);
2567 case LENGTH_TABLE_MOVL
:
2568 return h8300_move_length (operands
, &movl_length_table
);
2570 case LENGTH_TABLE_MOVA
:
2571 return h8300_mova_length (operands
[0], operands
[1], operands
[2]);
2573 case LENGTH_TABLE_MOVA_ZERO
:
2574 return h8300_mova_length (operands
[0], operands
[1], const0_rtx
);
2576 case LENGTH_TABLE_UNARY
:
2577 return h8300_unary_length (operands
[0]);
2579 case LENGTH_TABLE_MOV_IMM4
:
2580 return 2 + h8300_classify_operand (operands
[0], 0, 0);
2582 case LENGTH_TABLE_SHORT_IMMEDIATE
:
2583 return h8300_short_immediate_length (operands
[0]);
2585 case LENGTH_TABLE_BITFIELD
:
2586 return h8300_bitfield_length (operands
[0], operands
[1]);
2588 case LENGTH_TABLE_BITBRANCH
:
2589 return h8300_bitfield_length (operands
[1], operands
[2]) - 2;
2596 /* Return true if LHS and RHS are memory references that can be mapped
2597 to the same h8sx assembly operand. LHS appears as the destination of
2598 an instruction and RHS appears as a source.
2600 Three cases are allowed:
2602 - RHS is @+Rn or @-Rn, LHS is @Rn
2603 - RHS is @Rn, LHS is @Rn+ or @Rn-
2604 - RHS and LHS have the same address and neither has side effects. */
2607 h8sx_mergeable_memrefs_p (rtx lhs
, rtx rhs
)
2609 if (GET_CODE (rhs
) == MEM
&& GET_CODE (lhs
) == MEM
)
2611 rhs
= XEXP (rhs
, 0);
2612 lhs
= XEXP (lhs
, 0);
2614 if (GET_CODE (rhs
) == PRE_INC
|| GET_CODE (rhs
) == PRE_DEC
)
2615 return rtx_equal_p (XEXP (rhs
, 0), lhs
);
2617 if (GET_CODE (lhs
) == POST_INC
|| GET_CODE (lhs
) == POST_DEC
)
2618 return rtx_equal_p (rhs
, XEXP (lhs
, 0));
2620 if (rtx_equal_p (rhs
, lhs
))
2626 /* Return true if OPERANDS[1] can be mapped to the same assembly
2627 operand as OPERANDS[0]. */
2630 h8300_operands_match_p (rtx
*operands
)
2632 if (register_operand (operands
[0], VOIDmode
)
2633 && register_operand (operands
[1], VOIDmode
))
2636 if (h8sx_mergeable_memrefs_p (operands
[0], operands
[1]))
2642 /* Try using movmd to move LENGTH bytes from memory region SRC to memory
2643 region DEST. The two regions do not overlap and have the common
2644 alignment given by ALIGNMENT. Return true on success.
2646 Using movmd for variable-length moves seems to involve some
2647 complex trade-offs. For instance:
2649 - Preparing for a movmd instruction is similar to preparing
2650 for a memcpy. The main difference is that the arguments
2651 are moved into er4, er5 and er6 rather than er0, er1 and er2.
2653 - Since movmd clobbers the frame pointer, we need to save
2654 and restore it somehow when frame_pointer_needed. This can
2655 sometimes make movmd sequences longer than calls to memcpy().
2657 - The counter register is 16 bits, so the instruction is only
2658 suitable for variable-length moves when sizeof (size_t) == 2.
2659 That's only true in normal mode.
2661 - We will often lack static alignment information. Falling back
2662 on movmd.b would likely be slower than calling memcpy(), at least
2665 This function therefore only uses movmd when the length is a
2666 known constant, and only then if -fomit-frame-pointer is in
2667 effect or if we're not optimizing for size.
2669 At the moment the function uses movmd for all in-range constants,
2670 but it might be better to fall back on memcpy() for large moves
2671 if ALIGNMENT == 1. */
2674 h8sx_emit_movmd (rtx dest
, rtx src
, rtx length
,
2675 HOST_WIDE_INT alignment
)
2677 if (!flag_omit_frame_pointer
&& optimize_size
)
2680 if (GET_CODE (length
) == CONST_INT
)
2682 rtx dest_reg
, src_reg
, first_dest
, first_src
;
2686 /* Use movmd.l if the alignment allows it, otherwise fall back
2688 factor
= (alignment
>= 2 ? 4 : 1);
2690 /* Make sure the length is within range. We can handle counter
2691 values up to 65536, although HImode truncation will make
2692 the count appear negative in rtl dumps. */
2693 n
= INTVAL (length
);
2694 if (n
<= 0 || n
/ factor
> 65536)
2697 /* Create temporary registers for the source and destination
2698 pointers. Initialize them to the start of each region. */
2699 dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
2700 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2702 /* Create references to the movmd source and destination blocks. */
2703 first_dest
= replace_equiv_address (dest
, dest_reg
);
2704 first_src
= replace_equiv_address (src
, src_reg
);
2706 set_mem_size (first_dest
, n
& -factor
);
2707 set_mem_size (first_src
, n
& -factor
);
2709 length
= copy_to_mode_reg (HImode
, gen_int_mode (n
/ factor
, HImode
));
2710 emit_insn (gen_movmd (first_dest
, first_src
, length
, GEN_INT (factor
)));
2712 if ((n
& -factor
) != n
)
2714 /* Move SRC and DEST past the region we just copied.
2715 This is done to update the memory attributes. */
2716 dest
= adjust_address (dest
, BLKmode
, n
& -factor
);
2717 src
= adjust_address (src
, BLKmode
, n
& -factor
);
2719 /* Replace the addresses with the source and destination
2720 registers, which movmd has left with the right values. */
2721 dest
= replace_equiv_address (dest
, dest_reg
);
2722 src
= replace_equiv_address (src
, src_reg
);
2724 /* Mop up the left-over bytes. */
2726 emit_move_insn (adjust_address (dest
, HImode
, 0),
2727 adjust_address (src
, HImode
, 0));
2729 emit_move_insn (adjust_address (dest
, QImode
, n
& 2),
2730 adjust_address (src
, QImode
, n
& 2));
2737 /* Move ADDR into er6 after pushing its old value onto the stack. */
2740 h8300_swap_into_er6 (rtx addr
)
2742 rtx insn
= push (HARD_FRAME_POINTER_REGNUM
, false);
2743 if (frame_pointer_needed
)
2744 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2745 plus_constant (Pmode
, gen_rtx_MEM (Pmode
, stack_pointer_rtx
),
2746 2 * UNITS_PER_WORD
));
2748 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2749 gen_rtx_SET (stack_pointer_rtx
,
2750 plus_constant (Pmode
, stack_pointer_rtx
, 4)));
2752 emit_move_insn (hard_frame_pointer_rtx
, addr
);
2753 if (REGNO (addr
) == SP_REG
)
2754 emit_move_insn (hard_frame_pointer_rtx
,
2755 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2756 GET_MODE_SIZE (word_mode
)));
2759 /* Move the current value of er6 into ADDR and pop its old value
2763 h8300_swap_out_of_er6 (rtx addr
)
2767 if (REGNO (addr
) != SP_REG
)
2768 emit_move_insn (addr
, hard_frame_pointer_rtx
);
2770 insn
= pop (HARD_FRAME_POINTER_REGNUM
);
2771 if (frame_pointer_needed
)
2772 add_reg_note (insn
, REG_CFA_DEF_CFA
,
2773 plus_constant (Pmode
, hard_frame_pointer_rtx
,
2774 2 * UNITS_PER_WORD
));
2776 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
2777 gen_rtx_SET (stack_pointer_rtx
,
2778 plus_constant (Pmode
, stack_pointer_rtx
, -4)));
2781 /* Return the length of mov instruction. */
2784 compute_mov_length (rtx
*operands
)
2786 /* If the mov instruction involves a memory operand, we compute the
2787 length, assuming the largest addressing mode is used, and then
2788 adjust later in the function. Otherwise, we compute and return
2789 the exact length in one step. */
2790 machine_mode mode
= GET_MODE (operands
[0]);
2791 rtx dest
= operands
[0];
2792 rtx src
= operands
[1];
2795 if (GET_CODE (src
) == MEM
)
2796 addr
= XEXP (src
, 0);
2797 else if (GET_CODE (dest
) == MEM
)
2798 addr
= XEXP (dest
, 0);
2804 unsigned int base_length
;
2809 if (addr
== NULL_RTX
)
2812 /* The eightbit addressing is available only in QImode, so
2813 go ahead and take care of it. */
2814 if (h8300_eightbit_constant_address_p (addr
))
2821 if (addr
== NULL_RTX
)
2826 if (src
== const0_rtx
)
2836 if (addr
== NULL_RTX
)
2841 if (GET_CODE (src
) == CONST_INT
)
2843 if (src
== const0_rtx
)
2846 if ((INTVAL (src
) & 0xffff) == 0)
2849 if ((INTVAL (src
) & 0xffff) == 0)
2852 if ((INTVAL (src
) & 0xffff)
2853 == ((INTVAL (src
) >> 16) & 0xffff))
2863 if (addr
== NULL_RTX
)
2868 if (satisfies_constraint_G (src
))
2881 /* Adjust the length based on the addressing mode used.
2882 Specifically, we subtract the difference between the actual
2883 length and the longest one, which is @(d:16,Rs). For SImode
2884 and SFmode, we double the adjustment because two mov.w are
2885 used to do the job. */
2887 /* @Rs+ and @-Rd are 2 bytes shorter than the longest. */
2888 if (GET_CODE (addr
) == PRE_DEC
2889 || GET_CODE (addr
) == POST_INC
)
2891 if (mode
== QImode
|| mode
== HImode
)
2892 return base_length
- 2;
2894 /* In SImode and SFmode, we use two mov.w instructions, so
2895 double the adjustment. */
2896 return base_length
- 4;
2899 /* @Rs and @Rd are 2 bytes shorter than the longest. Note that
2900 in SImode and SFmode, the second mov.w involves an address
2901 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
2903 if (GET_CODE (addr
) == REG
)
2904 return base_length
- 2;
2910 unsigned int base_length
;
2915 if (addr
== NULL_RTX
)
2918 /* The eightbit addressing is available only in QImode, so
2919 go ahead and take care of it. */
2920 if (h8300_eightbit_constant_address_p (addr
))
2927 if (addr
== NULL_RTX
)
2932 if (src
== const0_rtx
)
2942 if (addr
== NULL_RTX
)
2946 if (REGNO (src
) == MAC_REG
|| REGNO (dest
) == MAC_REG
)
2952 if (GET_CODE (src
) == CONST_INT
)
2954 int val
= INTVAL (src
);
2959 if (val
== (val
& 0x00ff) || val
== (val
& 0xff00))
2962 switch (val
& 0xffffffff)
2983 if (addr
== NULL_RTX
)
2988 if (satisfies_constraint_G (src
))
3001 /* Adjust the length based on the addressing mode used.
3002 Specifically, we subtract the difference between the actual
3003 length and the longest one, which is @(d:24,ERs). */
3005 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */
3006 if (GET_CODE (addr
) == PRE_DEC
3007 || GET_CODE (addr
) == POST_INC
)
3008 return base_length
- 6;
3010 /* @ERs and @ERd are 6 bytes shorter than the longest. */
3011 if (GET_CODE (addr
) == REG
)
3012 return base_length
- 6;
3014 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
3016 if (GET_CODE (addr
) == PLUS
3017 && GET_CODE (XEXP (addr
, 0)) == REG
3018 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
3019 && INTVAL (XEXP (addr
, 1)) > -32768
3020 && INTVAL (XEXP (addr
, 1)) < 32767)
3021 return base_length
- 4;
3023 /* @aa:16 is 4 bytes shorter than the longest. */
3024 if (h8300_tiny_constant_address_p (addr
))
3025 return base_length
- 4;
3027 /* @aa:24 is 2 bytes shorter than the longest. */
3028 if (CONSTANT_P (addr
))
3029 return base_length
- 2;
3035 /* Output an addition insn. */
3038 output_plussi (rtx
*operands
)
3040 machine_mode mode
= GET_MODE (operands
[0]);
3042 gcc_assert (mode
== SImode
);
3046 if (GET_CODE (operands
[2]) == REG
)
3047 return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3049 if (GET_CODE (operands
[2]) == CONST_INT
)
3051 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3053 if ((n
& 0xffffff) == 0)
3054 return "add\t%z2,%z0";
3055 if ((n
& 0xffff) == 0)
3056 return "add\t%y2,%y0\n\taddx\t%z2,%z0";
3057 if ((n
& 0xff) == 0)
3058 return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3061 return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
3065 if (GET_CODE (operands
[2]) == CONST_INT
3066 && register_operand (operands
[1], VOIDmode
))
3068 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3070 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3071 return "add.l\t%S2,%S0";
3072 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3073 return "sub.l\t%G2,%S0";
3075 /* See if we can finish with 2 bytes. */
3077 switch ((unsigned int) intval
& 0xffffffff)
3082 return "adds\t%2,%S0";
3087 return "subs\t%G2,%S0";
3091 operands
[2] = GEN_INT (intval
>> 16);
3092 return "inc.w\t%2,%e0";
3096 operands
[2] = GEN_INT (intval
>> 16);
3097 return "dec.w\t%G2,%e0";
3100 /* See if we can finish with 4 bytes. */
3101 if ((intval
& 0xffff) == 0)
3103 operands
[2] = GEN_INT (intval
>> 16);
3104 return "add.w\t%2,%e0";
3108 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3110 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
3111 return "sub.l\t%S2,%S0";
3113 return "add.l\t%S2,%S0";
3117 /* ??? It would be much easier to add the h8sx stuff if a single function
3118 classified the addition as either inc/dec, adds/subs, add.w or add.l. */
3119 /* Compute the length of an addition insn. */
3122 compute_plussi_length (rtx
*operands
)
3124 machine_mode mode
= GET_MODE (operands
[0]);
3126 gcc_assert (mode
== SImode
);
3130 if (GET_CODE (operands
[2]) == REG
)
3133 if (GET_CODE (operands
[2]) == CONST_INT
)
3135 HOST_WIDE_INT n
= INTVAL (operands
[2]);
3137 if ((n
& 0xffffff) == 0)
3139 if ((n
& 0xffff) == 0)
3141 if ((n
& 0xff) == 0)
3149 if (GET_CODE (operands
[2]) == CONST_INT
3150 && register_operand (operands
[1], VOIDmode
))
3152 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3154 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3156 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3159 /* See if we can finish with 2 bytes. */
3161 switch ((unsigned int) intval
& 0xffffffff)
3182 /* See if we can finish with 4 bytes. */
3183 if ((intval
& 0xffff) == 0)
3187 if (GET_CODE (operands
[2]) == CONST_INT
&& INTVAL (operands
[2]) < 0)
3188 return h8300_length_from_table (operands
[0],
3189 GEN_INT (-INTVAL (operands
[2])),
3190 &addl_length_table
);
3192 return h8300_length_from_table (operands
[0], operands
[2],
3193 &addl_length_table
);
3198 /* Compute which flag bits are valid after an addition insn. */
3201 compute_plussi_cc (rtx
*operands
)
3203 machine_mode mode
= GET_MODE (operands
[0]);
3205 gcc_assert (mode
== SImode
);
3213 if (GET_CODE (operands
[2]) == CONST_INT
3214 && register_operand (operands
[1], VOIDmode
))
3216 HOST_WIDE_INT intval
= INTVAL (operands
[2]);
3218 if (TARGET_H8300SX
&& (intval
>= 1 && intval
<= 7))
3220 if (TARGET_H8300SX
&& (intval
>= -7 && intval
<= -1))
3223 /* See if we can finish with 2 bytes. */
3225 switch ((unsigned int) intval
& 0xffffffff)
3230 return CC_NONE_0HIT
;
3235 return CC_NONE_0HIT
;
3246 /* See if we can finish with 4 bytes. */
3247 if ((intval
& 0xffff) == 0)
3255 /* Output a logical insn. */
3258 output_logical_op (machine_mode mode
, rtx
*operands
)
3260 /* Figure out the logical op that we need to perform. */
3261 enum rtx_code code
= GET_CODE (operands
[3]);
3262 /* Pretend that every byte is affected if both operands are registers. */
3263 const unsigned HOST_WIDE_INT intval
=
3264 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3265 /* Always use the full instruction if the
3266 first operand is in memory. It is better
3267 to use define_splits to generate the shorter
3268 sequence where valid. */
3269 && register_operand (operands
[1], VOIDmode
)
3270 ? INTVAL (operands
[2]) : 0x55555555);
3271 /* The determinant of the algorithm. If we perform an AND, 0
3272 affects a bit. Otherwise, 1 affects a bit. */
3273 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3274 /* Break up DET into pieces. */
3275 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3276 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3277 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3278 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3279 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3280 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3281 int lower_half_easy_p
= 0;
3282 int upper_half_easy_p
= 0;
3283 /* The name of an insn. */
3305 /* First, see if we can finish with one insn. */
3306 if ((TARGET_H8300H
|| TARGET_H8300S
)
3310 sprintf (insn_buf
, "%s.w\t%%T2,%%T0", opname
);
3311 output_asm_insn (insn_buf
, operands
);
3315 /* Take care of the lower byte. */
3318 sprintf (insn_buf
, "%s\t%%s2,%%s0", opname
);
3319 output_asm_insn (insn_buf
, operands
);
3321 /* Take care of the upper byte. */
3324 sprintf (insn_buf
, "%s\t%%t2,%%t0", opname
);
3325 output_asm_insn (insn_buf
, operands
);
3330 if (TARGET_H8300H
|| TARGET_H8300S
)
3332 /* Determine if the lower half can be taken care of in no more
3334 lower_half_easy_p
= (b0
== 0
3336 || (code
!= IOR
&& w0
== 0xffff));
3338 /* Determine if the upper half can be taken care of in no more
3340 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3341 || (code
== AND
&& w1
== 0xff00));
3344 /* Check if doing everything with one insn is no worse than
3345 using multiple insns. */
3346 if ((TARGET_H8300H
|| TARGET_H8300S
)
3347 && w0
!= 0 && w1
!= 0
3348 && !(lower_half_easy_p
&& upper_half_easy_p
)
3349 && !(code
== IOR
&& w1
== 0xffff
3350 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3352 sprintf (insn_buf
, "%s.l\t%%S2,%%S0", opname
);
3353 output_asm_insn (insn_buf
, operands
);
3357 /* Take care of the lower and upper words individually. For
3358 each word, we try different methods in the order of
3360 1) the special insn (in case of AND or XOR),
3361 2) the word-wise insn, and
3362 3) The byte-wise insn. */
3364 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3365 output_asm_insn ((code
== AND
)
3366 ? "sub.w\t%f0,%f0" : "not.w\t%f0",
3368 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3372 sprintf (insn_buf
, "%s.w\t%%f2,%%f0", opname
);
3373 output_asm_insn (insn_buf
, operands
);
3379 sprintf (insn_buf
, "%s\t%%w2,%%w0", opname
);
3380 output_asm_insn (insn_buf
, operands
);
3384 sprintf (insn_buf
, "%s\t%%x2,%%x0", opname
);
3385 output_asm_insn (insn_buf
, operands
);
3390 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3391 output_asm_insn ((code
== AND
)
3392 ? "sub.w\t%e0,%e0" : "not.w\t%e0",
3394 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3397 && (w0
& 0x8000) != 0)
3399 output_asm_insn ("exts.l\t%S0", operands
);
3401 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3405 output_asm_insn ("extu.w\t%e0", operands
);
3407 else if (TARGET_H8300H
|| TARGET_H8300S
)
3411 sprintf (insn_buf
, "%s.w\t%%e2,%%e0", opname
);
3412 output_asm_insn (insn_buf
, operands
);
3419 sprintf (insn_buf
, "%s\t%%y2,%%y0", opname
);
3420 output_asm_insn (insn_buf
, operands
);
3424 sprintf (insn_buf
, "%s\t%%z2,%%z0", opname
);
3425 output_asm_insn (insn_buf
, operands
);
3436 /* Compute the length of a logical insn. */
3439 compute_logical_op_length (machine_mode mode
, rtx
*operands
)
3441 /* Figure out the logical op that we need to perform. */
3442 enum rtx_code code
= GET_CODE (operands
[3]);
3443 /* Pretend that every byte is affected if both operands are registers. */
3444 const unsigned HOST_WIDE_INT intval
=
3445 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3446 /* Always use the full instruction if the
3447 first operand is in memory. It is better
3448 to use define_splits to generate the shorter
3449 sequence where valid. */
3450 && register_operand (operands
[1], VOIDmode
)
3451 ? INTVAL (operands
[2]) : 0x55555555);
3452 /* The determinant of the algorithm. If we perform an AND, 0
3453 affects a bit. Otherwise, 1 affects a bit. */
3454 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3455 /* Break up DET into pieces. */
3456 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3457 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3458 const unsigned HOST_WIDE_INT b2
= (det
>> 16) & 0xff;
3459 const unsigned HOST_WIDE_INT b3
= (det
>> 24) & 0xff;
3460 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3461 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3462 int lower_half_easy_p
= 0;
3463 int upper_half_easy_p
= 0;
3465 unsigned int length
= 0;
3470 /* First, see if we can finish with one insn. */
3471 if ((TARGET_H8300H
|| TARGET_H8300S
)
3475 length
= h8300_length_from_table (operands
[1], operands
[2],
3476 &logicw_length_table
);
3480 /* Take care of the lower byte. */
3484 /* Take care of the upper byte. */
3490 if (TARGET_H8300H
|| TARGET_H8300S
)
3492 /* Determine if the lower half can be taken care of in no more
3494 lower_half_easy_p
= (b0
== 0
3496 || (code
!= IOR
&& w0
== 0xffff));
3498 /* Determine if the upper half can be taken care of in no more
3500 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3501 || (code
== AND
&& w1
== 0xff00));
3504 /* Check if doing everything with one insn is no worse than
3505 using multiple insns. */
3506 if ((TARGET_H8300H
|| TARGET_H8300S
)
3507 && w0
!= 0 && w1
!= 0
3508 && !(lower_half_easy_p
&& upper_half_easy_p
)
3509 && !(code
== IOR
&& w1
== 0xffff
3510 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3512 length
= h8300_length_from_table (operands
[1], operands
[2],
3513 &logicl_length_table
);
3517 /* Take care of the lower and upper words individually. For
3518 each word, we try different methods in the order of
3520 1) the special insn (in case of AND or XOR),
3521 2) the word-wise insn, and
3522 3) The byte-wise insn. */
3524 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3528 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3544 && (TARGET_H8300
? (code
== AND
) : (code
!= IOR
)))
3548 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3551 && (w0
& 0x8000) != 0)
3555 else if ((TARGET_H8300H
|| TARGET_H8300S
)
3561 else if (TARGET_H8300H
|| TARGET_H8300S
)
3582 /* Compute which flag bits are valid after a logical insn. */
3585 compute_logical_op_cc (machine_mode mode
, rtx
*operands
)
3587 /* Figure out the logical op that we need to perform. */
3588 enum rtx_code code
= GET_CODE (operands
[3]);
3589 /* Pretend that every byte is affected if both operands are registers. */
3590 const unsigned HOST_WIDE_INT intval
=
3591 (unsigned HOST_WIDE_INT
) ((GET_CODE (operands
[2]) == CONST_INT
)
3592 /* Always use the full instruction if the
3593 first operand is in memory. It is better
3594 to use define_splits to generate the shorter
3595 sequence where valid. */
3596 && register_operand (operands
[1], VOIDmode
)
3597 ? INTVAL (operands
[2]) : 0x55555555);
3598 /* The determinant of the algorithm. If we perform an AND, 0
3599 affects a bit. Otherwise, 1 affects a bit. */
3600 const unsigned HOST_WIDE_INT det
= (code
!= AND
) ? intval
: ~intval
;
3601 /* Break up DET into pieces. */
3602 const unsigned HOST_WIDE_INT b0
= (det
>> 0) & 0xff;
3603 const unsigned HOST_WIDE_INT b1
= (det
>> 8) & 0xff;
3604 const unsigned HOST_WIDE_INT w0
= (det
>> 0) & 0xffff;
3605 const unsigned HOST_WIDE_INT w1
= (det
>> 16) & 0xffff;
3606 int lower_half_easy_p
= 0;
3607 int upper_half_easy_p
= 0;
3608 /* Condition code. */
3609 enum attr_cc cc
= CC_CLOBBER
;
3614 /* First, see if we can finish with one insn. */
3615 if ((TARGET_H8300H
|| TARGET_H8300S
)
3623 if (TARGET_H8300H
|| TARGET_H8300S
)
3625 /* Determine if the lower half can be taken care of in no more
3627 lower_half_easy_p
= (b0
== 0
3629 || (code
!= IOR
&& w0
== 0xffff));
3631 /* Determine if the upper half can be taken care of in no more
3633 upper_half_easy_p
= ((code
!= IOR
&& w1
== 0xffff)
3634 || (code
== AND
&& w1
== 0xff00));
3637 /* Check if doing everything with one insn is no worse than
3638 using multiple insns. */
3639 if ((TARGET_H8300H
|| TARGET_H8300S
)
3640 && w0
!= 0 && w1
!= 0
3641 && !(lower_half_easy_p
&& upper_half_easy_p
)
3642 && !(code
== IOR
&& w1
== 0xffff
3643 && (w0
& 0x8000) != 0 && lower_half_easy_p
))
3649 if ((TARGET_H8300H
|| TARGET_H8300S
)
3652 && (w0
& 0x8000) != 0)
3664 /* Expand a conditional branch. */
3667 h8300_expand_branch (rtx operands
[])
3669 enum rtx_code code
= GET_CODE (operands
[0]);
3670 rtx op0
= operands
[1];
3671 rtx op1
= operands
[2];
3672 rtx label
= operands
[3];
3675 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3676 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3678 tmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
3679 tmp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, tmp
,
3680 gen_rtx_LABEL_REF (VOIDmode
, label
),
3682 emit_jump_insn (gen_rtx_SET (pc_rtx
, tmp
));
3686 /* Expand a conditional store. */
3689 h8300_expand_store (rtx operands
[])
3691 rtx dest
= operands
[0];
3692 enum rtx_code code
= GET_CODE (operands
[1]);
3693 rtx op0
= operands
[2];
3694 rtx op1
= operands
[3];
3697 tmp
= gen_rtx_COMPARE (VOIDmode
, op0
, op1
);
3698 emit_insn (gen_rtx_SET (cc0_rtx
, tmp
));
3700 tmp
= gen_rtx_fmt_ee (code
, GET_MODE (dest
), cc0_rtx
, const0_rtx
);
3701 emit_insn (gen_rtx_SET (dest
, tmp
));
3706 We devote a fair bit of code to getting efficient shifts since we
3707 can only shift one bit at a time on the H8/300 and H8/300H and only
3708 one or two bits at a time on the H8S.
3710 All shift code falls into one of the following ways of
3713 o SHIFT_INLINE: Emit straight line code for the shift; this is used
3714 when a straight line shift is about the same size or smaller than
3717 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask
3718 off the bits we don't need. This is used when only a few of the
3719 bits in the original value will survive in the shifted value.
3721 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to
3722 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline
3723 shifts can be added if the shift count is slightly more than 8 or
3724 16. This case also includes other oddballs that are not worth
3727 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts.
3729 For each shift count, we try to use code that has no trade-off
3730 between code size and speed whenever possible.
3732 If the trade-off is unavoidable, we try to be reasonable.
3733 Specifically, the fastest version is one instruction longer than
3734 the shortest version, we take the fastest version. We also provide
3735 the use a way to switch back to the shortest version with -Os.
3737 For the details of the shift algorithms for various shift counts,
3738 refer to shift_alg_[qhs]i. */
3740 /* Classify a shift with the given mode and code. OP is the shift amount. */
3742 enum h8sx_shift_type
3743 h8sx_classify_shift (machine_mode mode
, enum rtx_code code
, rtx op
)
3745 if (!TARGET_H8300SX
)
3746 return H8SX_SHIFT_NONE
;
3752 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
3753 if (GET_CODE (op
) != CONST_INT
)
3754 return H8SX_SHIFT_BINARY
;
3756 /* Reject out-of-range shift amounts. */
3757 if (INTVAL (op
) <= 0 || INTVAL (op
) >= GET_MODE_BITSIZE (mode
))
3758 return H8SX_SHIFT_NONE
;
3760 /* Power-of-2 shifts are effectively unary operations. */
3761 if (exact_log2 (INTVAL (op
)) >= 0)
3762 return H8SX_SHIFT_UNARY
;
3764 return H8SX_SHIFT_BINARY
;
3767 if (op
== const1_rtx
|| op
== const2_rtx
)
3768 return H8SX_SHIFT_UNARY
;
3769 return H8SX_SHIFT_NONE
;
3772 if (GET_CODE (op
) == CONST_INT
3773 && (INTVAL (op
) == 1
3775 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 2
3776 || INTVAL (op
) == GET_MODE_BITSIZE (mode
) - 1))
3777 return H8SX_SHIFT_UNARY
;
3778 return H8SX_SHIFT_NONE
;
3781 return H8SX_SHIFT_NONE
;
3785 /* Return the asm template for a single h8sx shift instruction.
3786 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2]
3787 is the source and OPERANDS[3] is the shift. SUFFIX is the
3788 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand
3789 prefix for the destination operand. */
3792 output_h8sx_shift (rtx
*operands
, int suffix
, int optype
)
3794 static char buffer
[16];
3797 switch (GET_CODE (operands
[3]))
3813 if (INTVAL (operands
[2]) > 2)
3815 /* This is really a right rotate. */
3816 operands
[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands
[0]))
3817 - INTVAL (operands
[2]));
3825 if (operands
[2] == const1_rtx
)
3826 sprintf (buffer
, "%s.%c\t%%%c0", stem
, suffix
, optype
);
3828 sprintf (buffer
, "%s.%c\t%%X2,%%%c0", stem
, suffix
, optype
);
3832 /* Emit code to do shifts. */
3835 expand_a_shift (machine_mode mode
, enum rtx_code code
, rtx operands
[])
3837 switch (h8sx_classify_shift (mode
, code
, operands
[2]))
3839 case H8SX_SHIFT_BINARY
:
3840 operands
[1] = force_reg (mode
, operands
[1]);
3843 case H8SX_SHIFT_UNARY
:
3846 case H8SX_SHIFT_NONE
:
3850 emit_move_insn (copy_rtx (operands
[0]), operands
[1]);
3852 /* Need a loop to get all the bits we want - we generate the
3853 code at emit time, but need to allocate a scratch reg now. */
3855 emit_insn (gen_rtx_PARALLEL
3858 gen_rtx_SET (copy_rtx (operands
[0]),
3859 gen_rtx_fmt_ee (code
, mode
,
3860 copy_rtx (operands
[0]), operands
[2])),
3861 gen_rtx_CLOBBER (VOIDmode
,
3862 gen_rtx_SCRATCH (QImode
)))));
3866 /* Symbols of the various modes which can be used as indices. */
3870 QIshift
, HIshift
, SIshift
3873 /* For single bit shift insns, record assembler and what bits of the
3874 condition code are valid afterwards (represented as various CC_FOO
3875 bits, 0 means CC isn't left in a usable state). */
3879 const char *const assembler
;
3880 const enum attr_cc cc_valid
;
3883 /* Assembler instruction shift table.
3885 These tables are used to look up the basic shifts.
3886 They are indexed by cpu, shift_type, and mode. */
3888 static const struct shift_insn shift_one
[2][3][3] =
3894 { "shll\t%X0", CC_SET_ZNV
},
3895 { "add.w\t%T0,%T0", CC_SET_ZN
},
3896 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", CC_CLOBBER
}
3898 /* SHIFT_LSHIFTRT */
3900 { "shlr\t%X0", CC_SET_ZNV
},
3901 { "shlr\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3902 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3904 /* SHIFT_ASHIFTRT */
3906 { "shar\t%X0", CC_SET_ZNV
},
3907 { "shar\t%t0\n\trotxr\t%s0", CC_CLOBBER
},
3908 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", CC_CLOBBER
}
3915 { "shll.b\t%X0", CC_SET_ZNV
},
3916 { "shll.w\t%T0", CC_SET_ZNV
},
3917 { "shll.l\t%S0", CC_SET_ZNV
}
3919 /* SHIFT_LSHIFTRT */
3921 { "shlr.b\t%X0", CC_SET_ZNV
},
3922 { "shlr.w\t%T0", CC_SET_ZNV
},
3923 { "shlr.l\t%S0", CC_SET_ZNV
}
3925 /* SHIFT_ASHIFTRT */
3927 { "shar.b\t%X0", CC_SET_ZNV
},
3928 { "shar.w\t%T0", CC_SET_ZNV
},
3929 { "shar.l\t%S0", CC_SET_ZNV
}
3934 static const struct shift_insn shift_two
[3][3] =
3938 { "shll.b\t#2,%X0", CC_SET_ZNV
},
3939 { "shll.w\t#2,%T0", CC_SET_ZNV
},
3940 { "shll.l\t#2,%S0", CC_SET_ZNV
}
3942 /* SHIFT_LSHIFTRT */
3944 { "shlr.b\t#2,%X0", CC_SET_ZNV
},
3945 { "shlr.w\t#2,%T0", CC_SET_ZNV
},
3946 { "shlr.l\t#2,%S0", CC_SET_ZNV
}
3948 /* SHIFT_ASHIFTRT */
3950 { "shar.b\t#2,%X0", CC_SET_ZNV
},
3951 { "shar.w\t#2,%T0", CC_SET_ZNV
},
3952 { "shar.l\t#2,%S0", CC_SET_ZNV
}
3956 /* Rotates are organized by which shift they'll be used in implementing.
3957 There's no need to record whether the cc is valid afterwards because
3958 it is the AND insn that will decide this. */
3960 static const char *const rotate_one
[2][3][3] =
3967 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0",
3970 /* SHIFT_LSHIFTRT */
3973 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3976 /* SHIFT_ASHIFTRT */
3979 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0",
3991 /* SHIFT_LSHIFTRT */
3997 /* SHIFT_ASHIFTRT */
4006 static const char *const rotate_two
[3][3] =
4014 /* SHIFT_LSHIFTRT */
4020 /* SHIFT_ASHIFTRT */
4029 /* Shift algorithm. */
4032 /* The number of bits to be shifted by shift1 and shift2. Valid
4033 when ALG is SHIFT_SPECIAL. */
4034 unsigned int remainder
;
4036 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */
4037 const char *special
;
4039 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE
4040 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4043 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE
4044 or SHIFT_SPECIAL, and REMAINDER is nonzero. */
4047 /* CC status for SHIFT_INLINE. */
4048 enum attr_cc cc_inline
;
4050 /* CC status for SHIFT_SPECIAL. */
4051 enum attr_cc cc_special
;
4054 static void get_shift_alg (enum shift_type
,
4055 enum shift_mode
, unsigned int,
4056 struct shift_info
*);
4058 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
4059 best algorithm for doing the shift. The assembler code is stored
4060 in the pointers in INFO. We achieve the maximum efficiency in most
4061 cases when !TARGET_H8300. In case of TARGET_H8300, shifts in
4062 SImode in particular have a lot of room to optimize.
4064 We first determine the strategy of the shift algorithm by a table
4065 lookup. If that tells us to use a hand crafted assembly code, we
4066 go into the big switch statement to find what that is. Otherwise,
4067 we resort to a generic way, such as inlining. In either case, the
4068 result is returned through INFO. */
4071 get_shift_alg (enum shift_type shift_type
, enum shift_mode shift_mode
,
4072 unsigned int count
, struct shift_info
*info
)
4076 /* Find the target CPU. */
4079 else if (TARGET_H8300S
)
4084 /* Find the shift algorithm. */
4085 info
->alg
= SHIFT_LOOP
;
4089 if (count
< GET_MODE_BITSIZE (QImode
))
4090 info
->alg
= shift_alg_qi
[cpu
][shift_type
][count
];
4094 if (count
< GET_MODE_BITSIZE (HImode
))
4095 info
->alg
= shift_alg_hi
[cpu
][shift_type
][count
];
4099 if (count
< GET_MODE_BITSIZE (SImode
))
4100 info
->alg
= shift_alg_si
[cpu
][shift_type
][count
];
4107 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */
4111 info
->remainder
= count
;
4115 /* It is up to the caller to know that looping clobbers cc. */
4116 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4117 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4118 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4122 info
->shift1
= rotate_one
[cpu_type
][shift_type
][shift_mode
];
4123 info
->shift2
= rotate_two
[shift_type
][shift_mode
];
4124 info
->cc_inline
= CC_CLOBBER
;
4128 /* REMAINDER is 0 for most cases, so initialize it to 0. */
4129 info
->remainder
= 0;
4130 info
->shift1
= shift_one
[cpu_type
][shift_type
][shift_mode
].assembler
;
4131 info
->shift2
= shift_two
[shift_type
][shift_mode
].assembler
;
4132 info
->cc_inline
= shift_one
[cpu_type
][shift_type
][shift_mode
].cc_valid
;
4133 info
->cc_special
= CC_CLOBBER
;
4137 /* Here we only deal with SHIFT_SPECIAL. */
4141 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated
4142 through the entire value. */
4143 gcc_assert (shift_type
== SHIFT_ASHIFTRT
&& count
== 7);
4144 info
->special
= "shll\t%X0\n\tsubx\t%X0,%X0";
4154 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
4156 info
->special
= "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
4158 case SHIFT_LSHIFTRT
:
4160 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
4162 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
4164 case SHIFT_ASHIFTRT
:
4165 info
->special
= "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
4169 else if ((8 <= count
&& count
<= 13)
4170 || (TARGET_H8300S
&& count
== 14))
4172 info
->remainder
= count
- 8;
4177 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
4179 case SHIFT_LSHIFTRT
:
4182 info
->special
= "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
4183 info
->shift1
= "shlr.b\t%s0";
4184 info
->cc_inline
= CC_SET_ZNV
;
4188 info
->special
= "mov.b\t%t0,%s0\n\textu.w\t%T0";
4189 info
->cc_special
= CC_SET_ZNV
;
4192 case SHIFT_ASHIFTRT
:
4195 info
->special
= "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
4196 info
->shift1
= "shar.b\t%s0";
4200 info
->special
= "mov.b\t%t0,%s0\n\texts.w\t%T0";
4201 info
->cc_special
= CC_SET_ZNV
;
4206 else if (count
== 14)
4212 info
->special
= "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
4214 case SHIFT_LSHIFTRT
:
4216 info
->special
= "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
4218 case SHIFT_ASHIFTRT
:
4220 info
->special
= "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
4221 else if (TARGET_H8300H
)
4223 info
->special
= "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
4224 info
->cc_special
= CC_SET_ZNV
;
4226 else /* TARGET_H8300S */
4231 else if (count
== 15)
4236 info
->special
= "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0";
4238 case SHIFT_LSHIFTRT
:
4239 info
->special
= "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0";
4241 case SHIFT_ASHIFTRT
:
4242 info
->special
= "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0";
4249 if (TARGET_H8300
&& 8 <= count
&& count
<= 9)
4251 info
->remainder
= count
- 8;
4256 info
->special
= "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
4258 case SHIFT_LSHIFTRT
:
4259 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
4260 info
->shift1
= "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
4262 case SHIFT_ASHIFTRT
:
4263 info
->special
= "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
4267 else if (count
== 8 && !TARGET_H8300
)
4272 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%s4,%t4\n\tmov.b\t%t0,%s4\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f4,%e0";
4274 case SHIFT_LSHIFTRT
:
4275 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\textu.w\t%f4\n\tmov.w\t%f4,%e0";
4277 case SHIFT_ASHIFTRT
:
4278 info
->special
= "mov.w\t%e0,%f4\n\tmov.b\t%t0,%s0\n\tmov.b\t%s4,%t0\n\tmov.b\t%t4,%s4\n\texts.w\t%f4\n\tmov.w\t%f4,%e0";
4282 else if (count
== 15 && TARGET_H8300
)
4288 case SHIFT_LSHIFTRT
:
4289 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
4291 case SHIFT_ASHIFTRT
:
4292 info
->special
= "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4296 else if (count
== 15 && !TARGET_H8300
)
4301 info
->special
= "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0";
4302 info
->cc_special
= CC_SET_ZNV
;
4304 case SHIFT_LSHIFTRT
:
4305 info
->special
= "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0";
4306 info
->cc_special
= CC_SET_ZNV
;
4308 case SHIFT_ASHIFTRT
:
4312 else if ((TARGET_H8300
&& 16 <= count
&& count
<= 20)
4313 || (TARGET_H8300H
&& 16 <= count
&& count
<= 19)
4314 || (TARGET_H8300S
&& 16 <= count
&& count
<= 21))
4316 info
->remainder
= count
- 16;
4321 info
->special
= "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4323 info
->shift1
= "add.w\t%e0,%e0";
4325 case SHIFT_LSHIFTRT
:
4328 info
->special
= "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
4329 info
->shift1
= "shlr\t%x0\n\trotxr\t%w0";
4333 info
->special
= "mov.w\t%e0,%f0\n\textu.l\t%S0";
4334 info
->cc_special
= CC_SET_ZNV
;
4337 case SHIFT_ASHIFTRT
:
4340 info
->special
= "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
4341 info
->shift1
= "shar\t%x0\n\trotxr\t%w0";
4345 info
->special
= "mov.w\t%e0,%f0\n\texts.l\t%S0";
4346 info
->cc_special
= CC_SET_ZNV
;
4351 else if (TARGET_H8300
&& 24 <= count
&& count
<= 28)
4353 info
->remainder
= count
- 24;
4358 info
->special
= "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
4359 info
->shift1
= "shll.b\t%z0";
4360 info
->cc_inline
= CC_SET_ZNV
;
4362 case SHIFT_LSHIFTRT
:
4363 info
->special
= "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
4364 info
->shift1
= "shlr.b\t%w0";
4365 info
->cc_inline
= CC_SET_ZNV
;
4367 case SHIFT_ASHIFTRT
:
4368 info
->special
= "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
4369 info
->shift1
= "shar.b\t%w0";
4370 info
->cc_inline
= CC_SET_ZNV
;
4374 else if ((TARGET_H8300H
&& count
== 24)
4375 || (TARGET_H8300S
&& 24 <= count
&& count
<= 25))
4377 info
->remainder
= count
- 24;
4382 info
->special
= "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
4384 case SHIFT_LSHIFTRT
:
4385 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0";
4386 info
->cc_special
= CC_SET_ZNV
;
4388 case SHIFT_ASHIFTRT
:
4389 info
->special
= "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0";
4390 info
->cc_special
= CC_SET_ZNV
;
4394 else if (!TARGET_H8300
&& count
== 28)
4400 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4402 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4404 case SHIFT_LSHIFTRT
:
4407 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4408 info
->cc_special
= CC_SET_ZNV
;
4411 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4413 case SHIFT_ASHIFTRT
:
4417 else if (!TARGET_H8300
&& count
== 29)
4423 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4425 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4427 case SHIFT_LSHIFTRT
:
4430 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4431 info
->cc_special
= CC_SET_ZNV
;
4435 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4436 info
->cc_special
= CC_SET_ZNV
;
4439 case SHIFT_ASHIFTRT
:
4443 else if (!TARGET_H8300
&& count
== 30)
4449 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0";
4451 info
->special
= "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0";
4453 case SHIFT_LSHIFTRT
:
4455 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0";
4457 info
->special
= "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0";
4459 case SHIFT_ASHIFTRT
:
4463 else if (count
== 31)
4470 info
->special
= "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
4472 case SHIFT_LSHIFTRT
:
4473 info
->special
= "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
4475 case SHIFT_ASHIFTRT
:
4476 info
->special
= "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
4485 info
->special
= "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
4486 info
->cc_special
= CC_SET_ZNV
;
4488 case SHIFT_LSHIFTRT
:
4489 info
->special
= "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
4490 info
->cc_special
= CC_SET_ZNV
;
4492 case SHIFT_ASHIFTRT
:
4493 info
->special
= "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
4494 info
->cc_special
= CC_SET_ZNV
;
4507 info
->shift2
= NULL
;
4510 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be
4511 needed for some shift with COUNT and MODE. Return 0 otherwise. */
4514 h8300_shift_needs_scratch_p (int count
, machine_mode mode
)
4519 if (GET_MODE_BITSIZE (mode
) <= count
)
4522 /* Find out the target CPU. */
4525 else if (TARGET_H8300S
)
4530 /* Find the shift algorithm. */
4534 a
= shift_alg_qi
[cpu
][SHIFT_ASHIFT
][count
];
4535 lr
= shift_alg_qi
[cpu
][SHIFT_LSHIFTRT
][count
];
4536 ar
= shift_alg_qi
[cpu
][SHIFT_ASHIFTRT
][count
];
4540 a
= shift_alg_hi
[cpu
][SHIFT_ASHIFT
][count
];
4541 lr
= shift_alg_hi
[cpu
][SHIFT_LSHIFTRT
][count
];
4542 ar
= shift_alg_hi
[cpu
][SHIFT_ASHIFTRT
][count
];
4546 a
= shift_alg_si
[cpu
][SHIFT_ASHIFT
][count
];
4547 lr
= shift_alg_si
[cpu
][SHIFT_LSHIFTRT
][count
];
4548 ar
= shift_alg_si
[cpu
][SHIFT_ASHIFTRT
][count
];
4555 /* On H8/300H, count == 8 uses a scratch register. */
4556 return (a
== SHIFT_LOOP
|| lr
== SHIFT_LOOP
|| ar
== SHIFT_LOOP
4557 || (TARGET_H8300H
&& mode
== SImode
&& count
== 8));
4560 /* Output the assembler code for doing shifts. */
4563 output_a_shift (rtx
*operands
)
4565 static int loopend_lab
;
4566 rtx shift
= operands
[3];
4567 machine_mode mode
= GET_MODE (shift
);
4568 enum rtx_code code
= GET_CODE (shift
);
4569 enum shift_type shift_type
;
4570 enum shift_mode shift_mode
;
4571 struct shift_info info
;
4579 shift_mode
= QIshift
;
4582 shift_mode
= HIshift
;
4585 shift_mode
= SIshift
;
4594 shift_type
= SHIFT_ASHIFTRT
;
4597 shift_type
= SHIFT_LSHIFTRT
;
4600 shift_type
= SHIFT_ASHIFT
;
4606 /* This case must be taken care of by one of the two splitters
4607 that convert a variable shift into a loop. */
4608 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4610 n
= INTVAL (operands
[2]);
4612 /* If the count is negative, make it 0. */
4615 /* If the count is too big, truncate it.
4616 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4617 do the intuitive thing. */
4618 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4619 n
= GET_MODE_BITSIZE (mode
);
4621 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4626 output_asm_insn (info
.special
, operands
);
4632 /* Emit two bit shifts first. */
4633 if (info
.shift2
!= NULL
)
4635 for (; n
> 1; n
-= 2)
4636 output_asm_insn (info
.shift2
, operands
);
4639 /* Now emit one bit shifts for any residual. */
4641 output_asm_insn (info
.shift1
, operands
);
4646 int m
= GET_MODE_BITSIZE (mode
) - n
;
4647 const int mask
= (shift_type
== SHIFT_ASHIFT
4648 ? ((1 << m
) - 1) << n
4652 /* Not all possibilities of rotate are supported. They shouldn't
4653 be generated, but let's watch for 'em. */
4654 gcc_assert (info
.shift1
);
4656 /* Emit two bit rotates first. */
4657 if (info
.shift2
!= NULL
)
4659 for (; m
> 1; m
-= 2)
4660 output_asm_insn (info
.shift2
, operands
);
4663 /* Now single bit rotates for any residual. */
4665 output_asm_insn (info
.shift1
, operands
);
4667 /* Now mask off the high bits. */
4671 sprintf (insn_buf
, "and\t#%d,%%X0", mask
);
4675 gcc_assert (TARGET_H8300H
|| TARGET_H8300S
);
4676 sprintf (insn_buf
, "and.w\t#%d,%%T0", mask
);
4683 output_asm_insn (insn_buf
, operands
);
4688 /* A loop to shift by a "large" constant value.
4689 If we have shift-by-2 insns, use them. */
4690 if (info
.shift2
!= NULL
)
4692 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
/ 2,
4693 names_big
[REGNO (operands
[4])]);
4694 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4695 output_asm_insn (info
.shift2
, operands
);
4696 output_asm_insn ("add #0xff,%X4", operands
);
4697 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4699 output_asm_insn (info
.shift1
, operands
);
4703 fprintf (asm_out_file
, "\tmov.b #%d,%sl\n", n
,
4704 names_big
[REGNO (operands
[4])]);
4705 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
4706 output_asm_insn (info
.shift1
, operands
);
4707 output_asm_insn ("add #0xff,%X4", operands
);
4708 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
4717 /* Count the number of assembly instructions in a string TEMPL. */
4720 h8300_asm_insn_count (const char *templ
)
4722 unsigned int count
= 1;
4724 for (; *templ
; templ
++)
4731 /* Compute the length of a shift insn. */
4734 compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4736 rtx shift
= operands
[3];
4737 machine_mode mode
= GET_MODE (shift
);
4738 enum rtx_code code
= GET_CODE (shift
);
4739 enum shift_type shift_type
;
4740 enum shift_mode shift_mode
;
4741 struct shift_info info
;
4742 unsigned int wlength
= 0;
4747 shift_mode
= QIshift
;
4750 shift_mode
= HIshift
;
4753 shift_mode
= SIshift
;
4762 shift_type
= SHIFT_ASHIFTRT
;
4765 shift_type
= SHIFT_LSHIFTRT
;
4768 shift_type
= SHIFT_ASHIFT
;
4774 if (GET_CODE (operands
[2]) != CONST_INT
)
4776 /* Get the assembler code to do one shift. */
4777 get_shift_alg (shift_type
, shift_mode
, 1, &info
);
4779 return (4 + h8300_asm_insn_count (info
.shift1
)) * 2;
4783 int n
= INTVAL (operands
[2]);
4785 /* If the count is negative, make it 0. */
4788 /* If the count is too big, truncate it.
4789 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4790 do the intuitive thing. */
4791 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4792 n
= GET_MODE_BITSIZE (mode
);
4794 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4799 wlength
+= h8300_asm_insn_count (info
.special
);
4801 /* Every assembly instruction used in SHIFT_SPECIAL case
4802 takes 2 bytes except xor.l, which takes 4 bytes, so if we
4803 see xor.l, we just pretend that xor.l counts as two insns
4804 so that the insn length will be computed correctly. */
4805 if (strstr (info
.special
, "xor.l") != NULL
)
4813 if (info
.shift2
!= NULL
)
4815 wlength
+= h8300_asm_insn_count (info
.shift2
) * (n
/ 2);
4819 wlength
+= h8300_asm_insn_count (info
.shift1
) * n
;
4825 int m
= GET_MODE_BITSIZE (mode
) - n
;
4827 /* Not all possibilities of rotate are supported. They shouldn't
4828 be generated, but let's watch for 'em. */
4829 gcc_assert (info
.shift1
);
4831 if (info
.shift2
!= NULL
)
4833 wlength
+= h8300_asm_insn_count (info
.shift2
) * (m
/ 2);
4837 wlength
+= h8300_asm_insn_count (info
.shift1
) * m
;
4839 /* Now mask off the high bits. */
4849 gcc_assert (!TARGET_H8300
);
4859 /* A loop to shift by a "large" constant value.
4860 If we have shift-by-2 insns, use them. */
4861 if (info
.shift2
!= NULL
)
4863 wlength
+= 3 + h8300_asm_insn_count (info
.shift2
);
4865 wlength
+= h8300_asm_insn_count (info
.shift1
);
4869 wlength
+= 3 + h8300_asm_insn_count (info
.shift1
);
4879 /* Compute which flag bits are valid after a shift insn. */
4882 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
)
4884 rtx shift
= operands
[3];
4885 machine_mode mode
= GET_MODE (shift
);
4886 enum rtx_code code
= GET_CODE (shift
);
4887 enum shift_type shift_type
;
4888 enum shift_mode shift_mode
;
4889 struct shift_info info
;
4895 shift_mode
= QIshift
;
4898 shift_mode
= HIshift
;
4901 shift_mode
= SIshift
;
4910 shift_type
= SHIFT_ASHIFTRT
;
4913 shift_type
= SHIFT_LSHIFTRT
;
4916 shift_type
= SHIFT_ASHIFT
;
4922 /* This case must be taken care of by one of the two splitters
4923 that convert a variable shift into a loop. */
4924 gcc_assert (GET_CODE (operands
[2]) == CONST_INT
);
4926 n
= INTVAL (operands
[2]);
4928 /* If the count is negative, make it 0. */
4931 /* If the count is too big, truncate it.
4932 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
4933 do the intuitive thing. */
4934 else if ((unsigned int) n
> GET_MODE_BITSIZE (mode
))
4935 n
= GET_MODE_BITSIZE (mode
);
4937 get_shift_alg (shift_type
, shift_mode
, n
, &info
);
4942 if (info
.remainder
== 0)
4943 return info
.cc_special
;
4948 return info
.cc_inline
;
4951 /* This case always ends with an and instruction. */
4955 /* A loop to shift by a "large" constant value.
4956 If we have shift-by-2 insns, use them. */
4957 if (info
.shift2
!= NULL
)
4960 return info
.cc_inline
;
4969 /* A rotation by a non-constant will cause a loop to be generated, in
4970 which a rotation by one bit is used. A rotation by a constant,
4971 including the one in the loop, will be taken care of by
4972 output_a_rotate () at the insn emit time. */
4975 expand_a_rotate (rtx operands
[])
4977 rtx dst
= operands
[0];
4978 rtx src
= operands
[1];
4979 rtx rotate_amount
= operands
[2];
4980 machine_mode mode
= GET_MODE (dst
);
4982 if (h8sx_classify_shift (mode
, ROTATE
, rotate_amount
) == H8SX_SHIFT_UNARY
)
4985 /* We rotate in place. */
4986 emit_move_insn (dst
, src
);
4988 if (GET_CODE (rotate_amount
) != CONST_INT
)
4990 rtx counter
= gen_reg_rtx (QImode
);
4991 rtx_code_label
*start_label
= gen_label_rtx ();
4992 rtx_code_label
*end_label
= gen_label_rtx ();
4994 /* If the rotate amount is less than or equal to 0,
4995 we go out of the loop. */
4996 emit_cmp_and_jump_insns (rotate_amount
, const0_rtx
, LE
, NULL_RTX
,
4997 QImode
, 0, end_label
);
4999 /* Initialize the loop counter. */
5000 emit_move_insn (counter
, rotate_amount
);
5002 emit_label (start_label
);
5004 /* Rotate by one bit. */
5008 emit_insn (gen_rotlqi3_1 (dst
, dst
, const1_rtx
));
5011 emit_insn (gen_rotlhi3_1 (dst
, dst
, const1_rtx
));
5014 emit_insn (gen_rotlsi3_1 (dst
, dst
, const1_rtx
));
5020 /* Decrement the counter by 1. */
5021 emit_insn (gen_addqi3 (counter
, counter
, constm1_rtx
));
5023 /* If the loop counter is nonzero, we go back to the beginning
5025 emit_cmp_and_jump_insns (counter
, const0_rtx
, NE
, NULL_RTX
, QImode
, 1,
5028 emit_label (end_label
);
5032 /* Rotate by AMOUNT bits. */
5036 emit_insn (gen_rotlqi3_1 (dst
, dst
, rotate_amount
));
5039 emit_insn (gen_rotlhi3_1 (dst
, dst
, rotate_amount
));
5042 emit_insn (gen_rotlsi3_1 (dst
, dst
, rotate_amount
));
5052 /* Output a rotate insn. */
5055 output_a_rotate (enum rtx_code code
, rtx
*operands
)
5057 rtx dst
= operands
[0];
5058 rtx rotate_amount
= operands
[2];
5059 enum shift_mode rotate_mode
;
5060 enum shift_type rotate_type
;
5061 const char *insn_buf
;
5064 machine_mode mode
= GET_MODE (dst
);
5066 gcc_assert (GET_CODE (rotate_amount
) == CONST_INT
);
5071 rotate_mode
= QIshift
;
5074 rotate_mode
= HIshift
;
5077 rotate_mode
= SIshift
;
5086 rotate_type
= SHIFT_ASHIFT
;
5089 rotate_type
= SHIFT_LSHIFTRT
;
5095 amount
= INTVAL (rotate_amount
);
5097 /* Clean up AMOUNT. */
5100 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5101 amount
= GET_MODE_BITSIZE (mode
);
5103 /* Determine the faster direction. After this phase, amount will be
5104 at most a half of GET_MODE_BITSIZE (mode). */
5105 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5107 /* Flip the direction. */
5108 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5110 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5113 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5114 boost up the rotation. */
5115 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5116 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5117 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5118 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5119 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5124 /* This code works on any family. */
5125 insn_buf
= "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0";
5126 output_asm_insn (insn_buf
, operands
);
5130 /* This code works on the H8/300H and H8S. */
5131 insn_buf
= "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0";
5132 output_asm_insn (insn_buf
, operands
);
5139 /* Adjust AMOUNT and flip the direction. */
5140 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5142 (rotate_type
== SHIFT_ASHIFT
) ? SHIFT_LSHIFTRT
: SHIFT_ASHIFT
;
5145 /* Output rotate insns. */
5146 for (bits
= TARGET_H8300S
? 2 : 1; bits
> 0; bits
/= 2)
5149 insn_buf
= rotate_two
[rotate_type
][rotate_mode
];
5151 insn_buf
= rotate_one
[cpu_type
][rotate_type
][rotate_mode
];
5153 for (; amount
>= bits
; amount
-= bits
)
5154 output_asm_insn (insn_buf
, operands
);
5160 /* Compute the length of a rotate insn. */
5163 compute_a_rotate_length (rtx
*operands
)
5165 rtx src
= operands
[1];
5166 rtx amount_rtx
= operands
[2];
5167 machine_mode mode
= GET_MODE (src
);
5169 unsigned int length
= 0;
5171 gcc_assert (GET_CODE (amount_rtx
) == CONST_INT
);
5173 amount
= INTVAL (amount_rtx
);
5175 /* Clean up AMOUNT. */
5178 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
))
5179 amount
= GET_MODE_BITSIZE (mode
);
5181 /* Determine the faster direction. After this phase, amount
5182 will be at most a half of GET_MODE_BITSIZE (mode). */
5183 if ((unsigned int) amount
> GET_MODE_BITSIZE (mode
) / (unsigned) 2)
5184 /* Flip the direction. */
5185 amount
= GET_MODE_BITSIZE (mode
) - amount
;
5187 /* See if a byte swap (in HImode) or a word swap (in SImode) can
5188 boost up the rotation. */
5189 if ((mode
== HImode
&& TARGET_H8300
&& amount
>= 5)
5190 || (mode
== HImode
&& TARGET_H8300H
&& amount
>= 6)
5191 || (mode
== HImode
&& TARGET_H8300S
&& amount
== 8)
5192 || (mode
== SImode
&& TARGET_H8300H
&& amount
>= 10)
5193 || (mode
== SImode
&& TARGET_H8300S
&& amount
>= 13))
5195 /* Adjust AMOUNT and flip the direction. */
5196 amount
= GET_MODE_BITSIZE (mode
) / 2 - amount
;
5200 /* We use 2-bit rotations on the H8S. */
5202 amount
= amount
/ 2 + amount
% 2;
5204 /* The H8/300 uses three insns to rotate one bit, taking 6
5206 length
+= amount
* ((TARGET_H8300
&& mode
== HImode
) ? 6 : 2);
5211 /* Fix the operands of a gen_xxx so that it could become a bit
5215 fix_bit_operand (rtx
*operands
, enum rtx_code code
)
5217 /* The bit_operand predicate accepts any memory during RTL generation, but
5218 only 'U' memory afterwards, so if this is a MEM operand, we must force
5219 it to be valid for 'U' by reloading the address. */
5222 ? single_zero_operand (operands
[2], QImode
)
5223 : single_one_operand (operands
[2], QImode
))
5225 /* OK to have a memory dest. */
5226 if (GET_CODE (operands
[0]) == MEM
5227 && !satisfies_constraint_U (operands
[0]))
5229 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[0]),
5230 copy_to_mode_reg (Pmode
,
5231 XEXP (operands
[0], 0)));
5232 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5236 if (GET_CODE (operands
[1]) == MEM
5237 && !satisfies_constraint_U (operands
[1]))
5239 rtx mem
= gen_rtx_MEM (GET_MODE (operands
[1]),
5240 copy_to_mode_reg (Pmode
,
5241 XEXP (operands
[1], 0)));
5242 MEM_COPY_ATTRIBUTES (mem
, operands
[0]);
5248 /* Dest and src op must be register. */
5250 operands
[1] = force_reg (QImode
, operands
[1]);
5252 rtx res
= gen_reg_rtx (QImode
);
5256 emit_insn (gen_andqi3_1 (res
, operands
[1], operands
[2]));
5259 emit_insn (gen_iorqi3_1 (res
, operands
[1], operands
[2]));
5262 emit_insn (gen_xorqi3_1 (res
, operands
[1], operands
[2]));
5267 emit_insn (gen_movqi (operands
[0], res
));
5272 /* Return nonzero if FUNC is an interrupt function as specified
5273 by the "interrupt" attribute. */
5276 h8300_interrupt_function_p (tree func
)
5280 if (TREE_CODE (func
) != FUNCTION_DECL
)
5283 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
5284 return a
!= NULL_TREE
;
5287 /* Return nonzero if FUNC is a saveall function as specified by the
5288 "saveall" attribute. */
5291 h8300_saveall_function_p (tree func
)
5295 if (TREE_CODE (func
) != FUNCTION_DECL
)
5298 a
= lookup_attribute ("saveall", DECL_ATTRIBUTES (func
));
5299 return a
!= NULL_TREE
;
5302 /* Return nonzero if FUNC is an OS_Task function as specified
5303 by the "OS_Task" attribute. */
5306 h8300_os_task_function_p (tree func
)
5310 if (TREE_CODE (func
) != FUNCTION_DECL
)
5313 a
= lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func
));
5314 return a
!= NULL_TREE
;
5317 /* Return nonzero if FUNC is a monitor function as specified
5318 by the "monitor" attribute. */
5321 h8300_monitor_function_p (tree func
)
5325 if (TREE_CODE (func
) != FUNCTION_DECL
)
5328 a
= lookup_attribute ("monitor", DECL_ATTRIBUTES (func
));
5329 return a
!= NULL_TREE
;
5332 /* Return nonzero if FUNC is a function that should be called
5333 through the function vector. */
5336 h8300_funcvec_function_p (tree func
)
5340 if (TREE_CODE (func
) != FUNCTION_DECL
)
5343 a
= lookup_attribute ("function_vector", DECL_ATTRIBUTES (func
));
5344 return a
!= NULL_TREE
;
5347 /* Return nonzero if DECL is a variable that's in the eight bit
5351 h8300_eightbit_data_p (tree decl
)
5355 if (TREE_CODE (decl
) != VAR_DECL
)
5358 a
= lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl
));
5359 return a
!= NULL_TREE
;
5362 /* Return nonzero if DECL is a variable that's in the tiny
5366 h8300_tiny_data_p (tree decl
)
5370 if (TREE_CODE (decl
) != VAR_DECL
)
5373 a
= lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl
));
5374 return a
!= NULL_TREE
;
5377 /* Generate an 'interrupt_handler' attribute for decls. We convert
5378 all the pragmas to corresponding attributes. */
5381 h8300_insert_attributes (tree node
, tree
*attributes
)
5383 if (TREE_CODE (node
) == FUNCTION_DECL
)
5385 if (pragma_interrupt
)
5387 pragma_interrupt
= 0;
5389 /* Add an 'interrupt_handler' attribute. */
5390 *attributes
= tree_cons (get_identifier ("interrupt_handler"),
5398 /* Add an 'saveall' attribute. */
5399 *attributes
= tree_cons (get_identifier ("saveall"),
5405 /* Supported attributes:
5407 interrupt_handler: output a prologue and epilogue suitable for an
5410 saveall: output a prologue and epilogue that saves and restores
5411 all registers except the stack pointer.
5413 function_vector: This function should be called through the
5416 eightbit_data: This variable lives in the 8-bit data area and can
5417 be referenced with 8-bit absolute memory addresses.
5419 tiny_data: This variable lives in the tiny data area and can be
5420 referenced with 16-bit absolute memory references. */
5422 static const struct attribute_spec h8300_attribute_table
[] =
5424 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
5425 affects_type_identity } */
5426 { "interrupt_handler", 0, 0, true, false, false,
5427 h8300_handle_fndecl_attribute
, false },
5428 { "saveall", 0, 0, true, false, false,
5429 h8300_handle_fndecl_attribute
, false },
5430 { "OS_Task", 0, 0, true, false, false,
5431 h8300_handle_fndecl_attribute
, false },
5432 { "monitor", 0, 0, true, false, false,
5433 h8300_handle_fndecl_attribute
, false },
5434 { "function_vector", 0, 0, true, false, false,
5435 h8300_handle_fndecl_attribute
, false },
5436 { "eightbit_data", 0, 0, true, false, false,
5437 h8300_handle_eightbit_data_attribute
, false },
5438 { "tiny_data", 0, 0, true, false, false,
5439 h8300_handle_tiny_data_attribute
, false },
5440 { NULL
, 0, 0, false, false, false, NULL
, false }
5444 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
5445 struct attribute_spec.handler. */
5447 h8300_handle_fndecl_attribute (tree
*node
, tree name
,
5448 tree args ATTRIBUTE_UNUSED
,
5449 int flags ATTRIBUTE_UNUSED
,
5452 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5454 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
5456 *no_add_attrs
= true;
5462 /* Handle an "eightbit_data" attribute; arguments as in
5463 struct attribute_spec.handler. */
5465 h8300_handle_eightbit_data_attribute (tree
*node
, tree name
,
5466 tree args ATTRIBUTE_UNUSED
,
5467 int flags ATTRIBUTE_UNUSED
,
5472 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5474 set_decl_section_name (decl
, ".eight");
5478 warning (OPT_Wattributes
, "%qE attribute ignored",
5480 *no_add_attrs
= true;
5486 /* Handle an "tiny_data" attribute; arguments as in
5487 struct attribute_spec.handler. */
5489 h8300_handle_tiny_data_attribute (tree
*node
, tree name
,
5490 tree args ATTRIBUTE_UNUSED
,
5491 int flags ATTRIBUTE_UNUSED
,
5496 if (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
))
5498 set_decl_section_name (decl
, ".tiny");
5502 warning (OPT_Wattributes
, "%qE attribute ignored",
5504 *no_add_attrs
= true;
5510 /* Mark function vectors, and various small data objects. */
5513 h8300_encode_section_info (tree decl
, rtx rtl
, int first
)
5515 int extra_flags
= 0;
5517 default_encode_section_info (decl
, rtl
, first
);
5519 if (TREE_CODE (decl
) == FUNCTION_DECL
5520 && h8300_funcvec_function_p (decl
))
5521 extra_flags
= SYMBOL_FLAG_FUNCVEC_FUNCTION
;
5522 else if (TREE_CODE (decl
) == VAR_DECL
5523 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
5525 if (h8300_eightbit_data_p (decl
))
5526 extra_flags
= SYMBOL_FLAG_EIGHTBIT_DATA
;
5527 else if (first
&& h8300_tiny_data_p (decl
))
5528 extra_flags
= SYMBOL_FLAG_TINY_DATA
;
5532 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
5535 /* Output a single-bit extraction. */
5538 output_simode_bld (int bild
, rtx operands
[])
5542 /* Clear the destination register. */
5543 output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands
);
5545 /* Now output the bit load or bit inverse load, and store it in
5548 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5550 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5552 output_asm_insn ("bst\t#0,%w0", operands
);
5556 /* Determine if we can clear the destination first. */
5557 int clear_first
= (REG_P (operands
[0]) && REG_P (operands
[1])
5558 && REGNO (operands
[0]) != REGNO (operands
[1]));
5561 output_asm_insn ("sub.l\t%S0,%S0", operands
);
5563 /* Output the bit load or bit inverse load. */
5565 output_asm_insn ("bild\t%Z2,%Y1", operands
);
5567 output_asm_insn ("bld\t%Z2,%Y1", operands
);
5570 output_asm_insn ("xor.l\t%S0,%S0", operands
);
5572 /* Perform the bit store. */
5573 output_asm_insn ("rotxl.l\t%S0", operands
);
5580 /* Delayed-branch scheduling is more effective if we have some idea
5581 how long each instruction will be. Use a shorten_branches pass
5582 to get an initial estimate. */
5587 if (flag_delayed_branch
)
5588 shorten_branches (get_insns ());
5591 #ifndef OBJECT_FORMAT_ELF
5593 h8300_asm_named_section (const char *name
, unsigned int flags ATTRIBUTE_UNUSED
,
5596 /* ??? Perhaps we should be using default_coff_asm_named_section. */
5597 fprintf (asm_out_file
, "\t.section %s\n", name
);
5599 #endif /* ! OBJECT_FORMAT_ELF */
5601 /* Nonzero if X is a constant address suitable as an 8-bit absolute,
5602 which is a special case of the 'R' operand. */
5605 h8300_eightbit_constant_address_p (rtx x
)
5607 /* The ranges of the 8-bit area. */
5608 const unsigned HOST_WIDE_INT n1
= trunc_int_for_mode (0xff00, HImode
);
5609 const unsigned HOST_WIDE_INT n2
= trunc_int_for_mode (0xffff, HImode
);
5610 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00ffff00, SImode
);
5611 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00ffffff, SImode
);
5612 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0xffffff00, SImode
);
5613 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0xffffffff, SImode
);
5615 unsigned HOST_WIDE_INT addr
;
5617 /* We accept symbols declared with eightbit_data. */
5618 if (GET_CODE (x
) == SYMBOL_REF
)
5619 return (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0;
5621 if (GET_CODE (x
) == CONST
5622 && GET_CODE (XEXP (x
, 0)) == PLUS
5623 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
5624 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x
, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA
) != 0)
5627 if (GET_CODE (x
) != CONST_INT
)
5633 || ((TARGET_H8300
|| TARGET_NORMAL_MODE
) && IN_RANGE (addr
, n1
, n2
))
5634 || (TARGET_H8300H
&& IN_RANGE (addr
, h1
, h2
))
5635 || (TARGET_H8300S
&& IN_RANGE (addr
, s1
, s2
)));
5638 /* Nonzero if X is a constant address suitable as an 16-bit absolute
5639 on H8/300H and H8S. */
5642 h8300_tiny_constant_address_p (rtx x
)
5644 /* The ranges of the 16-bit area. */
5645 const unsigned HOST_WIDE_INT h1
= trunc_int_for_mode (0x00000000, SImode
);
5646 const unsigned HOST_WIDE_INT h2
= trunc_int_for_mode (0x00007fff, SImode
);
5647 const unsigned HOST_WIDE_INT h3
= trunc_int_for_mode (0x00ff8000, SImode
);
5648 const unsigned HOST_WIDE_INT h4
= trunc_int_for_mode (0x00ffffff, SImode
);
5649 const unsigned HOST_WIDE_INT s1
= trunc_int_for_mode (0x00000000, SImode
);
5650 const unsigned HOST_WIDE_INT s2
= trunc_int_for_mode (0x00007fff, SImode
);
5651 const unsigned HOST_WIDE_INT s3
= trunc_int_for_mode (0xffff8000, SImode
);
5652 const unsigned HOST_WIDE_INT s4
= trunc_int_for_mode (0xffffffff, SImode
);
5654 unsigned HOST_WIDE_INT addr
;
5656 switch (GET_CODE (x
))
5659 /* In the normal mode, any symbol fits in the 16-bit absolute
5660 address range. We also accept symbols declared with
5662 return (TARGET_NORMAL_MODE
5663 || (SYMBOL_REF_FLAGS (x
) & SYMBOL_FLAG_TINY_DATA
) != 0);
5667 return (TARGET_NORMAL_MODE
5669 && (IN_RANGE (addr
, h1
, h2
) || IN_RANGE (addr
, h3
, h4
)))
5671 && (IN_RANGE (addr
, s1
, s2
) || IN_RANGE (addr
, s3
, s4
))));
5674 return TARGET_NORMAL_MODE
;
5682 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory
5683 locations that can be accessed as a 16-bit word. */
5686 byte_accesses_mergeable_p (rtx addr1
, rtx addr2
)
5688 HOST_WIDE_INT offset1
, offset2
;
5696 else if (GET_CODE (addr1
) == PLUS
5697 && REG_P (XEXP (addr1
, 0))
5698 && GET_CODE (XEXP (addr1
, 1)) == CONST_INT
)
5700 reg1
= XEXP (addr1
, 0);
5701 offset1
= INTVAL (XEXP (addr1
, 1));
5711 else if (GET_CODE (addr2
) == PLUS
5712 && REG_P (XEXP (addr2
, 0))
5713 && GET_CODE (XEXP (addr2
, 1)) == CONST_INT
)
5715 reg2
= XEXP (addr2
, 0);
5716 offset2
= INTVAL (XEXP (addr2
, 1));
5721 if (((reg1
== stack_pointer_rtx
&& reg2
== stack_pointer_rtx
)
5722 || (reg1
== frame_pointer_rtx
&& reg2
== frame_pointer_rtx
))
5724 && offset1
+ 1 == offset2
)
5730 /* Return nonzero if we have the same comparison insn as I3 two insns
5731 before I3. I3 is assumed to be a comparison insn. */
5734 same_cmp_preceding_p (rtx_insn
*i3
)
5738 /* Make sure we have a sequence of three insns. */
5739 i2
= prev_nonnote_insn (i3
);
5742 i1
= prev_nonnote_insn (i2
);
5746 return (INSN_P (i1
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5747 && any_condjump_p (i2
) && onlyjump_p (i2
));
5750 /* Return nonzero if we have the same comparison insn as I1 two insns
5751 after I1. I1 is assumed to be a comparison insn. */
5754 same_cmp_following_p (rtx_insn
*i1
)
5758 /* Make sure we have a sequence of three insns. */
5759 i2
= next_nonnote_insn (i1
);
5762 i3
= next_nonnote_insn (i2
);
5766 return (INSN_P (i3
) && rtx_equal_p (PATTERN (i1
), PATTERN (i3
))
5767 && any_condjump_p (i2
) && onlyjump_p (i2
));
5770 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes
5771 (or pops) N registers. OPERANDS are assumed to be an array of
5775 h8300_regs_ok_for_stm (int n
, rtx operands
[])
5780 return ((REGNO (operands
[0]) == 0 && REGNO (operands
[1]) == 1)
5781 || (REGNO (operands
[0]) == 2 && REGNO (operands
[1]) == 3)
5782 || (REGNO (operands
[0]) == 4 && REGNO (operands
[1]) == 5));
5784 return ((REGNO (operands
[0]) == 0
5785 && REGNO (operands
[1]) == 1
5786 && REGNO (operands
[2]) == 2)
5787 || (REGNO (operands
[0]) == 4
5788 && REGNO (operands
[1]) == 5
5789 && REGNO (operands
[2]) == 6));
5792 return (REGNO (operands
[0]) == 0
5793 && REGNO (operands
[1]) == 1
5794 && REGNO (operands
[2]) == 2
5795 && REGNO (operands
[3]) == 3);
5801 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
5804 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5805 unsigned int new_reg
)
5807 /* Interrupt functions can only use registers that have already been
5808 saved by the prologue, even if they would normally be
5811 if (h8300_current_function_interrupt_function_p ()
5812 && !df_regs_ever_live_p (new_reg
))
5818 /* Returns true if register REGNO is safe to be allocated as a scratch
5819 register in the current function. */
5822 h8300_hard_regno_scratch_ok (unsigned int regno
)
5824 if (h8300_current_function_interrupt_function_p ()
5825 && ! WORD_REG_USED (regno
))
5832 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */
5835 h8300_rtx_ok_for_base_p (rtx x
, int strict
)
5837 /* Strip off SUBREG if any. */
5838 if (GET_CODE (x
) == SUBREG
)
5843 ? REG_OK_FOR_BASE_STRICT_P (x
)
5844 : REG_OK_FOR_BASE_NONSTRICT_P (x
)));
5847 /* Return nozero if X is a legitimate address. On the H8/300, a
5848 legitimate address has the form REG, REG+CONSTANT_ADDRESS or
5849 CONSTANT_ADDRESS. */
5852 h8300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
5854 /* The register indirect addresses like @er0 is always valid. */
5855 if (h8300_rtx_ok_for_base_p (x
, strict
))
5858 if (CONSTANT_ADDRESS_P (x
))
5862 && ( GET_CODE (x
) == PRE_INC
5863 || GET_CODE (x
) == PRE_DEC
5864 || GET_CODE (x
) == POST_INC
5865 || GET_CODE (x
) == POST_DEC
)
5866 && h8300_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
5869 if (GET_CODE (x
) == PLUS
5870 && CONSTANT_ADDRESS_P (XEXP (x
, 1))
5871 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x
, 0),
5878 /* Worker function for HARD_REGNO_NREGS.
5880 We pretend the MAC register is 32bits -- we don't have any data
5881 types on the H8 series to handle more than 32bits. */
5884 h8300_hard_regno_nregs (int regno ATTRIBUTE_UNUSED
, machine_mode mode
)
5886 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5889 /* Worker function for HARD_REGNO_MODE_OK. */
5892 h8300_hard_regno_mode_ok (int regno
, machine_mode mode
)
5895 /* If an even reg, then anything goes. Otherwise the mode must be
5897 return ((regno
& 1) == 0) || (mode
== HImode
) || (mode
== QImode
);
5899 /* MAC register can only be of SImode. Otherwise, anything
5901 return regno
== MAC_REG
? mode
== SImode
: 1;
5904 /* Helper function for the move patterns. Make sure a move is legitimate. */
5907 h8300_move_ok (rtx dest
, rtx src
)
5911 /* Validate that at least one operand is a register. */
5914 if (MEM_P (src
) || CONSTANT_P (src
))
5916 addr
= XEXP (dest
, 0);
5919 else if (MEM_P (src
))
5921 addr
= XEXP (src
, 0);
5927 /* Validate that auto-inc doesn't affect OTHER. */
5928 if (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
)
5930 addr
= XEXP (addr
, 0);
5932 if (addr
== stack_pointer_rtx
)
5933 return register_no_sp_elim_operand (other
, VOIDmode
);
5935 return !reg_overlap_mentioned_p(other
, addr
);
5938 /* Perform target dependent optabs initialization. */
5940 h8300_init_libfuncs (void)
5942 set_optab_libfunc (smul_optab
, HImode
, "__mulhi3");
5943 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
5944 set_optab_libfunc (udiv_optab
, HImode
, "__udivhi3");
5945 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
5946 set_optab_libfunc (umod_optab
, HImode
, "__umodhi3");
5949 /* Worker function for TARGET_FUNCTION_VALUE.
5951 On the H8 the return value is in R0/R1. */
5954 h8300_function_value (const_tree ret_type
,
5955 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
5956 bool outgoing ATTRIBUTE_UNUSED
)
5958 return gen_rtx_REG (TYPE_MODE (ret_type
), R0_REG
);
5961 /* Worker function for TARGET_LIBCALL_VALUE.
5963 On the H8 the return value is in R0/R1. */
5966 h8300_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5968 return gen_rtx_REG (mode
, R0_REG
);
5971 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
5973 On the H8, R0 is the only register thus used. */
5976 h8300_function_value_regno_p (const unsigned int regno
)
5978 return (regno
== R0_REG
);
5981 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5984 h8300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5986 return (TYPE_MODE (type
) == BLKmode
5987 || GET_MODE_SIZE (TYPE_MODE (type
)) > (TARGET_H8300
? 4 : 8));
5990 /* We emit the entire trampoline here. Depending on the pointer size,
5991 we use a different trampoline.
5995 1 0000 7903xxxx mov.w #0x1234,r3
5996 2 0004 5A00xxxx jmp @0x1234
6001 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3
6002 3 0006 5Axxxxxx jmp @0x123456
6007 h8300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
6009 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6012 if (Pmode
== HImode
)
6014 mem
= adjust_address (m_tramp
, HImode
, 0);
6015 emit_move_insn (mem
, GEN_INT (0x7903));
6016 mem
= adjust_address (m_tramp
, Pmode
, 2);
6017 emit_move_insn (mem
, cxt
);
6018 mem
= adjust_address (m_tramp
, HImode
, 4);
6019 emit_move_insn (mem
, GEN_INT (0x5a00));
6020 mem
= adjust_address (m_tramp
, Pmode
, 6);
6021 emit_move_insn (mem
, fnaddr
);
6027 mem
= adjust_address (m_tramp
, HImode
, 0);
6028 emit_move_insn (mem
, GEN_INT (0x7a03));
6029 mem
= adjust_address (m_tramp
, Pmode
, 2);
6030 emit_move_insn (mem
, cxt
);
6032 tem
= copy_to_reg (fnaddr
);
6033 emit_insn (gen_andsi3 (tem
, tem
, GEN_INT (0x00ffffff)));
6034 emit_insn (gen_iorsi3 (tem
, tem
, GEN_INT (0x5a000000)));
6035 mem
= adjust_address (m_tramp
, SImode
, 6);
6036 emit_move_insn (mem
, tem
);
6040 /* Initialize the GCC target structure. */
6041 #undef TARGET_ATTRIBUTE_TABLE
6042 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table
6044 #undef TARGET_ASM_ALIGNED_HI_OP
6045 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
6047 #undef TARGET_ASM_FILE_START
6048 #define TARGET_ASM_FILE_START h8300_file_start
6049 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
6050 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
6052 #undef TARGET_ASM_FILE_END
6053 #define TARGET_ASM_FILE_END h8300_file_end
6055 #undef TARGET_PRINT_OPERAND
6056 #define TARGET_PRINT_OPERAND h8300_print_operand
6057 #undef TARGET_PRINT_OPERAND_ADDRESS
6058 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address
6059 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
6060 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p
6062 #undef TARGET_ENCODE_SECTION_INFO
6063 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info
6065 #undef TARGET_INSERT_ATTRIBUTES
6066 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes
6068 #undef TARGET_REGISTER_MOVE_COST
6069 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost
6071 #undef TARGET_RTX_COSTS
6072 #define TARGET_RTX_COSTS h8300_rtx_costs
6074 #undef TARGET_INIT_LIBFUNCS
6075 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs
6077 #undef TARGET_FUNCTION_VALUE
6078 #define TARGET_FUNCTION_VALUE h8300_function_value
6080 #undef TARGET_LIBCALL_VALUE
6081 #define TARGET_LIBCALL_VALUE h8300_libcall_value
6083 #undef TARGET_FUNCTION_VALUE_REGNO_P
6084 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p
6086 #undef TARGET_RETURN_IN_MEMORY
6087 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory
6089 #undef TARGET_FUNCTION_ARG
6090 #define TARGET_FUNCTION_ARG h8300_function_arg
6092 #undef TARGET_FUNCTION_ARG_ADVANCE
6093 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance
6095 #undef TARGET_MACHINE_DEPENDENT_REORG
6096 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg
6098 #undef TARGET_HARD_REGNO_SCRATCH_OK
6099 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok
6102 #define TARGET_LRA_P hook_bool_void_false
6104 #undef TARGET_LEGITIMATE_ADDRESS_P
6105 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p
6107 #undef TARGET_CAN_ELIMINATE
6108 #define TARGET_CAN_ELIMINATE h8300_can_eliminate
6110 #undef TARGET_CONDITIONAL_REGISTER_USAGE
6111 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage
6113 #undef TARGET_TRAMPOLINE_INIT
6114 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init
6116 #undef TARGET_OPTION_OVERRIDE
6117 #define TARGET_OPTION_OVERRIDE h8300_option_override
6119 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
6120 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p
6122 struct gcc_target targetm
= TARGET_INITIALIZER
;