1 /* Definitions of target machine for GNU compiler. Gmicro (TRON) version.
2 Copyright (C) 1987, 88, 89, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Masanobu Yuhara, Fujitsu Laboratories LTD.
4 (yuhara@flab.fujitsu.co.jp)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
28 /* Names to predefine in the preprocessor for this target machine. */
30 #define CPP_PREDEFINES "-Dgmicro -Acpu(tron) -Amachine(tron)"
32 /* #define CPP_SPEC ** currently not defined **/
34 /* #define CC1_SPEC ** currently not defined **/
37 /* Print subsidiary information on the compiler version in use. */
39 #define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
42 /* Run-time compilation parameters selecting different hardware subsets. */
44 extern int target_flags
;
46 /* Macros used in the machine description to test the flags. */
48 /* Compile for a Gmicro/300. */
49 #define TARGET_G300 (target_flags & 1)
50 /* Compile for a Gmicro/200. */
51 #define TARGET_G200 (target_flags & 2)
52 /* Compile for a Gmicro/100. */
53 #define TARGET_G100 (target_flags & 4)
55 /* Compile FPU insns for floating point (not library calls). */
56 #define TARGET_FPU (target_flags & 8)
58 /* Pop up arguments by called function. */
59 #define TARGET_RTD (target_flags & 0x10)
61 /* Compile passing first args in regs 0 and 1.
62 This exists only to test compiler features that will be needed for
63 RISC chips. It is not usable and is not intended to be usable on
65 #define TARGET_REGPARM (target_flags & 0x20)
67 #define TARGET_BITFIELD (target_flags & 0x40)
69 #define TARGET_NEWRETURN (target_flags & 0x80)
71 /* Do not expand __builtin_smov (strcpy) to multiple movs.
72 Use the smov instruction. */
73 #define TARGET_FORCE_SMOV (target_flags & 0x100)
75 /* default options are -m300, -mFPU,
76 with bitfield instructions added because it won't always work otherwise.
77 If there are versions of the gmicro that don't support bitfield instructions
78 then it will take some thinking to figure out how to make them work. */
79 #define TARGET_DEFAULT 0x49
81 /* Macro to define tables used to set the flags.
82 This is a list in braces of pairs in braces,
83 each pair being { "NAME", VALUE }
84 where VALUE is the bits to set or minus the bits to clear.
85 An empty string NAME is used to identify the default VALUE. */
87 #define TARGET_SWITCHES \
92 { "soft-float", -8}, \
96 { "no-regparm", -0x20}, \
97 #if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
98 STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions. */
99 { "bitfield", 0x40}, \
100 { "no-bitfield", -0x40}, \
102 { "newreturn", 0x80}, \
103 { "no-newreturn", -0x80}, \
104 { "force-smov", 0x100}, \
105 { "no-force-smov", -0x100}, \
106 { "", TARGET_DEFAULT
}}
109 /* Blow away G100 flag silently off TARGET_fpu (since we can't clear
110 any bits in TARGET_SWITCHES above) */
111 #define OVERRIDE_OPTIONS \
113 if (TARGET_G100) target_flags &= ~8; \
116 /* target machine storage layout */
118 /* Define this if most significant bit is lowest numbered
119 in instructions that operate on numbered bit-fields.
120 This is true for Gmicro insns.
121 We make it true always by avoiding using the single-bit insns
122 except in special cases with constant bit numbers. */
123 #define BITS_BIG_ENDIAN 1
125 /* Define this if most significant byte of a word is the lowest numbered. */
126 /* That is true on the Gmicro. */
127 #define BYTES_BIG_ENDIAN 1
129 /* Define this if most significant word of a multiword number is the lowest
131 /* For Gmicro we can decide arbitrarily
132 since there are no machine instructions for them. ????? */
133 #define WORDS_BIG_ENDIAN 0
135 /* number of bits in an addressable storage unit */
136 #define BITS_PER_UNIT 8
138 /* Width in bits of a "word", which is the contents of a machine register. */
139 #define BITS_PER_WORD 32
141 /* Width of a word, in units (bytes). */
142 #define UNITS_PER_WORD 4
144 /* Width in bits of a pointer.
145 See also the macro `Pmode' defined below. */
146 #define POINTER_SIZE 32
148 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
149 #define PARM_BOUNDARY 32
151 /* Boundary (in *bits*) on which stack pointer should be aligned. */
152 #define STACK_BOUNDARY 32
154 /* Allocation boundary (in *bits*) for the code of a function. */
155 /* Instructions of the Gmicro should be on half-word boundary */
156 /* But word boundary gets better performance */
157 #define FUNCTION_BOUNDARY 32
159 /* Alignment of field after `int : 0' in a structure. */
160 #define EMPTY_FIELD_BOUNDARY 32
162 /* No data type wants to be aligned rounder than this. */
163 /* This is not necessarily 32 on the Gmicro */
164 #define BIGGEST_ALIGNMENT 32
166 /* Set this non-zero if move instructions will actually fail to work
167 when given unaligned data.
168 Unaligned data is allowed on Gmicro, though the access is slow. */
170 #define STRICT_ALIGNMENT 1
171 #define SLOW_UNALIGNED_ACCESS 1
173 /* Make strings word-aligned so strcpy from constants will be faster. */
174 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
175 (TREE_CODE (EXP) == STRING_CST \
176 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
178 /* Make arrays of chars word-aligned for the same reasons. */
179 #define DATA_ALIGNMENT(TYPE, ALIGN) \
180 (TREE_CODE (TYPE) == ARRAY_TYPE \
181 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
182 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
184 /* Define number of bits in most basic integer type.
185 (If undefined, default is BITS_PER_WORD). */
186 #define INT_TYPE_SIZE 32
188 /* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */
190 /* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */
193 /* Standard register usage. */
195 /* Number of actual hardware registers.
196 The hardware registers are assigned numbers for the compiler
197 from 0 to just below FIRST_PSEUDO_REGISTER.
198 All registers that the compiler knows about must be given numbers,
199 even those that are not normally considered general registers.
200 For the Gmicro, we give the general registers numbers 0-15,
201 and the FPU floating point registers numbers 16-31. */
202 #define FIRST_PSEUDO_REGISTER 32
204 /* 1 for registers that have pervasive standard uses
205 and are not available for the register allocator.
206 On the Gmicro, the stack pointer and the frame pointer are
208 /* frame pointer is not indicated as fixed, because fp may be used freely
209 when a frame is not built. */
210 #define FIXED_REGISTERS \
211 {0, 0, 0, 0, 0, 0, 0, 0, \
212 0, 0, 0, 0, 0, 0, 0, 1, \
213 /* FPU registers. */ \
214 0, 0, 0, 0, 0, 0, 0, 0, \
215 0, 0, 0, 0, 0, 0, 0, 0, }
217 /* 1 for registers not available across function calls.
218 These must include the FIXED_REGISTERS and also any
219 registers that can be used without being saved.
220 The latter must include the registers where values are returned
221 and the register where structure-value addresses are passed.
222 Aside from that, you can include as many other registers as you like. */
223 #define CALL_USED_REGISTERS \
224 {1, 1, 1, 1, 0, 0, 0, 0, \
225 0, 0, 0, 0, 0, 0, 0, 1, \
226 /* FPU registers. */ \
227 1, 1, 1, 1, 0, 0, 0, 0, \
228 0, 0, 0, 0, 0, 0, 0, 0, }
231 /* Make sure everything's fine if we *don't* have a given processor.
232 This assumes that putting a register in fixed_regs will keep the
233 compilers mitt's completely off it. We don't bother to zero it out
234 of register classes. If TARGET_FPU is not set,
235 the compiler won't touch since no instructions that use these
236 registers will be valid. */
237 /* This Macro is not defined now.
238 #define CONDITIONAL_REGISTER_USAGE */
240 /* The Gmicro has no overlapping register */
241 /* #define OVERLAPPING_REGNO_P(REGNO) */
243 /* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO) */
245 /* Return number of consecutive hard regs needed starting at reg REGNO
246 to hold something of mode MODE.
247 This is ordinarily the length in words of a value of mode MODE
248 but can be less for certain modes in special long registers.
250 On the Gmicro, ordinary registers hold 32 bits worth;
251 for the Gmicro/FPU registers, a single register is always enough for
252 anything that can be stored in them at all. */
253 #define HARD_REGNO_NREGS(REGNO, MODE) \
255 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
257 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
258 On the Gmicro, the cpu registers can hold any mode but the FPU registers
259 can hold only SFmode or DFmode. And the FPU registers can't hold anything
260 if FPU use is disabled. */
261 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
264 ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT || \
265 GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
268 /* Value is 1 if it is a good idea to tie two pseudo registers
269 when one has mode MODE1 and one has mode MODE2.
270 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
271 for any hard reg, then this must be 0 for correct output. */
272 #define MODES_TIEABLE_P(MODE1, MODE2) \
274 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
275 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
276 == ((MODE2) == SFmode || (MODE2) == DFmode)))
278 /* Specify the registers used for certain standard purposes.
279 The values of these macros are register numbers. */
281 /* Gmicro pc isn't overloaded on a register. */
282 /* #define PC_REGNUM */
284 /* Register to use for pushing function arguments. */
285 #define STACK_POINTER_REGNUM 15
287 /* Base register for access to local variables of the function. */
288 #define FRAME_POINTER_REGNUM 14
290 /* Value should be nonzero if functions must have frame pointers.
291 Zero means the frame pointer need not be set up (and parms
292 may be accessed via the stack pointer) in functions that seem suitable.
293 This is computed in `reload', in reload1.c. */
294 #define FRAME_POINTER_REQUIRED 0
296 /* Base register for access to arguments of the function. */
297 /* The Gmicro does not have hardware ap. Fp is treated as ap */
298 #define ARG_POINTER_REGNUM 14
300 /* Register in which static-chain is passed to a function. */
301 #define STATIC_CHAIN_REGNUM 0
303 /* Register in which address to store a structure value
304 is passed to a function. */
305 #define STRUCT_VALUE_REGNUM 1
307 /* Define the classes of registers for register constraints in the
308 machine description. Also define ranges of constants.
310 One of the classes must always be named ALL_REGS and include all hard regs.
311 If there is more than one class, another class must be named NO_REGS
312 and contain no registers.
314 The name GENERAL_REGS must be the name of a class (or an alias for
315 another name such as ALL_REGS). This is the class of registers
316 that is allowed by "g" or "r" in a register constraint.
317 Also, registers outside this class are allocated only when
318 instructions express preferences for them.
320 The classes must be numbered in nondecreasing order; that is,
321 a larger-numbered class must never be contained completely
322 in a smaller-numbered class.
324 For any two classes, it is very desirable that there be another
325 class that represents their union. */
327 /* The Gmicro has two kinds of registers, so four classes would be
330 enum reg_class
{ NO_REGS
, FPU_REGS
, GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
332 #define N_REG_CLASSES (int) LIM_REG_CLASSES
334 /* Give names of register classes as strings for dump file. */
336 #define REG_CLASS_NAMES \
337 { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" }
339 /* Define which registers fit in which classes.
340 This is an initializer for a vector of HARD_REG_SET
341 of length N_REG_CLASSES. */
343 #define REG_CLASS_CONTENTS \
346 0xffff0000, /* FPU_REGS */ \
347 0x0000ffff, /* GENERAL_REGS */ \
348 0xffffffff /* ALL_REGS */ \
351 /* The same information, inverted:
352 Return the class number of the smallest class containing
353 reg number REGNO. This could be a conditional expression
354 or could index an array. */
356 extern enum reg_class regno_reg_class
[];
357 #define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS )
359 /* The class value for index registers, and the one for base regs. */
361 #define INDEX_REG_CLASS GENERAL_REGS
362 #define BASE_REG_CLASS GENERAL_REGS
364 /* Get reg_class from a letter such as appears in the machine description.
365 We do a trick here to modify the effective constraints on the
366 machine description; we zorch the constraint letters that aren't
367 appropriate for a specific target. This allows us to guarantee
368 that a specific kind of register will not be used for a given target
369 without fiddling with the register classes above. */
371 #define REG_CLASS_FROM_LETTER(C) \
372 ((C) == 'r' ? GENERAL_REGS : \
373 ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) : \
376 /* The letters I, J, K, L and M in a register constraint string
377 can be used to stand for particular ranges of immediate operands.
378 This macro defines what the ranges are.
379 C is the letter, and VALUE is a constant value.
380 Return 1 if VALUE is in the range specified by C.
382 For the Gmicro, all immediate value optimizations are done
383 by assembler, so no machine dependent definition is necessary ??? */
385 /* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */
386 #define CONST_OK_FOR_LETTER_P(VALUE, C) 0
389 * The letters G defines all of the floating constants tha are *NOT*
390 * Gmicro-FPU constant.
393 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
395 (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE)))
397 /* Given an rtx X being reloaded into a reg required to be
398 in class CLASS, return the class of reg to actually use.
399 In general this is just CLASS; but on some machines
400 in some cases it is preferable to use a more restrictive class. */
401 /* On the Gmicro series, there is no restriction on GENERAL_REGS,
402 so CLASS is returned. I do not know whether I should treat FPU_REGS
403 specially or not (at least, m68k does not). */
405 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
407 /* Return the maximum number of consecutive registers
408 needed to represent mode MODE in a register of class CLASS. */
409 /* On the Gmicro, this is the size of MODE in words,
410 except in the FPU regs, where a single reg is always enough. */
411 #define CLASS_MAX_NREGS(CLASS, MODE) \
412 ((CLASS) == FPU_REGS ? \
413 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
415 /* Stack layout; function entry, exit and calling. */
417 /* Define this if pushing a word on the stack
418 makes the stack pointer a smaller address. */
419 #define STACK_GROWS_DOWNWARD
421 /* Define this if the nominal address of the stack frame
422 is at the high-address end of the local variables;
423 that is, each additional local variable allocated
424 goes at a more negative offset in the frame. */
425 #define FRAME_GROWS_DOWNWARD
427 /* Offset within stack frame to start allocating local variables at.
428 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
429 first local allocated. Otherwise, it is the offset to the BEGINNING
430 of the first local allocated. */
431 /* On the Gmicro, FP points to the old FP and the first local variables are
433 #define STARTING_FRAME_OFFSET 0
435 /* If we generate an insn to push BYTES bytes,
436 this says how many the stack pointer really advances by. */
437 /* On the Gmicro, sp is decremented by the exact size of the operand */
438 #define PUSH_ROUNDING(BYTES) (BYTES)
440 /* Offset of first parameter from the argument pointer register value. */
441 /* On the Gmicro, the first argument is found at (ap + 8) where ap is fp. */
442 #define FIRST_PARM_OFFSET(FNDECL) 8
444 /* Value is the number of byte of arguments automatically
445 popped when returning from a subroutine call.
446 FUNDECL is the declaration node of the function (as a tree),
447 FUNTYPE is the data type of the function (as a tree),
448 or for a library call it is an identifier node for the subroutine name.
449 SIZE is the number of bytes of arguments passed on the stack.
451 On the Gmicro, the EXITD insn may be used to pop them if the number
452 of args is fixed, but if the number is variable then the caller must pop
453 them all. The adjsp operand of the EXITD insn can't be used for library
454 calls now because the library is compiled with the standard compiler.
455 Use of adjsp operand is a selectable option, since it is incompatible with
456 standard Unix calling sequences. If the option is not selected,
457 the caller must always pop the args.
458 On the m68k this is an RTD option, so I use the same name
459 for the Gmicro. The option name may be changed in the future. */
461 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
462 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
463 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
464 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
465 == void_type_node))) \
468 /* Define how to find the value returned by a function.
469 VALTYPE is the data type of the value (as a tree).
470 If the precise function being called is known, FUNC is its FUNCTION_DECL;
471 otherwise, FUNC is 0. */
473 /* On the Gmicro the floating return value is in fr0 not r0. */
475 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
477 /* Define how to find the value returned by a library function
478 assuming the value has mode MODE. */
480 #define LIBCALL_VALUE(MODE) \
481 (gen_rtx (REG, (MODE), \
482 ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0)))
485 /* 1 if N is a possible register number for a function value.
486 On the Gmicro, r0 and fp0 are the possible registers. */
488 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
490 /* Define this if PCC uses the nonreentrant convention for returning
491 structure and union values. */
493 #define PCC_STATIC_STRUCT_RETURN
495 /* 1 if N is a possible register number for function argument passing.
496 On the Gmicro, no registers are used in this way. */
497 /* Really? For the performance improvement, registers should be used !! */
499 #define FUNCTION_ARG_REGNO_P(N) 0
501 /* Define a data type for recording info about an argument list
502 during the scan of that argument list. This data type should
503 hold all necessary information about the function itself
504 and about the args processed so far, enough to enable macros
505 such as FUNCTION_ARG to determine where the next arg should go.
507 On the Gmicro, this is a single integer, which is a number of bytes
508 of arguments scanned so far. */
510 #define CUMULATIVE_ARGS int
512 /* Initialize a variable CUM of type CUMULATIVE_ARGS
513 for a call to a function whose data type is FNTYPE.
514 For a library call, FNTYPE is 0.
516 On the Gmicro, the offset starts at 0. */
518 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
521 /* Update the data in CUM to advance over an argument
522 of mode MODE and data type TYPE.
523 (TYPE is null for libcalls where that information may not be available.) */
525 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
526 ((CUM) += ((MODE) != BLKmode \
527 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
528 : (int_size_in_bytes (TYPE) + 3) & ~3))
530 /* Define where to put the arguments to a function.
531 Value is zero to push the argument on the stack,
532 or a hard register in which to store the argument.
534 MODE is the argument's machine mode.
535 TYPE is the data type of the argument (as a tree).
536 This is null for libcalls where that information may
538 CUM is a variable of type CUMULATIVE_ARGS which gives info about
539 the preceding args and about the function being called.
540 NAMED is nonzero if this argument is a named parameter
541 (otherwise it is an extra parameter matching an ellipsis). */
543 /* On the Gmicro all args are pushed, except if -mregparm is specified
544 then the first two words of arguments are passed in d0, d1.
545 *NOTE* -mregparm does not work.
546 It exists only to test register calling conventions. */
548 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
549 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
551 /* For an arg passed partly in registers and partly in memory,
552 this is the number of registers used.
553 For args passed entirely in registers or entirely in memory, zero. */
555 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
556 ((TARGET_REGPARM && (CUM) < 8 \
557 && 8 < ((CUM) + ((MODE) == BLKmode \
558 ? int_size_in_bytes (TYPE) \
559 : GET_MODE_SIZE (MODE)))) \
562 /* The following macro is defined to output register list.
563 The LSB of Mask is the lowest number register.
564 Regoff is MY_GREG_OFF or MY_FREG_OFF.
565 Do NOT use <i> in File, Mask, Regoff !!
566 Should be changed from macros to functions. M.Yuhara */
568 #define MY_GREG_OFF 0
569 #define MY_FREG_OFF 16
571 #define MY_PRINT_MASK(File, Mask, Regoff) \
575 fprintf(File, "#0"); \
577 fprintf(File, "("); \
578 for (i = 0; i < 16; i++) { \
579 if ( (Mask) & (1 << i) ) { \
582 fprintf(File, ","); \
585 fprintf(File, "%s", reg_names[Regoff + i]); \
587 } else if (first >= 0) { \
588 if (i > first + 1) { \
589 fprintf(File, "-%s", reg_names[Regoff + i - 1]); \
594 if ( (first >= 0) && (first != 15) ) \
595 fprintf(File, "-%s", reg_names[Regoff + 15]);\
596 fprintf(File, ")"); \
601 #define MY_PRINT_ONEREG_L(FILE,MASK) \
603 for (i = 0; i < 16; i++) \
604 if ( (1 << i) & (MASK)) { \
605 fprintf(FILE, "%s", reg_names[i]); \
606 (MASK) &= ~(1 << i); \
612 #define MY_PRINT_ONEREG_H(FILE,MASK) \
614 for (i = 15; i >= 0; i--) \
615 if ( (1 << i) & (MASK)) { \
616 fprintf(FILE, "%s", reg_names[i]); \
617 (MASK) &= ~(1 << i); \
622 /* This macro generates the assembly code for function entry.
623 FILE is a stdio stream to output the code to.
624 SIZE is an int: how many units of temporary storage to allocate.
625 Refer to the array `regs_ever_live' to determine which registers
626 to save; `regs_ever_live[I]' is nonzero if register number I
627 is ever used in the function. This macro is responsible for
628 knowing which registers should not be saved even if used. */
630 /* The next macro needs much optimization !!
633 #define FUNCTION_PROLOGUE(FILE, SIZE) \
634 { register int regno; \
635 register int mask = 0; \
636 register int nregs = 0; \
637 static char *reg_names[] = REGISTER_NAMES; \
638 extern char call_used_regs[]; \
639 int fsize = ((SIZE) + 3) & -4; \
640 for (regno = 0; regno < 16; regno++) \
641 if (regs_ever_live[regno] && !call_used_regs[regno]) { \
642 mask |= (1 << regno); \
645 if (frame_pointer_needed) { \
646 mask &= ~(1 << FRAME_POINTER_REGNUM); \
648 fprintf(FILE, "\tenter.w #%d,", fsize); \
649 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
650 fprintf(FILE,"\n"); \
652 fprintf(FILE, "\tmov.w fp,@-sp\n"); \
653 fprintf(FILE, "\tmov.w sp,fp\n"); \
655 myoutput_sp_adjust(FILE, "sub", fsize); \
657 fprintf(FILE, "\tmov.w "); \
658 MY_PRINT_ONEREG_H(FILE, mask); \
659 fprintf(FILE, ",@-sp\n"); \
664 myoutput_sp_adjust(FILE, "sub", fsize); \
667 fprintf(FILE, "\tstm.w "); \
668 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
669 fprintf(FILE, ",@-sp\n"); \
672 fprintf(FILE, "\tmov.w "); \
673 MY_PRINT_ONEREG_H(FILE, mask); \
674 fprintf(FILE, ",@-sp\n"); \
680 for (regno = 16; regno < 32; regno++) \
681 if (regs_ever_live[regno] && !call_used_regs[regno]) \
682 mask |= 1 << (regno - 16); \
684 fprintf(FILE, "\tfstm.w "); \
685 MY_PRINT_MASK(FILE, mask, MY_FREG_OFF); \
686 fprintf(FILE, ",@-sp\n", mask); \
691 /* Output assembler code to FILE to increment profiler label # LABELNO
692 for profiling a function entry. */
695 #define FUNCTION_PROFILER(FILE, LABELNO) \
696 fprintf (FILE, "\tmova @LP%d,r0\n\tjsr mcount\n", (LABELNO))
698 /* Output assembler code to FILE to initialize this source file's
699 basic block profiling info, if that has not already been done. */
701 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
702 fprintf (FILE, "\tcmp #0,@LPBX0\n\tbne LPI%d\n\tpusha @LPBX0\n\tjsr ___bb_init_func\n\tadd #4,sp\nLPI%d:\n", \
705 /* Output assembler code to FILE to increment the entry-count for
706 the BLOCKNO'th basic block in this source file. */
708 #define BLOCK_PROFILER(FILE, BLOCKNO) \
709 fprintf (FILE, "\tadd #1,@(LPBX2+%d)\n", 4 * BLOCKNO)
711 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
712 the stack pointer does not matter. The value is tested only in
713 functions that have frame pointers.
714 No definition is equivalent to always zero. */
716 #define EXIT_IGNORE_STACK 1
718 /* This macro generates the assembly code for function exit,
719 on machines that need it. If FUNCTION_EPILOGUE is not defined
720 then individual return instructions are generated for each
721 return statement. Args are same as for FUNCTION_PROLOGUE.
723 The function epilogue should not depend on the current stack pointer (when
724 frame_pinter_needed) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
725 It should use the frame pointer only. This is mandatory because
726 of alloca; we also take advantage of it to omit stack adjustments
729 /* The Gmicro FPU seems to be unable to fldm/fstm double or single
730 floating. It only allows extended !! */
731 /* Optimization is not enough, especially FREGs load !! M.Yuhara */
733 #define FUNCTION_EPILOGUE(FILE, SIZE) \
734 { register int regno; \
735 register int mask, fmask; \
736 register int nregs, nfregs; \
737 int offset, foffset; \
738 extern char call_used_regs[]; \
739 static char *reg_names[] = REGISTER_NAMES; \
740 int fsize = ((SIZE) + 3) & -4; \
741 FUNCTION_EXTRA_EPILOGUE (FILE, SIZE); \
742 nfregs = 0; fmask = 0; \
743 for (regno = 16; regno < 31; regno++) \
744 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
745 { nfregs++; fmask |= 1 << (regno - 16); } \
746 foffset = nfregs * 12; \
747 nregs = 0; mask = 0; \
748 if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
749 for (regno = 0; regno < 16; regno++) \
750 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
751 { nregs++; mask |= 1 << regno; } \
752 if (frame_pointer_needed) { \
753 offset = nregs * 4 + fsize; \
755 fprintf(FILE, "\tfldm.x @(%d,fp),", -(foffset + offset));\
756 MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
757 fprintf(FILE, "\n"); \
760 || current_function_pops_args) { \
761 fprintf(FILE, "\tmova @(%d,fp),sp\n", -offset); \
762 fprintf(FILE, "\texitd "); \
763 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
764 fprintf(FILE, ",#%d\n", current_function_pops_args); \
767 fprintf(FILE, "\tmov:l.w @(%d,fp),", -offset); \
768 MY_PRINT_ONEREG_L(FILE, mask); \
769 fprintf(FILE, "\n"); \
772 if (TARGET_NEWRETURN) { \
773 fprintf(FILE, "\tmova.w @(4,fp),sp\n"); \
774 fprintf(FILE, "\tmov:l.w @fp,fp\n"); \
776 fprintf(FILE, "\tmov.w fp,sp\n"); \
777 fprintf(FILE, "\tmov.w @sp+,fp\n"); \
779 fprintf(FILE, "\trts\n"); \
783 fprintf(FILE, "\tfldm.w @sp+,"); \
784 MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
785 fprintf(FILE, "\n"); \
788 fprintf(FILE, "\tldm.w @sp+,"); \
789 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
790 fprintf(FILE, "\n"); \
793 fprintf(FILE, "\tmov.w @sp+,"); \
794 MY_PRINT_ONEREG_L(FILE,mask); \
795 fprintf(FILE, "\n"); \
798 if (current_function_pops_args) { \
799 myoutput_sp_adjust(FILE, "add", \
800 (fsize + 4 + current_function_pops_args)); \
801 fprintf(FILE, "\tjmp @(%d,sp)\n", current_function_pops_args);\
804 myoutput_sp_adjust(FILE, "add", fsize); \
805 fprintf(FILE, "\trts\n"); \
810 /* This is a hook for other tm files to change. */
811 #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)
813 /* If the memory address ADDR is relative to the frame pointer,
814 correct it to be relative to the stack pointer instead.
815 This is for when we don't use a frame pointer.
816 ADDR should be a variable name. */
818 /* You have to change the next macro if you want to use more complex
819 addressing modes (such as double indirection and more than one
820 chain-addressing stages). */
822 #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
824 rtx regs = stack_pointer_rtx; \
825 if (ADDR == frame_pointer_rtx) \
827 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
828 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
829 offset = INTVAL (XEXP (ADDR, 1)); \
830 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
831 { rtx other_reg = XEXP (ADDR, 1); \
833 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
834 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
835 { rtx other_reg = XEXP (ADDR, 0); \
837 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
838 else if (GET_CODE (ADDR) == PLUS \
839 && GET_CODE (XEXP (ADDR, 0)) == PLUS \
840 && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
841 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
842 { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
843 offset = INTVAL (XEXP (ADDR, 1)); \
844 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
845 else if (GET_CODE (ADDR) == PLUS \
846 && GET_CODE (XEXP (ADDR, 0)) == PLUS \
847 && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
848 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
849 { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
850 offset = INTVAL (XEXP (ADDR, 1)); \
851 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
854 extern char call_used_regs[]; \
855 for (regno = 16; regno < 32; regno++) \
856 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
858 for (regno = 0; regno < 16; regno++) \
859 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
862 ADDR = plus_constant (regs, offset + (DEPTH)); } }
864 /* Addressing modes, and classification of registers for them. */
866 /* #define HAVE_POST_INCREMENT 0 */
867 /* #define HAVE_POST_DECREMENT 0 */
869 /* #define HAVE_PRE_DECREMENT 0 */
870 /* #define HAVE_PRE_INCREMENT 0 */
872 /* Macros to check register numbers against specific register classes. */
874 /* These assume that REGNO is a hard or pseudo reg number.
875 They give nonzero only if REGNO is a hard reg of the suitable class
876 or a pseudo reg currently allocated to a suitable hard reg.
877 Since they use reg_renumber, they are safe only once reg_renumber
878 has been allocated, which happens in local-alloc.c. */
881 #define REGNO_OK_FOR_GREG_P(REGNO) \
882 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
883 #define REGNO_OK_FOR_FPU_P(REGNO) \
884 (((REGNO) ^ 0x10) < 16 || (unsigned) (reg_renumber[REGNO] ^ 0x10) < 16)
886 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
887 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
889 /* Now macros that check whether X is a register and also,
890 strictly, whether it is in a specified class.
892 These macros are specific to the Gmicro, and may be used only
893 in code for printing assembler insns and in conditions for
894 define_optimization. */
896 /* 1 if X is an fpu register. */
898 #define FPU_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPU_P (REGNO (X)))
900 /* I used GREG_P in the gmicro.md file. */
903 #define GREG_P(X) (REG_P (X) && REGNO_OK_FOR_GREG_P (REGNO(X)))
905 #define GREG_P(X) (REG_P (X) && ((REGNO (X) & ~0xf) != 0x10))
908 /* Maximum number of registers that can appear in a valid memory address. */
910 /* The Gmicro allows more registers in the chained addressing mode.
911 But I do not know gcc supports such an architecture. */
913 #define MAX_REGS_PER_ADDRESS 2
915 /* Recognize any constant value that is a valid address. */
917 #define CONSTANT_ADDRESS_P(X) \
918 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
919 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
920 || GET_CODE (X) == HIGH)
922 /* Nonzero if the constant value X is a legitimate general operand.
923 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
925 #define LEGITIMATE_CONSTANT_P(X) 1
927 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
928 and check its validity for a certain class.
929 We have two alternate definitions for each of them.
930 The usual definition accepts all pseudo regs; the other rejects
931 them unless they have been allocated suitable hard regs.
932 The symbol REG_OK_STRICT causes the latter definition to be used.
934 Most source files want to accept pseudo regs in the hope that
935 they will get allocated to the class that the insn wants them to be in.
936 Source files for reload pass need to be strict.
937 After reload, it makes no difference, since pseudo regs have
938 been eliminated by then. */
940 #ifndef REG_OK_STRICT
942 /* Nonzero if X is a hard reg that can be used as an index
943 or if it is a pseudo reg. */
944 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) & ~0xf) != 0x10)
945 /* Nonzero if X is a hard reg that can be used as a base reg
946 or if it is a pseudo reg. */
947 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~0xf) != 0x10)
951 /* Nonzero if X is a hard reg that can be used as an index. */
952 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
953 /* Nonzero if X is a hard reg that can be used as a base reg. */
954 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
958 /* The gcc uses the following effective address of the Gmicro.
959 (without using PC!!).
960 {@} ( {Rbase} + {Disp} + {Rindex * [1,2,4,8]} )
962 @: memory indirection.
963 Rbase: Base Register = General Register.
964 Disp: Displacement (up to 32bits)
965 Rindex: Index Register = General Register.
966 [1,2,4,8]: Scale of Index. 1 or 2 or 4 or 8.
967 The inside of { } can be omitted.
968 This restricts the chained addressing up to 1 stage. */
972 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
973 that is a valid memory address for an instruction.
974 The MODE argument is the machine mode for the MEM expression
975 that wants to use this address.
977 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
978 except for CONSTANT_ADDRESS_P which is actually machine-independent. */
980 #define REG_CODE_BASE_P(X) \
981 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
983 #define REG_CODE_INDEX_P(X) \
984 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
986 /* GET_CODE(X) must be PLUS. This macro does not check for PLUS! */
987 #define BASE_PLUS_DISP_P(X) \
988 ( REG_CODE_BASE_P (XEXP (X, 0)) \
989 && CONSTANT_ADDRESS_P (XEXP (X, 1)) \
991 REG_CODE_BASE_P (XEXP (X, 1)) \
992 && CONSTANT_ADDRESS_P (XEXP (X, 0)) )
994 /* 1 if X is {0,Rbase} + {0,disp}. */
995 #define BASED_ADDRESS_P(X) \
996 (CONSTANT_ADDRESS_P (X) \
997 || REG_CODE_BASE_P (X) \
998 || (GET_CODE (X) == PLUS) \
999 && BASE_PLUS_DISP_P (X))
1001 /* 1 if X is 1 or 2 or 4 or 8. GET_CODE(X) must be CONST_INT. */
1002 #define SCALE_OF_INDEX_P(X) \
1008 /* #define INDEX_TERM_P(X,MODE) */
1009 #define INDEX_TERM_P(X) \
1010 ( REG_CODE_INDEX_P(X) \
1011 || (GET_CODE (X) == MULT \
1012 && ( (xfoo0 = XEXP (X, 0)), (xfoo1 = XEXP(X, 1)), \
1013 ( ( (GET_CODE (xfoo0) == CONST_INT) \
1014 && SCALE_OF_INDEX_P (xfoo0) \
1015 && REG_CODE_INDEX_P (xfoo1) ) \
1017 ( (GET_CODE (xfoo1) == CONST_INT) \
1018 && SCALE_OF_INDEX_P (xfoo1) \
1019 && REG_CODE_INDEX_P (xfoo0) ) ))))
1021 /* Assumes there are no cases such that X = (Ireg + Disp) + Disp */
1022 #define BASE_DISP_INDEX_P(X) \
1023 ( BASED_ADDRESS_P (X) \
1024 || ( (GET_CODE (X) == PLUS) \
1025 && ( ( (xboo0 = XEXP (X, 0)), (xboo1 = XEXP (X, 1)), \
1026 (REG_CODE_BASE_P (xboo0) \
1027 && (GET_CODE (xboo1) == PLUS) \
1028 && ( ( CONSTANT_ADDRESS_P (XEXP (xboo1, 0)) \
1029 && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1030 || ( CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) \
1031 && INDEX_TERM_P (XEXP (xboo1, 0))) ))) \
1033 (CONSTANT_ADDRESS_P (xboo0) \
1034 && (GET_CODE (xboo1) == PLUS) \
1035 && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1036 && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1037 || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1038 && INDEX_TERM_P (XEXP (xboo1, 0))) )) \
1040 (INDEX_TERM_P (xboo0) \
1041 && ( ( (GET_CODE (xboo1) == PLUS) \
1042 && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1043 && CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) ) \
1044 || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1045 && CONSTANT_ADDRESS_P (XEXP (xboo1, 0))) )) \
1047 (CONSTANT_ADDRESS_P (xboo1)) \
1049 (REG_CODE_BASE_P (xboo1)) )))))
1052 If you want to allow double-indirection,
1053 you have to change the <fp-relative> => <sp-relative> conversion
1056 #ifdef REG_OK_STRICT
1057 #define DOUBLE_INDIRECTION(X,ADDR) {\
1058 if (BASE_DISP_INDEX_P (XEXP (XEXP (X, 0), 0) )) goto ADDR; \
1061 #define DOUBLE_INDIRECTION(X,ADDR) { }
1066 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {\
1067 register rtx xboo0, xboo1, xfoo0, xfoo1; \
1068 if (GET_CODE (X) == MEM) { \
1070 if (GET_CODE (XEXP (X,0)) == MEM) { \
1071 DOUBLE_INDIRECTION(X,ADDR); \
1073 if (BASE_DISP_INDEX_P (XEXP (X, 0))) goto ADDR; \
1077 if (BASE_DISP_INDEX_P (X)) goto ADDR; \
1078 if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1079 && REG_P (XEXP (X, 0)) \
1080 && (REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM)) \
1086 /* Try machine-dependent ways of modifying an illegitimate address
1087 to be legitimate. If we find one, return the new, valid address.
1088 This macro is used in only one place: `memory_address' in explow.c.
1090 OLDX is the address as it was before break_out_memory_refs was called.
1091 In some cases it is useful to look at this to decide what needs to be done.
1093 MODE and WIN are passed so that this macro can use
1094 GO_IF_LEGITIMATE_ADDRESS.
1096 It is always safe for this macro to do nothing. It exists to recognize
1097 opportunities to optimize the output.
1099 For the Gmicro, nothing is done now. */
1101 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
1103 /* Go to LABEL if ADDR (a legitimate address expression)
1104 has an effect that depends on the machine mode it is used for.
1105 On the VAX, the predecrement and postincrement address depend thus
1106 (the amount of decrement or increment being the length of the operand)
1107 and all indexed address depend thus (because the index scale factor
1108 is the length of the operand).
1109 The Gmicro mimics the VAX now. Since ADDE is legitimate, it cannot
1110 include auto-inc/dec. */
1112 /* Unnecessary ??? */
1113 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1114 { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \
1118 /* Specify the machine mode that this machine uses
1119 for the index in the tablejump instruction. */
1120 /* #define CASE_VECTOR_MODE HImode */
1121 #define CASE_VECTOR_MODE SImode
1123 /* Define as C expression which evaluates to nonzero if the tablejump
1124 instruction expects the table to contain offsets from the address of the
1126 Do not define this if the table should contain absolute addresses. */
1127 #define CASE_VECTOR_PC_RELATIVE 1
1129 /* Specify the tree operation to be used to convert reals to integers. */
1130 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1132 /* This is the kind of divide that is easiest to do in the general case. */
1133 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1135 /* Define this as 1 if `char' should by default be signed; else as 0. */
1136 #define DEFAULT_SIGNED_CHAR 1
1138 /* Max number of bytes we can move from memory to memory
1139 in one reasonably fast instruction. */
1142 /* Define this if zero-extension is slow (more than one real instruction). */
1143 /* #define SLOW_ZERO_EXTEND */
1145 /* Nonzero if access to memory by bytes is slow and undesirable. */
1146 #define SLOW_BYTE_ACCESS 0
1148 /* Define if shifts truncate the shift count
1149 which implies one can omit a sign-extension or zero-extension
1150 of a shift count. */
1151 /* #define SHIFT_COUNT_TRUNCATED */
1153 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1154 is done just by pretending it is already truncated. */
1155 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1157 /* We assume that the store-condition-codes instructions store 0 for false
1158 and some other value for true. This is the value stored for true. */
1160 /* #define STORE_FLAG_VALUE -1 */
1162 /* When a prototype says `char' or `short', really pass an `int'. */
1163 #define PROMOTE_PROTOTYPES 1
1165 /* Specify the machine mode that pointers have.
1166 After generation of rtl, the compiler makes no further distinction
1167 between pointers and any other objects of this machine mode. */
1168 #define Pmode SImode
1170 /* A function address in a call instruction
1171 is a byte address (for indexing purposes)
1172 so give the MEM rtx a byte's mode. */
1173 #define FUNCTION_MODE QImode
1175 /* Compute the cost of computing a constant rtl expression RTX
1176 whose rtx-code is CODE. The body of this macro is a portion
1177 of a switch statement. If the code is computed here,
1178 return it with a return statement. Otherwise, break from the switch. */
1180 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1182 if ((unsigned) INTVAL (RTX) < 8) return 0; \
1183 if ((unsigned) (INTVAL (RTX) + 0x80) < 0x100) return 1; \
1184 if ((unsigned) (INTVAL (RTX) + 0x8000) < 0x10000) return 2; \
1189 case CONST_DOUBLE: \
1192 /* Define subroutines to call to handle multiply and divide.
1193 The `*' prevents an underscore from being prepended by the compiler. */
1194 /* Use libgcc on Gmicro */
1195 /* #define UDIVSI3_LIBCALL "*udiv" */
1196 /* #define UMODSI3_LIBCALL "*urem" */
1199 /* Tell final.c how to eliminate redundant test instructions. */
1201 /* Here we define machine-dependent flags and fields in cc_status
1202 (see `conditions.h'). */
1204 /* Set if the cc value is actually in the FPU, so a floating point
1205 conditional branch must be output. */
1206 #define CC_IN_FPU 04000
1208 /* Store in cc_status the expressions
1209 that the condition codes will describe
1210 after execution of an instruction whose pattern is EXP.
1211 Do not alter them if the instruction would not alter the cc's. */
1213 /* Since Gmicro's compare instructions depend on the branch condition,
1214 all branch should be kept.
1215 More work must be done to optimize condition code !! M.Yuhara */
1217 #define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;}
1219 /* The skeleton of the next macro is taken from "vax.h".
1220 FPU-reg manipulation is added. M.Yuhara */
1222 #define NOTICE_UPDATE_CC(EXP, INSN) { \
1223 if (GET_CODE (EXP) == SET) { \
1224 if ( !FPU_REG_P (XEXP (EXP, 0)) \
1225 && (XEXP (EXP, 0) != cc0_rtx) \
1226 && (FPU_REG_P (XEXP (EXP, 1)) \
1227 || GET_CODE (XEXP (EXP, 1)) == FIX \
1228 || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE \
1229 || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) { \
1231 } else if (GET_CODE (SET_SRC (EXP)) == CALL) { \
1233 } else if (GET_CODE (SET_DEST (EXP)) != PC) { \
1234 cc_status.flags = 0; \
1235 cc_status.value1 = SET_DEST (EXP); \
1236 cc_status.value2 = SET_SRC (EXP); \
1238 } else if (GET_CODE (EXP) == PARALLEL \
1239 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET \
1240 && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) {\
1241 cc_status.flags = 0; \
1242 cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \
1243 cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \
1244 /* PARALLELs whose first element sets the PC are aob, sob VAX insns. \
1245 They do change the cc's. So drop through and forget the cc's. * / \
1246 } else CC_STATUS_INIT; \
1247 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
1248 && cc_status.value2 \
1249 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
1250 cc_status.value2 = 0; \
1251 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM \
1252 && cc_status.value2 \
1253 && GET_CODE (cc_status.value2) == MEM) \
1254 cc_status.value2 = 0; \
1255 if ( (cc_status.value1 && FPU_REG_P (cc_status.value1)) \
1256 || (cc_status.value2 && FPU_REG_P (cc_status.value2))) \
1257 cc_status.flags = CC_IN_FPU; \
1261 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1262 { if (cc_prev_status.flags & CC_IN_FPU) \
1264 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1268 /* Control the assembler format that we output. */
1270 /* Output before read-only data. */
1272 #define TEXT_SECTION_ASM_OP ".section text,code,align=4"
1274 /* Output before writable data. */
1276 #define DATA_SECTION_ASM_OP ".section data,data,align=4"
1278 /* Output before uninitialized data. */
1280 #define BSS_SECTION_ASM_OP ".section bss,data,align=4"
1282 /* Output at beginning of assembler file.
1283 It is not appropriate for this to print a list of the options used,
1284 since that's not the convention that we use. */
1286 #define ASM_FILE_START(FILE)
1288 /* Output at the end of assembler file. */
1290 #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n");
1293 /* Don't try to define `gcc_compiled.' since the assembler do not
1294 accept symbols with periods and GDB doesn't run on this machine anyway. */
1295 #define ASM_IDENTIFY_GCC(FILE)
1298 /* Output to assembler file text saying following lines
1299 may contain character constants, extra white space, comments, etc. */
1301 #define ASM_APP_ON ""
1302 /* #define ASM_APP_ON "#APP\n" */
1304 /* Output to assembler file text saying following lines
1305 no longer contain unusual constructs. */
1307 #define ASM_APP_OFF ""
1308 /* #define ASM_APP_OFF ";#NO_APP\n" */
1310 /* How to refer to registers in assembler output.
1311 This sequence is indexed by compiler's hard-register-number (see above). */
1313 #define REGISTER_NAMES \
1314 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1315 "r8", "r9", "r10", "r11", "r12", "r13", "fp", "sp", \
1316 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1317 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15"}
1319 /* How to renumber registers for dbx and gdb. */
1321 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1323 /* Define this if gcc should produce debugging output for dbx in response
1324 to the -g flag. This does not work for the Gmicro now */
1326 #define DBX_DEBUGGING_INFO
1328 /* This is how to output the definition of a user-level label named NAME,
1329 such as the label on a static function or variable NAME. */
1331 #define ASM_OUTPUT_LABEL(FILE,NAME) { \
1332 assemble_name (FILE, NAME); \
1333 fputs (":\n", FILE); \
1336 /* This is how to output a command to make the user-level label named NAME
1337 defined for reference from other files. */
1339 #define ASM_GLOBALIZE_LABEL(FILE,NAME) {\
1340 fputs ("\t.global ", FILE); \
1341 assemble_name (FILE, NAME); \
1342 fputs ("\n", FILE); \
1345 /* This is how to output a command to make the external label named NAME
1346 which are not defined in the file to be referable */
1347 /* ".import" does not work ??? */
1349 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) { \
1350 fputs ("\t.global ", FILE); \
1351 assemble_name (FILE, NAME); \
1352 fputs ("\n", FILE); \
1356 /* The prefix to add to user-visible assembler symbols. */
1358 #define USER_LABEL_PREFIX "_"
1360 /* This is how to output an internal numbered label where
1361 PREFIX is the class of label and NUM is the number within the class. */
1363 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1364 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1366 /* This is how to store into the string LABEL
1367 the symbol_ref name of an internal numbered label where
1368 PREFIX is the class of label and NUM is the number within the class.
1369 This is suitable for output with `assemble_name'. */
1371 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1372 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1374 /* This is how to output an assembler line defining a `double' constant. */
1376 /* do {...} while(0) is necessary, because these macros are used as
1377 if (xxx) MACRO; else ....
1382 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1383 do { union { double d; long l[2];} tem; \
1385 fprintf (FILE, "\t.fdata.d h'%x%08x.d\n", tem.l[0], tem.l[1]); \
1389 /* This is how to output an assembler line defining a `float' constant. */
1391 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1392 do { union { float f; long l;} tem; \
1394 fprintf (FILE, "\t.fdata.s h'%x.s\n", tem.l); \
1397 /* This is how to output an assembler line defining an `int' constant. */
1399 #define ASM_OUTPUT_INT(FILE,VALUE) \
1400 ( fprintf (FILE, "\t.data.w "), \
1401 output_addr_const (FILE, (VALUE)), \
1402 fprintf (FILE, "\n"))
1404 /* Likewise for `char' and `short' constants. */
1406 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1407 ( fprintf (FILE, "\t.data.h "), \
1408 output_addr_const (FILE, (VALUE)), \
1409 fprintf (FILE, "\n"))
1411 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1412 ( fprintf (FILE, "\t.data.b "), \
1413 output_addr_const (FILE, (VALUE)), \
1414 fprintf (FILE, "\n"))
1416 /* This is how to output an assembler line for a numeric constant byte. */
1418 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1419 fprintf (FILE, "\t.data.b h'%x\n", (VALUE))
1421 #define ASM_OUTPUT_ASCII(FILE,P,SIZE) \
1422 output_ascii ((FILE), (P), (SIZE))
1424 /* This is how to output an insn to push a register on the stack.
1425 It need not be very fast code. */
1427 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1428 fprintf (FILE, "\tmov %s,@-sp\n", reg_names[REGNO])
1430 /* This is how to output an insn to pop a register from the stack.
1431 It need not be very fast code. */
1433 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1434 fprintf (FILE, "\tmov @sp+,%s\n", reg_names[REGNO])
1436 /* This is how to output an element of a case-vector that is absolute.
1437 (The Gmicro does not use such vectors,
1438 but we must define this macro anyway.) */
1440 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1441 fprintf (FILE, "\t.data.w L%d\n", VALUE)
1444 /* This is how to output an element of a case-vector that is relative. */
1446 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1447 fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL)
1450 /* This is how to output an assembler line
1451 that says to advance the location counter
1452 to a multiple of 2**LOG bytes. */
1454 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1455 fprintf (FILE, "\t.align %d\n", (1 << (LOG)));
1457 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1458 fprintf (FILE, "\t.res.b %d\n", (SIZE))
1460 /* This says how to output an assembler line
1461 to define a global common symbol. */
1463 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1465 assemble_name ((FILE), (NAME)), \
1466 fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)),\
1467 fprintf ((FILE), "\t.export "), \
1468 assemble_name ((FILE), (NAME)), \
1469 fprintf ((FILE), "\n") )
1471 /* This says how to output an assembler line
1472 to define a local common symbol. */
1474 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1476 assemble_name ((FILE), (NAME)), \
1477 fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)))
1479 /* Store in OUTPUT a string (made with alloca) containing
1480 an assembler-name for a local static variable named NAME.
1481 LABELNO is an integer which is different for each call. */
1483 /* $__ is unique ????? M.Yuhara */
1484 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1485 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \
1486 sprintf ((OUTPUT), "$__%s%d", (NAME), (LABELNO)))
1488 /* Define the parentheses used to group arithmetic operations
1489 in assembler code. */
1491 #define ASM_OPEN_PAREN "("
1492 #define ASM_CLOSE_PAREN ")"
1494 /* Define results of standard character escape sequences. */
1495 #define TARGET_BELL 007
1496 #define TARGET_BS 010
1497 #define TARGET_TAB 011
1498 #define TARGET_NEWLINE 012
1499 #define TARGET_VT 013
1500 #define TARGET_FF 014
1501 #define TARGET_CR 015
1503 /* Output a float value (represented as a C double) as an immediate operand.
1504 This macro is a Gmicro/68k-specific macro. */
1506 #define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE) \
1507 do { union { float f; long l;} tem; \
1509 fprintf (FILE, "#h'%x.s", tem.l); \
1513 /* Output a double value (represented as a C double) as an immediate operand.
1514 This macro is a 68k-specific macro. */
1515 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1516 do { union { double d; long l[2];} tem; \
1518 fprintf (FILE, "#h'%x%08x.d", tem.l[0], tem.l[1]); \
1521 /* Print operand X (an rtx) in assembler syntax to file FILE.
1522 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1523 For `%' followed by punctuation, CODE is the punctuation and X is null.
1525 On the Gmicro, we use several CODE characters:
1526 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1527 'b' for branch target label.
1528 '-' for an operand pushing on the stack.
1529 '+' for an operand pushing on the stack.
1530 '#' for an immediate operand prefix
1533 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1534 ( (CODE) == '#' || (CODE) == '-' \
1535 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
1538 #define PRINT_OPERAND(FILE, X, CODE) \
1540 static char *reg_name[] = REGISTER_NAMES; \
1541 /* fprintf (stderr, "PRINT_OPERAND CODE=%c(0x%x), ", CODE, CODE);\
1542 myprcode(GET_CODE(X)); */ \
1543 if (CODE == '#') fprintf (FILE, "#"); \
1544 else if (CODE == '-') fprintf (FILE, "@-sp"); \
1545 else if (CODE == '+') fprintf (FILE, "@sp+"); \
1546 else if (CODE == 's') fprintf (stderr, "err: PRINT_OPERAND <s>\n"); \
1547 else if (CODE == '!') fprintf (stderr, "err: PRINT_OPERAND <!>\n"); \
1548 else if (CODE == '.') fprintf (stderr, "err: PRINT_OPERAND <.>\n"); \
1549 else if (CODE == 'b') { \
1550 if (GET_CODE (X) == MEM) \
1551 output_addr_const (FILE, XEXP (X, 0)); /* for bsr */ \
1553 output_addr_const (FILE, X); /* for bcc */ \
1555 else if (CODE == 'p') \
1556 print_operand_address (FILE, X); \
1557 else if (GET_CODE (X) == REG) \
1558 fprintf (FILE, "%s", reg_name[REGNO (X)]); \
1559 else if (GET_CODE (X) == MEM) \
1560 output_address (XEXP (X, 0)); \
1561 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1562 { union { double d; int i[2]; } u; \
1563 union { float f; int i; } u1; \
1564 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1567 ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); \
1569 fprintf (FILE, "#h'%x", u1.i); } \
1570 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \
1571 { union { double d; int i[2]; } u; \
1572 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1573 ASM_OUTPUT_DOUBLE_OPERAND (FILE, u.d); } \
1574 else { putc ('#', FILE); \
1575 output_addr_const (FILE, X); }}
1577 /* Note that this contains a kludge that knows that the only reason
1578 we have an address (plus (label_ref...) (reg...))
1579 is in the insn before a tablejump, and we know that m68k.md
1580 generates a label LInnn: on such an insn. */
1581 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1582 { print_operand_address (FILE, ADDR); }