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1 /* Definitions of target machine for GNU compiler. Gmicro (TRON) version.
2 Copyright (C) 1987, 88, 89, 95-98, 1999 Free Software Foundation, Inc.
3 Contributed by Masanobu Yuhara, Fujitsu Laboratories LTD.
4 (yuhara@flab.fujitsu.co.jp)
5
6 This file is part of GNU CC.
7
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
26
27
28 /* Names to predefine in the preprocessor for this target machine. */
29
30 #define CPP_PREDEFINES "-Dgmicro -Acpu(tron) -Amachine(tron)"
31
32 /* #define CPP_SPEC ** currently not defined **/
33
34 /* #define CC1_SPEC ** currently not defined **/
35
36
37 /* Print subsidiary information on the compiler version in use. */
38 /*
39 #define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
40 */
41
42 /* Run-time compilation parameters selecting different hardware subsets. */
43
44 extern int target_flags;
45
46 /* Macros used in the machine description to test the flags. */
47
48 /* Compile for a Gmicro/300. */
49 #define TARGET_G300 (target_flags & 1)
50 /* Compile for a Gmicro/200. */
51 #define TARGET_G200 (target_flags & 2)
52 /* Compile for a Gmicro/100. */
53 #define TARGET_G100 (target_flags & 4)
54
55 /* Compile FPU insns for floating point (not library calls). */
56 #define TARGET_FPU (target_flags & 8)
57
58 /* Pop up arguments by called function. */
59 #define TARGET_RTD (target_flags & 0x10)
60
61 /* Compile passing first args in regs 0 and 1.
62 This exists only to test compiler features that will be needed for
63 RISC chips. It is not usable and is not intended to be usable on
64 this cpu ;-< */
65 #define TARGET_REGPARM (target_flags & 0x20)
66
67 #define TARGET_BITFIELD (target_flags & 0x40)
68
69 #define TARGET_NEWRETURN (target_flags & 0x80)
70
71 /* Do not expand __builtin_smov (strcpy) to multiple movs.
72 Use the smov instruction. */
73 #define TARGET_FORCE_SMOV (target_flags & 0x100)
74
75 /* default options are -m300, -mFPU,
76 with bitfield instructions added because it won't always work otherwise.
77 If there are versions of the gmicro that don't support bitfield instructions
78 then it will take some thinking to figure out how to make them work. */
79 #define TARGET_DEFAULT 0x49
80
81 /* Macro to define tables used to set the flags.
82 This is a list in braces of pairs in braces,
83 each pair being { "NAME", VALUE }
84 where VALUE is the bits to set or minus the bits to clear.
85 An empty string NAME is used to identify the default VALUE. */
86
87 #define TARGET_SWITCHES \
88 { { "g300", 1}, \
89 { "g200", 2}, \
90 { "g100", 4}, \
91 { "fpu", 8}, \
92 { "soft-float", -8}, \
93 { "rtd", 0x10}, \
94 { "no-rtd", -0x10}, \
95 { "regparm", 0x20}, \
96 { "no-regparm", -0x20}, \
97 #if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
98 STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions. */
99 { "bitfield", 0x40}, \
100 { "no-bitfield", -0x40}, \
101 #endif
102 { "newreturn", 0x80}, \
103 { "no-newreturn", -0x80}, \
104 { "force-smov", 0x100}, \
105 { "no-force-smov", -0x100}, \
106 { "", TARGET_DEFAULT}}
107
108
109 /* Blow away G100 flag silently off TARGET_fpu (since we can't clear
110 any bits in TARGET_SWITCHES above) */
111 #define OVERRIDE_OPTIONS \
112 { \
113 if (TARGET_G100) target_flags &= ~8; \
114 }
115 \f
116 /* target machine storage layout */
117
118 /* Define this if most significant bit is lowest numbered
119 in instructions that operate on numbered bit-fields.
120 This is true for Gmicro insns.
121 We make it true always by avoiding using the single-bit insns
122 except in special cases with constant bit numbers. */
123 #define BITS_BIG_ENDIAN 1
124
125 /* Define this if most significant byte of a word is the lowest numbered. */
126 /* That is true on the Gmicro. */
127 #define BYTES_BIG_ENDIAN 1
128
129 /* Define this if most significant word of a multiword number is the lowest
130 numbered. */
131 /* For Gmicro we can decide arbitrarily
132 since there are no machine instructions for them. ????? */
133 #define WORDS_BIG_ENDIAN 0
134
135 /* number of bits in an addressable storage unit */
136 #define BITS_PER_UNIT 8
137
138 /* Width in bits of a "word", which is the contents of a machine register. */
139 #define BITS_PER_WORD 32
140
141 /* Width of a word, in units (bytes). */
142 #define UNITS_PER_WORD 4
143
144 /* Width in bits of a pointer.
145 See also the macro `Pmode' defined below. */
146 #define POINTER_SIZE 32
147
148 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
149 #define PARM_BOUNDARY 32
150
151 /* Boundary (in *bits*) on which stack pointer should be aligned. */
152 #define STACK_BOUNDARY 32
153
154 /* Allocation boundary (in *bits*) for the code of a function. */
155 /* Instructions of the Gmicro should be on half-word boundary */
156 /* But word boundary gets better performance */
157 #define FUNCTION_BOUNDARY 32
158
159 /* Alignment of field after `int : 0' in a structure. */
160 #define EMPTY_FIELD_BOUNDARY 32
161
162 /* No data type wants to be aligned rounder than this. */
163 /* This is not necessarily 32 on the Gmicro */
164 #define BIGGEST_ALIGNMENT 32
165
166 /* Set this non-zero if move instructions will actually fail to work
167 when given unaligned data.
168 Unaligned data is allowed on Gmicro, though the access is slow. */
169
170 #define STRICT_ALIGNMENT 1
171 #define SLOW_UNALIGNED_ACCESS 1
172
173 /* Make strings word-aligned so strcpy from constants will be faster. */
174 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
175 (TREE_CODE (EXP) == STRING_CST \
176 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
177
178 /* Make arrays of chars word-aligned for the same reasons. */
179 #define DATA_ALIGNMENT(TYPE, ALIGN) \
180 (TREE_CODE (TYPE) == ARRAY_TYPE \
181 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
182 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
183
184 /* Define number of bits in most basic integer type.
185 (If undefined, default is BITS_PER_WORD). */
186 #define INT_TYPE_SIZE 32
187
188 /* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */
189
190 /* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */
191
192 \f
193 /* Standard register usage. */
194
195 /* Number of actual hardware registers.
196 The hardware registers are assigned numbers for the compiler
197 from 0 to just below FIRST_PSEUDO_REGISTER.
198 All registers that the compiler knows about must be given numbers,
199 even those that are not normally considered general registers.
200 For the Gmicro, we give the general registers numbers 0-15,
201 and the FPU floating point registers numbers 16-31. */
202 #define FIRST_PSEUDO_REGISTER 32
203
204 /* 1 for registers that have pervasive standard uses
205 and are not available for the register allocator.
206 On the Gmicro, the stack pointer and the frame pointer are
207 such registers. */
208 /* frame pointer is not indicated as fixed, because fp may be used freely
209 when a frame is not built. */
210 #define FIXED_REGISTERS \
211 {0, 0, 0, 0, 0, 0, 0, 0, \
212 0, 0, 0, 0, 0, 0, 0, 1, \
213 /* FPU registers. */ \
214 0, 0, 0, 0, 0, 0, 0, 0, \
215 0, 0, 0, 0, 0, 0, 0, 0, }
216
217 /* 1 for registers not available across function calls.
218 These must include the FIXED_REGISTERS and also any
219 registers that can be used without being saved.
220 The latter must include the registers where values are returned
221 and the register where structure-value addresses are passed.
222 Aside from that, you can include as many other registers as you like. */
223 #define CALL_USED_REGISTERS \
224 {1, 1, 1, 1, 0, 0, 0, 0, \
225 0, 0, 0, 0, 0, 0, 0, 1, \
226 /* FPU registers. */ \
227 1, 1, 1, 1, 0, 0, 0, 0, \
228 0, 0, 0, 0, 0, 0, 0, 0, }
229
230
231 /* Make sure everything's fine if we *don't* have a given processor.
232 This assumes that putting a register in fixed_regs will keep the
233 compilers mitt's completely off it. We don't bother to zero it out
234 of register classes. If TARGET_FPU is not set,
235 the compiler won't touch since no instructions that use these
236 registers will be valid. */
237 /* This Macro is not defined now.
238 #define CONDITIONAL_REGISTER_USAGE */
239
240 /* The Gmicro has no overlapping register */
241 /* #define OVERLAPPING_REGNO_P(REGNO) */
242
243 /* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO) */
244
245 /* Return number of consecutive hard regs needed starting at reg REGNO
246 to hold something of mode MODE.
247 This is ordinarily the length in words of a value of mode MODE
248 but can be less for certain modes in special long registers.
249
250 On the Gmicro, ordinary registers hold 32 bits worth;
251 for the Gmicro/FPU registers, a single register is always enough for
252 anything that can be stored in them at all. */
253 #define HARD_REGNO_NREGS(REGNO, MODE) \
254 ((REGNO) >= 16 ? 1 \
255 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
256
257 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
258 On the Gmicro, the cpu registers can hold any mode but the FPU registers
259 can hold only SFmode or DFmode. And the FPU registers can't hold anything
260 if FPU use is disabled. */
261 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
262 ((REGNO) < 16 \
263 || ((REGNO) < 32 \
264 ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT || \
265 GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
266 : 0 ))
267
268 /* Value is 1 if it is a good idea to tie two pseudo registers
269 when one has mode MODE1 and one has mode MODE2.
270 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
271 for any hard reg, then this must be 0 for correct output. */
272 #define MODES_TIEABLE_P(MODE1, MODE2) \
273 (! TARGET_FPU \
274 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
275 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
276 == ((MODE2) == SFmode || (MODE2) == DFmode)))
277
278 /* Specify the registers used for certain standard purposes.
279 The values of these macros are register numbers. */
280
281 /* Gmicro pc isn't overloaded on a register. */
282 /* #define PC_REGNUM */
283
284 /* Register to use for pushing function arguments. */
285 #define STACK_POINTER_REGNUM 15
286
287 /* Base register for access to local variables of the function. */
288 #define FRAME_POINTER_REGNUM 14
289
290 /* Value should be nonzero if functions must have frame pointers.
291 Zero means the frame pointer need not be set up (and parms
292 may be accessed via the stack pointer) in functions that seem suitable.
293 This is computed in `reload', in reload1.c. */
294 #define FRAME_POINTER_REQUIRED 0
295
296 /* Base register for access to arguments of the function. */
297 /* The Gmicro does not have hardware ap. Fp is treated as ap */
298 #define ARG_POINTER_REGNUM 14
299
300 /* Register in which static-chain is passed to a function. */
301 #define STATIC_CHAIN_REGNUM 0
302
303 /* Register in which address to store a structure value
304 is passed to a function. */
305 #define STRUCT_VALUE_REGNUM 1
306 \f
307 /* Define the classes of registers for register constraints in the
308 machine description. Also define ranges of constants.
309
310 One of the classes must always be named ALL_REGS and include all hard regs.
311 If there is more than one class, another class must be named NO_REGS
312 and contain no registers.
313
314 The name GENERAL_REGS must be the name of a class (or an alias for
315 another name such as ALL_REGS). This is the class of registers
316 that is allowed by "g" or "r" in a register constraint.
317 Also, registers outside this class are allocated only when
318 instructions express preferences for them.
319
320 The classes must be numbered in nondecreasing order; that is,
321 a larger-numbered class must never be contained completely
322 in a smaller-numbered class.
323
324 For any two classes, it is very desirable that there be another
325 class that represents their union. */
326
327 /* The Gmicro has two kinds of registers, so four classes would be
328 a complete set. */
329
330 enum reg_class { NO_REGS, FPU_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
331
332 #define N_REG_CLASSES (int) LIM_REG_CLASSES
333
334 /* Give names of register classes as strings for dump file. */
335
336 #define REG_CLASS_NAMES \
337 { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" }
338
339 /* Define which registers fit in which classes.
340 This is an initializer for a vector of HARD_REG_SET
341 of length N_REG_CLASSES. */
342
343 #define REG_CLASS_CONTENTS \
344 { \
345 0, /* NO_REGS */ \
346 0xffff0000, /* FPU_REGS */ \
347 0x0000ffff, /* GENERAL_REGS */ \
348 0xffffffff /* ALL_REGS */ \
349 }
350
351 /* The same information, inverted:
352 Return the class number of the smallest class containing
353 reg number REGNO. This could be a conditional expression
354 or could index an array. */
355
356 extern enum reg_class regno_reg_class[];
357 #define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS )
358
359 /* The class value for index registers, and the one for base regs. */
360
361 #define INDEX_REG_CLASS GENERAL_REGS
362 #define BASE_REG_CLASS GENERAL_REGS
363
364 /* Get reg_class from a letter such as appears in the machine description.
365 We do a trick here to modify the effective constraints on the
366 machine description; we zorch the constraint letters that aren't
367 appropriate for a specific target. This allows us to guarantee
368 that a specific kind of register will not be used for a given target
369 without fiddling with the register classes above. */
370
371 #define REG_CLASS_FROM_LETTER(C) \
372 ((C) == 'r' ? GENERAL_REGS : \
373 ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) : \
374 NO_REGS))
375
376 /* The letters I, J, K, L and M in a register constraint string
377 can be used to stand for particular ranges of immediate operands.
378 This macro defines what the ranges are.
379 C is the letter, and VALUE is a constant value.
380 Return 1 if VALUE is in the range specified by C.
381
382 For the Gmicro, all immediate value optimizations are done
383 by assembler, so no machine dependent definition is necessary ??? */
384
385 /* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */
386 #define CONST_OK_FOR_LETTER_P(VALUE, C) 0
387
388 /*
389 * The letters G defines all of the floating constants tha are *NOT*
390 * Gmicro-FPU constant.
391 */
392
393 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
394 ((C) == 'F' || \
395 (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE)))
396
397 /* Given an rtx X being reloaded into a reg required to be
398 in class CLASS, return the class of reg to actually use.
399 In general this is just CLASS; but on some machines
400 in some cases it is preferable to use a more restrictive class. */
401 /* On the Gmicro series, there is no restriction on GENERAL_REGS,
402 so CLASS is returned. I do not know whether I should treat FPU_REGS
403 specially or not (at least, m68k does not). */
404
405 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
406
407 /* Return the maximum number of consecutive registers
408 needed to represent mode MODE in a register of class CLASS. */
409 /* On the Gmicro, this is the size of MODE in words,
410 except in the FPU regs, where a single reg is always enough. */
411 #define CLASS_MAX_NREGS(CLASS, MODE) \
412 ((CLASS) == FPU_REGS ? \
413 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
414 \f
415 /* Stack layout; function entry, exit and calling. */
416
417 /* Define this if pushing a word on the stack
418 makes the stack pointer a smaller address. */
419 #define STACK_GROWS_DOWNWARD
420
421 /* Define this if the nominal address of the stack frame
422 is at the high-address end of the local variables;
423 that is, each additional local variable allocated
424 goes at a more negative offset in the frame. */
425 #define FRAME_GROWS_DOWNWARD
426
427 /* Offset within stack frame to start allocating local variables at.
428 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
429 first local allocated. Otherwise, it is the offset to the BEGINNING
430 of the first local allocated. */
431 /* On the Gmicro, FP points to the old FP and the first local variables are
432 at (FP - 4). */
433 #define STARTING_FRAME_OFFSET 0
434
435 /* If we generate an insn to push BYTES bytes,
436 this says how many the stack pointer really advances by. */
437 /* On the Gmicro, sp is decremented by the exact size of the operand */
438 #define PUSH_ROUNDING(BYTES) (BYTES)
439
440 /* Offset of first parameter from the argument pointer register value. */
441 /* On the Gmicro, the first argument is found at (ap + 8) where ap is fp. */
442 #define FIRST_PARM_OFFSET(FNDECL) 8
443
444 /* Value is the number of byte of arguments automatically
445 popped when returning from a subroutine call.
446 FUNDECL is the declaration node of the function (as a tree),
447 FUNTYPE is the data type of the function (as a tree),
448 or for a library call it is an identifier node for the subroutine name.
449 SIZE is the number of bytes of arguments passed on the stack.
450
451 On the Gmicro, the EXITD insn may be used to pop them if the number
452 of args is fixed, but if the number is variable then the caller must pop
453 them all. The adjsp operand of the EXITD insn can't be used for library
454 calls now because the library is compiled with the standard compiler.
455 Use of adjsp operand is a selectable option, since it is incompatible with
456 standard Unix calling sequences. If the option is not selected,
457 the caller must always pop the args.
458 On the m68k this is an RTD option, so I use the same name
459 for the Gmicro. The option name may be changed in the future. */
460
461 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
462 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
463 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
464 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
465 == void_type_node))) \
466 ? (SIZE) : 0)
467
468 /* Define how to find the value returned by a function.
469 VALTYPE is the data type of the value (as a tree).
470 If the precise function being called is known, FUNC is its FUNCTION_DECL;
471 otherwise, FUNC is 0. */
472
473 /* On the Gmicro the floating return value is in fr0 not r0. */
474
475 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
476
477 /* Define how to find the value returned by a library function
478 assuming the value has mode MODE. */
479
480 #define LIBCALL_VALUE(MODE) \
481 (gen_rtx_REG ((MODE), \
482 ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) \
483 ? 16 : 0)))
484
485
486 /* 1 if N is a possible register number for a function value.
487 On the Gmicro, r0 and fp0 are the possible registers. */
488
489 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
490
491 /* Define this if PCC uses the nonreentrant convention for returning
492 structure and union values. */
493
494 #define PCC_STATIC_STRUCT_RETURN
495
496 /* 1 if N is a possible register number for function argument passing.
497 On the Gmicro, no registers are used in this way. */
498 /* Really? For the performance improvement, registers should be used !! */
499
500 #define FUNCTION_ARG_REGNO_P(N) 0
501 \f
502 /* Define a data type for recording info about an argument list
503 during the scan of that argument list. This data type should
504 hold all necessary information about the function itself
505 and about the args processed so far, enough to enable macros
506 such as FUNCTION_ARG to determine where the next arg should go.
507
508 On the Gmicro, this is a single integer, which is a number of bytes
509 of arguments scanned so far. */
510
511 #define CUMULATIVE_ARGS int
512
513 /* Initialize a variable CUM of type CUMULATIVE_ARGS
514 for a call to a function whose data type is FNTYPE.
515 For a library call, FNTYPE is 0.
516
517 On the Gmicro, the offset starts at 0. */
518
519 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
520 ((CUM) = 0)
521
522 /* Update the data in CUM to advance over an argument
523 of mode MODE and data type TYPE.
524 (TYPE is null for libcalls where that information may not be available.) */
525
526 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
527 ((CUM) += ((MODE) != BLKmode \
528 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
529 : (int_size_in_bytes (TYPE) + 3) & ~3))
530
531 /* Define where to put the arguments to a function.
532 Value is zero to push the argument on the stack,
533 or a hard register in which to store the argument.
534
535 MODE is the argument's machine mode.
536 TYPE is the data type of the argument (as a tree).
537 This is null for libcalls where that information may
538 not be available.
539 CUM is a variable of type CUMULATIVE_ARGS which gives info about
540 the preceding args and about the function being called.
541 NAMED is nonzero if this argument is a named parameter
542 (otherwise it is an extra parameter matching an ellipsis). */
543
544 /* On the Gmicro all args are pushed, except if -mregparm is specified
545 then the first two words of arguments are passed in d0, d1.
546 *NOTE* -mregparm does not work.
547 It exists only to test register calling conventions. */
548
549 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
550 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
551
552 /* For an arg passed partly in registers and partly in memory,
553 this is the number of registers used.
554 For args passed entirely in registers or entirely in memory, zero. */
555
556 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
557 ((TARGET_REGPARM && (CUM) < 8 \
558 && 8 < ((CUM) + ((MODE) == BLKmode \
559 ? int_size_in_bytes (TYPE) \
560 : GET_MODE_SIZE (MODE)))) \
561 ? 2 - (CUM) / 4 : 0)
562
563 /* The following macro is defined to output register list.
564 The LSB of Mask is the lowest number register.
565 Regoff is MY_GREG_OFF or MY_FREG_OFF.
566 Do NOT use <i> in File, Mask, Regoff !!
567 Should be changed from macros to functions. M.Yuhara */
568
569 #define MY_GREG_OFF 0
570 #define MY_FREG_OFF 16
571
572 #define MY_PRINT_MASK(File, Mask, Regoff) \
573 { \
574 int i, first = -1; \
575 if ((Mask) == 0) { \
576 fprintf(File, "#0"); \
577 } else { \
578 fprintf(File, "("); \
579 for (i = 0; i < 16; i++) { \
580 if ( (Mask) & (1 << i) ) { \
581 if (first < 0) { \
582 if (first == -2) { \
583 fprintf(File, ","); \
584 } \
585 first = i; \
586 fprintf(File, "%s", reg_names[Regoff + i]); \
587 } \
588 } else if (first >= 0) { \
589 if (i > first + 1) { \
590 fprintf(File, "-%s", reg_names[Regoff + i - 1]); \
591 } \
592 first = -2; \
593 } \
594 } \
595 if ( (first >= 0) && (first != 15) ) \
596 fprintf(File, "-%s", reg_names[Regoff + 15]);\
597 fprintf(File, ")"); \
598 } \
599 }
600
601
602 #define MY_PRINT_ONEREG_L(FILE,MASK) \
603 { register int i; \
604 for (i = 0; i < 16; i++) \
605 if ( (1 << i) & (MASK)) { \
606 fprintf(FILE, "%s", reg_names[i]); \
607 (MASK) &= ~(1 << i); \
608 break; \
609 } \
610 }
611
612
613 #define MY_PRINT_ONEREG_H(FILE,MASK) \
614 { register int i; \
615 for (i = 15; i >= 0; i--) \
616 if ( (1 << i) & (MASK)) { \
617 fprintf(FILE, "%s", reg_names[i]); \
618 (MASK) &= ~(1 << i); \
619 break; \
620 } \
621 }
622
623 /* This macro generates the assembly code for function entry.
624 FILE is a stdio stream to output the code to.
625 SIZE is an int: how many units of temporary storage to allocate.
626 Refer to the array `regs_ever_live' to determine which registers
627 to save; `regs_ever_live[I]' is nonzero if register number I
628 is ever used in the function. This macro is responsible for
629 knowing which registers should not be saved even if used. */
630
631 /* The next macro needs much optimization !!
632 M.Yuhara */
633
634 #define FUNCTION_PROLOGUE(FILE, SIZE) \
635 { register int regno; \
636 register int mask = 0; \
637 register int nregs = 0; \
638 static char *reg_names[] = REGISTER_NAMES; \
639 extern char call_used_regs[]; \
640 int fsize = ((SIZE) + 3) & -4; \
641 for (regno = 0; regno < 16; regno++) \
642 if (regs_ever_live[regno] && !call_used_regs[regno]) { \
643 mask |= (1 << regno); \
644 nregs++; \
645 } \
646 if (frame_pointer_needed) { \
647 mask &= ~(1 << FRAME_POINTER_REGNUM); \
648 if (nregs > 4) { \
649 fprintf(FILE, "\tenter.w #%d,", fsize); \
650 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
651 fprintf(FILE,"\n"); \
652 } else { \
653 fprintf(FILE, "\tmov.w fp,@-sp\n"); \
654 fprintf(FILE, "\tmov.w sp,fp\n"); \
655 if (fsize > 0) \
656 myoutput_sp_adjust(FILE, "sub", fsize); \
657 while (nregs--) { \
658 fprintf(FILE, "\tmov.w "); \
659 MY_PRINT_ONEREG_H(FILE, mask); \
660 fprintf(FILE, ",@-sp\n"); \
661 } \
662 } \
663 } else { \
664 if (fsize > 0) \
665 myoutput_sp_adjust(FILE, "sub", fsize); \
666 if (mask != 0) { \
667 if (nregs > 4) { \
668 fprintf(FILE, "\tstm.w "); \
669 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
670 fprintf(FILE, ",@-sp\n"); \
671 } else { \
672 while (nregs--) { \
673 fprintf(FILE, "\tmov.w "); \
674 MY_PRINT_ONEREG_H(FILE, mask); \
675 fprintf(FILE, ",@-sp\n"); \
676 } \
677 } \
678 } \
679 } \
680 mask = 0; \
681 for (regno = 16; regno < 32; regno++) \
682 if (regs_ever_live[regno] && !call_used_regs[regno]) \
683 mask |= 1 << (regno - 16); \
684 if (mask != 0) { \
685 fprintf(FILE, "\tfstm.w "); \
686 MY_PRINT_MASK(FILE, mask, MY_FREG_OFF); \
687 fprintf(FILE, ",@-sp\n", mask); \
688 } \
689 }
690
691
692 /* Output assembler code to FILE to increment profiler label # LABELNO
693 for profiling a function entry. */
694 /* ??? M.Yuhara */
695
696 #define FUNCTION_PROFILER(FILE, LABELNO) \
697 fprintf (FILE, "\tmova @LP%d,r0\n\tjsr mcount\n", (LABELNO))
698
699 /* Output assembler code to FILE to initialize this source file's
700 basic block profiling info, if that has not already been done. */
701
702 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
703 fprintf (FILE, "\tcmp #0,@LPBX0\n\tbne LPI%d\n\tpusha @LPBX0\n\tjsr ___bb_init_func\n\tadd #4,sp\nLPI%d:\n", \
704 LABELNO, LABELNO);
705
706 /* Output assembler code to FILE to increment the entry-count for
707 the BLOCKNO'th basic block in this source file. */
708
709 #define BLOCK_PROFILER(FILE, BLOCKNO) \
710 fprintf (FILE, "\tadd #1,@(LPBX2+%d)\n", 4 * BLOCKNO)
711
712 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
713 the stack pointer does not matter. The value is tested only in
714 functions that have frame pointers.
715 No definition is equivalent to always zero. */
716
717 #define EXIT_IGNORE_STACK 1
718
719 /* This macro generates the assembly code for function exit,
720 on machines that need it. If FUNCTION_EPILOGUE is not defined
721 then individual return instructions are generated for each
722 return statement. Args are same as for FUNCTION_PROLOGUE.
723
724 The function epilogue should not depend on the current stack pointer (when
725 frame_pinter_needed) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
726 It should use the frame pointer only. This is mandatory because
727 of alloca; we also take advantage of it to omit stack adjustments
728 before returning. */
729
730 /* The Gmicro FPU seems to be unable to fldm/fstm double or single
731 floating. It only allows extended !! */
732 /* Optimization is not enough, especially FREGs load !! M.Yuhara */
733
734 #define FUNCTION_EPILOGUE(FILE, SIZE) \
735 { register int regno; \
736 register int mask, fmask; \
737 register int nregs, nfregs; \
738 int offset, foffset; \
739 extern char call_used_regs[]; \
740 static char *reg_names[] = REGISTER_NAMES; \
741 int fsize = ((SIZE) + 3) & -4; \
742 FUNCTION_EXTRA_EPILOGUE (FILE, SIZE); \
743 nfregs = 0; fmask = 0; \
744 for (regno = 16; regno < 31; regno++) \
745 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
746 { nfregs++; fmask |= 1 << (regno - 16); } \
747 foffset = nfregs * 12; \
748 nregs = 0; mask = 0; \
749 if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
750 for (regno = 0; regno < 16; regno++) \
751 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
752 { nregs++; mask |= 1 << regno; } \
753 if (frame_pointer_needed) { \
754 offset = nregs * 4 + fsize; \
755 if (nfregs > 0) { \
756 fprintf(FILE, "\tfldm.x @(%d,fp),", -(foffset + offset));\
757 MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
758 fprintf(FILE, "\n"); \
759 } \
760 if (nregs > 4 \
761 || current_function_pops_args) { \
762 fprintf(FILE, "\tmova @(%d,fp),sp\n", -offset); \
763 fprintf(FILE, "\texitd "); \
764 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
765 fprintf(FILE, ",#%d\n", current_function_pops_args); \
766 } else { \
767 while (nregs--) { \
768 fprintf(FILE, "\tmov:l.w @(%d,fp),", -offset); \
769 MY_PRINT_ONEREG_L(FILE, mask); \
770 fprintf(FILE, "\n"); \
771 offset -= 4; \
772 } \
773 if (TARGET_NEWRETURN) { \
774 fprintf(FILE, "\tmova.w @(4,fp),sp\n"); \
775 fprintf(FILE, "\tmov:l.w @fp,fp\n"); \
776 } else { \
777 fprintf(FILE, "\tmov.w fp,sp\n"); \
778 fprintf(FILE, "\tmov.w @sp+,fp\n"); \
779 } \
780 fprintf(FILE, "\trts\n"); \
781 } \
782 } else { \
783 if (nfregs > 0) { \
784 fprintf(FILE, "\tfldm.w @sp+,"); \
785 MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
786 fprintf(FILE, "\n"); \
787 } \
788 if (nregs > 4) { \
789 fprintf(FILE, "\tldm.w @sp+,"); \
790 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
791 fprintf(FILE, "\n"); \
792 } else { \
793 while (nregs--) { \
794 fprintf(FILE, "\tmov.w @sp+,"); \
795 MY_PRINT_ONEREG_L(FILE,mask); \
796 fprintf(FILE, "\n"); \
797 } \
798 } \
799 if (current_function_pops_args) { \
800 myoutput_sp_adjust(FILE, "add", \
801 (fsize + 4 + current_function_pops_args)); \
802 fprintf(FILE, "\tjmp @(%d,sp)\n", current_function_pops_args);\
803 } else { \
804 if (fsize > 0) \
805 myoutput_sp_adjust(FILE, "add", fsize); \
806 fprintf(FILE, "\trts\n"); \
807 } \
808 } \
809 }
810
811 /* This is a hook for other tm files to change. */
812 #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)
813
814 /* If the memory address ADDR is relative to the frame pointer,
815 correct it to be relative to the stack pointer instead.
816 This is for when we don't use a frame pointer.
817 ADDR should be a variable name. */
818
819 /* You have to change the next macro if you want to use more complex
820 addressing modes (such as double indirection and more than one
821 chain-addressing stages). */
822
823 #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
824 { int offset = -1; \
825 rtx regs = stack_pointer_rtx; \
826 if (ADDR == frame_pointer_rtx) \
827 offset = 0; \
828 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
829 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
830 offset = INTVAL (XEXP (ADDR, 1)); \
831 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
832 { rtx other_reg = XEXP (ADDR, 1); \
833 offset = 0; \
834 regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
835 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
836 { rtx other_reg = XEXP (ADDR, 0); \
837 offset = 0; \
838 regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
839 else if (GET_CODE (ADDR) == PLUS \
840 && GET_CODE (XEXP (ADDR, 0)) == PLUS \
841 && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
842 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
843 { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
844 offset = INTVAL (XEXP (ADDR, 1)); \
845 regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
846 else if (GET_CODE (ADDR) == PLUS \
847 && GET_CODE (XEXP (ADDR, 0)) == PLUS \
848 && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
849 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
850 { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
851 offset = INTVAL (XEXP (ADDR, 1)); \
852 regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
853 if (offset >= 0) \
854 { int regno; \
855 extern char call_used_regs[]; \
856 for (regno = 16; regno < 32; regno++) \
857 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
858 offset += 12; \
859 for (regno = 0; regno < 16; regno++) \
860 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
861 offset += 4; \
862 offset -= 4; \
863 ADDR = plus_constant (regs, offset + (DEPTH)); } }
864 \f
865 /* Addressing modes, and classification of registers for them. */
866
867 /* #define HAVE_POST_INCREMENT 0 */
868 /* #define HAVE_POST_DECREMENT 0 */
869
870 /* #define HAVE_PRE_DECREMENT 0 */
871 /* #define HAVE_PRE_INCREMENT 0 */
872
873 /* Macros to check register numbers against specific register classes. */
874
875 /* These assume that REGNO is a hard or pseudo reg number.
876 They give nonzero only if REGNO is a hard reg of the suitable class
877 or a pseudo reg currently allocated to a suitable hard reg.
878 Since they use reg_renumber, they are safe only once reg_renumber
879 has been allocated, which happens in local-alloc.c. */
880
881 /* Gmicro */
882 #define REGNO_OK_FOR_GREG_P(REGNO) \
883 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
884 #define REGNO_OK_FOR_FPU_P(REGNO) \
885 (((REGNO) ^ 0x10) < 16 || (unsigned) (reg_renumber[REGNO] ^ 0x10) < 16)
886
887 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
888 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
889
890 /* Now macros that check whether X is a register and also,
891 strictly, whether it is in a specified class.
892
893 These macros are specific to the Gmicro, and may be used only
894 in code for printing assembler insns and in conditions for
895 define_optimization. */
896
897 /* 1 if X is an fpu register. */
898
899 #define FPU_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPU_P (REGNO (X)))
900
901 /* I used GREG_P in the gmicro.md file. */
902
903 #ifdef REG_OK_STRICT
904 #define GREG_P(X) (REG_P (X) && REGNO_OK_FOR_GREG_P (REGNO(X)))
905 #else
906 #define GREG_P(X) (REG_P (X) && ((REGNO (X) & ~0xf) != 0x10))
907 #endif
908 \f
909 /* Maximum number of registers that can appear in a valid memory address. */
910
911 /* The Gmicro allows more registers in the chained addressing mode.
912 But I do not know gcc supports such an architecture. */
913
914 #define MAX_REGS_PER_ADDRESS 2
915
916 /* Recognize any constant value that is a valid address. */
917
918 #define CONSTANT_ADDRESS_P(X) \
919 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
920 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
921 || GET_CODE (X) == HIGH)
922
923 /* Nonzero if the constant value X is a legitimate general operand.
924 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
925
926 #define LEGITIMATE_CONSTANT_P(X) 1
927
928 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
929 and check its validity for a certain class.
930 We have two alternate definitions for each of them.
931 The usual definition accepts all pseudo regs; the other rejects
932 them unless they have been allocated suitable hard regs.
933 The symbol REG_OK_STRICT causes the latter definition to be used.
934
935 Most source files want to accept pseudo regs in the hope that
936 they will get allocated to the class that the insn wants them to be in.
937 Source files for reload pass need to be strict.
938 After reload, it makes no difference, since pseudo regs have
939 been eliminated by then. */
940
941 #ifndef REG_OK_STRICT
942
943 /* Nonzero if X is a hard reg that can be used as an index
944 or if it is a pseudo reg. */
945 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) & ~0xf) != 0x10)
946 /* Nonzero if X is a hard reg that can be used as a base reg
947 or if it is a pseudo reg. */
948 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~0xf) != 0x10)
949
950 #else
951
952 /* Nonzero if X is a hard reg that can be used as an index. */
953 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
954 /* Nonzero if X is a hard reg that can be used as a base reg. */
955 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
956
957 #endif
958 \f
959 /* The gcc uses the following effective address of the Gmicro.
960 (without using PC!!).
961 {@} ( {Rbase} + {Disp} + {Rindex * [1,2,4,8]} )
962 where
963 @: memory indirection.
964 Rbase: Base Register = General Register.
965 Disp: Displacement (up to 32bits)
966 Rindex: Index Register = General Register.
967 [1,2,4,8]: Scale of Index. 1 or 2 or 4 or 8.
968 The inside of { } can be omitted.
969 This restricts the chained addressing up to 1 stage. */
970
971
972
973 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
974 that is a valid memory address for an instruction.
975 The MODE argument is the machine mode for the MEM expression
976 that wants to use this address.
977
978 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
979 except for CONSTANT_ADDRESS_P which is actually machine-independent. */
980
981 #define REG_CODE_BASE_P(X) \
982 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
983
984 #define REG_CODE_INDEX_P(X) \
985 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
986
987 /* GET_CODE(X) must be PLUS. This macro does not check for PLUS! */
988 #define BASE_PLUS_DISP_P(X) \
989 ( REG_CODE_BASE_P (XEXP (X, 0)) \
990 && CONSTANT_ADDRESS_P (XEXP (X, 1)) \
991 || \
992 REG_CODE_BASE_P (XEXP (X, 1)) \
993 && CONSTANT_ADDRESS_P (XEXP (X, 0)) )
994
995 /* 1 if X is {0,Rbase} + {0,disp}. */
996 #define BASED_ADDRESS_P(X) \
997 (CONSTANT_ADDRESS_P (X) \
998 || REG_CODE_BASE_P (X) \
999 || (GET_CODE (X) == PLUS) \
1000 && BASE_PLUS_DISP_P (X))
1001
1002 /* 1 if X is 1 or 2 or 4 or 8. GET_CODE(X) must be CONST_INT. */
1003 #define SCALE_OF_INDEX_P(X) \
1004 ( INTVAL(X) == 4 \
1005 || INTVAL(X) == 2 \
1006 || INTVAL(X) == 8 \
1007 || INTVAL(X) == 1 )
1008
1009 /* #define INDEX_TERM_P(X,MODE) */
1010 #define INDEX_TERM_P(X) \
1011 ( REG_CODE_INDEX_P(X) \
1012 || (GET_CODE (X) == MULT \
1013 && ( (xfoo0 = XEXP (X, 0)), (xfoo1 = XEXP(X, 1)), \
1014 ( ( (GET_CODE (xfoo0) == CONST_INT) \
1015 && SCALE_OF_INDEX_P (xfoo0) \
1016 && REG_CODE_INDEX_P (xfoo1) ) \
1017 || \
1018 ( (GET_CODE (xfoo1) == CONST_INT) \
1019 && SCALE_OF_INDEX_P (xfoo1) \
1020 && REG_CODE_INDEX_P (xfoo0) ) ))))
1021
1022 /* Assumes there are no cases such that X = (Ireg + Disp) + Disp */
1023 #define BASE_DISP_INDEX_P(X) \
1024 ( BASED_ADDRESS_P (X) \
1025 || ( (GET_CODE (X) == PLUS) \
1026 && ( ( (xboo0 = XEXP (X, 0)), (xboo1 = XEXP (X, 1)), \
1027 (REG_CODE_BASE_P (xboo0) \
1028 && (GET_CODE (xboo1) == PLUS) \
1029 && ( ( CONSTANT_ADDRESS_P (XEXP (xboo1, 0)) \
1030 && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1031 || ( CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) \
1032 && INDEX_TERM_P (XEXP (xboo1, 0))) ))) \
1033 || \
1034 (CONSTANT_ADDRESS_P (xboo0) \
1035 && (GET_CODE (xboo1) == PLUS) \
1036 && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1037 && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1038 || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1039 && INDEX_TERM_P (XEXP (xboo1, 0))) )) \
1040 || \
1041 (INDEX_TERM_P (xboo0) \
1042 && ( ( (GET_CODE (xboo1) == PLUS) \
1043 && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1044 && CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) ) \
1045 || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1046 && CONSTANT_ADDRESS_P (XEXP (xboo1, 0))) )) \
1047 || \
1048 (CONSTANT_ADDRESS_P (xboo1)) \
1049 || \
1050 (REG_CODE_BASE_P (xboo1)) )))))
1051
1052 /*
1053 If you want to allow double-indirection,
1054 you have to change the <fp-relative> => <sp-relative> conversion
1055 routine. M.Yuhara
1056
1057 #ifdef REG_OK_STRICT
1058 #define DOUBLE_INDIRECTION(X,ADDR) {\
1059 if (BASE_DISP_INDEX_P (XEXP (XEXP (X, 0), 0) )) goto ADDR; \
1060 }
1061 #else
1062 #define DOUBLE_INDIRECTION(X,ADDR) { }
1063 #endif
1064 */
1065
1066
1067 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {\
1068 register rtx xboo0, xboo1, xfoo0, xfoo1; \
1069 if (GET_CODE (X) == MEM) { \
1070 /* \
1071 if (GET_CODE (XEXP (X,0)) == MEM) { \
1072 DOUBLE_INDIRECTION(X,ADDR); \
1073 } else { \
1074 if (BASE_DISP_INDEX_P (XEXP (X, 0))) goto ADDR; \
1075 } \
1076 */ \
1077 } else { \
1078 if (BASE_DISP_INDEX_P (X)) goto ADDR; \
1079 if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1080 && REG_P (XEXP (X, 0)) \
1081 && (REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM)) \
1082 goto ADDR; \
1083 } \
1084 }
1085
1086 \f
1087 /* Try machine-dependent ways of modifying an illegitimate address
1088 to be legitimate. If we find one, return the new, valid address.
1089 This macro is used in only one place: `memory_address' in explow.c.
1090
1091 OLDX is the address as it was before break_out_memory_refs was called.
1092 In some cases it is useful to look at this to decide what needs to be done.
1093
1094 MODE and WIN are passed so that this macro can use
1095 GO_IF_LEGITIMATE_ADDRESS.
1096
1097 It is always safe for this macro to do nothing. It exists to recognize
1098 opportunities to optimize the output.
1099
1100 For the Gmicro, nothing is done now. */
1101
1102 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
1103
1104 /* Go to LABEL if ADDR (a legitimate address expression)
1105 has an effect that depends on the machine mode it is used for.
1106 On the VAX, the predecrement and postincrement address depend thus
1107 (the amount of decrement or increment being the length of the operand)
1108 and all indexed address depend thus (because the index scale factor
1109 is the length of the operand).
1110 The Gmicro mimics the VAX now. Since ADDE is legitimate, it cannot
1111 include auto-inc/dec. */
1112
1113 /* Unnecessary ??? */
1114 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1115 { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \
1116 goto LABEL; }
1117
1118 \f
1119 /* Specify the machine mode that this machine uses
1120 for the index in the tablejump instruction. */
1121 /* #define CASE_VECTOR_MODE HImode */
1122 #define CASE_VECTOR_MODE SImode
1123
1124 /* Define as C expression which evaluates to nonzero if the tablejump
1125 instruction expects the table to contain offsets from the address of the
1126 table.
1127 Do not define this if the table should contain absolute addresses. */
1128 #define CASE_VECTOR_PC_RELATIVE 1
1129
1130 /* Specify the tree operation to be used to convert reals to integers. */
1131 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1132
1133 /* This is the kind of divide that is easiest to do in the general case. */
1134 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1135
1136 /* Define this as 1 if `char' should by default be signed; else as 0. */
1137 #define DEFAULT_SIGNED_CHAR 1
1138
1139 /* Max number of bytes we can move from memory to memory
1140 in one reasonably fast instruction. */
1141 #define MOVE_MAX 4
1142
1143 /* Define this if zero-extension is slow (more than one real instruction). */
1144 /* #define SLOW_ZERO_EXTEND */
1145
1146 /* Nonzero if access to memory by bytes is slow and undesirable. */
1147 #define SLOW_BYTE_ACCESS 0
1148
1149 /* Define if shifts truncate the shift count
1150 which implies one can omit a sign-extension or zero-extension
1151 of a shift count. */
1152 /* #define SHIFT_COUNT_TRUNCATED */
1153
1154 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1155 is done just by pretending it is already truncated. */
1156 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1157
1158 /* We assume that the store-condition-codes instructions store 0 for false
1159 and some other value for true. This is the value stored for true. */
1160
1161 /* #define STORE_FLAG_VALUE -1 */
1162
1163 /* When a prototype says `char' or `short', really pass an `int'. */
1164 #define PROMOTE_PROTOTYPES 1
1165
1166 /* Specify the machine mode that pointers have.
1167 After generation of rtl, the compiler makes no further distinction
1168 between pointers and any other objects of this machine mode. */
1169 #define Pmode SImode
1170
1171 /* A function address in a call instruction
1172 is a byte address (for indexing purposes)
1173 so give the MEM rtx a byte's mode. */
1174 #define FUNCTION_MODE QImode
1175
1176 /* Compute the cost of computing a constant rtl expression RTX
1177 whose rtx-code is CODE. The body of this macro is a portion
1178 of a switch statement. If the code is computed here,
1179 return it with a return statement. Otherwise, break from the switch. */
1180
1181 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1182 case CONST_INT: \
1183 if ((unsigned) INTVAL (RTX) < 8) return 0; \
1184 if ((unsigned) (INTVAL (RTX) + 0x80) < 0x100) return 1; \
1185 if ((unsigned) (INTVAL (RTX) + 0x8000) < 0x10000) return 2; \
1186 case CONST: \
1187 case LABEL_REF: \
1188 case SYMBOL_REF: \
1189 return 3; \
1190 case CONST_DOUBLE: \
1191 return 5;
1192 \f
1193 /* Define subroutines to call to handle multiply and divide.
1194 The `*' prevents an underscore from being prepended by the compiler. */
1195 /* Use libgcc on Gmicro */
1196 /* #define UDIVSI3_LIBCALL "*udiv" */
1197 /* #define UMODSI3_LIBCALL "*urem" */
1198
1199
1200 /* Tell final.c how to eliminate redundant test instructions. */
1201
1202 /* Here we define machine-dependent flags and fields in cc_status
1203 (see `conditions.h'). */
1204
1205 /* Set if the cc value is actually in the FPU, so a floating point
1206 conditional branch must be output. */
1207 #define CC_IN_FPU 04000
1208
1209 /* Store in cc_status the expressions
1210 that the condition codes will describe
1211 after execution of an instruction whose pattern is EXP.
1212 Do not alter them if the instruction would not alter the cc's. */
1213
1214 /* Since Gmicro's compare instructions depend on the branch condition,
1215 all branch should be kept.
1216 More work must be done to optimize condition code !! M.Yuhara */
1217
1218 #define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;}
1219
1220 /* The skeleton of the next macro is taken from "vax.h".
1221 FPU-reg manipulation is added. M.Yuhara */
1222 /* Now comment out.
1223 #define NOTICE_UPDATE_CC(EXP, INSN) { \
1224 if (GET_CODE (EXP) == SET) { \
1225 if ( !FPU_REG_P (XEXP (EXP, 0)) \
1226 && (XEXP (EXP, 0) != cc0_rtx) \
1227 && (FPU_REG_P (XEXP (EXP, 1)) \
1228 || GET_CODE (XEXP (EXP, 1)) == FIX \
1229 || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE \
1230 || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) { \
1231 CC_STATUS_INIT; \
1232 } else if (GET_CODE (SET_SRC (EXP)) == CALL) { \
1233 CC_STATUS_INIT; \
1234 } else if (GET_CODE (SET_DEST (EXP)) != PC) { \
1235 cc_status.flags = 0; \
1236 cc_status.value1 = SET_DEST (EXP); \
1237 cc_status.value2 = SET_SRC (EXP); \
1238 } \
1239 } else if (GET_CODE (EXP) == PARALLEL \
1240 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET \
1241 && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) {\
1242 cc_status.flags = 0; \
1243 cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \
1244 cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \
1245 /* PARALLELs whose first element sets the PC are aob, sob VAX insns. \
1246 They do change the cc's. So drop through and forget the cc's. * / \
1247 } else CC_STATUS_INIT; \
1248 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
1249 && cc_status.value2 \
1250 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
1251 cc_status.value2 = 0; \
1252 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM \
1253 && cc_status.value2 \
1254 && GET_CODE (cc_status.value2) == MEM) \
1255 cc_status.value2 = 0; \
1256 if ( (cc_status.value1 && FPU_REG_P (cc_status.value1)) \
1257 || (cc_status.value2 && FPU_REG_P (cc_status.value2))) \
1258 cc_status.flags = CC_IN_FPU; \
1259 }
1260 */
1261
1262 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1263 { if (cc_prev_status.flags & CC_IN_FPU) \
1264 return FLOAT; \
1265 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1266 return NO_OV; \
1267 return NORMAL; }
1268 \f
1269 /* Control the assembler format that we output. */
1270
1271 /* Output before read-only data. */
1272
1273 #define TEXT_SECTION_ASM_OP ".section text,code,align=4"
1274
1275 /* Output before writable data. */
1276
1277 #define DATA_SECTION_ASM_OP ".section data,data,align=4"
1278
1279 /* Output before uninitialized data. */
1280
1281 #define BSS_SECTION_ASM_OP ".section bss,data,align=4"
1282
1283 /* Output at beginning of assembler file.
1284 It is not appropriate for this to print a list of the options used,
1285 since that's not the convention that we use. */
1286
1287 #define ASM_FILE_START(FILE)
1288
1289 /* Output at the end of assembler file. */
1290
1291 #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n");
1292
1293
1294 /* Don't try to define `gcc_compiled.' since the assembler do not
1295 accept symbols with periods and GDB doesn't run on this machine anyway. */
1296 #define ASM_IDENTIFY_GCC(FILE)
1297
1298
1299 /* Output to assembler file text saying following lines
1300 may contain character constants, extra white space, comments, etc. */
1301
1302 #define ASM_APP_ON ""
1303 /* #define ASM_APP_ON "#APP\n" */
1304
1305 /* Output to assembler file text saying following lines
1306 no longer contain unusual constructs. */
1307
1308 #define ASM_APP_OFF ""
1309 /* #define ASM_APP_OFF ";#NO_APP\n" */
1310
1311 /* How to refer to registers in assembler output.
1312 This sequence is indexed by compiler's hard-register-number (see above). */
1313
1314 #define REGISTER_NAMES \
1315 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1316 "r8", "r9", "r10", "r11", "r12", "r13", "fp", "sp", \
1317 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1318 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15"}
1319
1320 /* How to renumber registers for dbx and gdb. */
1321
1322 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1323
1324 /* Define this if gcc should produce debugging output for dbx in response
1325 to the -g flag. This does not work for the Gmicro now */
1326
1327 #define DBX_DEBUGGING_INFO
1328
1329 /* This is how to output the definition of a user-level label named NAME,
1330 such as the label on a static function or variable NAME. */
1331
1332 #define ASM_OUTPUT_LABEL(FILE,NAME) { \
1333 assemble_name (FILE, NAME); \
1334 fputs (":\n", FILE); \
1335 }
1336
1337 /* This is how to output a command to make the user-level label named NAME
1338 defined for reference from other files. */
1339
1340 #define ASM_GLOBALIZE_LABEL(FILE,NAME) {\
1341 fputs ("\t.global ", FILE); \
1342 assemble_name (FILE, NAME); \
1343 fputs ("\n", FILE); \
1344 }
1345
1346 /* This is how to output a command to make the external label named NAME
1347 which are not defined in the file to be referable */
1348 /* ".import" does not work ??? */
1349
1350 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) { \
1351 fputs ("\t.global ", FILE); \
1352 assemble_name (FILE, NAME); \
1353 fputs ("\n", FILE); \
1354 }
1355
1356
1357 /* The prefix to add to user-visible assembler symbols. */
1358
1359 #define USER_LABEL_PREFIX "_"
1360
1361 /* This is how to output an internal numbered label where
1362 PREFIX is the class of label and NUM is the number within the class. */
1363
1364 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1365 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1366
1367 /* This is how to store into the string LABEL
1368 the symbol_ref name of an internal numbered label where
1369 PREFIX is the class of label and NUM is the number within the class.
1370 This is suitable for output with `assemble_name'. */
1371
1372 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1373 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1374
1375 /* This is how to output an assembler line defining a `double' constant. */
1376
1377 /* do {...} while(0) is necessary, because these macros are used as
1378 if (xxx) MACRO; else ....
1379 ^
1380 */
1381
1382
1383 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1384 do { union { double d; long l[2];} tem; \
1385 tem.d = (VALUE); \
1386 fprintf (FILE, "\t.fdata.d h'%x%08x.d\n", tem.l[0], tem.l[1]); \
1387 } while(0)
1388
1389
1390 /* This is how to output an assembler line defining a `float' constant. */
1391
1392 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1393 do { union { float f; long l;} tem; \
1394 tem.f = (VALUE); \
1395 fprintf (FILE, "\t.fdata.s h'%x.s\n", tem.l); \
1396 } while(0)
1397
1398 /* This is how to output an assembler line defining an `int' constant. */
1399
1400 #define ASM_OUTPUT_INT(FILE,VALUE) \
1401 ( fprintf (FILE, "\t.data.w "), \
1402 output_addr_const (FILE, (VALUE)), \
1403 fprintf (FILE, "\n"))
1404
1405 /* Likewise for `char' and `short' constants. */
1406
1407 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1408 ( fprintf (FILE, "\t.data.h "), \
1409 output_addr_const (FILE, (VALUE)), \
1410 fprintf (FILE, "\n"))
1411
1412 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1413 ( fprintf (FILE, "\t.data.b "), \
1414 output_addr_const (FILE, (VALUE)), \
1415 fprintf (FILE, "\n"))
1416
1417 /* This is how to output an assembler line for a numeric constant byte. */
1418
1419 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1420 fprintf (FILE, "\t.data.b h'%x\n", (VALUE))
1421
1422 #define ASM_OUTPUT_ASCII(FILE,P,SIZE) \
1423 output_ascii ((FILE), (P), (SIZE))
1424
1425 /* This is how to output an insn to push a register on the stack.
1426 It need not be very fast code. */
1427
1428 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1429 fprintf (FILE, "\tmov %s,@-sp\n", reg_names[REGNO])
1430
1431 /* This is how to output an insn to pop a register from the stack.
1432 It need not be very fast code. */
1433
1434 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1435 fprintf (FILE, "\tmov @sp+,%s\n", reg_names[REGNO])
1436
1437 /* This is how to output an element of a case-vector that is absolute.
1438 (The Gmicro does not use such vectors,
1439 but we must define this macro anyway.) */
1440
1441 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1442 fprintf (FILE, "\t.data.w L%d\n", VALUE)
1443
1444
1445 /* This is how to output an element of a case-vector that is relative. */
1446
1447 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1448 fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL)
1449
1450
1451 /* This is how to output an assembler line
1452 that says to advance the location counter
1453 to a multiple of 2**LOG bytes. */
1454
1455 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1456 fprintf (FILE, "\t.align %d\n", (1 << (LOG)));
1457
1458 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1459 fprintf (FILE, "\t.res.b %d\n", (SIZE))
1460
1461 /* This says how to output an assembler line
1462 to define a global common symbol. */
1463
1464 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1465 ( bss_section (), \
1466 assemble_name ((FILE), (NAME)), \
1467 fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)),\
1468 fprintf ((FILE), "\t.export "), \
1469 assemble_name ((FILE), (NAME)), \
1470 fprintf ((FILE), "\n") )
1471
1472 /* This says how to output an assembler line
1473 to define a local common symbol. */
1474
1475 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1476 ( bss_section (), \
1477 assemble_name ((FILE), (NAME)), \
1478 fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)))
1479
1480 /* Store in OUTPUT a string (made with alloca) containing
1481 an assembler-name for a local static variable named NAME.
1482 LABELNO is an integer which is different for each call. */
1483
1484 /* $__ is unique ????? M.Yuhara */
1485 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1486 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \
1487 sprintf ((OUTPUT), "$__%s%d", (NAME), (LABELNO)))
1488
1489 /* Define the parentheses used to group arithmetic operations
1490 in assembler code. */
1491
1492 #define ASM_OPEN_PAREN "("
1493 #define ASM_CLOSE_PAREN ")"
1494
1495 /* Define results of standard character escape sequences. */
1496 #define TARGET_BELL 007
1497 #define TARGET_BS 010
1498 #define TARGET_TAB 011
1499 #define TARGET_NEWLINE 012
1500 #define TARGET_VT 013
1501 #define TARGET_FF 014
1502 #define TARGET_CR 015
1503
1504 /* Output a float value (represented as a C double) as an immediate operand.
1505 This macro is a Gmicro/68k-specific macro. */
1506
1507 #define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE) \
1508 do { union { float f; long l;} tem; \
1509 tem.f = (VALUE); \
1510 fprintf (FILE, "#h'%x.s", tem.l); \
1511 } while(0)
1512
1513
1514 /* Output a double value (represented as a C double) as an immediate operand.
1515 This macro is a 68k-specific macro. */
1516 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1517 do { union { double d; long l[2];} tem; \
1518 tem.d = (VALUE); \
1519 fprintf (FILE, "#h'%x%08x.d", tem.l[0], tem.l[1]); \
1520 } while(0)
1521
1522 /* Print operand X (an rtx) in assembler syntax to file FILE.
1523 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1524 For `%' followed by punctuation, CODE is the punctuation and X is null.
1525
1526 On the Gmicro, we use several CODE characters:
1527 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1528 'b' for branch target label.
1529 '-' for an operand pushing on the stack.
1530 '+' for an operand pushing on the stack.
1531 '#' for an immediate operand prefix
1532 */
1533
1534 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1535 ( (CODE) == '#' || (CODE) == '-' \
1536 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
1537
1538
1539 #define PRINT_OPERAND(FILE, X, CODE) \
1540 { int i; \
1541 static char *reg_name[] = REGISTER_NAMES; \
1542 /* fprintf (stderr, "PRINT_OPERAND CODE=%c(0x%x), ", CODE, CODE);\
1543 myprcode(GET_CODE(X)); */ \
1544 if (CODE == '#') fprintf (FILE, "#"); \
1545 else if (CODE == '-') fprintf (FILE, "@-sp"); \
1546 else if (CODE == '+') fprintf (FILE, "@sp+"); \
1547 else if (CODE == 's') fprintf (stderr, "err: PRINT_OPERAND <s>\n"); \
1548 else if (CODE == '!') fprintf (stderr, "err: PRINT_OPERAND <!>\n"); \
1549 else if (CODE == '.') fprintf (stderr, "err: PRINT_OPERAND <.>\n"); \
1550 else if (CODE == 'b') { \
1551 if (GET_CODE (X) == MEM) \
1552 output_addr_const (FILE, XEXP (X, 0)); /* for bsr */ \
1553 else \
1554 output_addr_const (FILE, X); /* for bcc */ \
1555 } \
1556 else if (CODE == 'p') \
1557 print_operand_address (FILE, X); \
1558 else if (GET_CODE (X) == REG) \
1559 fprintf (FILE, "%s", reg_name[REGNO (X)]); \
1560 else if (GET_CODE (X) == MEM) \
1561 output_address (XEXP (X, 0)); \
1562 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1563 { union { double d; int i[2]; } u; \
1564 union { float f; int i; } u1; \
1565 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1566 u1.f = u.d; \
1567 if (CODE == 'f') \
1568 ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); \
1569 else \
1570 fprintf (FILE, "#h'%x", u1.i); } \
1571 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \
1572 { union { double d; int i[2]; } u; \
1573 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1574 ASM_OUTPUT_DOUBLE_OPERAND (FILE, u.d); } \
1575 else { putc ('#', FILE); \
1576 output_addr_const (FILE, X); }}
1577 \f
1578 /* Note that this contains a kludge that knows that the only reason
1579 we have an address (plus (label_ref...) (reg...))
1580 is in the insn before a tablejump, and we know that m68k.md
1581 generates a label LInnn: on such an insn. */
1582 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1583 { print_operand_address (FILE, ADDR); }
1584 \f
1585 /*
1586 Local variables:
1587 version-control: t
1588 End:
1589 */
GNU Compiler Collection
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