1 /* Definitions of target machine for GNU compiler. Gmicro (TRON) version.
2 Copyright (C) 1987, 1988, 1989 Free Software Foundation, Inc.
3 Contributed by Masanobu Yuhara, Fujitsu Laboratories LTD.
4 (yuhara@flab.fujitsu.co.jp)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions that relate to assembler syntax. */
27 /* Names to predefine in the preprocessor for this target machine. */
29 #define CPP_PREDEFINES "-Dgmicro -Acpu(tron) -Amachine(tron)"
31 /* #define CPP_SPEC ** currently not defined **/
33 /* #define CC1_SPEC ** currently not defined **/
36 /* Print subsidiary information on the compiler version in use. */
38 #define TARGET_VERSION fprintf (stderr, " (Gmicro syntax)");
41 /* Run-time compilation parameters selecting different hardware subsets. */
43 extern int target_flags
;
45 /* Macros used in the machine description to test the flags. */
47 /* Compile for a Gmicro/300. */
48 #define TARGET_G300 (target_flags & 1)
49 /* Compile for a Gmicro/200. */
50 #define TARGET_G200 (target_flags & 2)
51 /* Compile for a Gmicro/100. */
52 #define TARGET_G100 (target_flags & 4)
54 /* Compile FPU insns for floating point (not library calls). */
55 #define TARGET_FPU (target_flags & 8)
57 /* Pop up arguments by called function. */
58 #define TARGET_RTD (target_flags & 0x10)
60 /* Compile passing first args in regs 0 and 1.
61 This exists only to test compiler features that will be needed for
62 RISC chips. It is not usable and is not intended to be usable on
64 #define TARGET_REGPARM (target_flags & 0x20)
66 #define TARGET_BITFIELD (target_flags & 0x40)
68 #define TARGET_NEWRETURN (target_flags & 0x80)
70 /* Do not expand __builtin_smov (strcpy) to multiple movs.
71 Use the smov instruction. */
72 #define TARGET_FORCE_SMOV (target_flags & 0x100)
74 /* default options are -m300, -mFPU,
75 with bitfield instructions added because it won't always work otherwise.
76 If there are versions of the gmicro that don't support bitfield instructions
77 then it will take some thinking to figure out how to make them work. */
78 #define TARGET_DEFAULT 0x49
80 /* Macro to define tables used to set the flags.
81 This is a list in braces of pairs in braces,
82 each pair being { "NAME", VALUE }
83 where VALUE is the bits to set or minus the bits to clear.
84 An empty string NAME is used to identify the default VALUE. */
86 #define TARGET_SWITCHES \
91 { "soft-float", -8}, \
95 { "no-regparm", -0x20}, \
96 #if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
97 STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions. */
98 { "bitfield", 0x40}, \
99 { "no-bitfield", -0x40}, \
101 { "newreturn", 0x80}, \
102 { "no-newreturn", -0x80}, \
103 { "force-smov", 0x100}, \
104 { "no-force-smov", -0x100}, \
105 { "", TARGET_DEFAULT
}}
108 /* Blow away G100 flag silently off TARGET_fpu (since we can't clear
109 any bits in TARGET_SWITCHES above) */
110 #define OVERRIDE_OPTIONS \
112 if (TARGET_G100) target_flags &= ~8; \
115 /* target machine storage layout */
117 /* Define this if most significant bit is lowest numbered
118 in instructions that operate on numbered bit-fields.
119 This is true for Gmicro insns.
120 We make it true always by avoiding using the single-bit insns
121 except in special cases with constant bit numbers. */
122 #define BITS_BIG_ENDIAN 1
124 /* Define this if most significant byte of a word is the lowest numbered. */
125 /* That is true on the Gmicro. */
126 #define BYTES_BIG_ENDIAN 1
128 /* Define this if most significant word of a multiword number is the lowest
130 /* For Gmicro we can decide arbitrarily
131 since there are no machine instructions for them. ????? */
132 #define WORDS_BIG_ENDIAN 0
134 /* number of bits in an addressable storage unit */
135 #define BITS_PER_UNIT 8
137 /* Width in bits of a "word", which is the contents of a machine register. */
138 #define BITS_PER_WORD 32
140 /* Width of a word, in units (bytes). */
141 #define UNITS_PER_WORD 4
143 /* Width in bits of a pointer.
144 See also the macro `Pmode' defined below. */
145 #define POINTER_SIZE 32
147 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
148 #define PARM_BOUNDARY 32
150 /* Boundary (in *bits*) on which stack pointer should be aligned. */
151 #define STACK_BOUNDARY 32
153 /* Allocation boundary (in *bits*) for the code of a function. */
154 /* Instructions of the Gmicro should be on half-word boundary */
155 /* But word boundary gets better performance */
156 #define FUNCTION_BOUNDARY 32
158 /* Alignment of field after `int : 0' in a structure. */
159 #define EMPTY_FIELD_BOUNDARY 32
161 /* No data type wants to be aligned rounder than this. */
162 /* This is not necessarily 32 on the Gmicro */
163 #define BIGGEST_ALIGNMENT 32
165 /* Set this non-zero if move instructions will actually fail to work
166 when given unaligned data.
167 Unaligned data is allowed on Gmicro, though the access is slow. */
169 #define STRICT_ALIGNMENT 1
170 #define SLOW_UNALIGNED_ACCESS 1
172 /* Make strings word-aligned so strcpy from constants will be faster. */
173 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
174 (TREE_CODE (EXP) == STRING_CST \
175 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
177 /* Make arrays of chars word-aligned for the same reasons. */
178 #define DATA_ALIGNMENT(TYPE, ALIGN) \
179 (TREE_CODE (TYPE) == ARRAY_TYPE \
180 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
181 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
183 /* Define number of bits in most basic integer type.
184 (If undefined, default is BITS_PER_WORD). */
185 #define INT_TYPE_SIZE 32
187 /* #define PCC_BITFIELD_TYPE_MATTERS 1 ????? */
189 /* #define CHECK_FLOAT_VALUE (MODE, VALUE) ????? */
192 /* Standard register usage. */
194 /* Number of actual hardware registers.
195 The hardware registers are assigned numbers for the compiler
196 from 0 to just below FIRST_PSEUDO_REGISTER.
197 All registers that the compiler knows about must be given numbers,
198 even those that are not normally considered general registers.
199 For the Gmicro, we give the general registers numbers 0-15,
200 and the FPU floating point registers numbers 16-31. */
201 #define FIRST_PSEUDO_REGISTER 32
203 /* 1 for registers that have pervasive standard uses
204 and are not available for the register allocator.
205 On the Gmicro, the stack pointer and the frame pointer are
207 /* frame pointer is not indicated as fixed, because fp may be used freely
208 when a frame is not built. */
209 #define FIXED_REGISTERS \
210 {0, 0, 0, 0, 0, 0, 0, 0, \
211 0, 0, 0, 0, 0, 0, 0, 1, \
212 /* FPU registers. */ \
213 0, 0, 0, 0, 0, 0, 0, 0, \
214 0, 0, 0, 0, 0, 0, 0, 0, }
216 /* 1 for registers not available across function calls.
217 These must include the FIXED_REGISTERS and also any
218 registers that can be used without being saved.
219 The latter must include the registers where values are returned
220 and the register where structure-value addresses are passed.
221 Aside from that, you can include as many other registers as you like. */
222 #define CALL_USED_REGISTERS \
223 {1, 1, 1, 1, 0, 0, 0, 0, \
224 0, 0, 0, 0, 0, 0, 0, 1, \
225 /* FPU registers. */ \
226 1, 1, 1, 1, 0, 0, 0, 0, \
227 0, 0, 0, 0, 0, 0, 0, 0, }
230 /* Make sure everything's fine if we *don't* have a given processor.
231 This assumes that putting a register in fixed_regs will keep the
232 compilers mitt's completely off it. We don't bother to zero it out
233 of register classes. If TARGET_FPU is not set,
234 the compiler won't touch since no instructions that use these
235 registers will be valid. */
236 /* This Macro is not defined now.
237 #define CONDITIONAL_REGISTER_USAGE */
239 /* The Gmicro has no overlapping register */
240 /* #define OVERLAPPING_REGNO_P(REGNO) */
242 /* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO) */
243 /* #define PRESERVE_DEATH_INFO_REGNO_P(REGNO) */
245 /* Return number of consecutive hard regs needed starting at reg REGNO
246 to hold something of mode MODE.
247 This is ordinarily the length in words of a value of mode MODE
248 but can be less for certain modes in special long registers.
250 On the Gmicro, ordinary registers hold 32 bits worth;
251 for the Gmicro/FPU registers, a single register is always enough for
252 anything that can be stored in them at all. */
253 #define HARD_REGNO_NREGS(REGNO, MODE) \
255 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
257 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
258 On the Gmicro, the cpu registers can hold any mode but the FPU registers
259 can hold only SFmode or DFmode. And the FPU registers can't hold anything
260 if FPU use is disabled. */
261 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
264 ? TARGET_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT || \
265 GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
268 /* Value is 1 if it is a good idea to tie two pseudo registers
269 when one has mode MODE1 and one has mode MODE2.
270 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
271 for any hard reg, then this must be 0 for correct output. */
272 #define MODES_TIEABLE_P(MODE1, MODE2) \
274 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
275 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
276 == ((MODE2) == SFmode || (MODE2) == DFmode)))
278 /* Specify the registers used for certain standard purposes.
279 The values of these macros are register numbers. */
281 /* Gmicro pc isn't overloaded on a register. */
282 /* #define PC_REGNUM */
284 /* Register to use for pushing function arguments. */
285 #define STACK_POINTER_REGNUM 15
287 /* Base register for access to local variables of the function. */
288 #define FRAME_POINTER_REGNUM 14
290 /* Value should be nonzero if functions must have frame pointers.
291 Zero means the frame pointer need not be set up (and parms
292 may be accessed via the stack pointer) in functions that seem suitable.
293 This is computed in `reload', in reload1.c. */
294 #define FRAME_POINTER_REQUIRED 0
296 /* Base register for access to arguments of the function. */
297 /* The Gmicro does not have hardware ap. Fp is treated as ap */
298 #define ARG_POINTER_REGNUM 14
300 /* Register in which static-chain is passed to a function. */
301 #define STATIC_CHAIN_REGNUM 0
303 /* Register in which address to store a structure value
304 is passed to a function. */
305 #define STRUCT_VALUE_REGNUM 1
307 /* Define the classes of registers for register constraints in the
308 machine description. Also define ranges of constants.
310 One of the classes must always be named ALL_REGS and include all hard regs.
311 If there is more than one class, another class must be named NO_REGS
312 and contain no registers.
314 The name GENERAL_REGS must be the name of a class (or an alias for
315 another name such as ALL_REGS). This is the class of registers
316 that is allowed by "g" or "r" in a register constraint.
317 Also, registers outside this class are allocated only when
318 instructions express preferences for them.
320 The classes must be numbered in nondecreasing order; that is,
321 a larger-numbered class must never be contained completely
322 in a smaller-numbered class.
324 For any two classes, it is very desirable that there be another
325 class that represents their union. */
327 /* The Gmicro has two kinds of registers, so four classes would be
330 enum reg_class
{ NO_REGS
, FPU_REGS
, GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
332 #define N_REG_CLASSES (int) LIM_REG_CLASSES
334 /* Give names of register classes as strings for dump file. */
336 #define REG_CLASS_NAMES \
337 { "NO_REGS", "FPU_REGS", "GENERAL_REGS", "ALL_REGS" }
339 /* Define which registers fit in which classes.
340 This is an initializer for a vector of HARD_REG_SET
341 of length N_REG_CLASSES. */
343 #define REG_CLASS_CONTENTS \
346 0xffff0000, /* FPU_REGS */ \
347 0x0000ffff, /* GENERAL_REGS */ \
348 0xffffffff /* ALL_REGS */ \
351 /* The same information, inverted:
352 Return the class number of the smallest class containing
353 reg number REGNO. This could be a conditional expression
354 or could index an array. */
356 extern enum reg_class regno_reg_class
[];
357 #define REGNO_REG_CLASS(REGNO) ( (REGNO < 16) ? GENERAL_REGS : FPU_REGS )
359 /* The class value for index registers, and the one for base regs. */
361 #define INDEX_REG_CLASS GENERAL_REGS
362 #define BASE_REG_CLASS GENERAL_REGS
364 /* Get reg_class from a letter such as appears in the machine description.
365 We do a trick here to modify the effective constraints on the
366 machine description; we zorch the constraint letters that aren't
367 appropriate for a specific target. This allows us to guarantee
368 that a specific kind of register will not be used for a given target
369 without fiddling with the register classes above. */
371 #define REG_CLASS_FROM_LETTER(C) \
372 ((C) == 'r' ? GENERAL_REGS : \
373 ((C) == 'f' ? (TARGET_FPU ? FPU_REGS : NO_REGS) : \
376 /* The letters I, J, K, L and M in a register constraint string
377 can be used to stand for particular ranges of immediate operands.
378 This macro defines what the ranges are.
379 C is the letter, and VALUE is a constant value.
380 Return 1 if VALUE is in the range specified by C.
382 For the Gmicro, all immediate value optimizations are done
383 by assembler, so no machine dependent definition is necessary ??? */
385 /* #define CONST_OK_FOR_LETTER_P(VALUE, C) ((C) == 'I') */
386 #define CONST_OK_FOR_LETTER_P(VALUE, C) 0
389 * The letters G defines all of the floating constants tha are *NOT*
390 * Gmicro-FPU constant.
393 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
395 (C) == 'G' && !(TARGET_FPU && standard_fpu_constant_p (VALUE)))
397 /* Given an rtx X being reloaded into a reg required to be
398 in class CLASS, return the class of reg to actually use.
399 In general this is just CLASS; but on some machines
400 in some cases it is preferable to use a more restrictive class. */
401 /* On the Gmicro series, there is no restriction on GENERAL_REGS,
402 so CLASS is returned. I do not know whether I should treat FPU_REGS
403 specially or not (at least, m68k does not). */
405 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
407 /* Return the maximum number of consecutive registers
408 needed to represent mode MODE in a register of class CLASS. */
409 /* On the Gmicro, this is the size of MODE in words,
410 except in the FPU regs, where a single reg is always enough. */
411 #define CLASS_MAX_NREGS(CLASS, MODE) \
412 ((CLASS) == FPU_REGS ? \
413 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
415 /* Stack layout; function entry, exit and calling. */
417 /* Define this if pushing a word on the stack
418 makes the stack pointer a smaller address. */
419 #define STACK_GROWS_DOWNWARD
421 /* Define this if the nominal address of the stack frame
422 is at the high-address end of the local variables;
423 that is, each additional local variable allocated
424 goes at a more negative offset in the frame. */
425 #define FRAME_GROWS_DOWNWARD
427 /* Offset within stack frame to start allocating local variables at.
428 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
429 first local allocated. Otherwise, it is the offset to the BEGINNING
430 of the first local allocated. */
431 /* On the Gmicro, FP points to the old FP and the first local variables are
433 #define STARTING_FRAME_OFFSET 0
435 /* If we generate an insn to push BYTES bytes,
436 this says how many the stack pointer really advances by. */
437 /* On the Gmicro, sp is decremented by the exact size of the operand */
438 #define PUSH_ROUNDING(BYTES) (BYTES)
440 /* Offset of first parameter from the argument pointer register value. */
441 /* On the Gmicro, the first argument is found at (ap + 8) where ap is fp. */
442 #define FIRST_PARM_OFFSET(FNDECL) 8
444 /* Value is the number of byte of arguments automatically
445 popped when returning from a subroutine call.
446 FUNTYPE is the data type of the function (as a tree),
447 or for a library call it is an identifier node for the subroutine name.
448 SIZE is the number of bytes of arguments passed on the stack.
450 On the Gmicro, the EXITD insn may be used to pop them if the number
451 of args is fixed, but if the number is variable then the caller must pop
452 them all. The adjsp operand of the EXITD insn can't be used for library
453 calls now because the library is compiled with the standard compiler.
454 Use of adjsp operand is a selectable option, since it is incompatible with
455 standard Unix calling sequences. If the option is not selected,
456 the caller must always pop the args.
457 On the m68k this is an RTD option, so I use the same name
458 for the Gmicro. The option name may be changed in the future. */
460 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \
461 ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \
462 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
463 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
464 = void_type_node))) \
467 /* Define how to find the value returned by a function.
468 VALTYPE is the data type of the value (as a tree).
469 If the precise function being called is known, FUNC is its FUNCTION_DECL;
470 otherwise, FUNC is 0. */
472 /* On the Gmicro the floating return value is in fr0 not r0. */
474 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
476 /* Define how to find the value returned by a library function
477 assuming the value has mode MODE. */
479 #define LIBCALL_VALUE(MODE) \
480 (gen_rtx (REG, (MODE), \
481 ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0)))
484 /* 1 if N is a possible register number for a function value.
485 On the Gmicro, r0 and fp0 are the possible registers. */
487 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 16)
489 /* Define this if PCC uses the nonreentrant convention for returning
490 structure and union values. */
492 #define PCC_STATIC_STRUCT_RETURN
494 /* 1 if N is a possible register number for function argument passing.
495 On the Gmicro, no registers are used in this way. */
496 /* Really? For the performance improvement, registers should be used !! */
498 #define FUNCTION_ARG_REGNO_P(N) 0
500 /* Define a data type for recording info about an argument list
501 during the scan of that argument list. This data type should
502 hold all necessary information about the function itself
503 and about the args processed so far, enough to enable macros
504 such as FUNCTION_ARG to determine where the next arg should go.
506 On the Gmicro, this is a single integer, which is a number of bytes
507 of arguments scanned so far. */
509 #define CUMULATIVE_ARGS int
511 /* Initialize a variable CUM of type CUMULATIVE_ARGS
512 for a call to a function whose data type is FNTYPE.
513 For a library call, FNTYPE is 0.
515 On the Gmicro, the offset starts at 0. */
517 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
520 /* Update the data in CUM to advance over an argument
521 of mode MODE and data type TYPE.
522 (TYPE is null for libcalls where that information may not be available.) */
524 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
525 ((CUM) += ((MODE) != BLKmode \
526 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
527 : (int_size_in_bytes (TYPE) + 3) & ~3))
529 /* Define where to put the arguments to a function.
530 Value is zero to push the argument on the stack,
531 or a hard register in which to store the argument.
533 MODE is the argument's machine mode.
534 TYPE is the data type of the argument (as a tree).
535 This is null for libcalls where that information may
537 CUM is a variable of type CUMULATIVE_ARGS which gives info about
538 the preceding args and about the function being called.
539 NAMED is nonzero if this argument is a named parameter
540 (otherwise it is an extra parameter matching an ellipsis). */
542 /* On the Gmicro all args are pushed, except if -mregparm is specified
543 then the first two words of arguments are passed in d0, d1.
544 *NOTE* -mregparm does not work.
545 It exists only to test register calling conventions. */
547 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
548 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
550 /* For an arg passed partly in registers and partly in memory,
551 this is the number of registers used.
552 For args passed entirely in registers or entirely in memory, zero. */
554 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
555 ((TARGET_REGPARM && (CUM) < 8 \
556 && 8 < ((CUM) + ((MODE) == BLKmode \
557 ? int_size_in_bytes (TYPE) \
558 : GET_MODE_SIZE (MODE)))) \
561 /* The following macro is defined to output register list.
562 The LSB of Mask is the lowest number register.
563 Regoff is MY_GREG_OFF or MY_FREG_OFF.
564 Do NOT use <i> in File, Mask, Regoff !!
565 Should be changed from macros to functions. M.Yuhara */
567 #define MY_GREG_OFF 0
568 #define MY_FREG_OFF 16
570 #define MY_PRINT_MASK(File, Mask, Regoff) \
574 fprintf(File, "#0"); \
576 fprintf(File, "("); \
577 for (i = 0; i < 16; i++) { \
578 if ( (Mask) & (1 << i) ) { \
581 fprintf(File, ","); \
584 fprintf(File, "%s", reg_names[Regoff + i]); \
586 } else if (first >= 0) { \
587 if (i > first + 1) { \
588 fprintf(File, "-%s", reg_names[Regoff + i - 1]); \
593 if ( (first >= 0) && (first != 15) ) \
594 fprintf(File, "-%s", reg_names[Regoff + 15]);\
595 fprintf(File, ")"); \
600 #define MY_PRINT_ONEREG_L(FILE,MASK) \
602 for (i = 0; i < 16; i++) \
603 if ( (1 << i) & (MASK)) { \
604 fprintf(FILE, "%s", reg_names[i]); \
605 (MASK) &= ~(1 << i); \
611 #define MY_PRINT_ONEREG_H(FILE,MASK) \
613 for (i = 15; i >= 0; i--) \
614 if ( (1 << i) & (MASK)) { \
615 fprintf(FILE, "%s", reg_names[i]); \
616 (MASK) &= ~(1 << i); \
621 /* This macro generates the assembly code for function entry.
622 FILE is a stdio stream to output the code to.
623 SIZE is an int: how many units of temporary storage to allocate.
624 Refer to the array `regs_ever_live' to determine which registers
625 to save; `regs_ever_live[I]' is nonzero if register number I
626 is ever used in the function. This macro is responsible for
627 knowing which registers should not be saved even if used. */
629 /* The next macro needs much optimization !!
632 #define FUNCTION_PROLOGUE(FILE, SIZE) \
633 { register int regno; \
634 register int mask = 0; \
635 register int nregs = 0; \
636 static char *reg_names[] = REGISTER_NAMES; \
637 extern char call_used_regs[]; \
638 int fsize = ((SIZE) + 3) & -4; \
639 for (regno = 0; regno < 16; regno++) \
640 if (regs_ever_live[regno] && !call_used_regs[regno]) { \
641 mask |= (1 << regno); \
644 if (frame_pointer_needed) { \
645 mask &= ~(1 << FRAME_POINTER_REGNUM); \
647 fprintf(FILE, "\tenter.w #%d,", fsize); \
648 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
649 fprintf(FILE,"\n"); \
651 fprintf(FILE, "\tmov.w fp,@-sp\n"); \
652 fprintf(FILE, "\tmov.w sp,fp\n"); \
654 myoutput_sp_adjust(FILE, "sub", fsize); \
656 fprintf(FILE, "\tmov.w "); \
657 MY_PRINT_ONEREG_H(FILE, mask); \
658 fprintf(FILE, ",@-sp\n"); \
663 myoutput_sp_adjust(FILE, "sub", fsize); \
666 fprintf(FILE, "\tstm.w "); \
667 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
668 fprintf(FILE, ",@-sp\n"); \
671 fprintf(FILE, "\tmov.w "); \
672 MY_PRINT_ONEREG_H(FILE, mask); \
673 fprintf(FILE, ",@-sp\n"); \
679 for (regno = 16; regno < 32; regno++) \
680 if (regs_ever_live[regno] && !call_used_regs[regno]) \
681 mask |= 1 << (regno - 16); \
683 fprintf(FILE, "\tfstm.w "); \
684 MY_PRINT_MASK(FILE, mask, MY_FREG_OFF); \
685 fprintf(FILE, ",@-sp\n", mask); \
690 /* Output assembler code to FILE to increment profiler label # LABELNO
691 for profiling a function entry. */
694 #define FUNCTION_PROFILER(FILE, LABELNO) \
695 fprintf (FILE, "\tmova @LP%d,r0\n\tjsr mcount\n", (LABELNO))
697 /* Output assembler code to FILE to initialize this source file's
698 basic block profiling info, if that has not already been done. */
700 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
701 fprintf (FILE, "\tcmp #0,@LPBX0\n\tbne LPI%d\n\tpusha @LPBX0\n\tjsr ___bb_init_func\n\tadd #4,sp\nLPI%d:\n", \
704 /* Output assembler code to FILE to increment the entry-count for
705 the BLOCKNO'th basic block in this source file. */
707 #define BLOCK_PROFILER(FILE, BLOCKNO) \
708 fprintf (FILE, "\tadd #1,@(LPBX2+%d)\n", 4 * BLOCKNO)
710 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
711 the stack pointer does not matter. The value is tested only in
712 functions that have frame pointers.
713 No definition is equivalent to always zero. */
715 #define EXIT_IGNORE_STACK 1
717 /* This macro generates the assembly code for function exit,
718 on machines that need it. If FUNCTION_EPILOGUE is not defined
719 then individual return instructions are generated for each
720 return statement. Args are same as for FUNCTION_PROLOGUE.
722 The function epilogue should not depend on the current stack pointer (when
723 frame_pinter_needed) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
724 It should use the frame pointer only. This is mandatory because
725 of alloca; we also take advantage of it to omit stack adjustments
728 /* The Gmicro FPU seems to be unable to fldm/fstm double or single
729 floating. It only allows extended !! */
730 /* Optimization is not enough, especially FREGs load !! M.Yuhara */
732 #define FUNCTION_EPILOGUE(FILE, SIZE) \
733 { register int regno; \
734 register int mask, fmask; \
735 register int nregs, nfregs; \
736 int offset, foffset; \
737 extern char call_used_regs[]; \
738 static char *reg_names[] = REGISTER_NAMES; \
739 int fsize = ((SIZE) + 3) & -4; \
740 FUNCTION_EXTRA_EPILOGUE (FILE, SIZE); \
741 nfregs = 0; fmask = 0; \
742 for (regno = 16; regno < 31; regno++) \
743 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
744 { nfregs++; fmask |= 1 << (regno - 16); } \
745 foffset = nfregs * 12; \
746 nregs = 0; mask = 0; \
747 if (frame_pointer_needed) regs_ever_live[FRAME_POINTER_REGNUM] = 0; \
748 for (regno = 0; regno < 16; regno++) \
749 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
750 { nregs++; mask |= 1 << regno; } \
751 if (frame_pointer_needed) { \
752 offset = nregs * 4 + fsize; \
754 fprintf(FILE, "\tfldm.x @(%d,fp),", -(foffset + offset));\
755 MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
756 fprintf(FILE, "\n"); \
759 || current_function_pops_args) { \
760 fprintf(FILE, "\tmova @(%d,fp),sp\n", -offset); \
761 fprintf(FILE, "\texitd "); \
762 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
763 fprintf(FILE, ",#%d\n", current_function_pops_args); \
766 fprintf(FILE, "\tmov:l.w @(%d,fp),", -offset); \
767 MY_PRINT_ONEREG_L(FILE, mask); \
768 fprintf(FILE, "\n"); \
771 if (TARGET_NEWRETURN) { \
772 fprintf(FILE, "\tmova.w @(4,fp),sp\n"); \
773 fprintf(FILE, "\tmov:l.w @fp,fp\n"); \
775 fprintf(FILE, "\tmov.w fp,sp\n"); \
776 fprintf(FILE, "\tmov.w @sp+,fp\n"); \
778 fprintf(FILE, "\trts\n"); \
782 fprintf(FILE, "\tfldm.w @sp+,"); \
783 MY_PRINT_MASK(FILE, fmask, MY_FREG_OFF); \
784 fprintf(FILE, "\n"); \
787 fprintf(FILE, "\tldm.w @sp+,"); \
788 MY_PRINT_MASK(FILE, mask, MY_GREG_OFF); \
789 fprintf(FILE, "\n"); \
792 fprintf(FILE, "\tmov.w @sp+,"); \
793 MY_PRINT_ONEREG_L(FILE,mask); \
794 fprintf(FILE, "\n"); \
797 if (current_function_pops_args) { \
798 myoutput_sp_adjust(FILE, "add", \
799 (fsize + 4 + current_function_pops_args)); \
800 fprintf(FILE, "\tjmp @(%d,sp)\n", current_function_pops_args);\
803 myoutput_sp_adjust(FILE, "add", fsize); \
804 fprintf(FILE, "\trts\n"); \
809 /* This is a hook for other tm files to change. */
810 #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE)
812 /* If the memory address ADDR is relative to the frame pointer,
813 correct it to be relative to the stack pointer instead.
814 This is for when we don't use a frame pointer.
815 ADDR should be a variable name. */
817 /* You have to change the next macro if you want to use more complex
818 addressing modes (such as double indirection and more than one
819 chain-addressing stages). */
821 #define FIX_FRAME_POINTER_ADDRESS(ADDR,DEPTH) \
823 rtx regs = stack_pointer_rtx; \
824 if (ADDR == frame_pointer_rtx) \
826 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx \
827 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
828 offset = INTVAL (XEXP (ADDR, 1)); \
829 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
830 { rtx other_reg = XEXP (ADDR, 1); \
832 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
833 else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
834 { rtx other_reg = XEXP (ADDR, 0); \
836 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
837 else if (GET_CODE (ADDR) == PLUS \
838 && GET_CODE (XEXP (ADDR, 0)) == PLUS \
839 && XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
840 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
841 { rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
842 offset = INTVAL (XEXP (ADDR, 1)); \
843 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
844 else if (GET_CODE (ADDR) == PLUS \
845 && GET_CODE (XEXP (ADDR, 0)) == PLUS \
846 && XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
847 && GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
848 { rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
849 offset = INTVAL (XEXP (ADDR, 1)); \
850 regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
853 extern char call_used_regs[]; \
854 for (regno = 16; regno < 32; regno++) \
855 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
857 for (regno = 0; regno < 16; regno++) \
858 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
861 ADDR = plus_constant (regs, offset + (DEPTH)); } }
863 /* Addressing modes, and classification of registers for them. */
865 /* #define HAVE_POST_INCREMENT */
866 /* #define HAVE_POST_DECREMENT */
868 /* #define HAVE_PRE_DECREMENT */
869 /* #define HAVE_PRE_INCREMENT */
871 /* Macros to check register numbers against specific register classes. */
873 /* These assume that REGNO is a hard or pseudo reg number.
874 They give nonzero only if REGNO is a hard reg of the suitable class
875 or a pseudo reg currently allocated to a suitable hard reg.
876 Since they use reg_renumber, they are safe only once reg_renumber
877 has been allocated, which happens in local-alloc.c. */
880 #define REGNO_OK_FOR_GREG_P(REGNO) \
881 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
882 #define REGNO_OK_FOR_FPU_P(REGNO) \
883 (((REGNO) ^ 0x10) < 16 || (unsigned) (reg_renumber[REGNO] ^ 0x10) < 16)
885 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
886 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_GREG_P(REGNO)
888 /* Now macros that check whether X is a register and also,
889 strictly, whether it is in a specified class.
891 These macros are specific to the Gmicro, and may be used only
892 in code for printing assembler insns and in conditions for
893 define_optimization. */
895 /* 1 if X is an fpu register. */
897 #define FPU_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPU_P (REGNO (X)))
899 /* I used GREG_P in the gmicro.md file. */
902 #define GREG_P(X) (REG_P (X) && REGNO_OK_FOR_GREG_P (REGNO(X)))
904 #define GREG_P(X) (REG_P (X) && ((REGNO (X) & ~0xf) != 0x10))
907 /* Maximum number of registers that can appear in a valid memory address. */
909 /* The Gmicro allows more registers in the chained addressing mode.
910 But I do not know gcc supports such an architecture. */
912 #define MAX_REGS_PER_ADDRESS 2
914 /* Recognize any constant value that is a valid address. */
916 #define CONSTANT_ADDRESS_P(X) \
917 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
918 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
919 || GET_CODE (X) == HIGH)
921 /* Nonzero if the constant value X is a legitimate general operand.
922 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
924 #define LEGITIMATE_CONSTANT_P(X) 1
926 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
927 and check its validity for a certain class.
928 We have two alternate definitions for each of them.
929 The usual definition accepts all pseudo regs; the other rejects
930 them unless they have been allocated suitable hard regs.
931 The symbol REG_OK_STRICT causes the latter definition to be used.
933 Most source files want to accept pseudo regs in the hope that
934 they will get allocated to the class that the insn wants them to be in.
935 Source files for reload pass need to be strict.
936 After reload, it makes no difference, since pseudo regs have
937 been eliminated by then. */
939 #ifndef REG_OK_STRICT
941 /* Nonzero if X is a hard reg that can be used as an index
942 or if it is a pseudo reg. */
943 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) & ~0xf) != 0x10)
944 /* Nonzero if X is a hard reg that can be used as a base reg
945 or if it is a pseudo reg. */
946 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~0xf) != 0x10)
950 /* Nonzero if X is a hard reg that can be used as an index. */
951 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
952 /* Nonzero if X is a hard reg that can be used as a base reg. */
953 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
957 /* The gcc uses the following effective address of the Gmicro.
958 (without using PC!!).
959 {@} ( {Rbase} + {Disp} + {Rindex * [1,2,4,8]} )
961 @: memory indirection.
962 Rbase: Base Register = General Register.
963 Disp: Displacement (up to 32bits)
964 Rindex: Index Register = General Register.
965 [1,2,4,8]: Scale of Index. 1 or 2 or 4 or 8.
966 The inside of { } can be omitted.
967 This restricts the chained addressing up to 1 stage. */
971 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
972 that is a valid memory address for an instruction.
973 The MODE argument is the machine mode for the MEM expression
974 that wants to use this address.
976 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
977 except for CONSTANT_ADDRESS_P which is actually machine-independent. */
979 #define REG_CODE_BASE_P(X) \
980 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
982 #define REG_CODE_INDEX_P(X) \
983 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
985 /* GET_CODE(X) must be PLUS. This macro does not check for PLUS! */
986 #define BASE_PLUS_DISP_P(X) \
987 ( REG_CODE_BASE_P (XEXP (X, 0)) \
988 && CONSTANT_ADDRESS_P (XEXP (X, 1)) \
990 REG_CODE_BASE_P (XEXP (X, 1)) \
991 && CONSTANT_ADDRESS_P (XEXP (X, 0)) )
993 /* 1 if X is {0,Rbase} + {0,disp}. */
994 #define BASED_ADDRESS_P(X) \
995 (CONSTANT_ADDRESS_P (X) \
996 || REG_CODE_BASE_P (X) \
997 || (GET_CODE (X) == PLUS) \
998 && BASE_PLUS_DISP_P (X))
1000 /* 1 if X is 1 or 2 or 4 or 8. GET_CODE(X) must be CONST_INT. */
1001 #define SCALE_OF_INDEX_P(X) \
1007 /* #define INDEX_TERM_P(X,MODE) */
1008 #define INDEX_TERM_P(X) \
1009 ( REG_CODE_INDEX_P(X) \
1010 || (GET_CODE (X) == MULT \
1011 && ( (xfoo0 = XEXP (X, 0)), (xfoo1 = XEXP(X, 1)), \
1012 ( ( (GET_CODE (xfoo0) == CONST_INT) \
1013 && SCALE_OF_INDEX_P (xfoo0) \
1014 && REG_CODE_INDEX_P (xfoo1) ) \
1016 ( (GET_CODE (xfoo1) == CONST_INT) \
1017 && SCALE_OF_INDEX_P (xfoo1) \
1018 && REG_CODE_INDEX_P (xfoo0) ) ))))
1020 /* Assumes there are no cases such that X = (Ireg + Disp) + Disp */
1021 #define BASE_DISP_INDEX_P(X) \
1022 ( BASED_ADDRESS_P (X) \
1023 || ( (GET_CODE (X) == PLUS) \
1024 && ( ( (xboo0 = XEXP (X, 0)), (xboo1 = XEXP (X, 1)), \
1025 (REG_CODE_BASE_P (xboo0) \
1026 && (GET_CODE (xboo1) == PLUS) \
1027 && ( ( CONSTANT_ADDRESS_P (XEXP (xboo1, 0)) \
1028 && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1029 || ( CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) \
1030 && INDEX_TERM_P (XEXP (xboo1, 0))) ))) \
1032 (CONSTANT_ADDRESS_P (xboo0) \
1033 && (GET_CODE (xboo1) == PLUS) \
1034 && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1035 && INDEX_TERM_P (XEXP (xboo1, 1)) ) \
1036 || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1037 && INDEX_TERM_P (XEXP (xboo1, 0))) )) \
1039 (INDEX_TERM_P (xboo0) \
1040 && ( ( (GET_CODE (xboo1) == PLUS) \
1041 && ( ( REG_CODE_BASE_P (XEXP (xboo1, 0)) \
1042 && CONSTANT_ADDRESS_P (XEXP (xboo1, 1)) ) \
1043 || ( REG_CODE_BASE_P (XEXP (xboo1, 1)) \
1044 && CONSTANT_ADDRESS_P (XEXP (xboo1, 0))) )) \
1046 (CONSTANT_ADDRESS_P (xboo1)) \
1048 (REG_CODE_BASE_P (xboo1)) )))))
1051 If you want to allow double-indirection,
1052 you have to change the <fp-relative> => <sp-relative> conversion
1055 #ifdef REG_OK_STRICT
1056 #define DOUBLE_INDIRECTION(X,ADDR) {\
1057 if (BASE_DISP_INDEX_P (XEXP (XEXP (X, 0), 0) )) goto ADDR; \
1060 #define DOUBLE_INDIRECTION(X,ADDR) { }
1065 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) {\
1066 register rtx xboo0, xboo1, xfoo0, xfoo1; \
1067 if (GET_CODE (X) == MEM) { \
1069 if (GET_CODE (XEXP (X,0)) == MEM) { \
1070 DOUBLE_INDIRECTION(X,ADDR); \
1072 if (BASE_DISP_INDEX_P (XEXP (X, 0))) goto ADDR; \
1076 if (BASE_DISP_INDEX_P (X)) goto ADDR; \
1077 if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1078 && REG_P (XEXP (X, 0)) \
1079 && (REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM)) \
1085 /* Try machine-dependent ways of modifying an illegitimate address
1086 to be legitimate. If we find one, return the new, valid address.
1087 This macro is used in only one place: `memory_address' in explow.c.
1089 OLDX is the address as it was before break_out_memory_refs was called.
1090 In some cases it is useful to look at this to decide what needs to be done.
1092 MODE and WIN are passed so that this macro can use
1093 GO_IF_LEGITIMATE_ADDRESS.
1095 It is always safe for this macro to do nothing. It exists to recognize
1096 opportunities to optimize the output.
1098 For the Gmicro, nothing is done now. */
1100 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
1102 /* Go to LABEL if ADDR (a legitimate address expression)
1103 has an effect that depends on the machine mode it is used for.
1104 On the VAX, the predecrement and postincrement address depend thus
1105 (the amount of decrement or increment being the length of the operand)
1106 and all indexed address depend thus (because the index scale factor
1107 is the length of the operand).
1108 The Gmicro mimics the VAX now. Since ADDE is legitimate, it cannot
1109 include auto-inc/dec. */
1111 /* Unnecessary ??? */
1112 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1113 { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \
1117 /* Specify the machine mode that this machine uses
1118 for the index in the tablejump instruction. */
1119 /* #define CASE_VECTOR_MODE HImode */
1120 #define CASE_VECTOR_MODE SImode
1122 /* Define this if the tablejump instruction expects the table
1123 to contain offsets from the address of the table.
1124 Do not define this if the table should contain absolute addresses. */
1125 #define CASE_VECTOR_PC_RELATIVE
1127 /* Specify the tree operation to be used to convert reals to integers. */
1128 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1130 /* This is the kind of divide that is easiest to do in the general case. */
1131 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1133 /* Define this as 1 if `char' should by default be signed; else as 0. */
1134 #define DEFAULT_SIGNED_CHAR 1
1136 /* Max number of bytes we can move from memory to memory
1137 in one reasonably fast instruction. */
1140 /* Define this if zero-extension is slow (more than one real instruction). */
1141 /* #define SLOW_ZERO_EXTEND */
1143 /* Nonzero if access to memory by bytes is slow and undesirable. */
1144 #define SLOW_BYTE_ACCESS 0
1146 /* Define if shifts truncate the shift count
1147 which implies one can omit a sign-extension or zero-extension
1148 of a shift count. */
1149 /* #define SHIFT_COUNT_TRUNCATED */
1151 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1152 is done just by pretending it is already truncated. */
1153 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1155 /* We assume that the store-condition-codes instructions store 0 for false
1156 and some other value for true. This is the value stored for true. */
1158 /* #define STORE_FLAG_VALUE -1 */
1160 /* When a prototype says `char' or `short', really pass an `int'. */
1161 #define PROMOTE_PROTOTYPES
1163 /* Specify the machine mode that pointers have.
1164 After generation of rtl, the compiler makes no further distinction
1165 between pointers and any other objects of this machine mode. */
1166 #define Pmode SImode
1168 /* A function address in a call instruction
1169 is a byte address (for indexing purposes)
1170 so give the MEM rtx a byte's mode. */
1171 #define FUNCTION_MODE QImode
1173 /* Compute the cost of computing a constant rtl expression RTX
1174 whose rtx-code is CODE. The body of this macro is a portion
1175 of a switch statement. If the code is computed here,
1176 return it with a return statement. Otherwise, break from the switch. */
1178 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1180 if ((unsigned) INTVAL (RTX) < 8) return 0; \
1181 if ((unsigned) (INTVAL (RTX) + 0x80) < 0x100) return 1; \
1182 if ((unsigned) (INTVAL (RTX) + 0x8000) < 0x10000) return 2; \
1187 case CONST_DOUBLE: \
1190 /* Define subroutines to call to handle multiply and divide.
1191 The `*' prevents an underscore from being prepended by the compiler. */
1192 /* Use libgcc on Gmicro */
1193 /* #define UDIVSI3_LIBCALL "*udiv" */
1194 /* #define UMODSI3_LIBCALL "*urem" */
1197 /* Tell final.c how to eliminate redundant test instructions. */
1199 /* Here we define machine-dependent flags and fields in cc_status
1200 (see `conditions.h'). */
1202 /* Set if the cc value is actually in the FPU, so a floating point
1203 conditional branch must be output. */
1204 #define CC_IN_FPU 04000
1206 /* Store in cc_status the expressions
1207 that the condition codes will describe
1208 after execution of an instruction whose pattern is EXP.
1209 Do not alter them if the instruction would not alter the cc's. */
1211 /* Since Gmicro's compare instructions depend on the branch condition,
1212 all branch should be kept.
1213 More work must be done to optimize condition code !! M.Yuhara */
1215 #define NOTICE_UPDATE_CC(EXP, INSN) {CC_STATUS_INIT;}
1217 /* The skeleton of the next macro is taken from "vax.h".
1218 FPU-reg manipulation is added. M.Yuhara */
1220 #define NOTICE_UPDATE_CC(EXP, INSN) { \
1221 if (GET_CODE (EXP) == SET) { \
1222 if ( !FPU_REG_P (XEXP (EXP, 0)) \
1223 && (XEXP (EXP, 0) != cc0_rtx) \
1224 && (FPU_REG_P (XEXP (EXP, 1)) \
1225 || GET_CODE (XEXP (EXP, 1)) == FIX \
1226 || GET_CODE (XEXP (EXP, 1)) == FLOAT_TRUNCATE \
1227 || GET_CODE (XEXP (EXP, 1)) == FLOAT_EXTEND)) { \
1229 } else if (GET_CODE (SET_SRC (EXP)) == CALL) { \
1231 } else if (GET_CODE (SET_DEST (EXP)) != PC) { \
1232 cc_status.flags = 0; \
1233 cc_status.value1 = SET_DEST (EXP); \
1234 cc_status.value2 = SET_SRC (EXP); \
1236 } else if (GET_CODE (EXP) == PARALLEL \
1237 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET \
1238 && GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) != PC) {\
1239 cc_status.flags = 0; \
1240 cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \
1241 cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \
1242 /* PARALLELs whose first element sets the PC are aob, sob VAX insns. \
1243 They do change the cc's. So drop through and forget the cc's. * / \
1244 } else CC_STATUS_INIT; \
1245 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
1246 && cc_status.value2 \
1247 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
1248 cc_status.value2 = 0; \
1249 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM \
1250 && cc_status.value2 \
1251 && GET_CODE (cc_status.value2) == MEM) \
1252 cc_status.value2 = 0; \
1253 if ( (cc_status.value1 && FPU_REG_P (cc_status.value1)) \
1254 || (cc_status.value2 && FPU_REG_P (cc_status.value2))) \
1255 cc_status.flags = CC_IN_FPU; \
1259 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1260 { if (cc_prev_status.flags & CC_IN_FPU) \
1262 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1266 /* Control the assembler format that we output. */
1268 /* Output before read-only data. */
1270 #define TEXT_SECTION_ASM_OP ".section text,code,align=4"
1272 /* Output before writable data. */
1274 #define DATA_SECTION_ASM_OP ".section data,data,align=4"
1276 /* Output before uninitialized data. */
1278 #define BSS_SECTION_ASM_OP ".section bss,data,align=4"
1280 #define EXTRA_SECTIONS in_bss
1282 #define EXTRA_SECTION_FUNCTIONS \
1286 if (in_section != in_bss) { \
1287 fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \
1288 in_section = in_bss; \
1292 /* Output at beginning of assembler file.
1293 It is not appropriate for this to print a list of the options used,
1294 since that's not the convention that we use. */
1296 #define ASM_FILE_START(FILE)
1298 /* Output at the end of assembler file. */
1300 #define ASM_FILE_END(FILE) fprintf (FILE, "\t.end\n");
1303 /* Don't try to define `gcc_compiled.' since the assembler do not
1304 accept symbols with periods and GDB doesn't run on this machine anyway. */
1305 #define ASM_IDENTIFY_GCC(FILE)
1308 /* Output to assembler file text saying following lines
1309 may contain character constants, extra white space, comments, etc. */
1311 #define ASM_APP_ON ""
1312 /* #define ASM_APP_ON "#APP\n" */
1314 /* Output to assembler file text saying following lines
1315 no longer contain unusual constructs. */
1317 #define ASM_APP_OFF ""
1318 /* #define ASM_APP_OFF ";#NO_APP\n" */
1320 /* How to refer to registers in assembler output.
1321 This sequence is indexed by compiler's hard-register-number (see above). */
1323 #define REGISTER_NAMES \
1324 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1325 "r8", "r9", "r10", "r11", "r12", "r13", "fp", "sp", \
1326 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1327 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15"}
1329 /* How to renumber registers for dbx and gdb. */
1331 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1333 /* Define this if gcc should produce debugging output for dbx in response
1334 to the -g flag. This does not work for the Gmicro now */
1336 #define DBX_DEBUGGING_INFO
1338 /* This is how to output the definition of a user-level label named NAME,
1339 such as the label on a static function or variable NAME. */
1341 #define ASM_OUTPUT_LABEL(FILE,NAME) { \
1342 assemble_name (FILE, NAME); \
1343 fputs (":\n", FILE); \
1346 /* This is how to output a command to make the user-level label named NAME
1347 defined for reference from other files. */
1349 #define ASM_GLOBALIZE_LABEL(FILE,NAME) {\
1350 fputs ("\t.global ", FILE); \
1351 assemble_name (FILE, NAME); \
1352 fputs ("\n", FILE); \
1355 /* This is how to output a command to make the external label named NAME
1356 which are not defined in the file to be referable */
1357 /* ".import" does not work ??? */
1359 #define ASM_OUTPUT_EXTERNAL(FILE,DECL,NAME) { \
1360 fputs ("\t.global ", FILE); \
1361 assemble_name (FILE, NAME); \
1362 fputs ("\n", FILE); \
1366 /* This is how to output a reference to a user-level label named NAME.
1367 `assemble_name' uses this. */
1369 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1370 fprintf (FILE, "_%s", NAME)
1372 /* This is how to output an internal numbered label where
1373 PREFIX is the class of label and NUM is the number within the class. */
1375 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1376 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1378 /* This is how to store into the string LABEL
1379 the symbol_ref name of an internal numbered label where
1380 PREFIX is the class of label and NUM is the number within the class.
1381 This is suitable for output with `assemble_name'. */
1383 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1384 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1386 /* This is how to output an assembler line defining a `double' constant. */
1388 /* do {...} while(0) is necessary, because these macros are used as
1389 if (xxx) MACRO; else ....
1394 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1395 do { union { double d; long l[2];} tem; \
1397 fprintf (FILE, "\t.fdata.d h'%x%08x.d\n", tem.l[0], tem.l[1]); \
1401 /* This is how to output an assembler line defining a `float' constant. */
1403 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1404 do { union { float f; long l;} tem; \
1406 fprintf (FILE, "\t.fdata.s h'%x.s\n", tem.l); \
1409 /* This is how to output an assembler line defining an `int' constant. */
1411 #define ASM_OUTPUT_INT(FILE,VALUE) \
1412 ( fprintf (FILE, "\t.data.w "), \
1413 output_addr_const (FILE, (VALUE)), \
1414 fprintf (FILE, "\n"))
1416 /* Likewise for `char' and `short' constants. */
1418 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1419 ( fprintf (FILE, "\t.data.h "), \
1420 output_addr_const (FILE, (VALUE)), \
1421 fprintf (FILE, "\n"))
1423 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1424 ( fprintf (FILE, "\t.data.b "), \
1425 output_addr_const (FILE, (VALUE)), \
1426 fprintf (FILE, "\n"))
1428 /* This is how to output an assembler line for a numeric constant byte. */
1430 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1431 fprintf (FILE, "\t.data.b h'%x\n", (VALUE))
1433 #define ASM_OUTPUT_ASCII(FILE,P,SIZE) \
1434 output_ascii ((FILE), (P), (SIZE))
1436 /* This is how to output an insn to push a register on the stack.
1437 It need not be very fast code. */
1439 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1440 fprintf (FILE, "\tmov %s,@-sp\n", reg_names[REGNO])
1442 /* This is how to output an insn to pop a register from the stack.
1443 It need not be very fast code. */
1445 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1446 fprintf (FILE, "\tmov @sp+,%s\n", reg_names[REGNO])
1448 /* This is how to output an element of a case-vector that is absolute.
1449 (The Gmicro does not use such vectors,
1450 but we must define this macro anyway.) */
1452 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1453 fprintf (FILE, "\t.data.w L%d\n", VALUE)
1456 /* This is how to output an element of a case-vector that is relative. */
1458 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1459 fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL)
1462 /* This is how to output an assembler line
1463 that says to advance the location counter
1464 to a multiple of 2**LOG bytes. */
1466 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1467 fprintf (FILE, "\t.align %d\n", (1 << (LOG)));
1469 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1470 fprintf (FILE, "\t.res.b %d\n", (SIZE))
1472 /* This says how to output an assembler line
1473 to define a global common symbol. */
1475 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1477 assemble_name ((FILE), (NAME)), \
1478 fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)),\
1479 fprintf ((FILE), "\t.export "), \
1480 assemble_name ((FILE), (NAME)), \
1481 fprintf ((FILE), "\n") )
1483 /* This says how to output an assembler line
1484 to define a local common symbol. */
1486 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1488 assemble_name ((FILE), (NAME)), \
1489 fprintf ((FILE), ":\t.res.b %d\n", (ROUNDED)))
1491 /* Store in OUTPUT a string (made with alloca) containing
1492 an assembler-name for a local static variable named NAME.
1493 LABELNO is an integer which is different for each call. */
1495 /* $__ is unique ????? M.Yuhara */
1496 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1497 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \
1498 sprintf ((OUTPUT), "$__%s%d", (NAME), (LABELNO)))
1500 /* Define the parentheses used to group arithmetic operations
1501 in assembler code. */
1503 #define ASM_OPEN_PAREN "("
1504 #define ASM_CLOSE_PAREN ")"
1506 /* Define results of standard character escape sequences. */
1507 #define TARGET_BELL 007
1508 #define TARGET_BS 010
1509 #define TARGET_TAB 011
1510 #define TARGET_NEWLINE 012
1511 #define TARGET_VT 013
1512 #define TARGET_FF 014
1513 #define TARGET_CR 015
1515 /* Output a float value (represented as a C double) as an immediate operand.
1516 This macro is a Gmicro/68k-specific macro. */
1518 #define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE) \
1519 do { union { float f; long l;} tem; \
1521 fprintf (FILE, "#h'%x.s", tem.l); \
1525 /* Output a double value (represented as a C double) as an immediate operand.
1526 This macro is a 68k-specific macro. */
1527 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1528 do { union { double d; long l[2];} tem; \
1530 fprintf (FILE, "#h'%x%08x.d", tem.l[0], tem.l[1]); \
1533 /* Print operand X (an rtx) in assembler syntax to file FILE.
1534 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1535 For `%' followed by punctuation, CODE is the punctuation and X is null.
1537 On the Gmicro, we use several CODE characters:
1538 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1539 'b' for branch target label.
1540 '-' for an operand pushing on the stack.
1541 '+' for an operand pushing on the stack.
1542 '#' for an immediate operand prefix
1545 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1546 ( (CODE) == '#' || (CODE) == '-' \
1547 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!')
1550 #define PRINT_OPERAND(FILE, X, CODE) \
1552 static char *reg_name[] = REGISTER_NAMES; \
1553 /* fprintf (stderr, "PRINT_OPERAND CODE=%c(0x%x), ", CODE, CODE);\
1554 myprcode(GET_CODE(X)); */ \
1555 if (CODE == '#') fprintf (FILE, "#"); \
1556 else if (CODE == '-') fprintf (FILE, "@-sp"); \
1557 else if (CODE == '+') fprintf (FILE, "@sp+"); \
1558 else if (CODE == 's') fprintf (stderr, "err: PRINT_OPERAND <s>\n"); \
1559 else if (CODE == '!') fprintf (stderr, "err: PRINT_OPERAND <!>\n"); \
1560 else if (CODE == '.') fprintf (stderr, "err: PRINT_OPERAND <.>\n"); \
1561 else if (CODE == 'b') { \
1562 if (GET_CODE (X) == MEM) \
1563 output_addr_const (FILE, XEXP (X, 0)); /* for bsr */ \
1565 output_addr_const (FILE, X); /* for bcc */ \
1567 else if (CODE == 'p') \
1568 print_operand_address (FILE, X); \
1569 else if (GET_CODE (X) == REG) \
1570 fprintf (FILE, "%s", reg_name[REGNO (X)]); \
1571 else if (GET_CODE (X) == MEM) \
1572 output_address (XEXP (X, 0)); \
1573 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == SFmode) \
1574 { union { double d; int i[2]; } u; \
1575 union { float f; int i; } u1; \
1576 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1579 ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); \
1581 fprintf (FILE, "#h'%x", u1.i); } \
1582 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == DFmode) \
1583 { union { double d; int i[2]; } u; \
1584 u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X); \
1585 ASM_OUTPUT_DOUBLE_OPERAND (FILE, u.d); } \
1586 else { putc ('#', FILE); \
1587 output_addr_const (FILE, X); }}
1589 /* Note that this contains a kludge that knows that the only reason
1590 we have an address (plus (label_ref...) (reg...))
1591 is in the insn before a tablejump, and we know that m68k.md
1592 generates a label LInnn: on such an insn. */
1593 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1594 { print_operand_address (FILE, ADDR); }