1 ;;- Machine description for the AT&T DSP1600 for GNU C compiler
2 ;; Copyright (C)
1994,
1995,
1997,
1998,
2001,
2002
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Michael Collison (collison@isisinc.net).
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version
2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
21 ;; Boston, MA
02111-
1307, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; Attribute specifications
28 ; Type of each instruction. Default is arithmetic.
29 ; I'd like to write the list as this, but genattrtab won't accept it.
31 ; "jump,cond_jump,call, ; flow-control instructions
32 ; load_i,load, store, move ; Y space address arithmetic instructions
33 ; malu,special,f3_alu,f3_alu_i ; data arithmetic unit instructions
34 ; shift_i,shift, bfield_i, bfield ; bit manipulation unit instructions
35 ; arith, ; integer unit instructions
38 ; Classification of each insn. Some insns of TYPE_BRANCH are multi-word.
40 "jump,cond_jump,call,load_i,load,move,store,malu,malu_mul,tstqi,special,special_2,f3_alu,f3_alu_i,f3_alu_i_mult,shift_i,shift,shift_multiple,shift_i_multiple,bfield_i,bfield,nop,ld_short_i,data_move,data_move_i,data_move_memory,data_move_memory_2,data_move_short_i,data_move_multiple,data_move_2,nothing"
41 (const_string "malu"))
43 ;; Data arithmetic unit
44 (define_function_unit "dau"
1 1 (eq_attr "type" "data_move,data_move_i,f3_alu_i")
2 0)
46 (define_function_unit "dau"
1 1 (eq_attr "type" "special_2")
3 0)
48 (define_function_unit "dau"
1 1 (eq_attr "type" "data_move_2")
4 0)
51 (define_function_unit "bmu"
1 1 (eq_attr "type" "shift_i,shift_i_multiple")
2 0)
53 (define_function_unit "bmu"
1 1 (eq_attr "type" "shift_multiple")
4 0)
55 ;; Y-memory addressing arithmetic unit
56 (define_function_unit "yaau"
1 1 (eq_attr "type" "data_move_memory")
2 0)
58 (define_function_unit "yaau"
1 1 (eq_attr "type" "data_move_memory_2")
4 0)
61 ;; ....................
63 ;; Test against
0 instructions
65 ;; ....................
67 (define_expand "tsthi"
69 (match_operand:HI
0 "register_operand" ""))]
73 dsp16xx_compare_gen = gen_tst_reg;
74 dsp16xx_compare_op0 = operands[
0];
75 dsp16xx_compare_op1 = const0_rtx;
79 (define_insn "tsthi_1"
81 (match_operand:HI
0 "register_operand" "A"))]
84 [(set_attr "type" "malu")])
86 (define_expand "tstqi"
88 (match_operand:QI
0 "register_operand" ""))]
92 dsp16xx_compare_gen = gen_tst_reg;
93 dsp16xx_compare_op0 = operands[
0];
94 dsp16xx_compare_op1 = const0_rtx;
100 (match_operand:QI
0 "register_operand" "j,q"))
101 (clobber (match_scratch:QI
1 "=k,u"))]
105 (parallel [(set (cc0)
107 (use (match_dup
1))])]
110 (define_insn "tstqi_split"
112 (match_operand:QI
0 "register_operand" "j,q"))
113 (use (match_scratch:QI
1 "=k,u"))]
118 [(set_attr "type" "f3_alu_i,f3_alu_i")])
120 (define_insn "tstqi_1"
122 (match_operand:QI
0 "register_operand" "j,q"))
123 (clobber (match_scratch:QI
1 "=k,u"))]
128 [(set_attr "type" "tstqi,tstqi")])
132 ;; ....................
134 ;; Bit test instructions
136 ;; ....................
140 (and:HI (match_operand:HI
0 "register_operand" "A,!A")
141 (match_operand:HI
1 "register_operand" "Z,A")))]
145 switch (which_alternative)
154 [(set_attr "type" "f3_alu,f3_alu")])
159 ;; (and:QI (match_operand:QI
0 "register_operand" "h")
160 ;; (match_operand:QI
1 "const_int_operand" "I")))]
163 ;; [(set_attr "type" "f3_alu_i")])
167 ;; Compare Instructions
170 (define_expand "cmphi"
171 [(parallel [(set (cc0)
172 (compare (match_operand:HI
0 "general_operand" "")
173 (match_operand:HI
1 "general_operand" "")))
174 (clobber (match_scratch:QI
2 ""))
175 (clobber (match_scratch:QI
3 ""))
176 (clobber (match_scratch:QI
4 ""))
177 (clobber (match_scratch:QI
5 ""))])]
181 if (GET_CODE (operands[
1]) == CONST_INT)
182 operands[
1] = force_reg (HImode, operands[
1]);
184 dsp16xx_compare_gen = gen_compare_reg;
185 dsp16xx_compare_op0 = operands[
0];
186 dsp16xx_compare_op1 = operands[
1];
192 (compare (match_operand:HI
0 "general_operand" "Z*r*m*i")
193 (match_operand:HI
1 "general_operand" "Z*r*m*i")))
194 (clobber (match_scratch:QI
2 "=&A"))
195 (clobber (match_scratch:QI
3 "=&A"))
196 (clobber (match_scratch:QI
4 "=&A"))
197 (clobber (match_scratch:QI
5 "=&A"))]
198 "next_cc_user_unsigned (insn)"
201 if (GET_CODE(operands[
0]) == REG)
203 if (REGNO (operands[
0]) == REG_Y ||
204 REGNO (operands[
0]) == REG_PROD)
206 output_asm_insn (
\"a0=%
0\", operands);
208 else if (IS_YBASE_REGISTER_WINDOW (REGNO (operands[
0])))
209 output_asm_insn (
\"a0=%u0\;a0l=%w0
\", operands);
211 fatal_error (
\"Invalid register for compare
\");
213 else if (GET_CODE(operands[
0]) == CONST_INT)
214 output_asm_insn (
\"a0=%U0\;a0l=%H0
\", operands);
215 else if (GET_CODE (operands[
0]) == MEM)
219 xoperands[
0] = gen_rtx_REG (HImode, REG_A0);
220 xoperands[
1] = operands[
0];
221 double_reg_from_memory (xoperands);
224 if (GET_CODE(operands[
1]) == REG)
226 if (REGNO (operands[
1]) == REG_Y || REGNO (operands[
1]) == REG_PROD)
227 output_asm_insn (
\"a1=%
1\", operands);
228 else if (IS_YBASE_REGISTER_WINDOW (REGNO (operands[
1])))
229 output_asm_insn (
\"a1=%u1\;a1l=%w1
\", operands);
231 fatal_error (
\"Invalid register for compare
\");
233 else if (GET_CODE (operands[
1]) == MEM)
237 xoperands[
0] = gen_rtx_REG (HImode, REG_A1);
238 xoperands[
1] = operands[
1];
239 double_reg_from_memory (xoperands);
241 else if (GET_CODE(operands[
1]) == CONST_INT)
243 output_asm_insn (
\"a1=%U1\;a1l=%H1
\", operands);
246 return
\"psw =
0\;a0 - a1
\";
250 [(set (cc0) (compare (match_operand:HI
0 "register_operand" "A,!A")
251 (match_operand:HI
1 "register_operand" "Z,*A")))]
256 [(set_attr "type" "malu,f3_alu")])
258 (define_expand "cmpqi"
259 [(parallel [(set (cc0)
260 (compare (match_operand:QI
0 "register_operand" "")
261 (match_operand:QI
1 "nonmemory_operand" "")))
262 (clobber (match_operand:QI
2 "register_operand" ""))
263 (clobber (match_operand:QI
3 "register_operand" ""))])]
267 if (operands[
0]) /* Avoid unused code warning */
269 dsp16xx_compare_gen = gen_compare_reg;
270 dsp16xx_compare_op0 = operands[
0];
271 dsp16xx_compare_op1 = operands[
1];
278 (compare (match_operand:QI
0 "register_operand" "")
279 (match_operand:QI
1 "register_operand" "")))
280 (clobber (match_scratch:QI
2 ""))
281 (clobber (match_scratch:QI
3 ""))]
282 "reload_completed && next_cc_user_unsigned (insn)"
287 (parallel [(set (cc0)
288 (compare (match_dup
0)
291 (use (match_dup
3))])]
296 (compare (match_operand:QI
0 "register_operand" "")
297 (match_operand:QI
1 "const_int_operand" "")))
298 (clobber (match_scratch:QI
2 ""))
299 (clobber (match_scratch:QI
3 ""))]
300 "reload_completed && next_cc_user_unsigned (insn)"
303 (parallel [(set (cc0)
304 (compare (match_dup
0)
306 (use (match_dup
2))])]
309 (define_insn "cmpqi_split_unsigned_reg"
310 [(set (cc0) (compare (match_operand:QI
0 "register_operand" "k,k,!k,u,u,!u")
311 (match_operand:QI
1 "register_operand" "w,z,u,w,z,k")))
312 (use (match_scratch:QI
2 "=j,j,j,q,q,q"))
313 (use (match_scratch:QI
3 "=v,y,q,v,y,j"))]
314 "next_cc_user_unsigned (insn)"
322 [(set_attr "type" "malu,malu,malu,malu,malu,malu")])
324 (define_insn "cmpqi_split_unsigned_int"
325 [(set (cc0) (compare (match_operand:QI
0 "register_operand" "k,u")
326 (match_operand:QI
1 "const_int_operand" "i,i")))
327 (use (match_scratch:QI
2 "=j,q"))]
328 "next_cc_user_unsigned (insn)"
332 [(set_attr "type" "f3_alu_i,f3_alu_i")])
335 [(set (cc0) (compare (match_operand:QI
0 "register_operand" "k,k,!k,k,u,u,!u,u")
336 (match_operand:QI
1 "nonmemory_operand" "w,z,u,i,w,z,k,i")))
337 (clobber (match_scratch:QI
2 "=j,j,j,j,q,q,q,q"))
338 (clobber (match_scratch:QI
3 "=v,y,q,X,v,y,j,X"))]
339 "next_cc_user_unsigned (insn)"
352 (compare (match_operand:QI
0 "register_operand" "")
353 (match_operand:QI
1 "register_operand" "")))
354 (clobber (match_scratch:QI
2 ""))
355 (clobber (match_scratch:QI
3 ""))]
361 (parallel [(set (cc0)
362 (compare (match_dup
0)
365 (use (match_dup
3))])]
370 (compare (match_operand:QI
0 "register_operand" "")
371 (match_operand:QI
1 "const_int_operand" "")))
372 (clobber (match_scratch:QI
2 ""))
373 (clobber (match_scratch:QI
3 ""))]
377 (parallel [(set (cc0)
378 (compare (match_dup
0)
380 (use (match_dup
2))])]
383 (define_insn "cmpqi_split_reg"
384 [(set (cc0) (compare (match_operand:QI
0 "register_operand" "j,j,!j,q,q,!q")
385 (match_operand:QI
1 "register_operand" "v,y,q,v,y,j")))
386 (use (match_scratch:QI
2 "=k,k,k,u,u,u"))
387 (use (match_scratch:QI
3 "=w,z,u,w,z,k"))]
396 [(set_attr "type" "malu,malu,malu,malu,malu,malu")])
399 (define_insn "cmpqi_split_int"
400 [(set (cc0) (compare (match_operand:QI
0 "register_operand" "j,q")
401 (match_operand:QI
1 "const_int_operand" "i,i")))
402 (use (match_scratch:QI
2 "=k,u"))]
407 [(set_attr "type" "f3_alu_i,f3_alu_i")])
410 [(set (cc0) (compare (match_operand:QI
0 "register_operand" "j,j,!j,j,q,q,!q,q")
411 (match_operand:QI
1 "nonmemory_operand" "v,y,q,i,v,y,j,i")))
412 (clobber (match_scratch:QI
2 "=k,k,k,k,u,u,u,u"))
413 (clobber (match_scratch:QI
3 "=w,z,u,X,w,z,k,X"))]
426 (define_expand "cmphf"
428 (compare (match_operand:HF
0 "register_operand" "")
429 (match_operand:HF
1 "nonmemory_operand" "")))]
433 if (!dsp16xx_cmphf3_libcall)
434 dsp16xx_cmphf3_libcall = gen_rtx_SYMBOL_REF (Pmode, CMPHF3_LIBCALL);
436 dsp16xx_compare_gen = gen_compare_reg;
437 dsp16xx_compare_op0 = operands[
0];
438 dsp16xx_compare_op1 = operands[
1];
439 emit_library_call (dsp16xx_cmphf3_libcall,
1, HImode,
2,
441 operands[
1], HFmode);
442 emit_insn (gen_tsthi_1 (copy_to_reg(hard_libcall_value (HImode))));
447 ;; ....................
451 ;; ....................
454 [(set (match_operand:HI
0 "register_operand" "")
455 (plus:HI (match_operand:HI
1 "register_operand" "")
456 (match_operand:HI
2 "const_int_operand" "")))]
457 "reload_completed && !ADD_LOW_16(INTVAL(operands[
2])) &&
458 !ADD_HIGH_16(INTVAL(operands[
2]))"
459 [(parallel [(set (match_dup
3)
460 (plus:QI (match_dup
4)
462 (clobber (match_dup
6))])
464 (parallel [(set (match_dup
6)
465 (plus:QI (match_dup
7)
467 (clobber (match_scratch:QI
9 ""))])]
470 operands[
3] = gen_lowpart(QImode, operands[
0]);
471 operands[
4] = gen_lowpart(QImode, operands[
1]);
472 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
474 operands[
6] = gen_highpart(QImode, operands[
0]);
475 operands[
7] = gen_highpart(QImode, operands[
0]);
476 operands[
8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
480 (define_insn "addhi3"
481 [(set (match_operand:HI
0 "register_operand" "=A,A,A,A,A")
482 (plus:HI (match_operand:HI
1 "register_operand" "%A,A,A,A,A")
483 (match_operand:HI
2 "nonmemory_operand" "Z,d,L,M,?i")))]
490 %
0=%w1+%H2\;%
0=%b0+%U2"
491 [(set_attr "type" "malu,malu,f3_alu_i,f3_alu_i,f3_alu_i")])
494 [(set (match_operand:QI
0 "register_operand" "=k,u,!k,!u")
495 (plus:QI (plus:QI (match_operand:QI
1 "register_operand" "uk,uk,uk,uk")
496 (match_operand:QI
2 "register_operand" "wz,wz,uk,uk"))
497 (match_operand:QI
3 "immediate_operand" "i,i,i,i")))
498 (clobber (match_scratch:QI
4 "=j,q,j,q"))]
501 %m0=%m1+%m2\;%m0=%
0+%H3
502 %m0=%m1+%m2\;%m0=%
0+%H3
503 %m0=%m1+%m2\;%m0=%
0+%H3
504 %m0=%m1+%m2\;%m0=%
0+%H3")
506 (define_expand "addqi3"
507 [(parallel [(set (match_operand:QI
0 "register_operand" "")
508 (plus:QI (match_operand:QI
1 "register_operand" "")
509 (match_operand:QI
2 "nonmemory_operand" "")))
510 (clobber (match_scratch:QI
3 ""))])]
514 if (reload_in_progress)
516 if (REG_P (operands[
1]) &&
517 (REGNO(operands[
1]) == STACK_POINTER_REGNUM ||
518 REGNO(operands[
1]) == FRAME_POINTER_REGNUM) &&
519 GET_CODE (operands[
2]) == CONST_INT)
521 if (REG_P (operands[
0]) && IS_ACCUM_REG(REGNO(operands[
0])))
522 emit_move_insn (operands[
0], operands[
1]);
524 operands[
1] = operands[
0];
530 (define_insn "match_addqi3"
531 [(set (match_operand:QI
0 "register_operand" "=a,a,k,u,k,u,!k,!u,j,j,q,q")
532 (plus:QI (match_operand:QI
1 "register_operand" "
0,
0,uk,uk,uk,uk,uk,uk,
0,q,
0,j")
533 (match_operand:QI
2 "nonmemory_operand" "W,N,i,i,wz,wz,uk,uk,i,i,i,i")))
534 (clobber (match_scratch:QI
3 "=X,X,j,q,j,q,j,q,X,k,X,u"))]
538 switch (which_alternative)
544 switch (INTVAL (operands[
2]))
553 return
\"*%
0--\;*%
0--
\";
556 return
\"*%
0++\;*%
0++
\";
563 return
\"%m0=%
1+%H2
\";
567 return
\"%m0=%m1+%m2
\";
572 return
\"%m0=%m1+%m2
\";
578 return
\"%
0=%b1+%H2
\";
583 [(set_attr "type" "data_move_memory,data_move_multiple,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i")])
586 (define_expand "addhf3"
587 [(set (match_operand:HF
0 "register_operand" "")
588 (plus:HF (match_operand:HF
1 "register_operand" "")
589 (match_operand:HF
2 "nonmemory_operand" "")))]
593 if (!dsp16xx_addhf3_libcall)
594 dsp16xx_addhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, ADDHF3_LIBCALL);
596 emit_library_call (dsp16xx_addhf3_libcall,
1, HFmode,
2,
598 operands[
2], HFmode);
599 emit_move_insn (operands[
0], hard_libcall_value(HFmode));
605 ;; ....................
607 ;; Subtract instructions
609 ;; ....................
612 [(set (match_operand:HI
0 "register_operand" "")
613 (minus:HI (match_operand:HI
1 "register_operand" "")
614 (match_operand:HI
2 "const_int_operand" "")))]
615 "reload_completed && !ADD_LOW_16(INTVAL(operands[
2])) &&
616 !ADD_HIGH_16(INTVAL(operands[
2]))"
617 [(parallel [(set (match_dup
3)
618 (minus:QI (match_dup
4)
620 (clobber (match_dup
6))])
622 (parallel [(set (match_dup
6)
623 (minus:QI (match_dup
7)
625 (clobber (match_scratch:QI
9 ""))])]
628 operands[
3] = gen_lowpart(QImode, operands[
0]);
629 operands[
4] = gen_lowpart(QImode, operands[
1]);
630 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
632 operands[
6] = gen_highpart(QImode, operands[
0]);
633 operands[
7] = gen_highpart(QImode, operands[
0]);
634 operands[
8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
638 (define_insn "subhi3"
639 [(set (match_operand:HI
0 "register_operand" "=A,A,A,A,A")
640 (minus:HI (match_operand:HI
1 "register_operand" "A,A,A,A,A")
641 (match_operand:HI
2 "nonmemory_operand" "Z,d,L,M,?i")))]
648 %
0=%w1-%H2\;%
0=%b0-%U2"
649 [(set_attr "type" "malu,malu,f3_alu_i,f3_alu_i,f3_alu_i")])
651 (define_insn "subqi3"
652 [(set (match_operand:QI
0 "register_operand" "=a,k,u,k,u,!k,!u,j,j,q,q")
653 (minus:QI (match_operand:QI
1 "register_operand" "
0,uk,uk,uk,uk,uk,uk,
0,q,
0,j")
654 (match_operand:QI
2 "nonmemory_operand" "N,i,i,wz,wz,uk,uk,i,i,i,i")))
655 (clobber (match_scratch:QI
3 "=X,j,q,j,q,j,q,X,k,X,u"))]
659 switch (which_alternative)
662 switch (INTVAL (operands[
2]))
671 operands[
2] = GEN_INT (-INTVAL (operands[
2]));
673 if (SHORT_IMMEDIATE(operands[
2]))
674 return
\"set %
3=%H2\;*%
0++%
3\";
676 return
\"%
3=%H2\;*%
0++%
3\";
681 return
\"%m0=%
1-%H2
\";
685 return
\"%m0=%m1-%m2
\";
689 return
\"%m0=%m1-%m2
\";
693 return
\"%
0=%b1-%H2
\";
698 [(set_attr "type" "data_move_multiple,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i")])
700 (define_expand "subhf3"
701 [(set (match_operand:HF
0 "register_operand" "")
702 (minus:HF (match_operand:HF
1 "register_operand" "")
703 (match_operand:HF
2 "nonmemory_operand" "")))]
707 if (!dsp16xx_subhf3_libcall)
708 dsp16xx_subhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, SUBHF3_LIBCALL);
710 emit_library_call (dsp16xx_subhf3_libcall,
1, HFmode,
2,
712 operands[
2], HFmode);
713 emit_move_insn (operands[
0], hard_libcall_value(HFmode));
717 (define_insn "neghi2"
718 [(set (match_operand:HI
0 "register_operand" "=A")
719 (neg:HI (match_operand:HI
1 "register_operand" "A")))]
722 [(set_attr "type" "special")])
724 (define_expand "neghf2"
725 [(set (match_operand:HF
0 "register_operand" "")
726 (neg:HF (match_operand:HF
1 "register_operand" "")))]
734 target = gen_lowpart(HImode, operands[
0]);
735 result = expand_binop (HImode, xor_optab,
736 gen_lowpart(HImode, operands[
1]),
737 GEN_INT(
0x80000000), target,
0, OPTAB_WIDEN);
741 if (result != target)
742 emit_move_insn (result, target);
744 /* Make a place for REG_EQUAL. */
745 emit_move_insn (operands[
0], operands[
0]);
751 ;; ....................
753 ;; Multiply instructions
756 (define_expand "mulhi3"
757 [(set (match_operand:HI
0 "register_operand" "")
758 (mult:HI (match_operand:HI
1 "register_operand" "")
759 (match_operand:HI
2 "nonmemory_operand" "")))]
763 if (!dsp16xx_mulhi3_libcall)
764 dsp16xx_mulhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MULHI3_LIBCALL);
766 emit_library_call (dsp16xx_mulhi3_libcall,
1, HImode,
2,
768 operands[
2], HImode);
769 emit_move_insn (operands[
0], hard_libcall_value(HImode));
773 (define_insn "mulqi3"
774 [(set (match_operand:QI
0 "register_operand" "=w")
775 (mult:QI (match_operand:QI
1 "register_operand" "%x")
776 (match_operand:QI
2 "register_operand" "y")))
777 (clobber (match_scratch:QI
3 "=v"))]
780 [(set_attr "type" "malu_mul")])
782 (define_insn "mulqihi3"
783 [(set (match_operand:HI
0 "register_operand" "=t")
784 (mult:HI (sign_extend:HI (match_operand:QI
1 "register_operand" "%x"))
785 (sign_extend:HI (match_operand:QI
2 "register_operand" "y"))))]
788 [(set_attr "type" "malu_mul")])
790 (define_expand "mulhf3"
791 [(set (match_operand:HF
0 "register_operand" "")
792 (mult:HF (match_operand:HF
1 "register_operand" "")
793 (match_operand:HF
2 "nonmemory_operand" "")))]
797 if (!dsp16xx_mulhf3_libcall)
798 dsp16xx_mulhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, MULHF3_LIBCALL);
800 emit_library_call (dsp16xx_mulhf3_libcall,
1, HFmode,
2,
802 operands[
2], HFmode);
803 emit_move_insn (operands[
0], hard_libcall_value(HFmode));
810 ;; *******************
812 ;; Divide Instructions
815 (define_expand "divhi3"
816 [(set (match_operand:HI
0 "register_operand" "")
817 (div:HI (match_operand:HI
1 "register_operand" "")
818 (match_operand:HI
2 "nonmemory_operand" "")))]
822 if (!dsp16xx_divhi3_libcall)
823 dsp16xx_divhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVHI3_LIBCALL);
825 emit_library_call (dsp16xx_divhi3_libcall,
1, HImode,
2,
827 operands[
2], HImode);
828 emit_move_insn (operands[
0], hard_libcall_value(HImode));
832 (define_expand "udivhi3"
833 [(set (match_operand:HI
0 "register_operand" "")
834 (udiv:HI (match_operand:HI
1 "register_operand" "")
835 (match_operand:HI
2 "nonmemory_operand" "")))]
839 if (!dsp16xx_udivhi3_libcall)
840 dsp16xx_udivhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UDIVHI3_LIBCALL);
842 emit_library_call (dsp16xx_udivhi3_libcall,
1, HImode,
2,
844 operands[
2], HImode);
845 emit_move_insn (operands[
0], hard_libcall_value(HImode));
849 (define_expand "divqi3"
850 [(set (match_operand:QI
0 "register_operand" "")
851 (div:QI (match_operand:QI
1 "register_operand" "")
852 (match_operand:QI
2 "nonmemory_operand" "")))]
856 if (!dsp16xx_divqi3_libcall)
857 dsp16xx_divqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVQI3_LIBCALL);
859 emit_library_call (dsp16xx_divqi3_libcall,
1, QImode,
2,
861 operands[
2], QImode);
862 emit_move_insn (operands[
0], hard_libcall_value(QImode));
866 (define_expand "udivqi3"
867 [(set (match_operand:QI
0 "register_operand" "")
868 (udiv:QI (match_operand:QI
1 "register_operand" "")
869 (match_operand:QI
2 "nonmemory_operand" "")))]
873 if (!dsp16xx_udivqi3_libcall)
874 dsp16xx_udivqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UDIVQI3_LIBCALL);
876 emit_library_call (dsp16xx_udivqi3_libcall,
1, QImode,
2,
878 operands[
2], QImode);
879 emit_move_insn (operands[
0], hard_libcall_value(QImode));
884 ;; ....................
886 ;; Modulo instructions
888 ;; ....................
890 (define_expand "modhi3"
891 [(set (match_operand:HI
0 "register_operand" "")
892 (mod:HI (match_operand:HI
1 "register_operand" "")
893 (match_operand:HI
2 "nonmemory_operand" "")))]
897 if (!dsp16xx_modhi3_libcall)
898 dsp16xx_modhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MODHI3_LIBCALL);
900 emit_library_call (dsp16xx_modhi3_libcall,
1, HImode,
2,
902 operands[
2], HImode);
903 emit_move_insn (operands[
0], hard_libcall_value(HImode));
907 (define_expand "umodhi3"
908 [(set (match_operand:HI
0 "register_operand" "")
909 (umod:HI (match_operand:HI
1 "register_operand" "")
910 (match_operand:HI
2 "nonmemory_operand" "")))]
914 if (!dsp16xx_umodhi3_libcall)
915 dsp16xx_umodhi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UMODHI3_LIBCALL);
917 emit_library_call (dsp16xx_umodhi3_libcall,
1, HImode,
2,
919 operands[
2], HImode);
920 emit_move_insn (operands[
0], hard_libcall_value(HImode));
924 (define_expand "modqi3"
925 [(set (match_operand:QI
0 "register_operand" "")
926 (mod:QI (match_operand:QI
1 "register_operand" "")
927 (match_operand:QI
2 "nonmemory_operand" "")))]
931 if (!dsp16xx_modqi3_libcall)
932 dsp16xx_modqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, MODQI3_LIBCALL);
934 emit_library_call (dsp16xx_modqi3_libcall,
1, QImode,
2,
936 operands[
2], QImode);
937 emit_move_insn (operands[
0], hard_libcall_value(QImode));
941 (define_expand "umodqi3"
942 [(set (match_operand:QI
0 "register_operand" "")
943 (umod:QI (match_operand:QI
1 "register_operand" "")
944 (match_operand:QI
2 "nonmemory_operand" "")))]
948 if (!dsp16xx_umodqi3_libcall)
949 dsp16xx_umodqi3_libcall = gen_rtx_SYMBOL_REF (Pmode, UMODQI3_LIBCALL);
951 emit_library_call (dsp16xx_umodqi3_libcall,
1, QImode,
2,
953 operands[
2], QImode);
954 emit_move_insn (operands[
0], hard_libcall_value(QImode));
958 (define_expand "divhf3"
959 [(set (match_operand:HF
0 "register_operand" "")
960 (div:HF (match_operand:HF
1 "register_operand" "")
961 (match_operand:HF
2 "nonmemory_operand" "")))]
965 if (!dsp16xx_divhf3_libcall)
966 dsp16xx_divhf3_libcall = gen_rtx_SYMBOL_REF (Pmode, DIVHF3_LIBCALL);
968 emit_library_call (dsp16xx_divhf3_libcall,
1, HFmode,
2,
970 operands[
2], HFmode);
971 emit_move_insn (operands[
0], hard_libcall_value(HFmode));
978 ;; ********************
980 ;; Logical Instructions
984 [(set (match_operand:HI
0 "register_operand" "")
985 (and:HI (match_operand:HI
1 "register_operand" "")
986 (match_operand:HI
2 "const_int_operand" "")))]
987 "reload_completed && !AND_LOW_16(INTVAL(operands[
2])) &&
988 !AND_HIGH_16(INTVAL(operands[
2]))
989 && (REGNO (operands[
0]) == REGNO (operands[
1]))"
990 [(parallel [(set (match_dup
3)
991 (and:QI (match_dup
4)
993 (clobber (match_scratch:QI
6 ""))])
994 (parallel [(set (match_dup
7)
995 (and:QI (match_dup
8)
997 (clobber (match_scratch:QI
10 ""))])]
1000 operands[
3] = gen_lowpart(QImode, operands[
0]);
1001 operands[
4] = gen_lowpart(QImode, operands[
1]);
1002 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1004 operands[
7] = gen_highpart(QImode, operands[
0]);
1005 operands[
8] = gen_highpart(QImode, operands[
0]);
1006 operands[
9] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
1010 [(set (match_operand:HI
0 "register_operand" "")
1011 (and:HI (match_operand:HI
1 "register_operand" "")
1012 (match_operand:HI
2 "const_int_operand" "")))]
1013 "reload_completed && !AND_LOW_16(INTVAL(operands[
2])) &&
1014 !AND_HIGH_16(INTVAL(operands[
2]))
1015 && (REGNO (operands[
0]) != REGNO (operands[
1]))"
1016 [(parallel [(set (match_dup
3)
1017 (and:QI (match_dup
4)
1019 (clobber (match_dup
6))])
1020 (parallel [(set (match_dup
6)
1021 (and:QI (match_dup
7)
1023 (clobber (match_scratch:QI
9 ""))])]
1026 operands[
3] = gen_lowpart(QImode, operands[
0]);
1027 operands[
4] = gen_lowpart(QImode, operands[
1]);
1028 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1030 operands[
6] = gen_highpart(QImode, operands[
0]);
1031 operands[
7] = gen_highpart(QImode, operands[
0]);
1032 operands[
8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
1035 (define_insn "andhi3"
1036 [(set (match_operand:HI
0 "register_operand" "=A,A,A,A,?A")
1037 (and:HI (match_operand:HI
1 "register_operand" "%A,!A,A,A,A")
1038 (match_operand:HI
2 "nonmemory_operand" "Z,A,O,P,i")))]
1045 %
0=%w1&%H2\;%
0=%b0&%U2"
1046 [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i_mult")])
1048 (define_insn "andqi3"
1049 [(set (match_operand:QI
0 "register_operand" "=k,u,!k,!u,k,u,k,u,j,q,j,q,j,q,!j,!q")
1050 (and:QI (match_operand:QI
1 "register_operand" "%uk,uk,uk,uk,
0,
0,u,k,jq,jq,
0,
0,q,j,jq,jq")
1051 (match_operand:QI
2 "nonmemory_operand" "wz,wz,uk,uk,i,i,i,i,yv,yv,i,i,i,i,jq,jq")))
1052 (clobber (match_scratch:QI
3 "=j,q,j,q,X,X,j,q,k,u,X,X,k,u,k,u"))]
1071 [(set_attr "type" "f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu")])
1075 [(set (match_operand:HI
0 "register_operand" "")
1076 (ior:HI (match_operand:HI
1 "register_operand" "")
1077 (match_operand:HI
2 "const_int_operand" "")))]
1078 "reload_completed && !SMALL_INTVAL(INTVAL(operands[
2])) &&
1079 !ADD_HIGH_16(INTVAL(operands[
2]))
1080 && (REGNO (operands[
0]) == REGNO (operands[
1]))"
1081 [(parallel [(set (match_dup
3)
1082 (ior:QI (match_dup
4)
1084 (clobber (match_scratch:QI
6 ""))])
1085 (parallel [(set (match_dup
7)
1086 (ior:QI (match_dup
8)
1088 (clobber (match_scratch:QI
10 ""))])]
1091 operands[
3] = gen_lowpart(QImode, operands[
0]);
1092 operands[
4] = gen_lowpart(QImode, operands[
1]);
1093 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1095 operands[
7] = gen_highpart(QImode, operands[
0]);
1096 operands[
8] = gen_highpart(QImode, operands[
0]);
1097 operands[
9] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
1101 [(set (match_operand:HI
0 "register_operand" "")
1102 (ior:HI (match_operand:HI
1 "register_operand" "")
1103 (match_operand:HI
2 "const_int_operand" "")))]
1104 "reload_completed && !SMALL_INTVAL(INTVAL(operands[
2])) &&
1105 !ADD_HIGH_16(INTVAL(operands[
2]))
1106 && (REGNO (operands[
0]) != REGNO (operands[
1]))"
1107 [(parallel [(set (match_dup
3)
1108 (ior:QI (match_dup
4)
1110 (clobber (match_dup
6))])
1111 (parallel [(set (match_dup
6)
1112 (ior:QI (match_dup
7)
1114 (clobber (match_scratch:QI
9 ""))])]
1117 operands[
3] = gen_lowpart(QImode, operands[
0]);
1118 operands[
4] = gen_lowpart(QImode, operands[
1]);
1119 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1121 operands[
6] = gen_highpart(QImode, operands[
0]);
1122 operands[
7] = gen_highpart(QImode, operands[
0]);
1123 operands[
8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
1127 (define_insn "iorhi3"
1128 [(set (match_operand:HI
0 "register_operand" "=A,A,A,A,?A")
1129 (ior:HI (match_operand:HI
1 "register_operand" "%A,!A,A,A,A")
1130 (match_operand:HI
2 "nonmemory_operand" "Z,A,I,M,i")))]
1137 %
0=%w1|%H2\;%
0=%b0|%U2"
1138 [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i_mult")])
1140 (define_insn "iorqi3"
1141 [(set (match_operand:QI
0 "register_operand" "=k,u,!k,!u,k,u,k,u,j,q,j,q,j,q,!j,!q")
1142 (ior:QI (match_operand:QI
1 "register_operand" "%uk,uk,uk,uk,
0,
0,u,k,jq,jq,
0,
0,q,j,jq,jq")
1143 (match_operand:QI
2 "nonmemory_operand" "wz,wz,uk,uk,i,i,i,i,yv,yv,i,i,i,i,jq,jq")))
1144 (clobber (match_scratch:QI
3 "=j,q,j,q,X,X,j,q,k,u,X,X,k,u,k,u"))]
1163 [(set_attr "type" "f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu")])
1168 [(set (match_operand:HI
0 "register_operand" "")
1169 (xor:HI (match_operand:HI
1 "register_operand" "")
1170 (match_operand:HI
2 "const_int_operand" "")))]
1171 "reload_completed && !SMALL_INTVAL(INTVAL(operands[
2])) &&
1172 !ADD_HIGH_16(INTVAL(operands[
2]))
1173 && (REGNO (operands[
0]) == REGNO (operands[
1]))"
1174 [(parallel [(set (match_dup
3)
1175 (xor:QI (match_dup
4)
1177 (clobber (match_scratch:QI
6 ""))])
1178 (parallel [(set (match_dup
7)
1179 (xor:QI (match_dup
8)
1181 (clobber (match_scratch:QI
10 ""))])]
1184 operands[
3] = gen_lowpart(QImode, operands[
0]);
1185 operands[
4] = gen_lowpart(QImode, operands[
1]);
1186 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1188 operands[
7] = gen_highpart(QImode, operands[
0]);
1189 operands[
8] = gen_highpart(QImode, operands[
0]);
1190 operands[
9] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
1194 [(set (match_operand:HI
0 "register_operand" "")
1195 (xor:HI (match_operand:HI
1 "register_operand" "")
1196 (match_operand:HI
2 "const_int_operand" "")))]
1197 "reload_completed && !SMALL_INTVAL(INTVAL(operands[
2])) &&
1198 !ADD_HIGH_16(INTVAL(operands[
2]))
1199 && (REGNO (operands[
0]) != REGNO (operands[
1]))"
1200 [(parallel [(set (match_dup
3)
1201 (xor:QI (match_dup
4)
1203 (clobber (match_dup
6))])
1204 (parallel [(set (match_dup
6)
1205 (xor:QI (match_dup
7)
1207 (clobber (match_scratch:QI
9 ""))])]
1210 operands[
3] = gen_lowpart(QImode, operands[
0]);
1211 operands[
4] = gen_lowpart(QImode, operands[
1]);
1212 operands[
5] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1214 operands[
6] = gen_highpart(QImode, operands[
0]);
1215 operands[
7] = gen_highpart(QImode, operands[
0]);
1216 operands[
8] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
2]) &
0xffff0000) >>
16) &
0xffff));
1219 (define_insn "xorhi3"
1220 [(set (match_operand:HI
0 "register_operand" "=A,A,A,A,?A")
1221 (xor:HI (match_operand:HI
1 "register_operand" "%A,!A,A,A,A")
1222 (match_operand:HI
2 "nonmemory_operand" "Z,A,I,M,i")))]
1229 %
0=%w1^%H2\;%
0=%b0^%U2"
1230 [(set_attr "type" "f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i_mult")])
1232 (define_insn "xorqi3"
1233 [(set (match_operand:QI
0 "register_operand" "=k,u,!k,!u,k,u,k,u,j,q,j,q,j,q,!j,!q")
1234 (xor:QI (match_operand:QI
1 "register_operand" "%uk,uk,uk,uk,
0,
0,u,k,jq,jq,
0,
0,q,j,jq,jq")
1235 (match_operand:QI
2 "nonmemory_operand" "wz,wz,uk,uk,i,i,i,i,yv,yv,i,i,i,i,jq,jq")))
1236 (clobber (match_scratch:QI
3 "=j,q,j,q,X,X,j,q,k,u,X,X,k,u,k,u"))]
1255 [(set_attr "type" "f3_alu,f3_alu,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu,f3_alu")])
1257 (define_insn "one_cmplhi2"
1258 [(set (match_operand:HI
0 "register_operand" "=A")
1259 (not:HI (match_operand:HI
1 "register_operand" "A")))]
1262 [(set_attr "type" "special")])
1265 (define_insn "one_cmplqi2"
1266 [(set (match_operand:QI
0 "register_operand" "=k,k,u,u,j,j,q,q")
1267 (not:QI (match_operand:QI
1 "register_operand" "
0,u,
0,q,
0,q,
0,j")))
1268 (clobber (match_scratch:QI
2 "=X,j,X,q,X,k,X,u"))]
1279 [(set_attr "type" "f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i,f3_alu_i")])
1283 ;; MOVE INSTRUCTIONS
1287 [(set (mem:HI (match_operand:QI
0 "register_operand" ""))
1288 (match_operand:HI
1 "register_operand" ""))]
1289 "reload_completed && (operands[
0] != stack_pointer_rtx)"
1290 [(set (mem:QI (post_inc:QI (match_dup
0)))
1292 (set (mem:QI (post_dec:QI (match_dup
0)))
1296 operands[
2] = gen_highpart(QImode, operands[
1]);
1297 operands[
3] = gen_lowpart(QImode, operands[
1]);
1302 [(set (match_operand:HI
0 "register_operand" "")
1303 (mem:HI (match_operand:QI
1 "register_operand" "")))]
1304 "reload_completed && (operands[
1] != stack_pointer_rtx)"
1306 (mem:QI (post_inc:QI (match_dup
1))))
1308 (mem:QI (post_dec:QI (match_dup
1))))]
1311 operands[
2] = gen_highpart(QImode, operands[
0]);
1312 operands[
3] = gen_lowpart(QImode, operands[
0]);
1316 [(set (mem:HI (post_inc:HI (match_operand:QI
0 "register_operand" "")))
1317 (match_operand:HI
1 "register_operand" ""))]
1319 [(set (mem:QI (post_inc:QI (match_dup
0)))
1321 (set (mem:QI (post_inc:QI (match_dup
0)))
1325 operands[
2] = gen_highpart(QImode, operands[
1]);
1326 operands[
3] = gen_lowpart(QImode, operands[
1]);
1330 [(set (match_operand:HI
0 "register_operand" "")
1331 (mem:HI (post_inc:HI (match_operand:QI
1 "register_operand" ""))))]
1334 (mem:QI (post_inc:QI (match_dup
1))))
1336 (mem:QI (post_inc:QI (match_dup
1))))]
1339 operands[
2] = gen_highpart(QImode, operands[
0]);
1340 operands[
3] = gen_lowpart(QImode, operands[
0]);
1345 [(set (match_operand:HI
0 "register_operand" "")
1346 (match_operand:HI
1 "register_operand" ""))]
1347 "reload_completed &&
1348 !(IS_ACCUM_REG (REGNO(operands[
0])) &&
1349 (REGNO(operands[
1]) == REG_PROD || REGNO(operands[
1]) == REG_Y))"
1356 operands[
2] = gen_highpart(QImode, operands[
0]);
1357 operands[
3] = gen_highpart(QImode, operands[
1]);
1358 operands[
4] = gen_lowpart(QImode, operands[
0]);
1359 operands[
5] = gen_lowpart(QImode, operands[
1]);
1363 [(set (match_operand:HI
0 "register_operand" "")
1364 (match_operand:HI
1 "const_int_operand" ""))]
1372 operands[
2] = gen_lowpart(QImode, operands[
0]);
1373 operands[
3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
1]) &
0xffff);
1375 operands[
4] = gen_highpart(QImode, operands[
0]);
1376 operands[
5] = gen_rtx (CONST_INT, VOIDmode, (((INTVAL (operands[
1]) &
0xffff0000) >>
16) &
0xffff));
1379 (define_expand "movhi"
1380 [(set (match_operand:HI
0 "general_operand" "")
1381 (match_operand:HI
1 "general_operand" ""))]
1385 if (emit_move_sequence (operands, HImode))
1390 (define_insn "match_movhi1"
1391 [(set (match_operand:HI
0 "nonimmediate_operand" "=A,Z,A,d,d,m,?d,*Y,t,f")
1392 (match_operand:HI
1 "general_operand" "d,A,K,i,m,d,*Y,?d,t,f"))]
1393 "register_operand(operands[
0], HImode)
1394 || register_operand(operands[
1], HImode)"
1397 switch (which_alternative)
1399 /* register to accumulator */
1403 return
\"%u0=%u1\;%w0=%w1
\";
1405 return
\"%
0=%
0^%
0\";
1407 return
\"%u0=%U1\;%w0=%H1
\";
1409 double_reg_from_memory(operands);
1412 double_reg_to_memory(operands);
1416 return
\"%u0=%u1\;%w0=%w1
\";
1424 [(set_attr "type" "special,data_move_multiple,f3_alu,data_move_multiple,data_move_multiple,data_move_multiple,data_move_multiple,data_move_multiple,nothing,nothing")])
1427 ;; NOTE: It is cheaper to do 'y = *r0', than 'r0 = *r0'.
1429 (define_expand "movqi"
1430 [(set (match_operand:QI
0 "nonimmediate_operand" "")
1431 (match_operand:QI
1 "general_operand" ""))]
1435 if (emit_move_sequence (operands, QImode))
1439 ;; The movqi pattern with the parallel is used for addqi insns (which have a parallel)
1440 ;; that are turned into moveqi insns by the flow phase. This happens when an auto-increment
1443 (define_insn "match_movqi1"
1444 [(parallel [(set (match_operand:QI
0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>")
1445 (match_operand:QI
1 "general_operand" "r,A,J,i,m<>,D,Y,e,
0,m<>,xyz"))
1446 (clobber (match_scratch:QI
2 "=X,X,X,X,X,X,X,X,X,X,X"))])]
1447 "register_operand(operands[
0], QImode)
1448 || register_operand(operands[
1], QImode)"
1451 switch (which_alternative)
1454 /* We have to use the move mneumonic otherwise the
1610 will
1455 attempt to transfer all
32-bits of 'y', 'p' or an accumulator
1456 , which we don't want */
1457 if (REGNO(operands[
1]) == REG_Y || REGNO(operands[
1]) == REG_PROD
1458 || IS_ACCUM_REG(REGNO(operands[
1])))
1459 return
\"move %
0=%
1\";
1467 return
\"set %
0=%H1
\";
1491 [(set_attr "type" "data_move,data_move,data_move_short_i,data_move_i,data_move_memory,data_move_memory,data_move_memory,data_move_memory,nothing,malu,malu")])
1493 (define_insn "match_movqi2"
1494 [(set (match_operand:QI
0 "nonimmediate_operand" "=A,r,aW,c,?D,m<>,e,Y,r,xyz,m<>")
1495 (match_operand:QI
1 "general_operand" "r,A,J,i,m<>,D,Y,e,
0,m<>,xyz"))]
1496 "register_operand(operands[
0], QImode)
1497 || register_operand(operands[
1], QImode)"
1500 switch (which_alternative)
1503 /* We have to use the move mneumonic otherwise the
1610 will
1504 attempt to transfer all
32-bits of 'y', 'p' or an accumulator
1505 , which we don't want */
1506 if (REGNO(operands[
1]) == REG_Y || REGNO(operands[
1]) == REG_PROD
1507 || IS_ACCUM_REG(REGNO(operands[
1])))
1508 return
\"move %
0=%
1\";
1516 return
\"set %
0=%H1
\";
1540 [(set_attr "type" "data_move,data_move,data_move_short_i,data_move_i,data_move_memory,data_move_memory,data_move_memory,data_move_memory,nothing,malu,malu")])
1542 (define_expand "reload_inqi"
1543 [(set (match_operand:QI
0 "register_operand" "=u")
1544 (match_operand:QI
1 "sp_operand" ""))
1545 (clobber (match_operand:QI
2 "register_operand" "=&q"))]
1549 rtx addr_reg = XEXP (operands[
1],
0);
1550 rtx offset = XEXP (operands[
1],
1);
1552 /* First, move the frame or stack pointer to the accumulator */
1553 emit_move_insn (operands[
0], addr_reg);
1555 /* Then generate the add insn */
1556 emit_insn (gen_rtx_PARALLEL
1559 gen_rtx_SET (VOIDmode, operands[
0],
1560 gen_rtx_PLUS (QImode, operands[
0],
1562 gen_rtx_CLOBBER (VOIDmode, operands[
2]))));
1566 (define_expand "reload_inhi"
1567 [(set (match_operand:HI
0 "register_operand" "=r")
1568 (match_operand:HI
1 "register_operand" "r"))
1569 (clobber (match_operand:QI
2 "register_operand" "=&h"))]
1573 /* Check for an overlap of operand
2 (an accumulator) with
1574 the msw of operand
0. If we have an overlap we must reverse
1575 the order of the moves. */
1577 if (REGNO(operands[
2]) == REGNO(operands[
0]))
1579 emit_move_insn (operands[
2], operand_subword (operands[
1],
1,
0, HImode));
1580 emit_move_insn (operand_subword (operands[
0],
1,
0, HImode), operands[
2]);
1581 emit_move_insn (operands[
2], operand_subword (operands[
1],
0,
0, HImode));
1582 emit_move_insn (operand_subword (operands[
0],
0,
0, HImode), operands[
2]);
1586 emit_move_insn (operands[
2], operand_subword (operands[
1],
0,
0, HImode));
1587 emit_move_insn (operand_subword (operands[
0],
0,
0, HImode), operands[
2]);
1588 emit_move_insn (operands[
2], operand_subword (operands[
1],
1,
0, HImode));
1589 emit_move_insn (operand_subword (operands[
0],
1,
0, HImode), operands[
2]);
1596 (define_expand "reload_outhi"
1597 [(set (match_operand:HI
0 "register_operand" "=r")
1598 (match_operand:HI
1 "register_operand" "r"))
1599 (clobber (match_operand:QI
2 "register_operand" "=&h"))]
1603 emit_move_insn (operands[
2], operand_subword (operands[
1],
0,
0, HImode));
1604 emit_move_insn (operand_subword (operands[
0],
0,
0, HImode), operands[
2]);
1605 emit_move_insn (operands[
2], operand_subword (operands[
1],
1,
0, HImode));
1606 emit_move_insn (operand_subword (operands[
0],
1,
0, HImode), operands[
2]);
1610 (define_expand "movstrqi"
1611 [(parallel [(set (match_operand:BLK
0 "memory_operand" "")
1612 (match_operand:BLK
1 "memory_operand" ""))
1613 (use (match_operand:QI
2 "const_int_operand" ""))
1614 (use (match_operand:QI
3 "const_int_operand" ""))
1615 (clobber (match_scratch:QI
4 ""))
1616 (clobber (match_dup
5))
1617 (clobber (match_dup
6))])]
1623 if (GET_CODE (operands[
2]) != CONST_INT)
1626 if (INTVAL(operands[
2]) >
127)
1629 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[
0],
0));
1630 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[
1],
0));
1632 operands[
5] = addr0;
1633 operands[
6] = addr1;
1635 operands[
0] = change_address (operands[
0], VOIDmode, addr0);
1636 operands[
1] = change_address (operands[
1], VOIDmode, addr1);
1640 [(set (mem:BLK (match_operand:QI
0 "register_operand" "a"))
1641 (mem:BLK (match_operand:QI
1 "register_operand" "a")))
1642 (use (match_operand:QI
2 "const_int_operand" "n"))
1643 (use (match_operand:QI
3 "immediate_operand" "i"))
1644 (clobber (match_scratch:QI
4 "=x"))
1645 (clobber (match_dup
0))
1646 (clobber (match_dup
1))]
1649 { return output_block_move (operands); }")
1652 ;; Floating point move insns
1655 (define_expand "movhf"
1656 [(set (match_operand:HF
0 "general_operand" "")
1657 (match_operand:HF
1 "general_operand" ""))]
1661 if (emit_move_sequence (operands, HFmode))
1665 (define_insn "match_movhf"
1666 [(set (match_operand:HF
0 "nonimmediate_operand" "=A,Z,d,d,m,d,Y")
1667 (match_operand:HF
1 "general_operand" "d,A,F,m,d,Y,d"))]
1671 /* NOTE: When loading the register
16 bits at a time we
1672 MUST load the high half FIRST (because the
1610 zeros
1673 the low half) and then load the low half */
1675 switch (which_alternative)
1677 /* register to accumulator */
1681 return
\"%u0=%u1\;%w0=%w1
\";
1683 output_dsp16xx_float_const(operands);
1686 double_reg_from_memory(operands);
1689 double_reg_to_memory(operands);
1693 return
\"%u0=%u1\;%w0=%w1
\";
1698 [(set_attr "type" "move,move,load_i,load,store,load,store")])
1702 (define_expand "reload_inhf"
1703 [(set (match_operand:HF
0 "register_operand" "=r")
1704 (match_operand:HF
1 "register_operand" "r"))
1705 (clobber (match_operand:QI
2 "register_operand" "=&h"))]
1709 /* Check for an overlap of operand
2 (an accumulator) with
1710 the msw of operand
0. If we have an overlap we must reverse
1711 the order of the moves. */
1713 if (REGNO(operands[
2]) == REGNO(operands[
0]))
1715 emit_move_insn (operands[
2], operand_subword (operands[
1],
1,
0, HFmode));
1716 emit_move_insn (operand_subword (operands[
0],
1,
0, HFmode), operands[
2]);
1717 emit_move_insn (operands[
2], operand_subword (operands[
1],
0,
0, HFmode));
1718 emit_move_insn (operand_subword (operands[
0],
0,
0, HFmode), operands[
2]);
1722 emit_move_insn (operands[
2], operand_subword (operands[
1],
0,
0, HFmode));
1723 emit_move_insn (operand_subword (operands[
0],
0,
0, HFmode), operands[
2]);
1724 emit_move_insn (operands[
2], operand_subword (operands[
1],
1,
0, HFmode));
1725 emit_move_insn (operand_subword (operands[
0],
1,
0, HFmode), operands[
2]);
1731 (define_expand "reload_outhf"
1732 [(set (match_operand:HF
0 "register_operand" "=r")
1733 (match_operand:HF
1 "register_operand" "r"))
1734 (clobber (match_operand:QI
2 "register_operand" "=&h"))]
1738 emit_move_insn (operands[
2], operand_subword (operands[
1],
0,
0, HFmode));
1739 emit_move_insn (operand_subword (operands[
0],
0,
0, HFmode), operands[
2]);
1740 emit_move_insn (operands[
2], operand_subword (operands[
1],
1,
0, HFmode));
1741 emit_move_insn (operand_subword (operands[
0],
1,
0, HFmode), operands[
2]);
1747 ;; CONVERSION INSTRUCTIONS
1750 (define_expand "extendqihi2"
1751 [(clobber (match_dup
2))
1752 (set (match_dup
3) (match_operand:QI
1 "register_operand" ""))
1753 (set (match_operand:HI
0 "register_operand" "")
1754 (ashift:HI (match_dup
2)
1757 (ashiftrt:HI (match_dup
0) (const_int
16)))]
1761 operands[
2] = gen_reg_rtx (HImode);
1762 operands[
3] = gen_rtx_SUBREG (QImode, operands[
2],
1);
1765 (define_insn "internal_extendqihi2"
1766 [(set (match_operand:HI
0 "register_operand" "=A")
1767 (sign_extend:HI (match_operand:QI
1 "register_operand" "ku")))]
1769 "%
0 = extracts(%m1,
0x1000)"
1770 [(set_attr "type" "shift_i")])
1772 ;;(define_insn "extendqihi2"
1773 ;; [(set (match_operand:HI
0 "register_operand" "=A")
1774 ;; (sign_extend:HI (match_operand:QI
1 "register_operand" "h")))]
1778 ;;(define_insn "zero_extendqihi2"
1779 ;; [(set (match_operand:HI
0 "register_operand" "=t,f,A,?d,?A")
1780 ;; (zero_extend:HI (match_operand:QI
1 "register_operand" "w,z,ku,A,r")))]
1784 ;; switch (which_alternative)
1791 ;; if (REGNO(operands[
1]) == (REGNO(operands[
0]) +
1))
1794 ;; return
\"%w0=%
1\;%
0=
0\";
1796 ;; return
\"%w0=%
1\;%
0=
0\";
1799 ;; if (REGNO(operands[
1]) == REG_Y || REGNO(operands[
1]) == REG_PROD
1800 ;; || IS_ACCUM_REG(REGNO(operands[
1])))
1801 ;; return
\"move %w0=%
1\;%
0=
0\";
1803 ;; return
\"%w0=%
1\;%
0=
0\";
1809 ;;(define_expand "zero_extendqihi2"
1810 ;; [(clobber (match_dup
2))
1811 ;; (set (match_dup
3) (match_operand:QI
1 "register_operand" ""))
1812 ;; (set (match_operand:HI
0 "register_operand" "")
1813 ;; (ashift:HI (match_dup
2)
1815 ;; (set (match_dup
0)
1816 ;; (lshiftrt:HI (match_dup
0) (const_int
16)))]
1820 ;; operands[
2] = gen_reg_rtx (HImode);
1821 ;; operands[
3] = gen_rtx (SUBREG, QImode, operands[
2],
1);
1824 (define_expand "zero_extendqihi2"
1825 [(set (match_operand:HI
0 "register_operand" "")
1826 (zero_extend:HI (match_operand:QI
1 "register_operand" "")))]
1831 (define_insn "match_zero_extendqihi_bmu"
1832 [(set (match_operand:HI
0 "register_operand" "=?*Z,?*Z,?A,A")
1833 (zero_extend:HI (match_operand:QI
1 "register_operand" "?A,?*Y,*Z*x*a*W*Y,ku")))]
1837 switch (which_alternative)
1840 return
\"%w0=%
1\;%
0=
0\";
1843 return
\"%w0=%
1\;%
0=
0\";
1846 if (REGNO(operands[
1]) == (REGNO(operands[
0]) +
1))
1848 else if (REGNO(operands[
1]) == REG_Y || REGNO(operands[
1]) == REG_PROD
1849 || IS_ACCUM_REG(REGNO(operands[
1])))
1851 return
\"move %w0=%
1\;%
0=
0\";
1854 return
\"%w0=%
1\;%
0=
0\";
1857 return
\"%
0 = extractz(%m1,
0x1000)
\";
1862 [(set_attr "type" "data_move_2,data_move_2,data_move_2,shift_i")])
1864 (define_insn "match_zero_extendqihi2_nobmu"
1865 [(set (match_operand:HI
0 "register_operand" "=?Z,?Z,A")
1866 (zero_extend:HI (match_operand:QI
1 "register_operand" "A,Y,r")))]
1870 switch (which_alternative)
1873 return
\"%w0=%
1\;%
0=
0\";
1876 return
\"%w0=%
1\;%
0=
0\";
1879 if (REGNO(operands[
1]) +
1 == (REGNO(operands[
0]) +
1))
1881 else if (REGNO(operands[
1]) == REG_Y || REGNO(operands[
1]) == REG_PROD
1882 || IS_ACCUM_REG(REGNO(operands[
1])))
1884 return
\"move %w0=%
1\;%
0=
0\";
1887 return
\"%w0=%
1\;%
0=
0\";
1892 [(set_attr "type" "data_move_2,data_move_2,data_move_2")])
1895 ;; Floating point conversions
1897 (define_expand "floathihf2"
1898 [(set (match_operand:HF
0 "register_operand" "")
1899 (float:HF (match_operand:HI
1 "register_operand" "")))]
1903 if (!dsp16xx_floathihf2_libcall)
1904 dsp16xx_floathihf2_libcall = gen_rtx_SYMBOL_REF (Pmode, FLOATHIHF2_LIBCALL);
1906 emit_library_call (dsp16xx_floathihf2_libcall,
1, HFmode,
1,
1907 operands[
1], HImode);
1908 emit_move_insn (operands[
0], hard_libcall_value(HFmode));
1912 (define_expand "fix_trunchfhi2"
1913 [(set (match_operand:HI
0 "register_operand" "")
1914 (fix:HI (match_operand:HF
1 "register_operand" "")))]
1918 if (!dsp16xx_fixhfhi2_libcall)
1919 dsp16xx_fixhfhi2_libcall = gen_rtx_SYMBOL_REF (Pmode, FIXHFHI2_LIBCALL);
1921 emit_library_call (dsp16xx_fixhfhi2_libcall,
1, HImode,
1,
1922 operands[
1], HFmode);
1923 emit_move_insn (operands[
0], hard_libcall_value(HImode));
1927 (define_expand "fixuns_trunchfhi2"
1928 [(set (match_operand:HI
0 "register_operand" "")
1929 (unsigned_fix:HI (match_operand:HF
1 "register_operand" "")))]
1933 rtx reg1 = gen_reg_rtx (HFmode);
1934 rtx reg2 = gen_reg_rtx (HFmode);
1935 rtx reg3 = gen_reg_rtx (HImode);
1936 rtx label1 = gen_label_rtx ();
1937 rtx label2 = gen_label_rtx ();
1938 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (
1.0,
31);
1940 if (reg1) /* turn off complaints about unreached code */
1942 emit_move_insn (reg1, immed_real_const_1 (offset, HFmode));
1943 do_pending_stack_adjust ();
1945 emit_insn (gen_cmphf (operands[
1], reg1));
1946 emit_jump_insn (gen_bge (label1));
1948 emit_insn (gen_fix_trunchfhi2 (operands[
0], operands[
1]));
1949 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1950 gen_rtx_LABEL_REF (VOIDmode, label2)));
1953 emit_label (label1);
1954 emit_insn (gen_subhf3 (reg2, operands[
1], reg1));
1955 emit_move_insn (reg3, GEN_INT (
0x80000000));;
1957 emit_insn (gen_fix_trunchfhi2 (operands[
0], reg2));
1958 emit_insn (gen_iorhi3 (operands[
0], operands[
0], reg3));
1960 emit_label (label2);
1962 /* allow REG_NOTES to be set on last insn (labels don't have enough
1963 fields, and can't be used for REG_NOTES anyway). */
1964 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
1970 ;; SHIFT INSTRUCTIONS
1974 [(set (match_operand:HI
0 "register_operand" "=A")
1975 (ashiftrt:HI (match_operand:HI
1 "register_operand" "A")
1979 [(set_attr "type" "special")])
1982 [(set (match_operand:HI
0 "register_operand" "=A")
1983 (ashiftrt:HI (match_operand:HI
1 "register_operand" "A")
1987 [(set_attr "type" "special")])
1990 [(set (match_operand:HI
0 "register_operand" "=A")
1991 (ashiftrt:HI (match_operand:HI
1 "register_operand" "A")
1995 [(set_attr "type" "special")])
1998 [(set (match_operand:HI
0 "register_operand" "=A")
1999 (ashiftrt:HI (match_operand:HI
1 "register_operand" "A")
2003 [(set_attr "type" "special")])
2006 ;; Arithmetic Right shift
2008 (define_expand "ashrhi3"
2009 [(set (match_operand:HI
0 "register_operand" "")
2010 (ashiftrt:HI (match_operand:HI
1 "register_operand" "")
2011 (match_operand:QI
2 "nonmemory_operand" "")))]
2017 /* If we are shifting by a constant we can do it in
1 or more
2018 1600 core shift instructions. The core instructions can
2019 shift by
1,
4,
8, or
16. */
2021 if (GET_CODE(operands[
2]) == CONST_INT)
2025 rtx label1 = gen_label_rtx ();
2026 rtx label2 = gen_label_rtx ();
2029 if (!dsp16xx_ashrhi3_libcall)
2030 dsp16xx_ashrhi3_libcall
2031 = gen_rtx_SYMBOL_REF (Pmode, ASHRHI3_LIBCALL);
2033 emit_library_call (dsp16xx_ashrhi3_libcall,
1, HImode,
2,
2034 operands[
1], HImode,
2035 operands[
2], QImode);
2036 emit_move_insn (operands[
0], hard_libcall_value(HImode));
2039 do_pending_stack_adjust ();
2040 emit_insn (gen_tstqi (operands[
2]));
2041 emit_jump_insn (gen_bne (label1));
2042 emit_move_insn (operands[
0], operands[
1]);
2043 emit_jump_insn (gen_jump (label2));
2045 emit_label (label1);
2047 if (GET_CODE(operands[
2]) != MEM)
2051 stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode),
0);
2052 stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot,
0));
2053 emit_move_insn (stack_slot, operands[
2]);
2054 operands[
2] = stack_slot;
2057 emit_insn (gen_match_ashrhi3_nobmu (operands[
0], operands[
1], operands[
2]));
2058 emit_label (label2);
2065 (define_insn "match_ashrhi3_bmu"
2066 [(set (match_operand:HI
0 "register_operand" "=A,A,A")
2067 (ashiftrt:HI (match_operand:HI
1 "register_operand" "A,A,!A")
2068 (match_operand:QI
2 "nonmemory_operand" "B,I,h")))]
2074 [(set_attr "type" "shift,shift_i,shift")])
2076 (define_insn "match_ashrhi3_nobmu"
2077 [(set (match_operand:HI
0 "register_operand" "=A,A")
2078 (ashiftrt:HI (match_operand:HI
1 "register_operand" "A,
0")
2079 (match_operand:QI
2 "general_operand" "n,m")))]
2083 if (which_alternative ==
0)
2085 emit_1600_core_shift (ASHIFTRT, operands, INTVAL(operands[
2]));
2090 output_asm_insn (
\"cloop=%
2\", operands);
2091 output_asm_insn (
\"do
0 {
\", operands);
2092 output_asm_insn (
\"%
0=%
0>>
1\", operands);
2100 ;; Logical Right Shift
2103 [(set (match_operand:HI
0 "register_operand" "=A")
2104 (lshiftrt:HI (match_operand:HI
1 "register_operand" "A")
2107 "%
0=%
1>>
1\;%
0=%b0&
0x7fff"
2108 [(set_attr "type" "special")])
2111 [(set (match_operand:HI
0 "register_operand" "=A")
2112 (lshiftrt:HI (match_operand:HI
1 "register_operand" "A")
2115 "%
0=%
1>>
4\;%
0=%b0&
0x0fff"
2116 [(set_attr "type" "special")])
2119 [(set (match_operand:HI
0 "register_operand" "=A")
2120 (lshiftrt:HI (match_operand:HI
1 "register_operand" "A")
2123 "%
0=%
1>>
8\;%
0=%b0&
0x00ff"
2124 [(set_attr "type" "special")])
2127 [(set (match_operand:HI
0 "register_operand" "=A")
2128 (lshiftrt:HI (match_operand:HI
1 "register_operand" "A")
2131 "%
0=%
1>>
16\;%
0=%b0&
0x0000"
2132 [(set_attr "type" "special")])
2134 (define_expand "lshrhi3"
2135 [(set (match_operand:HI
0 "register_operand" "")
2136 (lshiftrt:HI (match_operand:HI
1 "register_operand" "")
2137 (match_operand:QI
2 "nonmemory_operand" "")))]
2143 /* If we are shifting by a constant we can do it in
1 or more
2144 1600 core shift instructions. The core instructions can
2145 shift by
1,
4,
8, or
16. */
2147 if (GET_CODE(operands[
2]) == CONST_INT)
2148 emit_insn (gen_match_lshrhi3_nobmu (operands[
0], operands[
1], operands[
2]));
2151 rtx label1 = gen_label_rtx ();
2152 rtx label2 = gen_label_rtx ();
2154 if (!dsp16xx_lshrhi3_libcall)
2155 dsp16xx_lshrhi3_libcall
2156 = gen_rtx_SYMBOL_REF (Pmode, LSHRHI3_LIBCALL);
2158 emit_library_call (dsp16xx_lshrhi3_libcall,
1, HImode,
2,
2159 operands[
1], HImode,
2160 operands[
2], QImode);
2161 emit_move_insn (operands[
0], hard_libcall_value(HImode));
2164 do_pending_stack_adjust ();
2165 emit_insn (gen_tstqi (operands[
2]));
2166 emit_jump_insn (gen_bne (label1));
2167 emit_move_insn (operands[
0], operands[
1]);
2168 emit_jump_insn (gen_jump (label2));
2170 emit_label (label1);
2172 if (GET_CODE(operands[
2]) != MEM)
2176 stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode),
0);
2177 stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot,
0));
2178 emit_move_insn (stack_slot, operands[
2]);
2179 operands[
2] = stack_slot;
2182 emit_insn (gen_match_lshrhi3_nobmu (operands[
0], operands[
1], operands[
2]));
2183 emit_label (label2);
2190 (define_insn "match_lshrhi3"
2191 [(set (match_operand:HI
0 "register_operand" "=A,A,A")
2192 (lshiftrt:HI (match_operand:HI
1 "register_operand" "A,A,!A")
2193 (match_operand:QI
2 "nonmemory_operand" "B,I,h")))]
2199 [(set_attr "type" "shift,shift_i,shift")])
2201 (define_insn "match_lshrhi3_nobmu"
2202 [(set (match_operand:HI
0 "register_operand" "=A,A")
2203 (lshiftrt:HI (match_operand:HI
1 "register_operand" "A,
0")
2204 (match_operand:QI
2 "general_operand" "n,m")))
2205 (clobber (match_scratch:QI
3 "=X,Y"))]
2209 if (which_alternative ==
0)
2211 emit_1600_core_shift (LSHIFTRT, operands, INTVAL(operands[
2]));
2216 output_asm_insn (
\"%
3=psw\;psw=
0\",operands);
2217 output_asm_insn (
\"cloop=%
2\", operands);
2218 output_asm_insn (
\"do
0 {
\", operands);
2219 output_asm_insn (
\"%
0=%
0>>
1\", operands);
2220 output_asm_insn (
\"}
\", operands);
2227 ;; Arithmetic Left shift
2229 ;; Start off with special case arithmetic left shift by
1,
4,
8 or
16.
2233 [(set (match_operand:HI
0 "register_operand" "=A")
2234 (ashift:HI (match_operand:HI
1 "register_operand" "A")
2238 [(set_attr "type" "special")])
2241 [(set (match_operand:HI
0 "register_operand" "=A")
2242 (ashift:HI (match_operand:HI
1 "register_operand" "A")
2246 [(set_attr "type" "special")])
2249 [(set (match_operand:HI
0 "register_operand" "=A")
2250 (ashift:HI (match_operand:HI
1 "register_operand" "A")
2254 [(set_attr "type" "special")])
2257 [(set (match_operand:HI
0 "register_operand" "=A")
2258 (ashift:HI (match_operand:HI
1 "general_operand" "A")
2262 [(set_attr "type" "special")])
2266 ;; Normal Arithmetic Shift Left
2269 (define_expand "ashlhi3"
2270 [(set (match_operand:HI
0 "register_operand" "")
2271 (ashift:HI (match_operand:HI
1 "register_operand" "")
2272 (match_operand:QI
2 "nonmemory_operand" "")))]
2278 /* If we are shifting by a constant we can do it in
1 or more
2279 1600 core shift instructions. The core instructions can
2280 shift by
1,
4,
8, or
16. */
2282 if (GET_CODE(operands[
2]) == CONST_INT)
2286 rtx label1 = gen_label_rtx ();
2287 rtx label2 = gen_label_rtx ();
2289 if (!dsp16xx_ashlhi3_libcall)
2290 dsp16xx_ashlhi3_libcall
2291 = gen_rtx_SYMBOL_REF (Pmode, ASHLHI3_LIBCALL);
2293 emit_library_call (dsp16xx_ashlhi3_libcall,
1, HImode,
2,
2294 operands[
1], HImode, operands[
2], QImode);
2295 emit_move_insn (operands[
0], hard_libcall_value(HImode));
2298 do_pending_stack_adjust ();
2299 emit_insn (gen_tstqi (operands[
2]));
2300 emit_jump_insn (gen_bne (label1));
2301 emit_move_insn (operands[
0], operands[
1]);
2302 emit_jump_insn (gen_jump (label2));
2304 emit_label (label1);
2306 if (GET_CODE(operands[
2]) != MEM)
2310 stack_slot = assign_stack_temp (QImode, GET_MODE_SIZE(QImode),
0);
2311 stack_slot = change_address (stack_slot, VOIDmode, XEXP (stack_slot,
0));
2312 emit_move_insn (stack_slot, operands[
2]);
2313 operands[
2] = stack_slot;
2315 emit_insn (gen_match_ashlhi3_nobmu (operands[
0], operands[
1], operands[
2]));
2316 emit_label (label2);
2323 (define_insn "match_ashlhi3"
2324 [(set (match_operand:HI
0 "register_operand" "=A,A,A")
2325 (ashift:HI (match_operand:HI
1 "register_operand" "A,A,A")
2326 (match_operand:QI
2 "nonmemory_operand" "B,I,!h")))]
2329 %
0=%
1<<%
2\;move %u0=%u0
2330 %
0=%
1<<%H2\;move %u0=%u0
2331 %
0=%
1<<%
2\;move %u0=%u0"
2332 [(set_attr "type" "shift_multiple,shift_multiple,shift_multiple")])
2334 (define_insn "match_ashlhi3_nobmu"
2335 [(set (match_operand:HI
0 "register_operand" "=A,A")
2336 (ashift:HI (match_operand:HI
1 "register_operand" "A,
0")
2337 (match_operand:QI
2 "general_operand" "n,m")))]
2341 if (which_alternative ==
0)
2343 emit_1600_core_shift (ASHIFT, operands, INTVAL(operands[
2]));
2348 output_asm_insn (
\"cloop=%
2\", operands);
2349 output_asm_insn (
\"do
0 {
\", operands);
2350 output_asm_insn (
\"%
0=%
0<<
1\", operands);
2359 [(set (match_operand:QI
0 "register_operand" "=k,u")
2360 (sign_extract:QI (match_operand:QI
1 "register_operand" "ku,ku")
2361 (match_operand:QI
2 "const_int_operand" "n,n")
2362 (match_operand:QI
3 "const_int_operand" "n,n")))
2363 (clobber (match_scratch:QI
4 "=j,q"))]
2368 = GEN_INT ((INTVAL (operands[
2]) <<
8) + (INTVAL (operands[
3]) &
0xff));
2369 return
\"%m0 = extracts (%m1, %H5)
\";
2371 [(set_attr "type" "shift_i")])
2373 (define_insn "extzv"
2374 [(set (match_operand:QI
0 "register_operand" "=k,u")
2375 (zero_extract:QI (match_operand:QI
1 "register_operand" "ku,ku")
2376 (match_operand:QI
2 "const_int_operand" "n,n")
2377 (match_operand:QI
3 "const_int_operand" "n,n")))
2378 (clobber (match_scratch:QI
4 "=j,q"))]
2383 = GEN_INT ((INTVAL (operands[
2]) <<
8) + (INTVAL (operands[
3]) &
0xff));
2384 return
\"%m0 = extractz (%m1, %H5)
\";
2386 [(set_attr "type" "shift_i")])
2389 ;; conditional instructions
2392 (define_expand "seq"
2393 [(set (match_operand:QI
0 "register_operand" "")
2394 (eq:QI (match_dup
1) (const_int
0)))]
2398 if (dsp16xx_compare_gen == gen_compare_reg)
2399 operands[
1] = (*dsp16xx_compare_gen)(EQ, dsp16xx_compare_op0, dsp16xx_compare_op1);
2401 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2404 (define_expand "sne"
2405 [(set (match_operand:QI
0 "register_operand" "")
2406 (ne:QI (match_dup
1) (const_int
0)))]
2410 if (dsp16xx_compare_gen == gen_compare_reg)
2411 operands[
1] = (*dsp16xx_compare_gen)(NE, dsp16xx_compare_op0, dsp16xx_compare_op1);
2413 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2417 (define_expand "sgt"
2418 [(set (match_operand:QI
0 "register_operand" "")
2419 (gt:QI (match_dup
1) (const_int
0)))]
2423 if (dsp16xx_compare_gen == gen_compare_reg)
2424 operands[
1] = (*dsp16xx_compare_gen)(GT, dsp16xx_compare_op0, dsp16xx_compare_op1);
2426 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2430 (define_expand "slt"
2431 [(set (match_operand:QI
0 "register_operand" "")
2432 (lt:QI (match_dup
1) (const_int
0)))]
2436 if (dsp16xx_compare_gen == gen_compare_reg)
2437 operands[
1] = (*dsp16xx_compare_gen)(LT, dsp16xx_compare_op0, dsp16xx_compare_op1);
2439 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2442 (define_expand "sge"
2443 [(set (match_operand:QI
0 "register_operand" "")
2444 (ge:QI (match_dup
1) (const_int
0)))]
2448 if (dsp16xx_compare_gen == gen_compare_reg)
2449 operands[
1] = (*dsp16xx_compare_gen)(GE, dsp16xx_compare_op0, dsp16xx_compare_op1);
2451 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2455 (define_expand "sle"
2456 [(set (match_operand:QI
0 "register_operand" "")
2457 (le:QI (match_dup
1) (const_int
0)))]
2461 if (dsp16xx_compare_gen == gen_compare_reg)
2462 operands[
1] = (*dsp16xx_compare_gen)(LE, dsp16xx_compare_op0, dsp16xx_compare_op1);
2464 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2468 (define_expand "sgtu"
2469 [(set (match_operand:QI
0 "register_operand" "")
2470 (gtu:QI (match_dup
1) (const_int
0)))]
2474 if (dsp16xx_compare_gen == gen_compare_reg)
2475 operands[
1] = (*dsp16xx_compare_gen)(GTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2477 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2481 (define_expand "sltu"
2482 [(set (match_operand:QI
0 "register_operand" "")
2483 (ltu:QI (match_dup
1) (const_int
0)))]
2487 if (dsp16xx_compare_gen == gen_compare_reg)
2488 operands[
1] = (*dsp16xx_compare_gen)(LTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2490 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2494 (define_expand "sgeu"
2495 [(set (match_operand:QI
0 "register_operand" "")
2496 (geu:QI (match_dup
1) (const_int
0)))]
2500 if (dsp16xx_compare_gen == gen_compare_reg)
2501 operands[
1] = (*dsp16xx_compare_gen)(GEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2503 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2507 (define_expand "sleu"
2508 [(set (match_operand:QI
0 "register_operand" "")
2509 (leu:QI (match_dup
1) (const_int
0)))]
2513 if (dsp16xx_compare_gen == gen_compare_reg)
2514 operands[
1] = (*dsp16xx_compare_gen)(LEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2516 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2521 [(set (match_operand:QI
0 "register_operand" "=jq")
2522 (match_operator:QI
1 "comparison_operator" [(cc0) (const_int
0)]))]
2524 "%
0 =
0\;if %C1 %b0 = %b0 +
1"
2525 [(set_attr "type" "special_2")])
2528 ;; Jump Instructions
2531 (define_expand "beq"
2533 (if_then_else (eq (match_dup
1)
2535 (label_ref (match_operand
0 "" ""))
2540 if (dsp16xx_compare_gen == gen_compare_reg)
2541 operands[
1] = (*dsp16xx_compare_gen)(EQ, dsp16xx_compare_op0, dsp16xx_compare_op1);
2543 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2546 (define_expand "bne"
2548 (if_then_else (ne (match_dup
1)
2550 (label_ref (match_operand
0 "" ""))
2555 if (dsp16xx_compare_gen == gen_compare_reg)
2556 operands[
1] = (*dsp16xx_compare_gen)(NE, dsp16xx_compare_op0, dsp16xx_compare_op1);
2558 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2562 (define_expand "bgt"
2564 (if_then_else (gt (match_dup
1)
2566 (label_ref (match_operand
0 "" ""))
2571 if (dsp16xx_compare_gen == gen_compare_reg)
2572 operands[
1] = (*dsp16xx_compare_gen)(GT, dsp16xx_compare_op0, dsp16xx_compare_op1);
2574 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2578 (define_expand "bge"
2580 (if_then_else (ge (match_dup
1)
2582 (label_ref (match_operand
0 "" ""))
2587 if (dsp16xx_compare_gen == gen_compare_reg)
2588 operands[
1] = (*dsp16xx_compare_gen)(GE, dsp16xx_compare_op0, dsp16xx_compare_op1);
2590 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2594 (define_expand "blt"
2596 (if_then_else (lt (match_dup
1)
2598 (label_ref (match_operand
0 "" ""))
2603 if (dsp16xx_compare_gen == gen_compare_reg)
2604 operands[
1] = (*dsp16xx_compare_gen)(LT, dsp16xx_compare_op0, dsp16xx_compare_op1);
2606 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2610 (define_expand "ble"
2612 (if_then_else (le (match_dup
1)
2614 (label_ref (match_operand
0 "" ""))
2619 if (dsp16xx_compare_gen == gen_compare_reg)
2620 operands[
1] = (*dsp16xx_compare_gen)(LE, dsp16xx_compare_op0, dsp16xx_compare_op1);
2622 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2626 (define_expand "bgtu"
2628 (if_then_else (gtu (match_dup
1)
2630 (label_ref (match_operand
0 "" ""))
2635 if (dsp16xx_compare_gen == gen_compare_reg)
2636 operands[
1] = (*dsp16xx_compare_gen)(GTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2638 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2642 (define_expand "bgeu"
2644 (if_then_else (geu (match_dup
1)
2646 (label_ref (match_operand
0 "" ""))
2651 if (dsp16xx_compare_gen == gen_compare_reg)
2652 operands[
1] = (*dsp16xx_compare_gen)(GEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2654 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2658 (define_expand "bltu"
2660 (if_then_else (ltu (match_dup
1)
2662 (label_ref (match_operand
0 "" ""))
2667 if (dsp16xx_compare_gen == gen_compare_reg)
2668 operands[
1] = (*dsp16xx_compare_gen)(LTU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2670 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2674 (define_expand "bleu"
2676 (if_then_else (leu (match_dup
1)
2678 (label_ref (match_operand
0 "" ""))
2683 if (dsp16xx_compare_gen == gen_compare_reg)
2684 operands[
1] = (*dsp16xx_compare_gen)(LEU, dsp16xx_compare_op0, dsp16xx_compare_op1);
2686 operands[
1] = (*dsp16xx_compare_gen)(dsp16xx_compare_op0);
2692 (if_then_else (match_operator
1 "comparison_operator"
2693 [(cc0) (const_int
0)])
2694 (label_ref (match_operand
0 "" ""))
2697 "pt=%l0\;if %C1 goto pt"
2698 [(set_attr "type" "cond_jump")])
2702 (if_then_else (match_operator
1 "comparison_operator"
2703 [(cc0) (const_int
0)])
2704 (label_ref (match_operand
0 "" ""))
2708 [(set_attr "type" "cond_jump")])
2711 ;; Negated conditional jump instructions.
2712 ;; These are necessary because jump optimization can turn
2713 ;; direct-conditional branches into reverse-conditional
2718 (if_then_else (match_operator
1 "comparison_operator"
2719 [(cc0) (const_int
0)])
2721 (label_ref (match_operand
0 "" ""))))]
2723 "pt=%l0\;if %I1 goto pt"
2724 [(set_attr "type" "cond_jump")])
2728 (if_then_else (match_operator
1 "comparison_operator"
2729 [(cc0) (const_int
0)])
2731 (label_ref (match_operand
0 "" ""))))]
2734 [(set_attr "type" "cond_jump")])
2743 (label_ref (match_operand
0 "" "")))]
2747 if (TARGET_NEAR_JUMP)
2748 return
\"goto %l0
\";
2750 return
\"pt=%l0\;goto pt
\";
2752 [(set_attr "type" "jump")])
2755 (define_insn "indirect_jump"
2756 [(set (pc) (match_operand:QI
0 "register_operand" "A"))]
2759 [(set_attr "type" "jump")])
2761 (define_insn "tablejump"
2762 [(set (pc) (match_operand:QI
0 "register_operand" "A"))
2763 (use (label_ref (match_operand
1 "" "")))]
2766 [(set_attr "type" "jump")])
2772 ;; Call subroutine with no return value.
2775 (define_expand "call"
2776 [(parallel [(call (match_operand:QI
0 "" "")
2777 (match_operand
1 "" ""))
2778 (clobber (reg:QI
24))])]
2782 if (GET_CODE (operands[
0]) == MEM
2783 && ! call_address_operand (XEXP (operands[
0],
0), QImode))
2784 operands[
0] = gen_rtx_MEM (GET_MODE (operands[
0]),
2785 force_reg (Pmode, XEXP (operands[
0],
0)));
2789 [(parallel [(call (mem:QI (match_operand:QI
0 "call_address_operand" "hR"))
2790 (match_operand
1 "" ""))
2791 (clobber (reg:QI
24))])]
2795 if (GET_CODE (operands[
0]) == REG ||
2796 (GET_CODE(operands[
0]) == SYMBOL_REF && !TARGET_NEAR_CALL))
2797 return
\"pt=%
0\;call pt
\";
2801 [(set_attr "type" "call")])
2803 ;; Call subroutine with return value.
2805 (define_expand "call_value"
2806 [(parallel [(set (match_operand
0 "register_operand" "=f")
2807 (call (match_operand:QI
1 "call_address_operand" "hR")
2808 (match_operand:QI
2 "" "")))
2809 (clobber (reg:QI
24))])]
2813 if (GET_CODE (operands[
1]) == MEM
2814 && ! call_address_operand (XEXP (operands[
1],
0), QImode))
2815 operands[
1] = gen_rtx_MEM (GET_MODE (operands[
1]),
2816 force_reg (Pmode, XEXP (operands[
1],
0)));
2820 [(parallel [(set (match_operand
0 "register_operand" "=f")
2821 (call (mem:QI (match_operand:QI
1 "call_address_operand" "hR"))
2822 (match_operand:QI
2 "" "")))
2823 (clobber (reg:QI
24))])]
2827 if (GET_CODE (operands[
1]) == REG ||
2828 (GET_CODE(operands[
1]) == SYMBOL_REF && !TARGET_NEAR_CALL))
2829 return
\"pt=%
1\;call pt
\";
2833 [(set_attr "type" "call")])
2836 (define_expand "untyped_call"
2837 [(parallel [(call (match_operand
0 "" "")
2839 (match_operand
1 "" "")
2840 (match_operand
2 "" "")])]
2846 emit_call_insn (GEN_CALL (operands[
0], const0_rtx, NULL, const0_rtx));
2848 for (i =
0; i < XVECLEN (operands[
2],
0); i++)
2850 rtx set = XVECEXP (operands[
2],
0, i);
2851 emit_move_insn (SET_DEST (set), SET_SRC (set));
2854 /* The optimizer does not know that the call sets the function value
2855 registers we stored in the result block. We avoid problems by
2856 claiming that all hard registers are used and clobbered at this
2858 emit_insn (gen_blockage ());
2863 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2864 ;; all of memory. This blocks insns from being moved across this point.
2866 (define_insn "blockage"
2867 [(unspec_volatile [(const_int
0)]
0)]
2875 [(set_attr "type" "nop")])
2878 ;; PEEPHOLE PATTERNS
2883 [(parallel [(set (cc0)
2884 (compare (match_operand:QI
0 "register_operand" "k,k,!k,u,u,!u")
2885 (match_operand:QI
1 "register_operand" "w,z,u,w,z,k")))
2886 (use (match_operand:QI
2 "register_operand" "=j,j,j,q,q,q"))
2887 (use (match_operand:QI
3 "register_operand" "=v,y,q,v,y,j"))])
2889 (if_then_else (match_operator
5 "uns_comparison_operator"
2890 [(cc0) (const_int
0)])
2891 (label_ref (match_operand
4 "" ""))
2894 "pt=%l4\;%
2-%
3\;if %C5 goto pt")
2897 [(parallel [(set (cc0)
2898 (compare (match_operand:QI
0 "register_operand" "k,k,!k,u,u,!u")
2899 (match_operand:QI
1 "register_operand" "w,z,u,w,z,k")))
2900 (use (match_operand:QI
2 "register_operand" "=j,j,j,q,q,q"))
2901 (use (match_operand:QI
3 "register_operand" "=v,y,q,v,y,j"))])
2903 (if_then_else (match_operator
5 "uns_comparison_operator"
2904 [(cc0) (const_int
0)])
2906 (label_ref (match_operand
4 "" ""))))]
2908 "pt=%l4\;%
2-%
3\;if %I5 goto pt")
2912 [(parallel [(set (cc0)
2913 (compare (match_operand:QI
0 "register_operand" "k,u")
2914 (match_operand:QI
1 "const_int_operand" "i,i")))
2915 (use (match_operand:QI
2 "register_operand" "=j,q"))])
2917 (if_then_else (match_operator
4 "uns_comparison_operator"
2918 [(cc0) (const_int
0)])
2919 (label_ref (match_operand
3 "" ""))
2922 "pt=%l3\;%
0-%H1\;if %C4 goto pt")
2925 [(parallel [(set (cc0)
2926 (compare (match_operand:QI
0 "register_operand" "k,u")
2927 (match_operand:QI
1 "const_int_operand" "i,i")))
2928 (use (match_operand:QI
2 "register_operand" "=j,q"))])
2930 (if_then_else (match_operator
4 "uns_comparison_operator"
2931 [(cc0) (const_int
0)])
2933 (label_ref (match_operand
3 "" ""))))]
2935 "pt=%l3\;%
0-%H1\;if %I4 goto pt")
2938 ;;; QImode SIGNED COMPARE PEEPHOLE OPTIMIZATIONS
2942 [(parallel [(set (cc0)
2943 (compare (match_operand:QI
0 "register_operand" "j,j,h,q,q,q")
2944 (match_operand:QI
1 "register_operand" "v,y,q,v,y,j")))
2945 (use (match_operand:QI
2 "register_operand" "=k,k,k,u,u,u"))
2946 (use (match_operand:QI
3 "register_operand" "=w,z,u,w,z,k"))])
2948 (if_then_else (match_operator
5 "signed_comparison_operator"
2949 [(cc0) (const_int
0)])
2950 (label_ref (match_operand
4 "" ""))
2953 "pt=%l4\;%
0-%
1\;if %C5 goto pt")
2957 [(parallel [(set (cc0)
2958 (compare (match_operand:QI
0 "register_operand" "j,j,j,q,q,q")
2959 (match_operand:QI
1 "register_operand" "v,y,q,v,y,j")))
2960 (use (match_operand:QI
2 "register_operand" "=k,k,k,u,u,u"))
2961 (use (match_operand:QI
3 "register_operand" "=w,z,u,w,z,k"))])
2963 (if_then_else (match_operator
5 "signed_comparison_operator"
2964 [(cc0) (const_int
0)])
2966 (label_ref (match_operand
4 "" ""))))]
2968 "pt=%l4\;%
0-%
1\;if %I5 goto pt")
2972 [(parallel [(set (cc0)
2973 (compare (match_operand:QI
0 "register_operand" "j,q")
2974 (match_operand:QI
1 "const_int_operand" "i,i")))
2975 (use (match_operand:QI
2 "register_operand" "=k,u"))])
2977 (if_then_else (match_operator
4 "signed_comparison_operator"
2978 [(cc0) (const_int
0)])
2979 (label_ref (match_operand
3 "" ""))
2982 "pt=%l3\;%b0-%H1\;if %C4 goto pt")
2985 [(parallel [(set (cc0)
2986 (compare (match_operand:QI
0 "register_operand" "j,q")
2987 (match_operand:QI
1 "const_int_operand" "i,i")))
2988 (use (match_operand:QI
2 "register_operand" "=k,u"))])
2990 (if_then_else (match_operator
4 "signed_comparison_operator"
2991 [(cc0) (const_int
0)])
2993 (label_ref (match_operand
3 "" ""))))]
2995 "pt=%l3\;%b0-%H1\;if %I4 goto pt")
2997 ;; TST PEEPHOLE PATTERNS
3000 [(parallel [(set (cc0)
3001 (match_operand:QI
0 "register_operand" "j,q"))
3002 (use (match_operand:QI
1 "register_operand" "=k,u"))])
3004 (if_then_else (match_operator
3 "signed_comparison_operator"
3005 [(cc0) (const_int
0)])
3007 (label_ref (match_operand
2 "" ""))))]
3009 "pt=%l2\;%b0-
0\;if %I3 goto pt")
3012 [(parallel [(set (cc0)
3013 (match_operand:QI
0 "register_operand" "j,q"))
3014 (use (match_operand:QI
1 "register_operand" "=k,u"))])
3016 (if_then_else (match_operator
3 "signed_comparison_operator"
3017 [(cc0) (const_int
0)])
3018 (label_ref (match_operand
2 "" ""))
3021 "pt=%l2\;%b0-
0\;if %C3 goto pt")
3023 ;; HImode peephole patterns
3027 (compare (match_operand:HI
0 "register_operand" "A,A")
3028 (match_operand:HI
1 "register_operand" "Z,A")))
3030 (if_then_else (match_operator
3 "signed_comparison_operator"
3031 [(cc0) (const_int
0)])
3032 (label_ref (match_operand
2 "" ""))
3035 "pt=%l2\;%
0-%
1\;if %C3 goto pt")
3039 (compare (match_operand:HI
0 "register_operand" "A,A")
3040 (match_operand:HI
1 "register_operand" "Z,A")))
3042 (if_then_else (match_operator
3 "signed_comparison_operator"
3043 [(cc0) (const_int
0)])
3045 (label_ref (match_operand
2 "" ""))))]
3047 "pt=%l2\;%
0-%
1\;if %I3 goto pt")